2.1. FPGA modeling 2.2. Programming considerations 2.3. Execution model L1 L2 L3 L4 L5 L6

Figure 1 .

 1 Figure 1. Fan-in: index are aggregated to form an address in thetable. Fan-out: the same index is presented to each table downstream.

  Figure 2. Compiler flow3.2. Hierarchical aspects

table. Fan-out: the same index is presented to each table downstream.

Table 1 . Average numbers of nodes and criti- cal path stages for all 4:3 RAID decoders Figure 3. Decoder 8+2 on a Lut-4 architecture

 1