Back Biased Controlled Thyristor BeST BBC-T enhanced STacked SCR BET-FET Bipolar-Enhanced TFET BL Bit Line BTBT Band To Band Tunneling BOX Buried OXide CC Capacitive Coupling CC-TLP Capacitively Coupled TLP CDM Charge Device Model CMOS Complementary MOS D Drain DIBL Drain-Induced Barrier Lowering DRAM Dynamic Random Access Memory DUT Device Under Test EHB-TFET Electron-Hole Bilayer TFET eDRAM Embedded DRAM ESD Electro-Static Discharge FBE Floating Body Effects FBJ Forward Biased Junction FDSOI Fully Depleted Silicon-On-Insulator Fe-FET Ferroelectric FET FED Field Effect Diode FET Field Effect Transistor FN Fowler-Nordheim Gb Back Gate Ge Germanium Gf Front Gate GIDL Gate-Induced Drain Leakage R0, R1 Read "0" and "1" states RPO Resist Protection Oxide RSU Remote-Sense and Switch Unit S Source SA Sense Amplifier SCE Short Channel Effects SCR Silicon Controlled Rectifier Si Silicon SiGe Silicon Germanium Si/SiGe HBT Si/SiGe Heterojunction Bipolar Transistor SIMOX Separation by IMplanted OXygen SL Select Line SiO2 Silicon Dioxide SOI Silicon-On-Insulator SPICE Simulation Program with Integrated Circuit Emphasis SRAM Static RAM SRH Shockley-Read-Hall SS Subthreshold Slope STI Shallow Trench Isolation TCAD Technology Computer-Aided Design TDR Time Domain Reflectometry TDRT Time Domain Reflectometry and Transmission TDT Time Domain Transmission TFET Tunnel FET TiN Titanium Nitride TLP Transmission Line Pulse ULP Ultra-Low Power URAM Unified RAM UTBB Ultra-Thin Body and Box UTSOI Compact Model of MOSFET developed by CEA-Leti VF-TLP Very Fast TLP VLSI Very-Large-Scale Integration W0 Write "0"

Waveform Generator/Fast Measurement Unit WL Word Line Z 2 -FET Zero subthreshold slope and Zero impact ionization FET Z

This PhD thesis was a collaboration between STMicroelectronics (Crolles) and IMEP-LaHC Laboratory in Grenoble.

First, I would like to thank the members of the jury for the time spent to evaluate this work and attend my PhD defense. Thank you, Prof. Jean-Pierre Colinge, Prof. Francisco Gamiz, Prof.

Fabien Pascal and Prof. Marise Bafleur.

Foremost, I would like to express my deepest sense of gratitude to my advisors Pascal Fonteneau, Philippe Ferrari and Sorin Cristoloveanu. Without them this thesis might not have been written. Thank you Pascal Fonteneau not only for your continuous support of my PhD study and research but also for your personality, humor and the way of thinking and dealing with things. I wish to express my very sincere gratitude to Philippe Ferrari. I would not have been in France doing my PhD thesis without your help. No words can express my thanks to Sorin Cristoloveanu for your daily support, patience, motivation, enthusiasm, and immense knowledge. I have learned a lot from you not only in scientific domain but also with your advices for daily life.

I would like to thank all the members of SPICE modeling team at STMicroelectronics for their precious help, theoretical and practical advices. Special thanks to L. Malier, S. Hanriat, M. Minondo and G. Gouget for giving me the opportunity of starting a new professional horizon by being a member of SPICE modeling team.

I am indebted to all my friends and colleagues at IMEP-LAHC, especially with whom I shared most of the time at the office A-287. I could not forget to thank also Prof. M. Bawedin and Prof.

G. Ghibaudo for their valuable comments and suggestions.

Particular thanks to all my friends with whom I shared unforgettable moments. Thank you Aziz, Auguste, Vincent, Hugo, Antoine, Jean-Baptiste and … There are too many to write here and I would not like to forget anyone.

GP Ground Plane GP-N N-type Ground Plane GP-P P-type

Introduction

The impressive development of microelectronic devices and circuits has enabled many new applications in several fields. Integrated circuits have become an integral part of our daily life as they can be found in the majority of electronic devices. Improving their performance and integration density requires a nonstop downscaling. However, nowadays they reach physical limitations, which implies searching for another concept. Proceeding from bulk to Silicon-On-Insulator (SOI) technology is one of the best solutions adopted by industrial companies. Thanks to Fully Depleted Silicon-On-Insulator (FDSOI), the Metal-Oxide Semiconductor FET (MOSFET) offers excellent features. Nonetheless, reducing its threshold voltage increases the leakage current and power consumption. As it is driven by the diffusion mechanism, the subthreshold slope is limited to 60 mV/dec. Hence, new software-hardware techniques from system to circuit level, dedicated to power saving, are a must. Different strategies have been proposed to reduce the supply voltage: channel engineering (Ge, III-IV, Graphene …), nanowire and nanotube FETs, circuits operate at low (cryogenic) temperatures. The study of structures achieving small swing switch is an attractive avenue that we have adopted. Band-modulation devices, which are the core of this thesis, offer not only a sharp switch but also very low leakage current, high current ION/IOFF ratio, fast access time and adjustable triggering voltage. With these promising characteristics, the sharp-switching devices that have been developed can be used in many applications. We focus on Electro-Static Discharge protection (ESD), single Transistor Dynamic Random Access Memory (1T-DRAM) operation and logic switch.

Our goal is to explore band-modulation devices and verify whether they feature outstanding characteristics even at advanced 28 nm and 14 nm FDSOI technology nodes. The thesis was organized in four chapters, as described below.

An overview of sharp-switching devices is initially carried out in Chapter 1. Different variants with their operation principles are presented. The ESD physical mechanism, stress models and protection methods are highlighted. The last section is dedicated to 1T-DRAM application: the state of the art of different structures in PDSOI, bulk and FDSOI technologies with their operation principle is described.

In Chapter 2, band-modulation devices fabricated with the most advanced FDSOI technologies (i.e. 28 nm and 14 nm) are presented. The band-modulation principle of Z 2 -FET (Zero subthreshold slope and Zero impact ionization), which is unique for all variants, is investigated with Synopsis TCAD simulations. The advantage of implementing an N-type ground plane underneath the front-gate (Z 2 -FET DGP) and operating with only back-gates (Z 3 -FET with no front-gate) is explored.

The concept of modulating electrostatically the energy bands, proved with static DC electrical characterization, is further developed in Chapter 3. The dependency of device characteristics on anode, front and back-gates biases is highlighted for all-Si, SiGe and doped Z-FET structures. The ESD behavior and capability of sustaining high current is investigated using TLP characterization method. Finally, a model for the surface potential distribution in Z-FET structures is proposed.

The memory operation of sharp-switching devices is deeply analyzed with TCAD simulations, in the fourth chapter, and confirmed with systematic transient measurements. Operating as 1T-DRAM, Z-FET family devices feature high current margin and remarkable retention time. The feasibility of dense memory matrix is also discussed. A last section stands for the experimental proof of band-modulation devices as logic switches.

Finally, a conclusion recalls all the main achievements carried out in this thesis, and presents some perspectives to this work.

Introduction

The first chapter presents the context of topics developed during three years of PhD thesis work. First, we briefly introduce the history of MOSFET (Metal-Oxide Semiconductor FET)

transistor and the trends of microelectronics. The unbreakable 60 mV/decade subthreshold slope of MOS transistor limits the reduction of power supply voltage even in FDSOI (Fully Depleted SOI) technology. This issue was the motivation of searching for sharp-switch devices described in the following. Devices with electrostatic modulation of energy bands attract attention nowadays.

Thanks to their promising characteristics (sharp switch, low leakage current, adjustable triggering voltage), they can be used for many applications. In this chapter, we focus on ESD protection and single-transistor 1T-DRAM operation. The context and physical mechanisms of aggressive discharge current, stress models and ESD protection methods are highlighted. A review of several 1T-DRAM variants with different operation in PDSOI, bulk and FDSOI technologies is given to set the landmarks of my work.

MOSFET Transistor: State of Art and Trends

In 1930, J. Lilienfeld [1], the Polish-American physicist, was the first to provide the idea of three-electrode structure using copper-sulfide semiconductor material. Today this device is called a Field-Effect-Transistor (FET). Few years later, in 1948, the first device was fabricated at Bell laboratories by W. Shockley [2], J. Bardeen and W. Brattain [3] (Nobel Prize 1956) while the first Integrated Circuit (IC) was created by J. Kilby [4] (Nobel Prize 2000). These inventions have changed the human life and our society.

During the past decades, the CMOS technology [5] emerged as the dominant fabrication method for semiconductor integrated circuits where the MOS [6] (Metal-Oxide-Semiconductor transistor, Figure 1.1) was and still is the central component. Its function is similar to a switch. The role of a MOS is to let the current flow or block it by controlling the carrier channel (electrons or holes) with a transverse electric field created by the front gate polarization. On both sides of the channel are the source and the drain, which act as a tank of carriers. As CMOS technology is the driving force, the MOS transistor was almost exclusively fabricated on Bulk silicon substrate (type P for nMOS and type N for pMOS). The source and the drain are realized by implantation of donor/acceptor dopants next to the conduction channel.

Considering the p-type silicon film, the source and the drain contacts are N + type. The gate is separated from the substrate by a dielectric layer. Generally, it is SiO2 thanks to its very good compatibility with silicon. The Si active zone is detached from the rest of substrate by shallow trench isolation (STI). Thus, the space delimited determines the transistor geometry with a defined channel length L (distance between source and drain) and width W.

The transistor scaling down increases the on-chip transistor density. Nowadays, a chip can contain several hundred million, or even a few billion transistors. However, the fast downscaling puts almost an end to Moore's law. The cost of transistor is no longer decreasing while the equipment investment increases aggressively (Figure 1.2) [7]. Despite the challenge of enhancing its architecture (Metal Gate, LDD implant, Halo implant, …) and eliminating all unwanted parasitic effects, the bulk planar silicon MOSFET is facing severe problems when scaling beyond 28 nm node particularly with respect to power consumption [8][9]. Short channel effects [10] (SCE), such

as threshold voltage roll-off, subthreshold slope (SS) degradation, mobility degradation and drain induced barrier lowering (DIBL) are some of these issues. When the device becomes smaller, the two depleted regions of source and drain can overlap affecting the channel electrostatic control induced by the gate bias. The potential distribution in the channel depends now on both transverse electric field (controlled by the gate) and longitudinal electric field (induced by the drain bias) which results in many forms of undesirable electrical behavior. The MOS transistor implementation became more and more complex. In order to address this challenge and improve the device performance, adoption of new technologies, new materials and new architectures is required. One part of the biggest companies favored the transition into Fully-Depleted Silicon-On-Insulator (FDSOI) [11][12][13] planar technologies, while others decided to continue scaling with more complicated architectures such as FinFET [14,15]. In this thesis we focus on FDSOI technology. In the next subsections a description of SOI, the benefits of this promising technology and its issues will be presented. Also we briefly define the MOS transistor in FDSOI technology.

Migration to FDSOI 1.3.1. SOI Technology

Unfortunately, existing solutions allowing the passage from the last node to next one are no longer sufficient to guarantee an optimal operation of MOSFET transistor (good current ratio ION/IOFF). Thus, new technology architectures have been introduced to improve the electrostatic control of the channel by the gate. Among these, the Silicon-On-Insulator (SOI) took part as one of the best solutions [16]. The SOI substrate consists of undoped monocrystalline silicon film isolated from silicon substrate by a buried oxide (BOX). The active zone of transistor is defined on the upper silicon layer. Many techniques have been developed for producing a film of singlecrystal silicon on top of insulator. However, SIMOX and UNIBOND seem to be the ideal candidates for VLSI CMOS applications [5]. SOITEC is the world's first SOI wafers provider using the SmartCut® technique (UNIBOND) [17]. The idea here is to realize:

1. An oxide layer on a silicon substrate (wafer A in Figure 1.3) followed by hydrogen ions implantation.

2. Hydrophilic bonding at room temperature of wafer A to a wafer B. Both wafers are previously cleaned using a modified RCA process.

3. Two-phase treatment of two wafers in order to split them into two parts at hydrogen ions level 4. In order to get a uniform and clean surface, a final touch of polish of SOI wafer is performed. The SmartCut® CMOS approach features several outstanding advantages like better electrostatic control, reduction of parasitic capacitances between source/drain contacts and the substrate thanks to BOX presence, reduction of short-channel effects, improved device isolation and subthreshold swing enhanced, latch-up elimination, etc. In contrast, and like other technologies, SOI presents some drawbacks such as self-heating and floating body effects.

However, the last issue (FBE) is useful for dynamic memory application as we will see later in section 1.6.

Two types of MOSFET transistors can be realized on SOI substrate. The first one is Partially Depleted Silicon-On-Insulator transistor (PDSOI [18]) where the depletion zone does not reach the BOX because of the important thickness of silicon film (tSi > 50 nm). Conversely, with an ultrathin silicon film the depletion zone reaches the buried oxide. Here we talk about Fully Depleted SOI transistors (FDSOI). In this thesis we focus on FDSOI devices and in the following subsection we describe the MOSFET transistor in Ultra-Thin Body and BOX (UTBB) FDSOI technology [16][17][18].

MOS Transistor in UTBB FDSOI Technology

Recently introduced by STMicroelectronics, the 28-nm UTBB FDSOI [12,19] technology features a better electrostatic control and reduced undesirable parasitic effects. The process of MOS transistor starts from a SOI substrate with 25 nm of buried oxide (BOX) and 7 nm active silicon layer thicknesses. The thin buried oxide separates the undoped silicon film (NA ≈ 10 15 cm -3 ) from a highly doped Ground Plane (with a concentration NGP > 10 18 cm -3 ) that prevents the substrate's deep depletion and acts as a back-gate. To access the GP and control the well potential, the BOX is locally etched. In 28 nm FDSOI process, a MOSFET can benefit from 2 types of ground planes (standard and flipped well, Figure 1.4). The undoped Si film is covered by a High-K dielectric and metal gate. This gate stack starts with a thermally grown oxide interface (SiO2) covered by high-K material (HfO2) and connected via a TiN or AlTiN metal layer. A silicon epitaxy is performed on the source and drain in order to reduce the access series resistances. After this step, Lightly Doped Drain implants (LDD) may be added at the source-channel and drain-channel junctions with the intention of reducing SCE and better controlling the transistor behavior. Finally, after the second gate spacer realization, the S/D are implanted (NA, ND > 10 20 cm -3 ). Nonetheless, the outstanding UTBB technology with its numerous advantages motivated us to develop sharp switching devices that can break the 60 mV/decade subthreshold slope of MOS transistors. In the following section, innovative switches based on different physical mechanisms, such as band-modulation devices, which will be the core of this thesis, are described in details.

Sharp-Switching Devices

Lowering the "power consumption" is a big challenge especially after reaching CMOS downscaling limits. However, involving new semiconductor materials (Ge, III-V) into MOSFET's world is not yet a mainstream solution. The unbreakable 60 mV/decade subthreshold slope is a nightmare for a MOSFET transistor. Indeed, reducing the threshold voltage Vth with such a slope implies an off-state current (IOFF) increase, and hence the static power consumption. In the hope of going below 60 mV/decade swing, several devices have been developed. We introduce these sharp-switch variants in the following subsections.

Tunnel Field Effect Transistor (TFET)

Due to its low subthreshold slope and good scalability, TFET is of great interest to replace or complement the MOSFET. Showed schematically in Figure 1.5-a, the Tunnel FET is essentially a gated P + -I-N + diode [20] operating under reverse bias mode. Unlike the MOSFET which uses thermal carrier injection, the TFET utilizes band-to-band tunneling as a source for carrier injection mechanism. When there is no gate bias, the diode body is fully depleted and the band edges of N + and P + terminals are spaced out. There is no tunneling in this case and the TFET is in OFF-state.

In contrast, increasing the gate voltage fills the channel with either electron or holes, depending on polarity (VG > 0 V for N type and VG < 0 V for P type), and alignment of energy band edges is observed. Now, the distance between the N + source and the P + channel is very short and the electrons can tunnel from the valence band of the P + region to the conduction band of the N+ region as shown in Figure 1.5-b. Figure 1.6 shows the transfer characteristics of N type all-Si TFET with a subthreshold SS = 52.8 mV/decade at low ID current [21]. Despite the enhanced SS, all-Si TFET suffer from a poor current ratio ION/IOFF. Even with a good SS achieved [21,22], the best ON current is still low (46 µA/µm) in comparison with MOSFET [23]. For further ION improvement, many approaches can be considered such as lowering the bandgap by using alternative compounds like III-V [24],

merging Si or replacing it totally with Germanium (Ge) [25]. Also, alternative geometries are of interest to enhance the ION current. For example, using a raised Ge electrode region permits a larger tunneling area and hence larger drain current could be obtained [S. H KIM and Schmidt] [26,27].

Modifying the channel (EHB-TFET) [28] or combining a standard TFET with a Si/SiGe HBT in a single device (BET-FET) [29] are also proposed to achieve better ION/IOFF current ratio.

However, the TFET roadmap is still full of challenges and needs more convincing experimental validation.

Ferroelectric FET

A material is ferroelectric when it has two distinct polarization states, which can be maintained in the absence of an electric field and between which one can switch by applying an electric field.

The main concept of Fe-FET [30], shown schematically in Figure 1.7, is replacing the gate dielectric by ferroelectric material. Polarizing the ferroelectric by applying a gate voltage modifies the conductivity of the semiconductor channel between source and drain. For example, a positive voltage directs the polarization along the semiconducting channel and results in a positive charge boosting the formation of an inversion electron layer. While switching the polarization to its other state, the ferroelectric charge becomes negative and the electrons close to the gate in the semiconductor get depleted. In this case, the Fe-FET is in OFF state with high threshold voltage

Vth and low IOFF leakage current. Unfortunately, fabricated Fe-FET devices feature a high subthreshold slope (SS > 60 mV/decade). They suffer not only from reliability issues but also from technical problems such as Ferroelectric layer thickness, which should be ultrathin to prevent short channel effects induced by the drain fringing field. However, the technology of Fe-based negative capacitors is progressing [31,32] and some solutions are proposed. For example, an external single-crystal BiFeO3 capacitor is added in the series with the gate terminal leading to 8 mV/decade swing over 8 decades of current [33].

Nano-electro-mechanical FET

The concept of nanoelectromechanical FET [34,35] consists in separating the gate from the channel by an empty cavity. More precisely, the gate electrode is anchored on two sides of the channel creating an air-gap between the channel and the gate (Figure 1.8). In the case of thick airgap, the device operates with high gate voltage [34]. The gate is pulled up in OFF state with negative VG and down in ON state with VG > 0 V. However, the increased air-gap induces SCEs that limits the IOFF current. In order to improve its operation, [START_REF] Kam | A new nano-electromechanical field effect transistor (NEMFET) design for low-power electronics[END_REF] proposed displacing the suspended gate in the opposite direction where the accumulation-mode channel is depleted when the gate is pulled down (VG < 0 V). Silicon is the most common material in forming not only integrated circuits but NEMS also.

However, the surface defects are uncontrollable in case of ultra-thin silicon. Instead, carbon nanotubes [START_REF] Cao | Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors[END_REF] and nanowires [START_REF] Kim | Steep subthreshold slope nanowire nanoelectromechanical field-effect transistors (NW-NEMFETs)[END_REF] are used. They feature perfect surfaces, mechanical and electrical properties but competitive NEM-FETs have still to be demonstrated.

NEM Relay

Nanoelectromechanical relay or NEM is a simple mechanical switch inspired from MOSFET.

Here, a metal beam, controlled by electrostatic force, replaces the "channel". Figure 1.9 shows different NEM structures used for logic applications. The 2-Terminal switch (Figure 1.9-a) is the simplest mechanical structure composed of source and drain terminals [START_REF] Osterberg | M-test: A test chip for MEMS material property measurement using electrostatically actuated test structures[END_REF]. However, it is not very useful for digital circuits because it requires a high actuation voltage (> 10 V) and presents nonseparable input-output electrodes. The solution is introduced by the 3-Terminal relay where the gate (input) and the drain (output) electrodes are separated [START_REF] Chong | Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage[END_REF]. In order to move up and down the beam, the gate is polarized. The potential difference between gate and source (VGS) determines the position of the cantilever beam while the drain current is determined by VDS. The 4-Terminal switch is similar to 3T relay with an additional body terminal and insulating layer. Here the gate is moving and its position is controlled by applying a body voltage. Many structures have been fabricated, for logic and NVM applications [START_REF] Akarvardar | Energy-reversible complementary NEM logic gates[END_REF][START_REF] Akarvardar | Design considerations for complementary nanoelectromechanical logic gates[END_REF][START_REF] Kam | Design and reliability of a micro-relay technology for zero-standby-power digital logic applications[END_REF], using different beam designs and various contact materials. However, the contact reliability remains a key issue. In order to improve the cycle endurance and face the "Hammer effect", some methods were proposed like covering one contact electrodes by thin SiO2 layer [START_REF] Jang | Fabrication and characterization of a nanoelectromechanical switch with 15-nm -thick suspension air gap[END_REF] or introducing insulating oil as a packaging liquid [START_REF] Lee | 3-Terminal nanoelectromechanical switching device in insulating liquid media for low voltage operation and reliability improvement[END_REF].

I-MOS: Impact Ionization MOSFET

Another interesting switching device with low subthreshold slope is the Impact Ionization MOS or I-MOS [START_REF] Gopalakrishnan | I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q[END_REF][START_REF] Mayer | Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)[END_REF], presented in Figure 1.10. The structure is similar to an asymmetric P-I-N diode partially covered by a gate and the rest of the channel is ungated. When there is no gate bias (VG = 0 V) the device is in OFF state featuring a fully depleted channel and low leakage current IOFF. The ON mode consists of increasing the number of holes in the channel, such as to reduce the length of the depleted region and induce avalanche breakdown. For this purpose, the gate is negatively biased and the drain is highly polarized (VD > 0 V) leading to a sharp switch ID-VG as shown in Figure 1.10. However, the high drain bias is not so welcomed for pracitcal applications.

An original application of this device structure was invented in [START_REF] Wan | A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection[END_REF] where the operation principle (Z 2 -FET) is different this time and it will be discussed in details in Chapter 2.

Band-Modulation Devices: Operation Principle and Variants

Devices relying on bands modulation attract a lot of attention nowadays. They exist in different forms but the operation principle is almost the same. For example, the Field Effect Diode uses two adjacent front gates separated by a gap [START_REF] Raissi | A brief analysis of the field effect diode and breakdown transistor[END_REF][START_REF] Manavizadeh | Performance assessment of nanoscale field-effect diodes[END_REF], as shown in Figure 1.11. The diode is forward biased. triggering voltage increase and if VON is higher than Vdd + 10%, it is possible to use the FED as a local ESD protection [START_REF] Yang | Design and optimization of the SOI field effect diode (FED) for ESD protection[END_REF][START_REF] Salman | Field effect diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies[END_REF][START_REF] Cao | Gate-controlled fieldeffect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology[END_REF]. Despite the flexible control of barriers and promising characteristics, the FED suffers from the gap between the two front-gates. In fact, it affects not only the ON current but also the high frequency performance of the device. In addition, the FED length reduction should respect certain limit imposed by the gates gap.

This problem is solved with Z-FET family devices presented in Figure 1.12. Unlike FED, The Z 2 -FET (Zero subthreshold slope and Zero impact ionization) [START_REF] Wan | A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection[END_REF][START_REF] Solaro | Z2-FET: A promising FDSOI device for ESD protection[END_REF][START_REF] Dirani | Sharp-Switching Z2-FET Device in 14 nm FDSOI Technology[END_REF] is fabricated with just one front-gate that modulates the barrier beside the anode while the barrier beside the cathode is manipulated by the back-gate, ground plane type P. An additional ground plane type N can be added underneath the gate of standard Z 2 -FET in order to reinforce the Gf barrier. This device is called Z 2 -FET DGP [START_REF] Dirani | Novel FDSOI band-modulation device: Z2-FET with Dual Ground Planes[END_REF] (Dual Ground planes) while the third variant, Z 3 -FET [START_REF] Dirani | A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology[END_REF][START_REF] Solaro | A sharp-switching device with free surface and buried gates based on band modulation and feedback mechanisms[END_REF] presented in Figure 1.12-c, presents no front gate and its barriers are controlled by N and P GPs acting as back-gates. These devices can be used for many applications such as ESD protection [START_REF] Solaro | Z2-FET: A promising FDSOI device for ESD protection[END_REF][START_REF] Dirani | A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology[END_REF][START_REF] Solaro | A sharp-switching device with free surface and buried gates based on band modulation and feedback mechanisms[END_REF][START_REF] Solaro | Innovative ESD protections for UTBB FD-SOI technology[END_REF][START_REF] Solaro | Z2-FET as a novel FDSOI ESD protection device[END_REF] and capacitor-less dynamic random access memory, 1T-DRAM [START_REF] Solaro | Innovative ESD protections for UTBB FD-SOI technology[END_REF][START_REF] Solaro | Z2-FET as a novel FDSOI ESD protection device[END_REF][START_REF] Wan | Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage[END_REF][START_REF] Wan | A systematic study of the sharpswitching Z2-FET device: From mechanism to modeling and compact memory applications[END_REF][START_REF] Wan | A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration[END_REF]. The state-of-art will be discussed in the following subsections while the operation principle and detailed devices description will be presented in the second chapter of the thesis.

. Context and Physical Mechanism

An electrostatic discharge is a charge reset of a system being initially unbalanced. It is originated by either triboelectric effect that occurs when two materials get into contact and then separated [START_REF] Williams | Triboelectric charging of insulators-evidence for electrons versus ions[END_REF], or by electrostatic induction [START_REF] Tanaka | CDM ESD Test Considered Phenomena of Division and Reduction of High Voltage Discharge in the Environment[END_REF], which happens when an isolated IC undergoes an external electric field. Historically, MOS technologies were most susceptible to ESD discharges because of their gate oxide. This trend then spread to other technologies by means of aggressive downscaling and the challenge to protect thin devices with low supply voltage (Vdd < 1 V) from this harmful event became critical. Thus, innovative ESD protection devices are a must. Figure The ESD design window presented in Figure 1.13 is valid whatever the used technology.

However, the value of two limit points (Vdd and VBD) varies with CMOS downscaling [START_REF] Cao | ESD design challenges and strategies in deeply-scaled integrated circuits[END_REF][START_REF] Duvvury | Esd qualification changes for 45nm and beyond[END_REF]. The circuit supply voltage decreases while the breakdown voltage falls down dramatically.

Consequently, the window becomes narrower and designing efficient electrostatic discharge devices becomes more difficult. Optimizing the fabrication process as proposed in [START_REF] Cao | Investigation on output driver with stacked devices for ESD design window engineering[END_REF][START_REF] Li | Technology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node[END_REF] and implementing reliable protection devices, which are suitable to the design window are of great interest [START_REF] Amerasekera | ESD in Silicon Integrated Circuits[END_REF]. In this thesis, we propose innovative ESD protection devices described in chapter 2.

ESD-Induced Failure in Integrated Circuits

The handling of electronic components in poorly controlled environments is the major cause of many failures due to electrostatic discharges. In addition of CMOS downscaling, using new techniques like light doped drains, silicidation, or ultrathin gate oxide makes modern integrated circuits more vulnerable to electrostatic discharges. Different ESD-type failures are considered in Figure 1.14. The most common breakdown mode in a MOSFET transistor is the gate/drain diffusion damage. In this case, the semiconductor material is locally melted due to high temperature, often observed in fabrication process, connecting the source and the drain together.

Another frequent degradation type, shown in Figure 1.14-b, is the gate oxide damage of transistors.

Eventually, when the electric field between drain and gate oversteps certain value (~ 12 MV/cm) due to high drain bias, it will cause damage in gate oxide. The gate isolation quality decreases and thus a leakage current increase is observed.

ESD Stress Models

The real world ESD events can be represented by different stress models in the form of RLC circuit. This electrical circuit can simulate the same event as an electrostatic discharge when the integrated circuit is touched by a human (Human Body Model), or manipulated by a machine (Machine Model) or even the discharge of a component itself when it goes into contact with another grounded element (Charge Device Model). We describe in details the ESD models in the following subsections, along with the different characteristics of each example such as current wave form, rise time, period and oscillations.

Human Body Model

Human Body Model or HBM [START_REF][END_REF] describes the transfer of charges when a human touches a circuit. The electrostatic charge source is modeled by a charged capacitor (100 pF in this case,

Machine Model

The Machine Model or MM was introduced first by Japanese IC manufacturers as a more severe case than HBM model. This time, the human is replaced by a machine. Consequently, the equivalent circuit of this ESD-type model in Figure 1. 16 In fact, integrated circuits are called to withstand at least 200 V discharge amplitude for which, in MM case, a damped oscillation is observed in Figure 1. 16

Charge Device Model

The most frequent discharge mechanism in automated handling environment is the Charge Device Model or CDM. It is modeled by a small value of capacitance (between 4 pF and 30 pF) [START_REF] Tanaka | CDM ESD Test Considered Phenomena of Division and Reduction of High Voltage Discharge in the Environment[END_REF][START_REF] Goeau | Impact of the CDM tester ground plane capacitance on the DUT stress level[END_REF]. Of course, after assembly and packaging, components could be charged in different ways and if they go into contact with a grounded metallic surface, an extremely rapid and severe discharge is produced. In particular, the CDM event lasts for few nanoseconds (5 to 10 ns) with rise time of picoseconds and a high peak of current (~ 15 A) with a damped pseudo-periodic waveform as shown in Figure 1.17.

Protection Methods

Finding the best current path between two pads, usually the discharge source (I/O pad, supply voltage pad Vdd …) and ground pad (Vss) presented in Figure 1.18, without affecting the circuit core, is a simple definition for ESD protection strategy. In practice, protection devices should be able to deviate the discharge current into the ground avoiding sensitive components. For this purpose, good ESD clamp should respect certain conditions [START_REF] Amerasekera | ESD in Silicon Integrated Circuits[END_REF]:

 Robustness: the protection element should not fail before evacuating the required discharge current. This property is defined by Vt2 and It2 points that can be evaluated with Transmission Line Pulse (TLP) characterization described in details in the following subsection.

 Effectiveness: an efficient ESD clamp triggers after the supply voltage (Vdd) and before the breakdown voltage (VBD) of core circuit (already discussed in 1.5.1) evacuating a sufficient discharge current.

 Speed: the turn on of ESD protection should be fast enough, avoiding overshoots especially in CDM events with sub nanoseconds rise times.

 Transparency: the protection should feature low leakage current in OFF state when the circuit operates normally. Moreover, the clamp capacitance should be very small avoiding the perturbation of high-frequency circuit operation. Prevention methods such as using air ionizers, antistatic bags and packages for transport, carrying grounded wrist straps at the work bench while handling integrated circuits are helpful but not sufficient to protect against aggressive discharges. Besides, self-consistent protection by implementing ESD devices on-chip is a need. Indeed, there are two ways of protection against an ESD event arising between a pad and the ground. Circuit designers have the choice now to choose between these two strategies ensuring an adequate protection against electrostatic discharges and taking, of course, into consideration surface constraints.

Characterization Methods

The ESD response of protection elements cannot be evaluated with DC characterization. In fact, static measurements with high voltage and current values certainly will destroy the "Device Under Test" (DUT) by excessive heating effect. Instead, an efficient technique (Transmission Line Pulse), proposed for the first time by Tim Maloney in 1985 [START_REF] Maloney | Transmission line pulsing technique for circuit modeling of ESD phenomena[END_REF], is used for clamp devices interpretation. The pulsed system will be discussed in details in the following subsection.

Transmission Line Pulse (TLP)

Transmission Line Pulse technique is based on generating pulses with high current values through a transmission line. Indeed, this method becomes the main measurement tool giving needed information on ESD protection behavior and efficiency. Actually, the famous 100 ns pulse width of TLP measurement is the typical duration of HBM stress model. It can be adjusted by modifying the length of the transmission line according to tpulse = 2L/v, where v is the wave propagation speed. The quasi static I-V characteristic is constructed point by point until the breakdown (Vt2, It2) of analyzed device. Each point of the curve corresponds to the average of DUT voltage response on transmitted current pulse.

There are three common methods used in TLP measurements. However, every technique has its own advantages and drawbacks. The first one, Time-Domain Reflectometry or TDR described in Figure 1.20, is used to determine the current and the voltage at the device terminals with the help of incident and reflected voltage pulses. In fact, when the emitted signal meets an impedance discontinuity, a part of its energy is returned to the pulse source. Thus, the expected information of tested device is obtained after analyzing the reflected signal. It is not possible, with this method, to characterize a tripole. Moreover, the indirect current and voltage measurement induces inaccurate results. The current pulse width and rise time can be decreased down to few ns, up to 300 ps by shortening the length of transmission line connecting the voltage source to the structure under test.

With these small values, we get closer to the time range of CDM stress model, we are talking here about Very Fast TLP (VF-TLP) [START_REF] Gieser | Very-fast transmission line pulsing of integrated structures and the charged device model[END_REF]. However, this technique does not offer the best correlation of stress currents between single pin CDM stress and two pins VF-TLP. Presented in Figure 1.23, the optimized version CC-TLP [START_REF] Wolf | Capacitively coupled transmission line pulsing cc-TLP -A traceable and reproducible stress method in the CDM-domain[END_REF] (Capacitively Coupled TLP) injects high current pulses via a single pin while the other one is connected to the ground through a background capacitance Cb.

During the stress Cb charges, and discharges at the end of the pulse, through the protection element

showing better correlation with CDM model. During this thesis work, the ESD behavior of our devices has been investigated with TLP and VF-TLP measurements using TDT technique. Detailed results will be presented in Chapter 3.

1.6. 1T-DRAM: Capacitorless Dynamic Random Access Memory

Introduction

Everyone is looking for a semiconductor universal memory that offers very fast access time, high integration density, infinite retention and low fabrication cost. The idea here is to bring together the perfect characteristics of volatile and non-volatile memories into a single device that would be able to store the information infinitely when there is no supply voltage, featuring low power consumption, unlimited endurance, and of course be compatible with modern technologies with aggressive scalability (Figure 1.24). Unfortunately, a memory that fits all these requirement does not exist at the moment. Nowadays, companies are trying to reduce the large gap between existing solutions and perfect memory. They already succeeded to combine just two or maximum three of previous conditions. Volatile memories, with Random Access Memory (RAM) as a trade name, could be static (Static RAM, SRAM) or dynamic (Dynamic RAM, DRAM). They present very fast access time (1 to 10 ns) but they lose the stored information when the supply voltage is turned off. In comparison with DRAM, SRAM are faster with higher retention time. However, they occupy more surface because of their architectures composed of many transistors. 4T-SRAM (4 transistors) may be smaller than 6T cell but it still about four times larger than a comparable DRAM cell. Moreover, applications demanding low power consumption (mobile phones, computers, servers …) favor the use of dynamic memories while static cells are used for high performance functions (Cache Memory).

The second category of memories is non-volatile memories, or NVM. They feature high integration density and long retention time (10 years) even if there is no power supply. Today, many types of emerging technologies with new materials are under investigation in order to get as close as possible to the universal memory. Those are magnetic memories MRAM [START_REF] Sugibayashi | A 16-Mb Toggle MRAM With Burst Modes[END_REF], organic memories ORAM [START_REF] Sezi | Organic Materials for High-Density Non-Volatile Memory Applications[END_REF], memories with ferroelectric materials FeRAM [START_REF] Lous | Ferroelectric Memory Devices, How to store the information of the future?[END_REF], phase change PCRAM [START_REF] Lee | Highly productive PCRAM technology platform and full chip operation: Based on 4F 2 (84nm pitch) cell scheme for 1 Gb and beyond[END_REF], and resistive memories ReRAM [START_REF] Yasuda | A Cross Point Cu-ReRAM with a Novel OTS Selector for Storage Class Memory Applications[END_REF] that attract a lot of attention nowadays due to their promising characteristics. However, they are still prototypes. From a commercial point of view, Flash memories dominate the market of NVM. They are used in applications where the information is stored for long time such as USB flash drives, hard disk drives and also in portable digital cameras.

The use of this type of architecture is advantageous because of its very small cell size and high retention time. Nonetheless, strong applied bias voltages with high programming time limit the number of cycles (10 6 cycles) of Flash memories.

Whatever the type is and despite all technical challenges, the market of memories is still increasing. The quest for the best candidate that will imitate the universal memory continues. In the following subsections, we focus on dynamic RAM with and without capacitance in different technologies (Bulk, PDSOI and FDSOI); how they work and examples of different variants will be presented.

Motivations and State of the Art

Working at IBM Thomas Watson research center, Robert Dennard invented in 1968 one of the most selling memories today in the world, Dynamic Random Access Memory (DRAM). It has been commercialized two years later by Intel in a 1 Kb PMOS integrated circuit defeating at that moment the magnetic core type memory. Each memory cell consists of one access MOS transistor and a storage capacitor where the information is saved in form of charges (~ 10 6 electrons).

Respecting scaling rules of progressing technologies, DRAM cell surface is reduced 2 times while the integration density is multiplied by 4 every three years [START_REF] Itoh | Limitations and Challenges of Multigigabit DRAM Chip Design[END_REF]. However, this surface reduction was rapidly limited not only because of the storage capacitor but also the access transistor. In order to solve this problem, two 3D structures have been proposed: trench [START_REF] Sunami | A Corrugated Capacitor Cell (CCC) For Megabit Dynamic MOS Memories[END_REF] and stacked [START_REF] Koyanagi | Novel high density, stacked capacitor MOS RAM[END_REF] capacitor DRAM cells presented schematically in Figure 1.25. The trench technology consists of first etching deep and narrow trenches and then connecting them to the transistor, fabricated in a second step, with buried straps. Contrarily, the stacked method counts on realizing the capacitance after CMOS procedure. Besides, other techniques have been introduced in order to give more surface and enhance the capacitance value such as using poly silicon HSG or metal electrodes (ruthenium or TiN), replacing the nitride dielectric by materials with high dielectric constant (Al2O3, HfO2) or mixing the dielectric materials (Al2O3/HfO2).

Thanks to these two architectures, the 1T-1C DRAM cell reached a high integration density.

Nowadays, the downscaling of memory elementary cell is still going on. However, difficulties related to process integration of both capacitance and access transistor are expanding especially beyond 90 nm node where the fabrication steps rebel against conventional CMOS. For this purpose, breakthrough architectures without external storage capacitor are proposed as alternatives to conventional DRAM memories. The operation principle is presented in section 1.6.3.3. Whether volatile or non-volatile memories, they are divided into two categories: Stand Alone where the memory array is realized independently of logic circuit, and embedded memories where logic transistors are combined with memory cells on the same chip. The last system (embedded memories, eDRAM) attracts a lot of attention nowadays featuring high performance, huge volume of exchanged data, very low power consumption and of course high integration density. Despite all these advantages, the co-integration of logic functions and memories on the same chip implies an increase of process steps and hence the cost of fabrication. The key feature of eDRAM [START_REF] Iyer | Embedded DRAM technology: Opportunities and challenges[END_REF] cells integration is to find the best compromise between manufacturing cost, integration density and power consumption according to applications. This was our motivation to test bandmodulation devices, which are fully compatible with the most advanced fully depleted CMOS technology, as capacitor-less DRAMs. Experimental results will be investigated in details in the last chapter of this manuscript. Originally, FBEs such as history effect, Kink effect and parasitic bipolar are considered as parasitic effects during the normal operation of a transistor. In particular, we focus on Kink effect [START_REF] Hafez | Analysis Of The Kink Effect In Mos Transistors[END_REF][START_REF] Mosfet | Analysis of Kink Characteristics in Siliconon-Insulator MOSFET's Using Two-Carrier Modeling[END_REF] that appears in the form of an overshoot on ID-VD curve at high drain voltage bias and an enhancement of subthreshold slope in transfer characteristic ID-VG of the transistor, shown in The dynamic fluctuation of body potential produced by Kink effect becomes an increasing interest as a memory outcome. In fact, the floating substrate of these transistors can be used to store the information in form of body charges and read it by applying voltage pulses on drain (VD)

and gate (VG) terminals.

Different 1T-DRAM Architectures in PDSOI and Bulk Technologies

The first capacitor-less memory in PDSOI technology was proposed in 1990 [START_REF] Tack | The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures[END_REF]. It has not been developed because it does not present a selective programming method which is a necessary condition for this kind of memories. Few years later, in 1993, the problem was solved by conceiving another 1T-DRAM cell accompanied by two transistors for writing and reading [START_REF] Wann | A Capacitorless DRAM Cell on SOI Substrate[END_REF]. However, it was a complex architecture that needed large surface. The topic came back later in 2001 [START_REF] Okhonin | A SOI capacitor-less 1T-DRAM concept[END_REF], with a rigorous proposition in 0.25 µm and 0.13 µm CMOS technologies. The area occupied by each innovative cell was half of that of a conventional 1T-1C DRAM. Thanks to their promising characteristics, industrial companies started looking forward in order to implement the cells in matrices; the first one was a 96 Kbit unveiled in 2003. After the demonstration of the possible implementation of these cells in 22 nm node CMOS, offered by Toshiba, other groups tried to find comparable programming methods that reduce the power consumption and increase the retention time. Looking at all these results, we can say that 1T-DRAM memories in PDSOI technology, presenting high integration density and faster programming time, had potential to replace the conventional DRAM memory.

Regarding bulk technology, the first free capacitance memory cell was proposed in 2003 [START_REF] Villaret | Mechanism of Charge Modulation in The Floating Body of Triple-Well nMOSFET Capacitor-less DRAM[END_REF].

The concept is similar to those in PDSOI technology. However, the body of the transistor (NMOS) is isolated not with a buried oxide but with an implantation of N layer in the lower part of the substrate P (~ 1 µm depth). The first variant, fabricated in 120 nm CMOS technology [START_REF] Villaret | Nouvelles architectures de mémoires embarquées compatibles CMOS[END_REF], is isolated laterally with not very deep STI (Shallow Trench Isolation) coupled with N wells on both sides, as presented in Figure 1.28-a. It features promising results as a memory cell. However, this architecture does not fulfil the required objectives of 1T-DRAM memory because of its low integration density. The surface of elementary cell reaches 54F 2 per bit which is much higher than a classic 1T-1C DRAM with 8F 2 /bit surface (F is the minimum dimension that can be achieved in a technology node). In order to get rid of this disadvantage, another method of device isolation was called. The N doped lateral wells, used for isolation, were replaced by deep shallow trenches touching the buried N layer, as seen in Figure 1.28-b. The surface is highly reduced with this approach (18F 2 /bit) which makes it competitive to a conventional embedded 1T-1C DRAM with 25-30F 2 elementary surface. However, the realization of deep and large STI (0.18 µm of width and > 1 µm of depth in 120 nm CMOS node) is not so easy with complicated manufacturing process steps which increase the cost of cell fabrication. For this reason, it was replaced rapidly by another innovative solution with simple integration, shown in Figure 1. 28-c [97]. This method consists of realizing the P-N junction directly under the standard STI, without any additional modification, and keeping the same surface (18F 2 ) as for NMOS with deep insulator trenches. Designed and fabricated at STMicroelectronics, the 1T-DRAM cell in 120 nm node featured promising results with decent retention time (100 ms at 85°C) and good current ratio I1/I0. A matrix of 8Mbits 1T-DRAM was also demonstrated with a current detection circuit (Current Mode Sense Amplifier, SA) [START_REF] Ranica | Architectures DRAM [Mémoire dynamique à accès aléatoire] innovantes pour les applications CMOS[END_REF]. This successful work was transferred to the following node (90 nm CMOS technology) [START_REF] Ranica | Scaled 1T-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications[END_REF]. Comparing to 1T-1C DRAM, obtained results on both elementary memory cell and matrix levels were featuring higher integration density (26% saved surface at matrix level). In the next subsection, we develop the operation principle of the previous memory variants.

Operation Principle

The operation principle of all 1T-DRAM versions, illustrated in Figure 1.29, is almost the same. The state "1" reflects an excess of majority carriers in the body causing an increase of the potential (VB > 0 V) and drain current while the "0" state consists of removing majority carriers from the body. In this case, the potential is lower implying higher threshold voltage Vth and low drain current. In order to generate the majority carriers, several mechanisms have been offered such as impact ionization, bipolar junction transistor, and band-to-band tunneling. The Table 1.1 presents the impact ionization technique used to program the state "1" of 1T-DRAM in both Bulk and PDSOI technologies. Erasing, reading and holding methods are also mentioned.

Mode Source Drain

Front Gate N-Implant (Bulk)

Back Gate (PDSOI)

Write "1" The operating mechanisms are almost the same in these technologies. However, they differentiate in holding the stored information. In order to limit the leakage current and save the information for a long time, in PDSOI technology, the front gate is biased negatively keeping the diodes in reverse mode. Programming state "1" is done by impact ionization. A positive voltage pulse is applied on the front gate (VGf > Vth) accompanied with a positive drain pulse higher than the saturation voltage VDSAT. With these polarizations, the electrons in the channel are accelerated by the high electric field present in the space charge region close to the drain and generate by impact ionization electron-holes pairs. The electrons are guided towards the drain while holes are injected into the floating body of the transistor where they will be stored. For the "0" state, the drain/body junction is forward biased by applying a negative drain pulse. In this case, the stored holes are evacuated and electrons are injected from the drain into the body lowering the potential.

0 V > VDSAT > Vth > 0 V 0 V Write "0" 0 V < 0 V > 0 V or < 0 V (PDSOI) < 0 V (Bulk) Read 0 V < VDSAT > Vth Hold 0 V 0 V < 0 V (PDSOI) 0 V (Bulk)
At the same time, in 1T-Bulk devices, a negative pulse is applied on the front gate switching off the transistor and strongly reducing the dynamic power consumption. In order to keep a remarkable margin between "0" and "1" states, it is strongly recommended in PDSOI technology to bias positively the gate instead of a negative pulse. Although, a negative gate pulse is used for "0" selective writing mode which is a big challenge in 1T-DRAM world. In reading mode, a high positive pulse is applied on the front gate terminal, while the drain voltage is smaller (< VDSAT) in order to not trigger the impact ionization mechanism that will disturb the "0" state of the memory cell. During all memory operations, the N buried layer (in Bulk technology) should be biased positively allowing a perfect body isolation. In this case, the leakage current of the reversely biased P-N diode is low.

This overview allows us to conclude that DRAM architectures without external storage capacitor in bulk technology can be used for embedded memory applications while PDSOI devices are viable as standalone memories. However, the evolution of 1T-PDSOI memory cells is facing serious problems with CMOS downscaling. In order to guarantee the neutral zone in sub-100 nm node, the channel doping concentration is increased. This high doping level induces threshold voltage variation and the generation current increase at the source/drain terminals affects the "0" retention time. On the other hand, 1T-Bulk memories seem to be compatible with eDRAM applications until 45 nm node according to ITRS 2003. Beyond this node, innovative solutions are needed to ensure the 1T-DRAM concept continuity. In the following, we describe the benefits of 1T-DRAM devices in Fully Depleted SOI (FDSOI) technology and how they operate.

1T-DRAM in Fully Depleted Silicon on Insulator (FDSOI) Technology

Motivations

Short-channel effects (SCE) appear in Bulk and PD devices when they are scaled down beyond 45 nm node which affects their operation as dynamic memories. In particular, the control of "0" state, especially in holding mode, becomes impossible. Doping the channel with high concentrations increases the leakage current of junctions [START_REF] Trivedi | Scaling fully depleted SOI CMOS[END_REF] which affects the "0" state retention time. By way of explanation, previous technologies cannot ensure anymore the continuity of capacitor-less DRAM keeping a remarkable current margin and high retention time. For this purpose, developing innovative architectures with thin silicon film is a must. In fact, SOI transistors with Fully Depleted body (FDSOI) attract much attention due to their numerous advantages [START_REF] Colinge | Thin-film SOI technology: the solution to many submicron CMOS problems[END_REF]:

better electrostatic control, steeper subthreshold slope and higher saturation current. In this context, researchers and industrial companies decided to test FDSOI transistors with thin silicon film as 1T-DRAM, believing that one day they will be fully compatible with CMOS logic transistors fabrication. The operation principle of FDSOI transistors and the memory variants are investigated in the next paragraph.

Operation Principle and 1T-FDSOI Memory Variants

Compared to PDSOI dynamic memories, operating with one single front gate and grounded back gate, FDSOI devices need back-gate biasing to perform as 1T-DRAMs. In fact, the potential distribution in a thin silicon film is completely different from that in partially depleted body. The source/substrate barrier is high enough allowing the accumulation of holes in the substrate where the potential-well is quite deep. This barrier is reduced in FDSOI technology due to the strong coupling effect between the front and the back gates. Here, holes are evacuated into the source instead of being accumulated in the transistor body. Nonetheless, floating-body effects, in particular the Kink, appear again in FDSOI transistors when the back gate is negatively biased.

Holes can accumulate in the silicon film inducing a front-channel threshold voltage reduction and drain current increase which is also the origin of Kink effect.

In 2004, first FDSOI memories without capacitance appear with two different silicon film thickness (16 nm by STMicroelectronics [START_REF] Ranica | A capacitor-less DRAM cell on 75nm gate length, 16nm thin Fully Depleted SO1 device for high density embedded memories[END_REF] and 55 nm by Toshiba [START_REF] Shino | Highly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications[END_REF]). Few years later, other variants such as double-gate 1T-DRAM, floating-junction gate devices and FinFet configurations have been developed. In the following, we present the most recent capacitor-less dynamic memories in FDSOI technology featuring interesting results in terms of current margin, retention time and integration density.

a. MSDRAM

MSDRAM is a single-transistor operating as capacitor-less DRAM [START_REF] Bawedin | A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation[END_REF]. The operation mechanism is based on Meta Stable Dip effect (MSD) discovered in 2004 [START_REF] Bawedin | Unusual floating body effect in fully depleted MOSFETs[END_REF]. This unusual floating body effect appears in regular FDSOI transistors where the double (front and back) gates cooperate by coupling, giving rise to a hysteresis in transfer ID-VG characteristics, illustrated in The 1T-MSDRAM is simple to program and read. It features a good current margin and high retention time. However, the memory cell suffers from super-coupling when the silicon film thickness goes into values smaller than 10 nm [START_REF] Cristoloveanu | Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four-Gate MOSFET[END_REF]. In fact, the coexistence of two types of carriers in the channel at the same time is not possible anymore.

b. A-RAM Family

In order to suppress the super-coupling effect and be certain of the presence of two types of carriers in transistors with tSi < 10 nm, a new concept has been proposed in 2009 [START_REF] Rodriguez | A-RAM : Novel capacitor-less DRAM memory[END_REF]. The Advanced RAM (ARAM) memory cell body, presented in Figure 1.32-a, is divided by a middle oxide (MOX) into two parts. The upper region is dedicated for storing majority carriers while electrons are present in the lower semi-body with the intention of current sensing. State "1" programming consists of filling the upper body part with holes using impact ionization or B2B tunneling techniques. The holes will enable, by electrostatic coupling through the MOX, an electron current flow in the sense region (lower semi-body). In contrast, when there is no charge stored above MOX, the concentration of minority carriers (electrons) in the bottom of the body is very low (due to full depletion) defining the state "0" with no current flow. Positive drain pulses are used to read the memory states. This memory cell exhibits decent retention time, low power operation and sufficient current margin. Also, with ONO stack for the MOX the Advanced RAM could present a nonvolatile functionality [START_REF] Rodriguez | A-RAM Memory Cell : Concept and Operation[END_REF].

Two years later, an updated version was proposed with an N + layer placed in the bottom of the transistor body that serves for current sensing. The middle oxide (MOX) is suppressed in this novel device, A2RAM [START_REF] Rodriguez | Novel capacitorless 1T-DRAM cell for 22nm node compatible with bulk and SOI substrates[END_REF] (presented in Figure 1.32-b). It features the same operating principle as MSDRAM, except that the bridge is "physical", made by epitaxy or implementation, rather than "electrostatic" induced by the back-gate. In A2RAM, the current flows through the N + bridge revealing the state "1". Experimental results show that this innovative memory cell features an acceptable retention time (20 ms for standard and 100 ms for optimized version at 85°C) and high current ratio I1/I0 [START_REF] Rodriguez | Experimental demonstration of capacitorless A2RAM cells on silicon-on-insulator[END_REF]. The critical issue is again film thinning which makes difficult the formation of variability free N-bridge.

c. Z 2 -RAM

Fully depleted Z 2 -FET transistor [START_REF] Wan | A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection[END_REF][START_REF] Dirani | Sharp-Switching Z2-FET Device in 14 nm FDSOI Technology[END_REF], unlike MSDRAM and A2RAM, is free from supercoupling effect and technological process constraints. The device has been already presented in section 1.4.6 and will be investigated in details in the next chapter. First experiments showing the functionality of this device as 1T-DRAM have been performed on P-type Z 2 FET [START_REF] Wan | Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage[END_REF][START_REF] Wan | A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration[END_REF],

schematically shown in Figure 1.33. Here the front gate, placed near the drain (N + doped), is negatively biased and the back-gate is positively biased. This kind of polarization emulates a virtual NPNP thyristor blocking the current flow. Increasing the drain current to a value higher that VON (ON voltage) will trigger the feedback mechanism between barriers controlled by the two gates and sharp switch is obtained. Therefore, a high current circulates through the device. The memory programming relies on the presence (state "1") or not (state "0") of holes stored under the gate.

The discharged gate capacitor during reading state "1" with a negative drain pulse unblocks the device giving rise to a high current I1 as seen in Figure 1.33. Nevertheless, in "0" state, Z 2 -RAM remains blocked with no current flow because there is no charge under the gate. The key feature of this memory cell is that the operation principle does not rely on the number of holes stored under the gate but on the discharge current ∆Q/∆t (higher current collected with fast reading).

d. Unified RAM

Assigning multifunction tasks to a transistor is an alternative solution when there is no more possibility to scale it down. The Unified memory, in planar SOI [START_REF] Ryu | Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM[END_REF] (Figure 1.34-a) or FinFET or channel hot-electron injection. For dynamic operation, an excess of holes are stored in the body region (state "1") using impact ionization or GIDL techniques, while "0" state consists of deriving holes into the drain/source by forward biasing the junctions. Preliminary results in different technologies [START_REF] Rodriguez | A-RAM : Novel capacitor-less DRAM memory[END_REF][START_REF] Rodriguez | A-RAM Memory Cell : Concept and Operation[END_REF] demonstrate the concept of URAM memory with the possibility of storing multiple bits using MDC method [START_REF] Bae | Multiple Data Storage of URAM (Unified-RAM) with Multi Dual Cell (MDC) Method[END_REF] . However, the programming voltage of 1T-DRAM operation can affect the trapped charges in ONO layer and induce an undesired threshold voltage shift. In order to avoid this interference, gate-to-source nonoverlap structures have been proposed [START_REF] Han | Gate-tosource/drain nonoverlap device for soft-program immune unified RAM (URAM)[END_REF] and an alternative 1T-DRAM programming method is adopted [START_REF] Han | Gate-induced drain-leakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM)[END_REF]. A different solution consists of employing ONO materials as BOX where the buried nitride layer is used for NVM charge storing [START_REF] Chang | FinFlash with buried storage ONO layer for flash memory application[END_REF] and the silicon body for dynamic memory mode. It has been demonstrated that the memory effect depends not only on the frontgate, back-gate and drain polarizations but on device geometry also. In shorter devices, the memory margin is extended [START_REF] Chang | FinFlash with buried storage ONO layer for flash memory application[END_REF]. The proposed FinFlash with buried storage ONO layer can serve for analog, logic or memory applications performed with the same cell.

Conclusion

In this first chapter, the history of MOSFET transistor in bulk technology was discussed,

showing the need of migration into UTBB FDSOI technology in case of aggressive downscaling.

We have tried to review the most important sharp-switching devices, showing the possibility of breaking the famous 60 mV/decade subthreshold slope of MOS transistor. Within this first chapter, it has been shown that band-modulation devices present superior performance with a very sharp switch. These devices can be used for many applications such as electrostatic discharge protection, sensing, logic switch and 1T-DRAM memories. We have focused on two applications:

Electrostatic discharge protection and capacitor-less dynamic random access memories. A survey of different 1T-DRAM variants in different technology has been carried out. In the next chapter, the detailed description and operation principle of our band-modulation devices will be addressed. Recently proposed in [1][2][3][4][5][6] as capacitor-less dynamic memory (1T-DRAM) and developed as a local electrostatic discharge (ESD) protection in [7][8][9][10], the standard Z 2 -FET features notable performance. Figure 2.1 shows the device structure in 28 nm FDSOI node [11,12]. The fabrication process of Z 2 -FET starts with delimiting the device surface using STI isolation. The 25 nm BOX separates the undoped ultra-thin silicon film (tSi = 7 nm with ~ 10 16 cm -3 doping concentration) from a highly P-type doped ground plane (~ 10 18 cm -3 ) that prevents the deep depletion of the substrate and acts as a back-gate. In order to access the GP and control the well potential, the BOX is locally etched. Unlike FED that controls the channel with two adjacent front-gates ( [13][14][15], see Standard Z 2 -FET is fully compatible with CMOS FDSOI technology process integration without any modification. However, the 28 nm node imposes an epitaxial layer (tepi = 15 nm) on the whole structure to reduce series resistance [16]. This process step induces a non-uniform silicon channel thickness. Hence, the ungated part length (Lp) of the channel is 22 nm instead of 7 nm for gated part, Ln. A final step, before contact realization, consists of protecting the intrinsic part (Lp)

from silicidation by covering it with an oxide layer (RPO).

14 nm FDSOI Technology

Z 2 -FET transistor was also designed and fabricated in 14 nm FDSOI technology [17]. Both advanced nodes (14 and 28 nm) feature promising characteristics. However, the fabrication process of 14FDSOI is a little different. For an enhanced electrostatic control, the silicon film channel and BOX thicknesses are reduced down to 6 nm and 20 nm, respectively, as shown in Figure 2.2-a.

Contrary to 28 nm node, a dual in-situ doped Si:CP/SiGeB epitaxy is only realized on the source/drain area. An oxide protection layer is deposited on the uncovered part of the channel to avoid silicidation during contacts realization. In this region, the silicon thickness is slightly reduced because of successive process steps (deposit and etching). Moreover, the source/drain contacts, in 14 nm node, take the form of trenches authorizing more integration density with local interconnections between devices without resorting to the first metal level. In order to study the impact of silicon film thickness, another variant was fabricated with tSi = 12 nm (Figure 2.2-b).

Principle of Operation

Switch ON Characteristics

The Z 2 -FET is a P-I-N diode operating in forward mode. When the front and back gates are grounded, the device behaves as a regular forward-biased diode with a high current flow as observed in Figure 2.3. Indeed, with this normal characteristic, the device cannot be used for applications where the sharp switch is a must. To get a steep switch, the structure must be blocked by biasing the two gates. Thus, a positive voltage is applied to the front-gate (VGf) creating a barrier of electrons in Ln region that prevents the path of holes from the anode into the channel. Simultaneously, a barrier of holes is formed in the Z 2 -FET ungated part by applying a negative back-gate bias, thus preventing the injection of electrons from the cathode into the channel. Thereby, a virtual N + /P/N/P + structure composed of three junctions is formed where the central P/N junction is realized by electrostatic doping.

Two-dimensional simulations indicate that the impact ionization is not a factor of device triggering [1]. Conversely, the operation mechanism of standard Z 2 -FET is based on bands modulation. This mechanism is confirmed by TCAD simulations [18] presented in This important characteristic makes the Z 2 -FET a practical device for dynamic memories, ESD protection, logic switch and other applications demanding a triggering flexibility. In addition, standard Z 2 -FET exhibits hysteresis that widens with front-gate voltage increase as a result of progressive shift of turn-on voltage (Von) due to stronger barriers created by gates.

Experimental IA-VA characteristics in Figure 2.5-b show that the device is in OFF state at low anode voltage VA. It turns ON sharply when VA reaches the triggering voltage VON. As VA sweeps back to 0 V, the device remains in its ON state until it reaches ~ 0.7 V, at which point it turns OFF (VOFF < VON), resulting in a large hysteresis and two stable states ("1" and "0") corresponding to high or low current levels for the same anode voltage as shown in To explore the details of Z 2 -FET operation mechanisms, two dimensional simulations were performed by employing Synopsis TCAD tools [18]. Room temperature (300 K), Fermi-Dirac statistics and standard models of doping and mobility (doping dependence, Philips unified mobility, high-field velocity saturation and transverse field dependence) were considered. Doping and temperature-dependent Shockley-Read-Hall (SRH) recombination model was also used. The simulated structure was constructed following the 28 nm fabrication process with a gate workfunction value, WF0 = 4.56 eV. Fixed charge traps (Nhk = 5 × 10 12 cm -2 ) were added on the shared interface between high-k HfO2 dielectric and the interfacial oxide layer (SiO2) to match experimental data [19]. The maximum carrier lifetime value (max = 10 -8 s and 0.8 × 10 -8 s for electrons and holes, respectively) is a critical factor that affects the device behavior as shown in the following.

Two simulation approaches were carried out, first, by very slow current ramping using a current source, second, by fast front/back gates voltage ramping followed by very slow raised anode voltage VA. The characteristics collected by increasing the anode current take the form of "S-shape" snapback curves, as shown in Figure 2.7-a. Reducing the voltage while the current increases is not supported yet in TCAD tools. For this purpose, the S-shape is not present in IA-VA curves obtained with voltage ramping, as plotted in Figure 2.7-b. The injection barriers start recovering with back-sweeping the anode voltage. At point E, the device turns OFF abruptly due to the interaction between minority diffusion current and the GR current like in a thysristor [21] to return into its initial position with strong barriers as shown in In ultra-thin silicon film, the carrier lifetime is degraded, which is beneficial to Z 2 -FET for sharp switching.

Ground Plane Impact on Triggering Voltage VON : Coupling Effect

The P-type Ground Plane (GP-P) is present under the whole Z 2 -FET structure. As seen in the previous section, its main role is to create, with negative back-gate bias (VGb < 0 V), a barrier preventing the pass of electrons from the cathode into the channel. Regrettably, it interferes with the front-gate voltage (VGf) affecting negatively the Ln barrier and thus decreasing the triggering voltage VON. The degradation of VON for different front-gate voltages is reported in Figure 2.14.

This action can be explained by the coupling effect between the front and back gates. In that case, the electrostatic control of gated region, with ultra-thin silicon film (tSi = 7 nm), depends on both VGb and VGf polarizations. Thus, the GP bias increase also modifies the body potential under the front-gate and strongly affects the holes injection barrier, thus lowering the ON voltage not only for VGf = 1 V but even for higher gate bias (VGf = 1.2 V) where the Ln barrier is reinforced. This undesirable effect for some applications has been the motivation to fabricate another Z-FET version where the degradation of triggering voltage VON by VGb is suppressed. The structure of the device and its operation principle are explained in the next subsection.

Novel Band-Modulation Device with Dual

Ground Planes: Z 2 -FET DGP

Device Architecture

To improve the triggering voltage VON and avoid the coupling effect between the metal gate and the ground plane acting as a back-gate, another band-modulation device was fabricated in UTBB FDSOI technology with a small modification compared to Z 2 -FET with single GP. The novel structure, Z 2 -FET DGP [23,24], schemed in Figure 2.15 (a-28FDSOI node and b-14FDSOI node), is similar to standard Z 2 -FET except that an additional N-type Ground Plane (GP-N) is placed underneath the front-gate. Hence, the channel is divided into two independent parts with no bias interference. The Ln region is concealed by a single metal front-gate in 28 nm node [12] and dual workfunction HKMG in 14 nm node [17], respectively, and accompanied with N-type

aligned

Advantage of Dual GP

Adding a second N type ground plane underneath the front-gate of standard Z 2 -FET does not change its fundamental operation principle: "Band-Modulation mechanism". However, the additional GP-N brings two advantages to the novel device. First, it suppresses the coupling effect, reinforces the Ln barrier and hence increases the triggering voltage VON. Second, it offers a biasing flexibility for device users, paving the way for more applications. For example, the GP-N can be biased with respect to the front-gate:

 Simultaneously, by applying the same voltage on both terminals (GP-N and frontgate). This can also be done by connecting, with a metal, the two terminals and applying just one bias on a shared pad.

 Independently, by applying a constant GP-N value and varying VGf. The inverse operation is also applicable.

Indeed, a certain limitation should be respected when applying a voltage bias to the additional N-type ground plane, since the two ground planes form a diode under the buried oxide. This diode must always be reversed biased, thus avoiding leakage current and early device triggering. DC experiments with reversed VGf scan were performed for the Z 2 -FET with dual ground planes showing similar sharp switch characteristics. Figure 2.17 shows that the structure can be blocked even at high anode voltages (VA = 1.2 V for example). The additional N-type ground plane placed underneath the front-gate reinforces the barrier in this region and prevents the flow of holes from the anode. This result cannot be achieved in single GP Z 2 -FET and motivates the implementation of dual GPs.

. Fabrication Process

The third "Z" for back-gate modulated device Z 3 -FET [25][26][27] stands for zero front-gate.

Compared to other Z-FET family members, this device features similar architecture but this time without the high-k metal front-gate eliminating all issues related to high voltage reliability. Instead, an N + heavily doped ground plane (GP-N) was placed under the BOX controlling together with its adjacent GP-P the sharp switching characteristics. Figure 2.20 presents the architecture of no frontgate device in (a) 14 nm [17] and (b) 28 nm [12] FDSOI technologies with P + /N + doped anode/cathode, respectively. The ultra-thin silicon film is still undoped and separated from ground planes (N & P) acting as back-gates by a thin buried oxide.

The free surface of Z 3 -FET can be functionalized for various applications like bio, light and radiation sensing. These functionalities can be combined with typical applications of bandmodulation devices (memory, ESD, fast logic) leading for example to sensors with built-in memory.

Advantage of No Front-Gate

This time, the sharp switching characteristics are controlled by two separated ground planes that act as back-gates. The GPs, heavily doped in order to avoid substrate/BOX interface depletion, are positively (GP-N) and negatively (GP-P) biased, respectively. The device is normally OFF thanks to potential barriers that block the injection of electrons from N + source and holes from P + drain into the body. The GbN electrode connected to the ground plane N (GP-N) controls the electrostatic potential of the intrinsic channel part (Ln) beside the anode while the P-type ground plane connected to GbP electrode controls the Lp part of the channel beside the cathode.

Increasing the anode voltage beyond VON leads to a remarkable sharp transition from low to high current with a ratio of 8 decades of ION/IOFF current, as shown in Figure 2 their initial height. This point is variable in Z 3 -FET and depends on the ground planes biasing (it will be investigated in Chapter 3). As a result, the advantage of having a free surface on the top of the channel with a wide hysteresis effect promotes the structure to be a competitive 1T-DRAM memory coupled with novel applications like ion, bio, photo and radiation sensors.

 High voltage operation

Another important feature of Z 3 -FET, benefiting from the BOX as a gate oxide, is the ability of sustaining high back-gate bias [27].

Conclusion

In this chapter, a detailed overview of band-modulation devices fabricated with advanced FDSOI 28 nm and 14 nm technology nodes was carried out, showing their easy operation and high flexibility in terms of applications. The band-modulation mechanism and switch ON characteristics are unique for all structures (Z 2 -FET, Z 2 -FET DGP and Z 3 -FET). They were demonstrated using 2D TCAD simulations and experimental DC results. Indeed, the standard Z 2 -FET with single Ptype ground plane features high performance in terms of triggering voltage, leakage current and current ratio ION/IOFF. However, the back-gate (GP-P) affects the gated barrier and lowers the triggering voltage VON. This unwanted effect was solved by adding an N-type ground plane underneath the metal-front gate of standard device giving rise to a novel structure with two ground planes, Z 2 -FET DGP. Finally, a third variant of Z-FET family devices featuring no metal frontgate was reported. As compared to previous architectures, the back-gate modulated Z 3 -FET presents a free top surface eliminating the metal gate reliability issues and operating in a high voltage range, up to 7 V. In the next chapter, detailed experimental results (DC and TLP) in a wide temperature range of all band-modulation devices will be presented. Also, a potential distribution model of all variants will be investigated.

DC Measurements

DC measurements of all band-modulation variants (with thick gate-oxide, GO2) in 14 nm FDSOI technology were carried out at room and high temperature (T = 125 °C). Note that the maximum current reached in all figures corresponds to the anode current IA compliance of the experimental setup and is not representative of a saturation mechanism.

Impact of Silicon Thickness on Z-FET Devices Behavior

The basic characteristics of Z 2 -FET with two different silicon film thicknesses (6 nm and 12 nm) are illustrated in Figure 3. The switching characteristics can be improved by two methods. First, by increasing the film thickness (from 6 nm up to 12 nm in our case), the feedback mechanism between the two barriers is retrieved, producing a steep switch (SS = 5 mV/dec) as shown in Figure 3.1-b. Second, by raising the front-gate voltage up to 4 V (red curve in Figure 3.1-c); in that case the holes injection barrier is reinforced. The latter solution enables a sharp switch but increases the leakage current and can be harmful for the device because the high-k metal gate cannot sustain continuously high voltage.

Impact of Z-FET Devices Parameters

The characteristics of Z-FET devices, such as turn-on voltage VON, leakage current ILeak and hysteresis, depend directly on barriers strength and height in the two parts of the channel. In that case, varying the terminals bias (anode, cathode, front-gate and back N-P GPs), increasing/decreasing the structure length, stressing or doping the channel affect the barriers of band-modulation devices and modify their features. In this part, a full study of these devices in different flavors and wide temperature range is given.

Front-Gate and Ground Plane (P&N) Polarizations a. Coupling effect

In standard Z 2 -FET, a single P-type ground plane is placed under the whole structure. The GP-P governs the ungated region of the device, forming the electrons injection barrier. Increasing the back-gate bias from VGb = 0 V (black square symbols in Figure 3.

b. Turn-on Voltage

The device turns ON as the anode voltage VA reaches VON. But when the front-gate voltage VGf increases, the Ln barrier is reinforced and therefore a higher VON is needed to turn the device ON. This can be seen in Figure 3.5 for both thin and thick silicon film devices. In Z 2 -FET with tSi = 6 nm, the ungated barrier is constructed at only VGb = 0 V (Figure 3.5-b) while in thicker devices the electrostatic control of 12 nm silicon film requires a higher back-gate bias as shown in Figure 3.5-a. However, both variants present inner coupling between the front and the back-gate.

Increasing VGb induces a triggering voltage VON reduction, which starts at VGb = -1 V in thick Z 2 -FET and VGb = 0 V in thin devices. The triggering voltage variation of thick Z 2 -FET DGP and Z 3 -FET with front-gate or backgates polarizations is presented in Figure 3.6. In Z 2 -FET with two ground planes, two different ways to polarize the GP-N (cooperating with the front-gate) can be used. Biasing simultaneously the N-type ground plane with the front-gate (Red circle symbols, in Figure 3.6-a) implies a higher turn-on voltage than black square symbols, where the GP-N is grounded (VGbN = 0 V). The Ln barrier is more reinforced when VGf and GbN raise up together. Also, increasing the negative GP-P bias (from -1 V up to -2 V) strengthens the electron injection barrier, leading to higher VON, which confirms the suppression of coupling effect, as mentioned before between the GP-P and the front-gate. The evolution of turn-on voltage in Z 3 -FET is analogous to other band-modulation devices, as shown in Figure 3.6-b.

c. High Voltage Operation in Z 3 -FET Device

The advantage of modulating the triggering voltage by the ground planes enables using the Z 3 -FET as a high voltage device [6]. In principle, increasing GbN requires a higher anode voltage VA to turn ON the device but here the actual mechanism is more subtle and depends on the channel length, as shown in

d. Hysteresis

The output IA-VA curves in Figure 3.9 show that the device is in OFF state at low anode voltage VA. It turns ON when VA reaches the triggering voltage VON (closed symbols) and remains in ON state as VA is swept back (open symbols) until it reaches  0.6-0.7 V, at which point it turns OFF. This results in a large hysteresis, as shown in Figure 3.9, which is gate controlled and useful for capacitor-less memory. The hysteresis is enlarged by increasing VGf (Figure 3.9-a), and can also be modified by varying the back-gate bias VGb (Figure 3.9-b). Note that the inner coupling between the GP-P and the front-gate not only affects the triggering voltage VON, but also VOFF, the point where the device turns OFF. VON and VOFF are reduced when the back-gate bias increases from VGb = -1 V to -2 V, as shown in Figure 3.9-b. Hysteresis is confirmed in Z 2 -FET DGP and Z 3 -FET devices.

Device Length

The scaling of the Z 2 -FET strongly depends on the control of the relevant injection barriers by VGf and VGb. In short devices, the barriers are narrow, which erodes their height and need high front/back gates bias to be constructed. For example, a negative back-gate bias (VGb = -2 V) is required to block the Z 2 -FET with Ln = Lp = 90 nm (Figure 3.11-a) while longer devices feature normal switch ON characteristics with VGb = 0 V (Figure 3.11-b). Figure 3.11-a shows that, with VGb = -2 V, the short Z 2 -FET (Ln = Lp = 90 nm) is functional in 14 nm FDSOI node. Also, the sharp switch is recovered (red curve, Figure 3.11-a) by applying a relatively high front-gate bias (VGf = 3 V), which is a sound feature for area-conscious applications. Note that, in thin Z 2 -FETs, the switch is not steep enough due to the weak feedback between the barriers and the high recombination rate of carriers. The dependence of leakage current, measured at VA = 1 V, on the length of gated (Ln) and ungated (Lp) parts of the channel is shown in Figure 3.12-a and b, respectively. In short devices, the snapback is totally suppressed because the ungated region of the channel is not enough controlled by the back-gate, and the electrons injection barrier is collapsed. This is shown in Figure 3.12-a where thick devices with Lp ≤ 90 nm operate as a forward-biased diode with high current rather than a Z 2 -FET, even with a reinforced electrons injection barrier at VGb = -2 V. As Lp increases, the ungated barrier is enlarged and more efficiently controlled by VGb, therefore the leakage current is improved and the device can be blocked with low front-gate voltages. On the other hand, if the ungated barrier is strong enough (VGb = -2 V), then the gate length Ln has no effect (Figure 3.12-b). Hence, the gate length can be scaled down to at least 90 nm without compromising the characteristics of the device. Like standard Z 2 -FET, the electrons injection barrier in short Z 2 -FET DGP (Ln = Lp = 90 nm) is collapsed even at high GP-P bias (VGbP = -2 V, black circle symbols in Figure 3.13-a). The Lp barrier retrieves its height beyond 90 nm. Then, the device is blocked and the ungated length has no effect anymore on the leakage current.

The GPs lengths of Z 3 -FET were restricted by minimum design rules in 14 nm FDSOI node (min Lp = Ln = 138 nm). However, the behavior does not change in Z 3 -FET (Figure 3.13-b). The leakage current decreases with raising up GbN bias and by increasing Lp.

Doping

A Z 3 -FET variant was fabricated with a highly doped Ln part of the channel. It is presented in

Silicon-Germanium (SiGe) and Strained Variants

Temperature

The main characteristics of Z 2 -FET (sharp switch, hysteresis) are maintained in a wide temperature range, as shown in Figure 3.17-a [1,13,14]. At high temperature, carriers have higher thermal energy to unblock the barriers and turn the device ON more easily. As expected from simple physics laws, VON decreases (∆VON/∆T = -1.4 mV/°C) for both long and short devices (Figure 3.17-b). Note that in MOSFETs, the threshold voltage decreases at T = 125°C, enlarging the barrier height (~ (VGf -Vth -VA)), which would lead to a higher VON to collapse the barriers.

This argument does not hold in Z 2 -FET because carriers have gained energy at high temperature and can more easily pass the barrier. The competition between these two effects (stronger barrier and higher carrier energy) explains the temperature dependence observed in Figure 3.17

FDSOI 28 nm node vs. 14 nm node

Standard Z 2 -FET

DC measurements show that the Z 2 -FET in 14 nm FDSOI node features the same high performance as its counterpart in 28 nm node [1,2,[15][16][17][18]. At VGf = 0 V, the device operates as a diode rather that a Z 2 -FET with high ION current (Figure 3.20-a). In ultra-thin silicon film (6 nm), the feedback is lost, leading to a non-steep switch (opened circle symbols, Figure 3.20-b). To retrieve the feedback between the barriers, the silicon film thickness has to be increased (here up to 12 nm). In that case, the 14FDSOI Z 2 -FET features a vertical switch with VON  1.

Back-Gate Modulated Device, Z 3 -FET

A comparison between Z 3 -FET devices in 14 nm and 28 nm nodes was carried out and results are presented in Figure 3.21 [6,19]. Due to the silicon film and BOX thinning, the electrostatic channel control of 14 nm Z 3 -FET is enhanced. Hence, the barriers are stronger and need higher anode voltage VA to collapse, leading to VON increase (blue curves with closed symbols, Figure 3.21). Also, the effective carrier lifetime, dominated by interfaces, decreases in 14 nm node. Since the carriers recombine more in the channel, the diffusion region expands (see section 2.2.2.1). This delays the collapse of barriers, thus inducing a moderate switch slope and increasing triggering voltage VON.

TLP Measurements

In this part, the ESD behavior and robustness at high current of Z-FET devices is investigated, at room temperature, using transmission line pulse (TLP) characterization method [20]. To simulate HBM, MM and CDM stress models, 100 ns and 5 ns pulse durations with native rise time ( 300 ps, limited by used equipment) were applied to the DUT (Device Under Test).

The values of ESD design window for three typical voltages (1.0 V, 1.8 V and 3.3 V) in 14 nm FDSOI technology and the latch-up (LU) electrical targets defined by the JEDEC78 standard are presented in Table 3.2 [21]. For example, to prevent the damage of a GO1 FET with thin gate oxide used in 1.0 V applications, the ESD protection device must trigger in a narrow ESD design window (between 1.0 V and 2.5 V) and must be able to drive high current (> 1.3 A for HBM). For 1.8 V applications, where the breakdown of stacked oxide GO2 FET devices is higher, the window is relaxed (2.0 V < Vt1 < 4.0 V). Moreover, the ESD protection element should not trigger during the core circuit normal operation. Thus, to prevent latch-up (LU) event, two possibilities can be retained, (i) increasing the ESD device holding voltage above Vddmax (Vdd + 10%), and (ii) tuning the triggering voltage and/or current of protection element above 1.5 × Vddmax and 100 mA, respectively. In the following, we present TLP measurement results of 14 nm Z-FET devices that fit the required targets, especially for 1.0 V and 1.8 V applications.

Voltage application ESD (2 kV, HBM)

LU (JEDEC78)

Vt1 (V) It2 (A) Vt1 (V) It1 (mA) VH (V) 0.9 -1.0 V < 2.5 > 1.3 > 1.5 -1.7 > 100 > 1 -1.1 1.8 V < 4.0 > 1.3 > 3.0 > 100 > 2.0 3.3 V < 8.0 > 1.3 > 5.4 > 100 > 3.6
Table 3.2. ESD/LU electrical specification summary. In green the targets which must be reached; in white the target which would be nice to reach; and in grey the holding voltage target.

Standard Z 2 -FET

The high current performance of Z 2 -FET device with two different silicon film thicknesses (tSi = 12 nm in black curves and tSi = 6 nm in blue curves) for two short pulse widths (tPW = 5 ns and 100 ns) is shown in Figure 3.22 [1]. Z 2 -FETs with thicker tSi feature higher maximum current and sharper turn-on than their ultrathin counterparts. The efficiency to evacuate high current depends strongly on the duration of the ESD event and the thickness of silicon film. Longer discharges as well as ultrathin films will cause more device heating that degrades the failure current It2. This effect is documented in Figure 3.22, which shows a clear reduction in current for longer TLP pulses. Moreover, the ESD ON-Resistance (RON) is lowered with increasing tSi from 6 nm up to 12 nm (R12nm = 200 Ω/µm < R6nm = 520 Ω/µm).

Z 3 -FET

Undoped Variant

The ESD behavior of undoped Z 3 -FETs with different body lengths was investigated and results are presented in Figure 3.24. Two distinct pulse widths were used, as before (tPW = 5 ns and 100 ns in Figure 3.24-a and b, respectively). Like in Z 2 -FET with single ground plane, short Z With this characteristic, the Z 3 -FET can be promoted as a high-voltage (HV) ESD protection element. Undoped Z 2 -FET and Z 3 -FET variants (normally ON at zero gate bias) could disturb the operation of the core circuit. Thus, an external control circuit (RC filter for example) connecting the front/back gates to a positive/negative power supply voltage is a must. With VGf/VGbN > 0 V and VGb/VGbP < 0 V, ESD devices are blocked (OFF state) featuring low leakage current without affecting the normal activity of protected circuit. When ESD occurs, the high discharge current turns on Z-FET structures and passes through toward the ground.

Doped Variant

The Z 3 -FET undoped variant features excellent performance but requires a positive bias on GP-N and a negative bias on GP-P, which may not be suitable for ESD chip designers [6]. To address this issue, another variant was designed and fabricated with N-type Ln doped part of the channel. As presented in section 3.2.2.5, Z-FET devices feature an admissible dependence on temperature variation. At high temperature where the triggering voltage decreases, bandmodulation devices could be threatened by latch-up events. Thus a vigilant bias of structure terminals (anode, front-gate and back-gate) should be chosen. Furthermore, the need of external trigger circuit (i.e. RC circuit) to block the undoped Z-FET devices during ESD events restrains their use as protection elements. Doping the silicon body (Ln or Lp parts) can solve this issue since no more front-back gate bias is needed to form the barriers and keep the device blocked. This was the motivation to study in the following the robustness of stacked doped devices with hybrid-bulk silicon controlled rectifier (SCR) against electrostatic discharges.

Stacked Architectures

The modulated triggering voltage is an important feature of Z-FET devices that makes them very attractive nowadays. For this purpose, Fonteneau et al. [22] choose to use them as trigger elements for ESD power devices. Thus, a stack composed of thin silicon film triggering structures over a hybrid-bulk SCR was developed. The first innovative device, presented in Figure 3.27-a, is composed of a Z 2 -FET (Ln = Lp = 0.15 µm) on top of SCR (Z 2 -FET enhanced Stacked SCR, ZeST). To avoid back-gate biasing, the Z 2 -FET Lp part of the channel was doped using P-type ion implantation. In the second stacked device, called BeST (Figure 3. The robustness and high current performance of ZeST and BeST stacked devices for 100 ns pulse width (HBM equivalent) were explored using TLP characterization method. In addition of tunable triggering voltage, low leakage current and high current drive capability, ZeST and BeST devices consume less surface (75%) than bulk-SCRs with an external hybrid-bulk FET trigger. With these very promising results, the use of Z-FET family structures is highly recommended as triggering elements for ESD protection of power devices.

Interface Potential Analytical Model

Introduction

The feasibility of band-modulation devices in advanced FDSOI technology was demonstrated successfully. DC and TLP measurements were presented, showing the outstanding features of Z-FET family devices. Now, to evaluate these structures by designers before fabrication and to determine their benefit at application level, a full compact model is needed. An analytical model of Z 2 -FET DC operation, compatible with SPICE simulator, was published recently [24]. The model generates the S-shaped IA-VA curve numerically with fitting parameter; the values of inversion/depletion surface potentials were evaluated through an adaptation of Leti-UTSOI model [25,26]. A sophisticated physics-based model for Z 2 -FET was derived in [27]. It is based on the continuity of the total current for each of three junctions: at anode, cathode and the center of the body, respectively. However, the model relies on numerical resolution of a set of 5 equations, which is not suitable for SPICE simulator. Since the simplest possible calculation chain is needed to get an efficient compact model, an analytical calculation of 28FDSOI Z 2 -FET interface potential, using

Poisson's equation and a parabolic function approach, is presented in the following, taking into consideration the internal voltage Vin (shown in Figure 3.30). The innovative idea here is to calculate the surface potential in every part of the channel separately, and then combine them after the evaluation of internal voltage Vin. The 2-D Poisson's equation was solved in the weak inversion/accumulation regimes of Ln/Lp channel parts, respectively, neglecting the mobile charges in the ultrathin film. Then, for strong inversion and accumulation regimes, we compute the value of surface potentials as they tend to saturate (adapted from Leti-UTSOI model), and propose an estimation with a smoothing function taken from [25].

The model was then applied for Z 2 -FET (tox = 3.2 nm, tbox = 25 nm, tSi = 7 nm for Ln part and 22 nm for Lp part) with different Ln, p lengths at VA = 0 V and different front and back-gate voltages. In the following, a detailed calculation of surface potential distribution in the whole Z 2 -FET body is given and compared, at the end of this section, with other Z-FET family devices.

Potential Distribution Model

Z 2 -FET SGP  Ln part

The potential distribution (x, y) in the undoped thin silicon film of Z 2 -FET is governed by

Poisson's equation [28,29]:

𝑑 2 (𝑥, 𝑦) 𝑑𝑥 2 + 𝑑 2 (𝑥, 𝑦) 𝑑𝑦 2 = 𝑞𝑁 𝐴 𝜀 𝑆𝑖 0 ≤ x ≤ L 𝑛,𝑝 and 0 ≤ y ≤ t 𝑆𝑖 , (3.3)
where NA is the channel doping concentration, Si is the dielectric constant of silicon, tSi is the silicon thickness (which is not uniform in the whole structure because of epitaxy layer in uncovered part of the channel) and Ln,p is the length of gated and ungated Z 2 -FET parts, respectively. Before the onset of strong inversion, in the gated part of the channel, the potential (x, y) can be approximated by a simple parabolic function along the vertical 'y' dimension [30]:

Φ(𝑥, 𝑦) ≈ 𝐶 0 (𝑥) + 𝐶 1 (𝑥) • 𝑦 + 𝐶 2 (𝑥) • 𝑦 2 , (3.4)
where the coefficients 𝐶 0 (𝑥), 𝐶 1 (𝑥), and 𝐶 2 (𝑥) depend only on 𝑥. For fully depleted SOI Z 2 -FET, the potential at the front-interface of gated part f (𝑥, 0) is different from that at the back-side b (𝑥, tSi). The boundary conditions at the channel-oxide interfaces can be written using Gauss's law in the y-direction:

𝑑Φ(𝑥, 𝑦) 𝑑𝑦 | 𝑦 = 0 = 𝜀 𝑜𝑥 𝜀 𝑆𝑖 Φ 𝑓 (𝑥) -𝑉 𝐺𝐹 𝑡 𝑜𝑥 (3.5) 𝑑Φ(𝑥, 𝑦) 𝑑𝑦 | 𝑦 = 𝑡 𝑆𝑖 = 𝜀 𝑜𝑥 𝜀 𝑆𝑖 𝑉 𝐺𝐵 -Φ 𝑏 (𝑥) 𝑡 𝑏𝑜𝑥 , (3.6)
where VGF = VGf -VFBf and VGB = VGb -VFBb are the front-gate and back-gate voltages, respectively, ) are the flat band voltages at the front and back interfaces, respectively, where VT is the thermal voltage and ni is the intrinsic carrier concentration. The acceptor concentration of the channel is given by NA, channel (10 15 cm -3 )

ox
and that of the P-type ground plane by NA, GP-P (10 18 cm -3 ). Solving the system of (3.2)-(3.4), the obtained 𝐶 𝑖 (𝑥) coefficients are:

𝐶 0 = Φ 𝑓 (𝑥), (3.7
)

𝐶 1 = 𝜀 𝑜𝑥 𝜀 𝑆𝑖 Φ 𝑓 (𝑥) -𝑉 𝐺𝐹 𝑡 𝑜𝑥 , (3.8)
Substituting the 𝐶 𝑖 values in (3.2) and taking the derivative in (3.1), we get the following 2 nd order differential equation:

𝑑 2 Φ 𝑓 (𝑥) 𝑑𝑥 2 -𝛼 𝑓 Φ 𝑓 (𝑥) = 𝛽 𝑓 . (3.10)
To simplify the equations, we assumed that the back-gate oxide capacitance Cbox = ox/tbox is much smaller than both the front-gate oxide capacitance Cox = ox/tox and the silicon film capacitance CSi = Si/tSi. Thus, f and f can be approximated as:

𝛼 𝑓 ≈ 𝜀 𝑜𝑥 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑜𝑥 , (3.11
The particular solution of the 2 nd order differential Eq. (3.8) is calculated and given by:

𝐴 1 = 𝛽 𝛼 = 𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑜𝑥 𝜀 𝑜𝑥 -(𝑉 𝐺𝐹 + 𝑡 𝑜𝑥 𝑡 𝑏𝑜𝑥 𝑉 𝐺𝐵 ). (3.13)
The boundary conditions of the gated part of the channel are Φ 𝑓 (0) = 𝑉 𝑖𝑛 𝑎𝑡 𝑥 = 0 and Φ 𝑓 (𝐿 𝑛 ) = 𝑉 𝑏𝑖 + 𝑉 𝐴 𝑎𝑡 𝑥 = 𝐿 𝑛 (where 𝑉 𝑏𝑖 = 𝑉 𝑇 ln (

𝑁 𝐴 𝑛 𝑖
) is the built in potential across the anode-channel junction). With these values and the particular solution, the expression along the Ln part of the front interface potential is obtained:

Φ 𝑓 (𝑥) = 𝐴 1 + 1 𝑒 2𝐿 𝑛 𝜆 1 -1 [(𝑉 𝑏𝑖 + 𝑉 𝐴 -𝐴 1 ) (𝑒 𝐿 𝑛 +𝑥 𝜆 1 -𝑒 𝐿 𝑛 -𝑥 𝜆 1 ) + (𝑉 𝑖𝑛 -𝐴 1 ) (𝑒 2𝐿 𝑛 -𝑥 𝜆 1 -𝑒 𝑥 𝜆 1 )], (3.14)
where

𝜆 1 = 1 √ 𝛼 𝑓 = √ 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑜𝑥 𝜀 𝑜𝑥 . (3.15)

 Lp part

The same procedure was applied to the ungated part of the channel (Lp). We assume that the potential at the surface f (x, 0) = 0. Thus a new 2 nd order differential equation is obtained:

𝑑 2 Φ 𝑏 (𝑥) 𝑑𝑥 2 -𝛼 𝑏 Φ 𝑏 (𝑥) = 𝛽 𝑏 , (3.16)
where

𝛼 𝑏 = 𝜀 𝑜𝑥 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 , (3.17)
𝑎𝑛𝑑 𝛽 𝑏 = 𝑞𝑁 𝐴 𝜀 𝑆𝑖 - 𝜀 𝑜𝑥 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝑉 𝐺𝐵 . (3.18)
The boundary conditions of this region are Φ 𝑏 (0) = 𝑉 𝑏𝑖 𝑎𝑡 𝑥 = 0 and Φ 𝑏 (𝐿 𝑝 ) = 𝑉 𝑖𝑛 𝑎𝑡 𝑥 = 𝐿 𝑝 (where 𝑉 𝑏𝑖 = 𝑉 𝑇 ln (

𝑁 𝐷 𝑛 𝑖
) is the built-in potential across the cathode-channel junction). The expression along the Lp part of the channel at the front interface is obtained:

Φ 𝑏 (𝑥) = 𝐴 2 + 1 𝑒 2𝐿 𝑝 𝜆 2 -1 [(𝑉 𝑖𝑛 -𝐴 2 ) (𝑒 𝐿 𝑝 +𝑥 𝜆 2 -𝑒 𝐿 𝑝 -𝑥 𝜆 2 ) + (𝑉 𝑏𝑖 -𝐴 2 ) (𝑒 2𝐿 𝑝 -𝑥 𝜆 2 -𝑒 𝑥 𝜆 2 )], (3.19)
with

𝐴 2 = 𝑉 𝐺𝐵 - 𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝜀 𝑜𝑥 , (3.20)
and

𝜆 2 = √ 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝜀 𝑜𝑥 . (3.21)

 The internal potential Vin

The surface potential of each part of Z 2 -FET device was evaluated separately. To have a continuous potential distribution all along the channel, Φ 𝑓 (𝑥) and Φ 𝑏 (𝑥) should be connected with Vin (the common internal voltage). The lateral electric field continuity between the two parts of Z 2 -FET (Ln and Lp, Eq. (3.20)) allows computing the value of Vin presented in Eq. (3.21). ) -1)].

𝐸 𝑏 (𝑥 = 𝐿 𝑝 ) = 𝑑Φ 𝑏 (𝑥) 𝑑𝑥 | 𝑥 = 𝐿 𝑝 = 𝐸 𝑓 (𝑥 = 0) = 𝑑Φ 𝑓 (𝑥) 𝑑𝑥 | 𝑥 = 0 , (3.22

Model Verification

 Weak accumulation/inversion

The proposed model was verified by comparing the analytical equations with Synopsis TCAD simulation results (Figure 3.31-a). At low front-gate and back-gate voltages (VGf = 0.5 V and VGb = -0.5 V), the Ln and Lp regions of Z 2 -FET are in weak inversion ( 10 17 cm -3 ) and accumulation ( 10 15 cm -3 ), respectively. A perfect agreement is obtained between the model (red solid line) and numerical results (black dashed line) all over the channel.

 Strong accumulation/inversion

The evolution of surface potentials Φ 𝑓 (𝑥) with VGf and Φ 𝑏 (𝑥) with VGb are presented in Figure 3.32-a, c. When the electrons density approaches 10 18 cm -3 (Figure 3.32-b), the Ln part enters into strong inversion, thus inducing a surface potential Φ 𝑓 (𝑥) saturation. This can be seen in Figure 3.32-a when the front-gate bias goes beyond VGf = 0.6 V. The same action is observed in Figure 3.32-c where Φ 𝑏 (𝑥) saturates when the holes density exceeds ~ 10 17 cm -3 (Figure 3.32-d) for

VGb ≥ -1.0 V. The model above did not take into consideration the surface potentials saturation in the channel. To reproduce a similar surface potential behavior at high front and back-gate biases in both parts of Z 2 -FET, the saturation values of interface potentials in each part were calculated. We assumed here that the Z 2 -FET is a long FDSOI device with undoped channel. The capacitance Ctot of the MOS system is given by the series connection of oxide Cox and inversion channel Cinv capacitances. Since in strong inversion regime (Ln region) Cinv ≫ Cox, Ctot = Cox. For same reason, Ctot in accumulation takes the value of BOX capacitance (Ctot = Cbox) in strong accumulation regime (Lp region) [25]. The expressions of saturated Φ 𝑓 (𝑥) and Φ 𝑏 (𝑥) are given by:

Φ 𝑓,𝑠𝑎𝑡 (𝑥) = 3𝑉 𝑇 + 𝑉 𝑇 ln ( 𝑉 𝑇 𝐶 𝑜𝑥 𝑞𝑛 𝑖 𝑡 𝑆𝑖 ) (3.24)
Φ 𝑏,𝑠𝑎𝑡 (𝑥) = 3𝑉 𝑇 + 𝑉 𝑇 ln ( 𝑉 𝑇 𝐶 𝑏𝑜𝑥 𝑞𝑛 𝑖 𝑡 𝑆𝑖 )

We make the estimation of interface potentials that tend to their respective saturation values with a smoothing function [25]:

Φ 𝑓,𝑓𝑖𝑛𝑎𝑙 (𝑥) = Φ 𝑓 (𝑥) -3𝑉 𝑇 (1 + 𝑒 [Φ 𝑓 (𝑥)-Φ 𝑓,𝑠𝑎𝑡 (𝑥)] 3𝑉 𝑇 ) (3.26) Φ 𝑏,𝑓𝑖𝑛𝑎𝑙 (𝑥) = Φ 𝑏 (𝑥) + 3𝑉 𝑇 (1 + 𝑒 [-Φ 𝑏 (𝑥)-Φ 𝑏,𝑠𝑎𝑡 (𝑥)] 3𝑉 𝑇 ) (3.27)
The evaluation of surface potential in the whole channel of Z 2 -FET obtained with the resolution of analytical equations is compared with TCAD simulation results at relatively high front and back-gate biasing in Figure 3.33-a, b. It is clearly seen that the potentials calculated by the model agree very well with the simulation results over the whole channel. The model was applied also to short (Figure 3.34-a) and long (Figure 3.34-b) Z 2 -FET devices.

The accuracy of the model is still good for different device lengths. It is noticed that, for VGf = 0.5 V or 1 V, the Ln barrier controlled by the gate is strong and the surface potential value is the same for short and long structures. On the other hand, the Lp barrier is affected by reducing the device length and starts to erode, as seen in Figure 3.34-a. In the following, we present the surface potential computation of Z 2 -FET DGP and Z 3 -FET devices.

Z 2 -FET DGP and Z 3 -FET

Same analytical procedure was applied to other Z-FET devices. Remember that, for Z 2 -FET DGP, the GP-N cooperates with the front-gate and reinforces the barrier in this region. For this purpose, in Ln part of the channel, the negative "VGB" term in Eq. (3.11) is replaced by "VGbN" with positive values. The potential distribution in the two parts of the channel (Φ 𝑛 (𝑥) for Ln and Φ 𝑝 (𝑥)

for Lp) is given by: (3.34)

Φ 𝑛 (𝑥) = 𝐴 1 + 1 𝑒 2𝐿 𝑛 𝜆 1 -
The interface potential distribution model is computed for Z 2 -FET DGP and Z 3 -FET variants and compared to standard Z 2 -FET with single GP (Figure 3.35) in weak inversion/accumulation regimes for Ln and Lp, respectively. As it is modulated by ground planes (N and P) with a thick back-gate oxide (tbox = 25 nm), the Z 3 -FET exhibits narrower Ln barrier as seen in Figure 3.35 (dotted black curve). On the other side, and compared to Z 2 -FET with single ground plane, the Ln barrier of Z 2 -FET DGP is stronger at VGf = 0.5 V. This is due to the presence of GP-N underneath the front-gate that reinforces the potential in this region even for zero bias (VGbN = 0 V).

Conclusion

A complete DC measurements set of band-modulation devices with promising results was presented in this chapter. These measurements showed that Z-FET structures feature an adjustable triggering voltage, low leakage current, large hysteresis and high current ratio ION/IOFF. The high current performance of these devices was also explored with TLP characterization, showing a good robustness against ESD events that is suitable for 1.0 V, 1.8 V and 3.

Capacitor-less Dynamic Random Access Memory: 1T-DRAM Application

Can we store and read simultaneously a bit of information in a single transistor without using an external storage capacitor? The answer lies at devices with isolated silicon channel (discussed in Chapter 1). They offer, in the form of charges, bit storage in the floating body, which is also used to read the memory state. As they are not entirely convincing, existing 1T-DRAM versions are not commercialized yet. While some of them consume relatively high power during writing mode [10,15,16] , other variants suffer either from super-coupling (beyond tSi = 10 nm) [9,[17][18][19][20] or technology constraints [21][22][23]. To address these issues, we propose the Z 2 -FET as a novel 1T-DRAM cell, which is fully compatible with 14 nm and 28 nm FDSOI fabrication process.

Operation Principle

In conventional 1T-DRAM, the shift of threshold voltage due to the excess or absence of holes in the body indicates the existence of a memory effect [24]. In Z-FET devices, the triggering

Memory Operation Analysis via TCAD Simulation

Thanks to TCAD simulations, a deep analysis of the Z 2 -FET operation as capacitor-less DRAM is carried out in this sub-section. Promising results are presented. It is shown that with reduced anode voltage for logic "1" writing, the power consumption is significantly reduced.

Read/write operations can be achieved with 1 ns pulse widths. Also, understanding why the device could lose its "0" state is succeeded by monitoring the concentration of carriers and surface potential. Finally, the properties of GO1 (thin gate oxide) Z 2 -FET memory are examined.

Detailed Explanation of Z 2 -RAM Operation Principle

The state of the Z 2 -FET at each critical memory step was studied via numerical simulations with the set of parameters given in Chapter 2 (section 2.2.2.1). Experimental results were confirmed by the simulated current window (I1-I0), which is equal to 25 µA/µm (Figure 4.3). In the following, the memory operation is detailed by monitoring the surface potential, carrier concentration and total current density in the two parts of the channel. The total currents during critical "1" and "0" writing and reading memory processes are illustrated in Figure 4.5. Since the drain voltage is zero at "W0", the current does not flow in the channel (Figure 4.5-a). The electron-less Ln part, after W0, features a strong barrier in this region and does not permit the anode pulse to read "0", collapse the barriers and turn on the diode. The result can be seen in Figure 4.5-b where the current I0 is negligible. On the other hand, programming the state "1" demands a positive drain bias and zero front-gate bias (VGf = 0 V). In this case, the Z 2 -FET acts as a forward-biased PIN diode with a high flow of current as indicated in Figure 4.5-c. The obtained current density in Figure 4.5-d is a consequence of barriers collapse and carriers flow from node to node due to a positive VA pulse.

Reduced Power Consumption

The capability of reducing Z 2 -FET DRAM power consumption is presented in Figure 4.6 [30,31]. Decreased anode voltage for logic "1" writing (VA(W1) = 0.

High Access Speed

The discharge current ∆QGf/∆t is a key feature of Z 2 -FET single-transistor DRAM [8].

Basically, the memory readout operation does not depend only on the charge stored under the gate but also on how fast the front-gate capacitance is discharged. In simulation, the read/write times reach 1 ns, easily outperforming conventional DRAM (Figure 4.8).

Retention Time

Unlike state "1", which is stable and does not need to be refreshed, holding "0" information in the body of Z 2 -FET is a critical problem. To understand the mechanism of the proposed 1T-DRAM when storing logic "0", helpful simulation results are discussed in this paragraph. The computed value of "0" state retention obtained with transient experiments is presented later in this chapter. Three simulation methodologies for "0" retention time are proposed. The first one presented in Figure 4.9-a consists of maintaining high VGf for 10 ms after setting "0" at the beginning of the bias scheme (inset of Figure 4.9-a). As VA = 0 V, the increased number of electrons under the front-gate noticed in Figure 4.9-b are supplied by carrier generation. As a result, the accumulated electrons lower the potential in the gated region inducing a weaker holes injection barrier not capable to resist the anode reading pulse. Thus, the "0" data is lost. This operation mode provides approximatively the real "0" retention time of Z 2 -FET DRAM. The second strategy used to evaluate "0" retention time is schemed in Figure 4.10-a. After "0" programming, a set of many regular fast pulses is send to the anode of Z 2 -FET with a period of 500 ns (Figure 4.10-b). The idea is to observe the behavior of DRAM cell after each VA read signal.

Normally, frequent reading of logic "0" improves the retention time as the accumulated electrons under the gate are swept into the anode (self-refresh). This can be seen in Figure 4.10-c, d where the concentration of electrons decreases slightly implying stronger barrier in the gated region.

However, the electron injection barrier in Lp region tends to increase due to the flow of parasitic holes after each VA pulse, which eventually would trigger the positive feedback and highly affect the retention time. Results presented in Figure 4.11 (3 rd operation mode) are not considered to evaluate the real "0" retention time as a long VA pulse is applied to Z 2 -FET after programming logic "0" (inset of Figure 4.11). Simulations were carried out to confirm that a continuous VA reading highly improves the retention time of state "0". Carrier concentration does not evolve during the whole bias pattern giving rise to a stable surface potential and almost an infinite "0" state holding time.

GO1 Z 2 -FET with Thin Gate-Oxide

Operating nearly and even under 1 V of supply voltage is a wish of every memory cell developer. This goal is almost achieved with thin gate-oxide (GO1) Z 2 -FET. The memory operation was investigated in details with TCAD simulations. In the following, experimental results of advanced FDSOI Z-FET devices are presented in a wide range of temperature.

Measurement Bench

Transient measurements were carried out using Cascade S300-based semi-automatic test bench monitored by "Nucleus" software, Agilent B1530A waveform generator/fast measurement unit (WGFMU), which is a plug-in module for the Agilent B1500A semiconductor device analyzer, connected to two remote-sense and switch units (RSU) by special composite cables (1.5 m) and DC probe card (Figure 4.13). The WGFMU provides two operation modes: fast current or voltage measurement mode (Fast IV) and pulse generator mode (PG mode). Following connections were used:

 RSU connected to the anode operating in Fast IV mode, which is able to create arbitrary waveforms via the ALWG function and measure at the same time the anode current.

 RSU connected to the front-gate working in PG mode and creating narrow voltage pulses.

Transient Experimental Results

In this section, band-modulation devices are demonstrated experimentally in 28 nm and 14 nm FDSOI nodes as low power/voltage 1T-DRAM embedded memories [30][31][32][33]. Retention time and memory margins at room and high temperature are presented, revealing the high performance of band-modulation devices as single-transistor memory. In addition, the impact of additional ground plane (in Z 2 -FET DGP) and SiGe layer (in Z 3 -FET) on memory behavior for enhanced power consumption is outlined. Finally, the ability of setting 1T-DRAM matrix with Z 2 -FET is also studied.

Z 2 -FET as 1T-DRAM in 28 nm FDSOI Technology a. Memory Margin

The hold-write-hold-read bias pattern applied on 28 nm Z 2 -FET and corresponding readout current are shown in As discussed before in section 4.2.2.2, the memory readout operation does not depend on the charge stored under the gate but on how fast we can access the memory cell. Based on TCAD simulations and results obtained in Figure 4.16, a low-voltage writing scheme of state "1" was proposed to reduce the power consumption of Z 2 -FET operating as 1T-DRAM.

As shown in Figure 4.17 starts decreasing and disappears at VA(W1) ≤ 0.3 V (Figure 4.17-b, c). However, increasing the anode voltage reading enhances the current margin. This can be seen in Figure 4.17-c, where the difference between read and write "1" currents is still significant despite the low-voltage "1" programming state (IR1 -IW1 = 45 µA/µm for VA(W1)= 0.3 V, blue square symbols).

b. Retention Time

Z 2 -FET features a stable "1" state with no need to be refreshed. The only matter of singletransistor DRAM is how long the "0" state can be maintained before it degrades. Two experimental different modes were used to extract logic "0" retention time: hold-read "0" operation ( As it improves the holes injection barrier, state "0" holding duration increases with front-gate bias. When VA approaches from VGf, the "0" state is lost rapidly (~ 250 µs, black square symbols in Figure 4.19) with remarkable I0 current (7 µA/µm). At slightly higher VGf, the "H0" period becomes long (> 4 ms) and I0 current is suppressed. The second method for measuring "0" state retention time is presented in Figure 4.20. The bias scheme applied to Z 2 -FET consists first of logic "1" programming and read followed by writing "0" and continuous reading with a long VA pulse (550 ms, Despite "0" writing and eliminating the accumulated electrons under the gate, the anode pulse can turn on the device, thus implying a higher I0 current. This issue can be solved by increasing the front-gate bias that reinforces the Ln barrier and reduces or stops the flow of holes into the channel.

In addition, the anode bias can be reduced at high temperature, still maintaining a respectable sensing margin (I1/I0 = 2.3 × 10 4 for VA = 1 V, red square symbols in

b. Z 2 -FET DGP

As it cooperates with the front-gate and reinforces the barrier in this part, the GP-N tolerates the aggressive downscaling of the gated region beyond 100 nm without affecting the device behavior. The power consumption while writing logic "1" can be also reduced in Z 2 -FET with dual ground planes (see Figure 3.6, Chapter 3). Figure 4.26 shows the variation of I1 current after applying reduced anode voltage for programming state "1". We can see that decreasing VA(W1) does not only eliminate the program "1" current but also affects, beyond 0.7 V, the "1" read current that almost disappears at VA(W1) = 0.5 V.

Z 2 -FET Memory Cell in a Matrix

The elementary Z 2 -FET memory cell (1T-DRAM) scheme is given in preventing the flow of unwanted current that could disorder the state of other memories sharing the same bit line. As it is perpendicular to both parallel word and select lines, the bit line offers a selective "1" writing operation. In contrast, programming logic "0" is still an issue as it depends only on VGf bias. If the front-gate signal switches off, all memory cells participating the same word line are set to "0". This information loss requires a memory state refresh. Logic "0" programming operation is preceded by a check of cells sharing the same word line and followed by writing "1"

where it was stored. Unlike other 1T-DRAM structures [9,23,34], the refresh of Z 2 -FET is not power-consuming, which is an excellent feature (see also section 4. As the integration density of DRAM cells is an important factor, another matrix was designed with reduced size, but without reaching the minimal 28 nm FDSOI design rules. The layout presented in Figure 4.33 consists of 2x2 1T-DRAM array using Z 2 -FET devices. This time and for more density integration, the MOS selector was distributed and connected to the cathode of each Z 2 -FET sharing the same select line. The area of the Z 2 -FET bit cell is given by: 𝐴 𝑍 2 -𝐹𝐸𝑇 = (𝑊 + 𝐿 𝑅𝑋 ) . (𝐿 𝑠𝑜𝑢𝑟𝑐𝑒 + 𝐿 𝑠 + 𝐿 𝑝𝑜𝑙𝑦-𝑅𝑃𝑂 + 𝐿 𝑝 + 𝐿 𝑛 + 𝐿 𝑝𝑜𝑙𝑦-𝑐𝑜𝑛𝑡𝑎𝑐𝑡 ) (4.35)

The width of Z 2 -FET structure is defined by W, LRX is the space between two adjacent silicon active zones, the length of the MOS source is delimited by Lsource, Ls is the selector transistor length and Lpoly-RPO and Lpoly-contact stand for the distance between the polysilicon and Resist-Protection-Oxide layer (RPO) from a side and the via contact from other side respectively. Ln (gated part) and Lp (ungated part) define the length of Z 2 -FET.

Compared to DRAM developed by TSMC at the same technology node [35], the area of the designed Z 2 -FET (Lp = 200 nm and Ln = 120 nm in Figure 4.33) is eight times larger (0.286 µm 2 > 8 × 0.035 µm 2 ). The selector transistor (Ls = 48 nm) is an essential element in this matrix but it negatively affects the bit cell area. Improving the surface depends not only on downscaling the Z 2 -FET but also on the large distance between polysilicon and silicide-block layer (Lpoly-RPO). With scaled Z 2 -FET (Lp = Ln = 138 nm) using minimum design rules of 28 nm FDSOI node, the bit cell area ratio shrinks down to 0.08 µm 2 offering a large integration density Dmm² = 11.93 Mb/mm 2 (~ 2.2 times < 27.24 Mb/mm 2 , which is the integration density of 28 bulk planar eDRAM [35]). The estimation of Dmm² without taking into account peripheral circuitry (current sense amplifier SA, drivers/decoders lines …) can be expressed by: 𝐷 𝑚𝑚 2 = 1 𝐴 𝑍 2 -𝐹𝐸𝑇 . 1𝑀𝑏𝑖𝑡𝑠 In addition to all presented features and even if they exhibit larger bit cell area, the reduced processing cost and simplicity of band-modulation devices will be the motivation of using them as embedded 1T-DRAM (eDRAM).

Z 2 -FET DGP as a Logic Switch in 14 nm node

The presence of hysteresis in band-modulation devices is beneficial as they can be used as ESD protection and capacitor-less dynamic memories. In this section, transient experiments were carried out, showing the possibility of eliminating, in particular conditions, the typical hysteresis and turn off Z-FET devices once they are triggered.

Transient Experimental Results

Measurements were carried out on Z 2 -FET DGP (Lp = Ln = 200 nm) in 14 nm FDSOI technology using the same equipment employed for memory tests. The bias scheme for turning off the device is presented in

Advantage of Ground Plane N Bias

The N-type ground plane placed underneath the front-gate is extremely beneficial for Z 2 This feature is unique at Z 2 -FET DGP making the present novel device highly recommended as a logic switch.

Conclusion

Band-modulation devices in most advanced FDSOI technologies have been presented as promising architectures for future embedded capacitor-less DRAM (eDRAM) applications. The Z 2 -FET memory operation principle was deeply analyzed using TCAD simulations. Understanding the device response when holding "0" state was achieved by monitoring the carrier concentration and surface potential. Thanks to the small gate capacitance, the programming/reading time can be reduced to 1 ns. Thinning the gate oxide features a better electrostatic control of Ln region offering a reduced front-gate bias. In addition, experimental results of 28 nm FDSOI Z 2 -FET as dynamic RAM cell were described. The device brings forward a remarkable current sense margin and high "0" retention time in a wide range of temperature. In 14 nm node, Z-FET devices with stronger barriers can operate with grounded GP bias. Furthermore, the additional GP-N in Z 2 -FET DGP tolerates the downscaling of the gated part beyond 100 nm, without affecting the device behavior.

Combining germanium with silicon in the body allows an ultra-low voltage memory operation (nearly 1 V) with very high current. The power consumption reduction, which is peerless for other

Conclusion and Perspectives

This study was aimed at exploring the concept and applications of band-modulation devices in 14 nm and 28 nm FDSOI technology nodes. In this context, a review of alternative variants has been given showing the possibility of obtaining a swing switch lower than SS = 60 mV/decade, the nightmare of MOSFET transistor. While the abrupt change of some of sharp-switch devices is a result of ferroelectric material polarization, mechanical contact or band-to-band tunneling, the operation mechanism of Z-FET structures relies on simple electrostatic band-modulation.

They are similar to gated diodes, but operated in forward-bias mode. The injection of holes/electrons from anode/cathode terminals into the channel is prevented by electrostatic barriers formed via front/gate biasing. Once VA reaches the triggering voltage, the device turns on sharply (≤ 5 mV/decade) to a high current. TCAD simulations were carried out on Z 2 -FET structure to explain the different physical mechanisms (Generation/Recombination, Diffusion, non-sustainable continuity between G/R and diffusion currents) governing its static DC operation.

We have concluded on the important influence of carrier lifetime.

Extensive DC measurements of 14 nm Z-FET family devices with different geometries were carried out in a wide range of temperature. Z 2 -FET features promising results in terms of sharpswitch, low leakage current, adjustable triggering voltage, large hysteresis and high current ION/IOFF ratio. However, the presence of negatively biased P-type Ground Plane (VGb < 0 V) under the whole structure affects by coupling effect the barrier of the gated part and reduces VON. This undesirable outcome for some applications has been the motivation to propose a novel variant, Z 2 -FET DGP, with a second GP-N placed underneath the front-gate. The N-type Ground Plane cooperates with the front-gate and enhances significantly the triggering voltage VON. The third fabricated free-surface (no front-gate) variant, Z 3 -FET, operates with only back-gates. It features similar sharp-switch characteristics with the possibility of working with high GP voltage bias. The effect of doping one part of the channel and introducing new materials (SiGe) into the body on Z-FET devices parameters has also been highlighted.

Thanks to their attractive characteristics, band-modulation devices can be used for many applications. In this thesis, we focused on:  Electro-Static Discharge (ESD) protection. The high current performance of Z-FET structures was investigated using TLP characterization method. Z 2 -FET and Z 3 -FET with undoped silicon channel feature high robustness against current discharge events and can fit the ESD window of 1.0 V and 1.8 V according to their different geometries, silicon thickness and front/back gates biases. However, they need external triggering circuit in order to be transparent during the normal operation of protected circuit. The doped Z 3 -FET overcomes this issue as it does not need an outer bias. The possibility of using band-modulation devices as triggering elements instead of power components has been underlined. Stacked architectures improve the behavior of classical SCR in bulk technology.

 1T-DRAM operation. The hysteresis obtained in static DC measurements indicates the existence of memory effect. In this context, a complete analysis of Z 2 -FET operating as 1T-DRAM with very fast access was reported using TCAD simulations followed by exhaustive systematic transient measurements for all Z-FET devices. The memory operation relies on the presence or not of electrons under the front-gate. In 28 nm node, Z 2 -FET exhibits remarkable current margin I1/I0 and high retention working at nearly 1 V on anode and front-gate terminals but with VGb = -1 V. The negative bias on the ground plane is no longer necessary in 14 nm node as the barriers are stronger. However, obtaining similar I1 current as in 28 nm node requires a higher VA. The possibility of reducing the power consumption in Z-FET DRAMs is achieved by decreasing the anode voltage when programming "1" state. In addition, short Z 2 -FET DGP benefits from the presence of GP-N to lower VGf. The Z 3 -FET with SiGe has also been characterized showing outstanding memory results. As the barriers are weaker, the nearly 1 V anode pulse results in a high current margin. Following the successful demonstration of Z-FET devices as elementary 1T-DRAM, a 2x2 matrix has been designed and fabricated in 28 nm node. The MOS selector added to each select line is essential as it prevents the flow of unwanted current that could disturb the state of other cells. However, it affects negatively the bit cell area. Improving the density of integration requires a severe scaling of Z-FET devices beyond 200 nm. We believe that Z 2 -FET DGP can complete this objective.

 Logic switch. Transient measurements were performed on Z 2 -FET DGP in 14 nm FDSOI technology. We showed that the hysteresis, which is beneficial for Z-FET devices operating as 1T-DRAM and detrimental for logic circuits, can be eliminated in particular conditions. Once it is triggered, the band-modulation device can be turned off successfully with front-gate pulse. The impact of device parameters (VGf, VA, VGbN) and length (Ln + Lp) on current ratio ION/IOFF was studied showing the capability of turning off Z 2 -FET DGP with only VGf = 0.4 V (if VGbN > 1 V).

In order to evaluate the capability of band-modulation devices by designers before fabrication, a full compact model is needed. We proposed an analytical model of surface potential distribution for all Z-FET structures. The potential is calculated separately for each part of Z-FET variant and combined together with electric filed continuity equations at Vin (internal voltage node). The model shows a good accuracy and is valid for short and long devices.

After clarifying the static and transient operation principles and demonstrating the superior characteristics of structures investigated in this thesis, the question now is : which device could be adopted and for which application ?

  Thank you Elodie for being by my side all these years. You have been a part of this successful work. I cannot finish without saying how grateful I am to my family. Without them I could not have been succeeded my career. Thank you my father Souleiman, my mother Daad and of course thank you my only brother and best mate Houssein. Thank you for supporting and encouraging me all the time. Thank you all.

Figure 1 . 1 .

 11 Figure 1.1. Schematic cross-section of N-type MOSFET transistor on 28 nm Bulk technology.

Figure 1 . 2 .

 12 Figure 1.2. (a) Transistor manufacturing cost and (b) minimum scaling cost at recent technology nodes (GlobalFoundries 2015).

Figure 1 . 3 .

 13 Figure 1.3. Schematic of SOI wafers fabrication using SmartCut® technique supported by SOITEC Company.

Figure 1 . 4 .

 14 Figure 1.4. Schematic view of (a) standard and (b) flipped well MOSFET transistors in UTBB FDSOI technology. (c) 28FDSOI Front-End process flow.

Figure 1 . 5 .

 15 Figure 1.5. (a) Schematic view and (b) band diagram in ON/OFF states of planar all-Si TFET in silicon-on-insulator technology.

Figure 1 . 6 .

 16 Figure 1.6. Room temperature experimental ID-VG characteristics of the first TFET showing SS < 60 mV/decade (adapted from W. Y. Choi et al. [21]).

Figure 1 . 7 .

 17 Figure 1.7. Schematic structure of a generic Ferroelectric FET.

Figure 1 . 8 .

 18 Figure 1.8. Schematic view of suspended-gate FET (SG-FET).

Figure 1 . 9 .

 19 Figure 1.9. Cross sectional view of different NEM relay structures. (a) 2-Terminal (b) 3-Terminal and (c) 4-Terminal switches.

Figure 1 . 10 .

 110 Figure 1.10. Basic device structure of I-MOS on SOI and measured Id-Vg transfer characteristics for different drain bias (adapted from [47]).

Figure 1 . 11 .

 111 Figure 1.11. Schematic cross section and experimental DC IA-VA characteristics for different gate voltage VG1 and VG2 = 0 V of Field Effect Diode (FED) on SOI (adapted from [51]). LG1 = LG2 = 500 nm.

Figure 1 . 12 .

 112 Figure 1.12. Schematic view of different band-modulation Z-FET devices: (a) standard Z 2 -FET (b) Z 2 -FET with dual GPs and (c) Z 3 -FET with no front gate.

1 .

 1 13 defines the required specifications of an efficient protection element. The main important points presented in Figure 1.13 are the following:  Vdd: the circuit supply voltage. The protection component should trigger after Vdd and should be transparent before it.  VBD: the breakdown voltage of protected devices in a core circuit. It is the maximum value tolerated by the used technology. The protection mechanism should be efficient before this value.  (Vt1, It1): the turn-on voltage and triggering current of ESD protection device where it starts working, respectively.  (VH, IH): the holding voltage and current. Below VH, the device should be in OFF state.  (Vt2, It2): the maximum voltage and current values that a protection component can withstand. Above these points, the device is broken and does not work anymore.

Figure 1 .

 1 Figure 1.13. ESD design window and main required characteristics of electrostatic discharge protection devices.

Figure 1 .

 1 14-c shows metal melting that occurs by Joule heating effect when a high current flows through metal interconnections. Usually, a metal degradation is the consequence of another mechanism: it is possible that junction damage or gate oxide breakdown induce an open circuit, which greatly increases the current passing in metal interconnections, thus causing material melting.

Figure 1 .

 1 Figure 1.14. SEM photographs of different ESD-type failures: (a) damage at the drain/gate diffusion edge, (b) gate oxide damage and (c) metal interconnection melting [72].

Figure 1 . 1 )

 11 Figure 1.15) connected to the electronic chip by 1.5 kΩ resistance and an inductance of 7.5 µH representing the electric contact. Depending on application, the maximum voltage VESD a circuit can handle without incurring failures varies between 1 kV (RF, wireless, …) and 4 kV (automotive, military, …). Applying these values into the simplified Eq. (1.1) allows us to calculate the discharge current:

Figure 1 . 15 .

 115 Figure 1.15. Schematic equivalent circuit of ESD stress model HBM with typical parameters and its discharge current waveform (R = 1.5 KΩ, C = 100 pF, L = 7.5 µH and V = 2 kV).

  is different. The resistance and inductance values are greatly decreased (RESD = 10 Ω and LESD = 0.5 µH, metal contact) while the capacitance value is doubled (CESD = 200 pF).

Figure 1 .

 1 Figure 1.16. Schematic equivalent circuit of ESD stress model MM with typical parameters and its discharge current waveform (R = 10 Ω, C = 200 pF, L = 0.5 µH and V = 200 V).

Figure 1 . 17 .

 117 Figure 1.17. Schematic equivalent circuit of ESD stress model CDM with typical parameters and its discharge current waveform (R = 10 Ω, C = 10 pF, L = 2.5 µH and V = 1 kV).

Figure 1 . 18 .

 118 Figure 1.18. Classical schematic view of CMOS integrated circuit with ESD clamps and different input, output and supply voltage pads.

Figure 1 .

 1 19-a shows the "global" strategy in which a unidirectional clamp is placed beside each pad driving the discharge current into the central bidirectional protection element located between the supply voltage rail Vdd and ground pad Vss.Another approved method is called "local" strategy presented in Figure1.19-b. It consists of using just one bidirectional protection clamp situated beside each ESD source pad to evacuate at the same time positive (in red) and negative (in blue) discharge currents.

Figure 1 .

 1 Figure 1.19. Simplified ESD protection examples: (a) global strategy and (b) local strategy evacuating positive (in red) and negative (in blue) discharge currents.

Figure 1 .

 1 Figure 1.20. Time Domain Reflectometry (TDR) characterization technique.

Figure 1 . 21 .

 121 Figure 1.21. Time Domain Transmission (TDT) characterization technique.

Figure 1 . 22 .

 122 Figure 1.22. Time Domain Reflection and Transmission (TDRT) characterization technique.

Figure 1 . 23 .

 123 Figure 1.23. Equivalent circuits of VF-TLP and CC-TLP stress tests.

Figure 1 . 24 .

 124 Figure 1.24. Organigram of semiconductor volatile and non-volatile memories. Universal memory is a combination of perfect characteristics of these two categories of memories.

Figure 1 . 25 .

 125 Figure 1.25. Schematic presentation of 1T-1C Dynamic Random Access Memory (1T-1C DRAM) with trench and stacked capacitors.

Figure 1 . 26 .

 126 Figure 1.26. Schematic cross sections of N type MOSFET transistors in (a) Partially Depleted SOI technology where the floating body is isolated by the buried oxide or (b) by an implant N-type in the case of Bulk technology.

Figure 1 . 27 .

 127 Figure 1.27. In fact, the high electric field, induced by polarizing the transistor in saturation regime (VD >VDSAT, VG > 0 V), triggers the impact ionization phenomenon close to the drain zone. This mechanism generates pairs of electron-hole in the space charge region of the junction. Minority carriers are swept into the drain, positively biased (VD > 0 V), increasing the conduction current while majority carriers, driven into the neutral zone of the floating body, modify the body potential, VB. For example, for nMOS transistor (PDSOI or Bulk), the holes generated by ionization and injected in the floating substrate will increase the potential VB inducing a threshold voltage reduction. The threshold voltage Vth drop leads to a feedback mechanism that increases the drain current which is the origin of the bump observed in Figure 1.27.

Figure 1 .

 1 Figure 1.27. ID-VD output characteristics[START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI, 3rd Editio[END_REF] on N channel MOSFET showing the kink effect as a bump and ID-VG transfer characteristics[START_REF] Fossum | Anomalous Subthreshold Current-Voltage Characteristics of n-Channel SOI MOSFET's[END_REF] showing kink effect in the form of steeper subthreshold slope (SS = 103 mV/dec for VD = 1 V increases up to 17 mV/dec for higher VD = 5 V).

Figure 1 . 28 .

 128 Figure 1.28. Architectures of 1T-DRAM memory cell on Bulk: (a) Triple wells. Conventional STI together with N Well isolate laterally the floating body while the N-type implant ensures the isolation of the lower part of the substrate. (b) Second variant with deep STI. (c) Variant with buried implant layer N-type touching the conventional STI isolation.

Figure 1 .

 1 Figure 1.29. ID-VG transfer characteristics of N-channel SOI MOSFET transistor showing the 1T-DRAM memory "1" and "0" states.

Figure 1 .Figure 1 .

 11 Figure1.30-a. State "1" features at the same time a back inverted channel (VG2 > Vth2) and an accumulated front interface. It is programmed by applying a high negative front gate pulse (VG1P ~ -6 V) that triggers B2B tunneling and efficiently fills the front channel with holes. State "1" is revealed by a high current flow at the back channel. Programming "0" state is obtained by deep depletion of the device, achieved by applying a less negative front-gate pulse (starting from 0 V to VG1P ~ -3 V). At this time, the device does not reach equilibrium (because there are no holes available) and the channel goes into deep depletion; hence the back channel current is temporarily suppressed. This method, called capacitive coupling (CC), exhibits better results than impact ionization or forward biased junction mode (FBJ). The current margin is enlarged and the retention time is improved, as shown in Figure1.30-b. Another advantage of this cell is the low drain voltage in reading mode (VD ~ 0.1-0.2 V). Reading the memory state implies a moderate front-gate pulse (-4 V < VG1R < -2.3 V) leading to a long retention time.

Figure 1 . 31 .

 131 Figure 1.31. Two dimensions (2D) simulations for MSDRAM with 50 nm gate length, 40 nm silicon film thickness, 3 nm front oxide and 6 nm buried oxide. The retention time is 14 s for a marge of 1 decade between I1 and I0 at 25°C at low front gate voltage VG1 = -1.5 V. Programming time TP = 5 ns.

Figure 1 . 32 .

 132 Figure 1.32. Architecture of capacitor-less DRAM in FDSOI technology: (a) ARAM with a middle oxide (MOX) and (b) A2RAM with N + implant in the bottom of the undoped body.

Figure 1 . 33 .

 133 Figure 1.33. Schematic cross section of Z 2 -FET P-type transistor and experimental results for Z 2 -FET operating as 1T-DRAM showing high I1 current (~ 90 µA) and negligible "0" state current. tSi = 20 nm, tBOX = 140 nm, LG = 400 nm and ungated part LIN = 500 nm. (From J. Wan et al. [61]).

[ 113 ]

 113 (Figure 1.34-b) architectures, tends to combine the functionalities of nonvolatile memory (NVM) together with the volatile DRAM in a single device. This can be achieved by introducing new materials, such as nanocrystals or ONO stack, into the gate stack serving as an electron trapped zone for NVM operation. The body is used for storing holes ensuring 1T-DRAM mechanism. The NVM program/erase (P/E) mode can be carried out by either Fowler-Nordheim (FN) tunneling

Figure 1 . 34 .

 134 Figure 1.34. Architectures of unified memory combining nonvolatile functionality, using ONO stack, with the volatile function of 1T-DRAM in (a) double-gate planar MOSFET with ONO gate and (b) FinFET with surrounded gate all around the silicon film and ONO stack.

Figure 2 .

 2 Figure 2.11 for comparison) , the undoped Si film of Z 2 -FET is partially covered by a single highk metal front-gate (Ln part, gate length) whereas the rest of the channel is ungated (Lp part, intrinsic part length). The gate stack starts with a thermally grown oxide interface (SiO2) ensuring a good interface quality clean of fixed charges. The interface SiO2 layer (IL) is covered by high-k hafnium dioxide layer (HfO2, 18 < k < 20) improving the drive current and reducing the gate leakage. It is connected via a mid-gap metal layer (TiN or AlTiN) with a low resistance Poly-Si electrode followed by gate patterning and offset spacer formation. After the second spacer realization, the anode and the cathode are implanted (P + and N + with 10 20 cm -3 , respectively).

Figure 2 . 1 .

 21 Figure 2.1. Cross-section view of standard Z 2 -FET in 28 nm FDSOI technology featuring undoped ultra-thin silicon film (tSi = 7 nm), very thin buried oxide (tBOX = 25 nm) and epitaxial layer reducing series resistance (tepi = 15 nm).

Figure 2 . 2 .

 22 Figure 2.2. Schematic cross-section view of Z 2 -FET in 14 nm FDSOI technology with (a) tSi = 6 nm and (b) tSi = 12 nm. The buried oxide is reduced for better electrostatic control (tBOX = 20 nm).

Figure 2 . 3 .

 23 Figure 2.3. IA-VA characteristics for standard 28FDSOI Z 2 -FET with Lp = Ln = 500 nm operating as a regular forwardbiased diode with no gate polarization.

Figure 2 . 4 ,

 24 where the conduction and valence bands are constructed by biasing the front and back gates (VGf = 1 V and VGb = -1 V), which results in a blocked Z 2 -FET structure until the anode voltage increases to trigger on the device.

Figure 2 . 4 .

 24 Figure 2.4. TCAD simulations showing the band-modulation mechanism and injection barriers during 28FDSOI Z 2 -FET operation in OFF state (VA = 0 V, VGf = 1 V and VGb = -1 V). The cut is taken at y = 2 nm channel depth.

Figure 2 .

 2 Figure 2.5. (a) Two dimensional TCAD simulations (cut at y = 2 nm channel depth) showing the collapse of injection barriers when Z 2 -FET is in ON state (VGf ≥ VON) and (b) experimental IA-VA results for Z 2 -FET in 28 nm node at different front-gate bias with modulated sharp switch, low leakage current and high current ratio ION/IOFF (> 8 decades). VGb = -1 V.

Figure 2 . 6 .

 26 In fact, recovering the feedback mechanism between holes and electrons injection barriers requires VA barrier decrease. Once the gap between anode and Ln energy bands is important, the device returns into his OFF state and hence it is blocked again with low leakage current. With this feature, the standard Z 2 -FET can be proposed as a capacitor-less dynamic memory 1T-DRAM. More experimental results showing the flexibility of the hysteresis depending on the polarization of front/back-gates or device geometry are investigated in the next chapter.

Figure 2 . 6 .

 26 Figure 2.6. Experimental hysteresis in IA-VA curves of 28 nm node standard Z 2 -FET with Ln = Lp = 200 nm for different front-gate biases VGf and VGb = -1 V.

Figure 2 . 7 .

 27 Figure 2.7. Simulated IA-VA curves for standard Z 2 -FET fitting experimental results obtained in 28 nm node for various VGf and VGb = -1 V with (a) current ramping and (b) voltage ramping. Lp = Ln = 200 nm.

Figure 2 . 8 .

 28 Figure 2.8. (a) Applied voltage pattern on simulated Z 2 -FET terminals showing fast VGf and VGb and slow VA ramps. (b) Surface potential profile and (c, d) electron/hole densities obtained with TCAD simulations before forward VA ramp at y = 1 nm channel depth. VGf = 1 V, VGb = -1 V and VA = 0 V.

Figure 2 . 9 .

 29 Figure 2.9. Different mechanisms in Z 2 -FET operation.

Figure 2 .

 2 Figure 2.10-d (black curve). A detailed and comprehensive model including the generationrecombination (GR) and diffusion currents for electron and holes was derived in [20]. It is based on three current continuity equations coupled to two MOS equations that define the concentration of electrons and holes in the gated and ungated regions, respectively.

Figure 2 . 10 .

 210 Figure 2.10. Surface potential profile resuming the different mechanisms of Z 2 -FET operation (Figure 2.9) starting from A to D with VA increase and from D to A with VA back sweep.

Figure 2 .

 2 11 shows simulated IA-VA curves for different carrier lifetimes(10 -7 s to 10 -9 s). The device parameters, such as triggering voltage VON, VOFF (where the device turns OFF) and leakage current, increase with lower carrier lifetime. As mentioned before, the generationrecombination current dominates in OFF-state of Z 2 -FET, and is inversely proportional to the generation lifetime. On the other hand, the diffusion current controls the 60 mV/decade region and depends on diffusion length (controlled by carrier lifetime). Both generation and recombination lifetimes rely on max. That is why high carrier lifetime (i.e. longer diffusion length, Ln, p  eff 2 ) triggers the direct diffusion of carriers from node to node and hinder the device functionality, as shown in Figure2.11 (red curve, e-= 10 -7 s). By contrast, at e-= 10 -9 s (black curve in Figure2.11), most of carriers recombine in the channel and do not contribute to barriers collapse. In that case, low carrier lifetime reduces the diffusion lengths (n and p), hence the effective injection. As a result, VON increases towards higher anode voltage VA. These simulations show that the effective lifetime in Z 2 -FET should be less than 10 -7 s, which is actually confirmed by measurements with the Hocus-Pocus diode[22].

Figure 2 .

 2 Figure 2.11. Simulated DC current versus anode voltage for 28 nm Z 2 -FET SGP with different values of carrier lifetime varying from 10 -7 s to 10 -9 s.

Figure 2 .Figure 2 .

 22 Figure 2.12. DC experimental IA-VA curves for Z 2 -FET in 14 nm FDSOI technology at different VGf values and backgate bias VGb = -1 V showing sharp switch on (< 1 mV/decade). Lp = Ln = 200 nm.

Figure 2 .

 2 Figure 2.14. Back-gate bias influence (VGb) on the triggering voltage VON at different front-gate voltages (VGf = 1 V and 1.2 V). Z 2 -FET structure in 28 nm node.

Figure 2 . 15 .

 215 Figure 2.15. Architectures of innovative band-modulation device, Z 2 -FET with Dual Ground Planes in (a) 28 nm FDSOI technology featuring undoped ultra-thin silicon film tSi = 7 nm, thin buried oxide tBOX = 25 nm, an epitaxial layer on the whole structure tepi = 15 nm and (b) 14 nm node with thinner silicon film tSi = 6 nm, thinner BOX tBOX = 20 nm and a dual in-situ raised source-drain.

Figure 2 .Figure 2 .

 22 Figure 2.16-a shows the IA-VA curves of Z 2 -FET DGP (variant with tSi = 12 nm) at room temperature with a grounded GP-N (VGbN = 0 V) and a negatively biased GP-P (VGbP = -2 V), providing a blocked structure. The device, with increased anode voltage VA, features a sharp switch and adjustable triggering voltage VON. The variation of VON versus front-gate voltage is quasi-linear with ∆VON/∆VGf = 820 mV/V. Typical output characteristics of Z 2 -FET DGP, where the GP-N is biased simultaneously with the front-gate (VGf = VGbN) are presented in Figure 2.16-b. Here, the GP-N cooperates with the metal gate to improve the ON voltage (∆VON/∆VGf = 990 mV/V). In that case, the Ln barrier is stronger and needs more anode voltage VA to collapse. With this feature, Z 2 -FET DGP can be proposed as a viable candidate for ESD protection.

Figure 2 .

 2 Figure 2.17. IA-VGf transfer characteristics with VGbP = -1 V for various reversed sweep anode bias VA in 14 nm node Z 2 -FET DGP with VGbN = 0 V. Lp = Ln = 138 nm.

Figure 2 .

 2 Figure 2.18. IA-VA curve showing large hysteresis for Z 2 -FET DGP with Ln = Lp = 138 nm at VGf = 1.2 V, VGbN = 0 V and VGbP = -1 V.

Figure 2 .

 2 Figure 2.19. (a) Schematic cross-section for complementary P-type Z 2 -FET DGP in 14 nm FDSOI technology and (b) experimental IK-VK results at different front-gate VGf biased negatively at the same time with the P-type ground plane. VGbN = 1 V.

Figure 2 . 20 .

 220 Figure 2.20. Schematic cross-section view of back-gate modulated device Z 3 -FET in (a) 14 nm and (b) 28 nm FDSOI technologies.

. 21 .

 21 The triggering voltage is of course adjustable by varying the GPs polarization. Like standard Z 2 -FET and Z 2 -FET with two ground planes, Z 3 -FET is a practical device with easy operation. Nonetheless, one bias condition should be avoided. The diode formed by the twins GPs under the BOX should not be polarized in forward mode to avoid leakage current.

Figure 2 .Figure 2 .

 22 Figure 2.21. IA-VA curves of 14FDSOI Z 3 -FET (Lp = Ln = 200 nm) at different GP-N voltage and VGbP = -2 V showing sharp switch, low leakage current and high current ratio ION/IOFF. tSi = 12 nm.

Figure 2 .

 2 23 provides output IA-VA characteristics for long back-gates modulated device Z3 -FET with Ln = Lp = 500 nm. The GP-P is biased negatively (VGbP = -1 V) blocking the pass of electrons from the cathode into the channel while the N-type ground plane is highly biased with positive GbN voltage values up to 7 V.As mentioned before, the carrier lifetime has an important role in Z-FET devices operation.It controls the diffusion length that should be smaller than the channel length for ensuring a sharp switch. When the carrier lifetime is degraded and lowers the diffusion rate, the carriers recombine in the channel before reaching the other node, which normally results in a steep switch. Although, the Ln and Lp regions of Z 3 -FET are long (1 µm, Figure2.23), there is no sharp switch. In this case, the region dominated by the diffusion mechanism (from B to C in Figure2.9) expands as a result of lifetime degradation (see also Figure2.11) inducing a non-vertical switch (SS = 60 mV/decade).Since the barriers are collapsing slowly, the high current ION is actually reached before the triggering voltage VON. Otherwise, the device exhibits a high-voltage operation without breaking down the buried diode under the BOX. This property makes the Z 3 -FET a competitive candidate for HV-ESD protection or a triggering element for Bulk ESD protection devices.

Figure 2 . 23 .

 223 Figure 2.23. Current versus anode voltage measured for GP-N reaching high voltage in long 14FDSOI Z 3 -FET with tSi = 12 nm (Lp = Ln = 500 nm) without device breakdown. VGbP = -1 V.

  1[1, 2]. The device is initially in OFF state at low VA. Increasing the anode bias VA lowers linearly the gate barrier (~ (VGf -VA)) and enables the injection of few holes from the P + anode into the channel, which flow to the N + cathode inducing a potential change at cathode-channel junction. As VA increases further towards the triggering voltage (VON), the Gb barrier is reduced sufficiently to permit electrons injection into the body and initiate a positive feedback mechanism between the barriers that sharply turns ON the device with a current ION/IOFF ratio of 10 8 for ∆VA < 50 mV (Figure3.1-b). This sharp switch is not present in Z 2 -FET with thin silicon film (tSi = 6 nm, Figure3.1-a). The silicon film thinning increases the recombination rate of carriers, which is dominated by the interfaces, and decreases the effective lifetime so that the carriers cannot make the complete path from node to node. The high recombination in the body leads to non-vertical switch (SS = 60 mV/dec, Figure3.1-a).

Figure 3 . 1 .

 31 Figure 3.1. Experimental DC IA-VA characteristics for different front-gate VGf bias of Z 2 -FETs (a, c) with thin tSi = 6 nm and (b) thick tSi = 12 nm. Ln = Lp = 138 nm. (the mismatch of leakage current is due to equipment resolution).

Figure 3 . 2 .

 32 Figure 3.2. Experimental DC IA-VA curves of (a) thick and (b) thin Z 2 -FET DGP for various VGf bias and VGbN = 0 V, (c) thick and (b) thin Z 3 -FET modulated by various GbN and GbP = -1 V. Ln = Lp = 138 nm.

  3-a) up to -1 V (red circle symbols, Figure3.3-a) makes the Lp barrier stronger, thus increases VON. The holes barrier in the gated section starts to be eroded for more negative VGb < 0 V, reducing the turn ON voltage due to the inner coupling between the front and the back-gate (VGb = -2 V with blue diamond symbols in Figure3.3-a). The ground plane extends underneath the gated region, where it tends to induce a positive charge that opposes the electron charge assigned by the front-gate VGf. This explains the non-monotonous shift of the characteristics reproduced in thin and thick Z 2 -FET devices (Figure3.3-a, c). However, increasing the front-gate voltage from 1.5 V up to 3 V strengthens enough the barrier under the gate and the coupling effect is minimized (Figure3.3-b). The rate of triggering voltage VON change with respect to the back-gate bias is ∆VON/∆VGb = 120 mV/V for both thin and thick silicon films[1, 2].

Figure 3 . 3 .

 33 Figure 3.3. Impact of back-plane bias on the DC IA-VA curves at (a) VGf = 1.5 V, tSi = 12 nm (b) VGf = 3 V, tSi = 12 nm and (c) VGf = 1.5 V, tSi = 6 nm. Ln = Lp = 138 nm.

Figure 3 . 4 .

 34 Figure 3.4. Impact of GP-P bias on DC IA-VA characteristics for (a) Z 2 -FET DGP at VGf = 1 V, VGbN = 0 V and (b) Z 3 -FET at VGbN = 1 V.

Figure 3 . 5 .

 35 Figure 3.5. Variation of triggering voltage VON with back-gate VGb bias for (a) thick and (b) thin Z 2 -FETs at different front-gate VGf polarization. Lp = Ln = 138 nm.

Figure 3 . 6 .

 36 Figure 3.6. Variation of triggering voltage VON for (a) Z 2 -FET DGP with VGf and N/P back-planes and (b) Z 3 -FET with back-gates (GbN and GbP).

Figure 3 .

 3 Figure 3.7 compares the triggering voltage of all Z-FET family devices. Z 3 -FET features higher VON than standard Z 2 -FET, while the important turn-on voltage belongs to Z 2 -FET with dual ground planes. The fact of synchronizing the GP-N with the front-gate reinforces strongly the gate barrier and increases drastically VON (blue diamond symbols). With this feature, Z 2 -FET DGP could be a viable candidate for ESD protection for 1.8V applications while Z 3 -FET can be used for High-Voltage (HV) ESD protection, as we will see in the next subsection [6].

Figure 3 . 7 .

 37 Figure 3.7. Comparison of turn-on voltage VON between Z-FET family devices with tSi = 12 nm at negative GP-P bias (VGbP = VGb = -1 V). Lp = Ln = 200 nm.

Figure 3 . 8 .

 38 In short Z3 -FET, VON increases with VGbN until 5 V and starts to decrease for higher VGbN (Figure3.8-a). This means that the holes junction barrier shrinks for VGbN > 5 V, which is counter-intuitive. This effect can be explained by the depletion region enlargement of the reverse-biased diode formed by the two ground planes below the BOX. The width Wdep of the junction depletion region is calculated for different doping concentrations in Figure3.8-c. In our case, where the GPs are doped NA (GP-P) = ND (GP-N) = 10 18 cm -3 , the depletion zone reaches 110 nm at VGP = VGbN -VGbP = 6 V. Thus, the electrostatic control of the channel by the GPs decreases, leading to narrower barriers and a VON reduction for VGP > 5 V, as noticed in Figure3.8-a. The channel control is retrieved by increasing the device length (Ln + Lp >> Wdep). The long Z3 -FET (Ln = Lp = 500 nm, Figure3.8-b) can sustain high anode voltage up to 8 V without device breakdown and with a negligible leakage current of the reversed biased diode. A second solution can consist in using higher doping in GPs: for NA = ND = 10 19 cm -3 , the space charge region of the diode falls down below 40 nm even at high back-gate bias (Figure3.8-c). However, over-doping the ground planes (by ion implantation) may affect the body doping by leaving residual charges in the channel and hence the device characteristics could change.

Figure 3 . 8 .

 38 Figure 3.8. Current versus anode voltage measured for GP-N bias reaching high voltage in (a) short Z 3 -FET with Ln = Lp = 200 nm and (b) long Z 3 -FET with Ln = Lp = 500 nm at VGbP = -1 V. (c) Evolution of lateral depletion width between the GPs versus reverse bias VGP = VGbN -VGbP for different doping concentrations. tSi = 12 nm.

Figure 3 . 9 .

 39 Figure 3.9. IA-VA curves showing sharp switching and gate controlled hysteresis for (a) various VGf at VGb = -1 V, Ln = Lp = 200 nm and (b) different back-gate bias at VGf = 1.2 V, Ln = Lp = 200 nm. Thick Z 2 -FETs, tSi = 12 nm.

Figure 3 .Figure 3 .Figure 3 .

 333 Figure 3.10), the barriers need higher VGf (for Z 2 -FET DGP, Figure 3.10-a) and VGbN (for Z 3 -FET, Figure 3.10-b) to retrieve their height and return the device into its OFF state. The forward/reverseVGf scan results in a hysteresis that can be enlarged with anode bias VA.

Figure 3 .

 3 Figure 3.10. IA-VGf/VGbN transfer characteristics for various anode bias VA in (a) Z 2 -FET DGP at VGbN = 0 V, VGbP = -2 V and (b) Z 3 -FET at VGbP = -0.5 V showing sharp switching and hysteresis.

Figure 3 . 11 .

 311 Figure 3.11. Current versus anode voltage measured for thin Z 2 -FETs (a) at VGb = -2 V, Ln= Lp = 90 nm and (b) VGb = 0 V, Ln = Lp = 200 nm.

Figure 3 . 12 .

 312 Figure 3.12. Current versus front-gate voltage measured at VA = 1 V (where the leakage current is defined) for (a) different Lp lengths, Ln = 100 nm and (b) different Ln lengths, Lp = 200 nm. tSi = 12 nm.

Figure 3 . 13 .

 313 Figure 3.13. Current versus front-gate voltage measured at VA = 1 V for different Lp lengths (a) Z 2 -FET DGP with Ln = 90 nm at VGbN = 0 V and (b) Z 3 -FET with Ln = 138 nm. VGbP = -2 V.

Figure 3 . 14 .

 314 Figure 3.14. Variation of triggering voltage VON with front-gate bias for standard Z 2 -FET at (a) tSi = 12 nm, VGb = 0 V and (b) VGb = -2 V; (c) tSi = 6 nm at VGb = 0 V and -2 V. (d) Evolution of VON with Z 2 -FET DGP and Z 3 -FET devices length at VGbP = -1 V and VGf = VGbN = 2 V.

Figure 3 .

 3 Figure 3.15-a [6]. Here, the band-modulation mechanism is attenuated. The N-doped Ln region forms a natural strong barrier against holes injection, avoiding the positive GP-N bias. Hence, the device is blocked even without back-gate bias, as shown in Figure 3.15-b. In short devices, the GP-N barrier is narrow and cannot prevent completely the injection of holes toward the cathode. Since at VGbP = 0 V the GP-P barrier is too weak, the leakage current is high. To avoid leakage, the electrons injection barrier should be strengthened by either increasing the length of the undoped part (Figure 3.15-b) or by negatively biasing the GP-P (Figure 3.15-d), which is efficient in both short and long devices. The triggering voltage increases not only when the barriers are broader (long device in Figure 3.15-b) or higher (VGbP < 0 V in Figure 3.15-d), but also by increasing the GP-N bias (despite the high doping), as shown in Figure 3.15-c.

Figure 3 .

 3 Figure 3.15. (a) Schematic of doped Z 3 -FET variant architecture in 14 nm FDSOI technology. (b) Current versus drain voltage measured for different geometries at VGbN = VGbP = 0 V and for short Z 3 -FET (c) at various GP-N bias with VGbP = 0 V and (d) various GP-P bias with VGbN = 0 V.

Figure 3 .

 3 Figure 3.16-a shows the experimental IA-VA curves of Z 3 -FET with Silicon-Germanium (SiGe) body at various GP-N bias and constant VGbP = -2 V. The main characteristics, such as the modulated triggering voltage and the sharp switch, are maintained. Compared to all-Si Z 3 -FET (Figure 3.16-d), the barriers in Z 3 -FET with SiGe body are weaker, hence the carriers can be injected more easily in the channel, increasing lightly the leakage current as seen in Figure 3.16-c.Introducing silicon strained technology and combining silicon (Si) with germanium (Ge) improves the holes effective mobility[10][11][12] and increases the carrier diffusion length. In that case, the injected carriers from the anode/cathode cross the channel and contribute faster in barriers collapse, leading to a slight triggering voltage VON reduction (Figure3.16-b), which is attractive for low-power applications.

Figure 3 .

 3 Figure 3.16. (a) Experimental IA-VA output characteristics for different VGbN bias in Z 3 -FET with SiGe body. Comparison of (b) triggering voltage and (c) leakage current extracted at Vdd = 1 V between Z 3 -FETs with Si and SiGe. (d) IA-VA curves for Si (blue curves) and SiGe (red curves) Z 3 -FETs at VGbN = 0 V and 2 V. VGbP = -2 V.

  -a. The linear dependence of VON on VGf and the slope ∆VON/∆VGf for different device lengths is conserved from room temperature (blue opened symbols) to 125°C (red closed symbols), as shown in Figure 3.17-b.

Figure 3 .

 3 Figure 3.17. (a) Experimental IA-VA curves at T = 125°C (closed red symbols) and room temperature (open blue symbols) for various VGf and VGb = -1 V. (b) VON versus front-gate bias and VGb = -1 V at T = 25°C and 125°C for different Z 2 -FET device lenghts. tSi = 12 nm.

Figure 3 .

 3 Figure 3.18. IA-VA curves at T = 125 °C (red symbols) and room temperature (blue symbols) with various VGbN for (a) Z 2 -FET DGP at VGf = 2 V, VGbP = -1 V and (c) Z 3 -FET at VGbP = -2 V. Variation of triggering voltage shift VON/∆T in (b) Z 2 -FET DGP and (d) Z 3 -FET versus device length.

Figure 3 .

 3 Figure 3.19. Experimental DC IA-VA characteristics for various VGf and VGb = -20 V at room temperature (closed red symbols) and T = 86K (open blue symbols). Thick Z 2 -FET variant from CEA-Leti with Lp = 500 nm and Ln = 200 nm.

Figure 3 .

 3 . Compared to 28 nm FDSOI technology, the BOX in 14 nm node is thinner, leading to an enhanced channel control via the back-gate. However, it affects more the gated barrier by

Figure 3 . 20 .

 320 Figure 3.20. Comparison of output IA-VA curves in 14 nm FDSOI Z 2 -FETs with thick (closed black circle symbols) and thin (open blue circle symbols) body and 28FDSOI Z 2 -FET (open red square symbols) for (a) VGf = 0 V, VGb = -2 V and (b) VGf = 2 V, VGb = -2 V. Lp = Ln = 200 nm.

Figure 3 . 21 .

 321 Figure 3.21. Comparison of experimental DC IA-VA curves in 14 nm FDSOI Z 3 -FETs with thick body (closed blue circle symbols) and 28FDSOI Z 3 -FET (open red circle symbols) at various GbN bias and VGbP = -1 V.

Figure 3 .

 3 Figure 3.22. TLP characterization results for thick (black curves) and thin (blue curves) Z 2 -FET exposed to 5 ns (open symbols) and 100 ns (closed symbols) pulse width, respectively, with native rise time ( 300 ps). VGf = 2 V and VGb = -2 V.

Figure 3 .

 3 Figure 3.23 shows the evolution of failure current It2 and triggering voltage Vt1 versus Z 2 -FET device length. The capability of sustaining high current in both (a) thick and (b) thin structures decreases with device length increase. Inversely, in long devices where the barriers are broader, Vt1 increases. All thin Z 2 -FETs (tSi = 6 nm, Figure 3.23-b) and long devices with thick silicon film (> 400 nm in Figure 3.23-a) feature a good latch-up immunity for 1.8 V applications. The turn-onvoltage of these devices surpasses the holding voltage criterion (VH = 2.0 V) imposed by JEDEC78[21]. On the other hand, despite the robustness and efficiency to evacuate high current (> 5 mA/µm and > 7.5 mA/µm for 100 ns and 5 ns pulse widths respectively in Figure3.23-a), the early trigger of short devices (Vt1 ≤ Vdd + 10 % for Ln + Lp < 400 nm) with tSi = 12 nm restrict their usage in 1.8 V ESD applications. For example, Z 2 -FET with Ln = Lp = 138 nm triggers at anode voltage VA = 1.7 V, which is lower than the supply voltage Vddmax = 2.0 V. However, short devices with both silicon film thicknesses fit perfectly the 1.0 V application requirements as they trigger in the dedicated ESD tight window (1.0 V < Vt1 (ESD) < 2.5 V).

Figure 3 . 23 .

 323 Figure 3.23. Variation of triggering voltage Vt1 (blue diamond symbols, right-hand y axis) and failure current It2 (left y axis) for 5 ns (circle symbols) and 100 ns (square symbols) pulses versus device length for (a) thick and (b) thin Z 2 -FETs. VGf = VGb = -2 V.

3 -

 3 Figure 3.24-b). It is confirmed that the maximum current and triggering voltage values depend strongly on device length. Shorter Z 3 -FETs show easier triggering Vt1, higher current capability and lower RON resistance [6].

Figure 3 .

 3 Figure 3.24. (a) 5 ns and (b) 100 ns TLP measurements of various undoped Z 3 -FET devices (length from 276 nm up to 1 µm) with thick silicon film (tSi = 12 nm) at VGbN = 2 V and VGbP = -2 V.

Figure 3 .

 3 Figure 3.25. Non-destructive TLP measurements for 100 ns pulse width in short (solid lines) and long (dotted lines) Z 3 -FETs for (a) VGbP = 0 V and various GP-N bias and (b) VGbN = 2 V and various GP-P bias.

Figure 3 .

 3 26 shows the S-shaped negative resistance characteristic for two different lengths of partially N-doped Z 3 -FET devices with no back-gate bias facing 5 ns (Figure 3.26-a) and 100 ns pulse widths (Figure 3.26-b), respectively. Doping the Ln part of short Z 3 -FET channel reinforces the barrier in this region and thus increases the triggering voltage (dashed lines in Figure 3.26-a, b).However, it does not reach the required latch-up VH target of 1.8 V application (VH = 1.5 V < 2 V), thus restricting its usage for GO2 FET protection against electrostatic discharges. This difficulty can be solved by increasing the device length. Yet, the holding voltage of Z 3 -FET with Ln + Lp = 550 nm does not fit LU requirements (dotted lines in Figure3.26-a, b).

Figure 3 .

 3 Figure 3.26. TLP IA-VA characteristics for N-doped long (dotted lines) and short (dashed lines) Z 3 -FETs against (a) 5 ns and (b) 100 ns pulse widths at VGbN = VGbP = 0 V. tSi = 12 nm.

  27-c), the doped Z 2 -FET was replaced by a Back Bias Controlled Thyristor (BBC-T with doped Ln part = 0.2 µm and undoped Lint region = 0.3 µm[15, 18, 23]), which is similar to doped Z 3 -FET, but with just one ground plane under the structure. To avoid the influence of positive Nwell back biasing on Z-FET devices, the NW/PW junction was shifted far from the channel region (Figure3.27-b, d).

Figure 3 .

 3 Figure 3.27. Cross-sections of (a) doped Z 2 -FET and (c) BBC-T Enhanced Stacked SCR (ZeST and BeST) with central NW/PW junction and (b, d) shifted NW/PW junction. Channel width W = 100 µm.

Figure 3 .

 3 Figure 3.28. Experimental IA-VA DC characteristics at room temperature on (a) ZeST and (b) BeST devices.

  Figure 3.29 confirms the Z-FET devices capability of turning ON the bulk-SCR at earlier anode voltage. First, the Z 2 -FET and BBC-T elements are activated and the current flows in the stacked structure to fire then the hybrid-bulk device at  200 mA (far from the forbidden Latch-Up criterion, 100 mA). Grounding the front-gate of Z 2 -FET permits fitting the 1.8 V ESD design window requirements (Figure 3.29-a), but with an external triggering circuit. This makes it less interesting than BBC-T (Figure 3.29-b), which does not need any external bias. It was also noticed that the incorporation of thin film devices with bulk-SCR increases the failure current of the overall ESD protection by 25%, as seen in Figure 3.29-a, b.

Figure 3 .

 3 Figure 3.29. IA-VA TLP measurements for 100 ns pulse width of (a) ZeST and (b) BeST structures vs. standard hybridbulk SCR.

Figure 3 . 30 .

 330 Figure 3.30. Schematic cross-section view of Z 2 -FET with dissociated silicon channel.

Figure 3 .

 3 Figure 3.31. (a) Surface potential versus x for Z 2 -FET in weak accumulation (Lp = 200 nm) and weak inversion (Ln = 200 nm) and (b) simulated carrier density (holes in blue and electrons in red) along the channel at y = 0 for VGf = 0.5 V, VGb = -0.5 V and VA = 0 V.

Figure 3 . 32 .

 332 Figure 3.32. Evolution of (a) surface potential f(x) in Ln part of the channel and (b) electrons density with front-gate bias VGf at VGb = -0.5 V. (c) Surface potential b(x) in Lp channel part and (d) holes density with back-gate bias VGb at VGf = 0.5 V. Simulated 28 nm FD Z 2 -FET. TCAD simulations.

Figure 3 . 33 .

 333 Figure 3.33. Surface potential versus x for Z 2 -FET with Ln = Lp = 200 nm along the channel at y = 0 for VGf = 0.7 V, 1.3 V and 1.5 V, VA = 0 V, (a) VGb = -1 V and (b) VGb = -2 V.

Figure 3 . 34 .

 334 Figure 3.34. Surface potential versus x for (a) short Z 2 -FET with Ln = Lp = 100 nm at VGf = 0.5 V, 1 V and (b) long Z 2 -FET with Ln = Lp = 400 nm at various front-gate VGf biases. VA = 0 V, VGb = -1 V.

Figure 3 . 35 .

 335 Figure 3.35. Comparison of surface potential distribution model along the whole silicon body between Z 2 -FET SGP at VGf = 0.5 V (dashed blue curve), Z 2 -FET DGP at VGf = 0.5 V, VGbN = 0 V (solid red curve) and Z 3 -FET at VGbN = 0.5 V (dotted black curve). Lp = Ln = 200 nm, VGb = VGbP = -0.5 V and VA = 0 V.

  3 V applications. Stacked architectures of band-modulation devices with hybrid-bulk SCR were reported, featuring high capability of sustaining current especially against HBM ESD event. Finally, a compact analytical model of potential distribution over the whole channel of Z 2 -FET was developed. It was successfully compared to TCAD simulations. The model was extended to other members of Z-FET family. The model shows a good accuracy and is valid for short and long devices in weak and strong inversion/accumulation regimes.

  voltage VON displacement caused by the presence (or not) of mobile charges (electrons) under the front-gate points to the same effect. The front-gate controlled hysteresis (Figure 4.1-b) achieved within low anode and front-gate voltage range paves the way for designing low-power 1T-DRAMs with Z 2 -FET architecture (Figure 4.1-a).

Figure 4 . 1 .

 41 Figure 4.1. (a) Cross-section view of Z 2 -FET in 28 nm FDSOI technology. (b) IA-VA curve showing gate-controlled hysteresis in 28 nm Z 2 -FET with Ln = Lp = 200 nm at various VGf and VGb = -1 V.

Figure 4 . 2 .

 42 Figure 4.2. Experimental bias pattern applied to front-gate (black line) and anode (red line) at VGf = 1.2 V, VA = 1.05 V and VGb = -1 V with TP = 320 ns. Z 2 -FET in 28 nm FDSOI node with Ln = Lp = 200 nm.

Figure 4 . 3 . 3 ,

 433 Figure 4.3. Bias pattern and corresponding current in simulated Z 2 -FET memory at VGf = 1.2 V, VGb = -1 V and VA = 1.05 V. Lp = Ln = 200 nm.

Figure 4 . 4 .

 44 Figure 4.4. (a) Simulated surface potential profile versus time, (b) electrons and (c) holes densities for Z 2 -FET operating as 1T-DRAM. (Cut was taken at y = 1 nm under the gate).

Figure 4 . 5 .

 45 Figure 4.5. Total current density for simulated Z 2 -FET (Lp = Ln = 200 nm) during (a) writing "0", (b) reading "0", (c) writing "1" and (d) reading "1". VGf = 1.2 V, VGb = -1 V and VA = 1.05 V.

  4 V in blue) limits the flow of carriers in the channel, implying a negligible current, and significantly reduces the power consumption during the writing operation of the single-transistor DRAM. The action does not affect the read current that still offers a remarkable sense margin (I1-I0 = 25 µA/µm, dotted blue curve). This feature is unrivalled by any competing DRAM, ReRAM, STRAM or PCRAM memory technology. In contrast, I1 disappears for lower VA(W1) < 0.4 V because not enough electrons can be secured at the gate (dotted red curve in Figure 4.6, VA(W1) = 0.1 V).

Figure 4 . 6 .

 46 Figure 4.6. Memory bias scheme and its response in simulated Z 2 -FET to limit the power consumption when programming "1" at VGf = 1.2 V, VGb = -1 V and VA(Reading) = 1.05 V.

Figure 4 . 7 .

 47 Figure 4.7. Simulated electrons density and surface potential for Z 2 -FET DRAM extracted for the bias scheme in Figure 4.6 for logic "1" (a, b) holding "HW1" and (c, d) reading "R1".

Figure 4 . 8 .

 48 Figure 4.8. Simulated Z 2 -FET (Ln = Lp = 200 nm) dynamic RAM features very fast access time. TP = 1 ns

Figure 4 . 9 .

 49 Figure 4.9. (a) Waveform of anode and front-gate pulses applied to Z 2 -FET. Evolution of (b) electrons density and (c) surface potential during hold "0" operation for 10 ms. VA = 0 V, VGf = 1.1 V and VGb = -1 V.

Figure 4 .

 4 Figure 4.10. (a) Global and (b) zoom view of repetitive anode pulses applied to Z 2 -FET after programming "0" state for 100 µs. (c) Electrons concentration and (d) surface potential evolution after each VA pulse. VA = 1.05 V, VGf = 1.1 V and VGb = -1 V.

Figure 4 . 11 .

 411 Figure 4.11. Bias pattern applied to Z 2 -FET DRAM for logic "0" retention evaluation. Change of (a) carrier concentration and (b) surface potential during 1 ms of "0" hold. VA = 1.05 V, VGf = 1.1 V and VGb = -1 V.

Figure 4 .

 4 12 shows that the front-gate, now controlling better the channel, can be decreased down to 1.05 V without affecting the memory operation. The current sense margin obtained at VA = 1.05 V is still remarkable (I1 = 26 µA/µm).

Figure 4 . 12 .

 412 Figure 4.12. Bias scheme applied to ultra-thin oxide GO1 Z 2 -FET and its current response at VGf = 1.05 V, VA = 1.05 V and VGb = -1 V. Ln = Lp = 200 nm.

Figure 4 . 13 .

 413 Figure 4.13. Instruments assembly schematic used for measuring band-modulation devices in transient mode as capacitor-less DRAMs.

Figure 4 . 14 .

 414 To program the "1" and "0" states, electrons are stored (or not) under the positively biased front-gate. Memory readout consists in discharging CGf with anode pulse. Grounding the front-gate while maintaining a low anode voltage (VGf from 1.25 V to 0 V and VA = 0 V) is used for "0" state programming. Since the electrons were eliminated from the gated region ("0" state), the anode reading pulse cannot collapse the enforced Ln barrier. Hence, a nearly zero discharge current is obtained (I0 ~ 1 nA/µm, Figure4.14). Forcing the device to act as a forward biased PIN diode (VGf = 0 V and VA = 1.1 V, W1 in Figure 4.14) permits the flow of carriers in the channel inducing a high current. At this moment, the front-gate collects and stores free electrons forming relatively weak potential profile in this region (see also Figure 4.4-a). The anode reading pulse (VA = 1.1 V) is able now to collapse the barriers featuring high I1 current

Figure 4 . 14 .

 414 Figure 4.14. Bias pattern used for Z 2 -FET memory operation and corresponding experimental anode current at VGf = 1.25 V, VGb = -1 V and VA = 1.1 V with programming pulse TP = 120 µs. Lp = Ln = 200 nm.

Figure 4 .

 4 Figure 4.15-b). The high anode pulse crashes the gated barrier (not strong enough) and turns on the device (no more memory effect). The solution is to increase VGf from 1.25 V up to 1.4 V, which reinforces the potential in this region avoiding barriers collapse.

Figure 4 .

 4 Figure 4.15. (a) Anode current IA obtained at VGf = 1.25 V and VA = 1.1 V with short programming pulse width Tp = 320 ns. (b) Current margin I1/I0 variation with VA for VGf = 1.25 V and 1.4 V. VGb = -1 V.

Figure 4 .

 4 16 shows the device response on anode bias with two different rise time (RT = 30 ms and 3 µs in Figure4.16-a, b respectively). For VA slightly lower than VON(DC), the long anode pulse cannot unblock the device (Figure4.16-a). However, decreasing the anode pulse rise time stimulates the capacitance discharging mechanism, which this time turns on the device, implying a higher IA current (IA = 18 µA/µm in Figure4.16-b).

Figure 4 . 16 .

 416 Figure 4.16. Impact of anode pulse rise time on read IA current at VGf = 1.2 V, VGb = -1 V and VA = 1.05 V. (a) Rise time RT = 30 ms and (b) RT = 3 µs.

  -a, the writing anode voltage VA(W1) is reduced from 1.05 V (blue dotted line) down to 0.5 V (red solid line). The program "1" current becomes almost negligible and significantly reduces the power consumption during the writing operation of the single-transistor DRAM. Despite using a much decreased VA(W1), sufficient electrons are still stored under the gate lowering the Ln barrier. The read anode voltage VA(Reading) = 1.05 V collapses the weak holes injection barrier offering a similar high current margin (I1-I0 = 26 µA/µm). For lower VA(W1) ≤ 0.35 V, I1

Figure 4 . 17 .

 417 Figure 4.17. Memory bias scheme and its response to limit the power consumption when programming "1" at VGf = 1.25 V, VGb = -1 V and VA(Reading) = 1.05 V. (a) VA(W1) = 0.5 V and (b) VA(W1) = 0.35 V. (c) Evolution of reading and writing current difference (IW1-IR1) with programming anode voltage VA(W1) at VGf = 1.3 V, VGb = -1 V for two different reading voltages VA(R1) = 1.05 V (red square symbols) and VA(R1) = 1.2 V (blue circle symbols).

Figure 4 . 18 )

 418 and continuous "0" reading(Figure 4.20). At VGf = 1.2 V and VA = 1.05 V (Figure4.18-a), the "0" state degrades to stabilize after 1.5 ms (I0 = 10 µA/µm) but still lower than I1 = 26 µA/µm (Figure4.17-a). Normally, frequent anode pulses improve the retention time by eliminating accumulated electrons under the gate. However, the reinstalled electrons under the front-gate, during hold stage, lower the energy bands in this region allowing the passage of holes into the body. Hence, VA pulses are able now to collapse the Ln barrier implying a "0" state degradation. Higher VGf raises up the potential in Ln region and stops holes injection from anode resulting in enhanced "0" retention time as illustrated in Figure4.18-b.

Figure 4 .

 4 Figure 4.18. Logic "0" retention time for 4 ms in hold-read stage at VA = 1.05 V and VGb = -1 V. (a) VGf = 1.2 V and (b) VGf = 1.25 V.

Figure 4 . 19 .

 419 Figure 4.19. Evolution of logic hold-read "0" retention time and I0 current with front-gate bias at VA = 1 V and VGb = -1 V.

Figure 4 .

 4 20-b). The device benefits from long anode pulse to eliminate the accumulated electrons under the front-gate featuring high retention time without any degradation (tre = 500 ms, Figure4.20-a).

Figure 4 .

 4 Figure 4.20. (a) Logic "0" retention time for continuous reading for 550 ms at VA = 1.05 V, VGb = -1 V and VGf = 1.25 V. (b) Anode and front-gate pulses schemes applied at the beginning of the retention bias pattern.

Figure 4 .

 4 21-b). For higher VA, the current ratio increases in both cases but collapses earlier at T = 85 °C (Figure 4.21-b).

Figure 4 .

 4 Figure 4.21. (a) High temperature experimental results for Z 2 -FET DRAM operating at VGf = 1.2 V, VGb = -1 V and VA = 1.05 V. (b) Comparison of current ratio I1/I0 at room temperature and T = 85 °C in terms of anode voltage VA at VGf = 1.25 V and VGb = -1 V. Ln = Lp = 200 nm.

Figure 4 .

 4 Figure 4.22 shows the "0" retention time at high temperature. As discussed before, the gated barrier at VGf = 1.2 V is relatively weak and cannot withstand anode voltage bias VA = 1.05 V for long time implying a high I0 current (I0 = 43 µA/µm in Figure 4.22-a, b). The retention time is improved by increasing VGf (Figure 4.22-a, b). The gated barrier retrieves its height and I0 is almost suppressed.

Figure 4 .

 4 Figure 4.22. Experimental "0" state retention time at VA = 1.05 V, VGb = -1 V and various VGf for (a) 4 ms in holdread mode and (b) 550 ms in continuous read mode. T = 85 °C.

Figure 4 . 23 .

 423 Figure 4.23. Bias pattern used for Z 2 -FET memory operation in 14 nm node with Lp = Ln = 200 nm and corresponding anode current at VGf = 1.1 V, VGb = 0 V, (a) VA = 1.05 V and (b) VA = 1.3 V. Short programming pulse width, TP = 250 ns.

Figure 4 .Figure 4 .Figure 4 .

 444 Figure 4.24-a shows that, at VGb = 0 V, the memory effect disappears in both short and long devices (138 nm < 200 nm < 350 nm) with comparable I1 and I0 currents at all anode voltages (Blue circle and black square symbols are superimposed, Figure 4.24-a). After applying a negative back-gate bias, devices retrieve their operation as 1T-DRAM cells at certain VA values (VGb = -1 V, Figure 4.24-b). Actually, the two devices do not benefit from back-gate bias in the same manner. While VGb < 0 V reinforces the weak Lp barrier in short Z 2 -FETs, it reduces by coupling effect the Ln barrier in long devices and VA can now collapse it (for example VA = 1.25 V in long Z 2 -FET, Figure 4.24-b). It is noticed that the device downscaling improves the current sense margin (note that the saturation of I0 and I1 in short devices is due to the current compliance imposed by used equipment).

Figure 4 . 24 .

 424 Figure 4.24. Evolution of I1 (left y axis, black square symbols) and I0 (right handed y axis, blue circle symbols) with anode voltage VA bias for two different Z 2 -FET device lengths at VGf = 1.1 V (a) VGb = 0 V and (b) VGb = -1 V.

Figure 4 .

 4 25 presents promising results of short Z 2 -FET DGP (Ln = 90 nm, Lp = 150 nm) as single-transistor DRAM where the Lp barrier is strong with no need of negative back-gate bias.The current sense margin is remarkable at nearly Vdd bias (I1 = 23 µA/µm for VA = 1.15 V).

Figure 4 . 25 .

 425 Figure 4.25. Bias pattern applied to Z 2 -FET DGP with Ln = 90 nm, Lp = 150 nm and corresponding anode current at VGf = 1 V, VGbN = VGbP = 0 V and VA = 1.15 V. Short programming pulse width, TP = 250 ns.

Figure 4 . 26 .

 426 Figure 4.26. Memory bias scheme and its response to limit the power consumption for Z 2 -FET DGP when programming "1" by applying reduced anode writing voltage VA(W1) at VGf = 1 V, VGbN = VGbP = 0 V and VA(Reading) = 1.15 V.

Figure 4 . 27 .

 427 Figure 4.27. Impact of GP-N bias on short Z 2 -FET DGP operating as 1T-DRAM at VGf = 0.95 V, VA = 1.15 V and VGbP = 0 V. Lp = 150 nm and Ln = 90 nm.

Figure 4 . 28 .

 428 Figure 4.28. Memory bias scheme applied to Z 3 -FET with SiGe body and its response at VGbN = 0.8 V, VGbP = 0 V and VA = 1.05 V. Lp = Ln = 200 nm.

Figure 4 . 29 .

 429 Figure 4.29. Comparison of I1 and I0 currents between Si and SiGe Z 3 -FETs for various GP-N bias at VGbP = 0 V, (a, c) VA = 1.05 V and (b, d) VA = 1.3 V. The saturation of I1 and I0 currents at VA = 1.3 V is due to equipment current compliance.

Figure 4 . 30 .

 430 Figure 4.30. Bias pattern applied to Z 3 -FET at VGbN = 0.8 V, VGbP = -1 V and VA = 1.1 V with (a) Ln = Lp = 150 nm and (b) Ln = Lp = 138 nm.

Figure 4 .

 4 31. The cathode (N + ) is connected to the Select Line (SL) with first level of metal (M1) while a second metal level (M2) links the anode (P + ) to the Bit Line (BL). The front-gate polysilicon plays the role of the Word Line (WL).

Figure 4 . 31 .

 431 Figure 4.31. Schematic representation of 28 nm FDSOI technology Z 2 -FET as capacitor-less DRAM in a matrix context.

  2.4.1.a).

Figure 4 .

 4 Figure 4.32. (a) Layout and (b) schematic views for 2x2 Z 2 -FET memory matrix. The active silicon region is in green; the front-gate (Ln) in red; the RPO layer in orange defines the ungated region (Lp); the cyan blue anode is connected to BL with M2 (dark blue) while the cathode (no color) and N-type MOS selector are linked with M1 (light blue).

( 4 . 36 )

 436 In order to be competitive, the Z 2 -FET overall length should be below 200 nm and all Lsource, Lpoly-RPO and Lpoly-contact spaces must not exceed 40 nm. We believe we can achieve this goal with the novel Z 2 -FET with additional GP-N. As the front-gate is reinforced by GP-N, it tolerates the aggressive downscaling. The short experimentally tested Z 2 -FET DGP (Lp = 150 nm, Ln = 90 nm) features, with minimum Lx-x distances, a remarkable integration density Dmm² = 20.5 Mb/mm 2 .

Figure 4 . 33 .

 433 Figure 4.33. Layout view of 2x2 Z 2 -FET memory matrix with distributed N-type MOS selector. The MOS transistor and Z 2 -FET share the source (N + ).

Figure 4 . 34 .

 434 It starts with setting the front-gate into an initial value (VGf = 0.8 V in this case) and switch it into 0 V during 200 ns within a 2 µs VA pulse width (VA = 1.15 V). The rise time of signals stands for 60 ns. At VA = 1.15 V, switching the front-gate bias from 0.8 V down to 0 V turns on the device inducing high ION current (ION = 34 µA/µm). Setting back VGf to its high value cuts off the current and Z 2 -FET DGP returns into its off state with negligible IOFF current (IOFF ~ 10 nA/µm).

Figure 4 . 34 .

 434 Figure 4.34. Bias scheme applied to Z 2 -FET DGP operating as a logic switch and corresponding current at VGf = 0.8 V, VA = 1.15 V and zero ground plane bias VGbN = VGbP = 0 V. Lp = Ln = 200 nm.

4. 3 . 1 . 1 .Figure 4 .

 3114 Figure 4.35 shows the influence of VGf and VA variation on current margin (ION/IOFF) of logic switch Z 2 -FET DGP. The device features high ION current at VA = 1.1 V and VGf = 0.3 V (ION = 22 µA/µm, Figure 4.35-a). But, the barriers are weak at low front-gate bias and behave ineffective due to the massive flow of carriers. As a result, the IOFF current is relatively high even if the gate is set back into its high value. Increasing VGf reinforces the Ln barrier and thus reduces the parasitic IOFF current to be eliminated at VGf = 0.6 V without affecting the device on state (gray curve, Figure 4.35-a). The current margin also depends strongly on anode voltage bias. The mechanism of device turn off starts to appear at low VA = 0.9 V with a moderate current ratio (ION/IOFF = 65, red curve in Figure 4.35-b). Increasing the anode voltage implies a higher ION current reaching the equipment compliance at VA = 1.2 V (ION = 38 µA/µm, gray curve in Figure 4.35-b). IOFF current stays steady (10 nA/µm).

Figure 4 . 35 .

 435 Figure 4.35. Logic switch Z 2 -FET DGP operation dependency on (a) front-gate bias at VA = 1.1 V and (b) anode bias at VGf = 0.8 V. VGbN = VGbP = 0 V.

  -FET DGP, allowing a very low logic switch operation. With a positive constant GP-N value, the device can be turned off at just VGf = 0.4 V. Though, a zero VGbN bias is not sufficient to totally eliminate the current in off state. To enhance the switch off operation, barriers need to be reinforced with VGbN bias. The parasitic IOFF current starts decreasing with GP-N bias and disappears at VGbN ≥ 1 V. Despite the ION reduction due to VGbN increase, the device still offers noticeable current margin (ION/IOFF ~ 100).

Figure 4 . 36 .

 436 Figure 4.36. Impact of N-type ground plane bias on Z 2 -FET DGP behavior while operating as logic switch. VA = 1.1 V, VGf = 0.4 V and VGbP = 0 V.

4. 3 . 1 . 3 .

 313 Device Length Effect on Device Switch ONResults of short and long Z 2 -FET DGP operating as ON-OFF switches are presented in

Figure 4 . 37 .

 437 Figure 4.37. Decreasing the device length is always beneficial as it offers less occupied silicon surface on chip. It also increases the current. Despite the larger ION current obtained in short Z 2 -

Figure 4 . 37 .

 437 Figure 4.37. Evolution of ION/IOFF current ratio with Z 2 -FET DGP device length at VGf = 0.6 V, VA = 1.1 V and VGbP =VGbN = 0 V.

Transistor MOX Middle OXide MRAM Magnetic RAM MSD Meta Stable Dip MSDRAM Meta Stable Dip Random Access Memory NEMS Nano-Electro Mechanical System nMOS

	GO1 GO2 GR H0 HBM HfO2 HKMG HR0 HSG HV-ESD HW0 HW1 I/O IC IL R6nm q R12nm RESD RON RT t ∆t T ∆T tBOX tepi tox TP tpulse tPW tre W Wdep WF0 Z0 1, 2  b b,final b,sat f,final f,sat e-eff tSi Vth max	Plane Thin Gate Oxide Thick Gate Oxide Generation Recombination Hold "0" operation Human Body Model Hafnium dioxide High-K Metal Gate Hold "R0" Hemi Spherical Grain High Voltage ESD Hold "W0" Hold "W1" Input/Output Integrated Circuit Interface Layer Electron charge ON resistance of devices with tSi = 6 nm ON resistance of devices with tSi = 12 nm ESD resistance ON resistance Rise time Time Time variation Temperature Temperature variation BOX thickness Epitaxy layer thickness Oxide thickness Programming time Pulse duration Pulse width duration Retention time Threshold voltage Channel width Depletion width Gate workfunction Impedance Natural lengths in gated and ungated regions Potential Initial ungated part potential of Z 2 -FET Final ungated part potential of Z 2 -FET Saturated ungated part potential of Z 2 -FET Final gated part potential of Z 2 -FET Saturated gated part potential of Z 2 -FET Electron lifetime Effective carrier lifetime Maximum carrier lifetime	C Ω/µm Ω/µm Ω Ω/µm s s s °C °C nm nm nm s s s s v nm nm eV Ω nm v v v v v v s s s
	IMOS	Impact Ionization MOS
	ITRS	International Technology Roadmap for Semiconductors
	JEDEC78	Joint Electron Device Engineering Council
	LDD	Lightly Doped Drain
	LU	Latch UP
	M1	First level of Metal
	M2	Second level of Metal
	MDC	Multi Dual Cell
	MM	Machine Model
	MOS	Metal Oxide Semiconductor
	MOSFET	MOS Field Effect n-type MOS
	NVM	Non Volatile Memories
	NW	N Well
	ONO	Oxide-Nitride-Oxynitride
	P/E	Program/Erase
	PCRAM	Phase Change RAM
	PD	Partially Depleted
	PDSOI	Partially Depleted Silicon-On-Insulator
	PG	Pulse Generator
	PMOS	P type MOS
	PW	P Well
	RAM	Random Access Memory
	RCA	Removal of metallic and organic Contaminations with surface Activation
	ReRAM	Resistive RAM

1.6.3. 1T-DRAM in Partially Depleted SOI and Bulk Technologies 1.6.3.1. Floating Body Effects (FBE): an advantage for transistor operating as 1T-DRAM

	The most challenging issue in Partially Depleted Silicon on Insulator (PDSOI) and bulk
	technologies, is the control of Floating Body Effects [87] (FBE). In form of mobile charge, FBEs
	appear in the device body due to the isolation of silicon film by using the buried oxide (BOX) layer

Table 1 .

 1

1. Operating bias for N-MOSFET transistor used as 1T-DRAM in Bulk and PDSOI technologies.

Chapter 2. Band-Modulation Devices: Fabrication Process and Operation Principle SUMMARY 1.1. Introduction ____________________________________________________________ 65 1.2. Zero Subthreshold Slope and Zero Impact Ionization FET: Standard Z 2 -FET ______ 66

	1.2.1. Device Fabrication ___________________________________________________________ 66
	1.2.2. Principle of Operation ________________________________________________________ 68
	1.3

. Novel Band-Modulation Device with Dual Ground Planes: Z 2 -FET DGP _________ 77

1.3.1. Device Architecture __________________________________________________________ 77 1.3.2. Advantage of Dual GP ________________________________________________________ 78 1.4. Back-Gate Modulated Device with No Front-Gate : Z 3 -FET ____________________ 81 1.4.1. Fabrication Process ___________________________________________________________ 81 1.4.2. Advantage of No Front-Gate ___________________________________________________ 81 1.5.

Conclusion _____________________________________________________________ 84 1.6. References _____________________________________________________________ 85 2.1. Introduction

	In this chapter, different variants of band-modulation devices are presented: Z 2 -FET, Z 2 -FET
	DGP and Z 3 -FET. They are fabricated with the most advanced UTBB FDSOI technology in 14
	nm and 28 nm nodes. The operation principle, relying on the modulation of electrons and holes
	injection barriers, is demonstrated with TCAD simulations. Sharp switch characteristics of all
	variants such as adjustable triggering voltage VON, high current ratio ION/IOFF, low leakage current
	IOFF and large hysteresis are confirmed with experimental results. In addition, the benefit of
	implementing an additional N-type ground plane (GP-N) underneath the gate of standard Z 2 -FET

or removing completely the front-gate and operating with only ground planes (N and P) acting as back-gates are highlighted.

2.

2. Zero Subthreshold Slope and Zero Impact Ionization FET: Standard Z 2 -FET 2.2.1. Device Fabrication 2.2.1.1. 28 nm FDSOI Technology

. Conclusion ____________________________________________________________ 124 3.6. References ____________________________________________________________ 124 3.1. Introduction

	Chapter 3. Measurement and
	Modeling of Z-FET
	Family Devices
	SUMMARY
	3.1. Introduction ____________________________________________________________ 88
	3.2. DC Measurements ______________________________________________________ 89
	3.2.1. Impact of Silicon Thickness on Z-FET Devices Behavior ______________________________ 89
	3.2.2. Impact of Z-FET Devices Parameters_____________________________________________ 91
	3.2.3. FDSOI 28 nm node vs. 14 nm node _____________________________________________ 104
	3.3. TLP Measurements ____________________________________________________ 106
	3.3.1. Standard Z 2 -FET ___________________________________________________________ 106
	3.3.2. Z 3 -FET ___________________________________________________________________ 108
	3.3.3. Stacked Architectures ________________________________________________________ 110
	3.4. Interface Potential Analytical Model _______________________________________ 113
	3.4.1. Introduction _______________________________________________________________ 113
	3.4.2. Potential Distribution Model ___________________________________________________ 114
	3.4.3. Model Verification __________________________________________________________ 118
	3.4.4. Z 2 -FET DGP and Z 3 -FET ____________________________________________________ 121
	3.5In this chapter, DC and TLP characterizations of band-modulation devices fabricated in
	advanced FDSOI technologies are presented. They feature promising assets such as adjustable
	triggering voltage, low leakage current IOFF, large hysteresis and high current ratio ION/IOFF. Stacked

architectures of Z-FET devices with hybrid-bulk SCR are explored showing high performance and robustness against ESD events. Analytical expressions for the potential distribution of Z 2 -FET all over the channel are developed. The compact model is valid for low-doped UTBB Z 2 -FET with different geometries, and agrees well with TCAD simulation results in a wide range of front and back-gate voltages.

  is the oxide dielectric constant and tox/tbox are the thicknesses of the front and back oxides, respectively. 𝑉 𝐹𝐵𝑓 = 𝑉 𝑇 ln (

	𝑁 𝐴,𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝑛 𝑖	𝑁 𝐴,𝐺𝑃-𝑃 ) and 𝑉 𝐹𝐵𝑏 = 𝑉 𝑇 ln ( 𝑛 𝑖

  )

	𝛽 𝑓 ≈	𝑞𝑁 𝐴 𝜀 𝑆𝑖	-	𝜀 𝑜𝑥 𝜀 𝑆𝑖	(𝑡 𝑏𝑜𝑥 𝑉 𝐺𝐹 + 𝑡 𝑜𝑥 𝑉 𝐺𝐵 ) 𝑡 𝑆𝑖 𝑡 𝑜𝑥 𝑡 𝑏𝑜𝑥	.

  )

	𝑉 𝑖𝑛 =	𝐵 1 𝜆 1 sinh ( 𝐿 𝑛 𝜆 1 𝜆 1 sinh ( 𝐿 𝑛 𝜆 1 ) cosh ( 𝐿 𝑝 𝜆 2	) + 𝐵 2 𝜆 2 sinh ( 𝐿 𝑝 ) + 𝜆 2 sinh ( 𝐿 𝑝 𝜆 2 ) cosh ( 𝐿 𝑛 𝜆 1 𝜆 2 )	) ,	(3.23)
	with 𝐵 1 = [𝑉 𝑏𝑖 + 𝐴 2 (cosh ( 𝐿 𝑝 𝜆 2	𝐿 𝑛 ) -1)] and 𝐵 2 = [𝑉 𝑏𝑖 + 𝑉 𝐴 + 𝐴 1 (cosh ( 𝜆 1

  FET, the interface potential distribution in Lp region is still the same as for other Z-FET devices while the Ln surface potential changes as it is now modulated, instead of front-gate,

		-Chapter 3 : Measurements and Modeling of Z-FET Family Devices -
		𝜆 1 = √ 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑜𝑥 𝜀 𝑜𝑥	, 𝑎𝑛𝑑 𝐴 1 = 𝜆 1 = 𝜆 2 = √ 𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑜𝑥 𝜀 𝑜𝑥 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 -(𝑉 𝐺𝐹 + 𝜀 𝑜𝑥 ,	𝑡 𝑜𝑥 𝑡 𝑏𝑜𝑥	𝑉 𝐺𝐵𝑁 ),	(3.29)
	similarly :	𝐴 1 = 𝑉 𝐺𝐵𝑁 -	𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝜀 𝑜𝑥	𝑎𝑛𝑑 𝐴 2 = 𝑉 𝐺𝐵𝑃 -	𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝜀 𝑜𝑥	.
		Φ 𝑝 (𝑥) = 𝐴 2 +	1 2𝐿 𝑝	[(𝑉 𝑖𝑛 -𝐴 2 ) (𝑒	𝐿 𝑝 +𝑥 𝜆 2 -𝑒	𝐿 𝑝 -𝑥 𝜆 2 )	(3.30)
				𝑒	𝜆 2 -1
								2𝐿 𝑝 -𝑥	𝑥
				+ (𝑉 𝑏𝑖 -𝐴 2 ) (𝑒	𝜆 2 -𝑒	𝜆 2 )],
	with
		𝜆 2 = √ 𝜀 𝑆𝑖 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥 𝜀 𝑜𝑥	, 𝑎𝑛𝑑 𝐴 2 = 𝑉 𝐺𝐵𝑃 -	𝜀 𝑜𝑥 𝑞𝑁 𝐴 𝑡 𝑆𝑖 𝑡 𝑏𝑜𝑥	.	(3.31)
	For Z 3 -by a back N-type ground plane (GP-N). Analytical equations of potential distributed in the whole
	body of Z 3 -FET are given by:
		Φ 𝑛 (𝑥) = 𝐴 1 +	𝑒	1 𝜆 1 -1 2𝐿 𝑛	[(𝑉 𝑏𝑖 + 𝑉 𝐴 -𝐴 1 ) (𝑒	𝐿 𝑛 +𝑥 𝜆 1 -𝑒	𝐿 𝑛 -𝑥 𝜆 1 )	(3.32)
		+ (𝑉 𝑖𝑛 -𝐴 1 ) (𝑒	2𝐿 𝑛 -𝑥 𝜆 1 -𝑒	𝑥 𝜆 1 )],
	and
		+ (𝑉 𝑖𝑛 -𝐴 1 ) (𝑒 + (𝑉 𝑏𝑖 -𝐴 2 ) (𝑒 2𝐿 𝑛 -𝑥 𝜆 1 -𝑒 𝜆 2 -𝑒 𝜆 1 )], 𝜆 2 )], 𝑥 2𝐿 𝑝 -𝑥 𝑥 𝑒 𝜆 2 -1 1 [(𝑉 𝑏𝑖 + 𝑉 𝐴 -𝐴 1 ) (𝑒 𝐿 𝑛 +𝑥 𝜆 1 -𝑒 Φ 𝑝 (𝑥) = 𝐴 2 + 1 2𝐿 𝑝 [(𝑉 𝑖𝑛 -𝐴 2 ) (𝑒 𝐿 𝑝 +𝑥 𝜆 2 -𝑒 𝐿 𝑝 -𝑥 𝐿 𝑛 -𝑥 𝜆 1 ) 𝜆 2 )	(3.28) (3.33)
	with where
								123

Table 4 .

 4 1. As capacitor-less DRAM cells are asked to respond very fast, the 10 mA current measurement range with minimum rise/fall time and pulse width was chosen to test Z-

	FET devices.

Table 4 .

 4 3. Minimum rise/fall time, pulse width and recommended settling time for different current measurement regimes in two operation modes of WGFMU.

Table 1 .

 1 Band-modulation devices and most probable appropriate applications.According to Table1, doped Z 3 -FET is highly recommended for ESD protection as it does not need an external bias to be transparent during the circuit normal operation. For 1T-DRAM operation, Z 2 -FET and Z 2 -FET DGP are proposed as competitive variants featuring exceptional current margin and high retention time. If they include SiGe channel they can be used as ULP embedded memories. The logic switch suits best to Z 2 -FET with Dual Ground Planes. As it is reinforced by GP-N, the hysteresis can be eliminated easily at low front-gate voltages. The backgate operated Z 3 -FET cannot pursue an aggressive scaling. But, the top surface free from metal gate is very beneficial and makes him a viable candidate for combined memory/sensing applications (bio, light and radiation sensing). Other Z-FET devices can also be used for sensing.

Acknowledgements

Abbreviations

Once the device quasi-static characteristics was recorded, transient measurements useful for practical applications were considered. The Z 2 -FET capability as a dynamic memory cell was checked by applying a simple transient pattern, as shown in Figure 4.2. Four main operations summarize the Z 2 -FET functionality as 1T-DRAM, as described below.

 Write "0" (W0)

The pattern starts by applying front-gate and anode biases (VGf = 1.2 V and VA = 0 V). Then, programming the state "0" ("Erasing", in other words) consists of lowering VGf down to 0 V while keeping VA = 0 V. In this case, accumulated electrons under the front-gate are evacuated from Ln region into the anode.

 Write "1" (W1)

The mechanism of writing "1" in Z 2 -FET is simple and does not depend on impact ionization [10,25], band-to-band tunneling [9,26,27] or gate tunneling current [28]. In this mode, the Z 2 -RAM is forced to operate as a forward-biased PIN diode with high current (IA = 26 µA/µm in Figure 4.2). For that purpose, the Ln barrier should be eliminated by setting the front-gate pulse to 0 V and embedding it in a VA pulse that triggers the flow of carriers from node to node. Electrons are stored again under the front-gate.

 Hold state

In order to maintain as long as possible the present cell state, the front-gate voltage should be returned into its high value and VA to 0 V. After W0, the remained electrons are not sufficient to form an inversion layer under the gate. Thus, the device enters in non-equilibrium state (deep depletion like effect, detailed in the next subsection) inducing a strong barrier in Ln region [29].

Conversely, while holding "1", the barriers are lower implying VON reduction. Since the electrons are numerous, the diode is at equilibrium conserving infinitely the state "1" of the memory cell.

 Read state (R0 and R1)

The Z 2 -FET memory response on anode pulse, when reading, depends on its previous state.

After writing "0", the gated region of Z 2 -FET is depleted from electrons featuring a strong Ln barrier and high triggering voltage VON. Hence, the anode pulse in this case (VA < VON) cannot Although this work attempted to provide a detailed study of band-modulation devices, several aspects could not be fully covered. They deserve to be addressed in future investigations:  Further Z-FET structures optimization and reliability test.

 1T-DRAM cell array simulation and benchmark.

 Extra transient measurements of SiGe variants for ULP applications.

 Advanced investigation of all structures as logic switch.

 RF characterization and analysis.

 Full compact SPICE model.

 Transfer of band-modulation concept to FinFETs, tri-gate, and nanowires architectures.

To summarize, the work presented in this thesis is a contribution for clarifying the static and transient operation principles of band-modulation devices in UTBB 14 nm and 28 nm technologies. Explored devices are innovative and feature outstanding characteristics. They are highly recommended for ESD protection, ULP embedded 1T-DRAM and logic switch.

Abstract

During the past 5 decades, Complementary Metal Oxide Semiconductor (CMOS) technology was the dominant fabrication method for semiconductor integrated circuits where Metal Oxide Semiconductor Field Effect Transistor (MOSFET) was and still is the central component.

Nonetheless, the continued physical downscaling of these transistors in CMOS bulk technology is suffering limitations and has been stopped nowadays. Fully Depleted Silicon-On-Insulator (FDSOI) technology appears as an excellent alternative that offers low-power consumption and improved electrostatic control for MOS transistors even in very advanced nodes (14 nm and 28 nm). However, the 60 mV/decade subthreshold slope of MOSFET is still unbreakable which limits the supply voltage reduction. This motivated us to explore alternative devices with sharpswitching: Z 2 -FET (Zero subthreshold slope and Zero impact ionization), Z 2