Nicolas Duchaux
email: nicolas.duchaux@telecom-bretagne.eu

Cyril Lahuec

Matthieu Arzel

Fabrice Seguin

Analog Decoder Performance Degradation Due to BJTs' Parasitic Elements

Keywords: Analog decoding, BiCMOS, parasitic elements, behavioral modeling

This paper presents the effect of BJTs' parasitic elements on the decoding performance of a BiCMOS analog decoder. The transistor's parasitic effects are taken into account to develop a more accurate behavioral model of the computing nodes. The model is applied to double-binary 0.25-µm BiCMOS analog decoders. Behavioral simulations show that the BJTs' parasitic elements deteriorate the error correcting performance of a stand-alone APP decoder by 0.5dB compared with the ideal BER. In a turbo scheme, the loss is reduced to 0.2dB for BER smaller than 10 -2 . A simple solution based on an NMOS amplifier is proposed to counterbalance the dominant parasitic element. The amplifier reduces the degradation by 0.2dB for the APP decoder. Similar improvements are observed in the turbo scheme for BER greater than 10 -2 .

I. INTRODUCTION

The usual architecture of a digital receiver employs a forward-error correcting device to overcome transmission errors due to a noisy communication channel. In the late nineties two research teams, led by Professor Hagenauer and Professor Loeliger showed that the digital decoder could be advantageously replaced by an analog counterpart [START_REF] Hagenauer | Der analoge Decoder[END_REF] - [START_REF] Loeliger | Probability propagation and decoding in analog VLSI[END_REF]. Probability-propagation algorithms such as the Belief Propagation or Turbo ones are directly mapped onto silicon thanks to the non-linear characteristics of transistors. The resulting analog network of computing nodes converges to a steady state to finally correct errors as well as digital counterparts, but with the major advantages of lower power consumption, higher speed and/or smaller on-chip area as shown by the first chips [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF] [START_REF] Lustenberger | All analog decoder for a binary (18,9,5) tail-biting trellis code[END_REF]. Since then, several other research teams have developed proof-of-concept circuits to validate new architectures, design methodology, automatic synthesis and even built-in self test [START_REF] Dai | Design methodology for analog VLSI implementations of error control decoders[END_REF] - [START_REF] Amat | Reconfigurable analog decoder for a serially concatenated convolutional code[END_REF]. Nevertheless, many issues are still to be solved in order to challenge digital decoders. As for any other system, before designing the decoder at transistor level, developing a behavioral model is mandatory first to validate the architecture, as in [START_REF] Hagenauer | The analog decoder[END_REF] [9] [START_REF] Arzel | Semiiterative analog turbo decoding[END_REF] and second to estimate the decoder's Bit and Frame Error Rates (BER/FER). For the latter purpose, transistor level simulations are too time consuming to obtain BER and FER when dealing with relatively large decoders. The behavioral models presented in previous works, such as [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF] and [START_REF] Arzel | Analog slice turbo decoding[END_REF], consider ideal computing nodes and only implement the decoding algorithm. For very small decoders there is, in general, a good agreement between behavioral and actual measurements from fabricated circuits, such as [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF]. When considering complex decoders, there is a relatively large discrepancy, from a few hundredths [START_REF] Lahuec | Design and test of a 0.25-µm BiCMOS double-binary analogue APP decoder[END_REF] up to a couple of dBs [START_REF] Gioulekas | A high-speed sige bicmos analog map decoder[END_REF], between the two. As most of the published work to date concerns the design of CMOS analog decoders [START_REF] Gaudet | A 13.3mbps 0.35µm CMOS analog turbo decoder ic with a configurable interleaver[END_REF] - [START_REF] Vogrig | A 0.35-µm cmos analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF], the performance degradations in terms of BER brought in by MOS transistors imperfections such as mismatches have been studied, see for instance [START_REF] Vogrig | A 0.35-µm cmos analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF]. Fewer works have been published on BJT-based analog decoders [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF] [12] [START_REF] Lustenberger | On mismatch errors in analog-VLSI error correcting decoders[END_REF]. Performance degradation of such decoders due to transistor mismatch was studied in [START_REF] Lustenberger | On mismatch errors in analog-VLSI error correcting decoders[END_REF]. The authors concluded that assuming random mismatch, the errors introduced do not impair the decoder's performance but merely imply a slower convergence [START_REF] Lustenberger | On the design of analog iterative VLSI decoders[END_REF]. However, no comprehensive study on the effects of non random BJT's parasitic elements over decoding performance exists to date. These effects are not random as they affect every single BJT in the decoder and hence could impair its performance. Some insights on this matter were given in [START_REF] Arzel | Semi-iterative analogue turbo decoding -An application to DVB-RVS-like codes[END_REF] [START_REF] Duchaux | Effect of BJT's parasitics on computing cells for analog decoders[END_REF] but the studies were rather incomplete. Moreover, although the cause of degradation was identified in the previous works, no attempt has been made to address these additional errors to improve the overall decoding performance of the decoders. This paper aims thus at providing an in-depth study of performance degradation of BJT-based analog decoders due to transistors' non-idealities. A simple solution counteracting the BJT parasitic elements is proposed and simulations are run for a stand-alone A Posteriori Probability (APP) decoder and a turbo decoder. The results are shown taking the case study of a 0.25-µm BiCMOS analog tail-biting double-binary APP decoder [START_REF] Arzel | Semiiterative analog turbo decoding[END_REF].

The paper is organized as follows. Section II presents the targeted code and the decoder's architecture. Section III is about the different BJT's parasitic effects to be taken into account and their corresponding behavioral models. Section IV presents the computing node behavioral model. Then, the decoding performance of a stand-alone APP decoder and a turbo-decoder are assessed. In Section V, a circuit is proposed to counterbalance the deterioration of the decoder's performance. Finally, Section VI concludes the paper.

II. APP DECODER ARCHITECTURE

A. Target code

The background of the study concerns a double-binary 8-state tail-biting Recursive Systematic Convolutional code. Double-binary simply means that the decoder processes 2-bit symbols. The convolutional encoder has a code rate of 2/3 and produces a single parity bit Y per double-binary input symbol X 1 X 2 as shown in Fig. 1. A trellis section of this code is illustrated in Fig. 2. Compared to a trellis section of a code using one-bit symbols, the number of branches is doubled but the length is halved.

The motivation behind choosing such a code is that it has major advantages compared with its simple binary counterparts. Berrou et al. [START_REF] Berrou | The advantages of non-binary turbo codes[END_REF] showed that the convergence of m-ary turbo codes is better but the gain is less noticeable for m > 2. Their minimal distances and their asymptotic gains are larger. They are also less sensitive to puncturing. Already used as the code for the DVB-RCS standard [START_REF]Interaction channel for satellite distribution systems[END_REF], these advantages also make double-binary turbo codes key candidates for many other telecommunication standards.

B. Decoder structure

The APP decoder of the tail-biting code is implemented as a ring, see Fig. 3. The decoder is designed to deal with a frame length of 24 double-binary symbols meaning that the decoder

B A Dec Γ Extr L(X i 1 ) L(X i 2 ) L(Y i ) L(X i eIN ) α i+1 α i β i+1 β i d 1 i d 2 i L(X i eOU T )
Fig. 3. Tail-biting APP decoder structure and decoding section.

processes 72-bit long input blocks, 48 information bits and 24 redundancy bits. There are as many decoding sections as symbols to decode, i.e. 24 in the present case. As in [START_REF] Lustenberger | All analog decoder for a binary (18,9,5) tail-biting trellis code[END_REF], each section is built from four modules: a Γ module to compute the branch metrics, an A module for the forward state metrics, a B module for the backward state metrics and a Dec module to decide on the value of the double-binary symbol. There are two sets of inputs to the section. The first set is the data generated by the channel, L(X i 1 ) L(X i 2 ) L(Y i ), which are associated with the i th symbol X i 1 X i 2 and its parity bit Y i . The second set of inputs is composed of the forward and backward state metrics i and i + 1 produced by the adjacent trellis sections. The outputs are the metrics i + 1 and i, fed to the adjacent sections, and the decisions

d 1 i d 2 i for the transmitted symbol X i 1 X i 2 .
A fifth module is required if the tail-biting APP decoder is part of a turbo decoder: the Extr module. This module computes the extrinsic information L(X i eOU T ) which is then used by the module of the second tail-biting APP decoder as L(X i eIN ). All the above modules -except the Dec one -are basically sum-product modules implementing the decoding algorithm. The design of the required computing nodes is described next.

C. Sum-product nodes

BJT-based Gilbert cells [START_REF] Gilbert | A precise four-quadrant multiplier with subnanosecond response[END_REF] are used as probability multipliers. Considering that the input voltages are proportional to Log-Likelihood Ratios (LLR), the output currents are proportional to the products of probabilities. Summing probabilities represented by currents is then simply done by connecting wires. This simple sum-product circuit was demonstrated in [START_REF] Loeliger | Probability propagation and decoding in analog VLSI[END_REF] for any field of probability and has been used in a number of analog decoders [START_REF] Lustenberger | On the design of analog iterative VLSI decoders[END_REF] [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF]. In the present case for instance, the A module of the decoding section requires the design of an extended Gilbert structure with 8-ary inputs, as illustrated in Fig. 4. It uses 72 transistors. The lower stage is an emitter-coupled set of bipolar transistors whose bases are connected to n X voltages V X i that are proportional to the log-likelihoods of the data X. The upper stage is made up of n X identical emitter-coupled bipolar sets, each of them being connected to a different collector on the lower level. The bases of these bipolar sets are connected to n Y voltages V Y j proportional to the log-likelihoods of the data Y . Thus, the outputs are n X ×n Y currents I out k given by:

V X V X V X X n V Y V Y V Y n Y 1 2 1 2 I n Y out n + 1 I Y out I Y n + 2 out ( X n Y n -1 ) + 1 out I n X n Y out I ( X n Y n -1 ) + 2 out

I

Connection stage

I I Y n 2 out 1 out 2 out I bias bias V I Z n I Z 1 I Z 2 I Z Fig. 4. Extended Gilbert cell. V IN V DD V P OL D 1 D 2 Q 1 Q 2 I C1 I C2 I E1 I E2 I BIAS
I out (i-1)×nY +j = p X (x i ) p Y (y j ) I BIAS (1)
All the pair-wise products p X (x i ) p Y (y j ) are thus available for further computations. For instance, in Fig. 4, the currents are summed using simple nodes to produce the output currents

I Z k .
Equation ( 1) is correct considering the collector current to be solely an exponential function of the base-emitter voltage. The next section shows how the BJT's parasitic elements impair the conversion of LLRs into probabilities.

D. Error converting LLRs into probabilities

The basic circuit in Fig. 5 ) of a minimal size emitter-coupled bipolar pair: ideal and simulated (transistor level), I BIAS = 250µA, V DD = 2.8V . currents I C1 and I C2 . Designed with Cadence® design tools for NXP's QUBIC4 0.25-µm BiCMOS process, the circuit uses minimal size transistors, a 2.8V supply and a 250µA biasing current. A transistor level simulation is run with Spectre® simulator to assess the accuracy of the LLR into probability conversion. This simulation takes into account all the parasitic effects present in the transistor electrical compact model (Mextram 504) [START_REF][END_REF] provided by NXP. Fig. 6 represents the output probability ratio versus the input probability ratio, i.e. the ratio of the two collector currents I C2 and I C1 versus exp( VIN VT ). Ideally, the curve obtained should be a straight line with a slope of 1. It is far from being the case as the conversion error is as high as 85 percent for an input LLR of 100 . This simple simulation shows that the assumption of having an ideal exponential relationship between the collector current and the base-emitter voltage is absolutely incorrect. Two questions arise from this, where does this come from and is this really a problem for the decoder?

Answering these requires a careful study of the transistor electrical model provided by NXP. From this analysis the relevant parasitic phenomena are extracted to build an accurate behavioral model of the transistor.

III. EFFECTS TO BE TAKEN INTO ACCOUNT

The transistor behavioral model has to be accurate and yet simple enough to simulate the decoder in a reasonable amount of time. Finding which parasitic effects have to be taken into account is somehow lengthy but not complicated. It is assumed that the transistor is in the forward active region, which reduces the number of physical effects to test for relevance. Each effect described by one or several equations in the Mextram model [START_REF][END_REF] has been simulated separately to see its impact on the collector current. Among all of them, only three have to be added to the Ebers-Moll model to correctly describe the transistor's collector current. These effects are the parasitic emitter resistor, the reverse Early and the Webster effects. First, a brief description of these effects is given. Second, a comparison is made between the collector currents obtained from spice-level simulations using the Mextram model and from three behavioral models, each described with an equation, taking the different effects into account.

A. Ebers-Moll model

This model is the one usually assumed to simulate the computing nodes of analog decoders designed using bipolar transistors as in [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF]. This is also the model used to obtain Equation [START_REF] Hagenauer | Der analoge Decoder[END_REF]. The Ebers-Moll model takes into account only the exponential I-V characteristic of the transistor. For the region of operation of the transistor and considering the Ebers-Moll model, the collector current I * em C is:

I * em C = I S exp V BE V T (2)
where I S is the saturated current of the of the base-emitter junction, V T the thermal voltage and V BE the base-emitter voltage. Despite the fact that this model is very convenient, it departs from reality too much as Fig. 6 shows. The effects to be added to obtain a collector current equation closer to the transistor's Mextram model are described next.

B. Parasitic emitter resistor

The most obvious effect to be added to the Ebers-Moll model is the emitter resistor. This resistor may not be negligible when small size transistors are used and large biasing currents are necessary. Considering that

I * R C ≈ I E , the collector current I * R
C is given by:

I * R C = I S exp V BE V T exp - R E I * R C V T (3)
where R E is the parasitic emitter resistor. Its value is about 220Ω for the process used and the minimal size transistors.

C. Forward and reverse Early effects

The Early effects take into account the finite output resistor of the BJT and the base-width modulation due to the biasing of the junctions. Base-width modulation reduces the collector current and affects more small size devices than large ones. The first effect is the well-known forward Early effect, characterized by the Early voltage V AF . The second effect is known as the reverse Early effect. It is also characterized by a voltage, denoted V AR . The Early effects term q 1 is described in [START_REF] Paasschens | Introduction to and Usage of the Bipolar Transistor Model Mextram[END_REF] as:

q 1 = 1 + V BE -R E I C V AR 0.5 + V BC + R C I C |V AF | 0.05 (4)
The values of V AF and V AR are, respectively, -33V and 2V in the process used and for minimal size BJT. The forward Early effect is ten times smaller than the reverse effect. Hence q 1 can be approximated to:

q 1 ≈ 1 + V BE -R E I C V AR (5)
This approximation yields a modeling error of four percent at most. Let I * RE C be the collector current taking the emitter resistor and the reverse Early effect into account:

I * RE C = I S exp VBE VT exp - RE I * RE C VT 1 + VBE -RE I * RE C VAR (6)

D. Webster effect

The last effect which has to be taken into account is the Webster effect [START_REF] Webster | On the variation of junction-transistor current-amplification factor with emitter current[END_REF]. This effect is not well-known and hence is often discarded when analyzing BJT circuits. Basically, it accounts for the increase of conductivity in the base. When higher current is injected into the base, the recombination rate increases hence lowering the emitter efficiency. The Webster effect term is used as defined in [START_REF] Paasschens | Introduction to and Usage of the Bipolar Transistor Model Mextram[END_REF]. Let I * REW C be the collector current where the emitter resistor, the reverse Early effect and the Webster effect are taken into account:

I * REW C = I F 1 + VBE -RE I * REW C VAR 1+ 1+4 I F I K 2 (7)
where I K is the knee current which is a model parameter due to the Webster effect. I K is equal to 1.97mA for the process used. I F is the ideal forward current of the transistor described in [START_REF][END_REF]:

I F = I S exp V BE V T exp - R E I * REW C V T (8)

E. Comparison of the different models

In this section, the accuracy of the different behavioral models defined in the above subsections is assessed. Let I C be the collector current simulated by Spectre® using the Mextram model provided by NXP. Let I * C be the collector current obtained from the behavioral model sought. Then, plotting the ratios I C /I * C versus V BE , where I * C is successively defined by Equation (2) to Equation [START_REF] Yiu | Digital built-in selt test of CMOS analog iterative decoders[END_REF], and comparing them to a ratio of 1 shows how good the models are with respect to the Mextram model. The closer to 1 the ratio is, the better the behavioral model is. This is shown in Fig. 7 for V BE ranging from 0.5V to 1V , which are typical values found in the actual decoder. It is important to have a behavioral model accurate over this full range of V BE as the lower range corresponds to a low transistor biasing, i.e. low probability, and the higher range corresponds to a high biasing, i.e. a high probability.

From Fig. 7 it can be seen that only the model described by Equation ( 7) is close enough (less than four percent in error) to the Mextram model over the full range of V BE . Hence, this model is chosen and used in the next section to build the complete decoder's behavioral model.

V BE I C /I * C Mextram model I * C = I * em C I * C = I * R C I * C = I * RE C I * C = I * REW C Fig. 7.
Ratio of I C , the collector current obtained from spice-level simulation, over I * C , the collector current yielded by the various behavioral models, versus V BE (V BC = 0V ).

IV. DECODERS BEHAVIORAL MODELING

A. Behavioral modeling of an emitter-coupled pair

The bipolar pair represented in Fig. 5 is the basic block of the sum-product nodes. It can be considered as a system composed of one input voltage V IN and two coupled outputs currents I C1 and I C2 . These two currents are modeled using Equation [START_REF] Yiu | Digital built-in selt test of CMOS analog iterative decoders[END_REF] and their ratio is:

I * C2 I * C1 = (1+ VBE1-RE I * C1 VAR )(1+ 1+4 IF 1 IK ) (1+ VBE2-RE I * C2 VAR )(1+ 1+4 IF 2 IK ) e ( V IN V T - R E V T I δ ) (9)
where

I δ = I * C2 -I * C1 ( 10
)
V BE1 is the base-emitter voltage of transistor Q 1 , I F 1 is the forward current of transistor Q 1 (respectively V BE2 and I F 2 for transistor Q 2 ).
Equation ( 9) is not easy to use as V BE1 , V BE2 , I F 1 and I F 2 depend on V IN . It would be easier to implement the behavioral model if the collector current ratio depended directly on V IN , I C1 and I C2 . This can be easily done if some approximations are made. Using the following Taylor expansions when x is small:

exp(x) ≈ 1 + x (11) √ 1 + x ≈ 1 + 0.5x (12)
and doing the first order approximation I F ≈ I * C in the Webster effect terms, then Equation ( 9) can be simplified to:

I * C2 I * C1 = exp V IN V T - R E V T I δ + R E V AR I δ - V IN V AR - I δ I K (13)
0.9 0.95

1 1.05 1.1 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 V IN ( IC2
I BIAS = 250µA, V DD = 2.8V
To show that the simplifications done are acceptable, the ratio ( IC2 IC1 )/(

I * C2 I * C1 ) is plotted versus V IN when I * C2 I * C1
is successively defined by Equations ( 9) and ( 13). I C1 and I C2 still represent the collector currents obtained from the NXP transistor model. The result is shown in Fig. 8. As in section III.E, the closer to 1 this ratio is the better the modeling. The error of modeling is at most six percent over the full range of V IN when Equation ( 9) is used and is at most seven percent when using Equation [START_REF] Gioulekas | A high-speed sige bicmos analog map decoder[END_REF]. This validates the final behavioral model represented by Equation [START_REF] Gioulekas | A high-speed sige bicmos analog map decoder[END_REF]. It can be noted this behavioral model is based on the NXP QUBIC4 0.25-µm process which is a typical process. The values of R E , V AR and I K should be adapted if another process is used but the results should be similar.

B. Behavioral simulation of the APP decoder

In this section, the bit error rate curve obtained using two behavioral models of the analog APP decoder defined in section II are presented. The first model considers that the decoder is made of ideal multipliers. The second model takes into account the non-idealities of the BJTs as described in Equation [START_REF] Gioulekas | A high-speed sige bicmos analog map decoder[END_REF]. Both models are first-order models implemented using Simulink® . Each module of the decoder in Fig. 3 is described by blocks programmed with C language and the analog exchange of information is made through RC lines. Runge-Kutta ODE solver with variable time-steps is used to compute the solution. The bias currents of the computing nodes are all equal to 250µA and the transistors are minimal size ones. The degradations brought in by the parasitic BJT's elements impair the error rate by 0.5dB when compared with the ideal case as shown in Fig. 9.

This degradation is significant enough to be taken into account for a stand-alone APP decoder. It is interesting to study if the parasitic elements impact an analog turbo decoder in the same manner.

C. Behavioral simulation of a turbo decoder

The behavioral models of the APP decoder presented in the above sections are now used to implement a turbo scheme. A turbo code with the following parameters is assumed: rate of 1/2 with no puncturing. The interleaver used is presented in Table I. The i th symbol in the natural order corresponds to the j th symbol in the interleaved order. Moreover a local disorder is introduced, the two bits of one double-binary symbol over two are inverted. The interleaver is modeled by RC lines in Simulink®. The analog turbo decoder is simulated considering the multipliers ideal and then taking into account the BJT's parasitic elements. The BER curves obtained are presented in Fig. 10. For a BER greater than 10 -2 , the parasitic BJT's elements deteriorate the performance by more than 0.5dB, while for a BER smaller than 10 -2 the loss is 0.2dB compared with the ideal case. As expected, the turbo structure compensates the errors brought by the two APP decoders at high SNR. Thanks to the uncorrelated data in each decoder, the turbo structure can almost overcome the errors added by the BJTs' parasitic elements when the SNR is larger that 2dB.

D. Computational cost

The computational cost of the proposed model is compared with the ideal and the Mextram models. A single 24-symbol frame is randomly generated at an SNR of 4dB. This frame is fed to two Simulink® behavioral models of the stand-alone APP decoder, one is ideal (using Equation ( 2)) and the other takes the parasitic elements into account (using Equation ( 13)). The time it takes to simulate the decoding of the frame on one 2) Equation ( 13) Normalized 1 24 155 000 simulation time core of an Intel Xeon 2.66GHz processor is recorded. For the ideal decoder model, the simulation runs for 1.3s while 31s are required when the proposed model is used. Decoding the same frame on the same computer using spice-level simulation (hence with the Mextram model) requires 2.3 days. These results are shown in Table II, normalized to the simulation time of the ideal decoder. Based on that, it is possible to estimate the simulation time required to reach a given BER. For instance, to reach 10 -4 for 200 bits in error, it takes two weeks with the proposed model while more than 300 years are necessary using spice-level simulations. Although the proposed model is relatively slow, it should provide a better idea on how the actual decoder will perform. The simulation time could be reduced using the importance sampling approach [START_REF] Sadowsky | A new method for viterbi decoder simulation using importance sampling[END_REF] [START_REF] Winstead | Importance sampling for spice-level verification of analog decoders[END_REF]. However, this work concentrates on the model accuracy and not on the simulation time, so importance sampling was not considered.

V. COUNTERBALANCING BJTS' PARASITIC ELEMENTS

A. Most relevant effect

The effects described with Equation (13) seem to be quite hard to counterbalance. The parasitic emitter resistor could be counterbalanced by modifying either the size of the BJTs or the bias current. The value of R E is directly proportional to the area of the emitter. Considering that the bias current remains the same, choosing a large BJT will reduce the size of R E . Whereas this is valid technically, it is not economically as the resulting circuit would be too expensive to produce due to its large size. Then, one can consider keeping minimal size BJT, for the aforementioned reason, and lowering the biasing current. This is not an option either, at least to a certain extent, as it would also reduce the decoding speed. Speed is one of the main reasons for using BJTs rather than subthreshold MOS to design the decoder. Hence, the design of the multiplier cannot be changed and an additional correcting circuit must be designed.

Before undertaking such a task, it is interesting to know if one of the three parasitic effects described is more relevant than the others. By using a simulation trick, the contribution of the parasitic R E can be accurately estimated from transistor level simulations. Adding an ideal negative resistor R EC such as R EC = -R E at each emitter of the transistors in the differential pair shown in Fig. 5 cancels out the effect of the actual R E . In other words the effective parasitic R E is zero. The result is shown in Fig. 11 and is compared with what is obtained when the effective R E = 220Ω. From this figure, the parasitic emitter resistors account for almost 80 percent of the probability transfer function error. The hardest effects to counterbalance are those which are the less relevant, that is to say the reverse Early and Webster effects. Therefore, this work concentrates on counterbalancing the effects of R E .

B. Counterbalancing circuit

Noting that the parasitic resistor lowers the effective transconductance g m of the transistor implies a less efficient conversion of voltages into collector currents and hence of the LLRs into probabilities. From a circuit point of view, as the effective g m is lowered, it implies a gain loss of the Gilbert multiplier thus modifying its transfer function. This suggests that a gain stage would suffice to counterbalance the inaccurate conversion due to the parasitic R E . The gain K is chosen so that the overall gain of the computation node is approximately one. This gain stage is implemented as a simple differential MOS stage as presented in Fig. 12. Actually, this circuit already exists and was proposed in [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF] where it is only used as DC level shifter. The DC level shift is necessary to adjust the input biasing of the next stage. One simply needs to design the differential NMOS stage to provide the necessary DC level shift and also some gain. Thus, there is no added complexity to the circuit. The circuit presented is for two outputs but it can be extended to a larger number of outputs. To assess the efficiency of this simple correcting circuit, a behavioral model of the gain stage is done in Simulink® . The MOS differential stage is modeled as a piecewise linear model with a linear region of gain K and two saturation regions. This is added to the overall behavioral model of the decoder. The results of the simulations are presented next.

C. Simulation of the corrected APP decoder

Considering that the biasing current is evenly divided into each branch of the Gilbert multiplier, the larger the multiplier the smaller biasing current of each transistor. It implies that the effect of the parasitic R E in each branch is reduced and hence, a smaller correction is required. Thus, the correction gain K is chosen depending on the size of the multipliers. The larger the multiplier is, the smaller K is. Fig. 13 shows that the decoder performs better than the uncorrected one. The simple differential gain stage improves the error rate by 0.2dB. However, to match the ideal case, this is not enough but the effect of the parasitic resistors is only corrected to a first order. Again, considering the simplicity of the correction circuit, the improvement is nevertheless significant. In the next section are presented the simulation results of the turbo decoder.

V OU T V OU T 2 from previous stage M 1 M 2 M 3 M 4 V DD I BIAS Next stage Gilbert cell Correcting circuit I 1 I 2 I 3 I 4 I 5 I 6 V X V Y

D. Simulation of the corrected turbo decoder

The APP decoder implementing the correction circuit is now put in a turbo scheme. As shown in Fig. 14, the correction is very efficient for small SNR values, i.e. between 1dB and 2dB, as the corrected BER curve gets very close to the ideal one. However, above 2dB the correction circuit does not improve the decoding performance which remains 0.2dB away from the ideal case. Thus, the correction circuit shows its interest in the APP decoder and for the turbo decoder in the low SNR range.

It is worth noting that if the parasitic emitter resistor were fully compensated (effective R E = 0Ω), the analog turbo decoder would perform as good as the ideal decoder and its digital counterpart (8 iterations, floating point), see Fig. 15. This means that the Early and Webster effects alone do not impact the performance of the analog turbo decoder even though they account for about 20 percent of the LLR to probability conversion as shown in Section V.A. Hence, these secondary effects need not to be taken into account if the decoder is used in a turbo scheme.

VI. CONCLUSION

Relevant BJTs' parasitic elements have been identified and characterized. A high level model has been developed and it shows that BJTs' parasitic elements deteriorate the decoding performance of the APP decoder by 0.5dB for a bias current of 250µA and minimal size transistors. When the APP decoder is used in a turbo scheme, the loss is down to 0.2dB for a BER smaller than 10 -2 . A simple circuit necessary for interconnecting decoding stages can also be used to counterbalance the BJT parasitic R E . Previously used as a simple DC level shifter, it can implement a compensating gain too. Thus, there is no added complexity to the decoder while improving the performance by 0.2dB compared with the uncorrected APP decoder. In a turbo scheme applying the correction helps reducing the loss only in the lower range of the SNR. However, to match the BER of a digital counterpart, a better compensating circuit needs to be designed. This certainly requires further investigations. Normalized simulation time of the decoding of one random frame using the different models for an SNR of 4dB 6

Reviewer 1:

The explanation of how the correcting circuit is used is a bit unclear. Perhaps, a figure showing how it is connected with the rest of the decoder would help.

We added to the Fig. 12 the connection of the correcting circuit with a Gilbert cell.

The main advantage of your model is computational efficiency. Therefore, I would like to have a comparison of the simulation time for your model versus the spice-level model. It would also be interesting to compare your simulation time with important sampling approach.

In Section IV, we added paragraph D: Computational cost. This subsection compares the simulation times required to decode a frame using an ideal behavioral model, our proposed model and a spice level model (Mextram model) of a stand-alone APP decoder. A table (Table II) summarizing this was added too. We did not consider importance sampling approach to speed up simulation time. This was not our main goal, as paragraph D states. However, for further works we will most likely use it.

There are also several small typos: Typos have been corrected, hopefully non are left. A space was missing in Extrmodule : Extr module. It refers to Extrinsic module not to Extra module.

There was some work that used important sampling to improve simulation time to produce BER curves by Winstead/Schlegel.

The references [START_REF] Sadowsky | A new method for viterbi decoder simulation using importance sampling[END_REF] and [START_REF] Winstead | Importance sampling for spice-level verification of analog decoders[END_REF] have been added in the paragraph IV.D.

Shuhuan Yu did work looking at affect of mismatch in analog decoders which may also be interesting for you.

We did not find the work of Shuhuan Yu concerning the mismatch in analog decoders. We do not have access to her Ph.D Thesis which might evoke this particular aspect. We would be pleased if you could indicate us available work from her on this matter.

Reviewer 2:

Page 1 -Column 1 -Line 1(P1-C1-L1): you are writing about a "channel". I think it's better is you refer to a "communication channel". Most of the introduction has been rewritten and what was named "channel" is now termed "communication channel" as suggested.

P1-C1-L15: You use for the second time the English structure "wheter ...or...". It's better if you change this one. P1-C1-L21: "BER and FER ...simulations.". This paragraph is not too clear These paragraphs have been rephrased.

P1-C2-L23

: "These effects...performances.". The novelty in the analysis of this non-random effects is clear. Are there other random effects that can impact on decoder performance? Have you considered them? Are they minor or they need a further analysis?

Transistor mismatch has been studied in [START_REF] Lustenberger | On mismatch errors in analog-VLSI error correcting decoders[END_REF] and concludes it does not impair the decoder's performance. This was already cited in the introduction. Others random effects such as temperature (on chip gradient for instance), chip to chip process variations have not been considered in this work. This needs a further analysis for higher order model. The Mextram model provided by NXP is described by many equations [START_REF][END_REF] and [START_REF] Paasschens | Introduction to and Usage of the Bipolar Transistor Model Mextram[END_REF]. Using those equations, simulations have been run on each different effect to see its impact on the collector current. From this analysis, the three most important effects have been found. This explanation has been added to Section III.

SectionII

Reviewer 3:

The introduction is complete gibberish. Begin by telling the reader about the general area and then guide him to the particular topic. Make sure that concepts and terms are properly introduced. Most of the introduction was rewritten to take your remarks into account.

About the title: what about something like "On the influence of nonideal transistors on analog decoders"?

We think our title is more precise so we keep it.

Last two statements in the abstract: the mentioned operating points ("2dB" and "3.25dB") should be stated in terms of BER rather than dB. This has been corrected.

"BER performance" -> simply "BER"

This has been corrected.

Beginning of the Introduction: "Therefore, two solutions exist..." This is a repetition of an ancient misunderstanding. These "two solutions" are really the same circuits described in different words. This is not in the introduction anymore as it has been rewritten.

Section II.A: "The target code is..." -> e.g. "For our numerical results, we will assume a turbo code with the following parameters..."

We changed the first sentence of this section.

Section II.A: "circular" is not a standard term in coding theory. Use "tail-biting". "Circular" has been replaced with "tail-biting". Section II.A and II.B: Only the component code (a tailbiting convolutional code) is described. What about the whole turbo code?

The description of the whole turbo code has been added in Section IV.C, in particular the interleaver (Table I) was added.

Section II.A: The standard term "binary code" is seriously misused here. Fig. 1 is an ordinary [START_REF] Loeliger | Probability propagation and decoding in analog VLSI[END_REF][START_REF] Hagenauer | The analog decoder[END_REF] binary convolutional encoder; there is nothing nonbinary about it. In other words, a doubinary convolutional code (as in this paper) is a special case of a binary code, not a nonbinary code. Section II.A was partially rewritten to take that into account.

Fig. 2: Tell the reader that this is only ONE trellis (not four).

We added in the legend of Fig. 2 that the trellis is split in four sub-parts for clarity.

Section II.B. It should perhaps be mentioned that the basic modular architecture is that of [START_REF] Loeliger | Probability propagation and decoding in analog VLSI[END_REF] and [START_REF] Gaudet | A 13.3mbps 0.35µm CMOS analog turbo decoder ic with a configurable interleaver[END_REF]. Added the reference [START_REF] Lustenberger | All analog decoder for a binary (18,9,5) tail-biting trellis code[END_REF](previously [START_REF] Loeliger | Probability propagation and decoding in analog VLSI[END_REF]): "As in [START_REF] Lustenberger | All analog decoder for a binary (18,9,5) tail-biting trellis code[END_REF], each section is built from four modules...".

Section III: The term "electrical model" is not defined and requires some explanation. (Another name would be preferable, too.) I assume that this is also based on some equations? It is exact that "electrical model" is not appropriate, the exact term is "electrical compact model" as used by foundries such as NXP, textbooks on IC design. However, we understand this can be confusing and we changed the term "electrical model" into "Mextram model". This model is described by some equations [START_REF][END_REF] as now stated in the first paragraph of Section III.

How reliable is this "electrical model" in reality?

This model is provided by the foundry (NXP) and is based on test and characterization of components. This is done before releasing the design kit. Hence, it is as close to reality as possible otherwise it would not be possible to design a working circuit.

Equation ( 3): what is the relation between IC and IC*R? Equation (3) described the model collector current I * R C when considering the parasitic emitter resistor. The term I C was misused here and has been replaced by I * R C . In the same way, Equations ( 6) and ( 7) have been corrected.

Equation ( 4) requires more explanations.

The text around the equation has been modified and we hope it is clearer. We named the Early effect terms q 1 as described in [START_REF] Paasschens | Introduction to and Usage of the Bipolar Transistor Model Mextram[END_REF]. Simplification is made clearer by separating Equation ( 4) into two equations.

Section IV.B: The details of the actual turbo code seem to be missing. The description of the whole turbo code has been added in Section IV.C, in particular the interleaver (Table I) was added.

Section V.B: I do not understand the first two statements. This part has been rewritten and should be clearer.

Section V.C: More details on the "digital counterpart" are needed. (How many iterations? Full precision? What about damping?) The digital counterpart: 8 iterations, floating point precision. This has been added to Section V.C.

Reference [START_REF] Gaudet | A 13.3mbps 0.35µm CMOS analog turbo decoder ic with a configurable interleaver[END_REF] looks strange: (i) what is "ser."? (ii) no publisher; (iii) why "Ch. 4"?. This was actually a PhD thesis at ETH Zurich. This reference has been corrected.

There are also some typos in other references.

The references have been corrected.

However, all these particular points are just examples. The whole text needs to be re-thought. About the organization and the way the paper is written.

The paper starts with a description of a stand-alone APP decoder designed using BJTs. We show next that there is a problem with the way LLRs are translated into probabilities. In order to evaluate the impact of this imperfection, a behavioral model of the transistor is developed and tested for correctness versus transistor level simulation using Cadence® design software tools. Then, from it, behavioral models of a stand alone APP decoder is developed et simulated to obtain the BER. As the APP decoder performance is seriously degraded by the BJT's parasitics, we simulated a turbo scheme using the previous elementary decoder in, to check if it could overtake that degradation. As the answer is no, we studied the way to compensate this error and came up with a simple solution that does improve the BER as our simulations show (even though it is not perfect). We think this is a valid way of presenting our work. However, some sections were not well written and organized. They have been rewritten: Introduction, II.D, III first paragraph, III.A, III.E, IV.A, V.B, V.C., Section V.A has been split into Section V.A: Most relevant effect and V.B: Counterbalancing circuit.

Reviewer 4:

There should be many more citations, particularly on behavioral simulations and alternative architectures. Many citations have been added (20 references for the first version of the paper vs 31 for the revised version). For instance, the references [START_REF] Hemati | Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes[END_REF] and [START_REF] Hagenauer | The analog decoder[END_REF] have been added in the introduction concerning the behavioral simulations and the references [START_REF] Amat | Reconfigurable analog decoder for a serially concatenated convolutional code[END_REF] and [START_REF] Arzel | Semiiterative analog turbo decoding[END_REF] for alternative architectures.

The "extended Gilbert cell" topology has been used in a number of analog decoders. Authors should note this and add citations. Section II.C now clearly state that and references [START_REF] Lustenberger | On the design of analog iterative VLSI decoders[END_REF] and [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF] have been added.

Authors need to explain more about their simulation methods (see below), and should add related citations where appropriate. The Section III. has been partially rewritten to explain more how the three effects have been selected. Information has been added in section IV. concerning the Simulink® model.

The paper addresses physical effects for a particular BiCMOS process. Are the paper's results expected typical of other current BiCMOS processes?

This BiCMOS process is a typical process. If another process is used, the values of R E , V AR , I K and the simplifications should be adapted of course but the results should similar. These explanations have been added in Section IV.A.

The primary text should state that the Mextram model is used in simulations, and identify the model's version number.

We added in Section II.D that the Mextram model is used in simulations and the version number (504).

What simulation method is used to evaluate the model equations given in ( 3)-( 6)? Equations ( 3)-( 7) are simply solved. The I C current is calculated by the Mextram model by Spectre® simulator. The ratio I C /I * C is simply plotted in Fig. 7 to asses the precision of each model.

What is the "forward current", I F , mentioned in Sec. III-D? How is it evaluated in the simulations? I F is the ideal forward current of the transistor described in [START_REF][END_REF]. In the forward active region, I Under what conditions can the secondary effects be minimized? Is it possible to bring the circuit closer to the ideal model by, for example, altering the bias current or the transistor dimensions? As stated in section V.A, we do not want to change the transistor dimension nor the bias current for cost and speed reasons.

Because the Reverse Early and the Webster effects are negligible in a Turbo decoder (see Fig. 15), we did not investigate further on how the secondary effects can be minimized.

What simulation procedure is used to obtain the BER results? Did the authors use, say, forward-Euler simulation with a fixed frame time-interval for decoding?

The solver used for decoding is a high order solver : Runge-Kutta ODE solver with variable time-steps. This has been added in section IV.B.

BER simulations are not very thorough. Is it possible to at least reach 10 -5 with the proposed behavioral model?

The simulation time takes about 2 weeks for a BER of 10 -4 so it would take about 20 weeks to reach 10 -5 . The simulation time could be reduced using the importance sampling approach [30] [31]. However, this work concentrates on the model accuracy and not on the simulation time, so importance sampling was not considered.

The paper should document the computational cost of using the behavioral model in place of the ideal model. For example, the paper could compare the measured simulation time needed to evaluate one forward-Euler iteration using the ideal model, vs the proposed model [START_REF] Dai | Design methodology for analog VLSI implementations of error control decoders[END_REF], vs the approximate model [START_REF] Hemati | Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes[END_REF]. We added the Section IV.D: Computational cost. This section compares the decoding simulation time of the ideal model vs the proposed model ( 13) vs the Mextram model. No this means "Analog decoder with parasitic R E = 0Ω". This has been rephrased in Fig. 15.

The introduction should speak to a broad audience. Say something like, "Many communication channels are modeled by AWGN. In an AWGN channel, the demodulated channel output is proportional to the log-likelihood ratio (LLR) of the corresponding emitted symbol [maybe cite some tutorial paper or book]." "Therefore" is misused in the second sentence. Probability propagation should be defined and identified as a major focus of the paper, with citations to fundamental references. The introduction has been partially rewritten.

The discussion in Sec. III-E is overly verbose. Most of the details are immediately obvious from Fig. 7.

The second paragraph has been nearly entirely removed.

You cannot "prove" that the simplifications are "acceptable" (Sec. IV-B) unless there is a quantifiable standard of acceptability. Should reword this.

Absolutely. This has been reworded.

This statement (Sec. V) is too strong: "The only parasitic that can be counterbalanced by design is the parasitic emitter resistor." Instead, try saying "The parasitic emitter resistor can be counterbalanced by design," or "There are few design options for counterbalancing parasitic effects." This sentence has been rephrased: "The parasitic emitter resistor could be counterbalanced by modifying either the size of the BJTs or the bias current.".

The first paragraph of Sec. V-A is very confusing. Please revise this section carefully.

This paragraph has been partially rewritten.

I think "Turbo" is usually capitalized in "Turbo codes" and "Turbo decoder". I could be mistaken. It seems you are mistaken. For example, in this paper: "Turbo codes with rate-m/(m+1) constituent convolutional codes" by Douillard, C. and Berrou, C.

Fig. 1 .Fig. 2 .

 12 Fig. 1. Double-binary encoder, code rate 2/3.

Fig. 5 .

 5 Fig. 5. Emitter-coupled pair.

Fig. 6 .

 6 Fig. 6. Probability ratio transfer function, i.e. I C2 /I C1 vs exp( V IN V T

)

  Fig. 8. Ratio ( I C2 I C1 )/( I * C2 I * C1

E

  Fig. 9. Behavioral simulation of the analog APP decoder considering the computing cells ideal and affected by BJTs' parasitic elements, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V .

Fig. 10 .

 10 Fig. 10. Behavioral simulation of the analog turbo decoder considering the computing cells ideal and affected by BJTs' parasitic elements, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V .

Fig. 11 .

 11 Fig. 11. Probability ratio transfer functions of a minimal size emitter-coupled pair. Solid line: ideal case; dashed line Effective parasitic R E = 0Ω; dotted line: Effective parasitic R E = 220Ω . I BIAS = 250µA, V DD = 2.8V (transistor level simulation).

Fig. 12 .

 12 Fig. 12. Correcting and interconnecting circuit.

EFig. 13 . 5 EFig. 14 .

 13514 Fig. 13. Behavioral simulation of the analog APP decoder considering the computing cells ideal, affected by BJTs' parasitic elements and counterbalanced, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V .

5 EFig. 15 .

 515 Fig.[START_REF] Winstead | CMOS analog MAP decoder for (8,4) hamming code[END_REF]. Behavioral simulation of the analog turbo decoder considering the computing cells perfect, affected by BJTs' parasitic elements, with BJTs emitter resistor fully compensated compared to a digital turbo decoder with 8 iterations, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V .

7 ) 9

 79 ) of a minimal size emitter-coupled bipolar pair: ideal and simulated (transistor level), I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ratio of I C , the collector current obtained from spice-level simulation, over I * C , the collector current yielded by the various behavioral models, versus V BE (V BC = 0V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . versus V IN for an emitter-coupled pair of minimal size transistors. I C2 /I C1 and I * C2 /I * C1 are obtained from spice-level simulation and behavioral models respectively. I BIAS = 250µA, V DD = 2.8V . . . . 5 Behavioral simulation of the analog APP decoder considering the computing cells ideal and affected by BJTs' parasitic elements, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . . . . . . . 6 10 Behavioral simulation of the analog turbo decoder considering the computing cells ideal and affected by BJTs' parasitic elements, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . . . . . . . 6 11 Probability ratio transfer functions of a minimal size emitter-coupled pair. Solid line: ideal case; dashed line Effective parasitic R E = 0Ω; dotted line: Effective parasitic R E = 220Ω . I BIAS = 250µA, V DD = 2.8V (transistor level simulation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Correcting and interconnecting circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Behavioral simulation of the analog APP decoder considering the computing cells ideal, affected by BJTs' parasitic elements and counterbalanced, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . 8 14 Behavioral simulation of the analog turbo decoder considering the computing cells ideal, affected by BJTs' parasitic elements and counterbalanced, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . 8 15 Behavioral simulation of the analog turbo decoder considering the computing cells perfect, affected by BJTs' parasitic elements, with BJTs emitter resistor fully compensated compared to a digital turbo decoder with 8 iterations, frame length 48 information bits, I BIAS = 250µA, V DD = 2.8V . . . . . . . . . . . . . . . . . . . . . 8 LIST OF TABLES I Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 II

  F = I S exp VBE VT exp -RE IC VT . This has been been added in Section III.D.

Fig. 15

 15 Fig.[START_REF] Winstead | CMOS analog MAP decoder for (8,4) hamming code[END_REF] is confusing: Does "Analog turbo decoder without parasitic REs" mean the same thing as "Analog turbo decoder with compensation circuit"? No this means "Analog decoder with parasitic R E = 0Ω". This has been rephrased in Fig.15.

1

  Double-binary encoder, code rate 2/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Trellis associated with the encoder of Fig. 1 (split in four sub-parts for clarity). Branches are labeled with the encoded symbol X 1 X 2 Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Tail-biting APP decoder structure and decoding section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Extended Gilbert cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Emitter-coupled pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Probability ratio transfer function, i.e. I C2 /I C1 vs exp( VIN VT

  Paragraph II.D has been rewritten. As stated by the last sentence of paragraph C, paragraph D analyzed the conversion error of LLR into probabilities. It also now clearly states that it takes into account all the parasitic effects present in the transistor electrical model (Mextram 504). A ratio of 100 (exp(V IN /V T ) = 100) corresponds to V IN ≈ 120mV , V IN = 0 is for a ratio of 1.

	-Par.D
	I haven't completely understood what is error analyzed in this section. When I have an Input probability ratio of 100, is Vin
	=0? And if this is true, how is possible that Ic2/Ic1 in the real simulation results about 15?
	Section III
	P3-C2-L8: "among...current". It's not clear if you have considered the three effects like the most important directly from a
	literature analysis or if you have selected after a experimental work.


Cyril Lahuec
email: cyril.lahuec@telecom.bretagne.eu

Matthieu Arzel
email: matthieu.arzel@telecom.bretagne.eu

Manuel Gouriou
email: manuel.gouriou@telecom.bretagne.eu

Franc ¸ois Gallée
email: francois.gallee@telecom.bretagne.eu

A ligament laxity telemetry system architecture for a knee replacement prosthesis

In this paper the feasibility of a novel instrumented orthopaedic implant for total knee replacement is studied. The system aims at providing an indication on the balance of the lateral ligaments. The measures will be used to estimate the wear out of the polyethylene part of the prosthesis and will also facilitate the patient rehab. The data will be transmitted outside the body through an RF link. Unlike other instrumented implants, the system will be self-powered. Piezo ceramics will be used both as pressure sensors and as power generators. This implies that the measurement system must be ultra low power as the available power is less than 1.8mW. First simulation results are given for a 0.35µm CMOS process.

I. INTRODUCTION

Total knee arthroplasty (TKA) is used to replace a damaged knee joint with metallic parts fixed or impacted over the bones and separated by a polyethylene part. The causes of damage are wide but the most common is osteoarthritis. During surgery any defect must be corrected to insure a proper functioning of the implant. In particular the collateral ligaments must be balanced in order to insure proper knee movements and stability. Imbalanced ligaments cause an early wear of the polyethylene part and could, in the end, cause the loosening of the tibial tray. Unfortunately, the skill of the surgeon is not enough to insure a perfect balance. In order to avoid injury due to a loosening of the implant, it seems interesting to be able to predict the lifespan of the prosthesis by measuring the forces applied onto the tibial tray. In-vivo force measurements have been shown to be possible [START_REF] Taylor | An instrumented prosthesis for knee joint force measurement in vivo[END_REF] [START_REF] Graichen | Implantable 9channel telemetry system for in vivo load measurements with orthopedic implants[END_REF]. These systems use strain gauges. The systems only measure and output the magnitude of the axial force applied. They do not provide any clue about the polyethylene wear. Most of the published smart orthopaedic implants use power hungry offthe-shelf components; they are hence powered by cumbersome inductive coil. The dimension of the coils used in such systems depends on the application, the losses are also important due to the presence of large metallic parts [START_REF] Graichen | Implantable 9channel telemetry system for in vivo load measurements with orthopedic implants[END_REF]. This paper presents a possible architecture of a self-powered telemetry system performing in-vivo interpretation of the measured forces to estimate the balance of the lateral ligaments. Then, from polyethylene wear data from implant manufacturers it will be possible to estimate the life expectancy of the prosthesis. Although some of the blocks in the architecture have not yet been fully evaluated, it is still possible to estimate the feasibility of such a system. The paper is organized as follows. Part II describes the sensor

Piezo ceramics Stem

II. KNEE PROSTHETIC PROTOTYPE

A. Piezo ceramics

The voltage across a piezo ceramic when mechanically stressed is proportional to the force applied. Hence, they can be used both as force sensor and as energy generator as proposed in [START_REF] Gouriou | Predictive autonomous orthopaedic device[END_REF]. The huge force applied onto the tibia, up to four times the person weight [START_REF]parameters for wear-testing machines with load control and corresponding environmental conditions for test[END_REF], can be used to harvest enough energy to power the telemetry system. In [START_REF] Platt | The use of piezoelectric ceramics for electric power generation within orthopedic implants[END_REF], three piezo ceramics were used to yield 2mW, enough to power a microcontroller. Platt was not concerned with measuring forces but with generating power, so the piezos were placed near the center of the tray. To obtain the axial force distribution over the tibial tray in both the medio-lateral (M-L) and the antero-posterior (A-P) directions, the tray is divided in four areas in which a piezo ceramic is placed, Fig. 1. One pair of piezo ceramics is located in the internal compartment (piezo ceramics 1 and 3) and the other in the external compartment (piezos 2 and 4). The prime concern of this work was to obtain a suitable metric to estimate the polyethylene wear out. Moreover, it was not wished to drastically modified the design of the tray as Platt did. Hence the choice of 10mm×10mm×4mm SCMA P09 so that they can be embedded into a normal 5mm-thick tray although they would generate less than 2mW.

B. Measurements

The prototype was fitted onto a MTS 858 MINI BIONIX I knee simulator both to estimate the amount energy that could be harvested and to find a metric suitable to estimate the ligaments laxity from the force measurements. Figure 2 shows the four output voltages representing the forces applied onto the piezo ceramics when the knee is balanced and for a 88kg person. Based on these signals, the average power generated over a walking cycle has a maximum value of 0.36mW on a 35kΩ resistor. With 7mm×7mm×8mm piezos, the proposed

III. USEFUL METRIC A. Medial offset and center of pressure

In a balanced knee, the internal condyle of the femur applies more efforts on the tibial tray than the external condyle. This corresponds to a medial offset (MO) in the application of the axial force of 0.07×W from the tibia axis [START_REF]parameters for wear-testing machines with load control and corresponding environmental conditions for test[END_REF], W the width of the tray. In the present case W =69mm, which corresponds to a MO of 4.83mm. What the surgeon is interested in is to estimate the life expectancy of the implant, is the actual shift from the ideal MO due to inaccurate implant fitting causing ligament imbalance. Any ligament imbalance modifies the MO and hence the axial force distribution on the tibial tray. The four data provided by the piezo ceramics can be combined into a single one by calculating the barycenter of the forces measured at each piezo ceramic. The barycenter, or center of pressure (COP), indicates on which part of the tray the axial force is mostly applied. The COP is thus the sum of the voltages weighted by the physical center of each piezo taking the center of the stem as origin.

B. Computing the center of pressure

The coordinates of the barycenter are given by the mediolateral (M-L) COP x and the antero-posterior (A-P) COP y displacements described by ( 1) and (2), respectively.

COP x = V 1 X piez1 + V 2 X piez2 + V 3 X piez3 + V 4 X piez4 4 i=1 V i (1)
COP y = V 1 Y piez1 + V 2 Y piez2 + V 3 Y piez3 + V 4 Y piez4 4 i=1 V i (2)
where V i is the average voltage over one walking cycle recorded at piezo number i, X piezi and Y piezi are the coordinates of the center of piezo i which are given in Table I.

When the knee is perfectly balanced, i.e. for an offset of 4.83mm the axial force is evenly distributed on the tray, the coordinates of the center of pressure are COP balanced x =0mm and COP balanced y =-2.25mm. Then the offset is changed from 0 to 5.5mm to shift the axial force application axis to simulate the ligament imbalance and the average COP is computed. This is represented in Fig. 3. The case for which the MO is 0mm never happens in practice but is given for reference.

C. Simplification

Although the required calculations to perform are relatively simple, for the sake of power it is worth trying to simplify them. The data collected allow for medio-lateral (M-L) and antero-posterior (A-P) displacement of the COP. These data are plotted in Fig. 4 and Fig. 5, for the average M-L and A-P displacements respectively. From these figures, the relation between the COP and the MO is almost linear. Hence, knowing the COP, it is possible to obtain the corresponding MO by linear fit. Only the M-L displacement could be used since it has a larger dynamic than the A-P displacement. It is thus easier to discriminate the medial offsets from one another using a simple linear fit. Therefore, the processing unit will only implement [START_REF] Taylor | An instrumented prosthesis for knee joint force measurement in vivo[END_REF]. IV. PROCESSING UNIT Considering the low average power available it is necessary to design a dedicated circuit. It should include the required analog interface functions, i.e. analog-to-digital converter and a transceiver as well as the digital data processing core. Since it is expected that most of the power will be used by the transmission link, a careful design of the processing unit is required to insure that the data conversion and the core consume the least power possible. The general architecture is shown in Fig. 6. At this stage of the project, the system will only output the value of COP x , the calculation of the corresponding MO is done on the medical staff's computer.

A. Supervisor core

The supervisor core is basically a 4-state machine scheduling the rest of the circuit. The supervisor block generates all the control signals for each part and, if need be, switches on or off the different parts of the measuring system. Although static leakage current is of no concern for the technology used [START_REF] Panic | Power gating in wireless sensor networks[END_REF], power gating could be used to redirect all the available power to one part of the system at a specific time, to the transceiver when emitting the data for instance. This might not be necessary if the system is designed for ultra low power consumption as power gating introduces a lot of noise in the system and might require a specific wake-up schedule [START_REF] Lee | Performance and wake-up schedule optimization of power gating design[END_REF]. This block must be on all the time. Clk

N clock cycles Convert V piez1 N clock cycles Convert V piez2 N clock cycles Convert V piez3 N clock cycles Convert V piez4 4 x N +2 clock cycles Sample V piez1 S 1 S 2 S 3 S 4 SAR enable Sample V piez2 Sample V piez3 Sample V piez4
Fig. 8. Simplified Sample-and-Hold block with corresponding timing diagram.

B. Analog to digital converter

The chosen architecture for the analog-to-digital converter is a successive approximation register (SAR) as it is the most efficient in terms of power consumption, few µW for rates up to 500kS/s, [START_REF] Roy | A 0.9v l00nw rail-to-rail sar adc for biomedical applications[END_REF]- [START_REF] Verma | An ultra low energy 12-bit rateresolution scalable sar adc for wireless sensor nodes[END_REF]. The block diagram of the ADC is given in Fig. 7, its functioning is briefly explained. The value V in to convert is sampled and held. The MSB of the Nbit SAR, D N -1 , is initialized at 1 and all the other bits at 0. This digital word corresponds to V ref /2, which is fed to the non-inverting input of the comparator through a digitalto-analog converter and compared to the sampled voltage. If

V in < V ref /2, then D N -1 is reset, the next bit, D N -2
, is set to 1 and the remaining bits stay at 0. If V in > V ref /2, then D N -1 remains at 1, D N -2 is set to 1 and the remaining bits stay at 0. The search continues until each bit in the SAR has been tested. Hence, it takes N clock cycles to perform a conversion. The DAC is implemented as a binary-weighted capacitor array that uses a unit capacitor C. To reduce on chip area and power consumption, a single ADC is used so that the four signals are sampled and converted in turns. The S/H block and its timing diagram are given in Fig. 8. Half a cycle is used to sample each piezo voltage, the next N clock cycles are used to convert the value into a digital word. An overall of 4×N+2 clock cycles is thus necessary to encode the four piezo voltages, a period of time during which the SAR ADC is enabled. Ideally, the four piezo signals should be sampled at the same time. Reducing the conversion time of the ADC for the four samples to a small fraction, one tenth for instance, of the sampling period helps approaching the ideal case. This helps reducing the energy consumption.

C. Computing core

The digital core computes the barycenter as described in section from which it is then possible to know the offset from the ideal position. The block diagram of the digital is shown in Fig. 9. The digital core is divided into three parts. The first part computes the average voltage over one walking cycle for each piezo using an adder-accumulator. The average value is obtained by dividing the cumulated sum by the number of samples N S . To simplify the design, N S is a power of 2. Only shifts are then necessary to obtain the average. This part of the circuit needs to run after each conversion, so four times during the 4 × N + 2 clock cycles and this N S times per walking cycle. The first part of the digital core runs thus at 4 × N S in the example taken. The average voltages V i are then transfered to the second and third blocks to compute in parallel the numerator and the denominator, respectively, of (1). The denominator of ( 1) is simply obtained through a tabulated inverse. The partial results are then multiplied to produce the average M-L displacement COP x , which value is stored in a memory. This part only runs once per walking cycle. The number of bits required for each step, i.e. N , n, m, t and d in Fig. 9 is optimised through behavioral simulations in order to reduce the power consumption.

D. Transmitter

This block reads out the result memory from the computing core module and transmits outside the patient's body. The transmitter must comply with standard ETSI 301-839 for Medical Implant Communication Systems. The allowed frequency band is 402MHz -405MHz with a maximum effective radiated power to 25µW [START_REF]Electromagnetic compatibility and radio spectrum matters (erm);radio equipment in the frequency range 402 mhz to 405[END_REF]. Some architectures for such block have been proposed for this standard, but they are not suitable considering the available power budget [START_REF] Bradley | An ultra low power, high performance medical implant communication system (mics) transceiver for implantable devices[END_REF]. A much simpler architecture is thus chosen, Fig. 10. The design of this block requires to take into account several parameters. First, the various human tissues with high permittivity (bones, muscles, fat, skin) do not help with RF transmission. Placed in a similar environment, planar inverted-F antennas (PIFA) have been shown to be smaller and have a higher radiation efficiency than other types of antennas [START_REF] Kim | Implanted antennas inside a human body: simulations, designs, and characterizations[END_REF]. Second, the antenna should be designed taking the metallic nature of the implant. Third, a power efficient modulation scheme, such as Binary Phase Shift Keying should be used. All these will relax the PA design. Finally, the PA and antenna will also constraint the sensitivity of the receiver frond-end. It is not planned yet to receive data, such as configuration bits, from the outside. If a transceiver is required, a simple receiver architecture, such as heterodyne architecture, should be implemented, as shown in grey in Fig. 10.

E. Carrier and clock generator

Besides the supervisor core the carrier and clock generator needs also to be on all the time to avoid transient in the oscillating frequency after switching on the oscillator. This block must thus be well thought to consume the least power. Two signals must be generated, one for the transmitter at 402MHz and the other at a much lower frequency, in the kHz range to clock the computing core. Due to the large frequency ratio it might be interesting for power reasons to implement a second low power low frequency oscillator.

V. SIMULATION RESULTS

At this stage of the work only the ADC and the computing core have been simulated. The accuracy of the system depends on the number of bits in the ADC and on the implementation of the computing core. The calculations done to produce Fig. 4 are used as a reference, they correspond to a floating point representation. The computing core will implement a fixed point representation which implies trade-off between accuracy and complexity. A behavioral C model is used for that purpose. Referring back to Fig. 9, the number of samples is chosen to be N S =128. The number of conversion bits N directly affects the rest of the circuit. Simulations shows that a 6-bit ADC is enough, hence the total number of bits required at the output of ADD 1 is 16, considering that 128 values are added per piezo. However, the MSB can be removed as the average value of the samples will never reach half the maximal value, i.e. n=9. This leads to the removal of a half-adder in the ADD 1 block and a flip-flop in registers REG piez2 to REG piez4 . Next, the number of bits going from the Average block to the Denominator and N umerator blocks is reduced by noticing that the average force value per piezo changes significantly only when in the vicinity of the balanced point. Hence, only the six MSB (t=6) can be kept without affecting the result. Following the same procedure, the data format through out the computing core are obtained and are listed in Table II. The computed medial offset using this system is compared to the one computed using the floating point representation versus the actual medial offset in Fig. 11. Despite simplifying the system a lot, there is still a good agreement between the two.

VI. POWER CONSUMPTION

A 0.35-µm CMOS technology from AMS is chosen to design the ASIC with a supply voltage of 1.3V. From the design kit it is possible to accurately estimate the power consumption of the digital parts to about 0.003mW. From the discussion on the ADC, the power consumption of the ADC is at most 1µW when working. The ADC clock period is 33kHz, choosing N S =128. Hence, the worst case power consumption of the digital core is estimated to 0.003mW. Building the 402MHz carrier and the 33kHz clock from a single 402MHz oscillator, which should not consume more than 100µW [START_REF] Rashdan | Ultra low power transceiver for wireless patient vital sign monitoring[END_REF], implies a large and fast frequency divider. This divider would consume more than a second harmonic oscillator consuming about 100µW [START_REF] Fan | On-chip real time clock oscillator without quartz cristal[END_REF]. Therefore, two oscillators will be used. This is not a problem since there is no synchronisation requirement between the acquisition/computing part and the transmitting part. Table III gives the estimated power consumption of each block and what is left for the transmitter if everything on at the same time (which will not be the case), at most 1.6mW. Considering a seven percent power amplifier efficiency, an isotropic antenna with a one percent radiation efficiency and a 30cm free-space link as in [START_REF] Kim | Implanted antennas inside a human body: simulations, designs, and characterizations[END_REF] then the exterior reading device sensitivity of the receiver, using a simple dipole antenna, should be below -41dBm to achieve a reliable link. Most RF receivers in the 300 to 900MHz range achieve input sensitivity below -90dBm such as the AMIS-53000 transceiver chip for medical application from ON Semiconductor [START_REF] On-Semiconductor | Amis-530xx frequency agile transceiver etsi test report[END_REF]. Hence the received signal level is well above what can be achieved by commercial receivers.

VII. CONCLUSION

This paper has presented a possible ASIC architecture for measuring the line of application of the axial force medial offset from force measurements on the tibial tray. As the simulation of the computing shows, despite many simplifications, it is possible to match the measurements. As expected the most difficult part to define is the transceiver. It cannot be designed without designing also the exterior receiving device, a system level approach is necessary. Moreover, the implanted antenna has to be designed taking the nearby metallic tibial tray into account. However, the proposed telemetry system can be done. The 1.6mW left for the transmitter allows for implementing the linear fit on-chip and output the MO directly. Also, a full transceiver could be implemented.

Fig. 1 .

 1 Fig. 1. Tibial tray prototype fitted with four piezo ceramics SCMA P09 of dimensions 10mm×10mm×4mm. Piezo ceramics 1 and 3 internal compartment, piezo ceramics 2 and 4 external compartment.

Fig. 2 .

 2 Fig. 2. Measured voltages representing forces over one walking cycle on a 10kΩ resistor, balanced prosthesis, person weight 88kg.

Fig. 3 .

 3 Fig. 3. Displacement of the center of pressure (COP) for various medial offsets (MO). The point (0,0) represents the center of the stem. The position of the COP for the ideal MO=4.83mm is represented with a diamond.

Fig. 4 .

 4 Fig. 4. Average M-L displacement of the center of pressure (COP) for various medial offsets (MO).

Fig. 5 .

 5 Fig. 5. Average A-P displacement of the center of pressure (COP) for various medial offsets (MO).

Fig. 6 .Fig. 7 .

 67 Fig. 6. Block diagram of the ligament balance measuring system.

Fig. 9 .Fig. 10 .

 910 Fig. 9. Digital core computing the average M-L displacement COPx.

Fig. 11 .

 11 Fig. 11. Comparison between the computed medial offsets using floating point (corresponding to Fig.4) and fixed point logic versus the actual medial offset.

TABLE I PIEZO

 I CERAMICS CENTER WITH RESPECT TO THE CENTER OF THE STEM (IN MM)

	Piezo ceramic i	X piez	Y piez
	1	-22.25	-13.25
	2	22.25	-13.25
	3	-17.25	8.75
	4	17.25	8.75
	method yields 1.8mW at the expense of thicker tray, 9mm
	instead of 5mm.

TABLE III POWER

 III LEFT FOR TRANSMITTER TO ESTIMATE RECEIVER SENSITIVITY.

	Available power (mW)	+1.81
	Consumed power (mW)
	SAR	-1E-3
	Digital core (computing + supervisor)	-3E-3
	Oscillator 1 (402MHz ring)	-0.1
	Oscillator 2 (33kHz harmo.)	-0.1
	Power left for transmitter (mW)	+1.6