Ali C Basaran
email: abasaran@physics.ucsd.edu

Javier E Villegas
email: javier.villegas@cnrs-thales.fr

J S Jiang
email: jiang@anl.gov

Axel Hoffmann
email: hoffmann@anl.gov

Ivan K Schuller
email: ischuller@ucsd.edu

Mesoscopic magnetism and superconductivity

la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Introduction

Magnetism and superconductivity provide excellent foundations for the development of novel ideas in materials physics and serve as examples for new mesoscopic science. Magnetic and superconducting (S) materials have a very interesting admixture of short and long length scales. The short, nanoscale (atomic, <1 nm) length scales, govern the ordering into specific crystalline structures and produce complex atomic-scale electronic interactions. It is probably safe to state that the appearance of superconductivity and magnetism in specific materials systems is often not well understood, and predicting specific, characteristic parameters such as the ordering temperatures, is even harder.

Typical length scales that govern the appearance of superconductivity are given by the atomic arrangements of elements within a unit cell or the exchange length in a magnetic material. On the other hand, many superconducting and magnetic phenomena are governed by longer, mesoscopic (often 10 to 1000 times longer than interatomic distances) length scales. At these scales, there are well-defined predictions in agreement with experimental observations. Typical long length scales that appear in superconductivity are the coherence length and penetration depth and in magnetic materials are the dipolar and Ruderman-Kittel-Kasuya-Yosida length scales, all of which are longer than interatomic distances and independent of detailed atomic arrangements. [ref] Many unique physical properties can be engineered into mesoscale artificial structures without the need for ultimate atomic perfection. In this article, we describe several general mesoscopic phenomena and illustrate them with an example from superconductivity or magnetism. Possible phenomena at mesoscopic length scales are categorized as topological, which depend on sample geometries; confinement, which are controlled by physical boundary conditions; proximity, in which close physical contact between dissimilar materials produces new effects; crossover, which is across different dimensions; and collective effects, which depend on some form of periodicity. Although we illustrate some of these phenomena in the fields of superconductivity and magnetism, the general concepts go beyond and can be extended to other physical phenomena such as ferroelectricity, elasticity, optics, and transport. Here, we specifically exclude phenomena that depend on detailed atomic arrangements, such as the appearance of superconductivity and magnetism at interfaces due to subtle atomic arrangements or bonding.

Figure 1 shows a comparison of length scales and structural characterization techniques. 1 It is important to note that at the nanoscale (<1 nm), structural characterization techniques have difficulties in providing high-accuracy quantitative structural or chemical information. Whereas at longer, mesoscopic (>1 nm) length scales, there are many structural and chemical tools that provide quantitative measurements. Thus, at the mesoscale, structural and chemical issues are much less severe and hamper less pertinent to the understanding of the origin of unusual phenomena encountered.

Long magnetic and superconducting length scales have been known to produce mesoscopic phenomena as described in this article, see e.g., Table I. The full complexity and current research opportunities of mesoscale phenomena in magnetism 2 can be illustrated by the behavior of spin waves ("magnons") in magnetic films. These fundamental excitations are due to the precession of the electron spin around an effective magnetic field, which may include internal fields, such as anisotropy fields, as well as externally applied fields. Besides the interaction with the effective magnetic field, the energy of the collective excitation is determined by the mutual interactions between spins, which includes short-scale exchange interactions, and mesoscopic-scale dipolar interactions.

These dipolar interactions may stabilize inhomogeneous magnetic structures, since the energy gain from minimizing dipolar interactions may exceed the energy loss from exchange energies, which favor homogenous magnetic structures. Thus, by changing the magnon wavelength, it is possible to investigate the transition in the dynamics dominated by dipolar interactions (long wavelengths) to a regime dominated by exchange (short wavelengths).

Unique manifestations of mesoscopic physics can appear when long-range quantum coherent states, such as superconductivity, exist. The long superconducting coherence length produces unusual phenomena such as the well-known proximity effect in which a normal material may become superconducting by proximity to a superconductor. As a consequence, unique phenomena appear, such as the Josephson Effect, flow of electric current without any voltage applied in mesoscopic superconducting-normal-superconducting structures, and quantum coherent states in normal materials (Bohm-Aharonov effect) may be enhanced.

Topology

In many solid-state systems, interactions across different length scales are often responsible for developing or stabilizing states with distinct topologies. There are many examples of the formation of topological phases in superconductivity and magnetism, both artificially and naturally produced. These include systems such as magnetic and superconducting vortices, skyrmions, vortex arrays, Majorana fermions, and topological superconductors. The interaction with artificially structured materials in unusual topologies produce unique physics beyond what is found in naturally occurring systems.

Magnetic skyrmions

In magnetic systems, a wide variety of magnetic structures with distinct topology exist, which can exhibit quasiparticle-like behavior. 18 Well-studied examples are magnetic vortices, 13,14 stabilized by long-range dipolar interactions that exhibit collective motion governed by the dynamics of the individual spins forming the vortex. 19,20 Recently, magnetic skyrmions 21 have garnered increasing interest. These are topologically distinct spin structures, in which the spins point in all three-dimensional directions, as is schematically shown in Figure 2a. Magnetic skyrmions were discovered 21 in bulk materials with chiral Dzyaloshinskii-Moriya interactions (DMI), which is an antisymmetric exchange interaction given by the vector cross product of two neighboring spins. At temperatures close to the magnetic ordering temperature and moderately high magnetic fields, the competition between the DMI (favoring a helical magnetic structure) and direct interactions with externally applied magnetic fields (favoring a preferred magnetization direction) results in a compromise, where tubes of magnetization form that are aligned antiparallel to that of the surrounding matrix. Unlike magnetic vortices, which occur in geometrically confined structures, magnetic skyrmions can form in extended bulk materials. Often, they form a well-defined hexagonal lattice similar to vortex-lattices in superconductors. Just like superconducting vortices, skyrmions in magnetic systems are mobile and can be moved with very small electric currents. 22,23 The efficient manipulation of skyrmions with small electric currents has two origins. First, electrons that move in a skyrmion spin texture experience a virtual magnetic field (exceeding 100 T for skyrmions with diameters in the 10 nm range and below) that results in their transverse deflection and gives rise to the topological Hall effect. 23,24 At the same time, a back-action results in motion of the skyrmions. The second aspect that facilitates skyrmion motion is decreased pinning due to their compact structure, which allows them to move around defects. Since skyrmions can be small (few nm) and easily manipulated electrically, they are potentially useful for information technologies. 25 To realize the ambitious goal of utilizing magnetic skyrmions for information technologies, efficient generation and annihilation of individual skyrmions on demand is needed. For instance, in thin FePd on Ir(111), skyrmions can be generated and annihilated via spin-polarized currents at cryogenic temperatures (8 K). 16 For practical applications, however, generation of skyrmions at room temperature and demonstration of high mobility is needed. This has recently been demonstrated in Ta/CoFeB/TaOx multilayers, as shown in Figure 2b. 15 The perpendicular anisotropy in this material results in extended magnetic band domains, as seen on the left-hand side of Figure 2b. At the same time, a heavy element (e.g., Ta) layer in combination with a thin ferromagnetic (FM) layer with perpendicular anisotropy may stabilize domain walls with welldefined chirality due to interfacial DMI. 26,27 These can be very efficiently moved due to the spin Hall effect. 28 In the device shown in Figure 2b, this electric current-driven domain-wall motion is used to push the band domain through the constriction. Upon exiting from the constriction, the band domain expands laterally due to laterally inhomogeneous spin transfer torque giving rise to an instability, generating individual skyrmion bubbles [see Figure 2c]. This mechanism is similar to Rayleigh-Plateau instabilities in surfacetension-dominated fluid flows, which result in droplet formation, i.e., for a dripping water faucet. 29 Interestingly, the critical electrical current for the motion of these synthetically produced skyrmions is two orders of magnitude smaller than for regular domain wall motion, indicating that indeed the peculiar structure of skyrmions results in significantly decreased pinning. 15

Superconducting ratchets

Superconducting vortices interacting with artificial pinning arrays have attracted attention for over two decades 30,31 and yielded unique phenomena such as vortex ratchets. In a superconducting ratchet, a periodic alternating current is rectified giving rise to a DC voltage. The topology that produces this effect consists of a superconducting (Nb, for instance) film on top of a rectangular array of triangular pinning sites, as shown in Figure 3. 32 Upon depinning under a symmetric AC driving current, vortices acquire a net velocity that depends on their number (i.e., on the perpendicular applied magnetic field). Up to three vortices per unit cell of the array are trapped in the triangles and acquire a net velocity in the same direction (red arrows) when depinned [see Figs. 3(a) and (b)]. For higher-vortex densities, the excess vortices become interstitial (blue), and "feel" the opposite asymmetry via their interaction with the (red) pinned vortices [see Figs. 3(c) and(d)]. Under an AC driving force, interstitials depin first and acquire a net velocity opposite (blue arrow) to the pinned ones (red). The reversed rectification holds until a sufficiently intense drive depins vortices trapped by triangles, producing positive rectification. Thus, the system behaves as a very unique electrical rectifier, in which an injected AC current leads to a DC voltage whose sign depends on the applied magnetic field and the magnitude of current.

Over the past decade, vortex ratchets have been profusely studied, (e.g., seeking new types of asymmetric pinning [nonuniform arrays, constrictions, surface barriers], high-frequency effects). 33,34 Recent developments in the area, including reconfigurable energy landscapes, 35,36 vortex manipulation through magnetic force microscopy, 37 and single-vortex imaging, 37,38 have provided key ingredients and paved the way toward novel vortex ratchet applications. At the same time, vortices on artificial pinning arrays constitute a much broader research area whose recent developments and exciting prospects cannot be detailed here.

Theory 39 and experiments 40 have shown that nonperiodic arrays provide sizable superconducting critical current enhancements over a larger field range than those obtained with periodic arrays. Thus, ordered, nonperiodic arrays are probably the route toward new developments in the field.

Proximity

Mesoscopic length scales clearly manifest themselves in situations when two dissimilar materials are in close physical proximity. In many cases, there are general so-called proximity effects in which the interactions between competing phenomena produce new physics. Examples of such long-range effects, which are independent of detailed atomic arrangements, include the classical superconducting or magnetic proximity effect in which a normal material may become superconducting or magnetic, and asymmetric magnetic reversal in FM/antiferromagnetic (AFM) bilayers.

FM heterostructures

FM heterostructures are classic examples in which mesoscopic phenomena appear due to competition between various magnetic length scales. The typical magnetic domain wall width is larger than several tens of nm in many FM materials. It is very unusual and unexpected to find a small (<10 nm) domain wall, especially in a typical soft ferromagnet, such as Permalloy or Yttrium Iron Garnet (YIG). A classic interesting example from the fundamental and applied points of view, where very short domain walls can be engineered, is the one formed by combinations of magnetically soft/hard bilayers. [41][42][43][44] In particular, an FM in intimate contact with an AFM 45 or a soft magnetic material in contact with a hard one exhibits these interesting effects. Due to the interfacial interactions in FM/AFM ("exchange biased") or soft/hard ("FM spring") heterostructures, a short mesoscopic domain wall (<10 nm) can form, as shown in Figure 4a. As a consequence, the FM reversal becomes asymmetric and reversible as shown in Figure 4b. 46 In these systems, the magnetization reversal initiates with the nucleation of a quasi-Bloch wall, where the magnetization rotates in the soft FM in a plane parallel to the interface. This results in a spiral spin configuration that motivates the expression 'exchange spring'. As the reversed field increases, the quasi-Bloch wall in the soft FM is compressed against the hard one, and the interfacial hard spins also increasingly rotate. The soft spins rotate back into alignment with the hard phase if the reverse field is removed.

Nucleation and evolution of the quasi-Bloch walls during exchange-spring reversal have been characterized using a magneto-optical indicator, 47 polarized neutron reflectivity, 48 coherent nuclear resonant scattering, 49 x-ray resonant magnetic scattering, 50 and layer-resolved conversion-electron Mössbauer spectroscopy, 51 and magnetotransport. 52 It is important to note that formation of mesoscopic quasi-Bloch walls are mainly governed by the interfacial coupling between soft/ hard or FM/AFM, which depends on the microstructural details of the interface and sample morphology. This can produce many rich phenomena 53 related to roughness, 54,55 grain size, [56][57][58] crystallinity, 59,60 interlayer diffusion, 61 and defects. [62][63][64] Furthermore, these properties depend on temperature and magnetic field history of the sample. 65,66 Therefore, general magnetic properties on these heterostructures are attributable to several extrinsic and intrinsic parameters, which become very important at the mesoscale. [67][68][69]

Triplet superconductivity

The superconducting (S) proximity effect-penetration of the superconducting condensate into a nonsuperconducting material in contact with a superconductor-is long-ranged (up to ~microns) for clean metals. However, it is usually short-ranged for FMs, because the exchange field tends to align the electron spins breaking apart conventional opposite-spin singlet Cooper pairs. 70 This occurs within a length scale ξF ~ nm, with 𝜉 F = √ℏ𝐷/2𝐸 ex for diffusive systems (D is the electronic diffusion constant, Eex is the exchange splitting, and ℏ is the reduced Planck constant) and ξF = vF/2Eex for ballistic systems (vF is the

Fermi velocity).

Long-range proximity effects have been experimentally observed at specific S/FM interfaces [71][72][73][74][75][76] and explained by the generation of unconventional equal-spin triplet pairs. These are immune to the exchange field and can propagate over long distances into the FM. [77][78][79] While the salient features of conventional S/FM proximity effects have received attention for two decades, 70 equal-spin triplets currently attract the spotlight. Although triplets were earlier evoked to explain the coexistence of ferromagnetism and superconductivity in certain bulk materials, 80 artificial S/FM hybrids have only recently opened the door to deeper understanding and manipulation of this unconventional superconducting state.

Open research topics in this area include an understanding of specific systems (e.g., cuprate/manganite interfaces 75,76,81 ) and the search for new S/FM combinations and novel mechanisms. Theory has recently shown that spin-orbit coupling 82 can promote equal-spin triplet pairing, a possibility that opens an approach to manipulate the triplet condensate. The dynamic coupling between the equal-spin triplet condensate and the FM magnetization is another appealing perspective. Theory shows that a time-varying magnetization influences the triplet condensate generation due to the non-equilibrium spin-accumulation induced at the interface. 83,84 Conversely, an equal-spin triplet supercurrent is predicted to affect the magnetization via spin-torque. 85,86 However, no experimental studies exist in which the triplet condensate is manipulated with stimuli such as microwaves. These fundamental prospects, in addition to the potential of triplet superconductivity for "superconducting spintronics," make this emergent topic an exciting area of research.

Outlook and future

The outlook for future research on mesoscopic behavior in magnets and superconductors is very bright. The synthesis and control of artificial structures in different, complex materials allows control across length scales, which are relevant for the development of novel physics. It is especially interesting that long-range coherent behavior allows for the study of quantum phenomena at room temperature, such as Bose-Einstein condensation of magnons. At the same time, it opens up a series of important issues, questions, and potential capabilities for new physics.

Magnon Bose-Einstein condensation

Interestingly, in thin films, the competition between short-range exchange and long-range dipolar interactions can give rise to nonmonotonic magnon dispersion with minima at finite wave vectors, schematically shown in Figure 5a. 87 These minima can be utilized to explore collective magnon states, which can form a Bose-Einstein condensate (BEC) even at room temperature, as initially demonstrated a decade ago 88 based on earlier theoretical predictions. 89 In this seminal experiment, a very dense gas of magnons was excited via parametric pumping to an energy well above the magnon dispersion minimum. During parametric pumping, a microwave photon generates two magnons with opposite wave vectors, as shown schematically in Figure 5a. Subsequently, four magnonscattering processes redistribute the energy, while maintaining the magnon density. Once the magnon density exceeds a critical value, the BEC forms at the dispersion curve minimum, as experimentally measured with spatially resolved Brillouin light-scattering. 87,88,[START_REF] Hillebrands | Modern Techniques for Characterizing Magnetic Materials[END_REF][START_REF] Serga | [END_REF] The coherence between the two components of the BEC with opposite wave vectors produces a standing wave pattern directly revealing the magnon wavelength at the dispersion minima.

The generation of room-temperature magnon BECs opens up exciting opportunities for the exploration of macroscopic quantum coherent phenomena at temperatures far above those studied in any superconductors or liquid He. For example, Josephson effects, between two superconducting condensates coupled via a weak link, have been key to high-precision measurements, as well as the practical implementations of quantum computation. Interestingly, although Josephson effects have been studied in superconducting systems for about half a century, only recently has this concept been extended to other BEC systems such as atomic gases. 92 A recent theoretical prediction claims that similar Josephson effects should exist for magnon BECs. 93 One main challenge is to generate magnon BECs with spatially modulated phase relationships. Toward this end, establishing magnon BEC via local charge 94 or heat currents 95 may offer a possible solution. In fact, it was suggested very recently that temperature gradients within magnon BECs may be accompanied by magnon supercurrents. 96 Other approaches of spatially tailoring magnon properties include local field modulations. 97,98

Superconducting spintronics

Conventional spintronics combines information storage in FMs (memory) and information transport by spin-polarized electrons. The archetypal device (spinvalve) consists of two FM electrodes connected by a nonmagnetic channel. The relative orientation of the electrodes' magnetization (parallel/antiparallel) yields electrical-resistance states (low/high, respectively), due to spin-dependent electron scattering. The superconducting analogues of the spin-valve generally consist of S/FM hybrids that show resistive switching driven by the magnetic history, [99][100][101][102][103][104][105][106][107] using the dependence of the critical temperature (TC) on the FM magnetization. However, many superconducting "spin-valves" do not truly exploit spin-dependent transport, rather they use a variety of different mechanisms, from FM stray magnetic field 102,104,108,109 or exchange field 99,105 effects on the superconductor, to the proximity effect-either the conventional (short-range singlet) 101 or triplet 107,110,111 (see example in Figure 6). Only in some cases 100,103 does resistive switching arise from spin accumulation in the superconductor due to quasiparticle injection from the ferromagnet. Regardless of the governing mechanism, resistance switching is usually much larger than in conventional spin-valves. However, as TC variations are minute, the "spin-valve" effect is observed only in a very narrow temperature range near the intrinsic TC

[see Figure 6c].
A conceptual leap uses superconductivity to improve "information transport" above the conventional "spin-valves" (which work as a memory). For this, superconductors (instead of metals or semiconductors) are used as the spintransport channel. Interestingly, experiments have repeatedly shown that the spindiffusion lengths in superconducting metals are significantly longer below TC than above TC, [112][113][114] due to different spin-relaxation mechanisms. Equal-spin triplet superconductivity can be used to induce "spin-polarized superconductivity" in the FM, as opposed to creating a spin accumulation in the superconductor. Therefore, information would be carried by spin-polarized superconducting pairs in the FM, which leads to important implications.

In contrast to the nonequilibrium spin accumulation produced by spin injection, equal-spin triplet superconductivity is an equilibrium state induced by proximity in the FM without any external stimuli (such as electrical current, microwaves, or light). This should allow for novel, simpler device architectures. Also, certain quantum coherence effects (e.g., nonlocality and Josephson effects) provide possibilities 115,116 that are absent in conventional spintronics. Recent realizations seeking that potential include magnetic-history switchable Josephson junctions. 117 Of course, there are quite a few challenges ahead. For instance, devising methods that efficiently discriminate and "read" the polarization of equal-spin triplet states in FMs, when both spin-up and spin-down triplet pairs coexist. A possible way is the use of half-FM metals, in which only one equalspin polarization is possible. Another standing challenge that could attract future attention is the transfer of the equal-spin triplets from the FM into another material, (e.g., a nonmagnetic metal) where equal-spin triplets could stay phase coherent over long distances.

Conclusions

The properties of materials at mesoscopic length scales provide a unique opportunity for interesting basic research studies and for the development of unique, useful devices. The long length scales (larger than interatomic spaces) of mesoscopic structures allow the pursuit of many studies without additional complications related to synthesis and characterization of structurally perfect materials. Nevertheless, it is important to be vigilant to avoid complications due to extrinsic effects. In many mesoscopic systems, it is precisely the imperfections that make the science interesting. In particular, in the field of magnetism and superconductivity, there are many phenomena that depend on a complicated interplay between long mesoscopic and atomic length scales. Because of the vast number of length scales existing in these materials and the broad area impacted, it is impossible to have a comprehensive review in which all different aspects of these are covered.

Figure 1 .

 1 Figure 1. Comparison of selected characterization techniques used for mesoscopic magnetism and superconductivity with relevant length scales. dex = exchange length, ds = screening length, dRKKY = Ruderman-Kittel-Kasuya-Yosida length, dw = domain walls, dm = magnetic dipolar length, dc = magnetic domains, dsd = spin diffusion length, l= mean free path, ξ= superconducting coherence length, λ= superconducting penetration length, IMSA = ion mill surface analysis, XRD = x-ray diffraction, TEM = transmission electron microscopy, M-O = magneto-optics, SEM = scanning electron microscopy, SPM = scanning probe microscopy, z is the direction perpendicular to a layered system, and x-y are the directions within the plane of a layered system. Adapted with permission from Reference 1, copyright (1999), Elsevier.

Figure 2 .

 2 Figure 2. Magnetic skyrmions. (a) Schematic showing a skyrmion spin structure as expected from interfacial Dzyaloshinskii-Moriya interactions in magnetic multilayers. The color is used to emphasize the different out-of-plane magnetization components. (b) Magneto-optic Kerr effect (MOKE) imaging of the domain structure in a Ta/CoFeB/TaOx trilayer patterned into a 60-μm wide wire with a 3-μm wide constriction. With a small magnetic field (𝐵 ⊥ ) of -0.5 mT applied perpendicular to the film plane, only isolated band (left) and bubble domains (right) are visible. (c) MOKE imaging after a current pulse of je = 5×10 5 A/cm 2 has been applied. This results in the transformation of band domains on the left into magnetic skyrmions on the right. Adapted with permission from (a) Reference 23, copyright (2014), AIP Publishing LLC; and (b-c) Reference 15, copyright (2015), AAAS.

Figure 3 .

 3 Figure 3. Superconducting vortex ratchets. (a-d) Sketches of the vortex configuration and net direction of motion (depicted with red and blue arrows) in Nb deposited over a magnetic nano-triangle pinning array, for different vortex densities. Vortices pinned on the triangles are shown in red and interstitial vortices in blue spheres. The distance between bottom sides of the triangles (white line) is 746 nm. (e-h) Net vortex velocity (<v>) as a function of the AC drive amplitude (FL) for the situations depicted in (a-d). n indicates the number of vortices per unit cell of the array. Adapted with permission from Reference 32, copyright (2003), AAAS.

Figure 4 .

 4 Figure 4. Exchange spring. (a) Depicted depth profile of the magnetization in the soft ferromagnetic layer during reversal. Colored arrows are to highlight different amount of rotations of moments from the pinning direction. (b) Example hysteresis curves of Py/FeF2 bilayer exchange bias system that exhibits asymmetric and reversible behaviour due to exchange spring formation. Note: M, magnetization; MS, saturation magnetization; H, external magnetic field; tPy, thickness of permalloy layer. Adapted with permission from Reference 46, copyright (2015), American Physical Society.

Figure 5 :

 5 Figure 5: Bose-Einstein condensed magnons. (a) Schematic illustration of the magnon dispersion in a magnetic thin film. The competition between short-range exchange and long-range dipolar interactions gives rise to two global minima in the dispersion at opposite wave vectors. Magnons excited at higher energy can subsequently create two coherent Bose-Einstein condensates at the wavevectors -kBEC and kBEC, where the magnon dispersion has two minima. (b) Measurement of the spatial distribution of Bose Einstein condensed magnons in a Y3Fe5O12 thin film. The two magnon-condensates can interfere, which gives rise to a standing wave pattern. This can be directly probed with spatially resolved Brillouin lightscattering (BLS) measurements along the two lateral directions (y and z), where the scattered intensity (indicated by the color code on the right side of the graph) is proportional to the condensate density. Dashed areas and circles indicate the position of topological defects in the condensate. Adapted with permission from Reference 87, copyright (2012), Macmillan Publisher Ltd..

Figure 6 .

 6 Figure 6. Superconducting spintronics. (a) Illustration of a triplet "superconducting spin valve". The superconductor (Nb) is sandwiched between two ferromagnetic (FM) (Ho/Py bilayers). Ho is a conical magnet that behaves as a spin-mixer to generate equal-spin triplet state. (b)The hysteresis loop for a spin valve with a 5-nm-thick layer of Ho on either side of Nb shows that the exchange bias exerted by the FeMn layer on the lower Py layer, allows for parallel/antiparallel magnetization states of the Py layers. (c) The spin-valve magneto-resistance (R) shows hysteresis, with a resistive switching within the field range in which the Py layers magnetization is labeled antiparallel. In the case of antiparallel magnetization, some of the triplet pairs are not be able to flow from one FM electrode into the opposite one, which results in higher resistance. The effect is observed only in a narrow (few mK) temperature range across the superconducting transition (Tc ~ 6.90 K). The curves correspond to two measurements at different temperatures within the range 6.98 to 6.90 K. Note: M, magnetization; MS, saturation magnetization; μ0, magnetic permeability of free space; H, applied magnetic field. Adapted with permission from Reference 107, copyright (2014), MacMillan Publishers Ltd.

Table I .

 I Selected effects where mesoscopic length scales play a determining role are summarized.

	Effect	System	Measurements	Length scales	Phenomenon Ref.
	Bohm-Aharonov	Rings	MT	l (S,M)		Topology	3-5
	Dimensional crossover Superlattices H C2	 (S)		Proximity	6,7
	Solitons	Pillars	FMR	d (M)		Topology	8,9
					w
	Collective pinning	Films/arrays	MT	 (S,M)	Topology	10
	Josephson	Trilayers	I-V	 (S)		Topology	11
	Andreev reflection	Hetero	I-V		,	d	(S,M)	Proximity	12
						sd
	Vortex	Dots	SPM	d (M)	Topology	13,14
					ex
	Skyrmion	Films	SPM	d (M)	Topology	15,16
					ex
	Magnon bands	Superlattices BLS	d (M)		Dimensional	17
					p
	Note: MT, Magnetotransport; SPM, scanning probe microscopy; BLS, Brillouin
	light scattering; Hc2, upper critical magnetic field; FMR, ferromagnetic resonance;
	l, electronic mean free path; ξ, coherence length; dw, domain walls; λ, penetration
	depth; dsd, spin diffusion length; dex, exchange length; dp, dipolar length(); I,
	current; V, voltage; S, superconducting; M, magnetic.

Acknowledgements

This is a highly collaborative review. The outline of this article was conceived jointly, extensively debated, and the article was written by multiple iterations between all the coauthors. The research at UCSD was supported by the Office of Basic Energy Science, US Department of Energy, BES-DMS funded by the Department of Energy's Office of Basic Energy Science, DMR under grant DE FG02 87ER-45332 and the US AFOSR Grant No. FA9550-12-1-0381. The work at Argonne was supported by the US Department of Energy, Office of Science, Basic Energy Sciences, Materials Sciences and Engineering Division. Work at CNRS/Thales supported by ERC grant No. 647100 "SUSPINTRONICS". I.K.S. thanks the US Department of Defense for a National Security Science and Engineering Faculty Fellowship (NSSEFF). We thank Y. Bruynseraede for work on the initial stages of this manuscript.


A Levisse

P Royer

B Giraud

J P Noel

M Moreau

J M Portal

Architecture, Design and Technology Guidelines for Crosspoint Memories

Keywords: RRAM, crosspoint memory, crossbar memory, 1S1R NVM device, NVM

While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (1S1R) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30µA and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories

I. INTRODUCTION

The data deluge triggered by the Internet of Things (IoT) arrival in the consumer market spotlights the need for nonvolatile memories (NVM) for servers/data centers (standalone NVM) and connected objects (embedded NVM). Both standalone and embedded floating gate Flash memory technologies are facing extreme process complexity and cost increase (due to multiple patterning [START_REF] Pikus | Advanced multi-patterning and hybrid lithography techniques[END_REF], split gate [START_REF] Do | Scaling of split-gate flash memory and its adoption in modern embedded non-volatile applications[END_REF], air gap [START_REF] Seo | Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies[END_REF], vertical stacking [START_REF] Park | Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming[END_REF]), as well as performance reduction [START_REF] Grupp | The bleak future of NAND flash memory[END_REF].

Facing this issue, new technologies, such as Resistive Switching Memories (RRAM) are thought as a possible replacement candidate for flash memories. Various RRAM technologies are reported and demonstrated, each based on a specific physical effect. Phase Change Memories (PCM) [START_REF] Wong | Phase Change Memory[END_REF], Magnetic Random-Access Memories (MRAM) [START_REF] Apalkov | Magnetoresistive Random Access Memory[END_REF] and filamentary Resistive Memories (Oxide-based RRAM -OxRAM and Conductive Bridge RRAM -CBRAM) [START_REF] Wong | Metal-Oxide RRAM[END_REF][START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF], are seen as the most popular RRAM technologies and explored as a Flash replacement candidate by both industrials and academics. The major strength of RRAM technologies compared to Flash memories is the low-cost Back-End-of-Line (BEoL) integration [START_REF] Clermidy | Resistive memories: Which applications?[END_REF], the write speed (down to few nano-seconds [START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF]) and a high scalability in the BEoL [START_REF] Xu | Fully CMOS compatible 3D vertical RRAM with self-aligned selfselective cell enabling sub-5nm scaling[END_REF].

To increase the RRAM array density compared to 1 Transistor -1 Resistance (1T1R) architecture, transistor-less architectures, such as crosspoint are reported [START_REF] Liu | A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology[END_REF][START_REF] Kawahara | An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput[END_REF]. To ensure operation of the crosspoint array, a BEoL Selection device must be integrated in series with the RRAM device (1S1R). BEoL selectors are widely studied in the literature [START_REF] Aluguri | Overview of Selector Devices for 3-D Stackable Cross Point RRAM Arrays[END_REF]. However, this additional device doubling the programming voltage [START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF]. This ending up to a 1S1R programming voltage higher than 2.5 Volts [START_REF] Zhang | Selector design considerations and requirements for 1 SIR RRAM crossbar array[END_REF]. This force the use of thicker oxide and more area consuming MOS transistors for the peripheral circuitry [START_REF] Federspiel | 28nm node bulk vs FDSOI reliability comparison[END_REF].

1S1R arrays basically enable 4F² density with minimum width and spacing metal lines. Practically, this density is however impacted by the periphery due to the high programming currents that cannot be reduced under a few tens of microamperes required to ensure a reliable writing operation [START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF]. This effect increases due to voltage drop effects in metal lines [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF].

Few studies considering voltage drop in metal lines are reported [START_REF] Kim | Crossbar RRAM Arrays: Selector Device Requirements During Write Operation[END_REF][START_REF] Zhou | Crossbar RRAM Arrays: Selector Device Requirements During Read Operation[END_REF][START_REF] Chen | A Comprehensive Crossbar Array Model With Solutions for Line Resistance and Nonlinear Device Characteristics[END_REF][START_REF] Zuloaga | Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design[END_REF]. However, none complete study considers the full structure of the macrocell, i.e. the crosspoint device, the array area, the array metal drop issues, the peripheral circuitry overhead and the in-array timing. Furthermore, no study considering multiple bit-write in a single array is reported. In this paper, we propose three complementary models (in-array timing, IR-drop and periphery overhead) taking into account multiple bit-write in the same array and develop a methodology allowing an extensive study of the crosspoint memories designspace.

The remainder of this paper is organized as follows; section II presents the general background of this paper and the previously published models, Section III extends the previously published models for multiple bit-write and introduce a new timing estimation model. Section IV presents an extensive study of design space of crosspoint memory array while section V discusses the results. Finally, section VI concludes the paper.

II. BACKGROUND A. 1 Selector -1 Resistance Bitcell Model

Selective access to RRAM requires specific devices able to drive the high programming currents. On one hand, regular Complementary Metal-Oxide-Semiconductor (CMOS) transistors can be used for this purpose but will severely increase the bitcell area [START_REF] Shen | High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process[END_REF]. Other Front-End-of-Line (FEoL) selection devices can be used (BJTs, vertical gate-all-around transistors) at the expense of increased process cost and complexity [23] [24]. On the other hand, crosspoint transistor-less architectures have been proposed, that integrate one RRAM device at each crossing point of word-lines and bit-lines (WL, BL) without FEoL devices in the array [START_REF] Liu | A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology[END_REF] [START_REF] Kawahara | An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput[END_REF]. These architectures achieve maximum bitcell density but suffer from sneaking currents through unselected bitcells (Sneakpath -SP) that quickly overtake the programming current as soon as the array size grows [START_REF] Levisse | Capacitor based SneakPath compensation circuit for transistorless ReRAM architectures[END_REF] [START_REF] Liang | Cross-Point Memory Array Without Cell Selectors-Device Characteristics and Data Storage Pattern Dependencies[END_REF]. To overcome these limitations, a BEoL selector has to be integrated in the RRAM stack. In 1S1R configuration, the SP effect is mitigated and can be efficiently compensated [START_REF] Levisse | Capacitor based SneakPath compensation circuit for transistorless ReRAM architectures[END_REF] [27] still allowing a dense 4𝐹 2 bitcell area only limited by metal pitch. However, this BEoL selector causes an increase of the programming voltages of a factor 2 at least increasing the programming voltage of the bitcells from 1 to 1.5V [6] [9] up to more than 2.5V [START_REF] Aluguri | Overview of Selector Devices for 3-D Stackable Cross Point RRAM Arrays[END_REF] [START_REF] Cha | Selector Devices for 3-D Cross-point ReRAM[END_REF].

The considered 1S1R bitcell is simply modeled by two parameters introduced in Fig. 1-a

B. Voltage Drop Model

In crosspoint memory arrays, the Iprog current combined with the sum of the Isp currents results in important voltage drops that have to be considered to correctly size the RRAMarray and periphery. The line resistance equivalent to a bitcell length is defined with the half metal pitch (F), the metal aspect ratio (AR) and the metal resistivity (σ) of the WLs/BLs (that are supposed identical). The physical structure of a crosspoint array with detailed parameters is introduced in Fig. 2. An aspect ratio of 2 is considered for the metal lines, as suggested in the ITRS roadmap for high density memory technology nodes [29]. This, results in an increase of the resistance per bitcell as the technology is scaled, as inferred by Eq. ( 1), that assumes a minimum pitch bitcell.

𝑅 𝑢𝑛𝑖𝑡 = 𝜎 • 𝐿 𝑆 = 𝜎 • 2𝐹 𝐹 • (𝐴𝑅 • 𝐹) = 2 • 𝜎 𝐴𝑅 • 𝐹 (1)
The worst-case voltage drop that corresponds to the farthest bitcell being programmed is considered. The first unit resistance (Runit) sees the Iprog and Isp currents of all the bitcells in the line. For every next bitcell, the current is reduced by one-unit SP current until the last bitcell in the line is reached with only Iprog left. In the end, the total voltage drop in a WL is as shown in Eq.

(2), where 𝑛 𝑏 is the number of BL connected to the selected WL. Eq. ( 2) is applied to BLs as well.

𝑉 𝐼𝑅𝑑𝑟𝑜𝑝 = 𝑅 𝑢𝑛𝑖𝑡 • (𝑛 𝑏 • 𝐼 𝑝𝑟𝑜𝑔 + 𝑛 𝑏 • (𝑛 𝑏 -1) 2 • 𝐼 𝑠𝑝 ) (2)
Figure 2: Physical schematic of a 2 x 2 crosspoint array with detailed physical parameters from [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF].

C. Periphery Area Estimation Model

While the array area scaling is usually considered as the most critical parameter of crosspoint memories, peripheral circuitry is poorly seen in the literature as a constraint since large arrays are considered. Beyond pitch matching issues (not considered in this work) that will substantially increase the complexity of peripheral circuitry layout (due to the thicker oxide transistors needed), this section introduces a periphery area overhead model of the ratio between the multiplexer (MUX) and the decoder and the crosspoint memory array.

The area estimation methodology is described in [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF]. It considers two contributions: the active area width of the transistors (that scales with the required current) and the minimum size constraints (width, length, transistor-to-transistor spacing) that has to be considered in order to provide accurate area estimation. In this work, a 150nm gate length IO transistor from a 28nm CMOS technology, reliable up to 3V, is considered. Each cell of the MUX contains two blocks, one driving WL or BL when selected, and one driving the WL or BL when not selected. The selected driver width is scaling with Iprog and Isp while the non-selected driver only scales with Isp. The decoder topology is detailed in [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF] where minimum width transistors are considered.

III. MODELS In this section, we introduce a timing estimation model based on metal lines parasitic capacitance, and extend the previous IR drop and periphery area models from [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF] to include the multiple-bit programming case.

A. Timing Estimation Model

Beyond the IR-drop and overhead estimation, with the scaling of the array, the time required to charge and discharge the selected WL and BL might have a significant impact on the overall programming and access time.

The parasitic capacitance is defined as the facing lateral and vertical capacitances of crosspoint memory metal lines (while crosspoint arrays with aggressive pitch can be integrated in high BEoL levels [START_REF] Liu | A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology[END_REF], coupling capacitance with silicon substrate is not considered in this work). Two different unit capacitance contributions are considered based on the physical schematic presented Fig. 2: (i) the lateral capacitance 𝐶 𝑙𝑎𝑡 , between the selected line and the ones running in parallel; (ii) the vertical capacitance 𝐶 𝑣𝑒𝑟 , between the studied line and the ones crossing it perpendicularly.

A vertical spacing of 𝐴𝑅 * 𝐹 with a typical SiO 2 permittivity (𝜀 𝑟 ≈ 3.9) is considered. As the distance between the considered line to the crossing lines (𝐴𝑅 * 𝐹) is higher than the crossing lines pitch (F) those can be approximated by a plane. This leads to an opposing surface of 2𝐹² which considers only the fringe capacitances in the direction of the studied line.

The horizontal spacing corresponds to the pitch of the technology. This makes 𝐶 𝑙𝑎𝑡 capacitance more critical. Hence, Flash NAND process commonly uses low-K insulator [START_REF] Helmet | A 128Gb MLC NAND-Flash device using 16nm planar cell[END_REF], such as air-gap (𝜀 𝑟 ≈ 2). The opposing surface of horizontal capacitance is 2 * 𝐴𝑅 * 𝐹² as seen in Fig. 2. While integrating airgap represents a huge additional process cost, in the following simulations we consider typical SiO 2 permittivity.

Considering all these parameters, 𝐶 𝑣𝑒𝑟 and 𝐶 𝑙𝑎𝑡 unit capacitances are shown in Eq. ( 3) and ( 4), respectively. Those inferred equations only take into account fringe capacitances in the bottom metal layer direction for the vertical capacitances. An increase of 50% and 20% of the 𝐶 𝑣𝑒𝑟 and 𝐶 𝑙𝑎𝑡 capacitances, respectively, would still be optimistic as benchmarked with a 50nm half pitch-pitch technology.

𝐶 𝑣𝑒𝑟 = 𝜀 𝑣𝑒𝑟 • 𝜀 0 • 2𝐹 • 𝐹 𝐴𝑅 • 𝐹 = 𝜀 𝑣𝑒𝑟 • 𝜀 0 • 2𝐹 𝐴𝑅 (3)
𝐶 𝑙𝑎𝑡 = 𝜀 𝑙𝑎𝑡 • 𝜀 0 • 2𝐹 • 𝐴𝑅 • 𝐹 𝐹 = 𝜀 𝑙𝑎𝑡 • 𝜀 0 • 2𝐹 • 𝐴𝑅 (4)
Once the equivalent capacitance is calculated, the worst-case bitcell is considered, that is the one laying in the last BL and WL from the MUX. Thus, the delay is calculated for a line length corresponding to the considered array parameters. The considered RC network, presented Fig. 3, is a Ladder RC network. To simplify the calculation, an Elmore delay [START_REF] Lamdan | Calculation of 'Elmore' delay for RC ladder networks[END_REF] is considered, that approximates the time constant of 𝑛 RC units (Eq. ( 5)).

𝜏 𝑅𝐶,𝑛 = 𝑛 2 2 • 𝑅 • 𝐶 (5)
Then, the array delay is determined for 95% of the full charging time, i.e. 3 * 𝜏 𝑅𝐶,𝑛 . The sum of charge and discharge times of the line is considered for the last bitcell of the line and the column. Runit, and the sum of 𝐶 𝑣𝑒𝑟 and 𝐶 𝑙𝑎𝑡 capacitances are injected in Eq. ( 5) to determine the time constant.

It is interesting to note that in the considered model, the metal resistivity is proportional to 1/𝐹 while the capacitance is proportional to 𝐹. This results in a timing estimation that is independent of the half pitch physical dimension.

B. Multiple-Bit In-Array Voltage Drop Model

When writing multiple bits, in addition to the SP current, the WL MUX has to provide Iprog times the number of bitcells that are written. These bitcells are spread along the WL. Each accessed bitcell is distributed every 𝑛 𝑏 /𝑛 𝑝 , where 𝑛 𝑝 is the number of programmed bitcells and 𝑛 𝑏 is the total number of bitcells in the WL, i.e., number of BLs. The BL MUX drives a single bitcell but 𝑛 𝑝 BL MUX are activated simultaneously. Fig. 4-a presents an example of 2 bit-write in a 4WL-8BL array. Each red dot corresponds to selected WLs, BLs and bitcells, while each orange dot corresponds to non-selected WLs, BLs and bitcells, biased to half of the programming voltage.

The first Runit of the WL sees a total current of 𝑛 𝑝 • 𝐼 𝑝𝑟𝑜𝑔 + (𝑛 𝑏 -𝑛 𝑝 ) • 𝐼 𝑠𝑝 corresponding to 𝑛 𝑝 bitcells being programmed plus the SP currents on all the bitcells in the WL (𝑛 𝑏 -𝑛 𝑝 ). The total current is reduced by 𝐼 𝑠𝑝 every non-selected bitcell and by 𝐼 𝑝𝑟𝑜𝑔 every programmed bitcell (𝑛 𝑏 /𝑛 𝑝 ). Eq. ( 6) shows the total IR drop in the selected WL. The voltage drops in both WL and BL are then added. IR drop in the WL is based on Eq. ( 6) while the one in the BL is based on Eq. ( 2). Eq. ( 7) shows the worst case total voltage drop when programming 𝑛 𝑝 bits in a 𝑛 𝑤 WL and 𝑛 𝑏 BL crosspoint memory array.

C. Multiple-Bit Periphery Area Estimation Model

The periphery area model has been extended to consider multiple bit writing. In particular, the sizes of the MUX are changed according to the required drives, as foreseen in Fig. 4a. TP transistors in the BL side still only require to drive 1xIsp as only 1 active WL crosses each unselected BL.

On the other hand, WL side TP transistors has to drive as many Isp as active BLs, that is, the amount of programmed bits. TG transistors driving the WLs additionally need to drive as many Iprog as written bits, while on the BL side TG transistors size remains unchanged.

The periphery area estimation model takes as an input the MUX proposed in Fig. 4-b. This MUX is more compact than the one previously published in [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF]. When unaccessed, the array is disconnected from the writing circuitry and biased to GND when 𝐸𝑁_𝑊𝑅 signal is low. When accessed (𝐸𝑁 𝑊𝑅 = ′1′), the Half-Bias generator (repectively the Write or Sense Amplifiers -WrA and SA) is connected to TP gate (resp. TG). TP and TG are controlled by the DA0-n signals generated by the dynamic decoder proposed in [START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF]. When TG is activated, TG is turned off. TP contains only a p-type transistor because the driven voltages are higher than its threshold voltage (half of the programming voltage). TG is made of p-type + n-type MOS transistors in parallel because the selected WL or BL has to be driven to a low or high voltage without voltage loss through the MOS transistors.

IV. DESIGN SPACE EXPLORATION METHODOLOGY In this section, we explore the design space of crosspoint memories. We introduce a design methodology that we first apply to a 1-layer crosspoint memory with 1 bit-write per array. For filamentary-based RRAM technologies (OxRAM, CBRAM), the assumption is taken that electro-forming step was achieved with a Iprog current. While this step is performed once in the lifetime of the device [START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF] MUX transistors reliability is assumed not critical and this step is considered as already achieved. During each programming operation (set or reset), programming conditions (current and voltage control, variability compensation, SP compensation) are controlled from the WrA. WLs and BLs MUX transistors have to sustain huge voltage differences across their terminals, forbidding cascode strategy. Such voltages make impossible the use of thin gate oxide transistors from sub-30nm CMOS nodes [START_REF] Federspiel | 28nm node bulk vs FDSOI reliability comparison[END_REF]. Thereby, thicker oxide 150nm gate length MOS IO transistors from a 28nm CMOS technology node are considered. Assuming a 3V CMOS operating voltage and a 2.5V 1S1R programming voltage, an IRdop of 0.5V is considered as the maximum in the following. First, we calculate the maximum possible array size based on the IR drop model presented in section II-b and III-b. For each Isp/Iprog couple, we determine the maximum possible array size for a given set of technology parameters taken from [29]. The maximum array size is calculated by increasing progressively the array size until the IR drop reaches the 0.5V criterion introduced previously. Square arrays are considered in order to provide equalized IRdrop between the selected WL and BL. It also provides an identical sizing between WLs and BLs MUXs.

In the following, a copper metal half pitch of 25nm with a conductivity (σ 25nm ) of 6.8µΩ.cm -1 at 300°K and anAR) of 2 are considered. Contacts and vias resistivity between the access transistors and the array are not considered.

Fig. 5 shows the array size (WL and BL amount) and area (µm²) versus Iprog and Isp currents. The array area is 4F²*WL*BL. Logically, the lower Iprog and Isp, the lower the effects of the IR drop, i.e., the bigger the array can be. Two main array size limitation zones are identified: the selector limiting zone and the RRAM limiting zone. While the Isp are summed along the selected WL and BL, only one Iprog is required as only one bitcell per array is programmed in this section. Thus, Isp has a higher impact in the limitation of the array size. The maximum design-able array size is directly limited by the 1S1R device specifications. As an example, a couple Iprog=40µA and Isp=10nA per device gives a 2048 WLs and BLs array.

Once the array size is determined, the total SP current consumed on the unselected WLs and BLs can be calculated. Thus, using the periphery estimation model presented in sections II-c and III-c, we calculate the MUX and decoder area of the peripheral circuitry. The MUX area is calculated using the schematic presented Fig. 4-a. In the proposed MUX, for 1 bitwrite in the array (p=1 in Fig. 4-c), the p-type transistor (TP) drives Isp current while the n-type + p-type transmission gate (TG) drives Iprog + m*Isp (where m is the number of WL and BL of the considered array). The transistors width is thus calculated depending on the current consumed by the array. The total MUX area is the sum of the WL and BL MUXs. The decoder is calculated using the same methodology than the MUX. Fig. 6 presents the area of TG (blue) and TP (red). It appears that the TP transistor impact on the MUX area is negligible in regards with TG area. TG area scales with both Iprog and Isp. In this section, the dynamic decoder area is not detailed, but will be taken into account in the area overhead estimation. For high Iprog and Isp, the TP area is negligible in regards with the TG area.

Once the peripheral circuitry (MUX and decoders) and the array areas are determined, the area overhead of the periphery w.r.t. the array is calculated by dividing the periphery area by the array area. With these data, it is possible to determine the requirements of a RRAM and BEoL selector devices for a specific application. As an example, in order to be competitive with Flash NAND memories, the area overhead must be lower than 20%. Thus, considering that constraint, Iprog must be lower than 30µA and Isp lower than 10nA. The resulting array size is bigger than 2500 WL and BL. As a reference, in Fig. 7, the red zone shows how a 20% area overhead limit, reduce the field of possible device specifications for the RRAM and the BEoL selector. Two 1S1R specific limitations are also presented in Fig. 7. The first one is the non-volatile minimum Iprog (Min NV Iprog). Depending on the RRAM technologies, it has been shown that a too low Iprog will result in volatile behavior or increased variability of the resistive state [START_REF] Grossi | Fundamental Variability Limits of Filament-based RRAM[END_REF]. Thereby, this limitation gives a lower bound in the Iprog. The second limitation comes from the selector Isp that may be difficult to achieve below tens of pA.

With the increase of the array size, as introduced in section III-a, the array WL and BL charging time may become a limiting parameter. Fig. 8 presents the charging time of a crosspoint array line versus the technology node and the number of WLs and BLs. For deeply scaled half metal pitch, copper lines resistivity increases from 6.8µΩ.cm -1 (50nm) to 8.5µΩ.cm -1 (15nm) [29] [START_REF] Van Der Veen | Barrier/Liner Stacks for Scaling the Cu Interconnect Metallization[END_REF].

Considering that, the lines charging time should not take more than 10% of the total programming pulse that can be as short as 10ns still ensuring a reliable RRAM operation [START_REF] Vianello | Resistive Memories for Ultra-Low-Power embedded computing design[END_REF], array size is limited by the timing. At F=25nm, 1ns charging time is achieved for a 3100 WL and BL array. In Fig 7, this maximum array size limitation is shown as a blue zone.

In this section, we explored the design space of crosspoint memories using the IR drop, the periphery area overhead and the in-array line charging time. In order to detail the methodology, we took as an an F=25nm copper interconnect 1-layer crosspoint memory in which only one bit is written at a time.

We showed that IR drop limits the maximum possible array size whereas reduction of periphery overhead would tend to design the biggest array possible. We also demonstrate that the lower the Iprog and Isp are, the bigger arrays can be designed for an equivalent area overhead. These parameters are however physically limited and thus arbitrary large arrays cannot be achieved. Moreover, large arrays would severely impact the time required to charge and discharge the lines. V. DISCUSSION The proposed design methodology can be applied to any technology node used to implement a crosspoint memory array. However, when scaled, metal line resistivity and periphery overhead becomes a strong limitation. The extension to multiple-layer crosspoint memory will not impact the density due to a peripheral circuitry that will be multiplied as much as the amount of stacked crosspoint layers.

This study shows that Isp has a major impact, however, regarding the literature, arrays sizes are commonly small (576*2048 in [START_REF] Kawahara | An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput[END_REF] and 2048*4096 in [START_REF] Liu | A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology[END_REF]). Thus, from the point of view of the IRdrop, designing a selector providing less than 1nA SP current is not critical while the programming current cannot be reduced under few tens of micro-ampere without reliability reduction [START_REF] Grossi | Fundamental Variability Limits of Filament-based RRAM[END_REF].

Due to huge area overhead, crosspoint bit density is lower than Flash NAND memory even though the bitcell area is the same (4F²). This gap increases as more bits are written in parallel. Fig. 9 shows the bit density of a crosspoint memory using Iprog=30µA and Isp=10nA versus the metal half pitch (from 50nm down to 15nm) for different word-length written in a single array (1bit to 32bits), and compared to other memory technologies (Flash NAND and DRAM). The presented bit densities are determined using the methodology presented in section IV and the multiple-bit write IR drop and periphery estimation models presented in section III-b and III-c. It appears that as the programmed word grows, the density quickly decreases.

While 1 bit-write enable bit densities (47Gb/cm² at F=15nm) almost competitive with planar Flash NAND densities (76Gb/cm² for F=16nm [START_REF] Helmet | A 128Gb MLC NAND-Flash device using 16nm planar cell[END_REF], 56Gb/cm² for F=19nm [START_REF] Shibata | A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface[END_REF] and 28Gb/cm² for F=32nm [START_REF] Park | 32nm 3-bit 32Gb NAND Flash Memory with DPT (d̲ ouble p ̲ atterning t̲ echnology) process for mass production[END_REF]), 16 and 32 bit-write per array strongly reduce the bit density (less than 5Gb/cm² for 16 bitwrite at F=15nm) lower than DRAM density (9.4Gb/cm² for F=20nm [START_REF] Brox | An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective highperformance applications[END_REF] and 3.8Gb/cm² for F=37nm [START_REF] Ting | An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache[END_REF]). This result highlights the need for write a small number of bits per array in order to maximize the density.

VI. CONCLUSION

In this work, we first present 3 innovative models (IR drop, periphery overhead and timing estimation) accounting for multiple bit-write in crosspoint memory arrays. We then introduce a design methodology for crosspoint memory arrays based on the proposed models. This methodology consists in, first, calculating the maximum array size taking in account the IRdrop effects in the metal lines and then, using the array size in order to determine both the area and the overhead of the periphery. Finally, the optimal I PROG , I SP , array size and physical BEoL specification can be determined considering the physical specifications of the 1S1R device and the in-array timing constraint. Finally, we apply this methodology to several application cases (1 to 32 simultaneous bit-write per array) and various technology nodes (from 15 to half metal pitch). We show that the area overhead and IRdrop strongly limits the crosspoint memory density (47Gb/cm² in 15nm for 1 bit-write) making it not yet competitive with flash NAND and even with DRAM for more than 16 bit-write per array. Reducing the written word length by spreading it in parallel in several banks appears as an effective way to provide competitive bit density for crosspoint memories.

VII. REFERENCES Figure 9: Extrapolated bit density in Gb/cm² for 1-layer crosspoint memories compared to planar Flash NAND and DRAM product bit densities versus the half metal pitch in nm. For bit-write in a crosspoint array, the bit density is reduced due to the higher amount of current needed in the array, i.e., increased IR drop and periphery area overhead.

  . The programming current (Iprog) corresponds to the current needed to program the selected RRAM in both High (HRS) by a reset operation, and Low (LRS) Resistance States by a set operation. Usual values for Iprog are from few tens of µA up to few mA [6] [9]. The non-selected bitcells, that are polarized in half bias scheme, see a potential under the BEoL selector threshold voltage (V TH ). The unselected bitcells SP current (Isp) is determined as the leakage current of the selector at half of the RRAM programming voltage as shown in Fig. 1-b. Usual values for Isp are from pA to µA [14] [28].

Figure 1 :

 1 Figure 1: (a) I-V curve of RRAM (blue) and 1S1R (red) bitcell. (b) Illustration of the SP in a transistor-less array architecture using 1S1R bitcells.

Figure 3 :

 3 Figure 3: Two major capacitance contributions are considered, the vertical capacitance and the lateral capacitance. The equivalent schematic diagram is a ladder RC network.

Figure 4 :

 4 Figure 4: (a) Organization of the decoders, MUX and array, with driving requirement for each WL and BL. (b) Schematic diagram of the proposed optimized MUX. DA0-n signals are generated by WL and BL decoders from[START_REF] Levisse | High Density Emerging Resistive Memories: What are the Limits ?[END_REF]. Unselected lines are connected to the half bias circuit through TP (orange), while selected lines are connected to the Write (WrA) and Sense (SA) Amplifiers through the transfer gates (red).

Figure 5 :

 5 Figure 5: Maximum possible array size and area versus selector leakage per 1S1R and RRAM programming current. The array size is limited by the leakage and the programming current.

  Fig 7 presents the area overhead versus Isp and Iprog current. The previous example, Iprog=40µA and Isp=10nA per device giving a 2048 WLs and BLs array, has a resulting area overhead of 45%.

Figure 6 :

 6 Figure 6: Detailed area of the TP transistor (red) and TG tranmission gate (blue) constituting the line and columns MUX, versus selector leakage per 1S1R and RRAM programming current. For high programming current and selector leakage, TP area is negligible compared to TG area.

Figure 7 :

 7 Figure 7: area overhead of crosspoint array versus selector leakage and RRAM programming current for F=25nm.

Figure 8 :

 8 Figure 8: Charging time and discharge of a crosspoint array versus the array size and the metal half pitch F. Increase of the metal resistivity with the scaling is taken into account.


Keywords: Double-Gate, FinFET, independent gates, single event transient, heavy ion, charge collection, bipolar amplification

The bipolar amplification and charge collection of Planar Double-Gate and FinFET with independent gates is simulated. The transient response of independent gate devices is compared to that of conventional devices having the gates tied together.

I. INTRODUCTION

S CMOS scaling is approaching its limits, Double-Gate (DG) MOSFET is recognized as the most scalable alternative to the conventional bulk MOSFET due to its high short-channel effects immunity [START_REF] Haensch | Silicon CMOS devices beyond scaling[END_REF]. In spite of excellent electrical performances due to its multiple conduction surfaces, conventional DG MOSFET allows only threeterminal (3T) operation because the two gate electrodes, i.e. the front gate and the back gate, are generally tied together. Planar Double-Gate and FinFET structures with independent gates have been recently proposed [START_REF] Masahara | Demonstration, Analysis, and Device Design Considerations for Independent DG MOSFETs[END_REF]- [START_REF] Mathew | CMOS vertical Multiple Independent Gate Field Effect Transistor (MIGFET)[END_REF], allowing a four terminal (4T) operation. Independent-Gate Planar Double-Gate MOSFET (4T-DGFET) and FinFET (4T-FinFET) devices offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates, transconductance modulation, signal mixer, in addition to the conventional switching operation. Thus, 4T-DGFET and 4T-FinFET are promising for future high performance and low power consumption very large scale integrated circuits. Previous simulation studies demonstrate that 3T-DGFET and 3T-FinFET show better radiation hardness than Single-Gate fully-depleted SOI transistors [START_REF] Castellani | Simulation Analysis of the Bipolar Amplification Induced by Heavy-Ion Irradiation in Double-Gate MOSFETs[END_REF]- [START_REF] Munteanu | 3-D Quantum Numerical Simulation of Single-Event Transients in Multiple-Gate Nanowire MOSFETs[END_REF], particularly due to the numerical simulation the sensitivity to single-event of enhanced control of the body potential and of the reduction of floating body effects. In the present work we investigate by 3D 4T-DGFET and 4T-FinFET devices compared with that of conventional 3T-DGFET and 3T-FinFET. The impact of the The description of the 3D architectures considered in the simulation and the definition of their geometrical parameters are represented in Fig. 1. Planar Double-Gate structures in both 3T-DGFET and 4T-DGFET configurations are based on that reported in [START_REF] Vinet | Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm[END_REF]. For these devices the channel length is 20 nm, the silicon film thickness is 6 nm and the gate oxide is 1 nm-thick. An intrinsic channel and a gate width of 100 nm are also considered. In 3T-DGFET the two gates are tied together and are biased at V g . In 4T-DGFET configuration the gates are biased independently at V g1 (front gate) and V g2 (back gate). FinFET structures are based on devices reported in [START_REF] Lu | Short-channel effects in Independent-Gate FinFETs[END_REF]. An intrinsic fin-body with a 12 nm-thick film thickness (or fin width, t Si ) and a device width h fin =50 nm (or fin height) are considered. The channel length is 25 nm and the front and back gate oxides are 1 nm-thick. 3D numerical simulations have been performed with 3D Synopsis code [START_REF]Synopsys Sentaurus TCAD tools[END_REF], including the SRH and Auger recombination models and the Fermi-Dirac carrier statistics. Both the impact ionization and the carrier mobility depend on carrier energy calculated with the hydrodynamic model. The mobility model also includes the dependence on the lattice temperature and on the channel doping level.

The irradiation track has a Gaussian shape with narrow radius (14 nm) and a Gaussian time dependence, centered on 10 ps and with a characteristic width of 2 ps. The ion strikes in the middle of the channel, as shown in Fig. 1. In planar DGFET, the ion strike is simulated in vertical incidence (parallel to the y axis). In FinFET, two ion strike directions have been considered: vertical (direction "1", parallel to the y axis, Fig. 1) and horizontal (direction "2" parallel to the z axis and perpendicular to the gates, Fig. 1). The deposited charge is calculated considering the Gaussian distribution of the ion track and the 3D geometry of the silicon body. The collected charge is given by the drain current integration over the transient duration and the bipolar gain is finally calculated as the ratio between the collected and deposited charges.

III. PLANAR DOUBLE-GATE

Figure 2 shows the static drain current characteristics as function of front gate bias in 4T-DGFET at different V g2 and in 3T-DGFET. As expected in 4T-DGFET, V g2 modulates the drain current and the main electrical parameters in the subthreshold regime (threshold voltage V T , subthreshold swing S and off-state current I off ).

The drain current transients produced by the ion strike are shown in Fig. 3a for a LET value of 1 MeV/(mg/cm 2 ). The drain current peak in 4T-DGFET is higher than in 3T-DGFET for positive V g2 (and respectively lower for negative V g2 ), due to the higher I off current (and respectively lower I off current for negative V g2 ). However, the collected charge (Fig. 3b) is always higher in 4T-DGFET than in 3T-DGFET. In 4T-DGFET, the control by the front of the electrostatic potential in the channel is less effective, which enhances the floating body effects and the collected charge and the parasitic bipolar amplification (Fig. 4) are higher.

IV. FinFET

Static drain current characteristics as function of front gate bias in 4T-FinFET at different V g2 and in 3T-FinFET are shown in Fig. 5. In 3T-FinFET the gate better controls the potential in the silicon body and reduces short-channel effects. Then, I off in 3T-FinFET is slightly lower than I off in 4T-FinFET with V g2 =0 V (Fig. 5) and the slope is improved in 3T-FinFET compared to 4T-FinFET.

3D electron density profile in the silicon film of 3T-FinFET and 4T-FinFET at Vg2=-0.1 V, before the ion strike, is presented in Fig. 6. In 4T-FinFET, near the back gate (gate 2) interface the electron density is lower than that of 3T-FinFET due to the negative bias of the back gate. 2D electron density in a vertical cross section perpendicular to the gates (C-C' cross-section shown in Fig. 6) confirms this observation.

Similar to Planar DGFET configuration, the peak of the drain current transient in 4T-FinFET is higher than in 3T-FinFET for positive V g2 and smaller for negative V g2 (Fig. 8). The bipolar amplification (presented in Fig. 8 for an ion strike in vertical incidence) increases (at low LET) with the increase of positive V g2 and with the decrease of the negative V g2 .

Front gate voltage V g1 (V) 3T-FinFET 4T-FinFET -Vg2=-0.1 V 4T-FinFET -Vg2=0 V 4T-FinFET -Vg2=0.1 V

3T-FinFET 4T-FinFET 3T-FinFET 4T-FinFET

Bef ore ion strike t=10 ps Fig. 7. 2D profile of electron density in a vertical cross-section (A-A' plane defined in Fig. 6) in the middle of the channel of 3D FinFET before the ion strike and at t = 10 ps (maximum charge generation). The gate material and a part of the buried oxide are not shown. Vg=0 V for 3T-FinFET. Vg1=0 V and Vg2=-0.1 V for 4T-FinFET. Vd=0.7 V. The ion strike LET is 1 MeV/(mg/cm 2 ).

V. DISCUSSION

To facilitate the comparison between FinFET and Planar DGFET, we simulate the transient response for an ion striking horizontally, parallel to the z-axis (perpendicular to the gates, direction "2") in 4T-FinFET. Figure 10 compares drain current transients in 4T-FinFET for the two ion strike directions. The simulation results show that the peak of the drain current transient is lower for a horizontal ion strike than for a vertical ion strike. The collected charge is smaller for an ion striking horizontally on the gates of 4T-FinFET than for a vertical strike, because of a lower deposited charge. However, the bipolar amplification is higher at low LET for a horizontal strike than for a vertical strike, as shown in Fig. 11.

Finally, the bipolar gain is found to be higher in 4T-FinFET than in 4T-DGFET for all LET values. This is due to the thicker silicon film considered in FinFET architectures (12 nm compared to 6 nm in DGFET). Then, floating body effects are more important in FinFET (because the front gate control over the body potential is less effective), which leads to more important bipolar amplification.

VI. CONCLUSION

This paper presents the transient response to heavy ion irradiation of independent gate (4 terminals) DGFET and FinFET. The bipolar gain and charge collection of 4T-DGFET and 4T-FinFET are analyzed as function of LET and ion strike location, and compared to that of 3T-DGET and 3T-FinFET, respectively. Our results show that the bipolar amplification is higher in independent-gates devices for both positive and negative back gate bias. The bipolar gain of FinFET is found to be higher than the bipolar amplification of DGFET, due to the thicker silicon body considered for the first architecture.

  Manuscript received March 31, 2008. This work was supported by the MEDEA+ Project #2A704 ROBIN and by the French Ministry of Research (ANR PNANO project "MULTIGRILLES"). D. Munteanu and M. Moreau are with IM2NP-CNRS, UMR CNRS 6242, Bât. IRPHE, 49 rue Joliot Curie, BP 146, 13384 Marseille Cedex 13, France (Phone: (33) 496 139 819 -Fax: (33) 496 139 709, Email: daniela.munteanu@univ-provence.fr).J.L. Autran is with IM2NP-CNRS, UMR CNRS 6242, Bât. IRPHE, 49 rue Joliot Curie, BP 146, 13384 Marseille Cedex 13, France and with Institut Universitaire de France (IUF), 75000Paris, France (Email: jeanluc.autran@univ-provence.fr).

Fig. 1 .

 1 Fig. 1. Schematic description of the 3-D simulated DGFET and FinFET structures with three and four terminals considered in this work. The main geometrical parameters used in simulation are also defined. (S=source region and D=drain region).

Fig. 2 .Fig. 3 .

 23 Fig. 2. Drain current characteristics as function of Vg1 for 4T-DGFET with different back gate biases. The drain current versus Vg of 3T-DGFET is also reported for comparison. Vd=0.7 V.

Fig. 4 .

 4 Fig. 4. Bipolar amplification as function of LET in 3T-DGFET and 4T-DGFET at Vg2=0.1 V and Vg2=-0.1 V.

Fig. 5 .Fig. 6 .

 56 Fig. 5. Drain current characteristics as function of Vg1 for 4T-DGFET at different back gate biases. The drain current curve versus Vg in 3T-FinFET is also shown. Vd=0.7 V.

Fig. 8 .Fig. 9 .

 89 Fig.8. Drain current transients in 3T-FinFET and 4T-FinFET (at different back gate biases) for an ion strike in vertical incidence. The transistors are biased in off-state (Vg=0 V for 3T-FinFET and Vg1=0 V for 4T-FinFET) and Vd = 0.7 V. The ion strike LET is 0.1 MeV/(mg/cm 2 ).

Fig. 10 .

 10 Fig. 10. Drain current transients in 4T-DGFET for vertical and horizontal ion strikes. The ion strike LET is 0.1 MeV/(mg/cm 2 ).

Fig. 11 .

 11 Fig. 11. Bipolar amplification versus LET in 4T-DGFET for vertical and horizontal ion strikes.