Gérard Bohner

Roméo Bonnefoy

Rémi Cornat

Pascal Gay

Jacques Lecoq

Samuel Manen

Laurent Royer

A very-front-end ADC for the electromagnetic calorimeter of the International Linear Collider

Keywords: ADC, pipeline, CMOS integrated circuit, comparator, differential, amplifier, ILC, CALICE, calorimeter, veryfront-end electronics

A 10-bits pipeline Analog-to-Digital Converter (ADC) is introduced in this paper and the measurements carried out on prototypes produced in a 0.35 µm CMOS technology are presented. This ADC is a building block of the very-front-end electronics dedicated to the electromagnetic calorimeter of the International Linear Collider (ILC). Based on a 1.5-bit resolution per stage architecture, it reaches the 10-bits precision at a sampling rate of 4 MSamples/s with a consumption of 35 mW. Integral and Differential Non-Linearity obtained are respectively within ±1 LSB and ±0.6 LSB, and the measured noise is 0.47 LSB at 68% C.L. The performance obtained confirms that the pipeline architecture ADC is suitable for the Ecal readout requirements.

I. INTRODUCTION

T HE Electromagnetic Calorimeter (ECAL) of the Inter- national Linear Collider (ILC) requires a performant very-front-end readout electronics which implies an ambitious R&D inside the CALICE collaboration [START_REF] Brinkmann | Tesla Technical Design Report, part II[END_REF]. This integrated electronics has to process 10 8 channels which deliver a 15-bits dynamic range signal with a precision of 8 bits. Moreover, the minimal cooling available for the embedded readout electronics imposed an ultra-low power limited to 25 µW per channel. This issue will be reached thanks to the timing of ILC which allows the implementation of a power pulsing with a duty ratio of 1% .

A key component of the very-front-end electronics is the Analog-to-Digital Converter (ADC) which has to reach a precision of 10 bits. In order to save the die surface of the chip and to limit the power consumption, one ADC will be shared by several channels. To fullfill this request, an ADC operating at a sampling rate of the order of one MSamples/s has been designed. This paper presents the design and the performance of a 35-mW 4-MSamples/s 10-bits ADC. After a description of the 1.5-bit per stage architecture, the gain-2 amplifier and comparator are detailed. Measurement results of the engineering samples fabricated in a 0.35 µm CMOS technology are then reported.

II. 1.5-BIT/STAGE PIPELINE ADC ARCHITECTURE

Among the various efficient ADC architectures developed and improved last tens years, the pipeline architecture is adapted to reach high resolution, speed and dynamic range with relative low power consumption and low component count. Typically, resolutions in the range of 10-14 bits at sampling frequency up to 100 MSamples/s are achieved in CMOS technologies with power lower than 100 mW [START_REF] Sumanen | A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter[END_REF]- [START_REF] Kurose | 55-mW 200-MSPS 10bit Pipeline ADCs for Wireless Receivers[END_REF]. The block diagram of a conventional m-bits pipeline ADC [START_REF] Van De Plassche | Integrated analog to digital and digital to analog converters[END_REF] with n output bits per stage is given in Fig. 1. Each stage consists of a sample-and-hold (S/H), a low-resolution n-bits flash sub-ADC, a substractor and a residue amplifier. This stage converts the input voltage into the corresponding n-bits code and provides the amplified residual voltage to the next stage. The complete m-bits system consists in piling up m stages and in adding an Error Correction Logic block which delivers the final digital code. The simplest architecture is designed with a resolution of 1 bit per stage. In such basic ADC, each sub-ADC is composed of one comparator, with the reference signal V REF fixed at the middle of the analog input dynamic ADC range, and the gain of the residue amplifier is 2. The algorithm for the i th stage is as follows: if

(V In ) i > V REF then b i = 1 and (V In ) i+1 = 2(V In ) i -V REF , else b i = 0 and (V In ) i+1 = 2(V In ) i ,
where (V In ) i is the input voltage of the i th stage and b i the output bit of this stage.

The accuracy of this type of ADC is limited by three main [START_REF] Cho | Low power, low voltage analog to digital conversion techniques using pipelined architectures[END_REF]- [START_REF] Lee | A 15-bit 1-Ms/s digitally self-calibrated pipeline ADC[END_REF] parameters :

• the interstage gain 2 accuracy limited by the gainbandwidth product of the amplifier and the mismatch of its feedback components; • the offset voltage of the comparators caused by the mismatch of components of its input stage; • the thermal noise which varies between samples. The noise contribution of the sampling in each stage, represented by the kT /C expression, is generally predominant but this noise contribution of a latter stage is effectively attenuated by the gain of the previous stage. An architecture with a resolution of 1.5 bits per stage is a solution to attenuate the contributions of the gain error and offset voltage to the non-linearity of the ADC. The Integral Non-Linearity (INL) obtained with algorithmic simulations is displayed on Fig. 2 ] i is delivered by each stage i. The corresponding algorithm is given by:

• if (V In ) i < V Low T h then [b 2 b 1 ] i = [00] and (V In ) i+1 = 2(V In ) i+1 • if V Low T h < (V In ) i < V High T h then [b 2 b 1 ] i = [01] and (V In ) i+1 = 2((V In ) i -V Low Ref ) • if (V In ) i > V High T h then [b 2 b 1 ] i = [10] and (V In ) i+1 = 2((V In ) i -V High Ref )

III. SCHEMATIC OF ONE STAGE

The global schematic of one ADC stage with resolution of 2 bits is given on Fig. 4. In order to reject the common mode noise, a fully differential structure has been adopted. In the very-front-end electronics of the electromagnetic calorimeter of ILC, the differential mode is particularly relevant considering the presence in the chip of a digital electronics which could induced common mode noise into the analogue part. Since the captor delivers a common mode signal, a commonmode to differential-mode conversion is required before the digitalisation stage. This interface should be inserted as soon as possible during the analogue processing of the signal in order to take advantage of the improvement signal-to-noise induced by the differential mode.

As represented on Fig. 4, the value of the reference signal added to the (V In ) i input signal is selected by comparators outputs through switches. Then the circuit operates on two clock phases: during the sampling phase, the input signal and the reference signal are summed through capacitors 2C, while during the hold phase, the summed signal is amplified by factor 2.

A. The gain-2 amplifier

The gain-2 amplifier is built with a differential amplifier and a capacitive feedbacked loop. A better matching is obtained with capacitors and they have been preferred to resistors [START_REF] Hastings | The art of analog layout[END_REF]. This matching is particularly important because it affects the precision of the gain 2, and therefore, the linearity of the ADC. Thus, feedback capacitors must be large enough to minimize both the thermal noise kT /C and the components mismatch proportional to 1/ √ C. In contrast, both the small die surface and the dynamical performance achieved with low supply current have to be carry out. Then capacitors values of 300 fF and 600 fF are used. To match these components with the precision required of 0.1%, the capacitors array has been drawn using a common-centroid layout composed of six poly-poly capacitor unit cells of 300 fF each. Dummy switches have been introduced in order to counterbalanced the parasitic capacitors introduced by the reset switches.

B. The operational amplifier

As represented in Fig. 5, the operational amplifier is based on a fully differential architecture with rail-to-rail inputs and outputs [START_REF] Gharbiya | Operational Amplifiers rail to rail input stages using complementary differential pairs[END_REF]- [START_REF] Kaiser | Introduction to CMOS analog integrated circuit[END_REF]. It includes a resistive Common Mode FeedBack circuit (CMFB) to control the common mode output voltage. This table shows that despite a large gain-bandwidth product of 50 MHz, the consumption is limited to 1.9 mW with a 5V power supply. The design of the differential amplifier must guarantee a stable behaviour of the gain-2 feedback amplifier over process parameters fluctuations. Both differential output signal and common mode output signal must be stable with a total load capacitance evaluated to 1 pF. On that purpose, a pole-zero compensation network is connected at the differential output and its parameters adjusted. Then, stability simulations give a phase margin better than 66 degrees for both differential and common mode signals. Statistical simulations with process parameters fluctuations give standard deviation of 3 degrees and 5 degrees respectively for differential and common mode phase margins.

A M P L I F I E R V R E F l o w - g n d 2 C C l o c k 2 C 2 C 2 C C C + - V R E F h i g h - V R E F l o w + g n d V R E F h i g h + V i n + V i n - V T H l o w - V T H l o w + C O M P . + - + - C l o c k V T H h i g h - V T

C. The comparator

As represented on Fig. 6, the comparator consists on a latched comparator [START_REF] Crolla | A fast latching current comparator for 12-bit A/D applications[END_REF] followed by a dynamic memory. This architecture is fully differential with two differential inputs: one for the differential signal (V In ) i from the previous stage and one for the differential reference signal. However, for simplicity, only one differential input is represented in Fig. 6. The very high impedance of the load represented by the latch gives the very high sensitivity of this comparator. The high gain is reached when the switch of the latch is open, leading the latch output to switch into a logical state corresponding to the sign of the differential input voltage namely (V In ) i -V Ref . The intrinsic sensitivity of this comparator is so high that the sensitivity is finally dominated by the input comparator noise.

The characteristics of the designed comparator are summarized on the table II. The code occurence histogram at the code value of 512 is given in Fig. 9. All the codes delivered are included into 512 ± 1 LSB, with about 90% of them at the center value. At a sampling rate of 4 Msamples/s the dissipation of the chip is 35 mW. With a time of 250 ns to convert one analogue signal and considering the number of events stored per channel to be less than 5, the power consumption integrated during the ILC duty cycle of 200 ms is evaluated to 0.22 µW /channel. Assuming that the ON-setting time and the pipeline latency of the convertion are neglected when the ADC is shared by tens of channels, the integrated power dissipation of the ADC is then limited to 1 % of the total power available for the very front-end electronics of the ECAL.

V. CONCLUSION

A 10-bit 4-MSamples/s 35-mW CMOS ADC based on a pipeline 1.5-bit/stage architecture has been designed and tested. Its performance confirms that this architecture fullfill the ADC requirements of the ECAL at ILC. Nevertheless, such results can not be obtained without the efficient comparator and amplifier presented in this paper. These building blocks have been optimized to fulfill the offset, sensitivity, speed and stability requirements with low power consumption. Their schematics are as simple as possible in order to improve integration and reliability. Bearing in mind that the comsumption is a key point, the next step will consist on a portage in 3V supply.

AFig. 1 .

 1 Fig. 1. Conventional m-bits pipeline ADC architecture with n bits delivered per stage.

Fig. 2 .Fig. 3 .

 23 Fig. 2. 1.5-bit/stage ADC: variation of INL as a function of offset voltage Voff on comprarators.

  and Fig 3. The Integral Non-Linearity refers to the deviation, in LSB, of each individual output code from the ideal transfert-function value. Fig 2 shows that, for an input dynamic range of 2V, the INL of the ADC is not affected by the offset voltage V of f of the comparators up to ±250 mV. Moreover, as reported in Fig 3, the precision is less sensitive to the gain 2 accuracy with the 1.5-bit/stage architecture compare to a basic 1-bit/stage one. This 1.5-bit/stage pipeline ADC architecture [9] involves two comparators per stage, with separate threshold voltages V Low T h and V High T h , and two reference voltages V Low Ref and V High Ref . A 2-bits word [b 2 b 1

1 b 2 Fig. 4 .Fig. 5 .

 1245 Fig. 4. Simplified schematic of one ADC stage: 2 comparators give the output bits of the stage and determine the reference signals substracted to the input signal; the amplifier amplifies by a factor 2 the redidual voltage and delivers it to the next stage.

Fig. 9 .

 9 Fig. 9. ADC code occurence histogram at the code centre

TABLE I OPEN

 I LOOP AMPLIFIER CHARACTERISTICS.

	Power supply	5.0 V
	Consumption	1.9 mW
	Gain-Bandwidth	50 MHz
	Differential phase margin	66 ± 3 degrees @ 68% C.L.
	Common Mode phase margin	66 ± 5 degrees @ 68% C.L.
	The main characteristics of the open loop amplifier are
	reported in the table I.

Code INL (LSB)

Fig. 8. Integral nonlinearity measurement

IV. MEASUREMENT RESULTS

A 10-bits ADC prototype has been fabricated using the Austriamicrosystems 0.35 µm 2-poly 4-metal CMOS process. The total area of the ADC is 1.35 mm 2 and the chip is bounded into a JLCC 44 pins package. The circuit is measured with a 5.0 V supply and a differential input swing of 2.0 V pp , at a frequency clock of 4 MHz.

Main performance is reported on table III. A dynamic input range of 2.0 V is measured with zero and gain errors respectively of 0.5 % and 0.8 % of the full scale. The standard deviation of the noise is lower than 0.5 LSB at 68% C.L.

The static linearity curves of the 1.5-bit/stage ADC are given in Fig. 7 and Fig. 8. The Differential Non-Linearity (DNL) is displayed in Fig. 7. This error is defined as the difference between an actual step width and the ideal value of one LSB. The DNL measured is