Nicolas Duchaux
email: nicolas.duchaux@telecom-bretagne.eu

Cyril Lahuec

Fabrice Seguin

Matthieu Arzel

Michel Jézéquel

Effect of BJT's parasitics on computing cells for analog decoders

This paper analyses the effect of inherent bipolar transistor parasitic elements over the computing nodes performance used in BJT analog decoders. It is shown that these undesirable effects significantly degrade, up to 85%, the conversion of Log-Likelihood Ratios into probabilities. This can lead to a wrong decoding outcome when complex computing nodes are designed. Simulation results are shown for a 0.25-µm BiCMOS process from NXP. I.

INTRODUCTION

Several works have been published over the last 15 years on analog decoding. Most of them are dealing with Turbo and LDPC codes [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF][START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF][START_REF] Gaudet | A 13.3-Mb/s 0.35µm CMOS analog turbo decoder IC with a configurable interleaver[END_REF][START_REF] Gioulekas | A high-speed SiGe BiCMOS analog MAP decoder[END_REF][START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF] and few with exotic codes such as Cortex codes [START_REF] Chamorro | Cortex codes and analogue decoding[END_REF]. All these codes however can be decoded using two mathematical operators which are the addition and the multiplication. The operands are probabilities which are simply extracted from an additive white gaussian noise (AWGN) channel using the exponential I-V characteristic of a forward-biased BJT or a subthreshold-biased MOS transistor. The latter is preferred for power issues and the former for speed issues. Hence, it exists two ways of implementing the computing nodes. The majority of the papers published on the design of analog decoders refers to MOS designs such as [START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF][START_REF] Gaudet | A 13.3-Mb/s 0.35µm CMOS analog turbo decoder IC with a configurable interleaver[END_REF][START_REF] Gioulekas | A high-speed SiGe BiCMOS analog MAP decoder[END_REF] and few deal with BJT designs [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF] [START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF].

When comparing simulated and actual decoding performance in terms of Bit-Error Rate (BER) most works show discrepancies [START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF][START_REF] Gaudet | A 13.3-Mb/s 0.35µm CMOS analog turbo decoder IC with a configurable interleaver[END_REF][START_REF] Gioulekas | A high-speed SiGe BiCMOS analog MAP decoder[END_REF][START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF] between the two, except in [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF] for which there is a good agreement. The performance degradation ranges from few hundredths of dBs [START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF][3] [START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF] up to few dBs [START_REF] Gioulekas | A high-speed SiGe BiCMOS analog MAP decoder[END_REF]. The reason for this is that the behavioral models used describe the decoding algorithm, not the functioning of the decoders. However, very few of these papers attempt to explain the origin of the discrepancies. [START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF] showed, using behavioral modeling, that the origin of the loss was due to mismatches in MOS current mirrors. An interesting point is that the BJT decoder designed in [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF] performs as well as its model while the more complex decoder designed in [START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF] is 0.3dB away from its ideal performance. This suggests a link between complexity and performance degradation. The decoder in [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF] decodes a simple binary code and uses simple Gilbert multipliers while in [START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF] the double-binary code to decode requires m-ary multipliers [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF] (having more than two differential inputs).

Hence, this paper addresses the effect of parasitic emitter resistors over the computing cell used in BJT-based analog decoders. The paper presents results for multipliers used to decode simple binary and double-binary codes. It is shown that while for the former the parasitic elements modify the probabilities they do not change their ranking order. For the latter, they can actually invert that ranking therefore potentially introducing additional decoding errors.

The paper is organized as follows. Section II presents the basic multiplier cell. Section III deals with the effect of the BJT's parasitic emitter resistor over the LLR-to-probability conversion and how it affects simple Gilbert multipliers. The result is extended to m-ary multipliers with a case study in section IV. Section V concludes the paper.

II. BASIC COMPUTING CELL

A. Converting LLRs into probabilities

A convolutional circular binary code can be decoded with the Maximum A Posteriori (MAP) algorithm [START_REF] Anderson | Tailbiting MAP decoders[END_REF]. It uses only two mathematical operators (addition and multiplication) and two functions (logarithm and exponential). The last two are necessary for converting log-likelihood ratios (LLR) to probabilities and vice-versa. If X is a binary random variable and x its outcome, the LLR of X, L(X), is defined as:

( ) ( )         = = = 0 1 ln ) ( x P x P X L X X (1)
The exponential and the natural logarithm functions are readily available from a forward active region BJT. Using the well known Ebers-Moll model, the collector current IC depends on the base-emitter voltage VBE:

T BE V V S C e I I ≈ (2)
where IS is the saturation current and VT is the thermal voltage. When diode connected, the BJT produces a voltage V which depends on the current I flowing through it:

        = S T I I V V ln (3)
Associating a current with a probability and a voltage with an LLR, it is thus possible by using transistors and diodes to convert LLRs to probabilities, equation ( 2), and probabilities to LLRs, equation [START_REF] Gaudet | A 13.3-Mb/s 0.35µm CMOS analog turbo decoder IC with a configurable interleaver[END_REF], respectively. This is a clear advantage of analog decoders over digital decoders since currents, representing the probabilities, can be easily added and multiplied. Thus, the MAP algorithm can be implemented using a BJT-based analog network [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF].

B. Multiplying and adding probabilities

The Gilbert multiplier shown in Fig 1 is use to perform both the LLR-to-probability conversion and the probability multiplication. If one considers that both input voltages are proportional to LLRs, then the collector currents I C1 and I C2 are proportional to P X (x=1) and P X (x=0) respectively. The proportionality constant is the bias current I BIAS . Since the upper pairs are biased with a current proportional to a probability, I C1 and I C2 , then the collector currents of Q3-Q6 are each proportional to a product of probabilities: Adding product of probabilities is then simply a matter of connecting wires together as shown in Fig. 1.

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) BIAS Y X C BIAS Y X C BIAS Y X C BIAS Y

III. BJT'S NON-IDELATIES

A. Parasitic emitter resistor

The Gilbert multiplier functioning described above assumes ideal BJTs, i.e. it supposes that they are fully described by the Ebers-Moll model defined by equation ( 2). However, a parasitic element, which is usually underestimated, may significantly alter the conversion of LLRs into probabilities. When the parasitic emitter resistor R E is taken into account the collector current is more accurately defined as:

T C E T BE V I R V V S C e e I I - ≈ (5)
The value of R E is inversely proportional to the area of the emitter. One may consider that designing with large BJTs will make R E negligible. Unfortunately, to compete with the ever-shrinking digital decoders, it is preferable to design with the smallest BJT available in the process. For instance, in NXP's QUBIC4 0.25-µm BiCMOS process, the parasitic R E is around 220Ω for the smallest available BJT.

The problem becomes even more acute when the biasing current is a few hundreds of µA. This is chosen to correctly bias the cell and to increase the decoding speed. Fig. 2 represents the output probability ratio, i.e. the ratio of the two simulated collector currents I C1 and I C2 , versus the input probability ratio, i.e. exp(VX/VT). Ideally, the obtained curve should be a straight line with a slope of 1. As one can see the result is far from the ideal case and the conversion error is as high as 85% for an input LLR of 100. Hence the usual assumption of having an ideal exponential relationship between the collector current and the base-emitter voltage is absolutely incorrect. It is interesting to see the actual contribution of R E to this error. This can be done by adding an ideal resistor R EC such as R EC = -R E at each transistor emitter in the Gilbert cell. Hence, each parasitic R E is fully compensated and the output probability ratio should get closer to the ideal one. As seen from Fig. 2, R E is the main source of conversion error as it would be reduced down to 20% by compensating the parasitic resistors. The simulation also shows that other effects impair the conversion but that they are less important.

B. Probability ranking

A question arises from the above discussion, is this really a problem for the decoder? It is known that in digital decoders, the value of the probability is voluntarily truncated to speed up the turbo-decoding process without degrading the overall performance. The degradation observed in Fig. 3 can be interpreted as such. The output probability I C6 /I BIAS is plotted versus the lower input voltage V X (V Y = 0, I BIAS = 250µA). The probability is reduced for positive values of V X (probability of having a "1") and increased for negative ones (probability of having a "0"). The degradation is more important around zero; that is to say for cases harder to solve for the decoder. Simulations show, however, that the ranking of the four output probabilities, equation ( 4), is not modified compared to the ideal case. It simply means that on a single stage, no error is introduced. This most likely explains in [START_REF] Moerz | An analog 0.25-µm BiCMOS tailbiting MAP decoder[END_REF] the performance matching between of the ideal behavioral model and of the actual decoder.

IV. M-ARY CASE

A. Extended multiplier

The above section described the implications when dealing with simple multipliers. How does this problem affect m-ary computing cells? M-ary computing cells are described in [START_REF] Arzel | Analogue decoding of duo binary codes[END_REF]. The Gilbert cell shown in Fig. 1 can be extended to a larger field of probability multipliers as illustrated in Fig. 4. The lower stage is an emitter-coupled set of bipolar transistors whose bases are connected to n X voltages V X which are proportional to the log-likelihood ratio of the data x. The upper stage is made up of n X identical emitter-coupled bipolar sets, each of them being connected to a different collector on the lower level. Thus, the outputs are n X × n Y currents I out k given by:

( ) ( ) [ ] [ ]      ∈ - ∈ = + × y x BIAS j Y i X out j n i n j n i I y P x P I y , 1 1 , 0 (6)
Unlike in the binary case previously studied, it may happen that not all the output currents are necessary to implement the decoding algorithm. This type of cases happens in fact quite often when designing double-binary decoders. For instance, this happens in the module computing the four probabilities (one per double-binary symbol) on which the hard decision is taken [START_REF] Lahuec | Design and test of a 0.25µm-BiCMOS double-binary analogue APP Decoder[END_REF]. For the sake of simplicity, the double-binary symbols d are noted as follows: "00" →0, "01" →1, "10" →2 and "11"→3. A multiplier having eight inputs, P X (x i ) and P Y (y i ) for i ∈ [0, 3], and requiring only four outputs, Pr(d=i) for i ∈ [0, 3], out of the sixteen available is simulated. The fact that not all the output currents are used implies renormalization. So the symbol probability is given by: ( ) ( ) ( ) ( ) ( )

∑ = = = 3 0 Pr i i Y i X i Y i X y P x P y P x P i d (7)
A case, shown in Fig. 5, is taken as an example to better explain what can happen. Fixing some to an input probability of 0 reduces the number of inputs: ( ) ( )

2 0 0 ≥ ∀      = = i y P x P i Y i X (8) hence: ( ) ( ) ( ) ( ) 0 1 0 1 1 1 y P y P x P x P Y Y X X - = - = (9)
Rearranging equations ( 7), ( 8) and (9) yields:

( ) ( ) ( ) ( ) ( ) ( ) ( ) 1 1 1 1 ) 1 Pr( 1 1 ) 1 Pr( 1 ) 1 Pr( x P d x P d x P d y P X X X Y = - + - = - = = (10)

B. Probability ranking

From equation (10), fixing the symbol probability makes P Y (y 1 ) only a function of P X (x 1 ). For instance, by fixing Pr(d=1) to 55% and varying P X (x 1 ), one can plot the simulated output probabilities Pr * (d=1) and Pr * (d=0) taking equation (5) into account. If the multiplier were ideal, then Pr * (d=1) and Pr * (d=0) would remain at 55% and 45%, respectively. However, as shown in Fig. 6, it is not the case and even worse, the outcome can be inverted. The most likely symbol can become "00" (d=1) instead of "01" (d=0). Hence, unlike in the binary case, the multiplier may well introduce additional errors, thus degrading the decoder's performance in terms of BER.

V. CONCLUSION

This paper showed how the bipolar transistor's parasitic elements introduce a significant degradation when converting data from the channel, LLRs, into probabilities. It is shown that the most degrading element is the parasitic emitter resistor. This work shows that this is more a problem when decoding m-ary codes than binary codes. Indeed, for doublebinary codes, there is a possibility to invert the probability ranking. As the decoding algorithm to output the decoded bits uses probabilities, errors can be introduced. This suggests that complex decoders require additional circuits to counteract the effect of parasitic elements.

Figure 1 :Figure 2 :

 12 Figure 1: BJT Gilbert multiplier, two input voltages and four output currents.

Figure 3 :

 3 Figure 3: Degradation of output probability of the Gilbert multiplier due to parasitic effects (transistor level simulation). The curve is plotted versus the lower differential-pair input voltage VX when VY=0. NXP's QUBIC4 0.25µm BiCMOS process, smallest BJT and IBIAS =250µA.

Figure 4 :

 4 Figure 4: Extended Gilbert cell for m-ary code, nx + ny inputs, nx x ny currents.

Figure 6 :

 6 Figure 6: Inversion in the ranking of output probability in a 4:4:4 multiplier. PX(xi) and PY(yi) equal 0 when i = 3 or 4. NXP's QUBIC4 0.25µm BiCMOS process.


Matthieu Arzel

Fabrice Seguin

Cyril Lahuec

Michel Jézéquel

Semi-Iterative Analog Turbo Decoding

This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and re-configurability. The architecture is applied to a DVB-RCS-like code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm² 0.25µm BiCMOS decoder can then decode any frame length from 40 up to 1824 bits.

I.

INTRODUCTION

Analog decoding has been plagued by the prohibitively large chip area required to implement decoders for long frame lengths and their lack of re-configurability. This increase in occupied chip area is due to the fact that the decoder usually has as many decoding sections as symbols to decode in a frame. This explains why most of the papers published so far deal with non-industrial codes. Only recently, three decoders have been proposed for industrial standards: UMTS (3GPP) in [START_REF] Vogrig | A 0.35-µm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code[END_REF], IEEE 802.16a standard in [START_REF] Winstead | Analog iterative error control decoders[END_REF] and DVB-RCS-like codes in [START_REF] Arzel | Analog slice turbo decoding[END_REF]. Only the first two were implemented on chip and tested; the third one was only simulated. Nevertheless, these decoders were designed in order to tackle some of the shortest frame lengths of their targeted standard and are not re-configurable.

A possible solution to this size increase was introduced in [START_REF] Moerz | Analog sliding window decoder for mixed signal turbo decoder[END_REF]: sliding windows. In this architecture, the turbo decoder "sees" only a small portion of the frame to decode at a time, thus reducing the number of implemented decoding sections. A clear advantage of this solution is that the decoder is able to decode any frame length. However, in this architecture, while the computation of the extrinsic information is done by an analog core, the continuous exchange of extrinsic information between the two constituent decoders is lost. The exchange of extrinsic information is done iteratively. Moreover, the scheme requires data converters which are notoriously power hungry and slow. This paper proposes an alternative solution which offers significant on-chip area reduction, keeps a (partial) continuous exchange of extrinsic information to help with convergence [START_REF] Arzel | Analog slice turbo decoding[END_REF] CRSC Encoder

Π

k m p = ´k m p = ḿ m ( ) n k p - (n k) - (n k) - ( ) n k p - Figure 1. A p-slice turbo encoder.
and is re-configurable: semi-iterative analog turbo decoding.

As an example, the semi-iterative architecture is applied to design a double-binary turbo decoder. A comparison in terms of size and performance is done between the fully-parallelized analog slice decoder as presented in [START_REF] Arzel | Analog slice turbo decoding[END_REF] and its equivalent semi-iterative analog decoder.

The paper is organized as follows. Part II deals with conventional design using slices. Part III presents the semiiterative analog decoder with the help of a simple example. Part IV explains how re-configurability can be easily implemented with this architecture. Part V compares the two types of decoders in terms of area and discusses the on-chip area reduction achieved. Finally, part VI presents some simulation results.

II. CONVENTIONAL DESIGN USING SLICES

Fully-parallelized analog slice turbo encoding/decoding was presented in [START_REF] Arzel | Analog slice turbo decoding[END_REF] and it will be briefly explained here. In this scheme, a frame of length k is sliced down into p shorter ones of equal length m=k/p. As shown in Fig. 1, the resulting sub-frames are independently encoded by a circular recursive systematic convolutional (CRSC) encoder. The overall frame is then interleaved, sliced and encoded by the second encoder. The complete decoder is made up of 2p elementary APP decoders, two per slice to decode. In [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF], an elementary APP decoder was designed for a frame length of 24 double-binary symbols and was used to design the 48 double-binary symbols slice turbo decoder proposed in [START_REF] Arzel | Analog slice turbo decoding[END_REF]. Implementing the turbo decoder this way only facilitates its design. This solution does not yield a surface reduction due to the number of elementary decoders required to decode a long frame. The only way to achieve a significant area reduction is to reduce the parallel processing of the data as in the architecture presented below in the following section.

Π -1 Π Y 1 1 + Y 1 2 S y s t 1 + S y s t 2 Y 2 1 + Y 2 2 E x tr 1 n E x tr 2 n M U X in 4 M U X in 1 M U X in 2 M U X e xtr2 M U X e xtr1 M U X in 3 M U X M E M 1 M U X M E M 2

III. SEMI-ITERATIVE DECODING

The architecture of the semi-iterative decoder is shown in Fig. 2. It fully exploits the slicing technique to reduce the required number of elementary decoders to two, regardless of the number of slices. Analog memories, implemented as trackand-holds, and multiplexers are added to the structure. The decoding process is iterative and performs turbo iterations. The number of iteration depends on the performance sought for. Each turbo iteration is divided into steps. There are as many steps as slices. Turbo iterations and steps are detailed next.

For the sake of simplicity, a 2-slice example is taken, Fig. 2. The slice decoders are APP decoders. This example performs the same decoding as presented in [START_REF] Arzel | Analog slice turbo decoding[END_REF]. Before the decoding process begins, the full frame is received and stored. The extrinsic memories A and B in Fig. 2 In the meantime, the second slice decoder provides the extrinsic data Extr 21 (linked to the interleaved Syst 1 , Π(Syst 1 )). Extr 21 data are tracked by the first half of extrinsic memory bank B, the second half being filled in with equiprobable data. The Extr 21 data are deinterleaved before being fed back to the first decoder as in a usual turbo scheme. The loop is now closed and there is a continuous exchange of information between the two decoders. The extrinsic data eventually converge to stable values, at which stage they are held in memory and the next step can start.

Step 2

During step 2, all the multiplexers have switched from one input set to the other and the second slice is fed to the decoder that is: Syst 2 , Y 12 , Y 22 . The only difference with step 1 lies in the content of the memories which now contain the extrinsic data Extr 11 and Extr 12 computed during step 1. This further enhances the decoding of the second slice since the two decoders benefit from the extrinsic data computed for the first slice.

Once the first turbo iteration has been performed, the whole frame is decoded. However, it is better to run at least another turbo iteration to improve the overall result. This is necessary since during decoding step 1, the decoders did not benefit from any extrinsic data relative to the second slice. This second turbo iteration will eventually modify Extr 11 and Extr 12 and make them converge toward more reliable values. The number of turbo iterations can be increased but, as in a digital decoder, it is not necessary to run more than half a dozen to get the best results. This was confirmed by running behavioral simulations. As can be seen from the above example, the iterative process introduced by this architecture does not affect the continuous exchange of extrinsic information which helps with convergence [START_REF] Arzel | Analog slice turbo decoding[END_REF]. This is a key feature of the semi-iterative decoder.

The architecture can be easily extended to any number of slices p; a turbo iteration is then composed of p steps and during each step the semi-iterative analog decoder processes 1/p of the overall data. Providing that the slice length remains the same, the slice decoder need not to be redesigned. Only the multiplexers and the memories have to be changed. MUX extr1 and MUX extr2 are p to 1 multiplexers and MUX MEM1 and MUX MEM2 are 1 to p multiplexers. The number of memory cells in either memory bank A or B is p, the number of slices, times m, the number of extrinsic data to store per slice. This increase in the number of storage elements is much smaller than that of duplicating the elementary decoder in the case of a fully parallelized architecture as shown in part V. The hardware required to decode large frame length is thus significantly reduced.

IV. RECONFIGURABILITY

An important aspect required by industry is the capability of a single-chip decoder to accept various frame lengths. When using slices this can be easily implemented. First, the elementary slice decoder must be designed for the longest slice length. Since the code is circular, the slice decoder is implemented as a ring. It is fairly easy to reduce the ring size depending on the slice length by means of switches as shown in Fig. 3. The ring size is selected by means of an N-bit word: sel_size. Second, the extrinsic analog memory blocks and the multiplexers represented in Fig. 3 must be sized up according to the longest slice length. Then, when working with a shorter frame length only the memory accesses have to be changed. To complete the scheme, programmable interleavers as in [START_REF] Gaudet | Programmable interleaver design for analog iterative decoders[END_REF] can be used.

V. AREA STUDY

The architecture is now applied to decode a DVB-RCS-like code, with frame length between 20 and 912 symbols. The comparison is made for two types of decoders designed for the same 0.25µm BiCMOS process: a fully-parallelized decoder and a semi-iterative one. The area estimations for a decoding section and a memory cell are based on the double-binary decoder circuit designed in [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF]. Referring to Fig. 2 and Fig. 4, the size of the decoder elements are given next as a function of the number of slices p and the number of systematic data per slice m.

Common to both decoders are the elementary APP decoder and the input memory cells. A decoding section has an area of L×l=0.124mm²; details about its design are given in [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF]. The elementary decoder area is thus L×l×m. The area of a single input memory cell is 2565µm². It is made of two track-andhold circuits put in parallel. While the first one holds the previous input value, the second samples the next frame. There are 2(p×m) memory cells for the systematic part and 2(p×m) cells per redundant part for a coding rate of one half.

An extra feature of the semi-iterative decoder is the extrinsic memory. Each decoding section deals with a doublebinary symbol. Each of its four possible values are weighted by an extrinsic probability. The four extrinsic data output per decoding section are needed by the other decoder and thus each is stored in a memory cell which has an area a² = 625µm². Hence, the total area of the extrinsic memory cells is given by 2×4×p×m×a².

area (mm²)

Fully-parallelized decoder Semi-iterative decoder Figure 6. Area comparison, element wise, fully-parallelized decoder as in [START_REF] Arzel | Analog slice turbo decoding[END_REF] vs semi iterative decoder for a 864 double-binary symbol frame length (0.25µm BiCMOS process).

semi-iterative architectures versus the number of required slices. In this figure, the interleavers are hard-wired using four metal layers. Taking the example of implementing the turbo decoder for the longest frame length of the DVB-RCS standard, i.e. 864 double-binary symbols, a fully-parallelized slice architecture occupies a 265mm² area while the semiiterative requires only a 27mm² area. There is thus a reduction of on-chip area by a factor of ten! Fig. 6 details the area per decoder's elements required to decode the longest frame of the DVB-RCS standard with 24 slices. It clearly shows the dramatic area reduction, the biggest gain coming, of course, from the slice decoders area required. Other significant gains in area are shown for the input interleaver and the extrinsic interleavers. The area of the latter, which includes the extrinsic memories and the multiplexers, is 0.14mm², too small to appear in the figure. Finally, the input memories occupy, of course, the same area since for both decoders, the whole frame has to be stored in memory before the decoding can take place.

VI. SIMULATION RESULTS

In this section, a performance comparison between three decoders decoding 48 double-binary symbol frames using two slices is made. The first decoder is a digital slice decoder, it uses floating point number representation and runs for 5 iterations. The second decoder is the analog decoder presented in [START_REF] Arzel | Analog slice turbo decoding[END_REF]. It is fully parallel. The third decoder is a semi-iterative analog decoder. It runs for five turbo iterations. Behavioral simulations were run to obtain the Bit and Frame Error Rate curves shown in Fig. 7. As can be seen from this figure, the decoding performance of the semi-iterative analog decoder lies in between the performance of the fully parallelized analog slice decoder and the performance of the digital counterpart. Therefore, the proposed solution presents no significant performance degradation.

VII. CONCLUSION

This paper has presented a novel semi-iterative analog turbo decoding architecture. It offers a significant reduction in occupied on-chip area when compared to previous architectures with no significant performance degradation. This was made possible by reducing parallel processing using slices and at the price of introducing iterations. At each iteration, the semi-iterative process keeps a partial continuous exchange of extrinsic information to improve the decoding speed and the correction performance. This is a key feature of the semiiterative analog decoding which thus provides a good compromise between on-chip area and data rate. Finally, the semi-iterative architecture is fully re-configurable to allow a single 27mm 2 chip to treat different frame lengths, from 40 to 1824 bits as in the example of this paper.

S lic e D e c o d e r # 1 S lic e D e c o d e r # 2 E

 12 xtrin s ic M e m . A (a n a lo g ) Π E x trin s ic M e m . B (a n a lo g )

Figure 2 .

 2 Figure 2. Semi-iterative architecture, 2-slice example.

Figure 3 .

 3 Figure 3. Reconfigurable circular slice decoder. Decoding section as defined in [5].

Figure 4 .

 4 Figure 4. Semi-iterative architecture, element dimensions.

Figure 5 .

 5 Figure 5. Total on-chip area comparison vs slice number for a fully parallelized and a semi-iterative implementation. The point on each curve corresponds to the decoding of 864 double-binary symbols frames with 24 slices.

Fig. 5

 5 Fig. 5 compares the total turbo decoder area for two decoders implementing either the fully-parallelized or the

Figure 7 .

 7 Figure 7. Performance comparison (behavioral).

  are set to values representing equiprobable data. A two-slice encoding yields two sub-frames: |Syst 1 |Y 11 |Y 21 | and |Syst 2 |Y 12 |Y 22 |, with Y 21 and Y 22 resulting from the encoding of the interleaved frame, Π(Syst 1 Syst 2 ). With two sub-frames, each turbo iteration is made up of two steps. Mux extr2 selects half of them, which are used by the second slice decoder. Some of these data are being computed and tracked by the analog memories, and others have fixed values representing equiprobable data.

	memory bank A are then interleaved and multiplexer
	Turbo iteration:
	Step 1
	By means of multiplexers MUX in1 and MUX in2 , Syst 1 and Y 11 are fed to Slice Decoder #1. This decoder outputs the extrinsic data Extr 11 which are loaded into the analog memories. Since the extrinsic memories are
	sized up to equal the length of the overall systematic
	data, half of the memory remains at equiprobable
	values. All the extrinsic data loaded in extrinsic

This work was partly funded by Brest Métropole Océane under the "Fond de Concours au Développement de la Recherche"


Matthieu Arzel

Cyril Lahuec

Fabrice Seguin

David Gnaedig

Michel J Éz Équel

Analog slice turbo decoding

This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a slice architecture which enhances the design in terms of simplicity, robustness, testability and reusability. Transistor-level simulations show potential throughput up to 1.2Gb/s for a 2.8mW power consumption per information bit and per state in a 0.25µm BiCMOS process.

I. INTRODUCTION

Research interest has grown over the last decade for analog decoding due to its potential advantages over digital decoding techniques in terms of speed, power consumption and on-chip area reduction [START_REF] Moerz | An analog 0.25µm BiCMOS tailbiting MAP decoder[END_REF]- [START_REF] Winstead | CMOS analog MAP decoder for (8,4) hamming code[END_REF]. Few proposed circuits are targeting industrial standards: [START_REF] Amat | A full CMOS analog turbo decoder for UMTS coding schemes[END_REF] proposed a decoder for UMTS and in [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF] the first steps toward a DVB-RCS decoder were presented. Recently, a particular type of turbo code was proposed in [START_REF]Interaction channel for satellite distribution systems[END_REF]: the slice turbo code. In slice turbo codes, frames are split into shorter ones. [START_REF]Interaction channel for satellite distribution systems[END_REF] showed that it does not introduce performance degradation. Implementing the decoder for this type of turbo code allows to concentrate on the design of a single elementary decoder much smaller than the one required to decode the full frame length. Thus, this design is simplier, more easily characterized, more robust and reusable for different frame lengthes. In this paper, a first analog implementation of slice turbo decoder is proposed for the DVB-RCS standard. The paper is organized as follow. Part II presents the slice turbo architecture. In part III the performances of the Maximum A Posteriori (MAP) decoder designed in [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF] are reminded and the interleaving is descibed. Part IV presents some simulation results obtained form a behavioral model and transistor-level simulation of the slice turbo decoder.

II. SLICE TURBO ARCHITECTURE

The principle of slice turbo codes is illustrated in Fig. 1. A frame of length k is sliced into m parts. Each subframe, or slice, is encoded independently using the usual turbo scheme of two circular recursive systematic convolutive (CRSC) encoders and an interleaver [START_REF] Gnaedig | On multiple slice turbo codes[END_REF]. It is worth noting that the interleaving is done over the full-length k of the initial frame. The work presented in this paper deals with the shortest frame length of the DVB-RCS standard: 48 duo-binary symbols or 96 bits [START_REF]Interaction channel for satellite distribution systems[END_REF]. Therefore, each CRSC encoder in Fig. 1 encodes slices of 24 duo-binary symbols. The corresponding turbo decoder block diagram is illustrated in Fig. 2 received frame is fed at once to the decoder, thus there is no specific handling of data. This architecture is flexible since to accommodate for longer frame length, one simply has to increase the number of MAP decoders. Therefore, one only has to design a set of relatively small, robust and optimized MAP decoders to accommodate for any frame length of the standard. This greatly simplifies the design and the test of the overall decoder. More details are given in section III-A.

III. CIRCUIT DESIGN

A. Map design

The design of the MAP decoder was presented in [START_REF] Arzel | Analogue decoding of duo-binary codes[END_REF] and only its main features are recalled here for convenience. The decoder is implemented using extended BJT-based Gilbert cells with analog I/O interfaces. Frames of 24 duo-binary symbols (96 bits treated by couples) altered by a gaussian noise are decoded. The simulated throughput is 600Mb/s for a power consumption of 1.4mW per information bit and per state. Transistor level simulations were compared with behavioral ones: the designed decoder corrects the errors as expected (Fig. 3). This elementary MAP decoder is certified. Therefore it can be reused to decode longer frames in a slice scheme without testing each time the ability to correct errors.

B. Interleaver design

A critical part in the slice architecture is the design of the interleaver [START_REF] Gnaedig | On multiple slice turbo codes[END_REF].

IV. SIMULATION RESULTS

A. Transistor-level simulation

The full turbo decoder for two slices was simulated at the transistor level on the same frames used to test the MAP decoder. Fig. XX presents the correction of the same error treated by the MAP in Fig. 3. The presented output of one of the four MAP decoders benefits from the work of the others thanks to the exchange of extrinsic information through the interleaving network. The liability of the decision in the turbo case is better than in the MAP case. Indeed the difference between the most liable values and the others is greater in the turbo case than in the MAP one. The decoding speed can be estimated at XX, which is greater that the speed of a lonely MAP. The interleavers do not introduce latency but reduce decoding time in this case. Therefore the turbo scheme not only enhances error correction but speeds up decoding in an analog implementation. Graph of turbo Simulations enable estimating the power consumption of the decoding core at 2.8mW per information bit and per state. The need for power doubles as expected: each information bit is decoded by two MAPs (one in natural order and one in interleaved order).

B. Behavioral modeling and simulation

Behavioral modeling is necessary to evaluate the performances of the decoder in terms of Bit Error Rate (BER) and Frame Error Rate (FER) since to obtain these curves several thousands of frames need to be fed to the decoder. At transistor-level this is impractical due to long simulation time (over a week per frame!). Therefore, a behavioral model for the CRSC MAP decoder was developed in Simulink. Fig. 4 shows a behavioral simulation comparing the BER/FER performances of the analog slice turbo decoder and its digital counterparts: the DVB-RCS standard decoder and the proposed slice decoder. The digital decoders run for 15 iterations and uses floating point number representation to guaranty the best MAP decoding performances. This figure actually shows that the analog turbo decoder performs better than its digital slice counterpart by 0.1dB and as well as the DVB-RCS standard digital decoder. The authors think that there are two possible explanations for this result. First, there is a real benefit in continuously exchanging information between the CRCS decoders instead of doing it iteratively: the analogue way is better for the slice implementation. Second, greater the size of the encoded frame, and also the asymptotic gain of the code, better the correction performance. Therefore the standard decoder without slices benefits from a greater asymptotic gain which enables this to achieve the performance of the analog slice decoder. To conclude, the slice analog decoder offers the same error correction performance as the standard one without slice but with the advantages of analog implementations: greater speed, lower consumption and reduced latency.

V. CONCLUSION

A suitable analog turbo decoder architecture to tackle long frames was presented. Behavioral and transistor-level simulations validate the concept. The circuit is expected to be sent to the foundry soon.

Fig. 3 .

 3 Fig. 3. Correction of an error (due to a gaussian noise at 2.4dB) in a transistor level simulation.

Fig. 4 .

 4 Fig. 4. Comparison of the correction performance of the DVB-RCS standard digital decoder, the slice digital decoder and the slice analogue decoder for frames of 48 duo-binary symbols.

21 Extr 22 Extr 11 Extr 12 Fig

  . It requires four elementary MAP decoders in the present case, two per slice to decode. Each decoder treats one slice in natural order (MAP 11 and MAP 12) or in interleaved order (MAP 21 and MAP 22) with the corresponding redundancy bits. The full

							k/2	k/2
							Syst 1 Syst 2
	Syst 1 Syst 2		Encoder CRSC		k/2 Y 11	k/2 Y 12
			Π
				Encoder CRSC		k/2 Y 21	k/2 Y 22
	Syst 1 Syst 2	Syst 1		Syst 2
	Y 21 Y 11	Y 22 Y 12	Y 11	MAP 11	Y 12		MAP 12
		Π	Π -1				Π
				MAP 21	Y 21 Syst Π( )	1	MAP 22	Y 22 Syst Π(

k Fig. 1. A two-slice turbo encoder. 2 ) Extr . 2. A two-slice turbo decoder.