Quang-Linh Nguyen

Emanuele Valea

Marie-Lise Flottes

Sophie Dupuis

Bruno Rouzeyre

A Secure Scan Controller for Protecting Logic Locking

Keywords: IP Piracy, Design-for-Security, Logic Locking, Design-for-Trust, Scan Chains

The globalized supply chain in the Integrated Circuit (IC) industry raises several security concerns such as overproduction, IP piracy and Hardware Trojan insertion. Logic locking has emerged as a potential countermeasure to address these issues. However, its efficiency is challenged by various attacks, especially oracle-guided attacks based on Boolean Satisfiability (SAT) solvers. These attacks rely on the possibility for an attacker to control and observe in the field the internal state of a functional IC, which acts as an oracle. This ability to control/observe the IC states is offered by scan chains, typically used for IC production testing. In this paper, we propose a method, complementary to logic locking, to prevent such attacks. This method introduces a scan chain controller with a key-based authentication mechanism, in order to prevent unauthorized access to the scan chains once the IC is deployed in the field. The solution can be coupled with any logic locking technique at the cost of negligible area overhead. Furthermore, it is secure against state-of-the-art attacks and supports full testing.

I. INTRODUCTION

Intellectual property (IP) infringement is a well recognized problem in the semiconductor industry. This issue stems from the globalization of the supply chain. Ever-shrinking technologies have rapidly raised the cost of manufacturing Integrated Circuits (ICs). Therefore, outsourcing the fabrication process to offshore foundries has become a major trend [START_REF] Kumar | Simply Fabless![END_REF]. Besides, using commercial third-party IPs allows companies to reduce design effort and, hence, time-to-market. However, different actors in this segmented IC supply chain may violate agreements by overproducing ICs, inserting malicious hardware Trojans or illegally reusing out-of-contract IPs.

While former counterfeit detection techniques are based on long and expensive parametric tests performed on suspected ICs, numerous recent Design-for-Trust approaches introduce preventive mechanisms at design time: sensors detect die and IC recycling [START_REF] Zhang | Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs[END_REF]; IC camouflaging prevents reverse engineering [START_REF] Rajendran | Security analysis of integrated circuit camouflaging[END_REF]; hardware watermarking is used for demonstrating compliance with the ownership [START_REF] Kahng | Watermarking techniques for intellectual property protection[END_REF]; passive hardware metering, based on physical unclonable functions or digitally stored serial numbers allows IC identification. Last but not least, active hardware metering consists in locking each IC until a key is provided by the IP holder. This solution can be used at IP core level to restrict illegal IP reuse, and at system level to prevent IC overproduction and, to some extent, prevent hardware Trojan insertion.

Logic locking [START_REF] Dupuis | Logic Locking: A Survey of Proposed Methods and Evaluation Metrics[END_REF]- [START_REF] Shamsi | IP Protection and Supply Chain Security Through Logic Obfuscation: A Systematic Overview[END_REF] is an active hardware metering technique dedicated to combinational structures. This approach consists in modifying the original netlist with additional logic controlled by additional key inputs. The modified design behaves as the original one only upon the application of the correct key value at the key inputs; otherwise, it outputs erroneous values. Only the designer who applies logic locking to the design knows the correct key value. When the modified design is sent to outsourced services for fabrication, test and packaging, the produced ICs are "locked" to an incorrect functionality, and thus unusable, until they are sent back to the designer for activation. The ICs are "unlocked" when the designer programs the correct key value in their tamper proof memory. Traditional logic locking techniques insert key-gates such as XOR/XNOR gates or multiplexers [START_REF] Rajendran | Fault Analysis-Based Logic Encryption[END_REF]- [START_REF] Karmakar | On Finding Suitable Key-Gate Locations In Logic Encryption[END_REF]. Key-gate locations can be random or strategic, for example, to avoid key recovery through netlist analysis or to maximize corruption.

Logic locking methods have been challenged by various oracle-guided attacks aiming at recovering the secret key. The attack model requires the access to two fundamental assets:

• a locked netlist, i.e. the reverse-engineered netlist containing the logic-locking structure; • an oracle, i.e. an unlocked IC with accessible scan chains. Sensitization attacks [START_REF] Rajendran | Security analysis of logic obfuscation[END_REF] identify the correct key bits by analyzing logic cones and sensitizing each key bit to observable outputs. This task requires that the targeted logic cones' inputs are controllable (Primary Inputs (PIs) or scan Flip-Flops (FFs)) and their outputs are observable (Primary Outputs (POs) or scan FFs). The attack can be prevented by making the sensitization of each key bit dependent on the other key bits.

Oracle-guided attacks using the Boolean Satisfiability (SAT) solver are, by far, the most effective attacks [START_REF] Subramanyan | Evaluating the security of logic encryption algorithms[END_REF]- [START_REF] Azar | SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks[END_REF]. They exploit the reasoning capability of a SAT solver to quickly eliminate wrong key values. A preliminary requirement of such attacks is to model the circuit as a Direct Acyclic Graph (DAG). However, combinational circuits can be interpreted as DAGs whereas sequential circuits cannot. A sequential circuit is modelled as a combinational circuit by converting internal FFs' outputs into pseudo-primary inputs (PPIs) and their inputs into pseudo-primary outputs (PPOs). Key values are correlated and grouped into equivalence classes. In each iteration, the attack chooses two key values from two classes and finds a so-called Distinguish Input Pattern (DIP) that results in different output values for the two key values when applied to the locked netlist. This DIP is then applied to the oracle to obtain the correct output. By comparing the different outputs, the attack is able to suppress at least one class of key values, which may contain multiple values. The key search space is reduced iteratively until the SAT solver deduces the correct key.

Existing countermeasures against SAT-based attacks focus mainly on increasing the number of iterations of the attack [START_REF] Yasin | SAR-Lock: SAT attack resistant logic locking[END_REF], [START_REF] Xie | Mitigating SAT Attack on Logic Locking[END_REF]. However, such solutions provide very low output corruption. For each wrong key value, only one (or very few) input pattern results in incorrect output. Furthermore, the additional locking structure is greatly distinguishable from the original netlist and, thus, can be easily removed [START_REF] Yasin | Removal Attacks on Logic Locking and Camouflaging Techniques[END_REF].

As mentioned above, most attacks on logic locking are based on the opportunity to control the inputs and to observe the outputs of the combinational block under attack. Because combinational blocks are generally surrounded by sequential elements (i.e. FFs) for synchronisation, all previous works assume that internal FFs of the unlocked IC can be accessed. This is possible since original FFs are generally replaced by scan FFs for production test purpose. Scan design is indeed a fundamental Design-for-Testability approach [START_REF] Wang | Design for Testability[END_REF] where scan FFs are linked together to form shift registers, so-called scan chains. A scan chain's input is a fully controllable PI and its output is a fully observable PO. By running shift operations in the scan chain, data stored into scan FFs can be read and modified. In addition, scan FF outputs and inputs are considered as the combinational part's PPIs and PPOs respectively. This allows test generation tools to model sequential designs as combinational, which decreases the test generation complexity. As the access to scan chains satisfies the model requirement of mentioned attacks on logic locking, they can be prevented by including an authentication step to block scan shift operations performed by the attackers.

In this paper, we present a scan solution that guarantees full testability without compromising the security of logic locking. We propose a scan controller that limits the scan access only to authorized users. We provide suitable logic locking techniques to combine with the proposed solution. A security analysis shows its capability to prevent SAT-based attacks on logic locking. Furthermore, we analyse potential attack schemes on the scan controller.

The rest of the paper is organized as follows. Section II details the threat model and the security requirements. Section III presents the proposed scan protection technique. The analysis of the solution is detailed in Section IV. Section V shows a comparison of our proposal with related works. Finally, Section VI concludes the paper.

II. THREAT MODEL

Designers can protect their hardware IPs by applying logic locking and our proposed scan controller. In this case, the design is locked with a logic locking key, referred to as K L ; and its scan chains are locked with a scan access key, referred to as K S .

Fig. 1 depicts the threat model corresponding to this scheme. The foundry, the test/packaging facility and the end user, depicted on a red background in Fig. 1, are potential attackers who want to recover K L . After fabrication and packaging, the ICs are sent to the designer or a trusted entity, who programs, into their tamper-proof memory (TPM), K L for unlocking their functionality and K S for securing the scan chains. Thus, the unlocked ICs have "locked" scan chains controlled by the scan controller. According to the model of the SAT attack and the sensitization attack, the following assets are required: (i) a locked netlist; (ii) an unlocked IC; (iii) K S .

The attacker's capabilities are defined as follows. We assume that unlocked ICs can be purchased from the market and, hence, accessible to all potential attackers. The manufacturer receives the layout of the logic locked design for fabrication. The locked netlist can be obtained by reverse-engineering the layout. The end user or the test facility can obtain the locked netlist by trading with the manufacturer or by reverseengineering an unlocked circuit if they have a capable facility.

According to the threat model, the attackers are not in possession of K S . The designer should restrict the distribution of K S only to trusted partners. The manufacturer is commonly in charge of conducting production test. It includes a scanbased structural test that is performed on wafers by probing each die. For this structural test, test patterns are generated with incorrect values of K L . Hence, K L is not required for performing production test. However, using scan chains is necessary. Thus the scan controller should be temporarily bypassed during this phase. Since K S is also required for further failure analysis when an IC presents an erroneous behavior in the field, debug and diagnosis must be conducted by the design house or a trusted partner.

III. PROPOSED SOLUTION

The main idea of the proposed solution is to use a key-based authentication for controlling the activation of scan chains. Upon the insertion of an incorrect key value to the scan controller, no scan data is available for attacking purposes. To further increase the robustness of the scheme, the scan controller includes a linear-feedback shift register (LFSR) that dynamically changes the value of the required key.

A. Scan Controller

The structure of the proposed scan chain controller is illustrated in Fig. 2. It includes an n-bit linear-feedback shift register and a comparator. The scan controller "locks" the Scan Enable (SE) signal by setting it to "0". SE is set to "1" only upon the insertion of the correct dynamic value of test key, referred to as K T , that matches the output of the LFSR. K S initializes the LFSR and, thus, defines the correct K T value.

K S is stored in a TPM that is programmed by the designer during the activation phase as depicted in Fig. 1. It is possible to program each IC with a different value of K S . Therefore, each IC requires a distinct K T bit stream that can not be reused on another IC. This property can be exploited to help designers track scan usage in each IC.

The LFSR is an n-bit shift register. It randomizes its state at every clock cycle, i.e. St LF SRt (K S ) = St LF SRt+1 (K S ) at any cycle t. As the LFSR is used as a bit stream generator, its output throughout n cycles represents one of its states. The comparator consists of a XNOR gate and a counter. The XNOR gate compares the inserted K T value and the current output of the LFSR, and feeds the result to the counter. The counter checks if the K T stream matches the state of the LFSR, i.e. the value of K T is correct for n consecutive cycles. If "1" has been inputted to the counter for the last n cycles, it sets SE signal to "1"; otherwise, SE remains at "0". If the comparison result becomes "0", the counter resets immediately and SE is set to "0". Given the correct K T bit stream, after the first n -1 cycles, SE is set to "1" continuously.

To switch scan cells from functional mode to shift mode, a Test Mode (TM) signal is used to set the SE pin in each scan cell to "1". The TM signal also avoids unwanted mode switching due to the periodic nature of the LFSR. The scan controller should be temporarily bypassed during manufacturing test to avoid communicating K S to adversaries. This can be done by physically connecting the output of the scan controller to a pull-up element or a controllable source. The former is based on the Saw Bow method [START_REF] Di Natale | Manufacturing Testing and Security Countermeasures[END_REF], where the connecting wire crosses the sawing line of the wafer. The latter is depicted in Fig. 3. An additional pin directly controls the value of the SE signal. It is blown off after the packaging process.

Upon knowledge of K S (i.e., its seed) and its structure, the LFSR can be recreated. An authorized tester who received the mentioned assets can build an equivalent model of the LFSR to generate the required K T bit stream.

B. Combining with Logic Locking

The proposed scan solution can be combined with any logic locking technique, as shown in Fig. 4, to increase the resilience against attacks that rely on scan chain access. Any related state-of-the-art logic locking technique focusing on identifying strong key-gate locations [START_REF] Yasin | On Improving the Security of Logic Locking[END_REF] and/or maximizing output corruption [START_REF] Rajendran | Fault Analysis-Based Logic Encryption[END_REF], [START_REF] Karmakar | On Finding Suitable Key-Gate Locations In Logic Encryption[END_REF] can be used to complement the scan shift protection mechanism provided by our solution.

IV. ANALYSIS

A. Security Analysis 1) Protecting Logic Locking: The SAT attack needs an oracle with accessible scan chains to control and observe respectively inputs and outputs of the combinational part under attack. The proposed scan controller blocks any unauthorized usage of the scan chains in the oracle. In other words, the attacker cannot apply any DIP generated by the SAT solver to the inputs of the combinational part, and he/she cannot deduce expected outputs for wrong key elimination. Therefore, the attack is unable to solve the problem of finding K L . The same remarks can be made concerning the sensitization attacks, which also require full control and observation of combinational logic cones.

A more computationally intensive way to represent a sequential circuit without scan chains as combinational is to use the time-frame expansion method. The circuit is modelled as a series of copies of its combinational part, where each copy corresponds to a time-frame. The same procedure is used to perform production test pattern generation on sequential circuits without scan chains. However, the number of timeframes must be large enough to reach all the states of the circuit, which can require up to 2 n F F time-frames, where n F F is the number of FFs. For this reason, sequential test pattern generation is avoided in practice and scan design is the de facto Design-for-Testability approach today. In [START_REF] Massad | Reverse engineering camouflaged sequential circuits without scan access[END_REF], [START_REF] Shamsi | KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation[END_REF], authors report that attacks based on "sequential" SAT approaches can only handle small circuits with a few thousands of gates.

As mentioned in Section III-B, key-gate insertion locking techniques should be used with the scan controller. After synthesis, inserted key-gates and their neighboring gates are structurally transformed into different forms, making them resilient against removal. Furthermore, these techniques have higher output corruption and smaller overhead compared to state-of-the-art SAT-resilient techniques.

2) Securing the Scan Access Key: K S needs to be kept secret; otherwise, an attacker with the reverse-engineered netlist can recreate the LFSR inside the scan controller to generate K T and activate the scan chains. However, the nature of the scan controller gives minimal output observability to attackers:

• SE is the only output signal of the scan controller and it is just 1-bit wide. • SE is an internal signal of the circuit, which makes observing its behavior challenging for attackers. As mentioned in section III-A, K T has to be correct for the last n cycles in order to enable the scan chains for 1 cycle. The probability of guessing this value with a brute-force approach is 1/2 n . The function of the scan controller at any cycle t can be modelled as a point function:

1, if K T t→t+n = St LF SRt (K S ) 0, otherwise ∀K S , K T t→t+n ∈ {0, 1} n
(1) A point function is a one-way function, which is a fundamental cryptographic primitive and is provably hard to invert. An attacker can resort to cryptanalytic principles to correlate the inserted K T and the SE signal, observed through scan output. However, due to the point function behavior, it is not possible to derive K S with a more efficient approach than brute-force guessing.

Point functions have also been proven to be resilient against SAT-based attacks [START_REF] Yasin | SAR-Lock: SAT attack resistant logic locking[END_REF], [START_REF] Xie | Mitigating SAT Attack on Logic Locking[END_REF]. Using a point function to hide secret information forces the SAT solver to check for every possibility. In other words, the SAT solver is forced to generate a new DIP for the elimination of only one key at every iteration, hence reducing the attack's efficiency to that of bruteforce. Therefore, using formal methods cannot aid attackers at retrieving the K S value.

Attackers who own the reverse-engineered netlist can resort to ScanSAT attack [START_REF] Alrahis | ScanSAT: Unlocking Static and Dynamic Scan Obfuscation[END_REF]. Based on a SAT solver, it targets scan protection methods that corrupt scan data in the absence of a secret key. Using the same attack model as the SAT attack on logic locking, ScanSAT depends on scan data control and observation. However, as mentioned in Section III, data from the scan chains are not available since the scan controller disables the scan chains. Furthermore, data observed at SO pin show no correlation with K S . Thus, ScanSAT is not effective against our scan protection.

The scan controller also improves data confidentiality in the circuit. Scan chains are the target of a plethora of attacks that aim to steal secret data from ICs [START_REF] Valea | A Survey on Security Threats and Countermeasures in IEEE Test Standards[END_REF]. The scan controller prevents attackers from using scan structure deliberately. Thus, malicious data cannot enter the scan chains, nor can secret data be examined from the scan chains.

3) Tampering: An untrusted manufacturer has the capability to modify the mask before IC fabrication, which allows them to bypass the scan controller introduced in the original design. However, this modification is easily detectable since scan shift would be allowed without the need to provide the correct K T . We assume that an untrusted packaging facility neglects to destroy the additional pin used to bypass the scan controller during production test. As the produced ICs are sent back to the design house for activation, the designers can perform an ad hoc test to detect such tampering before inserting K L .

B. Testability Analysis

Any fault in the scan controller easily propagates to the SE signal and affects the activation of the scan chains. Thus, the scan controller can be tested with a functional test. Furthermore, the built-in LFSR acts as a self-test structure to facilitate the test.

Structural test can be applied to the CUT before it is unlocked. Test patterns for such test are generated assuming that key inputs are controllable; thus, the correct K L value is not required. This procedure is shown to provide maximum fault coverage while preventing attackers from retrieving K L by analysing test patterns [START_REF] Yasin | Activation of logic encrypted chips: Pre-test or post-test?[END_REF].

C. Overhead

We implemented the scan controller in ITC'99 benchmarks [START_REF] Corno | RT-level ITC'99 benchmarks and first ATPG results[END_REF]. The benchmarks were synthesized on a 65nm technology library with Synopsis Design Compiler [START_REF]Design Compiler ®[END_REF]. Fig. 5 shows the area overhead for three versions of the proposed scan controller using a 64-bit, an 80-bit and a 128-bit LFSR, along with a comparison with related works [START_REF] Guin | Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test[END_REF], [START_REF] Karmakar | Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits[END_REF] using a 128bit key. The area overhead of the scan controller is as low as 0.3% in the b19 benchmark. Although the solution in [START_REF] Karmakar | Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits[END_REF] a smaller area cost, we show in the next section that it is less secure than the proposed solution.

We used Synopsis TetraMax [START_REF]Tetramax[END_REF] to generate test patterns for the mentioned benchmarks. The b18 benchmark is estimated to have a test time of about 6•10 7 clock cycles. Using a 128-bit scan controller takes 127 initial cycles to set up the SE signal. Thus, it represents a largely trivial test time overhead.

V. COMPARISON WITH RELATED WORKS

Research on secure scan chain has been established since the introduction of scan-based side channel attacks on crypto circuits [START_REF] Valea | A Survey on Security Threats and Countermeasures in IEEE Test Standards[END_REF]. The attacks deduce the cipher key by analyzing the partial results of the cryptographic operation that can be observed through the scan chains. However, countermeasures against such attacks may not adapt to the threat model of attacks on logic locking, where the attacker has the additional capability of reverse-engineering the circuit. Solutions that aim at masking scan data and assume that the scan chain structure is unknown to the attacker, such as [START_REF] Sengar | Secured flipped scan-chain model for crypto-architecture[END_REF] which judiciously inserts inverters into the scan chains, are therefore vulnerable in the scenario of logic locking. Other solutions based on manipulating scan data during the switch between functional mode and test mode [START_REF] Hely | Test control for secure scan designs[END_REF] also turn nullified as SAT attack or ScanSAT attack only work in test mode. Therefore, recent works have proposed secure scan solutions that accommodate the stronger threat of attacks on logic locking.

One class of solutions is based on scan obfuscation. Using the same principle as logic locking, Encrypt Flip-Flop technique [START_REF] Karmakar | Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits[END_REF] inserts key-gates in the scan chains to corrupt scan data, both at shift in and shift out operations. A stronger obfuscation effect can be achieved when the secret key changes dynamically, which makes the function of scan-data transformation change over time. Such dynamic scan obfuscation strategy is presented in [START_REF] Wang | Secure Scan and Test Using Obfuscation Throughout Supply Chain[END_REF]. An LFSR is connected to the key inputs of key-gates and it feeds new key values periodically. However, as is the case with logic locking, the obfuscated scan output reflects the inversion effect of key-gates and it can be used to trace back to the secret key. ScanSAT attack is indeed capable of modelling the locked scan chains as a combination

Solution

Attacks ScanSAT [START_REF] Alrahis | ScanSAT: Unlocking Static and Dynamic Scan Obfuscation[END_REF] Shift & Leak [33] Encrypt Flip-Flop [START_REF] Karmakar | Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits[END_REF] × Dynamic Scan Obfuscation [START_REF] Wang | Secure Scan and Test Using Obfuscation Throughout Supply Chain[END_REF] × Secure Cell [START_REF] Guin | Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test[END_REF] × Proposed denotes resilience against the attack × denotes susceptibility to the attack of key-gates inserted at PPIs and PPOs. Using the same attack model as SAT attack, the secret key is deduced by the SAT solver.

Guin et al. [START_REF] Guin | Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test[END_REF] proposed a solution to counteract the SAT attack by restricting the observation of scan output. The logiclocking key is hold inside modified scan cells, called Secure Cells (SC). A SC holds its previous state at test time. In addition, a test suppressor is introduced to delete scan output data whenever the circuit switches from functional mode to test mode, hence, preventing leaking the key through scan data. However, due to testing support, the solution does not control the scan shift-in operation, which is exploited by a customized attack called shift-and-leak [START_REF] Limaye | Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access[END_REF]. The key bits can be shifted to easily observable scan cells and test patterns can be used to set a condition for sensitizing each key bit to the POs.

Our proposed scan controller is shown to be resistant to ScanSAT (section IV-A2) while demanding minimal area cost. A comparison between the proposal and the mentioned solutions is presented in Table I.

VI. CONCLUSION

The scalability and efficiency of SAT-based attacks, as well as sensitization-based attacks, on logic locking rely heavily on the control and observation of inputs/outputs of the combinational part under attack. While scan chains are widely used in the industry for production test purpose, they also provide such capability and, thus, make these attacks possible.

In this paper, we present a low-cost scan controller that requires a dynamic key to enable the shift operations in the scan chains. The resulting blocked scan access prevents adversaries from shifting data in or out from the scan chains, making it impossible to implement the attacks. Using the scan controller with key-gate insertion techniques meets all the requirements of logic locking. Security analysis shows its ability to secure the scan access key and its robustness against tampering. Full testing is supported when performed by authorized partners without leaking secret data to adversaries. In addition, the solution is scalable and easy to integrate.

Fig. 1 .

 1 Fig. 1. Production flow and attack model.

Fig. 2 .

 2 Fig. 2. Structure of the proposed scan controller.

Fig. 3 .

 3 Fig. 3. Bypassing the scan controller during manufacturing test.

Fig. 4 .

 4 Fig. 4. Using the scan controller with a logic-locked circuit.

TABLE I .

 I Comparison with other scan-based SAT-resistant techniques

ACKNOWLEDGMENT

This work is funded by project MOOSIC ANR-18-CE39-0005 of the French National Research Agency (ANR).


Seonho Seok
email: seonho.seok@c2n.upsaclay.fr

Experiment and Analysis of the Effect of BCB Sealing Ring Flatness on BCB Cap Transfer Packaging

Keywords: Flatness, BCB sealing ring, packaging, polymer, FEM. I

This paper presents the effect of BCB sealing ring flatness on BCB bonding for wafer-scale BCB cap transfer packaging. BCB sealing ring has shown partial bonding or full bonding depending on its flatness. It is found that the principal cause of the partial bonding is due to non-flat BCB sealing ring caused by multilayer BCB coating process. As a solution, BCB dry etching has been proposed to improve the flatness of the BCB sealing ring for full BCB bonding. Besides, partial bonding of BCB ring has been analyzed through FEM modeling of BCB cap with a non-flat sealing ring. The FEM model consists of Si carrier wafer, BCB cap, and Si target substrate. Unique load is applying pressure on top of Si carrier wafer like wafer-scale bonding. The role of applying pressure is to get BCB sealing ring to be contacted and expand bondable area with target Si substrate. As BCB sealing ring is bonded through BCB polymerization by holding the pressure for 1 hour at 250 °C, mechanical properties of virgin BCB sealing ring has been changed during bonding. Thus, it has been chosen as variable for parametric analysis. Also, BCB cap dimension has been used as another parameter for the parametric analysis.

INTRODUCTION

Polymer materials have been widely used as an intermediate layer or encapsulation caps in MEMS packaging [START_REF] Giacomozziemail Authorviviana Mullonisabrina | RF-MEMS packaging by using quartz caps and epoxy polymers[END_REF][START_REF] Wang | Chip scale studies of BCB based polymer bonding for MEMS packaging[END_REF]. The polymer intermediate materials are used as sealing ring between packaging caps and device substrate since most of the packaging caps are glass or Si. They are bonded by means of thermocompression bonding or laser. Low temperature bonding capability of the polymer is particularly attractive as high process temperature in MEMS packaging could create thermal mechanical failure of MEMS devices. For usage, polymer material with high viscosity is dispensed in a cap wafer with a housing cavity for MEMS device. Due to the high topography of the MEMS packaging cap, wafer-scale coating of the polymer on MEMS cap wafer could create non-flat sealing ring on the rim of packaging cap [START_REF] Gong | Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer[END_REF]. Such a non-flat polymer ring can be a reason of low bonding strength of MEMS package [START_REF] Seok | Enhancement of Bonding Strength of Packaging Based on BCB Bonding for RF Devices[END_REF]. Thus, novel fabrication methods have been reported to implement the flat polymer ring on MEMS packaging cap with housing cavities [START_REF] Seok | Enhancement of Bonding Strength of Packaging Based on BCB Bonding for RF Devices[END_REF]. Recently, polymer cap encapsulation has been presented to take advantages of lowprofile and low packaging loss for high frequency devices [START_REF] Seok | Packaging methodology for RF devices using a BCB membrane transfer technique[END_REF][START_REF] Zine-El-Abidine | A Low-Temperature SU-8 Based Wafer-Level Hermetic Packaging for MEMS Devices[END_REF]. The polymer cap packaging of MEMS devices has been realized in two different ways; 1) release of packaging cap 2) transfer of packaging cap. Polymer cap release has been carried out by plasma etch of organic sacrificial layer through access holes or wet etch of the polymer cap partially cross-linked. Transfer packaging of polymer cap needs a temporary carrier wafer to literally transfer the fabricated packaging cap to a target device substrate. When the polymer packaging cap is prepared in a carrier wafer, we ought to use multilayer coating of the polymer to build packaging cover and the sealing ring of the packaging cap. When polymer sealing ring is coated on pre-patterned polymer cover, sealing ring layer shows certain non-flatness due to surface profile of the pre-patterned polymer cover layer. Moreover, polymer sealing ring is directly affected by the non-flatness since it should be built in the rim of polymer cover. It is thought that non-flat polymer sealing ring would not be significant because high applying bonding pressure can flatten it resulting in expansion of bonding area. Therefore, it is necessary to study the effect of non-flat polymer ring on polymer cap transfer packaging. FE (Finite Element) model is useful technique to evaluate mechanical stress and deformation of a MEMS package [START_REF] Satyajit | Evaluation of Die Stress in MEMS Packaging: Experimental and Theoretical Approaches[END_REF] and to investigate contact surface behavior when two different materials are jointed or contacted [START_REF] Seok | Fabrication and Modeling of Nitride Thin Film Encapsulation Based on Anti-Adhesion-Assisted Transfer Technique and Nitride/BCB Bilayer Wrinkling[END_REF].

In this paper, experimental results effect of flatness of BCB sealing ring on BCB packaging cap bonding and corresponding FEM analysis have been presented. BCB cap transfer packaging and experimental results of BCB cap transfer packaging with two different BCB sealing ring flatness are presented in Section II. FEM modeling and simulation of BCB cap packaging with non-flat BCB ring explained in Section III. Finally, conclusion will be made in Section IV.

II. BCB CAP TRANSFER PACKAGING AND BCB SEALING RING NONFLATNESS

Fig. 1 shows BCB cap transfer packaging process based on photosensitive BCB multilayer coating [START_REF]Processing Procedures for CYCLOTENE 4000 Series Photo BCB Resins[END_REF]. As shown in Fig. 1, BCB cap is prepared by using spin-coating of photosensitive BCB. BCB cap has one cover layer having thickness of 15-20 µm and one sealing ring of 15-20 µm. The BCB sealing ring can have non-flat shape as it is coated and patterned on the pre-defined BCB cover and thus it could cause partial bonding of the sealing ring to target Si substrate. Fig. 2 shows the profile measurement of BCB sealing ring built on bare silicon wafer and BCB sealing ring on pre-defined BCB cover respectively. As clearly seen in this figure, flat BCB ring area is substantially reduced due to pre-patterned BCB cover.

III. FEM MODELING AND SIMULATION

As mentioned in previous section, non-flat BCB sealing have caused partial bonding even if the applied larger bonding pressure. Thus, it is required to study the effect of applying pressure on non-flat BCB ring at wafer-level bonding. A FEM model of the BCB cap transfer packaging with non-flat BCB sealing ring has been built as shown in Fig. 6. It consists of Si carrier, BCB cap and target Si substrate as is in the packaging process. Note that it is a quarter model of a single package to reduce element number as well as simulation time. By consequence, boundary conditions are applied as follow; Ux = 0 at xg =0, Uy = 0 at yg = 0. Bottom surface of Si substrate is fixed. Si carrier wafer movement are constrained to be in z-axis when bonding pressure is applied on top of Si carrier. Applied force is 1500 N as is in the experiment [START_REF] Kim | Polymer-based Zero-Level Packaging Technology for High Frequency RF Applications by Wafer Bonding/Debonding Technique Using an Anti-adhesion Layer[END_REF]. Dimension of each component and material properties are summarized in Table 1 To reflect the non-flat BCB ring, it is modelled as two different parts as depicted in Fig. 7; bonded and non-bonded.

As non-flat BCB ring has been bonded from inner part of the ring to outer side, it is modelled to have bonded contact and frictional (non-bonded) contact. The bonded contact of the BCB cap means BCB cap has good bonding, while the frictional one is used to monitor the behavior of BCB cap deformation due to applied bonding pressure. The bonded contact has 50 µm width and the remained area of the BCB sealing ring are defined as frictionless one. As the BCB ring has 150 µm, the unbonded ring width is 100 µm. BCB ring is assumed to be fully cured in the previous simulation, but it should be partially cured or virgin BCB ring to achieve good bonding with target Si substrate. During bonding process, force is applied to wafer stack through 3 mm-thick glass pressure diffuser from 150 °C as seen in Fig. 9. After 10 minutes, temperature goes up to 250 °C and stays for 1 hour to get the BCB ring fully-cured. Therefore, a parametric study depending on BCB ring material properties such as Young's modulus (E) and poisson ratio is required. Fig. 9 BCB cap bonding process conditions At first, Young's modulus of BCB ring has been changed from 1 MPa to 3 MPa at the step of 1 MPa. The increase rate of bonded area is estimated 88 % for 1 MPa, 70 % for 2 MPa, and 63 % for 3 MPa respectively. Poisson ratio of BCB ring has values of 0.34, 0.40, and 0.45 makes increase rate to be 63 %, 61 %, and 56 % respectively. Larger poisson ratio is not positive to get large bonding area, which is due to its negative factor into transversal direction. Thus, smaller Young's modulus and smaller poisson ratio are better to get larger bonding area. For BCB ring, it is recommended that it is better to cure it with polymerization rate less than 75 % because it has around 2 MPa of EBCB when it has more than 80 % polymerization rate [START_REF] Wöhrmann | Low Temperature Cure of BCB and the Influence on the Mechanical Stress[END_REF]. BCB ring flatness plays an important role to achieve uniformly sealed ring packaging, which is experimentally proved. Typical photosensitive BCB polymer creates nonuniform morphology due to multilayer coating on prepattern underlayer. BCB ring patterned with dry etching is an effective solution to avoid partial bonding of BCB sealing ring. Through FEM modeling, it is found that Young's modulus of BCB polymer influences much more than poisson ratio, which lead to propose that cure rate of BCB less than 75 % would be an alternative way to improve BCB ring bonding. Besides, geometrical parameters such as thickness of BCB cap have been studied and found to be effective for the issues related with BCB ring flatness.

  Fig. 2 BCB ring profile on different underlying layersAs the non-flatness of BCB ring is caused by coating on a pre-defined BCB layer, dry etch-based BCB cap process has been presented as shown in Fig.3. The difference with the previous one is that BCB cover layer is not patterned before BCB ring layer coating. BCB ring and BCB cover are defined by using BCB dry etch to achieve better BCB sealing ring flatness. BCB cap profile measurement, shown in Fig.4, validated BCB ring flatness better than the previous one. Note that outer wall of the BCB sealing still has slightly inclined as it has been defined by wet etch of BCB after photolithography.

Fig. 7

 7 Fig. 7 Contact surfaces of BCB capDisplacement in z-axis direction and corresponding stress are shown in Fig.8. BCB cap associated with bonded BCB ring has slightly smaller displacement than other parts of the BCB cap and thus maximum stress is found inner side of BCB ring. The maximal stress of BCB cap is much lower than yield stress of BCB polymer of 87 ± 9 MPa[START_REF]Processing Procedures for CYCLOTENE 4000 Series Photo BCB Resins[END_REF]. Fig.8 (c)shows deformed BCB ring along the slope of the unbonded BCB ring referring to x and z axes as indicated in Fig.6. Point crossing with interface between Si substrate and BCB ring is upper limit of bonded sealing ring. In this case, the bonded zone is up to 62.5 µm among initial unbonded zone of 100 µm. Applying force of 1500 N makes total bonded area to be increased by 62.5 % of the unbonded BCB area.

  (a) Young's modulus (b) Poisson ratio Fig. 10 Effect of BCB ring material propertiesThe effect of BCB layer thickness is also studied as the geometical design can be a way to compensate non-flat BCB ring. As BCB cover thickness increases, bonded area of BCB ring is also increased. BCB ring thickness makes same tendency as the BCB cover thickness. It would beInterface between Si substrate and BCB ringInterface between Si substrate and BCB ring effect of length of BCB layer which means longer one makes larger deformation at same applied load when strain of the material is maintained. Note that BCB ring nonflatness defined in Fig.6(b) has been applied for all the BCB ring thickness and thicker BCB layer has demerits in view of mechanical stress and process cost. (a) BCB cover thickness (b) BCB ring thickness Fig. 11 Effect of BCB cap geometries IV. CONCLUSIONS

Table 1 .

 1 and Table2respectively. Dimension of the model

		(a) Total model
		(b) BCB cap
	Fig. 6 FEM model of BCB cap transfer packaging
		with non-flat BCB sealing ring
		Length	Width	Thickness
		(µm)	(µm)	(µm)
	Si carrier	500	500	300
	BCB cap
	BCB cover	350	350	20
	BCB ring	350	150	20
	Si substrate	500	500	300


Carlos Palo-Nieto

Abhijit Sau

Robin Jeanneret

Pierre-Adrien Payard

Aude Salamé

Maristela Braga Martins-Teixeira

Ivone Carvalho

Laurence Grimaud
email: laurence.grimaud@ens.fr

Carmen Galan
email: m.c.galan@bristol.ac.uk

Salamé Aude

M Carmen Galan

Copper Reactivity Can Be Tuned to Catalyze the Stereoselective Synthesis of 2-Deoxyglycosides from Glycals

à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Carbohydrates play significant roles in a wide range of biological events [START_REF] Varki | Biological Roles of Glycans: Two Decades Later[END_REF] and efficient catalytic and asymmetric methods to access this class of chiral molecules are needed to further our understanding of their various roles and functions in health and disease. [START_REF] Galan | Carbohydrate chemistry in drug discovery[END_REF][START_REF] Galan | Multivalent glyco(cyclo)peptides[END_REF] First row transition metals have recently attracted attention as alternatives to precious metals in catalysis. [START_REF] Zhu | Copper-catalyzed oxidative carbonheteroatom bond formation: a recent update[END_REF] Among those, copper is a cost-effective, earth-abundant and sustainable metal and Cu-complexes can display unique and versatile reactivity and good functional group tolerance. [START_REF] Zhu | Copper-catalyzed oxidative carbonheteroatom bond formation: a recent update[END_REF] The chemistry exhibited by Cu can be very diverse depending on its oxidation state, as this metal can efficiently catalyse reactions involving one or twoelectron mechanisms. [START_REF] Zhu | Copper-catalyzed oxidative carbonheteroatom bond formation: a recent update[END_REF][START_REF] Nogueira | Reagent-Controlled alpha-Selective Dehydrative Glycosylation of 2,6-Dideoxy-and 2,3,6-Trideoxy Sugars[END_REF][START_REF] Chemler | Copper catalysis in organic synthesis. Thematic Series[END_REF][START_REF] Schmid | Copper-catalyzed asymmetric conjugate addition of organometallic reagents to extended Michael acceptors[END_REF] In the context of O-linked glycosylation reactions, a few examples of Cu(II) as a mild oxophilic Lewis acid catalyst for the activation of oxygen-containing leaving groups have been reported. [START_REF] Sato | An Efficient Approach to O-Glycosides through CuBr2-Bu4NBr Mediated Activation of Glycosides[END_REF][START_REF] Yamada | A substrate-unspecified glycosylation reaction promoted by copper(II) trifluoromethanesulfonate in benzotrifluoride[END_REF][START_REF] Srinivas | Copper(II) Triflate as a Mild and Efficient Catalyst for Ferrier Glycosylation: Synthesis of 2,3-Unsaturated O-Glycosides[END_REF][START_REF] Battina | Copper mediated iodoacetoxylation and glycosylation: effective and convenient approaches for the stereoselective synthesis of 2-deoxy-2-iodo glycosides[END_REF] More recently, the use of Cu II (OTf)2 as an in situ oxidant in the photoinduced-activation of thioglycosides was also exemplified. [START_REF] Mao | Photoinduced C-S Bond Cleavage of Thioglycosides and Glycosylation[END_REF] However, despite copper catalysts being relatively cheap and widely available, we were surprised by the overall under exploration of this metal in glycosylation chemistry [START_REF] Li | Recent Advances in Transition Metal-Catalyzed O-Glycosylations[END_REF][START_REF] Li | Glycosylation via Transition-Metal Catalysis: Challenges and Opportunities[END_REF][START_REF] Sletten | Are Bronsted Acids the True Promoter of Metal-Triflate-Catalyzed Glycosylations? A Mechanistic Probe into 1,2-cis-Aminoglycoside Formation by Nickel Triflate[END_REF][START_REF] Mckay | Recent Advances in Transition Metal-Catalyzed Glycosylation[END_REF][START_REF] Ling | Recent Developments in Stereoselective Chemical Glycosylation[END_REF] .

Our group is interested in the development of sustainable and catalytic methods for the synthesis of oligosaccharides. [START_REF] Sau | Substrate-Controlled Direct alpha-Stereoselective Synthesis of Deoxyglycosides from Glycals Using B(C6F5)3 as Catalyst[END_REF][START_REF] Palo-Nieto | Cooperative Bronsted Acid-Type Organocatalysis for the Stereoselective Synthesis of Deoxyglycosides[END_REF][START_REF] Beattie | Stereoselective synthesis of protected L-and Ddideoxysugars and analogues via Prins cyclisations[END_REF][START_REF] Medina | Stereoselective synthesis of glycosides using (salen)Co catalysts as promoters[END_REF] 2deoxy-hexoses are prominent components of natural products which due to the lack of substituents at C-2 to direct the nucleophile approach present significant synthetic challenges and their improved and stereoselective protocols for their assembly has been of great intetest. [START_REF] Nogueira | Reagent-Controlled alpha-Selective Dehydrative Glycosylation of 2,6-Dideoxy-and 2,3,6-Trideoxy Sugars[END_REF][START_REF] Sau | Substrate-Controlled Direct alpha-Stereoselective Synthesis of Deoxyglycosides from Glycals Using B(C6F5)3 as Catalyst[END_REF][START_REF] Medina | Recent developments in the stereoselective synthesis of deoxy glycosides[END_REF][START_REF] Benito-Alifonso | Bronsted and Lewis Acid Catalyzed Glycosylation[END_REF][START_REF] Williams | Recent Advances in Organocatalytic Glycosylations[END_REF][START_REF] Zeng | Recent progress on the synthesis of 2-deoxy glycosides[END_REF][START_REF] Bennett | Methods for 2-Deoxyglycoside Synthesis[END_REF][START_REF] Beale | Organoboron-Catalyzed Regio-and Stereoselective Formation of beta-2-Deoxyglycosidic Linkages[END_REF][START_REF] Wang | Stereoselective Synthesis of alpha-Linked 2-Deoxy Glycosides Enabled by Visible-Light-Mediated Reductive Deiodination[END_REF][START_REF] Zhu | Direct Synthesis of 2-Deoxy-beta-Glycosides via Anomeric O-Alkylation with Secondary Electrophiles[END_REF][START_REF] Kaneko | Scope and limitations of 2-deoxyand 2,6-dideoxyglycosyl bromides as donors for the synthesis of beta-2-deoxy-and beta-2,6-dideoxyglycosides[END_REF][START_REF] Pradhan | Glycosylation Chemistry of 3-Deoxy-D-manno-Oct-2-ulosonic Acid (Kdo) Donors[END_REF][START_REF] Das | Organocatalytic Glycosylation by Using Electron-Deficient Pyridinium Salts[END_REF][START_REF] Song | De Novo Synthesis of Mono-and Oligosaccharides via Dihydropyran Intermediates[END_REF][START_REF] Zhao | Stereoselective Synthesis of 2-Deoxyglycosides from Glycals by Visible-Light-Induced Photoacid Catalysis[END_REF][START_REF] Soliman | Reagent-Controlled Synthesis of the Branched Trisaccharide Fragment of the Antibiotic Saccharomicin B[END_REF][START_REF] Lloyd | An Improved Approach to the Direct Construction of 2-Deoxy-beta-Linked Sugars: Applications to Oligosaccharide Synthesis[END_REF][START_REF] Bradshaw | Stereoselective organocatalyzed glycosylations -thiouracil, thioureas and monothiophthalimide act as Bronsted acid catalysts at low loadings[END_REF] Previous work from our group and others has shown that activation of glycals to yield glycosides can be achieved using transition metals such as Pd(II) [START_REF] Sau | Palladium-Catalyzed Direct Stereoselective Synthesis of Deoxyglycosides from Glycals[END_REF][START_REF] Sau | Palladium-Catalyzed alpha-Stereoselective O-Glycosylation of O(3)-Acylated Glycals[END_REF] , Au(I) [START_REF] Palo-Nieto | Gold(I)-Catalyzed Direct Stereoselective Synthesis of Deoxyglycosides from Glycals[END_REF] or Re(V) [START_REF] Sherry | Rhenium(V)-catalyzed synthesis of 2-deoxy-alpha-glycosides[END_REF] catalysts, however activation of sensitive enol ethers bearing electronwithdrawing groups at the C-3 position of the glycal was not possible under those conditions (Scheme 1) and in general harsher conditions used to activate such glycals often lead to donor hydrolysis and/or Ferrier type products. [START_REF] Bennett | Methods for 2-Deoxyglycoside Synthesis[END_REF] Scheme 1: Cu I -catalysed direct synthesis of deoxyglycosides from glycals These findings prompted us to explore the utility of copper in the activation of glycals to yield 2-deoxyglycosides. To that end, a series of Cu(I) and Cu(II) salts at different catalyst loadings, reaction temperatures and solvents were initially screened as promoters in the glycosylation of perbenzylated galactal 1a and glucoside acceptor 2a 6a (See Table S1 in ESI). It was found that 5 mol% (Cu I OTf)2 . C6H6 in toluene at 45 o C gave the best results (Table 1, entry 1). The substrate scope was thus investigated and Galactal 1a was reacted with a range of primary and secondary OH nucleophiles 2b-2i [START_REF] Balmond | a l p h a -S e l e c t i v e O r g a n o c a t a l y t i c S y n t h e s i s o f 2 -Deoxygalactosides[END_REF] under the optimized reaction conditions (Table 1). In all cases, reactions proceeded smoothly and in good to excellent yields and α-selectivity, demonstrating that the catalytic system tolerates the presence of common alcohol and amine protecting groups such as acetals, ethers, esters and carbamates. Glycosylations with primary alcohols such as simple benzyl alcohol 2b, glycosides 2c and 2d, thioglycoside 2e and Boc-protected serine 2f afforded the corresponding glycoside products in 79-88% yield within 2 h and with an >30:1 α:β ratio (Table 2, entries 2-6). Similarly, reactions with secondary alcohols such as, glycoside 2g, Bocprotected threonine 2h and cholesterol 2i also afforded the desired products in good yields (72-75%) and with high αselectivity (>30:1 α:β ratio, entries 7-9). Table 1. Reaction of glycal 1a with glycoside acceptors 2b-2i.

[a] Isolated yield. [b] Determined by 1 H-NMR. [c] Reaction using Cu(II)(OTf)2 (5 mol%) and sodium ascorbate (10 mol%) to generate Cu(I) in situ also afforded 4c in 89% yield and >30:1 α:β.

Next, the scope of the reaction with respect to the glycal donor was investigated. A series of differentially protected galactals 1b-1h, glucals 5a and 5b and fucal 6 bearing benzyl, acetate, methoxymethyl acetal, silyl ether and siloxane protecting groups were prepared and subjected to the glycosylation conditions with 2a or 2g as the acceptors (Table 2). Pleasingly, reactions involving galactal donors 1c-1h were complete within 2-4 h and in yields of 72-98% and high αselectivities (15:1 to 30:1) (entries 2-6). Excitingly, Cu I -activation of galactals bearing acetyl groups at C-3 such peracetylated galactal 1b and silyl acetal 1h with 2a gave glycosylation products 7b and 7h, in 63% and 84% yield respectively, with high α-stereocontrol (entries 1 and 7). This is noteworthy, as most protocols used to activate 'disarmed' glycals tend to give mixtures of glycoside and Ferrier-type products [START_REF] Sau | Substrate-Controlled Direct alpha-Stereoselective Synthesis of Deoxyglycosides from Glycals Using B(C6F5)3 as Catalyst[END_REF][START_REF] Palo-Nieto | Cooperative Bronsted Acid-Type Organocatalysis for the Stereoselective Synthesis of Deoxyglycosides[END_REF][START_REF] Sau | Palladium-Catalyzed alpha-Stereoselective O-Glycosylation of O(3)-Acylated Glycals[END_REF] as we also observe when using Cu(II) (Table 2, entry 1 [d] ). The reaction was also amenable to glycosylations with glucal substrates, and reactions with 3,4-O-siloxane-protected 5a [START_REF] Balmond | A 3,4-trans-Fused Cyclic Protecting Group Facilitates alpha-Selective Catalytic Synthesis of 2-Deoxyglycosides[END_REF] or 5b [START_REF] Balmond | A 3,4-trans-Fused Cyclic Protecting Group Facilitates alpha-Selective Catalytic Synthesis of 2-Deoxyglycosides[END_REF] afforded the corresponding glycosides 8a, 8b and 9 in high α-stereocontrol (>30:1α:β) and yields (72-79%) within 1-4 h (entries 8-10). Under the Cu-catalysed reaction, peracetylated glucal 5c could also be activated, however it afforded Ferrier type glycoside 10 as the major product (67%, 78:22 α:β, entry 11). [START_REF]acetate) at C-3, since glucals substrates favour a bigger shift toward 5 H4 conformations and undergo rearrangement/substitution more[END_REF] Conversely, activation of peracetylated L-fucal 6 [START_REF] Sau | Substrate-Controlled Direct alpha-Stereoselective Synthesis of Deoxyglycosides from Glycals Using B(C6F5)3 as Catalyst[END_REF] afforded 2,6dideoxyglycoside 10 in 71% yield within 2 h and in a >30:1 α:β ratio (entry 12).

Table 2. Reaction scope between glycals 1b-1h, 5a-5c and 6 with acceptors 2a or 2g.

[a] Isolated yield. [b] Determined by 1 H-NMR. [c] Reaction was carried out at 70° C. [d] reactions using Cu II-a or Cu II -b afforded inseparable anomeric mixtures of Ferrier and glycoside products (13:87 (79%) and 25:75 (67%), respectively). [d] The reaction favoured the Ferrier product over the 2-deoxyglycoside product (15%)). To probe the mechanism of our reaction, a 3:1 α/β-anomeric disaccharide mixture (4j, see ESI for details) was subjected to the reaction conditions in the absence and presence of the OH acceptor and gave no change in the anomeric ratio, indicating that the high α-selectivity is not the result of anomerization (Fig. S1 in ESI). Reaction with deuterated galactal 12 yielded disaccharides 13a and 13b in 70% yield as a 2:1 mixture of cis:trans products in favor of equatorial protonation and axial addition of the OH nucleophile across the double bond, (Scheme 2 and fig. S2). In the presence of 20 mol% of DIPEA the reaction between galactal 1a and 2d using either Cu I -b or Cu II -b was inhibited, which suggests that the presence of brØsted acid might be involved in the reaction. [START_REF] Sletten | Are Bronsted Acids the True Promoter of Metal-Triflate-Catalyzed Glycosylations? A Mechanistic Probe into 1,2-cis-Aminoglycoside Formation by Nickel Triflate[END_REF] To evaluate this, reactions between both 1a and 1b and 2a in the presence of 0.1-2 mol% of TfOH were carried out in toluene (Table S2 in ESI). In general, lower conversions (20-60%) and selectivities (3:1 α:β ratios) were observed in all cases including inseparable mixtures of other side-products (see ESI for details). This suggests that although a catalytic amount of TfOH alone is able to activate both armed and disarmed glycals, Cu(I) is essential for effective and controlled catalysis. [START_REF] Varki | Biological Roles of Glycans: Two Decades Later[END_REF] H-NMR spectroscopy studies carried out at room temperature in toluene-d 8 of equimolar mixtures of Cu(I) catalyst and glycoside acceptor 2a showed signal broadening for 2a, suggesting an interaction between Cu(I) and the alcohol (Fig. S3). NMR mixtures of 1 eq. (Cu I OTf)2.C6H6 and galactal 1a also showed slight H-shifts and peak broadening associated with an interaction between the alkene protons in 1a (from δ 6.22 to 6.21 ppm), while mixtures of 1 eq. Cu II (OTf)2 and 1a led to quick glycal activation and formation of degradation products (See Figs. S4-S6 in ESI). On the other hand, no interactions between deactivated per-acetylated galactal 1b and Cu(I) were observed by [START_REF] Varki | Biological Roles of Glycans: Two Decades Later[END_REF] H-NMR at room temperature, while slow degradation of 1b in the presence of Cu(II)OTf2 could be seen over time (Fig. S7 andS8). Moreover, reaction between 1a and 2c using 5 mol% Cu II (OTf)2 and 10 mol% sodium ascorbate (to generate Cu(I) in situ) also afforded 4c in 89% yield and >30:1 α:β (Table 2, entry 2 [d] ). This result further indicates that Cu(I) is important for effective catalysis towards stereoselective glycosylation. Scheme 2. Glycosylation of deuterated glycal donor 12 with 2a.

Entry

To better understand the interactions between the Cu catalysts and both donor 1b and the OH nucleophile, cyclic voltammetry experiments were undertaken. The electrochemical behaviors of both Cu (I) and Cu(II) were studied (Figure 1, [Cu I (OTf)]2 data shown). [START_REF]i d e o r triflate anions were used indiscriminately (as they exhibited the same electrochemical behavior in this instance) to avoid any binding competition issues[END_REF] The reduction of Cu(II) to Cu(I) is a reversible transfer occurring around E1/2 = +0.8 V vs SCE, while the electrodeposition and oxidative dissolution of Cu(0) occurred at +0.1 V and +0.6 V, respectively. The interaction with dihydropyran (DHP), as a model, was first investigated (Figure S13). Based on the shift of potentials observed for the reduction peak of Cu I , we can conclude that Cu I is stabilized compared to Cu 0 due to the formation of a Cu I -DHP complex, [START_REF]acetate) at C-3, since glucals substrates favour a bigger shift toward 5 H4 conformations and undergo rearrangement/substitution more[END_REF][START_REF]i d e o r triflate anions were used indiscriminately (as they exhibited the same electrochemical behavior in this instance) to avoid any binding competition issues[END_REF][START_REF] Salomon | Cationic Olefin Complexes of Copper(I) -Structure and Bonding in Group Ib Metal-Olefin Complexes[END_REF] suggesting that the complexation of one DHP to Cu I through the π system is possible.

The interaction of Cu(II) and Cu(I) with tri-acetyl galactal 1b was next considered (see ESI, Figure S14), since previous reported methods failed to activate electron-poor glycals towards direct glycosylation [START_REF] Sau | Substrate-Controlled Direct alpha-Stereoselective Synthesis of Deoxyglycosides from Glycals Using B(C6F5)3 as Catalyst[END_REF][START_REF] Palo-Nieto | Cooperative Bronsted Acid-Type Organocatalysis for the Stereoselective Synthesis of Deoxyglycosides[END_REF][START_REF] Sau | Palladium-Catalyzed alpha-Stereoselective O-Glycosylation of O(3)-Acylated Glycals[END_REF] , we wanted to better understand the interaction of this substrate with the metal. Interestingly, the pattern observed is somehow different with galactal than with DHP due to the possible complexation of copper by acetates. In the presence of 1b, the reduction peaks of both Cu(I) and Cu(II) were shifted towards lower potentials.. These observations are consistent with the formation of different Cu(I)-1b complexes and Cu(II)-1b. The latter is likely the result from an interaction between Cu(II) and acetates as expected from the oxophilicity of Cu(II) and also since no interaction with C=C bond was observed in the CV experiment with cyclohexene. However, the Cu(I)-1b has a lower stoichiometry than the Cu(I)-cyclohexene one, in agreement with the formation of aggregates (see ESI Figure S15). The interaction between the OH nucleophile and copper was also studied and BnOH was chosen as a model substrate, as it was the simplest alcohol used in our scope. In the presence of BnOH, the reduction peak of Cu(II) was shifted towards lower potentials, as was the reduction peak of Cu(I) (See Supporting

I (µA) E (V)
Information, Figure S16). These observations are consistent with the formation of complexes between BnOH and both Cu(I) and Cu(II) with a higher stoichiometry for the Cu(II) complex (see Supporting Information, Figure S17). Finally, in order to study the nature of the catalyst under conditions close to the catalytic ones, increasing amounts of galactal 1b were added to a mixture of Cu I (OTf) (Cu I -b) in the presence of an excess of BnOH (158 equiv). [START_REF]The model competition of BnOH with cyclohexene was also studied see SI for details[END_REF] The reduction peak of Cu(I) was shifted towards lower potentials (Figure 1 and Figure S20). This is consistent with the formation of a complex between Cu(I) and 1b even in the presence of a large excess of BnOH. The shifts of both reduction and oxidation peaks associated with the Cu(II) and Cu(I) redox couple measured are not trivial, but the addition of 1b seems to poorly impact them, which is consistent with the formation of a Cu(II)-1b complex of stoichiometry similar to that of the Cu(I)-1b complex. The slope of the E vs pL plot for the potential associated to Cu(I)/Cu(0) is close to 0.06 (Figure 1), indicating a 1:1 stoichiometry for Cu(I) and 1b. When comparing with the slope observed in the absence of BnOH (0.02, Figure S14) it appears that BnOH is able to dissociate the metallic clusters formed between Cu(I) and 1b. Indeed, the slope associated to Cu(II)/Cu(I) is close to 0 indicating that the complexes formed between Cu(II) and 1b also have a 1:1 stoichiometry (as observed in the absence of BnOH).

From our initial mechanistic studies one can conclude that (i) Cu(I)OTf leads to activation of the carbon-carbon double bond of glycals and that in the case of electron-deficient enol ethers, Cu(I)-interactions with the acyl groups facilitate the activation of the "disarmed" glycal; [START_REF]activation in which traces of triflic acid or another proton donor species are involved can not be completely discarded[END_REF] (ii) the active form of the catalyst is likely a complex involving both the glycal and the OH nucleophile [Cu(Glycal)(ROH)] + . Two possible isomers of [Cu(1b)(ROH)] + were optimized using DFT at the B3LYP/def2-SVP level to help us provide some insights with regards to the active species (see the SI for computational details): one featuring a copper-acetate interaction ("up") and one with the copper in the position opposite to the acetate moieties ("down"). Upon coordination to the C=C bond, copper induces a modification of the electronic structure (Figure S21 and Table S3, ESI). The electronic density on the carbon C 2 increases (0.063 for up and -0.161 for down) while the one on O 1 and C 1 (+0.075 for up and +0.104 for down) decreases. In the meantime, the C=C bond length increases (+0.032 for up and +0.040 for down) while the C=O bond shortens (-0.008 for up and -0.019 for down). All these observations suggest that these complexes have a carbocationlike behavior. Based on these observations, a mechanism can be proposed involving two [Cu(1b)(ROH)] + complexes "up" or "down" (A) which can form two different oxocarbenium intermediates (B) that are quickly trapped by the OH nucleophile to yield the glycoside products (Scheme 3). Two alternative pathways can be invoked for the nucleophile addition, one involving an outer sphere attack of the OH nucleophile (not coordinated to Cu) on the carbocation ((B) pink arrow) and a second one with an inner sphere addition involving the ROH coordinated to Cu ((B) red arrow). Based on the labelling experiments (Scheme 2), it seems that a bottom face attack of the nucleophile is preferred.

In summary, we have shown that adjusting the oxidation state and counter ion of Cu can be exploited to control its reactivity profile. We demonstrate for the first time the Cu Icatalyzed direct α-stereoselective glycosylation of glycals to give 2-deoxyglycosides in high yields and α-stereocontrol. The reaction is tolerant of most common protecting groups in both the glycal donor and nucleophile acceptor, including electrondeficient galactals. Initital investigations indicate that the Cucatalyzed enol ether activation/functionalization may proceed through dual activation of both the enol ether and nucleophile, whereby the Cu catalyst plays a key role in effective glycosylation and stereocontrol. Understanding the reactivity of these type of catalytic systems is of fundamental importance to be able to exploit the repertoire of transition metal catalysis in synthesis. Scheme 3. Proposed mechanism and 3D structures of mixed complexes [Cu I (1b)(ROH)] + optimized at the DFT B3LYP/def2-SVP level.

Figure 1 .

 1 Figure 1. top: CV towards oxidation potentials of [Cu I (OTf)] (2 mM) in the presence of benzyl alcohol (158 equiv) with increasing amounts of 1b (0, 1, 2, 5, 14, 50 equiv), recorded at a steady glassy carbon disk electrode (d = 3 mm) in nitromethane containing n-Bu4NBF4 (0.3 M) at 20 °C with a scan rate of 0.5 V s -1 .. bottom: Potential-pL (L = tri-acetyl-galactal, pL = -log(L)) plot constructed using the E(1/2) values extracted from the CV plots in the presence of excess BnOH (158 equiv). SCE = saturated calomel Electrode

Acknowledgements

MCG, RJ and AS thank the European Research Council (ERC-COG: 648239) and CPN thanks RS Newton Fellowship. LG thanks the CNRS, the ENS/PSL and the ENS Paris Saclay (Ph.D. scholarship to P.-A.P.) for financial support. IC and MBMT thank Fundação de Amparo à Pesquisa do Estado de São Paulo -FAPESP Proc n. 2016/21194-6 Keywords: Stereoselectivity • Copper catalysis • Glycosylation • Enol ether • Glycals


Seonho Seok
email: seonho.seok@u-psud.fr

Giorgio Cristiano

Taekwang Jang

Design of Ultra-Low Power Pulse-Driven MEMS Oscillator

Keywords: Low power, pulse-driven, MEMS oscillator

This paper presents an energy efficient pulse-driven on-chip MEMS oscillator which consists of MEMS resonator and sustaining CMOS circuit. Conventional oscillators are driven by means of an inverter-based amplifier low-pass filtered through a series resistor. However, this architecture suffers from multiple energy losses. Firstly, the inverter amplifier is driven by a sinusoidal input, thus consuming significant static power. Additional power is also consumed by the series resistance. The proposed pulsed driver provides a 180 o degree shift, effectively replacing the amplifier. The driver injects energy in the oscillator by periodically switching one oscillator end to VDD when the other end reaches the bottom voltage, and to VSS when the other end reaches the peak voltage. The proposed configuration reduces the static power consumption, as the switch is driven by two rectangular voltages and reduces leakage by activating only one of the two switches at a time. This pulse-driven oscillator, running at 33.14kHz, is simulated to consume 835pW when driven at 0.8V, leading to more than x15 power saving with respect to the traditional configuration, which consumes 13.2nW.

I. INTRODUCTION

The Internet of things (IoT) is a system of interrelated computing devices being able to transfer data over a network without requiring human-to-human or human-to-computer interaction. Miniaturization and interactive communication are the two main topics that dominate the recent research in the internet-of-things (IoT) [START_REF] Jang | Circuit and system designs of ultra-low power sensor nodes with illustration in a miniaturized GNSS logger for position tracking: Part II-Data communication, energy harvesting, power management and digital circuits[END_REF][START_REF] Jeong | A fully-integrated 71 nW CMOS temperature sensor for low power wireless sensor nodes[END_REF][3][START_REF] Kim | A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting[END_REF][START_REF] Lee | Circuit techniques for miniaturized biomedical sensors[END_REF]. The next generation of computing platforms, which is the IoT, increases proximity to the source of the information rather than to humans requesting much more aggressive miniaturization. The advantages of miniaturization are lowering cost, space reduction, and enhanced mobility. To this sense, mm-scale computer has been recently reported by university of Michigan for energy efficient sensor node for new IoT application [START_REF] Www | Millimeter-Scale Computers: Now With Deep-Learning Neural Networks on Board[END_REF]. All the functional ICs of the mm-scale computer have been designed to be operational only with the energy harvested photovoltaic cell integrated with the mm-scale computer. From technological point of view, the mm-scale computer has been implemented by stacking of multiple Si chips. Chip stacking has been done by die attach with gluing and wire bonding. As wire bonding has been used, epoxy overmolding should be followed to finalize the die stacking packaging. To improve technological limit of precision of the conventional packaging processes such as wirebonding, flip-chip bonding for miniaturization of IoT system, a novel packaging and heterogeneous integration method is highly required. Sensor node for IoT needs an essential element for synchronization between computing devices, which is socalled timer. For timekeeping application, 32 kHz quartz tuning fork crystals and oscillators are mostly used. Key specifications for this clock are frequency accuracy, PCB area and power consumption. Size reduction rate of 32 kHz quartz oscillator tends to be slowing due to scaling limitations and packaging/assembling difficulties and thus MEMS-based oscillators matching or outperforming the quartz counterparts have been introduced in the past decade. Indeed, MEMS-based oscillators have merits of reduced size as they are fabricated by semiconductor process. However, MEMS resonator and ICs are still being packaged by using conventional wire-bonding or flip-chip bonding technique in 2D or 3D [START_REF] Fischer | Integrating MEMS and ICs[END_REF]. Advanced packaging technique such as FOWLP (Fan-Out Wafer Level Package) could provide much lower packaging profile which is essential for miniaturized IoT systems.

In this paper, MEMS resonator and pulse-driver are designed for low-power timekeeper. MEMS resonator design and pulsedriven MEMS oscillator design are explained in section 2 and section 3 respectively. Section 4 will conclude our work.

II. MEMS RESONATOR DESIGN

MEMS resonator in flexural-mode and its equivalent massspring-damper model are shown in Fig. 1. Governing equation of the MEMS resonator is given as below.

𝑚 "## 𝜕𝑥 & 𝜕𝑡 & + 𝑐 "## 𝜕𝑥 𝜕𝑡 + 𝑘 "## 𝑥 = 𝐹 " (𝑡)
,where meff is effective modal mass, ceff is effective damping coefficient, and keff is effective stiffness.

The effective modal mass is designed through ANSYS modal analysis as shown in Fig. 2 and the effective stiffness and damping coefficient are determined with following equations.

𝑘 "## = 𝜔 0 & × 𝑚 "## 𝑐 "## = 𝜔 0 𝑚 "## 𝑄
,where wr is angular resonant frequency.

Electrostatic force Fe(t) is given by

𝐹 " (𝑡) = 𝜂 " 𝑣 67 (𝑡)
,where he is electromechanical coupling factor.

Equivalent electrical circuit parameters can be found as follows. Conventional drivers for the resonator are implemented by an inverter based amplifier in series with a resistor as shown in Fig. 4. Such oscillators have critical limitations in reducing the power consumption. First, the inverter-based amplifier suffers from the short circuit current while buffering the sinusoidal signal from the resonator to a square wave to drive the series resistor Rs. Second, the series resistance also dissipates a significant power due to a large voltage applied to it. Therefore, it is necessary to develop a circuit technique that improves energy regeneration efficiency by reducing the energy loss in the amplifier and the regeneration resistor. A pulsed driver, which was proposed to implement an ultralow-power crystal oscillator [START_REF] Yoon | A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks[END_REF], is an effective way to improve the energy efficiency of the MEMS oscillator. Fig. 5 shows a circuit schematic of the pulsed driver based oscillator. In this circuit, a resonation voltage, OSCIN, is buffered to a delaylocked loop (DLL) to generate two narrow pulses that are located at the peaks of the sinusoidal oscillation voltages, OSCIN and OSCDRV. Level shifters provide proper gate voltages for MN1 and MP1 to inject the energy into the resonator. As the switching transistors, MN1 and MP1, are turned on only for a short duration while the oscillation voltages reach their peaks, the voltage across the switches during the energy injection is small so that the most of the energy driven from the supply is delivered to the resonator with a minimal conduction loss. Furthermore, the static power consumption of MN1 and MP1 is very low because the transistors receive sharp rectangular pulses to reduce the leakage current.

To find the theoretical limit of the power consumption of the MEMS resonator, a theoretical analysis and the simulation is performed as follows.

First, four capacitors composing the MEMS oscillator can be merged as the following equation so that the resonator model is simplified to a series LCR circuit.

(

Then, by assuming an exponential settling of OSCDRV node voltage during the injection time, the residual voltage at the peak of the oscillation, ΔV, can be expressed as the following equation:

(2)

Where TON and RSW are the turn-on time and resistance of the switch driver, respectively. Ceq,sw is the equivalent capacitance that the switch driver sees toward the resonator which is equal to . A settling factor, γ, is adopted to express how much exponential settling was completed while the switch is turned on. By rearranging (2), ΔV can be found as

(3)
Consequently, the oscillation amplitude can be found by relating VSUP and ΔV. [START_REF] Kim | A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting[END_REF] Note that the oscillation amplitude is inversely proportional to the switch resistance when RSW is large as can be seen through the following approximation.

(5) On contrary, the oscillation amplitude reaches to its peak when RSW becomes very small so that γ is close to 1.

(6) ( )

1 2 eq x P O O C C C C C = + ! ! , 1 2 2 ON SW eq sw T R C DDL SSL OSC SUP OSC V V V V V e V V V g - ae ö - - +D ç ÷ D = - ç ÷ è ø - +D = ( ) 2 1 O O P C C C + ! ( ) , tanh . 2 ON SUP OSC SW eq sw T V V V R C ae ö D = - ç ÷ ç ÷ è ø ( ) , , 2 1 2 ,
T C R C V V R C C C T C R C L C p ae ö ç ÷ ç ÷ è ø = ae ö + + ç ÷ ç ÷ è ø ! ( ) ( ) , , 2 1 2 2 , 1 2 2 2
ON eq sw SW eq sw OSC

x P O O X eq m eq SUP ON SW eq sw x P O O T C R C V R C C C L C L C V T R C R C C C p p » + = × + ! ! ( ) , ,max 2 1 2 , eq sw OSC SUP x P O O eq sw x eq C V V R C C C C L C p = + + !

ΔV

The oscillation amplitude in (4), ( 5) and ( 6) are plotted in Fig. 7. The discussion to this point shows that the pulsed driver oscillator's amplitude is different from a conventional oscillator model whose energy is regenerated by a trans-conductance circuit. In the conventional mode, the regeneration current amount is proportional to the oscillation amplitude, so there exists a mathematical limit in reducing the oscillation amplitude to achieve the low power. However, a pulsed driver can sustain its oscillation with an arbitrarily small oscillation amplitude as found in ( 4). This gives a significant advantage in achieving the low power operation as can be found in the following derivations. The energy that needs to be regenerated by the pulsed driver can be found as the following equation: [START_REF] Fischer | Integrating MEMS and ICs[END_REF] Then, the energy provided by the supply can be calculated by integrating the current during the switching operation. [START_REF] Yoon | A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks[END_REF] By combining ( 5), ( 7) and ( 8), the energy derived from the supply can be found as the following equation when RSW is large.

(9) This implies that a large RSW reduces the oscillation amplitude by limiting the energy driven by the supply. When RSW is small enough to achieve a full exponential settling during the energy injection period, the maximum energy is driven from the supply as the following equation:

(10) Fig. 8 shows ESUP as a function of switch resistance. ESUP is inversely proportional to RSW when it is large while it asymptotically approaches ESUP,max when RSW becomes small.

While a large RSW is advantageous in reducing the energy driven from the supply at each restoration cycle, the regeneration efficiency is higher with a small RSW as the voltage across the switch becomes smaller.

(11) Therefore, a given amplitude of the oscillator for its jitter and long-term stability specification, it is more advantageous to reduce the supply voltage and operate the oscillator with a small RSW rather than including a large RSW with a high supply voltage.

IV. CONCLUSION

Ultra-low power MEMS oscillator for timekeeper of future IoT elements is proposed and designed. Theoretical background for low power consumption of the proposed pulsed driver based oscillator compared with inverter based amplifier is presented.

D

  Fig. 1 MEMS resonator and its equivalent model with electrostatic transduction

Fig 4 Fig 5 :

 45 Fig 4: Conventional MEMS resonator

Fig 6 :

 6 Fig 6: Waveforms of the signals in the pulsed driver based oscillator

Fig 7 :

 7 Fig 7: Simulation results of the oscillation amplitude Fig 8: Simulation results of the regeneration energy

Table 1 :

 1

Design parameters of MEMS resonator Fig. 3 Electrical model of a resonator III. PULSE-DRIVEN MEMS OSCILLATOR