Jiang Haitao

Xu Yun

Liao Yin

Jin Guojie

Chen Guoliang

UKCF: A New Graphics Driver Cross-platform Translation Framework for Virtual Machines

Keywords: virtualization, binary translation, operating system, driver, crossplatform

Virtual machine with dynamic binary translation system is the key technology to solve software compatibility problem. But traditional user space binary translation systems can't translate hardware drivers such as graphics drivers in operating system kernel directly, instead, they need translate the entire operating system. To solve this problem, we designed a new binary translation framework. This framework has a user space translator and a kernel space translator working coordinated and can translate graphics drivers directly. Compared with traditional binary translation systems, this framework can significantly improve the performance of the virtual machine. Based on our experiment, the multimedia performance of virtual machines can been improved about 30%.

Introduction

At present, with the innovation of computer architecture, Software compatibility issue has become increasingly prominent. Virtual machine (VM) can run binary format software on different architectures without modifying of source code, and thus become an important technology to solve this problem [START_REF] Smith | A unified view of virtualization[END_REF] [START_REF] Altman | Welcome to the Opportunities of Binary Translation[END_REF] . Graphic driver translation is a key problem in software compatibility issue because most multimedia softwares need graphic drivers working with them.

The key technology to run software on different architectures is binary translation which can translate an instruction stream based on one ISA (Instruction System Architecture) into the corresponding instruction stream based on another ISA [START_REF] Rl Sites | Binary translation[END_REF] . There are two kinds of binary translation systems: static binary translation system and dynamic binary translation system. Interactive virtual machines always use dynamic translation system, which translates instructions dynamically during execution of programs.

Traditional virtual machines with dynamic binary translation run upon host operation system (such as VMware [3] , QEMU [5][6] , virtualbox [4] ), these virtual machines have some advantages: clean hierarchy, easy to use, easy to migrate from one compute to another. But, they can't translate hardware drivers such as graphic drivers in operating system kernel directly; instead, they need translate the entire operating system [3][4][5] . This kind of translation mode brings about significant additional time consuming. At present, large-scale multimedia software usually need huge amount of computing resources and very high performance requirement, so this kind of low efficiency translation mode usually can't meet the demand.

To solve this problem, we designed a new binary translation framework (User space translator and Kernel space translator Cooperate Framework, UKCF). This framework has two translators, one works in user space, and the other works in operating system kernel space to translate the graphic driver directly. Compared with traditional binary translation systems, UKCF needn't translate the instructions of the entire operating system; instead, it only need translate the instructions of the application software's operating system kernel module (such as a graphic driver). UKCF can significantly improve the performance of the virtual machine because it reduces the number of instructions which need to be translated.

The remainder of this paper is as follows. In section II, we introduce existing widely used virtual machines, discuss why they can't translate graphic driver directly. In section III, we introduce the design and structure of UKCF. The experiment results and analysis are drawn in section IV.

Existing technology

VMware is a widely used business virtual machine. It provides an abstraction of x86 PC hardware to run multiple operating systems at the same time. As a mature business system used by millions of users, VMware has high stability and efficiency. But, it has no dynamic binary systems and can't run application softwares on different ISA, such as MIPS. So it can't be used to solve the graphic driver translation problem.

Virtualbox is a powerful x86 virtualization software for enterprise and home use which is freely available as Open Source Software under the terms of the GNU General Public License (GPL). It has comparative performance with VMware. It also has no dynamic binary systems, and is not a solution to graphic driver translation problem.

QEMU is a multihost, multitarget virtual machine. It can run on multiple host ISA, such as X86, X86-64, MIPS, PowerPC and so on, and it can emulate multiple guest ISA too [START_REF] Bellard | Qemu, a fast and portable dynamic translator[END_REF] . So it can be used to resolve software compatibility problem. QEMU runs upon host operating systems and it can only translate the instructions in user space. Graphic drivers are embedded in operating system kernel space, so it can't translate the instructions of graphic drivers directly. Fig. 1 gives a clear view of this problem.

Kernel-based Virtual Machine (KVM) [START_REF] Kivity | kvm: the Linux virtual machine monitor[END_REF] , is a subsystem of Linux operating system which leverages virtualization extensions of commodity x86 processors to add a virtual machine monitor capability to Linux. Using KVM, multiple virtual machines can run on Linux operating system. This is an operating system level virtualization system which can run in kernel space. But it has no dynamic binary translation module so can't be used to solve the graphic driver translation problem.

From fig. 1 shows that, to translate graphic drivers directly, we need to translate and execute the instructions of graphic drivers in operating system kernel space (as fig. 2 shows). In view of this point, we designed UKCF, a new binary translation framework with an operating system kernel space translator to solve this problem.

Design of UKCF

Workflow of traditional graphic drivers

Graphic drivers are embedded into operating system kernels. When an application software needs to use the graphic driver, it first calls an operating system kernel API and traps into the kernel, and then call the functions of the graphic driver. During the execution of the graphic driver, it may call other operating system kernel functions. Fig. 3 shows the workflow of graphic drivers.

Two calling processes of fig. 3 must be handled by UKCF, one is the calling process from the kernel API to the graphic driver, and the other is the calling process from the graphic driver to the operating system kernel. When a kernel API calls a function of the graphic driver, UKCF needs intercept the calling action and start the translation mechanism to execute the instructions of the graphic driver. When the graphic driver calls a function of the operating system kernel, UKCF needs end the translation mechanism and give the execution control to the operating system kernel. The detail method of this switching will be introduced in next section.

Workflow of the graphic driver in UKCF

In UKCF, instructions of the graphic driver and instructions of the operating system kernel have incompatible ISA, so, traditional kernel module loading method [8] can't embed the graphic driver into the kernel. To embed the graphic driver into the kernel, we treat the graphic driver as a stream of data and use an array in the operating system kernel to store it. When a function of the graphic driver is called, UKCF will get the address of the function, translate and execute the instructions of the function.

During the application software's execution, only a part of the instructions needs to be translated, and the other instructions must be executed directly. To solve this problem, UKCF needs to do two additional works, one is monitoring entrance points and exit points, and the other is saving and loading the translation context. When the operating system kernel calls a function of the graphic driver, the function's address is an entrance point. We use function shell technology to catch the entrance point. To work with the operating system kernel, the graphic driver must register its functions to the kernel [8] . To catch the functions' calling time, UKCF doesn't allow the graphic driver register its functions to the kernel directly, instead, UKCF register the shelled functions of the graphic driver to the operating system kernel. Fig. 4 shows this technology.

Figure 4: the shelling technology of UKCF

The shell of a function is another function, it is registered to the calling point of the shelled function. So when the kernel calls the shelled function, the shell function is called. When the shell function is called, it sends the address of the shelled function to UKCF, UKCF loads the translation context and starts the translation. The shell function also saves the return address of the shelled function, and when the shelled function ends, UKCF save the translation context and return to this address. This solves the entrance point monitoring problem.

UKCF monitors all the jump instructions' target address, if the target address is not in the content of the graphic driver, this means the target address is a kernel function. UKCF changes the pc to the target address and gives the control to the kernel. This solves the exit point monitoring problem.

Structure of UKCF

Fig. 5 shows the structure of UKCF. It contains six modules: a user space translator, a kernel space translator, a graphic driver shell, a jump monitor, and two CPU simulators. The user space translator is the first starting module of UKCF, it loads the application software and translates it. CPU simulator simulates a guest ISA CPU to execute the instructions. In UKCF, the CPU simulator is the same as traditional virtual machines [5] . The graphic driver shell monitors the entrance point of the graphic driver and gives the entrance address to the kernel space translator. The kernel space translator works together with the jump monitor, when the jump monitor catches a call from the graphic driver to the operating system kernel, the kernel space translator stops translation, saves the translation context, modifies the pc and gives control to the operating system kernel.

Experiment and Analysis

Traditional user space binary translation systems can't translate graphic drivers in operating system kernel directly, instead, they need translate the entire operating system. UKCF can translate graphic drivers directly in kernel space, so the number of instructions needing to be translated is reduced. To analyse the performance of UKCF quantitatively, we defined the concept of performance loss ratio (PLR), for a given instruction stream i with execution time t 1 on its original ISA platform, if its execution time on a different ISA platform with a binary translation system is t 2 , then the instruction stream PLR i of the binary translation system is:

PLR i = t2/t1 (1)
The PLR of the binary translation system is the average of the PLR i :

PLR ∑ / (2)
In order to facilitate the presentation, we call the traditional translation mode (translating the entire operating system) scheme 1, call the UKCF's translation mode (translating the graphic driver directly) scheme 2. We use NUM 1 to identify the number of instructions needing to be translated by scheme 1, NUM 2 to identify the number of instructions needing to be translated by scheme 2, t to identify the average execution time of one instruction, TIME 1 to identify the execution time of scheme 1, TIME 2 to identify the execution time of scheme 2, then:

TIME 1 = (3) TIME 2 = (4)
So the performance improved percentage of UKCF is:

P = (TIME 1 TIME 2 ) / TIME 1 = (5)
Formula 5 shows a fact that, the execution time saved depends on the reduction percentage of the instructions needing to be translated. We tested the reduction percentage of the instructions needing to be translated, the host ISA platform is the Loongson 3A platform [START_REF] Wei-Wu | Godson-3: A Scalable Multicore RISC Processor with x86 Emulation[END_REF] [START_REF] Wei-Wu | Micro-architecture of Godson-3 Multi-Core Processor[END_REF] , which has a MIPS compatible ISA. The host operating system is Linux, the guest ISA is x86 IA-32. The compared binary translation system is QEMU, which has been proven to be a very fast dynamic binary translation virtual machine [START_REF] Bellard | Qemu, a fast and portable dynamic translator[END_REF] . We used mplayer [13] and a group of videos as the testing set, the results are shown by fig. 6: Fig. 6 shows that, UKCF only needs to translate about 60% instructions. In our experiment environment, the PLR of QEMU is about 6. We can compute the performance improved percentage of UKCF using formula 5, the result is about 33%. We tested the result based on real videos played by mplayer, the experiment results are shown by fig. 7:

Conclusion

This paper designed a new graphics driver cross-platform translation framework named UKCF for virtual machines. Compared with existing dynamic binary translation system needing translate the entire operating system to run the graphic driver, UKCF can translate and execute the graphic driver in operating system kernel directly. Experiment results improved that UKCF runs faster than existing binary translation systems about 30%.

How to improve the performance is the key problem of binary translation systems. How to make good use of the advantages of kernel space, such as memory allocation privilege and direct hardware access privilege, to further improve the performance of UKCF, is the future research goal.

Figure 1 :

 1 Figure 1: the locations of QEMU and graphic drivers

Figure 3 :

 3 Figure 3: the workflow of graphic drivers

Figure 5 :

 5 Figure 5: the structure of UKCF

Figure 6 :

 6 Figure 6: experimental results: the numbers of translated instructions of QEMU and UKCF

Figure 7 :

 7 Figure 7: experimental results: the performance compare of QEMU and UKCFFrom fig.7we can see that, during the same time, UKCF can play about 30% more frames than QEMU, this result confirms the analysis based on formula 5.


Mouna Karmani
email: mouna.karmani@yahoo.fr

Chiraz Khedhiri
email: chirazkhedhiri@yahoo.fr

Belgacem Hamdi
email: belgacem.hamdi@issatgb.rnu.tn

Amir-Mohammad Rahmani
email: amir.rahmani@utu.fi

Ka Lok Man

Kaiyu Wan
email: kaiyu.wan@xjtlu.edu.cn

Design of a reliable XOR-XNOR Circuit for Arithmetic Logic Units

Keywords: XOR-XNOR circuits, Concurrent Error Detection, fault-secure property, self-testing property, fault model

Computer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology.

Introduction

With the continuous increase of integration densities and complexities, IC design has become a real challenge to ensure the necessary level of quality and reliability especially for high performance applications [START_REF] Bushnell | Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits[END_REF][START_REF] White | Scaled CMOS Technology Reliability Users Guide[END_REF]. Thus, computer systems used for instrumentation, measurement, and advanced processing in safety-critical applications like avionic, automotive and biomedical applications require high reliable ICs to ensure the accuracy of analytical data they process [START_REF] Edward | Performance and Reliability of Integrated Circuits within Computing Systems[END_REF]. In fact, a microprocessor is an internal hardware component that performs the mathematical calculations required for computers to run programs and execute commands while ALUs in microprocessors are combinatorial circuits allowing computers to add, subtract, multiply, divide and perform other logical operations at high speeds. Thanks to advanced ALUs, modern microprocessors are able to perform very complicated operations which make ALUs among the essential elements of computers. Consequently, designing efficient reliable ALUs is an important challenge in computer-based safety-critical systems [START_REF] Hamdi | Pass Transistor Based Self-Checking Full Adder[END_REF]. Thus approaches and techniques to increase the reliability of these digital blocks are gaining more importance.

Interest in on-line error detection continues to grow as VLSI circuits increase in complexity [START_REF] Nicolaidis | On-line testing for VLSI: state of the art and trends[END_REF]. The property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED) [START_REF] Mouna | A Concurrent Error Detection Based Fault-Tolerant 32 nm XOR-XNOR Circuit Implementation[END_REF]. Concurrent checking is increasingly becoming a suitable characteristic thanks to its ability to detect transient faults that may occur in a circuit during normal operation. CED also provides an opportunity for self-diagnosis and self-correction within a circuit design, especially in specific applications domains requiring very high levels of reliability [START_REF] Hamdi | Pass Transistor Based Self-Checking Full Adder[END_REF] Since XOR-XNOR circuits are basic building blocks in Arithmetic Logic Units, the performance and reliability of these digital circuits is affected by the individual performance of each XOR-XNOR included in them [START_REF] Nicolaidis | Fault-Secure Parity Prediction Arithmetic Operators[END_REF][START_REF] Chowdhury | A High Speed Transistor Full Adder Design using Novel 3 Transistor XOR Gates[END_REF]. Thus, XOR-XNOR circuits should be designed such that they indicate any malfunction during normal operation. In this paper, we propose a CED based reliable new design XOR-XNOR circuit implementation using the 32 nm process technology. The circuit is analysed in terms of fault-secure and self-testing properties with respect to the set of fault models including logical stuck-at faults, transistor stuck-on and transistor stuck-open faults.

The organization of this manuscript is as follows: the CED based reliable circuits technique is first presented in Section 2, followed by the proposed XOR-XNOR circuit implementation in Section 3. Finally, the circuit's fault analysis with all parasitic is illustrated in Section 4.

The CED based reliable circuits

Concurrent error detection verifies the results delivered by a circuit during its normal operation. Concurrent error can be achieved by means of duplication and comparison. However, this technique requires more than 100% hardware overhead [START_REF] Nicolaidis | Carry Checking / Parity Prediction Adders and ALUs[END_REF]. In fact, the CED technique presented in this paper is achieved by means of output duplication technique. The output of a circuit has a certain property that can be monitored by a checker. If an error causes a violation of the property, the checker gives an error indication signal [START_REF] Zeng | Finite State Machine Synthesis with Concurrent Error Detection[END_REF]. The concurrent error detection property can be used for verifying the fault secure or/and the self-testing properties for circuits requiring high level of reliability and availability.

The Fault-Secure property: A circuit is fault-secure for a set of faults, if for any valid input code word and any single fault, the circuit either produces an invalid code word on the output or doesn't produce the error on the output [START_REF] Hamdi | Pass Transistor Based Self-Checking Full Adder[END_REF]. In fact, ensuring the faultsecure property is essential for achieving safety and reliability in critical systems. Another useful property is the self-testing one.

The Self-Testing property: For each modelled fault there is an input vector occurring during normal operation that produces an output vector which do not belong to the output code. This property avoids the existence of redundant faults. If the circuit is both fault-secure and self-testing it is said Totally Self Checking (TSC property) [START_REF] Nicolaidis | Carry Checking / Parity Prediction Adders and ALUs[END_REF]. The concept of TSC circuits was first proposed in [START_REF] Anderson | Design of totally self-checking check circuits for m-out-of-n codes[END_REF] and then generalized and detailed in [START_REF] Pradhan | Error correcting codes and self-checking circuits in fault-tolerant computers[END_REF]. Thus, the combination of the fault secure and the self-testing properties offers the highest level of protection. The fault secure property is the most important one, since it guarantees error detection under any single fault, but it is also the most difficult to achieve [START_REF] Nicolaidis | Carry Checking / Parity Prediction Adders and ALUs[END_REF].

The proposed XOR-XNOR circuit implementation

In this paper, a novel XOR-XNOR circuit designed in modified pass transistor logic is presented. This gate has dual inputs (A, A~, B and B~) and generates dual outputs (XOR, XNOR). The circuit implementation is performed with six MOS transistors. In the current XOR-XNOR circuit implementation, errors caused by faults will be detected only by checking the complementarity principle between the XOR and XNOR functions. The proposed XOR-XNOR circuit and the correspondent layout are respectively given by Fig. 1 and Fig. 2.

Fig. 1. The proposed XOR-XNOR circuit implementation

The XOR-XNOR circuit is implemented in full-custom 32 nm technology [START_REF] Etienne | Microwind and Dsch version 3[END_REF]. SPICE simulations of the circuit extracted from the layout, including parasitic, are used to demonstrate that the circuit has an acceptable electrical behaviour. In Fig. 3, we can remark that XOR and XNOR the outputs obtained by simulating the fault-free XOR-XNOR circuit are complementary.

The XOR-XNOR Circuit Fault Analysis

In the following sub-sections, we analyse the behaviour of the proposed XOR-XNOR circuit in terms of fault-secure and self-testing properties with respect to the set of fault models including logical stuck-at faults, transistor stuck-on and transistor stuckopen faults.

The stuck-at fault model

The most common model used for logical faults is the single stuck-at fault. It assumes that a fault in a logic gate results in one of its inputs or the output is fixed at either a logic 0 (stuck-at-0) or at logic 1 (stuck-at-1) [START_REF] Lala | An introduction to logic circuit testing[END_REF]. In the following, we analyze the behaviour of the XOR-XNOR gate shown in Fig. 1 in terms of fault secure and selftesting properties with respect to the logical stuck-at faults. For inputs, we consider the logical stuck-at fault model. Table 1 gives the response of the gate for all inputs combinations. Multiple fault (detected)

0 1 0 0 1 1 Single fault (detected) 0 1 0 1 0 1 Valid input 0 1 1 0 1 0 Valid input 0 1 1 1 0 0 Single fault (detected ) 1 0 0 0 1 1 Single fault (detected) 1 0 0 1 1 0 Valid input 1 0 1 0 0 1 Valid input 1 0 1 1 0 0 Single fault (detected) 1 1 0 0 1 1 Multiple fault (detected) 1 1 0 1 1 1 Single fault (detected) 1 1 1 0 1 1 Single fault (detected) 1 1 1 1 1 1 Multiple fault (detected)
From Table 1, we can conclude that for primary logical stuck-at faults, all single and multiple faults on primary inputs will result in a non-valid code by producing no complementary outputs. In fact, each fault will be detected when there are non complementary (XOR, XNOR) outputs, because normally XOR and XNOR should be complementary data. Consequently, the proposed circuit is fault-secure and selftesting for single and multiple stuck-at faults.

In addition, by analyzing the table above we can remark that when a fault type stackat occurs, in the major case, it will affect the XOR output. In fact, when such faults occur we will obtain a faulty XOR and a fault-free XNOR output for all cases if the input A is equal to the low level. Otherwise, if the input A is equal to the high level we will obtain a faulty XOR output only when the logic product A~B is equal to the high level. Thereby, this remark can give us lots of ideas to consider when designing an error correction approach to ensure the fault tolerance property in the current XOR-XNOR circuit implementation. Next, we consider the stuck-on and stuck-open transistor fault model. We will examine all possible single transistor stuck-on and transistor stuck-open faults within the circuit of Fig. 1 in next two sub-sections.

The transistor stuck-on fault model

A transistor stuck-on fault may be modelled as a bridging fault from the source to the drain of a transistor [START_REF] Lala | An introduction to logic circuit testing[END_REF]. In order to analyse the circuit behaviour in the presence of stuck-on faults with realistic circuit defects, we simulate the considered XOR-XNOR circuit in the presence of faults. Faults are manually injected in the circuit layout of Fig. 2.

0 0 0 0 N1 1 0 1 1 0 1 0 0 N2 1 1 1 1 0 1 1 1 N3 1 1 0 0 0 0 1 1 N4 1 0 0 0 0 1 1 1 P1 1 0 1 1 0 0 1 1 P2 1 1 1 1
From Table 2, we can conclude that for any valid input code word, any injected single stuck-on fault within the gate produces an invalid code word (non complementary (XOR, XNOR) outputs), therefore the Fault-Secure property is verified for this set of faults. On the other hand, the self-testing property signify that for each single stuck-on fault within the gate there is at least one input vector occurring during the circuit normal operation that detects it. In fact, by analysing the simulation results summarized in Table 2, we can say that the self-testing property is also verified for this set of faults. Thus, the combination of the fault-secure and the self-testing properties makes the circuit Totally Self Checking for the stuck-on fault model.

The transistor stuck-open fault model

A stuck-open transistor involves the permanent opening of the connection between the source and the drain of a transistor [START_REF] Lala | An introduction to logic circuit testing[END_REF]. In order to analyse the circuit behaviour in the presence of stuck-open faults, faults are manually injected in the circuit layout In Fig. 4, we show that for the combination (0,0), (1,0) and (1,1) of the inputs (A,B) the circuit does not produce any error and both XOR and XNOR outputs are fault-free while for the combination (0,1) the circuit produce a fault-free XOR and a faulty XNOR. In fact, the Fault secure property require that for any valid input code word, any single transistor open fault within the gate produces an invalid code word on the output or does not produce an error on the output. Knowing that the considered fault will be detected because normally XOR and XNOR should be complementary data, we are sure that the fault secure property will not be lost. In the same way, we have simulated all possible single stuck-open faults within the XOR-XNOR circuit and simulation results show that the Fault-Secure property is verified for this set of faults.

Regarding the self-testing property, simulation results show that this property is verified for the NMOS transistors stuck-open. However, a stuck-open injected in any PMOS transistor (P1 or P2) don't produce any error in the circuit outputs and both XOR and XNOR outputs are fault-free. Thus, the fault will be undetectable because it has no effect on the circuit outputs. Theoretically, the self testing property is not ensured since a P1 or a P2 stuck-open transistor is undetectable but this is not catastrophic because firstly the fault-secure property is the most important one and secondly, we are sure that these two faults if they occur separately or even at the same time they have no effect on the outputs of the proposed circuit.

CONCLUSION

As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations which affects the circuit performance and introduces faults that can cause critical failures. Therefore, integrated circuits are more and more required to guarantee reliability for safetycritical applications in the presence of permanent and transit faults. Thus, to cope with the growing difficulty of off-line testing, the concurrent error detection property is indispensable when designing complex nanometer VLSI circuits ALUs. This paper presents a new design 6-transistors XOR-XNOR circuit that can be used to ensure the on-line detection of faults occurring in computer systems during the manufacturing process. The proposed circuit, designed using the 32 nm CMOS technology, is analysed in terms of fault-secure and self-testing properties with respect to the set of fault models including logical stuck-at faults, transistor stuck-on and transistor stuckopen faults.

Fig. 2 .

 2 Fig. 2. Layout of the XOR-XNOR circuit in full-custom 32 nm process technology SPICE simulation of the circuit without any fault is illustrated by Fig. 3.

Fig. 3 .

 3 Fig. 3. SPICE simulation of the XOR-XNOR circuit in 32nm technology without faults

of Fig. 2 .Fig. 4 .

 24 Fig. 4. SPICE simulation of the XOR-XNOR circuit with N1 stuck-open

Table 1 .

 1 The Gate Response for all inputs combinations.

Table 2 .

 2 The Gate Response for Transistor Stuck-on faults.

	Transistor Stuck-on	Input vectors detecting the A B fault	XOR	XNOR


Hui-Min Ko
email: gloriakohm@yahoo.com.tw

Soft Power: A Critical Factor for the Effectiveness and Development of a School

Keywords: soft power, organizational culture, learning school, marketing strategy

This research aims to explore the contents of a school's soft power, including culture, strategy, leadership, learning, marketing and innovation. Managing soft power not only is critical for a school's development, but also should be regarded as a indispensible asset of schools. The measures for a school to establish its soft power are: establishing core values, shaping a learning school, emphasizing on knowledge management, innovating, and introducing a more adaptive marketing strategy. A school could become more perspective and sustainable through soft power, and thus be able to deal with a fast-changing educational environment and meet practical requirements.

Introduction

Prof. Joseph S. Nye of Harvard University proposed his idea of "soft power" in 2004. Soft power, in accordance with Nye, is an ability to achieve goal through its own attraction rather than threats or seduction, and such an attraction comes from a country's culture, political values, and diplomatic policies. Since then, global research and application of soft power began; meanwhile, most countries also vigorously enhance their own soft power and regard it as an important strategic factor for domestic and international development. Currently, researches on and applications of soft power are so popular that soft power is discussed worldwide. Even most governments, enterprises and schools all have an idea to establish their own soft power in order to meet today's challenges. In the light of that schools play an important role in matters such as education and academic exchange, and that the establishment and management of soft power in the mean time are critical for a school's development, this research aims to explore the contents of soft power and establish some measures for soft power to improve a school's effectiveness and competitiveness, and thus the school's goal of sustainable management could be achieved.

The Contents of School Soft Power

The comprehensive power of a school includes hard power and soft power. Hard power is apparent and easy to evaluate, which includes buildings, facilities, teachers and funds. Soft power, on the other hand, is less obvious and more difficult to evaluate, which includes visions, spirits, culture, system, management, image and reputation. Internally, the soft power of a school represents a kind of cultural power, and, externally, an attraction and influence. It is the sum of a school's cultural power, strategic power, leadership power, learning power, innovation power, and marketing power (Chang, Ming-hui 2009).

Cultural Power

School culture is a school system composed by various codes, values, and meanings, which is shared and utilized by all the school members; it is also a legacy of ideology, including codes, systems, values, beliefs, rituals, and traditions, which could be divided into faculty culture, student culture, executive culture, community culture, material culture and spiritual culture (Zhang, Duo-yan, 2007). The power of these cultures is intangible but unlimited. They could not only enrich educational system, but also work in areas that system is unable to touch, and that is why they keep a school alive. The development of school culture could increase the performance of the school members, and help a school become more effective (Tsai, Chin-hsiong, 2000 ).

Strategic Power

Strategy is a form of integrating and coordinating resource allocation. In terms of an uncertain future, it is also a process analyzes the quality of internal and external resources, adapts the change of overall environment, and proposes the most adaptive way to achieve the goal of an organization (Tang, Chih-ming, 2009). A school's strategic power, therefore, is a set of plans that are determined in accordance with that school's goals, characteristics, and its own conditions, and aims to achieve the goal of sustainable operation. This set of plans defines a school's area of operation; it is also the blue print, procedure and measure to achieve goals of a school [START_REF] Hax | Redefining the Concept of Strategy and the Strategy Formation Process[END_REF]). An excellent strategic power of operation could outline the future development. A school head should have an overview of the environment and adopt proper operation strategy so as to survive and excellence, especially during a time when resources are limited and competition is fierce.

Leadership Power

Leadership is an art to influence people and stimulate them to complete missions and improve organizational behavior through providing motives, directions and goals, as well as utilizing personal charm, effective management and encouragement (Xie, Yulin, 2008). Leadership is to help a team to achieve its goals, maintain its integrity, and encourage it members (Wu, Ching-shan, 2006). The quality of leadership influences not only an organization's performances, atmosphere and future development, but also how much of its members' need could be met. A school leader's leadership style would have a profound influence on the performance and development of his or her school, and the satisfactory degree and performances of school members. Furthermore, the leadership style is the major power to develop the school's soft power.

Learning Power

The purpose of organizational learning is to endow an organization with learning power, making its members have a core value of being eager to learn, personal mastery and willing to change and innovate; it also aims to commence organizational transformation, and encourage members in an organization to examine themselves, learn from each other, ponder problems and take actions to solve them (Xie, Hui-juan, 2004). School learning activities are the extension of organization learning. A school's learning power could improve the quality of its members, develop a team learning environment, and promote the value of teamwork. This fact has a significant influence on a school's integration, innovation and organizational culture development. This fact also could encourage a school to learn and progress. Learning power, one of a schools' soft powers, emphasizes the fact that people could learn whenever and wherever, and that everyone is a learner. Such a learning system includes the learning activities of the student, the faculty and leader (Zhang, Minghui, 2005).

Marketing Power

School marketing is a concept that regards school as a market, and applies the idea of marketing to the daily life in a school. Through activities such as analysis, planning and execution, this concept aims to make faculty, community, parents, and general public understand a school's visions, teacher's quality and curriculum. A successful school marketing includes enhancing prestige, increasing competitiveness, solving recruiting difficulty, gaining more external resources, and effectively reaching an internal consensus (Xu, Xiao-jun, 2011). Measures for school marketing include internal marketing, external marketing and interactive marketing (Wu, Ching-shan, 2005).

Innovation Power

Innovation has the meanings of "make change" or "introduce new things" (Wu, Ching-shan, 2005). School innovation is "a process that adapts creative ideas and translates them into services, products, or means that deal with things in a school environment in order to develop a school's characteristics, improve its effectiveness, and thus to achieve the goal of education" (Wu, Ching-shan, 2003). The major functions of innovation are to display educational dynamics and creativities, enrich educational contents and activities, ensure schools' survival and development, and improve and excellence education quality. Innovation includes the change of ideas, technologies, services, operational procedures, activities and environments (Wu, Ching-shan, 2003).

3

Ways to Develop School Soft Power

Establishing Core Values

A school's core value comes from its history, culture and characteristics, as well as the spirit of the times. The core value is the stem and soul of school culture. It is also a prerequisite and foundation of a school's soft power. It reflects the common value and vision of the faculty and student, and represents a school's goals and visions. Based on school's characteristics and needs for development, the principles to establish a core value are: reviewing its own history; analyzing current situation; widely inquiring comments and suggestions from students, faculty, and people who concern the school; extracting merits from the school's tradition; forming a core value with profound and unique connotation; and making this value become a common belief and principle for each and every school member.

Shaping a Learning School

The idea of learning school develops from learning organization. The concept of learning organization is based on Peter M. Senge's "The Fifth Discipline", which is composed by system thinking, improving mental models, personal mastery, building shared vision and team learning. To thoroughly understand the fifth discipline is the foundation for the establishment of learning organization.

In addition to integrate the fifth discipline into school's learning strategy and major task, I feel that the essence of the idea of learning school is "learning". All the school head, faculty, student and parents of the community should be the main body of a learning school. The ways to form a learning school are: setting learning goals, transforming school leaders into learning ones, developing the student's self-directed learning ability, encouragement and rewarding.

High Quality School Leadership

A school leader should have characteristics that could lead, improve, and excel his or her school, and should also have a respectable personality to win respect from school members and make them follow his or her leadership wholeheartedly. In addition, one should notice that although there are various leadership theories, research results show that no one single type of leadership could be applied to everyone and everywhere. A leader should be able to adjust his or her leadership in accordance with circumstance. Therefore, a school head should choose an effective way to lead in accordance with the characteristics of faculty, student and environment so as to meet school's requirements, and to lead the school effectively and efficiently(Wu, Ching-shan, 2006).

Emphasizing Knowledge Management

In accordance with Zhang, Ji-cheng (2006), knowledge management is "a knowledge activity that promotes the accumulation, spread, sharing, creation, value-adding or efficiency of knowledge in an organization through development and effective utilization of knowledge by using of the tool of information management". The knowledge management in a school, therefore, is to establish an effective knowledge management system in order that the knowledge in school organization could be effectively created, circulated and added more values, and thus that more innovative professional knowledge of education could be produced constantly. In order to improve school knowledge management, there should be support and promotion from the leader, specially-assigned persons to be in charge of knowledge management matters, and a knowledge management strategy that encourages organization members to create and contribute special knowledge, and rewards anyone who do so. Furthermore, a knowledge base, data base and information circulation system should be established in order to transform any useful knowledge into information, systemize the knowledge, make the knowledge more accessible, and constantly update knowledge. Meanwhile, knowledge should also be permanently stored in computer software so that users could access to and utilize knowledge more efficiently and that the experience and knowledge of a school could be shared on information platform.

A More Adaptive School Marketing Strategy

A school should establish a service-and customer-centered culture. Under this culture, a school could more concern about customer while making decision, teaching and holding an activity. Under this culture, a school could improve its service quality to win the customer's heart and acquire more recognition and support. Furthermore, in prior to marketing itself, a school should have several discussions and brainstorming on matters such as upper guidance, school environment, internal and external resources, teacher's specialty, student's need, and expectation from parents, in order to reach a consensus between school members. Thus, school characteristics could be developed, reputation could be established, and recognition and support from the public could be gained.

Innovative Operation

Innovative operation demonstrates that fact that school operation concept is changing and school culture is reforming. The sustainable development of innovative operation is based on learning organization. School leaders should have an innovative mind set and shape a new organizational culture, atmosphere, environment and condition in order to establish a decision-making model composed by brainstorming, mutual discussion, and tolerance. They should be able to encourage school members to actively participate in school operation, work as a team, brainstorm, discuss mutually, and tolerant dissenting views so as to improve competitive edge of the school (Zhang, Ming-hui, 2009). The following measures could be used to promote innovative operation: creating a special team to promote innovative operation, encouraging cooperation and sharing among school members, learning from other schools, establishing a platform for innovation, providing adequate resources, and rewarding those who make significant contributions to innovative operation.

Conclusion

With the trend of globalization and commercialization of education, schools of all levels are facing a fierce competition and serious challenge. The establishment and development of soft power are critical for a school to survive and excel. Developing soft power is a lengthy and accumulative process that requires wisdom. The six components of school soft power proposed in this research include: cultural power, strategic power, leadership power, learning power, marketing power, and innovation power. The six soft powers that are interconnected and complemented each other could cohere, stabilize, influence, innovate, and develop a school organization. One who would like to bring soft power into full play should: establish profound and unique core values and translate these values into a common belief and code for all the members in the school; create a learning environment to promote group learning, encourage school members to work coherently and induce organization teamwork; develop high quality leadership to boost morale and improve organization efficiency; emphasize knowledge management in order to share and learn knowledge and experience; have the courage to change and innovate to fill the school with energy, So as to make sure a more forward looking, sustainable, adaptive, and responsive educational environment and requirements.


Yunji Chen

Tianshi Chen
email: chentianshi@ict.ac.cn

Qi Guo
email: guoqi@ict.ac.cn

Zhiwei Xu

Lei Zhang

An Elastic Architecture Adaptable to Millions of Application Scenarios

With the rapid development of computer industry, the number of applications has been growing rapidly. Furthermore, even one application may correspond to different application scenarios which impose different requirements on performance or power. This trend raises the following question: how to design processors that best suit millions of application scenarios? It is impractical to design a dedicated processor for each single application scenario. A better alternative is to design a general-purpose processor architecture that can generate different architecture instances on demand. This paper proposes a novel CPU architecture called Elastic Architecture (EA), which can be dynamically configured into different architecture instances to suit different application scenarios. By employing reconfigurable architecture components (instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on), the EA can achieve considerable elasticities on each application, which enables the EA to meet the performance or power requirements associated with each application scenario. We validate the effectiveness of the EA on a prototype implementation called Sim-EA. We demonstrate that Sim-EA exhibits large elasticities over 26 benchmarks of SPEC CPU2000, enabling Sim-EA to reduce the average energy-delay product (EDP) by 31.14% of a fixed baseline architecture.

Introduction

Since the appearance of the first electronic computer, millions of computer applications have emerged. Each single application (e.g., an internet game application running on hand-held terminals or desktop computers) may correspond to several application scenarios, which specify not only the concrete application but also the requirements imposed on the responses (response refers to some execution expenditure such as performance, power, performance-power tradeoff). To cope with the requirements of millions of application scenarios, more and more processor types are devised and used. For instance, the processor products of Intel increased from 5 types to near 30 types between 1999 and 2009 [10,11]. However, the problem of having a processor matching different application scenarios at the runtime and maintaining low costs in processor design and manufacture is not solved.

To address this problem, we propose a novel CPU architecture called the Elastic Architecture (EA) whose architecture components can be dynamically reconfigured to suit (adapt to) different application scenarios. The reconfigurable components in an EA may include instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on. Through dynamically reconfiguring these components, the processor can be adjusted on demand. The EA can potentially be configured to a considerable number of architecture instances1 , which is significantly larger than the number of architecture instances that can be activated by conventional architectures. For example, a modern processor with the Dynamic Voltage/Frequency Scaling (DVFS) technique, whose frequency can be dynamically configured to 1 GHz, 1.5 GHz, or 2 GHz, only has three different architecture instances. In contrast, this paper shows that the EA can be reconfigured into more 70 million architecture instances. Consequently, the EA can offer higher elasticity (defined as the ratio of the worst-case response to the best-case response) for each application scenario, compared with conventional designs. Taking again the processor with DVFS as an example, its performance elasticity is at most 2 (the ratio of execution times when running at 1 GHz and 2 GHz) for all applications. Such a small elasticity of the conventional architecture makes it hard to meet sophisticated requirements on responses (e.g., the power consumptions should be less than 100 Watt while the execution should be as fast as possible), while the EA is capable of tackling such requirements for various application scenarios.

We implement a prototype design of EA, named Sim-EA. Sim-EA can be reconfigured into more than 70,000,000 architecture instances. We evaluate the elasticity of performance-power tradeoff with EDP (Energy-Delay Product) of the EA, using 26 benchmarks of SPEC CPU2000. The arithmetic average EDP elasticity of Sim-EA is 5.41, and such a large elasticity indicates that selected reconfigurable components have crucial impacts on the performance-power tradeoff. To demonstrate the effectiveness of EA, we also compare the achieved EDPs of Sim-EA with those of a traditional fixed baseline architecture. Experimental results show that the EA can provide near-optimal EDPs for all benchmark applications, which results in 31.14% average EDP reduction.

2

Elastic Architecture

Concept

The EA is a flexible CPU architecture whose architecture components can be dynamically reconfigured so as to adapt to different application scenarios. The reconfigurable components may include instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on. For an application scenario with high-performance requirement, the EA can be configured into a highperformance CPU architecture instance. For an application scenario with low-power requirement, the EA can work as a low-power CPU. For an application scenario without a specific requirement, the EA can select an architecture instance with efficient performance-power tradeoff. The concrete configurable features of an EA may include:

1. The configurable instruction set mainly requires a configurable instruction decoder, which is sufficient to support instruction set variations. It enables an EA to support applications developed for different but closely-related computer families. 2. The configurable branch predictor enables the EA to adopt suitable branch prediction strategies (e.g., global history predictor, local history predictor, and so on) for applications with different types of branch behaviors. 3. The configurable data path provides flexible computational ability for the EA.

Through configuring data path, the number and functionality of computational units can be adjusted to meet specific performance and power requirements. 4. The configurable memory hierarchy is crucial to the EA, since the memory hierarchy may consume half of the area in a state-of-art CPU. There are many important memory hierarchy parameters, such as cache size, cache line size, cache way, cache replacement strategies, and so on. Each of these parameters has a nonnegligible impact on the performance and power. 5. The configurable concurrency includes not only TLP, but also ILP. Concretely, the concurrency configurations can include core number, issue width, instruction window size, and so on. 6. The configurable status & control include voltage adjustment, frequency adjustment, kernel-mode resource adjustment, and other miscellaneous CPU configurations.

Fig. 1. In an elastic architecture, the instruction fetch&decode model, execution engine, computational units, memory access unit, status, and interconnection can be dynamically configured.

Figure 1 illustrates the concept of EA, in which a central configuration module controls the other modules (instruction fetch & decode module, execution engine, computational units, memory access unit, status and core interconnection) through several configuration buses (instruction config bus, branch prediction config bus, concurrency config bus, data path config bus, memory hierarchy config bus, and status & control config bus).

It is worth noting that an EA does not require that all the above features of the CPU are reconfigurable. In other words, for a certain EA, it always consists of a part of fixed features and a part of reconfigurable features. Hence, determining which part to reconfigure and how to reconfigure should cautiously trade off between the design complexity and obtained benefits. An empirical guideline to determine the reconfigurable features is that such reconfigurable parts can provide large elasticities for applications, which can offer great adaptivity to a wide range of application scenarios.

Implementation of EA

To demonstrate the feasibility and merit of EA, we implement Sim-EA, a prototyping of EA on a simplescalar-like C simulator [START_REF] Austin | Simplescalar: An infrastructure for computer system modeling[END_REF]. As shown in Table 1, there are ten configurable parameters in the EA, which include the issue width (WIDTH), the number of floating-point functional unit (FUNIT), the number of integer functional unit (IUNIT), the size of L1 data cache (L1DC), the size of L1 instruction cache (L1IC), the size of L2 cache (L2UC), the size of gshare branch history table (GSHARE), the size of branch target buffer (BTB), the size of reorder buffer (ROB), and the size of load store queue (LSQ). We choose the above parameters to be configurable, not only because these parameters can be conveniently configured, but also because they are critical to control the overall performance/power of the processor, i.e., most of such parameters are closely related to the ILP, e.g., WIDTH, FUNIT, IUNIT, GSHARE, BTB and ROB etc. Among these parameters, WIDTH, FUNIT, IUNIT, ROQ and LSQ can be reconfigured in about ten cycles. Once the pipeline is flushed, they can take effect immediately. L1DC, L1IC, L2UC, GSHARE and BTB need relatively long time to be reconfigured, since the corresponding RAMs need to be flushed before reconfiguring these parameters. The detailed costs of reconfiguring such parameters are also shown in Table 1.

Experimental Methodology

To evaluate the EDP elasticity and the EDP reduction of Sim-EA, we employ the 26 benchmarks of SPEC CPU2000 as the representative applications for real life applications in different fields. As shown in Table 1, 10 crucial features of Sim-EA are variable, resulting in a design space consisting of more than 70 million architecture instances. As defined in Section 1, the EDP elasticity is the ratio of the worst-case EDP to the best-case EDP, which means that we should determine such two extreme architecture instances (i.e., achieving the best and worst EDPs) from the design space for each application. Furthermore, we also want to obtain the EDP reduction compared with a baseline architecture, which also requires us to obtain the optimal architectures from such a design space for each application via machine learning techniques (e.g., model tree algorithm [START_REF] Quinlan | Learning with continuous classes[END_REF]).

For fair comparison, we employ average Cycle-per-Instruction (CPI) to measure the performance of each architecture instance in the design space. In addition to the performance metric, we also estimate the average power consumption of each architecture instance with a widely-used metrics on performance-power tradeoff, i.e., Energy Delay Product (EDP) [START_REF] Gonzalez | Energy dissipation in general purpose microprocessors[END_REF], which equals to CP I 2 × power.

Elasticity

As the first step of experiments, for each of the 26 benchmark applications we employ predictive modeling techniques to explore the design space. For each application, we first randomly sample 500 architecture instances as the training set, that is, we simulate each application with 500 different architecture instances to obtain the corresponding performance/power responses. Then, such information is collected as the training data to build two predictive models i.e., model trees, for performance and power, respectively. After that, the performance/power with respect to a given architecture instance can be rapidly deduced by such models. Since we can easily know the performance/power responses with the help of predictive models, it is straightforward to find the two architecture instances with the best and the worst EDP for each application.

Once we can obtain the best and worst case EDP of Sim-EA, we can show the elasticity over 26 applications in SPEC CPU2000 in Fig. 2. We observe that the elasticity ranges from 3.31 (sixtrack) to 14.34 (art), and the arithmetic average elasticity is 5.41. Briefly, an application corresponding to larger elasticity implies that the applications are more sensitive to Sim-EA, which provides larger freedom for the EA to dynamically reconfiguring the architecture features on demand. For example, the elasticity of art is 14.34, which indicates that art is most sensitive (among all investigated 26 applications) to 10 reconfigurable parameters in Sim-EA. Moreover, the average elasticity as 5.41 indicates that the selected 10 reconfigurable parameters offer considerable freedom for Sim-EA to obtain an appropriate EDP for real-life scenarios. Similar situations can be observed when using performance or power as the alternative response for estimating the elasticity (i.e., performance elasticity or power elasticity).

EDP Reduction

Fig. 3. EDP reduction over the baseline architecture. The arithmetic average EDP reduction is 31.14%, ranging 6.26% (eon) to 82.84% (art) for 26 applications in SPEC CPU2000.

By integrating the optimal architecture instances (obtained for 26 benchmarks respectively) as the candidate running modes, Sim-EA can reconfigure its architecture to achieve promising EDP over different applications. The default architecture as a classical superscalar architecture in SimpleScalar Tool Suite, as shown in Table 2, is employed as the baseline. Fig. 3 shows the EDP reduction of Sim-EA to the baseline architecture, i.e., (1 -EDP Sim-EA /EDP baseline ) × 100%. It can be observed that, for all applications, Sim-EA can reduce the EDP of baseline architecture significantly, and the arithmetic average EDP reduction is 31.14%. The benefit of Sim-EA is highlighted by application art, which can reduce 82.84% EDP compared with the baseline architecture. However, for eon, it can only achieve 6.26% EDP reduction, an insignificant improvement on EDP. To be specific, the CPI and Power of Sim-EA on eon are 0.79 and 14.43 respectively, while the CPI and Power of the baseline are 0.69 and 19.14, respectively. In fact, the baseline architecture has already been at the Pareto Frontier of the performance-power tradeoff function [START_REF] Mariani | An industrial design space exploration framework for supporting runtime resource management on multi-core systems[END_REF], and it is a nearoptimal architecture instance with respect to EDP. In this case, the EDA reduction of the Sim-EA is not significant.

Conclusion

With the advance of computer industry, the programmers and end users have put more and more requirements on processors. For different application scenarios, they hope that the processors can adapt to specific requirements on performance/power. Such requirements cannot be satisfied with a processor diversity approach, and may lead to excessive processor market segmentation, which increases the overall cost of processor design and manufacture. A promising solution is to make the processor elastic, which has many configurable features (e.g., instruction set, data path, memory hierarchy, concurrency, and so on). In this paper, we propose a Elastic Architecture and a prototype design of EA, which is named Sim-EA. Experimental results show that with respect to the SPEC CPU2000 benchmark suite, the elasticity of Sim-EA ranges from 3.31 to 14.34, with 5.41 in arithmetic average, provides great flexibility to fulfill the different performance/power requirements in different scenarios. Moreover, Sim-EA can significantly reduce the energy-delay product by 31.14% in average compared with a baseline fixed architecture.

In the future development of EAs, it is possible that more architecture features are designed to be reconfigurable, resulting in advanced EAs. An advanced EA is said to be downward compatible with a former EA if the advanced one can reconfigure all architecture features that can be reconfigured by the former. Driven by the rapid development of the microprocessor industry, a new concept computer tribe may emerge, which is the set of consecutively-developed processors adopting downward compatible EAs.

Fig. 2 .

 2 Fig. 2. EDP elasticities of the Sim-EA over different applications.

Table 1 .

 1 Reconfigurable parameters in processor with EA.

	Abbr.	Parameter	Value	Reconfiguration Costs
	WIDTH	Fetch Width	2,4,6,8	~10 cycle (flush pipeline)
	FUNIT	FPALU/FPMULT Units	2,4,6,8	~10 cycle (flush pipeline)
	IUINT	IALU/IMULT Units	2,4,6,8	~10 cycle (flush pipeline)
	L1IC	L1-ICache	8-256KB: step 2*	~2000 cycle (flush L1D cache)
	L1DC	L1-DCache	8-256KB: step 2*	~2000 cycle (flush L1D cache)
	L2UC	L2-UCache	256-4096KB: step 2*	~10000 cycle (flush L2 cache)
	ROB	ROB size	16-256: step 16+	~10 cycle (flush pipeline
	LSQ	LSQ size	8-128: step 8+	~10 cycle (flush pipeline)
	GSHARE	GShare size	1-32K: step 2*	~200 cycle (flush GShare table)
	BTB	BTB size	512-4096: step 2*	~100 cycle (flush BTB)
	Total	10 parameters	70,778,880 options

Table 2 .

 2 Baseline architecture

	Parameter WIDTH FUNIT IUNIT	L1IC	L1DC	L2UC	ROB LSQ GSHARE BTB
	Value	4	4	4	16KB 16KB 128KB	16	8	2048	2048

An architecture instance is a runtime configuration of an architecture, in which all architecture components are fixed, and an application can be executed with fixed performance and power (if random disturbance is ignored).

Acknowledgement

This work is partially supported by the National Natural Science Foundation of China (under Grants 61003064, 61100163, 61173006, and 60921002), the National S&T Major Project of China (under Grant 2010ZX01036-001-002), the National 863 Program of China (under Grant 2012AA012202), and the Strategic Priority Research Program of the Chinese Academy of Sciences (under Grant XDA06010401-02).


Jinzhi Lin
email: linjinzhi@mail.nankai.edu.cn

Ying Wu
email: wuying@nankai.edu.cn

Gongyi Wu #

Jingdong Xu

NCCPIS: A Co-simulation Tool for Networked Control & Cyber-Physical System Evaluation

Keywords: Co-simulation, Ptolemy II, NS-2, Evaluation tool, NCS, CPS

As the researches on Networked Control & Cyber-Physical System (NCCPS) are growing, the requirement of reliable evaluation tools for these systems is urgent. There are several simulators, such as TureTime, Ptolemy II and so on, can be used, but they usually focus on modeling of the control dynamics, and are too simple and abstracted on the simulation of network communication. In this work, a co-simulation tool, NCCPIS is presented, which integrates the dynamic control system simulator, Ptolemy II and the network simulator, NS-2. We demonstrate the validation of the tool by presenting a case study of platoon longitudinal control in AHS (Automatic Highway System).

Introduction

In recent years, more and more researches focus on Cyber-Physical Systems (CPS), which integrate computation with the physical process. Actually, a CPS is often monitored and controlled by a Networked Control System (NCS). In this paper, we call them together as Networked Control & Cyber-Physical System (NCCPS). Basically, a NCCPS is composed of three components: physical process, computation and network [START_REF] Lee | CPS Foundations[END_REF]. The researches of NCCPS include investigating problems at the intersection of control systems, networking, and computer science [START_REF] Baillieul | Control and Communication Challenges in Networked Realtime Systems[END_REF], exploring compositional verification and testing methods [START_REF] Rajkumar | Cyber-physical Systems: the Next Computing Revolution[END_REF], and so on. Design and evaluation of NCCPS can not be accurately conducted without considering the effect of networks, it is important to develop a verification tool that not only has the ability of simulating the dynamics of the system's plant and controller, but also can simulate the realistic network environment for communication. To build a brand new tool from scratch satisfying the requirement is very difficult and unnecessary. There are several powerful model-based tools being used to simulate control systems in the academia, such as Ptolemy II [START_REF]Ptolemy II[END_REF], Simulink [START_REF]Simulink[END_REF], ViSim [19], and so on. On the other hand, there are a few network simulators can exactly emulate detailed network communication, such as NS-2 [12], OpNET [START_REF] Chang | Network Simulations with Opnet[END_REF], OMNet++ [START_REF]Omnet++: Discrete event simulation system[END_REF], and so on. The feasibility of integrating a control system simulator and a network simulator to evaluate NCCPS is foreseeable.

By considering the flexibility, reliability and technical supporting, we choose to integrate both open source simulators, Ptolemy II and NS-2, to build our co-simulation tool called NCCPIS. The challenges are significant, including designing the framework of NCCPIS and coordinating the synchronization of event time and data exchange in both sides of the simulators.

This paper is organized as follows. In section 2, we introduce the related work. In section 3, we present the implementation of NCCPIS. Time and data synchronization are discussed in section 4. A case study is given in section 5. Finally, this paper is concluded in section 6.

Related Work

As a most popular tool for validating NCS, TrueTime [START_REF] Henriksson | Truetime: Real-time Control System Simulation with Matlab/Simulink[END_REF] extends Matlab/Simulink with platform related modeling concepts (i.e., network, clock and schedulers) and supports simulation of networked and embedded control systems with implementation effects [START_REF] Cervin | Simulation of Networked Control Systems using Truetime[END_REF]. However, in TureTime, the modeling of network dynamics are highly abstracted, thus it's not appropriate to evaluate the systems that require detailed low layer network communication.

For different considerations, combining different control system simulators with network simulators, some similar ideas of seeking co-simulating methods exist in a few articles. In [START_REF] Riley | Networked Control System Wind Tunnel (NCSWT)-An Evaluation Tool for Networked Multi-agent Systems[END_REF], an evaluation tool called NCSWT was developed, which integrated Matlab/Simulink and NS-2 using the HLA standard for coordinating data communication and time synchronization. In [START_REF] Al-Hammouri | Co-simulation Tools for Networked Control Systems[END_REF], two approaches of extending NS-2 and one of integrating Modelica and NS-2 have been proposed. In [START_REF] Hasan1 | Co-simulation of Wireless Networked Control Systems over Mobile Ad Hoc Network using Simulink and Opnet[END_REF], for WNCS (Wireless NCS) over MANET (Mobile ad-hoc Network), the SIMULINK-OPNET co-simulation was investigated.

NCCPIS Implementation

Ptolemy II & NS-2

In Ptolemy II, actors are the basic computation units that can execute concurrently and communicate through messages sent via interconnected ports [START_REF]Ptolemy II[END_REF]. There may be a special actor in a model called Director, which manages the execution of this model. Actors have the key flow of control methods [START_REF] Brooks | Heterogeneous Concurrent Modeling and Design in Java (Volume 2: Ptolemy II Software Architecture)[END_REF][START_REF] Lee | Leveraging Synchronous Language Principles for Heterogeneous Modeling and Design of Embedded Systems[END_REF]:

The CT (continuous-time) domain in Ptolemy II aims to help the design and simulation of systems that can be modeled using ordinary differential equations (ODEs). ContinuousDirector is the main Director of CT domain. It contains an ODESolver who's responsible to determine the integration step sizes according to ODEs or time points of interest so as to achieve an accurate simulation. Meanwhile, Ptolemy II implements a ContinuousStepSizeController interface to support accurate time advancement. Any actors implemented the interface can influence the passage of simulation time. The interface has following methods [START_REF] Lee | Leveraging Synchronous Language Principles for Heterogeneous Modeling and Design of Embedded Systems[END_REF]:

 isStepSizeAccurate: to see if the current step is accurate.  suggestedStepSize: suggests the next step size.  refinedStepSize: if isStepSizeAccurate returns false, this method will be called, returns the step size this actor wants to refine currently.

Moreover, there is a ContinuousStatefullComponent interface which has a roll-BackToCommittedState method. It's for the actors who have tentative state to roll back if the current step size is not accurate. Figure 1 shows the process of the fire method of ContinuousDirector.

Framework & Integration

Figure 2 shows the framework of NCCPIS. Considering supporting separated hosts simulating, we integrate the two simulators through sockets, and design a few commands for synchronization shown in table 1. On the Ptolemy II side, NS2Node actors are considered as the shadows of Nodes in NS-2, they directly participate in the simulation of Dynamic Control System. Once they have state (e.g., position and velocity) updated or packets to send, they ask NS2Coordinator to send the corresponding commands to NS-2 through its socket thread, and waiting for the response commands from NS-2 so as to continue the simulation.

Time & Data Synchronization

Synchronization is critical for co-simulation tools. In NCCPIS, the time when nodes send and receive a packet should be same in both simulations. For wireless network simulation, the position and velocity of nodes are essential for packet transmissions, thus, we need to synchronize the position and velocity of nodes in both simulations.

Position and velocity synchronization is simple. The position and velocity of NS2Node can only change in the "Do Solver Iteration" process shown in figure 1, as long as NS2Node detects the change of its state, it delegates NS2Coordinator to send a "setdest" command to NS-2. Respectively, when NS-2 receives that command, as shown in figrue 2, ptIIEngine inserts an AtEvent like "ns at t 'nn setdest x y v'" into scheduler, and records it in TSO to prepare for following up "rollBackTo" command. TSO records all events generated by the synchronization commands from Ptolemy II, if ptIIEngine receives a "rollBackTo" command, it could remove these events from the scheduler, however, if receive a "runTo" command, just clear them from TSO.

Synchronization of sending packets is similar to that of position and velocity. But, to synchronize the time of receiving packets is a little hard. As shown in figure 3, the simulation time of Ptolemy II is always ahead of NS-2, while the time NS-2 receiving packets is unpredictable, thus we can't generate a future receiving packets event for Ptolemy II in advance. As a result, the time NS-2 receiving packets is always before or equal to (if the receiving time is equal to the time Ptolemy II invokes postfire) the current simulation time in Ptolemy II. Obviously, we should ensure that the time NS-2 receiving packets are exactly the time Ptolemy II invokes postfire. To accomplish this, as shown in figure 4, we invoke isStepSizeAccurate to ask NS-2 to check that if there are packet receiving events in the scheduler before the current simulation time (the time Ptolemy II is going to ask NS-2 to "runTo" if all actors' isStepSizeAccurate return true). If existing these events, return false and return the earliest time of all events when the upcoming command "refinedStepSize" is invoked, else return true. Actually, to NCCPIS, only application packets matter. While invoking isStepSize-Accurate, we can check the event queue of the scheduler in NS-2 to see if there are packet receiving events going to happen in the Application Layer. But there is a dependency problem needs to be considered, that after some related packet events in router, data link layer, physical layer, etc., being scheduled, packet receiving events in Application Layer may appear. By analyzing the simulation mechanism of NS-2, we found that before a packet received in application layer, it is either in the event queue of the scheduler for the upcoming scheduling, or blocked in a queue, a MAC layer, a physical layer and a channel for waiting to be put in the event queue. This means that we should check the event queue and the NS-2 components which may block the application packets for isStepSizeAccurate invoking. Specifically, figure 4 depicts the isStepSizeAccurate process flow for simulating 802.11 ad-hoc networks. There is a TolerableError in NCCPIS due to the timeResolution in Ptolemy II meaning the time precision. The default value of timeResolution is 1e-10. As we can see, the time synchronization between Ptolemy II and NS-2 is within this time precision.

CASE STUDY

NCCPIS in this work is intended to provide a co-simulation of dynamic control system and network communication. In this section, we present a simulation scenario to validate NCCPIS as well as show how the realistic network performs such as timevarying delays and packet losses and how they affect the overall system.

Experiment Setup

We consider a platoon of 16 vehicles running on a highway with 15 vehicles followed a lead vehicle. The lead vehicle transmits its position, velocity and acceleration measured by sensors periodically through an 802.11 wireless ad-hoc network to all the vehicles within the platoon. All vehicles are assumed to be initially traveling at the steady-state velocity of v 0 = 17.9m/s. Beginning at time t = 0s, the lead vehicle's velocity increases from its steady-state value of 17.9m/s until it reaches its final value of 25.9m/s: the maximum jerk and the peak acceleration values corresponding to this velocity time profiles were 2m/s 3 and 2m/s 2 , respectively. We adopt the control law in [START_REF] Sheikholeslam | Longitudinal Control of a Platoon of Vehicles[END_REF] The Recorder records all the packets NS2MobileNode received, but outputs the currently received packet of a specific node which here is set to the lead vehicle until a new packet arrives, in fact, the Recorder is a ZeroHolder.

In NS-2, we set the network parameters consistent with IEEE 802.11p as shown in table 2, and employ the public available highway patterns and ns traffic trace generation tools presented in [START_REF] Chevillat | Dynamic Data Rate and Transmit Power Adjustment in IEEE 802.11 Wireless LANs[END_REF] to obtain a realistic scenario with a dynamic network topology. We consider a 6km long highway composed of 6 lanes (3 in each direction) with high traffic density, where in total 523 vehicles pass along the road in both directions with an average speed of 120km/h (33.3m/s). For this scenario, we add a 7-th lane for the platoon with the lead vehicle's initial position at 2.5km of the highway. All the normal vehicles in the highway periodically broadcast packets, thus they interfere the communication of the platoon. We conduct three experiments with the normal vehicles broadcasting at different rates and packet sizes: (a) 500 bytes per packet, 5 packets per second; (b) 500 bytes per packet, 10 packets per second; (c) 1500 bytes per packet, 10 packets per second. The lead vehicle of the platoon broadcasts its state every 100ms by setting the interval of the PeriodicSampler shown in figure 5 to 0.1.

Evaluation

Figure 6, 7 respectively shows the delays and loss of packets that the platoon vehicles received from the lead vehicle. We can see that broadcasting of non-platoon vehicles have obvious effect on communication of platoon.Figure 8 shows the co-simulation results. Compared to [START_REF] Sheikholeslam | Longitudinal Control of a Platoon of Vehicles[END_REF], we can infer that our co-simulation results are valid.

Compared to [START_REF] Sheikholeslam | Longitudinal Control of a Platoon of Vehicles with no Communication of Lead Vehicle Information: A System Level Study[END_REF], our platoon performances are better, because in our law, we used the information of the lead vehicle by adding the wireless network communication to the simulation. In addition, due to the delay and loss of packets, the performances of experiment a, b and c shown in figure 8 are worse and worse. That also proves the validation of our co-simulation. In this case study, Ptolemy II and NS-2 are both running on a RedHat virtual machine with 1GB memory on an XP host with 2GB memory and a 2.80GHz dual-core CPU. The overall 18 seconds co-simulation has taken five minutes. The communications of the 523 MobileNodes for the normal vehicles in NS-2 and the frequent "rollback" in Ptolemy II cost most all of the time.

Conclusion

In this work we present NCCPIS, a co-simulation tool integrating a control system simulator, Ptolemy II and a network simulator, NS-2. By studying the architectures of them, we have designed the framework of NCCPIS, developed data exchange and time synchronization mechanism. At the same time, we demonstrate the validation of the tool by presenting case studies of platoon longitudinal control in AHS. As Ptolemy II is a tool orienting multi-domains and aiming to simulate hybrid systems, we will import the co-simulation of multi-domains to NCCPIS and validate it.

Fig. 1 .

 1 Fig. 1. The process of fire method of ContinuousDirector

Fig. 3 .Fig. 4 .

 34 Fig. 3. The synchronization between Ptolemy II and NS-2 Start

  and choose the same values for the coefficients: c a1 = 15, c v1 = 74, c p1 = 120, k a1 = -3.03, k v1 = -0.05; c a = 5, c v = 49, c p = 120, k a = 10, k v = 25, and the coefficients of vehicle dynamics are, for i = 1,2,…, K di = 0.3, τ i = 0.2, d mi = 5,m i = 1464.Figure 5 depicts the detail inside the Wireless component configured in Ptolemy II for each vehicle. The NS2MobileNode is the entity of NS2Node as discussed above.

Fig. 5 .

 5 Fig. 5. The detail of the Wireless component configured in Ptolemy II for each vehicle

Fig. 6 .Fig. 7 .Fig. 8 .

 678 Fig. 6. The delays of packets (Experiment a, b, c, respectively)

Table 1 .

 1 Synchronization Commands

				ContinuousDirector
			Dynamic Control System Simulation	NS2Node NS2Node	NS2Coordinator
				...
				NS2Node	socket	Ptolemy II
			Network Communication Simulation	Node (MobileNode) Node (MobileNode) ... Node (MobileNode)	ptIIEngine & socket TSO (Tentatively Schedule Operator)	NS-2
				Scheduler
			Fig. 2. The framework of NCCPIS
	Comm	Sender	Response comm Description
	setdest	Ptolemy II setdest_ok	Coordinate MobileNode to update position
	broadcast Ptolemy II broadcast_ok	Coordinate MobileNode to broadcast packet
	send_pkt Ptolemy II send_pkt_ok	Coordinate MobileNode to send packet
	iSSA	Ptolemy II iSSA [true/false] Consult NS-2 if the step size is accurate
	rSS	Ptolemy II rSS [t]		Consult NS-2 the step size
	sSS	Ptolemy II sSS [t]		Consult NS-2 the next step size
	rB [t]	Ptolemy II rB_ok		Ask NS-2 to roll back to time t
	runTo [t] Ptolemy II runTo_ok	Ask NS-2 to run to time t
	recvdata	NS-2	recvdata_ok	Coordinate NS2Node to generate packet
	Note: iSSA = isStepSizeAccurate, rSS = refinedStepSize, sSS = suggestedStepSize, rB = rollBackTo

The actor NS2Coordinator implements ContinuousStepSizeController and ContinuousStatefull-Component interfaces intrduced previously, every time before postfire, Continuous-Director invokes isStep-SizeAccurate, then NS2Coordinator turns to consult NS-2 whether the current step size is accurate. On the NS-2 side, similarly, we develop the class ptIIEngine as the proxy to coordinate synchronization with Ptolemy II.

Table 2 .

 2 Simulation configuration in NS-2

	Category	Parameter	Value
	PHY	Frequency	5.9 GHz
		Power Monitor Threshold	-102 dBm
		Transmission Power	1 mW
		SINR Preamble Capture	4 dB
		SINR Data Capture	10 dB
	MAC	Slot Time	13 us
		SIFS Time	32 us
		Header Duration	40us
		Symbol Duration	8us (3 Mbps)
		Modulation Scheme	BPSK

Acknowledgments. This work was supported by the Research Fund for the Doctoral Program of Higher Education of China (No. 20110031110026), and the National Natural Science Foundation of China (No. 61103214).


Chiou-Fen Lin

Meei-Ling Shyu

Meei-Shiow Lu

Chung-I Huang

Examining the effectiveness of A Distant Learning Education Program: Use of Patient Safety and Reporting Law and Ethics As Example

Keywords: Distant Learning Education Program, Patient Safety, Reporting, Law, Ethics

This study was to test a distant learning education program aiming to improve nurses' understanding of law and ethics regarding to patient safety and reporting in Taiwan. With stratified randomized sampling of 3 medical centers, 12 regional and 50 local hospitals, 2,323 questionnaires were distributed to nurses working at the sampled hospitals. Questionnaire return rate was 99.5% with 2,312 valid returned. Based on this survey, the researchers designed a distant learning education course targeting the knowledge deficits. The results indicated that 57.7% of the sampled nurses passed the patient safety and reporting law and ethic test before the education program was instituted by the National Union of Nurses Associations. 38,603 nurses completed the distant learning course and 94.8% passed the test. This study demonstrated that the distant learning education program is effective, and should be considered as a way to improve access to and reduce cost of continuing education.

Introduction

According to the Taiwanese Nursing Professional law no. 8, nurses should apply their practice license at the governing institute where the nurses practice. After register and receiving the practice license, the nurses can start nursing practice. The practicing nurses should receive certain hours of continuing education within 6 years in order to review the practice license (National Regulation Database, 2011). Therefore, all nursing associations have been providing all kinds of seminars and conferences to promote the accessibility of continuing nursing education. However, due to the time limitation and location issues, many nurses may not be able to participate in continuing education courses. Thus there is a need to explore the feasibility and effectiveness of distant learning education programs.

Study Purposes

The purposes of this study were: 1. To assess nurses' knowledge of patient safety and reporting law and ethics. 2. To design the content of the distant learning education course on patient safety and reporting law and ethics. 3. To examine the effectiveness of the distant learning education course on patient safety and reporting law and ethics.

Study Methods

Multiple methods were used in this study, which included systematic review of literature, cross-sectional survey, distant learning education and outcome evaluation. This study comprised of three stages in implementation. The first stage was to appraise current literature. According to the study purposes, we searched and reviewed domestic and international nursing literature related to patient safety and reporting law and ethics. Based on the review findings, we constructed a draft of assessment tool, Knowledge Assessment of Patient Safety and Reporting Law and Ethics, to assess nurses' understanding of the topic. Expert validity and internal consistency were assessed. A pilot study was conducted with randomized sampling. Data were collected and analyzed to identify the final items of the assessment tool.

The second stage was to conduct the knowledge assessment using the finalized tool.

Based on the assessment results, we designed a distant learning education course specifically targeting the knowledge deficit. The third stage was to publish the distant learning education course content in the Newsletter of The National Unions of Nurses' Association, R.O.C. A post-test assessment was included. After studying the distant learning education course regarding to patient safety and reporting law and ethics, nurses completed the post-test assessment and faxed it back to The National Unions of Nurses' Association. Continuing education credits were granted to those passed the course evaluation.

Study Population and Sampling Method

The study population for assessing the knowledge of patient safety and reporting law and ethics was the domestic nurses working at the local or regional hospitals or medical centers (including those qualified based on the New Hospital Accreditation) for at least 6 months. Stratified random sampling method was used to select the hospitals from three different levels: medical centers (including those judged to be outstanding hospital based on the accreditation), regional hospitals (including those judged to be excellent hospital based on the accreditation), and local hospitals (including those judged to be qualified hospital based on the accreditation), according to the 2007-2009 hospital and teaching hospital accreditation results published by the Department of Health. Sample hospitals were selected from each of the three clusters to ensure the appropriate sample size in each cluster. Sample size was calculated based on the rule of having 10-20 samples in each concept or variable. Considering the size of the nursing population, we applied the large population sampling principle [START_REF] Chiou | Quantitative research method (1): study design and data processing[END_REF] and estimated 1% attrition rate. This study planned to select about 11% of the nurses in Taiwan. We randomly selected three medical centers from 19 qualified medical centers, 12 regional hospitals from 92 regional hospitals, and 50 local hospitals from 432 local hospitals. The final sample included the day shift nurses working at one of these 65 hospitals for at least 6 months.

Study Materials

The demographic information was collected from the nurse participants, which included hospital, unit, professional level, years of working experience, age, gender, and educational level. The assessment tool, Knowledge Assessment of law and Ethics Regarding to Patient Safety and Reporting, included contents and performance of nurses' execution of patient safety reporting, knowledge of relevant law and ethics such as the purposes, benefits, types, ethics, and laws of reporting adverse events. A score was assigned to each item: the right answer received score 1 and the wrong answer score 0. The total scores indicate the nurse's assessment score; the higher score the better knowledge on the patient safety and reporting laws and ethics. The final tool comprised of 16 multiple choice questions. To pass the assessment, nurses should correctly answer at least 12 questions (70%). 1. Validity Test: Content validity of the assessment tool was evaluated by 10 experts of the patient safety and reporting system, from industry, regulation, and academics. The importance and suitability of each item were assessed. The content validity indexes were 0.8 and above. We also invited 5 nurses to assess the readability and wording. Revision was done to ensure the readability of the tool.

2. Reliability Test: Reliability was evaluated using the completed knowledge assessment tool from 92 nurses of a northern regional hospital. The results indicated that the internal consistency of the items, using Cronbach's α to express, ranged from 0.65 to 0.74.

3. Discriminant Validity Test: The tool, Knowledge Assessment of Patient Safety and Reporting Law and Ethics, was further assessed for discriminate power. We grouped the nurses with the highest 27% total scores into the high performance group, and the nurses with the lowest 27% total scores in the low performance group. The different score in each item between the high performance and low performance groups formed the discriminant index. The original tool contained 20 items. We removed 4 items with discriminant index of 0.2 or below. The final tool contains a total of 16 items.

Data Analysis and Statistics

Knowledge Assessment of Patient Safety and Reporting Law and Ethics. Based on the stratified randomization, we obtained the consents from the sample hospitals for conducting research. During unit/ward morning meeting, a research staff explained the study purposes and invited the day shift nurses to participate in this study. After consenting, the nurse participants were given the knowledge assessment tool with name removed. A written instruction was given to the participating nurses for how to complete the study. The knowledge assessment tool was returned and examined for completeness upon return. A total of 2323 questionnaires were sent out with 2312 valid return. The valid return rate was 99.5%. Data were entered into a computer software database and then analyzed using the Statistic Package for Social Study (SPSS, version 15.0). The nurse participants' demographic information were analyzed with descriptive statistics, including frequency, percentage, mean, and standard deviation. T-test, one way Analysis of variance (ANOVA) with Scheffe's posteriori comparison, and Pearson's correlation were used as inference statistics. Evaluation of the Distant Learning Education Program. For each of the 16 items, it would be scored as 1 if the nurse's answer was correct and 0 if the answer was wrong. The total possible score was 16 if the nurse answered all items correctly. The pass score was set as 12 (70%).

Study Results

Prior to conducting the distant learning education, there were only 57.7% of the participating nurses passed the knowledge assessment of patient safety and reporting law and ethics. The most frequent score was 12 (18.4%), and the next frequent score was 11 and 13 (16.3%). The mean score was 11.67 with standard deviation of 2.44. There were 364 nurses, 15.8% of the nurse participants, received score of 10 or below.

Nurses' knowledge on patient safety and reporting law and ethics was lower than their knowledge on patient safety. Among the 16 multiple choice questions, the majority of the nurses (62.8%) answered wrong on the question, the reporting type for delaying medication administration due to computer out of order. The next common mistaken question was what kind of ethical conduct would be if the nurse helps the patient and his/her family to communicate with other medical professionals about the safety issues they concerned. About 57.1% of the participating nurses answered the question wrong. The results demonstrated that among the nurses' knowledge of patient safety and reporting law and ethics, there was particular needs to improve nurses' understandings of adverse event reporting type and ethical principles and rules. ㎝ The distant learning education course was distributed through the Newsletters of the National Union of Nurses' Association. There were 38603 nurses read the distant learning education content and 94.8% of the participating nurses passed the knowledge assessment.

Conclusions and Recommendations

This study applied systematic review of literature, collected and compiled the relevant references on patient safety and reporting law and ethics. A cross-sectional survey was used to broadly and swiftly assess the nurses' knowledge related to patient safety and reporting law and ethics. Data analysis indicated that only 57.7% of the nurse participants passed the assessment. There was a need to improve nurse' knowledge on this topic. After implementing the distant learning education, the nurses increased their knowledge on patient safety and reporting law and ethics. There were 38603 nurses participated in the distant learning program and 94.8% passed the knowledge assessment. The nurse participants received immediate feedback from the distant learning education course and obtained the continuing education credits as a second gain. This study demonstrated the effectiveness of a distant learning education program on increasing nurses' knowledge of patient safety and reporting law and ethics. We recommended applying distant learning education programs in the future for national education topics, in order to improve the accessibility of continuing education and reduce the cost of delivering of the education.

Acknowledgement

This study was supported by the research fund from the Department of Health (DOH099-TD-M -113-099003). We thank the research team members for their active participation and the experts for taking time to attend the meetings. We also would like to express our gratitude to those nurses from the three medical centers, 12 regional hospitals, and 50 local hospitals and who completed the study assessment tool.