Xin Ming
email: mingxin@uestc.edu.cn

Ze-Kun Zhou
email: zkzhou@uestc.edu.cn

Bo Zhang
email: zhangbo@uestc.edu.cn

A Low-Power Ultra-Fast Capacitor-Less LDO With Advanced Dynamic Push-Pull Techniques

Keywords: adaptive biasing, dynamic push-pull technique, capacitive coupling, slew-rate enhancement, high bandwidth, low-dropout regulator, system-onchips

A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this chapter. It makes use of an adaptive biasing common-gate amplifier to extend loop bandwidth of the LDO at heavy loads greatly. Also, the dynamic push-pull (DPP) slew-rate enhancement (SRE) circuit based on capacitive coupling detects rapid voltage spikes at the output to provide an extra current to charge and discharge the large gate capacitance of the power transistor momentarily. The proposed circuit has been implemented in a 0.35µm standard CMOS process. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 10μA quiescent current at no-load condition and is able to recover within 0.8µs even under the maximum load current change.

Introduction

Various multimedia and portable devices lead the trend of system-on-chip (SoC) integration. The power management is an essential part in the battery-powered system. To get a fast transient response and noise-less output supply voltage, the onchip capacitor-less LDO is demanded to be integrated with the SoC systems. However, it takes the restriction of minimum load current and slow transient response into design consideration due to the low supply voltage [START_REF] Rincon-Mora | A low-voltage, low quiescent current, low drop-out regulator[END_REF]- [START_REF] Man | Development of singletransistor-control LDO based on flipped voltage follower for SoC[END_REF].

Normally, transient response is a critical dynamic specification in LDO design, which is dominated by the loop-gain bandwidth and slew rate at the gate of the power transistor. Both the amplitude of voltage spike and recovery time of regulated output voltage will affect its overall accuracy. Unfortunately, the generic approaches to optimize the transient response using external capacitors and large bias current are no longer useful in the power-saving SoC application. Several techniques are thus proposed to improve the transient responses without increasing quiescent current so much [START_REF] Lin | An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement[END_REF]- [START_REF] Hazucha | Area-efficient linear regulator with ultra-fast load regulation[END_REF]. An active-frequency compensation circuit is introduced in [START_REF] Lin | An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement[END_REF] to greatly boost the effective current multiplication factor by at least one order of magnitude and extend the loop bandwidth drastically. A low-power fast-transient low-dropout regulator with multiple small-gain stages is employed in [START_REF] Ho | A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages[END_REF] to provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency, which leads to larger loop gain and bandwidth. An adaptive reference control technique is proposed in [START_REF] Lin | Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push-Pull Techniques for Enhancing Transient Performance[END_REF] by dynamically and smoothly adjusting the reference voltage so as to increase the slew rate of error amplifier (EA). A low-power analog driver based on a single-stage amplifier with an embedded current-detection SRE circuit is presented in [START_REF] Lee | Design of low-power analog drivers based on slewrate enhancement circuits for CMOS low-dropout regulators[END_REF]. A low-dropout linear regulator topology with replicabiased common-source unity-gain buffer is used in [START_REF] Hazucha | Area-efficient linear regulator with ultra-fast load regulation[END_REF] to overcome the bandwidth limitation of the feedback loop.

Recently, non-static biasing has been proved to be an effective way to improve transient responses in low-power design, which enables bias current to be dramatically increased for bandwidth extension and slew-rate improvement. Adaptive biasing (AB), that increases the bias current according to the magnitude of the output current, is employed in [START_REF] Al-Shyoukh | A transient-enhanced low-quiescent current lowdropout regulator with buffer impedance attenuation[END_REF]- [START_REF] Zhan | Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips[END_REF]. For example, the buffer stage is adaptively biased as shown in [START_REF] Al-Shyoukh | A transient-enhanced low-quiescent current lowdropout regulator with buffer impedance attenuation[END_REF], where the increase in current in the buffer stage aids the circuit by pushing the parasitic pole associated with parasitical capacitors at the gate of power transistors to higher frequencies and by increasing the current available for slew-rate conditions; one more choice is used at the input stage in [START_REF] Lam | A 0.9 V 0.35 µm adaptively biased CMOS LDO regulator with fast transient response[END_REF] and [START_REF] Zhan | Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips[END_REF] to simultaneously extend both slewing and bandwidth. Another more current-efficient way is to utilize dynamic biasing technique where more bias current is adopted only at the transient instant when the output current is changed [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF]. Based on this idea, the capacitive coupling and dynamic charging method is reported lately, which is very promising in increasing circuitry response speed while keeping static power consumption low. It can be utilized to increase the bias current of error amplifier momentarily [START_REF] Or | An output-capacitorless low-dropout regulator with direct voltage-spike detection[END_REF]- [START_REF] Ho | A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application[END_REF] or construct a current-boosting voltage buffer [START_REF] Leung | A CMOS low-dropout regulator with a momentarily current-boosting voltage buffer[END_REF] and a differentiator [START_REF] Milliken | Full on-chip CMOS lowdropout voltage regulator[END_REF] for bandwidth and slew-rate improvement. Slewing detection can be made by either monitoring an internal node or at the output. The important issue here is that when the capacitive coupling circuit is used in a closed loop scheme, since it will introduce other control loop after being triggered when the capacitive coupling circuit is used in a closed loop scheme, the transient stability analysis is getting more complicated, which is very necessary to make sure it works robustly.

In this work, an adaptive biasing error amplifier with a low-power dynamic pushpull SRE circuit is applied to a capacitor-less LDO to show enhancements in transient responses. This chapter is organized as follows. Concept of the proposed LDO is discussed in Section II. Circuit design and implementation are shown in Section III. Experimental results and conclusions are given in Sections IV and V, respectively.

Design Of The Proposed Circuits

As shown in Fig. 1, the basic structure of this ultra-fast capacitor-less LDO is similar with [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF] focusing on dynamic biasing. It is constructed by two differential common-gate transconductance cells, a voltage buffer, a current-summation circuit and an additional SRE circuit. The two G m cells, which are made basically by a pair of matched transistors (M a and M b in Fig. 1 as an example) in the form of a current mirror, are cross-coupled achieving a push-pull output stage to inject and withdraw more current for charging and discharging during the transient instant. Because the output current I o has a quadratic dependence on its input-voltage difference according to the square-law characteristic of MOS transistor, the maximum output current I omax is no longer limited by the constant-current source as in the case of conventional amplifier with a tail-current. This is very practical for fully on-chip LDOs to improve transient response since low power and high slew rate can be realized at the same time. Although the SR-limit problem has been improved by enabling a higher bias current during the transient instant, this differential common-gate amplifier has limited input common-mode range (ICMR) and, most importantly, limited bandwidth which is determined by transconductance G m and gate capacitance C pass of the power transistor as shown in Fig. 1. Therefore, fast changing voltage spike cannot be detected effectively by the amplifier at low bias current. Moreover, this approach is not applicable when V OUT is at a small value, which happens when providing an adaptive supply for a power-saving SoC design. To combat the aforementioned challenges, a current efficient and high bandwidth error amplifier with a dynamic push-pull SRE circuit is proposed in this chapter.

Adaptive Biasing Error Amplifier

It is obvious that a larger transconductance G m means a larger GBW and faster transient response at the gate of the power transistor, which requires more power applied to the LDO. However, the traditional methods to improve G m of this simple common-gate amplifier have some difficulties to be realized. For instance, a large bias current I B will increase the minimum input voltage for the amplifier, deteriorating ICMR; also increasing the aspect ratios of input transistors may put them into weakinversion region when a low quiescent current has been adopted. Here, a currentmode method called current subtracter can be utilized to resolve this problem. As shown in Fig. 2, another duplicated common-gate amplifier (M 3 -M 4 ) has been crosscoupled with M 1 -M 2 to provide a current I M4 that varies contrarily compared to I M1 and is redirected to node C. The only difference is the aspect ratio of input transistors, which is 2/1, to guarantee a normal bias point of the total output current I push . The larger a voltage pike ΔV + is, the more I push will be gained compared to using M 1 -M 2 alone. As a result, the total transconductance G m is enhanced by a factor of 1.5 as given by ( )

1 4 1 1.5 m m m m G k g g kg = + = (1)
where k is the gain of current mirror M 7 -M 8 and set to be 3 in the circuit for boosting output-driving ability. This structure has nearly the same effects as increasing I B to increase G m while introducing less pressure on ICMR design.

Note that the power transistor can be designed to work in linear region when heavy load occurs, such that a more efficient usage of the chip area is achieved. In saturation region, the relationship between I d and V gs is quadratic, and in linear region, it is linear, where an equal factor of increment in I d requires a larger increment of V gs . Therefore, the circuit needs larger bandwidth and slew rate at heavy load for high speed control, which is achieved successfully by adaptive biasing [START_REF] Hazucha | Area-efficient linear regulator with ultra-fast load regulation[END_REF]. The operation revolves around sensing the output current of the regulator and feeding back a ratio of the current to the input stage of the amplifier. This can be done by a simple current mirror and a sense MOSFET that are area efficient. In addition to the small fixed biasing current I B , a feedback current I AB relating to load current I load (i.e., I AB =βI load ) is applied to the drain of transistor M 2 to control V gs2 at different loads. Because V gs1 and V gs2 are equal at DC operating point, the transconductance g m1 of M 1 can be expressed as

( ) ( ) 1 1 2 m p o x B A B g C I I W L µ = + (2)
The resulting larger bias current at heavy loads increases transconductance of the input pair, leading to a larger bandwidth of the amplifier. During low load current conditions, the feedback current I AB is negligible, yielding a high current efficiency and not aggravating battery life.

One important design issue is about carefully setting I AB or aspect ratio β between the current-sense transistor and power MOSFET at different loads. Too small β will not gain dynamic biasing advantages; however, since M 2 is diode-connected and the input V -is a stable reference voltage, too large β will introduce more feedback current I AB to the input stage pushing V B to a very low voltage especially when V OUT is small, which may result in transistors in the current source of I B and I AB entering into linear region. If this unluckily happens at large load current, there exists no isolation between ground and bias voltage V B . The ground noises will couple freely to the gate of input transistors, degrading performances of the amplifier. In this circuit, the largest load current is 100mA and the aspect ratio of I load /I AB is chosen as 10000/1, where the largest feedback current is approximately 10µA.

Dynamic Push-Pull SRE Circuit

Unluckily, the adaptive biasing is activated only when the gate voltage of the power MOS (V G ) goes down (i.e., when the feedback is going to compensate an abrupt increment of load current). However, if the load current suddenly increases, an amount of time occurs before V G is moved down and before the adaptive biasing is activated, which is determined by the bandwidth of the loop. This latency may strongly reduce effectiveness of the adaptive biasing. For example, when the load current steps down from heavy load to light load, the fast charging of the pass transistor gate enables small overshoot and fast recovery of the LDO output voltage. However, the biasing current of the amplifier is low at light load that leads to a large undershoot of the output voltage when the load current steps up from the minimum to the maximum in a very short time. 1) Principle of Operation: In order to get rid of the dependence on limited bandwidth and reduce output voltage spikes and recovery time further, a SR enhancement (SRE) circuit based on dynamic push-pull (DPP) techniques is implemented in parallel with the AB error amplifier to get a better regulated power supply. The SRE circuit only provides a dynamic current to charge or discharge gate capacitance C pass of the power transistor during transient if large voltage spikes take place, and is completely turned off in the static state, dissipating small quiescent current. It should improve both loop-gain bandwidth and slew rate at the gate drive of power transistor, while maintaining high current efficiency in static state.

V out

Normally, the SRE circuit consists of a sensing and driving circuit [START_REF] Ramírez-Angulo | A novel slew-rate enhancement technique for one stage operational amplifiers[END_REF]- [START_REF] Nagaraj | CMOS amplifiers incorporating a novel slew rate enhancement circuit[END_REF]. How to avoid a larger loading capacitance due to additional structures as well as high dynamic current at input stage in these existing methods is critical. For example, a current-detection SRE circuit detecting changes in the current signal at active load of the core amplifier is reported in [START_REF] Lee | Design of low-power analog drivers based on slewrate enhancement circuits for CMOS low-dropout regulators[END_REF]. The advantage is that it does not increase the loading of error amplifier.

In the proposed structure shown in Fig. 3(a), the sensing circuit adopts a voltage detection method based on capacitive coupling. It senses rapid transient voltage changes at the output of the LDO and then changes current signal I M4 or I M11 to trigger a dynamic push-pull circuit for increasing the driving current momentarily. The basic circuit is a modification to current mirrors M 3 -M 4 and M 3 -M 11 , where capacitor C 1 and resistor R 1 have been added to realize a high-pass filter. It provides a fast path to detect the output voltage spikes. As shown by the timing diagrams in Fig. 3(a), when the amplitude of V OUT changes from low to high (ΔV) instantaneously (represented by the real line), the rapid voltage change couples to the gate of M 11 directly due to the high-pass property of C 1 . When C 1 is chosen to be much larger than C gs3 + C gs4 +C gs11 , the gate voltage of M 11 is dominated by the coupled signal from C 1 in this instant. Thus, V gs11 is changed momentarily and the extra current ΔI 6 can be found from [START_REF] Or | An output-capacitorless low-dropout regulator with direct voltage-spike detection[END_REF] ( )

11 6 1 1 2 2 n ox M m B I g C V b I V W L µ Δ ≈ Δ = Δ (3)
It is found that a larger aspect ratio of the current mirror helps to increase ΔI 6 for injecting more transient current, but at the penalty of increased quiescent current in steady state. Therefore, the size of M 11 should be carefully designed to strike a balance between the above tradeoffs. This consideration is also applicable to transistor size design of M 4 . When V OUT changes from high to low (represented by the dotted line), the coupling effect generates a smaller I M4 and triggers the pull action. When V OUT stays at a constant voltage in the steady state, C 1 is open-circuited, resulting in an auto shutdown of the current boosting circuit. Besides, this coupling effect is independent of the DC value of V OUT due to the high-pass characteristic of C 1 , so the proposed method is suitable for detecting any output voltage level, improving ICMR of the amplifier considerably.

The driving circuit is composed of transistors M 9 -M 16 . Based on the appropriate ratios of current mirror (b 1 , b 2 ), M 9 and M 10 (M 11 and M 12 ) are designed such that if both transistors operate in the saturation region, their drain currents must meet the relationship I 3 <I 4 (I 5 >I 6 ). So M 10 and M 12 operate in the triode region such that voltages of node N 1 and N 2 are set to "1" and "0" to force transistors M 13 and M 16 to be turned off at steady state.

Once the load current decreases quickly and causes large output variations, the extra current ΔI 6 is generated to pull the voltage of node N 1 down. Then transistor M 13 will then be heavily turned on to charge the gate capacitance of power transistor. When V OUT is regulated back to its expected voltage in the steady state, I 6 decreases and the voltage of node N 1 is smoothly reset to "1" to turn transistor M 13 off.

2) Sensitivity to Supply voltage: Similarly, the transistor M 16 can be turned on by pulling the voltage of node N 2 high to discharge the gate capacitance during the negative slewing period. As shown in Fig. 3(b), the traditional method to increase a PMOS current I 3 momentarily is just by pulling down the gate voltage directly [START_REF] Or | An output-capacitorless low-dropout regulator with direct voltage-spike detection[END_REF]. However, there exist some problems for this structure. First, additional high-pass filter devices (R 2 and C 2 ) are needed, occupying large chip area inevitably. Second, it is sensitive to supply voltage variations. This is because when a large coupling capacitor C 2 has been connected to the gate of M 9 in Fig. 3(b), the bandwidth of current mirror M 8 -M 9 is degraded due to the largely increased capacitance at the gate. As a result, the gate voltage V G9 cannot follow variations of the supply voltage in lowpower design. For example, when V IN increases fast, V GS9 may be enlarged instantaneously. I 3 is thus increased, having the potential risk to pull the node voltage V N2 high and turn on M 16 falsely. An unwanted discharging current I discharge , depending on the amplitude of ΔV IN , flows to the gate of power MOS and tries to pull V G down. So the output voltage of the LDO is increased and must be regulated by the negative feedback loop in a certain time. Moreover, if V IN decreases rapidly, M 9 may be shut down to delay the pull function of SRE circuit, because only a small bias current is used here to pull V G9 low. The PSRR and line-transient performances are therefore degraded, which has a similar phenomenon in [START_REF] Or | An output-capacitorless low-dropout regulator with direct voltage-spike detection[END_REF].

The simplest solution is with the help of an RC filter in line with the power supply to filter out fluctuations before they reach the SRE circuit. However, the high power losses and reduction in voltage headroom caused by this resistor when the SRE circuit is triggered would severely limit its size, pushing the pole to high frequencies. Another methodology is assisted by adding a cascode structure such as resistors into the PMOS bias current pair M 8 -M 9 , making the coupling circuit insensitive to supply voltage noise. However, this may reduce the transconductance at the coupling input port and the dynamic charging effect is weakened. The new idea proposed in this brief to avoid such problems is just by adopting current subtracter M 4 -M 6 instead as shown in Fig. 3(a). After that optimization, only one coupling capacitor C 1 is needed leading to a smaller chip area. The main difference compared to using two coupling capacitors is that the circuit speed response for enabling charging action is degraded by additional two current mirrors (M 6 -M 7 and M 8 -M 9 ) and small bias current I B . However, by making the sizes of these transistors small, the parasitic capacitances are set small and the time delay can be ignored. In addition, transistors M 14 and M 15 are used to prevent the noise of N 1 and N 2 from coupling to the gate of the power transistor when transistors M 13 and M 16 are turned on.

3) Optimal Sizing of Drive Transistors: The response time of the SRE circuit is determined by the time required to turn on or turn off drive transistors M 13 and M 16 when an output voltage spike ΔV is applied to the DPP SRE circuit. During the positive (negative) output slewing, transistor M 12 (M 10 ) is in the saturation region. Therefore, the response time t res,p and t res,n of the SRE circuit for positive and negative slewing periods is approximately given by ( )

, 12 1 11
,

thp ov M p m res p V V C t g V - Δ ≈ (4)
( )

, 10 2 4
, 1

thn ov M p m res n V V C t b g V - Δ ≈ (5)
where V ov is the overdrive voltage of MOS transistor, C p1 (C p2 ) is the parasitic capacitance at node N 1 (N 2 ). Equations ( 4) and [START_REF] Lin | An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement[END_REF] show that the response time increases with the value of C p1 and C p2 . Increasing the sizes of transistors M 13 and M 16 thus slows down response time of the SRE circuit.

On the other hand, larger size of drive transistors is critical for controlling the amount of dynamic currents to charge and discharge V G , therefore affecting the maximum attainable slew rate. For example, assuming that M 13 and M 16 are in saturation regions with constant dynamic current during the output slewing periods and the channel length modulation is neglected, the drive transistor size can then be demonstrated as ( )

2 13
, 11

2 pass M p ox IN ov M thp SR C u W L C V V V + ⋅ ⋅ ≈ - - ⎛ ⎞ ⎜ ⎟ ⎝ ⎠ (6) ( ) 2 16
, 9

2 pass M n ox IN thn ov M SR C u W L C V V V - ⋅ ⋅ ≈ - - ⎛ ⎞ ⎜ ⎟ ⎝ ⎠ (7)
where SR + and SR -are the slew rate improvement achieved by DPP SRE One method to resolve the trade-off between speed response and SR is to enlarge g m4 and g m11 without increasing much power.

From the above analysis, it seems that the dynamic push-pull scheme adds a gain into the loop by the boosted current and can effectively enhance the transient response time for regulating the output voltage back to a stable voltage level, i.e., the circuit is used to enhance the slew rate of the error amplifier during the transient period.

Because the loop-bandwidth is low-pass and limited while this feedforward path due to capacitive coupling is high-pass, the values of R 1 and C 1 can thus be selected by setting the corner frequency (1/R 1 C 1 ) a little lower than the GBW to extend the loopbandwidth of the LDO and make sure the DPP SRE circuit only works for high frequency spikes.

Comparisons between the loop gains of the proposed LDO and circuit structure like [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF] at different load conditions are shown in Fig. 4 to prove the superiority. Method A (adaptive biasing) enlarges the bandwidth at heavy load and method B (dynamic push-pull techniques) focuses on voltage variation at high frequency, all of which will lead to a faster transient response at low bias current.

Circuit Realization

Fig. 5 shows the schematic of the proposed LDO regulator, which consists of a PMOS power transistor M o , a current-sensing circuit, a high slew-rate push-pull error amplifier, a SRE circuit and a reference buffer. The push-pull output stage constructed with transistors M 13 and M 20 facilitates the LDO regulator using only moderate size M o to provide a wide range of load currents. In this circuit, to provide 100mA load current with 150mV dropout, the aspect ratio of (W/L) Mo is chosen to be 15000µm/0.35µm in a 0.35µm standard CMOS process where the threshold voltage |V thp | of M o is about 0.66V. The error amplifier is mainly constructed of two cross-coupled common-gate cells G mH and G mL . Here some transistors like M 2 and M 3 have been reused in both input stages of the cells. The typical bandwidth of a LDO with 100mA output capability is about 200kHz to 1MHz [1]- [START_REF] Lau | A low-dropout regulator for SoC with Qreduction[END_REF]. Assuming the corner frequency is set to be about 100kHz, the required passive components R 1 and C 1 are 3pF and 500kΩ respectively, where the accuracy is not important. Current mirrors M 12 -M 13 and M 19 -M 20 are used to realize a current-summation circuit. To ensure the amplifier has fast-transient responses and large voltage-gain, the channel lengths of all transistors except M o are designed to be five times of the minimum feature size to guarantee that all the parasitic poles are at high frequency.

Since most of voltage references do not have output current driving ability [START_REF] Ming | A high-precision compensated CMOS bandgap voltage reference without resistors[END_REF], a voltage buffer without frequency compensation is introduced here to transfer the voltage V REF to the inputs of the G m cells. Because adaptive biasing is utilized in the circuit, the resulting bias current for the amplifier is increased at heavy load, which requires an enhanced driving current I drive from the buffer. Therefore, the aspect ratio (W/L) M30 should be designed to satisfy the maximum driving ability without using a large overdrive voltage, which must be always smaller than the dropout voltage at different loads. Otherwise, M 30 may enter into linear region when the difference between V IN and V OUT is small. This will provide a low-resistance path where the supply noises can couple to inputs of the G m cells, degrading PSRR greatly. Furthermore, the bandwidth of the buffer should be designed to satisfy the maximum bias current variation rate when the load current changes from light load to heavy load. If not it will cause large voltage droop at the output of the buffer, deteriorating transient responses.

As shown in Fig. 5, because the output of the LDO is connected to a low-resistance node such as the source terminals of M 1 and M 3 inside the G mH cell, this sets the dominant pole p 1 locating at the gate of the power transistor and the output pole p 2 of the LDO to be non-dominant. As both drive transistors M 44 and M 45 are off in the LDO during the static state, there is almost no difference between the ac responses of the LDO with and without the SRE circuit. Here four parts mainly contribute to total output load capacitance C load in this structure, including C db of the power MOSFET, input capacitors C in from G m cells, coupling capacitor C 1 from DPP SRE circuit and the parasitic output capacitance C par due to the metal lines for on-chip power distribution which is generally in the range of 10-100pF [START_REF] Hazucha | Area-efficient linear regulator with ultra-fast load regulation[END_REF]. By using the circuit proposed above, more input transistors and capacitors are implanted at the output of the LDO compared to [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF], C load is therefore unluckily increased pushing p 2 to lower frequency, which may degrade phase margin of the feedback loop. This stability may be even worse when a large parasitic capacitance C par and small I load are applied [START_REF] Milliken | Full on-chip CMOS lowdropout voltage regulator[END_REF].

In order to realize pole splitting under a wide range of I load from several tens of milliamperes to several µA and occupy less silicon area, the active capacitor multiplier is adopted for Miller compensation [START_REF] Rincon-Mora | Active capacitor multiplier in miller-compensated circuits[END_REF]. Here, capacitor C 2 performs the multiplied-miller capacitor with current buffer. The overall equivalent miller capacitor C c is equal to kC 2 , where k=(S 18 /S 17 )×(S 20 /S 19 ) and S i =(W/L) i is the aspect ratio of the i-th transistor.

Assuming G m1 and R o1 are the equivalent first stage transconductance and output resistance of the LDO, g mo and C pass are the transconductance and gate capacitance of the power transistor, R out is the overall output resistance, the frequency response can then be given by (

)

1 1 1 pass c mo out o p C C g R R + = ⎡ ⎤ ⎣ ⎦ (8) ( ) ( ) 2 1 / mo out load pass load p g R C C I = ∝ + + (9) ( )
[ ]

1 1 mo pass m out c m load mo GBW g C G R C G I g = ∝ + (10)
Here the input resistance 1/G m1 of the error amplifier mainly determines R out . Because adaptive biasing is applied, poles and GBW are changed accordingly in different load conditions as shown in equations ( 9) and [START_REF] Al-Shyoukh | A transient-enhanced low-quiescent current lowdropout regulator with buffer impedance attenuation[END_REF]. In order to make sure a phase margin larger than 45°, p 2 should be larger than GBW to determine the total Miller capacitor C c .

( )

C G R G C C C g R g R g > - + + ; (11)
The minimum load current for the LDO to ensure stability is 0.5mA. Normally, the parameter g mo R out or g mo /G m1 is set large enough to make this compensation achieved without using any large on-chip compensation capacitors. In this design, the required compensation capacitor C 2 is only 2.3pF. Area efficiency of such LDO regulator is thus maintained, which is particularly suitable for chip-level power management. Also the capacitor multiplier introduces a left-hand plane zero z 1 (g m17 /C 2 ) at a relatively high frequency, which can be designed near the output pole p 2 to add phase and optimize frequency compensation.

Experimental Results and Discussion

The proposed capacitor-less LDO has been implemented in standard 0.35µm CMOS technology. The circuit was designed to provide 2.5V output voltage at 100mA output current for input voltage greater than 2.65V. Load transient behavior, which is mainly decided by SR and its bandwidth of the LDO, is simulated here at to evaluate the transient performance. Fig. 6 shows the load-transient responses with a 100pF off-chip output capacitor, which is used to model the output-parasitic capacitance from the metal lines. In Fig. 6(a), I load varies from 0.5mA to 50mA and V IN is 2.8V, while the load current change is increased to 100mA in Fig. 6(b). The results show that the output voltage can be fully recovered within 0.7µs at a voltage spike less than 229mV. It can be also observed in Fig. 6(b) that with the use of DPP SRE circuit in the LDO, which only consumes 29.4% additional static current, significant improvement in transient responses can be achieved in low-power condition. The working process and advantage of the DPP SRE circuit can be analyzed in detail in Fig. 7. For example, when the load current changes from the light load to heavy load, a large undershoot occurs at the output. The current comparator (M 40 /M 41 ) takes effect to pull the node voltage V N2 high and turn on drive transistor M 45 heavily. A dynamic current I M45 (more than 100µA) can be provided to reduce the output-voltage excursion during transient. In addition, the pole located at the gate of the power transistor will be shifted to a higher frequency due to the turn on of drive transistor M 45 during transient, thereby improving the bandwidth of the LDO. The settling time is therefore improved by about 2.9 times when a 100mA output-current change is applied. The phenomenon for the overshoot reduction is similar in Fig. 7 The load-transient responses without an off-chip output capacitor are shown in Fig. 8. The current change ΔI load are chosen as 50mA and 100mA again respectively. Measurement results show that the proposed capacitor-less LDO can be fully recovered within 0.8µs at a voltage spike less than 250mV.

From the simulation results shown above, it can be seen that the DPP SRE circuit aids in adjusting the power MOS in the transient response effectively to avoid large output spikes, where the voltage deviation and response time are much better than that in [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF] even at a twice load current change. The sizes of driving transistors in SRE circuit have been optimized to avoid overcharging at the gate of M o and good stability of the LDO regulator can be achieved. To prove the DPP SRE circuit is not sensitive to supply voltage variations because of a current subtracter introduced, the line-transient is therefore simulated. The linetransient response with a 100pF off-chip output capacitor is shown in Fig. 9, where V IN varies from 2.65V to 3.3V. The result shows that the output voltage can be fully recovered within 1µs at a voltage spike less than 76mV when I load is 100mA. No dynamic spurs and injected noise occur and the circuit works robustly. However, if the load current is small, the bandwidth of the LDO is decreased, which may introduce a larger voltage spike and trigger the pull function of the DPP SRE circuit in a certain time. Because Miller compensation is adopted to guarantee sufficient phase margin during transient as analyzed before, the small ringing can be attenuated quickly without affecting the transient performance. Finally, power-supply ripple rejection (PSRR) against different load currents is shown in Fig. 10. The proposed LDO can achieve about 74dB PSRR at 1kHz when I load =100mA. 1 shows performance comparison with some previously reported capacitor-less LDOs. A figure of merit (FOM=T settle ×I Q /I load(max) ) used in [START_REF] Hazucha | Area-efficient linear regulator with ultra-fast load regulation[END_REF] and [START_REF] Man | A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[END_REF] is adopted here to evaluate different current efficient designs for improving transient response. The response time T settle (T settle =C load ×ΔV OUT /I load,max ) is found from C load for a specified I load,max and ΔV OUT . A lower FOM implies a better slewing performance, where the proposed regulator has the lowest FOM (0.05ns). This feature is very important and attractive to any high-density SoC applications.

Conclusion

This chapter presents an ultra-fast, capacitor-less LDO with an advanced commongate error amplifier and DPP SRE circuit. Some low-power methods like adaptive biasing and capacitive coupling have been adopted to improve both ICMR and loop bandwidth of the error amplifier greatly, while maintaining the traditional advantages such as low quiescent current and small chip area. By applying them to a LDO with a power-efficient methodology, the accuracy and response speed are significantly enhanced. The experimental results confirm that overshoots and undershoots in load transient of the LDO are improved greatly as results from the loop-gain-bandwidth enhancement. The performances are especially encouraging in chip-level power management.

Fig. 1 . 1 VBFig. 2 .

 112 Fig. 1. Conceptual schematic of the proposed capacitor-less LDO regulator

Fig. 3 .Fig. 4 .

 34 Fig. 3. DPP SRE circuits with capacitive coupling (a) Proposed DPP techniques (b) DPP structure with two coupling capacitors

Fig. 5 .

 5 Fig. 5. The proposed ultra-fast capacitor-less LDO with a reference buffer

Fig. 6 .

 6 Fig. 6. Simulated load-transient responses with a 100pF off-chip output capacitor for different current changes (a) ΔI load =50mA (b) ΔI load =100mA

Fig. 7 .

 7 Fig. 7. Partial enlargement of the voltage spikes for a 100pF off-chip output capacitor and 100mA load current change (a) undershoot (b) overshoot

  (b).

Fig. 8 .

 8 Fig. 8. Simulated load-transient responses without an off-chip output capacitor for different current changes (a) ΔI load =50mA (b) ΔI load =100mA

Fig. 9 .

 9 Fig. 9. Simulated line-transient response with a 100pF off-chip capacitor

Fig. 10 .

 10 Fig. 10. Simulated PSRR versus frequency for I load =0.5mA and I load =100mA when V REF =2.5V, V IN =2.8V and C load = 100pF

Table 1 .

 1 Performance Comparison With Previous Published Work

		[9]	[13]	[14]	[20]	This Work
	Technology(µm)	0.09	0.18	0.35	0.35	0.35
	Input voltage V IN (V)	1.2	1-1.8	0.95-1.4	3-4.2	2.65-3.3
	Dropout voltage V DO (mV)	300	100	200	200	150
	Quiescent current I Q (µA)	6000	1.2	43	65	10 (no load)
	Output current I load (mA)	100	50	100	50	100
	Load regulation(mV/mA)	N/A	0.148	~0.4	~0.56	0.005
	Line regulation(mV/V)	N/A	3.625	N/A	~23	0.38
	Settling time T settle (µs)	0.00054	~2.8	~3	~15	~0.5
	FOM(ns)	0.032	0.067	1.29	19.5	0.05
	Table


Xiaojin Zhao
email: eexjzhao@szu.edu.cn

Amine Bermak
email: eebermak@ust.hk

Farid Boussaid
email: boussaid@ee.uwa.edu.au

A Low Cost CMOS Polarimetric Ophthalmoscope Scheme for Cerebral Malaria Diagnostics

Keywords: Polarimetric ophthalmoscope, polarimetric imaging, micropolarizer array

In this chapter, we present a low cost CMOS polarimetric ophthalmoscope scheme enabling the capture of the retinal abnormalities that are unique to cerebral malaria. The proposed technology, which can be integrated into cellphones, offers the basis for quick and non-invasive screening of cerebral malaria. In addition, we report a micropolarizer array technology exploiting "guest-host" interactions in liquid crystals for visible imaging polarimetry. The proposed technology enables the fabrication of high resolution (5µm × 5µm pixel pitch) micropolarizer arrays with submicron thickness (0.95µm) to provide for larger light collection angles and reduced optical cross-talk. With the "host" nematic liquid crystal molecules photo-aligned by sulfonic azo-dye SD1, we report averaged major principal transmittance and polarization efficiency (PE) of 80.3% and 0.863, respectively across the 400nm -700nm visible spectrum range. The proposed fabrication technology is simple and costeffective, requiring only a single ultraviolet-exposure of the spin-coated "guest-host" mixture through a "photoalignment master".

Introduction

Cerebral malaria is an acute, widespread disease of the brain, which is accompanied by fever, cognitive impairments (especially in children) and coma. The mortality ratio is between 25-50%. If a person is not treated, cerebral malaria is fatal in 24-72 hours. The direct visualization of the malaria parasite, under the microscope, remains the gold standard for its diagnosis. To remove the need for the required skilled and specialized equipment (microscope, reagents), rapid diagnostic tests have been proposed to detect the antigens/products of the parasite in the blood. However, these tests are often difficult to interpret because they exhibit lower sensitivities at low parasite densities and vary in sensitivity between malaria species [START_REF] Beare | Malaria retinopathy: a newly established diagnostic sign in severe malaria[END_REF]. To improve the diagnosis of cerebral malaria, we propose a low cost digital polarimetric ophthalmoscopy technology that enables the capture of the retinal abnormalities that are unique to cerebral malaria. The cost of ophthalmoscopes and the level of skills required (pupil dilatation and eye examination) do not allow currently for the wider use of ophthalmoscopy in poor malaria-endemic countries. To address these issues, we propose a low cost CMOS polarimetric ophthalmoscope scheme that enables a simple mobile phone to be used as a digital ophthalmoscope (Fig. 1). The user could ultimately even take a polarimetric snapshot of his/her own retina. The retinal images would then be transmitted to a processing node, which would then screen the data for signs of malarial retinopathy. Since the retina is part of the central nervous system, it exhibits a similar cellular structure and blood-tissue barrier. As a result, examining the retina provides a non-invasive and in vivo means to detect infected microvasculature and neurologic tissue [START_REF] Beare | Malaria retinopathy: a newly established diagnostic sign in severe malaria[END_REF]. It is widely accepted that cerebral malaria is manifested by retinal whitening and a discoloration of retinal vessels to orange or white [START_REF] Beare | Malaria retinopathy: a newly established diagnostic sign in severe malaria[END_REF]. Furthermore, other research works have shown that polarization imaging can provide an enhanced view of the tissue and reveal details not visible by conventional retinal photography [START_REF] Campbell | Confocal Polarimetry Measurements of Tissue Infected with Malaria[END_REF]. As shown in Fig. 1, the integration of a micropolarizer array (i.e. a mosaic of micro-scale polarizer elements of different orientations) over the pixel array of an image sensor enables the concept of a low cost single-chip polarization camera capable of capturing, in a single frame, the polarimetric information of a scene [START_REF] Andreou | Polarization Imaging: Principles and Integrated Polarimeters[END_REF]. A number of micropolarizer array (MPA) implementations have been demonstrated for image sensors. Examples include patterned dichroic films such as polyvinyl alcohol (PVA) [START_REF] Guo | Fabrication of thin-film micropolarizer arrays for visible imaging polarimetry[END_REF][START_REF] Gruev | Fabrication of a Dual-Tier Thin Film Micro Polarization Array[END_REF], birefringent Y V O 4 crystal covered by patterned aluminum films [START_REF] Momeni | An Analog VLSI Chip Emulating Polarization Vision of Octopus Retina[END_REF], multiple-domain liquid crystal with micro-patterned alignment layers [START_REF] Harnett | Liquid-crystal micropolarizer array for polarization-difference imaging[END_REF], and nanometer-scale metal wire grid [START_REF] Gruev | Nano-wire Dual Layer Polarization Filter[END_REF]. In each case, selective etching is used to pattern micropolarizer elements at the pixel pitch. To completely remove the need for this complex selective etching, we proposed, in [START_REF] Zhao | Thin Photo-Patterned Micropolarizer Array for CMOS Image Sensors[END_REF], to use instead the well-controlled process of ultraviolet (UV) photolithography for the patterning of a high resolution pixel-level micropolarizer array. A spin-coated photosensitive azo-dye-1 (AD1) was used as the polarizing film [START_REF] Zhao | Thin Photo-Patterned Micropolarizer Array for CMOS Image Sensors[END_REF]. This material exhibits a strong dichroism after sufficient exposure to linearly polarized UV light. The rod-like molecules of a spin-coated AD1 film can be oriented with their long molecular axes perpendicular to the orientation of the projected polarized UV light. However, the orientation degree of AD1 molecules is a function of the exposure energy and saturates after prolonged UV exposure. As a result, a UV-patterned polymer AD1 film exhibits limited major principal transmittance and extinction ratio [START_REF] Zhao | Thin Photo-Patterned Micropolarizer Array for CMOS Image Sensors[END_REF].

Mi l i Micropolarizer array Patient's eye

O ti l l

Patient s eye

Cornea

CMOS i i

Optical lens

In this chapter, a "guest-host" MPA, with photo-aligned polymerizable nematic liquid crystal (NLC) as the "host" material and AD1 molecules as the "guest", is proposed to improve the orientation degree of AD1 molecules and thus the optical performance. Section 2 presents the micropolarizer array pattern design. Section 3 describes the principle of a "guest-host" micropolarizer array and its fabrication. Experimental characterization results are discussed in Section 4. Finally, a conclusion is drawn in Section 5.

Micropolarizer array pattern design

In this section, we describe the pattern design methodology for the "guest-host" micropolarizer array. Light's partial linear polarization information is fully characterized by the first three Stokes parameters (S 0 , S 1 , S 2 ) [START_REF] Goldstein | Polarized Light, 2nd Edition[END_REF]. With (S 0 , S 1 , S 2 ) representing the total intensity, the amount of linear 0 • or 90 • polarization and the amount of linear 45 • or -45 • polarization, respectively, the emerging light intensity after passing a linear polarizer can be expressed as a linear combination of (S 0 , S 1 , S 2 ) with their coefficients as functions of the transmission axis orientation of the linear polarizer. This can be accurately described by introducing the linear polarizer's Mueller matrix M linear [START_REF] Goldstein | Polarized Light, 2nd Edition[END_REF]:

    α βcos2θ βsin2θ 0 βcos2θ αcos 2 2θ + γsin 2 2θ (α -γ)sin2θcos2θ 0 βsin2θ (α -γ)sin2θcos2θ αsin 2 2θ + γcos 2 2θ 0 0 0 0 γ     (1)
with

α = p 2 x + p 2 y 2 (2)
β = p 2 x -p 2 y 2 (3)
γ = p x p y ( 4
)
where θ is the linear polarizer's transmission axis orientation, the quantities p x and p y are the absorption coefficients of the orthogonal optical axes (0 p x , p y 1). The total intensity of the emerging light (S ′ 0 , S ′ 1 , S ′ 2 , S ′ 3 ) after passing the linear polarizer is represented by its first Stokes parameter S ′ 0 :

I = S ′ 0 = α • S 0 + βcos2θ • S 1 + βsin2θ • S 2 (5)
For a given linear polarizer with reliable physical properties, we can assume its absorption coefficients (p x , p y ) constant. Therefore, mathematically, at least three intensity measurements, through linear polarizers with three different transmission axis orientations, are needed to extract the incident light's partial linear polarization information fully included in the first three Stokes parameters. To determine the optimal number of intensity measurements N , a popular strategy is to use a large number of measurements (e.g. N = 16) to reduce the system speckle noise and improve the quality of Stokes images, which are reconstructed with the extracted Stokes parameters for each pixel of the twodimensional photo-sensing array [START_REF] Vaughn | Noise reduction in a laser polarimeter based on discrete waveplate rotations[END_REF]. However, the approach of micropolarizer array, similar to that used in a color filter array, trades-off spatial resolution to allow for the acquisition of the first three Stokes components in a single frame and concretely, each micropolarizer makes only one of the N intensity measurements and N micropolarizers are dedicated to one pixel of the Stokes images to be reconstructed. Although this spatial resolution loss by a factor of N could be alleviated by examining the intensity values of neighboring pixels and adopting interpolation algorithms, it will become extremely difficult even unreliable for a large value of N . In addition, in a recently appeared literature [START_REF] Goudail | Estimation precision of the degree of linear polarization and of the angle of polarization in the presence of different sources of noise[END_REF], Goudail et al. indicate that some noise is independent of even increases with N such as additive noise, and the optimum value of N results from a compromise between the robustness to different noise sources. Here we choose an N value of 4 with the micropolarizers' transmission axis orientations denoted as (θ 1 , θ 2 , θ 3 , θ 4 ) and the intensity measurements can be expressed in matrix form:

    I 1 I 2 I 3 I 4     =     α βcos2θ 1 βsin2θ 1 α βcos2θ 2 βsin2θ 2 α βcos2θ 3 βsin2θ 3 α βcos2θ 4 βsin2θ 4     •   S 0 S 1 S 2   (6)
From Eq. ( 6), we can see that, a judicious choice of θ for each micropolarizer can significantly reduce the complexity of the Stokes parameters computation circuitry's silicon implementation. Fig. 1 illustrates the adopted micropolarizer array pattern with the micropolarizers' transmission axis orientations along 0 • , 90 • , 45 • and -45 • , respectively, which leads to a simplified extraction of the first three Stokes parameters.

3 "Guest-Host" Micropolarizer Array

"Guest-Host" Interactions in Nematic Liquid Crystals

Nematic liquid crystals (NLC) consist of rod-like organic molecules, whose regional ordering is characterized by the parallel alignment of molecules, along their long molecular axes. A well-known property of nematic liquid crystals is that the orientation of the molecules can be controlled with an external electric field. Furthermore, Heilmeier discovered that by controlling the molecular orientation of a nematic "host" material, the properties of the "guest" materials mixed with the nematic "host" can be controlled [START_REF] Heilmeier | Guest-Host Interactions in Nematic Liquid Crystals: A New Electro-Optic Effect[END_REF]. In this chapter, we propose a UVsensitive sulfonic azo-dye SD1 film-based non-contact photoalignment technique to fabricate high-resolution submicron thin "guest-host" micropolarizer arrays. Instead of applying an external electric field to orient the NLC "host" molecules [START_REF] Heilmeier | Guest-Host Interactions in Nematic Liquid Crystals: A New Electro-Optic Effect[END_REF], we adopt a non-contact high resolution photoalignment technique based on a UV-sensitive sulfonic-dye-1 (SD1) film, used in liquid crystal displays (LCDs) [START_REF] Chigrinov | Synthesis and properties of azo dye aligning layers for liquid crystal cells[END_REF]. As depicted in Fig. 2 spin-coated with this SD1 film. After subsequent irradiation by linearly polarized UV light, photoalignment of SD1 molecules occurs [Fig. 2 (B)] with the SD1's long molecular axes perpendicular to the polarization direction of projected linearly polarized UV light. The "guest-host" mixture of dichroic dye and NLC is then spin-coated on top of the SD1 film, which will act as an alignment layer for the NLC "host" molecules and the dichroic dye "guest" molecules. Fig. 2 (C) depicts this reorientation process with "host" and "guest" molecules aligned with SD1 molecules.

Fabrication

To demonstrate the proposed "guest-host" technology, we fabricated the micropolarizer array with the pattern shown in Fig. 1. The latter enables the extraction of full partial linear polarization information [START_REF] Goldstein | Polarized Light, 2nd Edition[END_REF]. As shown, the "guest-host" micropolarizer array exhibits a 2×2 pattern comprising 0 • , 90 • , 45 • and -45 • micropolarizers (Fig. 1). To enable the optical characterization of the fabricated micropolarizer array, a transparent glass substrate was used instead of the siliconbased opaque CMOS image sensor substrate. The detailed fabrication steps of the "guest-host" micropolarizer array can be summarized as follows:

1. Organic contaminants were removed from the surface of the transparent glass substrate, using an ultraviolet-ozone (UVO) cleaning machine (Jelight 144AX). 2. An SD1 solution was then spin-coated onto the glass at 800rpm for 10s then 3000rmp for 40s. In order to eliminate particle impurities, the solution of SD1 in dimethylformamide (DMF) with a concentration of 1% by weight was filtered before the spin-coating. 3. The glass substrate was then baked at 110 o C for 20min to remove the remaining solvent and strengthen the adhesion of the SD1 material to the substrate. 4. The spin-coated SD1 layer on the glass substrate was subsequently photoaligned with the customized "photoalignment master" applied, which is actually a patterned UV-regime metal-wire-grid polarizer from Moxtek Inc. This "photoalignment master", featuring 5µm × 5µm pixel pitch, enables one-step UV-photoalignment of the SD1 layer making the fabrication process simple, cost-effective and high resolution with no misalignment errors. The UV-exposure duration was 15min and the UV light intensity at 365nm was around 5.6mW/cm 2 . As a result, SD1 molecules were photo-aligned in different microdomains along 0 • , 90 • , 45 • and -45 • , respectively. 5. After patterning the NLC photoalignment SD1 layer, a mixture of the dichroic dye solution and the NLC solution (with a mass ratio of 1:1) was spin-coated on top of the patterned SD1 layer at a speed of 800rpm for 5s then 3000rpm for 30s. 6. Next, the substrate with the spin-coated "guest-host" mixture was baked at 50 o C for 3min to eliminate the solvents. 7. Finally, a UV light with an intensity of 2mW/cm 2 and a wavelength of 254nm, which is not within SD1's sensitive spectrum and cannot thus reorient SD1 molecules, is applied for 3min to polymerize the NLC "host" material and provide improved protection against changing environmental conditions.

Experimental Results

In order to examine each micropolarizer domain, the fabricated "guest-host" micropolarizer array sample was back-illuminated by a microscope's white light source. A broadband linear polarizer (from Moxtek Inc.) was inserted and rotated between the white light source and the fabricated sample to provide four different polarized inputs: 0 • linearly polarized, 90 • linearly polarized, 45 • linearly polarized and -45 • linearly polarized. According to [START_REF] Goldstein | Polarized Light, 2nd Edition[END_REF], the normalized Stokes parameters (S 1 /S 0 , S 2 /S 0 ) of the four different polarized inputs are (1, 0), (-1, 0), (0, 1) and (0, -1), respectively. Fig. 3 presents the sample's microphotographs examined by a linear polarization analyzer and recorded by the microscope's camera system. Note that 0 • , 90 • , 45 • and -45 • micropolarizers appear dark as expected when the input is 90 • , 0 • , -45 • and 45 • linearly polarized, respectively. In addition, a micropolarizer pitch as compact as 5µm × 5µm is achieved. The overall "guest-host" micropolarizer array thickness including the SD1 photoalignment layer was measured by a surface profiler (Tencor P-10) and found to be 0.95µm. Furthermore, the fabricated micropolarizer array was characterized by measuring the four important figures of merit: transmittances (T , T ⊥ ) and absorbances (A , A ⊥ ). Measurements were performed using a polarization state generator (PSG) comprising a mini deuterium halogen light source (DT-Mini-2-GS from Mikropack GmbH) and a broadband linear polarizer (from Moxtek Inc.). This PSG can provide linearly polarized input light with wavelengths ranging from 400nm to 700nm. Since the micropolarizer pitch is in the micrometer scale, which is much smaller than the PSG's laser beam, we fabricated unpatterned "guest-host" linear polarizer samples (2.5cm × 2.0cm) together with the micropolarizer arrays to cover the PSG's laser beam and enable the characterization of the fabricated micropolarizers. Fig. 4 (A) shows the spectral measurement results of both the major and the minor principal transmittances T , T ⊥ . The major principal transmittance is seen to range from 71.9% (551nm) to 96.8% (699nm) with an average of 80.3% across the whole visible spectrum (i.e. from 400nm to 700nm). The corresponding average P E across the whole visible spectrum is 0.863 with the maximum P E equal to 0.996 at a wavelength of 545nm and the minimum P E equal to 0.114 at a wavelength of 699nm [Fig. 4 (B)]. In this chapter, the spectrum band, for which P E exceeds 0.90, ranges from 417nm to 635nm. This corresponds to 73% of the whole visible spectrum. This enables high-quality monochromatic or achromatic polarization image sensing applications. Ongoing efforts are focusing on the development and synthesis of dichroic dyes, which are more sensitive to the visible spectrum towards the UV and infrared (IR) ends.

Conclusion

We have fabricated and characterized a high-resolution "guest-host" micropolarizer array with dichroic dye as the "guest" and polymerizable NLC as the "host". Experimental results demonstrate that micropolarizer arrays exploiting "guest-host" interactions can offer higher resolution (5µm×5µm pixel pitch), submicron thickness but also superior optical performance across the whole visible spectrum, with averaged major principal transmittance and polarization efficiency of 80.3% and 0.863, respectively. This is achieved by controlling the "guest" molecular orientation through the photoalignment of "host" molecules. The proposed non-contact micropolarizer array fabrication technology prevents mechanical damage, electronic charge or contamination to the substrate. Furthermore, it is simple and cost-effective, requiring only a single UV-exposure of the spin-coated "guest-host" mixture through a "photoalignment master". It is also compatible with standard CMOS process, enabling the integration of a "guest-host" micropolarizer array over a CMOS image sensor to realize the concept of a low cost single-chip polarization camera.

Fig. 1 .

 1 Fig. 1. Proposed low cost CMOS polarimetric ophthalmoscope scheme for cerebral malaria diagnostics.

Fig. 3 .Fig. 4 .

 34 Fig. 3. Microphotographs of the fabricated "guest-host" micropolarizer array, inspected by a linear polarization analyzer along the following orientations: (A) 0 degree; (B) 90 degree; (C) 45 degree; (D) -45 degree.

  (A), a substrate, representing the image sensor, is first

		Linearly polarized UV light Linearly polarized UV light
	SD1 SD1 l molecules l		"Guest" dichroic "Guest" dichroic d l l dye molecules	"Host" NLC Host NLC l l molecules
	S i Spin-coated SD1 film t d SD1 fil	Ph t Photo-aligned SD1 molecules li d SD1 l l	S i Spin-coated "guest-host" mixture t d " t h t" i t
	(A) (A)	(B) (B)	(C) (C)

Fig.

2

. Photoalignment of "host" NLC molecules and "guest" dichroic dye molecules.

Acknowledgment

The authors would like to thank the support from the Research Grant Council of Hong Kong SAR, P. R. China (Ref. GRF610608).


Toshiyuki Tsuchiya

Hiroyuki Tokusaki

Yoshikazu Hirai
email: hirai@me.kyoto-u.ac.jp

Koji Sugano
email: sugano@me.kyoto-u.ac.jp

Osamu Tabata
email: tabata@me.kyoto-u.ac.jp

Self-dependent Equivalent Circuit Modeling of Electrostatic Comb Transducers for Integrated MEMS

Keywords: electrostatic comb transducers, equivalent circuit, resonator, oscillation, circuit simulation

The article presents a new equivalent circuit model of electrostatic comb transducers for an integration of MEMS into LSI. The model detects the displacement using a dummy spring to express the current induced by the movement, and the model parameters can be derived from only its dimensions not from external parameters, such as acting force and applied voltage. In addition, being composed from basic circuit components, the model is easily utilized in conventional circuit simulation software. The in-plane two-degreeof-freedom comb model was applied to a simple SOI coupled resonator and the measured and simulated electrical and mechanical properties showed good agreement with each other. The model was also applied to a decoupled two-axis resonator for a vibrating gyroscope made on silicon-on-glass substrate. Frequency tuning and oscillating circuit with constant amplitude control have been tested and the tuning results and transient responses showed good agreement as well.

Introduction

In recent years, the downscaling of semiconductor devices is going to approach to the quantum limit and new technologies have been proposed for further performance improvements to extend the Moore's law to the future. Micro-electro-mechanical system (MEMS) is one of the solutions for breaking the limit by substituting circuit blocks with active and passive MEMS components, such as variable capacitors, RF filters, and switches. These components consist of mechanical, electrical, and electromechanical parts integrated with circuits.

On designing not only semiconductor devices but also MEMS, simulations are crucial for highly integrated devices and coupled analysis of electrical and mechanical domains is strongly demanded for ease of MEMS designing. Electrical equivalent circuit analysis is a good solution for this demand, since we can easily utilize existing tools for designing electronics. Mechanical structures are expressed with lumped parameter systems, such that a mass, spring, and dumper are simply converted to an inductor, capacitor, and resistor, respectively. Electro-mechanical transducers, such as piezoelectric, electrostatic, thermal, and electromagnetic have been expressed with simple transformers or controlled voltage/current sources. This substitution is valid for small signal ac analysis with a fixed dc operating point. Since the parameters of transformer are variable depending on their operating conditions, such as dc bias, force, and displacement, we need to change the circuit parameter whenever the modifying other components and it is difficult to perform transient analysis.

In this research, we focused on an electrostatic comb transducer. The electrostatic MEMS has been widely used for mechanical sensors and optical actuators and its compatibility to CMOS LSI on fabrication and operation is good. The comb (interdigitated cantilever electrodes) transducer has been widely utilized to these devices. Various models of comb transducer have been reported. Nguyen et al. reported an equivalent circuit of three port comb resonator in which the mechanical parts and transducers are described. In this model, the circuit parameters are varied with dc biases [START_REF] -C. Nguyen | An Integrated CMOS Micromechancial resonator High-Q oscillator[END_REF]. A method for composing equivalent circuit of arbitral comb transducers up to three degree of freedom has been reported to efficiently reconstruct component models using Lagrange equation [START_REF] Ayano | Electromechanical Analysis Of a Micromahicned Comb-Drive Actuator by Admittance Measurement[END_REF] [START_REF] Oiso | A proposal of gyroscope sensor using asymmetrical comb drive actuator[END_REF]. However, they also formulate the admittance after the system is decided. In these methods, the transducer characteristic is linearized at the equilibrium position balanced by connected springs to the transducer and applied force like electrostatic or external forces. Rebuilding of the equivalent circuit is required whenever the connected mechanical structure and electrical circuit are changed. To solve this problem, a new component modeling of the electromechanical transducer independent from connected system parameters is required. We proposed a new comb transducer model only depending on the dimensions of comb electrodes and physical constants.

In this article, the concept of the self-dependent model is described first, and the equivalent circuit analysis and experimental validation of two-degree-of freedom (2DOF) coupled resonator are shown. Then the frequency tuning analysis and the transient analysis of oscillating circuit for a 2DOF decoupled resonator as a vibrating gyroscope is described.

Self-Dependent Comb Transducer Model [4]

Equivalent circuit modeling of electrostatic transducer

Figure 1a shows a one-degree-of-freedom (1DOF) comb transducer model, having a uniform gap between opposing comb fingers of d, structure thickness of b, initial overlap of comb fingers of x 0 , and the number of comb fingers of n. A mechanical system of impedance Z m is connected to the movable electrode. x is a displacement of the comb transducer. The capacitance C(x) of comb fingers is given by

d x x b n x C ) ( 2 ) ( 0 + = ε , ( 1
)
where ε is the dielectric constant. The electrostatic force F along x-direction is equal to the negative derivative with respect to x of the electrostatic energy stored the capacitance, ( )

2 2 2 1 E d b n E x x C F ε = ∂ ∂ = , ( 2
)
where E is the applied voltage between opposing comb fingers. The electrical charge Q is given by ( )

E d x x b n E x C Q ) ( 2 0 + = = ε , (3)
The current i on the comb transducer is temporal differentiation of the electrical charge Q as follows ( )

dt dE x C dt dx d bE n t Q i + = ∂ ∂ = ε 2 . (4)
In conventional equivalent circuit model, as shown in Fig. 1b, these electromechanical transductions are described as a simple transformer of electro-mechanical coupling coefficient A;

d bE n E F A ε 2 = ∂ ∂ = . ( 5
)
This is simple and useful for small signal ac analysis on fixed dc bias condition. The mechanical responses are probed by the current on the mechanical impedance Z m .

c M k x x 0 d Z m M c R k 1 1:Α R ± E C(x) a) b)
Fig. 1. Simple equivalent circuit model of one-degree-of-freedom comb resonator.

Self-dependent equivalent circuit modeling of 1DOF comb transducer

The parameters in the model that is shown in Fig. 1 shall be changed when the equilibrium position of the comb fingers is changed. That is happen on changing the components in the circuit and inputs, such as dc bias voltage and applied force, since the coupling coefficient A and the capacitance C(x) depends on E and x, respectively. We need to recalculate the comb displacement x and put the parameters on the circuit, which is not convenient and makes the transient analysis difficult.

To develop a new self-dependent model, the current i on the comb transducer is described in a different expression as follows,

12 11 0 i i i t Q i + + = ∂ ∂ = , ( 6
)
dt dE C i 0 0 = , ( 7
)
vE d b n i ε 2 11 = , (8)
x x i dt dE d bx n i 0 0 12 2 = = ε , (9)
where C 0 is equal to C(0) which shows initial capacitance of comb transducer and v is the velocity of comb transducer. The current is separated into three terms. i 0 is the current on the initial capacitance C 0 . i 11 is the current generated by the motion of the comb electrodes, which is proportional to the velocity v. i 12 is the current on the changed capacitance, which is proportional to the displacement x and i 0 .

The model was designed by describing the equations 2 and 6. To express electrostatic force generated by applied voltage on the comb, a voltage source that outputs a force (voltage) proportional to square of E was adopted. For the current on the comb, the first two terms i 0 and i 11 in Eq. 6 can be described with a capacitance and a current source, respectively. The current from the source is proportional to the product of v and E, which are directly probed from the circuit. However, the third term i 12 , which represents a current caused by capacitance change proportional to the displacement x, is hard to be described, since there is no component showing the displacement of the comb. In the new model, we inserted a dummy spring k* into the mechanical circuit, which means that the spring connected between combs as shown in Fig. 2a. The spring constant k* is small enough to be neglected on response but it detects a force (voltage) on the dummy spring and the displacement x is obtained from the force. In summary, Fig. 3 shows the composed equivalent circuit.

k* x x 0 d E a) b) Z m k x * x x 0 d 1 E Z mx

Two-degree-of-freedom in-plane comb model

The self-dependent model was extended to an in-plane two-degree-of-freedom (2DOF) comb transducer, shown in Fig. 1b. The comb structure moves in-plane two directions and has asymmetrical gaps to detect and activate along gap (y) direction. The capacitance C(x, y) is

y d x x b n y d x x b n y x C + + + - + = 2 0 1 0 ) ( ) ( ) , ( ε ε , ( 10
)
where d 1 and d 2 are the gaps of asymmetric combs (d 1 <d 2 ). In this case, the displacement y is in denominator. C(x, y) was described with the Taylor series to avoid the dividing operation by the displacement y in the circuit, assuming y is small compared to the initial gaps. Then, the electrostatic forces along x (along finger) and y (gap) directions are described as;

2 2 2 1 yE X E X F x + = , ⎩ ⎨ ⎧ - = + = ) ( 2 1 ), ( 2
1 2 2 2 1 2 2 1 1 d b n d b n X d b n d b n X ε ε ε ε (11) 2 3 2 2 2 1 yE Y xE Y E Y F y + + = , ⎪ ⎪ ⎩ ⎪ ⎪ ⎨ ⎧ + = - = - = 3 2 0 3 1 0 3 2 2 2 1 2 2 2 0 2 1 0 1 ) ( 2 1 ), ( 2
1 d bx n d bx n Y x d b n d b n Y d bx n d bx n Y ε ε ε ε ε ε (12)
The current on the electrode is described as;

E v y I x I I E v y I I i y I x I i y x ) ( ) ( ) (
+ + + + + + = , ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎧ + = - = - = - = + = - = + = ) ( 2 , , 1 ) ( , 1 ) ( 3 2
n I ε ε ε ε ε ε ε ε ε ε ε ε ε ε (13)
Using eqs. 11, 12 and 13, a component model for 2DOF comb transducer was composed. The displacements x and y were detected using two dummy springs, as shown in Fig. 2b. The model is shown in Fig. 4.

The proposed equivalent circuit models can be easily implemented to circuit simulation software, since the models are described only with components provided in these software packages. In addition, the parameters of the components are determined only with the dimensions of the combs. When the comb structure has been decided, the model can be used without the modification of the parameter, even if other components both in electrical and mechanical circuits are changed.

Experiments

The 2DOF model was applied to a simple in-plane resonator fabricated on an SOI wafer. An asymmetric comb transducer is attached on the resonator mass supported with four meander springs. The structure is 20 μm thick and the springs are 5 μm wide. It moves along in-plane x and y directions. Fig. 5 shows the fabricated device and its equivalent circuit. The mechanical part of the equivalent circuit has two loops which corresponds x and y motions. The mass (inductor) parameters are common but those of the springs (capacitances) and dampers (resisters) have different values. In the electrical part, an additional capacitance was connected in parallel to comb input, which shows the parasitic capacitance through the substrate.

The measurement and simulation were performed by applying a small ac voltage (1 V) with dc bias (5, 6, and 7 V), in vacuum (~20 Pa). The electrical responses were measured using an impedance analyzer (Agilent, 4294A). The mechanical responses were measured using a stroboscopic microscope (Polytec, MSA400). The model parameters of comb transducers were derived from the dimensions in the design as shown in Table I. The ac responses of equivalent circuit were simulated using a spice software (National Instruments, MultiSim). The lumped parameters of mechanical components were fitted to the measured responses at 5 V of dc bias, while the mass was fixed to the designed value.

Frequency Responses

The measured resonant frequencies of x (along comb fingers) and y (gap direction) axis were 6.4 and 4.4 kHz, respectively. An in-plane rotation (θ z ) mode was observed at 7.2 kHz. Generally, both the mechanical and electrical responses are matched well between measurement and simulation at all the dc bias voltages, which indicates the proposed model describes the frequency responses properly. However, on the electrical measurement, the resonant peaks are not clear, especially for the x-mode, which is caused by a relatively large parasitic capacitance which dominates the impedance properties.

The mechanical and electrical frequency responses at the different dc biases near the x and θ z modes were plotted in Figs. [START_REF] Alper | A Compact Angular Rate Sensor System Using a Fully Decoupled Silicon-on-Glass MEMS Gyroscope[END_REF]. The mechanical responses in the region near x-mode of 6.4 kHz showed good agreement between the simulation and measurement, whereas those of the other region in Fig. 6a, 6c, 6e are dominated mainly by the inplane rotation mode (θ z ). The x-axis resonant frequency does not depend on the dc bias, since the electrostatic force for x-axis does not change by the x-displacement and no electrical spring effect occurs. The peak amplitude increased with the dc bias. The electrical responses were mainly dominated by parasitic capacitance and it is difficult to see the response from x-axis resonant vibration. The parasitic capacitance is from capacitance between substrate and electrode pads. parameters fitted with measured responses at E bias of 5 V agreed well with the measurements even at the different bias voltages as shown in Figs. 7c,7d, 7e and 7f. As the dc bias increased, the peak amplitude increases and the peak frequency decreases, which describe well the electrical soft spring effect of parallel plate capacitance.

Two-degree-of-freedom Decoupled Resonator

Equivalent circuit model

The comb transducer model was applied to a decoupled 2DOF in-plane resonator for analyzing frequency tuning capability and transient responses of comb resonator. In the latter analysis, dc operating point might be changed during analysis, which means the dc bias on comb transducer is not constant. Therefore it is difficult to analyze using conventional model, but the proposed model is applicable.

Single crystal silicon resonators were fabricated on a silicon-on-glass (SOG) structure. In this device, since substrate is insulating material, the parasitic capacitance that dominated electrical impedance characteristics of the SOI resonator in the previous chapter can reduce significantly. The resonators were designed as a simple vibrating gyroscope. The outer and inner frames are oscillated along x-axis using comb transducers (fix1 and fix2). Since the outer frame is movable for only x-axis and inner mass is movable for both x and y-axes, the inner frame is oscillated along y-axis caused by Coriolis force. The Coriolis vibration is detected by parallel plate capacitors (fix3 and fix4).

The comb transducers (fix1 and fix2) have a gap of 3 μm, structure height of 15 μm, and initial overlap of comb fingers of 20 μm and their capacitance are 124 fF. Fig. 9 shows the equivalent circuit of the driving structure of the resonator. Table 2 shows the lumped parameter of the resonator at the static pressure of 80 Pa which were calculated from the design, but they were adjusted to fit the measured resonance frequency (3.1 kHz) and quality factor (797).

Frequency tuning analysis

The frequency tuning of two (x and y) resonant modes are important for gyroscopes. Because of the fabrication error, it is difficult to tune only by structure designing. Therefore, electrical tuning which is described in the previous section is often used. In the present device, the parallel plate capacitors are employed at the comb attached to inner resonator. The capacitors for detecting y-axis displacement can be used for frequency tuning. The resonance frequencies of y-axis vibration at different voltages were obtained and measured. In the simulation, the electrical port corresponding to the movable electrode was biased, and ac analysis was performed. By probing the current flows on the mechanical circuits, the resonant frequencies were evaluated. The x-axis resonant frequency is 1970Hz and constant against E bias . Fig. 10 shows the y-axis resonant frequency in the bias voltage range from 9.5 to 11 V. The simulated and measured resonant frequency agreed well. At bias voltage of 11 V the measured frequency is slightly lower than Simulation, which may be caused by the non-linear response of the clamped-clamped beams of y-axis resonators.

Self-induced oscillation

In this section, power on response of comb resonator is simulated and measured [START_REF] Tokusaki | Equivalent circuit analysis of micromechanical resonator using comb transducer model with built-in displacement detection[END_REF]. We dealt with the outer frame resonator of decoupled resonator device as a simple xaxis resonator. The equivalent circuit for x-axis was simply modeled as lumped singleaxis resonator with two combs. To validate our model, all the circuit components including op-amps and special function ICs are modeled in the equivalent circuit and the measurement results and the simulation results were compared. The spice models of ICs are provided from manufacturers.

The block diagram of self-induced oscillation circuit is shown in Fig. 11 [START_REF] Alper | A Compact Angular Rate Sensor System Using a Fully Decoupled Silicon-on-Glass MEMS Gyroscope[END_REF]. The resonator has two comb transducers fix1 and fix2 for driving and sensing, respectively. The sensing comb was dc-biased at E bias . The capacitance change by the x-axis displacement generated the current, which was converted to output voltage V out using a transresistance amplifier (National Semiconductor, LF353). The output voltage is proportional to the vibration velocity. The rms voltage V a is obtained through demodulator (Analog Devices, AD630) and low pass filter (LPF) with cut off frequency of 20Hz. In order to attain constant vibration, a variable gain amplifier (VGA; Analog Devices, AD603) controls the loop gain by referring the difference between V a and dc voltage V set . The gain control range of the VGA is from -10 dB to 30dB. Finally, the output of VGA, V in , is fed back to the driving comb (fix1).

Power on transient response analysis

Transient response of the self-induced oscillation system was measured and analyzed by changing dc bias voltage E bias under V set = 173 mV at the ambient pressure of 80 Pa. V in and V out from power-on were monitored both in simulation and measurement. In simulation, transient analysis was done using the circuit simulator. Fig. 12 shows V in and V out from power-on (simulation start) at E bias 4.78V. The time from power-on to reaching V in to 80 % of the saturated amplitude (defined as a risetime). The risetime and the amplitude of the V in and V out in stable-state as a function of E bias are summarized in Fig. 13. The critical bias voltage E bias for self-induced oscillation in the measurement and analysis were 3.5 V and 4 V, respectively. The equivalent circuit analysis shows good agreement with the measured response. In addition, we confirm that the amplitude of vibration velocity can be controlled by changing V set both in the measurement and analysis.

Discussion

The lower limit of E bias for self-induced oscillation was 3.5-4 V. The closed loop gain (total gain) of the circuit is a sum of G 1 , G 2 and G 3 . G 1 is the gain of the MEMS resonator depending on E bias , driving frequency f, and damping factor r. G 2 is the transimpedance amplifier gain, 160 dB. G 3 is the gain of VGA that is changed from -10 to 16 dB. The range of G 3 is limited by V set =173 mV and positive value of V a . The total gain should be larger than 0 dB at start-up to induce oscillation. After the oscillation starts, G 3 decreases until the rms amplitude V a approached to V set . The closed-loop gain becomes 0 dB when the resonator reaches at its stable-state. The electrostatic force F at the drive comb and the sensitivity of the sensing comb is proportional to E bias . If the G 1 is lower than -176 dB at a low bias voltage, the resonator do not oscillate, since the maximum of G 2 + G 3 is 176 dB and the total gain at start-up is lower than 0 dB. Calculated G 1 at E bias 4 V is -173 dB using the parameters in Table 2, which agreed between the simulated and measured results. Fig. 14 shows the total gain G 1 + G 2 of electrostatic resonator and transimpedance amplifier. The minimum gain at which the oscillation induced is -15.2dB in the simulation, which agreed with the VGA controllable range. In the experiments, the minimum gain is slightly higher at -13dB, which may be caused by the noise from the resonator. In Fig. 12, V in and V out differed between simulation and measurement. Also in Fig. 13, the voltage at which oscillation induced was lower than the simulation, which may be caused by the offset voltages of the op-amps in the circuit. The stray capacitance in the resonator and the change in operating pressure are considered as a main reason. We assumed that the circuit has ideal and no phase shift on V out against V in at the resonance frequency. However the stray capacitance caused phase shift in the feedback loop, which resulted in driving frequency shift from the resonance. The driving frequency shift may cause a change in the device gain G 1 significantly since the resonator driven in vacuum had high Q-factor. The operating pressure also changes G

Conclusion

In this article, the self-dependent electrical equivalent circuit model of in-plane 2DOF comb transducers was proposed. The model has the dummy spring for detecting the displacement of comb, which allows us to simulate comb drive resonator without modifying the model parameter whenever the device or circuit parameter are modified. The validity of the model is proved through the simulation and measurement of both frequency response of 2DOF SOI resonator and the frequency tuning and transient response of decoupled SOG resonator. In the frequency response analysis, the effect of bias voltage on the amplitude and frequency on resonance was shown in simulation, which agreed well with the measurements. For the SOG resonator, the frequency tuning by electrostatic spring effect has successfully analyzed. In the transient analysis, the power on response was well analyzed and agreed well with the measurements. The oscillation criteria against the bias voltage were discussed using the simulation results.

Fig. 2 .Fig. 3 .

 23 Fig. 2. a) 1 DOF and b) 2DOF comb transducer with dummy springs.

Fig. 4 .

 4 Fig. 4. Equivalent circuit model of the 2DOF comb transducer

Fig. 5 .

 5 Fig. 5. In-plane 2DOF SOI resonator

Fig. 6 .

 6 Fig. 6. Mechanical (a, c, e) and electrical (b, d, f) frequency responses around x-axis resonance mode at bias voltage (a, b) 5 V, (c, d) 6 V, (e, f) 7V.

Fig. 7 .

 7 Fig. 7. Mechanical (a, c, e) and electrical (b, d, f) frequency responses around y-axis resonance mode at bias voltage (a, b) 5 V, (c, d) 6 V, (e, f) 7V.The y-axis resonant frequency decreased as the dc bias increased and the peak amplitude increased. In figs. 7, the mechanical and electrical frequency responses around y-axis resonant frequency at different dc bias voltages are plotted. The resonant frequency shift is caused by the electrostatic spring effect that is the non-linearity of force-displacement relationship. The simulation responses that are obtained with the

Fig. 8 .Fig. 9 .

 89 Fig. 8. In-plane decoupled 2DOF resonator (a) schematics and (b) fabricated device for SOG gyroscope

Fig. 10 .

 10 Fig. 10. Simulated and measured resonant frequency shift by the bias voltage.

Fig. 11 .

 11 Fig. 11. Schematic diagram of the constant amplitude and self-induced oscillating circuit with electrostatic comb resonator.

Fig. 12 .Fig. 13 .

 1213 Fig. 12. Transient response of self-induced oscillation under bias 4.78 V

Fig. 14 .

 14 Fig. 14. Simulated and measured total gain of the electrostatic resonator and transimpedance amplifier as a function of bias voltage.

  [START_REF] -C. Nguyen | An Integrated CMOS Micromechancial resonator High-Q oscillator[END_REF] , the equilibrium position of total gain = 0 dB was changed and the measured values V in and V out were changed to reach total gain at unity.

Table 1 .

 1 Parameters of the equivalent circuit

	Initial gap	d 1	3 μm
	Initial gap	d 2	5 μm
	Initial overlap	x 0	100 μm
	Structure height	b	20 μm
	The number of combs	n	45
	Mass	m	1.54×10 -8 kg
	Spring constant (x-axis)	k x	25.05 N/m
	Spring constant (y-axis)	k y	13.17 N/m
	Damping (x-axis)	r x	2.3×10 -6 Ns/m
	Damping (y-axis)	r y	37×10 -6 Ns/m
	Stray capacitance	C stray	2.45 pF

Table 2 .

 2 Lumped Parameters of Resonator

	Mass (drive-system)	m x	1.15×10 -8 kg
	Spring constant (drive-system)	k x	1.776 N/m
	Damping (drive-system)	c x	5.0×10 -7 Ns/m
	Mass (sense-system)	m y	5.549×10 -9 kg
	Spring constant (sense-system)	k y	9.38 N/m
	Damping (sense-system)	c y	1.4×10 -6 Ns/m

Acknowledgments. A part of this work was supported by the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for Young Researchers, 19676002.