Luca Maggiani

Claudio Salvadori

Matteo Petracca

Paolo Pagano

Roberto Saletti

Reconfigurable FPGA Architecture for Computer Vision Applications in Smart Camera Networks

Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In such a scenario, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely support the possibility of updating the application parameters and changing the running computer vision applications at run-time. In this respect, this paper presents a novel SCN node architecture based on a device in which a microcontroller manages all the network functionality as well as the remote configuration, while an FPGA implements all the necessary module of a full computer vision pipeline. In the paper the envisioned architecture is first detailed in general terms, then a real implementation is presented to show the feasibility and the benefits of the proposed solution. Finally, performance evaluation results prove the potential of hardware software codesign in reaching flexibility and reduced latency time.

I. INTRODUCTION

Smart Camera Networks (SCNs) is an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed systems. Indeed, in SCNs the application logic is not centralized, but spread among network nodes: every SCN node has the capability to (i) pre-process images to extract significant features, and (ii) aggregate data to understand the surrounding environment. In such a scenario a strong cooperation among nodes is necessary, as well as the possibility of having pervasive and redundant SCN devices [START_REF] Pagano | A middleware of things for supporting distributed vision applications[END_REF]. These main requirements are nowadays addressed by the research community by proposing SCN nodes based on low-complexity, low-power and lowcost devices able to exchange information through wireless communications.

In designing pervasive SCNs based on low-end devices, one of the biggest efforts is the porting (or the redefinition) of complex PC-based computer vision algorithms to embedded devices, as described in [START_REF] Salvadori | Gaussian mixture background modelling optimisation for micro-controllers[END_REF]. In the above mentioned paper a GMM-based background subtraction algorithm is implemented over a low-complexity, low-memory and low-power microcontroller while analyzing both the performance gap with respect to a state-of-the-art implementation (based on a floating point arithmetic), and its capability in performing real-time image processing (namely the capability to process images at around 25 fps) in isolation. Another important issue in the SCNs scenario is the definition and realisation of a flexible and reconfigurable node architecture able to update the application parameter and/or change the target application at run-time. In respect of such a problem, this paper proposes a camera node architecture based on a microcontroller, able to handle both the high level operations and the network communications, and an FPGA, devoted at processing complex computer vision algorithms (i.e., pixel-wise operations and/or machine learning blocks). The proposed architecture can have benefit from the high degree of parallelism that an FPGAbased solution makes available, thus permitting to optimise the algorithms at very low level (i.e., hardware level). In this sense it is possible to use the programmable logic to perform elaboration directly on the data stream, as a pixel appears at input port, and without buffering frames. This behaviour might be defined as a streaming method because the data is treated as a continuous flow of information.

Hardware programming in SCNs represents a radical different view with respect to pure software based solutions. However, nowadays no standard node architectures are available, although non-reconfigurable custom hardware based solutions targeted to specific applications have been proposed. The works of [START_REF] Negi | Deep pipelined onechip fpga implementation of a real-time image-based human detection algorithm[END_REF], [START_REF] Cao | Fast buffering for fpga implementation of vision-based object recognition systems[END_REF], [START_REF] Mizuno | Architectural study of hog feature extraction processor for real-time object detection[END_REF] and [START_REF] Martelli | Fpga-based pedestrian detection using array of covariance features[END_REF] follow this concept: the hardware is programmed from scratch in order to find an optimised solution for a specific problem. More in detail, [START_REF] Negi | Deep pipelined onechip fpga implementation of a real-time image-based human detection algorithm[END_REF], [START_REF] Cao | Fast buffering for fpga implementation of vision-based object recognition systems[END_REF] and [START_REF] Mizuno | Architectural study of hog feature extraction processor for real-time object detection[END_REF] present an implementation of the Histogram of Oriented Gradients (HOG) on streaming video flow, while [START_REF] Martelli | Fpga-based pedestrian detection using array of covariance features[END_REF] extracts aggregated features into a covariance matrix. This work aims at overcoming the state-of-the-art limits in FPGA-based SCN nodes by proposing, implementing and evaluating the performance of an innovative and reconfigurable architecture for designing computer vision pipeline inside nodes embedding FPGAs. Thus, by choosing a fixed set of hardware blocks (namely a set of computer vision algorithms able to define a certain group of consistent pipelines), our architecture permits at run-time to (i) change one block in the pipeline, (ii) instantiate a new application in parallel with another one already running, (iii) remove unused pipelines, and finally (iv) configure certain blocks with new parameters. All the above features give the possibility of creating a flexible and configurable solution without changing the whole FPGA bitstream. The paradigm that permits to implement all these feature is called hardware software codesign [START_REF] Chiodo | Hardware-software codesign of embedded systems[END_REF], and represents the state-of-the-art of the FPGA programming because merges the flexibility of software programming with the parallel computation allowed by hardware modules.

The proposed approach well fits with the Internet of Things (IoT) vision, in which each node of a global network shares a set of resources among nodes. In this direction, a given hardware block written in a generic Hardware Description Language (HDL), and instantiated inside the proposed SCN node architecture, can be abstracted as network resource and made available to other network nodes. This approach permits to see each hardware block (e.g., computer vision algorithm) as an abstract functional module, following the model-based design reasoning. Any computer vision pipeline can be easily created by connecting these blocks, thus reaching a higher level of abstraction. Although such abstract vision is similar to a model-based design approach, the proposed architecture is not affected by additional computation overheads, because each block is generated independently and the processing time strictly depends on its own optimisation level.

The rest of the paper is organized as follows. First, a detailed description of the architecture is given in Section II. In Section III an implementation performed by using the Altera Design Tools is detailed, in Section IV performance results are shown, finally Section V concludes the paper.

II. ARCHITECTURE DESCRIPTION

Every complex computer vision application can be seen as a pipeline of functional blocks. Following this view, and by using a set of hardware modules (i.e., hardware computer vision library) which implement some elaboration functions, this paper provides a reconfigurable solution able to combine pipeline items to implement different computer vision applications (e.g., tracking, recognition tasks, etc.).

The above introduced dynamic configuration is addressed in state-of-the-art approaches by using software oriented solutions. In such a vision it is straightforward to modify both configuration parameters and applications at run-time, at the cost of avoiding possible low-level optimizations. Instead, the use of a pure hardware based approach results in the realization of static and monolithic hardware pipelines optimized only for a single application. To overcome the above depicted limitations, while keeping the possibility of dynamic configuration, in this work we present a mixed solution, which takes advantages from hardware optimisation and still considers a software-based configuration. Along this line, we propose a microcontroller and a re-configurable FPGA architecture controlled by a SoftCore. This platform is designed to become the basement for a broad range of computer vision applications by allowing the configuration of computer vision pipelines at runtime.

A. Architecture of a SCN node

The proposed SCN node is mainly based on a microcontroller and an FPGA. The former is in charge of all network communications (i.e., data transmission and feature sharing among nodes), moreover it plays the role of high level controller able to manage remote configuration requests. The latter implements the reconfigurable hardware pipeline. This hybrid structure allows to speed-up the elaboration performance with respect to pure software oriented solutions, while keeping the possibility of a remote configuration.

The proposed SCN node architecture is depicted in Figure 1, where it has been reported the high level architectural view of the node, as well as a more detailed representation in which the FPGA communicates with software components run by the microcontroller. The dual layer structure realises a separation between the computer vision heavy processing operations, performed by the FPGA, and the remote node interface, represented by the software abstraction into the microcontroller. In the FPGA, reconfigurable hardware modules that perform optimised pixel elaborations are implemented, as well as a SoftCore in charge of controlling modules parameters and the whole computer vision pipeline. The microcontroller, instead, gives a high level abstraction of the whole system by providing network based interfaces to control configuration parameters of elementary blocks, pipeline composition, and data transmission. Where IoT compliant SCN nodes are necessary, the microcontroller provides an additional abstraction of the system through a middleware solution, thus permitting to show all the internal FPGA modules as resources for other network devices.

B. Internal FPGA architecture

The proposed FPGA architecture called Camera OneFrame,is detailed in Figure 2. It permits to create a full reconfigurable pipeline in a SCN node. The whole architecture is designed focusing on interconnection modules, called RouteMatrix, and functional blocks, called Elab. The former realises the connections between the functional blocks, while the latter implement basic computer vision algorithms that can be part of a specific elaboration pipeline tunable at run-time. In the left side of the figure four video input ports, labeled as VideoStream are shown. This architecture allows to have a multi-camera video inputs that can be parallel processed as a continuous pixel flow. The data flow, composed by one or more video streams, is captured and then processed by successive steps, represented by Elab blocks. In this respect, the captured flow has not an associated semantic, so that an user interacting with a configuration manager can select and compose the appropriate modules suited to the desired application. For instance, through the IoT middleware the desired pipeline can be remotely selected. Every parameter of each Elab block in the architecture as well as the connection among the blocks are managed by the SoftCore created into the FPGA.

The described internal FPGA structure can be expanded as a function of a set of possible applications. Indeed, the number of input and output ports, even the number of elaboration steps can be abstracted as parameters and then configured during the hardware compilation. This allows to modify the number of the parallel data flow, the amount of pipeline steps, or the elaboration blocks, without modifying the HDL instances, but easily inserting them as a new Elab instance using for example a graphic interface tool.

An image processing application has to be divided into functional blocks, algorithm steps, to unveil the internal datapath requested. Each functional block performs an associated algorithm, implemented by a hardware module available into a Hardware Library tool. This library contains a certain amount of functional blocks, defined using HDL, and then collected into a package made available as high level resource. After the instantiation phase, the system is ready to be compiled and programmed in the FPGA as a bitstream. Afterward, though the FPGA bitstream is statically programmed, the system still keeps the flexibility through the software configuration of blocks and connections. This leads to a dynamic and adaptive system, but optimised at the same time, because of the software re-configuration.

The proposed internal FPGA architecture introduces two degrees of freedom: (i) it is possible to grab the requested functional operation from a library, without any knowledge of HDL languages as it was in a model-based unit, and (ii) it is possible to configure the system at run-time to perform new pipelines with the already installed hardware modules configured and connected through the SoftCore.

C. RouteMatrix module

RouteMatrix is the core of the internal FPGA architecture: it is the connection point between hardware configuration and software programming. The logic behind our approach can be seen as a 3D-multiplexer, having a N ∈ N inputs and M ∈ N outputs (Figure 3), and configured by a N ×M matrix through a dedicated bus (the red lines in Figure 3). In this way, the RouteMatrix internal logic guarantees that each output is connected to a selected m-th input vector (with m ∈ [1, M ]), to avoid data collision. On the other side every input vector can be connected to several outputs, in order to generate two or more twin sub-pipelines from the same source. More in details, the RouteMatrix module permits to:

• define the routing path of a data stream (Figure 4a); • handle the execution of parallel pipelines with different data sources (Figure 4b); • split a data stream in two or more pipelines (Figure 4c).

D. Elab module

In this paper we define a hardware block as the implementation of a certain computer vision algorithm in any HDL language (e.g., Verilog, VHDL, CAPH [START_REF] Serot | Implementing stream-processing applications on fpgas: A dsl-based approach[END_REF]). Every block requires at least one input and one output with the related data-valid signals, that notify the validity of the data to the following blocks. The data-valid signals are necessary for enabling the streaming paradigm: in this direction the proposed architecture does not require to specify any data latency and processing time. Finally, the proposed architecture provides a dedicated bus for managing the FPGA region mapped as internal memory of the system. Such a memory can be directly addressed by the SoftCore for elaboration blocks configuration purposes.

III. IMPLEMENTATION

As described in the previous sections, the SCN architecture is based on a microcontroller and a FPGA: the former is in charge of managing the network communication and acts as high level resource controller, while the latter performs heavy processing operations by providing a reconfigurable internal architecture. To really evaluate the benefits of such architecture a real implementation has been performed by using two commercial off the shelf boards: the SeedEye [START_REF]Scuola Superiore Sant'Anna and Evidence s.r.l[END_REF] and the Terasic DE0-nano [START_REF]DE0-nano[END_REF].

The SeedEye board is an advanced device, specially targeted to wireless sensor networks, based on PIC32MX795F512L @80MHz provided by Microchip [START_REF]PIC32MX3XX/4XX Family Data Sheet[END_REF] and embeds: a wireless transceiver compliant with the IEEE802.15.4 standard, an IEEE802.3 interface and an USB interface. As discussed in [START_REF] Pagano | A middleware of things for supporting distributed vision applications[END_REF], this board is a state-of-the-art solution for IoT networks, providing enough memory and computational resources to execute both IoT protocols and complex middleware solutions performing distributed applications.

The Terasic DE0-nano board embeds an Altera Cyclone IV FPGA, with 22000 Logic Elements (LE), 600 Kbits of on-board memory and 144 9x9 bits DSP modules. In such FPGA we included an Altera NIOSII SoftCore as data flow controller embedded into the elaboration logic and connected to the Elab and RouteMatrix blocks by using an internal bus, called Avalon Memory Mapped (or Avalon-MM). As described in Section I, this approach permits to have a greater flexibility with respect to a pure hardware based solution. In fact, every elaboration block can be mapped on the Avalon-MM bus to be addressed from the NIOSII as a standard memory location. This main feature allow us to: (i) set up the block interconnection at run-time, using some dedicated registers in the RouteMatrix instances, and (ii) control the elaboration parameters for every block inserted into the elaboration pipeline.

A. Hardware library

The Camera OneFrame architecture allows a user to instantiate hardware elaboration blocks without modifying their internal HDL behaviour. This result is realized according to the model-based design view as a consequence of the hardware abstraction. To the end of validating this claim a minimal HDL library has been developed. The library implements the following functions: (i) the VideoSampler, which realises the CMOS camera interface; (ii) RemoteImg, which performs a serial acquisition of an image from an UART link; (iii) GradientHW, that implements a spatial gradient extraction, and (iv) HistogramHW, which extracts the histogram of an image divided in cells of a configurable size (as used in the HOG algorithm [START_REF] Dalal | Histograms of oriented gradients for human detection[END_REF]). Each block optimises a specific function by exploiting the advantages given by the hardware parallelism and the internal DSP modules embedded into the FPGA. Moreover, a complete run-time reconfiguration of all block parameters is allowed through a connection with the Avalon-MM bus. In Table I the FPGA occupancy of every block is described in terms of LE, on-chip RAM, and DSP elements by considering the EP4CE22 FPGA embedded on the Terasic DE0-nano board.

All the developed hardware library functions are compliant with the SoPC Builder [START_REF] Altera | SoPC Builder User Guide[END_REF] tool provided by Altera as a part of the Quartus II software edition [START_REF] Altera | Quartus II Software[END_REF]. SoPC Builder abstracts every HDL module as a functional entity into a graphical interface, thus helping its instantiation in the proposed architecture. In Figure 5 the design flow for a generic computer vision application is shown using the SoPC Builder tool: (i) the application is chosen (ii) and divided into functional elements; then (iii) the specific HDL blocks are instantiated using the above mentioned tool, and finally (iv) the code is compiled into a bitstream.

IV. EVALUATION AND RESULTS

In this section the performance of the proposed architecture is evaluated in terms of data output latency. Particularly, we propose a suite of test cases aimed at validating all the claims described in the previous sections by using the modules presented in Section III. More in detail, in the test cases (shown in Figure 6) the following modules have been instantiated: two VideoSampler, three GradientHW, a HistogramHW, three RouteMatrix instances and finally a NIOSII SoftCore. In this scenario the proposed architecture permits to generate several combinations of the considered blocks, thus performing a set of applications fitting inside a rather small FPGA size. In fact, considering the occupancy data reported in Table I, and considering the additional overhead due to the NIOSII SoftCore and the Avalon-MM bus, the whole bitstream occupies only 31% of the LE, the 38% of on-chip memory and the 51% of the 9x9 DSP modules. The all possible cases of the test suite are reported in Figure 6, where it is shown that the proposed architecture can: (i) handle a single pipeline (Figure 6a), (ii) handle two parallel pipelines using two cameras (Figure 6b) and (iii) split a data stream to follow two pipelines (Fig. 6c).

In order to evaluate the output latency of each pipeline, the time latency of each architecture block is shown in Table II in terms of FPGA clock cycles. These values measure the amount of clock cycles needed by data to flow inside each block, considering that they are implemented according to the streaming paradigm, without buffering a whole image. As reported in the table above, every module has a constant data delay, as a consequence of the hardware realisation based on the HDL description. More in detail, the VideoSampler and RemoteImage modules do not introduce any latency time, because they do not perform any elaboration, but only manage clock speed conversions. The GradientHW, instead, introduces a latency time 2 clock cycles. The largest latency values are related to the HistogramHW module, that introduces a latency dependent on image size and cell size: in the contingent case, using 8x8 pixels cells and Q-VGA images, it is of 2560 clock cycles. The last implemented block, RouteMatrix, only introduces a latency of 1 clock cycle.

The overall system performance in time delay can be evaluated as sum of the latencies of the modules inserted into a specific pipeline plus the one introduced by the architecture structure elements (namely the RouteMatrix), as shown in the following equation: where L B i is the latency of the i-th elaboration block, L RM the latency of RouteMatrix, M the number of RouteMatrix iterations, and N the depth of the considered pipeline.

L total = N -1 i=0 L B i + M • L RM (1)
The latency time value in number of clock cycles can be easily converted in time delay by defining the frequency of the FPGA master clock. In our design, all the system runs at a frequency of 50MHz, thus the values of Table II can be expressed as delay time by multiplying them for the clock period (in this case 40ns). Table III shows the delays for all the test cases depicted in Figure 6. For all the performed experiments the latency in terms of clock cycles and delay time is evaluated following the rule described in Equation 1.

V. CONCLUSIONS

In this paper, we present an innovative architecture concept for a smart camera network node. By leveraging the hardware software codesign concept we propose a hybrid SCN node composed by a microcontroller and a reconfigurable FPGA architecture controlled by an internal SoftCore. Concerning the FPGA architecture, it represents a flexible and reconfigurable solution into a static FPGA bitstream. The flexibility and the reconfigurability is enabled by providing the possibility of composing computer vision pipelines as well as configuring the elaboration block parameters. Moreover, in the proposed design the computer vision algorithms are realized with modules of an HDL library, thus helping programmers in the development of IoT based applications leveraging computer vision capabilities.

In the paper the proposed architecture is first presented by detailing the internal reconfigurable FPGA architecture. Then, a real implementation on commercial off the shelf devices is discussed in respect to three possible applications based on a three stage pipeline. Finally, performance evaluation results are presented in terms of latency time and FPGA occupancy. Results show that the high level abstraction realised by the architecture does not decrease the elaboration performance, indeed shows a constant output latency and an optimized solution, compared to a pure-software application.

Figure 1 :

 1 Figure 1: Proposed smart camera network node.

Figure 2 :

 2 Figure 2: Camera OneFrame architecture.

Figure 3 :

 3 Figure 3: RouteMatrix internal architecture.

  (a) Single pipeline. (b) Parallel pipelines. (c) Pipeline splitting.

Figure 4 :

 4 Figure 4: RouteMatrix functionality.

Figure 5 :

 5 Figure 5: Example of the architecture design flow.

(a) Test 1 :

 1 handling a single pipeline. (b) Test 2: handling two pipelines. (c) Test 3: split a data stream to follow two pipelines.

Figure 6 :

 6 Figure 6: Test cases.

Table I :

 I Hardware library occupancy.

		Logic	RAM footprint	DSP
		elements	(Bytes)	(9x9 bit)
	VideoSampler	200 (0,9%)	512	0
	RemoteImage	200 (0,9%)	1	0
	GradientHW	1200 (5,4%)	640	32
	HistogramHW	850 (4,0%)	16384	0
	RouteMatrix (x1)	400 (1,8%)	40	0

Table II :

 II Hardware module processing latency.

		Latency
		(clock cycles)
	VideoSampler	0
	RemoteImage	0
	GradientHW	2
	HistogramHW	2560
	RouteMatrix	1

Table III :

 III Tests case results.

		Latency (clock cycles)	Time (µs)
		Out 0	Out 1	Out 0	Out 1
	Test 1	2565	-	102,600	-
	Test 2	2565	9	102,600	0,360
	Test 3	2565	9	102,600	0,360


Luca Maggiani

Claudio Salvadori

Matteo Petracca

Paolo Pagano

Roberto Saletti

Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based Smart Camera

The design and development of distributed innovative services leveraging pervasive smart camera network solutions requires the use of reconfigurable low-cost smart cameras. In this respect, FPGA based Smart Cameras enabled to wireless communication that follow the Internet of things paradigm are a promising solution. The paper proposes an optimized design of the histogram extractor algorithm targeted to low-complexity and low-cost FPGA based Smart Cameras. The proposed solution is the basis for a wide range of distributed computer vision applications. We first define a general architecture for the image histogram core, then we evaluate its performance with a real implementation.

I. INTRODUCTION

Smart Camera Network (SCN) is the natural evolution of state-of-the-art centralized computer vision applications towards distributed and pervasive systems. Differently from Wireless Sensor Networks (WSNs) which generally perform basic sensing tasks, SCNs consist of autonomous devices, Smart Cameras (SCs), performing on-board image processing algorithms strongly optimized to fit to the limited amount of available resources [START_REF] Rinner | The evolution from single to pervasive smart cameras[END_REF].

One of the biggest efforts in designing pervasive SCNs based on low-end devices is the porting of complex, and computational intensive, computer vision algorithms to resource constrained embedded devices. For instance, an optimized/approximated version of Gaussian Mixture Model (GMM) is proposed in [START_REF] Salvadori | Gaussian mixture background modelling optimisation for micro-controllers[END_REF], with the goal of a real instantiation in low-complexity micro-controllers lacking Floating Point Unit (FPU). Although the authors proved that a microcontroller can reach real-time performance in performing GMM-based tasks, the limits of such CPU-based solution in performing heavy computer vision tasks have been outlined. An innovative architecture for smart cameras acting as nodes of a network following the Internet of Things (IoT) paradigm has been proposed in [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF], to overcome the computational limits in the SCs design. In such a work, a visual IoT node (i.e., IoT smart camera) consists of a micro-controller and an FPGA. The former is in charge of managing the network communications and the high-level organization of the computer vision pipeline. The latter handles the heavy processing operations (i.e., pixelwise or machine learning algorithms) according to the streaming paradigm (data are processed directly when they appear at the input port without any buffering stages). A key feature of the proposed SC architecture is a flexible and reconfigurable FPGA internal structure, managed by a SoftCore through the CPU data bus.

A challenging computer-vision algorithm to be ported to FPGA-based smart cameras is the Histogram of Oriented Gradient (HOG) [START_REF] Dalal | Histograms of oriented gradients for human detection[END_REF]. The algorithm basically extracts image features by deploying a histogram of the pixel edge directions, with the aim of identifying pedestrians in the scene. Even though the histogram software implementation is a simple task used in several light-weight detection algorithms [START_REF] Chowdhury | Fast scene change detection based histogram[END_REF], [START_REF] Hasanzadeh | Motion detection using differential histogram equalization[END_REF], the hardware realization of such algorithm in not a trivial task. A possible hardware oriented histogram extractor has been proposed in [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF], [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF]. The data dependency issues are directly managed at the hardware level in these cases, by deploying a linear pipeline elaboration cell. On one side this approach has the advantage of processing multiple data in a single clock cycle, on the other side it represents a dedicated solution designed to process buffered data. This paper proposes an optimized design of the histogram extractor algorithm targeted to low-complexity and low-cost SCs node based on a mid-range FPGA. This histogram core can work with a continuous input data flow, thus following the streaming paradigm. As pointed out in [START_REF] Guthier | Parallel algorithms for histogram-based image registration[END_REF], parallel histogram computation requires a complete algorithm redesign. In this context, our work removes the memory access conflicts from the histogram computation, leading to more flexible and efficient ways to exploit parallelism. This solution reaches better performance with respect to the state-of-the-art solutions, while being fully compatible with the reconfigurable SC architecture proposed in [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF]. More in detail, we first define a general architecture for the image histogram core in this paper, then we evaluate its performance in terms of FPGA resource occupancy, memory footprint and latency.

The rest of the paper is organized as follows. A detailed description of the methodology followed to design the histogram core is given in Sec. II. The implementation details and the performance results are shown in Sec. III. Conclusions are finally highlighted in Sec. IV.

II. METHODOLOGY

As briefly introduced in Sec. I, the realization of a histogram core is a challenging task, and requires a complete algorithm re-design with respect to a software-oriented solution. Indeed, in low-complexity FPGA-based SCs performing real-time image processing a high degree of parallelism is necessary to process data directly when they appear at the input port, in order to minimize the output latency. Moreover, the proposed histogram core has to be both reconfigurable and integrated with other blocks, to satisfy the requirements of an IoT oriented design compliant with the architecture shown in [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF]. Following these main requirements, the proposed histogram core can be seen as a black-box with two inputs, the data-stream and the data-valid signals (to trigger a new data acquisition), and one output, the histogram stream to be stored into the memory. Moreover, as proposed in [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF], the block is connected to the CPU data bus, thus enabling a direct communication with the SoftCore in charge of managing the reconfiguration tasks.

In general, a simple histogram computation core can be represented according to the diagram depicted in Fig. 1. In this configuration each pixel updates the value of the corresponding histogram bin by performing a read-modifywrite operation. The whole operation requires four clock cycles per pixel. Thus, if the first pixel appears as input at time T 0 , the complete histogram is available as output at the instant

T 0 + 4 • N p • T p = T 0 + 4 • T f ,
where N p is the number of pixels of the whole image, T p is the pixel period, and T f the frame period. The above described histogram evaluation method is not based on a streaming paradigm, since the processing of a new pixel requires the completion of the previous pixel, and strongly limits the development of real-time image processing applications.

We propose a new circuit based on the module depicted in Fig. 2 and called histogram-subcell, to reduce the computational time for evaluating the image histogram. This block is essentially composed by a dual-port RAM memory array, which has the same size of the histogram, and a Finite State Machine (FSM), which controls the data flow. By deploying a dual-port RAM module, the system can jointly execute read and write operations in the same clock cycle. At the same time, the internal FSM (subcell FSM in Fig. 2) controls the elaboration as a sequence of pipeline operations (reported in Fig. 3): READ, LOAD, ADD, and WRITE. When a pixel comes to the input port, a data valid signal is enabled and the internal FSM starts a new elaboration cycle. In the READ state the circuit reads the bin addressed by the current pixel value and then stores the bin content in a register during the LOAD state. In the ADD state, the bin value is updated by an incremental operation and finally the memory array is updated with the new value during the WRITE state. The transitions occur every clock cycle.

Though the designed pipeline architecture supports the streaming paradigm (every FSM state needs only one clock cycle to be executed), it introduces a memory access conflict to be solved. Indeed, the above described FSM does not provide an atomic read-modify-write operation. As matter of example, suppose that the i-th bin is addressed at time T 0 , and that the same bin is required at the following data-valid signal, at time T 1 (= T 0 + 1). The memory content in T 1 is not consistent because the previous elaboration phase is not completed and the bin value is not updated. A FSM-controlled parallel architecture called Histogram cell is proposed to address the above described issue. Since the histogram-subcell circuit requires four clock cycles to complete the read-modify-write iterations, we deploy four histogram-subcell instances to handle groups of four consecutive pixels as parallel flows.

The module computes four different sub-histogram data structure for the same image, where the j-th pixel updates the (j mod 4)-th histogram-subcell instance. Splitting the pixel operation in parallel processing flows prevents memory access conflicts, because each histogram-subcell instance is not considered until the previous operation has been completed (i.e., four clock cycles). The Histogram cell behavior is shown in Fig. 5.

When an image is completely acquired, the four sub- histograms has to be merged into the complete histogram. The final histogram can be obtained by using a final adder stage to sum the sub-histogram memory cells each other (i.e., the subhistogram bin) sequentially: this last hardware block introduces a latency of N + 2 clock cycles, where N is the number of bins. The Histogram core block diagram is depicted in Fig. 6. By considering the latency introduced by each block of the Histogram core, the overall latency L total (after the arrival of the last image pixel) can be evaluated as:

L total = N + 6
(1) The total latency depends on the number of bins plus 6 clock cycles (4 for the FSM plus 2 for the final adder stage). The histogram is completed after the adder stage and is eventually stored in memory.

Advantages with respect to the state-of-the-art solutions [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF], [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF] are hereby pointed out. First, this design permits an on-line re-configuration of the number of bins, giving the possibility of having histograms with different resolutions. Moreover, the streaming paradigm is realized using a single clock source, thus permitting to run the system at the maximum allowable frequency, unlike state-of-the-art solutions in which a second faster clock source is used for the FSMs [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF], [START_REF] Garcia | Implementing a histogram for image processing applications[END_REF].

The final Histogram core reported in Fig. 6 is the basis for successfully evaluating image histograms. Because of the streaming paradigm, the system has to be able to manage a continuous pixel flow, thus being able to handle multiple consecutive images. Considering the total latency of the Histogram core, the circuit is capable to process an image in a period equal to T f + L total , where T f is the frame period (see the time diagram in Fig. 7). The Histogram core cannot consider a new image until the previous one is completely processed, thus limiting again the real-time capabilities of the system. To avoid this problem it is possible to duplicate the histogram core

III. PERFORMANCE EVALUATION

The proposed histogram core has been first tested on a cycle accurate Verilog simulator [START_REF] Modelsim | ModelSim HDL simulator[END_REF], then it has been synthesized on a mid-range FPGA. We adopted the Terasic DE0-nano development board [START_REF]DE0-nano[END_REF] which embeds an Altera Cyclone IV FPGA with 22k Logic Elements (LE), 600 kbits on-board memory, and 144 9x9 bits DSP modules for the final implementation. A 1.3MPixels Omnivision CMOS Camera [START_REF]OV9650 datasheet[END_REF] was used as a real video source.

A. Algorithm footprint

As previously described, the proposed solution has the capability to re-configure at run-time the number of bins N , after having fixed at compilation-time the allocated memory M (in bits) and the bin resolution R (in bits). It is possible to vary N under according to the following equation:

N ≤ M/8 R (2)
where the factor 8 derives from the instantiation of 8 histogram subcells (in Fig. 2) in the definition of the Histogram core of Figs. 4 and8. For instance, considering to allocate a memory array of 65536 bits (i.e., 8192 Bytes) and to set a resolution of 32 bits, it is possible to configure the core for a histogram with a maximum of 256 levels.

To keep a memory constrained design, the circuit has to be carefully sized especially in terms of the amount of the instantiated memory. Thus in the scenario of [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF], let us suppose to have K histogram-based algorithms, such that each one requires a number of bins equal to N i , with i ∈ {1...K}. The memory to be instantiated at compilation-time equals to:

M = 8 • M AX(N i ) • R.
(3) B. Timing

As described in Eq. 1, the latency introduced by the Histogram core of Fig. 6 directly depends on the number of bins. The latencies introduced by the above mentioned core are detailed in Tab. I as a function of the number of bins N . It must be pointed out as the total latency is completely independent of the image resolution expressed as number of pixels. By considering the final implementation histogram core design, which uses only 4% of the Altera Cyclone IV resources, and a clock frequency of 100 MHz, a VGA video stream can be processed at a rate of 260 frame per seconds.

C. Performance comparison with state-of-the-art

In this subsection the streaming based approach proposed in the paper is compared with respect to two state-of-the-art solutions. More in detail, the comparison is with [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF], where a histogram is implemented making use of a linear array of bincells in which the computation proceeds in a pipelined fashion. We also compared our approach with [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF], where the same approach of [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF] is optimized using the C-slow retiming technique, thus reducing the critical path delay into the feedback loops, and improving the execution frequency. Both the considered solutions have been implemented in consumer Xilinx FPGAs.

Tab. II shows the allowed working frequency and the number of Logic Elements (LEs) used in each implementation. As far as system frequency is concerned, the proposed work, implemented in the Altera Cyclone IV EP4CE22 FPGA, is capable to process histograms with a maximum system clock over 100 MHz. The comparison in number of LEs between different chip vendors has been done by making use of the converter in [START_REF] Altera | Device comparison[END_REF]. The proposed work overcomes the state-ofthe-art solutions with at least a factor 2, in terms of FPGA resource occupancy.

Moreover, the memory footprint and the latency are compared in Tab. III. Although the proposed work uses a bigger amount of memory with respect to [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF], its memory footprint is half of the implementation proposed in [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF]. However, for a fair comparison, it should also be taken into account the

[#] System as in [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF] 144 2422 System as in [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF] 238 ≈ 4800 Proposed solution > 100 850

Table II: Allowed frequency and LEs occupancy comparison.

reconfigurability feature of the proposed solution. Both of the considered state-of-the-art works are not reconfigurable because of their architectural design, while the proposed approach can extract histograms with a configurable number of bins up to N . Finally, the latency of the proposed solution is lower than the compared works for all N > 6. In fact, both compared techniques have to wait N clock cycles to end the processing of the last pixel, and additional N clock cycles to empty the histogram structure.

Memory Latency [bits]

[clock cycles] Realization in [START_REF] Cadenas | Parallel pipelined array architectures for real-time histogram computation in consumer devices[END_REF] N × R 2N Realization in [START_REF] Cadenas | C-slow retimed parallel histogram architectures for consumer imaging devices[END_REF]

8 × N × R 2N Proposed solution 4 × N × R N + 6
Table III: Memory footprint and latency comparison.

IV. CONCLUSION A reconfigurable parallel histogram core for real-time image processing in FPGA based low-cost smart cameras is presented in this paper. The main feature of the proposed core is the ability of working according to the streaming paradigm, while providing a full compatibility with the reconfigurable SC architecture presented in [START_REF] Maggiani | Reconfigurable fpga architecture for computer vision applications in smart camera networks[END_REF]. The core performance, obtained through a real implementation in the Altera Cyclone IV chip, shows the benefits of the proposed solution in terms of working frequency, LEs occupancy, and required memory, with respect to state-of-the-art solutions. The final implementation of the histogram core is able to process a 260 frame per seconds VGA video stream, thus enabling a wide range of applications in the smart camera networks scenario.

Figure 1 :

 1 Figure 1: Typical histogram computation block.

Figure 2 :

 2 Figure 2: Histogram-subcell module.

Figure 3 :

 3 Figure 3: Histogram-subcell FSM.

Figure 4 :

 4 Figure 4: Histogram cell.

Figure 5 :

 5 Figure 5: Streaming pixel flow.

Figure 6 :

 6 Figure 6: Histogram core.

Figure 7 :

 7 Figure 7: Time diagram.

Figure 8 :

 8 Figure 8: Standard image histogram core scheme.

Table I :

 I Histogram core latencies as a function of N .

	N	Latency
	(#bins) (Clock cycles)
	8	14
	16	22
	32	38
	256	262


Amel Ghouali

Tewfik Sari

Jérome Harmand

Maximizing biogas

Keywords: optimal control, bioreactor, maximization, biogas, anaerobic digestion

published or not. The documents may come

Introduction

Anaerobic digestion or methanization is a biological process in which organic compounds are transformed into carbon dioxide and methane (biogas) by micro organisms. These processes represent a promising technology for treating liquid and solid waste while producing valuable energy and limiting the greenhouse [START_REF] Rehl | Müller CO2 abatement costs of greenhouse gas (GHG) mitigation by different biogas conversion pathways[END_REF]. The operation of such process poses however a number of practical problems since anaerobic digestion is a complex nonlinear system which is known to be unstable : an organic overload can destabilize the biological process and its restart needs long delays (over months). It is thus necessary to develop automatic systems to optimally manage such a process when dealing with disturbances or to optimize important steps as its operation during the starting period.

Schematically, there are two families of automatic controllers developed for such purpose : model-and knowledge-based approaches. The first refer to the synthesis and the application of automatic control laws when a model of the system is available. Most of such controllers have been proposed by people from the automatic control community. They include approaches based on both linear or nonlinear techniques. Their main advantage lie in their theoretical properties they are suppose to guarantee such as performance or stability robustness with respect to uncertainty or disturbances. For instance, the controllers proposed by [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF] are part of this family. The second class of approaches -called here knowledge-based -include approaches -not only but rather -developed by experts of the anaerobic digestion (biotechnologists, chemical engineers) who proposed control methods based on the detailed practical knowledge they have about bioprocess dynamics. They are most often validated on real processes than model-based controllers and are usually based on easily accessible measurements usually available in an industrial context such as pH, gas flow rates, H2 concentration, partial or total alkalinity... Approaches by [START_REF] Liu | Extremum-seeking with variable gain control for intensifying biogas production in anaerobic fermentation[END_REF], [START_REF] Rodryguez | A hydrogen-based variable-gain controller for anaerobic digestion processes[END_REF] or [START_REF] Steyer | Advanced control of anaerobic digestion processes throug disturbances modeling[END_REF] can be classified in this family. The counterpart of the fact they are easily applicable on real processes is that no theoretical guarantee with respect to performance can be given since no model is necessary to synthesize the controller. Steyer et al., 1999 [20] proposed the 'Disturbances Monitoring' principle as a way to control highly loaded anaerobic processes. This strategy is based on the following idea : a known overload is first applied voluntary to the process. The analysis of the system's response allows one to decide whether the system is able to deal with an increase in the pollutant load or not. If it is the case, the feeding flow undergoes a step while it remains at its actual value or is decreased otherwise. Once the new equilibrium has been reached, a new load test is applied and so on. In their paper, the authors claim that 'the control law allows to reach automatically the maximum treatment ability of the anaerobic process whatever the input concentration in organic matter is' without being able to prove it because their control law is completely heuristic. If we define the maximum treatment ability of an anaerobic system as the maximum biogas flow rate it can deliver over a given period of time, and if we consider a model of the process, we face an optimal control problem that can be posed from a mathematical viewpoint. To do so, we need a model of the anaero-bic digestion process. The anaerobic process involves thousands of microorganisms interacting together through a complex metabolic network which is, actually, only partially known. On the one hand, even if several synthetic functional models have recently been proposed, including high dimensional ones like the ADM1 (cf. [START_REF]IWA Task Group for Mathematical Modeling of Anaerobic Digestion Processes[END_REF]), but also more simplified ones like the AM2 (cf. [START_REF] Bernard | Dynamical model developpement and parameter identification for anaerobic wastwater treatment processl[END_REF]), it is to be noticed that the nonlinear character of biological models and their relatively high dimension (the AM2 is of dimension 4 in its simplest form) render their use inappropriate for the application of optimal control theory. On the other hand, it has been shown that under some circumstances, very simple models were able to adequately capture the main dynamical behavior of the anaerobic model [START_REF] García-Diéguez | Reducing the Anaerobic Digestion Model No. 1 for its application to an industrial wastewater treatment plant treating winery effluent wastewater[END_REF].

The use of such a simplified model is not new and several authors have already proposed to use it for optimal control design of anaerobic digesters (cf. for instance [START_REF] Stamatelatou | Optimal and suboptimal control of anaerobic digesters[END_REF]). From the seminal work by D'Ans and al. ( [START_REF] D'ans | Time-Optimal Control for a Model of Bacterial Growth[END_REF]) who established the bang-bang character of a simple optimal-time control problem of the chemostat, the optimal control of bioprocesses in general, and of the anaerobic digestion in particular, has been studied over a quite long time. More particulary, an optimal control policy to avoid the failure in the digester operation and restore its normal operation or lead it to a new optimal steady state was proposed by Stamatelatou and al. [START_REF] Stamatelatou | Optimal and suboptimal control of anaerobic digesters[END_REF]. It has been designed using a simplified model of anaerobic digestion to determine the optimal dilution rate as a function of time, in response to entry of inhibitors or sudden changes in the feed substrate concentration. The authors shown that there is a proportional relationship between the dilution rate and the methane production. A simpler and implementable suboptimal control law was derived by Dimitrova and Krastanov to stabilize in real time a dynamic model towards the maximum methane flow rate [START_REF] Dimitrova | Nonlinear adaptative stabilizing control of an anaerobic digestion model with unknown kinetics[END_REF]. Their approach is however not model-based : the algorithm is presented in the form of a block-scheme to iteratively adjust the dilution rate to drive the process dynamics towards a set point, where an optimal value of the output is achieved. The main limitation in applying this approach is that the dynamics should be open-loop stable. Otherwise, a locally stabilizing controller is necessary to stabilize the equilibrium points around the optimal operating point [START_REF] Dimitrova | Nonlinear adaptative stabilizing control of an anaerobic digestion model with unknown kinetics[END_REF]. Other extensions were derived by the same authors [START_REF] Dimitrova | Nonlinear stabilizing control of an uncertain bioprocess[END_REF][START_REF] Dimitrova | Nonlinear adaptive control of a model of an uncertain fermentation process[END_REF]. Sbarciog et al. [START_REF] Sbarciog | On the optimisation of Biogas Production in Anaerobic Digestion Systems[END_REF][START_REF] Sbarciog | An Optimizing startup strategy for a biomethanor[END_REF] have proposed a control strategy for maximizing biogas production of an anaerobic digestion system modeled by a 2-order system. The control law was synthesized by solving two optimization problems : firstly, a static optimization problem to determine the optimal operating point and, secondly, a transient optimization problem using the maximum principle of Pontryagin to find the control which will drive the system from an initial condition towards the optimal operating point while maximizing the gas flowrate. Recently, considering other sets of measurements, Sbarciog et al. [START_REF] Sbarciog | A biogas-Based Switching Control Policy for Anaerobic Digestion Systems[END_REF] proposed a simple switching strategy for optimizing anaerobic digestion process. In [START_REF] Stamatelatou | Optimal and suboptimal control of anaerobic digesters[END_REF], the problem of maximizing the biogas production over a given period of time has been investigated considering different possible disturbances (presence of an inhibitor or over/under-loads). The singular arcs were calculated using the Maximum Principle of Pontryagin. However, the optimal control synthesis was not given explicitly and no controllability analysis was performed.

In the present work, considering i) a simple model of a chemostat (see equations (1) below), ii) a restricted set of initial conditions (see Hypothesis 2 below) iii) assuming the biogas produced is a linear function of the activity defined as kµ(s)x as proposed in [START_REF] Bastin | On-line Estimation and Adaptative Control of Bioreactors[END_REF] (see section ( 2)), we solve the problem of maximizing the biogas production over a given period of time max D(t) t=T t=0 µ(s)xdt for a large class of kinetics functions (including both Monod and Haldane growth rates). These results are then used to better understand the knowledge-based controller proposed by [START_REF] Steyer | Advanced control of anaerobic digestion processes throug disturbances modeling[END_REF]. This paper is organized as follows. In section [START_REF] Bastin | On-line Estimation and Adaptative Control of Bioreactors[END_REF] we present the class of problems we are interested in. In the next section, we establish the main results of the paper about the maximization of the output gas flow rate for the chemostat model. In section 4, we compare the control law we establish in section 3 with that one proposed by Steyer et al., 1999 [20]. In section 5, we propose to use a direct approach to intuiter the optimal trajectories for a more general class of initial conditions than those considered in previous sections before some conclusions and perspectives are drawn.

Model description and control problem

In the present work, we consider a single-step model for the anaerobic digestion process based on one biological reaction, where the organic substrate denoted by s is degraded into methane biogas (CH 4 ) by a bacterial population x. We assume that the methane flow rate, Q CH 4 , is proportional to the microbial activity as proposed in [START_REF] Bastin | On-line Estimation and Adaptative Control of Bioreactors[END_REF]. The mass balance model of the classical chemostat model is given by the following nonlinear system of ordinary differential equations :

ẋ = (µ(s) -D)x ṡ = D(s in -s) -µ(s)x (1)
where x and s denote biomass and substrate concentrations, respectively, s in is the concentration of the influent substrate s, while µ(s) is the specific growth rate of biomass. D ∈ [D min , D max ] is the dilution rate which is considered hereafter as the control variable, µ is the specific growth rate of microorganisms. Notice that the yield coefficient Y which usually appears in the chemostat model, does not appear in the equations since it is straightforward to show that the change of variable x = X/Y allows us to reduce the system to (1). In the sequel, we will consider that the kinetic µ, satisfies the very general property :

Hypothesis 1. µ(0) = 0 and µ(s) > 0 for all s > 0. The function µ(•) is either increasing, or there exists s such that µ(s) is increasing for 0 < s < s and decreasing for s > s.

In this paper, we seek to maximize the biogas production over a given time interval. The total methane production over the interval [0, T ] can be expressed as :

J(x(•), s(•), D(•)) = T 0 kµ(s(t))x(t)dt (2)
where (x(•), s(•), D(•)) satisfy (1). Since k is constant, without loss of generality, we will consider k = 1 in the following. The problem of maximizing biogas production consist in maximazing the integral (2) under the constraint D min ≤ D(t) ≤ D max . As surprising as it may be, as posed hereabove in very general terms, the optimal control problem is very difficult to solve. It is why we restrict here our attention to a specific case in introducing the following additional hypothesis.

Hypothesis 2. The initial conditions of system (1) lie on the line x 0 + s 0 = s in .

Notice that under Hypothesis 2, x(t) + s(t) = x 0 + s 0 = s in holds for all positive t. Thus, the two dimensional dynamical system (1) is reduced to the following one dimensional system :

ẋ = γ(x) -Dx; x(0) = x 0 (3)
with γ(x) = µ(s in -x)x. Notice that γ(0) = 0 and γ(s in ) = 0. We can then rewrite the functional (2), with k = 1, as :

J(x(•), D(•)) = T 0 γ(x(t))dt (4)
where (x(•), D(•)) satisfy (3), subject to constraint D min ≤ D(t) ≤ D max . Finally, to completely define our problem, we introduce the following hypotheses Hypothesis 3. There exists 3 Maximizing the output gas flow rate

x * ∈]0, s in [ such that γ(x) ≤ γ(x * ) for all x ∈ [0, s in ] (5) γ(x) is increasing on [0, x * ] (6) γ(x) is decreasing on [x * , s in ] (7)

Main results

We first establish the following result (the proof is given in Appendix (A)) : Proposition 1. Assume that Hypotheses 1-4 hold. Then the optimal control maximizing the functional (4) is given by :

D(•) =    D min if x(t) < x * D max if x(t) > x * D * if x(t) = x * (8)
where D * = µ(s in -x * ) is the singular control which keeps x(t) = x * at the optimal steady state.

In such a case, according to the position of x(t) with respect to x * , the digester operates either at its minimum (D = D min ) or at its maximum capacity (D = D max ), until it reaches the singular arc D * and stay at the optimal steady state x * .

Remark 2

The bang-bang control law proposed within proposition 1 is equivalent to the fastest possible way to go towards the optimal point x * and stay there if x * is attained.

Implementation problems and robustness properties 3.2.1 Implementation of the control law

In this section, we discuss a number of questions related to the practical implementation of the optimal control law given in the previous section. The first question that may arise is related to the bang-bang character of the control. Indeed, when implementing the optimal strategy, we face the problem of simulating a dynamical system with a discontinuous second member ( [START_REF] Lobry | Equations différentielles à second membres discontinus[END_REF]). This problem can be solved using specific mathematical analysis tools and numerical algorithms. In practice, to apply this strategy on a real system, this problem is usually circumvented using regularization techniques. This approach consists in joining the two discontinuous arcs of the control by a continuous signal where the switch between two discontinuous values of the control is replaced by a continuous change between x * -2 and x * + 1 (resp. s * -2 and s * + 1 if s is measured instead of x, cf. Figure 1 where 1 and/or 2 are tuning parameters as shown in Figure 1. Once regularized, one may check by simulation that the closed loop system behaves satisfactorily.

𝐷 𝑚𝑎𝑥 𝑥 * -𝜀 2 𝐷 𝑚𝑖𝑛 𝐷 * 𝑥 * 𝑥 * + 𝜀 1 𝑠 * -𝜀 2 𝑠 * 𝑠 * + 𝜀 1 𝐷 𝑚𝑎𝑥 𝐷 𝑚𝑖𝑛 𝐷 * Figure 1 -Regularization of a discontinuous control signal depending on the mea- surement : x is measured (left), s is measured (right).
The presence of noise and the fact that sensors and/or actuators can be affected by delays may also disturb the functioning of the controller. In such cases, the use of different filters and other numerical techniques may limit the level of their influence on the closed-loop system. One must also keep in mind that measuring biological states can take some time and that actuators, like pumps in the present case, cannot deliver signals with too high derivatives. Thus, the discrete character of actuators and sensors must be dealt with. In more specific terms, engineers evaluate the robustness of the controller in the presence of such disturbances and if the simulation results are appropriate, do not implement sophisticated techniques. Apart from very specific application domains like in aeronautic or astronautic, such questions for biological processes are usually only studied in simulation or explored for very particular cases without considering any optimization criterion (cf. for instance [START_REF] Mazenc | Stabilization of the chemostat with delayed sampled measurements[END_REF]). However, it may happen that apparent small changes lead to important consequences for the closed-loop system. In our case, as already stated hereabove, notice that it may happen that the variable s is measured instead of x. In such a case, a corollary of Proposition 1 can directly be written and yields the same optimal control law unlike the decision is inverted with respect to the position of s with respect to s * since x(t) = s in -s(t). It seems that nothing is fundamentally changed in the control unless it is now the corollary to Proposition 1 which must be used to compute the actual control. However, if we investigate now the robustness properties of the control system, we will establish that under some circumstances, fundamental and actually dramatic changes may arise.

Robustness with respect to initial conditions

In practice, the condition x 0 + s 0 = s in , defined as the hypothesis 2, may not be satisfied. Studying the robustness of the control with respect to the initial conditions refers to studying what happens to the system when the closed loop system is simulated with the control law synthesized in proposition 1 -that has been designed for x 0 + s 0 = s in -while it is actually not the case.

Remark 3 When Hypothesis 2 is not satisfied, the control law is not optimal. More precisely, notice that the strategy proposed in Proposition 1 consists in applying either D min or D max and then to switch to the singular control D * which shall maintain the state on the singular arc x = x * or s = s * once it is attained. However, it has been established by Stamatelalou et al. (cf. [START_REF] Stamatelatou | Optimal and suboptimal control of anaerobic digesters[END_REF]) that s = s * (or x = x * ) are not singular arcs in the general case (however, as recalled in the introduction, in their paper Stamatelatou et al. did not give the optimal synthesis. The problem is difficult and actually remains open). Thus, the control proposed in Proposition 1 is not optimal when Hypothesis 2 is not satisfied.

First, assume x is measured. Let us apply the control law [START_REF] García-Diéguez | Reducing the Anaerobic Digestion Model No. 1 for its application to an industrial wastewater treatment plant treating winery effluent wastewater[END_REF] given in Proposition 1 for different values of s 0 , x 0 and s in such that x 0 +s 0 = s in is no longer satisfied. To illustrate our discussion, let consider a model with Monod kinetic where µ max = 4.5, K S = 10, S in = 100, D max = 1.2D * (all in arbitrary appropriate units 1 ). In such a case x * which only depends on µ max , K S and s in equals 76.8. Let us simulate the control over a period of time T = 2 for several sets of initial conditions and two different values of D min , that are D min = 0 and D min = 1. To avoid numerical problems due to the presence of a discontinuous second member, we regularize the control law with 1 = 1 yielding 2 = 5 where 1 and 2 are defined in Figure 1 and thus computed as :

2 = 1 D * -D min D max -D * if
x is measured and as :

2 = 1 D * -D max D min -D * if s is measured.
With the regulation of the control law, the system to be simulated is a simple system of ordinary differential equations which were solved using standard matlab solvers. The total biogas produced for each case is reported in the third column of Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF] while the dynamic behavior of some interesting cases (solutions with initial conditions {s 0 , x 0 } corresponding to {10, 10}, {10, 40} and {10, 70}, D min = 0) are plotted in Figure 2. For several initial conditions ({10, 10}, {10, 40} and {50, 10} in Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF]), when x is measured, the system behaves as a batch and the optimal steady state is never reached even for large T : since the yield of biogas production equals 1, the total biogas produced is simply equal to s 0 . The reason explaining this batch behavior is the following : as stated in Proposition 1, as long as x 0 < x * , the control applied is D = D min = 0 until x(t) reaches x * . If T is large enough, the condition x 0 + s 0 = s in guarantees that there is enough substrate for the biomass to reach x * . However, when x 0 + s 0 = s in no longer holds, like in the cases where initial conditions are {10, 10}, {10, 40} and {50, 10}, it may happen that there is not enough substrate for is the solution of (1) with initial condition (s 0 , x 0 ) and D(•) is given by [START_REF] García-Diéguez | Reducing the Anaerobic Digestion Model No. 1 for its application to an industrial wastewater treatment plant treating winery effluent wastewater[END_REF] [resp. [START_REF]IWA Task Group for Mathematical Modeling of Anaerobic Digestion Processes[END_REF]].

D min {s 0 , x 0 } functional (2) functional (
the biomass to grow sufficiently to attain x * . In other terms, if x 0 + s 0 = s in is not verified, if x 0 < x * and if s 0 is too small, then the control never switches to D max and remains to D = D min = 0 leading to the production of a very small amount of biogas. The control law is thus poorly robust with respect to initial conditions when x is measured. Now, assume that s is measured instead of x. The control law [START_REF] García-Diéguez | Reducing the Anaerobic Digestion Model No. 1 for its application to an industrial wastewater treatment plant treating winery effluent wastewater[END_REF] given in Proposition 1 is written now

D(•) =    D min if s(t) > s * D max if s(t) < s * D * if s(t) = s * (9)
where

s * = s in -x * .
Let us study by simulation the robustness of the control law with respect to the initial conditions. We choose 1 = 1 yielding now 2 = 0.2. Again, we simulate the system for the set of initial conditions reported in Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF] and for two values of D min . The total biogas produced for each case is reported in the fourth column of Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF]. As in the previous case, a number of simulation results are reported in Figure 3 (solutions with initial conditions {s 0 , x 0 } corresponding to {10, 10}, {10, 40} and {10, 70}, D min = 0) and the total biogas produced in each case is reported in Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF]. In this case, although s 0 +x 0 = s in is not satisfied, the system behaves well and as long as T is large enough and x 0 > 0, the optimal point is always attained.

Of course, the control law cannot be said to be 'optimal' with respect to the biogas production since some hypotheses are not verified, but at least, the system converges -asymptotically -towards the optimal point computed with x 0 + s 0 = s in . In this sense, we can then say that the control is robust with respect to initial conditions if s is measured instead of x.

Furthermore, as long as x * is attained (i.e. D min > 0 and T large enough) we noticed that the total biogas produced is always greater when s is measured instead of x (compare third and fourth columns of Table 1). However, we could not prove this point and there is thus no reason to affirm that it is a general result as long as Hypothesis 2 is not satisfied.

Comparison with the heuristic control law

In this section, we use the results established in Proposition 1 to show that the control law proposed in [START_REF] Steyer | Advanced control of anaerobic digestion processes throug disturbances modeling[END_REF] and ours drive the system towards the same functioning point.

Basically, the control by [START_REF] Steyer | Advanced control of anaerobic digestion processes throug disturbances modeling[END_REF] is based upon a test about the actual 'biological state' of the digester. The authors even presented their control law as a 'real dialog' between the operator and the microbial ecosystem of the process. The idea relies on the application of a controlled disturbance in the input flow rate during a given period of time. Assuming the input substrate concentration is known and constant, one may compute the theoretical increase in the gas flow this disturbance should cause. Monitoring the gas flow over the time allows then the user to estimate whether the applied overload has been supported by the process -through a corresponding increase in the biogas -or not. If yes, the process is considered to be in 'good health' and the input load can be increased through an increase of the input flow rate. If not, it means that the additional substrate that has been introduced through the disturbance has accumulated in the process (under the form of intermediate byproducts of the anaerobic digestion like VFA) possibly leading to a destabilization of the process. In such a case, the input flow rate is decreased. Let us compare this strategy with ours. Consider the output gas flow rate represented by the γ function in Figure 4 for the same model than in section (3.2.2) and S in = 100. Under the hypothesis that x 0 + s 0 = s in , the dynamic of the system is given by ẋ = γ(x) -Dx. First, consider an equilibrium point x such that x < x * (left side of Figure 4). Notice that the corresponding input flow rate verifies D max > D = µ(s in -x) > D * . In this case, we know that the optimal control consists in applying D = 0 and that this control will drive the system towards x * = 76.8 (once attained, the control is then switched to D * ). Now, from the same initial equilibrium point x < x * , let us apply the control by Steyer et al., 1999. In particular, let us apply a disturbance D d > D during a given period of time (step 1 on the left in Figure 4) and let us monitor the output of the system, that is the output gas flow rate. Since the dynamic of the system is given by ẋ = γ(x) -D d x, x will decrease (step 2 on the left in Figure 4) and since γ is increasing for all x < x * , we will observe a decrease in the biogas. Following the algorithm of Steyer et al., 1999 [20], we should conclude that the system does not behave very well and decrease the value of D accordingly (step 3 on the left in Figure 4). Reproducing again the same strategy, it is quite clear, at least intuitively, that the applied control should converge towards D * , which is actually the optimal strategy since it will finally drive the state x towards x * . Conversely, if we start from an initial condition with a D < D * such that x > x * , we can show using the same reasoning than previously (and taking into account that γ is decreasing for x > x * ), that the heuristic control will drive the state towards x * as the optimal control (steps 1 to 3 on the right in Figure 4). Obviously, the heuristic strategy is not optimal with respect to the functional (4) since it will take more time to reach the optimal state x * than using the bang-bang optimal strategy, but we can still conclude that the control is similar to ours in the sense it will drive the system towards the optimal point x * which maximizes the output gas flow rate.

A direct approach

In previous sections, we have designed an optimal control law for the system (1) with respect to the functional (4) under Hypotheses 1 to 3. Using tools of the optimal control theory, under Hypothesis 2, we were able to find the optimal feedback law to be applied in measuring one state of the system. When Hypothesis 2 does not hold anymore or when the model of the system is more complicated than ours so as it is not possible anymore to derive analytically the solution, a direct approach can be used. Here a 'direct approach' is referred to as a completely numerical optimization. The last decade, a number of softwares have been designed for that purpose. Here, we use a software called BOCOP ( [START_REF] Bonnans | BOCOP -A collection of examples[END_REF]). The principle of this tool is to discretize the problem and to find optimal trajectories among all candidates using numerical optimization toolkits. We have used this software in a 'blind way', i.e. without introducing any other knowledge than the criterion to be optimized, the model of the system and the known constraints on the actuator.

First, let us compare what BOCOP delivers when Hypothesis 2 holds with the application of the exact optimal solution. Again, we use the same parameters as those used in the section (3.2.2). In this case, recall that x * = 76.87 and D * = 3.14. The exact optimal control is given by Proposition 1 as long as Hypotheses 1 to 3 hold. Let x 0 = 10 and s 0 = 90. Again, to avoid numerical problems, the control is regularized with 1 = 1. Let us compare the trajectories obtained when applying Proposition 1 and those computed by BOCOP for this first example. Both state trajectories and corresponding control signals are plotted in Figure 5 while BOCOP optimization parameters and results are reported in Appendix (B). The flowrates in both cases are equivalent (equal to about 422). Obviously, BO-COP delivers a control signal which is comparable to the theoretical optimal solution.

These results suggest that BOCOP may be a good candidate to investigate extensions of the optimal control solutions when hypotheses used in the design of the optimal control do not hold anymore. In particular, we can investigate what could be the optimal controls computed with BOCOP when s 0 + x 0 = s in does not hold. Thus, one may compare the results obtained in the section (3.2.1) within the framework of the study of the robustness of the control law with respect to the initial conditions and those obtained with BOCOP. For that purpose, we solve the problem with BOCOP using x 0 = 10 and s 0 = 10, 40 and 70, respectively. Simulation results are presented in Figure 6 while the total biogas produced in each case is reported in Table [START_REF] Bastin | On-line Estimation and Adaptative Control of Bioreactors[END_REF] and BOCOP optimization parameters and results are reported in Appendix (B).

More precisely, three cases are represented in Figure 6. For easily comparing the trajectories obtained within the robustness study (applying Proposition 1 while 3) ; on the medium, optimal trajectories and controls computed with BOCOP and on the bottom, the same trajectories and control when the criterion is modified in penalizing the control to avoid control chattering ( = 5). s 0 + x 0 = s in does not hold) and those obtained with BOCOP, we plotted again the trajectories and controls of Figure 3 on the top of Figure 6. Just below, medium place of Figure 6, we plotted the optimal trajectories and corresponding controls obtained with BOCOP for the three initial conditions. The control signals are very noisy, simply because BOCOP has difficulties when the trajectory follows a singular arc. To avoid such chattering phenomena when using a numerical optimization software, one way to proceed is to modify the criterion to be optimized in penalizing the control signal. The criterion then becomes :

J(x(.), s(.), D(.)) = T 0 µ(s(t))x(t) + D(t) 2 dt (10)
Of course, when proceeding this way, a fine compromise must be found when choosing which must be kept small enough : it is expected that smaller closer the computed trajectories from the optimal ones since functional [START_REF] Liu | Extremum-seeking with variable gain control for intensifying biogas production in anaerobic fermentation[END_REF] Table 3 -Functional [START_REF] Liu | Extremum-seeking with variable gain control for intensifying biogas production in anaerobic fermentation[END_REF] when computing the optimal solution with BOCOP in the case where a penalty on the control is added in the criterion (here for = 5) and the corresponding biogas produced (functional (2)) over the period T = 2.

functional (2) when tends towards zero. The trajectories and controls corresponding to optimizations obtained with = 5 are plotted in the last line of Figure 6 (again, BOSOP optimization parameters and results are reported in Appendix (B)).

To evaluate the different results, we can first compare the biogas production values reported in Table [START_REF] Alcaraz-Gonzalez | Robust intervalbased SISO and SIMO regulation for a class of highly uncertain bioreactors : application to the anaerobic digestion[END_REF] of section (3.2.2) and those obtained with BOCOP (without penalty on the control) reported in Table (2) : for each pair of initial conditions considered, we notice that the total biogas produced is comparable. then, we can compare the optimal control performance with and without penalty on the control in the criterion in comparing results reported in Tables [START_REF] Bastin | On-line Estimation and Adaptative Control of Bioreactors[END_REF] and (3). Again, the results are comparable : whatever the control is left free or constrained by an additional penalty in the criterion, the optimal strategies are comparable for identical initial conditions. Thus, on the first hand, we suggest BOCOP to be a good candidate to rapidly intuiter optimal solutions when the analytical solution of a problem is not known. On the other hand, these results suggest that applying the control law proposed within the framework of Proposition 1 while Hypothesis 2 does not hold should produce reasonably good results in terms of biogas production and that the optimal solution is thus quite robust to uncertainty on the initial solutions as long as s is measured.

Conclusions and perspectives

In this work, we have discussed classical implementation problems and robustness issues with respect to recent results from optimal control theory for the chemostat with the class of kinetics satisfying Hypotheses 1 and (3). Using these results, the optimality of the heuristic control law initially proposed by Steyer et al., 1999 was investigated. It was shown that this heuristic control law is suboptimal with respect to the maximization of the biogas over a given period of time and that it drives the system towards the same optimal point than the actual optimal control law. Perspectives of this work include the extension of our results to more complex models than the simple chemostat model and, eventually based on numerical results obtained with a numerical optimization toolkit, e.g. the BOCOP software, the generalization of the results in the case where the condition x 0 + s 0 = s in does not hold, which, actually, remains an open problem. In Section (A.1), we give the proof of Proposition 1 for an increasing function µ(•). When µ(•) is increasing and then decreasing (like a Haldane growth function) the proof is similar with some technicalities, see Section (A.2).

A.1 The case of a Monod type function

Proof. In this section, we assume that µ(•) is increasing. According to Hypothesis 4, D min ≤ D * , µ(s * ) = D * and s * < s in . Thus there exists s min such that µ(s min ) = D min and s min ≤ s * < s in . Recall that x(t, x 0 , D min ) is the solution of :

ẋ = γ(x) -D min x, x(0) = x 0 (12)
The solution of (12) converges towards x min = s in -s min ≥ x * . Hence for all x 0 ≤ x * there exists t min (x 0 ) such that x(t min (x 0 ), x 0 , D min ) = x * . Similarly, x(t, x 0 , D max ) is the solution of :

ẋ = γ(x) -D max x, x(0) = x 0 (13)
If D max ≥ sup µ(•), the solution of (13) converges towards 0. If D max < sup µ(•), let s max be defined by µ(s max ) = D max . According to Hypothesis 4, we have s * ≤ s max . Two cases must be distinguished : If s max < s in then the solution of (13) converges towards x max = s in -s max ≤ x * . If s max ≥ s in it converges towards 0. Hence for all x 0 ≥ x * there exists t max (x 0 ) such that x(t max (x 0 ), x 0 , D max ) = x * . Let us define

t * (x 0 ) = min (T, t min (x 0 )) if x 0 ≤ x * min (T, t max (x 0 )) if x 0 ≥ x * (14)
In other words, t * (x 0 ) is the instant at which the solution x(t, x 0 , D min ) reaches x * , when x 0 ≤ x * , or x(t, x 0 , D max ) reaches x * , when x 0 ≥ x * , if its reaches it on [0, T ]. If these solutions never reach x * on [0, T ], t * (x 0 ) is put equal to T . Now, to prove Proposition 1, we consider an admissible control D(•) and an initial condition x 0 ∈ [0, s in )]. To simplify notations we note x(t) = x(t, x 0 , D(•)). We distinguish two cases depending on x 0 .

If 0 ≤ x 0 ≤ x * then let us consider the following control :

D * (t) = D min if 0 ≤ t ≤ t * (x 0 ) D * if t * (x 0 ) < t ≤ T (15)
where t * (x 0 ) is defined by [START_REF] Rehl | Müller CO2 abatement costs of greenhouse gas (GHG) mitigation by different biogas conversion pathways[END_REF]. The corresponding solution is given by

x * (t) = x(t, x 0 , D min ) if 0 ≤ t ≤ t * (x 0 ) x * if t * (x 0 ) < t
Using ( 16) and ( 17), for all t ∈ [0, T ], γ(x(t)) ≤ γ(x * (t)). Therefore, for all

x 0 ≤ x * J(x(•), D(•)) = T 0 γ(x(t))dt ≤ T 0 γ(x * (t))dt = J(x * (•), D * (•)) (18)
If x * ≤ x 0 ≤ s in then let us introduce the following control :

D * (t) = D max if 0 ≤ t ≤ t * (x 0 ) D * if t * (x 0 ) < t ≤ T (19)
where t * (x 0 ) is defined by [START_REF] Rehl | Müller CO2 abatement costs of greenhouse gas (GHG) mitigation by different biogas conversion pathways[END_REF]. The corresponding solution is given by

x * (t) = x(t, x 0 , D max ) if 0 ≤ t ≤ t * (x 0 ) x * if t * (x 0 ) < t ≤ T
Using Lemma 2, for all admissible control D(•) one has

x(t) ≥ x(t, x 0 , D max ) = x * (t) for all t ∈ [0, t * (x 0 )] Since x * (t) ≥ x * for all t ∈ [0, t * (x 0 )], from (7) we deduce that γ(x(t)) ≤ γ(x * (t)) for all t ∈ [0, t * (x 0 )] (20)
Since x * (t) = x * for all t ∈ [t * (x 0 ), T ], from (5) we deduce that

γ(x(t)) ≤ γ(x * (t)) for all t ∈ [t * (x 0 ), T ] (21)
Using ( 20) and ( 21), for all t ∈ [0, T ], γ(x(t)) ≤ γ(x * (t)). Therefore, for all

x 0 ≥ x * J(x(•), D(•)) = T 0 γ(x(t))dt ≤ T 0 γ(x * (t))dt = J(x * (•), D * (•)) (22)
From ( 18) and ( 22) we deduce that for all initial conditions x 0 ∈ [0, s in ] and the admissible control D(•) one has

J(x * (•), D * (•)) = max D min ≤D(•)≤Dmax J(x(•), D(•)).
Thus, depending on the initial conditions, the control defined by [START_REF] Rodryguez | A hydrogen-based variable-gain controller for anaerobic digestion processes[END_REF] and by ( 19) is optimal, which is exactly what Proposition 1 states.

A.2 The case of a Haldane type function

Proof. We assume that there exists s such that µ(s) is increasing for 0 < s < s and decreasing for s > s. The numbers s min or s max were defined in the previous sections as solutions of equations µ(s) = D min or µ(s) = D max respectively. Now these equations can have at most two solutions and we must explain how to choose their appropriate solution s min or s max .

Let x * ∈]0, s in [ given by Hypothesis 3. Then γ (x * ) = 0. Since

γ (x) = µ(s in -x) -µ (s in -x)x
we have µ (s * ) = µ (s in -x * ) > 0, that is to say 0 < s * < s. According to Hypothesis 4, D min ≤ D * , µ(s * ) = D * and s * < s in . Thus, there exists s min and s min such that µ(s min ) = µ s min = D min and s min ≤ s * < s in and s min < s < s min Two cases must be distinguished : If µ(s in ) ≥ D min , that is to say s in ≤ s min then for all x 0 ≤ x * , the solution of (12) converges towards x min = s in -s min ≥ x * . Therefore, there exists t min (x 0 ) such that x(t min (x 0 ), x 0 , D min ) = x * . If µ(s in ) < D min , that is to say s in > s min then, for all x 0 ≤ x * , the solution of (12) converges either towards x min ≥ x * , either towards 0. More precisely, 1. if x min < x 0 ≤ x * , where x min = s in -s min > 0, the solution of (12) converges towards x min ≥ x * , and we define t min (x 0 ) by x(t min (x 0 ), x 0 , D min ) = x * 2. if 0 < x 0 < x min , the solution of (12) converges towards 0, so that it never attains x * , and we let t min (x 0 ) = +∞.

If D max ≥ sup µ(•), the solution of (13) converges towards 0. If D max < sup µ(•), let s max and s max such that µ(s max ) = µ s max = D max and s * ≤ s max < s < s max Many cases must be distinguished : If s max ≥ s in then the solution of (13) converges towards 0. If s max < s in < s max , then it converges towards x max = s in -s max ≤ x * . If s max < s in , then it converges either towards x max ≤ x * , either towards 0. Therefore for all x 0 ≥ x * , the solution attains x * and therefore, there exists t max (x 0 ) such that x(t max (x 0 ), x 0 , D max ) = x * .

We define now t * (x 0 ) by [START_REF] Rehl | Müller CO2 abatement costs of greenhouse gas (GHG) mitigation by different biogas conversion pathways[END_REF]. The rest of the proof is the same as in Section (A.1). Remark 4 If µ(s in ) < D min , the washout is locally stable and there exist initial conditions (defined as 0 < x 0 < x min ) for which x converges towards 0. Notice however that it never happens if D min = 0.

B BOCOP optimization parameters for results reported in section 5

Hereafter, we report BOCOP parameters for the 7 optimizations realized with BOCOP reported in Figures 5 and 6

Hypothesis 4 .Remark 1

 41 Let D * = µ(s in -x * ) be the control for which x = x * is a steady state of equation (3). We assume that 0 ≤ D min ≤ D * ≤ D max . Note that both Monod and Haldane functions (that are µ(s) = µ max s s+ks and µ(s) = µ max s s+ks+ s 2 k i , respectively) verify Hypotheses 1 and 3.

Figure 2 -

 2 Figure2-Robustness of the optimal control when x is measured and s 0 + x 0 = s in does not hold, D min = 0 and D max = 1.2D * ; on the left, x is plotted in thick dotted lines and s in fine solid lines.

Figure 3 -

 3 Figure3-Robustness of the optimal control when s is measured and s 0 + x 0 = s in does not hold, D min = 0 and D max = 1.2D * ; on the left, x is plotted in thick dotted lines and s in fine solid lines.

Figure 4 -

 4 Figure 4 -The function γ and the heuristic control law.

Figure 5 -

 5 Figure5-Exact optimal control and optimal control computed with BOCOP : Monod kinetic, s 0 + x 0 = s in .

Figure 6 -

 6 Figure 6 -Comparison of optimal controls when s 0 +x 0 = s in does not hold ; Monod kinetic and D * ≤ D max : on the top, the plots are the same as those in Figure (3) ;on the medium, optimal trajectories and controls computed with BOCOP and on the bottom, the same trajectories and control when the criterion is modified in penalizing the control to avoid control chattering ( = 5).

Lemma 2 .

 2 Let D = D(•) a control satisfying D min ≤ D(t) ≤ D max for all t ∈ [0, T ].We have :x(t, x 0 , D max ) ≤ x(t, x 0 , D(•) ≤ x(t,x 0 , D min ), for all t ∈ [0, T ] Proof. It comes from a direct application of the theorem of comparison of solutions of dynamical systems since for any control D(•) satisfying D min ≤ D(t) ≤ D max one has : γ(x) -D max x ≤ γ(x) -D(t)x ≤ γ(x) -D min x

1 .

 1 Simulations of Figure 5, Initial conditions x 0 = 10 and s 0 = 90 : -Discretization method : 4th order Runge-Kutta -Discretization step : fix -Total simulation time : 0.85s -Desired convergence tolerance : 1.0000000000e -010 -Total CPU in IPOPT : 0.323s -Total CPU in NLP : 0.477s -Nb of iterations : 31 2. Simulations of Figure 6, medium figures, Initial conditions x 0 = 10 and s 0 = 10 : -Discretization method : 1st order Explicit Euler -Discretization step : fix -Total simulation time : 0.57s -Desired convergence tolerance : 1.0000000000e -012 -Total CPU in IPOPT : 0.29s -Total CPU in NLP : 0.223s -Nb of iterations : 40 3. Simulations of Figure 6, medium figures, Initial conditions x 0 = 10 and s 0 = 40 : -Discretization method : 1st order Explicit Euler -Discretization step : fix -Total simulation time : 0.64s -Desired convergence tolerance : 1.0000000000e -012 -Total CPU in IPOPT : 0.34s -Total CPU in NLP : 0.251s -Nb of iterations : 48 4. Simulations of Figure 6, medium figures, Initial conditions x 0 = 10 and s 0 = 70 : -Discretization method : 1st order Explicit Euler -Discretization step : fix -Total simulation time : 0.37s -Desired convergence tolerance : 1.0000000000e -012 -Total CPU in IPOPT : 0.207s -Total CPU in NLP : 0.138s -Nb of iterations : 37 5. Simulations of Figure 6, bottom figures, Initial conditions x 0 = 10 and s 0 = 10 : -Discretization method : 4th order Implicit Gauss -Discretization step : fix -Total simulation time : 0.58s -Desired convergence tolerance : 1.0000000000e -005 -Total CPU in IPOPT : 0.21s -Total CPU in NLP : 0.315s -Nb of iterations : 20 6. Simulations of Figure 6, bottom figures, Initial conditions x 0 = 10 and s 0 = 40 : -Discretization method : 1st order Explicit Euler -Discretization step : fix -Total simulation time : 0.32s -Desired convergence tolerance : 1.0000000000e -005 -Total CPU in IPOPT : 0.16s -Total CPU in NLP : 0.11s -Nb of iterations : 21 7. Simulations of Figure 6, bottom figures, Initial conditions x 0 = 10 and s 0 = 70 : -Discretization method : 1st order Explicit Euler -Discretization step : fix -Total simulation time : 0.37s -Desired convergence tolerance : 1.0000000000e -005 -Total CPU in IPOPT : 0.18s -Total CPU in NLP : 0.12s -Nb of iterations : 23

Table 1 -

 1 Gas flow rate wrt initial conditions, D min and the measurement used.

	2)

The third [resp. fourth] column gives the value of the functional (2), where x(•), s(•)

Table 2 -

 2 Gas flow rate when computing the optimal solution with BOCOP in the case where no penalty on the control in the criterion.

	tends towards

  ≤ T Using Lemma 2, for all admissible control D(•) one hasx(t) ≤ x(t, x 0 , D min ) = x * (t) for all t ∈ [0, t * (x 0 )] Since x * (t) ≤ x * for all t ∈ [0, t * (x 0 )], from[START_REF] Dimitrova | Nonlinear adaptive control of a model of an uncertain fermentation process[END_REF] we deduce that

	γ(x(t)) ≤ γ(x * (t)) for all t ∈ [0, t * (x 0 )]	(16)
	Since x * (t) = x * for all t ∈ [t * (x 0 ), T ], from (5) we deduce that
	γ(x(t)) ≤ γ(x

* (t)) for all t ∈ [t * (x 0 ), T ]

The values for µ max and K S will be the same in all simulations of the paper

Acknowledgment : The authors would like to thank the Euro-Mediterranean research network TREASURE (INRA-INRIA Euromed 3+3 project), the PHC TAS-SILI project no 33254QH and the Averroes program for their support. They also thank Terence Bayen, Claude Lobry, Ali Moussaoui and Alain Rapaport for fruitful discussions about this work.

Références

A Proof of Proposition 1

Let D(•) be an admissible control. Let x(t, x 0 , D(•)) be the solution of the system :

We need the following lemma :