Bruno Marques

Nazim Haouchine

Rosalie Plantefeve

Stephane Cotin

Improving depth perception during surgical augmented reality

Improving Depth Perception during Surgical Augmented Reality

Bruno Marques Inria

Nazim Haouchine Inria

Rosalie Plantefeve Altran Medic@

Stephane Cotin * Inria

Context

Minimally invasive surgery (MIS) is a recent surgical technique where the surgeon does not interact directly with the patient's organs.

In contrast to open surgery, the surgeon manipulates the organs through instruments inserted in the patient's abdominal cavity while observing the organ from a display showing the video stream captured by an endoscopic camera. While the benefits of MIS for patients are clearly claimed, performing these operations remains very challenging for the surgeons, due to the loss of depth perception caused by this indirect manipulation. To tackle this limitation, the research community suggests to use augmented reality (AR) during the procedure [START_REF] Haouchine | Image-guided simulation of heterogeneous tissue deformation for augmented reality during hepatic surgery[END_REF]]. The objective towards the use of AR during surgery is to be able to overlay the 3D model of the organ (that can be obtained from a pre-operative scan of the patient) onto the video stream. Surgical AR made considerable advances and reached a certain maturity in the estimation of tumors and vessels localisation. Howerver, very few studies have investigated depth perception and visualization of internal structures [START_REF] Lerotic | pq-space based non-photorealistic rendering for augmented reality[END_REF]], which is considered by surgeons as a very sensitive issue. This study suggests a method to compensate the loss of depth perception while enhancing organ vessels and tumors to surgeons. This method relies on a combination of contour rendering technique and adaptive alpha blending to effectively perceive the vessels and tumors depth. In addition, this technique is designed to achieve real-time to satisfy the requirements of clinical routines, and has been tested on real human surgery.

Technical Approach

This method relies on the adaptive computation of the alpha blending. To do so, a reference distance is defined, corresponding to the maximum depth perception. This reference distance (denoted d in the following) can be adapted by surgeons during the surgery regarding their needs to perceive depth (surgeon sensitivity to depth perception might vary during the operation). Moreover, the accuracy of the 3D model registration on the images drops in proportion * e-mail:stephane.cotin@inria.fr to its depth which makes it highly accountable. Therefore, this parameter should be kept reasonably small to avoid displaying flawed data caused by the limitations of the registration technique. Furthermore, the algorithms is as follows.

Let us denote V = {vi ∈ R 3 } the set of vessels vertices and S = {si ∈ R 3 } the set of organ surface vertices. The alpha ratio is computed for each vertex of the vessels meshes using a ray-casting technique. At initialization, a ray is projected from the camera optical center c ∈ R 3 to intersect each vertex vi of the vessels. Then, each vertex si of the organ's surface si is projected on the previously computed ray to find the closest vertex to the ray following:

α[vi] = vi -pi d , pi = argmin s j ∈S (sj -c)-γ(sj -c, vi-c) (1)
where d is the predefined maximal depth distance and γ(a, b) is the vector projection of a on b.

The organ surface is rendered with a simple contour rendering shader to display the surface of the organ. This will ensure an unobstructed view of the real organ while still allowing the in-depth perception of vessels.

The Figure 1 illustrates the augmented view of a human liver during a laparoscopic liver resection. The visualization takes into account the changing shape of the organ that requires real time computation of the alpha blending step while capturing organ deformations that emanates from instruments manipulation, heart beating and breathing. The maximal depth distance is experimentally set to d = 4 cm. The algorithm performs in near real-time at around 18 fps while using a mesh composed of more than 30.000 vertices, accounting for liver surface, vessels and tumors, thanks to a GPU implementation using NVidia CUDA. Future work will investigate the deployment of this method to the operating room as well as quantify surgeons feedback regarding visualization.

Figure 1 :

 1 Figure 1: Visualization of liver vessels and tumors during Surgical Augmented Reality with (a) the input image, (b) the registration with the original visualization, (c) our method without the adaptive alpha blending and (d) the final output visualization using our method.


Dominique Bergogne
email: dominique.bergogne@univ-lyon1.frwww.ampere-lab.fr

Christian Martin

Pascal Bevilacqua

Wided Zine

Jean-Christophe Riou

Hilal Izzeddine

Régis Meuret

Bruno Allard

Ampère

Safran

Integrated Coreless Transformer for High Temperatures Design and Evaluation

Keywords: <<Passive component>>, <<Device characterization>>, <<Integrated Circuit (IC)

A novel coreless technology based on an existing process, initially designed to produce integrated passive components for commercial temperatures, is used and its capability at 200°C is tested. Design aspects and electrical characterizations of the samples are presented. Finally, an endurance test shows a satisfactory behaviour at high temperatures.

Introduction

Ever since power electronics converters were implemented, either as laboratory scale demonstrators or in industrial applications, a major issue had to be solved: insulation of the high voltage power circuit from the low voltage control circuit. The resulting voltage stress is particularly focused at a specific point where digital meets power, the driver. The on/off digital signal is converted to some kind of voltage and current in order to turn the power device on or off. Engineers and scientists have produced a huge variety of solutions ranging from transformers to optical systems links. Recently coreless transformers have gained popularity as it is now possible to integrate them with driver integrated circuits, [START_REF] Munzer | Insulated signal transfer in a half bridge driver ic based on coreless transformer technology[END_REF][START_REF] Timothe | Design and characterization of a signal insulation coreless transformer integrated in a cmos gate driver chip[END_REF][START_REF] Falahi | Evaluation of commercial soi driver performances while operated in extreme conditions[END_REF]. For some applications especially or when full integration is not practical, it could be advantageous to have a discrete integrated coreless component. This is the first goal of the work described in this paper. More, recent applications involve high operating temperatures (the ambient is over 200°C), where the driver, closely placed to the power core, is stressed at the same time by high voltages and high temperatures. The second goal of the research involved here is the extension of the temperature range of the industrial process that is used to produce the coreless chips.

Coreless transformer for insulating control signals in a power converter at high temperatures

Recent advances have brought to industrial level the coreless technology for the insulation of control signals in an integrated driver chip [START_REF] Munzer | Insulated signal transfer in a half bridge driver ic based on coreless transformer technology[END_REF]. However, there is an interest to develop a discrete coreless transformer. In fact, discrete components require less development efforts than fully integrated systems and permits flexibility in various applications for example. The authors are studying an existing technology designed for for a mass production market in order to evaluate it for an airborne high temperature application specified in table I.

Coreless technology

Coreless transformers are processed using Integrated Passive Device technology (IPD) from STMicroelectronics. It consists of a glass wafer onto which two layers of copper are placed, insulated by a specific resin. It should be noted that the resin is a broad band-sensitive photopolymer named B-staged bisbenzocyclobutene (BCB). It is intended to be used as dielectrics in thin film microelectronics applications. The specifications for the BCB used in our process are given in table II. This polymer was not specially developed for high temperature applications, however the process of reticulation that happens during the initial curing process leads to believe that an extension of the usual temperature limit (125°C to 175°C) is achievable. For this purpose, an endurance test is carried out and described further down. Note that the windings are made of copper and have a square shape, they are built using two layers of metal, see figure 2. The primary winding and the secondary winding are etched on the same metal level, while the second metal level is used to "bring back" the extremum of the coil from the center of the device to the side of the chip. For some applications it is necessary to have the contact pads at the corner of the chip, for improved insulation in the package for example. This implementation is called "single layer" transformer and is noted "TRS". It was chosen over a double layer structure because the parasitic capacitance is less. In the double layer structure, an additional capacitance is introduced by the coils facing each other to form a plannar capacitor.

Coreless design

The design of the coreless transformer is based on system specifications such as maximum frequency and current for the transformer transceiver, maximum mechanical dimensions and the 200°C operating temperature. The coreless transformer is fed with a 5V square wave at 20MHz, this data permits to calculate the peak current that the transceiver has to produce. The integration objective sets the maximal mechanical size. Designing the coreless transformer is basically a three step iterative process. First, usage of a formula, see equation 1, to compute the inductance of a flat square coil according to [START_REF] Sunderarajan | Simple accurate expressions for planar spiral inductances[END_REF], the winding resistance and the mechanical size. The technology description is presented in figure 2. Secondly, the calculus of the peak current for a fixed voltage and frequency. Thirdly, the parasitic capacitance is estimated. The input parameters are : inner diameter din, track width w, track spacing s, number of turns n. Using a modified Weeler inductance equation and an empirical capacitance equation, the output parameters are calculated: track resistance rtrk, transformer's primary inductance lmw and primary to secondary parasitic capacitance capa. These equations are listed in Table IV and the result, an optimized transformer, is presented in Table V. Three constraints are taken into account: mechanical dimensions < 3mm, transceiver drive current < 25mA and parasitic capacitance between primary and secondary coils < 15pF. Many solutions, ranging from 30 turns to 60 turns, have been built with different layout options in a first explorative wafer run. In this paper, the optimal solution is presented, a single layer 30 turn transformer with maximized winding density: minimal allowed track spacing and width. The parasitic capacitance between the primary winding and the secondary winding can be evaluated by considering single layer structure of the transformer. Two wires, primary and secondary are wound side by side producing a wire-to-wire capacitance. The resulting capacitance is calculated using the design equation "capa" from table IV in which the rectangular shape of the wire has been approximated to a circle to match the generic expression of the capacitance of two wires placed side by side.

L mw = µ 0 K 1 n 2 d avg 1 + K 2 f r (1)
for a square inductor: K 1 = 2.34 and K 2 = 2.75 n is the number of turns and µ 0 = 4π10 -7

with

d avg = din + dout 2 and f r = dout -din dout + din (2)
Table IV: Design equations for the integrated single layer coreless transformer. Please refer to figure 2 for the geometrical signification of parameters.

dout =din + 2n(w + s)

davg =(din + dout)/2 len =4 davg n f r = dout -din dout + din rtrk = ρ len w t lmw = µ 0 K 1 davg n 2 1 + K 2 f r d = w + s/2 a = (w + t)/π K 1 = 2.34 K 2 = 2.75 0 = 8.810 -12 ρ = 1/51300000 capa = π 0 len log(d/2a + (d 2 /(4a 2 )) -1)

Electrical characterisation

For the purpose of verification and checking the design equations the transformer is characterized using an impedance analyzer. The primary impedance is studied to determine the frequency range in which the impedance is mainly inductive. It was found to be 100kHz to 20MHz. Below 100kHz the impedance is so low that the signal to noise ratio impairs the measurement. On a practical point of view, there is no interest in reducing the operating frequency of the transformer. What is looked after is, on the contrary, an increase of the carrier frequency to reduce the coil's driving current and to reduce the physical dimensions. The upper frequency limit for the transformer is set by the parasitic capacitances and the coil inductance with defines a self resonant frequency. Because this frequency is related to parasitics and electrical connections, it would not be a good idea to use this mode of operation for repeatability issues. The other limiting factor for the high frequencies is the ability of the transceiver to source and sink current at high frequency. The coils are measured by an impedance analyzer and matched to a simple equivalent circuit model because it is well adapted to low frequencies, lower than 100MHz. An electrical model schematic is proposed in figure 4.

Coupling factor

The coupling factor k is a key parameter and is calculated from two measurements made on the primary coil of the transformer, [START_REF] Fontana | Coreless transformers with high coupling factor[END_REF]. Equation 3 gives the coupling factor value as a function of two inductance measurements made on the primary coil, L oc : open secondary and L sc : short-circuited secondary. Due to the compactness of the chosen technology, the coupling factor is very good, k = 0.9.

k = L oc -L sc L oc (3)
Parasitic capacitance. To determine the parasitic capacitance between primary and secondary coils, the coils are short-circuited and a measurement of capacitance is made, corresponding to the parallel association of C1 and C2, see figure 5(a). The measured capacitance is 16pF, which complies with the global specifications of table I. Because of the symmetry of the transformer, one can assume that the capacitance is evenly spread between C1 and C2, see figure 4.

Winding capacitance. The winding capacitance is determined by measuring the self resonance frequency f sr of the transformer while shorting the insulation between primary and secondary in order to reject the effect of such a capacitance.

C = 1 L eq (2πf sr ) 2 with L eq = 1 -k 2 2(1 -k) L1 (4)
The equivalent circuit becomes two coupled inductors (giving an inductance L eq ) placed in parallel with a capacitor C, see figure 5(b). Again, by using symmetries in the transformer, here, L1 and L2 are identical, one can determine the resulting inductance using equation 4, where L is the primary inductance measured with an unloaded transformer and k the coupling factor already determined. The capacitance C calculated using equation 4 is the equivalent capacitance of C3 and C4 placed in parallel because C1 and C2 have been shorted to experimentally determine the self resonant frequency. Finally, The winding capacitance is 2pF for each coil.

Electrical tests

Measuring electrical parameters is a first step to determine if a component technological solution is valid. Secondly, it is needed to prove that the component is able to provide it's functionality in a practical application. For that, an experimental test board has been developed. In comprises an onboard adjustable oscillator -4 to 40 MHz range -for the carrier signal, a modulator controlled by an external Pulse Width Modulation signal and a bridge coil driver on the primary side. The modulator uses synchronized gating to produces full carrier periods during the on-state of the PWM signal and zero differential voltage during the off-state of the PWM signal. In that way, the inductive coil of the coreless transformer is never excited by portions of square waves and is not submitted to any DC voltage component. On the receiver side, a passive network is connected to the secondary coil, adapting the coreless output to an amplitude modulation detector. Figure 6 shows the measurements made using an oscilloscope on the demonstrator board. The modulated signal has been transmitted successfully through the coreless transformer and the level of the received signal is strong, a 2 V amplitude square wave. This signal is compatible with many detector circuits, from example a re-triggerable one-shot circuit.

High temperature endurance test

The first step in endurance tests is to place the component under a constant high temperature of 200°C. Temperature cycling is another aspect that will be treated in a second step, nevertheless, during the experiment, the coreless transformer has been cycled more than 500 times, every time it was taken out of the oven for the impedance measurement at room temperature. The technology implements glass, copper and an organic matter, BCB. The study focuses on the BCB as it is known that organic materials are more sensitive to high temperatures than metals or mineral compounds. The coreless transformer, as any transformer, has a parasitic capacitance between the primary winding and the secondary winding. The idea is to monitor the evolution of the transformer capacitance during the endurance test. The test consists in placing the samples at 200°C for a long period compared to the initial curing time of the BCB used for the insulation. Measuring the insulation resistance does not seem to be very reliable as oxidation on the pads might occur. Capacitance measurement can be made independent of resistance variations. The increase of capacitance can be explained by two different phenomena: weight loss of the BCB and modifications of the molecular arrangement. The physical basic formula to calculate the capacitance, C, of two flat metal parts of surface, S, separated by a distance, e, with a material of dielectric constant r is: C = 0 r S e with 0 = 4π10 -7 . So, as the copper structure is unlikely to be modified -S remains constant -, the weight loss impacts the volume of dielectric material, resulting in a reduction of the distance, e. The other possibility is a chemical evolution of the molecules that affects the dielectric constant. After checking of the experimental protocol it was found that the BCB of the coreless transformer had been exposed to ambient oxygen resulting in an oxidation at high temperatures. Such a phenomenon is well known and can be avoided using controlled atmosphere airtight packaging or protective overlaying with silicone gels for example. The aging that is observable on figure 7 is due to a lack of appropriate packaging, it will be corrected in the next endurance experiment. Nevertheless, the integrated coreless transformer was proved to withstand high temperatures, it is only the insulation that was degraded by the uncontrolled action of oxygen.

Conclusion

A specific integrated coreless component was designed and fabricated using an industrial production process. It was characterized using a specific simplified model. Electrical measurements gives a magnetic coupling factor of 0.9 and a primary to secondary capacitance of 16pF, which are two key parameters when designing a control signal insulation system for a power converter. During a preliminary aging test, a significant variation of the parasitic capacitance indicates a variation in the insulating material, this was due to an uncontrolled oxygen exposition of the samples. A new test using hermetic packages with gel is programmed in order to verify the possibilities of this technology at high temperatures. Further work encompasses extended endurance tests, implementation of the coreless transformer component in a transmitter-receiver circuit.

Figure 1 :

 1 Figure 1: Bloc diagram of an Integrated Power Core. Insulation in mandatory for both signal and gate driver supply. Coreless transformers are good candidates for the integration of the signal insulation.The insulation transformer is exposed to high voltages and high transients.

Figure 2 :

 2 Figure 2: Technological description of a single layer transformer.

Figure 3 :

 3 Figure 3: Left: photograph of a limited area of the wafer showing the various experimental patterns. Right: one of the tests boards developed for the coreless transformers chips.

Figure 4 :

 4 Figure 4: Electrical model of the coreless transformer with the values of the identified parameters. Primary terminals are pa and pb, secondary terminals are sa and sc.

Figure 5 :

 5 Figure 5: Characterization of the electrical model of the coreless transformer using shorts, some parts of the circuit disappear because the voltage is nulled in grey areas. The impedance measurement takes place between the shorts.

Figure 6 :

 6 Figure 6: Left. The evaluation board implementing the 20MHz modulation, a piggy-back circuit with the coreless sample, a receiver circuit. Right. Oscilloscope measurement showing : Top trace, PWM input signal prior to modulation at 20MHz, 5V amplitude and Bottom trace, the received modulated signal, 2V amplitude. The time base is 200ns/div.

Figure 7 :

 7 Figure 7: Measured normalized capacitance versus the number of hours at 200°C. Three transformer chips are tested, some dispersion occurs with aging. The variation of capacitance is used as an indicator of aging.

Table I :

 I Specifications for the insulation system of control signals for inverters used in airborne applications.

	Parameter	Value	Constraint
	DC breakdown voltage	> 2 kV	Insulating resin dielectric strength and thickness
	dv/dt immunity	> 75 kV/us	Transmitter and Receiver electronics
	Parasitic capacitance	< 18 pF	Insulating resin dielectric constant and thickness
	Low Temperature ambient	-50 °C	Materials and electronics
	High Temperature ambient	+200 °C	Materials and electronics
	Temperature cycling	> 30 000 cycles	Assembly, packaging
	Life span	50 000 hours	Ageing of insulation material and assembly

Table II :

 II Electrical and Thermal Properties of Photo-BCB (CYCLOTENE 4000 resin series)

	Property	Value
	Dielectric constant	2.65 (1kHz -20GHz)
	Dissipation factor	0.0008
	Breakdown voltage	5.3 MV/cm
	Leakage current	4.7 x 10

10 A/cm2 at 1.0 MV/cm Volume resistivity 1 x 10 19 Ω-cm Thermal conductivity 0.29 W/m°K at 24°C Thermal stability 1.7% weight loss per hour at 350°C

Table III :

 III Geometrical limits for copper tracks used in the coreless transformer

	Parameter	Value
	track thickness	6 µm
	minimum track width	10 µm
	minimum etching distance 10 µm

Table V :

 V Dimensions of the coreless transformer computed from the values of the design parameters.

	Transformer reference : TRS-10w30s300di30n
	Design parameter	Value	Dimension	Value
	inner diameter	300 [µm]	inductance	1.2 [µH]
	width	10 [µm]	capacitance	17 [pF]
	spacing	30 [µm]	size	2.6 [mm]
	n	30	peak current 25 [mA]

supported by CATRENE project THOR with SAFRAN and ST-Microelectronics as industrialists partners.


Alaa Hilal

Marie-Ange Raulet

Christian Martin

Christian Martin Magnetic

Magnetic Components Dynamic Modeling With Thermal Coupling for Circuit Simulators

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MAGNETIC COMPONENTS DYNAMIC MODELING WITH THERMAL COUPLING FOR CIRCUIT SIMULATORS

Virtual prototyping is essential in the development of new power electronics devices like transformers and static power converters. Circuit simulators as SPICE and SIMPLORER allow the optimization of complex circuit prototypes by associating models of passive and active components. Magnetic components constitute a major part of electronics devices, therefore accurate modeling of magnetic materials is mandatory in order to predict their realistic behavior under variable operating conditions. In fact nonlinear characteristics of magnetic materials in addition to dynamic and thermal effects have a non-negligible influence on device's performance and must be taken into account in circuit simulations [START_REF] Pr | Simulation of Magnetic Component Models in Electric Circuits Including Dynamic Thermal Effects[END_REF].

This paper takes place in this context by proposing a non-linear dynamic model of magnetic components for use in circuit simulators. It includes the material's nonlinear hysteresis behavior with accurate modeling of winding and core losses in addition to thermal effects that are not taken into account by existing models. The model is based on the principle of separation of static and dynamic contributions as well as Bertotti's theory [START_REF] Bertotti | General properties of power losses in soft ferromagnetic materials[END_REF].

In the interest of precision and in order to be adaptable for different types of magnetic materials, the magnetic component model adopts structural modeling approach. As a consequence the model consists of 3 major blocks as shown in the adjacent figure: a winding responsible for coupling between electrical and magnetic domains using Ampere's and Faraday's laws, a static model to describe the static hysteresis behavior of the magnetic material and a dynamic model to add classical and excess losses in the core. Each of these blocks is described using VHDL-AMS [START_REF] Ashenden G | The System Designer's Guide to VHDL-AMS[END_REF] modeling language due to its multi-domain modeling feature, allowing coupling with a thermal model. The thermal model can be represented by a simple temperature source for static thermal conditions or by an equivalent thermal circuit for self-heating conditions.

The magnetic component model is validated by modeling a Nanocrystalline-core inductor. The appropriate choice of static law able to describe the piecewise linear static behavior of the material is presented. The identification of static and dynamic models parameters is discussed. Thermal effects are investigated, by predicting the model's parameters variation as function of temperature. The effects of frequency and waveform are also studied.


Dominique Bergogne
email: dominique.bergogne@univ-lyon1.fr

Christian Martin

Bruno Allard

El Khalil

Gonzalo Falahi

Picun

Hilal Ezzeddine

Cédric Pintout

High Temperature Discrete Integrated Coreless Signal Insulator

For a few years now, some industrialists have been proposing commercial devices to realize the insulation of control signals in power conversion systems. Those devices have been used widely in the field with entire satisfaction. However, for some applications where extreme temperature requirements must be met, those components may not be adequate. In this paper, a discrete solution is presented using three chips: a transmitter, a coreless transformer and a receiver. The transformer chip is built using a copper on glass technology while transceivers and receivers use Silicon On Insulator. Operation with a Pulse Width Modulated signal is presented, the coreless technology was tested at 200°C.

I. INTEGRATED POWER CORE AND INSULATION

When it comes to implementing an Integrated Power Core (IPC), either as laboratory scale demonstrators or for industrial applications, a major issue has to be solved: insulation of the high voltage power circuit from the low voltage control circuit. The resulting voltage stress is focused at a specific point see figure 1. The on/off control digital signal, present on the primary side, is converted to some kind of voltage and current by the gate driver on the secondary site in order to switch the power device in the inverter leg. Engineers and scientists have produced a huge variety of solutions ranging from transformers to optical links systems, not all of them tuned for integration. Recent advances have brought to industrial levels the coreless technology for the insulation of control signals in an integrated driver chip [START_REF] Munzer | Insulated signal transfer in a half bridge driver ic based on coreless transformer technology[END_REF]. However, there is an interest in developing a discrete coreless transformer, especially to extend the temperature range to 200°C for instance in order to address aerospace applications, or niches, such as down hole drilling. In that case, several stress parameters must be considered, table I lists the major constraints for a coreless transformer implemented in a high temperature IPC and the resulting impact on the system. a) A few comments about table I : The temperature affects directly the materials such as resistivity or magnetic permeability, this is taken into account at design level. High temperatures also accelerates aging, this is very true for organic materials. This paper does not address reliability, however the technologies used have been selected for their high temperature capabilities. The insulation voltage is set by multiplying the nominal DC bus voltage by two and adding a safety margin of 50%, hence 1.5 kV for a 540 V supply. The voltage transients are produced by the inverter leg switches and are evaluated to be 50 kV/us. The footprint is a very important constraint as it affects volume and indirectly mass, two key specification parameters for airborne applications.

II. INTEGRATED CORELESS TRANSFORMER TECHNOLOGY

In this paper, the authors describe an hybrid solution to signal insulation using Silicon On Insulator (SOI) integrated circuits and Integrated Passive Device (IPD). SOI technology is used for the transmitter/receiver chipset and IPD technology for the coreless transformer. The SOI technology is commonly used to extend the temperature range of Silicon integrated circuits, [START_REF] Falahi | Evaluation of commercial soi driver performances while operated in extreme conditions[END_REF]. However, IPD is less common. The IPD Technology developed by STMicroelectronics, see figure 2, is already used in large volumes by major customer worldwide looking for space saving, improved performance, and high standard quality at a competitive cost for Radio Frequency applications. The IPD technology provides superior assembly and test yield on the final application as IPD device performance is lower tolerance compared to discrete Surface Mount Devices. The IPD technology uses glass wafers for a substrate and various materials to integrate capacitors and conductors. For a coreless transformer, integrated capacitors are not implemented. The remaining materials are glass, copper and an adhesive insulator based on Benzocyclobutene (BCB) of which the properties are listed in table II. In [START_REF] Bergogne | Integrated coreless transformer for high temperatures design and evaluation[END_REF], the coreless technology was tested on a laboratory sample 1000 hours at 200°C, the magnetic properties where not affected, but due to the uncontrolled presence of oxygen, the insulation was damaged. Proper industrial packaging should solve this detrimental aspect. The IPD technology provides several means of building a coreless transformer. First, for compact, reduced footprint transformers, the stacked structure is obtained by using both layers of copper to print the windings. The major drawback is an increased inter-winding capacitance which must be as small as possible in order to improve insulation of transients and reduced distance between primary and secondary windings. Secondly, the single layer structure, which is less efficient in terms of uH per footprint, permits to increase the minimum distance between primary and secondary coils, an interesting feature for high voltage insulation and reduced capacitance. In [START_REF] Bergogne | Integrated coreless transformer for high temperatures design and evaluation[END_REF], the design equations based on simple physics and analytical approximations, [START_REF] Mohan | Simple accurate expressions for planar spiral inductances[END_REF] are presented, they permit to estimate the inductance and resistance of the coils and the primary to secondary capacitance of the transformer. The IPD technology is used at its limits in terms of geometry: minimum distance between tracks (spacing = 10 um), minimum winding cross-section (width = 10 um), the transformer is built using the single layer layout, see figure 3. The electrical specifications are identical, the selected design parameters are listed in table III.

III. INDUCTIVE SIGNAL TRANSMISSION TECHNOLOGY

The principle of inductive signal transmission is to transmit an information through two isolated coupled inductors, such as in a transformer built using a magnetic core and two windings.

Depending on the nature of the information, the signal can be directly fed to the transformer or has to be modulated. The widely used On-Off-Keying (OOK) modulation is implemented here. The digital control signal for a power switch presents two states: high and low. The resulting On/Off signal is simply modulated by a high frequency carrier: the on state is coded by the presence of the carrier while the off state is the absence of the carrier. This modulation is relatively safe, the consequence of the loss of signal is the off state and the on state is constantly refreshed by the presence of the carrier frequency. The primary side of the transformer is connected to a transmitter consisting of an OOK modulator and a voltage buffer that should be able to sink and source the current absorbed by the transformer's primary. On the secondary side, the transformer is connected to a receiver that processes the signal in order to output a demodulated signal. Single pulse techniques can be preferred in order to reduce the power consumption, as in [START_REF] Munzer | Insulated signal transfer in a half bridge driver ic based on coreless transformer technology[END_REF]. In a wire wound winding transformer designers have a great degree of freedom to fulfill the voltage insulation and the transients specifications. For integrated transformers, the constraint is higher as insulating layers thickness is set by the technology and design rules. Coreless transformers, [START_REF] Fontana | Coreless transformers with high coupling factor[END_REF], [START_REF] Timothe | Design and characterization of a signal insulation coreless transformer integrated in a cmos gate driver chip[END_REF] do not use a magnetic core which relieves some constraints on the design. For the sake of comparison, a reference design uses a transformer made with a toroid on a board implementing two transceivers. A second design implements coreless chips from a first run (RUN1). The b) Transceiver chipset: the circuit used is a hightemperature, high reliability integrated circuit that implements a dual-channel isolated data transceiver, reference XTR40010. It can be used in any application where there is a need for galvanic isolation of a digital signal. The galvanic isolation is achieved by an external magnetic transformer for each digital signal, this transformer can be coreless, printed circuit board plannar with ferrite cores or wire wound on a magnetic torus for instance. The XTR40010 integrates in a single package 2 transceivers (two full duplex channels). The complete solution is optimized to minimize the size of the transformer, the number of external components, the transmission delay (<120ns) and to maximize the noise margin, even in harsh dV/dt conditions (50kV/us across 2pF of insulating capacitance). It is operational beyond the -60°C to +230°C temperature range. The supply voltage ranges from 4.5V to 5.5V. Data rate up to 2 Mbits/second per channel can be achieved and the transient common mode current immunity is 100mA. The XTR40010 implements OOK (On-Off Keying) modulation, and has a programmable carrier frequency. The maximum carrier frequency is around 20MHz, it can be noted that no external components are needed apart from the transformers.

IV. TRANSFORMER MODEL

A transformer model is determined for system simulation purposes. The primary impedance is studied to determine the frequency range in which the impedance is mainly inductive. It was found to be 100kHz to 20MHz. Below 100kHz the impedance is so low that the signal to noise ratio impairs the measurement. On a practical point of view, there is no interest in reducing the operating frequency of the transformer. What is looked after is, on the contrary, an increase of the carrier frequency to reduce the coil's driving current and to reduce the physical dimensions. The upper frequency limit for the transformer is set by the parasitic capacitances and the coil inductance with defines a self resonant frequency. Because this frequency is related to parasitics and electrical connections, it would not be a good idea to use this mode of operation for repeatability issues. The other limiting factor for the high frequencies is the ability of the transceiver to source and sink current at high frequency. The coils are measured by an impedance analyzer and matched to a simple equivalent circuit model because it is well adapted to low frequencies, lower than 100MHz. An electrical model schematic is proposed in figure 6. The transformer is characterized using an impedance analyzer and several techniques:

•
for the inductive part of the model, standard open secondary/short secondary impedance measurement is used to provide L1, R1 (L2 and R2 are identical to L1 and R1 because the geometry is identical) and the coupling factor, k.

• for the primary to secondary capacitance, C1 and C2, a capacitance measurement is made using circuit (a) from figure 7. Due to the symmetrical design, the primary coil is identical to the secondary coil, identification can be simplified.

• for the capacitive part of the windings, C3 and C4, the resonance frequency is measured using circuit(b) from figure 7.

V. EXPERIMENTAL VERIFICATION

In order to validate the idea of making a digital signal insulator using a coreless transformer and two transceiver integrated circuits, an experimental board has been built implementing the application circuit of figure 5. The oscillogram plot of figure 8 shows the input signal, top trace (DATA I) , the modulated signal and the output signal, bottom trace (DATA 0). The performance is listed in table VI. VI. CONCLUSION A high temperature insulation system is provided using commercially available transceivers and custom made coreless transformers using an industrial process. The coreless transformer was designed to match the transceiver with a minimal footprint (3 mm x 3 mm) which is an improvement over the cored transformer reference design solution. The transmission delay is lower than 170 ns, a figure compatible with high temperature operating converters operating at a switching frequency around 50kHz. Nevertheless, this delay can be taken into account in the digital control system. The proposed solution reduces the transformer footprint and height by a factor of 5 when compared with a transformer using a toroid magnetic circuit.

Fig. 1 .

 1 Fig. 1. Bloc diagram of an Integrated Power Core. Insulation in mandatory for both signal and gate driver supply. Coreless transformers are good candidates for the integration of the signal insulation.The insulation transformer is exposed to high voltages and high transients.

Fig. 2 .

 2 Fig. 2. Cross section of the IPD technology used, showing the two copper layers, the insulating medium and the glass substrate. Courtessy of STMicroelectronics.

Fig. 3 .

 3 Fig. 3. Real design for 1 µH coils. Courtesy of STMicroelectronics.

Fig. 4 .

 4 Fig. 4. Photograph showing the reference design toroid transformer, A, and the coreless transformer chip, B. Also shown on the picture, a size 1205 Surface Mounted Device, C.

Fig. 5 .

 5 Fig. 5. Application circuit for the transceiver ship-set with the transformers. Courtessy of X-Relsemi.

Fig. 6 .

 6 Fig. 6. Coreless transformer model and experimentally identified parameters. Primary terminals are pa and pb, secondary terminals are sa and sc.

Fig. 7 .

 7 Fig.7. Characterization of the electrical model of the coreless transformer using shorts, some parts of the circuit disappear because the voltage is nulled in grey areas. The impedance measurement takes place between the shorts. Due to the symmetrical design, the primary coil is identical to the secondary coil, identification can be simplified.

Fig. 8 .

 8 Fig. 8. Experimental verification of the operation of the transceiver ship-set implemented with the coreless transformers. Courtessy of X-Relsemi.

TABLE I .

 I CONSTRAINTS

	Constraint	Value	Impact
	Temperature	200°C	Insulating material
	Insulation	1.5 kV	Transformer geometry
	Transients	50 kV/us	Transceiver
	Footprint	minimal	Transformer inductance

TABLE II .

 II

ELECTRICAL AND THERMAL PROPERTIES OF PHOTO-BCB (CYCLOTENE 4000 RESIN SERIES) Property Value Dielectric constant 2.65 (1kHz -20GHz) Dissipation factor 0.0008 Breakdown voltage 5.3 MV/cm Leakage current 4.7 x 10 10 A/cm2 at 1.0 MV/cm Volume resistivity 1 x 10 19 Ω-cm Thermal conductivity 0.29 W/m°K at 24°C Thermal stability 1.7% weight loss per hour at 350°C

TABLE III .

 III

	Design parameter	Value	Dimension	Value
	inner diameter	300 [µm]	inductance	1.2 [µH]
	width	10 [µm]	capacitance	17 [pF]
	spacing	30 [µm]	size	2.6 [mm]
	n	30	peak current	25 [mA]

CALCULATED DIMENSIONS OF THE CORELESS TRANSFORMER Transformer reference : TRS-10w30s300di30n

TABLE IV .

 IV KEY PARAMETERS FOR TWO INSULATORS

	Property	Toroid	Coreless RUN 1
	Operating temperature	300°C	> 200°C
	Insulation voltage	> 2 kV	> 1.5 kV
	Insulation capacitance	< 2 pF	16 pF
	Inductance	1.7 uH	1.3 uH
	Footprint	7mm x 7mm	3mm x 3mm

TABLE VI .

 VI MEASURED PERFORMANCE OF THE SIGNAL INSULATOR.

	Parameter	Value
	Rising edge delay	170 [ns]
	Falling edge delay	87 [ns]
	Modulation frequency	24 [MHz]

ACKNOWLEDGMENT

The authors would like to thank Stéphane Martinez from the Atelier de mécanique, Université Claude Bernard, Lyon for the machining of specific equipment for high temperature testing and Pascal Bevilacqua and Abder Zaoui from INSA, Lyon, for their support to produce the experimental circuit boards needed for electrical testing at the Ampere-Lab.

The study presented in this very paper is supported by the European CATRENE CA402 project THOR with ST-Microelectronics and X-Relsemi as industrialists partners.


Magnetic Components Precise Modeling for Power Converters

A. Hilal, M.A. Raulet, C. Martin, F. Sixdenier University of Lyon, University Lyon 1, CNRS UMR5005 AMPERE, Villeurbanne, F69622, France In power electronics applications, magnetic components are often subjected to non-sinusoidal waveforms, variable frequencies and DC bias conditions. These operating conditions generate different losses compared to sinusoidal losses provided by manufacturers. Since virtual prototyping is used to predict and improve system's behavior before realization, losses and behavior prediction of components is required. Circuit simulators and their compatible components models are required. This work is summarized by proposing non-linear dynamic model of magnetic components for use in circuit simulators. It includes the material's nonlinear hysteresis behavior with accurate winding and core modeling. The magnetic component model is implemented in circuit simulation software "Simplorer" using VHDL-AMS modeling language. Waveforms and losses of a powder core inductor in a buck converter application are simulated and compared to measured ones. Index Terms-Dynamic magnetic modeling, DC-DC converters, power losses, simulation, powder core.

I. INTRODUCTION

ower consumption and efficiency have always been of great concern in the development of power electronics systems. The increasing demand of low power, high efficiency devices [START_REF] Calwell | Active mode power supply efficiency: Key issues, measured data and the design competition opportunity[END_REF] forced designers to precisely analysis losses in each component constituting the system. In the design and analysis of systems in general, specifically power converters, virtual prototyping assure time, failure rate and cost reduction [START_REF] Biela | Towards virtual prototyping and comprehensive multi-objective optimization in power electronics[END_REF]. Individual components models exist and are associated together to form a complete converter model. Passive components especially magnetic ones play a key role in power converters [START_REF] Marin | Applications of amorphous and nanocrystalline magnetic materials[END_REF], thus behavior and loss analysis of these components is essential [START_REF] Pr | Simulation of Magnetic Component Models in Electric Circuits Including Dynamic Thermal Effects[END_REF].

In this context our work takes place by proposing a nonlinear dynamic model of magnetic components for use in circuit simulators. It includes the material nonlinear hysteresis and dynamic behaviors with accurate modeling of winding and core losses. The full model is described using VHDL-AMS modeling language and implemented in the circuit simulator "Simplorer". It is then tested for a powder core inductor in a buck converter. The model is validated for different ripple currents, different loads and a wide frequency range (10-100 kHz).

II. MAGNETIC MODEL CONCEPT

Inductors are components found in most power applications and converters. For each point of load application a specific design of these components is required. Considering a buck converter circuit Fig. 1, the magnetic component model would replace the inductor. In the interest of precision and in order to be adaptable for different types of magnetic materials, the inductor model must adopt a structural modeling approach. As a consequence the model consists of 3 major blocks: a winding allowing the coupling between electrical and magnetic domains using Ampere's and Faraday's laws, a static model to describe the static hysteresis behavior of the magnetic material, and a dynamic model to add classical and excess losses in the core. VHDL-AMS language is chosen to describe each block behavior due to its multi-domain modeling feature and since it is supported by several circuit simulators. Considering the middle operating frequency range, parasitic effects are negligible and not taken into account in the model. Different static and dynamic models can be used to describe the behavior of magnetic material. The choice of the model depends on 3 main criteria: the material characteristics, the application and simulation factors like ease of implementation, accuracy and speed of simulation. The static and dynamic models chosen and their parameters identification are discussed in the following sections.

III. MAGNETIC MATERIAL CHARACTERIZATION

The behavior of magnetic components depends mostly on magnetic properties and geometry of core material used. Each material has its specific hysteresis and dynamic behaviors. Hence material characterization is mandatory to predict the appropriate static and dynamic models and their parameters.

Static measurements are performed on a test transformer consisting of primary and secondary coils wound on a toroid powder core. A sinusoidal current is applied to the primary winding, to create a magnetic field H and the flux density is calculated from the secondary voltage measured.

To describe the static behavior of the material, a mathematical model based on a piecewise polynomial function of order n is used. This model is reversible and limited to materials with low coercive field [START_REF] Chailloux | Magnetic behavior representation taking into account the temperature of a magnetic nanocrystalline material[END_REF]. The parameters of the static model are identified from the static measurements using basic mathematical fitting. P Dynamic measurements are performed on the same test transformer under a sinusoidal 30 kHz applied flux density for different induction levels. The aim of these measurements is to study the dynamic losses arising in the material due to relatively high frequency applied flux density and extract the model parameters.

The dynamic model is based on the principle of separation of losses into static and dynamic contributions, as well as Bertotti's theory [START_REF] Bertotti | General properties of power losses in soft ferromagnetic materials[END_REF] assuming that the dynamic loss is the sum of both classical and excess losses. The total magnetic field is the sum of static field due to hysteresis and dynamic fields due to eddy currents and wall motion effects.

IV. BUCK CONVERTER APPLICATION

In many power applications, magnetic materials are excited with non-sinusoidal waveforms. This provokes different losses compared to those provided by manufactures based on sinusoidal excitation [START_REF] Boglietti | Predicting iron losses in soft magnetic materials with arbitrary voltage supply: An engineering approach[END_REF]. DC bias has also a significant effect on losses In order to investigate magnetic components behavior in power applications, a 40 W buck converter is realized. The circuit design allows variable voltage, frequency and load. Inductor used in the circuit is the same powder core previously characterized with 30 turns copper wire.

To measure precisely magnetic losses, a small shunt is added in series with the inductor and 10 secondary turns are wound to the same core. The shunt allows precise current measurements, while open secondary side allows voltage measurement excluding coil losses. Knowing the primary current and secondary voltage, iron losses are calculated using Furthermore simulated iron losses for different induction levels are compared to measured ones in the 40 to 100 kHz frequency range. Results are shown in Fig. 10. We note that the losses are predicted using a single dynamic parameter "α" identified from sinusoidal measurements. Experiments confirm model's loss prediction accuracy with a maximum error of 3%.

Fig. 1 .

 1 Fig. 1. Buck converter with the magnetic component structure.

Fig. 9 .

 9 Fig.9. Measured and simulated inductor voltage and current at f=50 kHz.

Fig. 10 .

 10 Fig. 10. Measured and simulated core losses. V. CONCLUSION AND PERSPECTIVES In this paper the behavior of a power inductor in a widely used power converter topology is studied. Development of a magnetic component model for use in circuit simulation is presented. Simulations of a buck converter including the proposed model are compared to measurements. The magnetic component model allows precise prediction of core and winding losses. Simulated inductor current and voltage correspond to measured ones. Model's parameters are extracted from magnetic material characterization under sinusoidal excitation. Results are in good agreement for different induction levels and a wide frequency range.


PhD student; F Neveu

Doctor C Martin

Professor ; B Allard

Review of high frequency, highly integrated inductive DC-DC converters

This paper will review the state-of-the-art of high-frequency, highly integrated, inductive, low power DC-DC converters. This study aims to bring out the actual trade-offs between efficiency, level of integration, conversion ratio, technology … The analysis will focus on the electrical and the physical/technological aspects of DC-DC converters. The context of this study is the design and manufacturing of a high frequency (200 MHz), highly integrated DC-DC converter, based on the ultimate association in 3D of an active die to an interposer of passive devices.

Introduction

DC-DC converters are widely used in portable electronic devices. The need for integration of these converters comes from their actual significant area impact on the PCB of embedded devices. As the main area of a standard DC-DC converter is occupied by passive elements (inductors and capacitors), one way to reduce their footprints is to increase the switching frequency, leading to reducing the required values. Increasing the frequency will have a negative impact on switching losses. The state-of-the-art has been build upon 22 of the most significant papers presenting physical implementations and chip measurement of inductive converters. Capacitive converters are omitted because of their actual power density, incompatible for output power of 500 mW in few square millimeters. No references could be included for the sake of place.

State of the art

Electrical analysis of DC-DC converters

Populated space is represented in Figure 1. All values are extracted from papers by taking the electrical values when the efficiency is explicitly given by the author -in some papers, 2 or more points are reported. In this plot, the Xaxis is the switching frequency (logarithmic scale) of the converter and the Y-axis is the efficiency. The color of the dots represents the converter ratio (output voltage divided by input voltage). The diameter of the dots is proportional to the output power of the converter. The cross represents the target of a recently started design project. Many comments can be drawn from this landscape to highlight the challenges and trade-offs for higher switching frequency.

-When the frequency is kept constant, the efficiency decreases if the converter ratio decreases [Blanken08]. -For all converters listed, frequency is above 10 MHz, and efficiency is below 90 %. -At really high frequencies (greater than 200 MHz), the efficiency drops drastically. -Only few converters present a low conversion ratio: in most converters, output voltage is close to the input voltage.

-The vast majority of converters have an output power of approximately 500 mW.

Figure 1 Electrical landscape of high frequency inductive DC-DC converter

State-of-the-art addresses a reasonable range of switching frequencies. The factors that impact mostly the efficiency are the frequency -as predicted by analytical modelsand the conversion ratio. More comments and conclusions will be given in final paper based on other landscape views.

Missing elements in this landscape are mainly converters with a lower conversion ratio.

There is also no converter reaching 90 % efficiency. Some are quite close, but 90 % seems to be a difficult target to reach. -When scaling down technology, there is no impact on total size of the converter. State-of-the-art shows that scaling down technology and/or reducing input voltage have a positive impact on efficiency. Area is not dependent on these parameters. It is mainly impacted by output power and switching frequency (passive sizes). More comments and conclusions will be given in final paper based on other landscape views. There is no converter handling a high input voltage at a small technology node. Technology nodes under 45 nm are unexplored. And high efficiency converters with high input voltage are still missing.

Physical and technological analysis of DC-DC converters

Overcoming roadblocks

The design goal is a DC/DC non-isolated converter 3.3 V to 1.2 V (ratio is 0.36), exploring the 200 MHz switching frequency. The output power of the converter will be around 500 mW. The efficiency target is 90 %. The converter will be implemented in 40 nm technology.

The active area target is to be less than 1 mm 2 and the total area less than 5 mm 2 .

Passive integration

The converter will use high density trench capacitors, and high performance "racetrack" inductors. Passive and active chips will be stacked, using a 3D design approach and manufacturing. This design approach enhances passive performances and limits parasitic losses.

Active integration

Active design will be made in 40 nm CMOS technology. Nominal technology voltage is 1.2 V. This technology contains high voltage switches (2.5, 3.3 and 5 V), but first simulations will show that their parasitic capacitances don't allow reaching 90 % efficiency at 200 MHz using a standard power stage (Figure 3). Regular switches will be used, using a cascoded power stage (Figure 4). First simulations have shown a significant improvement in efficiency (from 75 % with standard power stage to 85% with cascoded power stage). This structure will be extensively analyzed through simulation in final paper.

A circuit tape-out is scheduled in September allowing for experimental results at time of the conference.

Converter topology and control

Another way to improve efficiency of a DC-DC converter is to use an efficient topology. Many topologies are available for DC-DC conversion; the paper will present an overview of relevant topologies and an evaluation in terms of efficiency. Topologies presented in the state-ofthe-art are mainly standard buck and some multi-phases.

Conclusion

State-of-the-art analysis has shown design objectives and highlighted design challenges. It also provides some ideas to overcome roadblocks.

5

Figure 2

 2 Figure2is a representation of the DC-DC converters using some physical and technological parameters, combined with input voltage and efficiency. The X-axis is the technology node (categorical scale). The Y-axis is the input voltage of the converter. The color of the dot represents the efficiency, and the size of the dot is

Figure 2

 2 Figure 2 Physical and technological landscape of DC-DC converter

Figure 3 Figure 4

 34 Figure 3 Standard power stage

Acknowledgements

This work is supported by the European Commission through the Seventh Framework Programme (FP7), under the project grant PowerSWIPE n°318529.


Rémi Perrin
email: remi.perrin@insa-lyon.fr

Dominique Bergogne

Christian Martin

Bruno Allard

GaN Power Module with High Temperature Gate Driver and Insulated Power Supply

Keywords: GaN, Dedicated Driver, High-Temperature, Power-Supply. Coreless Coreless Transformers VBus VBus Pwm DriverH

Emerging GaN power switches show advantages for integration in power modules at high temperature and/or high efficiency. These modules are good candidates for embedded power converters in harsh environment such as three phase inverters for Electro-Mechanical Actuators (EMA) in the vicinity of internal combustion engines. The power range is usually within 1 to 5 kW, extending sometimes up to 50 kW, using a high voltage DC bus (HVDC) that is usually comprised between 200 V and 600 V. For aeronautical applications, GaN power switches could challenge SiC transistors for their high switching speed, hence reduced switching losses, therefore lower embarked mass. For automotive applications, it is the relative promise for lower cost per Amp that is pushing this technology up. This is why a project joining GaN device conception, power module development and gate driver optimization using high temperature technologies was set-up. This paper presents the first practical results: a functional GaN power inverter-leg driven by a specific high temperature gate driver with signal and power insulation. This building block requires an auxiliary DC supply with a input voltage of 14 V or 28 V and an external PWM control signal. Current rating is 20 A and breakdown voltage is 200 V.

Introduction

The trend of electrification in Aerospace applications requires both high temperature and high frequency operation to achieve high power density for the future power converters. This implies that power modules in such converters need to operate at very high ambient temperatures, e.g. 200-250 °C, package parasitics must be as low as possible, switching frequencies are in the 20kHz to 200kHz range. Moreover, the GaN technology has emerged as promising for high frequency, high efficiency and high density power conversion due to a better figure of merit [START_REF] Ying | Device Selection Criteria -Based on Loss Modeling and Figure of Merit[END_REF][START_REF] Colino | Fundamentals of galium nitride power transistors. epc-co.com[END_REF][START_REF] Roberts | Integrated gan power modules, gan systems inc[END_REF][START_REF] Mcdonald | Ir's ganpowir and the inherent performance advantages of gan-based hemts[END_REF].than comparable Si and SiC transistors. A progressively larger number of GaN devices have been manufactured for a large field of applications from low power voltage regulators to high power infrastructure base-stations. The switching frequency has been continuously increased to reduce passive component size and to increase power density. The work presented in this paper aims to deliver a functional prototype of driver and power supply for a power module implementing normally-on High electron Mobility GaN Transistors (HEMT) in high temperature environment. The normally-on issue of power switches is not dealt with in this paper, previous work on SiC normally-on transistors have addressed this [START_REF] Dubois | Ultrafast safety system to turn-off normally on sic jfets[END_REF][START_REF] Bergogne | Towards an airborne high temperature sic inverter[END_REF][START_REF] Dubois | A high temperature ultrafast isolated converter to turn-off normally-on sic jfets[END_REF][START_REF] Khalil El Falahi | High temperature anti short circuit function for normally-on SiC JFET in an inverter leg configuration[END_REF][START_REF] Bergogne | An Airborne High Temperature SiC Power Converter for Medium Power Smart Electro Mechanical Actuators[END_REF][START_REF] Risaletto | A 200 • c safety system at power-up of normally-on sic jfets inverters[END_REF].

Prototype GaN Module

The GaN transistors come from the first run of HEMT devices provided by CEA-LETI laboratory, France. These test vehicles have been used to validate the process technique and to push forward experimental work on GaN. This power module is built with 200 V -20 A -30 mOhms GaN HEMT from CEA-LETI and 1200 V -50 A SiC Schottky diode (ref: 5SLY12E1200-5YA-1681-00 from ABB). Direct-bonded-copper technology (DBC) is used and GaN dies are brazed using a 63Sn/37Pb alloy.

Static characterizations

The scope of this paper is to provide guidance to design engineers and to assess the progress made on our project. Precise characterization of the HEMT static behavior is not addressed here, one practical reason is that the components used are the firsts to be tested on a program where improvements are made for each run of devices. More, for the power converter designer or the application engineer, power switches are firstly described by their gate threshold voltage,Vth, and by the on-resistance, RdsON, (static parameters), then by their switching speed and losses (dynamic parameters). The threshold voltage is an input for the gate drive circuit and the on-resistance permits to evaluate the voltage drop across the conducting switch, hence calculate the conduction losses. Firstly, the module is characterized under various temperatures up to 200 °C. Figure 3 and figure 4 show the temperaturedependence of static characteristics (Vth and RdsON). During the test, the module's substrate temperature is monitored with an external thermocouple, and is regulated by a hotplate. The test is set so that there is no significant self-heating, so the substrate's temperature is very close to the chip temperature. The threshold voltage is determined using two different techniques : first a standard transconductance curve is plotted and the threshold voltage is extracted, secondly, during the inverter leg switching operation, the value of the gate voltage during the transients (also known as the Miller plateau) permits to determine the threshold voltage. Both techniques provided the same values. Finally, the temperature dependency of Vth is plotted in figure 3. On the temperature range, the threshold voltage temperature dependency is almost linear and is -10 mV/°C. The second parameter is the onresistance, it is measured using a 1 A current pulse and measuring the voltage drop.

Switching characterizations

The switching test provides useful information on the module such as the influence of parasitic elements, switching speed or power losses. However, switching power losses measurements would not be relevant because the Power Module Package was not optimized for switching losses reduction. The internal assembly uses wire bonding and simple metal frame to make the electrical connections, introducing an important stray inductance in the power path that impacts the switching behavior. However, the gate charge specification is a key parameter for the gate driver designer as it sets the power consumption of the gate driver for a given operating frequency. For this test the module is driven by a -6 V gate voltage and a 2 Ohms gate resistor. The measured gate voltage turn-On and turn-Off in figure 5, show the energy necessary to bias the HEMT gate. It is also an experimental technique to determine a mean value of the gate capacitance, a parameter used to design the gate driver. With this HEMT module, the measured mean gate capacitance value is 1 nF.

Gate driver for GaN devices 2.1 Specifications

The specifications for the driver are partially set by the gate properties of the GaN transistors, especially the threshold voltage. The comes power consumption, board space, etc. We have chosen to use commercially available circuits and engineering samples for our project. There are several suppliers of commercial high temperature integrated circuits, one of them is situated near our laboratory, X-Relsemi, http: //www.x-relsemi.com/. The isolated gate driver is implemented with a XTR40011 transceiver and a XTR26011 driver. The baseline driver design implements ferrite cores from Ferroxcube (TC 6/4/2) ensure the data signal insulation. An improvement to increase the driver density is to replace those cores by coreless transformers, [START_REF] Rodriguez | Simulation and characterization of gan hemt in high-frequency switched-mode power converters[END_REF]. Characteristics of the driver are summarized in table 2. The XTR26011 offers the possibility to imple- ment different protections. The Under-Voltage-Lock-Out (UVLO) of the driver IC has been set to -5.5 V, because this is just over to the threshold voltage of the HEMTs at 200°C. The short-circuit protection, called DESAT, has been adjusted for a drain to source voltage of about 3V, this value is chosen according to the application and thermal limits. An interesting function specific to GaN devices is implemented, a gate circuit protection : in case of a gate to source short circuit, the driver decrease the output current and a flag turnsoff. This functionality, coupled with current regulation of the power gate supply, gives a safe system against over-current and overshoot voltage. Nevertheless, the system designer has take into account the failure of the power device, but the gate driver board remains safe. A linear post regulator will be used to provide a tighter tolerance, lower than 2%.

Insulated Power supply

In figure 7, the inductance of the input filter and the nanocrystalline transformer (two clear disks on the picture) are the largest components. They are both packaged using PEEK to withstand high temperature operation.

Moreover, we use NPO series ceramic capacitor from SRT-Ceramique, http://www.srt-mc.com/, for the input-filter.

Figure 8 shows the output voltage variation and duty-cycle variation vs. current output at ambient temperature. The quasi-regulation of the output voltage reaches less than ±8% accuracy. We can observe that the PWM controller adjusts correctly the dutycycle ratio for different load change. In figure 9, a high-temperature test is made at the nominal output current, (200mA), up to 200°C to plot the flyback output voltage variations. The performance is mainly determined by the PWM controller using the feedback loop. The test on the flyback converter shows an output voltage variation of about +1.8% in the temperature range, which is within the specifications for the gate drive.

Gate Driver Voltage Regulation

The HEMT gate might be damaged by over-voltages, this is why the tolerance on the gate voltage is set to 5%. The quasi-regulation implemented in the flyback converter has some drawbacks like a poor opal regulation. A post-regulation has been added to improve the voltage stability of the driver supply and to control tightly the gate voltage. A voltage linear regulator is proposed by X-Relsemi (ref. XTR75011) providing a 1% tolerance. However, the maximum regulated current is 50 mA. So, in order to increase the output current up to the specifications (200 mA), a common current booster circuit, as depicted in figure 10, is implemented. The principle is simple : a series resistor (R1) is placed at the input of the integrated voltage regulator. As the output current increases, the voltage drop across the resistor increases. This voltage drives an external P-MOSFET (M1) so that, when the gate threshold is reached, the transistor diverts as much current as needed to keep the voltage drop in the series resistor close to the gate threshold voltage. In that way, the voltage regulator integrated circuit (XTR75011) is operated at a constant current and the MOSFET supplies any value of current higher than that constant current. Note that this solution boosts the output current capability of the voltage regulator chip but does not provide any significant extension of the input voltage handling. To reach temperatures up to 200°C, this transistor must also be a high temperature device. The XTR2N0525, a P-MOSFET from X-Relsemi, has been chosen. put current range of 0 mA to 800 mA, well over the specified 200 mA. The voltage variation is 0.5%, well within the specifications. Figure 12 represents the effect of temperature on the output voltage. For this test, the current boosted regulator of figure 10 has been heated up to 200°C, with an input voltage of 16 V and an output current set at 200 mA. Temperature has little effect on the precision which is close to 0.5%, well within the specifications. To conclude with, the post-regulation proposed in this section permits to reach the gate driver supply specifications up to 200°C.

Insulation of control signals

Control signals sets the power module switches's states. This on/off digital signal comes from some sort of controller, at low voltages and has to be converted and applied to the gates of the power switches. In an inverter leg, such as the one implemented in the module, insulation is mandatory due to high voltages and separated voltage references. Engineers and scientists have produced a huge variety of solutions ranging from transformers to optical links systems. Recent advances have brought to industrial levels the coreless technology for the insulation of control signals in an integrated driver chip. However, there is an interest in developing a discrete coreless transformer, especially to extend the temperature range above 175°C.

Coreless technology

Coreless transformers are processed using Integrated Passive Device technology (IPD) from STMicroelectronics. It consists of a glass wafer onto which two layers of copper are placed, insulated by a specific resin. It should be noted that the resin is a broad band-sensitive photopolymer named B-staged bisbenzocyclobutene (BCB). It is intended to be used as a dielectric material in thin film microelectronics applications. This polymer was not specially developed for high temperature applications, however the process of reticulation that happens during the initial curing process leads to believe that an extension of the usual temperature limit (125°C to 175°C) is achievable. A preliminary endurance test at 200°C is presented further down in this paper. Note that the windings are made of copper and are built using two layers of metal. The primary winding and the secondary winding are etched on the same metal level, while the second metal level is used to "bring back" the extremum of the coil from the center of the device to the side of the chip. For some applications it necessary to have the contact pads at the corner of the chip, for improved insulation in the package for example. This implementation is called "single layer" transformer and is noted "TRS". It was chosen over a double layer structure because the parasitic capacitance is less. In the double layer structure, an additional capacitance is introduced by the coils facing each other to form a planar capacitor. In [START_REF] Bergogne | Integrated coreless transformer for high temperatures design and evaluation[END_REF], the authors describe the design of the coreless transformers and describe the equivalent model.

Signal transmission through coreless transformers

A demo board supplied by X-Relsemi was used to test the coreless transformers. The original Ferroxcube cores are replaced by the coreless transformers.

In figure 14 one can observe the input PWM signal, the output of the transceiver modulation, the output of the coreless transformer and finally the demodulated PWM signal. The transmission delay is impacted by the modulation/demodulation technique. The experimental date gives a mean delay od 300 ns. Conclusion. The coreless transformers are compatible with the X-Relsemi circuits.

Coreless transformers at 200°C

In a previous paper, [START_REF] Bergogne | Integrated coreless transformer for high temperatures design and evaluation[END_REF] endurance tests on the coreless chip had been performed at 200°C and an important degradation was observed. It was caused by oxydation of the insulation layer as no specific coating was used. In recent tests, the coreless chips have been coated with Parylene and the preliminary results are presented in figure 15. The parameter used to es-Figure 15: Relative capacitance evolution with in blue, the preliminary endurance test without Parylene, in orange the test with coated Parylene. The measurement error is estimated to be less than 5%, which corresponds to the height of the symbols used in the diagram. timate the ageing is the parasitic capacitance between the primary and the secondary windings of the coreless transformer. It can be observed that for coated transformer, there is no significant degradation. A preliminary conclusion is that the proposed coreless transformers withstand a temperature of 200°C.

3 First experimental results of the power module with the gate driver and power supply

The GaN HEMT power module is connected to the gate driver powered by the flyback converter with post regulation. At the time of writing, the module has not been tested on the full stated power range (200V, 20A) partly because of packaging issues and also because we are experimenting on a single sample. We have used a derating of 40% for the switched current (12A) to circumvent a thermal path flaw in the experimental package. The voltage derating is 70% to take into account overshoots. This value is acceptable in comparison to industrial deratings in the order of 50% to 60% for commercial power switching components. The first experimental results validate the system functions and shows some limits of the power module packaging. Figures 17 and18 Because the HEMT is a charge controlled device, that is, the driver must supply the gate a fixed quantity of electric charge in order to bias the device, the gate resistor the switching speed. This effect is plotted in figure 16. A maximum 2.4 kV/us dV/dt was observed during this test. It is very to low to what was expected (around 38 kV/us [START_REF] Rodriguez | Simulation and characterization of gan hemt in high-frequency switched-mode power converters[END_REF]), this explains by the not optimized packaging of the GaN inverter leg that impacts particularly the gate inductance and the built-in gate resistor of the driver (1.2 Ohms).

At the time of writing, generation 2 of GaN HEMT are produced and a new package is being designed.

Conclusion

This paper presents a functional GaN power inverterleg module driven by a specific high temperature gate driver with signal and power insulation. Packaging materials and active components are selected and tested to work up to 200 °C. The signal insulation was realized using a coreless transformer and gives good results. It is further pointed out that, due to the large stray inductances from the power terminals and from the gate terminals the expected switching speed was not met. This paper is thought to stimulate further experiments and serve as a start study for GaN high temperature power applications.

Figure 2 :

 2 Figure 2: High Temperature GaN inverter leg Power Module. Module property of CEA-LETI.

Figure 3 :

 3 Figure 3: Temperature dependence of the threshold gate voltage of GaN HEMT's.

Figure 4 :

 4 Figure 4: Temperature dependence of the drain to source resistance at null gate voltage and 1 A drain current.

Figure 5 :

 5 Figure 5: Gate voltage and gate current during turn-on and turn-off states.

Figure 6 :

 6 Figure 6: Picture of GaN driver board with 3 magnetic cores for signal insulation compatible with coreless transformers.

Figure 7 :

 7 Figure 7: Picture of the Insulated Flyback power supply with two quasi-regulated outputs. A post linear regulator is used, but it is not visible on this view.

Figure 8 :

 8 Figure 8: Output voltage and Duty-cycle variation vs. Current output.

Figure 9 :

 9 Figure 9: Temperature dependence of the flyback output voltage.

Figure 11 describesFigure 10 :

 1110 Figure 10: Schematic of current boost regulator (drawing courtesy of X-Relsemi).

Figure 11 :

 11 Figure 11: voltage drop vs. output current.

Figure 12 :

 12 Figure 12: Output voltage vs. Temperature.

Figure 13 :

 13 Figure 13: Equivalent model of the coreless transformer.

Figure 14 :

 14 Figure 14: Oscilloscope plot showing from top to bottom: input PWM signal (500 kHz, 50% duty-cycle), Modulated signal trough transformer (12 MHz), recovered data signal at the receiver's output and gate voltage output.

  display some of the switching behavior of the module. Ringing is visible producing a voltage overshoot unto 80 V. Figure17shows the ability of the module to switch 12A.

Figure 16 :

 16 Figure 16: External gate resistance driver impact on dV/dt (Vbus=60 V Id=1 A).

Figure 17 :

 17 Figure 17: Turn-Off. Drain voltage for different switched drain current values (Rg=1.8 Ohms).

Figure 18 :

 18 Figure 18: Turn-On. Drain current and different switched drain current values (Rg=1.8 Ohms).

Table

Table 1 :

 1 Experimental GaN power Module specifications. PEEK stands for PolyEther Ether Ketone

	Item	Parameter
	Base plate	AlN-Cu
	Top lid	PEEK
	Max voltage	200 V
	Rated current	20 A
	Gate charge	7 nC
	Gate capacitance	1 nF
	Threshold voltage -3.2 V @ 25°C

Table 2 :

 2 GaN driver board specifications.

	Item	Parameter
	Technology	SOI
	Temperature range	-60°C to +200°C
	Gate driver supply voltage	6 V
	Gate voltage tolerance	5%
	Peak output current	3 A
	Static power consumption 105 mW @ 25°C
	Gate resistor	adjustable
	Frequency range	up to 300 kHz

Table 3 :

 3 Insulated flyback converter specifications.

Acknowledgments

This paper is supported by the MeGaN project (French government founded PSPC project for a GaN Electronic Module, named "MEGaN", approved by MOVEO and MINALOGIC innovation centers). The acknowledgements would not be complete without a particular attention to the academic engineering and technical support from Pascal Bevilacqua and Abder Zaoui from Ampere-lab. The prototypes would have not been possible without the contribution of X-Relsemi for the supply of engineering samples. The coreless transformers used for the prototypes where produced within the European THOR. (THOR : a European founded project within the CATRENE frame, supported by Euripides, THOR stands for "Striking Technologies for Power"). May Nicolas Quentin and Sébastien Larousse, PhD students at Ampere Laboratory, find here my sympathy for their direct and indirect support to this work.