Cyril Buttay
email: cyril.buttay@insa-lyon.fr

Bruno Allard

Raphaël Riva

Silver sintering for power electronics integration

à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

I. INTRODUCTION

In the last few years, silver sintering has become a very attractive alternative to soldering in power electronics, and is now used in industrial processes [START_REF] Göbl | Low temperature sinter technology Die attachment for automotive power electronic applications[END_REF]. Advantages of silver sintering include high thermal and electrical conductivities [START_REF] Bai | Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection[END_REF], compliance to RoHS directives, low process temperature [START_REF] Wang | Low-Temperature Sintering with Nano-Silver Paste in Die-Attached Interconnection[END_REF] and high reliability [START_REF] Knoerr | Power Semiconductor Joining through Sintering of Silver Nanoparticles: Evaluation of Influence of Parameters Time, Temperature and Pressure on Density, Strength and Reliability[END_REF].

However, the vast majority of the research activity focuses on attaching power semiconductor dies only. Among other uses of silver sintering, one could cite topside contact [START_REF] Mertens | Top-Side Chip Contacts with Low Temperature Joining Technique (LTJT)[END_REF], or filling material for 3D integration [START_REF] Ning | A Novel High-Temperature Planar Package for SiC Multi-Chip Phase-Leg Power Module[END_REF]. In this paper, we propose to demonstrate the advantages of silver sintering for power electronics integration through two examples: in the first example, components with various packages (gate driver, passives) are mounted directly in the power module, taking advantage of the high temperature capability of silver sintering. In the second example, power dies are attached on both sides using silver sintering. As silver does not melt during the process, both sides can be attached successively without any loss of accuracy. This would not have been possible with soldering. Thanks to this solid state process, it is possible to process all the attaches simultaneously or successively [START_REF] Stockmeier | SKiN: Double side sintering technology for new packages[END_REF].

II. FUNCTIONNAL INTEGRATION

In addition to the power semiconductors, some commercial power module include peripheral functions: temperature monitoring, measurement of the current, or integration of the gate driver circuits [START_REF] Zurnaci | MiniSKiiP IPM -Intelligent Power Modules Family -Technical Explanations[END_REF]. The integration of the gate drivers is especially desirable for SiC or GaN devices to take advantage of their switching speed by reducing the impedance of the gate circuit.

The power module visible in figure 1 integrates two SiC JFETs (to form a half bridge structure), along with their respective gate driver IC, and some passives (decoupling capacitors, gate resistors, etc.). All components were attached in a single step, using a pressure-assisted silver sintering. A presentation of the circuit diagram of this power module, with a special focus on the custom-designed gate driver IC is given in [START_REF] Falahi | High temperature, Smart Power Module for aircraft actuators[END_REF]. This gate driver IC (as many commercial drivers) is manufactured using a Silicon-On-Insulator (SOI) technology, which reduces dramatically the leakage current of a junction compared to standard bulk silicon. Thanks to this lower leakage current level, SOI gate driver ICs can also operate at a higher temperature [START_REF] Falahi | High temperature anti short circuit function for normally-on SiC JFET in an inverter leg configuration[END_REF].

For fast GaN and SiC power devices, it is preferable to reduce the distance with the gate driver, to reduce the parasitic inductance. Ideally, the gate driver ICs should be located directly near to the power devices, which requires them to sustain the same temperature as the power devices. This is possible with SOI gate drivers, providing their packaging can also sustain the high temperature. Decoupling capacitors are also required to supply the gate driver during switching.

Here, we use high-temperature-rated X7R ceramic capacitors.

A sintered-silver attach can in theory operate up to the melting point of silver (961 °C). Providing the parts to bond have a suitable metal finish (for example silver), they can be bonded using silver sintering. In the module from figure 1, all parts (gate driver, SiC JFET dies, decoupling capacitors and gate resistors) are bonded this way. They all have a silver or palladiumsilver finish. To achieve better attach, some pressure (≈ 1 MPa) was applied on the assembly during sintering. Because of the difference in height among the various components, a compliant silicone layer (≈1 cm thick) was placed between the components and the top platen of the sintering press. This provides a quasi-isostatic pressure [START_REF] Bai | Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection[END_REF].

For testing, the half bridge from figure 1 was attached to a 50 Ω resistive load and mounted on an aluminium block equipped with a cartridge heater. The temperature was gradually increased up to 310 °C. The corresponding current and voltage waveforms at the output of the half bridge are visible in figure 2. At 315 °C, the gate drivers stopped, but they were able to resume operation after cooling-down.

III. 3D INTEGRATION

Another packaging approach is visible in figure 3. Here, only the power semiconductor dies are considered, and the objective is to provide them with an improved thermal management. Although they can operate at a temperature exceeding 300 °C, the SiC JFETs are nonetheless sensitive to thermal runaway [START_REF] Buttay | Thermal Stability of Silicon Carbide Power JFETs[END_REF], and the power they dissipate must be properly evacuated.

Dual-side cooling is an attractive solution to reduce the thermal resistance between a die and its environment. Several solutions have been presented previously [START_REF] Schulz-Harder | Review on Highly Integrated Solutions for Power Electronic Devices[END_REF], and they usually rely on soldering the dies on both sides to ceramic substrates. This requires two solder alloys, one to attach the dies to a first substrate, and a second alloy, with a lower melting temperature (to prevent the first alloy from re-melting), to attach this assembly to a second substrate. As a consequence, the first alloy is required to have a high melting temperature (e.g. AuGe, with a melting point of 361 °C). Silver sintering is an attractive replacement for soldering: as no liquid phase is involved in the sintering, and as the melting point of silver is much higher than the sintering temperature (961 °C vs. 240 °C), the first joint is not affected when performing the second. This low-temperature process can therefore be used for the entire module. Furthermore, the positioning accuracy of the die is better with silver sintering, as it cannot move during the thermal processing. With solder, the wetting forces occurring during the reflow may result in displacement of the die. This is sometimes desirable (self-alignment feature for flip-chip bonding), but in our case, we prefer to rely on proper initial alignment.

1) Assembly of the structure: The module visible in figures 3 and 4 relies on two DBC substrates with custom etching of the copper layers: this copper layer must have protruding features that match the layout of the dies, to provide an electrical contact with the pads of the die without creating short circuits. This is presented in figure 5.

We developed an etching process to achieve the high etching resolution required by the SiC JFET dies (for example 200 µm between gate and source) despite the thick layer of copper (300 µm). Indeed, such resolution is beyond the design rules of DBC manufacturers. This custom etching process is presented in figure 6: First, a blank DBC substrate is coated with a photosensitive resin (MC Dip Coating, Microchemicals). This photosensitive resin is patterned to form the protruding parts (fig. 6-1b), and the substrate is etched (fig. 6-2) using ferric chloride in a spray etcher (≈10 min). This results in a half-way etching, where about half of the copper thickness is removed in the exposed areas.

The substrate is cleaned, and coated with a new layer of photosensitive resin. This resin is patterned to form the actual tracks of the circuit (fig. 6-3b). However, it was found that this resin layer does not provide sufficient protection for the sharp edges of the protruding features, because of surface tension effects. Therefore, a layer of photosensitive dry film (Dupont Riston PM275) is laminated on top of the resin, and patterned using the same layout (fig. 6-4b). This film covers the edges properly, but is too thick to conform to the vertical surfaces of the copper ("tenting effect"). Therefore, both photosensitive material complement each other to provide complete masking of the copper area to be protected.

The second etching process (fig. 6-5) is then performed, again using ferric chloride in a spray tank (≈10 min). The substrate is then cleaned (acetone to dissolve the photosensitive materials), and the individual tiles are singulated using a high precision saw (disco DAD 3220).

Once the DBC tiles are manufactured, the sandwich structure can be assembled. The assembly workflow is depicted in figure 7. First, some solder paste is stencilprinted on the substrate that will contact with the gate and source of the dies. The silver paste (Heraeus LTS 117 O2P2) contains silver microparticles, and is deposited using a 50 µm-thick stainless-steel stencil. The paste is then dried for 5 minutes at 85 °C. This short drying time is sufficient to make the paste much more viscous (so it will not flow once the dies are placed on top), while keeping some tackiness (so the dies will not move once placed on the silver paste).

The dies are SiC JFETs from SiCED, on top of which a PVD Ti/Ag metallization was deposited using a metal mask, as their standard aluminium topside finish is not suitable for sintering. These dies are then placed (fig. 7-3) using a JFP Microtechnic PP-One die bonder, which has around 100 µm positioning accuracy. The populated DBC tile is placed on the platen of a custom-made sintering press, and submitted to the sintering profile: 30 min at 85 °C for complete drying, followed by a 240 °C, 30 min sintering step. During the sintering step, some pressure is applied to assist the sintering (2 MPa, corresponding to a force of 20 N approximately). Some silver paste is then stencil-printed on the remaining DBC tile (the one with the drain contacts), dried for 5 min, and then placed on top of the first DBC tile, using an alignment jig (fig. 7-5). The assembly then undergoes a second sintering step, with the same parameters as the first one.

2) Analysis of the sandwich assembly: A crosssection of the power module is visible in figure 8. Detail views of some key areas are also provided. This cross section was obtained by encapsulating one power module in clear acrylic resin (Buehler Varikleer) and cutting it with a low speed diamond saw. The sample was then ground using P320 grit paper until the area of interest was attained. Then a polishing process was performed to achieve a satisfying surface quality (P1200 paper/9 µm, 3 µm, 1 µm diamond slurry/50 nm oxide polishing).

The leftmost detail view shows the silver layer at the top DBC/die interface. It shows some porosity, which indicates that the joint is only partially sintered.

A more dense joint could be achieved by using a higher pressure or a higher sintering temperature (or a combination of both). The interface between the silver layer and the copper shows a relatively large gap (the dark area at the interface). This indicates that although the silver was deposited on the copper, it did not bond properly. This is probably related to the relatively low sintering pressure, as well as to the absence of a noblemetal finish on the DBC: direct silver sintering on copper has already been demonstrated, but was found not to be ideal [START_REF] Hascoët | Pressureless Silver Sintering Die-Attach for SiC Power Devices[END_REF]. DBC substrates with a silver finish might result in a better bond. A dark line is also visible between the silver layer and the die, but it is most likely an artefact due to the topside al metallization of the die: it is very regular in thickness, and follows the features of the die. A more detailed investigation would require a scanning electron microscope.

The middle detail view from figure 8 shows the space between the gate and source contacts. It can be seen that the copper layer has a very steep edges, and shows clearly the two-step etching process. The silver layers are well aligned with the copper features, with no bridging of voiding visible. A dark area can be observed on top of the die: it is the polyimide passivation that separates the gate and source pads. This shows that the alignment between the die and the copper features is satisfying.

The rightmost detail from figure 8 shows the bottom contact of the second SiC die. One can see that the die is well aligned with the copper features. The silver layer is shorter than the die (≈100 µm, but this gap is negligible compared to the size of the die (4 mm on a side). Some electrical characterizations (not shown here) demonstrate that this power module operates properly: both transistors can be turned on or off, without any noticeable change in their characteristics (leakage current, on-resistance) compared to bare dies.

Overall, the cross section in figure 8 shows that the proposed process offers sufficient alignment accuracy. It also demonstrates that the silver layer is thick enough to compensate for the surface roughness of the copper layers, or for differences in height across the module. A thin layer of silver paste (50 µm) was chosen to avoid any risk of short circuit between the contacts. As no such phenomenon was observed, a thicker layer (e.g. 100 µm) might actually be more suitable and might offer more compliance (to avoid the separation between the silver layer and the copper). A noble-metal finish covering the copper metallization should also improve the quality of the silver/copper interface.

IV. CONCLUSION

In this paper, we presented the application of the silver sintering technique beyond die attach. For high temperature converters, it is possible to use silver sintering to attach all the components (not only dies, but also SMD passives). This makes it possible to overcome the limits of soldering (in particular the low melting point of many alloys).

For 3D structures, silver sintering makes it possible to proceed to successive sintering operation without problem. When solders are used, the alloys must be carefully chosen so that successive soldering steps have decreasing melting temperature. Finally, we demonstrated a relatively simple process to manufacture "sandwich" power modules. A cross-section of this module shows that the alignment accuracy achieved is satisfying.

Figure 1 :

 1 Figure 1: An inverter half bridge, comprizing two siliconcarbide JFETs, their associated gate drivers, and their associated passives (capacitors and gate resistors). All components are attached using silver sintering. The substrate is attached to the case with the same technique. Substrate dimensions are 20 mm by 30 mm.

Figure 2 :

 2 Figure 2: Switching waveforms on a 50 Ω resistive load, for 200 V DC bus measured at 310 °C ambient temperature.

Figure 3 :

 3 Figure 3: Photograph of the "sandwich" package: two SiC JFETs are placed between both ceramic substrates and form an inverter half bridge. The ceramic tiles are 25.4×12.7 mm 2 each.

Figure 4 :

 4 Figure 4: 3D view of the module of fig. 3 showing the internal layout and the two SiC JFET dies.

Figure 5 :

 5 Figure 5: Zoom on the die area of the sandwich structure.

Figure 6 :

 6 Figure 6: Process flow for the two-step etching of the DBC substrates.

1 -

 1 Stencil-printing of DBC with source and gate contacts 2-DBC tile in alignment jig, pre-drying of paste 3 -Die positionning (flipchip). First sintering step. 4 -Stencil-printing of DBC with drain contacts. 5 -DBC Tile in alignment Jig, second sintering step Finished assembly

Figure 7 :

 7 Figure 7: Process flow for the assembly of the "sandwich" module, with two sintering steps.

Figure 8 :

 8 Figure 8: Top picture: cross section of the module from fig. 3. The orange layers correspond to the patterned copper. The top and bottom grey layers are alumina (12.7 mm on the side for the top tile, 25.4 mm for the bottom tile). The two lighter gray rectangles in the middle are the SiC dies (4 mm on the side). Bottom pictures, from left to right: zoom on the topside sintered silver layer, zomm on the space between gate and source contacts, and zoom on the bottomside contact.

ACKNOWLEDGMENTS

This work was supported through grants THOR (Euripides-Catrene) and EPAHT (FRAE).


Chenjiang Yu
email: chenjiang.yu@lgep.supelec.fr

Éric Labouré

Cyril Buttay

three prototypes Fig. 1 EPC 2015 GaN transistor [2] Thermal management of lateral GaN power devices

Keywords: GaN power device, thermal management, Flex circuit, 3D packaging, flip-chip I

This article investigates several thermal management techniques for GaN transistors with a Wafer-Level Packaging (WLP): advanced techniques are used to mount them on Direct-Bonded Copper (DBC) ceramic substrates, with the heat removed either through the topside of the die (as recommended by the manufacturer), or through the backside. The thermal resistance of the assembly is measured in the different configurations, for different die thicknesses. The paper describes the manufacturing process and the thermal simulation and experimental results will be shown.

INTRODUCTION

In the recent years, as the silicon technology has approached its theoretical limits, power devices made out of Gallium Nitride (GaN) have emerged as alternatives that outperform Si devices by overcoming the limitation of higher switching frequencies, efficiency and reliability [START_REF] Shu | High-Frequency High Power Density 3-D Integrated Gallium-Nitride-Based Point of load Module Design[END_REF]. As a wide bandgap material, GaN has a superior relationship between onresistance and breakdown voltage due to its higher critical electric field strength. This allows devices to be more compact.

The studied GaN transistors are shown in Fig. 1. Provided by EPC, they are eGaN FET (enhancement mode, 40V -33A) with a very small die size (4075 × 1602 × 685 µm) [START_REF]Efficient Power Conversion[END_REF]. These devices are based on Si substrate and have a "lateral" structure, with all the terminals on the same side of the power die. As a consequence, they are equipped with solder bumps for "flipchip" mounting. This is efficient from an electrical point of view, with very short distances between the active area of the GaN transistor and the other components. From a thermal point of view, however, this is not so efficient: the bumps have limited thermal conductivity, and cover only a fraction of the die surface area. Therefore, it is worth comparing the thermal performance of GaN transistors cooled either through their bumps (topside cooling) or through their silicon substrate (backside cooling). We also compare the thermal performance of die mounted on ceramic substrate or on a more standard PCB substrate.

II. FABRICATION PROCESS

Three functioning prototype designs are fabricated for comparing the cooling path of GaN transistors. Their crosssection structures are shown in Fig. 2. In the first configuration (prototype I), GaN transistors were flip-chip-mounted on a DBC substrate with an alumina layer of 635 µm. A special etching technique was used to achieve the high resolution (200 µm pitch) required to mount the transistors. In the second configuration (prototype II), the backside of the transistors was attached to the DBC substrate. This required grinding down the silicon substrate of the transistors, to reduce their thickness and to remove the marking. A Ti/Ag layer was deposited on the silicon substrate, and the dies were attached to the DBC substrate using silver sintering. A flex substrate is used on the topside for the electrical interconnects. The third configuration (prototype III) is the classical flip-chip mounting on PCB, used as a basis for comparison. The three prototypes are shown in Fig. 3.

A. Prototype I

For prototype I, a dual-step etching is used. This allows for using thick copper on most of the surface (for low electric resistance) while having thin copper (high resolution) around the GaN die. In order to realize the double etching, two masks have been designed. The first mask is used for etching the complete electric circuit and the second one addresses only the copper leads for chip soldering. The substrate supplied by Curamik is coated by a photosensitive resin (MC Dip Coating) with a "Dip Coating" machine. After this step, the substrate is exposed to the ultraviolet (UV) through the first mask and developed. The copper etching is performed in ferric chloride, with a spray system (Bernier Electronik PR2030) for 11m30s. This removes approximately 250 µm of the 300 µm thick copper layer. After cleaning, the second etching repeats the same process from coating to etching as the first one but with the second mask and a etching time of 2m30s. The etching result is shown in Fig. 4.

Once the substrates were etched and cleaned, GaN transistors were soldered. The bumps of the EPC's eGaN transistors utilize a Sn/Ag/Cu solder with a composition of 95.5% Sn, 4% Ag, 0.5% Cu (melting point: 217 °C). The total reflow process is realized by ZEVAC ONYX 21 can control the process temperature while ensuring proper alignment between dies and substrate. No additional solder is used, the bonding is achieved by the reflow of the solder bumps themselves, as presented in [START_REF]Assembly eGaN FETs[END_REF]. In order to ensure the adhesion of component and to avoid the local oxidation of the copper, a little of tacky flux has been dropped on the chip contact area just before the component placement. A thermocouple (TC) has been attached near the component to measure the actual device temperature in real time. The solder reflow profile for DBC is shown in the Fig. 5(a). Top Heater and Bottom Heater correspond to the temperature of the heating elements of the soldering equipment (ZEVAC ONYX 21). The TC corresponds to the actual thermocouple measurement on the substrate. Due to its superior thermal performance, the DBC substrate require much more energy to achieve the reflow temperature (TC = 250°C).

B. Prototype II

The realization of prototype II can be divided into two parts, the soldering of the components to the flex substrate and the sintering of the components to the DBC substrate. The first part begins with the grinding down of the silicon substrate of the GaN transistors. This is necessary to remove the marking at the back of the die, and to reduce the thermal resistance of the device, as we want to mount the backside of the chip to the DBC substrate. The components are first bonded on a sample holder (Struers' AccuStop) by utilizing some mounting wax (Buehler). Then, the holder is put on a polishing machine (MECATECH 334) with a P1200-grade grit paper. The next step is to metalize the backside of the polished part. This is done in an EVA300 PVD system. 50 nm Ti and 150 nm Ag are deposited by evaporation. Afterwards, the chips are soldered to the flex substrate by using the same process described for prototype I.

The second part uses silver sintering technology at low temperature and low pressure. It offers excellent electrical and thermal conductivity so that the reliability is much better than traditional solders. The first step is to apply the selected silver paste (NBE Tech Nanotach-X) on the DBC by screen printing. Then, the soldered GaN transistors and flex substrate are placed onto the paste. Finally, the DBC substrate is subjected to a heated mechanical press, where the silver sinter layer is formed. The temperature profile used in this study is shown in the Fig. 6.

C. Prototype III

The fabrication process of the prototype III is nearly the same as the first one, but without the second etching. The soldering process, as shown in Fig. 5(b), needs a lower temperature for the heaters because of the PCB's lower thermal mass and thermal conductivity.

III. THERMAL ANALYSIS AND CHARACTERISTICS

A. FEM simulation

The power loss will heat up the module and the steady-state junction temperature depends on cooling system. To evaluate the temperature distribution of the prototypes, a 3-D model has been developed. This analysis was conducted using COMSOL finite element method (FEM) tool on the three prototypes. A heat dissipation of 10W was used for one GaN transistor, and an equivalent heat-transfer coefficient of 8 W/(m 2 •K) from the surfaces of substrate and component. The bottom surface of the bottom copper layer is assumed as the reference temperature of 27°C. The thermal conductivity of different materials in simulation are shown in Table I. The results of the temperature distribution in the three prototypes obtained by thermal analysis is shown in Fig. 7. Comparing to the PCB, the DBC has much better thermal performance for its lower thermal resistance. Prototype II, where the heat dissipates through encapsulation to DBC, has better thermal management capability than the first prototype where the heat dissipates through bumps because of the lower thermal resistance of the wide area joint.

B. Experimental characteristics

The junction temperature should be monitored during the device operation. In this study, a thermosensitive electrical parameter is proposed for the measurement of the junction temperature. R DSon is an excellent indicator because it is actually measuring the heat rise in the exact physical location where the heat is being generated. However, the calibration of R DSon as a function of T is a time consuming procedure and requires precise instrumentation techniques.

In order to calibrate R DSon , a thermal conditioner has been used (Thermonics T2500/E). The calibration curve (Fig. 8) is acquired using a Keithley 2410 SMU and shows that R DSon measurement is an accurate way of monitoring the junction temperature of a GaN transistor. We used the test circuit in Fig. 9: the temperature rise in the Device Under Test (DUT) is estimated by monitoring the drain-to-source resistance (R DSon ) of the transistor as a large current (up to 30 A) flows in the component. The resistors in series with the power supply are used for the stabilization of the current before the turn ON of GaN transistor. The voltage between Drain and Source (Vds) is measured by a differential analog input module (NI 9205) and the current Id is measured by a current probe (Tektronics TC-0030). The prototypes are mounted on a 15x15 cm 2 heatsink, with a sil-pad interface.

The experimental results of the prototype I and III, shown in Fig. 10, demonstrates that the temperature of prototype III rises much more than that of prototype I. A static test has also been done to compare the thermal resistance of each prototype. The results are shown in Table II. The experimental results for prototype II are not ideal, the new development is currently in progress concerning the redesign of the flex circuit.

IV. CONCLUSION

In this paper, the realization of three packaging prototypes for GaN transistors, a flip-chip solution with DBC and PCB substrate and a flex circuit approach is presented. The manufacturing process flow for the three technology developments is given. Thermal analysis and measurements show the feasibility of the approaches. Based on the simulations, thermal dissipation through the topside of the die is expected to have the best thermal performance. Due to the high electrical resistance of the flex interconnects we used, we were not able to measure the thermal resistance of this backside of this configuration.

Regarding the effect of the substrate, it is shown that a ceramic substrate (DBC) makes it possible to reduce the total thermal resistance (from junction to ambient) from 15°C/W down to 4.5 °C/W, despite the use of an extremely thin PCB (145 µm).

ACKNOWLEDGMENT

The Author would like to thank Mr. Pascal Bevilacqua from the laboratory AMPERE and Mr. Gilles Brillat from the electronic service of University Paul Sabatier for their technical support. The Author would like to thank Dr. Vicent Bley and Ms. Celine Combettes from platform 3DPHI for their kindly help. The Author would also like to thank the ANR for its financial support through the grant ETHAER.

Fig. 3

 3 Fig. 3 Photographs of the three prototypes

FigFig. 7

 7 Fig. 6 Sintering temperature profile

Fig. 9

 9 Fig. 9 Circuit diagram used for the transient thermal test

TABLE I

 I

	.	THERMAL CONDUCTIVITY OF DIFFERENT MATERIALS IN
		SIMULATION
	Material	Thermal conductivity
	Copper		400
	Ceramic		27
	GaN Bumps		62
	GaN Encapsulation	130
	Prepreg		0.4
	Silver paste		200

TABLE II .

 II STATIC TEST RESULTS

						Experimental/
	Prototype	Vds (V)	Id (A)	Rdson (mΩ)	P (W)	Simulation Thermal resistance
						(°C/W)
	I	0.0926	20	4.63	1.8526	4.5/4.8
	III	0.1534	20	7.67	3.068	15.6/17.8


Note de travail « Limitations de la théorie des capes d'invisibilité thermiques » L. Krähenbühl, 10/09/2015, v00 page 1/7

Note de travail : mise en évidence des Limitations de la théorie des capes d'invisibilité thermiques (en conduction pure)

L. Krähenbühl,

Ces trois milieux emboités forment une partition de l'espace d'étude Ω. Il n'y a pas de source thermique2 dans Ω.

Le milieu ambiant Ω est fermé vers l'extérieur par des surfaces isothermes S séparées les unes des autres par des conditions de Neuman (densité normale de flux thermique nulle). Ces conditions de Neuman ne sont introduites que par commodité (au cas où des essais numériques seraient envisagés), elles ne jouent aucun rôle dans le raisonnement ; les sources S peuvent aussi être les surfaces de volumes isothermes dans Ω a , qui serait alors ouvert jusqu'à l'infini. Un cas particulier intéressant, que nous utiliserons aussi dans la suite, est celui où le volume Ω a est fermé vers l'extérieur par une seule surface isotherme, qui sera alors la seule source thermique.

Avant l'instant t=0, nous supposons que toutes les températures absolues sont identiques. Dans la suite, nous appelons « température » (notée T) les écarts à la température initiale (donc T=0 partout pour t<0). La température des surfaces source S sont notées T Si . Les autres grandeurs locales d'intérêt sont la densité de flux de chaleur -ߣ∇ܶ et la densité de chaleur accumulée depuis l'instant t=0 qui vaut ߩܿܶ. ρ est la masse volumique et c la capacité thermique massique (autrefois appelée chaleur spécifique).

Pour simplifier les écritures, nous noterons dans la suite ं = ߩܿ (capacité thermique spécifique) La conductivité thermique est notée ߣ. La contrainte technologique est de n'utiliser que des matériaux existants, ce que nous exprimons dans un premier temps uniquement par le fait que ߣ, et ं sont dans l'espace de travail continues par morceaux, non singulières, avec des valeurs locales strictement positives finies. L'équation de la chaleur relie ces grandeurs locales : la chaleur accumulée dans un petit volume quelconque entre t=0 et l'instant présent a pour source le flux de chaleur à travers la surface de ce petit volume, sur la même période temporelle. On écrit ainsi l'équation de la chaleur sans source :

∇(ߣ∇ܶ) = ं డ் ௗ௧
(1) On peut aussi écrire des bilans par région. Par exemple, la chaleur accumulée dans l'espace d'étude Ω depuis l'instant t=0 peut s'écrire de deux manières différentes : à partir de la densité de chaleur accumulée :

ܳ ஐ )ݐ( =  ,ݔ(ܶं ݒ݀)ݐ ஐ (2)
à partir du bilan de chaleur entrante :

ܳ ஐ )ݐ( =  ቄ∑  ߣ డ் డ ݏ݀ ୗ ቅ ௧ (3)
Dans le cas particulier où la température serait spatialement constante dans Ω à l'instant t, on peut écrire (2) sous la forme :

ܳ ஐ )ݐ( = )ݐ(ܶ  ݒ݀ं ஐ = .)ݐ(ܶ ܥ ஐ (4)
où ܥ ஐ est la capacité thermique de la région Ω.

Noter qu'on aura aussi à chaque instant :

ܳ ஐ )ݐ( = ܳ ஐ ೌ )ݐ( + ܳ ஐ )ݐ( + ܳ ஐ )ݐ( (5)
Les expériences 1 et 2 nous permettent de donner une définition de ce qui est communément appelé « cape thermique » universelle parfaite. Nous montrons ensuite qu'une telle cape n'existe pas. Cette démonstration n'interdit pas l'existence de capes exactes « adaptées à un contenu », dans des conditions cependant extrêmement restrictives. Enfin, la construction de capes approximatives reste possible, ce travail aide à en cerner les limites, qui ne pourront jamais être dépassées, quelle que soit l'habileté des expérimentateurs.

La cape parfaite

Expérience 1 : Dans un premier temps, on affecte à Ω et Ω les même propriétés qu'à Ω (le volume Ω est donc homogène), et on calcule le comportement thermique transitoire ܶ ଵ ,ݔ( )ݐ correspondant par exemple à un saut de température de l'une des surfaces source ܶ ௌଵ à l'instant t=0.

Plus généralement, on fera varier les températures source ܶ ௌ dans un intervalle de temps donné [0,t f ], et on observera les phénomènes thermiques jusqu'à la fin du régime transitoire (t=t ∞ > t f ).

Expérience 2 : Dans un second temps, on affecte à Ω et à Ω des propriétés thermiques (conductivité, capacité spécifique) différentes de celles de Ω , éventuellement non homogènes, et on recommence l'expérience, ce qui conduit à un comportement transitoire ܶ ଶ ,ݔ( .)ݐ

Définitions :

Cape parfaite adaptée. Ω est une cape parfaite adaptée à l'objet placé dans Réfutation de l'existence de capes thermiques parfaites universelles.

Ω si ܶ ଵ ,ݔ( )ݐ et ܶ ଶ ,ݔ( )ݐ sont égaux dans Ω pour tout t>0 (en pratique pour t∈[0,t ∞ ]), quelles que soient les excitations ܶ ௌ )ݐ( dans l'intervalle [0,t f ],
ݐ∀ ≥ 0 ∶ ܳ ଵ )ݐ( = ܳ ଶ )ݐ( (6)
La quantité de chaleur totale injectée dans Ω est également la même dans les deux cas, car elle peut être calculée à partir de l'intégrale de surface (3) qui ne dépend que de la répartition de la température dans Ω , identique à tout instant dans les deux expériences :

ݐ∀ ≥ 0 ∶ ܳ ଵ )ݐ( + ܳ ଵ )ݐ( + ܳ ଵ )ݐ( = ܳ ଶ )ݐ( + ܳ ଶ )ݐ( + ܳ ଶ )ݐ( (7)
Il résulte de (6) -(5) que :

ݐ∀ ≥ 0 ∶ ܳ ଵ )ݐ( + ܳ ଵ )ݐ( = ܳ ଶ )ݐ( + ܳ ଶ )ݐ( (8)
A la fin du régime transitoire thermique, la température est dans les deux situations uniformément égale à ܶ ௌ . En utilisant (4), on peut donc aussi (pour ݐ > ݐ ஶ ), exprimer les quantités de chaleurs dans la cape et dans l'objet uniquement à partir de ܶ ௌ et de la capacité thermique de chaque région :

ܳ ஐ , ݐ( > ݐ ஶ ) = ܶ ௌ  ݒ݀ं ஐ = ܶ ௌ ܥ ஐ , ݅ = 1,2 (9)
ܳ ஐ , ݐ( > ݐ ஶ ) = ܶ ௌ  ݒ݀ं ஐ = ܶ ௌ ܥ ஐ , ݅ = 1,2 (10)
On peut alors réécrire (8) sous une forme indépendante de l'expérience réalisée :

ܥ ஐ ,ଵ + ܥ ஐ ,ଵ = ܥ ஐ ,ଶ + ܥ ஐ ,ଶ (11)
C'est une condition nécessaire pour que l'objet situé dans Ω puisse être dissimulé par le dispositif situé dans Ω . Pour reprendre l'analogie mécanique de l'introduction, cela signifie que la capacité thermique des objets de l'expérience 1 et de l'expérience 2 doivent être identiques (comme les masses devaient être égales dans l'introduction), ou encore que leurs capacités thermiques spécifiques moyennes doivent être égales.

Les deux termes du membre de gauche sont fixés dans l'expérience 1 par les propriétés thermiques du milieu ambiant Ω , et par le choix géométrique des volumes Ω et Ω occupés par la cape et l'objet. Leur somme représente la capacité thermique qu'aurait la région Ω ∪ Ω si elle avait les propriétés de Ω . Le terme ܥ ஐ ,ଶ correspond aux choix faits lors de la conception de la cape idéale. Une fois la cape conçue, ce terme est lui aussi fixé.

La première conséquence de (11) est la condition nécessaire :

ܥ ஐ ,ଶ = ܥ ஐ ,ଵ + ܥ ஐ ,ଵ -ܥ ஐ ,ଶ (12)
c'est-à-dire que la capacité thermique de l'objet « caché » par une cape thermique donnée est obligatoirement fixée a priori (condition nécessaire, mais bien entendu pas suffisante).

Conclusions :

La cape thermique parfaite universelle, qui permettrait de « dissimuler » n'importe quel objet placé en son centre, n'existe donc pas, alors que rien n'interdit cette idée dans le cas de la cape optique.

Ces considérations n'interdisent pas l'existence d'une cape thermique parfaite adaptée à une famille d'objets de même capacité thermique.

Une seconde conséquence lourde de (12) est que, même si on construit une cape thermique adaptée à des objets dont la capacité thermique est fixée à l'avance, on ne pourra dans aucun cas dissimuler un objet dont la capacité thermique dépasse celle du volume du milieu ambiant qui a été enlevé pour y mettre la cape :

ܥ ஐ ,ଶ < ܥ ஐ ∪ஐ = ݉݁(Ωݑ݈ܸ ∪ Ω ). ं ஐ ೌ (13)
l'écart correspondant à la capacité thermique de la cape elle-même.

On peut réécrire (13) à partir de la capacité thermique spécifique moyenne de l'objet caché et du rapport des volumes ܸ ஐ ∪ஐ /ܸ ஐ :

ं ത ஐ < ं ஐ ೌ . ܸ ஐ ∪ஐ /ܸ ஐ (14)
Donc ou bien l'objet dissimulé est très petit par rapport au volume occupé (ܸ ஐ ≪ ܸ ஐ ∪ஐ ), ou bien l'objet caché à une capacité thermique spécifique moyenne proche de celle du milieu ambiant, ou inférieure à celle-ci (car la cape elle-même « consomme » aussi de la capacité thermique : ܥ ஐ ,ଶ n'est pas forcément petit) : cela est évidemment une restriction énorme.

Commentaire :

Cette remarque n'est pas sans conséquence, en raison de la gamme des variations possibles de la capacité thermique spécifique des matériaux réels. Ainsi, si le milieu ambiant (milieu de l'expérience 1) est de l'air, dont la capacité thermique spécifique est l'une de plus faibles qu'on peut trouver (beaucoup plus faible que celle d'objets techniques qu'on souhaiterait dissimuler, certains auteurs évoquant par exemple des composants électroniques), une cape thermique respectant (13) ne pourra guère être développée, puisque toute zone de Ω ∪ Ω à ं ଶ > ं ଵ devrait être compensée par une zone avec ं ଶ < ं ଵ , matériau difficile à trouver. C'est la raison pour laquelle les rares travaux expérimentaux réalisés ont tous utilisé pour le milieu ambiant un matériau à conductivité et capacité thermique spécifique relativement fortes, ce qui permet de créer des contrastes dans les deux sens pour la zone de la cape.

Toute application potentielle imaginée avec l'air comme milieu ambiant ne peut que laisser extrêmement sceptique.

Réfutation de la transformation de Pendry/Guenneau-Amra-Veynante

Enfin, il faut noter que la première transformation, issue de l'optique, qui a servi à concevoir une cape thermique théorique circulaire en 2D, consistait à concentrer la matière homogène d'un disque de rayon ܴ (correspondant dans notre raisonnement à Ω ∪ Ω ) vers un anneau entre deux rayons interne ܴ < ܴ et externe ܴ :

ं ஐ ,ଶ ݎ( ᇱ ) = ᇲ ିோ ᇱ ቀ ோ ோ ିோ ቁ ଶ ं ஐ ೌ (15)
pour constituer la cape (région Ω ). Le principe même de cette transformation fait que :

 ं ஐ ,మ ݒ݀ ஐ =  ं ஐ ೌ ݒ݀ ஐ ∪ஐ = ं ஐ ೌ . ܸ ஐ ∪ஐ (16)
en enlevant toute la matière pour ݎ ᇱ ߳ [0, ܴ ] (région Ω ), ce qui conduit à : ܥ ஐ ,ଶ = ܥ ஐ ,ଵ + ܥ ஐ ,ଵ et donc par l'équation (12) à : (17) ܥ ஐ ,ଶ = 0 (18) c'est-à-dire que l'objet caché a une capacité thermique nulle.

Conclusion :

La cape ainsi conçue est certes une cape parfaite adaptée exacte, mais elle ne peut « cacher » que du vide.

Commentaire :

En plus, cette approche conduit à des propriétés non physiques, la conductivité radiale et capacité thermique spécifique tendant vers 0 pour le rayon ݎ ᇱ = ܴ , ce qui est une manière déguisée d'introduire un isolant thermique parfait sur la face interne de la cape.

L'expérience avec un gradient de température unidirectionnel comme source

Les articles publiés jusqu'ici s'intéressent à une situation moins générale que celle que nous venons de décrire, l'invisibilité évoquée ne concernant que la situation où les sources externes servant à l'expérience sont deux plans parallèles, l'un des deux étant soumis à un saut de température à l'instant 0. A la fin du transitoire thermique, le gradient de température est uniforme dans Ω . Cette seule expérience n'est naturellement pas suffisante pour démontrer l'invisibilité d'une structure pour toute expérience de conduction thermique menée depuis l'extérieur, mais lorsque la cape et son contenu possèdent une symétrie (géométrique et physique) par rapport à leur plan médian Γ, parallèle aux plans des sources, on retrouve néanmoins le résultat précédent : même avec cette définition plus étroite de l'invisibilité, les mêmes contraintes très restrictives s'appliquent.

Preuve.

On note ܶ la température atteinte pour ݐ > ݐ ஶ en Γ ∩ Ω . Les symétries font qu'un point ܲ ଵ et son symétrique ܲ ଶ par rapport à Γ sont à la fin du régime transitoire tels que :

ሾ்( భ )ା்( భ )ሿ ଶ = ܶ ݐ > ݐ ஶ (19)

  Si cette condition est réalisée, il est en effet impossible, par des expériences menées en conduction avec des sources hors de Ω ∪ Ω , de « détecter » la présence de la cape avec l'objet dans Ω , quel qu'il soit. Pour l'équation des ondes, aucun argument théorique ne s'oppose à l'existence d'une telle cape universelle. Nous montrons dans la suite que ce n'est pas le cas pour les capes thermiques.

	Commentaire :
	Si cette condition est réalisée, il est en effet impossible, par des expériences menées en conduction
	avec des sources hors de Ω ∪ Ω , de « distinguer » les 2 situations : d'une part celle du milieu
	homogène, d'autre part le même milieu mais contenant la cape et l'objet spécifique pour lequel elle
	a été conçue.

pour des propriétés thermiques données (conductivité, capacité thermique spécifique) de l'objet dans Ω .

Cape parfaite universelle :

Ω est une cape parfaite universelle si elle est une cape parfaite adaptée à Ω , quel que soient les propriétés thermiques de l'objet dans Ω .

Commentaire :

  Réalisons les expériences 1 et 2 en entourant entièrement le volume Ω d'une seule surface source S et en portant la température de cette surface à la valeur ܶ ௌ constante et non nulle à partir de l'instant t=0.A la fin du régime transitoire de ces deux expériences, (temps que nous noterons ݐ > ݐ ஶ ), la température dans Ω est constante et uniforme, de valeur ܶ ௌ .Nous supposons maintenant que la configuration de l'expérience 2 est celle d'une cape parfaite (adaptée ou universelle, on ne le sait pas à ce stade). Les propriétés thermiques du milieu Ω n'ayant pas été modifiées entre les deux expériences, et la répartition de la température étant dans les 2 cas identique à tout instant dans le volume Ω , la chaleur stockée dans ce volume pendant les deux expériences est la même à chaque instant (et donc aussi à la fin du régime transitoire) :

Rappelons que la capacité thermique d'un objet est égale à la quantité de chaleur nécessaire pour élever sa température de 1K.

Cette condition est essentielle : elle est toujours imposée dans le détail des raisonnements des auteurs qui étudient ces capes, même s'ils ne l'indiquent pas explicitement ; par contre, la plupart des applications potentielles évoquées par les mêmes auteurs concernent la « protection » ou l' « invisibilité » d'objets qui sont des sources de chaleur (éléments électroniques, personnes, matériels militaires …).


Gianluca Argentini
email: gianluca.argentini@rielloburners.com

Costruction of classic exact solutions for Tricomi equation

Keywords: second order PDE, fluid dynamics, system of first order partial differential equations

A formula to construct classic exact solutions to Tricomi partial differential equation. The steps to obtain this formula require only elementary resolution of a simple system of first order PDEs.

The (generalized) Tricomi equation is the second order partial differential equation

∂ xx f + a(x)∂ yy f = 0 (1)
where f (x, y) and a(x) are regular functions. In the case a(x) = x, (1) is the classic Tricomi equation, as described by Prof. Francesco in his work dated 1923 [START_REF] Tricomi | Sulle equazioni differenziali alle derivate parziali di secondo ordine di tipo misto[END_REF]. The equation is an abstraction of the Euler equation on a 2D fluid motion in the case of a flow speed near the sonic condition. For Tricomi equation some exact solutions formulas exist ([4] or [2]), and solutions to some particular boundary values problems are known [START_REF] Cibrario | Equazioni a derivate parziali di tipo misto[END_REF]. Also, some results about weak solutions are found [START_REF] Yagdjian | Global Existence for the n-Dimensional Semilinear Tricomi-Type Equations[END_REF].

Let be u = ∂ x f = f x , v = ∂ y f = f y .
Then Tricomi equation can be written as a system of two first order equations:

u x (x, y) + a(x)v y (x, y) = 0 u y (x, y) -v x (x, y) = 0 (2)
We define, for convenience reasons, a function t = t(x, y) = v(x, y). From the first equation we can write u(x, y) = -

1 where a ∈ R and g is an arbitrary function of real variable. Now we have to find the condition that g and t must satisfy to verify the second equation of the system (2). This equation is now, from the usual rule of derivation of integrals depending on parameters,

- x a [a(s) t yy (s, y)] ds + g ′ (y) = t x (4)
and hence

g(y) = y b t x (x, r) + x a [a(s) t yy (s, r)] ds dr (5)
with b ∈ R. But g must depend only on y: using the Fundamental Theorem of the Integral Calculus we have

0 = ∂ x g(y) = y b [t xx (x, r) + a(x) t yy (x, r)] dr ∀y (6)
If t is a solution of Tricomi equation ( 1), previous condition is verified. Note that, integrating with respect to y in g(y) formula, the expression for u becomes

u(x, y) = y b t x (x, r)dr - x a [a(s) t y (s, b)] ds (7)
So, we have found that if t is a solution of Tricomi equation, then a function f such that f x = u and f y = t, with u given by (7), is a solution too. Hence, from f y = t we can write

f (x, y) = y b t(x, r)dr + h(x) (8)
where h is an arbitrary function of real variable. From f x = u follows

y b t x (x, r)dr + h ′ (x) = y b t x (x, r)dr - x a [a(s) t y (s, b)] ds (9) so that h(x) = - x a q a [a(s) t y (s, b)] ds dq (10)
We have so proven that if t = t(x, y) is a generic solution of Tricomi equation, then the following formula gives a solution of the same equation too:

f (x, y) = y b t(x, r)dr - x a q a [a(s) t y (s, b)] ds dq (11)
For a-posteriori verification, let be t such that t xx + a(x)t yy = 0. We have

f xx = y b t xx (x, r)dr -a(x) t y (x, b) = = - y b a(x)t yy (x, r)dr -a(x) t y (x, b) = = -a(x) t y (x, y) + a(x) t y (x, b) -a(x) t y (x, b) = = -a(x) t y (x, y) = = -a(x)f yy (12)
so the solving formula (11) is verified.

Example 1. Let be f xx + xf yy = 0 the original Tricomi equation. Note that t(x, y) = y is a (trivial) solution. Then, from (11) with a = b = 0, the function

f (x, y) = y 0 y dr - x 0 q 0 s ds dq = 1 2 y 2 - 1 6 x 3 (13)
is a solution too.

Example 2. Let be f xx + cos(x)f yy = 0 a generalized Tricomi equation. Note that t(x, y) = y is a (trivial) solution. Then, from (11) with a = b = 0, the function

f (x, y) = y 0 y dr - x 0 q 0 cos(s) ds dq = -1 + 1 2 y 2 + cos(x) (14)
is a solution too.

Note that formula (11) can be used as a solutions machine: starting from the most simple not null solution, that is from t(x, y) = 1, it can be used for iterative construction of solutions.

Also, formula (11) can be used to find solutions to some particular boundary values problems for Tricomi equation. For example, in the case a(x) = x and b = 0, if the function t(x, y) is such that t y (x, 0) = 0 ∀x (condition satisfied e.g. by t = -1 6 x 3 + 1 2 y 2 ), then from (11) follows

f (x, y) = y 0 t(x, r)dr (15)
so that f (x, 0) = 0 ∀x ∈ R. Hence, if t y (x, 0) = 0 ∀x, then f (x, y) = y 0 t(x, r)dr is a solution of the boundary values differential problem

∂ xx f + a(x)∂ yy f = 0 , f (x, 0) = 0 x ∈ R ( 16
)
If t is a solution of (1) satisfying the boundary conditions t(x, 0) = g(x), with g a function of real variable, then from (11) follows that f y (x, 0) = g(x), that is f is a solution of the problem with Cauchy-Neumann condition

  s) t y (s, y)] ds + g(y)


Noé Gaumont
email: noe.gaumont@lip6.fr

François Queyroi

Clémence Magnien

Matthieu Latapy

Expected Nodes: a quality function for the detection of link communities

Keywords: complex networks, community detection, link partition, quality measure

Many studies use community detection algorithms in order to understand complex networks. Most papers study node communities, i.e. groups of nodes, which may or may not overlap. A widely used measure to evaluate the quality of a community structure is the modularity. However, sometimes it is also relevant to study link partitions rather than node partitions. In order to evaluate a link partition, we propose a new quality function: Expected Nodes. Our function is based on the same inspiration as the modularity and compares, for a given link group, the number of incident nodes to the expected one. In this short note, we discuss the advantages and drawbacks of our quality function compared to other ones on synthetics graphs. We show that Expected Nodes is able to pass some fundamental sanity criteria and is the one that best identifies the most relevant partition in a more realistic context.

Introduction

In the past years, complex networks were extensively studied because of the broad range of systems they can model, from protein-protein interactions to social networks. One question of interest is the detection of communities. Despite the important literature that covers the detection of classical, overlapping or even dynamic communities, most works focus on grouping nodes. On the other hand, the question of link communities has received less attention [START_REF] Evans | Line graphs, link partitions, and overlapping communities[END_REF][START_REF] Ahn | Link communities reveal multiscale complexity in networks[END_REF][START_REF] Lim | LinkSCAN*: Overlapping community detection using the link-space transformation[END_REF]. Intuitively, partitioning a network's links is very relevant in some contexts. For example, in a social network, most individuals belong to multiple communities such as families, friends, and co-workers, while the links between individuals usually exist for a dominant reason. In this context, a link community would be a group of interactions on one topic.

In this paper, we address the problem of evaluating the quality of a link partition. After a review of previous works (Section 2), we introduce a novel measure: Expected Nodes (Section 3). It is based on the assumption that a link community corresponds to less individuals than expected while its surroundings links correspond to more individuals than expected. We use several test cases (Section 4) to study how this measure behaves when compared to other quality functions.

Related Work

We introduce some notations used throughout this paper. Let G = (V, E) ge a graph, d(u) denotes the degree of node u in G. A link partition in k groups is noted

L = (L 1 , L 2 , . . . , L k ) with L i ⊆ E ∀i, L i ∩ L j = / 0 ∀i = j and i L i = E. For a given link group L ∈ L , let V in (L) = {u ∈ V, ∃(u, v) ∈ L} be the group of nodes inside L and V out (L) = {u ∈ V \V in (L), (u, v) ∈ E \ L ∧ v ∈ V in (L)} be the nodes adjacent to L.
Ahn et al. [START_REF] Ahn | Link communities reveal multiscale complexity in networks[END_REF] were among the first to propose a method to detect link communities. Their method link clustering is a hierarchical clustering method constructing a dendrogram by iteratively merging groups of links according to a similarity measure based on the Jaccard index. To decide where to cut the dendrogram in order to create a partition, they use a density based measure: the partition density. For a given link partition L , the partition density is given by:

D(L ) = 2 |E| ∑ L∈L ,|L|>2 |L| |L| -(|V in (L)| -1) (|V in (L)| -1)(|V in (L)| -2) . (1)
However, the partition density cannot be easily generalized to weighted networks. An attempt in this direction has been made by Kim [START_REF] Kim | Community Detection in Directed Networks and its Application to Analysis of Social Networks[END_REF]. Evans et al. [START_REF] Evans | Line graphs, link partitions, and overlapping communities[END_REF] propose three quality functions to evaluate link partitions. Their quality functions can be computed and optimized on the original graph but also on specific weighted line graphs (LG 1 , LG 2 , LG 3 ) using existing algorithms such as the Louvain method [START_REF] Blondel | Fast unfolding of communities in large networks[END_REF]. A line graph of an undirected graph is a graph where each node represents a link from the original graph and two nodes are connected if the corresponding links share a node.

To define these particular line graphs LG 1 , LG 2 and LG 3 , let B denote the incidence matrix of a network G: the elements B iα of this |V | × |E| matrix are equal to 1 if link α is connected to node i and 0 otherwise. Matrices LG 1 , LG 2 and LG 3 are defined as:

x = 1 x = 2 x = 3 LG x (α, β ) B iα B iβ (1 -δ αβ ) ∑ i∈V,d G (i)>1 B iα B iβ d(i) -1 ∑ i, j∈V,d(i)d G ( j)>0 B iα A i j B jβ d(i)d( j)
Let k x (α) = ∑ β LG x (α, β ) be α's weighted degree in LG x and W x = ∑ α,β ∈|E| LG x (α, β ). For x ∈ {1, 2, 3}, the quality function Evans x is:

Evans x (L ) = 1 W x ∑ L i ∈L ∑ e 1 ,e 2 ∈L 2 i LG x (e 1 , e 2 ) - k x (e 1 )k x (e 2 ) W . (2)
Kim et al. [START_REF] Kim | Map equation for link communities[END_REF] explored the extension of the concept of Minimum Length Description introduced by Rosvall et al. [START_REF] Rosvall | Maps of random walks on complex networks reveal community structure[END_REF] which is an information-theoretic framework. This extension directly considers link partitions. An advantage of their method is the ability to compare link and node partitions.

Our quality function: Expected Nodes

One commonly accepted assertion for node communities is: a community should have more internal connections than the expected number of connections in a random null model where no communi ty structure exists. This assertion is at the core of the modularity introduced by Newman and Girvan [START_REF] Newman | Finding and evaluating community structure in networks[END_REF]. In the same way, to evaluate a link community, we compare the number of nodes to its expected number of nodes. Like modularity, the measure can be decomposed, for each group L, into two components: internal quality and external quality. Like modularity, we use the configuration model [START_REF] Bender | The asymptotic number of labeled graphs with given degree sequences[END_REF] for a null model. In this model, the links are created by choosing random pairs of half-link (or stubs), each node having as many stubs as is degree in the original graph.

We start by describing the internal quality. Intuitively, a group of links L is a relevant community if it consists of a large number of links adjacent to few nodes, i.e. if V in is small compared to what would be expected in the configuration model. By definition, a node is an internal node of L if one of its stubs (half-links) is in L. Therefore, to compute the expected number of internal nodes in the configuration model, we choose randomly 2|L| stubs among a total of 2|E| stubs. A node u has therefore d(u) ways to be picked. The expected number of internal nodes for a given link group L, denoted by µ G (|L|), is then:

µ G (|L|) = ∑ u∈V P(u picked at least once) = ∑ u∈V 1 - 2|E|-d(u) 2|L| 2|E| 2|L| . (3)
Note that the function µ G only depends on the degree sequence {d(v)} v∈V . Note also that if |L| = 1, then µ G (|L|) ≤ 2; this is because the configuration model allows self loops. A group L has a good internal quality if it has less internal nodes than expected. We therefore choose to define the internal quality function Q in for a given group L as the variation between the actual number of internal nodes and its expectation:

Q in (L) = µ G (|L|) -|V in (L)| µ G (|L|) . (4)
With this definition, for a given |L|, the fewer nodes a group of links involves, the higher Q in will be.

We now describe the external quality of a group L. The process to evaluate the neighbourhood V out (L) of a group L is similar to the process for the internal nodes. However in this case, we consider that L has a bad neighbourhood if it has fewer external nodes than expected. Indeed if there are many external links and few external nodes, these external links should be included in the community. Let d(L, u) = ∑ v∈V 1 (u,v)∈E\L be the degree of u restricted to links not in L and d(L) = ∑ u∈V in (L) d(L, u). The expectation of the number of adjacent nodes is evaluated as the number of nodes that are picked when d(L) stubs are chosen randomly in the configuration model where the links of L have been removed. The corresponding degree sequence is {d G\L (u)} u∈V where G \ L = (V, E \ L) . Only one half link is chosen randomly because the other half has to remain attached to an internal node of L. Thus, we have the following equation:

E[ d(L)] = µ G\L ( d(L)/2).
(

) 5
Since we are interested in penalizing groups that have few external nodes, but do not consider that a group is particularly good if it has a large number of external nodes, we bound the external quality by 0:

Q ext (L) = min 0, |V out (L)| -µ G\L ( d(L)/2) µ G\L ( d(L)/2) . (6)
Finally, we define Expected Nodes for a group L as:

Q(L) = 2 |L|Q in (L) + |L out |Q ext (L) |L| + |L out | . ( 7
)
Notice that the trivial group containing all links has a null quality because Q in and Q out will be equal to 0. The other trivial decomposition where each link belongs to its own group has a negative quality. However, in some cases a group containing a single link might be the best choice. It is the case when the link is a bridge between dense groups. Finally, we define Expected Nodes for a given link partition L as the weighted sum of the quality of each group:

Q G (L ) = ∑ L∈L |L|Q(L) |E| . ( 8
)

Comparison with existing methods

In order to study the relevance of Expected Nodes, we use two test cases.We also compare it to acknowledged quality functions: partition density [START_REF] Ahn | Link communities reveal multiscale complexity in networks[END_REF] and the quality functions developed by Evans et al. [START_REF] Evans | Line graphs, link partitions, and overlapping communities[END_REF] denoted by Evans1, Evans2 and Evans3.

Complete graph

We start with a simple case in order to check that Expected Nodes satisfies some important and fundamental properties. We study a complete graph of 100 nodes (we obtained similar results with different sizes). On this graph, we define the trivial partition with one group containing all links, and two partitions families: one with two groups and one with three groups. Given a parameter p < |V |, let V be a set of p nodes. Both partitions place all links in V × V in one group. The 2-groups partition places all other links in the second group. The 3-groups partition places all links in V ×V \V in a second group and all remaining links in the third. These assignment rules are illustrated in Figure 1 As the graph is a single complete graph, the best solution is to capture only one group with all the links, i.e. the trivial partition should have the highest ranking. Figure 2 shows the results. For each value of p and each quality function, we present the values for the corresponding partitions in 2 and 3 groups and for the trivial partition. Surprisingly, quality functions Evans1 and Evans2 fail this simple test because they evaluate the 2-or 3-groups partitions as better than the trivial one. According to partition density, Expected Nodes and E 3 , the trivial partition is best. The quality function Evans3 differs because of its small amplitude (≈ 10 -3 ).

Overlapping LFR benchmark

We now discuss results obtained by comparing the quality functions on random networks with a known community structure. To the best of our knowledge, there is no graph generator based on link partitions. We use the benchmark proposed by Lancichinetti et al. [START_REF] Lancichinetti | Benchmarks for testing community detection algorithms on directed and weighted graphs with overlapping communities[END_REF] which generates graphs based on a known node cover. We introduce two transformations of this overlapping community structure into link partitions denoted by TA and T B (see Figure 3). Given u, v ∈ V , let C u,v denote the intersection between the communities of u and v in the node cover and U u,v their union. We define the group of a link (u, v) ∈ E in the partitions as follows:

intra-community if |C u,v | = 1 then (u, v) is in community C u,v ; inter-community if |C u,v | = 0 then in TA, (u, v) belongs to its own community. In T B it belongs to community U u,v which contains all links (u , v ) such that U u ,v = U u,v ; overlapping if |C u,v | > 1 then (u, v)'s community is chosen randomly in C u,v .
3: Construction of TA and T B from a node cover. Link colours denote groups.

We describe the results averaged over 30 graph generations with 500 nodes, an average degree of 25, 10 overlapping nodes and a mixing parameter of 0.1 3 . There are on average 5620 intra-community links, 625 inter-community links and only 5 overlapping links. For each generation, the partition TA, T B, the partition LC found by link clustering [START_REF] Ahn | Link communities reveal multiscale complexity in networks[END_REF] and the partition E2 found by the second method of Evans et al. [START_REF] Evans | Line graphs, link partitions, and overlapping communities[END_REF] (based on the optimization of Evans2)4 are evaluated using Partition Density, Evans2 and Expected Nodes.

In TA (resp. T B), there are 650 (resp. 70) groups on average. Manual investigations show that the E2 partitions are very close to the ground truth (TA or T B) if inter-community links are not considered. Indeed in E2, inter-community links are randomly distributed among adjacent larger link communities. The LC partitions contain The box shows lower and upper quartiles and the median. The whiskers extend to 1.5 time the interquartile range. Flier points are those past the end of the whiskers. 720 groups on average and intra-community links are split into many small groups. Notice that neither TA nor T B get the best evaluation according to Evans2 and Partition density even though they are considered as ground truth. The following observations can be made. First, Expected Nodes (Fig. 4c) behaves differently than both other measures (Fig. 4a and4b). This shows that our measure brings something new to the picture. Moreover, its values are usually higher for TA and T B than for the partitions found using the two algorithms, which corresponds to our expectations. Second, the Expected Nodes values are significantly different for TA and T B. It is not the case for quality functions E2 and Partition density. Indeed, external links between the same community are likely to form a group of isolated links in T B. This situation is highly penalized by our measure. It also explains why Expected Nodes evaluates LC partitions better than E2 partitions. For those reasons, we believe that maximizing Expected Nodes would result in partitions close to TA in this benchmark.

Conclusion

In this paper, we propose a new quality function, Expected Nodes, to evaluate the quality of a link partition of a graph 5 . It compares the number of nodes adjacent to a link group to its expectation, in the same way as the modularity evaluates the relevance of a node group by comparing the number of adjacent links to its expected value. To show the relevance of Expected Nodes, we compared it to existing quality functions. The main perspective of our work is to design an algorithm for maximizing Expected Nodes in order to detect relevant link partitions. More detailed comparisons between quality functions may also be performed. For instance, it would be interesting to evaluate their behaviour to detect whether they are likely to present local maxima such as the one observed in Figure 2c or not.

Fig. 1 :Fig. 2 :

 12 Fig. 1: Two different link partitions of a complete graph with p = 5: (a) in two link groups and (b) in three link groups. The dark nodes corresponds to V and the color of a link corresponds to its group.

Fig. 4 :

 4 Fig. 4: Boxplots of the three quality functions values for the different link partitions. The box shows lower and upper quartiles and the median. The whiskers extend to 1.5 time the interquartile range. Flier points are those past the end of the whiskers.

Remaining parameters with original notations:k max = 50, t 1 = -2, t 2 = -1, C min = 20, C max = 100.

The results are similar for the algorithms using E1 and E3.

The code used to compute each quality function is available: https://github.com/ ksadorf/ExpectedNodes

Acknowledgements : This research was supported by a DGA-MRIS scholarship, by a grant from the French program "PIA -Usages, services et contenus innovants" under grant number O18062-44430 and by the CODDDE project ANR-13-CORD-0017-01.


Daniel Balouek-Thomert
email: daniel.balouek-thomert@ens-lyon.fr

Eddy Caron
email: eddy.caron@ens-lyon.fr

Pascal Gallard
email: pascal.gallard@nss.fr

Laurent Lefevre
email: laurent.lefevre@ens-lyon.fr

Nu

Keywords: Cloud federation, Iaas, Energy-aware scheduling Provider

The adoption of cloud computing is still limited by several legal concerns from companies. One of those reasons is the data sovereignty, as data can be physically host in sensible locations, resulting in a lack of control for companies.

In this paper, we present the Nu@ge project aimed at building a federation of container-sized datacenter on the French territory. Nu@ge provides a software stack that enables companies to put independent datacenters in cooperation in a national mesh. Additionally, a prototype of a container-sized datacenter has been validated and patented.

I. INTRODUCTION

Cloud Computing represents a significant evolution of Information and communications technology in terms of usage and organization. It allows companies to increase their competitiveness, by lowering IT infrastructure costs and improve quality of service. This field will lead to new markets and service, remotely and on-demand accessible, led by a market growth curve of 25% per year.

Despite unquestionable benefits to users, cloud computing raises several concerns about data sovereignty. Cloud providers reveal few information about geographical location and process of data and applications. As information which has been converted and stored in binary digital form is subject to the laws of the country in which it is located, it raises several concerns from a legal standpoint. Third-party entities or governments could take control of sensible data, and legal protections may not apply if one's data is located outside of its country. Additionally, data from a specific company could be physically hosted along with data from other companies. This causes security risks in terms of attacks (attempts to access data of other companies) or marketing purposes as a secondary use.

The Nu@ge consortium 1 is composed of the following members:

• NON STOP Systems, secure cloud solutions provider and leading architect of the project 1 Nu@ge is a research project funded by the FSN (Fund for the Digital Society, BPI France) as part of the Investissements d'Avenir program.

• CELESTE, Internet provider and manufacturer of the StarDC • Oodrive, online storage specialist • DotRiver, virtual desktop and environment provider • Init Sys, private network operator • New GenerationSR, Green IT consulting • LIP6, laboratory and its research team REGAL and PHARE of UPMC University, Paris. Those 6 innovating SMEs (Small and Medium-sized Enterprise) and 2 research teams are gathered with the ambition of creating the cloud of tomorrow : open to heterogeneous hardware and software stacks, spread on a regional network among France using low-energy consumption and ecological datacenters.

This Nu@ge project tackles several challenges. In this work, we describe a federated architecture which offers the provisioning of virtual clusters of resources over the network while providing administrators with a control over the localization of data and the Quality of Service. Our solution is based on innovative container-sized datacenters that enables deployment of a cost-effective and high-performance datacenter environment in any location, favoring the meshing of regional companyowned datacenters.

This paper is structured as follows. Section II presents the Nu@ge architecture and the associated technical choices. Section III introduces the related work. The prototype is described in Section IV. Section V discusses an evaluation in terms of energy efficiency. Section VI concludes the paper.

II. THE NU@GE APPROACH

Nu@ge defines a software stack as a coherent set of tools to homogenize the management and the exploitation of the resources. This section describes the architecture and its main components.

A. Overview

The architecture of the Nu@ge project addresses several concerns for the administrator:

• Single and shared vision of the whole infrastructure • Simplification of services implementation

• Management of a virtual cluster and an associated QoS A strong basis of Nu@ge is the virtualization of any service. This choice implies to break the link between the logical resources and the physical resources. In particular, we consider only the QoS of virtual/logical resource without consideration of the underlying hardware. Nu@ge aims to be modular and favor the autonomy of each component. In this context, a virtual resource is characterized by its ability to be migrated depending on the following circumstances:

• Hardware defection • Performance optimization • Energy efficiency improvement • Respect of QoS constraint
The unit of administration within Nu@ge is a rack. A rack contains:

• Equipments dedicated to virtualization, called V-nodes • Equipments dedicated to storage, called IO-nodes • Network equipments dedicated to internal communications within the rack • Network equipments dedicated to communication with other datacenters • Electrical equipments allowing the supervision and interventions The high-level components and their features are described below.

B. V-node

A V-node is a physical node dedicated to the execution of virtual systems. Several services related to the infrastructures are required, among:

• Interconnection between Nu@ge and the various IaaS • Setting up of network services • Piloting process of electrical alimentations In the context of Nu@ge, the main virtual machines deployed are:

The Internet Gateway Provides Internet access to the nodes, physical or virtual, present in the Nu@ge infrastructure. This specific machine enables the creation of filtering rules (firewall) in order to set a first level of security for the network services.

The VPN Gateway Offers, through the network, a secure access to Nu@ge's internal resources. Identification, authentication and data encryption are performed with digital certificates. Those are created and managed individually for each Nu@ge user.

The IaaS Gateway This is the component that links Nu@ge to the IaaS platform for the end-user. This virtual equipment is the separation between Nu@ge's area of responsibility and the IaaS administrators.

The DNS Service DNS is a primary service of Internet enabling the translation of simple identifier (ie : http://www.nuage-france.fr) into IP addresses (ie : 195.68.89.215). As a Nu@ge infrastructure service, it allows Internet browsing.

The Storage Access Service Creates dynamically storage units for the IaaS platforms. The storage units are available as file systems or hard drives. This service is linked to an IaaS exposing a dedicated storage zone to the Nu@ge infrastructure.

C. IO-node

The main objectives of the distributed storage system are:

• Availability • Traceability • Integrity and Safety For each IaaS hosted in the Nu@ge architecture, a storage cluster is created. The number and the location of hosts depends on the contract established with the IaaS owner.

IO nodes are machines with significant storage resources. High performance disks allow improvement of current writing/reading operations while traditional disks offer bigger capacity with drawbacks of increased access time and latency.

IO nodes are connected using a dedicated subnetwork, as they need to securely exchange user's data. For that purpose, the nodes had two Gbits/Ethernet interface and an InfiniBand interface.The QoS is guaranteed, in particular during the replication of data, to ensure the resiliency in case a datacenter is suddenly not available. Additionally, the system keeps a journal of the modifications of the data.

Unlike V-nodes, an IO-node provides locally to the close V-nodes the needed storage resources. An IO-node has a high storage capacity and embed sets of hard drives. Each set can contain dozens of hard drive.

D. Communications

We use two kinds of networks within the Nu@ge architecture: the internal, dedicated to the communication between the different IaaS and, the external, used for the interconnection with the end-users.

Internal network allows the creation of private networks between the user's nodes. The setting of private networks requires an IP addressing intra and inter-datacenter, in which the flows of information are encapsulated. As the interconnection with end-user is performed via third-party internet providers, it is necessary to have several networks, depending on the segmentation set by the internet providers.

1) External communication between the datacenters: A simple method would consist of a star network topology, built around a central site with a full redundancy among the links. In a star topology, every node is connected to a central node called a switch. The switch acts as a server and the peripherals as the clients [START_REF] Roberts | Computer network development to achieve resource sharing[END_REF]. However, for obvious reasons of cost and architecture consistency, we do not consider that solution.

Ensuring the same continuity of service, without setting a star network topology, requires to have a number of links superior to the number of Nu@ge datacenters. Without any protocol, the interconnection of those links would cause a loop and prevents the delivery of packets.

STP (Spanning Tree Protocol) is a level 2 protocol (Ethernet) allowing the construction of an Ethernet network without loop 2 . STP presents a simple approach of the problem by cutting some links, to obtain a tree architecture. Due to its simple functioning, STP is widely used despite a few limitations such as the poor repartition of flows and a convergence time up to 30 seconds.

While several extensions to STP address those limitations, a new protocol named TRILL is gaining popularity. TRILL (Transparent Interconnection of Lots of Links) is a IETF standard 3 . This protocol presents the avantages of the routers and the network bridges by creating a level 2 network on the different links available.

Then, the protocol sets dynamic routing tables with MAC addresses. Using this level 2 routing, the protocol ensure to always have the shortest path to route the packets. In the context of Nu@ge, we use TRILL in order to manage Ethernet segmentation.

2) Virtual Machine Mobility: In a context of user mobility and network virtualization, getting a proper identification of an end-user over the network can be a difficult task due to the various possibility of Internet access. The protocol LISP tackles this problem by enabling migration over network while maintaining the same IP address. LISP (Locator/ID Separation Protocol) is a protocol where IP addresses have two roles: localization and identification 4 . The purpose of LISP is to solve problems related to the growing size of IPv4 routing tables. Additionally, the protocol enables users to break the link with a single internet access provider (mobile users). LISP addresses this issue by separating the localization from the identification. An IP address is used in two ways:

• Identify a machine present in a network • Localize the identifier of the machine to route the traffic in an IP network A distributed table of matches allows to find a locator, RLOC (Routing LOCator) from an identifier EID (Endpoint Identifier). LISP is independent of the IP addresses version and can be deployed in an incremental fashion, without the necessity of having the full Internet architecture supporting it.

E. Energy-aware management

The purpose of the energy-aware management is to evaluate the benefit of green scheduling for reducing electric consumption while matching performance objectives for the virtual machines.

The performance criteria is CPU oriented, and based on a measure of the node performance using all its CPU cores. It produces a value in flops, indicating the number of floating points operations per second. Those benchmarks are based on measurements using ATLAS 5 , HPL 6 and Open MPI 7 .

2 STP is defined in IEEE 802.1d-2004 3 TRILL is defined in the RFC 6325 4 LISP is defined in the RFC 6830 5 Automatically Tuned Linear Algebra Software. 6 Portable Implementation of the High-Performance Linpack Benchmark for Distributed-Memory Computers. 7 High Performance Message Passing Library.

Regarding to the consumption criteria, two approaches are possible. A static way would imply to execute a job on all nodes before starting and measured the instantaneous electric consumption corresponding to the completion time on each node. That method is not significant for long periods because the power consumption of the machine may vary depending on the actual load or external conditions, such as the physical location of the server.

In this context, we use a more dynamic approach. The electric consumption metric is based on the number of request handled by a computational node weighted by the power consumption measured during the execution of the server. Thus, every time a client is submitting a request, each computational node will retrieve its electric consumption and total number of requests.

We rely on DIET [START_REF] Caron | DIET: A scalable toolbox to build network enabled servers on the grid[END_REF], an open-source middleware that enables the execution of applications using tasks that are scheduled on distributed resources using a hierarchy of agents for scalability. DIET comprises several elements, including:

• Client application that uses the DIET infrastructure for remote problem solving. • Server Daemon (SED) which acts as a service provider exposing functionality through a standardized computational service interface. A single SED can offer any number of computational services. • Agents, deployed alone or in a hierarchy, it facilitates service location and invocation interactions between clients and SEDs. Collectively, a hierarchy of agents provides high-level and scalable services such as scheduling and data management. The head of a hierarchy is termed as Master Agent (MA) whereas the others are Local Agents (LA).

The steps of the scheduling process are explained below: 1) Submission of a virtual machine creation request A client issues a request describing a virtual machine template. If none of the datacenter is able to create new instances, a notification is returned to the client.

2) Propagation of the request

The request is propagated through a hierarchy of agents.

3) Collect of estimation values

Each agent computes and gathers its metrics, particularly performance and energy consumption. A reply containing those value is sent back to the scheduler.

4) Sorting of candidates

Once the scheduler retrieves all the replies, it proceeds to a sort according to a specific criteria. The first ranked node is then elected and notified.

5) Virtual machine creation

The virtual machine is created on the elected node. Others criteria exists in the literature, involving the consideration of idle consumption [START_REF] Diouri | Your cluster is not power homogeneous: Take care when designing green schedulers![END_REF] or the use rate [START_REF] Lim | A dynamic energy management scheme for multi-tier data centers[END_REF] of the physical nodes.

We coupled the scheduling process to the provisioning of resources while taking into account energy-related events such as fluctuations of electricity prices or heat peaks. This feature [START_REF] Balouek-Thomert | Energy-aware server provisioning by introducing middleware-level dynamic green scheduling[END_REF] enable autonomic decisions from the scheduler by checking pre-defined threshold before executing placement/provisioning decisions.

III. RELATED WORK

This section presents the related work in the context of cloud providers and the existing cloud federation approaches. Then, we detail the notion of modular datacenters and its expected features. Finally, we justify the choice of implementing our own distributed storage solution and the different of energyaware scheduling mechanisms.

A. Cloud Providers

It exists plenty of surveys related to cloud providers [START_REF] Rimal | A taxonomy and survey of cloud computing systems[END_REF] [START_REF] Prodan | A survey and taxonomy of infrastructure as a service and web hosting cloud providers[END_REF]. Table I shows a classification of the current major public IaaS providers. That list of providers is by no means exhaustive, but it includes those that are believed to be the current major players at least in the European and North American markets [START_REF] Ferry | Towards model-driven provisioning, deployment, monitoring, and adaptation of multi-cloud systems[END_REF]. Most of the Cloud providers imposes to operate according to its specific models and protocols. This problem is known as vendor lock-in and restrict the transition and interoperability across providers [START_REF] Satzger | Winds of change: From vendor lock-in to the meta cloud[END_REF]. Furthermore, the headquarters and datacenters location columns show that most providers are based in the USA while only a few are based in the Europe. This constitutes one of Nu@ge's motivation which aims to relocate Cloud Computing in France.

A first step towards solving those problem is provided by IaaS stacks, such as OpenStack [START_REF] Satzger | Winds of change: From vendor lock-in to the meta cloud[END_REF] or VMWare vCloud [START_REF] Buyya | Intercloud: Utility-oriented federation of cloud computing environments for scaling of application services[END_REF], for creating and managing infrastructure cloud services in private, public, and hybrid clouds.

B. Cloud federation approach

The Cloud federation approach [START_REF] Buyya | Intercloud: Utility-oriented federation of cloud computing environments for scaling of application services[END_REF] aims to resolve the issues of both providing a unified platform for managing resources at different levels and abstracting interaction models of different cloud providers. Several European projects are providing stacks and/or adaptation of cloud-based systems at IaaS levels. Contrail [START_REF] Cascella | Contrail: A reliable and trustworthy cloud platform[END_REF], [START_REF] Carlini | Cloud federations in contrail[END_REF] aims at solving the vendor lockin problem by allowing the seamless switch of cloud provider. InterCloud [START_REF] Buyya | Intercloud: Utility-oriented federation of cloud computing environments for scaling of application services[END_REF] is a federated cloud computing environment that aims at provisioning application in a scalable computing environment, achieving QoS under variable workload, resource and network conditions. In the Reservoir project [START_REF] Rochwerger | The reservoir model and architecture for open federated cloud computing[END_REF], the authors propose an architecture for an open federated cloud computing platform. In such architecture, each resource provider is an autonomous entity with its own business goals. Celesti et al. [START_REF] Celesti | How to enhance cloud architectures to enable cross-federation[END_REF], proposed the Dynamic Cloud Collaboration, an approach for setting up highly dynamic cloud federations. In this work, a distributed agreement must be reached among the already federated partners to dynamically federate a new provider.

C. Modular Datacenter

Clouds depend on datacenters, large facilities used to house computer systems and associated components, such as telecommunications and storage systems. A modular data center system is a portable method of deploying data center capacity. As an alternative to the traditional data center, a modular data center can be placed wherever data capacity is needed.

Modular data center systems consist of purpose-engineered modules and components to offer scalable data center capacity with multiple power and cooling options. Numerous manufacturers such as Google, IBM, Sun, Verrari or HP built modular datacenters into standard intermodal containers (shipping containers) with the following key features:

High Density Maximum accommodation of servers, storage and network equipments within a limited surface.

Cost Reduction By comparison to the building and exploitation of a traditional raised-floor data center.

Self-contained Cooling Self-contained cooling technologies, which can enable a cost savings and improve system reliability.

Environmentally Responsible Minimal carbon footprint.

Disaster Recovery and Security Characterized by the time of autonomy of the container and the physical equipments dedicated to ensure its integrity.

Fast deployment Usually expected to be less than 6 months to be put in service after order to the manufacturer.

Industry relies on the TIA-942 specification [START_REF]Tia-942 data center standards overview[END_REF] to classify the minimum requirements for telecommunications infrastructure of data centers and computer rooms into 4 categories, presented in Table II

D. Distributed storage

The Nu@ge project specifications insists on resiliency. In case of the loss of connectivity of a datacenter, the data storage must be distributed among the federation while traceability, integrity and security of data must be ensured. Additionally, the storage system must keep a journal of data modifications to retrieve a coherent state after a incident. The following part evaluates existing distributed storage solutions with the purpose of integrating one suiting Nu@ge needs. Apart from functional aspects, the solution must be mature enough to be considered for production uses.

There is two main categories of storage [START_REF] Sacks | Demystifying storage networking das, san, nas, nas gateways, fibre channel, and iscsi[END_REF] [17], Network Attached Storage (NAS) and Storage Area Network (SAN). Network Attached Storage is file-level computer data storage server connected to a computer network providing data access to a heterogeneous group of clients, while Storage Area Network is a dedicated network that provides access to consolidated, block level data storage.

1) Network attached storage: The Ceph project [START_REF] Weil | Ceph: A scalable, high-performance distributed file system[END_REF] is quite close from our requirements. However, a Ceph cluster can only handle one file system, which is a serious technical restriction.

HDFS [START_REF] Shvachko | The hadoop distributed file system[END_REF] is conceived to distribute computations between several nodes. One of the nodes, the namenode is a necessary gateway to the system. It constitutes a serious bottleneck and is inappropriate for Nu@ge architecture.

GlusterFS, MooseFS, Pohmelfs and XtreemFS presented various limitations. Unstability reasons, troubles with operating system support or lack of contribution support led us to exclude those projects from our choices.

2) Storage area network: Despite its lack of journalization, Ceph project [START_REF] Weil | Ceph: A scalable, high-performance distributed file system[END_REF] features an extensive block data storage. Nevertheless, Ceph cluster gives no information about the localization of data. In this context, data traceability, one of the main objective of Nu@ge, could be achieved only by creating a Ceph cluster per datacenter. This solution is not worth considering due to the high resource consumption of Ceph. Sheepdog [START_REF] Morita | Sheepdog: Distributed storage system for qemu/kvm[END_REF] seems relatively inactive and only works with QEMU/KVM virtualization technologies. Some of Sheepdog technical choices would lead to scalability problems in terms of storage or number of datacenters.

Unfortunately, there were no project fitting our requirements among those two categories. In particular, the notion of journal is not a common feature and would be hard to implement among an existing file system. We decide to initiate a new project over a SAN, as it is less complex to implement. Unlike a NAS that needs the installation of a software on the client desktop, block level data storage can be access through standard protocols (specifically iSCSI [START_REF] Satran | Internet small computer systems interface (iscsi)[END_REF], supported in a native fashion by numerous operating systems).

E. Energy-aware scheduling

Despite the increasing popularity of Cloud computing, infrastructures on which they rely are seldom fully utilized [START_REF] Hawkins | Unused servers survey results analysis[END_REF], mostly as result of overprovisioning to handle peak demands. Workloads with large variations in demand can lead to periods of low resource utilization. As resources are generally not energy proportional, meaning their power consumption at low load is already high, the energy efficiency of an infrastructure is reduced during such periods. Power saving techniques proposed to circumvent such problems consist in slowing down certain server components [START_REF] Carrera | Conserving disk energy in network servers[END_REF], [START_REF] Snowdon | Power management and dynamic voltage scaling: Myths and facts[END_REF] during periods of light load -techniques that according to Le Sueur et al. are becoming less attractive on modern hardware [START_REF] Sueur | Dynamic voltage and frequency scaling: The laws of diminishing returns[END_REF] -or using software techniques to put idle servers into low power consumption modes [START_REF] Beloglazov | Managing overloaded hosts for dynamic consolidation of virtual machines in cloud data centers under quality of constraints[END_REF], [START_REF] Feller | Snooze: A scalable and autonomic virtual machine management framework for private clouds[END_REF]. These techniques are well suited to Clouds where virtualization is mainstream.

In the context of Nu@ge, the authors provide techniques for assigning virtual machines to federated resources, by exploring energy efficient resource provisioning. We defined mechanisms to adapt resource allocation according to energyrelated events and administrator-defined rules [START_REF] Balouek-Thomert | Energy-aware server provisioning by introducing middleware-level dynamic green scheduling[END_REF]. We take benefit of the plug-in scheduler functionality of the DIET middleware [START_REF] Caron | DIET: A scalable toolbox to build network enabled servers on the grid[END_REF] to evaluate.

IV. PROTOTYPE

This section briefly describes a prototype implementation of the Nu@ge project, that follows the architecture described in Figure 2. Such implementation has been used for evaluating performance and feasibility of the proposed approach. The

A. Roles

The IaaS administrator is in charge of the virtual infrastructure offered by Nu@ge. The Nu@ge administrator sets and configure resources (physical or virtual nodes, storage disks, virtual routers...).

B. StarDC

The StarDC (Figure 1) features 4 service units of 19 inches racks and can hold up to 168 computing servers. The container facility spans 15 square meters, a power capacity of 18 kilowatts and a Power Usage Effectiveness (PUE) of 1.24. The StarDC is built within Tier 3 specifications and is the subject of a patent.

Unlike most of the modular datacenters, the StarDC does not use water cooling. It allows an easier implantation, a broader range of physical locations and an eco-responsible behavior since ambiant air is used to cool the container. The StarDC uses a mechanism of temperature uphold using outdoor air as a free cooling source. The purpose is to take advantage of outdoor temperatures to obtain a natural chilling of equipments. When the air is injected into machines, its temperature raises by a delta number of 10 ˚(common value among commercialized servers). In case the outdoor temperature is higher than required, we use air conditioning to chill it.

The Nu@ge customer is in charge of the setting of the cold aisle temperature. If he chooses a temperature of 20 ˚to favor confort of use, the air conditioning will be active approximately 20% of the year (varies depending on the location). Choosing a temperature value up to 25 ˚and more results in less air conditioning and a better ecological impact.

C. Construction of a IaaS

The creation of a new IaaS does not impact the architecture of Nu@ge. The main evolution concerns the evolution of the virtual nodes allowing the mutualisation of physical resources. In particular, the instantiation of:

• A storage access point

• An IaaS access point • A virtual switch interconnecting the IaaS equipments A a result, several IO-nodes and V-nodes can be used by multiple IaaS.

D. Storage cluster

Nu@ge racks contains two IO-nodes. As storage management can require large computational resources, an IO-node features dual-core CPUs for a total of 24 threads and 256 gigabytes of RAM. Deployment of IO-nodes is performed via the following steps:

1) Booting via PXE / TFTP protocols 2) Configuration using Puppet 3) Creation and configuration of an object storage in RAID1 4) Creation and configuration of RAID6 objects 5) Creation of logical volumes At this point, the node executes an Openstack storage service specific to the newly created IaaS, and the storage server. This organization is coherent with Nu@ge objective of data isolation between IaaS and data traceability for the administrators.

V. DISCUSSION

The Power Usage Effectiveness is a usual metric to evaluate the green quality of a datacenter [START_REF] Belady | Green grid data center power efficiency metrics: PUE and DCIE[END_REF]. From a practical point of view, it is a measure of how efficiently a computer data center uses energy; specifically, how much energy is used by the computing equipment (in contrast to cooling and other overhead). The PUE is expressed by the ratio:

P U E =
T otalF acilityP ower IT EquipementP ower

Nevertheless, it is very hard to know the real PUE from a company because the area of Equipment Power can be debatable. As an example, for the Google Data center, if Google considers only the servers and the air conditioning, Google gives a PUE of 1.06. But if Google add generators, transformers, site substations and natural gas then the PUE is 1.14.

Green Datacenter from green.ch company (Switzerland) was designed with energy efficiency and reduction consideration. This project is based on energy-optimized data center architecture, latest generation of air conditioners, heat exchangers, waste heat utilization in new office building.

The container-sized datacenter designed by Nu@ge aims at keeping the PUE under the value of 1.30, using two cooling operating modes:

• Total free cooling when the room temperature is in-range with the servers specifications. That range is set by the customer resulting in a PUE value of 1,16. • Air recycling with air conditioning when the temperature is out of range results in a PUE value of 1,55. Thus, the PUE relies strongly on the climate conditions, and customer-defined rules. In the case of Nu@ge's StarDC at Marne-La-Vallee (France), weather forecast indicates that 80% of the time, the temperature is below 23 ˚. The theoretical maximal value for the PUE is then:

P U E N u@ge = 80% × 1. [START_REF] Sacks | Demystifying storage networking das, san, nas, nas gateways, fibre channel, and iscsi[END_REF]

VI. CONCLUSION

The Nu@ge project aims at designing and building a network of modular datacenters dedicated to the virtualization of IT services. This architecture can be referred as "Cloud" with the following guarantees:

• Control over the underlying infrastructure • Knowledge of data location • Control over the different QoS By using Nu@ge, a final user (ie. the administrator of an IT system) is focus on the management of a virtual cluster seamlessly spread on a collection of datacenters with a support on the infrastructure supervision.

Fig. 1 .

 1 Fig. 1. The public presentation of the StarDC container occured on September 18th 2014 during Nu@ge inauguration in CELESTE headquarters, Marne-lavallee, France.

  prototype has been realized by using a customized version of OpenStack over 4 different geographic locations in France.

Fig. 2 .

 2 Fig. 2. Nu@ge architecture including gateways and a IaaS

  .

		Characteristics of the site infrastructure design	Theoretical
		topology	availability
	Tier 1	Single path for power and cooling distribution. No redundant components.	99.671%
	Tier 2	Single path for power and cooling distribution. Includes redundant components	99.741%
		Multiple power and cooling distribution paths.
	Tier 3	Only one active path. Includes redundant components.	99.982%
		Concurrently maintainable.
		Multiple power and cooling distribution paths.
		All paths are active.
	Tier 4	Includes redundant components.	99.995%
		Concurrently maintainable.
		Fault tolerant.

  + 20% × 1.55 = 1.24[START_REF] Caron | DIET: A scalable toolbox to build network enabled servers on the grid[END_REF]

	Data Center	Company	PUE
	Prineville DC	Facebook	1.07
	Google DC	Google	1.14
	StarDC	Nu@ge	1.24
	Green Datacenter	grench.ch	1.4

TABLE III PUE

 III COMPARISON OF DIFFERENT DATACENTERS. THOSE VALUES ARE GIVEN BY EACH PROJECT BUT NO INDEPENDENT EVALUATION WAS DONE.

ACKNOWLEDGEMENTS

Nu@ge is a research project funded by the FSN (Fund for the Digital Society, BPI France) as part of the Investissements d'Avenir program.

The authors acknowledge the support of the Nu@ge consortium, composed of the following members: NON STOP Systems, secure cloud solutions provider; CELESTE, Internet provider and manufacturer of the StarDC; Oodrive, online storage specialist; DotRiver, private network operator; New GenerationSR, Green IT consulting; LIP6, laboratory and its research team REGAL and PHARE of UPMC University, Paris.