Gaël Pillonnet

Nicolas Jeanniot

Pascal Vivet

3D ICs: An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies

Keywords: Fully-integrated power supply, switched capacitor converter, multi-core, on-chip voltage regulator, 3D power management

With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2 ) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.

I. INTRODUCTION

Fully-integrated dc-dc converters seem to be a powerefficient solution to supply a heterogeneous System on Chip (SoC) on the same package such as multi-core processors (Fig. 1). The advantage is to provide clean, fine, high speed and individual power supply modulation for the various blocks in the SoC without bulky off-chip passive components or numerous power pins [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF].

Nonetheless, the recently published on-die power converters integrated in the same process as the digital core, i.e. the most advanced technology, still achieves performance far from the industrial targets in terms of power density, voltage regulation, efficiency versus conversion ratio or direct battery connection compatibility [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF], [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF], [START_REF] Wibben | A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors[END_REF].

Due to the difficulty in integrating on-die dense passive components [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF] and high voltage-rating transistors in recent CMOS technology, 3D integration is a key opportunity to propose an alternative and efficient way between off-and ondie converters by using a less recent and more compatible technology to integrate active and/or passive components in DC-DC converters [START_REF] Wibben | A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors[END_REF], [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF], [START_REF] Ishida | 3D stacked buck converter with 15 µm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's[END_REF].

This paper aims to compare the 2D and 3D approaches using one or multiple active and passive layers to improve the achievable efficiency of the integrated power supplies of a multi-core processor. The 65nm bulk (mature, high yield), 28nm FDSOI (dense integration, large DVFS capability [START_REF] Beigne | A 460 MHz at 397 mV[END_REF]) process and a potential TSC technology in a passive layer (high capacitance density [START_REF] Guiller | Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer[END_REF]) are studied in this paper. This comparison leads to the key question: how much area is needed to integrate power supplies from this combination of three technologies to reach targeted power efficiency?

To answer this key question, the power partitioning, converter structure, main design trade-off and different technology combinations are first introduced. Then, the converter efficiencies are compared using a combination of 28, 65nm and TSC technologies. The analysis leads to a discussion Fig. 1. Possible integration of quad-core processor and its dedicated granular power supplies.

of the opportunities of using 3D technology and the possible trends for more efficient on-chip power management in a single-chip multi-core system.

II. POWER MANAGEMENT DESCRIPTION

A. Power Tree Partioning

A typical power tree consists of two or three cascaded DC-DC conversion stages as shown in Fig. 2. The first step-down converter provides an intermediate power rail V dd from the primary supply bus V in e.g. from a chemical battery. An inductive-based switching converter is often used mainly to keep high efficiency over a large conversion ratio and at high current. Designing by power electronics community, the first stage is traditionally off-chip converter chosen in currently available buck type regulator. The V dd value is chosen to provide a compatible input voltage rating for the on-chip second stage, typically 1.8V where the greater this power rail value, the less current there is, thus requiring fewer power pins for the packaging.

In the latest N-core processor generation [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF], the second stage provides individual DVFS technique for N cores to dramatically reduce the processor consumption. It includes N converters as close as possible to the N cores to provide fast and clean power supplies. These converters could be off-chip, in-package or on-die. Off-chip i.e. an on-board solution (Fig. 1, left scheme) fails to meet the fast power demand of the different supply domains in the multi-core system mainly due to the trace impedance [START_REF] Guiller | Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer[END_REF]. Moreover, the N off-chip converters around the N-core processor occupy a large area on the PCB and need numerous power pins. Only in-package and on-die seem to be relevant solutions for granular power management (Fig. 1, other schemes). With the prospect of integration, the design of the second stage is mostly handled by the VLSI community.

A third stage could be added to protect against severe transient signals and so reduce the fluctuation of the power supply even if each step includes bypass capacitors and fasttransient feedback to smooth the power rails. For example, the current profile varies with tens of A per ns in real processors [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. Typically, N small-area linear regulators are implemented on-die i.e. closest to the N cores. As the conversion ratio is close to one, their efficiency can be more than 90% [START_REF] Gjanci | A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)[END_REF].

B. Converter Topology in the Second Stage

Linear voltage regulators are widely used in the second stage thanks to their dense integration [START_REF] Gjanci | A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)[END_REF]. Unfortunately, they suffer from low efficiency when the output voltage is not close to the input voltage. In the second stage, the input voltage is 1.8V and the output varies from 0.5 to 1V leading to less than 50% efficiency for a linear regulator. Some published work suggests replacing the linear regulator by the switched converter for power efficiency improvement ( [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF], [START_REF] Wibben | A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors[END_REF]). However, the inductive-based switching converter suffers from low on-chip integration as the magnetic-core inductor is not compatible with CMOS process [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF]. Therefore, with this topology, it is difficult to compare on-die and in-package solutions. Switched capacitor converters (SCCs) have been well studied to alleviate this problem. This approach offers easier on-chip integration thanks to the high capacitance density in recent CMOS technologies [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF], [START_REF] Biswas | A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency[END_REF]. However, SCCs also have different drawbacks such as efficiency dependence on conversion ratio and large input current pulse i.e. a potential EMC issue.

A non-external SCC component needs silicon area to integrate the capacitor which could be costly if they are integrated on the same die as the digital functions in most recent technology. However, 3D technology stacking of the N converters or their passive components just below the N cores is an alternative. It potentially reduces the overall cost of the chip saving costly silicon die by replacing the last digital technology by thicker or fewer-step processes. The active layer can also integrate other functional blocks such as non-volatile memory or intra-core communication which slightly gain performance from the CMOS scaling.

The 2:1 SCC topology is studied here because of its excellent integration capacity proved in the standard CMOS process [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF]. Under ideal conditions, the converter reduces the 1.8V voltage rail generated by the first stage to 0.9V. If other voltages are needed, N:M conversion ratios and voltage regulation of SCC are possible [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF].

The SCC mainly consists of a flying capacitor C fly charged and discharged in two phases by four switches as shown in Fig. 3.a. In the first phase, ϕ 1 , T 1 and T 4 are in on-state and the capacitor is charged from the input voltage through the output load. In the second phase, ϕ 2 , the flying capacitor is discharged into the load through T 2 and T 3 . Between the two phases, a dead time is introduced to avoid cross-conduction between the output, input voltage and ground (Fig. 3.b). The T 4 transistor is an N-type to improve its driving capability when the output voltage is lower than V dd /2.

In steady-state and under ideal conditions (infinite capacitor and switching frequency values, ideal switches), the output

V dd V core V 2 V 1 V 4 V 3 V 1 V 2 V 3,4 t C fly t dt V dd T 1 T 2 T 3 T 4 (a) (b) ϕ 1 ϕ 2 V cfly V dd V dd V dd V dd
Fig. 2. Third-stage power partioning

V in

N Switching Converters

N cores N Linear Converters 1 Switching Converter in-package or on-die on-die off-chip

First stage

Second stage (Third stage)

V dd V core voltage V core is equal to V dd /2 and the converter efficiency reaches 100%. In practical conditions, the switches introduce conduction and switching losses. Moreover, the capacitance value is limited by the finite silicon area which induces a charge/discharge loss and output voltage ripple. To predict the efficiency and gain physical insight, small signal models of this structure are given in the literature [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF], [START_REF] Ben-Yaakov | Behavioral Average Modeling and Equivalent Circuit Simulation of Switched Capacitors Converters[END_REF] as shown in Fig. 4.a. The resistances R c and R p represent the conduction and switching loss, respectively. In following the switching loss means the loss due to the charge and discharge of the gate capacitance, not the loss induced by the nonzero V ds ×I ds product during the switching. The overall loss can be summarized by the following equation from [START_REF] Pascal | Efficiency comparison of capacitor-, inductor-and resonant-based converters fully integrated in CMOS technology[END_REF] in SSL or FSL regions [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF]:

= ! ! ! " + 1 2 & '( ' 1 ) *+ ,- + & '( .
/0 1 ! ! 23 4

+ '( 5 6 7 8 9 : ;

<2 2= /! " + & '( > ?@ ABC 9 +D E F"G H! ! 23 = "G! " (1)
where, is the width of each transistor, ; the switching frequency, the gate capacitance density (expressed in F/m), ' the on-state resistance density (Ω×m metric) and 5 6 7 the parasitic to flying capacitance ratio.

Assuming the area of the switches is negligible, the flying capacitor is set by the desired surface of the SCC and capacitance density (F/m 2 ) offered by the targeted technology i.e. an area constraint optimization. The variables I; , K are the only design freedom parameters to maximize the power efficiency under a load profile I '( , & '( K defined by the digital core. As shown in Fig. 4.b, the maximal efficiency is obtained at an optimal value L; M7 , M7 N where M7 represents the total width of the switches. The optimal output voltage V opt is below a 2:1 voltage gain due to the finite equivalent output resistor R c (Fig. 4.a). It is important to notice our optimization maximizes the power efficiency without guarantee on the output voltage.

The SCC provides a sufficiently fast transient response to meet the load transient requirement as proven in [START_REF] Andersen | A 4.6 W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF], [START_REF] Souvignet | Sampled-Data Modeling of Switched-Capacitor Voltage Regulator With Frequency-Modulation Control[END_REF]. If a small voltage regulation range is required, the switching frequency could be slightly modulated. However, the efficiency is reduced as the SCC acts as a linear regulator outside its optimal 2:1 ratio (Fig. 4.b). As previously mentioned, this is one of the limitations of switched capacitor topology. For large output voltage regulation, reconfigurable SCC [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF] or MISO [START_REF] Pillonnet | Dual-input switched capacitor converter suitable for wide voltage gain range[END_REF] topologies can be used to maintain higher efficiency.

C. Area constraint of the on-die and in-package converters

The on-die solution requires the area of the core die to be increased as shown in Fig. 5. An additional area of 10% seems to be an acceptable solution for industry. On the other hand, a 3D solution could offer more flexibility in terms of area constraint. For instance, to keep the same chip surface, the surface of the stacked converter could be equal to the size of the digital core. However, the final choice is made according to the cost of the overall chip including the silicon die, 3D assembly and packaging. Unfortunately, the authors have insufficient data to provide a relevant cost analysis. Here, the 65nm and TSC process are expected to be far cheaper than the 28nm allowing more space allocation for an in-package SCC for the same price.

D. Load Profile

The power consumption of an MIPS32 core within the TSAR architecture [START_REF] Guthmuller | Architectural exploration of a fine-grained 3D cache for high performance in a manycore context[END_REF] in FDSOI is used to define the converter's consumption profile I '( , & '( K. The one digital core is modelled by a current source controlled by a voltage source defined as:

& '( = '( + 0.2 '( -0.1 (2)
For example, the power consumption is about 0.9W for a 0.9V core voltage. The die area of one core is approximately 21mm 2 . (This value is the S core in Fig. 5 and will be kept in the following analysis.) The power density is then 43mW/mm 2 , which is relatively low compared to current digital dies (about 1W/mm 2 ).

III. COMPARISON OF CONVERTER EFFICIENCY

A. Key Parameters for an Efficient Converter

Equation (1) predicts the SCC efficiency using three technology parameters: ' , and 5 6 7 . For example, ' and illustrate the switch capacity to reduce the conduction and switching losses, respectively, i.e. the 2 nd and 1 st terms in this equation. In this paper, thick oxide 150nm-and 280nm-long channel transistor R in 65 and 28nm technologies, respectively, are chosen to allow 1.8V input operation. The figure of merit (FoM) for the switch, well used in the power community, results from the trade-off between conduction and switching capacity and is given by:

;ST = . U × W X = ' × × ' Y( (3)
where, . U is the on-state resistance, W X the total charge The capacitance density Z is also a key parameter as the flying capacitor value is strongly linked to the achievable efficiency as shown by the 5 th term in [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. The two technologies offer poly/nwell and MIM capacitances. The high density poly-type capacitance i.e. thin oxide, is not permitted in the SCC design as the maximal voltage value across the flying capacitor (1.2V max in steady-state, 1.4V in transient) is higher than its maximal voltage rating (1V in 28nm and 1.2V in 65nm). The thick oxide poly-type capacitance was chosen as it offers a higher voltage rating but lower density. It also suffers from a non-negligible bottom plate capacitance which influences the efficiency as shown by the 4 th term of equation ( 1). The 5 6 7 parameter is expressed as:

5 6 7 = @ [,\ @ ABC (4)
Moreover, the poly capacitance area cannot be reused to stack the transistors of the digital core as it already uses the polysilicon layer. The MIM-type could be stacked on the polytype capacitor to gain density but the MIM option adds a slight cost (a few % more). Here, the 5 6 7 coefficient for MIM is assumed to be zero as the metal layers for the plates are far from the bulk i.e. typically on the 5 th and 6 th layers. For all capacitor types, the equivalent series resistor (ESR) is assumed to be negligible (though non-negligible in practice). This paper studies an ideal case which involves a lower SCC efficiency in reality.

B. Technology Capability

To highlight each technology capability, Table 1 gives the most critical parameters which influence the SCC efficiency. The best parameters are highlighted in bold. Concerning the switching capability, the two technologies offer a similar ;ST . The total stacked capacitance in the same surface is about 50% higher for the 28nm node which potentially allows the best power density for the SCC i.e. reducing the 5 th term in [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. In practice, the capacitance density is less than the given value for both technologies (see Table 1) as some partitioning is needed to reduce the effective ESR. The FDSOI process suffers from a higher bottom plate coefficient 5 6 7 thus increasing the 4 th term in (1). Table 1 gives an overview of the main advantages and disadvantages of these technologies but it fails to give an exact figure for the achievable efficiency of an SCC for a given surface. However, section III.D will discuss this.

C. Vertical Capacitor Integration: a Relevant Option

The previously mentioned capacitors (poly and MIM) have planar plates. The surface density σ ^F/m ) is mainly limited by the thickness of the dielectric b (about 1nm) and is expressed as:

σ = @ c = d c ( × > c = e ( (5)
Where, S is the surface required for the capacitor, and d is the permittivity.

The vertical capacitor is an alternative solution to alleviate this problem. For example, deep-trench capacitance has proven its ability to reach a high density value and efficient SCC on a smaller area [START_REF] Paul | Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities[END_REF], [START_REF] Andersen | A 4.6 W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF].

In recent literature from the 3DIC community, the through silicon capacitor (TSC) is introduced [START_REF] Guiller | Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer[END_REF]. The main advantage is its higher capacitance density compared to planar CMOS capacitance e.g. poly or MIM. As the SCC efficiency strongly depends on the capacitor value, this paper will also explore the TSC option as well as the planar capacitance. Fig. 6 shows the three possible stacking arrangements in the context of this paper. The first solution consists in integrating the TSC in the 65nm die where through silicon via (TSV) does not take up the total die area). The TSV is not shown in Fig. 6. The second solution is to have an additional layer with specific technology which integrates the passive components i.e. TSC capacitors. The third solution is to integrate the active part of the converter in a 28nm die i.e. the switches and control, and to use a passive layer for TSC capacitance. In all cases, the available on-die capacitor (poly and MIM) could also be used to improve the overall capacitance density.

Based on the literature and the expected evolution of this promising technology, a 100fF/µm 2 capacitance density with no bottom plate (5 6 7 = 0) and no ESR are assumed in the following sections.

D. Simulation-based Optimisation and Comparison

The same 2:1 SCC topology (Fig. 3) in both technologies is optimized to reach maximal power efficiency. The conditions are to supply the MIPS32 core defined in II.C with 1.8V input voltage for a given die area. The dead time is set to 500ps and the driver loss is taken into account. Figure 8 shows the achievable power efficiency versus die area of the SCC topology using 28 and 65nm nodes with planar (poly and MIM combination) and vertical (TSC) capacitances. These results come from transistor-level simulations. Fig. 8 shows the maximal efficiency achievable by SCC occupied a silicon surface from 0.1 to 50mm 2 for different capacitance options: poly only, poly and MIM stack, and TSC only. As our optimization does not guarantee any output voltage, the two gray lines illustre the achievable output voltage value. For examle, 0.8V and higher output voltage is reached at maximal efficiency in few cases: only surface higher than 10mm 2 for TSC option and than 25mm 2 in 28nm with MIM. To clarify the difference between the maximal efficiency at the optimal ouptut voltage (V opt ) and the achievable output voltage at a lower efficiency (V max ), two optimisation cases are traced in Fig. 7 where η is the efficiency and M is the conversion ratio (V core /V dd ).

In a poly configuration, the 28nm node is less efficient than 65nm. For example, the power efficiency in 28nm is decreased by 8 points for the same 1mm 2 surface or the area is multiplied by 6 to keep 73% efficiency compared to 65nm. This is mainly due to the high parasitic capacitance i.e. the 4 th term is predominant.

In the poly and MIM stack configurations, the 28nm process offers the best efficiency over the whole die area range. This is mainly due to better capacitance density as already shown in Table 1. The poly-type capacitance is removed from the stack in 28nm due to a high 5 6 7 parameter. The capacitance density Z H, p is lower but the overall efficiency is better allowing higher switching frequency. Now, 28nm has four points of efficiency more than 65nm at 1mm 2 . To keep the same efficiency, the converter needs to be 50% larger in 65nm than in 28nm. Thus, the surface area saved in the expensive 28nm die could cover the additional cost of a larger 65nm die.

The vertical capacitance improves power efficiency in both technologies. For 1mm 2 converter area, the efficiency is improved by 23 points in 28nm. The gap between 28nm and 65nm is negligible as the switch characteristics are equivalent (see Table 1). This option confirms the major role of the dense passive layer to propose efficient and dense integrated DC-DC converters. A decrease in surface highlights the benefit of using TSC.

For the processor being studied here, 10% additional area is allocated for its on-die power supply (see section II.C), meaning 2.1mm 2 of 28nm using poly-type capacitance. From Fig. 8, the power efficiency is equal to 65%. For in-package solution, the 65nm area could be up to 21mm 2 implying 87% power efficiency. If the MIM could be integrated on the top of the digital core, the surface dedicated to the SCC is S core . In this V opt V max V max optimization @S optimization @S'<S case, 92% efficiency is possible in 28nm, better than the inpackage solution. The TSC option improves the efficiency to 96% in both technologies as S core is used to integrate TSC capacitors (Fig. 6). Table 2 resumes the different options in 2D and 3D contexts.

If the power density of the load increases e.g. 1mm 2 instead of 21mm 2 , the dedicated area in 28nm-poly case is reduced to 0.1mm 2 leading to less than 50% efficiency i.e. lower than a linear regulator. Therefore, we can say that the introduction of TSC increases the efficiency to 90% as the flying capacitor covers the same area than the digital load i.e. 1mm 2 . To conclude, high power density digital load needs special layer such as TSC to reach acceptable efficiency and output voltage.

E. Optimal Switch Width and Switching Frequency

The optimal L; M7 , q N parameters of the four SCCs are given in Fig. 9. The total switch width is given by: M7 = ∑ ? s> = 3 × q + 2 × q + q + 2 × q (6)

A decrease in surface area, increases the switching frequency to compensate the 5 th term in [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF], but also decreases the total switch width to limit the 1 st term in [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. For 1mm 2 , the on-die converter operates at a 100MHz switching frequency with a total transistor width of 10mm for both technologies. These similar results can be explained as the result of a global optimization of all terms in (1).

The TSC option reduces the optimal switching frequency from 100 to 20MHz for 1mm 2 . This lower frequency leaves room to increase the total switch width as all terms in (1) are optimized at the same time. However, it is important to point out that the surface of the switches is far lower than the SCC area confirming the negligible surface of the switches, as:

u = M7 × R ≪ u '( (7)
F. Losses distribution Figures 10 and11 show the loss distribution in 65nm node with poly and MIM stack configuration at 27mm2 silicon surface (S core ) when the frequency or transistor widths vary. The losses are distributed between DC and AC conductions, bottom plate and driver which correspond to 2 nd , 4 th , 3 th and 1 st terms in equation ( 1) respectively. The woth ^{ ) coefficient places the SCC behavior in the SSL or FSL regions [START_REF] Ben-Yaakov | Behavioral Average Modeling and Equivalent Circuit Simulation of Switched Capacitors Converters[END_REF]. In Fig. 10 and 11, the optimal point to reach the maximal efficiency is L; M7 , q N = I9T~•, 34••K (see Fig. 9). For example, if the switching frequency decreases, the efficiency is reduced due to the AC conduction loss (Fig. 10). In this case, the SCC is in SSL region. In opposite, if the switching frequency increases (FSL region), the power feeds by the gate drivers and the bottom plate charge/discharge phenomena are increased then reducing the SCC efficiency. To conclude, these Figures clearly show the optimal point and losses distribution when the L; M7 , q N couple varies.

Fig. 12 shows the loss distribution at the maximal efficiency when the SCC surface varies from 0.05mm 2 to 50mm 2 . At higher surface i.e. higher flying capacitance value, the bottom plate loss contribution increases. The optimal SCC region is between SSL and FSL as woth ^{ ) is close to the unity.

G. Towards Reducing the Pin Number

By using higher voltage-rating components, the input voltage can be increased which then reduces the current through the power pins. Therefore, the number of pins is reduced in the final packaging. In the context of this paper, the 65nm process offers a 2.5V voltage rating transistor and 1.8V capacitor and so the 2.5V input voltage rail can divide the current by 0.7 compared to 1.8V case. The IO pins can be reduced by 50% to keep the current constraint. This scaling is more difficult in 28nm as the maximal voltage of the MIM capacitor is limited to 1.4V. Moreover, the switches have to be cascaded reducing the FoM s defined in (2).

H. Limitations and strengths of this analysis

A comparison has been made using assumptions justified in the previous sections: i) maximal capacitance density, ii) no capacitance ESR, iii) no effect of the interconnection (layer to layer), iv) no power consumption from the feedback, v) only 2:1 ratio analysis, vi) negligible effect of the layout especially on 5 6 7 , vii) low density digital core, viii) no static or dynamic FDSOI back biasing, ix) only results from transistor-level simulations, x) no driving swing optimization, xi) no interleave scheme, xii) no thermal analysis, xiii) no output voltage guaranteed in the optimization procedure. However, in practice, the power efficiency will be lower. The inductivebased converter is also not studied even if published work [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF] has proven their capacity for a dense and efficient converter with a passive layer.

The above assumptions are chosen to analyze the maximal efficiency achievable by the two technologies under the same constraints. Our aim is to avoid a table comparing previous published work using heterogeneous technologies (MIM, deep trench, SOI) under different constraints (load current profile, input voltage, die area) [START_REF] Biswas | A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency[END_REF], [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. On the one hand, the key advantage of these tables is to access the achievable efficiency in practice. On the other hand, the comparison range may be too large to clearly underline the effects of the process and design choices.

IV. DISCUSSION AND TRENDS

This study confirms that 3D technology is a relevant candidate to provide an efficient integrated power supply in a multi-core processor context. As DC-DC converters do not directly benefit from scaling technology, the additional active or passive layers in a 3D context allow a higher voltage rating transistor or higher capacitance density which better suits the converter requirements. This solution saves the expensive diearea of digital cores, improves the silicon yield, increases the acceptable input power supply and therefore reduces the pin number for the external package. The recent improvement for high capacitor and inductor value integration in a process including a small number of steps argues in favor of this.

The authors believe that the future of granular power management is 3D with dedicated layers for power as shown in Intel's choice [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF] rather than on-die converters. 3D design also allows multiple layers to integrate N converters in parallel to again improve the power density. However, the best topology between inductive-, capacitive-or resonant-based converters is not clear cut as it strongly depends on the passive performance offered by the emerging 3D technologies.

Fig. 3 . 2

 32 Fig. 3. 2:1 SCC topology

Fig. 4 .Fig. 5 .

 45 Fig. 4. Small signal model and power efficiency v. voltage gain

  Note: in bold, the best benefit value in terms of converter design (1) Thick oxide 150nm-and 200nm-long channel transistors in 28 and 65nm technology, respectively; driving voltage 1.8V; (2) Thick oxide polysilicon capacitors at 1.0V bias with 1.8V maximal voltage rating; (3) additional layers needed for Metal Insulator Metal capacitor option, the bottom plate of the MIM is negligible. In 28nm, the MIM voltage rating is 1.1V (4) included in the DKit model (not post-layout extracted).

Fig. 6 .

 6 Fig. 6. Stacking configuration to integrate TSC in the power distribution.

Fig. 8 .

 8 Fig. 8. Power efficiency v. die area in 28 and 65nm nodes from transistor-level simulations.

Fig. 7 .

 7 Fig. 7. Maximal efficiency versus maximal output voltage

Fig. 9 .

 9 Fig. 9. Power efficiency v. die area in 28 and 65nm nodes from transistor-level simulations.

Fig. 10 .Fig. 11 .Fig. 12 .

 101112 Fig. 10. Loss distribution v. switching frequency at the optimal width for 65nm in poly and MIM stack configuration (S=27mm 2 )

ACKNOWLEDGMENT

The authors wish to thank Guillaume Moritz, Yoann Pascal, Stéphanie Robinet, Fabien Clermidy and the IC designers of the LGECA and LISAN labs in the CEA-LETI research institute for their fruitful collaboration.


Nawal Benabbou
email: nawal.benabbou@lip6.fr

Possible Optimality and Preference Elicitation for Decision Making

Decision support systems often rely on a mathematical decision model allowing the comparison of alternatives and the selection of a proper solution. In the field of Multicriteria Decision Making, an aggregation function is often used to synthesize the different evaluations of each alternative into an aggregated value representing its overall utility. The aggregation function must be sufficiently expressive to efficiently approximate the decision maker's preferences in human decision support, or simulate a prescribed decision behavior in automated decision systems. This explains the diversity of decision models available in the literature but also the increasing interest for sophisticated parameterized models such as the Choquet integral [START_REF] Schmeidler | Integral representation without additivity[END_REF][START_REF] Grabisch | A decade of application of the Choquet and Sugeno integrals in multi-criteria decision aid[END_REF] which enables the representation of complex preferences and includes many other models as special cases (e.g. leximin and lexicographic aggregators [START_REF] Fishburn | Axioms for lexicographic preferences[END_REF], the Ordered Weighted Average operator [START_REF] Yager | On Ordered Weighted Averaging aggregation operators in multicriteria decision making[END_REF], and Weighted Ordered Weighted Average [START_REF] Torra | The weighted OWA operator[END_REF]).

To make use of such models, one needs to assess the model parameters in order to fit to the decision maker's preferences. Most of the previous work on the elicitation of Choquet integral parameters consider a static database of preference statements, and focus on the determination of the parameters that best fit to the available database (e.g. [START_REF] Grabisch | Fundamentals of Uncertainty Calculi, with Applications[END_REF][START_REF] Marichal | Determination of weights of interacting criteria from a reference set[END_REF][START_REF] Meyer | On the use of the Choquet integral with fuzzy numbers in multiple criteria decision support[END_REF][START_REF] Grabisch | A review of methods for capacity identification in Choquet integral based multi-attribute utility theory[END_REF][START_REF] Grabisch | Aggregation Functions. Encyclopedia of Mathematics and its Applications[END_REF]) for instance by minimizing a quadratic error. However, these approaches require a relatively large number of preference statements to model the decision maker's behaviour accurately which are not always possible to obtain. Preference elicitation with limited available information is a crucial task in many application domains, including recommender systems and interface customization [START_REF] Peintner | Preferences in interactive systems: Technical challenges and case studies[END_REF]. Departing from these standard approaches, we consider incremental elicitation methods based on the minimax regret which is a decision criterion that has been advocated as a means for robust optimization in the presence of data uncertainty [START_REF] Kouvelis | Robust Discrete Optimization and Its Applications[END_REF] and has been used for decision making with utility function uncertainty [START_REF] Boutilier | UCP-Networks: A directed graphical representation of conditional utilities[END_REF][START_REF] Salo | Preference ratios in multiattribute evaluation (PRIME)-elicitation and decision procedures under incomplete information[END_REF][START_REF] Boutilier | Constraint-based Optimization and Utility Elicitation using the Minimax Decision Criterion[END_REF]. The general principle of this approach is to iteratively ask questions to the decision maker so as to reduce the set of possible parameters until the preferred alternative can be detected with some guarantees (as given by the minimax regret). This elicitation approach enables limiting the decision maker's burden as preference information is only required to discriminate between alternatives (not to assess the model parameters). Incremental elicitation methods have been proposed for the simple case of linear utilities but have never been studied for Choquet Integrals. This constitutes the first challenging issue considered during my PhD.

Incremental elicitation of Choquet Integrals. Adapting the incremental elicitation approach used for linear functions to the case of Choquet integrals is not straightforward. In the linear case, the selection of new preference queries requires multiple linear programs to be solved, but these problems become significantly more difficult when considering a Choquet integral. More precisely, the Choquet integral's parameters take the form of a capacity, i.e. a monotonic function defined on the power set of criteria which enables the control of the importance attached to all subsets of criteria, and possibly positive or negative synergies between criteria. Thus the number of parameters to assess is exponential in the number of criteria. As a consequence, the nature of the Choquet integral's parameters induces an exponential number of optimization variables and an exponential number of constraints over these variables in the linear programs considered in this elicitation scheme. First, we have proved that, by focusing on a specific type of queries involving binary profiles versus constant profiles, the optimization problems to be solved can be simplified to problems admitting only a linear number of variables and constraints. Then, using the constraint graph associated with these simplified linear programs, we have proposed an iterative procedure to solve these optimization problems in polynomial time (instead of using linear programming); our iterative procedure reduces computation times by around five orders of magnitude. Finally, we tested "the query selection strategy" which consists of selecting the question that is the most informative in the worst-case scenario of answers and we observed that it enables the detection of the preferred option without asking too many questions. This work has been accepted for publication in the last European Conference on Artificial Intelligence and honored to receive the ECAI'14 Best Student Paper award [START_REF] Benabbou | Incremental elicitation of Choquet capacities for multicriteria decision making[END_REF]. The next step was to consider decision situations where the decision space is very large, which is often the case in recommender systems where the possible alternatives can be thousands. Elicitation on combinatorial domains is a challenging issue that recently motivated several contributions in various contexts, e.g. in constraint satisfaction problems [START_REF] Boutilier | Constraint-based Optimization and Utility Elicitation using the Minimax Decision Criterion[END_REF], in Markov Decision Processes [START_REF] Regan | Eliciting additive reward functions for markov decision processes[END_REF][START_REF] Weng | Interactive Value Iteration for Markov Decision Processes with Unknown Rewards[END_REF], in stable matching problems [START_REF] Drummond | Preference elicitation and interview minimization in stable matchings[END_REF] and in multiattribute spaces [START_REF] Gonzales | GAI Networks for Utility Elicitation[END_REF][START_REF] Braziunas | Minimax regret based elicitation of generalized additive utilities[END_REF][START_REF] Koriche | Learning conditional preference networks[END_REF]. We consider decision spaces defined implicitly as the set of possible solutions of a multiobjective combinatorial optimization problem. In standard interactive methods for multicriteria decision support, preference elicitation methods consists in iterating the generation of a feasible instance of the parameters and the computation of the corresponding optimal solution, until the decision maker is satisfied with the latter solution (e.g. [START_REF] Zionts | An interactive programming method for solving the multiple criteria problem[END_REF][START_REF] Vanderpooten | Description and analysis of some representative interactive multicriteria procedures[END_REF]). However, this elicitation approach does not guarantee that the final solution is actually the best alternative for the decision maker since the final instance of the model parameters does not necessarily fit to the decision maker's preferences. We proposed instead to combine search for possibly optimal solutions and elicitation in order to reduce the uncertainty over the model parameters during the resolution so as to more focus the search while determining a necessary optimal solution. A possibly (resp. necessary) optimal solution is an option that is optimal for some (resp. all) parameters compatible with our knowledge about the decision maker's preferences. We need first to propose efficient search procedures for the determination of all possibly optimal solutions given a set of feasible parameters, and then to design elicitation methods reducing the set of feasible parameters during the search while ensuring the determination of a necessary optimal alternative at the end of the resolution. So far, we have considered the two following multiobjective combinatorial optimization problems : multiobjective state space search and multicriteria spanning tree problem. In order to address one difficulty at a time, we have first considered the case of linear utilities and then Choquet Integrals.

Multiobjective State Space Search. Consider a state space graph endowed with q evaluation criteria, i.e. q cost functions to be minimized (e.g. time, distance, energy, risk). Each path is therefore valued by a cost vector and preferences over paths are inherited from the preference over their cost vectors. Preference over cost vectors are defined using a linear aggregation function f ω defining the overall cost (or disutility) f ω (x) attached to any cost vector x, where ω is a vector of preference parameters representing the relative importance of criteria. We want to find a path from an initial node to a goal node that minimizes the overall cost function f ω that represents the DM's preferences, but the vector of weights ω is imprecisely known. Since all preference models considered in multicriteria analysis are compatible with Pareto dominance, preference-based search methods in multiobjective optimization are often based on the exploration of the set of Pareto-optimal solutions. The so-called MOA * algorithm [START_REF] Stewart | White III. Multiobjective A*[END_REF][START_REF] Mandow | A new approach to multiobjective A* search[END_REF] is a multiobjective extension of A * [START_REF] Hart | A formal basis for the heuristic determination of minimum cost paths[END_REF] that determines the set of Pareto non-dominated cost vectors attached to solution paths and returns one path for each element. In the multiobjective case, there possibly exists several optimal paths with different cost vectors to reach a given node. Therefore, the basic graph exploration procedure consists in iteratively expanding subpaths rather than nodes. In order to compute the set of possibly optimal solution paths, we need to define new pruning rules that use sharper conditions than those based on Pareto-dominance tests. In other words, we need to be able to detect subpaths that cannot lead to possibly optimal solution given our knowledge about the decision maker's preferences. To do so, we introduced a dominance relation between sets of cost vectors and given a set of cost vectors, we proved that it enables to detect vectors that cannot be possibly optimal. Then, we proposed a filtering algorithm based on this dominance relation, enabling us to compute the set of possibly optimal cost vectors in a polynomial time. Finally, we proposed two pruning rules based on this filtering algorithm which enable us to discard subpaths that cannot lead to a possibly optimal solution path and we proved that the corresponding graph exploration procedure returns exactly the set of possibly optimal solution paths. Finally, to detect a necessary optimal solution paths, we proposed two incremental elicitation strategies based on the minimax regret criterion so as to reduce the uncertainty during the search. This work has been accepted for publication in the last AAAI Conference on Artificial Intelligence [START_REF] Benabbou | Incremental Weight Elicitation for Multiobjective State Space Search[END_REF]. The next step was to extend our approach to work with a non-linear f ω function such as a Choquet integral so as to obtain better fitting capacities to the decision maker's preferences. However, this extension raises challenging algorithmic questions since the use of a Choquet integral complicates the definition of pruning rules by not satisfying the Bellman principle (i.e. discarding supbaths by comparison with other subpaths is no longer possible). In order to design an efficient algorithm, we proposed to work on near optimal cost vectors using an approximate version of minimax regret. This work has been accepted for publication in the last IJCAI conference [START_REF] Benabbou | Combining preference elicitation and search in multiobjective state-space graphs[END_REF].

Multicriteria spanning tree problem. Consider a connected graph G where each edge is valued by a cost vector corresponding to its evalutation with respect to different criteria. Every criterion is assumed to be additive over the edges; therefore the cost of any subgraph is the sum of the cost of its constituent edges. A spanning tree of G is a connected subgraph of G which contains no cycle while including every node of G. We assume that preferences over cost vectors are defined using a linear aggregation function f ω but the weighting vector ω is imprecisely known. Here again, given a feasible set of weights, we first consider the problem of determining all possibly optimal spanning trees. In the single objective case, the minimum spanning tree problem can be solved in polynomial time using standard greedy algorithms due to Kruskal [START_REF]On the shortest spanning subtree of a graph and the traveling salesman problem[END_REF] and Prim [START_REF] Prim | Shortest connection networks and some generalizations[END_REF]. Unfortunately, as soon as the number of criteria is greater than 2, the problem becomes intractable because the number of Pareto-optimal cost vectors associated to spanning trees is, in the worst case, exponential in the number nodes. In the paper "On Possibly Optimal Tradeoffs in Multicriteria Spanning Tree Problems" that has been accepted for publication in ADT 2015 [START_REF] Benabbou | On possibly optimal tradeoffs in multicriteria spanning tree problems[END_REF], we proposed a multiobjective extension of Prim's algorithm which can compute the exact set of possibly optimal cost vectors associated to spanning trees; this algorithm is a greedy search based on a specific decomposition of the feasible set of parameters. Then, we proposed to interweave incremental elicitation and search to determine a necessary optimal spanning tree. This algorithm consists in selecting, at each iteration step, an edge in the cocycle of the current subgraph that is necessarily (or almost) optimal in the cocycle; if no such edge exists, the procedure asks questions to the decision maker to reduce the set of feasible weights until such edge can be detected. We are now studying the case of non-linear utility functions, which seems to be a challenging issue because our multiobjective greedy search is no longer valid.

Perspectives. As future work, we plan to study combinatorial voting with partial preference profiles. When individual preferences are incomplete, one can indeed study possible and necessary winners (e.g., [START_REF] Konczak | Voting procedures with incomplete preferences[END_REF][START_REF] Xia | Determining possible and necessary winners given partial orders[END_REF][START_REF] Lang | Winner determination in voting trees with incomplete preferences and weighted votes[END_REF][START_REF] Ding | Voting with partial information: what questions to ask[END_REF]). In this setting, incremental elicitation methods are used to progressively reduce the set of possible winners until a winner can be determined with some guarantee [START_REF] Kalech | Practical voting rules with partial information[END_REF][START_REF] Lu | Robust approximation and incremental elicitation in voting protocols[END_REF][START_REF] Dery | Reaching a joint decision with minimal elicitation of voter preferences[END_REF]). As a next step, we can study the potential of incremental elicitation methods in combinatorial voting (i.e. the set of alternatives has a combinatorial structure) with partial preference profiles. We also plan to adapt these approaches for utility elicitation in the context of decision making under risk, not only for expected utility models but also for rank-dependent utility model (elicitation of the probability distortion combined with the elicitation of utilities).


Vincent Sircoulomb

Ghaleb Hoblos

Houcine Chafouk

José Ragot

ANALYSIS AND COMPARISON OF NONLINEAR FILTERING METHODS

Keywords: state estimation, Kalman filters, particle filters, Monte Carlo method, nonlinearity, noise levels

This paper deals with the state estimation of a strongly nonlinear system. In a noisy state space representation setting, Central Difference Kalman Filter, Ensemble Kalman Filter and Particle Filter are tested on a second order system. The choice of estimators parameters is then discussed, and their behaviour in relation to noise is studied, in order to compare estimation quality according to noise's variance criteria.

INTRODUCTION

Filtering has always taken an important place in automatic control. It can be found in application areas as advanced control, navigation, signal processing and diagnosis.

In a state space representation setting, the most popular tool is the Kalman filter [START_REF] Kalman | A new approach to linear filtering and prediction problems[END_REF], also known as linear Gaussian optimal filter. But, in reality, most of systems do not respect these hypotheses. Many researchers have attempted to consider non Gaussian cases, with the Gaussian Sum Filter [START_REF] Aspach | Nonlinear bayesian estimation using Gaussian sum approximation[END_REF], and the nonlinear case, leading to the Extended Kalman Filter (EKF). But this state estimator has some well known drawbacks, such as needing to calculate the Jacobians of nonlinear functions, which is not easy, but above all, may cause divergence in some cases [START_REF] Anderson | Optimal filtering[END_REF]. Re-cent work partially solved these problems, see for example the Unscented Kalman Filter (UKF) [START_REF] Julier | A new extension of Kalman filter to nonlinear systems[END_REF], the Central Difference Kalman Filter (CDKF) [START_REF] Nφrgaard | New developments in state estimation for nonlinear systems[END_REF] and the Ensemble Kalman Filter (EnKF) [START_REF] Burgers | Analysis scheme in the Ensemble Kalman Filter[END_REF]. These versions lead to significant results, but are based on empirical developments.

A more general setting is provided by Monte Carlo filters, also called Particle Filters (PF) [START_REF] Arulampalam | A tutorial on particle filters for online nonlinear/non-Gaussian Bayesian tracking[END_REF] [START_REF] Doucet | On sequential simulationbased methods for Bayesian filtering[END_REF]. This kind of tool is more powerful, but also more timeconsuming and difficult to synthesize.

In this paper, a problem statement is first presented in section 2, and then, different methods of nonlinear filtering are exposed in section 3. The choice of the estimators parameters is discussed in section 4, and the behaviour of these tools in relation to noises is then studied in the next section. A comparison on a nonlinear second order system is provided in section 6.

PROBLEM STATEMENT

In a discrete state space setting, the problem of filtering is presented as shown in figure 1. It consists of attemting to make the estimated state xk the closest possible to the real value x k . To reach this purpose, the only knowledges we have are :

• the values of input vector u k and output vector y k , • the process model, represented by (1), where f and g are nonlinear vector fields, • some statistics of the process noise w k and the measurements noise v k .

x k = f (x k-1 , u k-1 , w k-1 , k -1) y k = g(x k , u k , k) + v k (1)

Fig. 1. Filtering problematic

In a stochastic setting, x k ∈ R nx , y k ∈ R ny , v k ∈ R nv and w k ∈ R nw are considered as random vectors, and u k ∈ R nu as a deterministic input [START_REF] Anderson | Optimal filtering[END_REF].

NONLINEAR FILTERING METHODS

The optimal filter is described by the probability density p(x k |y 0→k ), which can be recursively calculated by the optimal Bayesian filtering equation (2).

p(x k |y 0→k-1 ) = R nx p(x k |x k-1 ).p(x k-1 |y 0→k-1 ).dx k-1 p(x k |y 0→k ) = p(y k |x k ).p(x k |y 0→k-1 ) R nx p(y k |x k ).p(x k |y 0→k-1 ).dx k (2)
Then, the state can be calculated via the two optimality criterion :

• least square : xk = E(x k |y 0→k ) = R nx x k .p(x k |y 0→k ).dx k • maximum likelihood : xk = arg x k max x k ∈R nx [p(x k |y 0→k )]
Unfortunately, the equations (2) cannot analytically be solved, excepted in the Gaussian linear1 case : it leads to the Kalman filter. In the other case, these equations can be computed by Monte Carlo simulation, i.e. the realisation of a particle filter.

The principal nonlinear Kalman filters are the EKF, UKF, CDKF and EnKF. The estimators tested in this article are the last two. Their algorithms are given below:

1) Initialization with P xx 0|0 and x0|0 and :

• n a = nx + nw • σx = 2.nx + 1 • σ a = 2.n a + 1 • W (i) ma = (h 2 -na)/(h 2 ) if i = 1 1/(2.h 2 ) if 2 ≤ i ≤ na + 1 • W (i) mx = (h 2 -nx)/(h 2 ) if i = 1 1/(2.h 2 ) = if 2 ≤ i ≤ na + 1 • W c1 = 1/(4.h 2 ) • W c2 = (h 2 -1)/(4.h 2 ) 2) Prediction step : • Xk-1 = Xk-1|k-1 = xT k-1|k-1 0 T • P aa k-1 = P xx k-1|k-1 0 0 P ww • S aa k-1 = P aa k-1 • X (i) k-1 = Xk-1 if i = 1 Xk-1 + h.S aa k-1 (i -1) if 2 ≤ i ≤ na + 1 Xk-1 -h.S aa k-1 (i -na -1) if na + 2 ≤ i ≤ σa • x (i) k-1 T w (i) k-1 T T = X (i) k-1 i = 1, . . . , σa • x (i) k|k-1 = f x (i) k-1 , u k-1 , w (i) k-1 , k -1 i = 1, . . . , σa • xk|k-1 = σ a i=1 W (i) ma .x (i) k|k-1 • P xx k|k-1 = na+1 i=2 W c1 x (i) k|k-1 -x (i+na) k|k-1 2 + W c2 x (i) k|k-1 + x (i+na) k|k-1 -2x (1) k|k-1 2
3) Correction step :

• S xx k|k-1 = P x k|k-1 • x(i) k|k-1 = xk|k-1 if i = 1 xk|k-1 + h.S xx k|k-1 (i -1) if 2 ≤ i ≤ nx + 1 xk|k-1 -h.S xx k|k-1 (i -nx -1) if nx + 2 ≤ i ≤ σx • y (i) k|k-1 = g x(i) k|k-1 , u k , k i = 1, . . . , σx • ŷk|k-1 = σ x i=1 W (i) mx .y (i) k|k-1 • P yy k|k-1 = nx+1 i=2 W c1 y (i) k|k-1 -y (i+nx) k|k-1 2 + W c2 y (i) k|k-1 + y (i+nx) k|k-1 -2y (1) k|k-1 2 • P xy k|k-1 = √ W c1 S xx k|k-1 y (1) k|k-1 . . . y (nx) k|k-1 T • K k = P xy k|k-1 P yy k|k-1 -1 • xk|k = xk|k-1 + K k y k -ŷk|k-1 • P xx k|k = P xx k|k-1 -K k .P yy k|k-1 .K T k
CDKF algorithm, in the case of additive measurement noise [START_REF] Vandermerwe | Sigma-Point Kalman Filters for probabilistic inference in dynamic state-space models[END_REF] The nomenclatures is such that :

• in a general way :

P ab = E (a -E(a))(b -E(b))
T , where T denotes the transposition operator, • the augmented state X includes the process noise : X = x T w T T , • as covariance matrices are positive and symmetric, the matrices S can be computed via the Cholesky decomposition,

• M(i) denotes the i th column of M, • M 2 = MM T and M 2 P = MPM T , • in a general way : x ∼ ℵ(m, P) means that
x is normally distributed, with mean m and covariance P.

1) Initialisation with P xx 0|0 and x0|0 . 2) Prediction step :

•

x (i) k-1 ∼ ℵ(x k-1|k-1 , P xx k-1|k-1 ) i = 1, . . . , N • w (i) k-1 ∼ ℵ(0, P ww ) i = 1, . . . , N • x (i) k|k-1 = f x (i) k-1 , u k-1 , w (i) k-1 , k -1 i = 1, . . . , N • xk|k-1 = 1 N N i=1 x (i) k|k-1 • x (i) k|k-1 = x (i) k|k-1 -xk|k-1 i = 1, . . . , N • P xx k|k-1 = 1 N N i=1 x (i) k|k-1 x (i) k|k-1 T 3) Correction step : • y (i) k|k-1 = g x (i) k|k-1 , u k , k • ŷk|k-1 = 1 N N i=1 y (i) k|k-1 • y (i) k|k-1 = y (i) k|k-1 -ŷk|k-1 • P yy k|k-1 = 1 N N i=1 y (i) k|k-1 y (i) k|k-1 T • P xy k|k-1 = 1 N N i=1 x (i) k|k-1 y (i) k|k-1 T • K k = P xy k|k-1 P yy k|k-1 -1 • xk|k = xk|k-1 + K k y k -ŷk|k-1 • P xx k|k = P xx k|k-1 -K k .P yy k|k-1 .K T k
EnKF algorithm [START_REF] Burgers | Analysis scheme in the Ensemble Kalman Filter[END_REF] Concerning the particle filters, we restrict our choice to the simplest, which is also the most popular, i.e. using the transition kernel for importance density. The resulting algorithm is presented below :

1) Initialisation with P xx 0|0 and x 0 :

• x (i) 0 ∼ ℵ x 0 , P xx 0|0 i = 1, . . . , N • W (i) k = 1 N i = 1, . . . , N 2) Prediction step : • w (i) k-1 ∼ ℵ (0, P ww ) i = 1, . . . , N • x (i) k = f x (i) k-1 , u k-1 , w (i) k-1 , k -1 3) Correction step : • y (i) k = y k -g x (i) k , u k , k • K (i) k = 1 √ (2π) ny . det(P vv ) exp -1 2 y (i) k 2 (P vv ) -1 • W (i) k = W (i) k-1 .K (i) k i = 1, . . . , N • W (i) k = W (i) k N j=1 W (j) k i = 1, . . . , N 4) Resampling step (optional) 5) State estimation :
• In the case of maximum likelihood :

xk = x (i) k such that W (i) k ≥ W (j) k ∀j ∈ {1, . . . , N }, j = i • In the case of least squares : xk = N i=1 W (i) k .x (i) k
PF's algorithm, in case of Gaussian noises and importance density equal to transition kernel [START_REF] Doucet | On sequential simulationbased methods for Bayesian filtering[END_REF]

TUNING OF THE FILTERS PARAMETERS

Description of the system tested

The system we choose to study is commonly used in the particle filtering community [START_REF] Gordon | Novel approach to nonlinear/non-Gaussian Bayesian state estimation[END_REF], [START_REF] Arulampalam | A tutorial on particle filters for online nonlinear/non-Gaussian Bayesian tracking[END_REF]. In order to complicate this further, we added a second non linear state equation, giving the system (3), in a general way as : a = [a (1) . . . a (n) ] T .

x

(1) k = 1 2 .x (1)
k-1 +

25.x

(1) k-1

1 + x (1) k-1 2 + 8 cos(1.2k) + w (1) k-1 x (2) k = 8 sin x (1)
k-1 + 8 sin 1.2x

(2)

k-1 + w (2) k-1 y (1) k = x (1) k 2 20 + v (1) k y (2) k = x (2) k + v (2) k (3)
where v k and w k are zero mean noises, normally distributed with covariances R vv and R ww .

The Euclidian norm of the difference between the true measurements and that predicted by the filter ((4), where L denotes the simulation length) will be termed the filter variance.

variance(k) = y k -g(x k , u k , k) 2 variance = 1 L Σ L k=1 variance(k) (4)

Central Difference Kalman Filters parameter

The CDKF present one parameter (excepted the covariance matrices P vv and P ww ), which is h.

This parameter is said to be optimally set to h = √ 3 in the Gaussian case [START_REF] Nφrgaard | New developments in state estimation for nonlinear systems[END_REF]. This value has been checked successfully.

Particle Filters parameters

The parameters of particle filters are the following:

• the number of particles,

• the choice of the state estimator,

• the resampling scheme2 ,

• the resampling indicator.

The state estimator is simple to choose : after a number of running, it is clear that in this case, the estimator using least square gives better results than that based on maximum likelihood.

Concerning the resampling, the different schemes are :

• the multinomial resampling,

• the residual resampling [START_REF] Liu | Blind deconvolution via sequential imputation[END_REF]), • the systematic resampling [START_REF] Kitagawa | Monte Carlo filter and smoother for non-Gaussian nonlinear state space model[END_REF],

• the branching algorithm [START_REF] Crisan | Large deviation comparison of branching algorithms versus resampling algorithms : Application to discrete time stochastic filtering[END_REF].

Experimentally, they all provide similar results [START_REF] Douc | Comparison of resampling schemes for Particle Filtering[END_REF]. The most natural choice is then to choose the simplest algorithm, which is the systematic resampling. In addition, it is the one whose variance is minimal.

Resampling contribution is real, but it is not advised to use it at each step, because it impoverishes the particles cloud. There are two indicators for deciding when redistribution is necessary : the first calculates the effective number of particles [START_REF] Kong | Sequential imputation method and Bayesian missing data problems[END_REF] and the second the entropy of the particles system [START_REF] Pham | Stochastic methods for sequential data assimilation in strongly nonliear systems[END_REF]. The tests done on a filter with N = 1000 particles and different values of threshold give the results presented in tables 1 and 2. The results provided by these methods are close : we arbitrarily choose the entropy based estimator. The threshold value is a compromise between the filter's variance and the resampling ; ln(N/50) has been retained.

The last thing to choose is the number of particles. The method adopted is to run the simulation with different numbers of particles, and to choose the best compromise between computation time and number of particles. By seeing table 3, the number of particles adopted is 1000.

Number of particles of the EnKF

A similar method, as used with the PF, is adopted, providing the table 4. Contrary to PF, the EnKF's variance is quite independent on the number of particles. It can be explained by the fact that PF has a central theorem validating it, contrary to the EnKF. A too poor number of particles (in practice, 350), leads to non positive covariance matrix. The best choice is then to choose a number of 500 particles, in order to keep a security margin.

FILTERS BEHAVIOUR IN RELATION TO NOISE

Consider the following covariance levels :

R ww = I R vv = aI (5)
where a ∈ R * and I denotes the identity matrix of appropriate size. The noises covariances are assumed to be known. Consequently, the filters covariance can be set to these values, i.e. : P ww = R ww , P vv = R vv .

The mean variance of each filter in relation to a is given in table 5, and traces of the real and estimated states are exposed on figure 2 and3, for a = 10. With low covariance noise, the Monte Carlo sampling based filters (i.e. the EnKF and the PF) outperform clearly the CDKF. However, they cannot be used with a noise covariance smaller than the unity, because particles are not dispatched enough in the state space, leading to filter divergence [START_REF] Legland | An analysis of regularized interacting particle methods for nonlinear filtering[END_REF]. In addition, in the case of high noise, their performance is severely decreased, providing the same results as the CDKF. As it was exposed in the preceding section, the EnKF and the PF produce better results than the CDKF in the case of small covariance noise, but do not perform better when a becomes higher than a certain value (in practice, a ≈ 1000)(figures 4 and 5). But, contrary to the CDKF, these two filters have parameters allowing a better tuning. They are :

• the number of particles,

• the threshold of resampling indicator (for PFs).

The purpose of this section is to study the influence of these values on the estimation quality.

Number of particles of the EnKF

As we can explain, the effect of the number of particles of the EnKF does not affect the variance of the filter (it already was seen in section 4), as illustrated in table 6.

Parameters of the PF

With a high covariance measurement noise, the most remarkable fact is that PF does not proceed to resampling. Consequently, it is natural to reduce the threshold of the resampling indicator. reducing it produces an analogue result with less computation time.

CONCLUSION

On the system tested, the best results are provided by the PF and the EnKF for a measurement covariance noise included between 1I and 1000I.

Below this interval, the CDKF is the only one which can be used. Above this interval, the performance of the three estimators are equivalent, whatever their tuning : if the computation time consumption is taken into account, the CDKF would be the more efficient.

So, for such a system, when the measurement noise has a low or high covariance, it is advised to use the CDKF. In the other case, the EnKF is proving to be the best choice, because it provides the same results as the PF with half of particles, and furthermore, it is simpler to parameterize.

As an outlook of this work, on the one hand, is to compare with nonlinear robust H ∞ filtering. On the other hand, it is to study the behaviour of these estimators with respect to several sensor subsets, in order to develop a tool for the diagnosis of a strongly nonlinear system.

Fig. 2 .

 2 Fig. 2. Real and estimated state : 1 st component

Fig. 4 .

 4 Fig. 4. Filters variance for P vv = 10I

Table 1 .

 1 Entropy based indicator :

	Threshold	ln N 10	ln N 30	ln N 50	ln N 100	ln N 150
	Filter's variance	1.46	1.63	1.69	2.01	2.33
	MNR*	0.69	0.56	0.50	0.50	0.46
	Table 2. Effective particles number
		based indicator :
	Threshold	N 10	N 30	N 50	N 75	N 100
	Filter's variance 1.51 1.69 1.75 1.60 1.66
	MNR*	0.7	0.6	0.56	0.5	0.49

*MNR = Mean Number of Resampling, i.e. the number of resampling during the simulation divided by the running length.

Table 3 .

 3 PF's variance (PFV) in function of the number of particles (N ):

	N	50	100	500	1000	2000 5000 10000
	PFV 9.77 4.21 2.15	1.82	1.63	1.11	1.04

Table 4 .

 4 EnKF's variance (EnKFV) in function of the number of particles (N ):

	N	350	500	750	1000 2000
	EnKFV 1.55 1.52	1.52	1.59	1.56

Table 5 .

 5 Filters variance as a function of measurement noise covariance :

	a	1	10	50	100	500	1000
	CDKF 9.72 10.55	13.40 16.12	29.24 39.86
	EnKF	1.59	3.21	7.74	11.39	26.90 37.96
	PF	1.48	3.18	7.65	11.48	26.78 37.86

Table 6 .

 6

	N	350	500	750	1000	2000
	EnKFV 38.83 38.22 38.22 38.11 38.63

EnKF's variance (EnKFV) in function of the number of particles (N ):

Table 7 .

 7 PF's variance (PFV) and Mean Number of Resampling (MNR) in function of the threshold of the resampling indicator :Concerning the number of particles, different values have been tested, as exposed in table 8.Growing the number of particles does not improve the effectiveness of the PF. On the contrary, Table 8. PF's variance (PFV) in function of the number of particles (N ) :

	threshold	ln N 50	ln N 10	ln N 3	ln N 1.5	ln N 1.1
	MNR	0	0.02	0.03	0.08	0.27
	PFV	37.86 36.72 39.12	37.98	39.4
	In table 7, it can be seen that reducing the value
	of the threshold makes the resampling step more
	active, but it does not affect the PF's variance.
	It can be explained by the fact that the purpose
	of this step is to avoid the divergence problem,
	especially in the case of model uncertainty, which
	is not what we considered. The reason that the
	chosen value for this threshold is important with
	a low covariance noise (section 4, with a unity
	covariance) is that in this case, the Gaussian
	distribution is quite fit, making too few particles
	being likely at the correction step.

It can also been solved in nonlinear case, when p(x k |y 0→k ) is Gaussian or close to be Gaussian, and f and g keep this Gaussian character : it is the basis of the nonlinear extensions of Kalman filtering. See[START_REF] Julier | A general method for approximating nonlinear transformations of probability distributions[END_REF] for further details.

Resampling has been introduced by Gordon[START_REF] Gordon | Novel approach to nonlinear/non-Gaussian Bayesian state estimation[END_REF] for avoiding the divergence problems.