Sébastien Le Beux
email: sebastien.le-beux@ec-lyon.fr

Hui Li

Gabriela Nicolescu

Ian O'connor

A Reconfigurable Optical Network on Chip for Streaming Applications

Keywords:

Optical on-chip interconnects enable significantly increased bandwidth and decreased latency in MPSoC. They are characterized by high static energy and low dynamic energy consumption. Achieving high energy-efficient communication thus requires a certain adaptability degree to the executed application and its communication traffic in order to reduce the static energy. In this paper, we introduce a mapping method for CHAMELEON, an optical interconnect allowing configuring dedicated communication channels according to an application and its corresponding communication traffic.

INTRODUCTION

Optical Network-on-Chip (ONoC) is an emerging technology that is considered as one of the key solutions for the future generation of on-chip interconnects. It relies on optical waveguides to carry optical signals, so as to replace electrical interconnect and provide the low latency and high bandwidth properties of the optical interconnect. However, the design of an ONoC is a costly investment since it relies on the integration of heterogeneous technologies. Such investment thus requires a certain degree of reconfigurability of the design in order to ensure the ONoC can be adapted to various communication traffic scenarios, i.e. to be integrated in various hardware platforms. This reconfigurability degree should come with acceptable execution performances and power consumption overhead to keep benefits of the technology.

The approaches relying on MWSR (Multiple Writers Single Reader) such as Corona [START_REF] Vantrease | Corona: System Implications of Emerging Nanophotonic Technology[END_REF] implies that IP cores request an access to the optical interconnect. However, this requires an arbitration to avoid writing conflict, which can lead to extra latency, i.e. lower performances. Other approaches rely on SWMR (Single Writer Multiple Readers) such as ATAC [START_REF] Psota | ATAC: Improving Performance and Programmability With on-Chip Optical Networks[END_REF], which implement a permanent broadcast among IP cores. While this avoids the use of arbitration, it is an energyinefficient solution since all the data from an IP core needs to be transmitted to all the others. SWSR approaches (Single Writer Single Reader) aim at creating dedicated point-to-point communication channels between IP cores [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF]. This approach is power efficient with low latency, due to the fact that the communications between IP cores are not influenced by each other (i.e. optical crossbar implementation). The main disadvantage of the SWSR approach is the lack of scalability. This scalability issue can be partially leveraged by using reduction method [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF], but it comes at the price of limited connectivity which in turn impacts the reusability feature. Table 1 summarizes the main characteristics of MWSR, SWMR and SWSR approaches. In our previous works, we introduced CHAMELEON [2], a reconfigurable channel efficient optical network on chip. CHAMELEON extends the SWSR approach with a reconfigurability feature allowing opening and closing dedicated channels between IP cores. Hence, the bandwidth is shared according to the communication requirements, thus leading to a highly reusable network. The reconfiguration of CHAMELEON can be achieved at run-time, i.e. through a communication protocol, or specified at compile time, i.e. using static mapping method. The configurations generated by the later method lead to networks characterized by a low latency (no arbitration is required), highly energy-efficient (dedicated channels are used). In this paper we present a configuration of CHAMELEON implementing communications specific to the mapping of a streaming application.

II. CHAMELEON ARCHITECTURE

A. Architecture Overview

Figure 1 illustrates the considered 3D architecture. It is composed of an electrical layer implementing 4x4 IP cores and an optical layer implementing CHAMELEON. It is composed of ONIs (Optical Network Interface) crossed by waveguides propagating optical signals. The ONIs are composed of on-chip laser sources, Microring-Resonators (MR) and photodetectors. MRs and lasers are reconfigurable and allow opening dedicated communication channels between ONIs (i.e. connections that do not suffer from arbitration latency, similarly to SWSR architectures). In addition to point-to-point communication channels, it is possible to configure multicast, broadcast and high-bandwidth channels. If multiple waveguides propagate optical signals in both clockwise and counter-clockwise directions, bidirectional channels can be configured. Since CHAMELEON allows combining different channels within a single configuration at the same time, a high flexibility/reusability degree is reached.

B. Application Mapping

Reconfiguring CHAMELEON leads to setup of a given connectivity between IP cores that can well suit the targeted application to be executed (e.g. steaming) or the architectures communication requirements (e.g. processor to memory). The more wavelengths and waveguides there are, the higher the bandwidth is, i.e. the performance improvement wrt electrical interconnect. However, this comes at the cost of resource overhead and eventually performance penalty, meaning that design tradeoffs need to be explored. This exploration is driven by application cases, which is introduced in the following example mapping of a streaming application onto the targeted architecture. In the example, we consider 8 IP cores connected through 8 ONIs (A, B…H) with a single waveguide. We also assume that 6 wavelengths are available (λ 0 , λ 1 … λ 5 ).

Figure 2 a) represents a MP3 audio decoder application inspired from [START_REF] Schmitz | System-Level Design Techniques for Energy-Efficient Embedded Systems[END_REF]. This simple application is chosen only to illustrate the approach; it is obvious that optic will be justified only for applications requiring huge data transfer. The application is represented as a Directed Acyclic Graph G = (T, E), where T is a set of tasks (i.e. t i ) and E a set of data (i.e. e ij to be transferred from task i to task j). The right-hand side of Figure 2 a) represents the 8 ONIs crossed by the waveguide propagating optical signals. The arrows represent the mapping of the 17 tasks onto the IP cores connected to the ONIs, considering the constraint that source and sink are mapped on a same IP core. Such mapping solution can be obtained from methods similar to [START_REF] Chou | Contention-aware Application Mapping for Networkon-Chip Communication Architectures[END_REF] and adapted to silicon photonic interconnect properties. Figure 2 b) represents the configured communication channels using a representation highlighting the use of the 6 wavelengths. Wavelengths are allocated according to the inter-ONI communications implied by the mapping (the intra-ONI communications such as t 1 t 3 are realized locally by the corresponding IP core). For instance, the data dependencies t 0 t 1 and t 0 t 2 in the application lead to the configuration of channels between A and B (with λ 0 , λ 1 and λ 2 ), and between A and C (with λ 3 , λ 4 and λ 5 ) respectively (i.e. a multicast is realized). In this example, 3 wavelengths are allocated to each channel, i.e. the bandwidth is equitably shared. Depending on the data dependencies between the tasks (as specified in the application model), the wavelengths can be shared differently. For instance, between G and H, 5 wavelengths and 1 wavelength are allocated to the channel implementing t 11 t 13 and t 14 t 16 separately. The resulting configuration leads to a contention-free execution of the application. Figure 2 c) represents the configuration of MRs and lasers in ONI B and G and Figure 2 d) gives the resulting connectivity/bandwidth matrix.

III. CONCLUSION

In this paper, we have presented a configuration of CHAMELEON defined according to the mapping of a streaming application. By avoiding contention and offering a high adaptability to the applications, we believe that CHAMELEON has the potential to be embedded in multiple platforms and reconfigured according to the user requirements.

Figure 1 :Figure 2 :

 12 Figure 1: CHAMELEON is implemented on the optical layer, it interconnects IP cores located on the electrical layer

Table 1 : Pros and Cons of ONoC communication schemes

 1

	Approach	Latency	Power efficiency	Reusability
	MWSR	x	xx	xxx
	SWMR	xxx	x	xxx
	SWSR	xxx	xxx	x
	CHAMELEON (reconfigurable SWSR)	xxx	xxx	xxx


Yuliia Romenska

Florence Maraninchi

Efficient Monitoring of Loose-Ordering Properties for SystemC/TLM

SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of loose-ordering to specify when components interact with each other and we propose a set of patterns to capture this notion in assertions.

This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL.

Introduction

SystemC-based Transaction-level modeling (TLM) [9] has been very successful in providing high-level executable component-based models for systems-on-chip (SoCs). The rationale has been to raise the level of abstraction by removing details of lower models like RTL models, especially on timing aspects. The notion of loose-timing is very interesting in that perspective. Exact delays in SystemC models (e.g., wait(100, SC_NS);) have been identified as a source of over-constraints and spurious synchronizations in models. The Loose-timing principle allows to write wait (90, 110, SC_NS), to specify a non-deterministic delay.

Introducing Loose-Ordering In this paper, we identify another source of over-constraints. Typically, when a component needs several input data (e.g., the address of an image, the size of it, etc.) before one of the functions it provides (e.g., some transformation of the image) can be started, the order in which the input data elements are provided is usually irrelevant. The same is true for data and control outputs. Any specification in which the order is imposed is over-constrained.

This type of property can already be expressed in languages like the Property Specification Language (PSL) [START_REF] Cohen | Using PSL/Sugar for formal and dynamic verification: Guide to Property Specification Language for Assertion-based Verification[END_REF][START_REF] Maraninchi | IEEE Standard for Property Specification Language (PSL)[END_REF] (in the whole paper, PSL stands for PSL 1.1). But even simple loose-ordering properties require complex formulas, hence dedicated constructs are helpful.

Efficient Monitoring for Loose-ordering properties The first idea is to translate automatically our new properties into PSL, for which there exists monitor generation techniques. However, we will show that this produces complex formulas. Then, even the efficient techniques for exploiting such logics (e.g., the automatic modular generation of monitors described in [START_REF] Morin-Allory | On-line monitoring of properties built on regular expressions sequences[END_REF][START_REF] Pierre | A tractable and fast method for monitoring SystemC TL specifications[END_REF]) cannot do better than producing complex monitors from the obtained complex formulas.

The contributions are (i) a new notion called loose-ordering, allowing to remove the sources of over-constraints due to the order of interactions between components in a TL model; (ii) a set of patterns to capture these properties; (iii) a translation into PSL, for comparison purposes; (iv) a direct translation into efficient SystemC monitors.

Background and Related Work: Testing and Monitoring Hardware Designs

Figure 1 illustrates the general method for testing a design-under-verification (DUV), as presented in the Universal Verification Methodology (UVM) [START_REF]Universal verification methodology[END_REF], SystemC/SCV [START_REF]Open SystemC Initiative[END_REF], eRM [START_REF] Iman | The e hardware verification language[END_REF][START_REF]Verisity Design e Reuse Methodology Developer Manual[END_REF], SVM [START_REF] Oliveira | The system verification methodology for advanced tlm verification[END_REF], etc. A stimuli generator is in charge of producing inputs for the DUV; an assertion checker is in charge of deciding whether the test passes. An additional element of the method is a tool capable of evaluating the coverage of the design obtained with a set of stimuli. Assertions can be expressed with languages providing temporal logic constructs, i.e., ways of expressing what happens on a (finite or infinite) sequence of states. For instance PSL is built on the Linear Temporal Logic (LTL). The general method can be applied at various levels of abstraction. At the RT level, specifications are synchronous, and all the properties of the DUV can be expressed by specifying what happens on a unique discrete time scale.For TL models, the semantics of specification languages has to be adapted [START_REF] Pierre | A tractable and fast method for monitoring SystemC TL specifications[END_REF]. The idea is to recover the notion of a unique discrete scale on which to interpret the temporal logic constructs, by using the sequence of events instead of a unique clock.

In this paper, we focus on TL models. We follow the ideas of [START_REF] Pierre | A tractable and fast method for monitoring SystemC TL specifications[END_REF] for generating efficient monitors from our patterns, in a modular way. We compare with PSL, often used in assertion-based verification. Logics like the duration calculus or its discrete version [START_REF] Hansen | Duration calculus: Logical foundations[END_REF], which offer a "chop" operator to express sequences, could be more appropriate for the expression of our patterns, but they are not usual in the domain.

The Case-Study

Our case-study is an access-control device based on face recognition analysis. A virtual prototype of the system has been implemented using standardized SystemC/TLM (see Fig. 2). We focus on the Image Processing Unit (IPU), which performs face recognition. It contains read/write registers to configure the component; after termination of recognition, the IPU sends an interrupt through its channel irq. Its input/output interface is defined as follows: an input of the IPU is any action of the other components that affects the IPU (e.g. set_X standing for 'write' operation on the register X, start launching recognition); output is any activity performed by the IPU that affects other components (e.g. read_img standing for 'read image', set_irq for the interrupt signal). The specification of interactions is: (i) the input start must be preceded by at least one occurrence of each of the inputs set_X for all registers X, but the order does not matter (see Example 2 below); (ii) after face recognition has been requested (input start), the IPU reads images

GPIO

Grammar Rule Constraints a range α(R) = {n} ⊆ I ∪ O R = n [u,v] u, v ∈ N a fragment i = j =⇒ α(Ri) ∩ α(Rj) = ∅ F = ({R1, . . . , Rn}, ) ∈ {∧, ∨} a loose-ordering i = j =⇒ α(Fi) ∩ α(Fj) = ∅ L = F1 < • • • < Fq P = L α(P) ⊆ I ∪ O Q = L α(Q) ⊆ O an antecedent requirement α(P) ∩ {i} = ∅ A = (P << i, b) i ∈ I, b ∈ B a timed implication constraint t ∈ N T = (P ⇒ Q, t)
Figure 3: Abstract grammar and constraints for well-formed formulas from the gallery (i.e., repeats the output read_img several times in a row) and then sends an interrupt (i.e., produces the output set_irq, see Example 3).

Specification Patterns for Loose-Orderings

We generalize the case-study properties with two patterns for: antecedent requirements and timed implication constraints. Both patterns are written on the vocabulary of the input/output interface (I, O) of the component. The syntax is given by the abstract grammar shown in Fig. 3. The right column of the table is the set of additional constraints defining well-formed formulas of this grammar. They are expressed using α, which denotes the set of interface names (inputs or outputs) that appear in the formula. The constraints mainly state that we should not reuse the same interface names in two ranges, or fragments, of the same property. All well-formed formulas are interpreted on sequences where only the names of the root pattern appear; only one name at a time can occur due to asynchrony of considered models. The notion of time used in the timed implication constraint will be mapped directly to the simulation time of the SystemC simulation kernel.

Definition 1: Range -A range R = n [u,v] denotes any sequence of k occurrences of n, n ∈ I ∪ O and k ∈ [u, v]. Definition 2: Fragment -A fragment F = ({R 1 , . . . , R n }, ), ∈ {∧,
∨} is made of sequences s 1 , ...s n matching the corresponding ranges. If = ∧ then all these s i s should appear, concatenated in any order; if = ∨, at least one of these s i s should appear, and possibly several of them, concatenated in any order.

Definition 3: Loose-Ordering -A loose-ordering L = F 1 < • • • < F q
is made of sequences s 1 , ...s n matching the corresponding fragments. All the s i s should appear, concatenated in this exact order. Notice we call it loose-ordering because the order in fragments is free.

Example 1: Loose-Ordering -Consider the loose-ordering = n [2,8] 1 < ({n 2 , n 3 }, ∨).
It defines sequences such that: first we have several n 1 in a row (the number of occurrences of n 1 is in [START_REF]Spot's online ltl-to-tgba translator spot[END_REF][START_REF] Hansen | Duration calculus: Logical foundations[END_REF]); then we have either n 2 or n 3 , or both in any order. Definition 4: Antecedent requirement -An antecedent requirement A = (P << i, b), b ∈ B, means that i can occur only if P has been observed before. When b is true the condition has to be repeated: each occurrence of i should be preceded by its "own" occurrence of P, i.e. an occurrence that happened since the last i. When b is false one occurrence of P is enough to validate all the further occurrences of i.

Example 2: Non-repeated requirement with a conjunction -Before starting face recognition the environment of the IPU has to provide values of the image to be analyzed, the address of the image gallery, and the size of the gallery: (({set_imgAddr, set_glAddr, set_glSize}, ∧) << start, false).

Definition 5: Timed implication constraint -A timed implication constraint T = (P ⇒ Q, t) means that, whenever P has been observed, Q should occur, and should have finished before t time units have elapsed since the end of P. This pattern is implicitly of the "repeated" kind: when P has been observed, Q should occur, and if a new occurrence of P is observed, a new occurrence of Q should occur.

Example 3: Timed implication constraint -If the recognition starts, the IPU reads images from the gallery (i.e., produces several times the output read_img) and sends an interrupt (the output set_irq). All outputs must be produced during some time interval T, which models the duration taken by the face recognition: (start ⇒ read_img [100,60000] < set_irq, T )

Translation into PSL

The translation has been validated with the SPOT tool [START_REF]Spot's online ltl-to-tgba translator spot[END_REF] which translates LTL or PSL formulas into Büchi automata.

Dealing with Ranges Temporal logics lack counting facilities. One way to encode ranges is to use a big disjunction of nested next operators encoding all sequences defined by ranges. This encoding is explosive. The alternative approach to encode a range (e.g. n [1,2] ) is to treat sequences of consecutive occurrences of a range's name (e.g. n and nn) as new elements (e.g. n 1 and n 2 ). The new vocabulary of n [1,2] is α = {n 1 , n 2 } (instead of α = {n}). Implementation of this approach includes a lexical analyzer to define new elements.

Encoding of Antecedent Requirements

The encoding of A = (P << i, true) is a big conjunction of the expressions: Asynchalways( not(n x ∧ n y )) for all n x , n y ∈ α(A); MaxOne -before the occurrence of i each name of P can occur at most once, always(n x → next(not n x until! i)) for all n x ∈ α(P); Range -before the occurrence of i at most one name per range R k of the loose-ordering P can occur, always(n x k → (not n y k until! i)) for all n x k , n y k ∈ α(R k ), for all ranges R k s; Order -if any of the names of the fragment F k occurs, all names of the preceding fragment F k-1 have lost their turn, always(n x → (not(m y ) until! i)) for all n x ∈ α(F k ), for all m y ∈ α(F k-1 ); BeforeI -the name i can occur only after P has been observed, (not(i) until! n x ) for all n ∈ α(P); AfterI -the loose-ordering P should be observed before each occurrence of the name i (i.e., i plays the role of a reset point),

always(i → next( (not(i) until! n x k )))
where stands for all n x k ∈ α(R k ), for all the ranges R k s of P and for all fragments Fs of P with = ∨.

Encoding of Timed Implication Constraints

We can translate G = (P ⇒ Q, t) into PSL applying the encoding proposed above. To do that we need to (i) "concatenate" P and

Q giving F p 1 < • • • < F p k < F q 1 < • • • < F q , (
ii) consider the end of Q (i.e., the fragment F q ) as the reset point.

Modular Monitors in SystemC

All the monitors are expressed as synchronous parallel compositions of elementary recognizers for ranges (Fig. 5). The proposed constructions have been programmed in Lustre [START_REF] Caspi | Lustre, a Declarative Language for Programming Synchronous Systems[END_REF]; it allows to check their correctness with respect to the intuitive semantics given in section 4 using automatic testing tools.

The Recognition Context A recognizer for a range works in a recognition context, depending on where the range appears in the syntax tree of A or G. Consider for example the property of Figure 4. While recognizing n [START_REF]Spot's online ltl-to-tgba translator spot[END_REF][START_REF] Hansen | Duration calculus: Logical foundations[END_REF] 3 : (i) n 1 and n 2 are forbidden, since they are supposed to have happened before, the set of such names is denoted as B; (ii) n 4 is forbidden unless n 3 has occurred at least twice (notice that n 4 can occur both before and after the range n , because it belongs to the same parent fragment F 2 ), this set of names is denoted as C; (iii) n 5 is forbidden until n 3 has been observed at least twice, in which case it stops the recognition of the range n (and starts the recognition of the appropriate range), the appropriate set of names is A c ; (iii) i is forbidden since it must occur after n 3 and it may not act as a stopping condition, the set of names is A f . Moreover, the recognizer for a range depends on whether its parent fragment has a conjunctive (∧) or disjunctive (∨) semantics. Therefor, the context for a range recognizer is a tuple (B, C, A c , A f , s), where s ∈ {∧, ∨} stands for the semantics of the parent fragment.

Elementary Recognizers for Ranges The elementary recognizer for a range with context is shown in Figure 5. It is started with the input start, termination is signaled by the outputs ok or nok. In s 0 it is idle and waits to be started; s 5 is the error state; in s 1 it is started and waits for the first occurrence of its name n; in s 3 it is counting the occurrences with cpt; in s 2 it is started and waits for the first occurrence of its name n, another range of the same fragment has started; in s 4 the minimum number of occurrences of n have been recognized, and another range of the same fragment has started.

Recognizers for Fragments

The recognizer for a fragment F = ({R 1 , . . . , R n }, ) with ∈ {∧, ∨} is the synchronous parallel composition of the recognizers for the R i s. At any time these recognizers can be in one of the following global states: (i) all are idle (state s 0 ); (ii) all are waiting in state s 1 ;

(iii) exactly one recognizer is counting (state s 3 ) and all others are either still waiting for their names to come (state s 2 ) or have already recognized their ranges (state s 4 ). If the semantics s inherited from the parent fragment F is disjunctive (i.e. s=∨), each recognizer can be stopped before it has even started counting, provided that at least one of the other ranges of F has started recognizing a sequence of its name. The recognizer of F signals termination with the output ok if all the recognizers for the R i s have signaled termination.

(P << i, false) F1 < F2 < F3 ({R1, R2}, ∧) n [1,1] 1 n [1,1] 2 ({R1, R2}, ∨) n [2,8] 3 n [1,1] 4 ({R1}, ∧) n [1,1] 5
Attributes (for each node except the root): -inherited: [s=∨] Ac/nok

s, B, C, Ac, A f -synthesized: α Example for n [2,8] 3 : s= ∨ B = {n1, n2} C = {n4} Ac = {n5} A f = {i} α = {n3}
[cpt>=u] Ac/ok Ac/ok C/ n/ [cpt+=1] n/[cpt+=1] C/ [s=∧]Ac/err A f ∨ B/err A f ∨B∨Ac/err [cpt<u]Ac ∨ C/err A f ∨ B/err [cpt=v]n/err [cpt>=u] C/ A f ∨ B ∨ n/err C/ [cpt<v]n/ [cpt+=1]
true/err Recognizers for Loose-Orderings Consider a loose-ordering

L = F 1 < • • • < F q .
The recognizer of L is made by composing sequentially the recognizers of the F i s: to start recognizing L, we have to send start to the recognizer of F 1 ; the output ok of the recognizer of F i is connected to the input start of the recognizer of F i+1 . The output ok of the last fragment signals the stop of the recognizer of L.

SystemC Implementation Each node of the syntax tree of the formula is translated into a SystemC monitor. The monitor of a range encodes the state machine shown in Figure 5. Activation of the root monitor is propagated to monitors at lower levels. If any of the range monitors detects an error, the composite monitor of the property reports an error. The monitor of a timed implication constraint T = (P ⇒ Q, t) has two SystemC specific variables sc_core::sc_time start,stop. start is set to the current simulation time when P is recognized; stop is set to the current simulation time when the recognition of Q is finished; their difference should not be greater than T .

Experiments and Evaluation Results

Experimental Setting We consider two strategies to obtain monitors from loose-ordering properties: (i) Drct is the direct translation into SystemC (section 6); (ii) ViaPSL first translates the properties into PSL (section 5); then the built PSL encodings are translated into SystemC monitors as described in [START_REF] Pierre | A tractable and fast method for monitoring SystemC TL specifications[END_REF][START_REF] Amor | Validation de systèmes sur puce complexes du niveau transactionnel au niveau transfert de registers[END_REF]. The time and memory complexities of the obtained monitors are compared: the former is measured in the number of operations executed by the monitors for each event observed, the later is defined by the number of bits needed to store the Boolean and bounded Integer variables. α(F j-1 ) |) with i (resp. j) ranging over all ranges R i = n [ui,vi] (resp. fragments F j ) of A or G, ∆ is a cost of translating ranges into new names. The time complexity of the monitors generated with the Drct strategy is Θ(max i∈ [1..q] | α(F i ) |), i ranging over all the fragments of A (resp. G); "max" is due to the fact that only monitors of the active fragment work while scanning a sequence. The space complexity of the monitor is Θ( q i=1 | α(F i ) |) for both Boolean and bounded unsigned Integer variables. The maximum value which can be assigned to any of these Integers is equal to max v i for all ranges R i = n [ui,vi] i of the pattern.

Figure 6 lists different configurations of the loose-ordering patterns used in the specification of our case-study (see section 3). The provided results show that our monitors have always smaller time/space complexities than the monitors obtained from PSL encodings. The presence of non-trivial ranges has no effect on the complexities of our Drct monitors, however their impact on the complexities of the ViaPSL monitors is huge.

Figure 1 :

 1 Figure 1: The verification framework

Figure 4 :

 4 Figure 4: The property (({n 1 , n 2 }, ∧) < ({n [2,8] 3, n 4 }, ∨) < n 5 << i, false)

Figure 5 :

 5 Figure 5: Elementary recognizer for a range R = n [u,v] : cpt is a counter; {start, n, B, A c , A f , C} are inputs; {err, ok, nok} are outputs. Each transition is of the form [condition]input/output[action] where input is a Boolean formula and output is a set.

Figure 6 :

 6 Figure 6: Comparison of Drct and ViaPSL strategies

  < n 3 < n 4 , T ) 296 1051 4×10 11 +∆ 2×10 12 +∆

			Drct		ViaPSL
	Configurations	time space	time	space
			(ops) (bits)	(ops)	(bits)
	(n << i, true)	80	192	238+∆	896+∆
	(n [100,60K] << i, true)	80	192 4×10 11 +∆ 2×10 12 +∆
	(({n 1 , . . . , n 4 }, ∧) << i, false)	230 1132	1785+∆	6720+∆
	(({n 1 , . . . , n 5 }, ∧) << i, false)	280 1568	2142+∆	8064+∆
	(n 1 ⇒ n 2 < n 3 < n 4 , T )	296 1051	1428+∆	5376+∆
	(n 1 ⇒ n	[100,60K] 2

Conclusion and Further Work

We defined the notion of loose-ordering for specifying the interactions between components. We proposed patterns to capture these properties and an encoding into SystemC monitors which is direct, and modular. The encoding is very efficient because it avoids size explosion, and fully exploits the fact that sub-formulas do not share names; when translating into PSL this structural information is lost. Future work will be devoted to a translation of the patterns into some code for generating random sequences. This will provide a full integration of loose-orderings in an ABV framework.

* This work has been partially supported by the European CATRENE project CA703 and by the LabEx PERSYVAL-Lab (ANR-11-LABX-0025).

† F. Maraninchi is orcid.org/0000-0003-0783-9178


Hui Li

Sébastien Le Beux
email: sebastien.le-beux@ec-lyon.fr

Gabriela Nicolescu

Ian O'connor

Energy-Efficient Optical Crossbars on Chip with Multi-Layer Deposited Silicon

Keywords: Optical Network on Chip, crossbar, optical loss. I

The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.

INTRODUCTION

Optical Network-on-Chip (ONoC) is an emerging technology considered as one of the key solutions for the future generation of onchip interconnects. It relies on optical waveguides to carry optical signals, so as to replace electrical interconnect and provide the low latency and high bandwidth. Moreover, 3D integration technologies allow both optical and electrical layers to be stacked. Proposals for ONoC can, thus, realistically envision the integration of sufficient photonic devices for fast chip-length communications [START_REF] Psota | ATAC: Improving Performance and Programmability With on-Chip Optical Networks[END_REF][2] [START_REF] Ye | A Torus-based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip[END_REF].

Among the proposed ONoCs, the crossbar-based solutions show good properties since they do not require any arbitration [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF] [START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF]. In such networks, the signal propagates from a source IP core to a destination IP core according to its wavelength (i.e. it relies on Wavelength Division Multiplexing, WDM), which is achieved by passive Microring Resonators (MRs). Existing optical crossbar implementations show different tradeoffs between design complexity and energy efficiency and demonstrate a relatively poor scalability. Emerging design technology relying on multi-layer deposited silicon allows efficient stacking of optical layers connected by optical vias (optical vertical coupler) [START_REF] Parini | Vertical link solutions for multilayer optical-networks-on-chip topologies[END_REF]. This technology allows reducing the number of waveguide crossings which is a main loss source in ONoC. Using multi-layer deposited technology to improve the crossbar-based design may lead to more power-efficient network suitable for largescale systems.

In this paper, we propose multi-layer deposited silicon based implementation of optical crossbars. We compare them with their initial single-layer implementations according to worst-case and average losses. They are key metrics to evaluate the ONoC scalability and power efficiency since the performances of all the considered optical crossbars are the same. While interconnecting from 4 to 64 IP cores, our results show that the ring-based crossbar demonstrates, on average, 36.9% and 55.2% improvements for worst-case and average losses over the related networks.

The paper is structured as follows. Section II presents the related work. Section III presents the considered architecture model. Section IV and Section V are the description of the proposed implementation of the considered crossbar. Section VI gives the results and Section VII concludes the paper.

II. RELATED WORK A. Optical crossbar on chip

Optical crossbars rely on wavelength-based signal routing to realize full-connectivity among IP cores. Such ONoCs rely on passive MRs and do not require any arbitration [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF] [START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF]. Related implementations of optical crossbars lead to Matrix [START_REF] Bianco | Optical Interconnection Networks based on Microring Resonators[END_REF], -router [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF], Snake [START_REF] Ramini | Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis[END_REF] and ORNoC [START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF] networks. These networks exhibit different properties such as the number of waveguide crossings, required wavelengths, MRs, etc. Their suitability thus depends on the architecture size, the connectivity requirements and the metrics to optimize. Few studies were achieved to compare the networks for a given connectivity scenario. In [START_REF] Ramini | Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis[END_REF], the authors compared -router, Snake and ORNoC networks for processors to memories application, showing higher energy efficiency for ORNoC. In our prior work [START_REF] Beux | Optical Crossbars on Chip, A Comparative Study based on Worst-Case Losses[END_REF], we compared the above mentioned networks for NxN architecture scenarios according to the worst-case losses in the signal paths; the results highlighted significant advantages for ORNoC. In this paper, we consider the use of multi-layer deposited silicon for the efficient implementations of optical crossbars.

B. ONoC relying on multi-layer deposited silicon

Multi-layer deposited silicon was recently proposed to improve the implementation of ONoCs by reducing the insertion loss induced by the waveguide crossing in the same layer [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF] (typically around 0.05dB [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF]). Optical vias allow signals to propagate from a layer to another at the price of some losses (typically around 0.1dB [START_REF] Parini | Vertical link solutions for multilayer optical-networks-on-chip topologies[END_REF]), which thus results in a significant reduction in the number of waveguide crossings to reduce the total loss of the whole optical path. Following this idea, MPNOC [START_REF] Zhang | A Multilayer Nanophotonic Interconnetcion Network for On-Chip Many-core Communication[END_REF] was proposed to realize energyefficient communications. In R-3PO [START_REF] Morris | Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance[END_REF], MRs located on different layers allow reconfiguring the optical bandwidth between the optical layers. In this paper, we propose multi-layer deposited silicon implementation of optical crossbars and we compare them according to the worst-case and average losses. The proposed ring-based optical crossbar, so-called ORNoC ML , demonstrates, on average, 36.9% and 55.2% improvements of worst-case and average losses respectively compared to the other crossbars for the network scales we considered.

III. ARCHITECTURE MODEL A. Architecture model overview

The considered 3D architecture is composed of an electrical layer implementing NxN IP cores and two optical layers implementing ONoC, with N an even number. Figure 1 shows an instance of this architecture, where N is equal to 4. The optical network in the optical layers is composed of on-chip laser sources [START_REF] Van Campenhout | A compact SOI-integrated multiwavelength laser source based on cascaded InP microdisks[END_REF] (to remove the use of power waveguide in Corona [START_REF] Vantrease | Corona: System Implications of Emerging Nanophotonic Technology[END_REF], which may increase the waveguide crossings in the same layer), MRs, and photodetectors. The ONoC is connected to the IP cores with Through Silicon Vias (TSV) [START_REF] Loi | Supporting Vertical Links for 3D Networks-on-Chip: Toward an Automated Design and Analysis Flow[END_REF]. Numerous ONoCs relying on WDM were proposed. Among these networks, wavelength routing scheme can be used to propagate data from a source IP core to a destination IP core, thus leading to a contention-free network (without need of arbitration), with high throughput and low latency.

Figure 1: The optical crossbar (ring topology in the example) is implemented in the optical layers and it interconnects IP cores

In the interfaces of such optical crossbar, the transmitters are composed of on-chip laser sources, and the receivers are composed of photodetectors and passive MRs that drop the signal into the photodetectors (the transmitters and photodetectors are not illustrated in Figure 1). Since we consider a full connectivity between IP cores, (N²-1)xN² laser sources, together with (N²-1)xN² photodetectors and (N²-1)xN² passive MRs, are required in the interface. The use of onchip lasers is considered since, for a given wavelength, the size of an on-chip laser is of the same order of magnitude with the size of an MR used to modulate continuous waves emitted by off-chip lasers, which leads to a similar on-chip size for both approaches.

For a given communication from a source IP core to a destination IP core, the required laser output power depends on the cumulated loss along the optical path. Considering a given receiver sensitivity, the more the losses, the more the minimum laser output power, the more the ONoC power consumption. Reducing the worst-case losses is thus mandatory to reduce the overall system power consumption. The most significant losses sources are due to the propagation of signals in the waveguides, the waveguide crossing and drop. A reduction of losses can be achieved by i) improving the network topology, ii) optimizing the layout and iii) using improved fabrication process such as multilayer silicon deposited technology.

B. Multi-layer deposited silicon technology

Multi-layer deposited silicon technology allows efficient designs of ONoCs by stacking optical layers [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF]. A key advantage of this technology is to reduce the loss of the waveguide crossing in one layer by using different layers, Figure 2-a. In this figure, red and blue colors represent photonic devices implemented in the first and second layer respectively. The design of waveguide crossing within a single layer will lead to 0.05-0.2 dB while 0 dB is expected by considering two layers. Optical vias allow transmitting signals from one layer to another. 3D photonic devices, such as MRs [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF] and Photonic Switching Elements (PSEs), can also be efficiently implemented with this technology, Figure 2-b andc. However, a relatively high drop loss (e.g. 1 dB [START_REF] Zhang | A Multilayer Nanophotonic Interconnetcion Network for On-Chip Many-core Communication[END_REF]) is expected for the multi-layer implementation compared to the single layer counterpart implementation (e.g. 0.5 dB [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF]). Hence, a key point for the reduction of the total losses is to ensure that a "costly" drop operation from a layer to another will lead to a significant reduction in the number of waveguide crossings [START_REF] Zhang | A Multilayer Nanophotonic Interconnetcion Network for On-Chip Many-core Communication[END_REF] or the waveguide length.

C. Model of worst-case and average losses

The worst-case and average losses are key metrics to measure the ONoC power efficiency since lower losses lead to lower laser output power, i.e. reduced energy/bit communications. In an optical crossbar, the total loss along an optical path L total is given by the equation [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF] and is an extension from the model proposed in [START_REF] Beux | Optical Crossbars on Chip, A Comparative Study based on Worst-Case Losses[END_REF]. L total depends on: the total propagation loss in the waveguide L waveguide , the total loss due to the effective number of waveguide crossings L crossing (i.e. waveguide crossing occurring in a same layer, as illustrated in Figure 2-a), the drop loss in a same layer L drop,1 (Figure 2-c), the drop loss from a layer to another L drop,2 (Figure 2-c), and coupler loss L coupler introduced by optical via. The loss induced by fabrication process variation is not considered. The parameters are given in details in Table 1 andTable 2.

dB coupler dB drop dB drop dB g cros dB waveguide dB total L L L L L L      2 , 1 , sin (1)
L waveguide =P propagation ×l s-d ; L crossing =P crossing ×N crossing ; L drop,1 =P drop,1 ×N drop,1 ; L drop,2 =P drop,2 ×N drop,2 ; L coupler =P coupler ×N coupler ;
Each communication between IP cores is characterized according to these characteristics and, by considering a given set of insertion losses values, the total loss in the path is obtained. The worst-case loss (L wc ) and the average loss (L avg ) are thus extracted by identifying the maximum values and by applying mean function on the values. This model is generic to be used for both single-layer and multi-layer implementations, which is suitable for comparison purpose.

IV. OPTICAL RINGS RELYING ON MULTIPLE LAYERS

In this section, we present ORNoC ML , a ring-based crossbar network that can be implemented with multi-layer deposited silicon. We first present the topology and connectivity of the network and then introduce the method used for its design.

A. Multi-layer implementation of ORNoC ML

In ORNoC ML , inter-IP core communication is realized through waveguides forming a ring suitable for multi-layer implementation. This is achieved without increasing the number of waveguide crossings in the same layer. The following operations are performed:  Injection: the IP core injects an optical signal into a waveguide through its output port. The wavelength of the signal specifies the destination IP core;  Pass through: the incoming signal propagates along the waveguide (i.e. no MR with the same resonant wavelength is located along the waveguide);  Ejection: the incoming optical signal is ejected from the waveguide and is redirected to the destination IP core. This is achieved by one MR characterized by the same resonant wavelength with the signal. In ORNoC ML , the same wavelength can be used to realize multiple communications in the same waveguide at the same time. Furthermore, multiple waveguides can be used to interface IP cores and both clockwise (C) and counter-clockwise (CC) directions are considered using separate sets of waveguides. The main feature of the network is the absence of waveguide crossing, which is possible due to a) the serpentine layout and b) the use of on-chip laser sources.

 x  x  x  x  x  x c) PSE b) MR a)
Figure 3-a illustrates a structural view of ORNoC ML assuming 3x3 IP cores. This is presented in comparison with ORNoC illustrated in the left-hand side of the figure. The red color indicates an implementation of the waveguides in the first optical layer. Solid and dot lines are for C and CC direction, respectively. Each waveguide propagates signals from a source IP core to a destination IP core. An efficient implementation of the SWSR (Single Write Single Read) communication scheme is obtained through the reuse of a same wavelength in a same waveguide for multiple communications purpose (this is achievable through the combined use of injection and ejection for the same wavelength [START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF]).

B. Ring located on multiple layers

As previously mentioned, a serpentine layout is considered to reduce waveguide crossings in the same layer. Figure 3-b shows the layout for 4x4 IP cores architecture example. Communications IP 1 IP 9 and IP 4 IP 2 in ORNoC are realized through C and CC directions respectively since they show the shortest path between the source and destination (i.e. they will demonstrate the lower propagation losses). It is worth noticing that the response paths (IP 9 IP 1 and IP 1 IP 9 ) will rely on opposite direction for symmetry and loss reduction purposes. IP 1 IP 9 is one of the communications that demonstrate the worst-case losses with 7 intermediate crossed interfaces. By considering a mesh distribution of the interfaces and a distance d between neighborhood interfaces, the total propagation distance for this example is 8d. This is not negligible since, on dimensional side by considering X and Y directions, connecting both IP cores with a dedicated waveguide in the same layer would require a length of 4d for only the waveguide layout. However, adding such a dedicated waveguide will i) introduce waveguide crossings and ii) affect the regularity, thus leading into a less scalable network.

An additional ring network is implemented in a second silicon layer, so as to reduce the propagation loss. This additional network is similar to the initial one but it is rotated from 90° in order to provide a better connectivity between the IP cores, as illustrated in the righthand side of Figure 3-b. In this figure, red color is used to represent waveguides located in the first layer and blue one is for the second layer. Since the additional waveguides are located in a different layer, the propagation of signal does not suffer from any extra waveguide crossing in the same layer, as shown in Figure 3-b. In this example, the communications between IP 1 and IP 9 are realized in the second layer (both C and CC directions) since the propagation distance is shorter than that in the first layer. Communications between IP 2 and IP 4 are still implemented in the first layer.

It is important to notice that there is no interaction between the waveguides. Each communication between a source IP core and a destination IP core relies on only a single waveguide, either C or CC, either located in the first or second layer. In other words, signals propagating in the network are never dropped from a layer to another. For each communication, there is a single drop operation (P drop,1 ) occurring to eject signals from a waveguide toward a photodetector. For the communications using the second layer, the coupling losses occurring in two optical vertical couplers are considered (P coupler ): one from layer 1 to layer 2, the second from layer 2 to layer 1. Figure 4 illustrates a layout example of an ONI. The waveguides in red and blue lines allow propagating signals in the first and second layer respectively. In this example, a single waveguide is considered for a couple of layer-direction (C-CC); however multiple waveguides can be regularly implemented without any waveguide crossing by applying the layout guidelines from [START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF]. For communications in the second layer, optical couplers allow interfacing the laser sources and the photodetectors with the waveguides located in the second layer.

C. Design method

The ring-based network is designed following a two-step methodology. First, each inter-IP core communication is assigned to the ring minimizing the propagation distance (i.e. by considering both the layer and the direction). Second, each communication is assigned to a wavelength in order to maximize the bandwidth per waveguide.

1) Ring assignment scheme

In ORNoC ML , the propagation loss is reduced by implementing communications with the ring showing the shortest propagation distance between a source and a destination. For this purpose, four distance matrixes are defined, each for one possible ring (layer 1 or layer 2, C or CC direction). For each pair of source and destination, the ring with the shortest distance is assigned and the bidirectional communications (C and CC) utilize the same layer for sake of symmetry. Figure 5 illustrates an excerpt of the ring assignment matrix for the 4x4 architecture example from Figure 3. Source IP cores are represented in the first column and destination IP cores are in the first row. The communications between IP 1 , IP 2 , IP 3 and IP 4 are realized by using the two rings in the first layer. It is worth noticing that if equal distance is observed by using the first or the second layer (e.g. for the communication IP 1 IP 2 ), the first layer is assigned since it avoids the use of optical vias and the loss is less. Communication IP 1 IP 9 and IP 9 IP 1 are realized by using the second layer in C and CC directions separately. The purpose of the matrix is two folds: i) to specify the communications considered for the wavelength assignment of each ring, as detailed in the following; ii) to evaluate the worst-case and average losses in the network.

IP13 IP12 IP14 IP11  1  2  3 pd  1 pd pd  2  3  3  2  1 pd  3 pd pd  2  1  1  2  3 pd  1 pd pd  2  3  3  2  1 pd  3 pd pd  2  1  x MR (
D S IP1 IP2 IP3 IP4 … IP9 IP10 IP11 … IP1 - C C C C CC CC IP2 CC - C C C C CC IP3 CC CC - C CC C C IP4 CC CC CC - CC C C … IP9 CC CC C C - C C IP10 C CC CC CC CC - C IP11 C C CC CC CC CC - …

Figure 5: Ring assignment matrix for 4x4 IP cores

2) Wavelength assignment algorithm

The efficient design of ORNoC ML requires careful wavelength assignment between IP cores in order to reduce i) the number of wavelengths and ii) the number of waveguides per direction if the maximal wavelength number is reached in one waveguide.

Based on the matrix obtained from the ring assignment scheme, the wavelengths are assigned as follow: first, for each ring, starting from source core IP X , a wavelength is assigned to the longest-distance communication in direction C to a destination core IP Y ; second, the same wavelength is assigned to the communication from IP Y to the longest-distance communication (still in direction C) to a destination core IP Z . We apply the same assignment to the following longestdistance communications until source core IP X is reached, to ensure that the wavelength is used on the whole ring (i.e. the wavelength is efficiently used on the ring). The same process is applied by starting from each of other IP cores with a different wavelength. The same algorithm iterates with other wavelengths until a wavelength is assigned to each communication. If the wavelengths number reaches the maximum allowed in one waveguide, then another waveguide is added and the algorithm continues from the initial wavelength, without any impact on the layout complexity and waveguide crossing. For sake of symmetry, bidirectional communications are implemented in C and CC directions with the same wavelength.

V. MULTI-LAYER IMPLEMENTATIONS OF RELATED OPTICAL CROSSBARS ON CHIP

For a fair comparison of the proposed network with related optical crossbars, we consider the multi-layer based implementations of crossbar networks. The considered networks are 1) Matrix [START_REF] Bianco | Optical Interconnection Networks based on Microring Resonators[END_REF], 2) router [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF] and 3) Snake [START_REF] Ramini | Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis[END_REF]. For each network, we give i) a structural view example, ii) the considered layouts, iii) the required number of MRs and iv) the loss model parameters (e.g. effective number of waveguide crossings).

A. Matrix

Figure 6-a illustrates the use of Matrix crossbar to interconnect 4 IP cores. In order to avoid any waveguide crossing in the same layer, input and output waveguides (respectively represented with red and blue lines) are located in the first and second layers respectively. This implies that the MR drops resonating signals from a waveguide located in the first layer to a waveguide in the second one (Figure 2). If full connectivity is considered, a total of 16 MRs will be required in this example. However, when considering only inter-IP core communications, the MRs located on the diagonal can be removed. For NxN IP cores, (N 2 -1)xN 2 passive MRs are, thus, used to implement the crossbar itself.

In order to match with the layout constraints from the regular NxN architecture, it is mandatory to link i) the transmitter part of IP cores to the input of the Matrix and ii) the output of the Matrix to the receiver part of IP cores. This is achieved by extending the network waveguides until the IP cores, assuming only X and Y directions for the waveguides. It is worth noticing that the waveguides are extended in their respective layers. Finding an optimal layout is not an easy task and it depends on various parameters such as the number of IP cores, the distance between the IP cores and the considered insertion losses. For instance, if the considered propagation losses are rather large (e.g. 2dB/cm), then a layout with waveguide crossings in the same layer may demonstrate lower losses than a layout without waveguide crossings (but with longer waveguide). Hence, for a fair comparison with the ring (which totally avoids waveguide crossings in the same layer), we assumed two layouts which are designed to a) avoid any waveguide crossing in the same layer between the network interfaces and the crossbar network itself (the network in such layout is named as Matrix ML,A ), and b) minimize the waveguide length (the network in such layout is named as Matrix ML,B ). Figure 6-b andc illustrate these layouts for the example of a 4x4 IP cores architecture. The crossbar network (i.e. matrix) is located in the middle of the optical layer for layout symmetry purposes (it is represented as a box for the sake of clarity). -router and Snake are multistage networks sharing similar properties. The input signals propagate along waveguides and when necessary can be dropped from a waveguide to another in order to reach the targeted outputs, as illustrated in Figure 7-a andb. Compared to the Matrix, the switching structure of -router and Snake is a symmetric PSE implemented with 2 identical MRs. For a fair comparison with Matrix and the ring-based network, a reduction method [START_REF] O'connor | Reduction Methods for Adapting Optical Network on Chip Topologies to Specific Routing Applications[END_REF] reduces the network complexity by managing only the required optical connections and removing the unused PSEs. For router and Snake, the PSEs located in the central row and central column are removed respectively.

IP8 IP4 IP13 IP9 IP7 IP3 IP14 IP10 IP6 IP2 IP15 IP11 IP5 IP1 IP16 IP12 1 16 1 16 IP6 IP8 IP9 IP11 IP5 IP7 IP10 IP12 IP4 IP2 IP15 IP13 IP3 IP1 IP16 IP14 Matrix Matrix b) d d d d
When considering a single layer for the implementation of the waveguides, the multistage topologies imply a relative large number of waveguide crossings in the worst-case path. Indeed, for networks with N inputs, there are N²-1 and 2N²-5 waveguide crossings in the worst-case path of -router and Snake respectively. This can be significantly reduced by assuming two layers for the implementation of the waveguides. For sake of regularity and symmetry, the input waveguides are alternately located in the first and the second layers, as illustrated in Figure 7. Following this layout design rule, the number of effective waveguide crossings (i.e. the number of waveguide

4 3 2 1 1 2 3 4 2 3 4 1 3 4 1 2 4 1 2 3 4 3 2 1  x a)
crossings in the same layer) in the worst-case path drops to 12 and 13 for 4x4 -router and 4x4 Snake respectively, which represent a 20% and 51.9% reduction. PSEs with both waveguides located in the same layer will be implemented in a traditional way (i.e. with both MRs designed in the same layer). Otherwise, PSEs are implemented with one MR located in each layer (see Figure 2-c). Similarly to the Matrix, the inputs and outputs of the network are linked to the IP cores. This is achieved with the layouts illustrated in Figure 7-c andd. Since -router and Snake have the same interface (i.e. the same waveguides are located in layers 1 and 2), the two layouts are considered for both networks (named as -router ML,A , router ML,B , Snake ML,A , Snake ML,B ). It is worth noticing that the layout without waveguide crossings cannot be improved by considering the multiple layers for the implementation of the waveguides. However, a significant reduction in the number of waveguide crossings is achieved for the layout considering the shortest waveguide length. This will be further evaluated in the result section of the paper.

IP8 IP4 IP13 IP9 IP7 IP3 IP14 IP10 IP6 IP2 IP15 IP11 IP5 IP1 IP16 IP12 1 16 1 16 IP6 IP8 IP9 IP11 IP5 IP7 IP10 IP12 IP4 IP2 IP15 IP13 IP3 IP1 IP16

VI. COMPARATIVE STUDY

We evaluate and compare the multi-layer based implementations according to the worst-case and average losses. [START_REF] Biberman | Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors[END_REF] 0.05 0.5 0.5 -0.1 Zhang [START_REF] Zhang | A Multilayer Nanophotonic Interconnetcion Network for On-Chip Many-core Communication[END_REF] 0.05 1 -1 -Pan [START_REF] Pan | FlexiShare: Channel Sharing for an Energy-Efficient Nanophotonic Crossbar[END_REF] 0.05 1 1.5 --Kirman [START_REF] Kirman | A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing[END_REF] 0.12 1 1 --Koka [START_REF] Koka | A micro-architectural analysis of switched photonic multi-chip interconnects[END_REF] 0.2 0.1 1.5 --

A. Worst-case and average losses evaluation

Figure 8 illustrates the evaluation results of worst-case loss for the same architectures as in the previous comparison. A first observation on the worst-case loss can be made regarding the layouts: for 2x2, 4x4 and 6x6 IP cores, the layout with the shortest waveguide lengths outperforms the layout without any waveguide crossing, independently from the network topology. However, the layout without any waveguide crossing demonstrates better scalability since the loss is less impacted by the increasing number of IP cores. For 8x8 architecture, it exhibits lower losses for -router and Snake. Similar observation can be made for average loss (not illustrated). The results indicate that the most scalable ONoC would combine the use of i) deposited silicon to reduce waveguide crossings in the network and ii) a layout avoiding waveguide crossing between the network and IP cores. These criteria are gathered into ORNoC ML , which demonstrates the lowest worst-case loss despite the long distance introduced by the serpentine layout. For 8x8 case, the worst-case path in ORNoC ML is 4.5dB, followed by Matrix ML,B with 4.75dB. By considering the average loss, ORNoC ML allows reducing the average loss by 55.2% on average compared to the other implementations. This significant difference is obtained through the shorter propagation distance between neighborhood IP cores. The improvement reaches 54% for 2x2 case and it increases to 56.3% for 8x8 case, where the average loss is 2.02dB for ORNoC ML compared to 4dB for Matrix ML,B . By considering the use of tunable lasers output power [START_REF] Ye | A Torus-based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip[END_REF], ORNoC ML will thus demonstrate significant power saving compared to the other crossbar implementations. 9 represents the comparison results for a fixed number of IP cores (6x6) and various distances between them (d=1, 1.5, 2, 2.5 and 3mm). The increase of the loss with the distance is higher for the networks relying on the layout without any waveguide crossing. In any case, and despite the serpentine layout, even for the longest distance we considered (3mm, which leads to a realistic 3.24cm² die size), ORNoC ML is the most power-efficient network.

Figure 9: Crossbar comparison for 6x6 IP cores in worst-case loss with distance between IP cores ranging from 1mm to 3mm by using parameters from Biberman [6]

For a 8x8 architecture, the implementation of Matrix requires 63 wavelengths wrt 64 wavelengths for Snake and -router. Such value is rather high with regard to the high level of crosstalk and it will lead to the fabrication variability. A more reasonable implementation would be to consider several smaller networks, which implies additional waveguide crossings [START_REF] Beux | Multi-Optical Network on Chip for Large Scale MPSoC[END_REF]. The use of the ring topology intrinsically leverages this issue since the number of waveguides can be set according to the crosstalk and process variability requirements. This can be achieved without any waveguide crossing because of the multi-

B. Comparison through insertion loss ranges values

The comparisons from the previous sections are achieved with a given set of insertion losses values, which may lead to incomplete and/or unfair comparisons according to the implementation of the network. For instance, considering low propagation losses and high crossing losses values will give an advantage to the layout without any waveguide crossing over the layout with the shortest waveguide length and also to ORNoC ML over the other crossbars. For this purpose, we further compare ORNoC ML and Matrix ML,B (i.e. showing the closest losses values compared to the ring) crossbars for 8x8 scale by considering a range of 0-2dB/cm for propagation losses and a range of 0-0.2dB for waveguide crossing loss. Figure 10 illustrates the comparison results on the worst-case loss for different distances between IP cores (i.e. 1, 1.5, 2 and 2.5mm). For a given distance, we evaluate for which propagation loss value Matrix ML,B approximates ORNoC ML . The area below a line represents the design space for which ORNoC ML provides lower worst-case losses; the area above the line gives the design space where the worst-case loss is lower for Matrix ML,B , and the line itself represents the designs with the same worst-case losses for both implementations. For instance, ORNoC ML exhibits lower worst-case loss for all the insertion losses values from Table 3 for a distance between IP cores below or equal to 1mm. For 2.5mm, Matrix ML,B outperforms ORNoC ML when values from Pan [START_REF] Pan | FlexiShare: Channel Sharing for an Energy-Efficient Nanophotonic Crossbar[END_REF] are considered and both network implementations show equivalent worst-case losses with the value from Kirman [START_REF] Kirman | A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing[END_REF]. Overall, ORNoC ML performs better especially when the distance becomes smaller, even compared to the Matrix ML,B which outperforms other architectures in worst-case losses. Regarding the average losses (not illustrated), ORNoC ML exhibits lower loss than Matrix ML,B for all the insertion loss values from Table 3 and all the considered distances.

C. Summary of the main results and discussion

ORNoC ML provides the lowest worst-case loss for 2x2 to 8x8 architectures over Matrix, -router and Snake networks. For realistic chip sizes (4 cm 2 ), ORNoC ML performs 22% and 51.4% improvement for worst-case and average losses compared to Matrix ML,B . In any cases, ORNoC ML outperforms the related crossbar implementations regarding the average loss metric. For larger architecture size, e.g. 10x10, Matrix, Snake and -router will reach a physical limitation related to the maximum number of wavelengths per waveguide (i.e. 64 wavelengths [START_REF] Batten | Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics[END_REF]). A solution to tackle this limitation is to replicate the network implementation, which leads to additional waveguide crossings and less regular layout. ORNoC ML demonstrates a better scalability since the use of extra waveguides allows keeping the layout regular without any waveguide crossing.

VII. CONCLUSION

In this paper, we proposed implementation of optical crossbar on chip utilizing multi-layer deposited silicon design technology. The ring based topology demonstrates an average of 36.9% and 55.2% improvement for worst-case and average losses respectively compared to multi-stage and matrix based topologies. We demonstrate the superiority of ring-based optical networks despite the use of technology allowing drastic reductions in the number of waveguide crossings.

Figure 2 :

 2 Figure 2: Implementation with one and two layers: a) waveguide crossing, b) MR and c) PSE

Figure 3 :

 3 Figure 3: Optical crossbars ORNoC and ORNoC ML : a) topology to interconnect 9 IP cores and b) layout for 4x4 IP cores.

Figure 4 :

 4 Figure 4: An Optical Network Interface

Figure 6 :

 6 Figure 6: a) Matrix topology, b) layout without waveguide crossings and c) layout with the shortest waveguide length B. -router and Snake

Figure 7 :

 7 Figure 7: a) -router and b) Snake and layouts c) without waveguide crossings and d) with the shortest waveguide length.Similarly to the Matrix, the inputs and outputs of the network are linked to the IP cores. This is achieved with the layouts illustrated in Figure7-c and d. Since -router and Snake have the same interface (i.e. the same waveguides are located in layers 1 and 2), the two layouts are considered for both networks (named as -router ML,A , router ML,B , Snake ML,A , Snake ML,B ). It is worth noticing that the layout without waveguide crossings cannot be improved by considering the multiple layers for the implementation of the waveguides. However, a significant reduction in the number of waveguide crossings is achieved for the layout considering the shortest waveguide length. This will be further evaluated in the result section of the paper.

Figure 8 :

 8 Figure 8: Worst-case losses evaluation for 2x2 to 8x8 IP cores by using parameters from Biberman [6] Figure9represents the comparison results for a fixed number of IP cores (6x6) and various distances between them (d=1, 1.5, 2, 2.5 and 3mm). The increase of the loss with the distance is higher for the networks relying on the layout without any waveguide crossing. In any case, and despite the serpentine layout, even for the longest distance we considered (3mm, which leads to a realistic 3.24cm² die size), ORNoC ML is the most power-efficient network.

Figure 10 :

 10 Figure 10: Comparison between Matrix ML,B and ORNoC ML (8x8 IP cores, P drop,1 =0.5dB, P drop,2 =1dB)

Table 1 Insertion Loss Parameters

 1

	Parameter	Description
	Ppropagation (dB/cm)	intrinsic propagation loss in a waveguide
	Pcrossing (dB)	crossing loss
	Pdrop,1 (dB)	drop loss in the same layer
	Pdrop,2 (dB)	drop loss in MRML and PSEML
	Pcoupler (dB)	vertical coupling loss (in optical vertical coupler)

Table 2 Network Implementation Characteristics

 2

	Parameter	Description
	ls-d	waveguide length between a source and a destination
	Ncrossing	effective number of waveguide crossings
	Ndrop,1	number of drop operations in a same layer
	Ndrop,2	number of drop operations from a layer to another
	Ncoupler	number of vertical couplers in a path

Table 3 : Insertion Loss Parameters

 3

	Optical loss	Pcrossing	Ppropagation	Pdrop,1	Pdrop,2	Pcoupler
	Biberman

  the use of on-chip laser sources. Following the methodology from[START_REF] Beux | Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)[END_REF], the ring would require 16 waveguides if we consider the optimistic maximum number of 64 wavelengths per waveguides, and 63 waveguides if we consider more realistic scenario with 16 wavelengths per waveguide. Regarding ORNoC ML , no waveguide crossing is required and the layout is regular, which makes the network scalable without any custom place-and-route tool[START_REF] Ramini | Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis[END_REF][START_REF] Ramini | Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-Core Processor with Awareness of Layout Constraints[END_REF].

	layer implementation and
		propagation loss	coupler loss	drop,1 loss	drop,2 loss	crossing loss
				Architecture Size
		2x2	4x4		6x6	8x8
		propagation loss	coupler loss	drop,1 loss	drop,2 loss	crossing loss
				d (mm)
	6	1mm	1.5mm	2mm	2.5mm	3mm
	4
	(dB)
	Lwc
	2
	0

ACKNOWLEDGMENT

Hui LI is supported by China Scholarship Council (CSC).