Nabil Cr Cmp

Avril Stéphane

Batton-Hubert Mireille

Didier

Bigot Jean

Pierre Mr

Olivier Pr1

Ing Ingénieur

Gloria Luz

Rodriguez Verjan

ABSI

Dauzère-Pérès, pour sa disponibilité et son soutien constante. Sa conance, son expérience, sa vision et ses indications toujours assertifs ont permis de mener à bien ce projet. Mes remerciements vont également à Jacques Pinaton, mon encadrant industriel, qui a toujours été présent pour répondre à mes questions. Merci à tous ceux qui ont participé dans le groupe d'implémentation industriel du projet W@R de STMicroelectronics. Ce travail au sein du groupe m'a permis de vivre et d'apprendre sur la gestion des changements au sein d'une organisation. Merci à Eric Tartière et Benoit Pennachio pour leur travail et leurs commentaires toujours constructifs; leur aide a été très importante pour l'implémentation des solutions dans le processus de fabrication. Merci à Sylvain Housseman pour son implication dans le projet et sa collaboration dans le développement informatique des modèles. Mes remerciements vont ensuite aux membres du jury pour avoir accepté d'évaluer cette thèse. Merci au professeur Bernard Grabot pour avoir accepté d'être le président du jury et aux professeurs Philippe Castagliola, Lars Monch et Natalie Sauer pour leur rapport et leurs suggestions qui ont permis d'améliorer le manuscrit. Merci à Claude Yugma avec qui j'ai pu partager diérentes idées au cours de ces années de travail. Il est dicile de remercier toutes les personnes de qui j'ai beaucoup appris et à qui j'aimerai ici exprimer mon amitié. Je remercie sincèrement toutes les personnes du département SFL et tous les amis et collègues de STMicroelectronics. Je remercie également Elizabeth Zehendner pour avoir partagé sa bonne humeur avec moi tout au long de notre cohabitation au bureau. Merci à Rezvan Sadeghi avec qui j'ai pu partager le bureau les derniers mois de mon séjour chez SFL. Merci aussi à Mehdi Rowshannahad qui m'a montré par son exemple que la discipline et la persévérance sont le clé de la réussite d'un projet. Merci Anastasia Frank et les s÷urs Céline et Hyacinthe Aubert pour leur amitié, leurs encouragements, les éclats de rire et pour tous les bons moments passés ensemble. Merci à ma chère Hyacinthe pour ses explications de la langue française qui m'ont permis de mieux la comprendre. Merci à Mme Bellecombe pour son accueil et sa générosité. Je tiens à remercier vivement mon frère Carlos Rodriguez pour ses conseils et les moments de partage. Enn, un immense merci à mes parents, mes frères, ma s÷ur et toute ma famille pour m'avoir donnée la liberté et le soutien nécessaires à la poursuite de mes études dans les meilleures conditions. Ils ont toujours été là pour me guider et me rappeler que: "Lo mucho o poco que haga he de hacerlo bien y con amor".

(e.g. Téléphones, TVs, voitures, objets communicants, ordinateurs, cartes de crédit). Par ailleurs, les fabricants de circuits intégrés proposent des produits de plus en plus performants à des prix de plus en plus compétitifs. Pour cela, les fabricants de semi-conducteurs cherchent constamment des stratégies de contrôle plus ecaces pour pouvoir garantir la qualité du produit nal à des coûts raisonnables.

Dans les processus de fabrication de semi-conducteurs, diérents types de contrôles existent pour maîtriser les procédés. Dans cette thèse, on s'intéresse à la maîtrise et la réduction du risque sur les équipements de production. On se concentre sur les contrôles de défectivité. L'indicateur de risque utilisé concerne le nombre de produits traités par un équipement depuis la date du dernier produit contrôlé. L'introduction des diérentes étapes de contrôle est indispensable pour réduire et maîtriser le risque sur les équipements de production. Par contre, la capacité d'inspection est limitée et le temps de cycle des lots inspectés peut être impacté en générant des conséquences sur le coût de fabrication.

Pour éviter cela, diérentes stratégies de sélection des lots existent et peuvent être classiées selon leur capacité à intégrer la dynamique d'une unité de fabrication (fab). Dans les stratégies de sélection dynamique, les lots sont contrôlés en temps réel et en optimisant un critère de risque. Ces stratégies sont récentes et sont beaucoup plus ecaces que les stratégies précédentes, mais aussi plus complexes à mettre en ÷uvre. Dans ce cadre, le système de sélection des lots pour la défectivité à STMicroelectronics Rousset est passé d'une stratégie statique à une stratégique dynamique. Nous avons proposé et validé industriellement diérents algorithmes pour identier les lots à relâcher (à ne pas contrôler) dans les les d'attente des lots en défectivité. Nous avons aussi développé et implémenté un modèle d'optimisation de la capacité pour l'atelier de défectivité, qui permet d'évaluer l'impact de paramètres critiques (e.g. plan de production, positions des opérations de contrôles dans la gamme de fabrication, valeurs des limites de risques) dans la gestion du risque global de l'unité de fabrication.

Ce résumé est organisé comme suit: le contexte général de ce travail ainsi qu'une description des contrôles de defectivité sont présentés dans la section 0.2. L'évolution de la stratégie de sélection des lots pour la défectivité est développée dans la section 0.3. Les algorithmes proposés pour l'identication des lots à relacher sont décrits dans la section 0.3.1. L'outil pour la planication de la capacité dans l'atelier de défectivité est exposé 2 Chapter 0. Résumé en français dans la section 0.3.2. Enn, nous concluons ce résumé avec la section 0.4 où des résultats industriels, conclusions et perspectives sont présentés.

Contexte et problèmatique

Les circuits intégrés sont présents dans presque tous les produits de notre vie quotidienne (e.g. Informatique, automobile, communication, électroménagers, objets communicants) et sont à l'origine de nouvelles technologies qui changent notre mode de vie. C'est en cela que l'industrie des semi-conducteurs est un secteur très important de l'économie mondiale.

Figure 1: Fabrication des circuits intégrés La fabrication des circuits intégrés peut être divisée en trois grandes étapes (Figure 1).

• Préparation de plaquettes de silicium (Wafers en anglais): Dans cette étape le silicium est extrait du sable. L'ingot de silicium monocristallin est découpé en wafers.

• Traitement Front-End: Les composants électroniques (i.e. Transisteurs, capaciteurs, resisteurs) sont fabriqués et inter-connectés. Pour cela, les wafers sont traités en différentes opérations : dépôt, lithographie, gravure, dopage, isolation et interconnexion qui se répètent plusieurs fois (voir gure 2).

• Traitement Back-End: Les plaquettes sont testées et découpées. Les circuits individuels sont assemblés et mis en boitier an d'obtenir les circuits intégrés.

Le traitement Front-End est le plus important et complexe des trois étapes de fabrication. Cette complexité est due à : l'échelle nanométrique des opérations de fabrication, les conditions d'extrême propreté nécessaires pour éviter la contamination des produits et les ux ré-entrant des produits dans toutes les opérations de production (les produits les plus complexes peuvent avoir plus de 40 couches). C'est pour cela que diérents contrôles sont 0.2. Contexte et problèmatique 3

Figure 2: Représentation de traitement Front-End [1] eectués pour sécuriser la production et pouvoir garantir la qualité des produits naux.

Diérents types des contrôles sont utilisés pendant la fabrication, comme par exemple: SPC (Statistical Process Control en anglais), FDC (Fault Detection and Classication en anglais), R2R (Run to Run en anglais), VM (Virtual Metrology en anglais) et la defectivité [START_REF] Bettayeb | Conception et évaluation des plans de surveillance basés sur le risque, limitation des incertitudes qualité avec des ressources limitées de maîtrise[END_REF]. Cependant, les contrôles peuvent aecter le temps de cycle des produits inspectés, ils sont coûteux et la capacité d'inspection est limitée. Pour ces raisons, 100% des lots de production ne peuvent pas être inspectés et l'échantillonnage (que nous appelons aussi "sélection") est nécessaire.

Les stratégies d'échantillonnage peuvent être classiées selon leur capacité pour intégrer la dynamique de la fab [START_REF] Nduhura Munga | Literature Review on Sampling Techniques in Semiconductor Manufacturing[END_REF]. Dans les stratégies statiques (Static Sampling en anglais) les lots sont sélectionnés au début de leur gamme de fabrication et selon un taux d'échantillonnage xe par produit [4], [5]. Ces stratégies sont communément utilisées et relativement simples à implémenter, mais la dynamique de la fab (e.g. Panne des équipements, changement de priorités, saturation de l'atelier d'inspection, contrôles spéciales faites sur les équipements) ne peut pas être intégrée. Dans les stratégies adaptatives (Adaptive Sampling en anglais) le taux d'échantillonnage est adapté selon la situation. Si le processus est moins à risque, le taux d'échantillonnage peut être réduit. Si le processus dérive, le taux d'échantillonnage augmente pour inspecter plus de lots, et ainsi détecter et corriger le problème [6], [7]. Ces stratégies peuvent intégrer d'une meilleure façon la dynamique de la fab mais la capacité des équipements d'inspection est dicile à gérer. Dans les stratégies dynamiques (Dynamic Sampling en anglais) les lots sont sélectionnés en fonction de : l'information qui peut être obtenue en les mesurant, l'état de production et la capacité d'inspection disponible [START_REF] Good | An MILP Approach to Wafer Sampling and Selection[END_REF], [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF]. Ces stratégies sont relativement récentes et plus diciles à mettre en ÷uvre. Dans le cadre de cette thèse, la stratégie de sélection des lots pour les contrôles de défectivité est passée d'une stratégie statique à une stratégie dynamique. Les contrôles de défectivité sont particulièrement complexes et une description de ces caractéristiques sont rappelées par la suite.

Chapter 0. Résumé en français

Contrôles de défectivité

Les contrôles de défectivité sont utilisés pour : surveiller le processus de fabrication an de détecter les défauts qui peuvent entrainer une perte de rendement, anticiper les dérives des équipements de production, réduire les excursions 1 et enn améliorer le rendement.

Par la suite, on se référera aux contrôles eectués en défectivité comme "les opérations d'inspection" ou "inspections D0" (zero défauts). La position des opérations d'inspection dépend de plusieurs critères. Les principaux sont : la pertinence de l'inspection, la criticité de l'étape de production et l'exposition tolérée pour chaque équipement de fabrication en termes du nombre de wafers à risque (Wafers at Risk, W@R en anglais).

1 Les excursions sont une perte de rendement qui arrivent de façon aléatoire dans le temps et à cause de dérives dans les équipements de production [START_REF] Keefer | The Role of Metrology and Inspection in Semiconductor Manufacturing[END_REF]. C'est-à-dire que seuls certains produits pourront être inspectés dans les étapes d'inspection où la recette existe. Les produits dits "mesurables" sont donc les produits qui peuvent être inspectés car la recette existe.

Problématique

Lorsqu'un équipement de production dérive, tous les wafers qui sont traités sur cet équipement peuvent être aectés, et, par conséquent, générer des excursions. L'impact des excursions dépend de la sévérité du problème et du nombre de wafers aectés [START_REF] Bean | Variation reduction in a wafer fabrication line through inspection optimization[END_REF], il est donc nécessaire de détecter le plus rapidement possible les problèmes. Pour cela, des inspections régulières sont dénies par produit et les lots à inspecter sont sélectionnés selon une stratégie d'échantillonnage. Quand cette thèse a commencé, seulement une stratégie statique pour la sélection des lots en défectivité était utilisée. Avec cette stratégie, un pourcentage de lots était sélectionné selon un taux d'échantillonnage déni comme "1/N ", "N" étant le nombre des lots à risque.

y x t 1 L 1 R 1 L 1 L 1 t 2 R 2 L 1 R 1 Figure 8: Rapport de W@R
La gure 8 présente les valeurs de W@R sur les équipements de production d'un même atelier de fabrication du site de Rousset de STMicroelectronics. La stratégie de sélection des lots est seulement statique. On observe que les équipements 5, 6 et 7 sont sur-contrôlés et les équipements 8 et 13 ne sont pas susamment contrôlés. Par conséquent, un contrôle optimal en termes de W@R sur les équipements de production ne peut pas être garanti quand la stratégie de sélection des lots pour l'inspection est statique [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF].

La stratégie de sélection des lots est devenue dynamique pendant la thèse. Les lots sont sélectionnés selon l'information qui peut être obtenue en les mesurant (i.e. réduction du W@R). La gure 9 montre globalement les diérentes applications développées. L'objectif du "Dispatching for sampling" est de s'assurer que chaque équipement de production traite au moins un lot mesurable (i.e. Un lot dont la recette d'inspection existe en défectivité).

L'objectif du "Sampling and skipping before D0" est de sélectionner les lots avant d'entrer à l'atelier de défectivité. L'objectif du "Skipping at D0" est d'identier les lots qui peuvent sortir de la le d'attente de défectivité s'ils ont des informations redondantes. Dans la section suivante une description des algorithmes développés pour l'application de "skipping at D0" est présentée.

Algorithmes de sélection des lots

Dans cette section, la méthodologie utilisée pour identier les lots qui peuvent sortir de la le d'attente de défectivité est présentée. Cette section correspond au résumé du chapitre 4 de la thèse. Les lots sélectionnés pour la réduction du W@R portent une information de réduction de risque sur les équipements de production où ils ont été traités. Cependant, l'état de production change et le W@R des équipements évolue dans le temps. [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF]. Par la suite, une description des indicateurs est présentée et la notation de [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF] rappelée:

• T : Nombre des équipements de production considérés.

• IL t : Limite maximale de W@R de l'équipement de production t.

• RV t : Valeur actuelle du risque sur l'équipement de production t. Dans notre cas c'est le W@R sur l'équipement t.

• G t,l : Réduction du risque sur l'équipement t si le lot l est inspecté.

• N RV t,l : Nouvelle valeur de risque de l'équipement t si le lot l est inspecté, i.e. N RV t,l = RV t -G t,l . Dans notre cas, cette valeur correspond à la nouvelle valeur de W@R (NW@R).

• N RV t (S): Nouvelle valeur du risque de l'équipement t si les lots dans l'ensemble S sont inspectés. Le N RV t (S) est calculé comme suit:

N RV t (S) = min l∈S N RV t,l
• α: Paramètre utilisé pour donner plus ou moins de poids aux lots qui permettent de s'éloigner le plus de la valeur maximale de risque (I L).

Le GSI est calculé comme suit:

GSI(S) = T t=1 N RV t (S) IL t α (1)
Avec l'indicateur RI l'impact d'un lot ou d'un ensemble de lots sur le risque global est évalué. Supposons qu'il y ait 3 lots dans la le d'attente (L 1 , L 2 , L 3 ). Si deux lots sont retirés simultanément, les possibles combinaisons listées ci-dessous sont évaluées:

1. RI({L 1 , L 2 }) = GSI(S \ S{L 1 , L 2 }) -GSI(S) = GSI(L 3 ) -GSI({L 1 , L 2 , L 3 }). 2. RI({L 2 , L 3 }) = GSI(S \ S{L 2 , L 3 }) -GSI(S) = GSI(L 1 ) -GSI({L 1 , L 2 , L 3 }). 3. RI({L 1 , L 3 }) = GSI(S \ S{L 1 , L 3 }) -GSI(S) = GSI(L 2 ) -GSI({L 1 , L 2 , L 3 }).
Le seuil T M etro est utilisé pour déterminer si un lot L ou un ensemble des lots S peuvent être retirés de la le d'attente S Initial .

GSI(S

Initial \ S) -GSI(S Initial ) T M etro (2)
Diérents algorithmes ont été développés et implémentés industriellement. Une brève description est présentée par la suite (pour plus de détails voir le chapitre 4):

• Algorithme 1 (Identication des lots skippables): Pour chaque lot dans la liste initiale S Initial , le RI est calculé et tous les lots dont RI(L) T M etro avec une itération sont retirés. Cet algorithme est utilisé pour le pré-traitement des données mais pas pour prendre la décision nale. Par exemple, s'il y a 2 lots dans la liste initiale (L 1 , L 2 ), le RI de chaque lot sera calculé comme suit:

1. RI(L 1 ) = GSI(S initial \ {L 1 }) -GSI(S initial ) = GSI({L 2 }) -GSI({L 1 , L 2 }) 2. RI(L 2 ) = GSI(S initial \ {L 2 }) -GSI(S initial ) = GSI({L 1 }) -GSI({L 1 , L 2 })

Implémentation Industrielle

Lorsque la stratégie de sélection des lots était seulement statique (i.e. Start Sampling) le nombre des lots arrivant en défectivité ne pouvait pas être contrôlé et il était très dicile d'identier les lots qui pouvaient être retirés de la le d'attente. Avec l'implémentation des compteurs de risque W@R sur les équipements de production et l'évaluation des lots concernant la variation de risque global, l'identication des lots avec information redondant a été possible. La gure 4.5b présente les résultats obtenus lorsque l'application a été implémentée et utilisée industriellement. Entre 20% et 40% des lots en attente en défectivité ont pu être retirés (remplacés) pour inspecter des lots avec plus d'information. Ces gains importants ont motivé l'implémentation d'une application qui intègre les décisions de sampling (lot à échantillonner) et skipping (lots à relâcher) pour optimiser la sélection des lots avant qu'ils n'arrivent en défectivité [START_REF] Housseman | Smart dynamic sampling for wafer at risk reduction in semiconductor manufacturing[END_REF].

min k Def P k • A k + QT P • T imeQT • t QT t s.t. t X i p,t • hh i p,t = h i p • V i ∀i, p (3)
i,c

Y i c,t • ( p e i c,p • hh i p,t • IL t - p e i c,p • hh i p,t • W D i c,p )+ QT t • IL t + ρ t • ScQt t • IL t • i,p X i p,t ∀t (4)
Y i c,t p e i c,p • hh i p,t • X i p,t • γ i ∀i, c, t (5)
Z i c + α • V i • SS i • ob i c t Y i c,t • e i c,p • hh i p,t ∀i, c, p (6)
A k + R k i,c Z i c • b i c,k • T imeD0 i c ∀k (7)
A k + R k + c,i V i • SS i • ob i c • b i c,k • T imeD0 i c CapaM ax k ∀k (8) X i p,t 0 ∀i, p, t (9)
Y i c,t 0 ∀i, c, t (10)
Z i c 0 ∀i, c (11)
A k 0 ∀k

Les contraintes 5.20 dénissent comment le volume de production du produit i est reparti entre les équipements de production t qualiés pour eectuer l'opération de production p. Les contraintes 5.21 expriment comment le nombre d'inspections Y i c,t eec- tuées pour contrôler l'équipement de production t peuvent réduire le risque en considèrant l'exposition de l'équipement de production entre l'opération de production p et l'opération d'inspection c (W D i c,p ). Ces contraintes considèrent aussi le nombre de QTs utilisés pour contrôler l'équipement de production t lorsque les inspections avec les lots de production ne permettent pas de garantir les limites W@R. Les contraintes 5.22 assurent que le nombre d'inspections eectuées dans l'équipement de production t ne soit pas supérieur au nombre de lots mesurables. Les contraintes 5.23 dénissent le bloc de couverture de l'opération d'inspection c. Le nombre total d'inspections allouées pour la stratégie dynamique de sélection des lots n'est pas connu à l'avance et il est dénit à travers l'optimisation. Les contraintes 5.23 sont la linéarisation de l'expression:

Z c i = max i,c,p ( t Y i c,t • e i c,p • hh i p,t -α • V i • SS i • ob i c )
Les contraintes 5.

General Introduction

The technological advances in semiconductor industry are among of the most robust in modern economy. Nowadays, almost every product in our everyday's life has integrated circuits (ICs) (e.g. Phones, cars, computers, TVs, communicating objects). The strong competition and market conditions force manufacturers to provide high quality products at a competitive price. However, semiconductor fabrication is extremely complex due to the continuous shrinking of the critical dimension, the extreme process conditions and the large variety of product mixes. In this way, semiconductor manufacturers seek to develop ecient and eective control strategies to propose high quality products at competitive prices. Actually, the signicant progress in semiconductor manufacturing would not be possible without the technological improvement of in-line inspections.

In this thesis, we focus on how to manage and reduce the risk (i.e. number of wafers at risk) during fabrication. With the introduction of inspection operations the cycle times of product are directly impacted with consequences on production costs. Therefore, sampling strategies are used to reduce the number of inspection operations while satisfying quality objectives. Several sampling techniques exist and can be classied according to their capability to deal with factory dynamics. Static sampling strategies are commonly used, because they are relatively easy to implement but the dynamics of the fab cannot be correctly managed, which often leads to cases of inspection operations being performed without real added value and unexpected levels of risk on process tools. Dynamic sampling strategies are relatively recent and aim at integrating the dynamics of the fab. Decisions on whether to select lots or not are taken in real time and considering the current production state. In semiconductor manufacturing, several types of controls exist. In this thesis, we focus on defectivity inspections, which aims at monitoring the processes for defect reduction and yield improvement. During this thesis, the management policy of STMicroelectronics was to implement a strategy to reduce the impact of excursions. Therefore,the sampling system used for defect inspection changed in the site of Rousset of STMicroelectronics from a static sampling strategy to a dynamic sampling strategy. Results showed signicant improvements in terms of risk reduction of the fab without the need to increase defect inspection capacity.

In this thesis, a novel approach to select the lots to inspect is proposed, it is based on a skipping mechanism to eciently manage the defect inspection queues and enable the release of lots with redundant information. Then, a model for defect inspection capacity planning is proposed, which considers both static sampling and dynamic sampling strategies. Finally, a study on how the design of defect inspection control plans can impact risk is performed. The manuscript is organized as follows:

• Chapter 1 presents the industrial context. It provides a general description of the semiconductor manufacturing process and the principal types of controls that are performed during fabrication. Then the problems are described and the thesis objectives are discussed.

• Chapter 2 proposes a literature review for the inspection allocation problem, and discusses the dierent research axes that are considered in this thesis.

• Chapter 3 describes how the sampling system changed from static sampling to dynamic sampling in the Rousset factory of STMicroelectronics.

• Chapter 4 details the algorithms developed for optimizing the selection of lots through a skipping mechanism. Numerical experiments on industrial data are presented and discussed.

• In chapters 5 and 6, a model is proposed for the capacity planning problem when static sampling and dynamic sampling strategies are considered. As in chapter 4, numerical experiments on industrial data are presented and discussed.

• Chapter 7 presents a study on how the defect inspection control plan design can impact the tool risk management.

The manuscript concludes with a general discussion of the conclusions, industrial results after implementing the dynamic sampling approaches and perspectives for future work. Introduction

The semiconductor term refers to the availability of a material to conduct electricity.

Nowadays, more than 85% of Integrated Circuits (ICs) are made from silicon semiconductor material. IC devices refer to the transistors, diodes, resistors and capacitors that are manufactured on the silicon surface and that are connected into a circuit to dene how the chip will function [START_REF] Quirk | Semiconductor Manufacturing technology[END_REF].

The industry of semiconductors was born with the invention of the rst transistor in 1947 at Bell Laboratories. Some years later, in 1957 the rst commercial transistor was fabricated at Fairchild Semiconductor Corps. Then, in 1959 the integration of multiple electronic components on one silicon substrate was co-invented by Robert Noyce at Fairchild

Semiconductor and Jack Kilby at Texas Instruments. These two inventions represent the basis for the IC that we know nowadays [START_REF] Riordan | The invention of the transistor[END_REF]. The extraordinary development and innovation of semiconductor industry is one of the most robust in modern economy (more than U.S $ 2 trillion industry [START_REF] Mack | Fifty years of moore's law[END_REF]). Actually, electronics have been an enabler for productivity and growth in all areas of economic activity. Almost each product in our everyday's life has some microelectronic components: Phones, printers, cars, TVs, PCs, electrodomestics, etc. Moreover, consumers receive products with higher performances and ever lower prices.

Since 1970, the number of components per chip has doubled every two years following the historical trend known as Moore's Law. With this continuous down scaling of the critical dimension in the integrated circuit, the controls performed during the manufacturing of ICs have a key role to achieve the expected yield 1 . Indeed, the signicant progress during the last 30 years in the semiconductor industry would not be possible without the science of yield enhancement and defect reduction [START_REF] Guldi | In-Line Defect Reduction from a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing[END_REF]. In this chapter, we introduce the semiconductor manufacturing processes and the controls that are performed during fabrication.

1 Yield : Is one of the most important metrics to evaluate the performance of a wafer fab. It expresses the ratio of good produced parts over the total produced parts.

CHAPTER 1. INDUSTRIAL CONTEXT

This chapter is organized as follows: section 1.2 provides a general introduction of the semiconductor manufacturing process. Section 1.3 describes the role of process control and denes the framework of this work. In particular, this section introduces defect inspection and how defect inspection control plans are dened. Finally, the problem and scientic objectives are presented in Sections 1.4 and 1.5.

IC Fabrication

The fabrication of an Integrated Circuit (IC) can be divided into three general stages:

• Wafer Preparation: A silicon ingot with the appropriate diameter is sliced into thin wafers. A circular shape is used in order to minimize losses due to wafer handling during fabrication.

• Front-end Processing: In this stage the wafer fabrication is performed. It is divided into Front-End Of Line (FEOL) and Back-End Of Line (BEOL). In the FEOL the electronic components are fabricated (i.e. transistors, capacitors, resistors), and in the BEOL the electronic components are interconnected.

• Back-end Processing: It refers to the testing, sorting, assembling and packaging of each die of the wafer. In the testing and sorting steps, each die is probed and electrically tested, bad dies are marked to be sorted later. In the assembling and packaging steps, the wafers are cut to separate each die, the marked dies are scraped or rejected and the others are packed. Then, the metal connections are bounded to each die, which is encapsulated in a protective package. At the end, the nal test is performed to ensure that the product meets the electrical and environmental specications.

This thesis focuses on the Front-end Processing. Therefore, we introduce the dierent processes performed during the wafer fabrication. The wafer fabrication in semiconductor manufacturing is characterized by its complexity and highly expensive processes. An IC is made layer by layer and the number of layers depends on the product technology. Complex technologies can have more than 40 layers, which implies more than 400 successive processes. Figure 1.1 is a schematic representation of the wafer fabrication processes. A general explanation of the dierent processing steps to create a layer is presented. • Photolithography process : It is used to add the patterns on the wafer. First, the wafer is coated with a lm of photosensitive polymer. Then, the wafer pattern is transferred from a photo mask, also called reticle, onto the photosensitive polymer by projecting light through the reticle and exposing the wafer using ultraviolet light.

Finally, the polymerized sections of photoresist material are removed from the wafer to develop the pattern.

• Etch Processes : With the etch processes, the areas dened by the patterns can be removed. In wet etch, liquids are used such as, acids, bases and solvents to chemically remove wafer surface material. Whereas in dry etch, the wafer surface is exposed to a plasma created in the gaseous state. Dry etch is the most common etch process and a high-density, low-pressure etch reactor, such as the ICP (Inductively-coupled Plasma) is widely used [START_REF] Quirk | Semiconductor Manufacturing technology[END_REF].

• Planarization processes : In order to achieve a at layer, the wafer surface is polished. This is critical for the follow-on process steps (e.g. better linewidth control during photolithography) and can serve to increase device yields by removing undesirable foreign material on the wafer surface. The most common planarization technique is Chemical Mechanical Polishing (CMP) [START_REF] Quirk | Semiconductor Manufacturing technology[END_REF].

• Ion Implantation : With ion implantation, the doping process of the wafer is performed to obtain the right electrical properties (i.e. specic regions with positive 2 Cluster tool: A tool that combines several process chambers within a closed environment together with a handling robot.

CHAPTER 1. INDUSTRIAL CONTEXT

or negative charge). The most used gases carrying the desire dopant are arsenic, phosphorus, boron, boron diuoride, indium, antimony, germanium, silicon, nitrogen, hydrogen, and helium [START_REF] Rubin | [END_REF]. Ions are accelerated for implantation over an energy range from ≈ 100eV to nearly 10MeV and a dose range from 10 10 to over 10 18 ions/cm 2

[21].
Wafer fabrication is one of the most costly, complex and time consuming stages of the IC manufacturing. The complexity factors can be summarized in three categories:

• Process conditions, which refer to re-entrant ow, mix of dierent process types, unrelated parallel machines, sequence-dependent setup times, etc. [START_REF] Monch | Production Planning and control for semiconductor wafer fabrication facilities[END_REF][START_REF] Gupta | Operational planning and control of semiconductor wafer production[END_REF].

• Product evolution, which refers to the continuous change of products design in order to face the increasing demand for more powerful and faster devices [START_REF] Mack | Fifty years of moore's law[END_REF][START_REF] Arden | Towards a More than Moore Roadmap[END_REF].

• Market conditions, which refers to the highly uncertain demand, the long lead times and the high cost of capacity increase [START_REF] Gupta | Operational planning and control of semiconductor wafer production[END_REF][START_REF] Geng | A review on strategic capacity planning for the semiconductor manufacturing industry[END_REF].

For all these reasons, it is crucial to guarantee the quality of the nal products. The yield is one of the most signicant metrics to evaluate the ability of a wafer fab to produce high quality products [START_REF] Leachman | Competitive Semiconductor Manufacturing: Summary Report on Findings from Benchmarking Eight-inch, sub-350nm Wafer Fabrication Lines[END_REF]. It is expressed as the ratio of good produced parts over the total produced parts. The types of controls performed in semiconductor manufacturing can be classied into six main levels [START_REF] Bassetto | Contribution à la quantication et à l'amélioration des moyens de production[END_REF]: Facilities and technical installations, equipment sensors, fab and in-line measurements, parametric test, functional test and physical characterization. In this thesis, we focus on the in-line measurements and the process control performed during fabrication. The next section introduces the key areas for process control.

Process Control in Semiconductor Manufacturing

In order to achieve the challenging goals of the semiconductor industry, wafers fabs have improved the control over process parameters and reduced the source of defects during fabrication. The key areas for process control are Metrology and Defect Inspection [START_REF] Keefer | The Role of Metrology and Inspection in Semiconductor Manufacturing[END_REF].

The objective of Metrology is to control the physical and electrical properties of the wafers during fabrication. Many of the improvements on Metrology came from the development of sophisticated equipment that can provide real-time data. The objective of Defect Inspection is to detect and reduce the defects produced by particles or process drifts that aect the production yield. The main improvements in defect reduction came from the development of tools with higher sensibility and techniques for defect classication and source identication [START_REF] Guldi | In-Line Defect Reduction from a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing[END_REF]. Metrology and inspection tools can be divided into two categories:

stand alone measurement tools and integrated measurement tools (See Table 1.1).

The information acquired from the process and the product need to be properly processed in order to create knowledge, increase equipment eciency and accelerate yield improvement. Advance Process Control (APC) includes a wide range of techniques to obtain and treat the information in order to improve the electrical performance of devices by reducing variations and correcting drifts during the manufacturing process. The information can be classied as follows [START_REF] Su | On the Interaction between Measurement Strategy and Control Performance in Semiconductor Manufacturing[END_REF]: i) Real-time equipment data which are typical from in-situ sensors, ii) Data on geometric properties, which are obtained with integrated metrology tools and with stand-alone metrology tools, iii) Wafer Acceptance Test data (WAT), which are provided by the electrical tests at the end of the line and is available after long time delays because many steps are required to complete the structure before measurement, iv) Yield data, which give the percentage of good dies over the total produced dies, usually available after almost one month of production.

The dierent types of methods used to obtain and analyze the information can be summarized as follows:

• Statistical Process Control (SPC): It is based on statistical tools to ensure the stability of the process. SPC is used to decide whether the process is operating under statistical control or not. The SPC was born with the control chart proposed by Walter Shewart in 1930. Thanks to the availability of automated in-situ data collection and real time data processing, SPC has signicant evolve over the years (e.g. multivariate control, model-based SPC, time series models) [START_REF] Spanos | Statistical process control in semiconductor manufacturing[END_REF].

• Fault Detection and Classication (FDC): It is a statistical method focused on equipment data. The data is collected in real-time and, when a problem is detected, the tool is stopped and actions are taken. [START_REF] Spanos | Statistical process control in semiconductor manufacturing[END_REF] • Run-to-Run (R2R): It is a loop control technique based on equipment and lot information. Depending on results obtained in a run, the controller adjusts the recipe variables to reduce the output variability. In general R2R controllers are models coupled with a mechanism to observe the variables of interest. There are two types of control loops: Feed-forward and Feed-back. The Feed-forward loop adjusts the recipe parameters using the results of previous measurements. The Feed-back loop adjusts recipe parameters based on results of post-measurements in order to counteract process drifts [START_REF] Stoddard | Application of feed-fordward and adaptive feed back control to semiconductor device manufacturing[END_REF][START_REF] Edgar | Automatic control in microelectronic manufacturing: Practices, challenges and possibilities[END_REF]. reduction due to less direct measurements on wafers [START_REF] Kang | A virtual metrology system for semiconductor manufacturing[END_REF]. However, development of accurate models and robust over time is a challenge due to the large number of input variables and the lack of real measured lots in the learning phase of the model [START_REF] Besnard | Virtual metrology modeling for cvd lm thickness[END_REF], [START_REF] Ferreira | Virtual Metrology Models for Predicting Physical Measurement in Semiconductor Manufacturing[END_REF].

• Defect Inspections or Defectivity controls: They are used to monitor the process for defect excursions and to drive continuous improvement of the yield. Excursions are temporal yield losses that randomly happen (in time) as a consequence of an out-ofcontrol condition on a process tool. In this thesis we focus on how to manage and reduce the number of wafers at risk regarding defect inspections. Therefore, only the control operations performed in defect inspection area denoted as inspection operations are considered. This type of controls are presented in detail in the remaining of this section.

Description of Defect Inspections

The main role of defect inspections (or Defectivity controls ) during manufacturing is to monitor the process for defect excursions and to drive continuous improvement of the yield. Inspections are performed either on patterned wafers or non-patterned wafers. The inspections performed on patterned wafers are used to decrease defectivity during the ramp-up and full production phases, to monitor the processes that introduce contamination, scratches or pattern defects and to predict the yield. The inspections performed on non-patterned wafers are used to monitor contamination and surface quality of the wafer and to monitor the cleanliness of tools (e.g. process and metrology) [START_REF] Keefer | The Role of Metrology and Inspection in Semiconductor Manufacturing[END_REF]. In general, the control operations performed in the Defect Inspection Area are addressing all the production tools of the fab. Figure 1.2 is an operational description of the defect inspection area. within the slot is veried with a Sorter tool.

2. Wafer Inspection. The number of defects over the surface are counted (defect density) and the localization of defects over the wafer is generated (mapping of defects). This is done with optical detection tools (i.e. Brighteld, Darkeld) or tools for electrical test (i.e. Electro beam). The optical detection principle is based on the die to die comparison. If the intensity of the reected light is larger than a predened limit, a defect is detected. Results are compared with predened control limits and if the lot is considered under control, it can continues to the next process operation.

Otherwise, the lot cannot exit defect inspection and further analysis is performed.

3. Analysis. In this phase, the defects are reviewed, classied and the root cause identied. Defects can have a signature or a pattern that is characteristic of the process step and/or the process tool (Figures 1.3 and 1.4). At this stage, there are some defects whose root cause can be identied based on a typical signature. However when several failures occur simultaneously, detection becomes more complex.

(a) Review. In the review, an image of the defects is obtained. This is done with specialized microscopes that use dierent technologies (e.g. Optic microscope, Scanning Electron Microscope (SEM)).

(b) Defect classication. In this phase, the defects are classied and their relative importance is characterized based on their frequency and size. In the past, this phase was entirely manual, i.e. a trained operator sorted the defects into categories using a reference book that contained the image of typical defects. Nowadays, Automatic Defect Classication (ADC) systems are available which signicantly reduce the subjectivity and errors from operators [START_REF] Keefer | The Role of Metrology and Inspection in Semiconductor Manufacturing[END_REF].

Future trends include real-time defect classication, higher detection sensitivity, improvements on data management for yield learning and in-situ particle monitoring [START_REF] Guldi | In-Line Defect Reduction from a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing[END_REF].

(c) Defect source identication. The objective of this phase is to identify the process tool that generates the defect. This is performed using a variety of techniques such as Spatial Signature Analysis (SSA), Automated Image Retrieval (AIR) [START_REF] Tobin | Integrated applications of inspection data in the semiconductor manufacturing environment[END_REF]. The root cause of some defects can be identied based on typical signatures, gure 1.3 is an example of three types of signatures. The signature of gure 1.3(a) is a double-slot signature. This was produced by a robot handler that attempts to place a wafer in a slot that is already occupied, this information is enough to locate the source of the problem without further analysis. This is the same for gure 1.3(b), which is due to a robot handler that scratched the wafer. However, there are some signatures that need further analysis. For example, gure 1.3(c) presents the signature of a CVD contamination. In this case, the defect engineer isolates a particular CVD but there is not enough information on the composition and source of the contamination defects [START_REF] Gleason | An integrated spatial signature analysis and automatic defect classication system[END_REF]. • Criticality. The criticality of a process is based on the killer ratio (KR). The KR denes whether a defect is killer or not depending on the size and the pattern density where it is located 5 [START_REF] Pepper | Inline automated defect classication: a novel approach to defect management[END_REF]. In general, defect inspections are located between critical processes for the product (e.g. Metal deposition, photolitography, etching steps, lm deposition).

• Relevance. It refers to the capability to detect defects and the time required to perform the inspection. The capability of an inspection operation depends on the nature of the layer. For example, after an opaque layer, it is not possible to inspect the wafer because the light cannot be reected. After a transparent layer, the defects of all layers can be observed, hence locating the defect is too complex. After a metallic layer, the material reects too much light, thereby many false defects are detected. In addition, there are some process conditions that restrict the creation of inspection operations, such as time constraints between consecutive process steps.

These constraint loops are established to prevent the native oxidation and contamination eects on the wafer surface. If the time constraint is violated, the lot will be scrapped [START_REF] Klemmt | Scheduling jobs with time constraints between consecutive process steps in semiconductor manufacturing[END_REF].

• Exposure. It refers to the minimum number of wafers that are exposed if a problem occurs. It is calculated as the throughput (TH) of the process tool multiplied by the cycle time (CT) from the process operation until the inspection operation (C T ×T H).

With the introduction of dynamic controls, this criterion is now very important to locate defect inspection operations.

In order to inspect a new product or to control a given process, it is necessary to create an inspection recipe. The inspection recipe contains the measurement parameters such as optical and signal processing congurations. Due to the number of parameters to consider, the complexity for creating inspection recipes increases as the inspection technology advances [START_REF] Keefer | The Role of Metrology and Inspection in Semiconductor Manufacturing[END_REF]. This is why only the necessary number of inspection operations are created. Therefore, when a lot of a given product can be inspected, it is said measurable, otherwise, the lot is not measurable.

Problem Description

When a process or a tool drifts out its control limits, all the wafers that are processed can be aected and generate excursions 6 . Considering that the impact of an excursion depends on the severity and the number of wafers that are aected before the problem is identied and corrected [START_REF] Bean | Variation reduction in a wafer fabrication line through inspection optimization[END_REF], the need to nd defective products as fast as possible is critical. This is 5 A defect is considered Killer when its presence can cause the dice structure to fail. 6 Excursions: Temporal yield losses that randomly happen (in time) as a consequence of an out-of- control condition on a process tool.

1/N N × CHAPTER 1. INDUSTRIAL CONTEXT 1.

Thesis Objectives

Within the framework of this thesis, we focus on how to manage and reduce the number of wafers at risk on process tools regarding defect inspection controls. As previously discussed, defect inspection controls are particularly complex because they address all the production tools of the fab. During the realization of this thesis, the sampling system in the site of Rousset of STMicroelectronics changed from a sampling strategy that was only focusing on yield enhancement (achieved with start sampling) to a sampling strategy that also focuses on faster detection and reduction of excursion impacts (achieved with dynamic sampling).

Hence, the following objectives were dened:

• To propose and implement new methods to reduce and manage the number of wafers at risk on process tools.

• To propose and implement a new model for defect inspection capacity planning that considers both sampling strategies (i.e. Static and Dynamic sampling).

• To study how the design of defect inspection control plans inuence the risk on tools.

Conclusions

In this chapter, we introduced the dierent processes performed during wafer fabrication and the importance of process control during manufacturing. Control operations are necessary to ensure the quality of products, however they are costly and directly impact cycle times of products. Hence, only a limited number of lots can be controlled. It is thus critical to cleverly select these lots. In this thesis, we focus on how to manage and reduce the number of wafers at risk on process tools regarding defect inspections. At the beginning of the project, only a Static sampling strategy named Start Sampling was used in the site of Rousset of STMicroelectronics to select the lots for inspection. This strategy consists in selecting the lots at the beginning of their manufacturing process that will later be controlled in all the inspections operations dened in their defect inspection control plan.

The main concern is yield enhancement by controlling critical processes for the product which are evaluated with the killer ratio. However, with Start Sampling, the dynamics of the fab (e.g. tool qualication, dispatching rules, lot priorities) cannot be correctly handled, generating cases of over-control and lack of control on process tools. In order to better control process tools by reducing the number of wafers at risk, dierent research axes are investigated: New methods to dynamically select lots for inspection, a new model for inspection capacity allocation and the analysis of the impact of the control plan design on the risk on tools. In the next chapter, a literature review on these dierent axes is provided, and chapter 3 presents a description of how the sampling system changed. Introduction

Inspection allocation problems on multi-stage manufacturing systems have been widely studied in the literature. Dierent surveys can be found in [START_REF] Raz | A survey of models for allocating inspection eort in multistage production systems[END_REF], [START_REF] Mandroli | A survey of inspection strategy and sensor distribution studies in discrete-part manufacturing processes[END_REF], [START_REF] Shi | Quality control and improvement for multistage systems : A survey[END_REF], [START_REF] Shetwan | Allocation of qualigy controls stations in multistage manufacturing systems[END_REF] and [START_REF] Nduhura Munga | Literature Review on Sampling Techniques in Semiconductor Manufacturing[END_REF].

The main objective of inspection allocation is to determine: i) The number and location of inspection stations, ii) The sampling frequency and sample size and iii) The rigor of inspections (acceptance limits) [START_REF] Shetwan | Allocation of qualigy controls stations in multistage manufacturing systems[END_REF]. These three questions are interrelated. Thereby, when the problem aims at nding the optimal location of inspections, it is assumed a xed sampling rate. When the problem aims at nding the optimal sampling mechanism, it is assumed that the inspection locations are already established. Works that address the two questions simultaneously use an iterative mechanism [START_REF] Williams | Optimized Sample Planning for Wafer Defect Inspection[END_REF], [START_REF] Hall | A quality-cost model of in-line inspections for excursion detection and reduction[END_REF]. According to the life cycle of the product, dierent inspection allocation objectives are considered. During the rampup phase, most of the problems are unknown, and as many data as possible are necessary to characterize defects and systematic issues. Therefore, a high sampling frequency is required to dene the critical layers to inspect. When the product is in the full production phase, the critical layers are already dened and the focus is on an economic sampling strategy to monitor excursions [START_REF] Bousetta | Adaptive Sampling Methodology for In-Line Defect Inspection[END_REF].

In the following, a review of inspection allocation problems is presented. The scope of the literature is excursion monitoring and control. The reviewed papers are classied according to the following criteria: i ) System Characteristics, ii ) Solution approach and iii ) Sampling Strategy.

System Characteristics

According to the conguration of the system, three general categories can be identied: i) Serial systems, ii) Assembly systems and iii) Non-serial systems. In Serial Systems, the products pass through a sequence of processing stations where each processing activity has a single immediate predecessor [START_REF] Van Volsem | An evolutionary algorithm and discrete event simulation for optimizing inspection strategies for multi-stage processes[END_REF]. In an Assembly System, products from dierent manufacturing lines are assembled [START_REF] Penn | Optimizing the quality control station conguration[END_REF]. Congurations that are neither serial nor assembly are Non-Serial systems. A semiconductor manufacturing system can be considered as a typical example of a Non-serial manufacturing system. Therefore, we focus on this system conguration. Concerning the risk associated to performing an inspection, there are two type of errors: Type I error and type II error. Type I is the risk associated to the rejection of good items. Type II error refers to the acceptance of non-conforming items. In general, the type II error is more serious [START_REF] Shetwan | Allocation of qualigy controls stations in multistage manufacturing systems[END_REF]. Some authors considered both errors [START_REF] Elliott | Critical Dimension Sample Planning for Sub-0.25 Micron Processes[END_REF], [START_REF] Gudmundsson | Inspection and metrology capacity allocation in the full production and ramp phases of semiconductor manufacturing[END_REF], while others considered only one type of error [START_REF] Bousetta | Adaptive Sampling Methodology for In-Line Defect Inspection[END_REF], and others considered that inspection is error free [START_REF] Narahari | Modeling Re-entrant Manufacturing Systems with Inspections[END_REF], [5], [START_REF] Hall | A quality-cost model of in-line inspections for excursion detection and reduction[END_REF].

Another important characteristic is the defect mechanism, which can be classied into two categories. In the rst category, the probability of an item to become defective is independent of the processing of previous items [START_REF] Shiau | Inspection resource assignment in a multistage manufacturing system with an inspection error model[END_REF], [START_REF] Lee | Planning quality inspection operations in multistage manufacturing systems with inspection errors[END_REF]. In the second category, the process is modeled as a two-state Markov process, because during the time that the process is performing out-of-control, it can generate defects on wafers, and the state changes when the problem is detected and corrected [START_REF] Gudmundsson | Inspection and metrology capacity allocation in the full production and ramp phases of semiconductor manufacturing[END_REF]. In this work it is considered that inspections are error free and the excursion monitoring and control problem is a two-state Markov Process. Several works consider that the inspection can be performed immediately after any process station [5]. But the type of controls considered in this thesis can address several process tools and cannot be performed after each process operation. The location of control operations (i.e. inspection operations) are determined by the criticality and capability to detect defects and the exposure of process tools, which is established in the defect inspection control plan design.

Sampling Strategies

In order to verify the quality of products and processes, in-line inspection operations are introduced in the manufacturing process. With this, an early detection of problems can be guaranteed. However, unnecessary inspection operations can have a negative impact on the yield due to long waiting times of lots in front of metrology or inspection tools, which result in delays to take corrective actions [START_REF] Tirkel | In-Line Inspection Impact on Cycle Time and Yield[END_REF]. In addition, some excursions can only be detected at the probing test. Hence, long manufacturing cycle times may have a detrimental eect on yield [START_REF] Leachman | Excursion Yield Loss and Cycle Time Reduction in Semiconductor Manufacturing[END_REF], [START_REF] Wein | Random yield and scrap in a multistage batch manufacturing environment[END_REF]. For all these reasons, sampling strategies are used to nd a trade-o between product yield, costs and cycle time. Several sampling strategies exist and can be classied according to their capability to deal with factory dynamics and variability. An excellent review is presented in [START_REF] Nduhura Munga | Literature Review on Sampling Techniques in Semiconductor Manufacturing[END_REF] where authors propose three categories to classify sampling strategies: Static, Adaptive and Dynamic.

Static sampling is based on rules that do not change throughout production and dierent static sampling strategies exist. Inspecting every constant number of lots arriving at a workstation or selecting a xed number of lots at the beginning of their manufacturing route are the most common strategies used in practice. With these strategies the inspection capacity is allocated in advance via the sampling rate of lots. Since the selected lots are systematically inspected, a limited number of inspection operations are introduced in the manufacturing routes to avoid saturating the inspection capacity. The main advantage of this strategy is that the added defect density can be identied between sequential steps [START_REF] Guldi | In-Line Defect Reduction from a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing[END_REF]. This technique has been widely used in semiconductor manufacturing thanks 2.4. GENERAL DISCUSSION AND THESIS APPROACH 41 to the relative simplicity for implementation. However, with this strategy, the dynamics and variability of the fab cannot be correctly handled [START_REF] Nduhura Munga | Dynamic Management of Controls in Semiconductor Manufacturing[END_REF].

Adaptive Sampling is based on Static Sampling but the sampling rate is adjusted according to the production state [START_REF] Song-Bor | A Capacity-Dependence Dynamic Sampling Strategy[END_REF], [START_REF] Bousetta | Adaptive Sampling Methodology for In-Line Defect Inspection[END_REF], [START_REF] Mouli | Adaptive Sampling Technology -the next step to factory eciency[END_REF]. When a problem occurs, the sampling rate increases in order to inspect more lots and correct the process variations. When process is under control or the risk is not signicant, the sampling rate decreases to better use the inspection capacity. However, managing inspection capacity is more complex due to variations on the workload of metrology and inspection tools during production.

Dynamic Sampling is a strategy that selects the lots in real time. No rule is dened in advance and decisions are taken according to the manufacturing state (e.g. information obtained by inspecting lots, workload of inspection tools, level of risk in the fab.) [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF],

[60], [START_REF] Sun | Method and System for Determining Optimal Wafer Sampling in Real-Time Inline Monitoring and Experimental Design[END_REF]. With this strategy, the workload of metrology and inspection tools is better controlled contrary to the adaptive and static sampling strategies. Table 2.1 summarizes the classication of surveyed papers.

General discussion and thesis approach

The scope of this thesis is the inspection allocation in order to manage the number of Wafers at Risk (W@R) on process tools. The concept of material at risk (MAR) was introduced by Bean [START_REF] Bean | Variation reduction in a wafer fabrication line through inspection optimization[END_REF]. He proposed a model based on probabilities of excursion to allocate inspection operations. First an identication of the risk operations and their probability of excursion is performed. Then, the re-allocation of inspection operations is proposed and the minimum level of material at risk is evaluated in order to compare the gain of re-allocating inspection operations. Their model assumes that there is only one inspection location per defect source. Elliot et al. [START_REF] Elliott | Critical Dimension Sample Planning for Sub-0.25 Micron Processes[END_REF] study the optimal Critical Dimension (CD) sample planning that aims at identifying problems more quickly. The inspection errors I and II are considered. Through data analysis, the systematic and random components of variations between lots, wafers, elds and sites and their baseline distributions is determined and used as inputs for the sample planning model. The work of Chien et al. [START_REF] Chien | A Cost-Based Heuristic for Statistically Determining Sampling Frequency in a Wafer Fab[END_REF] also addressed the CD measurements. The error types I and II are considered, and after inspection two decisions are possible, to accept or to reject the wafer.

A cost-based heuristic for statistically determining the sampling rate is proposed.

Nurani et al. [START_REF] Nurani | Development of an Optimal Sampling Strategy for Wafer Inspection[END_REF] propose a cost-based sampling methodology to allocate inspection capacity. The model aims at specifying the process operations to inspect, the number of lots, the number of wafers within a lot and a percentage area of the wafer. They discuss the possibility of implementing dynamic sampling for deteriorating processes. They point out that the problem is to nd when to schedule inspections and cleans to minimize cost or to maximize the number of good dies. An extension of this work can be found in [START_REF] Gudmundsson | Inspection and metrology capacity allocation in the full production and ramp phases of semiconductor manufacturing[END_REF],

where an analytic model and a genetic algorithm are proposed for inspection allocation in full production and ramp-up phases.

Williams et al. [START_REF] Williams | Optimized Sample Planning for Wafer Defect Inspection[END_REF] propose a cost based sample planning optimization. The inspection cost and the associated excursions costs are considered. Once the inspection sampling plan is close to the theoretical sample plan, the inspection operations are re-allocated to support alternate inspection activities. [START_REF] Purdy | Method for Eciently Managing Metrology Queues[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Rule based Holfeld et al [START_REF] Holfeld | A Fab-Wide APC Sampling Application[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Statistical Su A.J et al [START_REF] Sun | Method and System for Determining Optimal Wafer Sampling in Real-Time Inline Monitoring and Experimental Design[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Mathematical Pfeer et al [START_REF] Pfeer | Predictive sampling approach to dynamically optimize defect density control operations[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Simulation Bettayeb et al [START_REF] Bettayeb | Quality and exposure control in semiconductor manufacturing. part I : Modelling[END_REF] [START_REF]Quality and exposure control in semiconductor manufacturing. part II : Evaluation[END_REF] Non-serial Multi-Stage Error free Dynamic Inspection location Heuristic Nduhura et al [START_REF] Nduhura Munga | Dynamic Management of Controls in Semiconductor Manufacturing[END_REF] Non-serial Multi-Stage Error free Dynamic Risk Calculation Mathematical Nduhura et al [START_REF] Nduhura Munga | A Mathematical Programming Approach for Determining Control plans in Semiconductor Manufacturing[END_REF] Non-serial Multi-Stage Error free Dynamic Key Parameters MIP for sampling Dauzère-Pérès et al [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling, Skipping Mathematical Scheduling Purdy et al [START_REF] Purdy | Dynamic, Weight-Based Sampling Algorithm[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling MILP Hyung [START_REF] Hyung | Advanced process control and optimal sampling in semiconductor manufacturing[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Mathematical Lin et al [START_REF] Lin | Defect Intelligent Sampling System[END_REF] Non-serial Multi-Stage Error free Dynamic Sampling Ruled Based Rodriguez-Verjan et al [START_REF] Rodriguez-Verjan | Skipping algorithms for defect inspection using a dynamic control strategy in semiconductor manufacturing[END_REF] Non developed where results showed a reduction of more than 70% of material at risk compared with previous sampling strategies [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF]. This index can be used to compute the Global Sampling Indicator used in the sampling, skipping and scheduling algorithm proposed by Dauzère-Pérès et al. [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF]. Pfeer et al. [START_REF] Pfeer | Predictive sampling approach to dynamically optimize defect density control operations[END_REF] propose a predictive sampling algorithm, they also conclude that, by using a dynamic sampling strategy, the number of required defect density measurements could be reduced by 67% compared to the previous sampling strategy. Then, Nduhura-Munga et al. [START_REF] Nduhura Munga | A Mathematical Programming Approach for Determining Control plans in Semiconductor Manufacturing[END_REF] propose a mixed integer linear program to calculate key parameters required in Dynamic Sampling. Their model aims at allocating inspection capacity to manage the risk on process tools. Close to this work is the work of Bettayeb et al. [START_REF] Bettayeb | Optimized design of control plans based on risk exposure and resources capabilities[END_REF]. They present an approach to control risk in two stages. The rst stage consist of a minimum allocation of inspection operations that ensures a level of risk during a specic time horizon. In the second stage, additional inspection operations are allocated according to the remaining available capacity of metrology tools. Results show that the pre-allocation of inspection operations based on risk, allows the risk exposure to be balanced among the operations in the process ow. In Bettayeb et al. [START_REF] Bettayeb | Quality and exposure control in semiconductor manufacturing. part I : Modelling[END_REF], an extension of their approach for allocation of inspection operations within the manufacturing route CHAPTER 2. LITERATURE REVIEW ON INSPECTION ALLOCATION of products is presented. Their algorithm provides a predicted quality control plan which aims at managing the risk exposure and quality control eectiveness. Then, in [START_REF]Quality and exposure control in semiconductor manufacturing. part II : Evaluation[END_REF], an evaluation of their model is performed with industrial instances that consider the process tools of two workshops (i.e. 35 process tools). The results provide the maximum exposure that can be expected using the sampling algorithm of [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF]. The proposed approach in this thesis aims at determining whether a set of predened limits of risk exposure on process tools can be achieved with the available inspection capacity and if necessary, the required additional inspection capacity to meet these limits. Rodriguez-Verjan et al. [START_REF] Rodriguez-Verjan | Skipping algorithms for defect inspection using a dynamic control strategy in semiconductor manufacturing[END_REF] present an industrial application of skipping algorithms to eectively manage inspection queues. Concerning the problem of locating inspection operations, Hall et al. [START_REF] Hall | A quality-cost model of in-line inspections for excursion detection and reduction[END_REF] propose a methodology to optimize based on statistical process control (SPC) model for defect excursion monitoring. They use a cost function that considers the power of the inspection, the interval between inspections and the yield impact (costs). This function is optimized for all inspection allocations in a given process ow. The proposed methodology can be used to allocate the inspections based upon the risk of yield excursions and also to estimate a return on investment of inspections. The sampling strategy is Static Sampling and the risk of adding or removing inspection operations in the ow is evaluated with a cost-of-risk function.

Narahari and Khan [START_REF] Narahari | Modeling Re-entrant Manufacturing Systems with Inspections[END_REF] propose an analytical model of a non-serial multi-stage manufacturing system in presence of inspections. Their model aims at predicting the mean steady-state cycle time and throughput based on a Mean Value Analysis (MVA) and under various scheduling policies. They include probabilistic routing after inspections for the cases of accept, reject or rework at some previous stages. Results show that a small number of strategically located inspection stations can perform better than a larger number of poorly located inspections. An extension of their work is presented in Rau and Cho [5].

They propose a mathematical model to optimize the location of inspections and solve it with heuristic methods. Then, Rau and Cho [START_REF] Rau | Genetic algorithm modeling for the inspection allocation in reentrant production systems[END_REF] propose a genetic algorithm to solve the problem of inspection allocations. They compare a complete enumeration method, a heuristic and a genetic algorithm. Solutions obtained with the genetic algorithm give better total prot than solutions obtained with other methods. Shin et al. [START_REF] Shin | Strategic allocation of inspection stations for a ow assembly line: a hybrid procedure[END_REF] study the impact on throughput due to variation in the inspection time. They show that allocating more inspection operations helps to maintain a low bottleneck time. This is actually one of the advantages when selecting the lots dynamically. With more inspection operations, the system is more exible to manage the risk because lots are selected when information is required while satisfying the inspection capacity constraints.

In summary, Dynamic Sampling is considered to be one of the most suitable strategies for modern high-mix semiconductor fabs to increase yield while limiting the impacts on cycle times [START_REF] Nduhura Munga | Literature Review on Sampling Techniques in Semiconductor Manufacturing[END_REF]. Hence, our research work focus on new strategies for dynamic sampling that can be implemented as in [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF]. Moreover, using these strategies, the inspection capacity to be allocated is not known in advance because lots are selected in real time in any of the inspection operations of their manufacturing route. Hence, new models for inspection capacity planning are proposed in chapters 5 and 6, and nally a study concerning the design of defect inspection control plan is performed in chapter 7.

Chapter 3

System Analysis and Evolution Strategy

This chapter introduces the system description and evolution from static sampling strategies (called Start Sampling) to dynamic sampling strategies (called Smart Sampling). Until recently in the site of Rousset of STMicroelectronics the selection of lots to be inspected was only done at the beginning of their manufacturing process and according to xed sampling rates per product. However, static sampling strategies cannot handle the dynamics of the fab (i.e. tool qualications, process ows, lot priorities). In order to reduce the number of wafers at risk on process tools, dynamic sampling has been implemented.

The evolution of the system has been possible thanks to the work of all the participants of the W@R implementation group in ST Rousset and the people of SFL department at EMSE-CMP. 1

Introduction

Inspections are necessary to guarantee the early detection of defective products. However, more inspections do not always result in more quality. When the sampling rate increases, the yield also increases but only until to a certain point. If the sampling rate increases without taking inspection capacity into account, the yield can be negatively impacted due to longer queues of lots waiting for inspection and thus longer delays for corrective actions [START_REF] Tirkel | In-Line Inspection Impact on Cycle Time and Yield[END_REF]. This is why it was decided to implement an eective sampling strategy that reduces the level of material at risk in the fab and considers tool capacity constraints. In this chapter, we present how the sampling strategy has evolved from a static sampling to dynamic sampling in the site of Rousset of STMicroelectronics.

This chapter is organized as follows, section 3.2 presents an analysis of the previous system and the motivation to change from start sampling to dynamic sampling. Section 3.3 describes the dierent phases required for the system evolution. Finally, section 3.4 is devoted to the concluding remarks.

1 Sponsors: P. Campion and M. Le Gall. Leaders: E. Tartière and J. Pinaton.

ST Rousset

• • 1/N N • y- x- t 1 R 1 t 2 R 2 3.2. SYSTEM ANALYSIS 47 W@R covered by Lot L1 (R 1 )
. By observing the wafers at risk in the fab, several cases of overcontrol and lack of control on process tools were found. Figure 3.2 presents the results of the W@R on tools in the same area during 4 weeks. It can be observed that tools 5, 6 and 7 are over controlled because their average W@R levels are well below the expected average W@R level. This means that most of the selected lots to be inspected were processed on these tools. On the other hand, tools 8 and 13 are not suciently controlled.

Figure 3.2: W@R Levels (on industrial data)

In order to reduce those cases of lack of control and over control on process tools, an analysis of the sampling strategies was performed. The objective was to check whether the static sampling (called start sampling) strategy could reduce the W@R on tools above a given limit (i.e. 100 * L) with the current inspection capacity. Data are normalized for condentiality reasons. Experiments were performed using industrial data on the Smart Sampling Scheduling and Skipping Simulator (S5) developed by the EMSE-SFL

. Results

are presented in gure 3.3. The x-axis is the available capacity in the defect inspection area (data are normalized with the value A), the y-axis is the average of the maximum W@R value for all the tools in the fab during one month of production. The red trend (i.e. the rst from the top) is the W@R obtained when static sampling (i.e. start sampling) is used and the blue trend is the W@R obtained when dynamic sampling (i.e. smart sampling) is used. It can be observed that with the same available capacity, the dierence changes from 60% to 24% (i.e. from capacity A to 2,5*A). When the capacity is reduced, the impact on the risk highly increases with static sampling. In other words, if the defect inspection capacity changes due to unexpected events (e.g. breakdowns), the risk increases because the selected lots systematically visit the inspection operations of their routes. They will be directed to the inspection area even if they cannot be inspected. Moreover, lots can be redundant in terms of W@R information because they may have been processed on the same tools.

With dynamic sampling, the system also depends on the defect inspection capacity but is less sensitive to unexpected events. If the capacity changes, the risk will be adapted maximum value of acceptable W@R on the process tool. The Warning Limit (WL) is the limit after which actions have to be taken in order to control the situation. These limits have been calculated taking into account the current defect inspection capacity, the cycle time to reach an inspection operation and the throughput rates of process tools. More details concerning the optimization of control limits can be found in [START_REF] Nduhura Munga | A Mathematical Programming Approach for Determining Control plans in Semiconductor Manufacturing[END_REF]. The system to dispatch the lots that are later inspected is described in gure 3.4. Each time the W@R level is updated, several conditions are tested and the information is gathered and presented with the color code below. • Green : The W@R level is considered as normal. No specic actions are necessary.

• Orange : The W@R level is larger than the Warning Limit (WL). Hence, the operator should load on the process tool a lot that is measurable in the defectivity area. If the lot has been selected in previous process operations it is more suitable to be processed on the tool. Note that the lot can also reduce the risk on several process tools from previous operations, which is dened with the coverage block of inspection operations.

• Blue : The W@R level is larger than the WL, but a lot has already been selected and the results of the inspection are expected.

• Red : The W@R level achieved the Inhibit Limit (IL). Therefore, the situation is critical and the tool is automatically stopped. Once a tool is stopped a Quality Task (QT) is performed. A QT is a special control performed on non-product wafers (NPW), they are used for qualication, testing, stabilization of process performance, tool qualication or other purposes [START_REF] Foster | Simulation of test wafer consumption in a semiconductor facility[END_REF].

Phase III -Dynamic sampling. Due to the dynamics of the fab, when lots are selected in front of process tools, some events cannot be controlled (e.g. selected lots may be stopped, the time to get to the inspection is longer than expected, breakdown of 3.4. CONCLUSIONS 51

Conclusions

In this chapter we described how, in the site of Rousset of STMicroelectronics the sampling system for defect inspection changed from static sampling to dynamic sampling. Figure 3.6 summarizes the implemented applications for dynamic sampling. The dispatching for sampling guides operators in selecting the lots that will later be inspected in defect inspection. This ensures that a process tool that needs to be controlled will process a measurable lot (i.e. a lot for whose recipe exists in defect inspection). Moreover, the W@R reduction of a lot can be enhanced throughout its route until the next defect inspection operation. However, dispatching and sampling eorts can be lost if the arrival rate results in an unbalanced workload of inspection tools. In addition, while a selected lot is waiting for inspection, the production state changes and it may no longer be interesting to inspect this lot. This is why, a skipping mechanism for lots in defect inspection area was implemented.

In summary, dispatching for sampling and smart sampling and skipping are complementary strategies that enable the system to be more eective. Chapter 4

Dynamic Selection of Lots for Defect Inspection

In this chapter a new methodology to manage defect inspection queues is presented 1 . This work is an extension of [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF] and [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF] and is based on their proposed risk indicator (i.e.

Global Sampling Indicator, GSI). The objective is to identify the lots that can be removed from the inspection queue with limited impacts on the global risk of the fab. Signicant industrial results have been obtained by implementating this skipping algorithms 2 .

Introduction

In chapter 3 we presented how the sampling system changed from static sampling to dynamic sampling in the site of Rousset of STMicroelectronics. In this chapter we describe the algorithms used for selecting the lots that can remain in the inspection queue. The proposed approach is a skipping mechanism of lots that are already in the inspection area but can be released from inspection because the production state changed. It is based on the Global Sampling Indicator (GSI) proposed in [START_REF] Dauzère-Pérès | A Smart Sampling Algorithm to Minimize Risk Dynamically[END_REF] and an indicator of Risk Increase (RI) inspired from the Lot Scheduling Indicator (LSI) proposed in [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF]. These indicators are used to identify the impact of inspecting or not a lot or a set of lots on the global risk of the fab.

The chapter is organized as follows: Section 4. 2 Special thanks to Sylvain Housseman for his participation in the industrial implementation of these algorithms. N RV t (S) = min l∈S N RV t,l

S • T • IL t • RV t • G t,l • N RV t,l N RV t,l = RV t -G t
• α: Parameter used to give more or less emphasis on getting as far as possible from Inhibit Limits.

The GSI is calculated as follows:

GSI(S) = T t=1 N RV t (S) IL t α (4.1)
Through simulation, Nduhura-Munga et al. [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF] studied the impact of the parameter α on the performance of the GSI-based sampling algorithms. They observed that satisfactory results are achieved by setting α = 6. We use a Risk Increase (RI ) indicator to evaluate the associated risk of not inspecting a lot or a set of lots. The smaller the value of RI, the less important is the lot or the set of lots. When the RI is calculated for a single lot, it is equal to the LSI (Lot Scheduling Indicator) proposed in [START_REF] Munga | Implementing and optimizing dynamic control plans in semiconductor manufacturing[END_REF]. Let us suppose that there are 3 lots L 1 , L 2 and L 3 in the waiting queue of the defect inspection area. To dene the impact of skipping a single lot, three combinations are evaluated. These combinations are obtained by removing each lot from the initial set of lots (S):

1. GSI(S) = GSI({L 1 , L 2 , L 3 }) 2. RI(L 1 ) = GSI(S \ {L 1 }) -GSI(S) = GSI({L 2 , L 3 }) -GSI({L 1 , L 2 , L 3 }) 3. RI(L 2 ) = GSI(S \ {L 2 }) -GSI(S) = GSI({L 1 , L 3 }) -GSI({L 1 , L 2 , L 3 }) 4. RI(L 3 ) = GSI(S \ {L 3 }) -GSI(S) = GSI({L 1 , L 2 }) -GSI({L 1 , L 2 , L 3 })
When a set of lots is removed simultaneously, the RI is associated to that set of lots and not only to each lot removed independently. For instance, if two lots are going to be removed, the combinations that need to be evaluated are:

1. RI({L 1 , L 2 }) = GSI(S \ S{L 1 , L 2 }) -GSI(S) = GSI(L 3 ) -GSI({L 1 , L 2 , L 3 }). 2. RI({L 2 , L 3 }) = GSI(S \ S{L 2 , L 3 }) -GSI(S) = GSI(L 1 ) -GSI({L 1 , L 2 , L 3 }). 3. RI({L 1 , L 3 }) = GSI(S \ S{L 1 , L 3 }) -GSI(S) = GSI(L 2 ) -GSI({L 1 , L 2 , L 3 }).
A threshold named T M etro is used to decide whether a lot or a set of lots can be skipped.

It can be interpreted as the maximum risk value that can be tolerated for degrading the initial GSI. It can also be seen as the minimum gain in terms of GSI that a lot or a set of lots should bring to remain in the waiting queue.

In order to understand the setting of T M etro , let us consider the GSI of a single tool which Inhibit Limit is 750 wafers. Figure 4.2 shows the GSI values for dierent W@R values and using α = 6. Let us suppose that the current W@R value is near the Inhibit Limit (e.g. 650 wafers). If the T M etro is equal to 0.5 it represents a maximum risk value of 90 wafers that is tolerated to degrade the GSI. If T M etro is equal to 0.3 the GSI can be T M etro is equal to 0.01 the GSI can be degraded by 2.5 wafers. Hence, the smaller the value of T M etro , the more restricted is the system for skipping lots. Aside from the RI indicator to decide if a lot or a set of lots can be skipped, the defect inspection team needs to dene additional rules that can be temporal or permanent in order to focus on measuring a particular group of lots with a given attribute. This information is used to create a subset of lots that can skip the inspection. The next section describes the ve algorithms that we developed for the skipping mechanism.

Skipping Mechanism

This section summarizes the implemented algorithms. The objective is to maximize the number of skipped lots while satisfying the threshold (T M etro ). When equivalent solutions are found in terms of number of lots to skip, the solution that minimizes the impact on the global risk is selected (i.e. min(RI)). The algorithms are listed according to their complexity and their capability to obtain solutions of better quality. Let us consider the following notations:

• S Initial : Set of lots already in the inspection queue,

• S Skippable : Set of lots that are in the inspection queue and can be skipped S Skippable ⊂ S initial . When there are not additional rules for not skipping lots, S Skippable = S Initial ,

• S SkipList : Set of lots identied for skipping, • T M etro : Maximum risk value tolerated for degrading the initial GSI. It can also be seen as the minimum gain in terms of GSI that a lot or a set of lots should bring to remain in the waiting queue.

Algorithm 1 -Identication of Skippable Lots

For each lot l in set S Initial the RI is calculated. Those lots whose RI value is lower than or equal to the threshold T M etro can potentially be skipped. end if 11: end for 12: return S SkipList Note that GSI(S initial ) is calculated considering that all lots in the waiting queue are inspected. Then, the impact of removing a lot is compared to the same initial situation.

Consider an example where, only the lots L 1 and L 2 are in the waiting queue and both reduce the W@R on the same process tools. The evaluation of RI is as follows:

1. RI(L 1 ) = GSI(S initial \ {L 1 }) -GSI(S initial ) = GSI({L 2 }) -GSI({L 1 , L 2 }) 2. RI(L 2 ) = GSI(S initial \ {L 2 }) -GSI(S initial ) = GSI({L 1 }) -GSI({L 1 , L 2 })
When RI(L 1 ) is evaluated, the lot L 2 is in the waiting queue and, by removing L 1 , the GSI is not impacted because the information is obtained with L 2 . When RI(L 2 ) is calculated, the lot L 1 is in the waiting queue, hence by skipping L 2 the GSI is not impacted. If the nal decision of whether to skip or not is taken with this algorithm, both lots (L 1 and L 2 ) would be released. Therefore, the nal decision of skipping lots cannot be taken with this algorithm. However, the list of lots than can potentially skip the inspection operation is reduced. If the RI of a given lot is strictly larger than T M etro , it means that not enough W@R reduction can be obtained with the inspection of the remaining lots.

Algorithm 2 -Local Evaluation

The RI for each lot in the set S Initial is calculated. The decision to skip a lot or not is done immediately after the calculation of the RI. Therefore, once a lot is identied for skipping, it is not considered for the evaluation of the remaining lots. if RI(l) < T M etro then 6:

S * = {S * \ {l}} 7: S SkipList = {S SkipList ∪ {l}} 8:
end if 9: end for 10: return S SkipList Note that the RI of all lots is compared to the same initial situation (GSI (S initial ).

The main dierence between algorithm 1 (Identication of Skippable Lots) and algorithm 2 (Local Evaluation) is that the list of the remaining lots in the waiting queue is updated when a lot is identied for skipping. Let us consider that lots L 1 , L 2 and L 3 are in the waiting queue (S initial = {L 1 , L 2 , L 3 }). Lots L 1 and L 2 reduce the W@R on the same process tools. Then, the evaluation of RI is as follows:

1. RI(L 1 ) = GSI(S initial \ {L 1 }) -GSI(S initial ) = GSI({L 2 , L 3 }) -GSI({L 1 , L 2 , L 3 }).
Since lot L 2 is in the waiting queue lot L 1 is immediately skipped. When the RI of the remaining lots is determined, the L 1 is not considered in the waiting queue.

RI({L

2 , L 1 }) = GSI(S initial \{L 2 , L 1 })-GSI(S initial ) = GSI({L 3 })-GSI({L 1 , L 2 , L 3 }) 3. RI({L 3 , L 1 }) = GSI(S initial \{L 3 , L 1 })-GSI(S initial ) = GSI({L 2 })-GSI({L 1 , L 2 , L 3 })
Since the waiting queue is updated when a lot is identied for skipping, the nal decision can be taken with this algorithm. The drawback is that the quality of the resulting solution depends on the list order. In this example, lot L 1 is evaluated rst and therefore is skipped. If L 2 is evaluated rst, it would be skipped.

SKIPPING MECHANISM

Algorithm 3 -Greedy

The RI for each lot l in set S Initial is calculated. The lot l with the smallest RI is identied and, if RI(l) < T M etro this lot is immediately skipped. Then, the RI of the remaining lots are recalculated. This procedure is performed until the lot with the smallest RI cannot be skipped. is that the lots with smallest RI are skipped rst. Therefore, the order of the list does not inuence the nal solution. Let us consider three lots L 1 , L 2 and L 3 and assume that lots L 1 and L 2 reduce the W@R on the same process tools, but lot L 1 has more information in terms of W@R reduction compared to L 2 . In the rst iteration, all the combinations are evaluated:

1. RI(L 1 ) = GSI(S initial \ {L 1 }) -GSI(S initial ) = GSI({L 2 , L 3 }) -GSI({L 1 , L 2 , L 3 }) 2. RI(L 2 ) = GSI(S initial \ {L 2 }) -GSI(S initial ) = GSI({L 1 , L 3 }) -GSI({L 1 , L 2 , L 3 }) 3. RI(L 3 ) = GSI(S initial \ {L 3 }) -GSI(S initial ) = GSI({L 1 , L 2 }) -GSI({L 1 , L 2 , L 3 })
If the smallest RI is obtained with lot L 2 , it is skipped and the waiting queue is updated.

Therefore, the combinations that are evaluated in the next iteration are the following:

1. RI({L 1 , L 2 }) = GSI(S initial \{L 1 , L 2 })-GSI(S initial ) = GSI({L 3 })-GSI({L 1 , L 2 , L 3 }) 2. RI({L 3 , L 2 }) = GSI(S initial \{L 3 , L 2 })-GSI(S initial ) = GSI({L 1 })-GSI({L 1 , L 2 , L 3 })
With this algorithm, the identication of lots to skip is improved compared to algorithm 2. However, once a lot is skipped, the decision is not reviewed. The objective of the next algorithm is to improve the solutions with a local search. end for 10: until A new lot is added to the S SkipList

11: return S SkipList

Let us consider four lots in the waiting queue, i.e. S Initial = {L 1 , L 2 , L 3 , L 4 } and assume that the greedy algorithm identify lots L 2 and L 3 to skip and the last added lot was L 3 .

The local search procedure tries to replace the previous lots identied for skipping (i.e.

L 2 ). Therefore, the evaluated combinations are:

1. RI({L 1 , L 3 }) = GSI(S initial \{L 1 , L 3 })-GSI(S initial ) = GSI({L 2 , L 4 })-GSI({L 1 , L 2 , L 3 , L 4 }) 2. RI({L 2 , L 3 }) = GSI(S initial \{L 2 , L 3 })-GSI(S initial ) = GSI({L 1 , L 4 })-GSI({L 1 , L 2 , L 3 , L 4 }) 3. RI({L 4 , L 3 }) = GSI(S initial \{L 4 , L 3 })-GSI(S initial ) = GSI({L 1 , L 2 })-GSI({L 1 , L 2 , L 3 , L 4 })
Let us assume that RI({L 4 , L 3 }) < RI({L 2 , L 3 }). Then, lot L 2 is replaced by L 4 and the evaluation restarts with an updated list. Hence, the procedure reevaluates the previous decisions (i.e. L 3 ) and the following combinations are considered:

1. RI({L 4 , L 1 }) = GSI(S initial \{L 4 , L 1 })-GSI(S initial ) = GSI({L 2 , L 3 })-GSI({L 1 , L 2 , L 3 , L 4 }) 2. RI({L 4 , L 2 }) = GSI(S initial \{L 4 , L 2 })-GSI(S initial ) = GSI({L 1 , L 3 })-GSI({L 1 , L 2 , L 3 , L 4 }) 3. RI({L 4 , L 3 }) = GSI(S initial \{L 4 , L 3 })-GSI(S initial ) = GSI({L 1 , L 2 })-GSI({L 1 , L 2 , L 3 , L 4 })
Let us assume that RI({L 4 , L 3 }) has the smallest value. Then, the local search procedure stops, because the last added lot is the same that the one to replace (i.e. L 3 ). Since the set S SkipList changed, the algorithm will try to add a new lot (i.e. a solution with three lots). If a new lot is added, the local search starts again but with the set of three 4.3. SKIPPING MECHANISM 61 lots. If a new lot cannot be added, the algorithm stops. With this algorithm, the solutions obtained from the Greedy can be improved. However, each lot is evaluated individually and dierent solutions can be obtained if sets of lots are considered. The next algorithm aims at nding the best set of lots to skip.

Algorithm 5 -Branch and Bound

The RI is calculated for each lot in S Initial . Lots are sorted by increasing RI and a Branch and Bound method is applied. Bounds consider both the number of lots that can be skipped and the RI of the solution. Let us consider the set of lots S SkipList as the local solution and the set S Solution as the best solution found. A recursive function is implemented to explore the nodes. The index of the evaluated lot in the list S Skippable is expressed with the parameter IndexLot. if S Solution can be improved in terms of number of lots or RI then 7: Explore({S SkipList ∪ {l N extIndex }}, N extIndex, S initial ) 8: else 9:

Stop branching on this node

The handling of a search tree node stops if the solution cannot be improved in terms of number of lots or resulting RI. The number of the remaining lots to evaluate in a node is calculated as the total number of lots in S Initial minus the value of IndexLot (i.e. |S Initial | -IndexLot). Hence, if the number of lots in the local solution (S SkipList ) plus the remaining number of candidate lots is smaller than the number of lots in the best solution (S Solution ) the search stops; because we know that the current solution cannot be improved to contain as many lots as the best known solution. The second condition to stop the branching of a node corresponds to the evaluation of the RI. The gap in terms of number CHAPTER 4. DYNAMIC SELECTION OF LOTS FOR DEFECT INSPECTION of lots between the local solution (S SkipList ) and the best solution (S Solution ) is calculated. If the RI of the local solution (S SkipList ) plus the RI of lots considered in the gap is larger than T M etro , the search on that branch is stopped (i.e. RI(S SkipList ) + indexLot+gap+1 i=indexLot+1 RI(l i ) > T M etro ).

Emergency Mode

In practice, there can be unexpected events (e.g. breakdown of tools) that change the available capacity in defect inspection area. Hence, the total number of lots in the waiting queue cannot be inspected. These versions of the skipping algorithms can be used when the engineer would like to dene the number of lots to skip.

In the previous algorithms, T M etro is considered as a parameter which is used as a to satisfy for the Risk Increase indicator. In the emergency mode, the number of lots to skip is dened in advance and the algorithm identies the set of lots to skip with minimum impact on the overall risk. if S Solution can be improved in terms of number of lots or RI then 7: explore({S SkipList ∪ l}, index(l), S initial ) 8: else 9:

Do not explore the branch In this version of the branch and bound skipping algorithm, the conditions to stop the handling of a search tree node are dierent. The number of the remaining lots to evaluate in a node is calculated as the total number of lots in S Initial minus the value of IndexLot (i.e. |S Initial | -IndexLot). Hence, if the number of lots in the local solution (S SkipList ) plus the remaining lots to explore in a node is smaller than the number of lots to skip, the search tree node stops. If the RI of the local solution (S SkipList ) considering the remaining 4.3. SKIPPING MECHANISM 63 lots of the branch is larger than the RI of the best solution (S Solution ), the search tree node is also stopped.

The section below presents a numerical example of the skipping mechanism. More numerical experiments are presented in section 4.4.

Numerical Example

In the following, we illustrate the proposed algorithms using a numerical example. Let us suppose that there are 5 lots in the defect inspection queue. Table 4.1 shows the W@R reductions that can be obtained with the inspection of each lot. The column W@R represents the current W@R level of process tools. The column NW@R shows the new risk value if the lot is inspected and the column IL gives the value of the Inhibit Limit on the associated process tool. As previously mentioned, a lot can reduce the W@R of several process tools. It depends on the product and the coverage block of the inspection operation. In this example, if lot L1 is inspected, the value of W@R on process tools 07, 08 and 12 is reduced. 4.2 gives the GSI for the initial set of lots and the RI for each lot. Let us consider that T M etro = 0.007. If all lots are inspected, GSI(S initial ) = 0.01159. If lot L1 is removed from the queue, GSI(S initial \ {L1}) = 0.01159 and RI(L1) = 0.000, thus lot L1 can be skipped. This is because, although the W @R on process tools (i.e. Tools 7, 8 and 12) can be reduced by inspecting L1, the W @R on the same tools is also reduced by inspecting other lots that are in the queue (i.e. L3, L4 and L5). If lot L5 is removed from the queue, GSI(S initial \ {L5}) would be 0.002024 and RI(L5) = 0.00865. Since RI(L5) is larger than T M etro , L5 cannot be skipped because it is the only lot that reduces the risk on tools 1, 2, 9 and 10. It is important to note that the RI has been calculated only with one If Algorithm 1 is used to skip lots that have their RI smaller than T M etro , then the nal decision would be to skip lots L1, L2, L3 and L4. However, when the RI of lot L2 is calculated, lots L3 and L5 are in the queue. When the RI of L3 is calculated, lots L1, L2 and L5 are in the queue. Thus, skipping simultaneously all the lots with RI < T M etro can lead to uncontrolled (and thus undesirable) situations. However, with Algorithm 1 we can establish that lot L5 will not be skipped. Therefore, the number of lots to evaluated is reduced, which reduce the number of iterations for the other algorithms. In the following, the mechanism of Algorithm 3 is explained. In each iteration, the lot with the smallest RI is identied. In this example, lot L1 is skipped (i.e. RI(L1) = 0.000) and the RI of the remaining lots is recalculated (See Table 4.3). In the second iteration, lot L2 has the smallest RI (i.e. RI(L2) = 0.002024). Since RI(L2) is smaller than T M etro , lot L2 can be skipped. In the third iteration, the smallest RI is obtained with lot L5 which cannot be skipped because RI(L5) is larger than T M etro . Therefore, the nal decision is to skip lots L1 and L2. Dierent lots may be selected when computing RI for sets of lots rather than evaluating lots individually. Table 4.4 gives the resulting RI when sets of lots are considered. It can be observed that the set of lots {L2, L3, L4} has the smallest RI (0.006673) hence, it can be skipped. Let us note that, compared to the previous solution, lot L1 is not skipped.

The reason is that, when RI(L1) is calculated, lots L3 and L4 are in the queue and if L1 is skipped RI(L3) and RI(L4) increase. When the RI is calculated for sets of lots, it is preferable to keep lot L1 in the queue and to skip lots L3 and L4. Then, evaluating sets of lots for skipping performs better than evaluating each lot individually. The complexity of the problem was not deeply studied due to time considerations. Evidence (calculation time and structure of the problem) let us think that it is a particular instance of a quadratic assignment problem, indicating NP complexity. The decision about which lot should be skipped depends on an underlying location problem. However, a deep study could be interesting. Next section presents the results on industrial instances.

Numerical Results and Discussion

The algorithms were developed with the R software [START_REF]R: A Language and Environment for Statistical Computing, R Foundation for Statistical Computing[END_REF]. The computational experiments in this section compare the eciency of the dierent algorithms on a set of 3 industrial instances. The results of 12 industrial instances are presented in appendix B . Table 4.5 details the results for dierent values of T M etro (0.001, 0.005, 0.01, 0.05 and 0.1). With Algorithm 1 the lots for which RI ≤ T M etro in the rst iteration are identied. As previously mentioned, skipping all those lots can lead to uncontrolled situations. As it can be observed, the resulting RI on all the instances is larger than T M etro . However, the list of lots that can be skipped is reduced, which reduces the number of possible combinations to be evaluated for the other algorithms, and therefore, the calculation times are also reduced.

Algorithm 2 only screens once the list of lots and, each time a lot is identied for skipping, the lot is immediately removed. With this algorithm T M etro is satised. However, it works as a blind search because solutions highly depend on the list order. In nds the best solution only in 42% of the analyzed cases (i.e. 60 scenarios). With algorithm 3 solutions are improved compared with algorithm 2. For example, the solution for instance 1 and T M etro = 0.05 has a larger number of lots and a smaller RI (i.e. 12 lots and RI = 0.04545 T M etro = 0.005, the same number of skipped lots is obtained but the resulting RI is smaller (i.e. 7 lots for skipping with RI = 0.004219). It also nds solutions with more lots while satisfying the parameter T M etro (i.e. Instance 7 with T M etro = 0.005, 8 lots to skip with RI = 0.004317). During manufacturing, the defectivity group may focus on controlling a specic group of lots according to a given attribute (i.e. technology, product, process operation). Hence, a predened set of additional rules (temporal or permanent) are dened. The problem associated to increasing the number of rules is that the number of lots that can be selected by the skipping algorithms is reduced. Figure 4.3 shows the average number of lots identied for skipping with two algorithms (i.e. Algorithms 2 and 5) and when additional rules are considered. In Figure 4.3a there are not additional rules, the only criterion to select lots is the impact on the global risk of the fab. It can be observed that the larger T M etro , the larger the dierence between algorithms 2 and 5. The reason is that more lots can be considered in the set S Skippable hence more combinations are evaluated. When additional rules are considered, the number of lots that can be skipped decreases. In gures 4.3b and 4.3c, two and four additional rules are considered respectively. It can be observed that the dierence between the algorithms is reduced. Hence, the quality of solutions is dominated by the number of rules that are considered. The same conclusions can be drawn for sampling or skipping, when the number of rules increases it is dicult to nd solutions that satisfy all the rules [START_REF] Good | An MILP Approach to Wafer Sampling and Selection[END_REF]. In order to evaluate the emergency mode algorithm (see section 4.3.6), a set of industrial instances were selected, associated to cases where the defect inspection area was saturated.

In the emergency mode, the engineer denes the number of lots to skip and the algorithm CHAPTER 4. DYNAMIC SELECTION OF LOTS FOR DEFECT INSPECTION identies the set of lots with the minimum resulting RI. In order to dene the number of lots to skip, the number of lots that exceed capacity was calculated and four cases were tested. In the rst one, only 30% of the lots exceeding capacity were skipped. In the second case, only 50% of lots were skipped, in the third and fourth cases, the 70% and 100% of lots exceeding capacity were skipped.

(a) Skip 30% of lots exceeding capacity (b) Skip 50% of lots exceeding capacity (c) Skip 70% of lots exceeding capacity (d) Skip 100% of lots exceeding capacity shows the resulting RI and its y-axis on the left side. The second line from the bottom is the number of skipped lots and the bar graph is the resulting number of process tools whose W @R would remain over the W L (i.e. Warning Limit). The axis for both graphs is the y-axis on the right side. Figure 4.4a shows the results when 30% of the lots exceeding capacity are skipped. It can be observed that for the studied instances, between 1 and 9 lots can be skipped without impacting the risk of the fab (i.e. RI = 0.0). Moreover, there are not process tools whose W@R remain over their WL. When 50% of lots exceeding capacity are skipped, the risk is not impacted, except on some instances in which RI = 0, 015, the maximum number of process tools which W @R > W L is 3. The larger the number of skipped lots, the higher is the impact on the risk and the potentially impacted tools.

When 70% of lots exceeding capacity are skipped, the RI varies from 0.02 to 0.04, and the maximum number of process tools whose W @R > W L is 5. Finally, when all the lots

L x L y L x L y
4.6. CONCLUSION AND PERSPECTIVES 71 Figure 4.6 shows the results related to using the automatic selection of lots for skipping during for several weeks. Between 20% and 40% of lots were removed from the inspection queues, allowing the inspection of lots with more relevant information in terms of W@R.

The gains in terms of number of lots to inspect motivated the development of an integrated application that considers the sampling and skipping decisions simultaneously [START_REF] Housseman | Smart dynamic sampling for wafer at risk reduction in semiconductor manufacturing[END_REF].

Conclusion and perspectives

In this chapter we presented a new approach for managing defect inspection queues. The objective is to identify the lots that can skip inspection with limited impacts on the overall risk of the fab. Various skipping algorithms are proposed and evaluated on industrial instances. The Add-Remove and Branch&Bound algorithms (algorithms 4 and 5) give the best solutions compared with the other algorithms. However, the calculation time for algorithm 5 quickly increases with the number of lots to consider. Even-though algorithm 4 does not give in all the cases the optimal solution, 92% of the analyzed cases were solved to optimality. Hence, Algorithm 4 provides a good trade-o between quality of solutions and calculation time when the number of lots to consider increases.

This skipping mechanism has been implemented and is currently being used in the site of Rousset of STMicroelectronics. Gains in terms of a better selection of lots to inspect have been obtained and the work methods changed. Thanks to the new system, between 20% and 40% of lots were removed from inspection with limited impacts on the global risk of the fab. Moreover, because of the implementation of the W@R on process tools and the mechanism to evaluate the pertinence of measuring sets of lots (i.e. by using GSI and RI), the potential impacts of skipping lots or not can now be directly linked to the fab productivity. This can be expressed in terms of saved Quality Tasks (QT) incurred when process tools are stopped.

These encouraging results have motivated the improvement of the application and various research directions have been identied. Sampling and Skipping decisions are interrelated. The sampling of lots depends on the available capacity and the information obtained with lots already in the inspection queue. The skipping decision is inuenced by the arrival of new lots sampled for inspection. Therefore, considering both decisions simultaneously is the next step to improve the selection of lots. Moreover, considering inspection times, instead of number of lots, should help to improve the workload on inspection tools.

Chapter 5

Allocation of Defect Inspection Capacity

With the evolution of the sampling strategy, from static sampling to dynamic sampling, new models are required to estimate the associated inspection capacity. The models proposed in this chapter aim at determining whether a set of predened W@R limits (i.e. Warning limits and Inhibit limits) can be satised and, if not, the additional inspection capacity that is required to keep the W@R on process tools below the limits 1 .

Introduction

With the introduction of dynamic sampling a new model to estimate the required defect inspection capacity is necessary. In this chapter we are interested in the dual problem of [START_REF] Nduhura Munga | Dynamic Management of Controls in Semiconductor Manufacturing[END_REF]. They propose a mixed integer linear program to determine the optimal value of W@R limits on process tools according to a xed inspection capacity. Their model is aggregated and does not consider the details of the manufacturing routes. With the models proposed in this chapter we aim at determining whether a set of predened W@R limits can be satised and, if not, the additional inspection capacity that is required to keep the W@R on process tools below the limits. Our model takes into account all the process operations of the manufacturing routes, the qualications of process and inspection tools, and the design of defect inspection control plans.

The chapter is structured as follows: the problem is detailed in section 5.2. Section 5.3

presents the proposed mathematical model. Sections 5.4 and 5.5 introduce two improved versions of the model that include more industrial details. This chapter ends with a description of the industrial implementation in section 5.6 and the concluding remarks in section 5.7.

Problem Description

When fabs use static sampling to select lots for inspection, the defect inspection capacity is allocated in advance via the sampling rates of lots. The sampled lots are systematically the same sequence of process operations. Figure 5.1 shows a portion of the manufacturing routes for products of technologies "A" and "B". All lots from a product of technology "A" (gure 5.1a) have to be processed on operation 1200 and then go through operations 1210 to 1290. Lots from a product of technology "B" are processed through process operations 1185 to 1280 (gure 5.1b). The process tools that can process lots of a given product are dened through recipe qualications.

• Tool Qualications: The qualication of process tools refers to a kind of setup that assures the right conditions for the process (e.g. right temperature, metal composition, gas pressure). Each process operation is associated with a recipe. The qualication of recipes on several process tools allows the workload to be better allocated. However, not all the process tools of a toolset can be qualied on the same process operations. This is due to technical restrictions (e.g. machine hardware or software restrictions) and also because performing a qualication is costly and time consuming. Therefore, only a limited number of qualications are performed [START_REF] Johnzén | Flexibility Measures for Qualication Management in Wafer Fabs[END_REF], [START_REF] Rowshannahad | Qualication management with batch size constraint[END_REF]. The qualication on inspection tools refers to the set of instructions or control parameters that are necessary to inspect a wafer. Figure 5.1 is a representation of the route of two products from Technologies A and B. The products of both technologies have some common process operations, but the qualications of process tools are dierent. For example, the products of Technology "B" can only be performed on tool 5-1 in process operation 1280. Whereas, for the products of Technology "A", the same process operation 1280 can be performed on two process tools (i.e. Tools 5-1 and 5-2). Concerning the qualication of inspection tools, in our example, the inspection operation 1202 can be performed with a Darkeld tool and the inspection operation 1330 can be performed with a Brighteld tool. Qualications have to be considered in the model because they dene which products can be processed or controlled on which tool throughout the manufacturing route.

• Defect Inspection Control Plan: It denes the position and coverage of defect inspection operations within the manufacturing route (see section 1.3.3). The coverage block refers to the process operations that can be controlled with a given inspection operation. In gure 5.1a the process tools that are qualied to perform operation 1200 can be controlled with lots inspected in inspection operation 1202 of Technology "A". The process tools that are qualied for operations 1210 to 1290 can be controlled with lots inspected in inspection operation 1330 of Technology "A". This implies that, by inspecting one lot, several process tools can be controlled. In addition, process tools can be qualied to perform several operations and thus can be controlled through several inspection operations.

• Product mix and production volumes: The manufacturing route and the defect inspection control plan are dened by product. Hence, the product mixes and the volumes must be considered because they directly aect the resulting W@R on process tools.

• W@R Limits on process tools (i.e. WL and IL): The W@R limits are key parameters to manage the W@R on process tools. WL and IL play dierent roles and co-exist in the dynamic sampling strategy. They dene the maximum number of wafers at risk that is acceptable on each process tool. Hence, with a continuous reduction of W@R limits, the frequency of lots to inspect increases.

Defect Inspection Capacity Planning -Model 1

This section introduces a Linear Program (LP) to calculate the requirements in terms of number of inspections to ensure W@R limits on process tools. The model allocates the production volumes on process tools while taking into account their qualications. Then, the number of inspections that need to be performed on a process tool is calculated as the total processed volume divided by the warning limit. Using this information, the model determines where to allocate inspections and how many to allocate considering the predened control plans. Process tools are modeled individually because qualications and W@R limits are dened for each process tool (see gure 5.1). Inspection tools are modeled by type because all inspection tools of the same type are identical. This assumption is valid since the type refers to the detection capability and inspection technology (e.g. darkeld, brighteld).

In order to estimate the capacity required for W@R, an initial percentage of capacity is reserved. If it is not enough, additional capacity will be required. In this version of the model it is supposed that, once a lot is inspected, the W@R on the process tools that were covered is set to zero. R k : Reserved Capacity for W @R measures on inspection tool type k.

Decision Variables

X i p,t : Production volume of product i processed on tool t in process operation p, Y i c,p,t : Number of inspections of product i in inspection operation c, that covers process tool t of process operation p, Z i c : Total number of inspections performed in inspection operation c of product i, A k : Additional capacity required for inspection tool type k.

The objective is to minimize the additional defect inspection capacity required to satisfy the Warning Limits on process tools.

min k A k s.t. t X i p,t • hh i p,t = h i p • V i ∀i, p (5.1) i,c,p Y i c,p,t i,p X i p,t W L t ∀t (5.2)
Y i c,p,t X i p,t • hh i p,t ∀i, c, p, t (5.3)
Z i c t Y i c,p,t • hh i p,t ∀i, c, p (5.4)
A k + R k i,c Z i c • b i c,k ∀k (5.5) X i p,t 0 ∀i, p, t (5.6)
Y i c,p,t 0 ∀i, c, p, t (5.7)
Z i c 0 ∀i, c (5.8)
A k 0 ∀k (5.9) Constraints (5.1) dene how the volume of product i is processed among tools t that are qualied for process operation p. The equality sign in this constraint is important, since we want to check how a given product mix (quantities of each product) covers the risk on process tools. If an inequality sign was used, the model could articially produce more than required of some products to cover the risk on process tools.

Constraints (5.2) express the requirements in terms of number of inspections for process tool t. This number is calculated as the total volume processed on tool t divided by its W L t . Constraints (5.3) ensure that the number of lots inspected for process tool t cannot be larger than the total number of lots processed on tool t. Constraints (5.4) consider the coverage block of an inspection operation. They dene how the total number of inspections performed at inspection operation c are assigned to control the process tools which are covered. These constraints are not summed over p because, by inspecting one lot, the process operations p where the lot was processed can be covered (if they belong to the coverage block of inspection operation c). The number of inspections performed in inspection operation c of product i is not known in advance and is dened through the optimization. Constraints (5.4) are actually the linearization of:

Z c i = max i, c,p ( t Y i c,p,t • hh i p,t ) Constraints (5.5)
calculate the total number of inspections allocated to each inspection tool type k and dene the additional capacity required on inspection tool k when reserved capacity R k is not enough. Decision variables should be integer. However, the model is resolved for industrial instances with the manufacturing routes and defect inspection control plans of 10 technologies. This corresponds to 1800 process operations, 170 inspection operations and more than 700 process tools. Moreover, since this model is used to support decisions at the tactical level, using continuous variables is enough to relevant satisfactory results in a reasonable time.

Defect Inspection Capacity Planning -Model 2

In this model, the exposure of process tools is considered. The exposure refers to the number of wafers processed on a tool before the results of inspection are obtained. When a process tool is controlled with the inspection of a production lot, the time before obtaining the results of the inspection must be considered. This time corresponds to the cycle time (CT) between the process operation p and the inspection operation c. It depends on the manufacturing route of the product and it is calculated considering the intermediate process operations that must be performed before the lot reaches the defect inspection operation. This is illustrated in gure 5.1a. If tool 7-1 at process operation 1210 is controlled with a lot

CT × T H W D i c,p p c i p Y i c,p,t e i c,p c i i,c,p Y i c,t • e i c,p • hh i p,t i,c,p W D i c,p • Y i c,t • e i c,p • hh i p,t + i,p X i p,t W L t ∀t W D i c,p p c i T C × T H

Modied Decision Variables

Y i c,t : Number of inspections of product i in inspection operation c that covers process tool t,

The new model is given below:

min k A k s.t. t X i p,t • hh i p,t = h i p • V i ∀i, p (5.10) i,c Y i c,t • ( p e
i c,p • hh i p,t • W L t - p e i c,p • hh i p,t • W D i c, p ) i,p X i p,t ∀t (5.11)
Y i c,t p X i p,t • hh i p,t • e i c,p ∀i, c, t (5.12)
Z i c t Y i c,t • hh i p,t • e i c,p ∀i, c, p (5.13)
A k + R k c,i Z i c • b i c,k ∀k (5.14) X i p,t 0 ∀i, p, t (5.15)
Y i c,t 0 ∀i, c, t (5.16)
Z i c 0 ∀i, c (5.17)
A k 0 ∀k (5.18) The problem of the model at its present form is that the selected term of constraints (5.11) can be negative when the average number of wafers between process operations and inspection operation is larger than the Warning Limit.

i,c

Y i c,t • ( p e i c,p • hh i p,t • W L t - p e i c,p • hh i p,t • W D i c,p ) i,p X i p,t ∀t
In order to tackle this situation, two considerations have been taken into account: the planned quality task (i.e. ScQT t ), they are not fully coordinated with the W@R controls, hence, when a planned QT is performed, the W@R level on the process tool is not necessarily at the maximum acceptable level (IL). Therefore, the W@R reduction that can be obtained is modeled as a percentage of the IL (i.e. ρ t ).

QT t + ρ t • ScQt t + i,c,p Y i c,t • e i c,p • hh i p,t i,c,p W D i c,p • Y i c,t • e i c,p • hh i p,t + i,p X i p,t IL t ∀t (5.19)
In the previous models, we have considered that all the production volume can be inspected. However, a technology is composed of dierent types of products with the same route but not with the same defect inspection control plan (see section 1.3.3). Hence, there is only a percentage of the production volume of each technology that is measurable. This is included with the parameter γ i .

Concerning the total defect inspection capacity, it is shared between two sampling strategies: Dynamic sampling and static sampling. Lots selected with static sampling are systematically inspected in all inspection operations dened as mandatory in their defect inspection control plan. This is included with the parameter SS i , that gives the predened sampling rate of product i and the parameter ob i c represents the set of mandatory inspec- tions operations for product i. Moreover, the inspection time depends on the technology and the qualied inspection tool. For example, a Brighteld tool is slower than a Darkeld tool but can detect more types of defects. In consequence, the capacity is considered in terms of time. Finally, there are some inspection tools that are preferably used for some types of inspections other than W@R (e.g. Static sampling), therefore a penalty per inspection tool type (Def P k ) was introduced.

New Parameters

QT P : Penalty associated to the total number of additional QTs performed, The model is given below:

min k Def P k • A k + QT P • T imeQT • t QT t s.t. t X i p,t • hh i p,t = h i p • V i ∀i, p (5.20)
i,c

Y i c,t • ( p e i c,p • hh i p,t • IL t - p e i c,p • hh i p,t • W D i c,p )+ QT t • IL t + ρ t • ScQt t • IL t • i,p X i p,t ∀t (5.21) Y i c,t p e i c,p • hh i p,t • X i p,t • γ i ∀i, c, t (5.22)
Z i c + α • V i • SS i • ob i c t Y i c,t • e i c,p • hh i p,t ∀i, c, p (5.23)
A k + R k i,c Z i c • b i c,k • T imeD0 i c ∀k (5.24)
A k + R k + c,i V i • SS i • ob i c • b i c,k • T imeD0 i c CapaM ax k ∀k (5.25) X i p,t 0 ∀i, p, t (5.26)
Y i c,t 0 ∀i, c, t (5.27)
Z i c 0 ∀i, c (5.28)
A k 0 ∀k

(5.29)
Constraints (5.20) are the same as constraints (5.1). Constraints (5.21) express how the number of inspections Y i c,t for process tool t reduces the level of risk taking into account the number of wafers between the process operation p and the control operation c (i.e. W D i c,p ). These constraints also consider the number of QTs that should be performed on tool t when inspections with production lots are not enough to satisfy the Inhibit Limit (I L t ). Constraints (5.22) ensure that the number of inspections on process tool t cannot be larger than the total number of measurable lots processed on t. Constraints (5.23) dene the coverage block of an inspection operation by stating how the inspections performed on inspection operation c are assigned to the process tools that are covered. These constraints are not summed over p because, by inspecting one lot, all the process operations p where the lot was processed can be covered (if they belong to the coverage block of inspection operation c). The number of controls for dynamic sampling performed in inspection operation c of product i is not known in advance and is dened through the optimization. Constraints (5.23) are the linearization of:

Z c i = max i,c,p ( t Y i c,t • e i c,p • hh i p,t -α • V i • SS i • ob i c )
Constraints (5.24) assign the total number of inspections on each inspection tool k and dene the additional capacity required on inspection tool k when the reserved capacity R k for W@R measures is not enough. This constraint also includes the capacity used for inspections of lots selected with the static sampling strategy. Since this model includes more industrial aspects, we added constraints (5.25), which ensure that the total inspection capacity allocated is smaller than the maximal capacity per inspection tool k. Hence, if the total required capacity per inspection tool k is larger than the maximal (C apaM ax k ) the model allocates additional QTs. When the model is used to analyze the inspection capacity increases (i.e. decisions at the strategic level), this constraint can be ignored or

CapaM ax k increased.

Industrial Implementation

The data preparation is performed with R. The information of manufacturing routes, defect inspection control plans, tools qualications, planned QTs, processing times and W@R limits are extracted from the data base. The defectivity engineer prepare the dierent scenarios with the information of mix and volume of products to consider. Figure 5.4

shows the general scheme of the application. Introduction

In the proposed model, the capacity allocated with dynamic sampling is divided into two categories: (i) Reserved capacity (R k ) and (ii) Additional capacity (A k ). R k is a percentage of the available capacity dedicated for dynamic sampling. If the reserved capacity is not enough to satisfy the inspection requirements additional capacity will be allocated. Therefore, the model proposed in chapter 5 aims at minimizing the total additional capacity required per inspection tool types. Section 6.2 presents the results obtained with the capacity model version 1 (proposed in section 5.3). Since it is not possible to solve the second model without including additional parameters, we then only present in section 6.3 the results obtained with the model version 3 (proposed in section 5.5). Finally the concluding remarks and future work are presented in section 6.4.

Experiments on capacity model version 1

Numerical experiments on the model proposed in section 5.3 are presented. In this version of the model, the average number of wafers between the process operation p and the inspection operation c of product i is not considered (i.e (W D i c,p )), hence, the W@R on process tools can be set to zero with the inspection of a production lot. The inspection time is similar for all lots and the considered capacity is only for the dynamic sampling strategy. Other type of sampling strategies are not explicitly included. We considered more R k y -axis

x -axis 6.2. EXPERIMENTS ON CAPACITY MODEL VERSION 1 89 requirements. Even if the total volume considered increases, the required capacity for W@R inspections is reduced. The reason is that the defect inspection control plan of the new product in group 11 has more inspection operations for which the coverage block is larger. Consequently, with the inspection of one lot more process tools can be covered.

Impact of Mix and Volume of Products

Table 6.1 presents the total required capacity with dierent product mixes and the value of the W@R limits when the experiments were conducted. To satisfy the W@R limits on process tools with product Mix 1, it is necessary to reserve 30.7% of the total defect inspection capacity, which represents 16.0% of T1 capacity, 10.0% of T2 capacity and 4.7% of T3 capacity. These results help to anticipate the qualication of inspection tools. The required capacity among inspection tool types is not balanced. Inspection capacity on T1 is the most required while inspection capacity on T3 is the less required. The main reason is that T1 is qualied on more inspection operations than the other tool types. However, for Mix 5, T2 is slightly more required than T1. The reason is that some inspection operations qualied on T2 can have similar W@R reduction than some inspection operations qualied on T1. Hence, these inspection operations are chosen when solving the model. The total required capacity with Mix 4 and Mix 7 is very close (46.9% and 46.3%) but the balance among inspection tool types changes. In particular, the capacity required on T1 decreases from 22.6% with Mix 4 to 17.0% with Mix 7 and the capacity required on T2 increase from 16.7% to 19.0%. The reason is that the manufacturing route of each technology is dierent. Therefore, the position, number and qualication of inspection operations are also dierent. 6.2 presents the results obtained when the W@R limits change. The objective is to check whether W@R limit targets can be achieved. The total required capacity in Mix 4 and Mix 7 is similar (59.7% and 59.3%) and the requirement among inspection tool types is also similar (32.7% to 31.7% for T1, 19.6% to 19.8% for T2 and 7.4% to 7.8% for T3) contrary to Table 6.1. With these new limits, more lots are selected and the inspection CHAPTER 6. EXPERIMENTS ON THE CAPACITY MODEL operations where lots are sampled are also dierent. This explains why the balance on the capacity requirements among inspection tool types can change when W@R limits change.

Moreover, the results illustrate the impact of the defect inspection control plan design over the defect inspection allocation. For example, with the previous W@R limits and product mix 5 (Table 6.1) the capacity allocated on T2 is larger than T1, because with the defect inspection control plan conguration, it was possible to choose between inspection operations qualied on T1 and T2. However, when limits are more restricted (Table 6.2), both inspection tool types are chosen at the same time. This is the reason why T1 is the most used in all mixes. In this version of the model when a production lot is inspected the W@R drops to zero, i.e. the average number of wafers between process operation p and inspection operations c of product i, W D i c,p is not included. Considering this parameter, the decisions regarding the selection of inspection operations and therefore the allocated inspection capacity change.

Experiments on capacity Model Version 3

This version of the model includes the average number of wafers between process operations and inspection operations (W D i c,p ), the QTs that need to be performed if the W@R level reaches the IL, the planned QTs and the capacity allocated to the dierent sampling strategies: (i) Static sampling and (ii) Dynamic sampling. We tested scenarios in which the utilization of QTs are allowed and scenarios in which QTs are highly restricted. Also, the preference for an inspection tool type can be set via a specic penalty (i.e. Def P k ).

For these experiments, a new inspection tool has been considered because new inspection operations were created and an additional tool qualied.

If the problem is feasible and limits can be satised, solving the model shows the utilization rate per inspection tool type (i.e. Total allocated time/ Total capacity in terms of time) and estimates the additional required QTs. If limits cannot be satised, the potentially uncovered process tools are listed with the estimated number of additional QTs. The sets of W@R limits presented in We consider that the time to perform a QT is as long as the time to perform the longest inspection operation of a production lot. When there is no restriction for using a particular tool type (i.e. Scenario 7), the utilization rates of T1 and T4 are 100%. Let us note that the utilization rates due to lots selected with start sampling are already 70.4% on T1 and 62.8 % on T4. Hence, it is easier to achieve 100% of utilization compared with T2 and T3. If there is a restriction on using an inspection tool type the estimated number of QTs can increase in the solution of the model (i.e. scenarios from 8 to 10). Restricting the use of T1 will generate more QTs than restricting the use of T4 (i.e. scenario 8 with 303 QTs and scenario 9 with 361 QTs).

M 70% M 75% M 80% M 90% 3 × M 90% 3 × M 90% 3 × M 90% 3 × M 100% 7 × M 100% 7 × M 100% 7 × M 100% 7×M
The reason is that T1 is qualied on more inspection operations than T4. The number of additional QTs generated vary according to the inspection tool type that is restricted.

The number of QTs is reduce from 361 in scenario 9 to 354 in scenario 10. The reason is that with the restriction of T1 and T2, the utilization rate of T2 and T3 increases. In this set of experiments, we aim at studying the impact of the W@R reduction that can be obtained with lots selected with the static sampling strategy. For this, we use the parameter alpha. This parameter expresses the percentage of lots selected with static sampling that can reduce the W@R to its minimum level (i.e. resulting W@R is CT ×T H).

Table 6.9 gives the other parameters. The results are presented in table 6.10. For these experiments, the utilization of additional QTs are highly restricted. When the percentage of lots from static sampling that reduce the W@R increases the resulting utilization rate is reduced. However, having all lots from static sampling that reduce the W@R levels to its minimum level, implies that these lots will need to be dispatched on the tools that need to be controlled. Moreover these lots should have a high priority to reduce the waiting times on intermediate process operations and to ensure that the maximum W@R reduction can be obtained. However, the scheduling of lots in each process area is already complex and having an additional criterion to accelerate all the lots selected for static sampling would increase the complexity. With the dispatching for sampling application (see section 3.3), the operators can identify when it is necessary to process a measurable lot on a process tool that needs to be controlled. That is why, scenarios with an alpha between 0.2 and 0.5 were representative of the fab activity.

Def P k R k Def P k R k Def P k R k Def P k R k R k Def P k R k Def P k R k Def P k Def P k
all the product mixes that were evaluated, most of the W@R limits on process tools can be satised. However, there are some process tools with limits that cannot be satised and thus additional QTs are necessary. Using this information, defect inspection engineers can anticipate the required modications in the defect inspection control plan to stay within the W@R limits on the process tools. Moreover, if new inspection operations cannot be created, QTs associated with violated W@R control limits are estimated.

Impact of W@R limit reduction

In this section, we analyze the impact of reducing the W@R limits. Experiments have been divided in two dierent cases:

1. The group of W@R limits B, C, D and E are evaluated with dierent product mixes, only the lots dynamically selected are considered and a capacity of 20% is reserved in advance (i.e R k ) on all inspection tool types. The objective of the rst case is to analyze the additional requirements only for dynamic sampling.

2. Lots selected with both sampling strategies (static sampling and dynamic sampling) are considered. Concerning the set of limits for the second case, we consider all the inspection operations that can cover each process tool, and then reduce the IL of each process tool to its minimum exposure (min T C × T H). The new value of the Inhibit Limit is set 10% larger than the minimum exposure.

In the following, the limits reductions in the rst case are presented. The values for the other parameters are summarized in table 6.12. Table 6.12: Parameters for evaluating W@R limit reductions

Parameters

Product Mixes Mix1, Mix2, Mix3, Mix4, Mix5, Mix6 Limits B, C, D, E

Def P k [1,1,1,1] QT P 10 R k

20%

Table 6.13 shows the utilization rates required only with lots dynamically selected and the set B of W@R limits. There is no restriction for using a particular inspection tool (i.e. Def P k =[1,1,1,1]). In the rst set of W@R limit reductions, from limits B (table 6.13) to limits C (table 6.14), the impact in terms of utilization rates is similar and the additional number of QTs does not change. Hence, it is possible to reduce the limits with is that, the time to get the inspection results from inspection 1330 is too long to avoid the W@R of process tool 8-4 to reach the IL. Hence this process tool will be controlled with QTs.

Conclusions

In this chapter, numerical experiments conducted with industrial data on the models for defect inspection capacity planning were presented and discussed. The model is used as a decision support tool to help answering the main question: Is it possible or not to satisfy a given set of W@R limits under dierent scenarios? the approach takes into account the design of control plans, the qualications of process and inspection tools, the mix and volumes of products and the W@R limits. The approach can be used at dierent decision levels:

• At the tactical level, it helps anticipating the impact of product mix changes on the required defect inspection capacity, but also dening the objectives in terms of feasible reductions of W@R limits.

• At the strategic level, it can support decisions on the capacity increase of the defect inspection workshop.

Since reductions of W@R levels highly depend on the defect inspection control plans, the system depends on the product mix. Therefore, situations in which W@R limits are ensured may change if the product mix changes. Quality tasks are special controls performed on process tools when the W@R levels reaches Inhibit Limit. When quality tasks are necessary, even if inspection capacity is available, it means that the W@R limits of all the process tools cannot be satised only with the inspection of production lots. In the next chapter, a rst study on how the defect inspection control plans design can impact the W@R level on process tools is presented.

Chapter 7

Impact of Control Plan Design on Tool Risk Management

In this chapter 1 , we aim at analyzing how the position and coverage of inspection operations may inuence the manufacturing robustness from the point of view of the risk on tools (i.e.

W@R). This study was performed with the simulation tool S5 2 developed by the EMSE-SFL department 3 . Results show that not only the number and position of inspection operations impact the risk on tools, but also how each inspection operation covers process operations.

The chapter concludes with the proposition of a mathematical model for the inspection operation location and allocation problem.

Introduction

In the previous chapters we analyzed the inspection capacity allocation problem based on predened defect inspection control plans. Let us recall that a defect inspection control plan, corresponds to the position and coverage of inspection operations within the manufacturing route (see Section 1.3.3). Control plans and sampling strategies are highly related. However, few methods link risk analyses and actual control plan design in a detailed manner [START_REF] Bettayeb | Optimized design of control plans based on risk exposure and resources capabilities[END_REF]. In this chapter we aim at analyzing the impact of control plan design on the overall Wafers at Risk of the fab.

The chapter is structured as follows. Section 7.2 introduces the problem. Section This chapter focuses on how the defect inspection control plan can impact the W@R levels in the fab. As shown in previous chapters, the W@R on process tools is inuenced by the throughput of process tools and the time to get the inspection results. Figure 7.1 illustrates the minimum W@R (i.e. exposure) on a process tool with two dierent defect inspection control plans. In order to reduce the exposure of process tool 1 two factors can be managed (i.e. reduced): (1) The throughput of the process tool, but this would not be acceptable from a productivity point of view or (2) the delay to get the inspection results. Hence, a new inspection operation is introduced which enables the delay to get the inspection results to be reduced. In this study, we analyze how the conguration of new control plans can have a positive or negative eect on the W@R levels.

Experimental Results

Experiments were conducted on industrial data, and the instances we use correspond to the activity of the fab during one month of production, i.e. they include more than 700 production tools. The experiments were conducted at the beginning of the thesis, hence the only available sampling strategy was Static Sampling (i.e. Start Sampling).

For condentiality reasons, all results are normalized. The selected indicator is the max W@R average, which refers to the average of the maximum Wafers at Risk level for each process tool in the fab. All performance measures are compared with historical data, which correspond to the results obtained with the static sampling strategy in the fab.

Therefore, the column static Sampling is set to 100% and results with the dynamic sampling strategy are compared with the use of a static sampling strategy. Dierent capacity values for the defect inspection area are considered. Capacity A corresponds to the available capacity when the experiments were conducted. Capacities A2, A3, A4 and A5 correspond to a reduced number of inspection tools. Innite Capacity, refers to the case where all measurable lots are inspected, it represents a lower bound for W@R levels that can be achieved with each conguration.

Table 7.1 presents the results of max W@R averages with dierent congurations of defect inspection control plans. Results for X+20 and X+50 correspond to defect inspection control plans with 20 and 50 new inspection operations. These new inspection operations cover the same process operations than the initial defect inspection control plan. Results

for capacity A and the original defect inspection control plan (i.e. X inspection operations)

show the large gains that can be obtained by only changing the sampling strategy. The maximum W@R average is reduced from 100% with static sampling to 72.6% with dynamic 106CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT sampling. Results obtained when the capacity is reduced (i.e. A4 and A5) show that the maximum W@R average can increase when considering additional inspection operations and no overlapping (155.2% and 104.2% with X+50 inspection operations respectively).

The reason is that without overlapping, the coverage block of an inspection operation is reduced. As illustrated in gure 7.2, with the original defect inspection control plan, the inspection operation D0_1 validates six process operations and, with an additional inspection operation D0_2 (without overlapping) it only validates three process operations.

This dierence between overlapping and no overlapping is detailed in table 7.2. In the case of capacity A5, we observe that an additional reduction on W@R is obtained when overlapping is considered, 3.2% and 15.0% with X+20 and X+50 respectively. Therefore, when the number of inspection operations increases and the capacity is reduced, the inuence of the overlapping of inspection operations becomes more important. of defect inspection control plans with X+20 and X+50 inspection operations. The new inspection operations are included with dierent positions within the manufacturing route and all of them with overlapping. In conguration 1, the throughput of process tools are considered but no in an exhaustive way. In particular, some inspection operations are placed near process tools with high throughput, which leads to a reduction on the maximum W@R levels for these process tools and better results compared with the other congurations. In conguration 2, the throughput is not considered, hence the W@R levels are degraded compared to the other congurations, which reects that inspecting a lot would not be ecient enough in terms of W@R reduction. These results show that 108CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT Results with innite capacity show that, when new process operations are covered, the impact of additional inspection operations is signicant. The maximum W@R average decreases from 57.7% with the original defect inspection control plan (X inspection operations) to 26.2% with a defect inspection control plan of X+20 inspection operations.

Therefore, when capacity is increased, the factor that enables the reduction of W@R is the number of inspection operations. When capacity is reduced (i.e. case of capacity A4), overlapping is an important factor that helps to reduce the overall W@R. The maximum W@R average obtained with the original defect inspection control plan is 95.4%, compared with a maximum W@R average of 102.7% without overlapping and 89.1% with overlapping.

Mathematical Model for the Location and Allocation Problem

In this section, a model is proposed to optimize the location of inspection operations within the manufacturing routes of products. The model is based on the inspection capacity allocation model proposed in chapter 5.

The following sets are used to write the model: CapaM ax k : Total capacity of inspection tool k, calculated in terms of total number of inspections that can be performed on k, X i p,t : Production volume of product i processed on tool t in process operation p, γ : Penalty for the lost in the process tool availability due to a Quality Task performed on process tool t.

I : Set of
The following variables are used in the model: The main objective of our model is to determine the right number and the locations of inspection operations to minimize the exposure in terms of W @R on process tools. A

U i c : Decision of creating an inspection operation, =    1 if inspection operation c of product i is created 0 otherwise. Z 1
QT is performed on tool t if there is no inspection operations that can be located. Since a process tool is stopped while a QT is performed, the exposure is considered as the number of wafers that cannot be produced (W DQT t ). min i,c,p,t

W D i c,p • Y i c,t + γ • t W DQT t • QT t s.t. i,c,p U i c • e i c,p • hh i p,t + QT t 1 ∀{t ∈ T |W D i c,p IL t } (7.1) Y i c,t p e i c,p • hh i p,t • X i p,t ∀i, c, t (7.2)
QT t • IL t + i,c,p Y i c,t • (IL t • e i c,p • hh i p,t -e i c,p • hh i p,t • W D i c,p ) i,p X i p,t ∀t (7.3) U i c • Z i c t Y i c,t • hh i p,t • e i c,p ∀i, c, p (7.4
) (U i c = 1). Constraints (7.5) ensures that the total number of inspections performed for inspection operation c is lower than or equal to the capacity of inspection tool k. This model is not linear because of the term U i c • Z i c in constraints (7.4) and (7.5). To linearize our model, we dene a the new variable below:

CapaM ax k c,i U i c • Z i c • b i c,k ∀k (7.5) Y i c,t 0 ∀i, c, p (7.6)
Z i c 0 ∀i, c (7.7)
U i c ∈ {0, 1} ∀i, c (7.8
λ i,c = U i c • Z i c (7.9)
A set of constraints are included in the model to replace the non-linear term, where M is a big number:

λ i,c M • U i c ∀i, c (7.10) CapaM ax k c,i λ i,c • b i c,k ∀k (7.11)
In constraints (7.10), if the inspection operation c of product i is not created (U i c = 0) λ i,c is equal to zero. When the inspection operation is created (U i c = 1), the variable λ i,c can take any value smaller than M but not larger than the total capacity of inspection tool k. The later condition is veried with constraints (7.11). Therefore, the nal model is as follows:

min i,c,p,t W D i c,p • Y i c,t + γ • t W DQT t • QT t s.t. i,c,p U c,i • e i c,p • hh i p,t + QT t 1 ∀{t ∈ T |W D i c,p IL t } (7.12) Y i c,t p e i c,p • hh i p,t • X i p,t ∀i, c, t (7.13) QT t • IL t + i,c,p Y i c,t • (IL t • e i c,p • hh i p,t -e i c,p • hh i p,t • W D i c,p ) i,p X i p,t ∀t (7.14) λ i,c t Y i c,t • hh i p,t • e i c,p ∀i, c, p (7.15
)

CapaM ax k c,i λ i,c • b i c,k ∀k (7.16) λ i,c M • U i c ∀i, c (7.17)
λ i,c 0 ∀i, c, t

(7.18) U c,i ∈ {0, 1} ∀c, i (7.19)
112CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT

Conclusion and perspectives

In this chapter we analyze the impact of defect inspection control plans on the W@R of process tools. Experiments were performed on industrial instances with the simulation tool S5 developed by EMSE-SFL. The results showed that more inspection operations in the defect inspection control plan do not always reduce the overall W@R. The W@R reduction highly depends on the position of inspection operations and how they cover process operations. Moreover, when inspection capacity is reduced, the overlapping of inspection operations can enhance the W@R reduction. When inspection capacity is increased, the number of inspection operations is a key factor to consider. The chapter concludes with a mathematical model to optimize the location of new inspection operations within the manufacturing route. Our perspectives include the implementation and the validation of the proposed model.

General Conclusion and Perspectives

General Conclusion

This thesis was conducted within the framework of a joint collaboration between industrial and academics. We have faced the problem of how to eciently manage and reduce the risk on process tools. The notion of risk considered in this thesis refers to the number of Wafers at Risk (W@R) on process tools regarding defect inspection operations, which corresponds to the number of wafers that are potentially impacted if a problem occurs.

Hence, by limiting the W@R on process tools, the impact of excursions can be better controlled. Sampling strategies are used to nd a trade-o on the number of inspections.

More inspections lead to high product yields, and thus reduced costs for scraps and reworks, while fewer inspections lead to lower cycle times, and thus reduced production cost.

When a static sampling strategy is used, several factors related to the dynamics of the fab cannot be handled resulting in cases of over-control or lack of control on process tools.

Therefore, the sampling system for defect inspection has changed from a static sampling to a dynamic sampling strategy in the site of Rousset of STMicroelectronics. In a dynamic sampling strategy, lots are selected in real time and according to the information that can be obtained by inspecting sampled lots. Results showed that dynamic sampling strategies are more suitable for modern fabs to stay competitive by increasing yield through an ecient selection of lots to sample.

An application that dynamically selects the lots for inspection was developed. It is based on a skipping mechanism that aims at identifying the lots that can be released from inspection due to redundant information in terms of W@R. This mechanism helps to avoid inspections without added value for reducing the W@R of process tools. The W@R management highly depends on the product mix. Therefore, situations were W@R limits are satised may change if the product mix changes. In order to anticipate the production changes that directly aect W@R management, a model that optimizes the inspection capacity allocation was proposed. It takes into account the key factors that inuence the W@R on process tools (e.g. manufacturing routes, tools qualications, W@R limits, product mix, defect inspection control plans). It helps to identify the capacity required in the defect inspection workshop to satisfy the W@R limits on process tools.

When these limits cannot be satised, the model gives an estimation of the additional inspection capacity that is required and the potentially uncovered tools. Results showed that not always more inspections means less risk, since the W@R reduction highly depends 114CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT on the position of inspection operations within the manufacturing routes of products and how inspection operations cover process operations. Important savings were obtained with the industrial implementation of the system, not only in terms of overall W@R reduction but also in terms of number of measurements, thanks to a better selection of lots to inspect.

Industrial Results

In the following, the industrial results obtained after the implementation of the W@R and dynamic sampling are discussed. The evolution of the system has been possible thanks to the collaborative work of all the participant of the W@R Implementation group 4 . Special thanks to the people who are in charge of the W@R defectivity project in the site of Rousset of STMicroelectronics: Eric Tartière and Jacques Pinaton, whose commitment and daily work guarantee the good performance of the system.

Table 7.5 presents the key metrics one year after the implementation of the various components of the project. A scrap reduction of 11% has been obtained thanks to the early detection of excursions. The scheduled Quality Tasks (QTs) were reduced by 15% thanks to the systematic control of production lots that is assured with the W@R limits. shows the average value of the IL in the fab, which has been reduced by 66% since the beginning of the project.

Scrap Reduction 11%

Average W@R Inhibit Limit Reduction 66%

Quality Task (QT) Reduction 15%

Fab deployment (Covered process tools) 100%

4 Sponsors: P. Campion and M. Le Gall. Leaders: E. Tartière and J. Pinaton. A second perspective concerns the extension of W@R to other type of controls such as metrology. Several dierences between defectivity inspection and metrology need to be considered. The objective of metrology is to control the physical and electrical properties of the wafers during fabrication. Hence, metrology steps are dened according to the property to control (e.g. Thickness, critical dimension, uniformity, electrical tests). A rst challenge concerning the extension to metrology is to dene the context in order to develop the W@R counters. Due to the sensibility of the product several W@R counters would be required on the same process tool. An additional dierence is that the physical locations of metrology tools need to be considered. Contrary to defect inspection tools that are located in a single workshop, the metrology tools are located in dierent areas of the fab.

ST Rousset

An additional perspective concerns the optimisation of the number and location of inspection operations. The optimisation problem can be seen as a maximal covering location problem, where the clients are the process tools that need to be controlled. The demands of clients are the requirements in terms of lots to inspect. Selecting a facility corresponds to selecting an inspection operation to allocate and the distance between a site and client is the average number of wafers between the process operations and the inspection operations. • SPC: Statistical Process Control, it is based on statistical tools to ensure the stability of the process.

• VM: Virtual Metrology, it is a control technique that aims to predict metrology measurements and forecast electrical and physical parameters on the wafer.

• Wafer: Slice of silicon used to manufacture semiconductor devices.

• W@R: Wafers at Risk, it is the number of wafers produced on a tool since the process date of the latest inspected lot.

• WL: Warning Limit, it is a limit after which actions have to be taken in order to control a lot that can reduce the W@R level on a process tool.

• Yield: It is the number of good produced units (e.g. wafers, dies, etc) over the total produced units. It is one of the most important metrics to evaluate the eciency of a fab.

Appendix B Experimental Results

Skipping Experimentation Abstract :

In semiconductor manufacturing, several types of controls are required to ensure the quality of final products. In this thesis, we focus on defect inspections, which aim at monitoring the process for defect reduction and yield improvement. We are interested in managing and reducing the risk on process tools (i.e. number of wafers at risk) during fabrication. To reduce this risk, inspection operations are performed on products. However, because inspection operations directly impact the cycle times of products, sampling strategies are used to reduce the number of inspected lots while satisfying quality objectives. Several sampling techniques exist and can be classified according to their capability to deal with factory dynamics. Dynamic sampling strategies have recently been proposed, in which lots to inspect are selected in real time while considering the current production risk. These strategies are much more efficient than previous strategies but more complex to design and implement. In this thesis, a novel approach to select the lots to inspect is proposed. Multiple algorithms have been proposed and validated to efficiently manage the defect inspection queues by skipping (i.e. releasing) lots that do no longer bring enough information. In order to support strategic and tactical decisions, an optimization model for defect inspection capacity planning is also proposed. This model calculates the required defect inspection capacity to ensure the risk limits on process tools when the production conditions change. Industrial results show significant improvements in terms of risk reduction without increasing defect inspection capacity.

Résumé :

Dans les processus de fabrication de semi-conducteurs, différents types des contrôles existent pour maîtriser les procédés et garantir la qualité du produit final. Ces travaux de thèse s'intéressent aux contrôles de défectivité qui visent à maîtriser le risque sur les équipements de production. L'indicateur utilisé est le nombre de produits traités par un équipement depuis la date du dernier produit contrôlé. On s'intéresse à la maîtrise et la réduction du risque sur les équipements de production. Pour cela, différentes stratégies de sélection des lots existent et peuvent être classifiées selon leur capacité à intégrer la dynamique d'une unité de fabrication. Dans les stratégies de sélection dynamique, les lots sont contrôlés en temps réel et en optimisant un critère. Ces stratégies sont récentes et sont beaucoup plus efficaces que les stratégies précédentes, mais aussi plus complexe à mettre en oeuvre. Dans ce cadre, nous avons proposé et validé industriellement différents algorithmes pour identifier les lots à relâcher (à ne pas contrôler) dans les files d'attente des lots en défectivité. Nous avons aussi développé et implémenté un modèle d'optimisation de la capacité pour l'atelier de défectivité, qui permet d'évaluer l'impact de paramètres critiques (e.g. plan de production, positions des opérations de contrôles dans la gamme de fabrication, valeurs des limites de risques) dans la gestion du risque global de l'unité de fabrication.

Figure 3 :

 3 Figure 3: Exemples de motifs et de signatures des défauts

6 Chapter 0 .

 60 Résumé en français opérations d'inspection peuvent être eectuées (1202 et 1330), si un lot de la technologie "A" est inspecté dans l'opération d'inspection 1202, l'équipement de production tool 8-4 peut être contrôlé. Si un lot est inspecté à l'opération d'inspection 1330, les équipements de production qui ont traité le lot entre les opérations de production 1210 et 1290 sont contrôlés. Par conséquent, avec l'inspection d'un lot, plusieurs équipements de fabrication peuvent être contrôlés. En outre, si un lot d'un produit de la technologie "B" est inspecté à l'opération d'inspection 1330, les équipements de production qui ont traité le lot entre les opérations 1185 et 1280 sont contrôlés. C'est à dire que le bloc de couverture de l'opération d'inspection 1330 est diérent entre les produits de la technologie "A" et "B". De plus, lorsqu'une nouvelle opération d'inspection est mise en place, une recette 2 d'inspection doit être créée. La complexité pour créer une recette d'inspection augmente quand le nombre des paramètres à considérer augmente. Le nombre de paramètres augmente parce que les technologies pour détecter les défauts sont de plus en plus avancées et aussi parce que la conception des produits est plus complexe. Par conséquent, un nombre limité d'opérations d'inspection sont créées

Figure 1 .

 1 8 est une représentation de la problématique des stratégies statiques. Dans cet exemple, un sur deux lots sont sélectionnés pour être inspectés en défectivité. Dans la gure 1.8, les lots L2, L4 et L6 sont sélectionnés pour être inspectés et les lots L1, L3 et L5 ne seront pas inspectés. Si les lots sont fabriqués selon la disponibilité des équipements de fabrication et que le lot L1 est traité dans la machine 1, le lot L2 sera traité dans la machine 2, le lot L3 sera assigné à la machine 1 et le lot L2 sera traité par la machine 2 et ainsi de suite. Il est donc possible que tous les lots qui ont été sélectionnés pour l'inspection soient passés seulement dans la machine 2. Il résulte de cette situation que la machine 2 est sur-contrôlée et que la machine 1 n'est pas susamment contrôlée. Cet exemple nous permet de constater quelques désavantages des stratégies statiques pour contrôler tous les équipements de production. Par ailleurs, la complexité augmente quand plusieurs produits sont pris en considération car le plan de contrôle et les taux d'échantillonnage sont diérents entre les produits. Pour ces raisons, la stratégie d'échantillonnage a évolué vers une stratégie dynamique. Dans le cadre de cette 2 La recette d'une opération d'inspection contient les paramètres nécessaires pour pouvoir eectuer l'inspection, comme par exemple : la conguration des signaux et de paramètres optiques.

• Algorithme 2 (

 2 Évaluation locale): Pour chaque lot dans la liste initiale S Initial , le RI est calculé, et lorsque RI(L) T M etro le lot L est retiré immédiatement. Par conséquent, le RI des lots restant dans la le d'attente prendra en compte tous les lots retirés antérieurement. • Algorithme 3 (Greedy): Pour chaque lot de la liste initiale S Initial le RI est calculé. Si le min L∈S (RI) est inférieur à T M etro le lot est retiré de la liste. Ensuite, le RI des lots restants est recalculé. Cette procédure continue jusqu'à ce que le lot avec le plus petit RI ne peut plus être retiré. • Algorithme 4 (Add/Remouve): Cet algorithme est basé sur l'algorithme 3 (Greedy), mais les solutions sont améliorées grâce à une procédure de recherche locale d'ajout et suppression. • Algorithme 5 (Branch & Bound): Le RI des lots dans la liste S Initial sont calculés et les lots sont ordonnés selon RI croissant. Une méthode de recherche arborescente est utilisée pour trouver le meilleur ensemble de lots à retirer de la liste initiale. Les conditions d'évaluation considèrent le nombre de lots et le RI résultant. • Méthode d'urgence: Les 5 premiers algorithmes considèrent la valeur de T M etro comme une donnée d'entrée. Dans cette version d'urgence, on considère que le nombre des lots à retirer est connu en avance et le résultat obtenu est l'ensemble des lots avec le plus petit RI. Cette version peut être utilisée quand il y a des événements inattendus comme un changement dans la capacité d'inspection (e.g. Arrêts ou pannes des équipements d'inspection.). Les algorithmes ont été développés avec le logiciel R [13] et ils ont été testés avec des instances industrielles. Les résultats obtenus avec les diérents algorithmes sont présentés et analysés en détail dans le chapitre 4 de la thèse. Les résultats ont montré qu'avec l'algorithme 2 le T M etro est respecté, mais les solutions dépendent de l'ordre d'évaluation des lots. Seulement dans 42% de cas (60 scénarios) la meilleure solution est trouvée. L'algorithme 3 trouve la meilleure solution dans 82% des cas. Les résultats ne dépendent pas de l'ordre d'évaluation des lots en raison du fait qu'à chaque itération le lot avec le plus petit RI est retiré. Ensuite, le RI des lots restants est recalculé. Avec l'algorithme 4, les décisions sont améliorées grâce à la procédure d'ajout et suppression. La meilleure solution est trouvée dans 92% des cas analysés avec cet algorithme. L'algorithme 5 trouve les solutions optimales, avec le même nombre de lots à retirer le RI résultant est plus petit, ou encore, des solutions avec plus de lots identiés pour être retirés et en respectant la contrainte de T M etro sont trouvés. Par contre, le temps de calcul peut augmenter considérablement quand le nombre des lots à évaluer augmente. Par conséquent, l'algorithme 4 reste un bon compromis entre qualité des solutions et temps de calcul.

I

  : Ensemble des produits indexés avec i, P : Ensemble des opérations de production indexés avec p, C : Ensemble des opérations d'inspection indexés avec c, K : Ensemble des types d'équipements d'inspection indexés avec k, T : Ensemble des équipements de production indexés avec t.V i : Volume total de production du produit i, IL t : Limite maximale de W@R sur l'équipement de production t, h i p : Gammes de fabrication, =1 si le produit i est traité dans l'opération de production p, 0 sinon. hh i p,t : Qualication des équipements de production, 'équipement de production t est qualié pour traiter le produit i dans l'opération de production p, 0 sinon. b i c,k : Qualication des équipements d'inspection k dans l'opération d'inspection c, 'opération d'inspection c du produit i est qualié sur le type d'équipement d'inspection k, 0 sinon. R k : Capacité réservée pour les inspections W @R eectuées dans le type d'équipement d'inspection k. W D i c,p : Nombre de wafers à risque entre l'opération de production p et l'opération d'inspection c du produit i. Cette valeur est calculée comme T C × T H (voir gure 11), e i c,p : Bloc de couverture de l'opération d'inspection c du produit i, 'opération d'inspection c du produit i couvre les équipements de production qualiés dans l'opération de production p, 0 sinon.

Figure 1 . 2 :

 12 Figure 1.2: Operational Description of the Defectivity Area

  which depend on the product (e.g. Phases of integration, maturity, design).

  -serial Multi-Stage Error free Dynamic Skipping Heuristic and B&B B&B = Branch and Bound, EA = Evolutionary Algorithm, EM = Enumeration Method, NLP = Non Linear Programming, AT = Analytic Technique, ILP = Integer Linear Programming, GA = Genetic Algorithm, MIP = Mixed Integer Programming.

  Team: A. Thieullen, G. Rodriguez-Verjan, P. Palouar, S. Detivaud, B. Pennachio, J.C. Mattlin, F. Chairat, C. Klingelschmidt, V. Lemaire, J. De-selle, D. Courilleau, B. Mari, C. Giuliani, D. Viard. EMSE-CMP SFL Team: S. Dauzère-Pérès, C. Yugma, J.L. Rouveyrol, S. Housseman.

2

  EMSE-SFL: École de Mines de St-Etienne, Département Science de la Fabrication et Logistique 100 * L 3.3. SYSTEM EVOLUTION 49

Figure 3 . 4 :

 34 Figure 3.4: Flow diagram of the dispatching for sampling system

Figure 3 . 6 :

 36 Figure 3.6: Implemented applications for dynamic sampling

  3 presents the developed algorithms to skip lots that are already in the waiting queue. The decision to skip a lot or a set of lots is taken by checking whether inspecting a lot do not reduce the global risk, or if lots have redundant information compared with other lots in the waiting queue. Numerical experiments on industrial instances are presented and discussed in section 4.4. The industrial implementation of the skipping mechanism is discussed in section 4.5. Finally, concluding remarks and perspectives are presented in section 4.6 . 1 Part of this chapter was published in the 9th International Conference on Modeling and Analysis of Semiconductor Manufacturing (included in the 2013 Winter Simulation Conference)[START_REF] Rodriguez-Verjan | Skipping algorithms for defect inspection using a dynamic control strategy in semiconductor manufacturing[END_REF]

Figure 4 . 2 :

 42 Figure 4.2: Impact of dierentT M etro values

4. 3 . SKIPPING MECHANISM 57 •

 357 S * : Set of lots remaining in the inspection queue, S * = {S Initial \ S SkipList } ,

Algorithm 1

 1 Identication of Skippable Lots 1: S * = S initial 2: S SkipList = ∅ 3: for each lot l ∈ S initial do 4: RI(l) = GSI(S initial \ {l}) -GSI(S initial ) 5: end for 6: for each lot l ∈ S initial do 7: if RI(l) < T M etro then 8: S * = {S * \ {l}} 9: S SkipList = {S SkipList ∪ {l}} 10:

Algorithm 2 Local Evaluation 1 :

 1 S * = S initial 2: S SkipList = ∅ 3: for each lot l ∈ S initial do 4: RI(l) = GSI(S * \ {l}) -GSI(S initial ) 5:

59

 59

Algorithm 3 Greedy 1 :

 1 S * = S initial 2: S SkipList = ∅ 3: l = arg min RI{S * } 4: while RI(l ) < T M etro do 5: S * = {S * \ {l }} 6: S SkipList = {S SkipList ∪ {l }} 7: for each lot l ∈ S * do 8: RI(l) = GSI(S * \ {l}) -GSI(S initial ) min RI{S * } 11: end while 12: return S SkipListThe main dierence between algorithm 2 (Local Evaluation) and algorithm 3 (Greedy)

CHAPTER 4 .Algorithm 4

 44 DYNAMIC SELECTION OF LOTS FOR DEFECT INSPECTION 4.3.4 Algorithm 4 -Add-Remove This algorithm is based on the Greedy algorithm. Once the solution obtained with Greedy a local search is performed. Each lot of the solution (S SkipList ) is removed from the list and all the candidates (S * ) are evaluated to replace it. If the lot with the smallest RI is dierent from the lot that was removed, the procedure restarts with the modied list. The procedure stops when the list (S SkipList ) is not modied and when a new lot cannot be added. Add-Remove 1: S * = S initial 2: S SkipList = Algorithm3(S initial ) l ∈ S SkipList do 5: remove l from S SkipList and replace it with k=arg min RI{S * \ S Skiplist } 6:if k = l then 7:Restart evaluation with an updated list of S SkipList and S *

Algorithm 5

 5 Branch & Bound 1: Order the set of lots S initial by increasing RI 2: S Solution = ∅ 3: RI(S Solution ) = T M etro + 1 4: Explore(S Solution , 0, S Initial ) 5: return S Solution Function Explore (S SkipList , IndexLot, S Initial ) 1: Evaluation of S SkipList 2: if S SkipList is better than S Solution then 3: S Solution = S SkipList 4: nb Solution = |S SkipList | 5: for NextIndex=IndexLot+1 until |S SkipList | do 6:

Algorithm 6

 6 Branch & Bound Emergency Mode 1: Order the set of lots S initial by increasing RI 2: S Solution = ∅ 3: RI(S Solution ) = 999999 4: Explore(S Solution , 0, S Initial ) 5: return S Solution Function Explore (S SkipList , IndexLot, S Initial ) 1: Evaluation of S Solution 2: if S SkipList is better than S Solution then 3: S Solution = S SkipList 4: nb Solution = |S SkipList | 5: for each lot l in the subset S Initial from indexLot until last lot of S Initial do 6:

Figure 4 . 3 :

 43 Figure 4.3: Average number of skipped lots with algorithm 2 and 5

Figure 4 . 4 :

 44 Figure 4.4: Resulting RI for Emergency Mode Algorithm

Figure 4 .

 4 Figure 4.5 shows the results for the dierent instances. The rst line from the bottom

SetsI:

  Set of products indexed by i, P : Set of process operations indexed by p, C : Set of inspection operations indexed by c, K : Set of inspection tools type indexed by k, T : Set of process tools indexed by t. Parameters V i : Total production volume of product i, W L t : Warning Limit of process tool t, IL t : Inhibit Limit of process tool t, h i p : Product route,=1 if product i is processed on process operation p, : Qualication of process tools, = 1 if process tool t is qualied to process product i on process operation p, 0 otherwise. b i c,k : Qualication of inspection tool k on inspection operation c, = 1 if the inspection operation c of product i is qualied on inspection tool type k, 0 otherwise.

80 CHAPTER 5 .

 805 ALLOCATION OF DEFECT INSPECTION CAPACITY e i c,p : Coverage block of inspection operation c of product i, inspection operation c of product i covers the tools of process operation p, 0 otherwise.

  c is mandatory for product i 0 Otherwise SS i : Static sampling rate for product i, Def P k : Factor to express a restriction to use the defect inspection tool k for W@R measures, α : Percentage of mandatory inspections that also reduce the W@R on process tools,γ i :Percentage of volume of product i that is measurable, T imeQT : Inspection time of a QT, T imeD0 i c : Inspection time of product i on inspection operation c, CapaM ax k : Total capacity of inspection tool k given in time, ScQt t : Number of QTs that are scheduled on tool t, ρ t : W@R reduction considered for the planned QTs on process tools, New Decision variables QT t : Number of additional QTs performed on process tool t.

7 . 3 is

 73 devoted to the experimental study and analysis of results. Section 7.4 presents the formulation of a mathematical model for the location and allocation problem. Finally, conclusions and perspectives are discussed in Section 7.5. 1 Part of this chapter was published in the 7th International Conference on Modeling and Analysis of Semiconductor Manufacturing (included in the 2011 Winter Simulation Conference)[START_REF] Rodriguez-Verjan | Impact of Control Plan Design on Tool Risk Management: A Simulation Study in Semiconductor Manufacturing[END_REF]

Figure 7 . 1 :

 71 Figure 7.1: Illustration of minimal W@R

Figure 7 .

 7 2 is a representation of both strategies to include more inspection operations. With the "Overlapping" strategy, the coverage of the original defect inspection control plan is maintained and additional inspection operations are included.Therefore, the impact of the original defect inspection control plan is conserved. With the "No Overlapping" strategy, the coverage of each inspection operation is reduced, hence the number of process operations that are covered is divided by the number of inspection operations. Results on industrial instances are presented in the next section.

Figure 7 . 2 :

 72 Figure 7.2: Defect inspection control plans with and without overlapping

  e i c,p : Coverage block of inspection operation c in product i, inspection operation c of product i covers the tools of process operation p, 0 otherwise. b i c,k : Qualication of inspection tool k in inspection operation c of product i, inspection operation c of product i is qualied on inspection tool k 0 otherwise.

Figures 7 .

 7 Figures 7.4 present the resulting W@R on process tools from the same area. Each boxplot represents the value of the W@R on each process tool. The cases of lack of control and over control on process tools were reduced. The number of wafers potentially impacted if a problem occurs are limited with the Inhibit Limit (IL) of each process tool. Figure7.5

  Team: A. Thieullen, G. Rodriguez-Verjan, P. Palouar, S. Detivaud, B. Pennachio, J.C. Mattlin, F. Chairat, C. Klingelschmidt, V. Lemaire, J. De-selle, D. Courilleau, B. Mari, C. Giuliani, D. Viard. EMSE-CMP SFL Team: S. Dauzère-Pérès, C. Yugma, J.L. Rouveyrol, S. Housseman.116CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT

•

  S5: Smart Sampling, Skipping and Scheduling Simulator. It is a simulator developed by the department SFL (Science de la Fabrication et Logistique) of the Ecole de Mines de St Etienne, Microelectronic Center of Provence. It is used to compare dierent sampling strategies for defect inspection and based on historical data.

1

  Fabrication des circuits intégrés . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Représentation de traitement Front-End . . . . . . . . . . . . . . . . . . . 3 3 Exemples de motifs et de signatures des défauts . . . . . . . . . . . . . . . 4 4 Technologies de détection Brighteld et Darkeld . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Désavantages des stratégies statiques . . . . . . . . . . . . . . . . . . . . . 7 7 Compteur W@R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Rapport de W@R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter of a process tool . . . . . . . . . . . . . . . . . . . . . . . . 'industrie de semi-conducteurs est considérée comme une des industries les plus importantes dans l'économie moderne. Actuellement, la plupart des produits utilisés dans notre vie quotidienne contiennent des circuits intégrés (ICs Integrated Circuits en anglais)

				5
	5	Example de gammes de fabrication pour les produits des technologies "A"
		et "B.	33
	1.6	Representation of a defect inspection control plan and coverage block . . .	34
	1.7	Evaluation of the minimal number of wafers at risk on a process tool . . .	36
	1.8	Drawback of Static Sampling	. . . . . . . . . . . . . . . . . . . . . . . . .	37
	3.1	W@R 46
	3.2	W@R Levels (on industrial data) . . . . . . . . . . . . . . . . . . . . . . .	47
	3.3	Average of maximum W@R obtained with static sampling vs. dynamic
		sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	3.4	Flow diagram of the dispatching for sampling system . . . . . . . . . . . .	49
	3.5	Report of process tools with W@R levels close to their IL . . . . . . . . . .	50
	3.6	Implemented applications for dynamic sampling . . . . . . . . . . . . . . .	51
	4.1

9 9 Description générale des applications utilisées pour la sélection dynamique des lots à STMicroelectronics, Rousset . . . . . . . . . . . . . . . . . . . . 10 10 Résultats de l'implémentation industrielle . . . . . . . . . . . . . . . . . . 13 11 Réduction du W@R avec de lots de production et de QT (Tâche de qualité) 14 12 Schéma général du modèle de capacité . . . . . . . . . . . . . . . . . . . . 18 13 Exemple de la couverture du plan de contrôle original et modication de la couverture avec l'introduction d'une nouvelle opération d'inspection . . . . 19 14 W@R sur les équipements de production avant et aprés l'évolution du système de sélection des lots . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 15 Déploiement et réduction des limites maximales des risque (IL) des équipements de production dans l'unité de fabrication (fab). . . . . . . . . . . . . . . . . 21 1.1 Schematic representation of the Wafer Processing . . . . . . . . . . . . . . 27 1.2 Operational description of the defectivity area . . . . . . . . . . . . . . . . 30 1.3 Examples of defect signatures . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4 Examples of defect patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.5 Defect inspection techniques . . . . . . . . . . . . . . . . . . . . . . . . . Wafers at risk evolution on process tool 1 . . . . . . . . . . . . . . . . . . . 54 4.2 Impact of dierentT M etro values . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3 Average number of skipped lots with algorithm 2 and 5 . . . . . . . . . . . Introduction L

  Lorsque le RI du lot L 1 est calculé, le lot L 2 est considéré dans la le d'attente et inversement pour le calcul de RI du lot L 2 . Si les deux lots ont des informations redondantes (i.e. ils réduisent le risque des mêmes équipements) leur RI peut être inférieur au T M etro et, par conséquent, être retirés simultanément de la le d'attente.

	Pour cette raison, l'algorithme 1 est utilisé pour le pré-traitement mais pas pour
	prendre la décision nale.

  Les détails des expérimentations et les résultats sont présentés dans le chapitre 6 de la thèse. Ce modèle permet d'anticiper l'impact des diérents scénarios sur la maîtrise des risques des équipements de production. C'est un outil d'aide à la décision qui répond à diérentes questions aux niveaux tactique et stratégique. Au niveau tactique, il permet de déterminer si les objectifs en termes de réduction des limites W@R peuvent être atteint avec la capacité actuelle de défectivité. De plus, il permet d'évaluer l'impact que les changements de mix et volume de production peuvent avoir sur la maîtrise du risque des équipements de production. Les résultats montrent que lorsque les QTs sont utilisées, même s'il y a de la capacité disponible en défectivité, une revue du plan de contrôle est souhaitable, car la position des opérations de contrôle ne permet pas de garantir entièrement les limites de risque. De plus, les changements de mix et volume de production peuvent entrainer des situations dont les limites de W@R ne sont plus garanties, car les plans de contrôle de défectivité sont dénis par produit. Au niveau stratégique, les questions concernant l'augmentation de la capacité peuvent être aussi analysées. Étude de la conception des plans de contrôle pour la défectivité Le W@R des équipements de production peut être réduit avec l'introduction de nou-

	20		Chapter 0. Résumé en français
	la nouvelle opération d'inspection D0_2 couvrira les opérations de production Op6 à Op8.
	C'est-à-dire qu'avec "No overlapping" le nombre des opérations de production qui sont
	couvertes est divisé par le nombre d'inspections introduites. Avec la stratégie "Overlap-
	ping", la couverture du plan de contrôle original est maintenue et les nouvelles opérations
	velles opérations d'inspection. Cette section correspond au chapitre 7 de la thèse. Dans sont incluses avec leur couverture. Dans la gure 13c la couverture de l'opération D0_1
	cette section, on s'intéresse à la manière dont la position et la couverture des opérations est maintenue (i.e. les opérations de production Op6 à Op11 sont couvertes) et la nouvelle
	d'inspection du plan de contrôle de défectivité impacte la maîtrise des risques. Cette étude opération D0_2 est introduite avec la couverture des opérations de production Op6 à Op8.
	a été eectué à l'aide du simulateur S5 développé par le département de Sciences de la Les expérimentations ont été faites avec les données industrielles correspondant à un mois
	fabrication et logistique (SFL) de l'École Nationale Supérieure des Mines de St-Étienne d'activité. Les résultats sont présentés et détaillés dans le chapitre 7 de la thèse. Les
	(ENSM-SE). L'objectif a été d'analyser comment l'introduction de nouvelles opérations résultat ont montré que lorsque la capacité d'inspection est limitée, la stratégie "Over-
	d'inspection peut avoir un impact positif ou négatif sur la maîtrise du risque global de lapping" permet d'avoir un meilleur impact sur la réduction de risque qu'avec la stratégie
	l'unité de fabrication (fab). Deux stratégies de couverture des opérations de production "No overlapping". De plus, quand les nouvelles opérations d'inspection couvrent des nou-
	ont été considérées au moment d'introduire les nouvelles opérations d'inspection: "Over-velles opérations de production, l'impact sur la réduction du risque est plus signicatif.
	lapping" et "No overlapping" (voir la gure 13). Le chapitre se termine avec la proposition d'un modèle mathématique pour optimiser le
	nombre et le positionnement des opérations d'inspection.
	Implémentation industrielle
	0.4	Conclusions et perspectives
	Avec l'implémentation du système de sélection dynamique des lots pour la défectivité, une
	meilleure maîtrise du risque a été possible. Les résultats industriels montrent l'ecacité
	du système. L'implémentation industrielle a été possible grâce au travail collectif des tous
	les participants du projet W@R
		(a) Couverture du plan de	(b) "No Overlapping"	(c) "Overlapping"
		contrôle original
	Figure 13: Exemple de la couverture du plan de contrôle original et modication de la
	couverture avec l'introduction d'une nouvelle opération d'inspection
		La gure 13 présente un exemple du plan de contrôle et de couverture des opérations
	d'inspection. Dans le plan de contrôle original (gure 13a) l'opération d'inspection D0_1
	couvre les opérations de production du Op6 au Op11. Une nouvelle opération d'inspection
	est introduite. Si la stratégie "No Overlapping" est utilisée pour introduire une nouvelle
	opération d'inspection (gure 13b) la couverture de l'opération initiale (D0_1) sera ré-
	duite, l'opération d'inspection D0_1 couvrira les opérations de production Op9 à Op11 et

24 dénissent le nombre total d'inspections allouées à chaque type d'équipement d'inspection k. Ces contraintes considèrent la capacité nécessaire pour l'inspection des lots sélectionnés avec les stratégies dynamique et statique. Les contraintes 5.25 assurent que la capacité allouée soit inférieure à la capacité maximale par type d'équipement d'inspection. Chapter 0. Résumé en français La gure 12 présente un schéma du modèle de capacité. L'information concernant les gammes de fabrication, les plans de contrôle de défectivité, la qualication des équipements de production et inspection, les QTs planiés par équipement de production et les limites de W@R sont obtenus à partir de la base des données. Un pré-traitement des données est fait avec le logiciel R et la résolution est faite avec les solveurs GLPK ou CPLEX. L'ingénieur prépare les diérents scénarios avec l'information du mix et volume de production à considérer. Le modèle donne comme résultats: la capacité nécessaire par type d'équipement d'inspection, les équipements de production dont les limites peuvent être garantis ou non et le nombre potentiel des QTs générées pour respecter les limites W@R.

Figure 12: Schéma général du modèle de capacité 0.3.3

Table 1 .

 1 1: Measurement tools classication[START_REF] Quirk | Semiconductor Manufacturing technology[END_REF]

	1.3. PROCESS CONTROL IN SEMICONDUCTOR MANUFACTURING	29
	Category Measurement Description
		System
	Stand-Alone	O-line	Available only outside fab (i.e. Laboratory)
	Tools	At-line	Available in the fab (measure monitor wafers
			that are destructive, contaminated of unpatterned
		In-line	Used during production (can measure patterned wafers)
	Integrated	On-line	Available at the process workstation to measure
	Tools		patterned wafers
		In-situ	Measure wafer, process or equipment during processing
			(real-time measurement)

Table 2 .

 2

		1: Classication of models for inspection allocation
	Article	Model	Inspection Sampling Decisions	Solution
		Conguration	Error	Strategy		Approach
	Raz et Kaspi [62]	Serial Multi-Stage	I and II	Static	Inspection Location	NLP and B&B
	Chien et al[63]	Serial Multi-Stage	I and II	Static	Sampling rate	Heuristic
	Shiau [54]	Serial Multi-Stage	I and II	Static	Inspection Location	EM and Heuristic
	Kakade et al [64]	Serial Multi-Stage	Error free	Dynamic	Inspection rate	SA and B&B
	Van Volsem et al[50]	Serial Multi-Stage	I and II	Static	Location, Sampling rate EA and Simulation
					and inspection limits
	Vaghe et al [65]	Non-serial Multi-Stage Error free	Static	Inspection Location	Analytical and
						Simulation
	Naharani et Khan [53]	Non-serial Multi-Stage Error free	Static	Inspection location	AT and Simulation
	Nurani et al [66]	Non-serial Multi-Stage I and II	Static	Sampling	Statistical
	Nurani et al [4]	Non-serial Multi-Stage I and II	Static	Sampling	Heuristic
	Bean [11]	Non-serial Multi-Stage		Static	Inspection location	ILP
	Elliot et al [52]	Non-serial Multi-Stage I and II	Static	Sampling rate	Statistical
	Rau et al [5]	Non-serial Multi-Stage I and II	Static	Inspection Location	Heuristic
	Gudmundsson [40]	Non-serial Multi-Stage I and II	Static	Sampling rate and	GA
					Inspection Location
	Emmons et Rabinowitz [67] Non-serial Multi-Stage Error free	Static	Sampling rate and	NLP
					Inspection Location
	Hall et al [48]	Non-serial Multi-Stage Error free	Static	Inspection location	Statistical and Linear
						cost model
	Rau and Cho [68]	Non-serial Multi-Stage I and II	Static	Inspection Location	GA
	William et al [47]	Non-serial Multi-Stage Error free	Adaptive	Sampling rate and	Statistical and
					Inspection Location	Simulation
	Mouli et al [7]	Non-serial Multi-Stage Error free	Adaptive	Sampling	Statistical
	Bousseta and Cross [49]	Non-serial Multi-Stage I	Adaptive	Sampling rate	Statistical
	Kuo [6]	Non-serial Multi-Stage I	Adaptive	Sampling rate	Mathematical
	Verduzco et al [69]	Non-serial Multi-Stage I and II	Dynamic	Sampling based on	Heuristic
					Cost model
	Purdy et al

  Bousetta and Cross[START_REF] Bousetta | Adaptive Sampling Methodology for In-Line Defect Inspection[END_REF] propose a method to monitor key parameters to adjust the sampling plan for eective inspection capacity utilization. The key parameters are the variance ratio, excursion frequency and normalized mean shift. Mouli et al.[7] propose a score mechanism based on APC and SPC to weight each lot and wafer within a lot to decide whether to sample or not. Sun and Johnson[START_REF] Sun | Method and System for Determining Optimal Wafer Sampling in Real-Time Inline Monitoring and Experimental Design[END_REF] also use a score mechanism which is based on weighted objectives to optimize the sampling decisions. Verduzco et al.[START_REF] Verduzco | Information-based inspection allocation[END_REF] study

	a real-time Automated Visual Inspection in an electronic assembly system. They propose
	a model for a real-time inspection allocation based on the information gained by inspecting
	one additional component. They propose a model as an information maximization problem,
	to dene a real-time inspection allocation based on the information gained if one additional
	component is inspected.

Purdy et al.

[START_REF] Purdy | Method for Eciently Managing Metrology Queues[END_REF]

propose a method to release lots in metrology queue, each lot is evaluated individually and the objective is to guarantee the measurement of lots with more recent information. If two or more lots providing the same type of information are in the metrology queue and the one more recently processed is measured, the older lot (lots) can be removed. The developed application is part of a sampling system which combines a number of separate sampling rules into a single sampling decision. Holfedet al.

[START_REF] Holfeld | A Fab-Wide APC Sampling Application[END_REF]

propose a detail of lot level and wafer level sampling application. At the lot level: the application combines several restrictions with past sampling decisions to nd a well balanced lot sampling conclusion. The result is that a lot is only measured if ultimately required by a certain state, e.g. exceeding a risk threshold. At the wafer level: The wafer sampling application collects all wafer context information and incorporates historic wafer properties and APC application wafer properties. All of these contexts are associated to wafer sampling rules. These rules carry weights (violation penalty) and are then merged with historic rule violations to nd a well balanced wafer sampling decision. Nduhura-Munga et al.

[START_REF] Nduhura Munga | Dynamic Management of Controls in Semiconductor Manufacturing[END_REF]

propose a global indicator that allows very quick and fast computations of material at risk. This indicator (named IPC, Permanent Index per Context) is a generic solution that can be used to calculate dierent types of risk. An industrial prototype was

  New risk value of tool t if lots in set S are inspected. It is calculated as follows:

	4.2. PROBLEM DESCRIPTION AND SOLUTION APPROACH
	,l

55

• N RV t (S):

Table 4 .

 4 1: Example of lots waiting to be inspected

	Lot Process Tool W@R NW@R	IL
	L1	Tool 07	960	481	1100
	L1	Tool 08	948	486	1100
	L1	Tool 12	625	425	2500
	L2	Tool 05	179	104	500
	L2	Tool 06	622	349	1200
	L3	Tool 03	82	56	500
	L3	Tool 04	79	52	500
	L3	Tool 06	622	274	1200
	L3	Tool 07	960	456	1100
	L4	Tool 08	948	462	1100
	L4	Tool 11	737	274	2500
	L5	Tool 01	226	104	500
	L5	Tool 02	31	1	500
	L5	Tool 06	622	299	1200
	L5	Tool 09	306	293	1100
	L5	Tool 10	302	290	1100
	L5	Tool 12	625	425	2500

Table

Table 4 .

 4 2: Example of GSI and RI calculations (Iteration 1)(N W @R/IL) α

	Tools	S initial	{S initial \ {L1}}	{S initial \ {L2}}	{S initial \ {L3}}	{S initial \ {L4}}	{S initial \ {L5}}
	Tool 1	0.00008	0.00008	0.00008	0.00008	0.00008	0.00853
	Tool 2	0.00000	0.00000	0.00000	0.00000	0.00000	0.00000
	Tool 3	0.00000	0.00000	0.00000	0.00002	0.00000	0.00000
	Tool 4	0.00000	0.00000	0.00000	0.00002	0.00000	0.00000
	Tool 5	0.00008	0.00008	0.00211	0.00008	0.00008	0.00008
	Tool 6	0.00014	0.00014	0.00014	0.00024	0.00014	0.00014
	Tool 7	0.00507	0.00507	0.00507	0.00699	0.00507	0.00507
	Tool 8	0.00549	0.00549	0.00549	0.00549	0.00744	0.00549
	Tool 9	0.00036	0.00036	0.00036	0.00036	0.00036	0.00046
	Tool 10 0.00034	0.00034	0.00034	0.00034	0.00034	0.00043
	Tool 11 0.00000	0.00000	0.00000	0.00000	0.00066	0.00000
	Tool 12 0.00002	0.00002	0.00002	0.00002	0.00002	0.00002
	GSI	0.01159	0.01159	0.01361	0.01363	0.01419	0.02024
	RI	0.00000	0.00000	0.00202	0.00204	0.00260	0.00865
				Table 4.3: Example of RI calculations
			(a) Iteration 2			(b) Iteration 3
		Lot	RI	Decision	Lot	RI	Decision
		L2	0.002024	Skip		L2
		L3	0.436901 Not Skip	L3	0.438925 Not Skip
		L4	0.404892 Not Skip	L4	0.406916 Not Skip
		L5	0.008865 Not Skip	L5	0.010890 Not Skip

iteration.

Table 4 .

 4 4: Example of RI calculations for sets of lots

	4.4. NUMERICAL RESULTS AND DISCUSSION	65
	Set of Lots	RI
	L1, L2, L4	0.406916
	L1, L2, L5	0.010890
	L1, L3, L4	0.841793
	L1, L3, L5	0.446132
	L1, L4, L5	0.413757
	L2, L3, L4	0.006673
	L2, L3, L5	0.031869
	L2, L4, L5	0.013273
	L3, L4, L5	0.013660

Table 4 .

 4 5: Number of skipped lots and nal RI for dierent values of T M etro

	Instance	TypeAlgo	Number of skipped lots (Related RI)
				T M etro
		0.001	0.005	0.01	0.05	0.1
	1	Algorithm 1 6 (0.001279) 12 (0.284293) 13 (0.291487) 19 (0.435451) 22 (0.722157)
		Algorithm 2 5 (0.000653) 7 (0.004930)	7 (0.008011) 10 (0.049931) 14 (0.095832)
		Algorithm 3 5 (0.000626) 7 (0.004930)	8 (0.008628) 12 (0.045453) 15 (0.098124)
		Algorithm 4 5 (0.000626) 7 (0.004930)	8 (0.008628) 12 (0.035398) 15 (0.093280)
		Algorithm 5 5 (0.000626) 7 (0.004219) 8 (0.007871) 12 (0.035398) 15 (0.093280)
	2	Algorithm 1 4 (0.070563) 10 (0.131550) 11 (0.167974) 13 (0.194752) 15 (0.312755)
		Algorithm 2 3 (0.000882) 5 (0.004762)	7 (0.007275) 10 (0.047746) 11 (0.084170)
		Algorithm 3 3 (0.000115) 6 (0.003970)	7 (0.006507) 10 (0.046978) 11 (0.083402)
		Algorithm 4 3 (0.000115) 6 (0.003970)	7 (0.006507) 10 (0.043171) 11 (0.079595)
		Algorithm 5 3 (0.000115) 6 (0.003970)	7 (0.006507) 10 (0.043171) 11 (0.079595)
	7	Algorithm 1 7 (0.001262) 13 (0.396196) 14 (0.401685) 18 (0.522087) 19 (0.595998)
		Algorithm 2 6 (0.000512) 7 (0.004225)	8 (0.009715) 12 (0.045763) 14 (0.099489)
		Algorithm 3 6 (0.000385) 7 (0.001262)	9 (0.009661) 12 (0.038781) 14 (0.081529)
		Algorithm 4 6 (0.000385) 7 (0.001262)	9 (0.009661) 12 (0.037227) 14 (0.081529)
		Algorithm 5 6 (0.000385) 8 (0.004317) 9 (0.008450) 12 (0.037227) 14 (0.081529)

Table 4 .

 4 6: Average Calculation Time (sec)

			T M etro
	Type Algorithm 0.001 0.005	0.01	0.05	0.1
	Algorithm 1	0.347 0.287	0.336	0.311	0.284
	Algorithm 2	0.338 0.281	0.335	0.306	0.277
	Algorithm 3	1.194 1.471	2.072	2.392	2.732
	Algorithm 4	2.717 5.184	7.905	12.358	17.493
	Algorithm 5	0.316 8.544 17.510 439.952 2250.984

vs. 10 lots and RI = 0.04993). Algorithm 3 nds the best solution in 82% of the analyzed cases. However, lots are evaluated individually and once a lot is selected for skipping, previous decisions will not be reconsidered. These decisions are improved with algorithm 4 trough a local search. Actually, it can nd the best solution in 92% of the analyzed cases, but it is still myopic since lots are evaluated individually. Algorithm 5 is an exact method and thus nds the optimal solutions. For example, considering instance 1 and

Table 4 .

 4 6 presents the average calculation times for the dierent algorithms. When .4. NUMERICAL RESULTS AND DISCUSSION 67 Another case in which the set S Skippable is reduced is when additional rules are dened.

T M etro increases, the calculation time increases. This is explained by the fact that more combinations are possible because more lots can be skipped (i.e. The size of S Skippable increases with the value of T M etro ). When the set S Skippable is reduced, algorithm 5 gives the best solutions in a reasonable time. Algorithm 4 is a good trade-o between quality of solutions and calculation time when the set S Skippable increases.

4

Table 6 .

 6

	1: Current W@R limits and dierent product mixes
	Inspection tool types Mix 1	Mix 2	Mix 3	Mix 4	Mix 5	Mix 6	Mix 7
	T1	16.0% 15.8% 12.4% 22.6% 14.0% 19.9% 17.0%
	T2	10.0% 10.2% 11.4% 16.7% 14.8% 12.6% 19.0%
	T3	4.7%	4.5%	8.8%	7.2%	7.4%	5.8%	10.4%
	Total	30.7% 30.5% 32.6% 46.5% 36.2% 38.3% 46.4%
	Table

Table 6 .

 6

		2: Target W@R limits and dierent product mixes
	Inspection tool types Mix 1	Mix 2	Mix 3	Mix 4	Mix 5	Mix 6	Mix 7
	T1	19.6% 23.4% 23.4% 32.7% 25.5% 26.5% 31.7%
	T2	11.5%	9.2%	10.7% 19.6% 15.5% 16.3% 19.8%
	T3	7.4%	6.0%	6.6%	7.4%	5.7%	6.0%	7.8%
	Total	38.5% 38.6% 40.7% 59.7% 46.7% 48.8% 59.3%

Table 6

 6 .3 are evaluated. For condentiality6.3. EXPERIMENTS ON CAPACITY MODEL VERSION 3 91 reasons all limits are normalized with the value M . Let us recall that in this version of the model we consider the Inhibit limits (IL). Set B corresponds to 65% of process tools with their ILs smaller than M, 90% of process tools with their ILs smaller than 3× M and 100% of process tools with their ILs smaller than 7 × M . The parameters used for the experiments are presented in tale 6.4. The production volume considered in experiments corresponds to one month of activity. Therefore, the number of additional QTs that can be generated due to W@R controls are generated during a month.

		Table 6.3: Sets of W@R limits for process tools
	Set B	Set C	Set D	Set E
	65%

Table 6 .

 6 4: Parameters used for scenarios with Model 3 As presented in section 5.5, two penalty factors are used in the capacity model: Def P k and QT P . The penalty Def P k is used to restrict the utilization of a given inspection tool type over another inspection tool to inspect lots dynamically selected. The interest of this 94 CHAPTER 6. EXPERIMENTS ON THE CAPACITY MODEL b) Variation of QT P valueIn the capacity model, we consider two types of QTs: The planned QTs and the additional QTs. The planned QTs are dened in advance and are thus inputs in our model. The additional QTs are allocated in the model when the W@R limits on process tools cannot be satised. Hence, the penalty QT P is used for QTs due to W@R control. The values of the other parameters in this scenario can be found in Table6.7 Table6.7: Parameters for evaluating QT P variations

	Parameters	Values	Interpretation
	Product Mixes	Mix1, Mix2, Mix3, Dierent mixes and volumes
		Mix4, Mix5, Mix6	of products
	Limits	B, C, D, E	Set of W@R Limits on process
			tools
	Def P k Penalty	[1, 5, 10]	Restriction of using a given inspection
			tool type for W@R control
	QT Penalty (QT P ) [1, 10]	Restriction of using QTs that
			are not planned
	Alpha	[0, 0.2, 0.5, 0.7, 1]	Percentage of lots selected with Static
			Sampling that can also reduce the W@R
	Reserved Capacity	[0, 0.2, 0.5, 0.7]	Capacity reserved in advance on inspection
	(R k )		tool types for W@R control
	The model was solved using IBM ILOG 12.5.1 and experiments were run on a PC
	Intel Core i5 (2.40 Ghz). Instances include more than 700 process tools (cluster tools are
	considered at the chamber level), 1800 process operations, 170 inspection operations and
	10 product families.
	6.3.1 Impact of penalty values

Table 6 .

 6 8 presents the results for QT P = 1.

Table 6 .

 6

						8: Impact of QTs without penalty
			Def P k				Utilization rates		Total utilization rates
	Scenario	Values T1 T2 T3 T4	T1	Static sampling T2 T3	T4	Static and Dynamic sampling T1 T2 T3 T4	QTs
	7	1	1	1	1 70.4% 16.1% 15.3% 62.8% 100.0% 46.6% 16.7% 100.0%	248
	8	1	1	1	10 70.4% 16.1% 15.3% 62.8% 100.0% 51.4% 19.0%	62.8%	303
	9	10	1	1	1 70.4% 16.1% 15.3% 62.8%	70.4%	71.7% 38.4% 100.0%	361
	10	10	1	1	10 70.4% 16.1% 15.3% 62.8%	70.4%	76.5% 58.5%	62.8%

Table 6

 6

	.9: Parameters for evaluating Alpha variation
	Parameters
	Product Mix	Mix 1
	Limits	C
	Def P k	[ 10,1,1,10 ]
	QT P	10
	Reserved Capacity	0

Table 6 .

 6

						10: Impact of alpha variation
				Def P k			Utilization rates		Total utilization rates
	Scenario Alpha	Values T1 T2 T3 T4	T1	Static sampling T2 T3	T4	Static and Dynamic sampling T1 T2 T3 T4	QTs
	12	0	10	1	1	10	70.4% 16.1% 15.3% 62.8% 91.1% 69.0% 88.0%	66.9%	45
	14	0.2	10	1	1	10	70.4% 16.1% 15.3% 62.8% 86.6% 64.9% 80.1%	66.8%	45
	16	0.5	10	1	1	10	70.4% 16.1% 15.3% 62.8% 80.0% 59.9% 65.8%	66.8%	45
	18	0.7	10	1	1	10	70.4% 16.1% 15.3% 62.8% 75.6% 55.8% 58.5%	66.8%	45
	20	1	10	1	1	10	70.4% 16.1% 15.3% 62.8% 71.0% 51.0% 43.8%	66.8%

Table 6 .

 6

	14: Impact of W@R Limits C

Table 6 .

 6

	Product		Utilization Rates
	Mix		Dynamic Sampling	QTs
		T1	T2	T3	T4
	Mix 1	100% 100% 100% 100% 054
	Mix 2	100% 100% 100% 100% 184
	Mix 3	100% 100% 100% 100%
	Mix 4	100% 100% 100% 100% 436
	Mix 5	100% 100% 100% 100% 407
	Mix 6	100% 100% 100% 100% 771
	15: Impact of W@R Limits D

Table 6 .

 6 [START_REF] Riordan | The invention of the transistor[END_REF]: Impact of W@R Limits E In the set of experiments conducted in the second case, the value of ILs are calculated according to the minimum exposure on process tools. For each process tool, the new value IL is 10% larger than the minimum exposure (i.e. T C × T H). With this rule, 77% of the process tools have their ILs smaller than or equal to M, 94% of process tools have their ILs smaller than or equal to 3 × M and 100% of process tools have their ILs smaller than or equal to 6 × M . Table6.17 shows the results with the product mix 1. It can be observed that, with this strategy, all inspection tools are required at 100%. When the two strategies to select lots are considered (Static and Dynamic), it is better to dispatch the inspection operation 1330 of technology B. When the new IL is the minimum exposure, the only inspection operation that can control this tool is 1202 of technology A. The reason

  2 S5: Smart Sampling, Skipping and Scheduling Simulator 3 EMSE-SFL: École des Mines de St-Etienne, Département Science de la Fabrication et Logistique.

	104CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT
	7.2	Problem Description and Solution Approach

Table 7 .

 7 1: Impact of defect inspection control plans with and without overlapping

	Maximum W@R	Static S. Dynamic S. Dynamic S. Dynamic S. Dynamic S. Dynamic S.	Innite
	average	Capa A	Capa A5	Capa A4	Capa A3	Capa A2	Capa A	Capacity
	X inspection operations	100.0%	140.3%	95.4%	78.8%	74.3%	72.6%	57.7%
	X+20 no overlap.	100.0%	142.5%	95.1%	78.9%	73.6%	72.6%	57.0%
	X+50 no overlap.	100.0%	155.2%	104.2%	86.5%	81.7%	80.6%	66.0%
	X+20 with overlap.	100.0%	139.3%	92.5%	78.0%	73.4%	71.6%	56.3%
	X+50 with overlap.	100.0%	140.1%	93.3%	77.8%	73.3%	71.8%	56.3%

Table 7 .

 7

	2: Dierence between defect inspection control plans with and without overlapping
	Delta between defect inspection control Dynamic S. Dynamic S. Dynamic S. Dynamic S. Dynamic S.	Innite
	plan with and without overlapping	Capa A5	Capa A4	Capa A3	Capa A2	Capa A	Capacity
	X+20 inspection operations	3.2%	2.6%	0.9%	0.3%	1.0%	0.7%
	X+50 inspection operations	15.0%	10.9%	8.7%	8.3%	8.8%	9.7%
	In table 7.3, the positions of inspection operations are studied. It presents the results

Table 7 .

 7 4: Impact of new inspection operations that cover new process operations

	Maximum W@R	Dynamic S.	Dynamic S.	Dynamic S.	Dynamic S.	Dynamic S.	Innite
	average	Capacity A5 Capacity A4 Capacity A3 Capacity A2	Capacity A	Capacity
	X inspection operations	140.3%	95.4%	78.8%	74.3%	72.6%	57.7%
	X+20 without overlapping (B)	156.7%	102.7%	74.7%	62.6%	54.3%	26.2%
	X+20 with overlapping (B+2)	146.6%	93.1%	73.9%	59.8%	53.0%	26.2%
	X+20 with overlapping (B+4)	143.7%	90.9%	69.9%	61.2%	52.5%	26.0%
	X+20 with overlapping (B+6)	137.4%	89.1%	70.0%	58.7%	51.2%	25.9%

  : Average number of wafers of product i between process operation p and inspection operation c, W DQT t : Average number of wafers that cannot be produced while a Quality Task is being performed on process tool t. It is calculated as the throughput of t multiplied by the time required to perform a Quality Task on t,

	7.4. MATHEMATICAL MODEL FOR THE LOCATION AND ALLOCATION PROBLEM109
	W D i c,p hh i p,t : Qualication of process tools,
	=	 	1 if process tool t is qualied to process product i in process operation p,
			0 otherwise.
	products indexed by i,
	P : Set of process operations indexed by p,
	C : Set of inspection operations indexed by c,
	T : Set of process tools indexed by t,
	K : Set of inspection tools indexed by k,
	The parameters below are necessary:
	IL t : Inhibit Limit of process tool t,

  110CHAPTER 7. IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT Y i c,t : Number of inspections performed for product i in inspection operation c that covers process tool t, QT t : If the Inhibit Limit of process tool t cannot be satised with the locations of inspection operations a Quality Task is performed,

c : Total number of inspections performed on inspection operation c of product i,

  )

	Constraints (7.1) ensure that the position of the selected inspection operation U i c is
	used for the control of tool t if the distance W D i c,p is smaller than or equal to the Inhibit
	Limit IL t . If there are no possible locations, a QT would be performed on process tool
	t. Constraints (7.2) state that the total number of inspected lots Y i c,p is smaller than
	or equal to the quantity of product i processed on tool t. Constraints (7.3) dene the
	number of inspections performed on production lots (Y	i c,t ) that are needed to satisfy the

W@R limits (I L t ) of process tool t. Constraints (7.4) dene the number of inspections performed for inspection operation c of product i if the inspection operation c is created 7.4. MATHEMATICAL MODEL FOR THE LOCATION AND ALLOCATION PROBLEM111

Table 7 .

 7 5: Key Metrics of the project

	Item	Results

Table B .

 B 1: Number of skipped lots and nal LSI for dierent values of T M etro Algorithm 1 6 (0.001279) 12 (0.284293) 13 (0.291487) 19 (0.435451) 22 (0.722157) Algorithm 2 5 (0.000653) 7 (0.004930) 7 (0.008011) 10 (0.049931) 14 (0.095832) Algorithm 3 5 (0.000626) 7 (0.004930) 8 (0.008628) 12 (0.045453) 15 (0.098124) Algorithm 4 5 (0.000626) 7 (0.004930) 8 (0.008628) 12 (0.035398) 15 (0.093280) Algorithm 1 8 (0.001878) 10 (0.007715) 10 (0.007715) 10 (0.007715) 12 (0.087647) Algorithm 2 4 (0.000447) 6 (0.004665) 10 (0.007715) 10 (0.007715) 12 (0.087647) Algorithm 3 4 (0.000000) 8 (0.004741) 10 (0.007715) 10 (0.007715) 12 (0.087647) Algorithm 4 4 (0.000000) 8 (0.004741) 10 (0.007715) 10 (0.007715) 12 (0.087647) Algorithm 5 4 (0.000000) 8 (0.004741) 10 (0.007715) 10 (0.007715) 12 (0.087647) 10 Algorithm 1 9 (0.111135) 13 (0.120418) 13 (0.12418) 19 (0.488045) 21 (0.682193) Algorithm 2 6 (0.000985) 9 (0.004572) 11 (0.009628) 13 (0.041486) 13 (0.098187) Algorithm 3 7 (0.000724) 9 (0.003832) 10 (0.006745) 13 (0.029081) 15 (0.077084) Algorithm 4 7 (0.000724) 9 (0.003832) 11 (0.008887) 13 (0.029081) 15 (0.077084) Algorithm 5 7 (0.000724) 9 (0.003759) 11 (0.008887) 13 (0.029081) 15 (0.077084)

			Algorithm 1 7 (0.001262) 13 (0.396196) 14 (0.401685) 18 (0.522087) 19 (0.595998)
			Algorithm 2 6 (0.000512) 7 (0.004225)	8 (0.009715) 12 (0.045763) 14 (0.099489)
			Algorithm 3 6 (0.000385) 7 (0.001262)	9 (0.009661) 12 (0.038781) 14 (0.081529)
			Algorithm 4 6 (0.000385) 7 (0.001262)	9 (0.009661) 12 (0.037227) 14 (0.081529)
			Algorithm 5 6 (0.000385) 8 (0.004317)	9 (0.008450) 12 (0.037227) 14 (0.081529)
	8		Algorithm 1 1 (0.000000) 2 (0.003037)	2 (0.003037)	5 (0.091761)	5 (0.091761)
			Algorithm 2 1 (0.000000) 2 (0.003037)	2 (0.003037)	4 (0.042092)	5 (0.091761)
			Algorithm 3 1 (0.000000) 2 (0.003037)	2 (0.003037)	4 (0.042092)	5 (0.091761)
			Algorithm 4 1 (0.000000) 2 (0.003037)	2 (0.003037)	4 (0.042092)	5 (0.091761)
			Algorithm 5 1 (0.000000) 2 (0.003037)	2 (0.003037)	4 (0.042092)	5 (0.091761)
	9
		Instance	TypeAlgo	Number of skipped lots (Related LSI)
						T M etro
				0.001	0.005	0.01	0.05	0.1
	11	1	Algorithm 1 6 (0.001644) Algorithm 2 4 (0.000670) 7 (0.003612) 9 (0.29586)	13 (0.128561) 13 (0.128561) 13 (0.128561) 8 (0.009209) 11 (0.043792) 12 (0.074949)
			Algorithm 3 5 (0.000951) 7 (0.003612)	8 (0.006475) 11 (0.043792) 12 (0.074949)
			Algorithm 4 5 (0.000951) 7 (0.003612)	8 (0.006475) 11 (0.043792) 12 (0.074949)
	12	2	Algorithm 5 5 (0.000626) 7 (0.004219) Algorithm 5 5 (0.000951) 7 (0.003612) 8 (0.006475) 11 (0.043792) 12 (0.074949) 8 (0.007871) 12 (0.035398) 15 (0.093280) Algorithm 1 0 (0.000000) 2 (0.003039) 4 (0.024960) 6 (0.074434) 7 (0.124853) Algorithm 1 4 (0.070563) 10 (0.131550) 11 (0.167974) 13 (0.194752) 15 (0.312755) Algorithm 2 3 (0.000882) 5 (0.004762) Algorithm 2 0 (0.000000) 2 (0.003039) 2 (0.009072) 4 (0.044788) 6 (0.074434) 7 (0.007275) 10 (0.047746) 11 (0.084170) Algorithm 3 3 (0.000115) 6 (0.003970) Algorithm 3 0 (0.000000) 2 (0.003039) 2 (0.009072) 5 (0.047339) 6 (0.074434) 7 (0.006507) 10 (0.046978) 11 (0.083402) Algorithm 4 3 (0.000115) 6 (0.003970) Algorithm 4 0 (0.000000) 2 (0.003039) 2 (0.009072) 5 (0.047339) 6 (0.074434) 7 (0.006507) 10 (0.043171) 11 (0.079595) Algorithm 5 3 (0.000115) 6 (0.003970) 7 (0.006507) 10 (0.043171) 11 (0.079595) Algorithm 5 0 (0.000000) 2 (0.003039) 2 (0.009072) 5 (0.047339) 6 (0.074434)
		3		Algorithm 1 4 (0.002080) 9 (0.099745)	9 (0.099745) 14 (0.209593) 14 (0.209593)
				Algorithm 2 1 (0.000989) 3 (0.004692)	6 (0.009018)	9 (0.047786) 12 (0.093494)
				Algorithm 3 2 (0.000532) 5 (0.003150)	7 (0.007983) 10 (0.045235) 12 (0.091388)
	Algorithm 4 2 (0.000532) 5 (0.003150) Algorithm 5 2 (0.000532) 5 (0.003150) Results capacity planning	7 (0.007983) 10 (0.045235) 12 (0.091388) 7 (0.007983) 10 (0.045235) 12 (0.091388)
		4		Algorithm 1 0 (0.000000) 2 (0.005700)	3 (0.013162)	6 (0.084101)	6 (0.084101)
				Algorithm 2 0 (0.000000) 1 (0.004455)	2 (0.005700)	4 (0.041514)	6 (0.084101)
				Algorithm 3 0 (0.000000) 1 (0.001171)	2 (0.005700)	4 (0.032991)	6 (0.084101)
				Algorithm 4 0 (0.000000) 1 (0.001171)	2 (0.005700)	4 (0.032991)	6 (0.084101)
				Algorithm 5 0 (0.000000) 1 (0.001171)	2 (0.005700)	4 (0.032991)	6 (0.084101)
		5		Algorithm 1 4 (0.001457) 5 (0.005294)	5 (0.005294) 11 (0.166730) 12 (0.227748)
				Algorithm 2 3 (0.000493) 4 (0.001457)	5 (0.005294)	7 (0.048881)	7 (0.091766)
				Algorithm 3 3 (0.000493) 4 (0.001457)	5 (0.005294)	7 (0.038333)	9 (0.081920)
				Algorithm 4 3 (0.000493) 4 (0.001457)	5 (0.005294)	7 (0.038333)	9 (0.081920)
				Algorithm 5 3 (0.000493) 4 (0.001457)	5 (0.005294)	7 (0.038333)	9 (0.081920)
		6		Algorithm 1 0 (0.000000) 4 (0.008165)	5 (0.017027)	9 (0.125484) 10 (0.211769)
				Algorithm 2 0 (0.000000) 2 (0.003708)	4 (0.008165)	6 (0.027115)	8 (0.096540)
				Algorithm 3 0 (0.000000) 2 (0.003396)	4 (0.008165)	6 (0.027115)	8 (0.083012)
				Algorithm 4 0 (0.000000) 2 (0.003396)	4 (0.008165)	6 (0.027115)	8 (0.083012)
				Algorithm 5 0 (0.000000) 2 (0.003396)	4 (0.008165)	6 (0.027115)	8 (0.083012)

Table B .

 B 2: Parameters of the scenario parameters for Def P k variation

	124	APPENDIX B. EXPERIMENTAL RESULTS	123
		Factors Product Mix Limits QT P Alpha Reserved Capacity Table B.3: Variation of Def P k Penalties Mix 1 C 10 0.2 0 Def P k Total Utilization Rates Values Static and Dynamic Sampling T1 T2 T3 T4 T1 T2 T3 T4 1 1 1 1 100.0% 56.2% 23.3% 100.0% 1 1 1 5 100.0% 61.1% 31.2% 70.9% 1 1 1 10 100.0% 64.0% 40.3% 62.8% 1 1 5 1 100.0% 62.3% 15.3% 100.0% 1 1 5 5 100.0% 64.1% 15.3% 93.0% 1 1 5 10 100.0% 63.8% 18.6% 84.0% 1 1 10 1 100.0% 62.3% 15.3% 100.0% 1 1 10 5 100.0% 64.1% 15.3% 93.0% 1 1 10 10 100.0% 67.6% 15.3% 89.9% 1 5 1 1 100.0% 42.0% 95.3% 100.0% 1 5 1 5 100.0% 42.0% 95.3% 100.0% 1 5 1 10 100.0% 46.6% 100.0% 66.8% 1 5 5 1 100.0% 56.2% 23.3% 100.0% 1 5 5 5 100.0% 56.2% 23.3% 100.0% 1 5 5 10 100.0% 58.9% 23.3% 88.2% 1 5 10 1 100.0% 60.2% 17.4% 100.0% 1 5 10 5 100.0% 60.2% 17.4% 100.0% 1 5 10 10 100.0% 60.2% 17.4% 100.0% 1 10 1 1 100.0% 41.6% 100.0% 100.0% 1 10 1 5 100.0% 41.6% 100.0% 100.0% 1 10 1 10 100.0% 41.6% 100.0% 100.0% 1 10 5 1 100.0% 51.3% 39.4% 100.0% 1 10 5 5 100.0% 51.2% 39.5% 100.0% 1 10 5 10 100.0% 51.3% 39.3% 100.0% 1 10 10 1 100.0% 56.2% 23.3% 100.0% 1 10 10 5 100.0% 56.2% 23.3% 100.0% 1 10 10 10 100.0% 56.2% 23.3% 100.0% 5 1 1 1 86.6% 65.3% 48.4% 100.0% 5 1 1 5 88.1% 65.1% 64.9% 70.9% 5 1 1 10 87.3% 65.5% 74.9% 66.8% 5 1 5 1 98.8% 64.1% 15.3% 100.0% 5 1 5 5 100.0% 64.1% 15.3% 93.0% 5 1 5 10 100.0% 63.8% 18.6% 84.0% 5 1 10 1 98.8% 64.1% 15.3% 100.0% 5 1 10 5 100.0% 64.1% 15.3% 93.0% Def P k Total Utilization Rates QTs Values Static and Dynamic Sampling T1 T2 T3 T4 T1 T2 T3 T4 5 1 10 10 100.0% 67.6% 15.3% 89.9% 45 5 5 1 1 100.0% 42.0% 95.3% 100.0% 45 5 5 1 5 100.0% 42.0% 95.3% 100.0% 45 5 5 1 10 100.0% 46.6% 100.0% 66.8% 45 5 5 5 1 100.0% 56.2% 23.3% 100.0% 45 5 5 5 5 100.0% 56.2% 23.3% 100.0% 45 5 5 5 10 100.0% 58.9% 23.3% 88.2% 45 5 5 10 1 100.0% 60.2% 17.4% 100.0% 45 5 5 10 5 100.0% 60.2% 17.4% 100.0% 45 5 5 10 10 100.0% 60.2% 17.4% 100.0% 45 5 10 1 1 100.0% 41.6% 100.0% 100.0% 45 5 10 1 5 100.0% 41.6% 100.0% 100.0% 45 5 10 1 10 100.0% 41.6% 100.0% 100.0% 45 5 10 5 1 100.0% 51.2% 39.6% 100.0% 45 5 10 5 5 100.0% 51.3% 39.3% 100.0% 45 5 10 5 10 100.0% 51.3% 39.4% 100.0% 45 5 10 10 1 100.0% 56.2% 23.3% 100.0% 45 5 10 10 5 100.0% 56.2% 23.3% 100.0% 45 5 10 10 10 100.0% 56.2% 23.3% 100.0% 45 10 1 1 1 86.6% 65.3% 48.4% 100.0% 45 10 1 1 10 86.6% 64.9% 80.1% 66.8% 45 10 1 1 5 86.6% 65.1% 73.5% 70.9% 45 10 1 5 1 94.3% 64.3% 23.3% 100.0% 45 10 1 5 5 94.3% 64.3% 23.3% 100.0% 45 10 1 5 10 96.3% 64.3% 23.3% 89.0% 45 10 1 10 1 98.8% 64.1% 15.3% 100.0% 45 10 1 10 5 98.8% 64.1% 15.3% 100.0% 45 10 1 10 10 100.0% 67.6% 15.3% 89.9% 45 10 5 1 1 91.6% 49.8% 93.1% 100.0% 45 10 5 1 5 91.6% 49.8% 93.1% 100.0% 45 10 5 1 10 91.6% 54.3% 100.0% 66.8% 45 10 5 5 1 100.0% 56.2% 23.3% 100.0% 45 10 5 5 5 100.0% 56.2% 23.3% 100.0% 45 10 5 5 10 100.0% 58.9% 23.3% 88.2% 45 10 5 10 1 100.0% 60.2% 17.4% 100.0% 45 10 5 10 5 100.0% 60.2% 17.4% 100.0% 45 10 5 10 10 100.0% 60.2% 17.4% 100.0% 45 10 10 1 1 100.0% 41.6% 100.0% 100.0% 45 10 10 1 5 100.0% 41.6% 100.0% 100.0% 45 10 10 1 10 100.0% 41.6% 100.0% 100.0% 45 10 10 5 1 100.0% 51.3% 39.3% 100.0% 45 10 10 5 5 100.0% 51.3% 39.3% 100.0% 45 10 10 5 10 100.0% 51.3% 39.3% 100.0% 45 10 10 10 1 100.0% 56.2% 23.3% 100.0% 45 10 10 10 5 100.0% 56.2% 23.3% 100.0% 45 10 10 10 10 100.0% 56.2% 23.3% de Saint-Étienne NNT : 2014 EMSE 0747 Gloria Luz RODRIGUEZ VERJAN SMART SAMPLING FOR RISK REDUCTION IN SEMICONDUCTOR QTs 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 MANUFACTURING Speciality : Industrial Engineering Keywords : Excursion monitoring, Wafers at Risk, Defect Inspection, 100.0% École Nationale Supérieure des Mines Sampling.

  Sélection dynamique, échantillonnage dynamique, contrôle, défectivité, gestion du risque, fabrication de semi-conducteurs.

	École Nationale Supérieure des Mines
	de Saint-Étienne
	NNT : 2014 EMSE 0747
	Gloria Luz RODRIGUEZ VERJAN
	ÉCHANTILLONNAGE DYNAMIQUE DE LOTS POUR LA
	RÉDUCTION DES RISQUES EN FABRICATION DE SEMI-
	CONDUCTEURS.
	Spécialité : Génie Industriel
	Mots clés :

entre SMicroelectronics et l'ENSM-SE. La plupart des cas dans lesquels les équipements de production n'étaient pas susamment contrôlés ou qui étaient sur-contrôlés ont été réduits. La gure 14 présente le niveau de risque dans un groupe d'équipements d'un même atelier avant et après l'implémentation du système dynamique de sélection des lots. Le nombre de wafers potentiellement impactés lorsqu'un problème arrive est limité par l'IL (Inhibit limit en anglais) des équipements de production.La gure 15 présente la valeur moyenne des IL de la fab, cette valeur a pu être réduite de 66% depuis le début du projet. Enn, d'importantes économies ont été obtenues non seulement en termes de réduction de risque global de la fab, mais aussi en termes d'une meilleure utilisation de la capacité en défectivité grâce à une meilleure sélection des lots à inspecter.4 Sponsors: P. Campion and M. Le Gall. Leaders: E. Tartière and J. Pinaton.ST RoussetTeam: A. Thieullen, G. Rodriguez-Verjan, P. Palouar, S. Detivaud, B. Pennachio, J.C. Mattlin, F. Chairat, C. Klingelschmidt, V. Lemaire, J. De-selle, D. Courilleau, B. Mari, C. Giuliani, D. Viard. ENSM-SE SFL Team: S. Dauzère-Pérès, C. Yugma, J.L. Rouveyrol, S. Housseman.

Remerciements

Canción de Violeta Parra) Les travaux présentés dans cette thèse ont été réalisés dans le cadre d'une convention CIFRE (N. 2010/1440) accordée par l'Association Nationale de la Recherche Technique, en collaboration avec STMicroelectronics et l'École Nationale Supérieure des Mines de St-Etienne.

Je tiens à exprimer ma gratitude à mon directeur de thèse, le professeur Stéphane

CHAPTER 5. ALLOCATION OF DEFECT INSPECTION CAPACITY

inspection operations of their routes, the identication of yield-limiting process operations is possible thanks to the added-defect analysis [START_REF] Guldi | In-Line Defect Reduction from a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing[END_REF]. When dynamic sampling is used, the W@R on process tools can be better controlled, because lots are selected in real time.

Therefore, the two sampling strategies (i.e. Static sampling and dynamic sampling) are still being used in the factory, and are considered in the model. Industrial details that are critical for W@R control on process tools are included, such as: The conguration of control plans, qualications of tools (i.e. process and inspection tools), the QTs performed on process tools and the W@R limits. Numerical experiments on industrial data are presented in chapter 6. Chapter 6 Experiments on the Capacity Model Numerical experiments on industrial data are presented in this chapter. The model can be used at dierent decision levels. At the tactical level, it shows if W@R limits can be satised when the product mix changes and/or if planned W@R reductions can be met with the available inspection capacity. At the strategic level, the model helps to justify capacity investments if the objectives in terms of W@R reduction cannot be achieved with the available capacity.

6.1 CHAPTER 6. EXPERIMENTS ON THE CAPACITY MODEL penalty is to analyze scenarios where a given inspection tool type is reserved to be used for an activity other than W@R measures or where a dierent balance in terms of utilization rate among inspection tool types is explored. Concerning the penalty QT P penalty, it is used to restrict the utilization of additional QTs due to W@R control.

a) Variations of Def P k value

To analyze the impact of restricting the utilization of some inspection tool types over others, dierent combinations of this penalty were evaluated (i.e. 1, 5 and 10). Concerning the setting of the other parameters, we chose the values corresponding to a standard scenario of the fab when experiment were conducted. These values are summarized in table B.2. Limits C is the set of W@R limits when experiments were conducted and Alpha = 0.2 is the percentage of lots selected with static sampling that can reduce the W@R to its minimum level (i.e. T C × T H). All experiments are presented in Appendix B. In this section we discuss the results of six scenarios presented in table 6.6. The performance measure is the utilization rate of each inspection tool type and the number of additional QTs. In the following, the inspection tool type 1 will be referred as T1, the same for inspection tool types 2, 3 and 4 (T2, T3 and T4). The columns named as Def P k values, refer to the penalty selected on each inspection tool type. The columns named as Utilization Rates for Static Sampling, refer to the time used for the inspection of lots selected only with the static sampling strategy over the total capacity in terms of time. The Total Utilization Rates for Static and Dynamic Sampling, refer to the time used to inspect the total number of lots selected with both strategies. The column QTs refers to the number of additional QTs that are estimated. In this scenario, performing QTs due to W@R is highly restricted. For that, we set QT P = 10 and we consider that performing a QT would be six times longer than the longest inspection time of a production lot.

When there is no restriction for using a particular tool type (i.e. Scenario 1), the utilization rates of T1 and T4 are larger than the other two inspection tool types. The

EXPERIMENTS ON CAPACITY MODEL VERSION 3

93 reason is that the inspection time on T1 is larger than the others (e.g. average inspection time of 30 minutes on T1 versus 15 minutes on T2) and because there are more inspection operations qualied on T1 than on T3. However, the inspection time depends on the recipe, the product to inspect and the required inspection technology (e.g. Darkeld or Brighteld). Inspection tool type T4 corresponds to only one tool. Hence, the total capacity is smaller than the other tool types and it is easier to achieve 100% utilization rate. Moreover, an important aspect to consider is that the utilization rates dedicated to static sampling are 70.4% on T1 and 62.8% on T4. This implies that, even if there is a high penalty for using these tools, the utilization rates will not be smaller than the capacity already assigned with static sampling. When the use of T1 is restricted (i.e. scenario 2 with penalties 10,1,1,1) the workload is mainly transferred to T2 and T3. Since the utilization rates of T1 and T4 are 100% without restriction, only penalizing T1 will not impact T4 and vice-versa (scenarios 2 and 3).

When there is a restriction on T1 and T4 (i.e. scenarios 4, 5 and 6) the workload is transferred on T2 and T3. These results illustrate the exibility of the control plan to cover the process tools. If there is a change on the available capacity for T1 or T4, there are other inspection operations qualied on T2 and T3 that can cover the process tools that were previously controlled with T1 or T4. Nevertheless, this is only true for the lots dynamically selected, because the dynamic sampling strategy takes the available capacity on the inspection tools into account before sampling a lot. It is important to note that the number of additional QTs does not change among the scenarios. This means that, with the current design of defect inspection control plans (i.e. position and coverage of inspection operations), there are some process tools that cannot be controlled only with the inspection of production lots.

Glossary

In the following a glossary of the terminology used in this thesis is presented. References [START_REF] Quirk | Semiconductor Manufacturing technology[END_REF], [START_REF]Sematech dictionary of semiconductor terms[END_REF], [START_REF] Ruzyllo | Semiconductor glossary[END_REF] should be consulted for more extensive glossaries.

• APC: Advanced Process Control. A set of techniques used to control processes and machines.

• BEOL: Back End Of Line. It refers to the processes performed from the contact through completion of the wafer and prior to electrical tests.

• Brighteld: In optical detection or photolithography tools, it refers to the illumination and detection technique. The incident light and the reected light are parallel to each other and the illuminated object appears on a bright background.

• Cluster Tool: A tool that combines several process chambers within a closed environment together with a handling robot.

• Coverage Block: In this thesis, the term coverage block refers to the set of process operations that can be controlled with an inspection operation. The coverage block is dened in the defect inspection control plan.

• Darkeld: In optical detection or photolithography tools, it refers to the illumination and detection technique. The incident light and the reected light has an angle and the illuminated object appears on a dark eld background.

• Defect inspection: Type of control that aims at detecting the defects produced on wafers during the production.

• Defect inspection control plan: Is the list of inspection operations that are performed throughout the manufacturing route of products. It states the position within the manufacturing route and the coverage block of each inspection operation.

• Dies: Individual chips cut from a wafer before they are packaged.

• Excursions: Temporal yield losses that randomly happen (in time) as a consequence of an out-of-control condition on a process tool.

APPENDIX A. GLOSSARY

• Fab: It refers to a semiconductor fabrication plant. Usually refers to the front-end process of making the devices in semiconductor wafers.

• FEOL: Front end of line. It refers to all the processes from the wafer start through contact etch.

• FOUP: Front Opened Unied Pod, it is a pod used to transport wafers, usually contains 25 wafers.

• GSI: Global Sampling Indicator. Score used to evaluate the global risk of the fab and helps to dene the best set of lots to inspect.

• IL: Inhibit Limit. Is the maximum value of wafers at risk, if the W@R level achieves this limit, the process tool should be stopped and a special control performed.

• IMPROVE: Implementing Manufacturing science solutions to increase PRoductiVity and fab pErformance.

• Killer Defect: Defects that cause the chip to fail.

• Lot: It is a group of wafers that is manipulated with a FOUP. Usually it contains 25 wafers.

• Manufacturing Route: Sequence of processes that are necessary to obtain the nal product.

• Qualication: It refers to the setting of a recipe on the tools, in order to be able to perform the processing or the inspection of the wafers.

• Quality Tasks: It refers to a special control performed on Non-patterned wafers.

These type of controls are used to monitor contamination and surface quality of the wafer and monitor the cleanliness of tools.

• R2R: Run to Run, is a loop control technique based on equipment and lot information.

• Recipe: Set of instructions and parameters required in order to perform semiconductor processing or control on a given tool.

• RI: Risk Increase indicator. It is the the associated risk (i.e. GSI variation ) of not inspecting a lot or a set of lots.

Instance TypeAlgo

Number of skipped lots (Related LSI)

T M etro 0.001 0.005 0.01 0.05 0.1