text:
Bhanukiran Perabathini

Vineeth S Varma

Mérouane Debbah

Marios Kountouris

Alberto Conte

Physical Limits of point-to-point communication systems

In this paper, we explore the physical limits of successful information transfer in a point-to-point communication system. In interest of studying the fundamental limits imposed by physics on communication systems in general, we model a simple generic system that enables us to make some basic inquiries about the energy efficiency in information transfer and processing. We use ideas from thermodynamics such as Szilard engine to represent information bits. We further use ideas from electromagnetic theory for transfer of information, and information theory to define the energy efficiency metric. We find the upper limit of this efficiency and conditions at which it can be achieved.

I. INTRODUCTION

For a long time, it has been known that the process of communication has a cost in terms of energy [START_REF] Bekenstein | Energy Cost of Information Transfer[END_REF], [START_REF] Lloyd | Physical Limits to Communication[END_REF], [START_REF] Brillouin | Science and Information Theory[END_REF]. In 1948, Shannon published his revolutionary paper [START_REF] Shannon | A Mathematical Theory of Communication[END_REF], in which the conditions under which information can be communicated reliably are mathematically quantified. We intend to address this specific point but from the perspective of energy expenditure, taking information creation and processing into account.

In its colloquial sense, information may be an abstract and subjective concept. However, in its objective sense information precisely means an ensemble of suitable physical systems prepared in desired states. The physical nature of information is discussed in [START_REF] Landauer | Information is a Physical Entity[END_REF]. To give examples:

• A text message written on a piece of paper with a pencil is but one among several possible arrangements of an ensemble of carbon molecules in the two dimensional plane of a paper. • An audio file inscribed on a compact disk is essentially a collection of pits and bumps engraved on it in a unique order. If a chosen physical system has distinct binary states (represented by a Bernoulli random variable), the information represented by such a system is called a bit. A large amount of information may be represented in terms of necessary number of such bits [START_REF] Shannon | A Mathematical Theory of Communication[END_REF]. Preparing a physical system in a state or to change its state from one to another requires energy. While there may be countless possible physical systems that can be used in preparing, changing and storing a given information, the choice of the system decides how much energy is needed to perform all these operations. Our first inquiry lies in this point. In an attempt to explore the answer to the question: 'What is the most energy efficient choice of physical systems to represent and process information?', we choose to begin with a simple thermodynamic system (section II-A) to represent an information bit. We discuss energy expenditure in preparing and processing (operations on) such bits.

The process in which physical systems prepared in desired states are transported from the transmission point to the reception point in space and time through a communication channel is called information transfer. This is a physical process too and requires energy. The correlation between the states sent and the states received is what determines the quality of information transfer. This correlation may be distorted due to interference from the physical world (noise), and such a distortion is quantified as error. There exists a trade off between the amount of energy spent at the transmission point and the mutual information (between the received states and the transmitted states) that can be achieved. Our second inquiry lies in this point. In an attempt to explore the answer to the question:"What is the limit on the efficiency of a communication system taking information creation into account?", we convert the information represented by the above mentioned thermodynamic bits into electromagnetic waves to reach the reception, and evaluate the energy efficiency of the system. We are particularly interested in evaluating energy efficiency in communicating one bit of information as a limiting case (section III-D). Contrary to the intuitive notion that efficiency can be maximized arbitrarily by increasing energy investment, our result shows that excess expenditure of energy does not necessarily have to be an efficient solution in point-to-point communication.

Our paper organization is as follows. In Section II, we elaborate on the communication system that we intend to study. In Section III, we discuss the energy efficiency of the proposed system that uses binary phase-shift keying (BPSK). In Section IV, we extend our analysis to higher constellations by comparing the present case with that of QPSK. In Section V, we make plots of energy efficiency of the proposed system and comment on its behavior for cases of BPSK and QPSK signaling.

II. PROPOSED POINT-TO-POINT COMMUNICATION SYSTEM

In order to model a communication system at its most basic physical form, we first look at how information itself can be physically represented. Secondly, we look at how this information can be extracted from the physical system and converted to electromagnetic waves. Finally, this signal is received by a physical antenna and stored as thermodynamic information at the receiver. What we call 'information' here is the source coded form of raw information. We do not take into account the influence of source coding on the efficiency.

A. Thermodynamic representation of information

Imagine an isolated cylindrical container of gas molecules in equilibrium. Now imagine that an insulating wall with a small door is introduced in the middle. Maxwell postulated that a small demon that can operate this door can cause a violation of second law of thermodynamics by allowing gas molecules with high speeds pass in one direction and slow ones in the other direction. Because transferring heat between systems that are mutually at thermal equilibrium without doing any work violates second law of thermodynamics [START_REF] Bennett | Demons, engines and the second law[END_REF], [START_REF] Bennett | Notes on Landauer's principle, reversible computation, and Maxwells Demon[END_REF]. Szilard resolved this paradox by arguing based on the proposition that "destruction of physical information creates entropy in the environment". For the demon to create such a temperature difference, without disturbing the system, it has to have an infinite memory at hand. Because having finite memory restricts the amount of information that can be stored at a given time and therefore excess information obtained by observing positions and velocities of several molecules would have to be destroyed continuously. This destruction of information would have dissipated energy back into the environment (container). This dissipated energy in turn would have increased the net disorder in the system contradicting Maxwell's prediction that the demon would actually decrease it [START_REF] Szilard | On the decrease of entropy in a thermodynamic system by the intervention of intelligent beings[END_REF], [START_REF] Gopalkrishnan | The Hot Bit I: The Szilard-Landauer Correspondence[END_REF], [START_REF] Brillouin | Maxwell's Demon Cannot operate:Information and Entropy. I[END_REF].

An "engine" that Szilard used to illustrate the above idea, consists of a single molecule of an ideal gas in a cylindrical vessel with an adiabatic friction less piston locked in the middle separating it into two halves. The single molecule has two distinct physical states (left/right of the box) and therefore can represent one bit of information. To destroy this information, this system is brought in contact with a thermal reservoir at the same temperature as the molecule and the piston is unlocked. As a result the molecule jitters back and forth and repeatedly kicks the wall until the wall reached the other end of the container. Finally the molecule's position is totally randomized and the information about its location is destroyed with the help of heat drawn from the reservoir. And since the internal energy of the molecule has not changed, the excess work is dissipated into the environment.

Heat dissipated in destroying a bit (Q dissip. ) which is the work done by the molecule (W mol. ) to push the volume from V /2 to V in an isothermal limit, using the ideal gas law P V = kT is given by [START_REF] Feynman | Feynman Lectures On Computation[END_REF]

Q dissip. = W mol. = V V /2 P dV = V V /2 kT dV V = kT ln 2, ( 1
)
where k is the Boltzmann constant. It has to be noted that the time taken to push the piston (τ ) at a given temperature depends on the size of the container V . Note that τ cannot be infinitely small unless V is infinitely small in which case quantum effects have to be taken into account [START_REF] Wook | Quantum Szilard Engine[END_REF].

We use a modification of Szilard engine as shown in Figure 2 in our model. There are two possible states for such a system. The Bernoulli random variable corresponding to each state is P right := 1{Probability[X > L -] = 0}, where X is the x coordinate of the position of the molecule, L is the horizontal dimension of the box, is any arbitrarily small positive number. Clearly P right ∈ {0, 1}.

1) State 0: The piston is pushed to the extreme end and the information about the location of the molecule is totally randomized. There is no mechanical energy that can be derived out of this system (P right = 0). 2) State 1: The molecule is confined in the left half and the piston is push to the middle from the right. A mechanical energy of at least kT ln 2 can be derived out of it (P right = 1). We say that these systems come in state 0 by default and we spend energy kT ln 2 in creating state 1. The two states together represent one bit of information which we here on wards refer to as the Thermal-bit. 1 A certain amount of raw information that is sampled and converted into necessary number of bits (0's and 1's) can be physically represented using a tape (an array) of Thermal-bits as shown in Figure 3.

B. Transmission setup (T)

Figure 4 depicts the communication device that we intend to study in the subsequent sections. Part T of the system is the transmission setup and R is the reception setup. We intend to send n bits of information from T to R which a distance r apart in space. For a very large n it maybe assumed that the source generates as many bits in state 0 as in state 1. That implies that the probability of having either of them is 1/2.

The Transmission Setup consists of an ideal AC power source (with no internal resistance) connected to a wire loop antenna of radius b. There is a switching mechanism S at the bottom. It works as follows:

1) A tape of Thermal-bits is fed into the switching mechanism. Each time a bit enters in, it remains in S for τ seconds before the next bit enters. 2) If a bit enters the switch in state 1, mechanical energy is extracted out of it and is used to open the switch of the circuit and keeps it so for the time τ until the bit is replaced by the next one. The amount of mechanical energy extracted out of each Thermal-bit is given by eq. ( 1). Whereas, if it is a Thermal-bit in state 2 that enters in, the switch remains closed for τ seconds until the next bit enters.

Each time the switch is closed, current from the AC source flows through the loop antenna and an electromagnetic field is radiated (magnetic dipole radiation). Let us represent the k th bit to be sent by a k , a Bernoulli random variable of probability 1/2. Therefore, depending on a k , the switch remains either closed or open each for a period of time τ . The current 'signal' through the loop can be written as I(t) = I 0 (t) cos(ω c t), where I 0 (t) = I 0 k a k S(t -kτ ) with I 0 as the amplitude of the AC current, ω c is the carrier frequency and S represents a square wave of period τ . We assume that the switching time τ 2π/ω c . Information which has been stored in the form of Thermalbits thus far is now converted into a series of electromagnetic pulses. These pulses travel at the speed of light and each pulse has a time length of τ . The phase difference between the pulses is what represents the information making it a BPSK (Binary Phase-Shift Keying) signal.

C. Reception setup (R)

Reception setup consists of a wire loop receiving antenna (radius b) attached in series to a resistor (Figure 4). The resistance of this resistor is adjusted/chosen such that the total impedance of the receiving antenna matches the free space impedance. By this, we can safely assume that all the power that reaches the antenna is absorbed in the form of induced EMF which in turn is amplified and then completely converted into heat at the resistor A switching mechanism S is located at the bottom. It works as follows:

1) A tape of thermal bits created in states 1 is sent in.

2) Each time the Thermal-bit is kept in contact with the resistor for a time τ allowing heat to transfer. 3) If the temperature of the resistor T R ≥ T , the piston of the Thermal-bit will be pushed out creating a bit in state 0

III. THE ENERGY EFFICIENCY LIMIT

In this section, we derive the equations for the energy consumed by the communication system and the achievable rate of such a system. With these equations, we finally calculate the fundamental limit on energy efficiency of a physical system that communicates with electromagnetic waves.

A. The signaling system

We know that the magnitude of the Poynting vector generated by a magnetic dipole, as defined in the previous section, at a distance r from the dipole and at an angle θ with vertical axis (Figure 5

| S| = µ 0 c m 0 (t)ω 2 c 4πc sin θ r cos(ω c (t -r/c)) 2 (2)
where c is velocity of light, m 0 (t) = πb 2 I 0 (t) is the maximum dipole of the loop [START_REF] Griffiths | Introduction to electrodynamics[END_REF]. We find the average of the power density over the time period of one complete wave cycle τ 0 = 2π ωc .

S = µ 0 b 4 ω 4 c sin 2 θ 16r 2 c 3 I 2 0 ×E a k ,τ0 [( k a k S(t -kτ )) 2 × cos 2 (ω c (t -r/c))] = µ 0 b 4 ω 4 c sin 2 θ 16r 2 c 3 I 2 0 ×E τ0 [ k =l E[a k a l ]S(t -kτ ) 2 + k E[a 2 k ]S(t -kτ ) 2 ] × cos 2 (ω c (t -r/c)) .
But we know that a k ∈ {0, 1} with probability 1/2 each and that a k 's are not correlated. Therefore,

E[a k ]E[a l ] = 1/4 and E[a 2 k ] = 1/2. Which gives, S = µ 0 b 4 ω 4 c sin 2 θ 16r 2 c 3 I 2 0 × 3 4 E τ0 k S(t -kτ ) 2 × cos 2 (ω c (t -r/c)) .
By using the assumptions that τ τ 0 and that S(t -kτ ) is either 0 or 1, we get

S = µ 0 b 4 ω 4 c sin 2 θ 16r 2 c 3 I 2 0 3 4 . 1 2 = 3µ 0 b 4 ω 4 c sin 2 θ 128r 2 c 3 I 2 0 . (3)
The total radiating power emitted by the antenna is obtained by integrating eq. ( 3) over the surface area of any sphere surrounding the loop. Therefore the average energy per bit emitted by the transmission setup during one operation for time τ (that is for bit in state 0) is given by

E rad T = τ × 3µ 0 b 4 ω 4 c I 2 0 128c 3 π 0 (sin θ) 2 sin θ dθ 2π 0 dφ = τ × 3µ 0 b 4 ω 4 c I 2 0 128c 3 × 8π 3 = ατ ω 4 c I 2 0 , (4)
where α = µ0πb 4 16c 3 .

B. Energy considerations at T

In the whole process of transmitting n bits of information, we like to evaluate the total amount of energy spent in the Transmission Setup. We have shown earlier that the energy required for an operation on state 1 to switch it to state 0 is kT ln 2 and an operation on state 0 costs zero energy. And by the assumption that the states are equally probable, we can say that an operation on a Thermal-bit on an average costs an energy of 1 2 kT ln 2. Therefore, the average amount of energy required to read a total of n Thermal-bits would be E bits T = n 2 kT ln 2 joules. To emit all the bits, the radiator must have been operated n/2 times and for time τ each time. Therefore the fundamental lower bound on the total energy spent is:

E tot T (n) := n[ατ ω 4 c I 2 0 + 1 2 kT ln 2]. (5)
C. Energy considerations at R Equation ( 3) gives the magnitude of the Poynting vector at a distance r from the transmitting antenna. We assume that both transmitting and receiving loops are in the same plane (θ = 0). Assuming that all the power absorbed into the loop is equal to the product of the magnitude of the Poynting vector and the area πb 2 . The received signal energy on average per bit is given by

E 0 R := τ × 3µ 0 b 4 ω 4 c I 2 0 128r 2 c 3 × πb 2 = βτ ω 4 c I 2 0 , (6)
where β = 3µ0πb 6 128r 2 c 3 . If we assume that the distance is large, i.e. for large enough r, the sum of received energy per bit and the channel noise can be much less than the energy needed to write a bit at the reception end, i.e.

E 0 R 1 2
kT ln 2.

In this case, in order to write a bit into the tape at the receiver, the received non-zero signal will be amplified by an amplifier that has to supply an average total energy (for all n bits)

E tot R (n) := n 2 kT ln 2. (7)
Finally, we define the total energy cost of preparing a Thermal-bit → transmitting it electromagnetically → constructing it back at the receiver as (from eq. ( 5) and eq. ( 7))

E 0 tot = E tot T (n = 1) + E tot R (n = 1) = ατ ω 4 c I 2 0 + 1 2 kT ln 2 + 1 2 kT ln 2 = ατ ω 4 c I 2 0 + kT ln 2. (8)

D. The energy efficiency

The energy per bit to noise energy ratio snr b 0 is given as

snr b 0 = E 0 R N 0 W = βω 4 c W 2 I 2 0 N 0 , (9)
where, I 2 0 which is proportional to the energy spent by the AC source at T per bit, N 0 is the noise spectral density, and W := 1 τ is the bandwidth where τ is the time length of each pulse.

We know that the mutual information of BPSK channel as a function of snr 0 is given by [START_REF] Samah | Mutual Information for Generalized Arbitrary Binary Input Constellations[END_REF]

I b (snr b 0 ) = 1 ln 2 snr b 0 - 1 √ 2π ∞ -∞ e -y 2 2 log cosh(snr b 0 -y snr b 0 ) dy . (10)
Finally, we define energy efficiency η as the ratio

η b = W I b (snr b 0 ) E 0 tot bits/sec/joules.
By substituting snr b 0 from eq. ( 9), η b (ω c ) can be expressed as a function of ω c as

η b (W, ω c , I 0 , kT ) = W ( βω 4 c I 2 0 W 2 N0 -1 √ 2π ∞ -∞ e -y 2 2
log cosh(

βω 4 c W 2 I 2 0 N0 -y βω 4 c W 2 I 2 0 N0 ) dy) (ln 2)( αω 4 c I 2 0 W + kT ln 2) . (11)
IV. ENERGY EFFICIENCY FOR HIGHER CONSTELLATIONS So far, we only considered the case where only one bit is encoded by one symbol. However, by making appropriate modifications to the proposed setup and the scheme of phasing, one should in principle be able to encode any number of bits per symbol.

Instead of caring for the details of the engineering, we focus on the energy considerations for the case of quadrature phase shift keying (QPSK). The main difference in the case of QPSK is that we have four symbols {11, 01, 10, 00} and the probability that the source produces a typical symbol a k is now assumed to be 1/4. This will result in the following changes:

1) The average energy per symbol emitted is 1 4 (2E rad T + E rad T + E rad T + 0) = E rad T /2. 2) Similarly, the received signal energy on average per symbol E 0 R is changed by a factor 1/2. 3) A thermal operation in this case is on two bits at once.

The average energy spent on the a symbol is kT ln 2.

Including the cost of operation at T and R makes the average energy spent per operation per symbol 2kT ln 2.

Which is twice the case of BPSK. The total energy spent on a symbol in preparing, transmitting and writing (analogous to eq. ( 8)), will be

E 0 tot = α 2 τ ω 4 c I 2 0 + 2kT ln 2 (12)
And the energy per bit to noise energy ratio snr q 0 is given as

snr q 0 = E 0 R 2N 0 W = βω 4 c 2W 2 I 2 0 N 0 . ( 13
)
We know that the mutual information of QPSK channel as a function of snr q 0 is given by [START_REF] Samah | Mutual Information for Generalized Arbitrary Binary Input Constellations[END_REF] I q (snr q

0 ) = 1 ln 2 2snr q 0 - 2 π ∞ -∞ e -y 2 2
log cosh(snr q 0 -y snr q 0 ) dy .

Energy efficiency in this case is given as

η q (W, ω c , I 0 , kT ) = W ( βω 4 c I 2 0 2W 2 N0 -2 π ∞ -∞ e -y 2 2
log cosh(

βω 4 c I 2 0 2W 2 N0 -y βω 4 c I 2 0 2W 2 N0 ) dy) (ln 2)( αω 4 c I 2 0 2W + 2kT ln 2) . ( 15
)
Energy efficiency for any M -ary constellation can be theoretically determined in the same lines. However, the engineering of the setup and the scheme of phasing get much more complicated.

V. NUMERICAL ANALYSIS Equations ( 11) and [START_REF] Griffiths | Introduction to electrodynamics[END_REF] give expressions for energy efficiency in the case of BPSK and QPSK, respectively. In this section, we numerically verify and compare the behavior of the functions η b (W, ω c , I 0 , kT ) and η q (W, ω c , I 0 , kT ).

We use the values µ 0 = 4π×10 -7 N A -2 , c = 3×10 8 ms -1 , r = 1m and b = 1m to get the values of α = 9.25926 × 10 -34 and β = 3.42695 × 10 -33 .

Figure 7 is a plot of η b and η q against carrier frequency ω c for W = 1Hz, N 0 = 1, kT = 1 and I 0 = 1A. It can be seen that at lower frequencies BPSK is more efficient that QPSK, but for higher frequencies QPSK is much more efficient than BPSK. We numerically determine the optimal carrier frequencies from the plots as ω * b = 1.57013 × 10 8 Hz and ω * q = 2.00214 × 10 8 Hz. Figure 8 is a plot of η b and η q against bandwidth W for optimal frequencies ω * b = 1.57013 × 10 8 Hz, ω * q = 2.00214 × 10 8 Hz, N 0 = 1, kT = 1 and I 0 = 1A. The energy efficiency approaches 0 when band width is infinitely large.

Figure 9 is a plot of η b and η q against square of the amplitude square of current I 0 for W = 1Hz, N 0 = 1, ω b = ω q = 10 8 Hz and kT = 1 For low values of current (amplitude), BPSK is seen to be more efficient than QPSK, but for higher amplitudes QPSK is much more efficient than BPSK.

Figure 10 is a plot of optimal frequency ω * c against temperature (kT ) of the Thermal-bits in both cases of BPSK and QPSK for W = 1, N 0 = 1 and I 0 = 1A . Since temperatures cannot be arbitrarily small in classical conditions, this suggests that the optimal frequency cannot be arbitrarily small either.

VI. CONCLUSION

In this work, we devised a hypothetical communication system and calculated the upper bound on energy efficiency using electromagnetic and thermodynamic theory. We have seen that, in the proposed model, for a given total amount of energy that is at disposal to prepare, transmit and rewrite information bits, there exists a unique transmitting antenna frequency that yields maximum energy efficiency. We have also seen the dependence of energy efficiency on the bandwidth and the amplitude of the signal, and that it has an optimum at suitable values for the two. We have made a comparison of these dependencies in the cases of binary phase key shifting model and quadrature phase key shifting model. Similar treatment can be performed on various choices of physical systems to store and transport information. Our choice of thermodynamic Szilard boxes and electromagnetic waves is in the interest of exploring the classical limits. However, when we consider very low energy systems, the quantum mechanical effects could be more pronounced and this requires further study. In our future work we are interested to explore further fundamental physical systems to represent bits. For example: quantum spin states of particles, quantum mechanically described thermodynamic systems [START_REF] Wook | Quantum Szilard Engine[END_REF].

Fig. 1 .

 1 Fig. 1. Point-to-Point communication scheme.

Fig. 2 .

 2 Fig. 2. The Thermal Bit.

Fig. 3 .

 3 Fig. 3. Information as a tape of thermodynamic bits.

Fig. 4 .

 4 Fig. 4. Communication device.

Fig. 5 .

 5 Fig. 5. Magnetic dipole[15].

Fig. 6 .

 6 Fig. 6. Information as a series of electromagnetic pulses.

  ), making the assumptions b r, b c ωc and r c ωc , is given by

Fig. 7 .

 7 Fig. 7. Energy efficiency vs. Frequency (ωc).

Fig. 8 .

 8 Fig. 8. Energy efficiency vs. Bandwidth (W ).

Fig. 9 .Fig. 10

 910 Fig. 9. Energy efficiency vs. I 2 0 .

Similar Thermal-bits can be prepared with systems with any number of molecules and not necessarily just one. But we deliberately choose single molecule systems as a limiting case.


Bertrand Blancheton
email: bertrand.blancheton@u-bordeaux4.frchritian.bordes@u-paris1.fr

Christian Bordes

Samuel Maveyraud
email: samuel.maveyraud@u-bordeaux4.fr

Philippe Rous
email: philippe.rous@unilim.fr

Risk of liquidity and contagion of the crisis on the US, UK and Euro Zone money markets

Keywords: E4, G15, E58

The financial crisis has produced a generalized rise of the liquidity risk on the money markets. The purpose of this article is to highlight the mechanisms of contagion between the money markets of the United States, the United Kingdom and the Euro Zone. To give an account of these mechanisms, a BEKK model, in which we introduce a structural break, is adopted. Thus, this model explicitly tests the spillover effects of the liquidity risk premium on money markets. The results show that before the financial crisis (i.e. the reference period), the spillover effects are observed on money markets, as a result of the interconnectedness of these markets, whereas over the crisis period, the liquidity problems go from the United Kingdom to the American money market and then to the euro area. .

I. Introduction

The upsurge of the financial crisis stems directly from the solvability crisis of the least well-off American households who took out subprime mortgages. From August 2007, the solvability crisis has turned into a bank liquidity crisis that has contributed to the spread of international upheaval. The bank liquidity issue has since appeared as the Gordian knot of the financial crisis (suspicion between financial institutions, credit restrictions, etc.). This paper focuses on the major issue of liquidity on the money markets. It sets out to achieve two purposes. It seeks to analyse the dynamics of bank liquidity problems in the United States, the Euro Zone and the United Kingdom through the evolution of the interest rate spreads between LIBOR (London Interbank Offered Rate) and OIS (Overnight Index Swaps) on the different money markets. It aims to show the growing intensity of difficulties encountered by financial institutions in this matter. In an original way, this paper means to highlight the spreading process of strain on liquidity by testing potential causal connections between the spreads of the three money markets. By extension, it will attempt to reveal the truth about the causes of this liquidity crisis: did it too start in America? Did tensions in American money markets really spread to European markets as suggested by some authors: "This week a year ago, on 9 August 2007, a French investment house announced that it would suspend redemption of shares held by investors on a few of its enhanced-return euro money market funds. The reason for this move was that the market, for some of the paper in which these funds had invested, US-dollar denominated asset-backed commercial paper, had collapsed. With this announcement, the credit crisis -which was to broaden into a fullblown financial crisis -had started in earnest" (Deutsche Bank, Global Economic Perspectives, August 4, 2008).

To shed light on these questions, the BEKK model, named after the bivariate model proposed by [START_REF] Baba | Multivariate simultaneous generalised Arch[END_REF] has been adopted. This model reveals in particular the spreading mechanisms governing the evolution of variances and covariances in discrepancies between LIBOR and OIS interest rates over time. The originality of our modelling lies with the introduction of a structural break in the equation of central tendency and equations of conditional variances and covariances (as proposed by [START_REF] Beirne | Volatility Spillovers and Contagion from Mature to Emerging Stock Markets[END_REF]. Taking this break into account  first exposed with the technique used by [START_REF] Westerlund | Simple Unit Root Tests with Multiple Breaks[END_REF]  helps to explicitly test the potential modifications of the overspill phenomenon between money markets.

This article is organized in the following way: the second section analyses the meaning of the spreads of interest used, as well as their evolution between January 2007 and November 2008. The third section presents the adopted econometric model (BEKK with a structural break) and specifies the results obtained. Finally, the last section provides a conclusion to our study.

II. Amplification of liquidity problems on money markets

Banks make two types of banking operations on the money market to manage liquidity (or cash-flow): non-secured operations and repurchase transactions. These operations lead to risk-taking: credit risk (or counterparty risk) and liquidity risk (or market risk).

To deal with these risks, banks can resort to the derivatives market, in particular to the overnight index swaps market (OIS) in order to guard against events unforeseen by LIBOR, i.e. the unexpected degradation of the borrower situation and non-anticipated changes in liquidity demand addressed to the creditor and to the market [START_REF] Kwan | Behavior of Libor in the Current Financial Crisis[END_REF], as well as CDS (credit default swap) to hedge against credit risk.

Of these two types of risks, credit risk for non-secured operations and overnight index swaps operations is almost non-existent, these operations being of short maturity. Therefore, spread between LIBOR and OIS hardly reflects the credit risk premium. It thus mainly reveals the liquidity premium amount5 . Indeed, the OIS is the fixed-leg rate in the coupon swap. The variable rate is an overnight rate; the interests from the variable leg are capitalized and are subjected to maturity payment in the same way as interests from the fixed-leg. The LIBOR is a cash rate in the sense that the creditor immediately releases (at contract signature) liquidities to transfer them to the borrower whereas there is no immediate cash released with the OIS (cash swap occurs at maturity providing there is a gap between rates). Consequently, the spread between LIBOR and OIS primarily reflects the intensity of bank liquidity problems.

In this paper, we will proceed to analyse three daily series of spread between LIBOR and OIS three months apart, in the United States, the Euro Zone6 and the United Kingdom.

[Figure 1] During the first semester of 2007 before the financial crisis arose, spreads seemed quite stable, around 5-6 base points for the Euro Zone, 7-8 base points in the United States and 10 base points in the United Kingdom. None of these markets appeared to be the driving force for the overall dynamics of the three markets.

On August 9, 2007, the spread between LIBOR and OIS increased in all the markets.

In the United States, it rose by 13 base points on the 8 th to 34 on the 9 th and 49 on the 10 th . In the Euro Zone, it rose by a smaller proportion by 11 to 18 points and 27 points on the 10 th . In the United Kingdom, the increase was even more moderate, from 20 to 25 then 32 points. This rise in liquidity price can be linked to upheavals that were then affecting the pricing system of sophisticated financial products. Indeed, the growing rise of uncertainty (and thus of the liquidity premium) came from the implementation of an increasingly complex securitization system that made risk pricing more and more difficult [START_REF] Gonzalez-Paramo | Financial Turmoil, Securitisation and Liquidity[END_REF]; [START_REF] Zagaglia | Money-market segmentation in the euro area: what has changed during the turmoil? Bank of Finland Research[END_REF]). As a result, the first American defaults warned operators that they were short of information for risks associated with these new financial products: they began to have doubts. On August 9, 2007, uncertainty was so acute that BNP-Paribas suspended the calculation of the net asset values of three of its funds.

From August 9, the European Central Bank reacted by injecting liquidities (€94.8 billion) and the Fed injected in turn $24 billion. On August 13, both banks again injected €48 billion and $2 billion respectively into banks. These measures had limited impact on the liquidity risk: the spread increased until September 12, 2007.

[Figure 2] Over this period, the liquidity risk appeared to be more significant in the United States and the United Kingdom than in the Euro Zone, for the situation of banks in the Euro Zone appeared to offer better security against liquidity issues. Subsequently, the liquidity risk fell in the United Kingdom by about 50 points: this fall could be related to the emergency aid granted on September 14 by the Bank of England to Northern Rock, the fifth largest bank in Great Britain. Spreads stabilized to similar levels between September 21 and November 14, 2007.

Spreads shot up again from November 15: the rise was halted on December 7 for the dollar, December 11 for the pound and December 7 for the euro. This reversal could be explained by the concerted support measure from five central banks (the European Central Bank, the Fed, the Bank of England, the Bank of Canada and the Bank of Switzerland) which injected liquidities on December 12. Over this period, as shown by the figure above, the euro spread seemed to lag behind the movements affecting the dollar and pound sterling.

Spreads reached minimum levels on January 29 for the euro and the pound and on January 30 for the dollar. Subsequently, they rose until April 16 for the pound, April 30 for the dollar and May 14 for the euro. Then, until mid-September 2008, spreads stabilized around 70 base points. This relative stability was certainly linked to the support measures from the Fed and the American Treasury to help a number of the organisations in difficulty (Fannie Mae and Freddie Mac on July 13, 2008).

[Figure 3] September 15, 2008 marked a break in the trajectory of liquidity risk. The announcement of the failure of Lehman Brothers (the fourth largest investment bank on Wall Street) led to a sharp rise in spreads. The "too big to fail" principle that seemed to be governing rescue actions from authorities on an international level was abandoned. It then put an end to the moral hazard induced by systematic rescue. This option made operators think that other institutions were not shielded from a similar sanction. After this episode, interbank loans were considered riskier, rates on money markets shot up and liquidity problems grew worse. Unsecured loans seemed frozen as suspicion became widespread amongst bankers. As shown in figure 3, the LIBOR-OIS spread soared after the failure of Lehman Brothers. It peaked on October 10 with 366 base points for the dollar and 194 base points for the euro. For the pound, the spread kept on increasing until November 6, 2008 (it then reached 298 base points), while it fell in the United States and stabilized in the Euro Zone. During this period of extreme tension, risk remained lower for the euro.

At the end of 2008, the problems of liquidity slowly decline so that we can consider, at the end of May, the return to a "normal" situation, according to Fed Chairman Alan Greenspan (Bloomberg, May 26, 2009) This description of the evolution of liquidity risk suggests that support from central banks had, at best, helped to stabilize the liquidity premium level rather than sharply reduce it.

Each period of tension on money markets implied a long-term and cumulative rise between LIBOR and OIS. This hysteresis effect may be explained by the observed substitution between repurchase transactions and non-secured operations (LIBOR). Indeed, on money markets, repurchase transactions were preferred to non-secured actions as they naturally offer better security. Considering the increase of counterparty risk, it was more precisely repurchased transactions on Treasury bills that were preferred to non-secured transactions (without guaranty). Accordingly, the interest rate on repurchase transactions with Treasury bills security decreased so much that it dropped below the LIBOR or the OIS (Hördahl and King, 2008). The absorption of liquidity on the interbank market led to a rise in the LIBOR in such a way that the spread between the LIBOR and OIS rose.

The liquidity crisis associated with the financial crisis gives food for thought over the existence of contagion mechanisms that could have been set between the different money markets. We would like to determine more particularly, the extent to which the periods of strain on money markets in the Euro Zone and Great Britain together with the subsequent BCE and Bank of England"s support actions, may be primarily explained by the rise in the liquidity risk on the American money market or whether the absorption of liquidity was simultaneous on the markets we are studying.

III. Frame of analysis and findings

To highlight the potential links between three variables Y 1 , Y 2 and Y 3 , representing more specifically the daily variances in spread rates observed in the United States, the United Kingdom and the Euro Zone over the period from January 3, 2002 to June 22, 2009, the BEKK model with a structural break [START_REF] Beirne | Volatility Spillovers and Contagion from Mature to Emerging Stock Markets[END_REF] has been adopted. This model helps to evidence propagation mechanisms that govern the evolution of variances and covariances of these variables over time.

In order to bring to the fore the specificity of the contagion mechanism during the financial crisis, we distinguish two subperiods a "reference" period from January 3, 2002 to August 8, 2007 and the financial crisis period from August 9, 2007 to June 22, 2009.

Can the three series be directly modelized over this period with a muli-variate autoregressive BEKK-type model? To do so, unit-root tests must conclude with the rejection of H 0 (chart 1). Yet, as shown by tests performed on level series (ADF test with constant) and over the period from January 3, 2002 to August 8, 2007, this hypothesis can never be rejected irrespective of the chronicle studied. However, over the financial crisis period, we have to reject the null hypothesis at a 5% level: the spreads are non-stationnary.

[Chart 1 here] Considering the acute increase of the spread that existed in money markets after the failure of Lehman Brothers, we introduce a structural break on September 15, 2008 over the financial crisis period.

We then proceed to the multivariate modelling of the three series. The model adopted is a trivariate BEKK model over the reference period and a trivariate BEKK model with 1 structural break over the financial crisis period. In matrix form, this last model is written:

Equations of average values:

/1/ Y t =  t  + [I - t ] +  Y t-1 +  t
Where Y t is a column vector with three components:

Y t " = [Y 1t , Y 2t , Y 3t ];  (resp. ) is
likewise the column vector with three components: constants that prevail from September,

to the order of one; finally,  t is an identity matrix of dimension 3 as from August 9, 2007 and nil before this date.

Equations of conditional variancescovariances

We set H t as the symmetrical matrix of conditional variances and covariances of  jt errors:

H t = h h h h h h     
Generically, we modelize these conditional variances and covariances as follows:

/2/ H t = C'  t C + D" [I - t ] D + + A'  t  t  t ' A + B'  t [I- t ]  t ' B + + G' H t-1  t G + F" H t-1 [I - t ] F
Considering the way the  t matrix is constructed, we note that the C, A and G matrices are those of coefficients governing the evolutions of conditional variancescovariances from the structural break; matrices D, B and F are those prevailing before this break.

Matrices C and D have, whatever the hypothesis made subsequently on the propagation mechanism, a superior triangular structure:

C = 1 1 1 2 1 3 2 2 2 3 33 c c c 0 c c 0 0 c      D = 1 1 1 2 1 3 2 2 2 3 33 d d d 0 d d 0 0 d     
The structure of matrices A, B, F and G varies according to the hypothesis made on the spreading mechanism of volatility levels.

The "complete" model M1 introduces no restrictions on these volatilities propagation mechanisms: the conditional variance in zone i is determined not only by its own lag but also by those of conditional variances of other zones:

A = 1 1 1 2 1 3 2 1 2 2 2 3 3 1 3 2 3 3 a a a a a a a a a      B = 1 1 1 2 1 3 2 1 2 2 2 3 b b      G = 1 1 1 2 1 3 2 1 2 2 2 3 3 1 3 2 3 3 g g g g g g g g g      F = 1 1 1 2 1 3 2 1 2 2 2 3 3 1 3 2 3 3 f f f f f f f f f     
The

     G = 11 2 1 2 2 3 1 3 2 3 3 g 0 0 g g 0 g g g      F = 11 2 1 2 2 3 1 3 2 3 3 f 0 0 f f 0 f f f     
According to this scheme, the conditional variance in zone 3 can only depend on its own lags while the one in zone 1 depends both on its own lag and on lags of the conditional variances of zones 2 and 3.

Lastly, the "diagonal" model supposes that each variance and covariance never depends only on its own lags and squares or cross-products of corresponding lagged-innovations. The The equations of variances and covariances associated with each of these three models are reproduced in annex 1.

Chart 2 provides the values obtained for the log-likelihood function of the sample associated with the triangular model for each potential scheme of propagation over the two subperiods considered.

[Chart 2 here]

From this table it ensues that if a "triangular"-type model should challenge the complete model, the UK → EuroZone → USA scheme would be favoured over the reference period.

However, the UK → USA → EuroZone scheme would be adopted over the financial crisis period. It is thus on the basis of this scheme that several tests on various restrictions that may be added to coefficients and correspond to different propagation schemes We can firmly deduce that the "complete" model must be favoured over the reference period.

However, the "triangular" model (UK → USA → EuroZone scheme) must be chosen over the financial crisis period.

These results must mainly be explained by the interconnectedness of banks" international balance sheets. Indeed, Banks" foreign positions have surged since 2000: the stock of foreign claims grew from $11 trillion at end-2000 to $31 trillion by mid-2007 (the year-on-year growth in foreign claims approached 30% by mid-2007) [START_REF] Mc Guire | The US dollar shortage in global banking[END_REF].

Hence, over the reference period, this interconnectedness of banks" balance sheets implied a manifold propagation scheme.

Before the financial crisis period, the long position in dollar of UK banks, as foreign claims were predominantly in dollars: more than $300 billion by mid-2007. UK banks maintained largely balanced net interbank US dollar positions (i.e. cross currency funding) (BIS, 2009).

Hence, the liquidity problems on the British money market, primilarly due to an inadequate monetary policy as the BoE did not provide liquidity as fast and as much as the other central 7 When these tests involve model M2, we always work with a "triangular" propagation scheme UK → EuroZone → USA over the reference period and UK → USA → EuroZone over the financial crisis period.

banks, have mainly been propagated to the US money market and to a less extent to the euro money market. Furthermore, dislocations in FX swap markets over the financial crisis period made more expensive to obtain US dollars via currency swaps [START_REF] Baba | Interpreting deviations from covered interest parity during the financial market turmoil of 2007-2008[END_REF])

which has reinforced liquidity problems and the speed of contagion.

IV. Conclusion

This paper, focused on the major issue of liquidity on money markets, has set out to Then, in an original and novative manner, the article has highlighted the propagation process of the liquidity crisis by testing, with a trivariate BEKK model in which a break was introduced, the causal links between spreads in the three money markets. Tests could evidence the following results. Over the period of analysis chosen for the econometric study (i.e. from January 3, 2002 to June 22, 2009), we see that over the reference period (before the beginning of the financial crisis on August 9, 2007), the overspill between money markets was manifold: interest spreads interacted. Over the financial crisis period, the propagation scheme goes from the UK money maket to the US money market and then to the Euro money market: the bank liquidity crisis would not have come specifically from America but rather from the United Kingdom.

Annex 1: conditional variances and covariances in the different models "Complete" model M1

h 11 t = 1 t 2 c 11 2 +  2 t 2 d 11 2 +  1 t a 11  1 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 21  2 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 31  3 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 11  1 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 21  2 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 31  3 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 )
+ f 11 ( 2 t f 11 h 11 t-1 +  2 t f 21 h 12 t-1 +  2 t f 31 h 13 t-1 ) + g 11 ( 1 t g 11 h 11 t-1 +  1 t g 21 h 12 t-1 +  1 t g 31 h 13 t-1 ) + f 21 ( 2 t f 11 h 12 t-1 +  2 t f 21 h 22 t-1 +  2 t f 31 h 23 t-1 ) + g 21 ( 1 t g 11 h 12 t-1 +  1 t g 21 h 22 t-1 +  1 t g 31 h 23 t-1 ) + f 31 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 31 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 )

h 22 t =  1 t 2 c 12 2 +  1 t 2 c 22 2 +  2 t 2 d 12 2 +  2 t 2 d 22 2 +  1 t a 12  1 t-1 ( 1 t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  1 t a 22  2 t-1 ( 1 t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  1 t a 32  3 t-1 ( 1 t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  2 t b 12  1 t-1 ( 2 t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) +  2 t b 22  2 t-1 ( 2 t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) +  2 t b 32  3 t-1 ( 2 t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) + f 12 ( 2 t f 12 h 11 t-1 +  2 t f 22 h 12 t-1 +  2 t
f 32 h 13 t-1 ) + g 12 ( 1 t g 12 h 11 t-1 +  1 t g 22 h 12 t-1 +  1 t g 32 h 13 t-1 ) + f 22 ( 2 t f 12 h 12 t-1 +  2 t f 22 h 22 t-1 +  2 t f 32 h 23 t-1 ) + g 22 ( 1 t g 12 h 12 t-1 +  1 t g 22 h 22 t-1 +  1 t g 32 h 23 t-1 ) + f 32 ( 2 t f 12 h 13 t-1 +  2 t f 22 h 23 t-1 +  2 t f 32 h 33 t-1 ) + g 32 ( 1 t g 12 h 13 t-1 +  1 t g 22 h 23 t-1 +  1 t g 32 h 33 t-1 )

h 33 t =  1 t 2 c 13 2 +  1 t 2 c 23 2 +  1 t 2 c 33 2 +  2 t 2 d 13 2 +  2 t 2 d 23 2 +  2 t 2 d 33 2 +  1 t a 13  1 t-1 ( 1 t a 13  1 t-1 +  1 t a 23  2 t-1 +  1 t a 33  3 t-1 ) +  1 t a 23  2 t-1 ( 1 t a 13  1 t-1 +  1 t a 23  2 t-1 +  1 t a 33  3 t-1 ) +  1 t a 33  3 t-1 ( 1 t a 13  1 t-1 +  1 t a 23  2 t-1 +  1 t a 33  3 t-1 ) +  2 t b 13  1 t-1 ( 2 t b 13  1 t-1 +  2 t b 23  2 t-1 +  2 t b 33  3 t-1 ) +  2 t b 23  2 t-1 ( 2 t b 13  1 t-1 +  2 t b 23  2 t-1 +  2 t b 33  3 t-1 ) +  2 t b 33  3 t-1 ( 2 t b 13  1 t-1 +  2 t b 23  2 t-1 +  2 t b 33  3 t-1 )
+ f 13 ( 2 t f 13 h 11 t-1 +  2 t f 23 h 12 t-1 +  2 t f 33 h 13 t-1 ) + g 13 ( 1 t g 13 h 11 t-1 +  1 t g 23 h 12 t-1 +  1 t g 33 h 13 t-1 ) + f 23 ( 2 t f 13 h 12 t-1 +  2 t f 23 h 22 t-1 +  2 t f 33 h 23 t-1 ) + g 23 ( 1 t g 13 h 12 t-1 +  1 t g 23 h 22 t-1 +  1 t g 33 h 23 t-1 ) + f 33 ( 2 t f 13 h 13 t-1 +  2 t f 23 h 23 t-1 +  2 t f 33 h 33 t-1 ) + g 33 ( 1 t g 13 h 13 t-1 +  1 t g 23 h 23 t-1 +  1 t g 33 h 33 t-1 )

h 12 t =  1 t 2 c 11 c 12 +  2 t 2 d 11 d 12 +  1 t a 12  1 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 22  2 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 32  3 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 12  1 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 22  2 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 32  3 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 )
+ f 12 ( 2 t f 11 h 11 t-1 +  2 t f 21 h 12 t-1 +  2 t f 31 h 13 t-1 ) + g 12 ( 1 t g 11 h 11 t-1 +  1 t g 21 h 12 t-1 +  1 t g 31 h 13 t-1 ) + f 22 ( 2 t f 11 h 12 t-1 +  2 t f 21 h 22 t-1 +  2 t f 31 h 23 t-1 ) + g 22 ( 1 t g 11 h 12 t-1 +  1 t g 21 h 22 t-1 +  1 t g 31 h 23 t-1 ) + f 32 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 32 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 )

h 13 t =  1 t 2 c 11 c 13 +  2 t 2 d 11 d 13 +  1 t a 13  1 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 23  2 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 33  3 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 13  1 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 23  2 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 33  3 t-1 ( 2 t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 )
+ f 13 ( 2 t f 11 h 11 t-1 +  2 t f 21 h 12 t-1 +  2 t f 31 h 13 t-1 ) + g 13 ( 1 t g 11 h 11 t-1 +  1 t g 21 h 12 t-1 +  1 t g 31 h 13 t-1 ) + f 23 ( 2 t f 11 h 12 t-1 +  2 t f 21 h 22 t-1 +  2 t f 31 h 23 t-1 ) + g 23 ( 1 t g 11 h 12 t-1 +  1 t g 21 h 22 t-1 +  1 t g 31 h 23 t-1 ) + f 33 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 33 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 )

h 23 t =  1 t 2 c 12 c 13 +  1 t 2 c 22 c 23 +  2 t 2 d 12 d 13 +  2 t 2 d 22 d 23 +  1 t a 13  1 t-1 ( 1 t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  1 t a 23  2 t-1 ( t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  1 t a 33  3 t-1 ( t a 12  1 t-1 +  1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  2 t b 13  1 t-1 ( t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) +  2 t b 23  2 t-1 ( t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) +  2 t b 33  3 t-1 ( t b 12  1 t-1 +  2 t b 22  2 t-1 +  2 t b 32  3 t-1 )
+ f 13 ( 2 t f 12 h 11 t-1 +  2 t f 22 h 12 t-1 +  2 t f 32 h 13 t-1 ) + g 13 ( 1 t g 12 h 11 t-1 +  1 t g 22 h 12 t-1 +  1 t g 32 h 13 t-1 ) + f 23 ( 2 t f 12 h 12 t-1 +  2 t f 22 h 22 t-1 +  2 t f 32 h 23 t-1 ) + g 23 ( 1 t g 12 h 12 t-1 +  1 t g 22 h 22 t-1 +  1 t g 32 h 23 t-1 ) + f 33 ( 2 t f 12 h 13 t-1 +  2 t f 22 h 23 t-1 +  2 t f 32 h 33 t-1 ) + g 33 ( 1 t g 12 h 13 t-1 +  1 t g 22 h 23 t-1 +  1 t g 32 h 33 t-1 ) "Triangular" model M2 ) +  1 t a 32  3 t-1 ( t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 22  2 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 32  3 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) + f 22 ( 2 t f 11 h 12 t-1 +  2 t f 21 h 22 t-1 +  2 t f 31 h 23 t-1 ) + g 22 ( 1 t g 11 h 12 t-1 +  1 t g 21 h 22 t-1 +  1 t g 31 h 23 t-1 ) + f 32 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 32 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 ) h 13 t =  1 t 2 c 11 c 13 +  2 t 2 d 11 d 13 +  1 t a 33  3 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 33  3 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) + f 33 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 33 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 )

h 11 t = 1 t 2 c 11 2 +  2 t 2 d 11 2 +  1 t a 11  1 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 21  2 t-1 ( t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  1 t a 31  3 t-1 ( t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1 ) +  2 t b 11  1 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 21  2 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) +  2 t b 31  3 t-1 ( t b 11  1 t-1 +  2 t b 21  2 t-1 +  2 t b 31  3 t-1 ) + f 11 ( 2 t f 11 h 11 t-1 +  2 t f 21 h 12 t-1 +  2 t f

  "triangular" model M2 postulates an oriented propagation Y 3  Y 2  Y 1 . It is materialized by a restriction of nullity concerning the superior triangle of each A, B,

  model M2 versus H A : model M1 -H0: model M3 versus H A : model M2 [Chart 3 here]

  highlight several phenomena and produce several findings. The analysis of the dynamics of bank liquidity issues in the United States, the Euro Zone and the United Kingdom through the evolution of the interest rate spread between LIBOR and OIS in various money markets indicates the growing intensity of the liquidity risk as suspicion grew between financial institutions. From this perspective, the failure of Lehman Brothers marked a break: after September 15, 2008 the price of liquidity shot up. Support actions from central banks only served to contain tensions around liquidity between August 2007 and September 2008 and they seemed overwhelmed by the growing distrust amongst financial institutions thereafter.

Figure 1 :

 1 Figure 1: Spreads between the LIBOR and OIS over the whole period

  31 h 13 t-1 ) + g 11 ( 1 t g 11 h 11 t-1 +  1 t g 21 h 12 t-1 +  1 t g 31 h 13 t-1 ) + f 21 ( 2 t f 11 h 12 t-1 +  2 t f 21 h 22 t-1 +  2 t f 31 h 23 t-1 ) + g 21 ( 1 t g 11 h 12 t-1 +  1 t g 21 h 22 t-1 +  1 t g 31 h 23 t-1 ) + f 31 ( 2 t f 11 h 13 t-1 +  2 t f 21 h 23 t-1 +  2 t f 31 h 33 t-1 ) + g 31 ( 1 t g 11 h 13 t-1 +  1 t g 21 h 23 t-1 +  1 t g 31 h 33 t-1 ) 1 t a 22  2 t-1 ( 1 t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  1 t a 32  3 t-1 ( t a 22  2 t-1 +  1 t a 32  3 t-1 ) +  2 t b 22  2 t-1 ( 2 t b 22  2 t-1 +  2 t b 32  3 t-1 ) +  2 t b 32  3 t-1 ( t b 22  2 t-1 +  2 t b 32  3 t-1 ) + f 22 ( 2 t f 22 h 22 t-1 +  2 tf 32 h 23 t-1 ) + g 22 ( 1 t g 22 h 22 t-1 +  1 t g 32 h 23 t-1 ) + f 32 ( 2 t f 22 h 23 t-1 +  2 t f 32 h 33 t-1 ) + g 32 ( 1 t g 22 h 23 t-1 +  1 t g 32 h 33 t-1 )  1 t a 22  2 t-1 ( 1 t a 11  1 t-1 +  1 t a 21  2 t-1 +  1 t a 31  3 t-1

	h 22 t =  1 t 2 + h 33 t =  1 t 2 c 12 2 +  1 t 2 c 22 +  2 t 2 d 12 2 +  2 t 2 d 22 2 c 13 2 +  1 t 2 c +  1 t 2 c 33 2 +  2 t 2 d 13 2 +  2 t	2 d 23 2 +  2 t	2 d 33 2 +  1 t	2 a 33 2  3 t-1	2
	+  2 t	2 b 33	2  3 t-1	2 +  2 t f 33	2 h 33 t-1 +  1 t g 33 2 h 33 t-1
	h 12 t =  1 t	2 c 11 c 12 +  2 t	2 d 11 d 12 +

The discrepancy between IBOR and REPO from which is substracted the CDS discrepancy also helps to measure the liquidity premium. The liquidity premium thus obtained is very close to the IBOR-OIS discrepancy that we have adopted in this study.(cf. ECB, 2008, p. 144)

For an analysis of the Euro Area money market we may refer to the article published by the ECB in February 2009.

1 , t 1

, t 1

, t 1 2 , t 2 2 , t 2 3 , t 1 3 , t 2 3 , t 3 3 , t h h h


Loic Zussa
email: loic.zussa@mines-stetienne.fr

Jean-Max Dutertre
email: jean-max.dutertre@mines-stetienne.fr

Jessy Clediere
email: jessy.clediere@cea.fr

Bruno Robisson
email: bruno.robisson@cea.fr

Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter

Power supply underpowering and negative power supply glitches are commonly used for the purpose of injecting faults into secure circuits. The related fault injection mechanism has been extensively studied: it is based on setup time violations. Positive power supply glitches are also used to inject faults. However, an increase of the supply voltage is not consistent with a mechanism based on setup time violation. Besides, no research work has yet identified the corresponding mechanism. In this work, we report the use of an embedded delay-meter to monitor the core voltage of a programmable device exposed to power supply glitches. It permitted us to gain a further insight into the mechanism associated with power glitches and also to identify the injection mechanism of positive power supply glitches.

I. INTRODUCTION

Secure circuits are targeted by a wide range of physical attacks. Among these are fault attacks (FA) based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. Fault injection (FI) may be performed thanks to several means: laser shots, overclocking, underpowering, temperature increase, power supply glitches or electromagnetic pulses. A fine understanding of the properties and the mechanisms involved with these FI techniques is of high interest to evaluate the related threats and also to facilitate the design of counter-measures.

Laser FI has a specific mechanism that is well known. Whereas FI based on setup time violations [START_REF] Selmane | Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks[END_REF], [START_REF] Zussa | Investigation of timing constraints violation as a fault injection means[END_REF] may be obtained by various techniques: overclocking , underpowering [START_REF] Selmane | Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks[END_REF], temperature increase, clock and negative power supply glitches, and to a certain extent EM pulses. The latter FI techniques are linked to an increase of the target's propagation delays over its clock period (see section II).

Positive power supply glitches, despite being a practical fault injection means [START_REF] Hutter | Contact-based fault injections and power analysis on rfid tags[END_REF], have been less studied. It can not be explained by a setup time violation because a voltage increase will lead to a decrease of the target's propagation times, which is inconsistent with this hypothesis. Its FI mechanism has not yet been ascertained.

In this paper, we report the use of a digital delay-meter embedded in a programmable device (FPGA) as presented in [START_REF] Zick | Sensing nanosecond-scale voltage attacks and natural transients in fpgas[END_REF] and [START_REF] Bowman | All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control[END_REF] for the purpose of identifying the fault injection mechanism related to positive power supply glitches. It allowed us to monitor the core voltage of the device when exposed to positive and negative power supply glitches. It also made it possible to correlate the perturbations induced on the target's core voltage with the faults injected into an implementation of the advanced encryption standard (AES [START_REF]Announcing the advanced encryption standard (aes)[END_REF]). Our contributions to that research field are:

• An illustration of the use of a delay-meter to monitor the core voltage of a circuit exposed to power supply glitches,

• An identification of the fault injection mechanism related to positive power supply glitches,

• An in-depth experimental study of the practice of FI with power supply glitches. This article is organized as follows. In section II, a reminder of timing constraints and an explanation of how faults may be injected by their violation is provided. In section III, the architecture and principles of the delay-meter used as an on-chip voltmeter are described. The experimental setup is described in section IV. The obtained experimental results are presented and analyzed in section V. Finally, our findings are summarized in section VI with some perspectives.

II. PRELIMINARIES

In this section the basics of timing constraints are summarized. Then the mechanism of fault injection through timing constraint violations is reviewed.

A. Timing constraints

Almost all digital ICs use a common clock signal to synchronize their internal operations. Fig. 1 On a clock rising edge, data are released from the upstream DFF after a delay D clk2q which represents the delay between the clock rising edge and the actual update of a register's output. Then, these data are processed through the logic before being latched into the next register on the next clock rising edge. The data propagation time, D p(data) , through the logic is not constant. It depends on the handled data (those of the current and previous clock periods) and also on the power supply voltage. D pM ax is the longest propagation time (i.e. the logic critical time).

A proper functioning of a DFF requires its input to be stable all along a time window that extends before and after the clock rising edge from the setup (T setup ) and hold (T hold ) times respectively. The data shall not arrive too late nor too early. This arrival constraints can be described mathematically with two timing constraint equations: the setup time timing constraint expressed in eq. 1 and the hold time timing constraint expressed in eq. 2 [START_REF] Rabaey | Digital Integrated Circuits[END_REF].

T clk > D clk2q + D pM ax + T setup -T skew (1)
T hold < D clk2q + D pM in + T skew (2)
where T skew is the slight phase difference that may exist between the clock signals at the clock inputs of two different registers due to the clock propagation times through the clock network, and D pM in is the minimal propagation time through the logic.

B. Fault injection due to timing constraints violations

The violation of these timing constraints is a means to inject faults into synchronous integrated circuits (IC).

Previous studies have shown how underpowering a synchronous circuit leads to setup time violations [START_REF] Selmane | Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks[END_REF], [START_REF] Zussa | Investigation of timing constraints violation as a fault injection means[END_REF], [START_REF] Barenghi | Low voltage fault attacks to aes[END_REF]. As the target's supply voltage is decreased, the propagation times through its logic are increased. Consequently, a violation of the setup time constraint may happen when the propagation time increase is large enough: thus a fault is induced. Fig. 2(a) illustrates the effect of underpowering an IC implementing the AES algorithm (its nominal voltage and clock period are 1.2V and 10ns respectively). The critical times of the AES' rounds at nominal voltage are depicted in white on the upper curve (they are obviously shorter than the clock period in order to comply with the setup time constraint). The bottom curve represents the decrease of the target's core voltage (i.e. the underpowering). As a result, the critical times of the whole AES' rounds are increased (depicted in grey). In this illustration a setup time violation occurs during the 9 th round.

Fig. 2(b) illustrates the effect of a negative power supply glitch: the critical time of the round centered on the glitch (and also those of its neighbors rounds) is increased. As a result, the setup time violation occurs during the 6 th round. This allows an attacker to target a given round, which is mandatory to perform a successful differential fault attack [START_REF] Barenghi | Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures[END_REF]. Fig. 2(c) illustrates the effect of an increase of the target's core voltage (i.e. overpowering): its critical times are decreased (depicted with grey stripes). No faults were obtained because there were neither setup time nor hold time violations (for the latter, the rounds' propagation times are too large). Note that the illustrations of Fig. 2 are based on actual experiments. We were not able to inject faults into the AES' computations by overpowering. However, faults may be injected in the parts an IC which has very small propagation times: e.g. a shift register.

Nevertheless, we have successfully injected faults into the AES' computations using positive power supply glitches. According to the previous examples, the related FI mechanism seemed unlikely to be due to setup or hold time violations. It was the main motivation of our work: sensing the core voltage of an IC when exposed to voltage glitches in order to find out the relevant FI mechanism.

III. VOLTMETER DESIGN

Previous experiments [START_REF] Zussa | Investigation of timing constraints violation as a fault injection means[END_REF] on the IC used to carry out the experimental part of this paper showed that the propagation times of the IC logic vary linearly with its power supply voltage. Consequently, measuring the delay of a logic block reveals its supply voltage value. Thus, for the purpose of monitoring the core voltage of an IC exposed to power glitches, we designed a delay-meter (the so-called voltmeter). Note that this technique has already been introduced and validated by K. Zick et al. [START_REF] Zick | Sensing nanosecond-scale voltage attacks and natural transients in fpgas[END_REF].

Fig. 3 shows the simplified architecture of the delay-meter. It is made out of two blocks:

• a delay block for which the delay depends on the IC's core voltage,

• a time-to-digital converter (TDC [START_REF] Dudek | A high-resolution cmos time-to-digital converter utilizing a vernier delay line[END_REF]) used to obtain a binary code correlated with the delay. The input of the delay-meter is the clock signal of the device (clk). It is fed into the delay block to produce a delayed clock, clk delay(0) . The corresponding delay, delay(V dd), depends on its supply voltage V dd. Then, the TDC is used to convert the phase difference between clk and clk delay(0) into a binary code. The TDC consists of a series of 8 delay elements (their elementary delay is δd). Its input is the delayed clock clk delay(0) . Thus, it provides 8 delayed clocks with an additional delay: n * δd, where n is the index of the corresponding delay element. Then, 8 DFFs are used to compare the phases of the delayed clocks with the main clock clk. The output of the n th DFF is low, resp. high, when clk delay(n) is in phase advance, resp. in phase delay, with respect to clk. As a result, the outputs of the DFFs form an 8-bit vector, which depends on delay(V dd) ([4], [START_REF] Dudek | A high-resolution cmos time-to-digital converter utilizing a vernier delay line[END_REF]). The right-hand side of Fig. 3 illustrates the obtained output vectors for different settings of the core voltage. As V dd varies, the phase shift between the clock signals also varies leading to a change in the TDC's output vector. The obtained binary code is a thermometer code: it consists in 2 blocks of consecutive "0" and "1". The information it contains is twofold:

• its Hamming Weight (HW),

• the order of these blocks to differentiate e.g. "000111" and "111000". Thus, to take into account both these pieces of information, we used the notion of Signed Hamming Weight (SHW): e.g. "00000111" and "11100000" were respectively denoted "+3" and "-3" (see also Fig. 3). We used 4 instances of the previous delay-meter (with different delay blocks) to build a voltmeter with a proper voltage measurement range and resolution: 0.7V to 2.4V and around 20mV respectively. Note that the voltage resolution was not constant over the whole measurement range. Fig. 4 displays its SHW output as a function of the core voltage. The device embedding the voltmeter was exposed to static voltage underpowering to gather the measures used to build this curve. The bijective function corresponding to this curve was used hereafter to convert the output vectors of the voltmeter into a voltage; despite the fact that the corresponding experiments were carried out with dynamic perturbations (i.e. glitches).

TDC delay0 delay2 D Q delay8 delay7 D Q 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 D Q D Q D Q D Q D Q D Q 2

IV. EXPERIMENTAL SETUP

In this study we used two different setups, a voltmeter and an AES, embedded alternately in the same test vehicle: a programmable circuit (FPGA -Xilinx Spartan3 700A).

A. Pulse generator

We used an Agilent 8114A pulse generator to inject power supply glitches into our test vehicle. This pulse generator is able to produce positive or negative voltage pulses in the 1V to 50V range, with constant fall and rise times equal to 10ns and a tunable pulse width between 10ns and 100ms. The voltage pulse is centered on a tunable DC voltage. We used this feature to provide the voltage supply of the test chip and also to set and modify at will its value.

B. Voltmeter setup

This subsection presents the first FPGA setup used to sense its core voltage when exposed to power supply glitches. The voltmeter introduced in section III is well suited to measure a static voltage. Its output is updated at the rate of its clock signal. Its period is 5ns. In order to monitor a transient perturbation (i.e. a voltage glitch), a 30 stage shift register (SR) with an 8-bit width was connected to its output. It makes it possible to register the core voltage over a 150ns range with a 5ns time resolution (it was not feasible to further increase the length of the SR because of design and practical constraints).

Because the FPGA and the pulse generator were synchronized thanks to a common trigger signal, we were able to extend this time window by carrying out the measurements at different times for identical settings (i.e. the voltage pulse parameters). The measurements were carried out over a global time range of 750ns by dividing it in time slots of 150ns. Moreover, during each time slot the experiments were reproduced 5 times with a successive time increment of 1ns. Hence, the time resolution was upgraded to 1ns. In addition, all these measurements were conducted three times and then averaged.

Note also that, many of the voltage glitch injection experiments were performed with a core voltage set over the FPGA nominal voltage of 1.2V. In order to center the glitch within the voltmeter's best achievable resolution range and thus to obtain accurate measurements (this was the case for the curves displayed in section V).

C. Fault injection setup

This subsection presents the second FPGA setup used to inject faults and verify our assumptions about the fault injection mechanisms. The target is a hardware 128-bit AES designed to operate at a 10ns clock period and to complete a whole encryption in 11 clock cycles. In this work, the 128-bit AES ( [START_REF]Announcing the advanced encryption standard (aes)[END_REF]) is mainly used as a test element. Thus, we will not go deeper into its properties. However, because this algorithm is likely to be subject to FA, the obtained results are still of interest.

We used the following methodology to induce faults into the AES' calculations: we kept constant the pulse amplitude (either positive or negative) and width settings while varying both the core voltage provided by the pulse generator to the test chip and the starting time of the pulse. At first, the core voltage was set over its nominal voltage and then progressively decreased until a first fault was induced. The starting time of the pulse was also swept along a time range encompassing the whole AES in order to target all its rounds. Then, other pulse amplitude and width settings were tested according to the same methodology.

V. EXPERIMENTAL RESULTS

First, we performed both negative and positive power supply glitches with a pulse width varying from 10ns to 500ns and an amplitude varying from 1V to 50V. During these injections the core voltage of the FPGA was observed with the on-chip voltmeter. Then, these obtained waveforms were analyzed and an assumption about the fault injection mechanism related to positive power supply glitches was made. Second, we verified this assumption by targeting an AES with relevant positive and negative power supply glitches.

A. Negative power supply glitch effects on the core voltage 1) Observations:

The first injection experiments with negative voltage glitches were carried out on the voltmeter. We observed two sets of damping oscillations corresponding to the falling and rising edges of the injected voltage pulse. As an example, Fig. 5 displays the FPGA core voltage (measured with the on-chip voltmeter) for a voltage pulse of -14V amplitude and 400ns duration. The time interval between the 2 sets of damping oscillations is 400ns, which is also the time interval between the falling and rising edges of the power glitch. The first negative oscillation after the perturbation's falling edge is the biggest: its amplitude is close to 400mV and its width at the oscillation's tip is around 20ns. Similar shapes for the core voltage were measured for other settings of the pulse's parameters. Analyzing the obtained core voltage shapes, we drew the assumption that the first negative oscillation following the pulse's falling edge was well suited to induce faults into an IC: it might be used according to the principle depicted in Fig. 2(b). Fault injection is a result of setup time violations induced by a transient underpowering of the target corresponding to the oscillation width.

2) Fault injection: Consequently, the 2 nd set of experiments was performed on the AES setup (see subsection IV-C) with a (400ns, -14V) pulse. The moment of the negative oscillation's tip was swept over the AES' rounds. Moreover, for each time location, the DC component of the glitch was gradually decreased from 1.7V until the injection of the first faults. As a result, the voltage of the oscillation tip went under the target's nominal voltage (1.2V) inducing a setup time violation.

This methodology made it possible to inject faults into every AES round (except the first one). We also verified that the faulted rounds always corresponded with the time location of the oscillation tip. Most of the induced faults were single-bit faults affecting only one round. For the sake of brevity, these results are not detailed here. However, subsection V-C4 reports very similar results.

B. Positive power supply glitch effects on the core voltage

1) Observations: Fig. 6 displays the FPGA's core voltage measured with the voltmeter when exposed to a positive power supply glitch. Its duration and amplitude were 400ns and +14V respectively. The induced core voltage perturbation is very similar to that induced by a negative voltage pulse (see Fig. 5), except that the damping oscillation sets corresponding to the falling and rising edges are inverted. Similar shapes were obtained with close settings of the voltage pulse. The main result of these experiments is that a positive power supply glitch induces negative transient voltage modifications under its DC component. For the experiment reported in Fig. 6, the second oscillation (corresponding to the rising edge of the pulse) has a voltage at its tip end which is 300mV under its DC component. Moreover, this transient underpowering has a duration around 20ns at its tip, which seems well suited to target the rounds of our AES setup.

From the observation of Fig. 6, we drew the counterintuitive assumption that a positive power supply glitch may create setup time constraint violations because of the induced negative oscillations. The following experiments were meant to ascertain this assumption.

2) Fault injection: Fault injection experiments with a positive power supply glitch (400ns, +14V) were then carried out on the AES setup. The injection time of the voltage pulse was varied in order to sweep the whole AES' rounds with the tip of the second oscillation which is negative. For each time location, the DC component of the glitch was gradually decreased from 1.7V until the injection of the first faults. Following this methodology we succeeded in injecting faults into the various rounds of the AES' calculations. For a given dataset (i.e. the plaintext and key used for the AES encryption), the injected faults were equal to the faults induced with negative power supply glitches. Moreover, the faulted rounds always corresponded to the time location of the negative oscillation tip end. This is an experimental proof that the faults injected with positive power supply glitches are due to setup time violations created by the negative oscillations induced by the voltage pulse edges.

C. Further results

According to the previous experiments the pulse width value had no significant effect on the induced voltage perturbations. The main parameters influencing fault injection were the pulse amplitude and DC component values. However, with proper width settings, the oscillation sets will overlap creating offsetting, addition, or sharping effects which may facilitate FI.

1) Offsetting: For a negative voltage pulse with a width equal to the period of the damping oscillation sets, an offsetting effect arises. It consists in offsetting the 2 nd negative oscillation induced by the falling edge of the pulse with the 1 st positive oscillation of its rising edge. Offsetting allows us to avoid injecting extra faults during the erased oscillation. Fig. 7(a) displays the obtained core voltage perturbations for a (100ns, -14V) pulse.

2) Addition: The addition effect of a (50ns, +8V) positive voltage glitch is given in Fig. 7(b), where the 50ns width corresponds to the oscillations half-period. As a result, the amplitude of the 1 st negative oscillation is increased by addition of the 1 st negative oscillation of the 2 nd set: a 400mV amplitude is obtained for an 8V pulse amplitude whereas a 14V amplitude was required without an addition effect (see Fig. 7(a)).

3) Sharping: Fig. 7(c) illustrates the sharping effect for a (10ns, -22V) pulse. It consists in a partial overlap of the 1 st oscillation induced by the glitch falling and rising edges in order to thin down the faulting negative oscillation. The sharping effect increases the resolution of FI at the expense of its amplitude: the width of the oscillation tip end is decreased to approximately 10ns, while an increase of the pulse amplitude to 22V was required to obtain an oscillation amplitude of 400mV (as obtained in Fig. 7(a) and 7(b) for pulse amplitude of 14V and 8V resp.).

4) Fault injection: The (100ns, -14V), (50ns, +8V) and (10ns, -22V) pulses used to illustrate the offsetting, addition and sharping effects were then applied to the AES setup for FI characterization (the same data were used during the following experiments). All AES' rounds were targeted by sweeping the time of the negative oscillation tip end over a large time window. For each time step, an increasing stress was applied to successive encryptions by decreasing step by step the DC component of the voltage glitch from 1.7V until a first fault appears. It made it possible to draw a time map of the fault sensitivity threshold of the AES rounds as displayed in Fig. 8(a), 8(b) and 8(c) (the fault sensitivity threshold is expressed as the pulse voltage DC component maximal value inducing faults). The obtained voltage sensitivity shapes are very similar, which was expected because the faulting oscillations have a same oscillation amplitude of 400mV. They differ in time because their respective oscillation tips have different timing w.r.t. the synchronization signal.

The sharped oscillation of Fig. 7(a) achieved the best time resolution: single-bit faults were injected into the whole AES' rounds (except the 1 st one). Whereas the broader negative oscillations induces by the (100ns, -14V) and (50ns, +8V) pulses did not succeed in faulting the 6 th round (the time sensitivity windows of the 5 th and 7 th rounds were accordingly expanded as depicted in Fig. 8(a) and 8(b)).

During these three sets of experiments the faults injected in the same AES round were identical. This proves again that the FI mechanism related to both negative and positive power supply glitches is the same.

VI. CONCLUSION

In this paper we presented an on-chip delay-based voltmeter. This voltmeter was used to monitor the FPGA core voltage when exposed to power supply glitches. It revealed the induction of two damping oscillation sets inside the target corresponding to the falling and rising edges of the voltage glitch. It also permits us to correlate FI with the tip ends of negative oscillations. Moreover, because the faults injected with negative and positive voltage glitches were identical (and because the FI mechanism of negative voltage glitches was already established to be linked to setup time violations), it demonstrates on a practical basis that the FI mechanism of positive voltage glitches is related to setup time violations. Various techniques of glitch shaping were also introduced that may enhance the efficiency of FI. Designers of secure devices shall be aware that such voltage glitches make it possible to inject single-bit faults with very good timing accuracy.

One interesting consequence of this finding, is that the counter-measures designed to thwart negative power supply glitches should also be effective to defeat FI attempts with positive supply glitches. This will be investigated through further research work.

  illustrates the corresponding architecture. Data are computed by combinatorial logic (marked ) surrounded upstream and downstream by register banks made of D flip-flops (DFF) sharing the same clock signal (clk).

Fig. 1 .

 1 Fig. 1. Internal architecture of digital ICs.

Fig. 2 .

 2 Fig. 2. Critical paths of the AES' rounds when subject to: (a) underpowering, (b) a negative power supply glitch, (c) overpowering.

Fig. 3 .

 3 Fig. 3. Simplified architecture of the delay-meter (i.e. voltmeter).

Fig. 4 .

 4 Fig. 4. TDC outputs vs. core voltage.

Fig. 5 .

 5 Fig. 5. Core voltage of the FPGA for a (400ns , -14V) power supply glitch.

Fig. 6 .

 6 Fig. 6. Core voltage of the FPGA for a (400ns , +14V) power supply glitch.

Fig. 7 .

 7 Fig. 7. Core voltage curves of the FPGA for various pulse settings.

Fig. 8 .

 8 Fig. 8. Faulted AES' rounds for various pulse DC component and time settings.