J M Dutertre
email: dutertre@lirmm.fr

F M Roche
email: roche@lirmm.fr

Robustness of CMOS Circuits Designed for Space and Terrestrial Environment

The behaviour of Integrated Circuits (IC), in Space, the high atmosphere or even in earth environment, are adversely affected by radiation. One of the most concerning effect is stochastic, caused by heavy ions of high energy which cannot be shielded. Striking the circuits, the invasive particles induce transient current upsets, being the cause of unpredictable soft errors in combinatorial logic and memory cells. After a brief survey of the phenomenon and its consequences, we report a strategy to improve the hardening capabilities of a standard commercial technology only using a design methodology. We present a new inverter architecture for which robustness is naturally attained during upset. The hardening is carried out through the use of an integrated information redundancy and a double tristate output. The design prevents errors to propagate and gives an uncorrupted information source. Post layout SPICE simulations of the cells confirm the efficiency of our integrated approach to avoid the induced effect of a pulse shape current generation inside the IC.

Introduction

The robustness of Integrated Circuits dedicated to Space has been the object of a considerable amount of attention since the first unexplained failure of satellite due to solar eruptions and unpredictable cosmic rays [START_REF] Binder | Satellite Anomalies from Galactic Cosmic Rays[END_REF][START_REF]Analysis of Environmentally Induced Spacecraft Anomalies[END_REF][START_REF] O'neil | Single event upsets for space shuttle flights of new general purpose computer memories devices[END_REF]. At this point the problems seemed confined to the space and high atmosphere. Nevertheless, since the works of IBM reporting soft fails in terrestrial computer electronics [START_REF] Ziegler | IBM experiments in soft fails in computer electronics[END_REF][START_REF] Normand | Single event upset at ground level[END_REF], the question became a real priority problem for the circuits dedicated to secure systems or to insure watching functions. Optimising reliability is a challenge for example in aeronautics or medical applications. This question is getting an increasing weight with the regular reductions of scale, voltage and power in the new technologies. The situation is still magnified by economical reasons: the founders being unable to maintain in production an old but verified rad-hardened technology for few components. With systems for which the functional outcome is essential, a redundancy at the system level is generally considered. This increases -more than three times -silicon area, cost and energy consumption of the systems, while the trends are precisely to reduce it with systems on chip. We propose to use a methodology integrating the hardening and redundancy properties at the design level, taking into account the degradation phenomenon. We present a new inverter architecture compatible with the highly submicronic technology and its superimposed metal layers. In the following we introduce the different phenomena and focus the study on an effect due to external particles impinging the device. We analyse the degradation of the signal and propose a new inverter cell designed to prevent error propagation.

Phenomenon and the sensitive areas

Different radiation effects can take place in ICs. The Total Ionizing Dose effects ( TID ) due to charge in oxides which can cause threshold voltage shift and current leakage. The Single Event Effects ( SEE ) induced by a single particle hit in a sensitive area, effects not determinist : among these effects, the Single Event Latch-Up ( SEL ) and the Single Event Upset ( SEU ). The SEL is a destructive effect through parasitic thyristor activation while the SEU results in transient current pulse upset on sensitive nodes. Presently, we shall not address TID or SEL corrected by adequate process techniques but the SEU effect which represents a radiation-induced hazard difficult to avoid. Afterwards we shall provide some brief background in the area of SEU mechanisms and describe their implications. Some more details will be found in [START_REF] Peterson | Single Event Analysis and Prediction[END_REF][START_REF] Massengill | SEU Modeling and Prediction Techniques[END_REF][START_REF] Sexton | Measurement of Single-Event Phenomena in Devices and ICs[END_REF]. Three basic concepts explain SEU: energy loss, charge collection and transient upset. When an energetic ion passes through any material it loses energy through interaction with the semiconductor bound electrons. It creates a dense track of holeelectron pairs, which may recombine with no effect. But in the presence of electric fields, typically in reverse biased P-N junction, electrons and holes are drifted in opposite directions and collected at device junctions. The consequence is a transient current pulse. Such an upset drives the drain voltage of PMOS or NMOS respectively to the high or low level. Considering an inverter, the sensitive area is The resulting voltage transient determines a logic upset being indistinguishable from common signal. So, the logic upset can propagate through for example combinatorial logic, clock or control lines and causes bit flip soft errors.

Because of the random nature of the particle, the effect observed is unpredictable and can not be "tested". So, the hardening must be anticipated on a worst case basis. Fortunately we have to take into consideration the low frequency of the upset, due to the very low value of the particle flux. We shall assume that just one upset can happen at the same time and in the same sensitive area, excluding the case of multiple upsets. The post lay-out SPICE simulation will be conducted using a pulse current source to emulate the SEU at the sensitive node. The simulation can reproduce a charge equal from two to three times the worst event generally observed. The current pulse is fixed at a 10 mA amplitude, 50 ps rise and fall times and a programmable duration.

Inverters chain simulation

In this section, we present the post layout SEU simulations of an inverters chain (Fig. 2). Parasitic capacitance extraction was conducted after the circuit was designed using ST Microelectronics 0.25 µm CMOS process. The broken arrow indicates the location of the upset. The results are illustrated on the Fig 3 . As expected the standard inverters are very sensitive to upsets. As soon as the perturbation is exceeding a 100 ps duration, which is common, any upset at node Q1 will be propagated up to the output at the extremity of the chain. The current I alea injected on node Q1 to emulate upset results in driving this node to low level during the whole upset duration. The transient voltage is propagating through the three inverters to the output node (see Fig. 3 ). Mavis et al [START_REF] Mavis | Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits[END_REF] have shown that even with a larger number of inverters the perturbation will propagate unattenuated. Similar result occurs for upset to high level. When used into ICs general Clock and Data lines, such inverters need to have the integrity of their signal preserved across the whole circuit. Thus upset propagation along inverters chains is a main issue when hardening . In the next section, a SEU hardened design to cope with this outcome will be detailed.

The SEU hardened HZ inverter

A. Description

Some hardened CMOS inverters have been presented in the past few years [START_REF] Canaris | An SEU Immune Logic Family, 3rd[END_REF][START_REF] Wiseman | Design and Testing of SEU/SEL Immune Memory and Logic Circuits in a Commercial CMOS Process[END_REF][START_REF] Velazco | Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits[END_REF][START_REF] Salager | Conception en vue du Durcissement des Circuits Intégrés numériques aux effets radiatifs[END_REF][START_REF] Monnier | Flip-flop Hardening for Space Applications[END_REF][START_REF] Roche | A design methodology to secure memories in Space environnement[END_REF]. We propose here a new design which on a simulation basis can be advantageously compared with the previous issues. Hereafter, the hardening is completed through the use of two techniques: an information redundancy and a tristate double-output, respectively for protecting the information and preventing an error propagation. ( Fig. 4). If the two inputs have the same logic level, the circuit works like an inverter, with the two outputs established in the complementary logic state. The truth table ( Table 1 ) makes this point obvious, and the fact that as soon as the inputs have not the same status, the outputs are switched onto a high impedance state. So, if a single transient arises from anyone of the inputs, it acts turning the HZ inverter outputs in the high impedance status, preserving the logic state and stopping upset propagation. This design has been named HZ-Inverter with reference to this high impedance status.

In 1 In 2 Out 1 Out 2 0 0 1 1 0 1 H Z H Z 1 0 H Z H Z 1 1 0 0 Table 1. Truth table
Alike the standard inverter, the HZ-Inverter has its SEUs sensitive areas located on the OFF-transistor drains ( Fig. 5 ).

B. Simulation of an HZ inverters chain

A layout of HZ-Inverters is completed with the same CMOS process. The parasitic capacitance is extracted and SPICE simulations run to verify functionality and hardening capabilities. For comparison purpose, a chain of four inverters is used ( Fig. 6 ). The broken arrow indicates the nodes ( Q1 and Q11 ) where the upsets are simulated. Various pulse durations are applied. The Figure 7 illustrates the effect of an upset on node Q1 for a 2000 ps pulse. Upset drives the Q1 node voltage to low level, while node Q11 undergoes only a negligible voltage perturbation; its state remains high. Nodes Q22, Q33 and Out2 voltages were not drawn as they are respectively the same than the nodes Q2, Q3 and Out1 voltages. The little increase of Q2 (and Q22) voltage is not sufficient to flip the third inverter of the chain. These simulations show that even an upset of 2000 ps duration and 10 mA amplitude on node Q1 will not propagate. This duration is far beyond the specifications of a realistic SEU. All the upsets susceptible to exist on nodes Q1 and Q11 from 1 to 0 and 0 to 1 have been simulated and they do not propagate until a 3500 ps duration, which is out of the realistic conditions. This proves the efficient robustness of the HZ inverter. When used in global clock or data lines it will prevent the upset propagation across the whole circuit, as we shall see now.

C. Performance of the HZ inverters chain

So consider the previous HZ-Inverter set as a Clockline with a 200 MHz signal frequency and submitted to successive upsets during the static and dynamic regimes. The Figure 8 illustrates the better and the worst cases: A 500 ps pulse during the static regime and a 500 ps pulse during the rising edge transition. The first perturbation is completely absorbed preserving the integrity of the Clock. The second perturbation induces just a delay in the signal transmission. In the both cases, no untimely effect is observed while Standard circuit will exhibit glitches in the same conditions. So if care is taken in design to set-up and hold times, no adverse effect on the IC functionality will be efficient The major drawback of the HZ inverter is its area compare to standard inverter area. The Figure 8 gives the layouts respectively of the standard inverter and the HZ inverter for comparison purpose. Another object of concern is the cell area. The HZ inverter area is 45 µm², about twice and half the standard inverter area which is 18 µm².But the area must be compared to a corresponding redundant circuit including three Standard inverters and the voter, wich consumes a large area. Excluding the hardening of the voter the area of the standard redundant circuit can be estimated to more than the double of the HZ inverters equivalent.

CONCLUSION.

In this paper we have presented the use of design techniques to solve the SEU hardening problem. They only apply to design at circuit level, therefore no fabrication process development is required. The HZ-Inverter proposed exhibits a very efficient hardness to SEU propagation, as SPICE simulations show. One major interest of this cell is its ability to be easily integrated in design where a dual and sequential transfer of the level is not a challenge. It will be worthy in IC for which absolute hardness assurance against upset is required.

XVIFig. 1

 1 Fig. 1 Location of the inverter SEU sensitive areas.

Fig. 2

 2 Fig. 2 Upset location on the inverters chain

Fig. 3

 3 Fig. 3 Upset propagation through inverters chain.

Fig. 4

 4 Fig. 4 HZ inverter design.

Fig. 5

 5 Fig. 5 HZ-Inverter sensitive area according nodes voltage SEU may arise on only one sensitive node at the same time ( out1 or out2 ), however its propagation will be impossible in a chain of HZ inverters as the following simulations show.

Fig. 6

 6 Fig.6HZ inverters chain and upset location.

Fig. 7

 7 Fig. 7 Simulation of a 2000 ps upset on node Q1

Fig. 8

 8 Fig. 8 SEUs on hardened Clock line.

Fig. 9

 9 Fig. 9 Layout of the classic and HZ inverters.


Abstract--The purpose of this work is to present one investigation utilizing a pulsed laser as a tool to improve the Single Event Upset tolerance of a memory cell. These results coming with a previous ion testing evaluation of the circuit allow an optimization of the design. The laser results permit a more detailed analysis of the phenomenon leading to the upset and a precise localization of the most sensitive areas. As a result the behavior verification of the design combined with the use of robust elementary blocks strengthens the hardening capabilities of the cell.

I. INTRODUCTION

In the past a considerable amount of efforts has been directed towards the improvement of the SEU rad tolerance of SRAMs [START_REF] Rockett | A SEU Hardened CMOS Data Latch Design[END_REF][START_REF] Axness | Single Event Upset in Irradiated 16k CMOS SRAMs[END_REF][START_REF] Kohler | SEU Characterisation of Hardened CMOS SRAMs Using Statistical Analysis of Feedback Delay in Memory Cells[END_REF][START_REF] Sexton | SEU Simulation and Testing of Resistor-Hardened D-latches in the SA3300 Microprocessor[END_REF][START_REF] Koga | On the Suitability of non-Hardened High Density SRAMs for Space Applications[END_REF][START_REF] Wiseman | Design and Testing of SEU/SEL Immune Memory and Logic Circuits in a Commercial CMOS Process[END_REF][START_REF] Velazco | Two CMOS Memory Cells Suitable for the Design of SEU Tolerant VLSI Circuits[END_REF][START_REF] Monnier | Flip-flop Hardening for Space Applications[END_REF] or basic devices for combinational logic [START_REF] Baze | A Digital CMOS Design Technique for SEU Hardening[END_REF]. The topic is still of interest due to a size scaling of the commercial technology. Furthermore the pulsed laser tool has become mature to collect information about the Single Event Upset (SEU) behavior of a wide range of integrated circuits [START_REF] Velazco | SEU-Hardened Cell Validation Using a Pulsed Laser[END_REF]. The advantages of this technique have been exhaustively studied and detailed in particular by Melinger, Buchner, McMorrow of NRL and other teams [START_REF] Melinger | Critical Evaluation of the Pulsed Laser Method for Single Event Effects Testing and Fundamental Studies[END_REF][START_REF] Buchner | Implications of the Spatial Dependence of the Single-Event-Upset Threshold in SRAMS Measured with a Pulsed Laser[END_REF][START_REF] Buchner | Laboratory Tests for Single-Event Effects[END_REF][START_REF] Mcmorrow | Application of Pulsed Laser for Evaluation and Optimization of SEU-Hard Designs[END_REF][START_REF] Duzellier | Application of Laser Testing in Study of SEE Mechanisms in 16-Mbit DRAMs[END_REF]. With the object of improving the circuit hardness assurance, one of the main benefit of the laser use is the ability to locate the sensitive area -and consequently the electric node involved -in a deterministic way compared to the random nature of upsets induced by ions during synchrotron experiments. As a consequence, this tool of investigation brings convenience, consistence and repeatability .

In this paper we report on a set of experiments performed at the IXL Laboratory using laser facilities to determine the threshold sensitivity of chips previously evaluated in particles accelerator. The circuits presented hereafter have a flip-flop configuration and are fabricated in a commercial unhardened CMOS 0.7 m technology. The tests described in this paper P. Fouillat is with the IXL, Bordeaux FRANCE (e-mail: fouillat@ixl.ubordeaux.fr).

D. Lewis is with the IXL, Bordeaux FRANCE (e-mail: lewis@ixl.ubordeaux.fr).

are part of a library design optimization (on this subject the reader could refer to the chart of McMorrow et al. [START_REF] Mcmorrow | Application of Pulsed Laser for Evaluation and Optimization of SEU-Hard Designs[END_REF]). The laser is used to draw up a map revealing the threshold location. Then the upset mechanisms and the sensitive nodes are identified making possible an adjustment of the design parameters for improving hardness assurance.

II. METHOD

A. Device Description

The test vehicle consists of twelve independent shift registers. Each of them combine a set of 40 D-latches organized into 20 flip-flops [START_REF] Monnier | SEU Testing of a Novel Hardened Register Implemented Using Standard CMOS Technology[END_REF]. Half of the registers are designed with CMOS standard cell D-latches (Fig. 1), the other half with rad tolerant ones (Fig. 2). The two latches form the memory cells of the flip-flop. An examination of these cells at transistor level allows us to locate the specific design areas that are SEU sensitive when exposed to the hit of an energetic particle. These areas match the reverse biased junctions of both the access transistors and the memory latches. Their locations change according to the logic state of the nodes. Summarizing, PMOS junctions at low level are liable to be driven to high voltage when hit by energetic ions ( respectively NMOS junctions at high level are In the following, to give a simple description of the logic "status" of the nodes a standard D-Latch will be said in the state 1 if Qi=Gi=1 with Qbi=0, and in the state 0 when Qi=Gi=0 with Qbi=1. In a similar way a rad hardened latch will be said in the states 1 and 0 respectively if Qi=Gi=1with Qbi=Gbi=0, and if Qi=Gi=0 with Qbi=Gbi=1.

SEU sensitive node for state 1.

SEU sensitivenode for state 0. To achieve SEU hardness this last cell combines two distinct techniques : a RC filtering and a switching into a high impedance state. The RC filtering prevents the feedback loop from causing a bit flip in case of an upset on nodes Qi and Qbi. The circuit-switching into a high impedance state also prevents any transient bit flip from stabilizing. As a matter of fact, when the node Gi ( Gbi ) storing a 1 is upset to 0, Qbi ( Qi ) is brought into a high impedance state ; so, its logic state is kept safe during the disturbance, then the Gi ( Gbi ) node value is restored. Ground test were performed at the Lawrence Berkeley Laboratory 88'Cyclotron [START_REF] Monnier | SEU Testing of a Novel Hardened Register Implemented Using Standard CMOS Technology[END_REF]. The experimental results show that this design approach was relevant to achieve SEU hardening capability, as the SEU Linear Energy Transfer ( LET ) threshold of the hardened flip-flop was up to 27 MeV.cm 2 /mg while the standard flipflop presents a LET threshold of 6 MeV.cm 2 /mg.

Clk

Clk

Gi

B. Experimental conditions

The laser test is carried out using a Ti : Sapphire pulsed laser delivering 1ps width pulses with a central wavelength of 800 nm. The penetration depth is estimated to 12 m. The beam is focused by a 100X microscope lens objective down to 1 m above the surface of the device under test. A CCD camera coupled with the microscope objective allows us to visualize the impact point. The scanning resolution is 0.2 m. The upset detection is carried out by checking the electric state of the register output on a Slave. For each strike location producing an upset the corresponding point is colored on a map. The red points corresponds to the sensitive points, i.e. the lower energy sensitivity areas.

The laser test is performed with a clock set down in state 0 corresponding to the static mode of the memory cell. The Master latch is settled in a well established memory mode while the Slave latch is in a write mode. So, the value memorized by the Master is permanently written in the Slave. This usual pattern has an impact on the experimental results expected.

On the one hand, if an upset arises at the Master level, the wrong value will be stored and the erroneous value transferred to the Slave ; and, for laser testing the error will be rightfully identified as coming from the Master.

On the other hand, a bit flip of the Slave state will not be traceable if the correct value is still stored in the Master because of a permanent writing of the Slave to the right value before an error transference to the output. One must be prepared to see the observed laser sensitive areas confined in the Master part of the map.

III. EXPERIMENTAL RESULTS Some maps of the standard flip-flop sensitive areas are presented on Figure 5 with a microphotograph of the layout. The result evidences the sensitivity evolution of the Master nodes of the figures 1 and 3, for energies starting from 9 pJ up to 50 pJ. The picture draws the outline contour of contacts, via and metal interconnects of the cell, as laser is reflected by metallization. But the map of Figure 5 exhibits also unexpected sensitive regions of the Slave -areas D2 and G2 (state 1). In principle these upset areas should not be observable. Indeed, the sensitivity mapping being conducted in static mode, any flip of the Slave should be corrected by the Master. The observation of points on the map in the Slave area means that the Master itself was flipped too. In turn the Master is imposing its new false state onto the slave. Then the upset is detected and the point is colored on the map as coming from the Slave. This indirect phenomenon, made clear for the first time, is due to a "back-generation" of the transient effect by the circuit structure. This interpretation will be confirmed by the SPICE simulations of the section IV (see Fig. 7). In a parallel experience, a laser mapping of the hardened flip-flop (Fig. 6) still makes manifest the presence of some sensitive zones on the Slave ( G2 and D2 in the state 1, with Gb2 and Db2 in the state 0 ) bringing to the fore the existence of the same phenomenon of back-generation from the Slave to the Master despite the hardened design of the cells.

Moreover one may also observe the existence of similar sensitive areas on the nodes Q1 if the Master is in the state 1 and on the node Qb1 if in the state 0.

Table 1 lists the different areas which are SEU sensitive, and the observed energy thresholds for states 1 and 0. An increase of the laser pulse energy beyond 50 pJ does not reveal other sensitive area; the only effect to mention is an extent of the former ones. If we apart the G1 area because of its high occurence value (50 pJ) , the SEUs concern mainly the Q1 area in state 1 and the Qb1 area in state 0. Following our previous remark regarding back-generation this observation becomes noticeable on hardened circuit since areas D2 and G2 are connected to Q1 and respectively areas Db2 and Gb2 to Qb1 (Fig. 2 and4). The experimental results are confirmed by the SPICE simulations of the section IV (Fig. 8 and9). When we analyze more tightly the behavior of the standard flip-flop under laser exposure, the presence of a SEU sensitivity is observed on D2 but also on G2 of the Slave. Indeed the electrical disturbance propagates from G2 through the transmission transistors mtg1 and mtg2 to D2 and Q1 (see Fig. 1) and finds propitious conditions for a permanent switching of the Master. This interpretation has been confirmed by SPICE simulations of an upset on the node G2 with a flip-flop in the memory mode (Clk=0, Clkb=1) storing the logic state 1. The sensitivity is effective for a (600ps, 2mA) current pulse applied between node G2 and the bulk (gnd). The simulation data of the standard flip-flop presented on figure 7 show that the rapid decrease of G2 to 0V pulls down Q1, inducing a switch of the Master latch. So, an upset on the Slave involves a definite change of the bit memorized by the Master. Now, if we look at the laser results of the Hardened flipflop, in state 1, we observe that in the flip-flop configuration the more appealed node is the node Q1 of the Master latch. Many laser impact areas are related to this node and its electric state while in state 1 ( respectively Qb1 in state 0 ).

The figure 8 illustrates in detail the permanent flip of the Master. The rapid decrease to 0V of Q1 voltage pulls down G1 voltage, inducing a permanent change of the Master latch. As a matter of fact the upset on node Q1 is propagated to node G1 despite the RC filtering, due to a persistence of the upset (600 ps ). Note that in a previous paper [START_REF] Monnier | SEU Testing of a Novel Hardened Register Implemented Using Standard CMOS Technology[END_REF], the hardening assessment of the basic hardened latch of this flip-flop was successfully simulated and found "immune" through post layout SPICE simulations, while the very same hardened designs organized in a register of flip-flops were tested SEU sensitive to a heavy ion irradiation (beyond a LET Threshold of 27 MeV.cm2/mg). This can be explained by the time duration limitation of the pulses fixed to (500ps, 10mA) and even (500ps, 20mA) for simulations.

In the present study the (600ps, 10 mA) current pulse SPICE simulations is in accordance with the 1ps width laser pulse to highlight a SEU sensitivity of the whole flip-flop structure. The above study points out another observation: the evaluation of a circuit sensitivity cannot be done using the sole charge deposited criterion expressed in pC. The boundary conditions must be considered too (see also the approach of Baze and al. [START_REF] Baze | A Digital CMOS Design Technique for SEU Hardening[END_REF]).

In a similar way for this hardened structure, we observe that a sufficiently long pulse duration (900ps, 10mA) on the node G2 of the Slave, can also provoke a permanent switch of the flip-flop. This is illustrated on Figure 9. In this circuit, G2 is once again connected to the node Q1 via a pass transistor as it can be seen on figure 2. So, while attenuated a "backgeneration" of the upset can still exploit the SEU sensitivity of the node Q1 in state 1 ( respectively Qb1 in state 0 ). In this experiment, the test laser analysis allows first to evidence a SEU back propagation phenomena from the Slave to the Master in flip-flops and then to point out the relative weakness of a RC-filtering in our hardened circuit. All these results permit us to undertake an amelioration of the SEU tolerance as the next section will now present.

V. SEU IMMUNITY IMPROVEMENT

Once the soft error origin is identified and analyzed on laser mapping, we look for the optimal hardening conditions with SPICE circuit simulations taking into account the layout parasitic capacitances. In the present case the sensitivity being caused by a weakness of the feedback circuit, we conclude that an unsuited RC filtering towards the node G1 is the cause of the SEU sensitivity when an upset to zero occurs on Q1 (or from Gb1 to state 0 when an upset to 0 is happening in Qb1). Then the filtering margins are adjusted through a cell resizing using SPICE. New simulations undertaken after intervention on the design are presented on Figure 10 demonstrates that a resizing of the cell prevents a decrease of the node G1 voltage, enough to induce a bit flip of the Master. So, after the 600 ps upset duration, the high level of the node Q1 can be promptly restored.

VI. CONCLUSION

Laser testing of circuit can carry on the identification of some configurations propitious to the development of peculiar single event. To illustrate the purpose, we have presented a case not previously reported of a "back-generation" effect. This effect is related to an upset in a flip-flop. It leads to detect the presence of unattended soft errors in the memory cells of shift registers. A mapping allows us to intervene on the right element of the hardened circuit and to improve even more its capabilities by resizing the design. This investigation shows relevant applications of the laser testing not only as a failure analysis instrument but also as a tool to improve the design rad hardening of the circuits.

  Manuscript submitted March 14, 2001 J.M Dutertre is with the Laboratoire d'Informatique de Robotique et de Micro lectronique de Montpellier, Montpellier, 34392 Cedex FRANCE ( e-mail: dutertre@lirmm.fr ). F.M. Roche is with the Laboratoire d'Informatique de Robotique et de Micro lectronique de Montpellier, Montpellier, 34392 Cedex FRANCE (e-mail: roche@lirmm.fr).

Fig. 1 .Fig. 2 .

 12 Fig. 1. Standard flip-flop.

Fig. 3 .

 3 Fig. 3. Standard latch design and location of sensitive areas.

Fig. 4 .

 4 Fig. 4. Rad hard latch design and sensitive nodes.

Fig. 5 .

 5 Fig. 5. Standard flip-flop layout and SEU sensitivity mapping of the state 1 at different energies.

Fig. 6 .

 6 Fig. 6. Hardened flip-flop layout and SEU sensitivity mapping of state 1 at 30 pJ, 50 pJ and 70 pJ.

Fig. 7 .

 7 Fig. 7. Upset 600 ps 2 mA on node G2, standard flip-flop, state 1.

Fig. 8 .

 8 Fig. 8. Upset 600 ps 10 mA on node Q1, hardened flip-flop, state 1.

Fig. 9 .

 9 Fig. 9. Upset 900 ps 10mA on node G2, hardened flip-flop, state 1.

figures 10 and 11 .Fig. 10 .

 1110 figures 10 and 11. Checking the immunity on node Q1 of the Master in a new worst case condition of upset will confirm the validity of the diagnosis and the efficiency of the hardening solution.

  Figure10demonstrates that a resizing of the cell prevents a decrease of the node G1 voltage, enough to induce a bit flip of the Master. So, after the 600 ps upset duration, the high level of the node Q1 can be promptly restored. Figure11confirms the hardness improvement. The design adaptation, realized with the help of laser testing and electrical simulations, ameliorate significantly the SEU immunity of the hardened flip-flop.

Fig. 11 .

 11 Fig. 11. Upset 900 ps 10 mA on node G2, re-hardened flip-flop, state 1.

  to be driven to low voltage). The sensitive areas or nodes are pointed out on figures 3 and 4 according to the electrical state of the nodes.

	Radiation and Its Effects on Components and Systems, 2001. 6th European Conference on
	http://dx.doi.org/10.1109/RADECS.2001.1159287
		Improving an SEU Hard Design using a Pulsed
					Vcc	Vcc	Laser
		Clk
	Di	mtg1	Gi	J.M. Dutertre, F.M. Roche, Member, IEEE, P. Fouillat, Member, IEEE, D. Lewis Qi Qbi m1 m4
		mtg2			m2	m3
		Clkb		Clk	gnd	gnd
		mtg3 mtg4
		Sensitive area for state 1.	Sensitive area for state 0.

liable

TABLE I SEU

 I SENSITIVE AREAS OF THE HARDENED FLIP-FLOP AND THEIR CORRESPONDING ENERGY OBSERVATION THRESHOLDS

	State 1	State 0
	D2 17 pJ	Qb1 27 pJ
	Q1 30 pJ	Db2 30 pJ
	G2 30 pJ	Gb2 30 pJ
	G1 50 pJ
	IV. ANALYSIS AND SIMULATIONS