Dong-Hyeok Son
email: dhson@ee.knu.ac.kr

Terirama Thingujam
email: trthingujam@gmail.com

Jeong-Gil Kim
email: ksim@kumoh.ac.kr

Dae-Hyun Kim
email: dae-hyun.kim@ee.knu.ac.kr

In Man Kang
email: imkang@ee.knu.ac.kr

Ki-Sik Im

Christoforos Theodorou
email: theodoch@minatec.grenoble-inp.fr

Gerard Ghibaudo
email: ghibaudo@minatec.inpg.fr

Sorin Cristoloveanu

Jung-Hee Lee
email: jlee@ee.knu.ac.kr

D. -H Son

J. -G Kim

D.-H Kim

J.-H Lee

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

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Abstract--GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gateall-around structure. In this work, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low voltage/power applications. However, the devices with smaller diameter of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance. Systematical analyses with dc and noise measurements as well as TCAD simulations show that the observed characteristics are due to the contact potential which strongly depends on the nanowire diameter and the trapping effect into deep traps at the sidewall surface of the nanowire channel.

Index Terms--GaN vertical nanowire MOSFET, low voltage application, nanowire diameter, contact potential, negative transconductance

I. INTRODUCTION

-V semiconductors such as GaAs and InAs offer superior material and electrical properties and are considered to replace the channel layers in the conventional Si-based devices which technologies have been quiet close to their limitations [START_REF] Persson | Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates[END_REF][START_REF] Zhao | Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach[END_REF][START_REF] Tomioka | A III-V nanowire channel on silicon for high-performance vertical transistors[END_REF][START_REF] Shirak | High performance horizontal gate-all-around silicon nanowire field effect transistors[END_REF][START_REF] Mirza | One dimensional transport in silicon nanowire junction-less field effect transistors[END_REF][START_REF] Azize | High-electron-mobility transistors based on InAlN/GaN nanoribbons[END_REF]. In contrast with other III-V semiconductors, GaN-based materials and devices have been rarely studied for low-power purpose. Instead, they have been generally considered as promising candidates for high power and high frequency applications due to their material advantages such as wide bandgap energy, high breakdown field, and high electron saturation velocity [START_REF] Chow | Wide bandgap compound semiconductors for supe rior high-voltage unipolar power devices[END_REF][START_REF] Akutas | High temperature characteristics of AlGaN/GaN modulation doped fieldeffect transistors[END_REF]. Nevertheless, theoretical and simulation studies have shown that GaN nanowires could be the proper elements for extremely short channel MOSFET compared to GaAs, InAs, Ge, and Si-based nanowires [START_REF] Chowdhury | GaN Nanowire n-MOSFET with 5 nm Channel Length for Applications in Digital Electronics[END_REF]. Indeed, relatively small permittivity and large electron effective mass of the GaN-based materials are important parameters for alleviating the short channel effects because they reduce the source-to-drain tunneling current and the natural length which represents the penetration distance of the electric field lines from the drain [START_REF] Colinge | Multi-gate SOI MOSFETs[END_REF]. Recently, GaNbased 3-dimsional FETs with gate-all-around (GAA) structures have shown improved device performances such as linearity, suppressed current collapse, high on/off-state current ratio, and high voltage characteristics, resulting from the enhanced gate control of the channel [START_REF] Jo | AlGaN/GaN Fin FET with extremely broad transconductance by sidewall wet etch[END_REF][START_REF] Yu | Vertical architecture for enhancement mode power transistors based on GaN nanowires[END_REF][START_REF] Takashima | Sidewall Dominated Characteristics on Fin-Gate AlGaN/GaN MOS-Channel-HEMTs[END_REF][START_REF] Im | High-performance GaN-based nanochannel finFETs with/without AlGaN/GaN heterostructure[END_REF][START_REF] Son | Low voltage operation of GaN vertical nanowire MOSFET[END_REF]. Especially, GaN vertical nanowire MOSFET features small threshold voltage of ~ 0.6 V and saturation drain voltage of less than 1 V which open up possibility of GaN devices as a future logic applications [START_REF] Son | Low voltage operation of GaN vertical nanowire MOSFET[END_REF].

In this work, we present GaN GAA vertical nanowire MOSFETs (VNW-MOSFETs) with variable diameter (d NW ). The device with d NW of 120 nm has m-plane sidewall surface with hexagonal symmetry and features normal low-voltage operation. The devices with smaller d NW of 75 and 45 nm show two additional characteristics such as second rise of drain current in output characteristic and negative transconductance (NT). Systematic experiments including low-frequency noise point on the role of the drain contact potential and the trapping effects through deep-level traps at the irregular sidewall surface of the nanowire. These results offer a sound base for further optimization of VNW-MOSFETs with narrow diameter.

II. DEVICE FABRICATION

A. Formation of GaN vertical nanowire.

The epitaxial layers for the nanowire consisted of an n + -GaN layer for source, an undoped GaN channel layer, and an

Effects of Contact Potential and Sidewall Surface Plane on the Performance of Vertical GaN Nanowire MOSFETs for Low Voltage Operation

Dong-Hyeok Son 1 , Terirama Thingujam 1 , Jeong-Gil Kim, Dae-Hyun Kim, In Man Kang, Ki-Sik Im, Christoforos Theodorou, Gerard Ghibaudo, Sorin Cristoloveanu, and Jung-Hee Lee* III n + -GaN layer for drain with thickness of 800, 300, and 500 nm and with doping concentration (N D ) of 2.0 × 10 18 , 2.0 × 10 16 , 2.0 × 10 18 cm -3 , respectively, which were sequentially grown by metal-organic chemical vapor deposition (MOCVD) on sapphire (0001) substrate. From the x-ray diffraction (XRD) measurement, the full widths at half maximum (FWHM)s for GaN (002) and (102) planes for this work were 314 and 310 arcsec, respectively. The screw and edge dislocation densities were 9.5ⅹ10 7 cm -2 and 5.0ⅹ10 8 cm -2 , respectively. Considering the GaN nanowire diameter of 120 nm for this work, the numbers of dislocations one per nanowire were 1.07ⅹ10 -2 for screw and 5.65ⅹ10 -2 for edge dislocations, respectively. Even with 9 parallel VNW in a device the probability of 1 dislocation per nanowire is very small, which unlikely to affect the device operation.

To form the etch mask layer, the HfO 2 /SiO 2 dielectric layer was first deposited with using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) in sequence. The Ti/Ni/Au metal layer was evaporated on the dielectric layer after electron-beam lithography to define the initial mask pattern. The pattern was transferred to the dielectric HfO 2 /SiO 2 layer with using CF 4 -based inductively coupled plasma reactive ion etching (ICP-RIE) to complete the double metal-dielectric mask structure. Cl 2 -based ICP-RIE was then carried out to selectively etch GaN down to 1 μm depth with using the mask, which results in flat-top coneshape nanowires. Anisotropic lateral wet etching in TMAH solution (5 % concentration at 80 ºC) was followed to form pillar-shaped nanowires with very steep sidewall. After 30 min wet etching in TMAH solution, however, different shapes of nanowires were obtained as shown in Fig. 1(c) and(d); hexagonal symmetry nanowire pillar with m-plane sidewalls and non-hexagonal irregular nanowire pillar with mixed-plane sidewalls rather than a single crystal plane, respectively. The difference in shape for the nanowires after TMAH wet etching depends on the strength of the adhesion between the etch mask layer and the top surface of the GaN nanowire. If the adhesion of the mask layer on the top surface of the GaN nanowire is sufficiently strong, the mask layer can be sustained during the anisotropic lateral TMAH wet etching, which typically leads to the hexagonal GaN nanowire pillar with m-plane sidewall surfaces as shown in Fig. 1 (c). However, if the adhesion is weak, the mask layer can be peeled off during the TMAH wet etching to expose the vulnerable edges between c-plane surface (top of nanowire) and m-plane surface (sidewall of nanowire) [START_REF] Moses | Hybrid functional investigations of band gaps and band alignments for AlN, GaN, InN, and InGaN[END_REF]. Then, the etching loses the anisotropic property and proceeds toward all lateral directions, which results in forming the GaN nanowires with irregular sidewall surfaces with various crystal planes, as shown in Fig. 1 (d) [START_REF] Yu | GaN nanowire arrays with nonpolar sidewalls for vertically integrated fieldeffect transistors[END_REF]. After formation of GaN vertical nanowires, the etch mask layer was removed in Hydrofluoric acid (HF) solution.

B. GaN VNW-MOSFET fabrication.

For the formation of ohmic contact, the nanowire structure was coated with photo-resist (PR). In general, there exist a finite difference in the PR thickness between top and bottom of nanowire due to high etching aspect ratio in GaN layer. The etch-back process utilizing dry etching was applied to selectively remove the PR only on top of the nanowire. This etch-back process enables the Si/Ti/Al/Ni/Au drain ohmic metal to be deposited only on the top of nanowires. After depositing the source ohmic metal, rapid thermal annealing was followed at 800 °C in N 2 ambient to obtain the ohmic contact for the source and the drain,. The specific contact resistance was 3 ⅹ 10 -5 Ω-cm 2 , which was evaluated from transmission line method (TLM).

For the formation of the gate, 10 nm-thick ALD Al 2 O 3 gate dielectric, 200 nm-thick sputtered Cr gate, and 50 nm-thick PECVD SiN protection layer were sequentially deposited. To define the gate, coating of PR and etch-back process enable revealing the top of vertical nanowire. The SiN protection layer was etched in buffered oxide etch (BOE) solution and the Cr gate was etched with O 2 plasma. The Al 2 O 3 dielectric layer, which covers the drain, protects the ohmic metal on the drain during the O 2 plasma etching. The overlap length of gate metal at drain-side access region was 100 nm.

To ensure electrical isolation between the gate and the drain, 100 nm-thick PECVD SiN spacer layer was deposited. SiN spacer layer on top of vertical nanowires was selectively removed by coating of PR and etch-back process mentioned above to reveal the drain metal on top of nanowire. Additional O 2 plasma etching was performed for removal of PR. Before deposition of pad metal on top of source, drain and gate electrode, dielectric layer on those electrode was selectively removed by using UV-lithography and ICP-RIE, in sequence. The Al 2 O 3 layer on the drain, the source, and the gate electrode was selectively removed with using ICP-RIE and the pad metal layer was finally deposited. The cross-sectional image in Fig. 1 (e) is for the hexagonal m-plane sidewall GaN VNW-MOSFET with d NW of 120, and the images in Fig. 1

C. Device measurement and characterization.

The semiconductor parameter analyzer (Keysight HP4156) was used to apply the grounded source voltage, drain voltage and gate voltage to measure the drain current. The noise measurement system (Synergie Concept Noisys7) was used to measure the low frequency noise characteristic. Silvaco TCAD software was used for the simulation of GaN VNW-MOSFETs.

III. RESULTS AND DISCUSSION

Fig. 2 (a), (b), and (c) show the output characteristics of the GaN VNW-MOSFETs with d NW of 120, 75, and 45 nm, respectively. The device with d NW of 120 nm has hexagonal nanowire pillar with m-plane sidewall surface and the devices with d NW of 75 and 45 nm have non-hexagonal nanowire pillar with various crystalline planes in the sidewall. The GaN VNW-MOSFET with d NW of 120 nm exhibits considerably lower saturation drain voltage (< 0.5 V) compared to conventional GaN-based planar devices because the drain current in such a narrow nanowire channel can be easily pinched-off due to the electric field distribution between the gate and the drain [START_REF] Son | Low voltage operation of GaN vertical nanowire MOSFET[END_REF].

On the other hand, the output characteristics of the device with d NW of 75 nm show even lower saturation voltage at low current level, but exhibit a kink (second rise in drain current) at drain voltage (V D ) of 0.5 ~ 0.6 V. Furthermore, the device with d NW of 45 nm shows output characteristics with offsetlike turn-on voltage at V D = ~ 0.5 V. For V D < 0.5 V, the drain current is two orders of magnitude lower than in the device with d NW of 75 nm. These contrasting behaviors can be understood from the simulations of the electric field distribution. At equilibrium (V G = V D = 0 V), the heavily n +doped (2 × 10 18 cm -3 ) access region between the gate and the drain contact comprises a 20 nm thick depletion region due to the surface potential formed at the Al 2 O 3 -deposited sidewall of the GaN nanowire channel [START_REF] Suri | Investigation of MOS interfaces with atomic-layer-deposited high-k gate dielectrics on III-V semiconductor[END_REF]. This surface depletion induces a small but finite contact potential at the drain terminal. In the case of the device with d NW of 120 nm, the contact potential is not important since a sufficiently wide access region remains neutral, as purple region shown in Fig. 2 (d). At V G > V TH , the device shows normal output characteristics with applying V D . In the device with d NW of 75 nm, the neutral access region becomes very narrow and the drain contact deviates from the original ohmic nature by building a contact barrier of 0.16 eV at the center of the drain contact. When the device is turned on, relatively low output current flows due to this contact barrier and the increased access resistance at low V D . However, applying V D of ~ 0.5 V lowers the height of the contact barrier to a negligible value, as shown in Fig. 2 (e), and hence the output current rapidly increases, showing an apparent second rise in drain current. For the device with d NW of 45 nm, the resistance of the n +access region becomes very high due to very narrow neutral region and the contact potential increases to 0.3 V at equilibrium. With V G > V TH , extremely small drain current flows at low V D . A V D of ~ 0. 5 V lowers the contact potential close to the thermal potential, and unblocks the device. This results in output current increase with offset-like turn-on voltage as in Fig. 2 (c). The effect of higher V D is two-fold; it lowers the contact barrier and supplies energy to electrons. We conclude that this abnormal behavior originates from the nano-channel squeezing caused by the surface depletion regions. The solution to reduce the surface depletion and series resistance is to increase the n + -type doping in the ungated access region [START_REF] Doundoulakis | Nanofabrication of normally-off GaN vertical nanowire MESFETs[END_REF]. The transfer characteristics of the device with d NW of 120, 75, and 45 nm at V D = 1 V are shown in Fig. 3. The corresponding threshold voltages (V TH ), extracted at fixed drain current of (0.1)ⅹ(channel width/channel length) μA [START_REF] Hu | Modern Semiconductor Devices for Integrated Circuits[END_REF], are 0.7, 0.9, and 1.2 V, respectively. In equilibrium, the surface potential of the nanowire channel with doping density of 2 × 10 16 cm -3 results in depletion thickness of ~ 210 nm [START_REF] Hu | Modern Semiconductor Devices for Integrated Circuits[END_REF], which forces the entire nanowire channel of the device with d NW of 120 nm to be depleted and ensures normally-off operation. The flat-band voltages (V FB ), estimated from the V G at maximum transconductance, were 1.19, 1.40, and 1.75 V for the devices with d NW of 120, 75, and 45 nm, respectively. The V FB value calculated from the work-function of Cr gate and electron affinity of non-polar GaN sidewall surface with doping concentration of 2 ⅹ 10 16 /cm 3 is 1.1 ~ 1.2 V [START_REF] Moses | Hybrid functional investigations of band gaps and band alignments for AlN, GaN, InN, and InGaN[END_REF],similar to that of our wider device. V FB increases in narrower d NW where the surface potential makes the nanowire channel more deeply depleted and further raises the conduction band (E C ) above the Fermi level (E F ) in inside of the nanowire channel. As a result, a higher positive gate voltage is needed to recover flat energy bands.

Another interesting aspect is that devices with d NW of 75 and 45 nm exhibit negative transconductance (NT) characteristics. This is mainly due to the significant trapping effect related to the deep traps at sidewall surface of the GaN nanowire channel, rather than trapping/detrapping through shallow surface traps. Narrow devices have higher deep trap density as well as shallow trap density, because their surface features various crystal planes and relatively rough surface as discussed above. The device with d NW of 120 nm has hexagonal symmetry with smooth m-plane surface which results in the lower interface trap density [START_REF] Yu | GaN nanowire arrays with nonpolar sidewalls for vertically integrated fieldeffect transistors[END_REF][START_REF] Gupta | Comparing electrical performance of GaN trench-gate MOSFETs with a-plane (1120) and m-plane (1100) sidewall channels[END_REF].

The trapping effect through deep traps is responsible for the NT characteristics observed from the output and transfer curves for the narrow devices in Fig. 2 and3. They can be explained as follows: when V G is lower than V TH , the entire nanowire channel is completely depleted due to the gate electric field from the GAA structure and hence no current flows. As V G increases above V TH , the current starts to flow in the center and expands in the entire nanowire channel; the current continually increases until V G reaches the V FB , and the transconductance attains a maximum as shown in Fig. 3. At V FB , the depletion layer disappears and the energy bands across the channel become flat. For even higher V G , electrons tend to accumulate at the surface of the nanowire channel due to downward band bending and hence the surface accumulation current adds to the volume current.

Simultaneously, some electrons tend to be captured into the deep traps as well as shallow traps at nanowire surface. Nevertheless, the device current keeps increasing until V G reaches the peak voltage (V peak ). As V G increases beyond V peak , however, the device current starts to decrease because the electron trapping into the deep traps becomes sufficiently high to give rise to dynamic shift of V TH of the device due to negative charge trapping. Additionally, the higher rate of scattering between the trapped charges and the channel electrons leads to the mobility degradation of the channel electron. The trapping effect through the shallow interface traps is not significant, however, because the trapping/detrapping process is fast and hence is not supposed to cause a dynamic shift of V TH for the device. The current continually decreases until V G increases to valley voltage (V valley ) where all traps are filled and trapping no longer occurs. At V G above V valley , electrons are accumulated in the surface channel and their mobility is slightly increased due to the screening effect, as shown in Fig. 5 (a). As a result, the current and transconductance increase again. On the other hand, the NT characteristics are not observed from the device with hexagonal pillar with m-plane sidewall surface and width d NW of 120 nm, because the trapping occurs mostly through relatively shallower interface traps rather than deep traps.

To further analyze the NT characteristics observed in the devices with d NW of 75 and 45 nm, the emission time constants were evaluated from the time response of transfer characteristics [START_REF] Tanaka | Quantitative evaluation of slow traps near Ge MOS interfaces by using time response of MOS capacitance[END_REF], as shown in Fig. 4. In this measurement, V G is swept from 0 V to 3.0 V to fill electrons into the interface traps on the sidewall of nanowire. After a standby time (at off-state condition), the sweeping of V G is repeated again to observe the shift of V FB (∆V FB ) due to electron capture into the interface traps. It is noticed that the ∆V FB for the device with d NW of 120 nm is much smaller compared to that of the narrower devices, as shown in (a) and (b) of the figure. Fig. 4 (c) presents the ∆V FB vs. standby time for both devices, which clearly show exponential time decay. The charge variation (∆𝑁 𝑑𝑡 ) due to the trapping into the deep traps can be expressed as

Δ𝑁 𝑑𝑡 = 𝐶 𝑜𝑥 (Δ𝑉 𝐹𝐵 ) 𝑞 ∝ 𝐴𝑒𝑥𝑝 ( -𝑡 𝜏 ) (1)
, where 𝑞 is the elementary charge, 𝐶 𝑜𝑥 is the unit area gate dielectric capacitance, A is a constant, t is the standby time, and 𝜏 is the emission time constant of electron de-trapping process, respectively. The emission time constants estimated from the equation above is < ~ 0.6 sec and > ~ 500 sec for the devices with d NW of 120 and 75 nm, respectively. This clearly indicates that the trapping/detrapping process in the wide device is mainly due to the trapping/detrapping through shallow interface traps, whereas the trapping in the device with d NW of 75 nm occurs mostly through deep traps. This trapping behavior through deep interface traps in the devices with d NW of 75 nm is causes the dynamic shift of V TH which leads to the NT characteristics discussed in Fig. 3. Fig. 5 (a) shows the field-effect mobility versus gate overdrive voltage (V G -V TH ) for the investigated GaN VNW-MOSFETs [START_REF] Son | Low voltage operation of GaN vertical nanowire MOSFET[END_REF], exhibiting the mobility decrease as d NW narrows. When V G is less than V FB , the channel current consists of electron flow through the nanowire volume where the mobility is superior. At V G higher than V FB , the surface accumulation channel current starts to flow and increases the device current, but the mobility is degraded by additional scattering with the trapped charges at the surface. However, the mobility of the device with d NW of 70 nm tends to slightly increase as the gate overdrive voltage increases above 2 V, which corresponds to (V G > V valley ), whereas the mobility of the device with d NW of 45 nm becomes saturated at gate overdrive voltage higher than 1 V. The reason is that the strong electron accumulation at surface channel screens the electric field from the charges in interface traps.

On the other hand, the screening effect is hardly observed in the device with d NW of 120 nm, because the trapping into the interface trap is not significant. lower interface trap density. The corresponding values for the drain-induced barrier lowering (DIBL) are 120, 50, and 100 mV/V, respectively (data are not shown), which confirm that the device with smaller d NW is less affected by short-channel effect due to the enhanced gate controllability. Finally, the gate leakage current remains small even at V G of 3 V, due to the good dielectric properties of the Al 2 O 3 gate insulator.

Low-frequency noise measurements were performed to further analyze the characteristics of GaN VNW-MOSFETs. Fig. 6 (a) and (b) show the noise spectral density (S Id ) versus frequency for the device with d NW of 120 and 75 nm, respectively. The results for the device with d NW = 45 nm were similar to those obtained from the device with 75 nm. When V G is higher than V FB , both devices show 1/f noise characteristics at low frequencies (below 100 Hz), which indicates that the noise originates from mobility fluctuations or carrier number fluctuations due to trapping/detrapping in defects located at the interface between the gate dielectric layer and the surface of the GaN nanowire channel. The deviation from 1/f noise above 100 Hz in many spectra is related to the measurement bandwidth which, for I d < 1 nA, is limited at 5-100 Hz. Therefore, this behavior is not attributed to Lorentzian noise related to generation-recombination events. Using the CNF model (2), we were able to extract the volumetric oxide trap density, N t , for all measured devices. The results are presented in Fig. 8 . As one can observe in Fig. 8, where the extraction results are presented, N t seems to increase in devices with smaller diameter, which is in agreement with the D it extraction and probably related to the presence of various crystal planes as already mentioned. The field-effect mobility (~ 200 cm 2 /Vs at very low V G ) is rapidly degraded when V G < V FB , and then decreases slowly to ~ 90 cm 2 /Vs for V G > V FB . However, the devices with multiple sidewall planes (d NW of 75 and 45 nm) show higher V TH of 0.9 and 1.2 V and V FB of 1.4 and 1.7 V, and relatively large SS of 90 and 120 mV/decade, respectively. The field-effect mobility for both devices are much lower than for the device with d NW of 120 nm. Furthermore, the narrow nanowires exhibit two peculiar characteristics such as second rise of drain current in output characteristics and negative transconductance, which are strongly related to the higher contact potential near the drain and higher deep trap density at sidewall surface. The high density of deep traps causes the threshold voltage shift and mobility degradation of the channel electron which leads to negative transconductance. The results obtained in this work suggest that the contact potential must be lowered at drain access region of the nanowire, via heavy n + -type doping, while maintaining m-plane sidewalls of the nanowire channel for low interface trap density.

  (f) and (g) are for the non-hexagonal sidewall GaN VNW-MOSFET with d NW of 75 and 45 nm, respectively.

Figure 1

 1 Figure 1 (a) Schematic of GaN VNW-MOSFET. (b) SEM image after dry etching of VNW. (c) SEM image of VNW with 120 nm diameter after TMAH etching. (d) SEM image of VNW with 56 nm diameter after TMAH etching. Cross-sectional image of GaN VNW-MOSFET with diameters of (e) 120 nm, (f) 75 nm, and (g) 45 nm.

Figure 2

 2 Figure 2 Output characteristics of GaN VNW-MOSFETs with diameter of (a) 120 nm, (b) 75 nm, and (c) 45 nm. (d) and (e) are simulated electric field profiles in the corresponding devices.

Figure 3

 3 Figure 3 Transfer characteristics of GaN VNW-MOSFET with diameter of (a) 120 nm, (b) 75 nm, and (c) 45 nm.

Figure 4

 4 Figure 4 Transfer characteristics of GaN VNW-MOSFET with diameter of (a) 120 nm and (b) 75 nm after various standby times. (c) ∆VFB versus standby time of same VNW-MOSFETs.

Figure 5

 5 Figure 5 (a) Field-effect mobility versus gate voltage overdrive and (b) subthreshold characteristics of investigated devices.

Fig. 5 (

 5 Fig. 5 (b) shows the semi-logarithmic transfer characteristics of all investigated devices. The device with d NW of 120 nm exhibits excellent off-state performances, such as extremely small leakage current of ~ 10 -13 A and very low subthreshold swing (SS) of ~ 70 mV/dec with high on/off current ratio of ~ 10 8 . This is the benefit of smooth m-plane sidewall surfaces and hence lower interface trap density. In contrast, the performances are degraded for the devices with smaller d NW , which suffer from much higher interface trap density (D it ) caused by the sidewall formation with different crystal planes rather than m-plane only. The D it extracted from the SS values are 8.3ⅹ10 11 , 2.5ⅹ10 12 , and 5.0ⅹ10 12 /cm 2 • eV for the devices with d NW of 120, 75, and 45 nm, respectively, which clearly indicates that the m-plane surface has much

Figure 6

 6 Figure 6 Noise spectral density of GaN VNW-MOSFETs with diameter of (a) 120 nm and (b) 75 nm.

Fig. 7 2 )

 72 Fig. 7 shows the (g m /I d ) 2 characteristics and the normalized noise spectral density (S Id /I d 2 ) measured at 10 Hz. When V G is higher than V TH , S Id /I d 2 and (g m /I d ) 2 well match each other for both devices, as shown in (a) and (b) of the figure, which proves that the noise mechanism is related to carrier number fluctuations (CNF), originating caused by electron trapping/de-trapping between the channel and the traps near the gate dielectric [23-25], and not to mobility fluctuations.

Figure 7

 7 Figure 7 Normalized noise spectral density (SId/Id 2 ) and (gm/Id) 2 versus drain current of GaN VNW-MOSFETs with diameter of (a) 120 nm and (b) 75 nm.

Figure 8

 8 Figure 8 The input referred gate noise spectral density versus gate bias in GaN VNW-MOSFETs with diameter of 120 and 75 nm.

V. ACKNOWLEDGMENT This work was partly supported by the BK21 Plus funded by the Ministry of Education (21A20131600011), and this invention was supported by Samsung Research Funding & Incubation Center of Samsung Electronics under Project Number SRFC-TA1703-08.


Petros Sideris

J Lugo-Alvarez

P Batude

L Brunet

P Acosta-Alba

S Kerdiles

C Fenouillet-Beranger

G Sicard

O Rozeau

F Andrieu

Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential Integration

come

Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential Integration P. Sideris 1,2 , J. Lugo-Alvarez 1 , P. Batude 1 , L. Brunet 1 , P.Acosta-Alba 1 , S.Kerdiles 1 , C.Fenouillet-Beranger 1 , G. Sicard 1 , O.Rozeau 1 , F.Andrieu 1 , J-P.Colinge 1 , G.Ghibaudo 2 , C. Theodorou 2 1 CEA-LETI, Grenoble, France, email: petros.sideris@cea.fr 2 IMEP-LAHC, Univ. Grenoble Alpes, Univ. Savoie Mont Blanc, CNRS, Grenoble INP, Grenoble, France.

Abstract-For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

I. INTRODUCTION

In 3D sequential integration (also named 3D monolithic integration or 3D VLSI), the stacked devices are fabricated sequentially on top of each other. This process yields to outstanding high-density-contacts between the tiers (up to 10 8 3D via/mm 2 ) owing to the high alignment precision obtained with lithography steppers [1], [2], compared to packaging integration schemes (TSV, copper to copper bonding etc.). However, the ultra-thin Inter-Layer Dielectric (ILD) separating the sequential tiers can act as a Back Gate (BG) oxide for the top transistors, becoming a pathway of electrical interference between stacked devices. Consequently, if no Ground Plane (GP) is introduced, the top device is an asymmetrical SOI MOSFET sensitive to the bottom device electrode voltage variations (Fig. 1(a)) or iBEOL metal biasing (Fig. 1(b)). The goal of this study is to analyze the immunity of top devices with EOT in 1nm range (VDD=1V) for a wide range of applications (Digital, Mixed signal/ RF) when bottom layer is either digital, RF or analog circuit (VDD=2.5V). Simulations and experimental measurements will be used to draw conclusion on the necessity to introduce an inter-tier Ground Plane, demonstrating also a novel integration solution.

II. EXPERIMENTS AND SIMULATIONS DETAILS Experiments:

Characterization has been performed on 3D sequential integration devices. Top-tier FDSOI MOSFET are processed at low temperature (LT) (details can be found in [2]) on bottom-tier FDSOI MOSFET fabricated with standard thermal budget. The process specifications are given in Fig. 2(a). The dynamic device characterization was performed using the fast IV module (down to 10ns time resolution) of the Agilent B1530A device parameter analyzer. Simulation tools: For the inter-tier RF crosstalk, we used Ansoft's High Frequency Structure Simulator (HFSS) in conjunction with Silvaco's TCAD suite. The circuit simulations were performed using the Leti-UTSOI model [3].

III. INTER-TIER COUPLING EFFECTS A. Electro-Static Coupling

Experiments were performed on digital top-tier transistors varying the bottom tier transistor gate bias (from 0 to VDD=1V) to extract the threshold voltage shift (∆Vth) due to electrostatic (DC) coupling as a function of gate length (Fig. 3) and are in line with TCAD simulations. The static coupling decreases with the gate length due to the screening by the high source/drain electric field of the top -tier transistor and results in a reduction of the coupling-induced ∆Vth by 5mV for nominal device gate length in 28nm FDSOI technology. This level of ∆Vth is negligible compared to the mismatch related ∆Vth in 28nm FDSOI digital design [4] (Fig. 4). However in the case of bottom devices with VDD up to 2.5V, the coupling-induced ∆Vth becomes significant and a thicker ILD (≥350nm) or a GP layer has to be introduced.

B. Dynamic Coupling

Dynamic switching of the back-plane bias has never been involved in the normal operation of conventional planar integrated circuits. However in 3D sequential integration, the pulse-shaped switching of the bottom transistor gate bias may lead to an important dynamic coupling to the top transistor channel. In order to experimentally determine the importance of this effect, we performed high-speed drain current sampling measurements for a top-tier FDSOI MOSFET during the application of a pulse bias from 0 to VDD at its bottom gate (setup shown in Fig. 5). We chose a bottom instead of a top toptier device because it has a buried oxide (BOX) capacitance almost 5 times higher than the ILD, allowing us to capture more accurately the capacitance-related effects. As shown in Fig. 6(a), it is evident that a parasitic spike occurs in the drain current at the beginning of the back-gate voltage pulse. This spike corresponds to the charging current of the drain-substrate capacitance (Cd,bg) and the peak amplitude, iac, is given by Ohm's law for capacitors. Therefore, as the rise time of the switching event at the back gate gets shorter (Fig. 6(b)), iac is increased, making the dynamic more critical than the DC coupling. TCAD simulations were also performed for the same bias setup and the results are presented in Fig. 8 showing good agreement with the measurements. In order to assess the expected behavior for the top devices, we ran TCAD simulations with the architecture of Fig. 7(a). The effect appears to be the same with the bottom tier devices, however in this case the capacitance of interest can be either due to the fringing fields (Fig. 7(a)) or the parallel plate capacitance (Fig. 7(b)) between the top SOI drain and the bottom SOI gate. To investigate the impact of the geometrical parameters we varied the width WGtop and the length LGtop of the top top-tier devices. As shown in Fig. 8, there is an evident increase of iac with WGtop, while there is no dependence on LGtop. The maximum value of CDtop,Gbot is reached when the gate of the bottom tier device is right underneath the top-tier device drain region (Fig. 7(b) ).

IV. IMPACT ON THE STABILITY OF A SRAM CELL

We examined the configuration of a 3D Sequential 2-bitcell SRAM in 28FD, i.e. two stacked (no inter-tier GP) 6T-SRAM cells that are identical in layout design, so that the inter-tier coupling effects are maximized. Mixed-mode TCAD simulations were performed on a circuit containing the stacked SRAM cells. A schematic of the top-tier circuit is presented in Fig. 9: each transistor is composed by a TCAD structure including the stacked transistors of Fig. 2 (a) and all the necessary physical models. Moreover, the impact of the relative positioning was studied, by placing each top-tier transistor drain in different distances with respect to the bottom-tier transistor gate. We considered two cases: a gate overlap=1 when all bottom-and top-tier transistor gates are perfectly aligned (Fig. 7(a)) and a gate overlap=0 when the bottom-tier gates are aligned with the respective top-tier transistor drains (Fig. 7(b)).

First, we obtained the DC characteristics of the top-tier SRAM circuit for each case of bottom-tier operation (no power supply, stored'0', stored'1') and for the two positioning scenarios (gate overlap=0/1), revealing a coupling induced SNM reduction of only 10 mV for the top tier SRAM (see Fig. 10). Afterwards, we emulated a Read operation on the top tier SRAM cell with '1' stored at the Channel High (CH) node (Fig. 11(a)), and a write operation was emulated for the bottom SRAM showing that the dynamic coupling is not strong enough to result in a Read destructive operation (Fig. 11(b)). The demonstrated immunity of a sensitive digital circuit like SRAM to both static and dynamic coupling shows that digital on digital circuits with 130nm ILD thickness do not need an inter-tier GP.

V. IMPACT ON RF APPLICATIONS C. Ring Oscillator (RO)

In order to assess the sensitivity of top-tier RF circuits on electrostatic coupling due to bottom-tier analog circuits without GP in between, we selected the circuit example of a 3-stage RO (Fig. 12). Fig. 13(a) shows a frequency shift of 510MHz for a 30.5 GHz oscillating signal due to the 2.5V shift of the bottomtier electrode bias. This 1.67% shift is far from negligible for RF applications, therefore a GP layer is needed for inter-tier isolation. However, regarding the phase noise of the top RO, there is no observable impact of DC coupling from the bottom Analog tier (Fig. 13(b)).

D. Intertier RF Crosstalk

Due to the proximity of the two tiers, electromagnetically induced crosstalk can take place between them. Prior work [5] -[10] was carried out for the isolation of active devices targeting planar and 3D technologies, however they require complex process techniques, not suitable for 3D sequential integration. Here we examine an efficient way of inter-tier crosstalk isolation with the insertion of a polysilicon GP between the sequential tiers. In order to estimate the inter-tier RF decoupling efficiency of the GP, we followed the methodology proposed in [11], [12] implementing the simulation setup of Fig. 14 and testing various materials for the GP region (SiO2, PolySi, Copper). The S21 parameter that indicates the forward voltage gain from the in-port (bottom SOI gate) to the out-port (top SOI drain) is used to analyze the intertier crosstalk. Figure 16 shows the TCAD simulation results for the S21 parameter in the frequency range of 0.01-100 GHz for SiO2 (no GP) and a PolySi GP. We observe that increasing the doping concentration of the PolySi GP can help extend the decoupling frequency range: for a concentration of 10 20 cm -3 , there is a 20dB reduction up to 100GHz. Figure 17 also shows the results obtained by HFSS, to test the scenario of a Copper GP. The latter shows 8 dB more crosstalk attenuation than the highly doped polysilicon GP, related to the optimum conductivity of the copper. Repeating the simulation setup of Fig. 16 and expanding the GP area with respect to the top tier device active region we extract the attenuation level as a function of the well GP coverage of the top tier active device region. As Fig. 18 shows, there is a GP sizing that can result to the maximum reduction level, whereas the difference between the two tested materials varies from 3dB to 8dB. However, the increase of the area yields a decrease of the decoupling frequency range, related to the bias attenuation across the GP level. To address this issue, we increased the number of ground (gnd) taps for the GP layer (Fig. 19) up to a total number of 6, indeed observing from figure 20 that both the decoupling frequency range and the suppression level are increased.

E. Inter-tier GP processing challenges and solutions

A polysilicon GP offers several advantages compared to a metallic GP. Firstly, it is compatible in terms of Front End Of Line (FEOL) contamination environment for top MOSFET processing. Secondly, it offers the possibility of dual doping type to propose several VTH flavors without requiring gate stack engineering or channel doping. However, for RF applications where high GP doping level are required, traditional GP doping through the top channel cannot be applied (Fig. 21). To increase the GP doping concentration above this limit, the polysilicon needs to be doped directly after its deposition or deposited using in-situ doped epitaxy. With GP direct doping, a doping concentration of 1.8 x10 20 at/cm 3 has been reached (Fig. 22), enabling one to reach a sheet resistance of 295 Ω/sq for a 34nm-thick polysilicon layer. Therefore, this type of GP answers to all the specifications in terms of doping level and sheet resistance (-20 dB up to 100 Ghz for 1 GP tap), as well as thickness (to preserve the 3D contact aspect ratio (AR)) and FEOL contamination category.

VI. CONCLUSION

Through experiments and simulations we have shown that, for purely digital 3D sequential circuits there is no major coupling between top and bottom tiers, therefore inter-tier GP integration is not needed. However, when it comes to mixed signal and RF applications, a polysilicon GP layer provides the necessary immunity to inter-tier coupling effects like crosstalk. We have also demonstrated a novel integration scheme of inter-tier isolation with a polysilicon GP, highlighting its SOI compatibility and the advantages over metallic solutions.

ACKNOWLEDGMENT

This work was partially supported by the LabEx Minos ANR-10-LABX-55-01 program.

Fig. 1 :

 1 Fig. 1: (a) TEM cross-section of two stacked transistors fabricated in 3D sequential (b) Schematic of structure in a 3D sequential integration scheme with iBEOL.

Fig. 2 :

 2 Fig. 2: Schematic of the devices under study with (a) and without (b) GP. The scope of the study is to conclude on the GP insertion need.

Fig. 3 :

 3 Fig. 3: Threshold voltage shift vs. gate length for top tier SOI. 28FD nominal length devices show better immunity to inter-tier DC coupling.

Fig. 4 :

 4 Fig. 4: Threshold voltage shift due to DC coupling for 2 different stacks of devices. To preserve the same coupling-to-noise margin for Analog bottom-tier devices a thicker ILD (≥350nm) or a GP layer has to be introduced.

Fig

  Fig. 5: Setup for bottom-tier SOI dynamic coupling characterization.

Fig. 6 :

 6 Fig. 6: Dynamic coupling transient results for a bottom tier SOI (W=30um, L=0.5μm) at VG=0.1V. (a) Experimental transient for rt= 30μs with the applied pulse at the back gate of the device (blue) and the measured drain current (red) revealing the parasitic spike iac. (b) TCAD simulation for a shorter rise time (rt=3us) shows that the iac becomes greater than the coupling-induced DC shift (Idc,coupl).

Fig. 7 :

 7 Fig. 7: (a) Setup for top-tier SOI dynamic coupling characterization, (b) worst case scenario (max. CDtop,Gbot), (c) top-tier SOI layout view.

Fig. 8 :

 8 Fig. 8: Peak amplitude of iac vs rise time of the applied pulse at the back gate of the Bottom/Top SOI for Fig.5/Fig.7(a) case. The iac increases with WGtop whereas it does not change with LGtop. Fig. 9: Simplified layout representation of the superimposed SRAM. Each top-tier SOI is comprised by the TCAD structure shown here.

Fig. 11 :

 11 Fig. 11: (a) Read operation for top-tier SRAM cell: The WLtop is enabled and BLLtop discharges to VCLtop. (bottom SRAM off). (b) VCLtop during a write operation (0→1V and 1→0V from t1 to t2) with 10ps rise time (shortest in 28FD [13]) at the bottom SRAM.

Fig. 12 :

 12 Fig. 12: Top tier Ring Oscillator composed of three NOT gates. Up to 2.5V bias is applied at the BG of each top-tier SOI (VDD for bottom-tier SOI with EOT=5nm).

Fig. 13 :

 13 Fig.13: FFT (a) and Phase noise shift (b) for toptier Ring Oscillator with.2.5V bias application at each SOI back-gate.

Fig. 14 :

 14 Fig.14: Simulation setup to determine the GP decoupling efficiency. The GP area is 2x the top active with 1 gnd tap. Inset: Cross-section view.

Fig. 15 :

 15 Fig.15: Threshold voltage shift vs. GP doping concentration. The insertion of the PolySi reduces the DC coupling by 10 5 .

Fig. 17 :

 17 Fig.17: Copper GP offers 8 dB more crosstalk attenuation than the highly doped PolySi GP. The already very high attenuation level and FEOL compatibility make PolySi GP the ideal choice.

Fig. 18 :

 18 Fig.18: Expanding the GP area, suppression level of crosstalk is increased. There is a maximum covering of the top-tier SOI for which GP reaches the suppression limit.

Fig. 19 :

 19 Fig.19: The GP area now is 3x the top active and gradually up to 6 gnd taps are added. Inset:Top-tier layout view.

Fig. 20 :

 20 Fig.20: Crosstalk vs. frequency. A larger PolySi GP needs greater number of gnd taps for decoupling frequency up to 100GHz. Optimum GP size: minimum number of gnd taps (denser integration) for good suppression.

Fig. 21 :

 21 Fig.21: Examples of GP doping conditions (N&P type) through thin channel for SOI devices. GP concentration cannot exceed the 1x10 18 at/cm 3 in order to avoid top channel parasitic doping.

Fig. 23 :

 23 Fig.23: Summary table on the need of inter-tier GP. Fig.24: References