Yoan Decoudu

Matheus Garay

Thiago Leite

Ioanna Kriekouki

Hani Mallough

Halim Saadi

Olivier Occello

Mohamed Tmimi

Antonio Lisboa

Dayana Pino

Giovani Orozco

Ali Al

Sana Ibrahim

Laura Antonietti

Anissa Zerrouki

N Vcm

Keywords: Successive-approximation ADCs, analog-to-digital converters, static linearity test, reduced-code linearity testing, built-in self-test, design-for-test

and also to Florence Podevin and Philippe Ferrari. Thanks also to Mamadou Diallo for all his support with the analog layout of the blocks in this work, and to Abdelhamid Atoumeri and Mohamed Ben Jrad from CIME for their kind support with the simulation software. Special thanks to my office mates Ankush Mamgain, Manasa Madhvaraj (whom I also thank for the help with the HDL debugging), Florent Cilici, and especially to Marc Margalef-Rovira, who started as an office colleague and grew into one of

lished in VLSI and ISSCC (from [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF], adopted from [START_REF] Murmann | ADC Performance Survey 1997-2021[END_REF]). As it can be observed, SAR ADCs dominate the high-efficiency section of the curve. . . . . . . . . . . 6 1. 4 The trend of the power efficiency of SAR ADCs over the last decades [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF][START_REF] Murmann | ADC Performance Survey 1997-2021[END_REF]. . . is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f p = 900 mV and V re f n = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit in the figure for each decision step. . 20 2.12 SAR ADC set-and-down (monotonic) switching with the energy associated to each transition. As it can be observed, the energy for each transition is smaller and also better distributed in comparison to the conventional algorithm. . . . . . 22 2.13 Top-plate voltage of the set-and-down switching SAR ADC. The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f p = 900 mV and V re f n = 300 mV. The output code is 0000101010 as it is explicit on the figure for each decision step. The commonmode voltage converges to V re f n . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 SAR ADC V cm -based switching with top plate sampling. The energy in each transition is smaller in comparison to the previous shown algorithms. . . . . . . . . . 24 2.15 Top-plate voltage of the MCS switching SAR ADC. The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f ,p = 900 mV and V re f ,p = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit on the figure for each decision step. . . . . . . . . . 24 2.16 SAR ADC V cm -based switching with bottom plate sampling. . . . . . . . . . . . 25 vi List of Figures 2.17 Top-plate voltage of the V cm -based switching SAR ADC. The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f ,p = 900 mV and V re f ,p = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit on the figure for each decision step. . . . . . 2.18 Energy consumption of the SAR ADC for each of the considered switching algorithms a) normalized energy and b) percentage of energy saving. . . . . . . . . . IN present-day's society, electronics are taking a prominent position as they become more and more ubiquitous in our daily lives. As predicted more than 50 years ago by Moore's law [1], exponential growth in the number of transistors that can be integrated into a given integrated circuit (IC) has been observed. In that context, the usage of analog and mixed-signal (AMS) circuits has also presented extensive growth. AMS encompasses circuits such as operational amplifiers, PLLs, LDO voltage regulators, analog-to-digital (ADC), and digital-to-analog converters (DAC). Such circuits are key building blocks for a plethora of industrial applications, like automotive, consumer electronics, medical, telecommunications, computing, and others. Decades of this exponential development of design and fabrication technologies for integrated circuits created new operation ranges (higher frequencies, lower voltages/currents, etc), and the also increasing density leads to an implacable reduction in the manufacturing cost per transistor. That opens the way for new applications such as the Internet of Things (IoT), autonomous driving, 5G, etc. This ends up boosting the need for AMS circuits. If one focuses on the particular example of IoT, a large quantity of AMS systems are necessary. In such an environment, objects are connected through a network and they interact and respond to the environment around them. To enable such capabilities, several AMS circuits need to be applied, such as the sensors used for pervasive sensing and their front-end signal conditioning circuits such as analog filters and instrumentation amplifiers, data converters for allowing the data to be treated in the digital domain and reconverted to the analog domain for driving actuators, transceivers for transmitting/receiving the data, amongst others.

IC testing challenges

The fabrication process of an integrated circuit includes several steps of printing, masking, etching, implanting, and chemical vapor deposition. As in any industrial process, these steps are susceptible to imperfections that might introduce failures to the operation of the fabricated device. Due to the abstraction level inherent to digital operations, that work with a limited number of well-defined signal levels, digital circuits are intrinsically more robust to these variations. On the other hand, state-of-the-art AMS circuits are extremely sensitive even to the slightest variations in the fabrication process.

In that context, we can define the act of testing an IC as the process of verifying if a given IC meets its aimed specifications [2]. The development of the electronics industry is driven -as it is with any other competitive industry -by the ability to provide more value for less money, and the validation of the circuit operation before commercialization is a fundamental step in this chain. The goal of IC testing in this picture is the screening of such defects, in a way that manufacturers can assure the performance of their designs to the end-user. However, testing ICs is a very expensive process. Indeed, as it was shown in the ITRS report [3], the cost of testing becomes more and more significant in comparison to fabrication costs as technological advancements move forward. What can be observed is that while the fabrication cost per transistor is steadily dropping over several decades, the test cost tends to rise, or in the best-case scenario remain constant. Indeed, the increase in complexity within a single die with the advent of systems on a chip (SoCs) highly increases the challenge of testing such intricate systems, especially for AMS ICs.

Functional tests using automated test equipment (ATE) are the most widely spread form of AMS IC testing, and that helps to explain the high cost associated with the post-fabrication validation process for AMS ICs. Functional testing consists of the direct measurement of the circuit performance in comparison to the intended one. To attain that goal, the test equipment must outperform the circuit under test by a given margin. Also, considering the conceptual schematic in Figure 1.1, an ATE must include test stimulus generators to be provided as the input for the circuit under test, acquisition instruments to receive and process the output of test circuitry, and power supplies and loads to activate the circuit under test. All this adds up to very expensive test equipment. This high cost might be further increased if the dedicated test board require also use of I/O circuitry responsible for adapting the ATE inputs and outputs to communicate with the device under test, and interfaces to access and establish all connections between both systems. As the specifications of the circuit under test become more stringent, the more challenging it becomes for the ATE to outrun these specs and correctly characterize the circuit under test, further increasing its price. Another aspect worthy of note regarding functional testing is that even though it allows for on-site testing on the factory floor, it can not warrant anything regarding drifts over time. Dedicated accelerated aging test such as burn-in or stress voltage are required to estimate the reliability of the IC.

A known alternative to functional test is the so-called structural test, which measures if defects are present or not in the circuit. Structural test is so widely deployed for built-in self-test (BIST) of digital ICs that it can be called the counterpart of functional testing for AMS ICs. The idea behind this test approach is that since a defect-free design should achieve its intended functionality by definition (inside the margin of process variations), it is intuitive to assume that the detection Chapter 1. Introduction of defects in a given IC is a legitimate form of assuring its correct operation. Even though this assumption is generally correct, in a practical case it is virtually impossible to search and detect every physical defect in a given chip. Therefore, structural tests necessarily come associated to a statistical level of confidence related to the number of faults that can be detected by a particular test. Also, structural tests are based on fault models, which are not straightforward to define. Though being a technique associated with digital testing, analog structural test has recently gained a lot of interest in safety-critical applications where quality and reliability are of extreme importance (automotive, aerospace, health, etc) [4,5]. Indeed, defects that induce no performance loss at production time might be inadmissible as a possible hazard for the operation of the circuit in its real application scenario [START_REF] Leger | Mixed-signal test automation: are we there yet?[END_REF].

Despite advances to define analog fault models [7], functional testing is still the standard for evaluating the performance of AMS circuits. These tests are ATE-based and unlike structural testing of digital ICs, no general solution for BIST was developed. To further aggravate that, the challenges for the external tester systems are inevitably increasing due to the evolution of device under test (DUT) specifications, demanding large storage space for data acquisition, high-performance instruments for computation, and extremely linear stimulus. For instance, the measurement of an N-bit data converter demands the measurement of 2 N codes with a stimulus whose linearity is higher than at least a few times the linearity of the ADC under test, usually two or three bits of margin [START_REF] Renaud | Fully differential 4-V output range 14.5-ENOB stepwise ramp stimulus generator for on-chip static linearity test of ADCs[END_REF]. For noise averaging, a few measurements per code are needed, further increasing the number of measurements necessary for its complete characterization. The increase in ATE complexity necessarily leads to the increase of its cost [3]. Indeed, the rapidly advancing integration rate on system-on-chip (SoC), which includes digital and AMS circuits, often might include also optical, RF circuits, MEMS, etc, complicating the access to internal blocks and requiring dedicated test access. Furthermore, as it was shown in [START_REF] Poehl | production test challenges for highly integrated mobile phone socs -a case study[END_REF], the testing of mixed-signal, RF, and power management blocks dominate the overall test time. Typically, mixed-signal circuits occupy an area that is less than 5 % in a modern SoC, but it can take up to 30 % of the total test time.

Indeed, reliability and quality enhancement is becoming one of the main drivers for the development of analog and mixed-signal BIST. In that context, BIST techniques emerge as a very promising candidate for the cost-effective characterization of AMS circuits. Even though they were first developed for digital testing, they have also been applied for the characterization of AMS and RF designs [START_REF] Barragán | Some) open problems to incorporate BIST in complex heterogeneous integrated systems[END_REF]. In the last few years, there have been several advances to develop analog/RF BIST strategies [START_REF] Jeong | Built-in self-test for stability measurement of low dropout regulator[END_REF][START_REF] Beohar | Online built-in selftest of high switching frequency DC-DC converters using model reference based system identification techniques[END_REF][START_REF] Yilmaz | Test Application for Analog/RF Circuits With Low Computational Burden[END_REF][START_REF] Elsayed | A low THD, low power, high output-swing timemode-based tunable oscillator via digital harmonic-cancellation technique[END_REF][START_REF] Fan | A current injection built-in test technique for RF low-noise amplifiers[END_REF][START_REF] Aouini | Anti-imaging time-mode filter design using a PLL structure with transfer function DFT[END_REF][START_REF] Cilici | A Nonintrusive Machine Learning-Based Test Methodology for Millimeter-Wave Integrated Circuits[END_REF][START_REF] Bounceur | Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model[END_REF][START_REF] Stratigopoulos | Adaptive test with test escape estimation for mixed-signal ICs[END_REF][START_REF] Azaïs | Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs[END_REF]. In this regard, a wide variety of BIST techniques for ADCs have been explored [START_REF] Renaud | Fully differential 4-V output range 14.5-ENOB stepwise ramp stimulus generator for on-chip static linearity test of ADCs[END_REF][START_REF] Barragan | A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio Σ∆ ADC[END_REF][START_REF] Laraba | Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique[END_REF][START_REF] Azaïs | A low-cost adaptive ramp generator for analog BIST applications[END_REF][START_REF] Pavlidis | SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety[END_REF][START_REF] Arteaga | Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus[END_REF][START_REF] Chen | USER-SMILE: Ultrafast stimulus error removal and segmented model identification of linearity errors for ADC built-in self-test[END_REF][START_REF] Duan | Low-cost dithering generator for accurate ADC linearity test[END_REF][START_REF] Xing | High-resolution ADC linearity testing using a fully digital-compatible BIST strategy[END_REF][START_REF] Chen | A low-cost on-chip built-in self-test solution for ADC linearity test[END_REF]. The idea is to move some of the ATE functionalities into the circuit under test, lowering the constraints to the external ATE and simplifying the test protocol. Generally, the use of BIST for AMS on-chip testing aims to keep a high test quality while reducing the overall test cost. A BIST implementation might bring benefits on the following points:

É Test time and effort: moving the majority or even all of the test instruments on-chip allows for a strong reduction regarding the test time to set up and configure an external ATE.

É Self-testability: with respect to the aforementioned disadvantage of being able to measure in the factory only, a full-BIST implementation allows for the self-test in the real operating environment of the chip without the need for external ATE. This opens the way for real-time calibration, self-healing, and operation in safety-critical and mission-critical applications.

For instance, in safety-critical applications such as automotive, mixed-signal BIST is even becoming a design requirement in many integrated systems.

É Access complexity: as it was also aforementioned, the access to individual blocks of a given SoC might not be a straightforward task. A BIST approach allows for a significant reduction of the number of I/O pins required to connect the SoC to an external tester.

É Test accuracy: by moving the tester on-chip, one might eliminate several limitations brought by the external ATE or by the noise and other error sources generated on the test board. A conceptual block diagram of a full-BIST scheme for testing AMS systems is depicted in Figure 1.2. Usually, it consists of an on-chip stimulus generator, whose type will depend on the type of test to be performed (sinusoidal, ramp, square, or an arbitrary waveform). A response analyzer is used for treating the output of the AMS circuit under test. A BIST controller is responsible for managing the test and standard operation modes, and the steps that are needed in order to characterize the circuit being measured. A few features that are important to guarantee in a BIST design are low area overhead, low design effort, low power consumption, robustness to aging, and PVT variations, amongst others. The more these constraints are guaranteed, the more the characterization is accurate while the increase in the overall cost of the chip is kept contained.

Analog-to-digital converters

The use of pure AMS circuits for analog processing for SoCs is becoming too costly and often even unfeasible. Digital signal processing (DSP) units offer crucial capabilities such as higher reproducibility, large access to data storage, and the possibility of carrying out complex algorithms that enable new features within the context of the unprecedented computational power of DSPs. In order to be able to harvest these benefits related to the higher densities of transistors in modern technological nodes and of the advantages of DSPs, data conversion at the beginning of the chain is needed to allow the translation from the analog domain to digital and vice-versa. Hence, ADCs and DACs are key design blocks that will dictate the overall performance that can be achieved by a given digital system.

It is known that different ADC topologies display different performances and are hence used in different applications. One of the most crucial existing trade-offs is the one between resolution and speed. The high-resolution range is dominated by Σ∆ converters. Since the Σ∆ architecture is based on oversampling, their application is mostly limited to the low-speed range, such as audio and some biomedical applications. On the other limit, high-speed applications are dominated by flash, pipelined, and folding topologies. Pipelined ADCs are also used for applications that Chapter 1. Introduction Figure 1.3: A plot of the energy efficiency versus the SNDR for different ADC topologies published in VLSI and ISSCC (from [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF], adopted from [START_REF] Murmann | ADC Performance Survey 1997-2021[END_REF]). As it can be observed, SAR ADCs dominate the high-efficiency section of the curve.

require medium-to-high resolution and conversion rate. SAR ADCs are used for medium-tohigh resolutions and low-to-medium conversion rates, with considerable overlap with applications where the pipelined topology is also applied.

Figure 1.3 provides an overview of state-of-the-art ADCs published in key technical conferences in the AMS field (VLSI and ISSCC from 1997 to 2017). The energy per sample of the converters is plotted as a function of their signal to noise and distortion ratio (SNDR) [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF][START_REF] Murmann | ADC Performance Survey 1997-2021[END_REF]. As it can be observed, the SAR ADC is one of the most power-efficient architectures. To further investigate that, the trend of the energy consumption for SAR ADCs is plotted as a function of time in Figure 1.4. The power-efficiency of SAR ADCs has been steadily increasing over several decades, and a factor of more than a thousand times reduction in power consumption can be observed for SAR ADCs in the last 20 years [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF].

Even though the advantages of technology scaling are a very positive factor for digital design, the same can not necessarily be said regarding AMS design. For instance, despite the f T of transistors being highly increased, the larger Early effect of small transistors considerably reduces the intrinsic gain g m r O . To make things even worse, the scaling of the threshold voltage is a lot less significant in comparison to supply voltage scaling [START_REF] Jespers | The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches[END_REF]. This reduces the available output swing for analog amplifiers, which highly limits the possibility of applying cascoding techniques for boosting the gain and improving linearity. Smaller transistors are also more prone to process variations, and they are also limited by second-order effects such as drain-induced barrier lowering (DIBL), velocity saturation, gate current leakage, and parasitic drain/source resistances [START_REF] Schneider | CMOS analog design using all-region MOSFET modeling[END_REF]. This fact limits the application of pipelined ADCs in deep-scaled technology nodes. On the other hand, the SAR ADC is an amplifier-free topology, which makes it a very digital-friendly architecture. Because it yields a lot more benefits of digital scaling and suffers less from the drawbacks imposed to AMS design, together with its high power efficiency and ability to go on sleep mode, the SAR ADC is rapidly taking over speed and resolution ranges that used to be dominated by pipelined ADCs.

However, SAR ADCs are still prone to errors that might reduce their linearity and performance. These errors are mostly caused by mismatches between its internal components. Espe-1.4. Thesis motivation and outline Figure 1.4: The trend of the power efficiency of SAR ADCs over the last decades [START_REF] Alioto | Enabling the Internet of Things: From Integrated Circuits to Integrated Systems[END_REF][START_REF] Murmann | ADC Performance Survey 1997-2021[END_REF].

cially in high power-efficient designs, where the unit capacitance needs to be made as small as possible (in the order of a few fF or even below that value for customized MoM capacitors), the process variability can damage the overall yield due to the increased average mismatch and consequent reduction of the converter's linearity. Hence, testing and validating these ADCs is becoming even more important.

Thesis motivation and outline

The SAR ADC is one of the most relevant and surface/power-efficient architectures applied nowadays in a plethora of applications. Due to the increased challenges of analog design for deep-scaled technologies, it is also slowly replacing pipeline ADCs for medium-resolution and medium-speed applications. However, SAR ADCs are very prone to static errors, and the main source of these errors is the mismatches in the components used for implementing the internal DAC of the ADC. Static linearity tests are then necessary to assure the correct functionality of the converter.

This work proposes alternative test techniques for the static characterization of SAR ADCs. These techniques focus on reducing the overall test time of ADC testing, consequently highly reducing the cost associated with testing. By implementing such techniques in a BIST fashion, the overall test cost can be further decreased. This thesis is organized as follows.

Chapter 2 covers the basic operation of SAR ADCs. Its main operation is presented, and the main sources of static errors are analyzed. Finally, some of the main switching schemes to implement power-efficient architectures are presented.

Chapter 3 tackles the static linearity characterization of ADCs, presenting the classical techniques and reviewing some of the alternative and BIST techniques proposed in the literature. The contribution of this thesis starts to be presented in this chapter. Strategies based on major carrier transitions and segmented-based DACs are presented to simplify the SAR ADC characterization. Behavioral-level simulations are presented in order to validate the operation of the proposed techniques. In Chapter 4 a practical BIST implementation is introduced in order to carry out the measurements needed for the implementation of the proposed alternative test techniques. The Chapter 1. Introduction trade-offs linked to the design of the BIST circuitry are also considered. After obtaining the highlevel specifications, the circuit-level requirements are derived for the design of the blocks related to the proposed architecture.

Chapter 5 targets the circuit-level design of a proof-of-concept prototype. A complete design of a SAR ADC case study is performed from scratch, including the auxiliary blocks such as reference buffers and clock reconstruction circuits. The complete design of the BIST circuitry is also provided. Simulation results at transistor and post-layout level are provided to validate the feasibility of the proposed on-chip test technique.

Finally, Chapter 6 epitomizes the work performed in this thesis and discusses the directions for future research on this topic.

2

The Successive Approximation ADC This chapter covers the basic operation of SAR ADCs. Its general operation is explained, and the most relevant architectures are presented. The static non-linearities of a general ADC and its sources in a SAR ADC implementation are explained. Finally, the main SAR ADC switching algorithms for energy saving are presented and its performances compared. This introduction to SAR ADCs is not to be considered as an exhaustive review. Instead, it is intended for introducing concepts that will be useful for a better understanding of the test techniques that will be presented in later chapters.

SAR ADC basic operation

SAR ADC basic operation

The typical block diagram of a generic SAR ADC architecture is shown in Fig. 2.1. Its basic block diagram consists of a sample/hold (S/H) circuit, a DAC, a comparator and the SAR control logic [START_REF] Maloberti | Data converters[END_REF][START_REF] Pelgrom | Analog-to-digital conversion[END_REF]. Its operation relies on a binary search through the DAC. The sampled input voltage is compared to the reference voltage in the output of the DAC, and each subsequent cycle gives a better approximation of the input, as illustrated in Fig. 2.2 for a 4-bit example. The S/H has to hold the signal constant throughout the whole SAR operation. Note that an N-bit SAR ADC needs at least one clock cycle for sampling plus N clock cycles for realizing the conversion, thus N + 1 cycles. The SAR logic controls the DAC output based on the output of the comparator for each cycle.

Sample/Hold

N

Digital to Analog Converter

SAR Logic

Output Bits Theoretically, any DAC topology can be used in the SAR ADC, but due to the fact that capacitive DACs (CDACs) do not experience static consumption, present good matching, small area, and can provide intrinsic S/H capabilities, they are the most applied DAC topology for SAR ADCs. Also, several other variations exist, such as the hybrid resistor-capacitor [START_REF] Chen | A successive approximation ADC with resistorcapacitor hybrid structure[END_REF], and the hybrid SAR + Σ∆ ADC [START_REF] Almarashli | A Nyquist rate SAR ADC employing incremental Sigma Delta DAC achieving peak SFDR= 107 dB at 80 kS/s[END_REF], to cite some examples. Time-interleaving can be also applied to SAR ADCs in high-speed applications such as communications. The major contribution of this thesis is the development of static-test techniques for charge redistribution SAR ADCs. This choice was based on the fact that the vast majority of the highly power-efficient SAR ADC designs mentioned in the bottom part of Figure 1.4 are based on charge redistribution. For this reason, this chapter will focus on describing and analyzing the functionality of this family of SAR ADCs.

Therefore, the so-called charge redistribution SAR ADC architecture is illustrated in Figure 2.3. In this capacitive array approach, the CDAC merges the S/H function to perform the binary search in the charge domain. Note that the energy consumption is dynamic, enabling very low power design. At the end of the last cycle, the voltage in the CDAC output -which represents the conversion error (or residue of the conversion) -converges to zero (V cm ). The capacitors are binary weighted, i.e. C i = 2 i C u for i = 0, 1, ...N -1, where C u is the unit capacitor of the array. A dummy capacitor of value C u is added such as the total capacitance of the array is given by

C tot = C u + N-1 ∑ i=0 C i = 2 N C u .
(2.1)

In the sampling phase (Figure 2.3a) all capacitors are connected to V in and the top plates are connected to the ground, and the total charge is given by

Q tot = -V in C tot . (2.2)
Chapter 2. The Successive Approximation ADC After the sampling phase, the conversion phase is started (Figure 2.3b). It is assumed that V re f p = V re f and V re f n = 0 V for simplifying the calculations without much loss of generality. The first step of conversion consists of connecting the MSB capacitor to V re f and the remaining capacitors to the ground. By charge conservation, it can be shown that the charge in the array is now given by:

V in

MSB = 0 MSB-1=1 MSB-2=0 LSB=1 V DAC V ref 3/4V ref 1/2V ref 1/4V ref
Q tot,2 = (V X -V re f )C N-1 +V X (C tot -C N-1 ) (2.3)
and by charge conservation, the equations 2.2 and 2.3 have the same value. Hence, by rearranging the two equations, the voltage on the CDAC output is given by

V X = -V in + C N-1 C tot V re f = -V in + V re f 2 . (2.4)
This voltage is then compared using the comparator. If V X > 0, the input voltage is below half of the full-scale of the SAR ADC and hence the most significant bit d N-1 = 0 and V re f stays connected to the capacitor C N-1 ; otherwise, d N-1 = 1 and capacitor C N-1 is connected to ground. Subsequently, this process continues for the next capacitor, namely C N-2 . Either

V X = -V in + V re f 2 + V re f 4 = -V in + 3V re f 4 , (2.5)
in the case of Figure 2.3c, or

V X = -V in + V re f 4 , (2.6)
as shown in Figure 2.3d. This procedure is repeated until the least significant bit, and the output binary code is given by

[d N-1 , d N-2 ...d 1 , d 0 ].

Split-DAC SAR ADC

The exponential increase of the input capacitance of a classical CDAC with the number of bits N may impose a considerable penalty on the surface and power consumption of middle-tohigh resolution SAR ADCs. For instance, a 14-bit CDAC with a unit capacitor of 40 fF has a total capacitance of about 655 pF, which can become very unpractical and costly to implement, especially in sub-micron technological nodes. Further, the design of the input buffers to load such a high capacitance would become too intricate and power-hungry. One way to overcome that is by using the so-called split-capacitor DAC (SCDAC) SAR ADC, as it is depicted in Figure 2.4. A bridge capacitor C B is inserted between the two partial binary-weighted CDACs, reducing the total occupied area and power consumption. The resolution of the SCDAC is N = M + L, where M and L are the MSB and LSB partial CDACs resolution, respectively. One drawback of this implementation is the reduced linearity due to the extra parasitics associated with C B . The total Chapter 2. The Successive Approximation ADC

SAR Logic

C u C u 2C u 2 M-2 C u 2 M-1 C u V in V refp V refn C u 2C u 2 L-2 C u 2 L-1 C u C B V X V A
C MT = M-1 ∑ i=0 2 i C u = (2 M -1)C u , (2.7)
while the total capacitance of the LSB sub-DAC is

C LT = C u + L-1 ∑ i=0 2 i C u = 2 L C u . (2.8)
Note that the weight of the LSB CDAC and the bridge capacitor seem from the MSB DAC should be equal to the weight of the LSB capacitor of the MSB CDAC, hence

C B 2 L C u = C u , which solved for C B gives C B = 2 L 2 L -1 C u .
(2.9)

It is important to remark that this leads to a capacitor that is not an integer multiple of C u , which intricates the matching of the bridge capacitor with the rest of the capacitors in the array. This adds up to the extra parasitics drawback of using a SCDAC, potentially increasing the harm inflicted on the converter's linearity. The operation of the SCDAC SAR ADC can be better understood considering the equivalent models in Figure 2.5. The switching of the i-th capacitor of the MSB array can be represented by the model in 2.5a, and the output voltage change of the DAC is given by:

∆V X = V re f C i C MT + (C B C LT ) = V re f C i C MT +C u , (2.10)
since C B C LT is ideally equal to C u . Considering the equivalent circuit when the i-th capacitor C i in the LSB partial CDAC is being switched (Figure 2.5b), it can be written:

C L,T C i C B V A C M,T -C i V ref V X C M,T C i C B V A C L,T -C i V ref V X a) b)
Figure 2.5: Equivalent circuits for the SCDAC, a) MSB partial CDAC is switching and b) LSB partial CDAC is switching.

∆V A = V re f C i C LT + (C B C MT ) = V re f C i C LT + C B C MT C B +C MT .

Static Error Sources in SAR ADCs

Then, the voltage change at the actual output can be calculated as:

∆V X = ∆V A C B C B +C MT = V re f C i C B C LT (C B +C MT ) +C B C MT . (2.11)
To further simplify the understanding of the SCDAC SAR operation, let us consider a simple example of a 4-bit (2 × 2) array. In such scenario, note that C MT = 3C u , C LT = 4C u , and C B = (4/3)C u . According to 2.10, for the MSB capacitor 2C u , the voltage change when this capacitor is connected to V re f is given by V re f (2/4) = V re f /2. It is not hard to show that for the next capacitor of value C u , the voltage step is given by V re f /4. For the LSB array, when the capacitor 2C u is connected, it can be seen through equation 2.11 that the voltage step is given by V re f /8, which is the expected weight for the MSB-2 capacitor. Finally, when evaluating the voltage change for the LSB capacitor C u , this computation yields a value of V re f /16, the LSB of a 4-bit converter. Hence, neglecting the effects of capacitor mismatch and parasitics, the same voltage weights as the classical CDAC SAR ADC are obtained, but yielding the aforementioned improvements on surface and energy efficiency.

Static Error Sources in SAR ADCs

It is important to point out that for the capacitive ratios calculated in Sections 2.1 and 2.2, it was assumed that no mismatches exist in the components that constitute the SAR ADC. In a real case, several fabrication practical issues may limit the performance of the converter. For instance, the random mismatch variation between the comparator's transistors causes it to present a voltage offset between its inputs. On the DAC array side, the random mismatch variation between capacitors causes the binary weights to deviate, which leads to deteriorated linearity. The main static parameters of an ADC are differential nonlinearity (DNL), integral nonlinearity (INL), gain error, and offset error.

The input offset error is defined as a linear shift from a given ADC transfer function in relation to its ideal curve. It is usually caused by offsets in the internal components of the ADC. One example of a transfer function with a positive offset of 1 LSB is illustrated in Figure 2.6. It can be evaluated simply by connecting the input to the ground and measuring the corresponding output. If the output is non-zero for a zero input, the offset is negative. If the offset is positive, it can be calculated as the difference between the actual transition and the ideal transition of the ADC, namely

ε os = V actual T L -V ideal T L .
(2.12)

On the other hand, the gain error is defined as the variation in the slope of the ADC transfer characteristic, as illustrated in Figure 2.7. For a SAR ADC, as it can be observed in Figure 2.3, only one comparator is used. That means that the gain and offset errors can be easily corrected 1 .

The DNL is defined as the deviation between the ideal step length of a code and its real length (after removing gain and offset errors). This idea is illustrated in Figure 2.8. In other words, it describes the uniformity of the LSB step sizes along the codes of the converter [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF]. For an ideal converter, all the steps are one LSB in size, and hence the DNL is zero for all codes. When the DNL is specified without mention to a specific bin, it refers to the maximum value of the absolute DNL over the entire range. If the absolute value of the DNL is bigger than 1, the ADC may have missing codes in its transfer characteristic. Indeed, this is true for the negative case, since the DNL is always defined in an interval [-1, ∞). The i-th DNL value can be calculated by

V in

Output Code

Ideal ADC ADC with gain error

DNL i = V tl,i -V tl,i-1 V LSB -1, (2.13
) transfer characteristic, and V LSB = V re f /2 N is the ideal LSB step of the converter. Note that the first term of equation 2.13 represents the code with W i in LSB. Hence

from i = 1 to i = 2 N -1,
DNL i = W i -1.
Once the DNL is obtained, INL can be directly evaluated. It represents the total deviation between the ideal transfer function line and the actual transfer characteristic of the ADC. It can be obtained by performing the running sum of the DNL

INL i = i ∑ j=1 DNL j .
(2.14)

Similarly to the DNL, it is common to find the INL of an ADC simply by the maximum of |INL| over the entire transfer characteristic. Note also that

DNL i = INL i -INL i-1 , (2.15)
which provides an alternative approach to compute the INL from the DNL.

SAR ADC switching schemes

Previously in this thesis, the recent growing need for energy-efficient converters was addressed. In that context, the use of a SCDAC instead of a conventional CDAC to highly decrease power consumption in a SAR ADC was explained. Adding to that idea, it is important to comment on the extensive research effort that has been put on in order to reduce the SAR ADC power consumption by using different switching schemes [START_REF] Ginsburg | An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[END_REF][START_REF] Chang | A 8-bit 500-KS/s low power SAR ADC for bio-medical applications[END_REF][START_REF] Liu | A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13µm CMOS process[END_REF][START_REF] Hariprasath | Merged capacitor switching based SAR ADC with highest switching energy-efficiency[END_REF]. That comes after the realization that the conventional switching used in SAR ADCs does not move the charges in the most effective way [START_REF] Ginsburg | An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[END_REF]. To tackle that issue, in the first part of this section, a simplified CDAC model to calculate Chapter 2. The Successive Approximation ADC the voltage and energy in SAR ADCs will be presented. Then, in the second half of the section, a summary of the most relevant switching schemes in the literature will be described, also providing a brief comparison of the advantages and drawbacks of each technique.

V ref V ref C i C R C G V ref V ref C i C R C G V X V X V cm a)

Models for voltage and energy in SAR ADCs

For this model [START_REF] Rabuske | Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications[END_REF], it is assumed that the comparator has infinite input impedance and hence does not play a role in the calculation (later in this thesis, the effect of the parasitic capacitances will be taken into account). The reference voltages are again V re f and ground. A simplified model is shown in Figure 2.9a. The capacitor C R represents the sum of capacitors whose bottom plates are connected to V re f , while C G represents the sum of capacitors whose bottom plates are connected to the ground. The remaining capacitor C i represents the capacitor being switched. Note that

C tot = C i + C R + C G .
At time t = 0 -, the switch S i is connected to ground and at t = 0 + it is connected to V re f . Assuming all voltages and currents have settled at time T ck , where T ck is the clock period, the discrete voltages V X (0) = V X [i -1] and V X (T ck ) = V X [i] can be defined. By charge conservation, it can be written

Q X [i -1] = Q X [i]. (2.16)
Then, by evaluating all the charges at node X:

C i V X [i -1] +C R (V X [i -1] -V re f ) +C G V X [i -1] = = C i (V X [i] -V re f ) +C R (V X [i] -V re f ) +C G V X ,
which can be simplified as:

V X [i] = V X [i -1] + C i C i +C R +C G V re f = V X [i -1] + C i C tot V re f . (2.17)
This equation is a generalized version of 2.4, but in this form, it is very convenient for implementing the behavioral models in code, as it will be done later in this work. If S i is switched from V re f to ground, then equation 2.17 becomes

V X [i] = V X [i -1] - C i C tot V re f . (2.18)
Regarding the energy, note that the instantaneous power is given by P(t) = V re f I re f (t), and that I re f (t) can be written as

I re f (t) = - dQ C R dt + dQ C i dt .

SAR ADC switching schemes

So the energy E re f can be obtained by

E re f = T ck 0 P(t)dt = -V re f T ck 0 dQ C R dt + dQ C i dt dt = = -V re f Q C R (T ck ) Q C R (0) dQ C R + Q C i (T ck ) Q C i (0) dQ C i = -V re f (Q C R [i] -Q C R [i -1] + Q C i [i] -Q C i [i -1]).
By calculating the charge like previously, the energy can be rewritten as

E re f = V re f C i (V re f +V X [i -1] -V X [i]) -V re f C R (V X [i -1] -V X [i]), (2.19)
and by substituting Equation 2.17 into 2.19, it can be written

E re f = V 2 re f C i 1 - C i C i +C R +C G -V 2 re f C R C i C i +C R +C G ,
which can be finally simplified to

E re f = C i C G C i +C R +C G V 2 re f = C i C G C tot V 2 re f . (2.20)
This equation together with 2.17 can be used for calculating the energy and CDAC voltage when only two references are used. It is important to point out that equation 2.20 is only valid if one capacitor is switched at a given transition. Yet, it can be extended to include more references. Indeed, as it will be shown shortly, V cm will be applied as a third voltage reference. In that case, let us consider the simplified model with three references in Figure 2.9b. Let us also assume without much loss of generality that V cm = V re f /2. The switch S i moves from V cm to ground or V re f . It is not hard to prove by following the same steps as before that either if S i transitions from V cm to V re f or to ground, the switching energy for moving this new charge will be given by

E re f = C i C G C i +C R +C G V 2 cm = C i C G C tot V 2 re f 4 , (2.21)
i.e. a factor of 4 times smaller than using V re f . That fact will be exploited subsequently in order to scale down power consumption in the SAR ADC.

Switching algorithms

Comprehensive research efforts have been directed to the reduction of SAR ADC energy consumption [START_REF] Ginsburg | An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[END_REF][START_REF] Chang | A 8-bit 500-KS/s low power SAR ADC for bio-medical applications[END_REF][START_REF] Liu | A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13µm CMOS process[END_REF][START_REF] Hariprasath | Merged capacitor switching based SAR ADC with highest switching energy-efficiency[END_REF]. In the scope of this work, some relevant switching algorithms are presented, including conventional switching as the reference, set-and-down (also called monotonic), merged capacitor switching (or V cm -based with top sampling), and V cm -based switching.

Conventional Switching

A fully differential conventional SAR ADC algorithm with the energy of each transition is summarized in Figure 2.10 for a 3-bit ADC. That is done in order to simplify the calculations and it can be easily extended for larger resolutions. Also, the voltages at the inputs of the comparator for a differential input voltage of V in = -550 mV with V re f p = 900 mV and V re f n = 300 mV are shown in Figure 2.11. The energy used to move the charges in each operation can be calculated using equation 2.20 where only one capacitor transitions. If two capacitors are switched, like is the case for the down transitions, 2.19 can be directly applied to obtain the switching energy. It is important to observe that even though the conventional algorithm does achieve its goal which is performing Chapter 2. The Successive Approximation ADC The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f p = 900 mV and V re f n = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit in the figure for each decision step.

4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V in,p V in,n V in,n V in,n V in,n V in,p V in,p V in,p 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref V ref V ref E ref =4C u V ref 2 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref V ref 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref E ref =C u V ref 2 E ref =5C u V ref 2 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref V ref 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref 4C u C u C u 2C u 4C u C u C u 2C u V cm V cm V ref V ref E ref =1/4C u V ref 2 E ref =13/4C u V ref 2 E ref =5/4C u V ref 2 E ref =9/4C u V ref 2 V ref V ref V ref V ref V ref V ref V ref V ref V ref V ref V ref
2.4. SAR ADC switching schemes the sample and binary search operation, it does not without unnecessary waste of energy. Further, notice that the total energy to move the charges in up and down transitions is highly unbalanced. As a consequence, the total energy dispensed to convert a given sample is a strong function of the input voltage. Since the sampling of the input is performed in differential mode, the top-plates in Figure 2.10 are connected to V cm . Notice however that the bottom plates are only switched between the references V re f and ground. After the sampling operation, V re f is connected to the MSB capacitor and the remaining capacitors are connected to the ground. Since it is a fully differential operation, the negative CDAC does the opposite, and the energy to perform that is 4C u V 2 re f . If V in,p > V in,n , the output of the comparator is 1 and an up transition is taken, with a energy cost of C u V 2 re f . However, if V in,p < V in,n , the output of the comparator is 0 and the energy consumption of the down transition is 5C u V 2 re f . This is due to the fact that the charge in capacitor 4C u is not recycled to capacitor 2C u , it is lost and the energy to charge capacitor 2C u is re-drawn from the supply. Assuming that the probability of each code is the same throughout the transfer characteristic of the ADC, the average energy consumption of an N-bit conventional SAR ADC can be derived as [START_REF] Chang | A 8-bit 500-KS/s low power SAR ADC for bio-medical applications[END_REF]

E conventional = N ∑ i=1 2 N+1-2i (2 i -1)C u V 2 re f = 2 -N+1 + 2 N+2 3 -2 C u V 2 re f . (2.22)

Set-and-down switching

To try and solve the issue of waste of energy on the conventional SAR ADC, [START_REF] Liu | A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13µm CMOS process[END_REF] proposed an algorithm where only discharge takes place. Figure 2.12 illustrates the operation of the set-anddown (also called monotonic switching) with the energy needed for each transition. Note that the array has half of the capacitance of the conventional algorithm, and this is achieved by performing top-plate sampling, which eliminates the need for the MSB capacitor. In the sampling operation, the bottom plate of all capacitors is connected to V re f and the top plates to the inputs, so the MSB can be determined without switching any capacitor. The second issue that the algorithm tackles is the problem of charging and later discharging the same capacitor, which does not happen here, neither for up and down transitions. Depending on the result of the comparison, the positive or the negative CDAC transitions from V re f to ground. The same procedure is performed until the last bit, reducing the CDAC differential voltage-which can also be seen as the conversion error-towards 1 LSB. Nonetheless, as can be seen in Figure 2.13, where the top plate voltage is illustrated, the common-mode voltage of the CDAC has a large variation throughout the conversion. This can introduce nonlinearities and undermine the performance of the converter, considering that the input capacitance of the comparator and the top-plate parasitics of the capacitors are strongly dependent on this voltage. Even more crucial, this can cause modulation of the input-referred offset of the comparator [START_REF] Rabuske | Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications[END_REF], further degrading the performance of the ADC. Finally, designing a comparator that meets the specifications in a large input range can pose a challenge, making the converter design more complex and time-consuming. The energy consumption of the set-and-down switching, again assuming equiprobability of the codes, can be written as

E set-and-down = N-1 ∑ i=1 2 N-2-i C u V 2 re f = 2 N-2 - 1 2 C u V 2 re f . (2.23)
Chapter 2. The Successive Approximation ADC

C u C u 2C u C u C u 2C u V in,p V in,n E ref =0 E ref =C u V ref 2 E ref =C u V ref 2 E ref =1/4C u V ref 2 E ref =3/4C u V ref 2 E ref =3/4C u V ref 2 E ref =1/4C u V ref 2 V ref V ref V ref V ref V ref V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V ref V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V ref C u C u 2C u C u C u 2C u V ref V ref V ref C u C u 2C u C u C u 2C u V ref V ref C u C u 2C u C u C u 2C u V ref V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V ref V ref V ref V ref V ref Figure 2
.12: SAR ADC set-and-down (monotonic) switching with the energy associated to each transition. As it can be observed, the energy for each transition is smaller and also better distributed in comparison to the conventional algorithm.

SAR ADC switching schemes

Let us do a quick comparison by evaluating the ratio E set-and-down /E conventional :

E set-and-down E conventional = 2 N-2 -1/2 2 -N+1 +2 N+2 3 -2 ≈ 3 2 N-2 2 N+2 = 3/16,
which means that it is reduced to 18.75% of the conventional switching energy (almost) independently of the number of bits of the ADC. The simplification performed above will be verified later in this chapter.

Merged capacitor switching

The merged capacitor switching (MCS) has been known already for pipeline ADCs in [START_REF] Yoo | A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching[END_REF] and has been adapted to SAR ADCs for the first time in [START_REF] Hariprasath | Merged capacitor switching based SAR ADC with highest switching energy-efficiency[END_REF]. Its operation together with the energy consumption of each transition is shown in Figure 2.14. As it can be observed, the inputs are sampled in the top-plates of the array while the bottom-plates are initialized at V cm . That means that like the set-and-down switching, this topology also resolves the MSB without the need for switching any capacitor, reducing the capacitor array size from 2 N to 2 N-1 capacitors. Depending on the output of the comparator on the sampling phase, the capacitor 2C u of the array is either connected to V re f or ground, while the negative CDAC will do the opposite. This operation is then repeated for all the remaining bits of the converter. Further, like it was already anticipated by equation 2.21, since now the bottom-plate voltages move from V cm to ground or V re f instead of all the way from ground to V re f , that yields a fourfold reduction on the energy consumption in each cycle. That translates to even higher energy efficiency when compared to the set-and-down switching. Further, as can be observed in Figure 2.15, the common-mode voltage in the input of the comparator is kept constant throughout the complete conversion, which avoids the problems described in algorithms where the common-mode voltage is not constant, improving linearity. The average energy can be calculated using

E MCS = N-1 ∑ i=1 2 N-2-2i (2 i -1)C u V 2 re f = 2 -N + 2 N-1 3 - 1 2 . ( 2.24)
Performing an energy analysis similar to the one done for the set-and-down, the energy ratio can be evaluated:

E MCS E conventional = 2 -N + 2 N-1 -1/2 2 -N+1 + 2 N+2 -1/2 ≈ 2 N-1 2 N+2 = 1 8 ,
i.e. the MCS algorithm dispenses a fraction of 12.5% of the energy consumption of the conventional switching independently of the SAR ADC resolution.

V cm -based switching

To the best of the author's knowledge, the MCS algorithm for SAR ADCs [START_REF] Hariprasath | Merged capacitor switching based SAR ADC with highest switching energy-efficiency[END_REF] and the V cm -based switching [START_REF] Zhu | A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[END_REF] were independently published almost simultaneously. The operation of the V cmbased switching is illustrated in Figure 2.16. The inputs are sampled in the bottom plate of the capacitors, while the top plates are connected to V cm . The remaining operation is the same as the MCS algorithm, as well as the energy consumption per transition. At first glance, they might look the same, but bottom-plate sampling has better performance in comparison to top-plate sampling. First, comparing Figures 2.15 and 2.17, it can be seen that in the MCS algorithm the starting and ending point are different, while they are the same for the V cm -based switching. That difference in the MCS switching increases the sensitivity to the parasitics of the CDAC and comparator, mostly for the second, whose input capacitance will vary as the input voltage varies. Second, it Chapter 2. The Successive Approximation ADC The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f ,p = 900 mV and V re f ,p = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit on the figure for each decision step.

C u C u 2C u C u C u 2C u V in,p V in,n E ref =0 E ref =1/2C u V ref 2 E ref =1/2C u V ref 2 E ref =1/8C u V ref 2 E ref =5/8C u V ref 2 E ref =5/8C u V ref 2 E ref =1/8C u V ref 2 V cm C u C u 2C u C u C u 2C u C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm

SAR ADC switching schemes

has been demonstrated that bottom-plate sampling allows one to eliminate the voltage-dependent charge injection [START_REF] Razavi | Principles of data conversion system design[END_REF]. Charge injection2 will always be present when a switch is opened, but once it is independent of the input voltage, the differential implementation will highly mitigate this issue. With that in mind, it can be expected that the V cm -based switching will be more robust and that it will present better performance when compared to the MCS algorithm. In short, the V cmbased switching algorithm has the advantage of using bottom-sampling and still yields a twofold reduction in surface and a switching energy consumption 87.5% smaller than the conventional algorithm.

C u C u 2C u C u C u 2C u V in,p V in,n E ref =0 E ref =1/2C u V ref 2 E ref =1/2C u V ref 2 E ref =1/8C u V ref 2 E ref =5/8C u V ref 2 E ref =5/8C u V ref 2 E ref =1/8C u V ref 2 V cm C u C u 2C u C u C u 2C u C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref C u C u 2C u C u C u 2C u V ref V ref V ref V ref V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V cm V in,p V in,p V in,n V in,n

Summary and comparison between switching schemes

Figure 2.18a illustrates the energy consumption of each of the presented algorithms as a function of the number of bits of the SAR ADC. As it can be observed, the MCS and the V cm -based switching are the most efficient schemes. Figure 2.18b plots the energy savings as a function of the number of bits, and it confirms the assumptions made before, that for practical values of SAR ADC resolution, the relative energy savings in relation to the conventional switching is almost independent of the ADC resolution. Table 2.1 summarizes each of the considered algorithms with some of the main metrics discussed previously. Again, a varying common-mode translates to modulation of the comparator offset voltage, causing nonlinearities on the dynamic performance of the ADC. All the considered topologies present an area reduction of 50% in comparison to the conventional switching. Regarding sampling, note that the V cm -based technique is the only alternative switching technique presented here that performs bottom-plate sampling, which eliminates inputdependent charge injection and increases linearity, paying a price of a slightly slower conversion rate, since the first bit can not be determined directly like it is the case for the set-and-down and MCS switching schemes.

Conclusion

Conclusion

This chapter presented basic concepts related to the SAR ADC architecture. Starting from its block diagram, the charge redistribution SAR ADC using a capacitive DAC was presented, setting the theoretical basis for the development of the techniques which will be presented in the following chapters. Taking into consideration the growing needs of the industry for reduced area and low power converter designs, the split-capacitor DAC SAR ADC was also presented, one of the most promising and ubiquitous architectures addressing these design constraints. To further undertake these design challenges, different alternative capacitor switching algorithms available in recent literature were presented, and a performance comparison was provided taking into consideration power consumption, total area, sensitivity to comparator offset, and type of sampling. The presented techniques were the conventional switching, set-and-down switching, merged capacitor switching and V cm -based switching, and it was shown that the two latter have a large potential for considerable reductions in power consumption. Further, the V cm -based strategy has the extra advantage of performing bottom-plate sampling, which improves the overall linearity of the converter by eliminating voltage-dependent parasitic capacitance and voltage-dependent charge injection. A thorough understanding of the SAR ADC operation is a strong requirement for the development of efficient reduced test techniques, and this chapter introduced the theoretical concepts necessary for the comprehension of the techniques developed later in this manuscript.

3

Reduced-code SAR ADC static linearity test

This chapter presents a novel strategy for the reduced-code static linearity test of SAR ADCs. First, the classical techniques for static linearity test that have been used for decades in the industry are presented, namely the servo-loop and the histogram techniques. Then, the main drawbacks of these all-codes test approaches are addressed-more importantly, the large time and test cost related to them-, and the so-called reduced-code (or selected-code) test techniques are introduced as an alternative to reduce these limitations. The strategies presented here are based on major carrier transition and segmented-based techniques. In the former, some particular transitions are explored to provide a mapping between the measured codes and the estimated ones, highly reducing the number of codes that need to be measured and consequently the overall test time of the converter. In the latter, it is the segmented nature of the converter that is exploited in order to reduce the total global test time. Finally, in the last part of the chapter, these general techniques are adapted and applied to different SAR ADC topologies, namely the CDAC SAR ADC, the SCDAC SAR ADC, the V cm -based switching SAR ADC, and the hybrid resistive-capacitive SAR ADC.

Standard test methods for static linearity test

Standard test methods for static linearity test

In chapter 2 the properties that define the static nonlinearity of a SAR ADC were described. Since gain and offset are relatively easy to measure, the focus here will be on the techniques for characterizing the DNL and INL of the ADC. This section introduces the two main standardized testing techniques used in industry, namely the servo-loop-based and the histogram-based linearity tests. The former is a closed-loop technique, while the latter is an open-loop one.

Servo Loop Method

The principle of the servo-loop-method [START_REF]IEEE Standard for Terminology and Test Methods of Digital-to-Analog Converter Devices[END_REF] in its digital and analog implementations is illustrated in Figures 3.1a and 3.1b. As is can be observed, it is a closed-loop technique. The goal is to track a given transition V tl (i) by comparing the ADC output with a reference code c re f (i) that represents the code transition V tl (i) that is to be determined.

After defining the target code transition V tl (i)-supposing the ADC output is below the targeted reference code c re f (i)-the ADC input is increased until its output is equal to or larger than c re f (i). Once this point is achieved, the input of the ADC is now lowered until the target transition is crossed again. Note that this operation generates an oscillation around the transition, and the measurement of the transition voltage is now a triangular wave that can be filtered to yield the actual value of the transition voltage.

For the digital implementation, the idea is summarized in the block diagram of Figure 3.1a. There, the input stimulus for the ADC is generated by a high precision DAC whose inputs are produced by a digital control. According to the comparison result between the ADC output code and c re f (i), the DAC input is incremented or decreased by one LSB of the DAC. As a consequence, the test accuracy can be boosted by increasing the resolution of the DAC. The lower bound is determined by noise issues, that have to be taken into account. The transition level can be determined if one knows the transfer function of the DAC, or a high-precision voltmeter can be also used.

The block diagram of the analog implementation is shown in Figure 3.1b. Here, a currentdriven integrator is used for generating a highly linear continuous ramp stimulus. Working in a similar fashion to the digital scenario, while the output of the ADC is smaller than c re f (i), the current I 1 is injected into the feedback capacitor, causing the output of the integrator to be a positive slope ramp. On the other hand, once the output of the ADC is larger than the reference, the current source I 2 pumps out current from the integrating capacitor, yielding a ramp with a negative slope.

Despite the simplicity of the servo-loop principle, both analog and digital implementations demand a stimulus with a resolution considerably larger than the ADC under test, which can be a huge constraint, above all for high-resolution ADCs. Additionally, averaging is also necessary for reducing noise influence on the measurements.

Histogram Method

For the histogram-based test technique, the ADC under test is excited by a very linear, slow (quasistatic) stimulus at its input. Different waveforms can be used as long as their distribution over the ADC input range is known, the most widely applied being the linear ramp [START_REF]IEEE Standard for Digitizing Waveform Recorders[END_REF] and the sinusoidal [START_REF] Blair | Histogram measurement of ADC nonlinearities using sine waves[END_REF] stimuli. The histograms of both linear and sinusoidal stimuli are shown in Figure 3.2. The latter is simpler to implement than the former, but it demands a higher number of hits-per-code for the same test accuracy, i.e. larger test times are needed.

A slow input in comparison to the sampling rate of the ADC under test is applied in a way that a large number of hits in each code of the converter can be obtained. It is assumed that a linear ramp is used for it is simpler to illustrate the concept in comparison to a sinusoidal stimulus. It is quite intuitive that the histogram of the outputs of an ideal ADC fed by a linear ramp would be flat, considering each code would be hit the same number of times. This is not true for the codes 0 and 2 N -1-as it can be observed in Figure 3.2a-due to the overdrive at the ADC input. However, that does not pose a problem since as it was mentioned before, the DNL is only defined from 1 to 2 N -2. Hence, for a practical ADC, the wider codes are going to be hit more times while the narrower codes are going to be hit fewer times. As long as a sufficient number of hits-percode is employed, the static characteristic of the ADC can be obtained by comparing the actual output distribution histogram with the known ideal distribution. It is also important to mention that nonlinearities in the stimulus will of course translate to static test errors. A common rule of thumb applied in test environments is to employ a stimulus with two to three bits of resolution higher than the ADC under test in order to assure an accurate characterization. Finally, note that the number of hits-per-code translates to noise averaging, implying that a trade-off between test reliability and time exists. Given H i the number-of-hits associated with code c(i), and knowing that the ideal number of hits-per-code of a ramp stimulus H re f can be easily obtained by the following equation

H re f = n T FS 2 N (3.1)
where n T is the total number of gathered samples on the ADC full-scale FS, the width W i of code c(i) can be then calculated as

W i = H i H re f , for i = 1, ..., 2 N -2, (3.2)
and thus the DNL can be easily determined by using

DNL i = W i -1 LSB. (3.3)
This is an alternative representation of equation 2.13. Then, the INL can finally be computed by using equation 2.14.

Advanced linearity test techniques

The standard methods for the static test can be a very demanding and costly task. Indeed, the mixed-signal sections of a complex System-on-Chip (SoC) are amongst the more critical in terms of test time [START_REF] Poehl | production test challenges for highly integrated mobile phone socs -a case study[END_REF], and to complicate things even more, relative test cost is increased with Chapter 3. Reduced-code SAR ADC static linearity test further technology scaling. Focusing specifically on ADC/DAC testing, the paramount issues are the need for an accurate and linear test stimulus and the huge volume of samples that have to be collected in order to perform an accurate measurement. This is the case for both the servo-loop and the histogram methodologies, where the number of samples scales exponentially with the converter resolution. In addition, the servo-loop uses a closed-loop strategy that requires a number of oscillations around the transition level to filter out noise. The histogram method has also to measure each code a few times to average noise. This further increases the total test time. Clearly, the development of techniques to reduce the overall test time is a critical task.

As opposed to the above techniques that can be referred to as all-code testing approaches, in recent years, the development of the so-called reduced-code (or selected-code) test techniques has been drawing attention due to the potential to yield large reductions in test time. They rely on the repetitive operation of some ADC topologies, where errors across the ADC transfer function are caused by a reduced set of components. This allows inferring the complete transfer function of the ADC by measuring only a carefully selected subset of the total set of codes, greatly reducing the global test time. Moreover, the inherent simplification of static linearity tests provided by reducedcode test techniques may open the door to a full Built-In Self-Test (BIST) implementation. This way, tester requirements can be relaxed and test cost may be further contained by moving static linearity test resources to the device under test itself. If these techniques are successfully applied and the use of expensive automatic test equipment can be avoided, test costs can be vastly reduced. Another feature to take into account is the fact that in a densely integrated SoC, the input/output pins may not be available externally. As a consequence, the measurement of the target circuit becomes impracticable, unless some BIST option is integrated with the circuit that needs to be characterized. In the following, an overview of the state-of-the-art for these techniques is provided.

State-of-the-art on BIST and DfT for static test of ADCs

A wide variety of alternative test techniques have been proposed to facilitate the static linearity test of ADCs [START_REF] Renaud | Fully differential 4-V output range 14.5-ENOB stepwise ramp stimulus generator for on-chip static linearity test of ADCs[END_REF][START_REF] Barragan | A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio Σ∆ ADC[END_REF][START_REF] Laraba | Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique[END_REF][START_REF] Azaïs | A low-cost adaptive ramp generator for analog BIST applications[END_REF][START_REF] Pavlidis | SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety[END_REF][START_REF] Arteaga | Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus[END_REF][START_REF] Chen | USER-SMILE: Ultrafast stimulus error removal and segmented model identification of linearity errors for ADC built-in self-test[END_REF][START_REF] Duan | Low-cost dithering generator for accurate ADC linearity test[END_REF][START_REF] Xing | High-resolution ADC linearity testing using a fully digital-compatible BIST strategy[END_REF][START_REF] Chen | A low-cost on-chip built-in self-test solution for ADC linearity test[END_REF][START_REF] Arabi | Efficient and accurate testing of analog-to-digital converters using oscillation-test method[END_REF][START_REF] Vries | Built-in self-test methodology for A/D converters[END_REF][START_REF] Lee | A high precision ramp generator for low cost ADC test[END_REF][START_REF] Balestrieri | DAC Standardization and Advanced Testing Methods[END_REF][START_REF]Test time reduction of successive approximation register A/D converter by selective code measurement[END_REF][START_REF] Peralias | INL systematic reduced-test technique for Pipeline ADCs[END_REF][START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF]. Thus, in [START_REF] Arabi | Efficient and accurate testing of analog-to-digital converters using oscillation-test method[END_REF], the oscillation-based BIST technique is introduced. It resembles the servo-loop technique, but in this scheme, an integrated system is forced to oscillate between two established codes. The oscillation frequency depends on the transition voltages and conversion time of the two codes. Since the oscillation frequency is correlated to the code length, the static nonlinearity can be determined. In [START_REF] Vries | Built-in self-test methodology for A/D converters[END_REF], the authors take advantage of the fact that the LSB of an ADC always transitions between two successive codes to extract the static performance of the ADC. This can be accomplished if the nonlinearity errors are not very large. Once the LSB transitions, a counter driven by a clock starts to increment. Since the number of output counts is a function of the transition width, this can be exploited to determine the DNL and consequently the INL of the converter. The accuracy of this technique is very susceptible to noise and clock jitter. Additionally, a very linear input signal is needed to attain correct results.

[28] proposes a fully digital compatible BIST strategy, also based on the servo-loop test, where a deterministic dynamic element matching technique is used to control the reconfiguration and improve the linearity and accuracy of the stimulus. Also, test performance presents low sensitivity to process and mismatch variations. Thanks to these features, the INL of 12-bit ADCs could be characterized within an accuracy of ±0.15 LSB by using 7-bit DACs. On the other side of classic test implemented on-chip, BIST histogram has been investigated in several works, for instance in [START_REF] Azaïs | A low-cost adaptive ramp generator for analog BIST applications[END_REF][START_REF] Lee | A high precision ramp generator for low cost ADC test[END_REF]. The general idea consists of generating a ramp by charging a capacitor with a constant current source. The linearity of such circuits is limited by the output impedance of the current source, which poses an even bigger challenge in deep sub-micron technologies, where the intrinsic gain of transistors is highly limited. More particularly in [START_REF] Renaud | Fully differential 4-V output range 14.5-ENOB stepwise ramp stimulus generator for on-chip static linearity test of ADCs[END_REF], the ramp is generated by using an OTA-based switched-capacitor integrator whose step is very small. Note that these integrated ramp generator designs do not deal with the large test time issue.

The development of techniques with the goal of reducing the test time of ADC/DAC has also 3.2. Advanced linearity test techniques been explored in the literature. In [START_REF] Chen | Ultrafast stimulus error removal algorithm for ADC linearity test[END_REF] an algorithm is proposed to reduce both test time and source linearity constraints. However, a high error value on the integral nonlinearity (INL) measurement was demonstrated to occur when the quantization noise was dominant in relation to the test noise level. Hence, in [START_REF] Duan | Low-cost dithering generator for accurate ADC linearity test[END_REF] a dithering generator circuit has to be included in order to improve the measurement accuracy. The latest version of this technique, named the USER-SMILE algorithm, can be found in [START_REF] Chen | A low-cost on-chip built-in self-test solution for ADC linearity test[END_REF]. In these publications, the only consideration regarding the architecture of the ADC under test is that it should present an INL curve somewhat periodic that can therefore be segmented. If this constraint is met, no other requirements are necessary for the ADC under test and it can be measured as a black-box. In general, the techniques where the converter is viewed as a black-box belong to the group of model-based methods. A good review focused on model-based approaches can be found in [START_REF] Balestrieri | DAC Standardization and Advanced Testing Methods[END_REF].

Another category of rapid testing, commonly classified as reduced-code test methods, is based on taking advantage of the operation of a particular ADC architecture (e.g. SAR, pipelined, cyclic, algorithmic, etc.), where the static errors are correlated and caused by the same set of components. In [START_REF]Test time reduction of successive approximation register A/D converter by selective code measurement[END_REF], the full nonlinearity is estimated by measuring a subset of the total set of code widths of a SAR ADC using a piecewise linear ramp. Even though the method is effective, this kind of excitation may be impractical to be generated in the context of a BIST application. Also, if the ADC transfer curve has missing codes, the algorithm does not have the capability of handling them. This type of approach is applied for pipelined ADCs in [START_REF] Laraba | Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique[END_REF] and [START_REF] Peralias | INL systematic reduced-test technique for Pipeline ADCs[END_REF]. In the former, each output transition of the converter is carefully mapped to the correct comparators. Also, a noise cancellation scheme is adopted in order to increase the reliability of the measurements. In the latter, simple DC stimuli are applied to the ADC input, and the full INL curve is reconstructed by measuring a number of test points that is at least one order of magnitude smaller than the total number of ADC levels.

Huang et al. [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF] propose a bit-weight extraction strategy for measurement and calibration of SAR ADC. It takes advantage of the major-carrier transition (MCT) approach, which is strongly consolidated in the test literature [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF]. The MCTs are generated through a modified operation of the SAR ADC. After they are generated, a successive approximation search is performed through the use of an auxiliary low-resolution switched-capacitor DAC (sub-CDAC). A similar approach has been demonstrated in [START_REF] Lee | A self-calibrating 15 bit CMOS A/D converter[END_REF], but using a resistive sub-DAC and a resistor string calibration DAC. In [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF], since the MCTs have an order of magnitude close to one LSB of the SAR ADC, a coarse sub-CDAC whose full-scale (FS) is comparable to the LSB of the SAR ADC under test is enough to correctly characterize the ADC. The sub-CDAC is coupled to the dummy capacitor of the main switched-capacitor DAC (CDAC), whose value is twice the capacitance of the unit capacitor in order to provide the necessary full-scale adjustment.

Even though the approach of [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF] works well for calibration of the SAR ADC, it has some disadvantages for test applications. First, the fact that the dummy capacitor value is higher than the unit capacitor unbalances the equilibrium of the CDAC. Since they operate in a sub-radix regime for later calibration, this is not a problem in that context. However, because in this work the idea is to disturb the SAR ADC's usual operation the least possible, this technique would not be suitable. Secondly, this kind of approach is very susceptible to mismatches of the sub-DAC itself. The fact that a coarse DAC is used allows the test DAC capacitors to be larger and less prone to mismatches, but still, random variations on capacitors might compromise the test reliability.

For SCDAC SAR ADCs, the focus in the existing literature has been more on the calibration of the capacitive mismatches than on characterizing the static nonlinearity of the converter. In works such as [START_REF] Chen | Split capacitor DAC mismatch calibration in successive approximation ADC[END_REF][START_REF] Yoshioka | A 10-b 50-MS/s 820-µW SAR ADC With On-Chip Digital Calibration[END_REF][START_REF] Huynh | Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS[END_REF], a tunable capacitor is added in parallel with the LSB array to compensate for the mismatches, but no static linearity information is explicitly extracted. In [START_REF] Um | A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits[END_REF], a differential SC-SAR ADC is tested in such a way that one branch is responsible for the measurement of the adjacent branch. There, only the MSB capacitors are characterized. The main advantage of this approach is that no extra analog circuitry is needed to perform the measurements. Similarly, in [START_REF] Lin | A mutual characterization based SAR ADC selftesting technique[END_REF] one sub-array is responsible for the bit weight extraction of the other. The main disadvantage of Chapter 3. Reduced-code SAR ADC static linearity test this kind of approach is that since they require several iterative operations to converge, they are slower than algorithms such as [START_REF]Test time reduction of successive approximation register A/D converter by selective code measurement[END_REF][START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF].

MCT-based reduced-code static test techniques

As explained in the previous section, some works explore the so-called MCTs of the DAC in order to obtain the full transfer of a SAR ADC. Since that is the main technique explored in this work, this section has the goal of giving it a deeper look. The concept of MCT in DACs is a well-known concept [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF]. The interest in the MCT comes from the fact that in binary-weighted DAC topologies, the mid-scale transition is usually the most critical one because it translates to all components of the converter switching at the same time. The mismatch between these components is very likely to cause the worst-case DNL. That justifies for instance the use of thermometer code or hybrid thermometer/binary-weighted converter topologies.

Several DAC architectures use binary-weighted capacitors, resistors, current sources, etc, to obtain the analog output voltages or currents. These voltages/currents are superimposed to obtain the target value at the output. Since this technique is applied in the context of capacitive SAR ADCs, let us assume without loss of generality that an N-bit CDAC is being analyzed. For this specific case, the weights W N-1 ...W 0 are determined by the capacitive ratios, and the bits D N-1 ...D 0 represent the CDAC binary input. Assuming superposition, the following model can be used for describing the output voltage of the CDAC:

V tl [D N-1 ...D 0 ] = D 0 W 0 + D 1 W 1 + ... + D N-2 W N-2 + D N-1 W N-1 . (3.4)
Notice that the output of the DAC is directly labeled V tl since it represents the transition-level voltages of the SAR ADC. If this model is accurate, it would be possible to measure the whole characteristic of the CDAC by performing only N measurements. The most straightforward way of doing that is by choosing D i = 1, setting all the remaining bits equal to 0, and computing W i for i = 0, ..., N -1. However, that makes the output range of voltages span from 0 to half the FS of the SAR ADC. Measuring these values with sufficient accuracy would demand an instrument with a resolution comparable to the SAR ADC under test. A smarter way of doing that is by measuring the difference between the transition level voltages of the codes 2 i and 2 i -1, which is the textbook definition of the MCT of code i [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF]. This idea is illustrated in Figure 3.3 for the transfer curve of an example 4-bit SAR ADC whose MSB-1 capacitor was artificially increased by 50% of its ideal value. Notice how by comparing the ideal and real curves, the mismatch indeed causes the transition level voltages V tl to move away from its ideal value, changing the code width and causing the DNL to be nonzero. In this scenario, each measured voltage

V i = V tl [2 i ] -V tl [2 i -1]
corresponds to a step size which is ideally around 1 LSB, which highly alleviates the constraints on the dynamic range of the measurement device. In conclusion, after all the respective transitions are mapped, it is possible to measure only the code widths of the N MCT voltages and extrapolate it to the full transfer curve of the DAC. This is done taking into account that the MCT voltages being measured correspond to the following values:

V 0 = V tl [1] -V tl [0] = W 0 , V 1 = V tl [2] -V tl [1] = W 1 -W 0 , V 2 = V tl [4] -V tl [3] = W 2 -(W 1 -W 0 ), V 3 = V tl [8] -V tl [7] = W 3 -(W 2 -W 1 -W 0 ), . . . V N-1 = V tl [2 N-1 ] -V tl [2 N-1 -1] = W N-1 - N-2 ∑ k=0 W k . (3.5)
This means that a recursive calculation can be used for obtaining the estimation of the weights W i . For instance, it is clear that V 0 gives a direct measure of W 0 . Then W 1 can be calculated by

V tl,1 V tl,2 V tl,3 V tl,4 V tl,5 V tl,6 V tl,7 V tl,8 V tl,9 V tl,10 V tl,11 V tl,12 V tl,13 V tl,14 V tl,15 V tl,0 V 0 V 1 V 2 V 3 V 2 Figure 3
.3: Transfer function for an example 4-bit SAR ADC. These plots are for an ideal ADC and for an ADC whose MSB-1 capacitor is 50% larger than its ideal value.

performing W 1 = V 0 +W 0 , and so forth. Once all values of W i are obtained, the complete transfer function can be reconstructed by sweeping equation 3.4 [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF]. Notice hence how this equation can be rewritten as

V tl [D N-1 ...D 0 ] = D 0 V 0 + D 1 (V 1 +V 0 ) + ... + D N-1 N-1 ∑ k=0 V k . (3.6)
To help better illustrate the idea behind the reduced-code test through MCTs, consider the example of a simple 4-bit CDAC. For this case, let us consider for example the second MCT code width (i = 2). In that case, according to equation (3.4)

, V tl [2 2 ] = V tl [0100] = W 2 and V tl [2 2 -1] = V tl [0011] = W 1 +W 0 , which means that V 2 = V tl [0100] -V tl [0011] = W 2 -W 1 -W 0 . Now, consid- ering V tl [1100] = W 3 + W 2 and V tl [1011] = W 3 + W 1 + W 0 , the difference V tl [1100] -V tl [1011] = W 2 -W 1 -W 0 is also equal to V 2 ,
since the effect of W 3 is canceled. That means that both lengths of codes 0011 and 1011 are the same, and hence only one needs to be measured. This can also be seen in Figure 3.3 for a SAR ADC whose MSB-1 capacitor in its CDAC was artificially increased by 50% of its ideal value, showing that indeed the code lengths of codes 3 and 11 are the same and equal to V 2 . The same logic can be applied to the remaining MCT voltages.

On a final note on the MCT technique, it is important to point out that it assumes the mismatch between capacitors as the main responsible for the CDAC nonlinearities. Of course, second-order effects may reduce the effectiveness of the technique. For instance, parasitic capacitances that have a voltage dependency might play a role to reduce the accuracy of the test, and they need to be carefully investigated.

Segmented-based reduced-code static test techniques

A segmented DAC is composed of two or more low-resolution DAC stages, whose LSB is scaled in a way that the outputs can be combined to form a higher resolution DAC. For instance, let us consider an M-bit "coarse" DAC and an L-bit "fine" DAC like it is shown in the conceptual block diagram in Figure 3 If the fine and coarse DACs are binary-weighted, the previous MCT-based technique could be directly applied to the individual converters. However, segmented architectures usually rely on thermometer-code rather than a binary-weighted structure. For this reason, MCT-based approaches are not suitable for characterizing these converters. Instead, the idea is to measure all codes of each partial DAC and then use superposition to infer the full characteristic of the composite DAC. In a general case where an L-resolution fine DAC and an M-resolution coarse DAC are used, a full all-code linearity test would take at least 2 L+M measurements. However, by performing two partial all-code tests, the total number of measurements is reduced to 2 M + 2 L , highly reducing the total test time. After the sub-DAC voltages are measured, the actual output can be reconstructed by adding the coarse and fine contributions [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF] V DAC (i) = V FINE DAC (i & 0...001...11)

+V COARSE DAC i & 1...110...00 2 L , (3.7)
where V FINE DAC is the LSB DAC contribution, V COARSE DAC is the MSB DAC contribution and & is the AND bit-wise operator.

Reduced-code test techniques for SAR ADCs

Conventional SAR ADCs

As it was already mentioned, the fact that the SAR ADC uses only one comparator opens the way for measuring the CDAC alone and extending its nonlinearity for the complete SAR ADC. The MCT-based test methodology can be directly applied to the CDAC SAR ADC in Figure 2.3, just by monitoring the output of the binary-weighted DAC, labeled V X in the figure, and programming the CDAC for generating the code widths associated with the MCTs. As detailed in [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF][START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF], the voltage corresponding to the i-th transition is generated by performing a modified SAR operation, which will soon be analyzed. Before that, let us define some important features related to the SAR ADC that will be useful for understanding the proposed measurement strategy. First, it can be 3.3. Reduced-code test techniques for SAR ADCs shown that the transition level associated with the code D N-1 ...D 0 is given by

V tl (D N-1 ...D 0 ) = ∑ N-1 i=0 D i C i C tot V re f , (3.8)
and as it was already defined, the voltage associated with the i-th MCT is the same as the width of the 2 i -1 step, i.e. the transition level voltage difference between the codes 2 i and 2 i -1:

V cw (2 i -1) = V tl (2 i ) -V tl (2 i -1) = C i -∑ i-1 j=0 C j C tot V re f , for i = 0, ..., N -1. (3.9)
Since the i-th capacitive weight of the binary-weighted DAC is given by C i /C tot , it is important to notice that this equation is equation 3.5 translated to the particular CDAC under analysis. Thus, as it was previously explained, by measuring these N values it would be possible to infer the whole characteristic of the converter.

To help us further understand how the mapping is done, let us consider the 4-bit example in Table 3.1. It illustrates each of the CDAC transitions where the same bits are being changed. The MSB transition, i.e. T 3 in Table 3.1, represents the transition where the bits from LSB to MSB-1 are flipped from high to low, and the MSB flips to high. This transition is generally where the worst-case DNL is found in a binary-weighted DAC. The MSB-1 transition is T 2 and it happens when the bits from LSB to MSB-2 flip from high to low and MSB-1 flips from low to high, independent of the MSB. Hence, there are two transitions where that happens. Following this reasoning, one can observe that T 1 has four transitions, and T 0 eight transitions. Generalizing, it can be seen that the i-th MCT shares the same length with other 2 N-i-1 transitions. That is, by measuring N voltages associated with the code length of the MCTs of the DAC, the previous discussion can be generalized and used to deduce the following relation [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF]:

V cw [(2 i -1) + ( j -1)2 i+1 ] = V cw (2 i -1), (3.10)
for j = 1, ..., 2 N-i-1 . This equation can be used for mapping the N measured code lengths to the full transfer characteristic of the CDAC. • Each MCT voltage V i is generated at node V X by using a modified SAR operation.

• V i is switched to the input of the test device through S X in order to obtain a quantized version of the i-th MCT code length.

• Each of the N measured step sizes is mapped to its respective codes and the full DNL is estimated.

• The INL is calculated from the DNL and further calibrated for the elimination of accumulated quantization errors.

This test procedure is also illustrated in the flowchart in Figure 3.6. It begins with the generation of the MCTs of the SAR ADC that has been adapted from [START_REF] Huang | Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction[END_REF]. To generate the MCT associated with the code transition i, first, the switch that connects node X (top plates) to the ground is closed (see Figure 3.7a), capacitor C i is charged to V re f and the bottom of all other capacitors are connected to ground. To help formulate this idea, Figure 3.7 illustrates the process for a 4-bit SAR ADC example. There, the process is for generating the MCT voltage associated with the capacitor C 2 = 4C u . Hence, as it can be seen in Figure 3.7a, C 2 is connected to V re f while all other capacitors are connected to the ground. The total charge at time t 0 is then given by

Q t 0 = -C 2 V re f = -4C u V re f .
After this step, the initial charge is distributed between the remaining capacitors of the array by opening the top plate switch (node X) and connecting the bottom of C i to the ground. Even though this phase is called redistribution, to salvage one clock cycle, the next capacitor (i -1) is connected to V re f . For the example under consideration that is C 1 = 2C u as shown in Figure 3.7b. Mathematically, the charge at t 1 can be written as

Q t 1 = V X (C tot -C 1 ) + (V X -V re f )C 1 ,
and using charge conservation, Q t 0 = Q t 1 , which means that the voltage V X can be written as

V X = - C 2 C tot V re f + C 1 C tot V re f .
Now, a comparison is performed. As it will be shown in the following paragraphs, V X needs to be negative to guarantee that no missing codes exist. Hence, if the output of the comparator (cmp) is equal to zero, capacitor C 1 keeps connected to V re f , as it is shown in Figure 3.7c. On the other hand, if V X > 0 and cmp = 1, C 1 is switched to ground, as it is shown in Figure 3.7d. Either way as it can be also seen in Figures 3.7c and 3.7d, the next LSB capacitor (C 0 = C u ) is connected to V re f . The comparison is performed for every step of the process to check if V X keeps below zero.

Assuming no missing codes were present, the final value of the CDAC voltage is given by

V X = - C 2 C tot V re f + C 1 C tot V re f + C 0 C tot V re f = -V re f C i -∑ 1 j=0 C j C tot .
which corresponds exactly to the length of the step 2 2 -1 = 3 step defined in equation 3.9. Generalizing to the measurement of the i-th capacitor, the final CDAC voltage corresponding to the step 2 i -1 can be written as

V X = -V re f C i -∑ i-1 j=0 C j C tot .
For an ideal CDAC array, the absolute value of V X is equal to 1 LSB, and when mismatches occur, they can be detected by measuring the voltage V X . However, let us consider the scenario where missing codes happen. Without loss of generality, let us assume that only C i is prone to random variations. As the code length is proportional to C i -∑ i-1 j=0 C j , variations in C i that lead to lower values make the code length smaller and hence result in a negative DNL. In the limit when C i = ∑ i-1 j=0 C j , the code length is zero and the DNL is equal to -1. In short, missing codes will happen for C i ≤ ∑ i-1 j=0 C j . Note that if it was not for potential missing codes, all the LSB capacitors to the i-th capacitor being measured (i.e. from i -1 to 0) could be simultaneously connected to the ground after the pre-charging phase. By connecting these capacitors to V re f equation 3.9 is obtained, but in the where case there are missing codes, they would not be detected and the whole test accuracy may be jeopardized.

The modified SAR operation is hence necessary for missing-code detection. After this process, it can be shown that the residual voltage is V X = -V i (refer to equation 3.5), and the binary output of the modified SAR operation corresponds to 2 i -Λ i -1, where Λ i represents the number of missing codes related with the capacitor C i . In summary, the voltage V X = -V i representing the code length of the i-th code is measured by the embedded device in figure 3.5, and the output of the modified SAR ADC operation is stored for the detection of missing codes in the post-processing

INL k = k ∑ j=1 (DNL j -δ ) = -(k -1)δ + k ∑ j=1 DNL j , (3.11)
where k ranges from 1 to 2 N -2. In fact, the INL curve has to be calibrated by estimating the value of δ . The calibrated INL curve can then be calculated by summing the average quantization error for each DNL value

INL cal k = k ∑ j=1 (DNL j + δ ), (3.12)
where it can be shown that considering the expected FS of the SAR ADC V ideal FS and calculating the estimated V estimated FS = ∑ N-1 j=0 W j , the average quantization error δ can be estimated by

δ = V ideal FS -V estimated FS 2 N -1 . (3.13)

Split-CDAC SAR ADCs

As it was previously explained, the SCDAC SAR ADC employs a bridge capacitor between MSB and LSB arrays in order to reduce the area and power consumption of the ADC (refer to Figure 2.4). However, these improvements do not come without a cost, and one drawback is that the parasitics added by the bridge capacitor limit the performance of the converter. Moreover Let us detail the complete test strategy for a generic M × L SC-SAR ADC whose simplified schematic is illustrated in Figure 3.9a. Like it was done for the conventional CDAC SAR ADC, an example is done for the measurement of the capacitor C 2 , and the process is shown in Figure 3.9b. Here, the capacitor C 2 is the MSB-1 capacitor of the 4-bit MSB partial CDAC. First, the M-bit MSB segment is characterized in the following way: initially, switches S X and S A in Figure 3.8 are opened, and the bottom of C 2 in Figure 3.9b is connected to V re f , while all the remaining capacitors are connected to the ground. Also, in this first phase all the top plates are connected to the ground through the upper switches (see in Figure 3.9b). As a consequence, all other capacitors have both plates grounded while the i-th capacitor is pre-charged to Q = -V re f C 2 . Then, in the next clock cycle, the top plates are disconnected from ground, the capacitor C 2 bottom plate is switched to the ground and all capacitors of the MSB array from i -1 to 0 are simultaneously connected to V re f , in this particular example capacitors C 1 and C 0 . By charge conservation, it can be shown that after performing this operation, in an ideal SC-SAR ADC voltage V X evolves to V X ≈ ∆ X , where ∆ X = V re f /2 M is the ideal step of the MSB segment of the DAC array. Voltage V X then is fed to the embedded acquisition instrument through S X and it is subsequently digitized and stored for post-processing. The process is repeated for each of the M capacitors in the MSB array. Observe that this operation is similar to the classical CDAC case, but it is performed for the partial CDAC.

The methodology is similar for the L-bit LSB segment of the DAC array. The bottom of the j-th capacitor in the LSB array is first connected to V re f and all remaining capacitors to the ground. In the following clock cycle, the j-th capacitor is switched to ground, and capacitors j -1 to 0 are connected to V re f . Again, by charge conservation, it can be shown that voltage V A in an ideal SC-SAR ADC is given by

V A ≈ ∆ A = V re f C u 2 L C u + C atten C tot,M C atten +C tot,M ≈ V re f 2 L + 1 . (3.14)
Once again, this voltage is fed to the embedded acquisition instrument via the S A switch and it is digitized and stored for further post-processing. The process is repeated for each of the L capacitors in the array. Before moving forward with the description of the algorithm, let us comment on the fact that here the LSB capacitors to the i-th capacitor being measured are connected at the same time, while this was not done for the conventional CDAC. Note that the condition for the occurrence of 3.3. Reduced-code test techniques for SAR ADCs missing codes is

C i - i-1 ∑ j=0 C j ≤ 0.
As the resolution of the SAR ADC increases, the threshold mismatch that causes this condition to occur becomes smaller. For instance, considering a random mismatch σ occurring only for capacitor C i , for a 5-bit converter the critical variation to cause a missing code at the middle-scale is 6.5%. On the other hand, for a 12-bit ADC, the critical mismatch that causes a missing code at the middle-scale drops to the order of only 0.05%! This shows that since the partial DACs are being measured instead of the full N-bit CDAC like it was the case for the conventional SAR ADC, this highly alleviates the measurement constraints and it makes the occurrence of missing codes in the partial CDACs very unlikely. Of course, if a conservative measurement for high-resolution SCDAC SAR ADCs is intended, the modified SAR ADC operation can still be performed similarly to the technique implemented for the conventional CDAC SAR ADC, paying the price of a higher test time. Also, notice that that does not mean that missing codes will not occur in the full SCDAC SAR ADC transfer characteristic. It just means that the modified SAR ADC operation can be relaxed and, as it will be shown very shortly in this chapter, this opens the way for the detection of missing codes in the digital post-processing domain.

Once both segments of the DAC array have been characterized as described above, the obtained digitized measurements represent the width of the codes associated with the MCTs of the MSB and LSB segments of the SCDAC, which will be denoted as MSB i and LSB j , respectively, with i = 0, . . . , M -1 and j = 0, . . . , L -1. The partial weights of the MSB and LSB segments of the SCDAC can be easily computed from MSB i and LSB j as described in the previous section and in [START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF]. However, to estimate the static linearity of the complete SC-SAR ADC they should be appropriately combined.

First, after performing the inductive calculations (equation 3.

W = V re f 2 N Ŵ. (3.16)
Considering the previous definitions of MCT and its associated code width, it is important to observe that each element in W corresponds to a digital representation of W i in equation (3.5). That means that the actual binary weights of an N-bit ADC have been obtained by measuring the partial CDACs. Thus, one can now define a "digital" MCT code width Ṽi by using the same relationship used for the analog domain, applying it on the elements of W Ṽ0 = W 0 , (3.17)

Ṽi = W i - i-1 ∑ j=1 W j i = 1, . . . , N -1. (3.18)
Besides, it is important to notice that the ideal values of Ṽi are positive because they correspond to the code width of each MCT. If they happen to be negative, that means that there are missing codes, since a zero or negative step length should correspond to a code that does not exist. It can Chapter 3. Reduced-code SAR ADC static linearity test be shown that the number of missing codes corresponds to the number of times V LSB can be added to Ṽi before the voltage is larger than 0, where V LSB = V re f /2 N is the LSB step of the full SC-SAR ADC. A simple routine can be implemented in order to digitally estimate the number of missing codes associated with code i, Λ i . The pseudo-code that performs this task is described below.

Algorithm 1: Computation of the number of missing codes.

Algorithm 1: Digital detection of missing codes

for i = 0 to i = N -1 do Λ i = 0 if Ṽi ≥ 0 then Λ i = 0 else while Ṽi < 0 do Ṽi = Ṽi +V LSB Λ i = Λ i + 1 end while end if end for
After performing this estimation of the missing codes, the obtained code widths are mapped to the full 2 N codes of the SC-SAR ADC by following the guidelines related to equation 3.10 in order to obtain the code widths Wk , for k = 1, . . . , 2 N -2. Finally, the DNL and INL can be calculated by

DNL k = Wk -1, (3.19
)

INL k = k ∑ j=1 DNL j , (3.20)
for k = 1, . . . , 2 N -2. It is important to remark that like in the standard CDAC case, INL k may be severely affected by the accumulation of quantization errors in the estimation of DNL k . However, since the accumulation of this error is linear, it can be easily corrected using well-known best-fit techniques, like it was already shown for the classical CDAC case and in [START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF][START_REF] Mahoney | DSP-based testing of analog and mixed-signal circuits[END_REF] to subtract the error contribution.

Application to V cm -based switching SAR ADCs

In Section 2.4.2 the operation of the V cm -based switching SAR ADCs was explained. Due to the fact that it presents one of the best trade-offs in terms of efficiency and surface, without the drawback of top plate sampling like the merged capacitor switching, this switching technique is chosen as the target topology to extend even further the proposed reduced-code test technique.

The idea is to expand the SCDAC SAR algorithm taking into account the particularities of the V cm -based switching, proving that our technique is also feasible for novel structures with high potential for power and area efficient applications. So far the mathematical modeling was considerably simplified by analyzing single-ended designs. Since V cm -based switching is intrinsically (pseudo) differential, the following calculations will take the differential nature of the input DAC into account. The schematic of a M × L V cmbased switching SAR ADC is illustrated in Figure 3.10a. The complete resolution of the ADC is given by N = M + L. Like a conventional SAR ADC, it consists of a M × L bits SCDAC, where the resolutions of the MSB and LSB CDACs are M -1 (because the MSB CDAC does not need the MSB capacitor) and L, respectively, a comparator and the digital control logic. The negative CDAC is omitted in the figure, but its output is represented by V X,n on the negative input of the comparator. The digital logic is built with shift registers and switch drivers that control the CDAC to perform a binary search operation. In the first cycle, the input voltage is sampled on the bottom plate of every capacitor of the array, while the upper plate is connected to V cm . In the following cycle all bottom plates are connected to V cm , and it can be shown that the top plates are charged to V X p,n ≈ 2V cm -V in p,n . The first output bit can hence be defined without the need of the MSB capacitor, halving the size of the MSB CDAC and drastically reducing the switching energy consumption of the MSB bit calculation. Note that the first comparison is the most critical one in terms of energy for the conventional switching SAR ADC (because the energy to move the charges is proportional to C × ∆V 2 , where C is the capacitor value and ∆V is the voltage variation on the capacitor plates). Since no capacitor is unnecessarily charged and subsequently discharged after the comparison, the overall energy needed for moving the charges between capacitors is highly reduced. Additionally, since now the following capacitors are switched from V cm to V re f ,p or V re f ,n depending on the output of the comparator, instead of all the way from V re f ,n to V re f ,p , the power consumption for the following cycles is further reduced.

As it was shown in [START_REF] Zhu | Split-SAR ADCs: Improved Linearity With Power and Speed Optimization[END_REF], the first comparison does not depend on the capacitive array, which eliminates the need for the MSB capacitor and makes the INL ideally zero at the middle scale. Regarding the static characteristic of this structure, compared to the conventional SCDAC with M capacitors, this causes the DNL to be half the value of conventional switching, but distributed in two codes instead of one, as illustrated in the comparison between conventional switching and V cmbased switching in Figure 3.11 for the behavioral models of CDACs with mismatch only on the largest capacitor. It can be shown that this DNL splitting is repeated for the codes associated with each MCT. This fact is taken into account in post-processing for correctly mapping the complete transfer characteristic of the ADC under test. In short, an algorithm that is similar to the SCDAC test can be applied, and the particularities are considered in the post-processing step to obtain the correct results of the rapid static linearity test [START_REF] Feitoza | On-chip reduced-code static linearity test of V cm -based switching SAR ADCs using an incremental analog-to-digital converter[END_REF][START_REF] Feitoza | Static linearity BIST for V cm -based switching SAR ADCs using a reduced-code measurement technique[END_REF][START_REF] Portolan | A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System[END_REF].

Concerning the generation of voltages V A and V X , associated with the length of the MCT codes in the LSB and MSB sub-DAC arrays, respectively, a modified operation of the control switches of the DAC array is applied. The following description explains the procedure for the ith capacitor. Note that it is similar to the cases proposed previously, but some extra considerations are needed since it is a differential implementation. First, for generating the i-th voltage related to the i-th capacitor in the MSB sub-DAC, the i-th capacitor is connected to V re f ,p while all the Chapter 3. Reduced-code SAR ADC static linearity test LSB capacitors from 0 to i -1 are connected to V re f ,n , the remaining capacitors being connected to V cm , including the capacitors in the LSB sub-DAC. The negative path of the fully differential CDAC performs the inverse of this procedure. The operation is similar for the LSB sub-DAC. As an example, this process is illustrated in Fig. 3.10b for the specific case of i = 2. For an ideal DAC array with no mismatch, at the end of each operation for the MSB sub-array, the (M -1)-bit CDAC output voltage can be written as

V X ≈ 1 2 M-1 2(V re f ,p -V re f ,n ), (3.21)
similarly, for the LSB CDAC, the output voltage V A is given by

V A ≈ 2(V re f ,p -V re f ,n ) 2 L + 1 . (3.22)
This process is repeated for each one of the L capacitors in the array. As it can be seen, the obtained values for V X and V A are close to the code length for the MSB and LSB sub-DAC arrays, respectively. By measuring these voltages and taking into account the DNL splitting effect in V cmbased SCDAC SAR ADCs, it is possible to reconstruct the complete ADC static characteristic. To provide a practical example of a segmented topology such as the one explored in Figure 3.4, Figure 3.12 shows a conceptual block diagram of a hybrid resistive-capacitive SAR ADC. In this 3.4. Conclusion topology, the binary search is performed using each of the resistive sub-DACs while the relative scaling of the fine and coarse DAC LSBs is achieved by a capacitive divider. This capacitive array is also responsible for sampling the input. This architecture is hence based on a segmented DAC. Defining V M as the output of the MSB resistive sub-DAC and V L the output of the LSB resistive sub-DAC, it can be seen that

Application to segmented DAC SAR ADCs

V X = V M , V A = αV L .
Where α is an attenuation factor produced by the ratio between capacitors. Then, the histogram test can be performed for each partial DAC. By monitoring the voltages V X and V A , one can postprocess the results and reconstruct the total 2 M+L codes by performing only 2 M +2 L measurements by using equation 3.7.

Conclusion

This chapter dealt with the static linearity test of ADCs. First, the two most consolidated techniques applied in the industry were presented, namely the servo-loop and the histogram-based techniques. The operation of each technique was explained, and also the advantages and drawbacks related to each one. The main bottleneck of these all-code test techniques for high-resolution ADCs in small technology nodes is the relative increase of test cost, which can pose significant challenges in the IC supply chain. In that scenario, an overview of the BIST and selected-code test literature were introduced. Regarding the reduced-code test strategies, two major types were presented, particularly the MCT-based and the segmented-based techniques. After presenting the operation of the techniques, the last part of this chapter focused on adapting these techniques to specific flavors of the SAR ADC. First, a technique for measuring the classical CDAC SAR ADC was demonstrated. There, a voltage that is proportional to the code width of a given transition being measured is directly generated through a modified SAR ADC operation. That enables not only the characterization of the ADC without the need for an input stimulus, whose design can be quite challenging, but also allows the detection of missing codes if there are any. Subsequently, the technique is extended to the SCDAC SAR ADC. The voltage related to the MCTs of each partial CDAC is generated in a similar fashion as it was done for the previous case, but a digital technique for the detection of the missing codes is proposed, further reducing the overall test time. Since each sub-DAC is measured separately, post-processing is needed in order to retrieve the true weights of the full SAR ADC. The SCDAC SAR ADC technique is even further developed to allow its application to V cm -based SAR ADC. This is convenient due to the fact that this topology allows an extensive reduction in energy switching (by a theoretical factor of 92 %, as demonstrated in the previous chapter). Furthermore, it also enables a reduced surface, given that the MSB capacitor is no longer needed. Extra features of this topology such as DNL splitting are considered, enabling the development of a new technique that takes into account these particularities and enables the retrieval of the static non-linearity. Finally, an example of a SAR ADC that used segmented DAC is given, and the segmented technique is directly applied. In this chapter, testing techniques were proposed and detailed without any regard for how to measure the internal voltages that carry information about the static nonlinearities of the converter. This is done in the next chapter, where a practical BIST implementation is proposed. There, the trade-offs and particularities of this solution are thoroughly analyzed for each of the proposed alternative test approaches.

Practical SAR ADC BIST Implementation

This chapter deals with the on-chip implementation of the proposed static linearity test technique. An embedded instrument for voltage measurement is proposed as a solution to carry out the measurements necessary for the implementation of the techniques discussed in Chapter 3. A practical implementation based on the use of a simple embedded ADC for the on-chip measurement of the MCT voltages is proposed. In this regard, the Incremental ADC is proposed as a promising candidate. First, the operation of the proposed architecture is introduced. Subsequently, the trade-offs associated with the implementation of each selected-code test technique are explained in the context of an embedded ADC BIST technique. Then, the cointegration of the DUT and the BIST circuitry is discussed, and a thorough explanation of its main features is provided. Finally, after obtaining the high-level specifications of the BIST circuitry, the circuit-level requirements are derived for the design of the blocks related to the embedded test instrument.

Practical on-chip implementation

Chapter 3 introduced the classic and alternative methodologies for characterizing the static nonlinearity of data converters. Amongst them, techniques that aim to reduce the total test time were presented and adapted to different SAR ADC topologies. For each one of the demonstrated approaches, a voltage that captures the information about a given code length was generated, but no information on how to measure it was provided. This chapter addresses the challenges of the voltage acquisition and digitization block and the trade-offs associated with this measurement.

The proposed reduced-code test strategy has the advantage of not requiring a test stimulus. This greatly simplifies the on-chip implementation of the technique and opens the door to an efficient BIST approach. All presented techniques can be conceptually represented as depicted in Figure 4.1. The key element for the on-chip implementation of the proposed technique is the embedded test instrument that acquires and digitizes the DAC voltages. The test circuitry can also be tested using the BIST control block to guarantee the accuracy of the test. The digital part consists of a SAR/Test control block and a digital analyzer. The SAR/Test control is responsible for managing the DAC in the SAR ADC in standard mode and for generating the desired voltages in test mode as explained in the last chapter. Further, the SAR/Test control is also responsible for launching the digital analysis block. The analysis block is then responsible for performing the post-processing of the static nonlinearity as explained in the last chapter. Then, based on the test results, a Go-NoGo flag is produced signaling if the circuit has passed or not the minimum static linearity specifications. In this work, the digital analyzer will be implemented off-chip.

In this chapter, it will be shown that a suitable candidate for performing the voltage acquisition and digitization task is the Incremental ADC, which, conceptually, is a mix between a dual-slope and a Σ∆ ADC [START_REF] Márkus | Theory and applications of incremental ∆Σ converters[END_REF]. This topology is suited for measuring DC voltages such as in digital voltmeters and instrumentation and measurement applications. On the other hand, oversampling Σ∆ ADCs are more prone to gain and offset errors, and it has been proved that the incremental ADC operation is inherently more robust to complex non-linear effects such as idle tone generation and dead zones [START_REF] Schreier | Understanding delta-sigma data converters[END_REF]. In the remainder of this chapter, the basic operation of the proposed BIST implementation is explained and the design trade-offs for sizing the proposed circuitry are explored. Moreover, it will be shown that the CDAC/SCDAC of the SAR ADCs under test can be merged with the input stage of an Incremental ADC by using the same operation principle of a multiplying DAC (MDAC) [START_REF] Song | A 10-b 15-MHz CMOS recycling two-step A/D converter[END_REF], which further reduces the overhead and simplifies the implementation.

N

Digital to Analog Converter

SAR/Test Control Digital Analyzer

From SAR/Test logic integrator and counter are reset at the beginning of each conversion1 . Thus, for a given resolution R, the integration of each input sample is performed for 2 R cycles. The output of the comparator is triggered every time the integrator output crosses 0, incrementing the counter and sending a logic 1 via the feedback path to be subtracted from the converter input. After 2 R cycles, the output of the integrator can be written as

V in

Voltage acquisition and digitization

Go-NoGo

The Incremental ADC

V int = b2 R V in -b 2 N out V re f ,
where N out represents the number of times V re f was fed back to the input of the integrator, i.e. how many times the comparator detects that the integrator output is above zero, and b and b 2 are the forward and feedback gains of the integrator, respectively. Rearranging this equation leads to

N out = b2 R V in b 2 V re f - V int b 2 V re f .
It is important to bear in mind that V int is between the interval -b 2 V re f to 0, which means that the second term of the equation above represents the quantization error of the Incremental ADC. Hence, the output of the counter N out can be written as [START_REF] Márkus | Theory and applications of incremental ∆Σ converters[END_REF]]

N out = 2 R bV in b 2 V re f + ε, (4.1)
where |ε| ≤ 1. Note that since the number of counts is acquired by a simple digital counter, this result is already a quantized representation of the input. By making N out equal to 2 R , it can be demonstrated that the full-scale (FS) of the Incremental ADC is given by Let us first consider the MCT approach, which is suitable, as advanced in the last chapter, for binary-weighted DAC topologies such as CDACs and SCDACs. For an N-bit DAC, one can define N MCTs, where the i-th MCT is defined as the transition from code 2 i -1 to code 2 i [START_REF] Burns | An introduction to mixed-signal IC test and measurement[END_REF].

FS = b 2 b V re f . ( 4
Concerning the resolution and the FS of the embedded test ADC, a good trade-off is to relax its resolution while adjusting its FS to the magnitude of the target measurements, in such a way that the effective resolution of the test circuit, compared to the resolution of the ADC under test is larger. What that means in a practical case is that since the MCT is around 1 LSB of the ADC under test, the FS of the embedded ADC can be made much smaller than that of the ADC under test, highly reducing the constraints on its resolution. Regarding the conventional CDAC SAR ADC in Figure 4.3a, during test mode the test instrument is connected directly to node V X , and the CDAC is operated to generate the widths of the codes associated with the MCTs as detailed in Chapter 3. Also as discussed in Chapter 3, the MCT voltage V i is obtained at the output of the CDAC after the steps of pre-charge and redistribution. Subsequently, this voltage is switched to the input of the embedded ADC through the test switch S (Figure 4.1) and integrated for 2 R cycles using a first-order Incremental ADC to obtain N out ∝ V i . Observe that the input of the Incremental ADC corresponds to the code length of the transition being measured. Then, by rearranging equation 4.1, the width of the i-th MCT is given by

i ≈ b 2 b V re f N out,i 2 R V LSB = b 2 b 2 N-R N out,i . (4.3)
Like it was already discussed, by definition i represents the quantized version of the i-th MCT, which will be the length of 2 N-i-1 codes in the CDAC SAR ADC. After associating each of the N measured step sizes to its respective codes, the DNL of the k-th code in LSB can be calculated:

DNL k = k -1.
The calculation and post-processing of the INL were already provided in detail in Chapter 3.

In order to provide some design guidelines for the implementation of the Incremental ADC in the context of the proposed reduced-code static linearity test application, the trade-offs between the accuracy in the estimation of static linearity performances and the resolution and full-scale of the test ADC will be exploited. These trade-offs are analyzed based on behavioral simulations performed in Matlab. Realistic behavioral models of the test setup in Figures 4.2 and 4.3a have been developed following the guidelines in [START_REF] Malcovati | Behavioral modeling of switched-capacitor sigma-delta modulators[END_REF] and the SAR ADC models developed in the last chapter.

Considering the test methodology proposed in Section 3.3, Figure 4.4a plots the average error in the estimation of INL (computed as the difference between estimated and actual INL) as a function of FS for a capacitor mismatch standard deviation σ = 0.3% and R = 10. The FS in equation 4.2 is normalized by V re f for simplifying the trade-off evaluation. A total of 250 randomly generated SAR ADC samples have been simulated. Note that the curve presents a range of small errors around the center region of its horizontal axis and a high error region around its extremities. As expected, the errors are higher for higher resolution SAR ADCs. Notice that only N measurements are needed in each scenario for inferring the complete INL characteristic.

To help illustrate why there are high error values on the curve extremities, the output of the integrator is plotted in Figure 4.5 for FS << 1 and FS ≈ 1, considering an input amplitude of 5 LSB. The continuous and dashed lines correspond to extreme and marginal cases, respectively. As b 2 ∝ FS, for small values of FS, b 2 is also small enough to the point of not bringing the integrator output voltage below zero. That means the system is unstable, as can be seen in Figure 4.5a. Conversely, if FS is large in comparison to the input, so is b 2 and hence the integrator output does not exceed 0 (or only very little) for a given input. Therefore, large quantization errors take place. This latter case can be observed in Figure 4.5b. Consequently, the lateral extremities of Figure 4.4a represent zones where the Incremental ADC operation is out of range.

Figure 4.4b illustrates the average INL error as a function of FS for a 10-bit SAR ADC, now for different values of R. Again, there is an optimal range for FS. However, in this case, the dependence with R happens only on the right side of the curve. For smaller values of FS, increasing R has little effect on the INL error. This is due to the fact that if the integrator output is unstable, taking more samples would not solve the instability issue. The integrator output would only continue to go up until eventually reaching saturation voltage (refer to error is smaller for higher values of R, as expected. However, it is important to pay attention to the existing trade-off between error and test time, since the latter increases exponentially with R. Also, as will be demonstrated in the next sections, increasing the resolution of the Incremental ADC also escalates the design constraints on the building blocks of the Incremental ADC, particularly on the OTA used in the integrator. Taking into account the conversion time of each of the Incremental ADC measurements, the test time for a complete static linearity characterization can be estimated. Note that the voltage representing the code width of the MCT needs to be generated for every integration step. This means that for the i-th capacitor being measured, the modified SAR operation needs (2 + i)T ck 2 R cycles to finish the operation, with exception of the case i = 0 where it needs 3T ck 2 R cycles. Thus, for the CDAC SAR ADC in Figure 4.3a, the total test time can be expressed as

T CDAC = T ck 2 R 3 + N-1 ∑ i=1 (2 + i) = 1 2 T ck 2 R (N 2 + 3N + 2), (4.4)
where T ck is the clock period (assuming that both the SAR ADC under test and the Incremental ADC share the same clock) and R is the resolution of the Incremental ADC. The quadratic growth is due to the modified SAR operation for missing code detection. The percentage of the total savings in test time in comparison to a 128 hits-per-code linear ramp histogram as a function of the SAR and Incremental ADC resolutions is plotted in Figure 4.6. As it can be observed, the test time reductions are substantial. Also, as it would be expected, the test time savings improve as the SAR ADC resolution increases. The main conclusion that can be drawn from Figures 4.4 and 4.5 is that if the FS of the In-4.3. Implementation for different SAR ADC architectures cremental ADC is not carefully chosen, the test accuracy can be at stake. In order to provide a quantitative way of obtaining an appropriate value for the FS of the embedded test instrument, the fact that the expected measurements are around 1 LSB of the ADC under test can be exploited. Indeed, once the standard mismatch deviation of the unit capacitor in the CDAC for a given technology is known, the worst-case DNL can be estimated:

A max ≈ V re f 2 N 1 + 3σ 2 N -1 , (4.5)
where A max is an estimation of the maximum variability of the MCT voltage. For providing an extra design margin to account for additional error sources, a scaling factor ξ > 1 is introduced, and the FS of the Incremental ADC can be designed using

FS IADC = ξ A max . (4.6)

MCT-based testing: SCDAC SAR ADC

For the SC-SAR ADC in Figure 4.3b, the idea is similar to the measurement of the CDAC SAR ADC, with the post-processing particularities addressed in Subsection 3.3.2. During test mode, the embedded Incremental ADC is first connected to the V A node, and the SCDAC array is programmed to generate the code widths of the MCTs corresponding to the LSB section of the array as detailed in [START_REF] Feitoza | Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental Σ∆ Converter[END_REF]. Subsequently, the Incremental ADC is connected to node V X and the SCDAC array generates the code widths of the MCTs for the MSB section. The FS of the Incremental ADC can be designed following the same guidelines as the ones given for the conventional SAR ADC, but now adjusting the FS to the magnitude of the partial MCTs instead of the full CDAC.

The following analysis is similar to the one performed to explain the operation of the conventional SAR ADC selected-code test, with some particularities. Now, the digital code length representations in LSBs of each partial CDAC are given by

MSB i ≈ 2 M-R b 2 b X N out,i , (4.7) LSB j ≈ (2 L + 1) 2 R b 2 b A N out, j , (4.8)
where b X and b A represent the input gain of the Incremental ADC when the system is configured for measuring the MSB and LSB segments of the SCDAC array, respectively. Notice that these input gains do not have to be equal, which, as it will be shown later, may have important implications for simplifying the implementation.

To provide some design guidelines for the implementation of the embedded ADC in this case, let us explore the trade-offs between the accuracy in the estimation of static linearity performances and the resolution and full scale of the Incremental ADC for test. These trade-offs are explored based on behavioral simulations performed in Matlab. Realistic behavioral models of the test setup in Figs. 4.1 and 4.2 have been developed once again following the guidelines in [START_REF] Malcovati | Behavioral modeling of switched-capacitor sigma-delta modulators[END_REF].

The first relevant aspect to take into consideration is the measurement accuracy as a function of the full-scale range of the dedicated ADC for test. In this line, to simplify the interpretation of the results, the full-scale of the embedded Incremental ADC for the MSB measurement configuration FS MSB IADC = (b 2 /b X )V re f was normalized to the FS of the SCDAC (i.e., V re f ). Figure 4.7a plots the average INL estimation error as a function of FS MSB IADC using the proposed test methodology for different SAR ADC resolutions, N (LSB CDAC resolution is fixed to L = 4). The results are obtained by calculating the average test error of 250 randomly generated SC-SAR ADC samples with capacitor mismatch standard deviation σ = 0.1 % and R = 8. It can be observed that the curve presents a zone with high measurement errors in the lateral extremities of its horizontal axis and a range of small errors around its center. Not surprisingly, higher SC-SAR ADC resolutions Chapter 4. Practical SAR ADC BIST Implementation On the other hand, Figure 4.7b shows the INL estimation error as a function of FS MSB IADC for different values of the Incremental ADC resolution, R. The resolution of the SC-SAR ADC is fixed to N = 10 bits (M = 6 and L = 4) for this experiment. It can be observed that there is an optimal range for FS MSB IADC , like the previous case. Nonetheless, for this case, there is no significant dependence with R for low values of FS MSB IADC . This is due to the fact that the output of the integrator saturates, which means that taking more samples does not affect the operation of the circuit. This effect is the same as for the CDAC SAR ADC like it was demonstrated in the previous subsection [START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF]. It can also be observed that in the optimal range, the error is smaller for higher values of R. However, since the test time is again proportional to 2 R , it is important to pay attention to the existing trade-off between error and test time.

In this line, Figure 4.8 illustrates the total percentage of time saved in comparison to the standard linear histogram test with 128 hits-per-code for different values of N. As it can be observed, major savings in test time can be obtained. As expected, the test time savings for the SCDAC SAR ADC are larger than for the conventional CDAC SAR ADC. Looking at Figure 4.7b, it can be seen that relatively small errors can be obtained for some values of FS MSB IADC even for modest values of R. For instance, less than 0.4 LSB error can be obtained for a 6-bit Incremental ADC measuring a 10-bit SC-SAR ADC with less than 1 % of total standard LHT time.

A similar estimation of the value of the FS of the Incremental ADC can also be developed for the SCDAC SAR ADC. Observe that equations 4.5 and 4.6 can be applied here by considering the resolution of the partial CDAC M instead of N. Then, the full-scale can be calculated using:

FS MSB IADC = ξ V re f 2 M 1 + 3σ 2 M -1 , (4.9)
where M is the resolution of the MSB CDAC. As it will be shown later in this chapter when the SAR/Incremental ADC co-design is undertaken, the FS can be automatically adjusted by design when the LSB array is being measured. Also, note that A max is proportional to 3σ √ 2 N -1 and 3σ √ 2 M -1 for the CDAC and SCDAC SAR cases, respectively. This is the reason why the modified SAR operation for the detection of missing codes is applied for the CDAC SAR ADC. This relaxation in the magnitude of the MCT voltages for the SCDAC SAR ADC is what enables the digital detection of missing codes, which further reduces the total test time. Now, instead of i + 2 cycles per capacitor being measured like in the CDAC SAR case, only 3 cycles per capacitor per integration step are needed. As a consequence, the test time for a full static characterization can be estimated as

T SCDAC = 3T ck 2 R N, (4.10)
which is indeed faster in comparison to the CDAC SAR ADC measurement.

To further explore how the unit capacitor mismatch factor σ plays a role in the measurement errors, Figure 4.9 shows boxplots for the INL estimation error of a 10-bit SC-SAR ADC (M = 6, L = 4) as a function of the expected capacitor mismatch level in the capacitors, ranging from σ = 0.1% to σ = 1.5%. The resolution of the embedded Incremental ADC used in this simulation is R = 9 bits (512 clock cycles per sample). For each iteration, the values of FS MSB IADC are chosen using FS MSB IADC = ξ A max , with ξ = 1.25. The number of iterations for each σ value was 200. It can be observed that the proposed full-scale sizing strategy yields good results, with smaller measurement errors for smaller values of σ , as it could be expected.

Split-capacitor V cm -based SAR ADC

The analysis provided for the SCDAC SAR ADC can be also applied to the split-capacitor V cmbased SAR ADC. However, a few particularities have to be taken into account. Since the MSB capacitance is no longer necessary, the total capacitance of the MSB partial CDAC is now given by (2 M-1 -1)C u instead of (2 M -1)C u . That will change the computation of the optimal FS in equation 4.9. Furthermore, the post-processing steps have to be adapted to take into account the Chapter 4. Practical SAR ADC BIST Implementation particularities of the V cm -based switching such as DNL splitting, which was already explained in 3.3.3. Regarding the test time, the MSB partial array has one less capacitor that needs to be measured, which translates to an overall test time of (4.11) meaning that the test time savings will be further increased.

T VCM = 3T ck 2 R (N -1),

Segmented SAR ADC

Regarding the segmented SAR ADC in Figure 4.3c, a selected-code test technique that applies superposition of the all-code measurements of each individual sub-DAC is proposed [START_REF] Feitoza | Reduced-code techniques for on-chip static linearity test of SAR ADCs[END_REF]. The main idea was already described in 3.3.4. During test mode, the Incremental ADC is subsequently connected to nodes V X and V A for characterizing the MSB and LSB DAC segments, respectively. In this case, the FS of the Incremental ADC can be separately adjusted to match the output range of the MSB and LSB sub-DACs. For the MSB sub-DAC, the maximum output voltage to be measured can be expressed as V re f (2 M -1)/2 M , while for the LSB sub-DAC the maximum output voltage is scaled by a factor of 2 L . Even if making the FS programmable adds further complexity to the design, the proposed reduced-code technique offers a significant reduction of static linearity test time. The total test time for a full static linearity characterization can be expressed as

T SEG = T ck 2 M+R MSB + 2 L+R LSB . (4.12)
where R MSB and R LSB are the resolution of the Incremental ADC for measuring the MSB and LSB segments, respectively. This reflects the fact that the FS of the Incremental ADC is independently adjusted for each segment. It has to be noted that for this topology, the quantization error introduced by the embedded ADC for the measurement of the MSB sub-DAC can significantly degrade the measurement. Thus R MSB has to be designed so that the quantization error is negligible in comparison to one LSB of the complete N-bit ADC. Note that this is not an issue for MCT-based techniques because the FS is scaled to 1 LSB of the ADC, the quantization error is naturally negligible.

System-level simulation results

In order to provide a visual comparison of the potential test time reduction for the presented reduced-code test techniques, Figure 4.10 shows the time savings in comparison to a complete 128 hits-per-code linear ramp histogram test as a function of the SAR ADC under test resolution. As an illustrative example, the resolution of the Incremental ADC is kept constant as 10 bits for the three MCT-based tests and as 14-bits/10-bits for the MSB/LSB parts of the segmented architecture. It can be observed that, as expected, the segmented method yields a higher test time. However, it is still considerably faster than the complete histogram test. Note also that as the resolution N increases the relative savings in test time improves.

The feasibility and performance of the proposed reduced-code test static linearity test techniques were verified by realistic behavioral simulations of three SAR ADCs with embedded firstorder Incremental ADCs. The proposed case studies include a 10-bit CDAC SAR ADC, a 6×4 SC-DAC SAR ADC, and a 5×5 segmented ADC with capacitor-resistor divider sub-DACs. The embedded test ADC for each case study was dimensioned as explained in the previous section. For the two pure capacitive architectures, the resolution is set to 6-bits. For the segmented case, the resolution is set to 14/10-bits for characterizing the MSB/LSB segments, respectively. As previously explained, this value is chosen in order to make sure the quantization error is negligible and does not compromise the overall test accuracy. technologies. Capacitor mismatch was modeled with σ =0.3 %, and resistor mismatch is set to σ =1 %. The INL estimation error is illustrated in Figure 4.12. It is obtained by calculating the difference between the INLs retrieved by histogram and reduced test methods. As can be observed, the test results for the selected-code test methodologies are very close to the results obtained with the all-code histogram tests. Total test times were 0.27 %, 0.12 %, and 35.42 % of the 128 hitsper-code linear histogram test time for the CDAC, SCDAC and segmented DAC SAR ADCs, respectively.

Finally, Figure 4.13 illustrates the INL estimation error as a function of the resolution of the embedded Incremental ADC. Since the constraints for the segmented-based SAR ADC are more stringent for the MSB segment, R LSB =10 bits is fixed R MSB is swept. As it was previously discussed, it can be observed that for the MCT-based methodology Figure 4.13a confirms that the scaling of the FS relieves the constraints for the embedded instrument. In contrast to that, Figure 4.13b confirms that for the segmented-based technique the embedded Incremental ADC has to be designed with a resolution that is larger than the SAR ADC itself in order to mitigate the measurement errors. It is also important to observe that errors are higher when characterizing the SCDAC SAR ADC in comparison to the CDAC SAR ADC. In general, for the SCDAC SAR ADC, it is good practice to apply an instrument with higher resolution than the one employed to characterize the CDAC SAR ADC.

Co-integration of SAR ADC and BIST circuitry

Hereafter, the focus is going to be directed to the SCDAC SAR ADC. This topology has been selected for a physical implementation taking into account today's applications. This topology is the most ubiquitous and it provides the best trade-offs for surface and power consumption. From a testing standpoint, it is also the topology that presents the most important challenges, mainly due to the parasitics associated with the bridge capacitor. In any case, the co-integration guidelines presented in this section can be easily extended to other capacitive-based SAR ADCs.

In a switched-capacitor implementation of a first-order Incremental ADC as the one in Fig- at time nT ck . Nonetheless, a dedicated sampling capacitor is not a requirement for the implementation proposed in this work. It is possible to perform this charge transfer by using a principle similar to an MDAC in a pipelined ADC [START_REF] Song | A 10-b 15-MHz CMOS recycling two-step A/D converter[END_REF], by building capacitor C s with the output capacitance of each partial CDAC. This way, the sampling stage is performed by the CDAC operation, with the additional advantage of scaling the input voltage of the Incremental ADC according to the capacitor ratios between each CDAC segment total capacitance and C f , as it will be shown in the following paragraphs. In this line, Figure 4.15 shows a conceptual schematic of the complete BIST scheme for reduced-code test measurements. The capacitor C sR is responsible for the feedback of the scaled reference voltage -V re f C sR /C f when the comparator detects that the output of the integrator is positive. The DC voltages V X and V A are generated by the capacitive array and digitized by the embedded converter. As it was previously explained, two cycles are used for generating the voltage related to the step length of the i-th MCT being measured. The third cycle is the integration step, where the switches S X and S A control the MSB and LSB partial CDAC connections to the test instrument.

charge conservation, V in [nT ck ]C s -V out [nT ck ]C f = -V out [(n + 1/2)T ck ]C f , i.e. V out [(n + 1/2)T ck ] = V out [(n + 1)T ck ] = V out [nT ck ] - C s C f V in [nT ck ], (4
A further simplified version of Figure 4.15 is conceptually shown in Figure 4.16. Voltage V i corresponds to the target MCT length to be measured, generated as described in Chapter 3. After S k (k = A for the LSB segment, k = X for the MSB segment) is connected, in a similar manner to equation 4.13, the charge stored in the CDAC is transferred to C f in a way that the output is incremented by

≈ V i ×C tot,k /C f = b k V i , where b k = C tot,k /C f
is the integrator gain. By substituting the capacitor C s by the CDAC itself, the area overhead of the test can be highly reduced.

Taking into consideration the guidelines for sizing of FS MSB IADC derived previously, the capacitors in the integrator can be sized. By using the definition of FS MSB IADC together with the estimation of A max in equation 4.5, it follows that

FS MSB IADC = b 2 b X V re f = b 2 C f C out,MSB V re f = ξ A max , (4.14)
Chapter 4. Practical SAR ADC BIST Implementation where the output capacitance of the MSB array is C out,MSB ≈ 2 M C u , with C u being the unitary capacitor of the array. Hence, the optimal value for the integrator feedback capacitor C f ,opt can be derived

- + Cf Cout,k + - Vi Sk - + Cf Cout,k Sk + - bkVi Cout,LSB Cout,MSB CL-1 C1 Cu SL-1 S1 S0 Sd C0 C1 SM(M-1) SM1 SM0 C0 Catten CM-1
C f ,opt = ξ b 2 C u 1 + 3σ 2 M -1 . (4.15)
The value of the reference feedback capacitor, C sR,opt , is then sized as

C sR,opt = b 2 C f ,opt . (4.16)
The capacitive scaling of the proposed implementation has the additional advantage of naturally compensating the magnitude difference between the measurements of the MSB and LSB sections of the SCDAC. Let us consider again the proposed test strategy described in Section 3.3.2 in view of the proposed implementation. For the measurements of the MSB segment, switch S X in Figure 4.16 is turned on and the integrator input gain is given by b X ≈ 2 M C u /C f . As discussed before, for an ideal SCDAC, the voltage generated at the node V X when generating the partial MCTs is given by ∆ X = V re f /2 M , where ∆ X is the ideal step of the MSB partial CDAC. Conversely, when S A is on for the measurement of the LSB segment of the SCDAC, the integrator input gain is given by b A ≈ (2 L + 1)C u /C f , while, for an ideal SCDAC, the voltage generated at node V A is given by ∆ A ≈ V re f /(2 L + 1), as it was shown in equation 3.14. Defining r as the ratio between step sizes, one obtains

r = ∆ X ∆ A ≈ V re f /2 M V re f /(2 L + 1) = 2 L + 1 2 M , (4.17)
but at the same time by computing the ratio between the input gains of the integrator in the two configurations b

X b A = FS LSB IADC FS MSB IADC = C out,MSB /C f C out,LSB /C f = 2 M 2 L + 1 = 1 r , (4.18)
which shows that the FS of the Incremental ADC is scaled in a way that naturally compensates for the change in magnitude of the expected values of the partial step sizes. The proposed implementation assures that the factor by which these magnitudes change is exactly the value that guarantees that the measurement remains on the optimal range for both the MSB and LSB segments of the SCDAC.

Finally, let us introduce one last important feature of merging the SCDAC and embedded test circuitry. Since the voltage V X in the CDAC of Figure 2.10 starts and finishes at V cm (Figure 4.4. Co-integration of SAR ADC and BIST circuitry 2.11), it is known that the dependency on the parasitics connected to the comparator's input is eliminated [START_REF] Yoshioka | A 10-b 50-MS/s 820-µW SAR ADC With On-Chip Digital Calibration[END_REF][START_REF] Huynh | Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS[END_REF][START_REF] Chen | Split capacitor DAC mismatch calibration in successive approximation ADC[END_REF]. This is not different for the MSB partial CDAC in Figure 4.17. Note that C p,M and C p,L represent the total parasitic capacitances connected to ground from nodes X and A, respectively, while C p,B represents the parasitic capacitance between the top plate of the bridge capacitor C B with the top plates of the other capacitors of the CDAC array. Hence, by considering these parasitic effects for the MCT generation algorithm, it can be shown that the new voltage V X is given by

V X = V re f C i -∑ i-1 j=0 C j C MT +C L,eq +C p,M , (4.19)
where C L,eq is the equivalent capacitance looking at the bridge capacitor

C L,eq = (C B +C p,B )(C LT +C p,L ) C B +C p,B +C LT +C p,L . (4.20)
Hence, since the parasitics appear in the denominator of equation 4.20 in the MCT generation process, that leads to a smaller voltage and hence to large measurement errors. However, by looking at the conceptual schematic in Figure 4.16 and considering that parasitics are present, note that the updated gain is now given by

b = C MT +C L,eq +C p,M C f ,
because the parasitic capacitor is also charged in the pre-charging phase. This shows that at the output of the integrator V int = bV X the effects of parasitics are eliminated, yielding the correct results for the mismatch measurement. On the other hand, to make sure that the effects of metaloxide-metal (MOM) capacitor parasitics at the LSB side are accounted for, a modified version of the post-processing algorithm is proposed. Notice that the total parasitics in the LSB side are given by

C p,L = C T -S,0 +C T -S,B + L-1 ∑ i=0 C T -S,i , (4.21)
where C T -S,i (from i = 0 to L -1) and C T -S,B are the parasitic capacitances from the top-plate of the LSB array and bridge capacitors to the substrate, respectively. The extra factor of C T -S,0 accounts for the parasitics of the dummy capacitor. Extra parasitics exist due to the surroundings of the MOM capacitor, and they can be extracted on the post-layout level. However, as it will be shown later in this work, the bridge capacitor can be co-designed to compensate for the parasitic capacitors, at least for the nominal case. Hence, once the parasitics are extracted from the post-layout results and the values of the capacitors in the SCDAC array are extracted from the measured weights after the end of the reduced-code technique, a model of the SAR ADC can be constructed. Even though the parasitics on the MSB side of the array do not play a big role on the SAR ADC non-linearity, it is important to extract them to obtain a complete model. The total parasitic capacitance in the right MSB DAC can be evaluated by using

C p,M = C T -S,B + M-1 ∑ j=0 C T -S, j , (4.22)
where C T -S, j with j = 0 to M -1 (or to M -2 for the V cm -based SAR ADCs) is the parasitic capacitance associated with the j-th capacitor in the MSB array. Then, a digital ramp in the digital domain can be used to perform the reduced-code measurement of the SAR ADC using this extracted model. Another possible solution to reduce the effects of parasitics and make sure the mismatches are the main source of nonlinearities would be to implement the parasitic calibration algorithms in [START_REF] Yoshioka | A 10-b 50-MS/s 820-µW SAR ADC With On-Chip Digital Calibration[END_REF][START_REF] Huynh | Design of a capacitive DAC mismatch calibrator for split SAR ADC in 65 nm CMOS[END_REF][START_REF] Chen | Split capacitor DAC mismatch calibration in successive approximation ADC[END_REF] prior to the start of the reduced-code linearity test technique.

Chapter 4. Practical SAR ADC BIST Implementation Figure 4.17: Schematic of the SCDAC SAR ADC including the effects of the parasitic capacitors. C p,M represents all the parasitic capacitors connected to node X, C p,L represents all the parasitics capacitors connected to node A, and C p,B represents the parasitics between the top metal plate of the bridge capacitor and the other top plates of the capacitors in the CDAC arrays.

SAR Logic C u C u 2C u 2 M-1 C u V in V refp V refn C u 2C u 2 L-1 C u C B V X V A C p,M C p,B C p,L C L,eq C M,eq
To provide a first validation of this idea, a 10-bit (6×4)V cm -based SAR ADC behavioral level is constructed in Matlab using the same guidelines as in 4.3.5. First, a SAR ADC model whose only source of errors is the MOM capacitor parasitics is set up. This is done to obtain a first verification of the proposed technique without the effects of mismatch. To obtain practical results for this measurement, an artificial error of 10% was introduced in the estimated parasitics of the reduced-code model to account for eventual discrepancies that may happen in a real-case implementation. The linear ramp histogram and reduced-code static linearity test results are plotted in Figure 4.18. The RMS error of the INL estimation is of 0.11 LSB, which shows that the parasitic errors can be detected with good accuracy. Notice that since a 4-bit LSB array is used, the DNL problems appear at multiples of 32. In general, the nonlinearities due to parasitics are going to show at the codes that are multiples of 2 L+1 . After that, an artificial mismatch of 2% is introduced in the MSB-1 capacitor to validate the test methodology in the presence of both capacitor mismatch and parasitics. The guess in the parasitic capacitance is kept with a 10% error. The simulation results are shown in Figure 4.19. The INL measurement estimation RMS error is of only 0.13 LSB.

Guidelines for the design of the embedded Incremental ADC for test

As the Incremental ADC in Figure 4.15 is formed simply by an integrator, a comparator and a digital counter, its performance is mainly limited by the non-idealities of the integrator. This is due to the fact that the comparator can be reused from the SAR ADC, and the main limitation it adds to the circuit performance is its offset that, as it will be shown later, it can be virtually eliminated through the use of offset-canceling techniques. Regarding the digital counter, it is a fairly simple circuit, and once the timing constraints of the D flip-flops are respected, it should not play a big role on the converter performance. In this section, the impact of the main non-idealities in the Incremental ADC building blocks are analyzed and the design guidelines for an accurate test are derived. In particular, the effects of integrator leakage and the dynamic behavior of the amplifier are considered. The amplifier offset can also be greatly compensated using well-known techniques such as auto-zeroing or chopper stabilization, and for this reason it is not considered in this analysis. Other non-idealities in the Incremental ADC can be considered as second-order contributions.

First, let us consider the effect of a finite gain in the amplifier. The classical model of a negative

v e (t) = v in (t) 1 + β A 0 ,
where β is the feedback factor and A 0 is the open-loop gain of the amplifier, the minimum DC gain of the OTA as a function of the Incremental ADC resolution R can be derived by defining a value of v e that is smaller than a fraction of one LSB of the Incremental ADC. To provide a sufficient design margin, the maximum allowable error is set to one-eighth of the Incremental ADC LSB. Hence, the minimum gain of the amplifier A 0min,dB in dB is given by

A 0min,dB = 6.02(R + 3) -20log(β ξ ), (4.23)
where ξ is defined as the ratio between the FS of the Incremental ADC and the LSB of the SAR ADC under test, as it was previously defined in this chapter and in [START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF][START_REF] Feitoza | Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental Σ∆ Converter[END_REF]. This equation is plotted in Figure 4.21a for different values of ξ . Observe that increasing the value of ξ alleviates the constraints on the minimum amplifier gain.

Concerning the dynamic behavior of the amplifier, a similar reasoning can be used for estimating the minimum gain-bandwidth product and Slew Rate (SR). Considering a dominant-pole model for the amplifier, if one requires the integrator output voltage to settle within one-eighth of the LSB precision to the ideal final value, it can be shown that,

0 v in (t) v e (t) β v out (t) v fb (t)
v out (t) = V out, f inal 1 - 1 2 R+3 = V out, f inal 1 -e -1 2 f ck τ
, where τ = 1/(2πGBW) and f ck is the integrator frequency. Then, it follows that the minimum 4.6. Some comments on the testing of the Incremental ADC gain-bandwidth GBW min can be estimated using

GBW min = f ck (R + 3) ln(2) π . (4.24)
Regarding the slew rate, the largest output variation is given by

V s = C sR C f (V re f ,p -V re f ,n
), and hence this value defines our worst case scenario. The actual output of the integrator in equation 4.13 by considering also its settling characteristics and the integration in the feedback path is given by

v out [(n + 1)T ck ] = v out [nT ck ] + αV s (1 -e -1 2 f ck τ ),
where α = A 0 /(1 + A 0 ) is the leakage factor of the integrator. The minimum required SR can be determined as

dv out (t) dt max = SR limit = α C sR C f (V re f ,p -V re f ,n )2πGBW. (4.25)
Figure 4.21b shows the minimum required GBW and SR of the amplifier as determined by equations (4.24) and (4.25) as a function of the Incremental ADC clock frequency. It is important to notice that the Incremental ADC operation frequency may be considerably smaller than the clock frequency of SAR ADC to significantly relax the design constrains of the Incremental ADC while maintaining test accuracy. Even though that will increase the reduced-code test time, it is important to observe that based on previously obtained results [START_REF] Feitoza | Reduced-code static linearity test of SAR ADCs using a built-in incremental Σ ∆ converter[END_REF][START_REF] Feitoza | Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental Σ∆ Converter[END_REF][START_REF] Feitoza | Reduced-code techniques for on-chip static linearity test of SAR ADCs[END_REF] in Figure 4.10, a large margin for test time reduction is available.

Some comments on the testing of the Incremental ADC

As it can be observed from the previous sections, the Incremental ADC has some conditions and minimum specifications to work properly. If the BIST circuitry fails either by variability and/or defects on the IC fabrication process or by other causes such as aging or PVT variations, the whole test may be jeopardized. Even though this is out of the scope of this thesis, it is important to point out that the domain of digital test and calibration of Σ∆ ADCs is already quite developed [START_REF] Wu | A 81-dB Dynamic Range 16-MHz Bandwidth Σ∆ Modulator Using Background Calibration[END_REF][START_REF] Edward | A 43-mW MASH 2-2 CT Σ∆ Modulator Attaining[END_REF][START_REF] Bafandeh | Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH Σ∆ Modulators[END_REF][START_REF] Leger | Low-Cost Digital Detection of Parametric Faults in Cascaded Σ∆ Modulators[END_REF]. Errors such as integrator leakage [START_REF] Wu | A 81-dB Dynamic Range 16-MHz Bandwidth Σ∆ Modulator Using Background Calibration[END_REF][START_REF] Edward | A 43-mW MASH 2-2 CT Σ∆ Modulator Attaining[END_REF] and limited GBW [START_REF] Bafandeh | Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH Σ∆ Modulators[END_REF] can be fully-calibrated in the digital domain. Hence, the digital part of the proposed BIST can be extended to evaluate and calibrate the Incremental ADC, assuring the test accuracy.

Conclusion

This chapter handled the trade-offs regarding the on-chip implementation of the proposed test technique. First, an architecture based on an embedded ADC for test was proposed. In particular, the use of a first-order Incremental ADC (also known as Incremental Σ∆ ADC) was explored. Subsequently, the required specifications of the embedded ADC were derived as a function of the characteristics of each of the different topologies of the SAR ADC under test, which for this work are the CDAC SAR ADC, the SCDAC SAR ADC, the V cm -based SAR ADC and the hybrid resistor-capacitor segmented DAC SAR ADC. It was demonstrated that for a given set of specifications of the SAR ADC, there is an optimal range of values for the FS of the embedded ADC for test. These values are also dependent on the expected mismatch in a given CMOS technology process. The test time reduction in comparison to the linear histogram test for each SAR ADC topology was also evaluated, and a comparison between each testing technique was provided. A merging of the CDAC with the embedded ADC for test is proposed, and it was demonstrated that not only this implementation reduces the area overhead of the test circuitry because it eliminates the need for the sampling capacitor on the input integrator of the embedded test ADC, but it also has very good properties such as the automatic adaptation of the optimal FS when measuring the LSB partial CDAC. Hence, based on the derived values for the optimal FS for the embedded ADC and on the merged circuit itself, a methodology to design the optimum values of the feedback capacitor C f and reference voltage feedback capacitor C sR was provided. It was also shown that this merging eliminates the measurement errors related to the parasitic capacitors connected to the output node of the MSB partial CDAC. To account for the parasitics, an extension of the previous algorithms is provided to guarantee that the test can also detect the errors caused by the MOM capacitor parasitics. Accurate results were obtained for the behavioral level simulations. In the last part of the chapter, the specifications for the blocks of the Incremental ADC were provided. Since the comparator can be reused from the SAR ADC design and the counter is a fairly simple design, the characteristics of the amplifier were taken into account. Based on the maximum allowed leakage, the minimum gain was derived; and based on the dynamic properties of the integrator, the minimum GBW and SR were determined. These specifications will be relevant in the next chapter where the transistor-level design of a case-study SAR ADC + BIST will be provided.

5

Case study: design of a SAR ADC with built-in reduced-code static test

In this chapter, the circuit-level design of the proposed static linearity BIST is performed. First, a case study is designed, namely the V cm -based switching SCDAC SAR ADC. The trade-offs and design choices are provided for each one of the key building blocks of the converter. Further, design details are provided for some of the auxiliary blocks needed to guarantee a good performance of the ADC, namely the on-chip clock recovery circuit and the on-chip reference buffers. Subsequently to the case study design, the transistor-level design of the BIST is provided. Particular attention is given to the design of the OTA, which is the heart of the Incremental ADC in the BIST. The specifications were derived from the guidelines provided in Chapter 4, and the details on the design trade-offs and implementations are also provided. Furthermore, the problem of offset canceling is also undertaken, and a solution based on inverting the inputs of the integrator circuit is proposed. Subsequently, the digital blocks are presented. The main digital control block is implemented using well-established digital flow techniques, and the remaining digital blocks are implemented using a semi-custom approach. Finally, the layout of the complete system is provided, together with transistorlevel and extracted post-layout level simulation results which prove the feasibility of the design.

Case Study: SAR ADC design

In order to validate the design guidelines presented in chapter 4, this chapter provides an example of application in a practical case study. For this case study, a 20 MSPS (clock frequency of 240 MHz) 10-bit (6x4) fully differential SCDAC SAR ADC that will be used as the DUT was designed. The overall architecture of the proposed ADC is shown in Figure 5.1. The BIST inputs and outputs are neglected for the moment for clarity. The SAR ADC features a metal-oxidemetal (MOM) unit capacitor of C u = 9 fF, using the V cm -based capacitor switching for low power consumption. The SAR comparator is based on the well-known StrongARM latch topology. The full-scale of the SAR ADC is FS = 1.2 V pp with an input common-mode voltage of 640 mV. The reference voltages are V re f ,p = 940 mV and V re f ,n = 340 mV. The design of other blocks such as clock recovery and reference buffers is also presented. The ADC and the embedded test instrument have been designed using STMicroelectronics 65 nm CMOS technology.

CDAC design

One of the most important blocks of the SAR ADC design is the CDAC responsible for sampling the input signal and performing the binary search. A significant component of the total SAR ADC power consumption and area is determined by this section of the converter. As previously discussed, the V cm -based switching is used, which highly reduces the power consumption and halves the area by a factor of two when compared to a conventional SAR ADC. Since a split-DAC capacitor is used, the total surface occupied by the CDAC is further reduced. Also, the smaller the unit-capacitor of this binary-weighted array, the smaller the power consumption. This is due to the fact that the total energy is dynamic and hence proportional to CV 2 . That poses a clear trade-off with noise, due to the kT /C noise, and it may also deteriorate the performance due to higher component mismatches. Further, a large total capacitance complicates the design of an input buffer that can drive such load with high bandwidth, linearity, and low noise.

A 10-bit (6 × 4) SCDAC is designed. The clock frequency of the SAR ADC is 240 MHz and the converter needs 12 clock cycles per sample, which translates to a sampling frequency of 20 MSPS. This is due to the fact that an N-bit SAR ADC needs N cycles for estimating the input and two extra cycles for sampling. The extra clock cycle for sampling is good practice to ensure that the sampled input has enough time to settle. MOM capacitors are chosen because they provide better scalability when compared to metal-insulator-metal (MIM) capacitors. Also, MOM capacitors have the advantage of not requiring a dedicated thin oxide, which simplifies the fabrication process. Note that the LSB of this particular configuration is given by

LSB = 2 V re f ,p -V re f ,n 2 N ≈ 1.17 mV. (5.1)
For a random Gaussian noise, it can be estimated that the peak-to-peak value of the noise is given by six times its root-mean-square value. Since it is a differential topology, the random noise is added at both sides, and hence the noise value has to be further divided by √ 2 [START_REF] Ohnhäuser | Analog-digital converters for industrial applications including an introduction to digital-analog converters[END_REF], which yields a value of 138 µV. Note that since the top plates of both partial CDACs in Figure 5.1 are connected to V cm in the sampling phase, the total sampling capacitance is given by

C s = (2 M-1 -1 + 2 L )C u .
The minimum sampling capacitance is then given by

C s = kT V 2 n,rms ≈ 217 fF, (5.2)
which leads to a minimum unit capacitance C u of around 4.6 fF. The chosen value for the unit capacitor is then C u = 9 fF, which guarantees a good trade-off between sampling noise and area. The total MSB and LSB capacitances are given by C MT = 31C u = 279 fF and C LT = 16C u = 144 fF, respectively. The ideal value of the bridge capacitor C B can be determined using equation 2.9 and, for this specific design, it is given by C B = 16/15C u = 9.6 fF. Note however that the MOM capacitor models at the schematic level take into account the parasitics from the capacitor plates to the substrate. If this is not taken into consideration in the design, the SAR ADC is going to be highly nonlinear. Indeed, after accounting for the parasitics, the equivalent capacitance looking at the bridge capacitor should still be C u . Hence, the new design equation is given by

C B (C LT +C p,L ) = C u , (5.3)
where C p,L is the total capacitance from the LSB top plate to the substrate, as it was defined in equation 4.21. Hence, the bridge capacitor is co-designed to compensate for the parasitics on the LSB side, yielding an optimized design value of 9.95 fF.

For the choice of the switches, it is important to take into account the resistance of the transistors when the switches are turned on. This value together with the total capacitance is going to determine the settling time of the input and consequently the maximum speed at which the converter is able to operate. Thus, the on-resistance of a transistor as a function of the voltage between its terminals is given by

R on = 1 µ n C ox W L (V GS -V T H,N ) . (5.4)
This equation is presented for an NMOS transistor but it is also valid for a PMOS transistor by changing µ n by µ p , V GS by V SG and the threshold voltage by |V T H,P |, where µ n,p is the mobility of the electron/holes in the technology and C ox is the oxide capacitance per unit of area. The threshold voltage V T H is given by

V T H = V T 0 + γ( |2φ F +V SB | -|2φ F |), (5.5)
where V T 0 is the threshold voltage when V SB = 0, V SB is the source to body potential, γ represents the body effect coefficient or body factor, and φ F is the surface potential or flatband voltage.

The on-resistance of the transistors is plotted in Figure 5.2. As it can be observed, the resistance value explodes for low and high voltages for the PMOS and NMOS transistors, respectively. When sampling the input, that causes the delay to be a strong function of the input value, which can lead to distortion and nonlinearity. One solution to that is the use of transmission gates with both switches in parallel, as shown in Figure 5.3a. Its input resistance is also shown in Figure 5.2. Another option would be the use of bootstrapped switches [START_REF] Dessouky | Very low-voltage digital-audio ∆Σ modulator with 88-dB dynamic range using local switch bootstrapping[END_REF], but that adds extra design complexity and area overhead to the system, which is not really justified for a 10-bit design. Hence, transmission gates are chosen for the sampling of the differential inputs. Since the switches that connect the reference voltages to the CDAC are connected to a fixed voltage, simple transistors can be used as reference switches. I.e., since V re f ,p and V re f ,n are in the low resistance regions of the PMOS and NMOS transistors, respectively, single transistors are used as the switches, in the configuration shown in Figure 5.3b. Since V cm is around the middle scale, transmission gates are also used for guaranteeing a small delay for the common-mode voltage.

It is also important to consider the charge injected in the CDAC by the switches. Consider the sampling circuit of Figure 5.4a, which is an example of a top-plate sampling scheme. When the switch is closed, a charge is stored in the channel of the transistor M 1 . Subsequently, when the switch is opened, this charge flows into the circuit, causing a voltage error which can be estimated as [START_REF] Razavi | Design of analog CMOS integrated circuits[END_REF]

∆V = W LC ox (V DD -V in -V T H ) 2C H . (5.6)
This effect is mitigated because a differential implementation is used, however, since the injected charge depends on the input value, this still introduces nonlinearities to the conversion. Bottom sampling can be applied as a solution to this problem. As it is shown in Figure 5.4b the input V in is sampled in the bottom plate of the capacitor, while V cm is sampled in the top plate. Notice that if the switches open simultaneously, the charge injection is going to be dependent on the input. However, if the switch S cm opens slightly before S in , the injected charge is ∝ W LC ox (V DD -V cm -V T H )/(2C H ), which is a constant value. Subsequently, when the switch S in is opened, the top plate is floating and hence the CDAC voltage is not disturbed. Since the injected charge is no longer a function of the input voltage, its value can be seen as a constant offset value, which is eliminated by the differential implementation of the CDAC.

Comparator Design

Another key building block of the SAR ADC is the comparator. A StrongArm latch [START_REF] Razavi | The StrongARM latch [a circuit for all seasons[END_REF] reduces the global power consumption of the ADC. When the SAR ADC is on sleep mode, there is virtually no consumption in the comparator. In normal operation, only dynamic consumption happens in the regeneration phase. Its schematic is shown in Figure 5.5. As it can be observed, it consists of an input differential pair loaded with inverter latches. When the clock signal is 0, the nodes V out,p ,V out,n ,P and Q are pre-charged to V DD . When the clock signal goes up, the tail transistor M 7 starts conducting, the switches S 1 to S 4 are open, and the circuit regenerates the voltages at nodes V out,p and V out,n in response to the polarity of the differential input signal. The large-signal transient voltages in the strongArm latch are shown in Figure 5.6. Notice that since the voltages at nodes V out,p and V out,n are pre-charged to V DD in every clock cycle, this effect has to be isolated from the actual output of the comparator. There are several ways of achieving that, and in this work, an RS latch like the one shown in Figure 5.7 is shown. Observe that since the offset is not really relevant for SAR ADCs, the main bottleneck is guaranteeing that the input-referred noise of the strongArm is below the LSB of the ADC. A good design analysis that takes into account the noise of comparators can be found in [START_REF] Nuzzo | Noise analysis of regenerative comparators for reconfigurable ADC architectures[END_REF]. In short, increasing the aspect ratio W 1,2 /L 1,2 of the input transistors in comparison to W 7 /L 7 increase the gain and in turn reduces the input-referred noise, but this has the consequence of increasing the power consumption and reducing the overall speed of the comparator. These trade-offs are taken into consideration and the comparator is designed to perform at 240 MHz. The power consumption of the comparator is 74 µW .

Clock Recovery Circuit

As the speed and sampling rate of ADCs increase, its effective resolution tends to decrease due to second-order factors. One of the most relevant error sources for high-speed ADCs is the clock jitter [START_REF] Brannon | Sampled systems and the effects of clock phase noise and jitter[END_REF]. A clock signal is said to have jitter when it presents variations in its period or duty cycle. Further, since the clock frequency in our design is 240 MHz, the frequency dispersion and the low-pass characteristic of the pads might distort the clock signal and reduce the performance of the system. With that in mind, a clock recovery circuit is used in order to generate the highquality and low jitter clock signal on-chip. A conceptual schematic of the designed ultra-low jitter on-chip clock recovery circuit [START_REF] Núñez | Low-jitter differential clock driver circuits for high-performance high-resolution ADCs[END_REF] is illustrated in Figure 5.8. Ignoring all other error sources, the maximum ENOB that can be achieved by an ADC with clock jitter is given by [START_REF]IEEE Standard for Terminology and Test Methods of Digital-to-Analog Converter Devices[END_REF][START_REF] Núñez | Low-jitter differential clock driver circuits for high-performance high-resolution ADCs[END_REF] ENOB jitter = SNR jitter -1.76 6.02

= 3.32 log 1 J -2.94 -3.32 log ( f in ), (5.7)
where the clock jitter J is a zero mean random noise with standard deviation (RMS jitter) J = (∆t J ) 2 , ∆t J is the time variation in relation to the actual sampling time, f in is the frequency of the input signal, and SNR jitter is the signal-to-noise ratio, which is given by [START_REF]IEEE Standard for Terminology and Test Methods of Digital-to-Analog Converter Devices[END_REF] SNR jitter = 10 log P in P error,J = 10 log

1 2 A 2 in 1 2 (2π f in A in J) 2 = -20 log (2π f in J), (5.8)
where A in is the amplitude of the input signal. Note that the error power increases as A in and f in increase and no dependency is observed with the sampling frequency.

Considering the input frequency as the maximum Nyquist input of 10 MHz and ENOB jitter = 11 to provide some design margin, the maximum allowed value of the RMS jitter J is 6.35 ps. For the clock recovery circuit, a differential stage with active load and passive common-mode feedback is the chosen topology [START_REF] Núñez | Low-jitter differential clock driver circuits for high-performance high-resolution ADCs[END_REF]. Its schematic is illustrated in Figure 5.9. The first stage is responsible for detecting the zero-crossing point for the positive and negative input voltages. The embedded differential to single-ended conversion is done in current mode (transistors M 21 to M 24 ). The operation mode at nodes X and Y is established by the two resistors R, which works as a passive common-mode feedback. Inverter-based digital buffers are included in the circuit output in order to provide the required digital capability to drive the output load. The design methodology in [START_REF] Núñez | An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs[END_REF] is applied for the design of the clock recovery circuit, i.e. a systematic simultaneous optimization of jitter and power consumption is implemented. Post-layout large-signal Monte-Carlo simulations are performed for estimating the jitter of the proposed clock recovery circuit. For each Monte-Carlo sample, an ideal clock signal1 is fed to the input of the circuit, and a PNOISE analysis is performed to extract the clock jitter at the output of the clock recovery circuit. Figure 5.10 shows a histogram of the clock rms jitter calculated from the set of Monte-Carlo samples. As it can be observed, the average value for the clock rms jitter is 5.1 ps, which is equivalent to an ENOB jitter of 11.35. The standard deviation of the clock rms jitter for this Monte-Carlo set is 540 fs, and the total power consumption of the clock recovery circuit is 530 µW.

Reference Buffers

The overall performance of a SAR ADC relies strongly on the precision, stability, and drive capability of its voltage references. Incomplete DAC settling can cause conversion errors and enormous damage to the linearity of the converter. Since the CDAC operation presents a dynamic load, the reference source has to be able to handle this time-varying current. Dedicated and accurate reference voltages can be generated on-chip by using circuits such as bandgap references. However, the design of such circuits is very complex and power-hungry. Off-chip references might be a more power-efficient solution, but like the case for the clock in Section 5.1.3, the settling time of the DAC might be worsened by the limited bandwidth of the pads, or other effects such as the parasitic inductance of the bondwires, PCB traces, and the mutual inductance between adjoining bondwires [START_REF] Harikumar | Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS[END_REF]. Furthermore, these large currents drawn from the external reference flowing through these inductances might cause ringing on the DAC voltages. Such problems can be avoided by using on-chip reference buffers, as it is shown in the conceptual schematic in Figure 5.11. Several close-loop topologies are suggested in the literature, such as the operational amplifier in a source-follower configuration proposed in [START_REF] Harikumar | Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS[END_REF]. However, in this work, a simple source-follower in a common-drain configuration is proposed as the reference buffer. The main limitation of such topology is its relatively high noise, so a thorough investigation is performed in order to make sure the performance of the SAR ADC is not jeopardized. Another issue that prevents the application of the common-drain topology is the input-output voltage drop.

Here, the source-follower is implemented in a level-shifter fashion, i.e. the input voltages are different from the intended reference voltages. The on-chip buffer/level-shifter for the two references V re f ,p and V re f ,n and the internal V cm are shown in Figure 5.12. Note that the inputs do not need to have the same value as the intended reference, and for convenient reasons they are chosen to be V DD , V cm and ground, since these values need to be generated externally anyway for the ADC and BIST. An analysis will be carried for the generation of V re f ,p and it can be extended for the other two buffers in Figure 5.12. The on-chip buffers have the following design specifications: É Enough driving capability, which will translate to a high current.

É Low process variability, which will translate to large transistors.

É Low noise to avoid compromising the SAR ADC performance. Let us first consider the dynamic characteristics of the buffer. Note that the worst-case switching happens when the MSB capacitor transitions from V cm to V re f ,p . This is a smaller constraint in comparison to the conventional switching SAR ADC, where the signal changes from 0 to V re f in a capacitor that is twice as large. On the other hand, the V cm -based switching ADC needs an extra buffer for V cm . The signal needs to settle in half the clock period (T clk /2) because the comparison is done using the falling edge of the clock signal

SR = 2(V re f ,p -V cm ) 0.1T ck = I D 16C u , (5.9)
which yields a current higher than 200 µA. Performing a derivation similar to the one did for equation 4.24, the minimum GBW is given by

GBW min = f ck (N + 3)ln(2) π . (5.10)
Hence, a GBW of at least 688.4 MHz is needed. Regarding the DC characteristics, the circuit has to be designed to attain V re f ,p in its output. Note that since the values of L and W are high to reduce 5.1. Case Study: SAR ADC design the process variability and mismatch, the square current-voltage law of CMOS can be used. Since the current in transistors M 1 and M 2 is the same, the following relationship can be written

1 2 K n W L 1 (V DD -V re f ,p -V T H1 ) 2 [1+λ 1 (V DD -V re f ,p )] = 1 2 K n W L 2 (V b -V T H2 ) 2 (1+λ 2 V re f ,p ),
where K n = µ n C ox and λ is the channel-length modulation parameter. That yields the following design equation: .11) Further developing the analysis, let us point out that the input-referred noise is given by

(W /L) 1 (W /L) 2 = (V b -V T H2 ) 2 (1 + λ 2 V re f ,p ) (V DD -V re f ,p-V T H1 ) 2 [1 + λ 1 (V DD -V re f ,p )] . ( 5
v 2 n,in = γ4k B T g m1 , (5.12)
where g m1 is the transconductance of the input transistor M 1

g m1 = K n W L 1 (V DD -V re f ,p -V T H1 ).
This in turn shows that the large transistors and high currents also increase the transconductance and hence reduces the buffer noise contribution. It can be seen that as g m1 and I D increase the overall performance of the buffer is improved, with the drawback of increasing its power consumption.

Taking into account all the aforementioned design constraints, the three reference buffers of Figure 5.12 are designed. The simulation results for 200 post-layout Monte-Carlo samples are performed, and the results are summarized in Table 5.1. As it can be observed, the results are around the target voltages for the references and common-mode, while the standard deviation is below LSB/2. From Spectre transient simulations it was possible to verify that the DAC voltages were indeed able to settle in the required time. Further validation of this structure will be provided in the following sections when the complete SAR ADC structure is considered.

SAR Logic

The SAR ADC logic is the block responsible for controlling the binary search algorithm. After an external start signal is sent to its inputs, it generates the signals that control the sampling and conversion operations. In the operation of conversion, it should store the outputs of the comparator and generate the right control signal to the switches of the CDAC also based on the comparison results. The SAR logic circuit can be designed in a custom fashion by implementing shift-registers controlled by the output of the comparator, that decides which value will be stored in the DAC register [START_REF] Harpe | A 26µW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios[END_REF]. Another possibility is to use hardware description languages (HDL) to describe the behavior of the digital circuit, and then to use the well-established digital flow techniques and tools [START_REF] Vahid | Digital design with RTL design, VHDL, and Verilog[END_REF] to synthesize the transistor-level and intelligently generate the place-and-route (PnR) of the standard cells. In this work, the logic has to handle not only the SAR ADC binary search in Chapter 5. Case study: design of a SAR ADC with built-in reduced-code static test standard operation but also the test control. That adds complexity to the control system and makes it unpractical to customize the entire digital circuitry in a customized approach. Hence, the digital flow from HDL description to PnR is implemented with the aid of Cadence tools. However, some semi-custom digital blocks are also implemented to complement and post-process some signals generated by the synthesized block. Since the digital control block encompasses the standard operation and the test mode, this is left to be further described in the SAR ADC + BIST co-design later in this chapter.

BIST transistor-level design 5.2.1 Preliminary considerations

In order to validate the BIST design guidelines presented in Chapter 4, this section provides an application example in a practical case study, the V cm -based SCDAC SAR ADC presented in the previous section. A first-order Incremental ADC is then used as the main block in the BIST for the MCT-based reduced-code test of SAR ADCs. The clock frequency of the BIST circuitry was set to f ck = f ck,SAR /8 = 30 MHz to reduce the constraints for the GBW and slew-rate (refer to Figure 4.21b). Taking into consideration the analysis in Chapter 4 [START_REF] Feitoza | Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental Σ∆ Converter[END_REF], a resolution of 8-bits is chosen for the Incremental ADC (i.e. 256 cycles/sample) as a trade-off between test accuracy and design complexity (Figure 4.21a). To further reduce the design effort, the comparator in the BIST is reused from the ADC under test. The reference voltages are also reused from the SAR ADC, V re f ,p = 940 mV and V re f ,n = 340 mV. Since the test clock is considerably slower than the standard conversion clock, the constraints for the on-chip reference buffers and for the clock recovery are less stringent; hence the designs presented in the previous sections are still suited and no modifications are needed. Since the sampling capacitor at the input of the Incremental ADC is replaced by the CDACs of the M × L SAR ADC, this represents one less degree of freedom for the BIST design. The total capacitance at node X in Figure 4.17 is then given by C MT = (2 M-1 -1)C u + C l,eq ≈ 2 M-1 C u . As a design choice, the feedback gain is set to b 2 = 1 V/V, and the feedback and integrating capacitors are set to C sR = C f = 5C u , which gives an equivalent FS range for the Incremental ADC of

FS IADC = C sR C MT 2(V re f ,p -V re f ,n ) = 5C u 2 M-1 C u 2(V re f ,p -V re f ,n ). (5.13)
The design specifications for the integrator, obtained by using the design guidelines discussed in the previous chapter, are summarized in Table 5.2.

OTA design

As it was previously mentioned, the amplifier is the core of the BIST circuitry. The amplifier in the integrator was designed to comply with the specifications in Table 5.2. The selected architecture is based on a fully differential telescopic OTA with a second stage, also fully differential, to increase the total gain, and its schematic is depicted in Figure 5.13. Observe that since one of the main drawbacks of the telescopic OTA is its low output swing, the addition of a fully differential common source as a second stage helps to achieve the high intended gain and it relieves the constraints on the output swing of the first stage. On the other hand, that clearly poses a challenge for the stability of the amplifier, and some scrutiny has to be put on compensation for achieving the intended minimum 45 degrees of phase margin. The output common-modes of the first and second stages are set using a switched-capacitor Common-Mode Feedback (CMFB) circuit [START_REF] Choksi | Analysis of switched-capacitor common-mode feedback circuit[END_REF], and the 5.2. BIST transistor-level design

Output range (mV) ±600

Equivalent input noise minimize schematic of such a circuit is illustrated in Figure 5.14. The two CMFB circuits generate the feedback voltages V f b1 and V f b2 in 5.13, and these voltages regulate the current in order to maintain the correct output common-mode voltage. Due to the fact that the PMOS input pair of the first stage has the tail current source at the top of the schematic, the output common-mode is chosen to be below V DD /2 in order to guarantee that all transistors remain in the saturation region. More specifically, this voltage is chosen to be equal to 450 mV. For the same reason, the second stage has an output common-mode of 640 mV, which is the same value as the input common-mode of the SAR ADC. Both reference common-mode voltages are provided off-chip for simplicity. The bias voltages V cp , V cn , V bn and V bp are generated by an on-chip bias circuitry. Note that the bias voltages for the CMFB circuits in Figure 5.14 are V bn and V bp for the input and second stages, respectively. Because of that fact, the switches S 1 and S 2 are made with NMOS transistors for the input stage CMFB circuit and with PMOS transistors for the second stage CMFB The differential gain of the first stage in Figure 5.13 is given by A v,d ≈ g m1 (g m3 r o3 r o5 ) (g m5 r o5 (r o7 r o8 )),

V cn V cp V bn V fb1 V fb1 V bp V fb2 V fb2 C C C C inp inm outp1 outm1 outp outm V dd V bn V bp MBP M1 M2 M3
where r o = (λ I D ) -1 is the small-signal output resistance of the transistor. The differential gain of the second stage is given by A v,d2 = g m11 (r o,11 (r o,13 r o,14 )).

(5.15)

Like aforementioned, the high gain two-stage amplifier might present stability problems. To achieve the intended phase margin, Miller compensation [START_REF] Razavi | Design of analog CMOS integrated circuits[END_REF] is adopted using capacitor C c in Figure 5.13. Note that the stability of the amplifier also trades with speed, since C c is the capacitance that limits the GBW (∝ g m1 /C c ) and slew-rate (∝ I 1 /C c , where I 1 is the bias drain current in the first stage). All these trade-offs are considered when designing the OTA to attain the minimum specifications that were summarized in Table 5.2. In order to validate the design of the amplifier, transistor-level simulations for the nominal and analog process corners fast-fast (FF), fast-slow (FS), slow-fast (SF), and slow-slow (SS) are run in Virtuoso. The obtained simulation results are summarized in Table 5.3. As it can be seen, all target specifications were met by the proposed design.

Offset cancellation

Another aspect to take into consideration is the input offset of the OTA. Note that when the loop is closed to implement the integrator, such a constant DC voltage would also be integrated together

cmp_bist D Q Q n clk D Q Q n clk D Q Q n clk rst rst D Q Q n clk rst Q 0 Q 1 Q 2 D Q Q n clk Q 7 rst rst rst clk Figure 5
.17: An 8-bit semi-custom digital counter. The output is a binary word corresponding to the number of pulses received at the input. more than one clock cycle, which would prevent the counter from incrementing. The Incremental ADC output should still increment each clock cycle that the signal cmp_bist is high, and the AND operation between these signals achieves this goal.

Assembling the Incremental ADC

Finally, the final schematic of the embedded Incremental ADC used in the BIST is shown in Figure 5.18. The input voltages V X and V A are generated through the CDAC using the modified SAR operation. The switches S int and S int,A are activated in test mode in the integration phase depending if the LSB or MSB CDACs are being measured. The sampling of the feedback voltages V f b,1 and V f b,2 is done through the capacitor C sR . The switches linked to C sR are controlled by the signals S re f ,1 and S re f ,2 . The signal S re f ,1 is also used as the clock for the BIST comparator to make sure the comparison is triggered at the right instant. Note that if the output of the comparator cmp_bist = 0, the block analog multiplexer selects both outputs to be V cm and hence no feedback happens. Once the threshold is crossed, cmp_bist = 1 and the analog MUX outputs are going to be V re f ,p and V re f ,n , yielding the intended feedback. Internally the analog MUX is constructed as shown in Figure 5.19. The control signal at the input is cmp_bist, and when it is equal to zero, the PMOS is on and hence the output is V cm . Since it is the inverted version of cmp_bist that controls the transistors M 3 and M 4 , the NMOS is active and V cm is indeed the output for this stage as well. Observe that cmp_bist = 1 would invert this behavior, yielding at the outputs the goal value of V re f ,p and V re f ,n . It is important to point out that when the inputs of the integrator are inverted, the outputs of the comparator and the analog MUX should also be inverted to guarantee the good operation of the circuit. That explains the switches inv and inv_n at the output of these blocks in Figure 5.18. need some specific signal delays that are not straightforward to implement in an HDL description without increasing the clock frequency (or reducing the sampling frequency of the converter). One good example of such an obstacle is the implementation of the necessary delays for the bottomplate sampling explained in Figure 5.4b. To achieve this behavior, some extra digital blocks are customized to further process the digital signals after they are output from the synthesized digital logic. In that context, Figure 5.21 explains how the sampling and top V cm signals are generated. The pure sampling command smp comes from the digital logic and it is input to the nonoverlapping clocking generator (refer to Figure 5.15). Note that in that case, the output S samp goes low before S cm , and it has to be inverted in order to obtain again signals that are overlapping but with different duty cycles. Finally, a digital multiplexer controlled by tm is added to control the sampling signal: if tm = 0 the sampling signal is passed; on the other hand, for tm = 1 no input has to be sampled, and hence the signal smp should be connected to the ground.

Transistor-Level Results

To validate the feasibility and performance of the proposed on-chip reduced-code test strategy, transistor-level transient simulations of the complete system are performed, including the V cmbased SAR ADC under test with the BIST circuitry. The digital logic controlling the approximation register and the execution of the test procedure has been implemented as explained in the previous section. No degradation of the SAR ADC is observed due to the co-design of the Incremental ADC for test. Dynamic transistor-level simulations yield an ENOB of 9.4 bits for the complete SAR ADC plus test instrument system. To provide a realistic validation of the technique, the mismatch Monte-Carlo models in the PDK of the technology are used to generate samples of the SCDAC SAR ADC under test. These samples are generated and characterized by transistor-level electrical simulations using both the proposed reduced-code test strategy and the standard linear ramp histogram test using a highresolution ramp stimulus with 128 hits-per-code. The obtained results for DNL and INL estimations are shown in Figures 5.22a and 5.22b. For this sample, the effect of capacitor mismatch is less relevant in comparison to the effect of the capacitor parasitics and mismatch of the bridge capacitor. Hence, the parasitics dominate the ADC static linearity response, and the curve resembles Chapter 5. Case study: design of a SAR ADC with built-in reduced-code static test block and the total power consumption for the standard and test modes. The total area of the circuit core is 0.073 mm 2 . Including the MIM decoupling capacitors and the I/O pads, the total area of the chip is 0.96 mm 2 . The power consumption for the standard mode of operation is 500 µW considering the stand-alone SAR without the on-chip clock recovery and reference buffers. Adding both circuits to the power budget, the total power consumption increases to 3.7 mW. The Walden's Figure of Merit (FoM) is given by

FoM = P 2 f in 2 ENOB .
(5.17)

Where P is the total power consumption of the converter. That is a widely used benchmark to assess the power efficiency of an ADC. For the case-study SAR ADC designed in this work, the FoM is equal to 281 fJ per conversion step for the stand-alone SAR ADC, and 2 pJ per conversion step considering the clock-recovery and reference buffers circuits. Note that the goal of this work is not to present a SAR ADC with an optimized state-of-the-art FoM, but to have a realistic case study to validate the proposed test technique. Regarding the test mode operation, the total power consumption is 3.9 mW and 1.15 mW with and without the reference buffers, respectively. This is due to the fact that the external DC bias current for the buffers is not changed for both test and standard modes of operation. Since the constraints on the speed are highly reduced for the test mode, it would be possible to reduce the bias current to limit the total power consumption. However, the ADC characterization runs for a limited amount of time, and hence the power consumption is not that relevant as a constraint. For this particular case study, the test runs for a total time of 460.8 µs, which translates to a total energy of 1.8 µJ.

It is not a straightforward task to provide an accurate estimation for the BIST area overhead. The digital control circuitry encompasses both SAR and test control in a single co-design, where several components like internal registers are reused for both tasks. Still, to provide an overall estimate, let us consider the SAR ADC area as all the blocks used to perform the standard SAR operation, and as BIST overhead just what is used solely for test purpose, not accounting for the circuits that are used for both test and standard operations (buffers, clock recovery, digital control). In that case, the area overhead of the BIST circuitry is around 30 % of the total area of the core. Note however that this might provide an optimistic estimation for the total BIST area overhead. On the other hand, it is important to point out that the SAR ADC area increases exponentially with the converter resolution, while the BIST resolution is not dependent on its area but on the number of cycles it takes to convert one sample, which hints that the interest in such BIST might increase as the SAR ADC resolution increases. This is further backed up by the fact that higher resolution SAR ADCs are more sensitive to mismatch and they intrinsically take longer times to test using standard methodologies. Secondly, the proposed BIST technique and hardware could be easily extended to applications where an array of SAR ADCs are used, such as in imaging applications [START_REF] Leñero-Bardallo | Review of ADCs for imaging[END_REF].

The post-layout extraction of the circuit is performed and the first aspect to point out is that the ENOB of the SAR ADC is highly deteriorated due to the extra parasitics. This happens because, at the schematic level, the only parasitics taken into account are the ones between the top and bottom plates of the capacitors to the substrate. The post-layout extraction takes also into account the extra parasitic capacitances due to the surroundings of the MOM capacitors, which highly increases the total parasitic capacitance. An optimization process is then carried out again by sweeping the value of the bridge capacitor until the parasitics in the LSB partial CDAC are compensated. Basically, this corresponds to assuring the validity of equation 5.3 taking the extra parasitics into consideration. With that in mind, Figure 5.28 shows the signal to noise and distortion ratio (SINAD) of the extracted circuit for an input of 2.5 MHz. The transient simulation is performed including transient noise and the FFT calculation uses 2048 points. This corresponds to an ENOB of 9.8, which shows that the optimization of the bridge capacitor was correctly executed and that the overall operation of the SAR ADC does not present any dynamic issues. Note that Chapter 5. Case study: design of a SAR ADC with built-in reduced-code static test this simulation is performed with the on-chip BIST circuitry loaded to the SAR ADC, which indicates that the co-design of SAR ADC plus BIST does not seem to harm the standard SAR ADC operation. Also, this indicates that the noise added by the buffers based on the source follower configuration does not seem to be critical. Furthermore, Figure 5.29 illustrates a histogram of the Monte-Carlo simulation results for the SAR ADC schematic and layout-level ENOB results. 28 Monte-Carlo samples are taken for each case. The mean ENOBs are 9.23 and 8.95 for schematic and layout levels, respectively. For both cases, the standard deviation of the ENOB is 0.55. The reduced-code static linearity test results in comparison to the standard linear ramp histogram for the post-layout extracted circuit under typical conditions are shown in Figure 5.30. As it can be seen, even though the parasitics are higher, the main aspect that plays a role in the nonlinearity is the relative matching between the bridge capacitor and the total capacitance at the left side. The RMS error of the estimation of the INL is 0.25 LSB when compared to the standard measurement.

Conclusion

This chapter carried out the design of the SAR ADC with the on-chip embedded ADC for reduced static linearity BIST. The design of a case study V cm -based SCDAC SAR ADC was provided with details on the design of its main building blocks. For the SCDAC, the main trade-offs were considered in order to define the capacitance values and the choice of the switches. The stron-gArm latch comparator was also demonstrated, and some details of its design were provided. The auxiliary blocks were also presented, namely the on-chip low-jitter clock recovery circuit and the reference buffers. For the former, the circuit was optimized to make sure that its jitter performance would be enough so the specifications of the converter were respected. For the buffer, the design of a source-follower were detailed in order to guarantee that the reference voltages can be driven to the circuit with enough accuracy and bandwidth. The design of the BIST was also provided. The comparator was reused from the SAR ADC, and the output digital counter was customized using components from the technology standard-cells library. The most challenging part of the BIST is the OTA used in the integrator at the input of the Incremental ADC, and its design was provided. A fully differential telescopic cascode amplifier followed by an also fully differential commonsource amplifier was designed to attain the high gain specifications. The second stage used Miller compensation to assure the stability of the system. The designed amplifier presented performance above the specifications for all the main analog corners. An offset cancellation scheme was implemented in order to guarantee that a good performance could be achieved in the presence of input-referred offsets at the input of the OTA. The digital circuits were also presented, including the synthesized and semi-custom blocks. The post-layout results for the SAR ADC presented an 5.5. Conclusion ENOB of 9.8 bits, with a power consumption of 500 µW and a FoM of 281 fJ per conversion step.

Adding the auxiliary blocks to the power budget increases the power consumption of the converter to 3.7 mW and the Walden's FoM to 2 pJ per conversion step. The BIST circuitry consumes a total energy of 1.8 µJ in a total test time of 461 µs. The total estimated area overhead of the BIST is around 30% of the total surface of the SAR ADC. The relative area overhead is expected to be reduced as the resolution of the SAR ADC is increased. It was demonstrated that the full static linearity of the converter could be measured through the use of the proposed reduced-code test methodology with an RMS error below 1 LSB. For the considered case study, the full static linearity of the converter could be estimated with good accuracy by measuring only 9 of the 1024 codes of the SAR ADC, enabling a test time reduction of 93% in comparison to a 128 hits-per-code standard linear ramp histogram test.

6

Conclusions

This thesis project was carried out as part of the HADES European project in collaboration with STMicroelectronics Crolles. The main goal of this thesis is to develop novel reduced-code BIST techniques for the static linearity test of SAR ADCs. In this chapter, the contributions of this work are summarized, and some thoughts and ideas on the future direction of research on the topic are provided.

Thesis contributions

This work presented novel reduced-code static linearity test techniques for different SAR ADC topologies. The proposed test strategies are based either on the direct measurement of 1) the code width associated with the Major Carrier Transitions of each of the segments of the CDAC/SCDAC of the converter under test, or 2) the partial segmented DACs for SAR ADCs based on a segmented resistor-capacitor topology. The set of voltages to be measured in both cases are directly generated with no need for a test stimulus, which simplifies the practical implementation of the technique. For the MCT-based techniques, it has been shown that the complete static linearity characteristic of an N-bit SC-SAR ADC can be inferred with only N measurements, which yields significant test time reductions in the static characterization of the converter. The technique is also extended for the SCDAC SAR ADC using V cm -based switching algorithm, proving that the technique is also feasible for state-of-the-art SAR ADC architectures.

Practical guidelines for the on-chip implementation of the proposed reduced-code techniques were also provided. In this line, it has been shown that the code width associated with each MCT can be measured with an embedded ADC-based test instrument in a full BIST fashion. First, the feasibility and performance of the proposed reduced-code test techniques have been validated with behavioral simulations for different combinations of resolutions for the SAR ADC and resolution and full-scale for the measurement instrument. It was demonstrated that for each given SAR ADC flavor and specification, an optimal range exists for the BIST measurement instrument.

An incremental ADC is then proposed as a compelling candidate for the implementation of the on-chip BIST test ADC. Some of the features that made the incremental ADC the chosen topology for the implementation of the measurement instrument are the following: 6.2. Perspectives É The incremental ADC is very suitable for the characterization of the DC voltages generated by the modified SAR ADC operation since this Σ∆-based topology does not have idle tones or dead zones for DC measurements.

É This topology presents an intrinsically averaging process, which helps to reduce the nocive effects of noise on the test accuracy. This is very important in the context of our work, where the full-scale of the embedded BIST is translated to the size of the MCT of the partial CDAC.

É Other than the challenges related to the OTA, a first-order incremental ADC is a relatively simple design. The other blocks in the design are 1) a simple counter used as the interpolating filter at the output, and 2) a comparator that can be reused from the SAR ADC under test.

É The possibility of merging the input SCDAC as the sampling capacitor of the integrator at the input of the incremental ADC helps to decrease the total area overhead. Also, the automatic resizing of the FS proves to be a very convenient feature for the SAR ADC characterization, especially for the evaluation of non-symmetric SCDACs.

The design of such a converter in the context of the full BIST characterization of SAR ADCs has been discussed and an efficient implementation that reuses the input SCDAC as the sampling capacitor for the Incremental ADC was proposed. After obtaining the high-level specifications of the on-chip ADC for test, the circuit-level requirements are derived for the design of the blocks related to the Incremental ADC.

After the validation of the technique on a behavioral level, an extensive design effort was performed to design a practical proof-of-concept prototype containing a SAR ADC + BIST. First, a V cm -based switching SC-SAR ADC was designed as a case study. The case study is co-designed with the BIST inputs loaded to each side of the SCDAC. A slight increase in the parasitics is caused by the switches that connect the CDAC to the BIST, but no harm could be observed to the performance of the SAR ADC. Indeed, the bridge capacitor was directly optimized in the codesign process to compensate for the extra capacitance. Subsequently to the case study design, the transistor-level design of the proposed BIST was provided. An offset canceling scheme was implemented to make sure the BIST technique can be correctly carried out. A digital SAR + BIST control was implemented through the complete digital flow from HDL to PnR and integrated into the overall MS design. Transistor-level and post-layout level simulations show the feasibility of the technique. Obtained results show the equivalence of the proposed measurements to standard Linearity Histogram Test methods. INL and DNL estimation errors were contained to an RMS error of less than one LSB, while test time savings are in the order of 93% when compared to a 128-hit-per-code linear ramp histogram test. Note that the estimated area overhead is around 30%. Test time reduction and BIST overhead tend to decrease as the resolution of the SAR ADC increases. Although the area overhead is high for testing a single ADC, it can be pointed out that the BIST circuitry can be shared between different SAR ADCs, which makes this technique very suitable for multi-ADC designs such as pixel arrays in CMOS imagers.

Perspectives

Despite the big challenges posed by the implementation of BIST techniques in the context of AMS design, much progress has been achieved in the last decades. In this work, an accelerated full static linearity characterization of the SAR ADC was achieved without the need for dedicated Chapter 6. Conclusions stimulus generation, which simplifies and helps opening the way for the implementation of BIST techniques.

Still, it seems like a long road is ahead of analog test engineers to allow for full deployment of such techniques in an industrial setting. Because the reduced-code test strategies are very adhoc, small modifications in the SAR ADC topology require alterations in the BIST technique, which increases the challenge of a broad application of reduced-test code BIST for SAR ADCs. Nonetheless, the strategies demonstrated in this work show that relatively small adjustments in the technique allowed for the measurement of different types of SAR ADCs. Indeed, the reduced-code test techniques appear to be a very appealing and flexible solution.

Yet, advancements are still to arise in order to further help to enable such techniques to be widely deployed. Some thoughts regarding the future work that can be conducted in this research topic include but are not limited to: É Further exploration of the proposed reduced-code test techniques regarding the capability for on-chip calibration of SAR ADCs, including SAR ADCs that use redundant techniques for error correction.

É The exploration of inverted-based amplifiers might come as an interesting solution for the implementation of the OTA in the BIST. They might allow for better output swing, speed, and power efficiency in deep-scaled technologies [START_REF] Chatterjee | 0.5-V analog circuit techniques and their application in OTA and filter design[END_REF]. The exploration of inverted-based amplifiers in such context has been already presented in the literature for Σ∆ ADCs [START_REF] Chae | Low voltage, low power, inverter-based switched-capacitor deltasigma modulator[END_REF][START_REF] Michel | mV 7[END_REF][START_REF] Tang | 80dB dynamic range 100KHz bandwidth inverter-based Σ∆ ADC for CMOS image sensor[END_REF] and Incremental ADCs [START_REF] Chae | A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset[END_REF][START_REF] Wang | A 1.8-V 14-bit inverter-based incremental Σ∆ ADC for CMOS image sensor[END_REF][START_REF] Bisiaux | A 14-b twostep inverter-based Σ∆ ADC for CMOS image sensor[END_REF].

É It might be worthwhile to exploit the use of higher-order incremental ADCs for the BIST implementation. This adds design complexity and area overhead, but it might further reduce test time and the constraints on the OTA, which might turn out to be useful in some applications where test time reduction and precision are overly stringent.

É Recent works in the literature apply customized capacitors in the sub-Femto Farad range to achieve ultra-low-power operation [START_REF] Harpe | A 26µW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios[END_REF]. A next step to this work would be to validate the technique for state-of-the-art SAR ADCs.

É In this work, the evaluation of the raw results of the BIST circuitry was processed off-chip. It was not in the scope of this thesis to implement such a digital solution on-chip. However, for a more mature version of the test algorithms implemented in this work, one might benefit from the exploitation and implementation of digital ASIC solutions for the on-chip evaluation of the complete test processing. That may open the door to intelligent computational decision-making for applications such as self-healing circuits, or to digitally-assisted analog design of SAR ADCs with very stringent specifications, to cite a few examples.

1. 1 1 . 2

 112 Diagram of a test setup with an automated test equipment (ATE). . . . . . . . . . 3 Block diagram of a general BIST for on-chip testing. . . . . . . . . . . . . . . . 5 1.3 A plot of the energy efficiency versus the SNDR for different ADC topologies pub-

7 2 . 1

 21 Conceptual block diagram of an N-bit SAR ADC. . . . . . . . . . . . . . . . . . 11 2.2 Example of a 4-bit binary search operation. The input is captured using an S/H input and a DAC is used for generating the comparison analog voltage. . . . . . . 12 2.3 Switching of the conventional capacitive SAR ADC. . . . . . . . . . . . . . . . 13 2.4 Schematic of a split-capacitor SAR ADC. . . . . . . . . . . . . . . . . . . . . . 14 2.5 Equivalent circuits for the SCDAC, a) MSB partial CDAC is switching and b) LSB partial CDAC is switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 Example of a transfer characteristic for an ADC which has an offset of 1 LSB. . . 16 2.7 Example of a transfer characteristic for an ADC with a gain error. . . . . . . . . 16 2.8 Differential non-linearity of an ADC. . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 Simplified model used to calculate CDAC voltage and energy a) two references and b) three references. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 SAR ADC conventional switching with the energy associated to each transition. . 20 2.11 Top-plate voltage of the conventional switching SAR ADC. The differential input

3. 1

 1 Servo-loop test and its two different implementations a) digital and b) analog. . . 3.2 Histograms of input stimuli for an ideal ADC output a) linear ramp and b) sinusoidal input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Transfer function for an example 4-bit SAR ADC. These plots are for an ideal ADC and for an ADC whose MSB-1 capacitor is 50% larger than its ideal value. 3.4 Conceptual block diagram of a segmented DAC. . . . . . . . . . . . . . . . . . . 3.5 Conceptual schematic of the SAR ADC testing technique. . . . . . . . . . . . . 3.6 Flow of the proposed conventional switching SAR ADC testing. . . . . . . . . . 3.7 Illustration of the modified SAR operation for generation of the MCT voltages. . 3.8 Conceptual schematic of the SCDAC SAR ADC testing technique. . . . . . . . . 3.9 The modified SAR ADC operation for the SCDAC a) schematic and b) example of MCT code length voltage generation algorithm for i = 2. . . . . . . . . . . . . 3.10 V cm -based Switching SAR ADC a) schematic and b) example of MCT code length voltage generation algorithm for i = 2. . . . . . . . . . . . . . . . . . . . . . . . 3.11 Behavioral simulation comparing conventional switching and V cm -based switching CDACs. As can be observed, the DNL is split between two codes, with half the magnitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Conceptual schematic of the segmented DAC SAR ADC. . . . . . . . . . . . . 4.1 Conceptual block diagram of the proposed embedded reduced-code linearity test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Conceptual block diagram of an Incremental ADC. . . . . . . . . . . . . . . . . 4.3 Conceptual schematics of the three different SAR topologies studied in this chapter based on its DAC topology: a) binary-weighted capacitive DAC, b) splitcapacitor DAC and c) segmented DAC. . . . . . . . . . . . . . . . . . . . . . . 4.4 INL measurement error as a function of FS IADC (σ = 0.3 %) for a) different conventional SAR ADC resolutions (R = 10) and b) different resolutions of the Incremental ADC (N = 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Integrator outputs for extreme values of FS a) FS << 1 and b) FS ≈ 1. . . . . . 4.6 Percentage of test time saved in comparison to 128 hits per code linear ramp histogram for different conventional CDAC SAR ADC and Incremental ADC resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 INL measurement error as a function of FS MSB IADC (σ = 0.1 %) for a) different SC-DAC SAR ADC resolutions (R = 8) and b) different resolutions of the Incremental ADC (N = 10, (6 × 4) ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Percentage of test time saved in comparison to 128 hits per code linear ramp histogram for different SCDAC SAR ADC and Incremental ADC resolutions. . . . . 4.9 INL error as a function of the capacitor mismatch standard deviation. 200 iterations for each value of σ , R = 9, M = 6, L = 4. . . . . . . . . . . . . . . . . . . 4.10 Test time savings comparison of different 10-bit SAR ADC topologies with the 128 hits-per-code linear ramp histogram (10-bit Incremental ADC for MCT-based test and 14/10-bit Incremental ADC for segmented-based test). . . . . . . . . . . vii List of Figures 4.11 INL results for histogram and reduced-code test for the three considered SAR ADC architectures: a) binary-weighted capacitive DAC, b) split-capacitor DAC and c) segmented DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 INL estimation error results for histogram and reduced-code test for the three considered SAR ADC architectures: a) binary-weighted capacitive DAC, b) splitcapacitor DAC and c) segmented DAC. . . . . . . . . . . . . . . . . . . . . . . 4.13 INL estimation error results as a function of the resolution of the embedded Incremental ADC for the three considered SAR ADC architectures: a) binary-weighted and split-capacitor DACs and b) segmented DAC (R LSB = 10 bits). . . . . . . . . 4.14 Conceptual block diagram of the switched-capacitor integrator. . . . . . . . . . . 4.15 Conceptual schematic of the Incremental ADC merged with the SCDAC of the SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Conceptual operation of merging between CDAC and Incremental ADC: first, MTC step length V i is generated. Then, charge in C out,k is transferred to C f via S k , integrating V i with gain b k . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Schematic of the SCDAC SAR ADC including the effects of the parasitic capacitors. C p,M represents all the parasitic capacitors connected to node X, C p,L represents all the parasitics capacitors connected to node A, and C p,B represents the parasitics between the top metal plate of the bridge capacitor and the other top plates of the capacitors in the CDAC arrays. . . . . . . . . . . . . . . . . . . . . 4.18 Behavioral level simulations for the linear ramp histogram and reduced-code test with parasitic detection for a 10-bit V cm -based SCDAC SAR ADC whose errors are solely caused by parasitics, a) DNL and b) INL. . . . . . . . . . . . . . . . . 4.19 Behavioral level simulations for the linear ramp histogram and reduced-code test with parasitic detection for a 10-bit V cm -based SCDAC SAR ADC whose errors are caused by parasitics and mismatch, a) DNL and b) INL. . . . . . . . . . . . . 4.20 General model of a feedback amplifier used for estimating the OTA minimum gain. 4.21 OTA specifications definitions, a) minimum gain and b) minimum values of GBW and slew-rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Schematic of the designed V cm -based SCDAC SAR ADC. The BIST inputs and outputs are neglected for clarity. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Comparison between different switch resistances for different implementations. . 5.3 Different implementations of CMOS switches. a) Transmission gate and b) the simple PMOS switch for voltages closer to V DD and NMOS for voltages closer to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Different implementations of a sampling circuit, a) charge injection on a topsampling configuration and b) bottom-plate sampling configuration, where the switch S cm closes slightly before S in to avoid input dependent charge injection. . . 5.5 Schematic of the StrongArm latch. No static power is consumed in standby mode, and only dynamic currents are present during regeneration. . . . . . . . . . . . . 5.6 Large signal transient level simulation of the StrongArm comparator. When clock signal is down, all voltages are preset to V DD . After the clock signal goes high, both differential outputs go towards zero, until one of the outputs is regenerated to V DD while the other is discharged towards ground. . . . . . . . . . . . . . . . . 5.7 RS latch at the output of the strongArm to isolate the output from the internal transient voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Conceptual diagram of the low-jitter on-chip clock recovery circuit. . . . . . . . 5.9 Schematic of the low-jitter clock recovery circuit, the differential stage with active load and positive feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures 5.10 200 sample Monte Carlo simulation results for process corner variations in ST 65nm DK. The clock jitter has a value of 5.1 ps and a standard deviation of 540 fs. 5.11 Block diagram of the on-chip buffer for driving the medium to high-speed ADC. 5.12 Schematic of the source-follower/level-shifter for on-chip reference. . . . . . . . 5.13 Transistor-level schematic of the two-stage fully differential telescopic cascode plus common-source operational transconductance amplifier. . . . . . . . . . . . 5.14 Switched-capacitor common-mode feedback circuit. . . . . . . . . . . . . . . . . 5.15 Non-overlapping circuit generator. A clock signal is input and the outputs have a phase difference of 180 degrees and they do not overlap. . . . . . . . . . . . . . 5.16 Offset cancellation scheme by inverting the inputs. After 2 R steps the polarity of the signal inv is flipped. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 An 8-bit semi-custom digital counter. The output is a binary word corresponding to the number of pulses received at the input. . . . . . . . . . . . . . . . . . . . 5.18 Circuit-level schematic of the embedded Incremental ADC for test. . . . . . . . . 5.19 Schematic of the analog multiplexer used to choose the feedback voltages V f b,1 and V f b,2 . When the input ctrl is zero, both outputs go to V cm , else the outputs are V re f ,p and V re f ,n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 Digital control block illustrating its inputs and output signals. This block only takes four inputs and generate most of the signals needed for controlling both standard operation and reduced-code test of the SAR ADC. Some signals need extra processing to achieve the needed delays. . . . . . . . . . . . . . . . . . . . 5.21 Semi-custom digital control to post-process the signal smp from the synthesized digital block. This circuit guarantees the right delays for bottom-sampling when in standard operation mode, and it also outputs the correct values of the sampling and common-mode control signal for both operation modes. . . . . . . . . . . . 5.22 Static linearity test results comparing the standard linear histogram test and the proposed V cm -based reduced test technique for a representative Monte-Carlo sample, a) DNL and b) INL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23 Error results comparing the static nonlinearities of the standard linear histogram test and the proposed V cm -based reduced test technique a) DNL error and b) INL error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.24 Error distribution results comparing the measured INLs using the standard linear histogram test and the proposed V cm -based reduced test technique. . . . . . . . . 5.25 Static linearity test results comparing the standard linear histogram test and the proposed V cm -based reduced test technique for a sample whose MSB capacitor was artificially increased by C u /8, a) DNL and b) INL. . . . . . . . . . . . . . . 5.26 Floorplan of the complete SAR ADC with on-chip embedded Incremental ADC for reduced-code static linearity test. . . . . . . . . . . . . . . . . . . . . . . . . 5.27 Layout of the complete SAR ADC with on-chip embedded Incremental ADC for reduced-code static linearity test. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.28 FFT of the output for the post-layout simulations of the SAR ADC with transient noise for a 2.4 MHz input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.29 ENOB distribution results for the schematic and layout-level Monte-Carlo simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.30 Static linearity test results comparing the standard linear histogram test and the proposed V cm -based reduced test technique for the extracted post-layout SAR ADC + BIST, a) DNL and b) INL. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 1 . 1 :

 11 Figure 1.1: Diagram of a test setup with an automated test equipment (ATE).

1. 3 .Figure 1 . 2 :

 312 Figure 1.2: Block diagram of a general BIST for on-chip testing.

Contents 2 . 1

 21 SAR ADC basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Split-DAC SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Static Error Sources in SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . 2.4 SAR ADC switching schemes . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Models for voltage and energy in SAR ADCs . . . . . . . . . . . . . . 2.4.2 Switching algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Summary and comparison between switching schemes . . . . . . . . . 2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2 . 1 :

 21 Figure 2.1: Conceptual block diagram of an N-bit SAR ADC.

Figure 2 . 2 :

 22 Figure 2.2: Example of a 4-bit binary search operation. The input is captured using an S/H input and a DAC is used for generating the comparison analog voltage.

Figure 2 . 3 :

 23 Figure 2.3: Switching of the conventional capacitive SAR ADC.

Figure 2 . 4 :

 24 Figure 2.4: Schematic of a split-capacitor SAR ADC.

Figure 2 . 6 :

 26 Figure 2.6: Example of a transfer characteristic for an ADC which has an offset of 1 LSB.

Figure 2 . 7 :

 27 Figure 2.7: Example of a transfer characteristic for an ADC with a gain error.

Figure 2 . 8 :

 28 Figure 2.8: Differential non-linearity of an ADC.

Figure 2 . 9 :

 29 Figure 2.9: Simplified model used to calculate CDAC voltage and energy a) two references and b) three references.

Figure 2 . 10 :Figure 2 . 11 :

 210211 Figure 2.10: SAR ADC conventional switching with the energy associated to each transition.

Smp # 1 Figure 2 . 13 :

 1213 Figure 2.13: Top-plate voltage of the set-and-down switching SAR ADC. The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f p = 900 mV and V re f n = 300 mV. The output code is 0000101010 as it is explicit on the figure for each decision step. The common-mode voltage converges to V re f n .

Figure 2 .Figure 2 . 15 :

 2215 Figure 2.14: SAR ADC V cm -based switching with top plate sampling. The energy in each transition is smaller in comparison to the previous shown algorithms.

Figure 2 .

 2 Figure 2.16: SAR ADC V cm -based switching with bottom plate sampling.

Chapter 2 .Figure 2 . 17 :

 2217 Figure2.17: Top-plate voltage of the V cm -based switching SAR ADC. The differential input is -550 mV, which corresponds to V in,p = 325 mV and V in,n = 875 mV. The reference voltages are V re f ,p = 900 mV and V re f ,p = 300 mV, with V cm = 600 mV. The output code is 0000101010 as it is explicit on the figure for each decision step.

Figure 2 . 18 :

 218 Figure 2.18: Energy consumption of the SAR ADC for each of the considered switching algorithms a) normalized energy and b) percentage of energy saving.

Contents 3 . 1

 31 Standard test methods for static linearity test . . . . . . . . . . . . . . . . .3.1.1 Servo Loop Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Histogram Method . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3. 2

 2 Advanced linearity test techniques . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 State-of-the-art on BIST and DfT for static test of ADCs . . . . . . . . 3.2.2 MCT-based reduced-code static test techniques . . . . . . . . . . . . . 3.2.3 Segmented-based reduced-code static test techniques . . . . . . . . . . 3.3 Reduced-code test techniques for SAR ADCs . . . . . . . . . . . . . . . . . 3.3.1 Conventional SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . Chapter 3. Reduced-code SAR ADC static linearity test 3.3.2 Split-CDAC SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Application to V cm -based switching SAR ADCs . . . . . . . . . . . . . 3.3.4 Application to segmented DAC SAR ADCs . . . . . . . . . . . . . . . 3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 .

 3 Reduced-code SAR ADC static linearity test Digital Method (optional voltmeter). (b) Analog Method (required voltmeter).

Figure 3 . 1 :

 31 Figure 3.1: Servo-loop test and its two different implementations a) digital and b) analog.

3. 2 .Figure 3 . 2 :

 232 Figure 3.2: Histograms of input stimuli for an ideal ADC output a) linear ramp and b) sinusoidal input.

3. 2 .

 2 Advanced linearity test techniques

Figure 3 . 4 :

 34 Figure 3.4: Conceptual block diagram of a segmented DAC.

Figure 3 . 5 :

 35 Figure 3.5: Conceptual schematic of the SAR ADC testing technique.

Figure 3 . 6 :

 36 Figure 3.6: Flow of the proposed conventional switching SAR ADC testing.

3. 3 .

 3 Reduced-code test techniques for SAR ADCs the INL is given by

PostFigure 3 . 8 :Figure 3 . 9 :

 3839 Figure 3.8: Conceptual schematic of the SCDAC SAR ADC testing technique.

5 )

 5 for each individual partial CDAC, an array containing the normalized weights of the LSB segment is obtained, namely ŴLSB = [ Ŵ 0 LSB , ..., Ŵ L-1 LSB ], and another consisting of the relative normalized weights of the MSB segment, that is Ŵ MSB = [ Ŵ 0 MSB , ..., Ŵ M-1 MSB ]. Considering the weight scaling between the two CDAC segments, the normalized weights of the MSB segment are given by ŴMSB = 2 L Ŵ MSB . (3.15) After that step, the two matrices ŴMSB and ŴLSB are concatenated, giving as a result the normalized weights matrix of the full SC-SAR ADC Ŵ = [ Ŵ0 , ..., ŴN-1 ]. Finally, the normalized weights can be converted to the actual voltage weights

Figure 3 .

 3 Figure 3.10: V cm -based Switching SAR ADC a) schematic and b) example of MCT code length voltage generation algorithm for i = 2.

Figure 3 . 11 :

 311 Figure 3.11: Behavioral simulation comparing conventional switching and V cm -based switching CDACs. As can be observed, the DNL is split between two codes, with half the magnitude.

Figure 3 . 12 :

 312 Figure 3.12: Conceptual schematic of the segmented DAC SAR ADC.

Contents 4 . 1

 41 Practical on-chip implementation . . . . . . . . . . . . . . . . . . . . . . . 52 4.2 The Incremental ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 Implementation for different SAR ADC architectures . . . . . . . . . . . . 54 4.3.1 MCT-based testing: Conventional SAR ADC . . . . . . . . . . . . . . 54 4.3.2 MCT-based testing: SCDAC SAR ADC . . . . . . . . . . . . . . . . . 57 4.3.3 Split-capacitor V cm -based SAR ADC . . . . . . . . . . . . . . . . . . . 59 4.3.4 Segmented SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.5 System-level simulation results . . . . . . . . . . . . . . . . . . . . . 60 4.4 Co-integration of SAR ADC and BIST circuitry . . . . . . . . . . . . . . . 61 4.5 Guidelines for the design of the embedded Incremental ADC for test . . . . 68 4.6 Some comments on the testing of the Incremental ADC . . . . . . . . . . . 71 4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 4 . 1 :

 41 Figure 4.1: Conceptual block diagram of the proposed embedded reduced-code linearity test setup.

Figure 4 .Figure 4 . 2 :

 442 Figure 4.2 shows a conceptual block diagram of a first-order Incremental ADC, also known as Incremental Σ∆ ADC. The operation of the Incremental ADC differs from a Σ∆ in which both

Figure 4 . 3 :

 43 Figure 4.3: Conceptual schematics of the three different SAR topologies studied in this chapter based on its DAC topology: a) binary-weighted capacitive DAC, b) split-capacitor DAC and c) segmented DAC.

4. 3 .Figure 4 . 4 :

 344 Figure 4.4: INL measurement error as a function of FS IADC (σ = 0.3 %) for a) different conventional SAR ADC resolutions (R = 10) and b) different resolutions of the Incremental ADC (N = 10).

Figure 4 .Figure 4 . 5 :

 445 Figure 4.5: Integrator outputs for extreme values of FS a) FS << 1 and b) FS ≈ 1.

Figure 4 . 6 :

 46 Figure 4.6: Percentage of test time saved in comparison to 128 hits per code linear ramp histogram for different conventional CDAC SAR ADC and Incremental ADC resolutions.

Figure 4 . 7 :

 47 Figure 4.7: INL measurement error as a function of FS MSB IADC (σ = 0.1 %) for a) different SCDAC SAR ADC resolutions (R = 8) and b) different resolutions of the Incremental ADC (N = 10, (6 × 4) ).

Figure 4 . 8 :

 48 Figure 4.8: Percentage of test time saved in comparison to 128 hits per code linear ramp histogram for different SCDAC SAR ADC and Incremental ADC resolutions.

Figure 4 . 9 :

 49 Figure 4.9: INL error as a function of the capacitor mismatch standard deviation. 200 iterations for each value of σ , R = 9, M = 6, L = 4.

Figure 4 .Figure 4 . 10 :

 4410 Figure 4.10: Test time savings comparison of different 10-bit SAR ADC topologies with the 128 hits-per-code linear ramp histogram (10-bit Incremental ADC for MCT-based test and 14/10-bit Incremental ADC for segmented-based test).

Chapter 4 .Figure 4 . 11 :

 4411 Figure 4.11: INL results for histogram and reduced-code test for the three considered SAR ADC architectures: a) binary-weighted capacitive DAC, b) split-capacitor DAC and c) segmented DAC.

ure 4 . 2 ,Figure 4 . 13 : 1 Figure 4 . 14 :

 424131414 Figure 4.13: INL estimation error results as a function of the resolution of the embedded Incremental ADC for the three considered SAR ADC architectures: a) binary-weighted and split-capacitor DACs and b) segmented DAC (R LSB = 10 bits).

Figure 4 . 15 :

 415 Figure 4.15: Conceptual schematic of the Incremental ADC merged with the SCDAC of the SAR ADC.

Figure 4 . 16 :

 416 Figure 4.16: Conceptual operation of merging between CDAC and Incremental ADC: first, MTC step length V i is generated. Then, charge in C out,k is transferred to C f via S k , integrating V i with gain b k .

4. 5 .

 5 Guidelines for the design of the embedded Incremental ADC for test

Figure 4 . 18 :

 418 Figure 4.18: Behavioral level simulations for the linear ramp histogram and reduced-code test with parasitic detection for a 10-bit V cm -based SCDAC SAR ADC whose errors are solely caused by parasitics, a) DNL and b) INL.

Figure 4 . 19 :

 419 Figure 4.19: Behavioral level simulations for the linear ramp histogram and reduced-code test with parasitic detection for a 10-bit V cm -based SCDAC SAR ADC whose errors are caused by parasitics and mismatch, a) DNL and b) INL.

A

Figure 4 . 20 :

 420 Figure 4.20: General model of a feedback amplifier used for estimating the OTA minimum gain.

Figure 4 . 21 :

 421 Figure 4.21: OTA specifications definitions, a) minimum gain and b) minimum values of GBW and slew-rate.

Chapter 4 .

 4 Practical SAR ADC BIST Implementation

Contents 5 . 1

 51 Case Study: SAR ADC design . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.1 CDAC design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.2 Comparator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1.3 Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.1.4 Reference Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1.5 SAR Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 BIST transistor-level design . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.2.1 Preliminary considerations . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 5 . 2 :Figure 5 . 3 :Figure 5 . 4 :

 525354 Figure 5.2: Comparison between different switch resistances for different implementations.

5. 1 .Figure 5 . 6 :Figure 5

 1565 Figure 5.6: Large signal transient level simulation of the StrongArm comparator. When clock signal is down, all voltages are preset to V DD . After the clock signal goes high, both differential outputs go towards zero, until one of the outputs is regenerated to V DD while the other is discharged towards ground.

Chapter 5 .Figure 5 . 8 :

 558 Figure 5.8: Conceptual diagram of the low-jitter on-chip clock recovery circuit.

5. 1 .Figure 5 . 9 :

 159 Figure 5.9: Schematic of the low-jitter clock recovery circuit, the differential stage with active load and positive feedback.

Figure 5 .

 5 Figure 5.10: 200 sample Monte Carlo simulation results for process corner variations in ST 65nm DK. The clock jitter has a value of 5.1 ps and a standard deviation of 540 fs.

Figure 5 . 11 :

 511 Figure 5.11: Block diagram of the on-chip buffer for driving the medium to high-speed ADC.

Figure 5 . 12 :

 512 Figure 5.12: Schematic of the source-follower/level-shifter for on-chip reference.

Figure 5 . 13 :

 513 Figure 5.13: Transistor-level schematic of the two-stage fully differential telescopic cascode plus common-source operational transconductance amplifier.

Chapter 5 .Figure 5 . 16 :

 5516 Figure 5.16: Offset cancellation scheme by inverting the inputs. After 2 R steps the polarity of the signal inv is flipped.

Figure 5 . 18 :Figure 5 . 20 :

 518520 Figure 5.18: Circuit-level schematic of the embedded Incremental ADC for test.

Figure 5 . 22 :Figure 5 . 25 :

 522525 Figure 5.22: Static linearity test results comparing the standard linear histogram test and the proposed V cm -based reduced test technique for a representative Monte-Carlo sample, a) DNL and b) INL.

Figure 5 . 26 :

 526 Figure 5.26: Floorplan of the complete SAR ADC with on-chip embedded Incremental ADC for reduced-code static linearity test.

Figure 5 . 27 :

 527 Figure 5.27: Layout of the complete SAR ADC with on-chip embedded Incremental ADC for reduced-code static linearity test.

Figure 5 . 28 :

 528 Figure 5.28: FFT of the output for the post-layout simulations of the SAR ADC with transient noise for a 2.4 MHz input.

Figure 5 . 29 :Figure 5 . 30 :

 529530 Figure 5.29: ENOB distribution results for the schematic and layout-level Monte-Carlo simulations.

V in Output Code Ideal ADC Real ADC DNL=1.5LSB DNL=0.5LSB

  where V tl,i represents the i-th transition level voltage of the DAC/ADC

							2.4. SAR ADC switching schemes
	111
	110
	101
	100
	011
	010
	001
	000
	0	1	2	3	4	5	6	7

Table 2 . 1 :

 21 Summary of SAR ADC switching schemes

					Common-mode Sens to comparator offset Total Cap	Sampling	Energy
	Conventional		Constant			Low				1×		Bottom-plate	100%
	Set-and-down		Varying			High				0.5×		Top-plate	18%
		MCS			Constant			Low				0.5×		Top-plate	12%
	V cm -based			Constant			Low				0.5×		Bottom-plate	12%
		10 6
	)				E conv
	Normalized Energy (C u 2 V ref	10 0 10 2 10 4			E V cm E set-and-down E MCS					8 10 12 14 16
		10 -2	0	2	4	6	8	10	12	14	6	2	4	6	8	10	12	14
						ADC resolution						ADC resolution

Table 3 .

 3

			1: MCT Transitions for a 4-bit converter
	T 0		T 1		T 2		T 3
	Init State Final State Init State Final State Init State Final State Init State Final State
	0000	0001	0001	0010	0011	0100	0111	1000
	0010	0011	0101	0110	1011	1100	X	X
	0100	0101	1001	1010	X	X	X	X
	0110	0111	1101	1110	X	X	X	X

Chapter 3. Reduced-code SAR ADC static linearity test Post C N-1

Generate V i (Modified SAR operation) Measure V i and Λ i Estimate W i i=N-1 ? i++ Map N codes to the full characteristic and calculate DNL Calculate INL and elimination of quantization errors

  3.3. Reduced-code test techniques for SAR ADCs

	Start (i=0)

  is used in this work. Because this configuration is very fast and it presents no static consumption, it highly Chapter 5. Case study: design of a SAR ADC with built-in reduced-code static test Figure 5.5: Schematic of the StrongArm latch. No static power is consumed in standby mode, and only dynamic currents are present during regeneration.

				V DD
	CLK	M 5	M 6		CLK
	S 1	S 3	V out,n	V out,p	S 4	S 2
		M 3		M 4
			P	Q
		V in,p	M 1	M 2	V in,n
		CLK	M 7

Table 5 . 1 :

 51 Reference buffer simulation results

		Mean	Standard Deviation
	V re f ,p 940.1 mV	383 µV
	V re f ,n	340 mV	410 µV
	V cm	639.8 mV	650 µV

Table 5 .

 5 2: OTA Integrator Specifications

	Incremental ADC resolution R	8
	f ck,OTA (MHz)	30
	A 0min,dB	65
	GBW (MHz)	63
	SR (V/µs)	343
	PM (degrees)	>

  Figure 5.15: Non-overlapping circuit generator. A clock signal is input and the outputs have a phase difference of 180 degrees and they do not overlap.circuit. The signals that control S 1 and S 2 are generated by the digital control circuit. They need to be non-overlapping while in test mode, hence, a signal S 1 is generated by the digital control, and a non-overlapping clock (NOC) circuit generator is used for generating signals S 1 and S 2 . The NOC generator is a circuit used to derive a two-phase clock signal from a single clock signal. The schematic of the NOC implementation is illustrated in Figure5.15. The outputs S 1 and S 2 have a phase of 180 degrees and the circuit guarantees that the high signal has completely settled to zero before allowing the low signal to go high.

	V cm,ref	S 1	S 2	out,p	out,m	S 2	S 1	V cm,ref
			C 2	C 1	C 1		C 2
		S 1	S 2			S 2	S 1
	V bias							V bias
					V fb
		Figure 5.14: Switched-capacitor common-mode feedback circuit.
								S 1
	CLK
								S 2

Table 5 .

 5 5: Total area and power consumption per blockArea (µm 2 ) SAR ADC operation power (µW ) Test-mode power (µW )

	CDAC	160 × 51	14.5	0.7
	Comparator	11 × 22	73.85	12
	OTA + Bias	119 × 82	X	650
	Digital	91 × 180	412.4	135
	Buffers	55 × 64	2740	2740
	Clock recovery	48 × 60	453.5	370

"Strategies for Reduced-code Static Testing of SAR ADCs" Résumé La

  mesure des performances de linéarité statique est l'une des tâches clés dans le test d'un convertisseur analogique-numérique (CAN). Normalement, les paramètres de linéarité statique sont mesurés pendant la phase de production, et les méthodologies standard dans l'industrie exigent l'extraction d'une grande quantité de données puisque chaque code doit être mesuré plusieurs fois pour faire la moyenne de l'effet du bruit. Les techniques à nombre réduit de codes pour le test de linéarité statique des CANs ont le potentiel de réduire considérablement le nombre de mesures nécessaires pour une caractérisation complète. Ces techniques exploitent le fonctionnement répétitif dans certaines familles de convertisseurs comme les pipelines, les registres à approximation successive (SAR), les cycliques, etc. Dans cette thèse, des nouvelles techniques à nombre réduit de codes pour le test de linéarité statique des ADCs SAR sont présentées. Elles sont basées sur la génération et la mesure sur puce des transitions du convertisseur numérique-analogique (CNA) interne du CAN. Cela permet de déduire la fonction de transfert complète du CAN en ne mesurant qu'un sous-ensemble soigneusement sélectionné de l'ensemble des codes, ce qui réduit considérablement le temps de test global. De plus, la simplification inhérente des tests de linéarité statique fournie par les techniques à nombre réduit de codes peut ouvrir la porte à une mise en oeuvre complète de l'auto-test intégré (BIST). De cette façon, les exigences du testeur peuvent être relâchées et le coût du test peut être davantage contenu en déplaçant les ressources du test de linéarité statique vers le dispositif testé lui-même. La méthodologie de test proposée ne nécessite pas de stimulus de test, et il est démontré que les mesures nécessaires peuvent être facilement extraites en reconfigurant des parties du SAR en un convertisseur incrémental à faible résolution.

Mots-clés : CAN à approximations successives, convertisseurs

analogiques-numériques, test de linéarité statique, test de linéarité à nombre réduit de codes, auto-test intégré, conception pour le test.

Of course this assumption is not valid for time-interleaved SAR ADC topologies

Further discussion on charge injection and bottom/top-plate sampling will be given in Chapter 5.

X X X X X X 1010 1011 X X X X X X 1100 1101 X X X X X X 1110 1111 X X X X X XThe conceptual block diagram of the proposed built-in test setup is shown in Figure3.5. The DAC array is connected to the test instrument, which here is conceptually depicted as a voltmeter. Then it is followed by a digital post-processing circuit that performs the calculations needed in order to obtain the full static characteristic of the SAR ADC. The testing algorithm can be summarized in the following steps:

The memory feature of a Σ∆ operation is eliminated due to the reset operation at the beginning of each cycle, and hence the Incremental ADC is actually classified in the Nyquist family of converters. This is why in this work it is preferred to use the nomenclature of Incremental ADC instead of Incremental Σ∆ ADC, to avoid misleading the reader. However, both designations can be found in the current literature.

In order to obtain a more realistic signal, the ideal square signal is fed to a first-order lowpass filter used to emulate the effect of the pads.

Note that semi-custom accounts for the fact that the circuit is customized almost from scratch, but the technology standard cells are used as the blocks for the customized design. A full-custom design would also include the utilization of customized digital cells.

Acknowledgements

Acknowledgements

aspects of it. Thanks also to Daniel Dzahini from X-digit

It is also important to point out that independently of the instrument used to measure the MCT code lengths in figure 3.5, a quantization error δ will necessarily be introduced. Since the MCT code lengths are of the order of one LSB of the ADC under test, this is not very critical for the DNL measurement. However, since the INL is calculated as an integration of the DNL, this accumulated error becomes critical for the INL. Fortunately, this translates to a linear error that can be easily removed. Suppose the measured DNL k is equal to DNL k -δ , where DNL k is the true DNL. Hence,

List of Tables

Test Logic

8C u cmp=1

(d) Second step of modified SAR operation, case cmp=1. phase. In the case where there are missing codes, the mapping of the N measured codes to the full 2 N codes of the converter is slightly modified to take into account the value of Λ i . then given by

Then, when switches S 1 and S 2 are opened and closed (t = (n+1/2)T ck ), respectively, the capacitor C s is grounded in both plates, and its charge is transferred to the feedback capacitor C f . Due to with the MCT voltages and hence potentially cause large measurement errors at the output of the Incremental ADC. Known techniques such as chopper and auto-zeroing can be used [START_REF] Enz | Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization[END_REF]. To avoid adding much area overhead and complexity, this work proposes to implement an inversion of the inputs of the integrator to eliminate the effects of the input-referred offset. The scheme proposed in this work is illustrated in Figure 5.16. First, the signal inv = 0 and the input is integrated for 2 R cycles. Subsequently, the signal inv goes high, the inputs of the integrator are inverted, and the integration process is performed again for 2 R cycles. By reasoning in a similar way to the derivation of equation 4.3, but including the input voltage offset V os and the differential operation of the system, it can be shown that the representation of the code length of the i-th MCT in LSB for the non-inverted integration is given by

SAR Logic

which can cause high errors if the offset is not negligible in comparison to one LSB. However, the inverted integration yields

Hence, the actual length of the i-th MCT is given by

Hence, by acquiring the number of counts from direct integration N out,1 and the inverted number of counts N out,inv through the output digital counter, the correct value of the code width can be retrieved. The main drawback of this technique is the need for a twofold test time to preserve the same resolution R.

Dedicated digital counter

Since the counter is a relatively simple design, it was decided to implement it in a customized fashion. The schematic of an 8-bit semi-custom 2 digital counter is illustrated in Figure 5.17. The output is a binary word corresponding to the number of pulses received at the input. Note that the signal rst that is responsible for resetting the Incremental ADC is also connected to the reset input of the flip-flops, pushing all the outputs to zero when the Incremental ADC is reset. The clock input of the first D flip-flop is connected to the output of an AND operation between the clock input and the signal cmp_bist. This is because the signal cmp_bist may remain equal to 1 for

.19: Schematic of the analog multiplexer used to choose the feedback voltages V f b,1 and V f b,2 . When the input ctrl is zero, both outputs go to V cm , else the outputs are V re f ,p and V re f ,n .

Co-design SAR ADC + embedded test circuitry

SAR + Test logic

The block SAR + Test control logic is depicted in Figure 5.20. It has only four inputs, namely the clock generated by the on-chip clock recovery circuit clk, the output of the SAR ADC comparator cmp, an external signal called tm which is responsible for indicating to the control circuit if the ADC is in standard conversion mode (tm = 0) or test mode (tm = 1), and a not reset RST signal which tells the system to operate or go to standby mode (RST = 0). Table 5.4 summarizes each of the outputs of the control circuit and what function they have in each operation mode. This table together with state-machine theory [START_REF] Vahid | Digital design with RTL design, VHDL, and Verilog[END_REF] is applied for writing the HDL description of the digital control circuit in Verilog. The Verilog HDL is then synthesized into gate-level Verilog with the aid of the software Cadence Genus®, yielding a total number of 410 standard cells for the complete control block. Subsequently, the PnR of the standard cells is performed with the aid of the Cadence Innovus® tool. The complete digital flow and the details of the complete digital implementation are omitted for the sake of brevity. the behavioral-level simulations with parasitics only in Figure 4.18. It is important to notice that the reduced-code test only employs 9 measurements to derive the complete static characteristic, which represents less than 1% of the codes of the 10-bit SAR ADC under test. The DNL and INL errors-calculated as the difference between the real and estimated static linearity errorsare shown in Figure 5.23. To help better visualize the distribution of the errors, a histogram of the errors is plotted in Figure 5.24. The RMS INL error for this case is 0.137 LSB. The ENOB for this sample is 9.4. The total test time for the reduced-code test strategy was 460.8 µs while the standard 128 hits-per-code histogram test takes 6.56 ms. The obtained test time reduction represents a test time saving of 93% compared to the standard histogram. For most samples, the effect of parasitics and mismatch on the bridge capacitor played a more significant role to the linearity than the mismatch on the capacitors of the MSB/LSB arrays.

For less established technology nodes where the capacitor fabrication is more prone to variations or for full-custom MOM capacitors for sub-femto unit capacitors, the mismatches still play a very important role. Hence, to also provide a validation of the technique when capacitor mismatch overrules the parasitics and the mismatch of the bridge capacitor, Figures 5.25a and 5.25b provide the static linearity results for a sample whose MSB capacitor of both branches was artificially increased by C u /8. The proposed methodology is able to retrieve the static response with a high reduction in test time even for such an extreme case. The obtained RMS error in the estimation of the INL was 0.45 LSB. The ENOB of this sample is 8.4 due to the higher static nonlinearity.

Layout

The floorplan of the proposed layout of the complete system is illustrated in Figure 5.26. The final layout of the complete mixed-signal circuit including the SAR ADC and the BIST circuitry is shown in Figure 5.27. The analog and digital power supplies are separated in order to reduce the influence of the noisy digital switching into the quiet analog blocks. The empty areas of the chip are filled with metal-insulator-metal (MIM) capacitors to decouple the noise from the power supplies. The layout of the SCDAC is done using the common-centroid technique to reduce the effect of process variations. Since the differential clocks (clk p and clk n ) are the fastest signals, some extra diligence was put into minimizing their distance to the on-chip clock recovery circuit. The circuit has been sent to fabrication, but unfortunately, the fabricated samples have not arrived before the conclusion of this manuscript. Further work in this research will include the full characterization of the prototype in the laboratory. Table 5.5 summarizes the total surface used by each

Abstract

The measurement of the static linearity performance is one of the key tasks in the test of an Analog-to-Digital converter (ADC). Normally, the static linearity performance figures are measured during the production phase, and the standard methodologies in the industry require the collection of a large amount of data since each code needs to be measured a few times to average the effect of noise. Reducedcode techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity test. These techniques take advantage of the repetitive operation of certain families of converters such as pipeline, successive-approximation registers (SARs), cyclic, etc. In this thesis, novel reduced-code techniques for static linearity test of SAR ADCs are presented. They are based on the on-chip generation and measurement of the transitions of the internal digital-to-analog converter (DAC) of the ADC. This allows inferring the complete transfer function of the ADC by measuring only a carefully selected subset of the total set of codes, greatly reducing the global test time. Moreover, the inherent simplification of static linearity tests provided by reduced-code techniques may open the door to a full built-in self-test (BIST) implementation. This way, tester requirements can be relaxed and test cost may be further contained by moving static linearity test resources to the device under test itself. The proposed test methodology does not require a test stimulus, and it is shown that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution incremental converter.