Yazan Barazi

Frédéric Richardeau

Nicolas Rouger

Jean-Marc Blaquière

Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

This paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond -150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board).

Introduction

The silicon carbide (SiC) MOSFETs have much better physical characteristics than Silicon. And, SiC MOSFETs offer several advantages such as low switching losses, higher switching frequencies, and high temperature stability, which makes them an alternative solution of Silicon IGBTs or SJ-MOSFETs [START_REF] Baliga | Silicon Carbide Power Devices[END_REF]. SiC MOSFETs are taking over different markets, where they are found in different applications, especially automotive applications. However, short-circuit (SC) robustness is a key application requirement for power semiconductor devices. The short-circuit (SC) withstanding time (TSCWT) of SiC MOSFETs is lower than silicon devices [START_REF] Wang | Design and Performance Evaluation of Overcurrent Protection Schemes for Silicon Carbide (SiC) Power MOSFETs[END_REF], within tSC=2µs, [START_REF] Romano | Influence of design parameters on the short-circuit ruggedness of SiC power MOSFETs[END_REF] against tSC=10µs for Si IGBTs. Many kinds of SC detection methods have been demonstrated for Silicon IGBTs [START_REF] Chen | A Smart IGBT Gate Driver IC with Temperature Compensated Collector Current Sensing[END_REF] and SiC MOSFETs [START_REF] Sadik | Short-Circuit Protection Circuits for Silicon-Carbide Power Transistors[END_REF][START_REF] Awwad | Short-circuit evaluation and overcurrent protection for SiC power MOSFETs[END_REF]. Most of the proposed techniques rely on the drain-source high-voltage or direct current sensing. Those techniques are more suitable for bipolar transistors such as IGBTs, and on the other hand they are limited due to the use of a highvoltage rating diode or using special sense-FET SiC devices [START_REF] Bertelshofer | Design Rules to Adapt the Desaturation Detection for SiC MOSFET Modules[END_REF]. This detection method is proposed in order to pile on exciting detection methods and to fill the present gap, as well as, to answer to several problematics faced nowadays by SiC MOSFETs. This paper proposes an original 2D diagnosis [START_REF] Bakran | Integrating the New 2D -Short circuit detection method into a power module with a power supply fed by the gate voltage[END_REF] detection method which is the best candidate to minimize the detection timing. The studied method depends on the fast integration of the gate current, the gate charge sequence at turn-on. The gate charge method already proved interesting results for Si IGBTs [START_REF] Oberdieck | Short circuit detection using the gate charge characteristic for Trench/Fieldstop-IGBTs[END_REF] but unclear results for SiC MOSFETs in terms of performances and practical PCB integration [START_REF] Horiguchi | A fast short-circuit protection method using gate charge characteristics of SiC MOSFETs[END_REF]. This study validates experimentally the gate charge method and fault-management for SiC MOSFETs embedded circuit in real full-voltage operation. This method is an adapted detection method, which depends on the gate charge variation on the switching cycle, between normal operation and short-mode. This method detects as early as possible the SC and turn softly the device off. Power semiconductors devices are exposed to several types of short circuits. In summary, internal Hard switching fault (HSF, SC type1) and external fault under load (FUL, SC type2) are the two main fault behaviors. HSF occurs when the switch turns on with a permanent full bus voltage across itself typically caused by faulted control signals. FUL occurs when the device is already in on-state and an external short-circuit occurs. HSF and FUL can be distinguished by the presence or not of a dv/dt on the drain source of the MOSFETs. In all cases, MOSFETs saturates at high current density leading to a thermal dynamic source of heat in a few microseconds for the least robust components. The scope of this study is limited to HSF mode.

Fast detection method

The benefits of a sub-microsecond detection

In fact, the detection methods used nowadays in the industry require the measurement of VDS. Therefore, the measurement of a high voltage involves different problems such as noise, high dV/dt, high-voltage components and over-cost to protect the control circuit, etc... The well-known detection method is the desaturation method and it requires a high-voltage diode for sensing, as well as, a blanking time. Moreover, the blanking time increases the protection time, which can cause the device to undergo more thermal stress at high short-circuit SC drain current. In order to support this, a thermal modelling and simulation of the chip temperature is carried out, Fig. 1., which shows different thermal levels where the device undergoes different stress levels and corresponding failure-modes. The important stress level is the first one where the SiO2 strength is reached around 600K and the device goes through mechanical stress, or even visible mechanical Fig. 1. 1D electro-thermal-metallurgical (Al) simulation highlighting different stress levels. [START_REF] Diaz Reigosa | Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs[END_REF][START_REF] Dou | Sûreté de fonctionnement des convertisseurs -Nouvelles structures de redondances pour onduleurs sécurisés à tolérance de pannes[END_REF][START_REF] Othman | Etude d'interrupteurs en carbure de silicium et potentiel d'utilisation dans des applications aéronautiques[END_REF] failures [START_REF] Diaz Reigosa | Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs[END_REF]. Afterwards the device enters an ageing region, where the gate starts to weaken until the devices reaches Al solidus to liquidus temperature range, 933K. Above this temperature, the device shows two failure modes: gate-damage also called Fail-to-open 'FTO' mode or thermal-runaway and BJT region latch-up giving the Fail-to-short 'FTS' mode. Using the desaturation method; which detects the presence of the SC around 1-2µs; can lead the device into the ageing region. Therefore, even if the power device is protected, the device will not withstand several SC due to the accumulation of the nonvisible damage brought by the thermal and physical stress. On the other hand, by protecting rapidly the device under 1µs, its reduces the physical and thermal stress on the oxide of the SiC MOSFET, which allows a longer operation lifetime.

Gate charge method under Hard Switch Fault

This study is focused in short-circuit under Hard Switch Fault 'HSF', whose fault dynamic is faster than Fault Under load 'FUL' one. In the literature there are different architectures proposed for the gate charge method. In this study the circuit is quite the same in the concept. This gate charge method does not require high voltage diode for sensing or setting a detection period as the desaturation method. Moreover, this method has also, potentially, a high SNR. In the principle, this method requires a resettable integrator to estimate the amount of gate charge QG; and two comparators. The first comparator is to distinguish the difference between the charge amount under short circuit QG-SC and normal turn-on (NTO) QG-NTO; the second comparator comes to create a reading flag using only VGS signal threshold crossing [START_REF] Barazi | Comparison between ig integration and vgs derivation methods dedicated to fast short circuit 2D diagnosis for wide band gap power devices[END_REF] and therefore a blanking time is not required. Fig. 2.(a). summarizes in a 2D diagram the gate charge amount under NTO and SC-HSF as a function of VGS. The validation of the gate charge method has been presented in [START_REF] Barazi | ig,vgs' Monitoring for Fast and Robust SiC MOSFET Short-Circuit Protection with High integration Capability[END_REF]. And in order to furthermore study the robustness of the designed circuit, the same test presented in Fig. 2

Robustness study under different parameters

VBus variation:

For the first robustness test, RG is fixed at 10Ω and VBus was increased with a 150V step towards 600V, as shown in Fig. 3. As presented in Fig. 3. (a) under NTO, the device behaves normally with no interferences from the gate charge circuit. The drain current is around 15A (The current scale is big in order to be able to compare the waveforms under SC), and dV/dt is equal to 32V/ns. On the other hand, under SC-HSF the detection and protection are assured for different VBus. The protection time under 50V, 150V and 300V is around 171ns, where under 450V and 600V is around 158ns. One should note as well, that ISC-MAX @ 600V is limited to 151A (68%) instead of 220A without any protection, as presented in fig. 4, Tab.1. In order to illustrate the difference in gate charge amount under SC-HSF and NTO, Fig. 5 is presented. The figure displays the image of VGS, which represents the voltage VGS adapted to 5V supply functions, therefore this voltage is compared with a reference level VRef higher than the Miller plateau. The figure presents as well the gate charge quantity under SC-HSF and NTO, and in order to differentiate between both operations a threshold level is set QRef. This configuration set of the references will activate the detection.

ILoad variation: (robustness in normal operation: no unwanted detection)

In order to increase the drain current, the pulse is increased. The used test in this configuration is a double pulse method. As presented in Fig. 6. the device does not show any false protection/detection. Different inductances have been tested as well. dV/dt at 600V decreases to 23V/ns. And the drain current in the second pulse increases as well with the bus voltage increase: (ID-Max= 10A @50V, ID-Max= 20A @150V, ID-Max= 31A @300V, ID-Max= 46A @450V, ID-Max= 60A @600V). The evolution of the gate charge amount of the second pulse at different VBus is presented in Fig. 7.

The increase of the plateau Miller does not affect the detection: no unwanted detection appears that's confirm the global robustness in normal operation. Analytical Gate charge characteristics under different parameters variations are presented (fig. 8, [START_REF] Barazi | Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology[END_REF]) in order to support the study of fig. 7. As one can see the amount of the gate charge is reduced with the reduction of RG. The reduction is proportional to the created split on RG, which is around 50%. Mainly, the origin is due to the increase of the Miller plateau indirectly by he increases of dv/dt when RG is decreased, which decreases the gate charge quantity when Ciss is max and thus QTotal is decreased. Fig. 10. shows this respective proportionality between the gate resistor values under NTO (a) and SC-HSF(b). Using a gate resistor equal to 5Ω requires a new set of the gate charge threshold level QRef=1.5V., where, the previous QRef is equal to 3V for RG=10Ω. Therefore, with the new reference set the detection circuit properly detect and protect the device under SC-HSF, and does not show any false trigging under NTO. The circuit shows robustness as well for different dV/dt, in this case dV/dt=36V/ns @600V. Different bus voltages have been tested as well with a 5Ω gate resistor.

Device generation variation:

Different devices have been studied in order to set the robustness of the method. In this section a 3 rd generation device C3M0065090D is considered.

Since the recommended gate to source voltage between both transistor of different generations (G2 & G3) differ, respectively -5/20V and -4/15V, the reference level VRef should adapt for each generation (and not each transistor), Fig. 11. Fig. 12 presents the gate charge quantity under SC-HSF and NTO for both components (Gen.II) C2M00800120D device and (Gen.III) C3M0065090D device respectively, Fig. 12.a and Fig. 12.b. As one can see, the quantity under NTO and SC-HSF for each component is nearly proportional to 42%. The major difference between both component is the total gate charge and the input capacitance of the power device Ciss=1.17nF, Ciss=0.76nF (-35%). Therefore, in order to safely protect the device and insure the detection, both references set (QRef, VRef) should adapt. In this case QRef can be set as well at 1.7V, due the 50% proportionality between the input capacitances. And, VRef can be set at 2.7V, instead of 3.3V for Gen.II.

Discussion and analysis

After the detection of a SC fault, the SiC MOSFET must be turned off safely, to limit IDS from increasing to a thermal stress point, as well as to avoid dangerous over-voltages. Therefore, to protect the circuit safely, a Soft Shut Down SSD system is included in the circuit. If the protection is not well designed it can lead to breakdown voltage by the total stray inductance due to high negative dIDS/dt imposed by the transistor's channel dynamic, the protection should be soft to prevent this phenomenon. A high impedance (HZ) state is required before the activation of the SSD to avoid the driver to be short circuited by the SSD circuit. The observed plateau in the gate-source voltage VGS under protection is due to the inductive effect through the kelvin inductance LSK (parasitic inductance of package and terminal pin on PCB in the presence of a di/dt < 0). The protection is activated between 150ns and 180ns depending on the test condition, limiting the drain current around 110A -151A instead of respectively 130A -220A. In such a short time and at such a low current value, the dynamic temperature of the chip remains lower than the melting temperature of the aluminum to metal of the die, which would allow a large number of repeated short circuits without ageing effect [START_REF] Fayyaz | Aging and failure mechanisms of SiC Power MOSFETs under repetitive short-circuit pulses of different duration[END_REF]. One should note that optimization can be realized in order to protect earlier and limiting the drain current to lower value, therefore reducing furthermore the physical and thermal stress on the device. The robustness of the circuit has been tested for several pulses, VDS values, Iload values, RG values and different components. Detection at lower bus voltages is more critical between SC-HSF and NTO, where the circuit showed high performances at 50V and lower.

Regarding the gate side variation, a different threshold set is required for values higher than 50% of the defined gate charge amount. On the other hand, one can set a trade-off between the integrator capacitor/resistor (C1/R1) and the gate resistor/gate input capacitance of the device (RG/CEq). Fig. 13. presents a 3D plot of the output of the integrator, VOut, under different variation, where this trade-off can be met. On the figure, two representative equivalent capacitors define a plateau of C1/R1 choices. The equivalent capacitors represent the input capacitance of the power device under NTO and SC-HSF. Since the gate charge amount ratio under NTO and SC-HSF is 50%, the same ratio is respected for the equivalent capacitors. Therefore, the one can easily define the threshold set QRef in order to differentiate between NTO and SC-HSF gate charge amount. As well, one can define different family sets for the gate variations (Gate resistor, input capacitance) in order to have a programmable threshold level set. the detection circuit can be further optimized and the delays can be strongly reduced. At the end, the goal is to integrate all the functions in a dedicated gate driver. Avoiding the drain side of the device facilitate the integration of the detection method within the gate driver. A programmable reference set should be carefully designed.

  .(b) has been led. The circuit in fig.2(b) was proposed using on the low side a 1.2kV-80mΩ, C2M0080120D gen. II SiC MOSFET transistor, and on the high side a SiC 600V SBD (Schottky barrier diode) with a coreless inductor of 270 µH as the load for the normal operation. A copper short-strap across the high side switch is used in order to get the HSF mode. The gate driver used is a 3-state fast buffer, which allows a high impedance configuration. The dedicated and optimized SMD/PCB circuit was implemented in the power test bench as a plugging board. Low voltage signals (as VGS and VDrv) are mostly measured with selfcompensated voltage probes (300V and 1 GHz bandwidth (BW) Tektronix TPP1000). High voltages (as VDS) are typically measured with a probe (1000V and 800MHz BW Tektronix TPP0850). The current is measured through a 2GHz coaxial shunt.

Fig. 2 .

 2 Fig.2. (a). Gate Charge characterization under NTO and HSF. (b). Circuit under test. LS: Stray inductance. (c). view of the detection circuit,3.5cm*5.3cm.

Fig. 3 .

 3 Fig. 3. Oscilloscope waveforms of the gate charge detection circuit with protection (a). under NTO. (b). under SC-HSF. @600V, RG=10Ω, VDrv= -5/20V.

Fig. 4 .

 4 Fig. 4. Oscilloscope waveforms of the device under SC with and without protection. @600V, RG=10Ω, VDrv= -5/20V.

Fig. 5 .

 5 Fig.5. Integrator output "QG" under NTO and SC-HSF operation @600V, RG=10Ω, C2M0080120D, VDrv= -5/20V, ILoad-NTO=15A.

Fig. 6 .

 6 Fig.6. Oscilloscope waveforms under NTO, double pulse and different VBus. @600V, RG=10Ω, VDrv= -5/20V.

Fig. 7 .

 7 Fig.7. QG and the image of VGS oscilloscope waveforms of the second pulse associated to Fig.6, different VBus & ILoad.

Fig. 8 .Fig. 9 .

 89 Fig.8. Analytical Gate charge characteristics under different parameters variations. [16] 3.3. RG variation: Fig.9. (a). presents oscilloscope waveforms from the power device side (VDS, VGS, ID) at 600V under NTO

Fig. 10 .

 10 Fig.10. Oscilloscope waveforms comparison between RG=5Ω and RG=10Ω under (a). NTO (b). SC-HSF @600V, VDrv= -5/20V.

Fig. 11 .Fig. 12 .

 1112 Fig.11. "VGS image" under 400V NTO and SC-HSF

Fig. 13 .

 13 Fig.13. (a). Basic integrator schematic (b). 3D plot of the integrator output VOut under different variation. [16], with R1>>RG & C1>>CStray 5. Conclusion 2D diagnosis once again proves it is the perfect candidate for fast short-circuit detection and protection. The original gate-charge method (2D diagnosis) detects as fast as possible the behavior of the circuit, within 155ns. High robustness have been observed for main parameters variations. Moreover,

Table 1 .

 1 ISC-Max under different VDS.

	VDS	ISC-Max without protection	ISC-Max protection	Ratio %	Protection time
	50V	133A	110A	82%	183ns
	150V	180A	135A	75%	171ns
	300V	202A	139A	69%	171ns
	450V	213A	139A	65%	158ns
	600V	220A	151A	68%	158ns

*Ratio%: ISC-Max-Protection / ISC-Max-Without-Protection*100


Hervé Rabat

Caroline Andreazza

Pascal Brault
email: pascal.brault@univ-orleans.fr

Amaël Caillard

François Béguin

Christine Charles

Rod Boswell

Carbon/platinum nanotextured films produced by plasma sputtering

Platinum loaded carbon layers were synthesized by a two-step plasma sputtering process. 200 nm thick columnar (columns with an average diameter of 20 nm) carbon films having a large open porosity were formed in the first step. Using the same plasma system, the films were subsequently loaded with platinum. SEM, TEM and Rutherford backscattering spectrometry analysis show that platinum diffuses into the carbon layer and forms nano-sized particles (mean diameter ca. 3 nm) along and around the carbon nanocolumns and down to the film/support interface. Optimized catalytic layers were formed at low plasma pressure operation (<1 Pa) and had an upper platinum loading limit of about 0.1 mg.cm -2 .

Introduction

Heterogeneous catalysis is of primary importance in many chemical and electrochemical processes. To be efficient a solid catalyst is usually an assembly of nano-sized particles dispersed on a support with (preferably) a large surface area. Nanoporous carbons are one of the most currently used physical supports for catalysts deposition [1][2][3][4][5][6][7][8][9]. In the future, due to environmental concerns, both the catalyst usage conditions and catalyst preparation methods will suffer from severe international rules.

The development of new and environment friendly catalyst preparation methods remains a challenging research task aimed at simplifying the industrial processes, while reducing the fabrication costs and preparation times, and increasing the catalysis efficiency and selectivity.

Plasma technologies have been involved in catalysis with some success [10][11][12]. Most of the studies are related to ultra-fine particles production, direct catalyst deposition on a support [13,14] and also assistance of catalytic reactions [START_REF] Khacef | Proceedings of the VIIIth Hakone[END_REF][START_REF] Gorce | SAE technical paper[END_REF]. Although very few studies are devoted to low pressure plasma deposition of catalytic thin films, the latter is expected to be advantageous for controlling low catalyst content and location [START_REF] Matsumyia | Sensors and Actuators B[END_REF][START_REF] Tiggelaar | Solid-State Sensors[END_REF][START_REF] Randolph | [END_REF][20][21][22][23]. The present study reports on a new fabrication method using plasma sputtering for obtaining an active carbon layer loaded with platinum. The influence of the deposition parameters on the carbon layer morphology and platinum diffusion into the layer is investigated and discussed.

Experimental

Sputtering device

Carbon and platinum were deposited by plasma sputtering and a scheme of the low pressure plasma experimental set up (MHS Equipment) is shown in Figure 1. An argon plasma is created in a 80 L cylindrical stainless steel chamber by using an external water cooled planar three turn radiofrequency antenna powered at 300 W using a 13.56 MHz Radio Frequency generator coupled to an impedance matching box. The chamber is evacuated to less than 5.10 -5 Pa and the depositions are performed in the pressure range 0.5 Pa to 5 Pa. To sputter carbon and platinum, two 50x50 mm high purity planar targets for each material are placed at half height in the chamber and DC biased at a fixed voltage of -300 V. The targets are placed at a distance of 80mm from the substrate (100 type silicon) at an angle of 45° with respect to the grounded substrate holder axis. Silicon wafers are used as substrates because they allow a correct measurement of the thickness and composition of the carbon and Pt -carbon films. The substrate is rotated and its temperature is measured with a thermocouple.

Pt/C synthesis

The carbon films loaded by platinum catalyst are made in two consecutive steps. Initially, in order to obtain identical carbon layers, carbon is deposited onto ten silicon samples during a single one hour deposition run at 2 Pa. Catalyst is subsequently deposited onto each of these carbon layers using various pressures and deposition times to get some insight into the resulting morphology changes.

Analysis

Scanning Electron Microscopy (SEM-Hitachi S4500) and Transmission Electron Microscopy (TEM-Philips CM20) were used to characterize the film's morphology and the platinum particle size in the carbon layer. Cross sections were prepared in order to observe the in-depth profile of the deposits.

The presence of platinum was detected by EDX (energy dispersive X-ray spectrometry) and the films were analyzed by RBS (Rutherford Backscattering Spectroscopy) with a Van de Graaf accelerator (CERI-CNRS, Orléans, France) using a 2 MeV 4He + ion beam. Coupled with the SimNRA [24] software, it is a powerful method for determining the composition and depth profile. From the RBS analysis, the total number of Pt atoms per cm² (N s ) of deposited film is measured, whereas the film thickness is estimated by SEM observations of the cross-sections.

Results and discussion

The carbon layer

The SEM image in Figure 2 shows a typical cross-section of the carbon coating deposited by plasma sputtering on (100) type silicon. The carbon layer growth is columnar with column density depending on plasma process parameters as a result from the so-called shadowing effect [25]. The columns stand on a 20 nm thick dense carbon interface with the silicon substrate. From bottom to top, the columns diameter increases from about 10 to 25 nm and the total film thickness is around 200 nm.

Using RBS analysis, about 12 µg.cm -2 (560x10 15 atoms.cm -2 ) of carbon was found to make up this layer leading to a density of about 0.7 g.cm -3 . Hence this open structure exhibits an adequate morphology and can be used as a support for the catalyst.

The Pt/C layers

Platinum was deposited onto the carbon layers using different sputtering times (from 1 min to 15 min at 1 Pa) and pressures (from 0.5 Pa to 5 Pa during 10 min). Table 1 shows the quantities of deposited platinum and the morphological characteristics of the resulting Pt coated carbon thin films deduced from RBS and SEM measurements, respectively. For a given pressure (samples 2 to 4 in Table 1), the increase of the amount of deposited platinum, from 131×10 15 atoms.cm -2 to 408×10 15 atoms.cm -2 , leads to an increase in the height and diameter of the columns. Broadening mainly occurs at the top of the columns, but is also present at the bottom. From these results, we can deduce that platinum diffuses well inside the carbon layer.

Platinum diffuses over the whole pressure range investigated here (0.5 to 5 Pa) with the platinum deposition rate and the top and bottom diameters of the carbon columns decreasing with increasing operating pressure as shown in Table 1 (samples 6 to 8).

Figure 3a shows a TEM micrograph cross section of sample 8 (t=10min, P= 5 Pa). At the substrate interface, a dense layer, with a thickness of about 20 nm can be seen, as previously mentioned ( Figure 2). Above this interface layer, nano-sized Pt particles are observed along and around all the columns (dark areas on the micrographs), from the top where the nanoparticles are more prevalent to the bottom where they are more dispersed. The nanoparticle size (1-8 nm) and density decrease from the top to the bottom of the columns and depend on the pressure and deposition time. In the HRTEM image (Figure 3c) for Pt nanosized particles well oriented to the electron beam, 0.23 nm spaced lattice fringes corresponding to the d 111 interplanar distance of platinum are observed . The EDX analyses confirm a decrease of the platinum amount from the surface to the interface.

Figure 4 shows the influence of the deposition time at a constant pressure of 1 Pa on platinum diffusion in the carbon layer. At the beginning of the deposition (Figure 4a corresponding to 1 min deposition time), platinum is present everywhere in the layer with a denser surface layer (10 nm thickness). Increasing the deposition time from 1 to 10 min, the thickness of this surface layer increases from 10 to 80 nm and the nanoparticle sizes increase from 1.5-5 nm for 1min deposition to 1.8-8 nm for 10 min, as shown in Table 2.

TEM analyses of two samples obtained with the same deposition time at different pressures (1 and 5 Pa, samples 4 and 8) indicate a thin and dense surface layer and smaller particle size (Table 2) at low pressure, leading to a more homogeneous distribution of the Pt nanoparticles in the carbon layer.

Figure 5 displays SEM micrographs of the cross-section of carbon layers coated by platinum for the samples 3, 5 and 6. The regions occupied by Pt atoms appear brighter than the carbon ones.

Compared with sample 1 without platinum (figure 2), the micrographs clearly show that the columnar structure of the deposited film is preserved for deposition times less than 10 min at 0.5 and 1 Pa (samples 3 and 6 in Figure 5). For a deposition time of 15 min (sample 5 in Figure 5), the carbon columnar structure has collapsed and the layer thickness is considerably reduced. Interestingly, the platinum quantity deposited at 0.5 Pa for 10 min (sample 6) is similar to that of sample 5 (about 450 ×10 15 atoms.cm -2 ), although the corresponding film presents very different morphologies. The platinum diffusion into the carbon thin film is favoured at low pressure (0.5 Pa) which leads to strengthening the columnar structure and preventing the formation of a dense platinum top layer at the film surface.

Otherwise, as in sample 5, a thick dense platinum layer induces stress onto the carbon column structure and it collapses [26]. The fact that platinum diffuses deeper at low pressure results from a higher kinetic energy of the sputtered platinum atoms and from ion bombardment occurring during deposition as previously reported on flat surfaces [27][28][29][30].

Hence to ensure an adequate morphology of the loaded film with a good dispersion of the catalyst, the amount of deposited platinum should be limited to 300×10 15 atoms.cm -2 , e.g., 0.1 mg.cm -2 and the working pressure should be less than 1 Pa.

Conclusion

In summary, this experimental study demonstrates that plasma sputtering can be successfully applied to preparing and controlling the composition and the structure of catalyst loaded carbon layers.

Low pressure (<0.5 Pa) deposition below a typical maximum limit of about 300×10 15 atoms.cm -2 leads to the growth of Pt loaded porous carbon films with a good platinum dispersion. Experiments are under progress to evaluate the electrochemical performance of active layers prepared by this novel process.

Figure 1 :

 1 Figure 1: Scheme of the Transformer Coupled Plasma sputtering reactor.

Figure 2 :

 2 Figure 2: SEM image of the cross-section of a carbon coating prepared at 2 Pa during 60 minutes.

Figure 3 :

 3 Figure 3: TEM image of loaded carbon films; Sample 8 (t=10 min, P=5 Pa). (a) cross section, (b)

Figure 4 :

 4 Figure 4: Influence of the platinum deposition time at 1 Pa on the surface layer thickness; (a) Sample 2

Figure 5 :

 5 Figure 5: SEM images of carbon films loaded with platinum at different pressures and deposition times;

Table captions :Table 1 : Pt quantities and morphological characteristics of the catalyst loaded carbon films.

 captions1

	Sample	Deposition time (min)	Operating Pressure (Pa)	Pt quantity (10 15 at.cm -2 )	Mean column height (nm)	Bottom column mean diameter (nm)	Top column Mean diameter (nm)
	1	0	-	0	176	10	24
	2	1	1	131	178	16	31
	3	5	1	245	187	18	35
	4	10	1	408	243	24	46
	5	15	1	458	177	-	52<w<84
	6	10	0.5	441	231	27	54
	4	10	1	408	243	24	46
	7	10	2	395	241	22	47
	8	10	5	326	245	19	43

Table 2 : Platinum particle diameter ranges.

 2

	Sample	2	3	4	8
	Diameter (nm) 1.5<d<5	1.5<d<6	1.8<d<8	2.5<d<5

Acknowledgement

This work was supported by CAdD, FSE-EU, MHS Equipment, ACI PLASMAPAC and GDR-I CNRS "Plasmas". All authors would like to thank Y. Tessier from GREMI (Orléans, France), A. Richard from CME (Orléans, France) and Thierry Sauvage from CERI (Orléans, France).


Wadia Jouha

Frédéric Richardeau

Stephane Azzopardi

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe "Fail-To-Open" (FTO) mode in planar power SiC MOSFET devices under shortcircuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm²) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e VBRmin / 2. The boundary of the power density between FTO and "Fail-To-Short" (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

Introduction

Wide bandgap semiconductor materials like Silicon Carbide (SiC) stands in the centre of attention for designing new power semiconductor devices thanks to their better intrinsic properties than Silicon (Si) [START_REF] Shenai | The figure of merit of a semiconductor power electronics switch[END_REF]. SiC has interesting physical properties such as high electric field and high thermal conductivity that makes ability to ensure superior performances in high power applications (temperature, switching frequency, efficiency) [START_REF] She | Review of silicon carbide power devices and their application[END_REF]. SiC MOSFET are an effective technology solution to design high performance electrical-power switches that provides lower switching losses and high power density [START_REF] Wu | 1200 V SiC MOSFETS for high voltage power conversion[END_REF][START_REF] Othman | Robustness of 1.2 kV SiC MOSFET devices[END_REF]. Beside the switching performance, SiC MOSFETs robustness in the industrial field is a major feature that must be considered for power conversion systems [START_REF] Riccio | Experimental analysis of electro-thermal instability in SiC Power MOSFETs[END_REF]. Indeed, SiC MOSFET capability in withstanding stressful conditions, such as short-circuit (SC) operation, is the main obstacle of the expansion of these devices to industrial applications.

Literature highlights several studies investigating the SC capability of SiC MOSFETs [START_REF] Castellazzi | Shortcircuit robustness of SiC Power MOSFETs: Experimental analysis[END_REF][START_REF] Wang | Temperature-dependent short-circuit capability of silicon carbide power MOSFETs[END_REF][START_REF] Chen | Study of short-circuit robustness of SiC MOSFETs, analysis of the failure modes and comparison with BJTs[END_REF][START_REF] Pappis | Failure modes of planar and trench SiC MOSFETs under single and multiple short circuits conditions[END_REF]. According to the literature, SiC MOSFETs may present, under short circuit operation, a competition between two failure modes. The first one is called drain-source Fail-To-Short (FTS) failure characterized by a drain-source short and leads to a permanent damage of the device. The second one is named drain-source Fail-To-Open (FTO) failure caused by a hard gate -source short-circuit path which Vgs < Vgsth (threshold voltage) is applied.

The FTS mode is issued from a thermal runaway and/or the parasitic BJT latch-up inducing the local destruction of the die and the creation of a metallic path between drain and source. In the FTO mode, fusion and diffusion of the Al top metal through gate-cracks are observed [START_REF] Liu | Gate Failure Physics of SiC MOSFETs Under Short-Circuit Stress[END_REF]. This failure is related to the extreme heat in short-circuit between the poly silicon gate and the Al source. This metallic path can be located either on top of the chip between the gate fingers and the source pad below the passivation layer, and/or through the ILD (Inter-Layer Dielectric) across metallized cracks [START_REF] Boige | Ensure an original and safe "fail-to-open" mode in planar and trench power SiC MOSFET devices in extreme shortcircuit operation[END_REF]. This is due to a very low coefficient of thermal expansion of the oxide compared to those of Al and SiO2. In the latter case, the short-circuit between the gate and source electrodes can lead to a permanent FTO mode if Vgs < Vgsth or a partial FTO mode if Vgs > Vgsth. In any case, FTO is clearly a more secure failure mode and is suitable for safety applications. In the literature [START_REF] Boige | Investigation on damaged planar-oxide of 1200 V SiC power MOSFETs in non-destructive short-circuit operation[END_REF], to preserve the FTO mode, a drain source voltage (Vds) depolarization method was used to reduce the power density crossing the chip in order to avoid thermal runaway. Obviously, this approach directly reduces the switching power capability to the same power semiconductor device.

This paper focuses on the faculty to obtain a FTO failure mode using the two above approaches based on direct depolarization of the gate source voltage (Vgs) by reducing the buffer voltage (Vbuffer). These approaches aim to determine the maximum value of Vgs allowing a FTO mode to be maintained at a voltage Vds close to the nominal value i.e VBRmin/2 (eg.600 V for 1.2 kV rating). The short circuit characterizations are performed on commercially available power SiC MOSFETs. The device performance and robustness are investigated under single pulse short circuit, for various Vbuffer bias conditions and at room temperature T = 25 °C. This paper is organized as follow: first, the device under test and test protocol are presented. Then, the experimental results of Vgs depolarization approach, the Vgs estimation method and the penalty of these approaches on Rds(on) are discussed.

Device under test and test protocol

Device under test

In this work, short circuit tests are carried out on 1200 V planar SiC MOSFETs manufactured by Cree (C2M0080120D) [START_REF] Cree | D-SiC MOSFET Datasheet[END_REF]. Main electrical characteristics are presented in Table 1.

Protocol of short circuit test

Commercially power SiC MOSFET are examined under type 1 short circuit test. The test setup is presented in Fig. 1. The characterization of the Device Under Test (DUT) under type 1 short-circuit test is performed by placing the DUT in the Low Side (LS) position and the High Side (HS) device is replaced by a strap bar. A circuit breaker based on Si IGBT mounted in series is used to protect the DUT from any damage after short-circuit failure. An adjustable gate drive was developed in order to drive the various DUT. The turn-on voltage (Vbuffer(on)) can be adjusted from 9 V to 21.5 V and the turn-off voltage (Vbuffer(off)) can be adjusted from 0 V to -6 V. The control signal for the driver is provided by an FPGA allowing to adjust the desired short-circuit duration through a touch screen. The FTO and / or FTS failure mode occurs by applying successive short circuit tests with increasing short circuit duration (Tsc) by 1µs at each test. The DC bus voltage (VDC) or Vds is provided by a DC voltage supply (0 V-600 V). Vds is gradually applied until the desired value is reached. A gate resistance (RG) fixed to 47 Ω was used for this study for local measurement of gate leakage and permits a slow turn-off to avoid overvoltage without the use of a Soft Shut Down (SSD).

Experimental results and discussion

Failure mode and Gate voltage depolarization

Both FTS and FTO modes are controlled by the temperature increase inside the device, and more precisely by its growth rate. In [START_REF] Romano | A Comprehensive Study of Short-Circuit Ruggedness of Silicon Carbide Power MOSFETs[END_REF], the authors explain the appearance of these failure modes and its dependence on device temperature. This approach presented in Fig. 2.

From Fig. 2a, the FTS mode occurs when the junction temperature rises quickly and reaches a thermal runaway temperature (TRNW) in a time that does not allow the gate degradation delay time to be reached. If the device temperature remains between the degradation temperature (TDEG) and the runaway temperature for sufficient time, the device should reached in an FTO type defect (Fig. 3b). This implies that in Table 1. Electrical characteristics of power device under test

FTO

FTO+FTS or FTS

order to obtain the FTO failure, the temperature within the chip should not rise too quickly. According to equation (1) [START_REF] Clemente | Transient thermal response of power semiconductors to short power pulses[END_REF], there are two ways to decrease junction temperature in a shortcircuited chip: decrease Vds or decrease the density of saturation current by Vgs depolarization.

∆𝑇 𝑗𝑚𝑎𝑥 (𝑡) = 2.𝑉 𝑑𝑠 .𝐽 𝑠𝑎𝑡 𝜌𝑐√𝜋𝛼 √𝑡 ( 1
)
where ρ is the density of SiC, c is the specific heat of SiC, α is the thermal diffusivity of SiC and t is the SC time.

In our study, to preserve a FTO under a Vds value close to the nominal voltage, an approach based on the direct depolarization of Vgs is investigated. Short circuit tests are carried out by setting the gate source polarization value at 15 V and starting with a voltage Vds of 300 V. Many commercial SiC MOSFET components have a FTO mode at a reduced Vds. This voltage is the starting point of the study. If the test induces a secure failure mode FTO at this value of Vgs, then the Vds voltage is gradually increased by one step (between 33V and 100V). On the other hand, if the test induces a FTS, then Vgs is reduced with a step of 1V. Fig. 3 summarizes the results of short circuit tests carried out on the C2M0080120D devices under various polarization conditions of Vds using a direct depolarization of Vgs. Table 2 presents for each DUT:

-the failure mode (FTO or FTS) -the maximum short circuit duration Tsc, -the maximum energy Esc = Idsmoy . Vds . Tsc, -the dissipated power per unit area P = Idsmoy .Vds / (surface of the chip). It can be observed that direct polarization of Vgs method shows a promising results in terms of Tsc that exceeds 10µs (standard for IGBT device), and the appearance of FTO mode under a Vds close to the nominal value. From Fig. 3, three critical regions must be defined in order to choose an optimum short circuit bias conditions. The first region (1) appears for very low drain voltages where the device is in strong derating in Vds. In this region, the device robustness is more assured by FTO mode, however its performance is penalized in terms of the converter efficiency and its cost. In the second zone (2), the device is placed under high Vds and Vgs which reduce its robustness and leads to its degradation (appearance of a strong drain leakage and gate leakage currents) or to its failure with a FTO mode followed by a FTS or directly an FTS mode. For the third region (3), the device is placed under a small gate polarization (strong depolarization in Vgs), which generates an increase in Rds(on) and consequently losses in higher conduction. On the other hand, with a Vgs too close to Vgsth makes the device more sensitive to electron trapping effect at SiC/SiO2 interface and Vgsth drift [START_REF] Reigosa | Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs[END_REF][START_REF] Lelis | Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements[END_REF]. Also, due to the variability of local Vgsth from one local MOSFET cell to another, a too low Vgs can lead to a high current density inhomogeneity of the chip surface in the channel regions. Fig. 4 depicts the waveforms of the various voltages and currents obtained for the short circuit test performed on DUT#8 under Vbuffer =12 V and Vds = 550 V. From the Fig. 4, a delayed FTO with 5µs from the short circuit duration applied (Tsc=18 µs) is observed. Before the appearance of the FTO mode, a gate leakage current (Igs) of 12 mA is measured, although the polarization is reduced to 12 V, to around 2/3 of the Tsc. During the short-circuit event, Ids slope variation can be noticed which results in the appearance of the drain leakage current very clear at turn-off. This drain leakage is always clearly visible from 500 V.

Using the direct depolarization method of Vgs is not always promising for keeping FTO a value of Vds closer to the nominal value. In Fig. 5, the short circuit characterization of DUT#10 under Vbuffer = 11.2V and Vds = 600V, shows the appearance of the FTS failure mode which leads to catastrophic damage of the device. This failure mode appears after 4 µs from the applied short circuit duration (Tsc = 19 µs). Fig. 5 illustrates the waveforms of the various resulting voltages and currents. The appearance of FTS failure mode is linked to the increase of the drain leakage current compared to the results obtained under the Vds = 550 V. On the other hand, the gate leakage current (Igsmax= 10 mA) is less pronounced compared to the previous test (Igsmax = 12 mA at Vbuffer = 12V) due to the lower applied value of Vbuffer.

Gate source voltage estimation methodology

To complete the direct depolarization method of Vgs, a second approach is developed to estimate the Vgs value permitting to keep the appearance of FTO failure. This approach allows to investigate the critical dissipated power (W/mm²) boundary between FTO and FTS modes, responsible for the the device failure. The method is based on the results of two single pulse short circuit events. The first one leads to a FTO mode, and the second one induces a FTS mode.

The results of SC tests on DUT#8 and DUT#10 are analyzed for such purpose. The first short circuit event performed on DUT#8, under Vds=550 V and Vgs=12 V, shows a dissipated power of PFTO=3418 W/mm² leading to appearance of FTO failure. While the second event carried out on DUT#10, under Vds=600 V and Vgs=11.2 V, presents a dissipated power of PFTS=4014 W/mm² leading to appearance of FTS failure. The dissipated power is expressed by equation ( 2).

𝑃 = 𝑉 𝑑𝑠 . 𝐼 𝑑𝑠𝑚𝑜𝑦 (2)
In small signal of Vgs variation, the Idsmoy current can be presented by equation [START_REF] Wu | 1200 V SiC MOSFETS for high voltage power conversion[END_REF].

𝐼 𝑑𝑠𝑚𝑜𝑦 = 𝐾 𝐿𝑉 . (𝑉 𝑔𝑠 -𝑉 𝑔𝑠𝑡ℎ )² (3)
where KLV (A/V²) is a constant that represents transconductance parameter in Low Voltage (LV) of Vgs.

For Vgs values higher than the threshold voltage Vgsth (Vgs >> Vgsth), the operating device can be placed in the large signal of saturation zone (i.e proportionality relation). Therefore, equation ( 3) can be expressed by equation [START_REF] Othman | Robustness of 1.2 kV SiC MOSFET devices[END_REF].

𝐼 𝑑𝑠𝑚𝑜𝑦 = 𝐾 𝐻𝑉 . (𝑉 𝑔𝑠 -𝑉 𝑔𝑠𝑡ℎ ) ( 4
)
where KHV is a constant that represents transconductance parameter in High Voltage (HV) of Vgs. Consequently, the dissipated power P is related to Vgs voltage through equation [START_REF] Riccio | Experimental analysis of electro-thermal instability in SiC Power MOSFETs[END_REF].

For DUT#8 that presents a FTO mode under Vds=550V, Vgs=12 V, Vgsth =2.61 V and PFTO=3418 w/mm², the transconductance KHV is calculated as:

𝐾 𝐻𝑉 = 𝐾 𝐹𝑇𝑂 = 𝑃 𝐹𝑇𝑂 𝑉 𝑑𝑠 .(𝑉 𝑔𝑠 -𝑉 𝑔𝑠𝑡ℎ ) = 0.661 A/V.mm² (6)
From this result, we found that the Vgs estimated (Vgs_es) estimated at Vds=600 V, using the same PFTO value and is equal to 11.22 V. However, it has been demonstrated that this value of Vgs_es induces a FTS mode on DUT#10. The 𝐾 𝐻𝑉 𝑖𝑠 𝑎 posteriori calculated for (PFTS = 4014 w/mm²) and Vds=600 V. Then, Vgs_es is estimated more precisely for a test under Vds=600V with a dissipated power leading to a FTO (PFTO) and the calculated KFTS coefficient:

𝑉 𝑔𝑠_𝑒𝑠 = 𝑃 𝐹𝑇𝑂 𝑉 𝑑𝑠 𝐾 𝐹𝑇𝑆 + 𝑉 𝑔𝑠𝑡ℎ  10 𝑉 (8)
This method allows to find the Vgs interval which ensures a FTO mode at Vds=600 V:

10V ≤ Vgs_es< 11.22 V (9)
To validate this method of Vgs estimation from the dissipated power density, the short-circuit test is performed under the voltage Vbuffer = 10 V and Vds = 600 V on two DUTs in order to evaluate the repetitiveness of the proposed approach. Table 3 presents the short circuit test duration (Tsc), the measured dissipated power (Pmes) compared to the estimated dissipated power (Pest) that confirm the validity of the new approach for the two DUTs. Fig. 6 illustrates the waveforms results of short circuit test performed on DUT#11. It can be observed that the secure failure mode FTO appears after 6 µs from the applied short-circuit duration (Tsc = 24 µs). The gate leakage current (Igsmax = 2.5 mA) is less pronounced compared to the previous test (Igsmax =12 mA at Vbuffer = 12 V and Igsmax = 10 mA at Vbuffer = 11.2 V) given the low value of the applied voltage (Vbuffer=10 V). The drain leakage is high because Vds has a high value of 600 V. However, this leakage current remains the same magnitude as for the test for 550V preserving the FTO failure. This observation proves that the applied power density over the duration Tsc is preserved to give the same failure mode.

By associating the two approach results presented previously, it can be identified that the damaged devices in FTO mode follows a quasi linear Vgs -Vds characteristics (Fig. 7) which becomes improvable at high voltage close to 600 V due to the appearance of a drain leakage causing a delayed FTO/FTS sequence. This trend allows the prediction of Vgs that leads to the appearance of a FTO.

Penalty of the Vgs depolarization on the Rds(on) resistance

The impact of Vgs depolarization approaches on Rds(on) resistance must be investigated. Fig. 8 presents the Rds(on) resistance evolution as a function of the Vgs voltage at two temperatures 25 °C and 150 °C. These results were obtained from the datasheet. It can be observed that relative variation of Rds(on) against Vgs voltage is +247% at 25 °C and only +44% at 150 °C. Moreover, if we consider that the conduction losses only account 50% of the total losses, thus the Vgs depolarization will represent an acceptable impact on Rds(on) @ 150 °C with a 22% ratio. The reduction of the Rds(on) penalty at Tj = 150 °C is physically related to the mobility behavior affected by Coulomb scattering [START_REF] S L Rumyantsev | Channel mobility and on-resistance of vertical double implanted 4H-SiC MOSFETs at elevated temperatures[END_REF]. Indeed, the mobility in the channel is governed at low polarization by Coulomb scattering mechanism which becomes dominant compared to the others mechanisms in particular surface acoustic scattering for the JFET and drift regions. The Coulomb mobility has a positive thermal sensitivity coefficient for a Tcase range between 25 °C and 200 °C. Therefore, the channel resistance decreases when the case temperature of the chip in operation increases.

However, the other resistances of JFET and drifts regions increase with the temperature rise. Consequently, a compensation effect appears and becomes more effective as Vgs is reduced. At a given Vgs, there is an optimum case temperature which gives the lowest total value of Rds(on) corresponding to a state of thermal effects compensation between the resistive terms.

Conclusion

In this paper, planar gate structure SiC MOSFETs robustness has been experimentally evaluated under short circuit operation. The obtained results confirm the existence of two failure modes (FTO and FTS) for thirteen devices (80mΩ/1.2kV, 2 nd Gen). Two approaches based on direct depolarization of Vgs are developed to ensure a secure failure mode FTO at Vds close to the nominal value i.e VBRmin/2. The direct depolarization approach shows promising results in terms of short circuit duration (Tsc) that exceeds 10 µs, and the appearance of FTO mode taking into account a maximum power density around 3.5 kW.mm -2 . This critical value is identified as the power density boundary between FTO and FTS modes. For these devices, the Vgs estimated from the dissipated power calculations leads to a FTO appearance at Vds=600 V. The study of Rds(on) resistance evolution as a function of Vgs, shows that Vgs depolarization impacts Rds(on) in acceptable way at 150 °C. This approaches have been validated on other current rating devices (25mΩ/1.2kV) and for voltage rating devices (45mΩ/1.7kV) from the same manufacturer. However, the trench gate-structure evaluated did not show satisfying results for Vgs depolarization approach. The results may provide useful indicators for converter design and fault protection conditions of SiC power MOSFETs with planar structure.

Fig. 1 .Fig. 2 .Fig. 3 .

 123 Fig. 1. Schematic of Type 1 short-circuit test [11].

Fig. 4 .

 4 Fig. 4. Experimental waveforms during short circuit of the DUT#8 (Vds=550 V; Vbuffer(on/off)= +12 V/-5 V; Tcase=25 °C; RG=47 Ω).

Fig. 5 .Fig. 6 .

 56 Fig. 5. Experimental waveforms during short circuit of the DUT#10 (Vds=600 V; Vbuffer(on/off)=+11,2 V/-5 V; Tcase=25 °C; RG=47 Ω).

Fig. 7 .

 7 Fig. 7. Evolution of Vgs as a function of Vds according to iso-power (P) criterion and FTO failure mode.

  779 A/V.mm²[START_REF] Wang | Temperature-dependent short-circuit capability of silicon carbide power MOSFETs[END_REF]

Fig. 8 .

 8 Fig. 8. Rds(on) as a function of Vgs at two temperatures 25 °C and 150°C for C2M0080120D device.

Table 2 .

 2 Summary of short circuit tests performed on C2M0080120D 80mΩ / 1200V devices using a direct depolarization of Vgs

	DUT	#1	#2	#3	#4	#5	#6	#7	#8	#9	#10
	Vds (V)	300	333	363	400	500	450	500	550	600	600
	Vgs (V)	15	15	15	15	15	14	13	12	12	11.2
	Failure	FTO	FTO	FTO	FTO	FTS	FTO	FTO	FTO	FTS	FTS
	mode
	Tsc (µs)	40	28	25	21	16	20	21	18	13	19
	Esc (J)	0.80	0.97	0.93	0.90	0.81	0.82	0.82	0.64	0.63	0.79
	P(W/mm²)	1918	3316	3589	4102	4936	3948	3757	3418	4640	4014


Wadia Jouha

Frédéric Richardeau

Stephane Azzopardi

Repetitive short circuit capability of SiC MOSFET at specific low gate-source voltage bias for more robust extreme operation

This paper presents short-circuit (SC) performance of a commercial silicon-carbide (SiC) MOSFET device under repetitive SC stress at high drain source voltage. Two protocols are investigated to evaluate the impact of gate-source voltage (VGS) depolarization and SC duration (TSC) reduction. The VGS depolarisation provides a power density reduction and allows to preserve a secure failure mode (FTO: Fail To Open) with an increase of the short circuit duration TSCmax. The results demonstrate that SiC MOSFET VGS depolarization does not reduce SC cycling capability at TSCmax. However, using VGS depolarization allows to get performance close to IGBT robustness levels with almost 1000 cycles @TSC=10µs. The simulation of the chip temperature evolution during SC tests suggests that the degradations stay attributed to the increase of junction temperature (TJ) during the SC cycles, which leads to the fusion of the top Al inducing cracks into the thick oxide.

Introduction

After years of research on device physics and manufacturing technology, silicon-carbide (SiC) power semiconductor devices have become key devices for future power electronics applications, e.g., railway traction, electric vehicles, and power grids [START_REF] Fabre | Characterization and implementation of dual-SiC MOSFET modules for future use in traction converters[END_REF]. The SiC thermal and physical properties make this material more attractive that can far exceed the performance of Si counterparts (i.e. high electric field strength, thermal conductivity and electron velocity) [START_REF] Millan | A survey of wide bandgap power semiconductor devices[END_REF].

SiC MOSFETs have been commercialized since 2011 and show promising performance when considering static losses, fast switching, high voltage and high temperature operations in power conversion applications [START_REF] Hazra | High Switching Performance of 1700-V, 50-A SiC Power MOSFET over Si IGBT/BiMOSFET for Advanced Power Conversion Applications[END_REF]. However, the long term reliability of these devices has not been fully established especially the reliability under abnormal operating conditions, such as short-circuit (SC) [START_REF] Ceccarelli | A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis[END_REF][START_REF] Reigosa | A short-circuit safe operation area identification criterion for SiC MOSFET power modules[END_REF]. Various studies have reported that silicon-based devices have proven to be more reliable than SiC MOSFETs, under SC conditions due to higher current density and the thinner gate oxide of SiC MOSFETs [START_REF] Nguyen | Gate Oxide Fig. 12. ILD-crack and Al-gate-Poly fusion[END_REF][START_REF] Ionita | Comparative assessment of 3.3kV/400A SiC MOSFET and Si IGBT power modules[END_REF]. According to the literature, two main failure mechanisms under single-event SC stress have been observed until now [START_REF] Ceccarelli | A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis[END_REF][START_REF] Reigosa | A short-circuit safe operation area identification criterion for SiC MOSFET power modules[END_REF][START_REF] Nguyen | Gate Oxide Fig. 12. ILD-crack and Al-gate-Poly fusion[END_REF][START_REF] Ionita | Comparative assessment of 3.3kV/400A SiC MOSFET and Si IGBT power modules[END_REF][START_REF] Jiang | Failure modes and mechanism analysis of SiC MOSFET under short-circuit conditions[END_REF]: thermal runaway and gate oxide damage. The first mechanism is induced by extreme heat build-up in depletion regions within a short time period, leading to a drain-to-source holes generation and BJT triggering visible by a drain -source breakdown. The second mechanism is characterized by structural damage (e.g. crack) in the gate structure leading to a gate-to-source breakdown and the appearance of permanent gate leakage current [START_REF] Reigosa | Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs[END_REF].

Furthermore, it has been reported that the failure mechanism is highly related to the dissipated power density [START_REF] Romano | A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs[END_REF]. This power density could be impacted by many parameters such as the gatesource voltage, DC-link voltage, pulse time duration and junction temperature of the device [START_REF] Ionita | Short-circuit ruggedness assessment of a 1.2 kV/180 A SiC MOSFET power module[END_REF]. SiC MOSFETs have to face different faults during it lifetime. Hence, the interest in performing repetitive SC test that enhances the different failure mechanisms and also provides more insight about the degradation process. Hence, the interests in performing repetitive SC tests reflecting the influence of a single SC event and also providing more valuable insights about the degradation process [START_REF] Maxime | Electrical performances and reliability of commercial SiC MOSFETs at high temperature and in SC conditions[END_REF].

In this context, the aim of this paper is to analyze the effect of gate-source voltage depolarization and pulse time duration on the electrical performance of a discrete SiC MOSFETs under repetitive SC stress. Various aging indicators are used to evaluate the robustness of SiC MOSFETs under repetitive SC stress: gate leakage current (IGSS) and drain source current (IDS). The thermal behavior during repetitive SC test is evaluated using 1D electro-thermal-metallurgical model simulation. The paper is organized as follows: section II presents the device under test and the SC test setup. In section III, the results of the repetitive SC tests are discussed. Electro-thermal-metallurgical model simulation is presented in section IV.

Experimental setup

The devices under test are commercially available 2 nd generation planar SiC MOSFETs rated at 1200V/36A (ref.

C2M0080120D), manufactured by CREE [START_REF] Cree | D-SiC MOSFET Datasheet[END_REF] and packaged in TO247 case. The experiments are carried out on the bench describe in Fig. 1 [START_REF] Boige | Ensure an original and safe "fail-to-open" mode in planar and trench power SiC MOSFET devices in extreme shortcircuit operation[END_REF]. This bench provides an interface allowing users to set various SC test conditions such as various drain-source voltage (VDS), gate-source voltage (VGS), and short circuit duration (TSC) values. The SC test is conducted with series of SC cycles frames with a dead time of 3s avoiding the average overheating of the chip and allowing a threshold voltage (VGSTH) stabilization. For each last cycle of the SC test frame, VDS, VGS, buffer voltage (VBUFFER), IGSS IDS waveforms are recorded. The repetitive SC test is stopped when VGS drops around 15% showing clear gate damage.

Device capability under repetitive SC stress

Repetitive SC tests have been performed at room temperature under two protocols. The first protocol aims at studying the effect of VGS on the robustness of SiC MOSFETs under repetitive SC test. The second protocol is conducted to evaluate the impact of reducing TSC on the robustness of SiC MOSFETs under repetitive short-circuit.

First protocol

For the first protocol, repetitive SC tests are conducted on two DUTs at VDC=600V and TSCmax-1µs. TSCmax is the maximum pulse duration before the device failure under single-event SC test. For two fresh devices, TSCmax was experimentally investigated for 2 values of VGS: VGS=20V and VGS=10V, which leads to preserve a secure failure mode (FTO) approved by the authors [START_REF] Jouha | Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization[END_REF]. It has been found that TSCmax=6µs and TSCmax= 23µs for VGS=20V and VGS=10V respectively. These results are used to select the suitable testing conditions for the repetitive aging SC tests. Several tests have been led and for this study, gate-source polarization and SC duration are fixed at VGS=20V, TSC=5µs for DUT#1 and VGS=10V, TSC=22µs for DUT#2, where theses operation conditions show an important gate leakage current before failure. Fig. 2 depicts the VBuffer and VGS waveforms for repetitive SC tests on DUT#1 and DUT#2.

The SC tests show that devices DUT#1 and DUT#2 exhibit similar degradations at various VGS biases. For both devices, VGS drop can be observed starting from 300 SC cycles after delayed gate-crack at turn-off, excepted for DUT#1 at end cycling. This shift becomes more significant at 400 cycles (@ 80% of DUT#1 and @ 75% of DUT#2). The VGS decrease is due to an increase of permanent IGSS which becomes more important as the number of SC cycles increases, as illustrated in Fig. 3. The resulting leakage current is due to occurrence of cracks, and diffusion of metal (aluminium, Al) through interlayer dielectric (ILD) region leading to the partial shorting of the gate and source terminals. A thermal modelling and simulation of the chip temperature will be performed in section 3 in order to support this hypothesis. Fig. 4 shows a reduction of IDS as the number of repeated SC increases, especially after 300 cycles, which is in agreement with the decreasing of VGS. It can be noticed for each cycle that at the beginning of the gate pulse, IDS rises rapidly to a peak value then it keeps decreasing during the stress time due to the increase of junction temperature. By comparing the variations of VGS, IG and IDS of the DUT#1 and DUT#2, it can be noticed that the two devices present the same shifts from the same number of cycles whereas the power density is 2.9 kW/mm² for DUT#1 and 0.9 kW/mm for DUT#2 (Table 1). However, the degradations are emphasized for the DUT#1, at end of cycling more than 300 cycles with gate-crack during pulse, which is subjected to a higher gate polarization (VGS=20V) and a power density 3 times higher than DUT#2. It can be concluded that the VGS depolarization and the low power density applied do not have a direct and great beneficial impact on the number of cycles at which degradation appears considering each TSCmax value in the two cases.

Table 1 presents a summary of dissipated power and critical energy of DUT#1 and DUT#2 after the first cycle and the last cycle. For the two stressed devices (DUT#1 and DUT#2), a decrease in the dissipated power density and the critical energy(EC) can be noticed between the first cycle and last cycle. The DUT#1 has a higher dissipated power density compared to DUT#2, because the VGS applied on DUT#1 is twice higher than the one applied on DUT#2. However, DUT#2 has a higher critical energy EC since its SC duration TSC is longer.

Second protocol

For the second protocol, repetitive SC aging stress is performed at TSC= (TSCmax-1µs)/2 which presents typically the maximum duration, for designer, in order to ensure the gatedriver protection. The SC stress is conducted at room temperature on two devices, DUT#3 and DUT#4, with VDS=600V. VGS and the TSC are fixed at (10V, 12µs) and (20V, 2.5µs) for DUT#3 and DUT#4 respectively. Fig. 5 presents the experimental waveforms of VBUFFER and VGS of DUT#3 and DUT#4. It can be noticed that VGS is stable for DUT#4. However, the DUT3 shows a slight decrease of VGS at 600 cycles due to the increase of permanent gate leakage current as shown in Fig. 6. The drop of VGS and the increase of IG is in correlation with the decrease of IDS as shown in Fig. 7.

Table 2. summarizes the results of dissipated power density and critical energy of DUT#3 and DUT#4 after the first cycle and the last cycle (1000 cycles). Table 2 shows a decrease in the dissipated power and the critical energy (EC) for the DUT#3 at 1000 cycles. Therefore, for DUT#4, the critical energy is stable and a small variation of the dissipated power is noticed between the first cycle and the last cycle (1000 cycles). It can be noted that gate depolarization allows the SiC devices to approach IGBT robustness levels with 1000 cycles @10µs "Hard-Switch Fault" (HSF), which is not possible at its nominal gate polarization.

Electro-thermal-metallurgical model simulation

High VGS polarization Effect

The electro-thermal-metallurgical model developed in [START_REF] Richardeau | Circuit-type modelling of SiC power Mosfet in short-circuit operation including selective fail-to-open and fail-to-short modes competition[END_REF] is used to simulate the thermal behavior of studied devices under repetitive short-circuit test. This model considers the temperature dependency of thermal conductivity and mass heat of the SiC and Al metal, as well; the solid-liquid phase transition of the upper Al layer. Using Comsol™ software, IDS(t) is used as input data with a constant VDS value of 600 V. However, this model does not take into account the structural damage of the metal-oxide region in the thermal simulation between the first cycle and the last cycle. It is our belief that the decoupling is acceptable in this respect because the cracks in the oxide are very small size compared to the geometries of a cellular region. Fig. 8 presents the temperature of the main chip layers during the short circuit time, for the first and last cycle using DUT#1 under VGS=20V and Tsc=5µs. The simulation results of the first cycle (#1) illustrated in Fig. 8a shows from 4µs that the temperature on the top layer of the Al reaches the start point of the metallurgical phase transition (solid-liquid). However, it should be noted that the pulse is very short. Moreover, the end of the short circuit appears just after 1µs (tPW=5µs) which leads to a partial melting of the layer. In fact, it is clearly shown that during this 1µs time slot, the metal layer temperature forms a plateau which shows a transient phase of latent heat accumulation of the metallurgical phase transition. Furthermore, at the end of the pulse (tPW=5µs), the Al layer still seems to be in a phase transition regime since the temperature on top layer of the Al did not change and did not follow the temperature increase on the bottom layer of the Al. Afterwards, the accumulated energy over 1µs is released during the following microsecond, leading to the solidification of the whole Al layer. Through a thermo-mechanical stress point of view, it is obvious that the estimated temperature of the metal top is above 600K, which leads to the mechanical rupture of the ILD -SiO2 to 1.4GPa, by compression to the Al layer on the top of SiO2 [START_REF] Liu | Gate Failure Physics of SiC MOSFETs Under Short-Circuit Stress[END_REF]. At cycle #400, as illustrated in Fig. 8b, the simulation shows the lack of the Al layer melting even if the device continues its ageing. This is related to IDS decrease which is propositional to the power density reduction causing the metal temperature fails to reach the Al melting level. However, as indicated previously this level is still sufficient to exceed the critical limit of 600K and the mechanical failure of the ILD in which molten Al could have infiltrated at the beginning of cycling.

High VGS depolarization effect (VGS=10V)

Fig. 9 presents the estimated temperature of the main chip layers during the short circuit time for the first and the last cycle using DUT#2 under VGS=10V and TSC=22µs. The simulation shows the same behavior as for DUT1# under VGS=20V and VDS=600V. Consequently, the VGS depolarization does not show any benefits on SiC MOSFET capabilities submitted to repetitive short-circuit.

Short circuit duration effect

The device DUT#3 (VGS=10 V and TSC=12µs) shows different behavior of the estimated temperature as presented in Fig. 10. The simulation does not show the same behavior as for DUT1# under VGS=20V and VDS=600V because the maximum junction temperature does not reach the level of Al solid-liquid phase transition at 960K, yet the device shows ageing signs (such as VGS drops). This result deserves to be consolidated by further works including thermo-mechanical simulation. It may be suggested that the main gate-degradation condition is related to the oxide rupture at around 600K, without the necessity to reach the melting temperature of aluminum. In such conditions, it can probably deform the oxide and let aluminum penetrates cracks by compression of metal and epoxy resin. An additional condition is that mechanical deformation time constants have to be respected. Indeed, at low power density a slower temperature rate allows longer duration for cracks initiation to form completely deep down. The simulation shows that at cycle #1000 the temperature remains above 600K which is well confirmed by an ageing of the oxide. For both simulation cases, the temperature of top metal always exceeds the limit of the mechanical failure of the ILD-SiO2.

However, in Fig. 11, the estimated temperature during the short-circuit time for DUT#4 (VGS=20V and TSC=2.5µs) does not present any variations between the first and the last cycle (#1000) while the temperature is still above 600K the considered SiO2 strength. It should be noted that the pulse duration is 4.8 times shorter (2.5µs vs. 12µs) and we can therefore hypothesize that the formation of gate damage is governed by a time constant and probably also a threshold effect which is not reached in the 2.5µs pulse case Therefore, no-visible degradation has been observed for this device which shows the benefit of reducing TSCmax-1µs to (TSCmax-1µs)/2 at VGS=20V.

Imaging -Failure mode analysis

To confirm the assumptions on the failure mode type and also to provide a more detailed technological analysis, we carried out a failure analysis of aged DUT#2 @Vds=600V / Vgs=10V / Tsc=22µs, @Ncyle #500 as illustrated in Fig. 9b). Fig. 12 a) shows a magnitude Lock In Thermography analysis (LIT) @26Hz on one of the two failure zones on the surface along a gate line, localized close one edge of the chip. Through a phase mode of the same LIT analysis, we have chosen to further analyze the zone with the most intense and rapid heating. Fig. 12b) shows an example of micro section, FIB and MEB analysis in the cross-sectional plane of the gate line zoom. The presence of significant through cracking of the ILD between the Al source plan and the polysilicon gate contact is clearly demonstrated, as well as a possible melting region between the gate polysilicon and the aluminum layer.

Conclusion

This paper presents the impact of repetitive short-circuit operation on a commercial SiC MOSFET. The device performance under repetitive stress is analyzed under two protocols. The first one aims at studying the effect of the gatesource voltage (VGS) and the second one aims to evaluate the impact of the SC duration (TSC) reduction.

The first approach (VGS depolarization) at (TSCmax-1µs) shows that, despite this technique ensured a safe failure mode (FTO) and a short circuit duration exceeding 10µs, has no beneficial impact on the number of cycles for the degradation initiation. Since these degradations occur for high and low VGS (VGS=20V and VGS=10V) at the same number of cycles. The aged devices at repetitive SC test under low TSC ((TSCmax-1µs)/2) shows obviously a better robustness compared to ((TSCmax-1µs).

The simulation results highlight two main degradation behaviors. Both degradations are related to thermal stress. The first one is initiated when the temperature reaches around 600K which is related to the mechanical failure at the ILD-SiO2. The second one is related to metallurgical phase transition where the junction temperature reaches the Al melting, leading to partial cracks short between gate-source terminals (shorting gatesource). The ageing of the gate at (Tsc-1µs)/2 can also occur even if the source metal has not reached the melting temperature as we can see when VGS voltage drops. Hence the need to monitor other electric parameters such as gate source capacitance (CGS-VGS) and static gate leakage current (IGSS) to have other degradations signatures and reveal the failure mechanism.

Fig. 1 .

 1 Fig.1. Schematic of Type 1 short-circuit test[START_REF] Boige | Ensure an original and safe "fail-to-open" mode in planar and trench power SiC MOSFET devices in extreme shortcircuit operation[END_REF]

Fig. 4 .

 4 Fig. 4. Experimental waveforms of IDS under VDS=600V and TCASE=25°C for: (a) DUT#1 and (b) DUT#2.

Table 1 .

 1 Summary of dissipated power and critical energy of DUT#1 and DUT#2 at the first and last cycle. (First cycle)0.740 (First cycle) 0.352 (400 cycles) 0.530 (500 cycles)

Fig. 5 .Fig. 6 .

 56 Fig. 5. Experimental waveforms of VBUFFER and VGS under VDS=600V and TCASE=25°C for: (a) DUT#3 and (b) DU#T 4.

Fig. 7 .

 7 Fig. 7. Experimental waveforms of IDS under VGS=600V and TCASE=25°C for: (a) DUT#3 and (b) DUT#4. Table 2. Summary of dissipated power and critical energy of DUT#3 and DUT#4 at the first and last cycle. DUT#3 (VGS=10V,TSC=12µs) DUT#4 (VGS=20V,TSC=2.5µs)

Fig. 8 .

 8 Estimated temperatures of the main chip layers under Comsol for the DUT#1 at VDS=600V, VGS=20V and TCASE=25°C: (a) first cycle and (b) last cycle (#400).

Fig. 9 .

 9 Fig. 9. Estimated temperature of the main chip layers under Comsol for the DUT#2 at VDS=600V, VGS=10V and TCASE=25°C: (a) first cycle (b) last cycle (#500).

Fig. 10 .

 10 Fig. 10. Estimated temperature of the main chip layers under Comsol for the DUT#3 at VDS=600V, VGS=10V and TCASE=25°C: (a) first cycle (b) last cycle (#1000).

Fig. 11 .

 11 Fig. 11. Estimated temperature of the main chip layers under Comsol for the DUT#4 at VDS=600V, VGS=20V and TCASE=25°C: (a) first cycle (b) last cycle (#1000).

Acknowledgments

We thank the team of experts from the ITEC Lab, THALES, Toulouse, France for the failure analysis of SiC Mosfet power devices by LIT-FIB-MEB analysis.