Detector Power Supply Switch Signal Generator Phase Error Detecor AC Switch Ch3 (blue): Output signal of the error amplifier used in AGC VEAOUT

Keywords: Ultrasonic transducer, HIFU, Automatic impedance tuning, Switched capacitor, Ultrasonic power supply, Half-bridgeClass D amplifier Ultrasonic transducer, HIFU, Automatic impedance tuning, Switched capacitor, Ultrasonic power supply, Half-bridge Class D amplifier

High intensity focused ultrasound (HIFU) technology is now broadly used for cancer treatment, because of its non-invasiveproperty. In a HIFU system, a phased array of ultrasonic transducers is utilized to generate a focused beam of ultrasound (1M~10MHz) into a small area of the cancer target locations within the body. Most HIFU system are guided by magnetic resonance imaging (MRI) in nowadays. In this paper, a half-bridge class D power amplifier and an automatic impedance tuning system are proposed. Both the class D power amplifier and the auto-tuning system are compatible with MRI system. The proposed power amplifier is manufactured by using of printed circuit board (PCB) and discrete components. According to the test results, the proposed power amplifier has a power efficiency of 82% with 3 W output power at 1.25 MHz working frequency. The automatic impedance tuning system proposed in this paper is designed in two versions: a PCB and an integrated circuit version. Unlike the typical auto-impedance tuning networks, it is no need of microprogrammed control unit (MCU) or computer in the proposed design. Besides, without using bulky magnetic components, this auto-tuning system is compatible with MRI equipment. The PCB version is designed to verify the principle of the proposed automatic impedance tuning system, and it is also used to help the design of the integrated circuit. The surface area of the PCB auto-tuning system is 110cm 2 . The test results confirmed the expected performance. The proposed auto-tuning system can perfectly cancel the imaginary impedance of the transducer, and it can also compensate the impedance drifting caused by unavoidable variations (temperature variation, technical dispersion, etc.). The integrated auto-tuning system is realized by using CMOS process (C35B4C3) provided by Austrian Micro Systems (AMS). The die area of the integrated circuit is only 0.42 mm 2 . This design provides a wide operation frequency range with a very low power consumption (137 mW). The power efficiency improved by using this auto-tuning circuit is 20% compared with the static tuning network.

Les chronogrammes de sortie de demi-pont V HB et sortie de l'amplificateur de puissance V OUT sont dé montré s dans la Figure 3. Selon les ré sultats du test, il a rendement de conversion en puissance de 82%, quand le circuit est bien accordé , pour une puissance de sortie conç ue de 1.25W avec une fré quence de travail de 3MHz.

Le systè me d'accord automatique d'impé dance proposé a é té conç u en deux versions: une version en PCB et une version en circuit inté gré (IC). Contrairement aux systè mes d'accord automatique proposé s dans la litté rature, il n'y a pas besoin de l'unité de microcontrôleur (MCU) ou de l'ordinateur dans la conception proposé e. D'ailleurs, sans l'aide de composants magné tiques volumineux, ce systè me d'auto-ré glage est entiè rement compatible avec l'é quipement IRM.

Le sché ma de principe de systè mes d'accord automatique, qui est basé sur le condensateur commute synchrone, est repré senté dans la Figure 4. La variation de capacité est obtenue en faisant varier le rapport cyclique de conduction d'un interrupteur bidirectionnel (AC switch) en respectant les conditions de synchronisation indiqué es dans les chronogrammes repré senté s Figure 5. Si ces conditions sont respecté es, on montre alors que la fonction de transfert de la capacité commutée s'écrit :

𝐶 𝐸𝑄 = 𝐶 𝑆 • 𝑠𝑖𝑛 [ 𝜋𝑉 𝑂𝐸𝐴 2𝑀𝑎𝑥(𝑉 𝑇𝑟𝑖𝑔 ) ] (2)
Avec V OEA = tension de commande, αV CFix = amplitude de le signal utilisé e pour gé né rer la commande PWM. Pour garantir la stabilité du systè me, αV CFix est un signal sinusoï dal avec l'ampleur constant. Il a aussi la mê me phase et la fré quence que le signal de sortie de l'amplificateur de puissance. En portant ce résultat dans l'expression [START_REF] De Geronimo | Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration[END_REF], on obtient finalement une fonction de transfert liné aire de la forme:

𝐶 𝐸𝑄 = 𝐶 𝑆 𝑉 𝑂𝐸𝐴 [𝛼𝑀𝑎𝑥(𝑉 𝐶𝐹𝑖𝑥 )] ⁄

(3) Contrairement à la solution traditionnel, cette mé thode de liné arisation a permis de réaliser un système d'accord automatique relativement simple et performant.

Le sché ma de systè me à condensateur commuté synchrone pour l'exé cution de l'auto tuning est illustré dans la Figure 6. Le systè me de syntonisation automatique à l'aide d'un condensateur commuté synchrone est dé limité par le polygone de vert. Afin de faciliter son analyse, l'auto-ré glage system a é té partitionné en pointillé s. Comme il peut ê tre vu de cette figure, l'auto-ré glage systè me proposé dans ce document se compose de cinq blocs fonctionnels: Bloc de ré glage, bloc de commande automatique de gain, bloc de dé tection d'erreur de phase, bloc de gé né ration d'un signal d'interrupteur et bloc de commutateur AC. La version en PCB a é té conç ue pour vé rifier le principe du systè me proposé , et il est é galement utilisé pour guider à la conception du circuit inté gré . La ré alisation en PCB occupe une surface de 110cm 2 . Le prototype de l'auto-ré glage system est illustré dans la Les ré sultats des tests du gé né rateur d'ultrasons avec le carte du circuit d' auto-ré glage est illustré dans la Figure 9. Les ré sultats des tests ont confirmé la performance attendue. Le systè me d'auto-ré glage proposé peut parfaitement annuler l'impé dance imaginaire du transducteur, et il peut é galement compenser l'impé dance de la dé rive causé e par les variations iné vitables (variation de tempé rature, dispersion technique, etc.).

La conception du systè me d'auto-ré glage en circuit inté gré a é té ré alisé avec une technologie CMOS (C35B4C3) fournies par Austrian Micro Systems (AMS). La surface occupé e par le circuit inté gré est seulement de 0,42mm 2 . Le post-layout de l'auto-ré glage system en circuit inté gré est illustré dans la Figure 10. Les ré sultats des tests du gé né rateur d'ultrasons avec l' auto-ré glage circuit en circuit inté gré est illustré dans la Figure 12. 2. It is easily fabricated into different shapes (e.g., round, ring, and rectangle)

3. It has a stable performance and is very cheap for large-scale applications.

The ultrasonic transducers that were studied and used in this paper are piezoelectric transducers.

Ultrasonic Power Supply

An ultrasonic power supply, or ultrasonic generator, is a device that can provide a suitable power supply for ultrasonic transducers [DS2011]. Generally, an ultrasonic power supply consists of three parts: a signal generator, power amplifier, and an impedance-tuning network. The signal generator is used to produce a signal with a specific frequency which is equal to the working frequency of the transducer. Then this signal is amplified by the power amplifier. And the amplified signal is applied to the ultrasonic transducer, which is well matched by the impedance tuning network. The signal used in an ultrasonic power supply is usually a sinusoidal or a pulse signal.

Currently, there exist two types of ultrasonic power supply, namely separate excitation and self-excitation [YY2014]. The difference between these two types of power supply is capability of frequency tracking. The separate-excitation ultrasonic power supply is composed of an oscillator circuit and a power amplifier [YY2014, HE2013], while the self-excitation ultrasonic power supply consists of an oscillator circuit, a power amplifier, a frequency-tracking circuit, and a power-control circuit. The transducer can reach its highest efficiency in its resonant state. However, unavoidable variations (temperature drifting, load variation, etc.) change the resonance frequency of the transducer. The frequency-tracking circuit is used to guarantee that the transducer is functioning at resonance. Moreover, the power-control circuit is applied to stabilize the output power of the transducer [HE2013].

The development of a power amplifier, which is used in ultrasonic generators, has gone through two phases: analog power amplifier and switched power amplifier.

Analog amplifiers, such as class A, class B, and class AB amplifiers, are all suitable for ultrasonic power supplies. However, several disadvantages limit their usage

[RJW2014]:

1. Low power efficiency: The maximum theoretical efficiencies of class A, B, and AB amplifiers are 50%, 78.5%, and 78.5%, respectively.

High working temperature:

There must be a cooling facility for the amplifier.

3. Hard to control: Because they are all analog amplifiers, it is difficult to control the output power and frequency.

Switched-mode amplifiers, such as class D, class E, and class DE amplifiers, are also suitable for transducers. The efficiencies of switched-mode amplifiers are all higher than those of analog amplifiers. The theoretical efficiencies of class D, E, and DE amplifiers are all 100%. Besides, the output power of switched amplifiers can be controlled very easily [BB2006]. The topologies of analog amplifiers and switched amplifiers will be discussed in chapter 3.

Impedance-tuning Network for Transducers

Impedance-tuning networks are required in ultrasonic applications because the output impedance of an ultrasonic power supply and the characteristic impedance of parallel coaxial lines are all pure resistive. Further, ultrasonic transducers are usually reactive components [GRM2010]. If a transducer is driven directly by ultrasonic power, there will be a reflected power that will cause an increase in the temperature of the transducer. When the temperature exceeds a certain value, the transducer will encounter unrecoverable damage. Therefore, in an ultrasonic power supply, the impedance-tuning network should be properly designed to resolve the mismatch between the power supply and transducer.

Two main kinds of impedance-tuning techniques are used for ultrasonic transducers, namely static tuning and dynamic tuning. The static impedance-tuning technique uses a vector network analyzer to measure the impedance value of the transducer. Then, based on the impedance characteristic of the transducer, the parameters of the components used in the static-tuning network are selected based on the measured impedance [HH2011]. These parameters will remain constant during its operation. The static impedance-tuning network can be subdivided into three types based on the form: inductor-tuning network, capacitor-tuning network and inductor-capacitor tuning network. The static-tuning method has a very simple structure and is very easy to implement. However, this method cannot compensate for the impedance and resonance-frequency drifting of the transducer during operation. These unavoidable fluctuations will lead to an impedance mismatch, which can result in an increase in the temperature and damage to the transducer. In addition, the parameters of the tuning network are calculated based on the approximate model of the transducer.

Therefore, these calculated parameters may deviate far from the theoretical value. To adjust the tuning parameters, the dynamic impedance-tuning network uses a feedback signal, which is generated by an impedance-detector circuit [MGJF2012, DDR1998]. In this way, the transducer can always work under its resonance state.

The topologies of impedance-tuning networks for transducers will be discussed in chapter 2. Nowadays, two types of imaging techniques are used to guide HIFU operations, namely diagnostic ultrasound and magnetic resonance imaging (MRI). The diagnostic ultrasound technique uses the high frequency sound waves that travel from the ultrasound probe through human tissue. Some of the sound waves bounce back to the transducer. This reflected sound is used by a computer to form the ultrasound image.

History of HIFU

And MRI is one of the newest and most technically elegant examinations ordered. The scan relies on the use of a large magnet and radio transmitters and receiver to visualize the atoms of the body. Ultrasound-guided focused ultrasound (USgFUS) was the most popular method for HIFU operation. The photo of a real USgFUS is shown in Figure 1.2 (left). It can provide anatomical imaging during surgery, and can offer a rough figure of temperature. And the using of diagnostic ultrasound makes the system very cheap and easy to realize. However, the motion of the tissue that is illustrated by diagnostic ultrasounds is degraded, and because of interference between the diagnostic system and HIFU, the real image of the tissue component is covered by fog artifacts [BJ2004-LD2008]. This leads to a negative effect on the safety and effectiveness of HIFU therapy. Currently, the most innovative area of HIFU research is MRI-guided focused ultrasound (MRgFUS). The picture of an MRgFUS is shown in Figure 1.2 (Right). MRI systems can offer excellent soft-tissue contrast, 3D imaging capabilities, and real-time temperature measurement [CHE1995].

Motivation and Objective

In a HIFU system, the designed transducer array is utilized to focus a beam of ultrasound (1 MHz ~ 10 MHz) energy into human organs with small tissue volumes, such as the breast, kidney, and liver. The focused beam causes localized high temperatures (45 ~ 90°C) in a small region, which will ablate the target tissues without the need for an incision [ZYF2011]. Ultrasonic power generators are the most important components in a HIFU system.

Power generators should have the capability to generate enough power for the transducers. In this case, the energy at the focal point can kill the target cancer in a very short time without causing damage to the transducer for long-term treatment. Moreover, sophisticated multi-element ultrasound transducer arrays usually have over a hundred elements, and the size of the ultrasonic generator should be considered. Therefore, the design of ultrasonic power generators for HIFU systems has become a very interesting area of study.

The objective of this thesis is to design a power amplifier and a novel automatic impedance tuning network for transducers in MRgFUS. The main challenges of this thesis are as follows:

1. The size of the power amplifier and the automatic impedance tuning network should be as small as possible.

2. MRgFUS is an MRI-guided HIFU. Therefore, the use of large magnetic components, such as a ferromagnetic-core or iron-core inductors and transformers, should be eliminated in both the power amplifier and the impedance-tuning network.

3. To avoid overheating, the amplifier must have a very high efficiency, and the automatic impedance-tuning network should have a high accuracy.

4. The power that is required by the transducer is 3 W, and the peak-to-peak voltage of the power supply is required to be about 260 V.

5. The resettling time of the automatic impedance-tuning network should be as small as possible to eliminate the reflected power and protect the transducer.

Outline

This thesis consists of eight chapters:

In chapter 1, we introduce the background, the motivation, and the objective of this thesis. In the first section, we describe the concept of the ultrasound transducer, ultrasonic power supply, and impedance-tuning network. We also present a historical review of HIFU in this section. Then, we present the research purpose and the main goals of this thesis in the second section. Finally, we present the organization of this thesis.

Chapter 2 presents a model of the transducer that we used in our project, and it reviews several existing impedance-tuning techniques. The characterization of the ultrasound transducer and the equivalent circuit are given in the first section, while details regarding several existing impedance-tuning techniques will be introduced in the second section.

In chapter 3, we present an analysis of the topologies of existing power amplifiers that can be used in HIFU applications, and explain the theory and the circuit design of the power amplifier proposed in this thesis. It begins with the principles of five typical power amplifiers. Then, it focuses on the presentation of the published works involving these power amplifiers. Finally, we present a half-bridge class D amplifier with a square-wave input. The simulation and the test results of the power amplifier are also presented in this chapter.

Chapter 4 covers the theory of the automatic impedance-tuning network that was designed in this thesis. In this chapter, we also explain the impact of temperature drifting and technological dispersions on transducer's impedance. The diagram of the proposed realization is also given in this chapter. In this thesis, we present two versions of circuit design: the discrete-component circuit version and the integrated-circuit version. In chapter 5, we focus mainly on the discrete version of the auto-tuning network. Then, in chapter 6, we explain the integrated-circuit design.

Chapter 5 mainly focus on the printed circuit design of the auto-tuning system. The automatic impedance-tuning system proposed in this thesis consists of three parts: an automatic gain amplifier, a phase-error detector, and a pulse-width modulation (PWM) signal generator. Circuit designs of the sub-blocks are presented in the first section.

Then test results of the designed circuit are presented in the second section. The stability analysis is also presented in this chapter.

In chapter 6, we present the integrated-circuit design of the auto tuning system. In the first section, we present an integrated automatic gain amplifier that is suitable for our application. Then, we introduce a phase-error detector, which is realized by using integrated circuit. Finally, we present an integrated switched signal generator. The simulation results and the test results of the integrated circuits are also presented in this chapter. At the end of this chapter, the layout design and the post-layout simulation results are given out.

Chapter 7 shows the test and simulation results of the ultrasonic power supply obtained using the different versions of auto-tuning systems presented in this thesis. We also discuss the experimental environment that was used to test or simulate the circuit.

In chapter 8, we conclude this thesis and present a summary of the contributions that were realized from this thesis. Future research goals are also presented in this chapter.

Chapter 2

Transducer Modeling and Tuning

Introduction

High-power ultrasonic piezoelectric transducers are used in the development of ultrasound generators in HIFU applications. In ultrasonic applications, there usually exist detuning problems. The output impedance of the ultrasonic power supply and the characteristic impedances of parallel coaxial cables are all purely resistive. However, ultrasonic transducers are usually reactive components. Therefore, the design of an ultrasonic power supplies should include an impedance-tuning network to solve these problems.

In this chapter, we describe the modeling of the piezoelectric transducer. We also present the equivalent circuit for the transducer used in our project. Then, after modeling the transducer, we review the impedance-tuning topologies and several existing automatic impedance-tuning theories. A backing layer, which comprises an epoxy loaded with powder, is applied behind the piezoelectric active element. The density and acoustic impedance of the backing layer can be adjusted by using different materials [NVMD2003].

Modeling of Ultrasonic Transducer

Mathematical Model

Because the most important part of an ultrasonic transducer is the piezoelectric active element, the modeling of ultrasonic transducer can be simplified as a model of a piezoelectric active element. And the piezoelectric element can be considered as an electromechanical vibration system [GM1997]. In order to realize an equivalent circuit based on the electrical model and mechanical model, the mechanical parameters are transferred to equivalent electrical components. The transformation formulas are tabulated in Table 2.1.

2.12

The admittance at the mechanical resonance frequency can be simplified as, 𝑌 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 = 𝑗𝑤 𝑚 𝐶 𝑃 + 1 𝑅 𝑚

2.13

In order to obtain the general frequency characteristic of the piezoelectric active element, as well as simplify the calculation, we introduce a normalization Ω = w/w m into Equation 2.12 as follows.

𝑌 𝐸𝑞 (𝑗𝛺) = 𝛺 𝛽•√𝐿 𝑚 𝐶 𝑚 ⁄ • (𝛼𝛽 2 𝛺+𝑗•((𝛼𝛽𝛺) 2 +(1-𝛺 2 )•(1+𝛽-𝛺 2 ))) (𝛼𝛽𝛺) 2 +(𝛺 2 -1) 2

Calculations of the Model Parameters

Usually, ultrasonic transducers have several resonance frequencies. In other words, the series resonant branch of the equivalent circuit consists of several subordinate branches. Moreover, it can be observed that excitations at frequencies that are even multiples of the natural vibrating fundamental frequency, i.e., ω 2n = nω o = n2πf o , where n is even and f o is the first resonance frequency, do not cause a displacement at the ends of the piezoelectric material [VAA2008]. Thus, the series resonant branches can be simplified by removing all of the even branches.

Equations 2.10, 2.11, 2.19, and 2.20 are applied at the series and parallel resonance frequencies, which are given by the transducer manufacturer, to calculate the value of the electrical components of the equivalent circuit. In our study, the operation frequency is less than 2 MHz. Therefore, we calculated the equivalent circuit of the piezoelectric transducer up to the third harmonic.

However, additional resonant frequencies can be found during the measurement because a piezoelectric resonator is a three-dimensional (3D) object [VAA2008]. These non-harmonic frequencies do not correspond to harmonics or multiples of the fundamental frequency. In order to obtain a more accurate model, we use the Matlab program to approach the measurements. Although other kind of software can be used here to perform the approaching, the Matlab provides the simplest way of approaching.

The equivalent circuit and values of the components are shown in Figure 2.5. The odd harmonics are a set of resonant frequencies that are based on odd multiples of the fundamental resonant frequency, and depend on the thickness and physical properties of the piezoelectric material [GTR1985]. As shown in Figure 2.5, the variable C P denotes the static capacitor. Components L m1 , C m1 , and R m1 comprise the fundamental branch. Similarly, L m3 , C m3 , and R m3 represent the third harmonic branch, and L ms , C ms , and R ms represent the non-harmonic frequency branch.

Based on the equivalent circuit shown in Figure 2.5, the impedance of the equivalent circuit at the working frequency (1.25 MHz) of the transducer can be described as

𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑤𝑜𝑟𝑘𝑖𝑛𝑔 = 1 𝑗𝑤𝐶 𝑃 + 1 𝑍 𝑚1 (𝑗𝑤) + 1 𝑍 𝑚3 (𝑗𝑤) + 1 𝑍 𝑚𝑠 (𝑗𝑤)

2.21

It is known that Z m1 (jw) = 1/R m1 , so Z Eq (jw) can be rewritten as

𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑤𝑜𝑟𝑘𝑖𝑛𝑔 = 1 𝑗𝑤𝐶 𝑃 + 1 𝑅 𝑚1 + 1 𝑍 𝑚3 (𝑗𝑤) + 1 𝑍 𝑚𝑠 (𝑗𝑤)

2.22

By introducing the values of the components in the equivalent circuit into Equation 2.22, the equation becomes, 𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑤𝑜𝑟𝑘𝑖𝑛𝑔 = 36.65 -308.2𝑗

2.23

The equivalent circuit of the transducer can be simplified, as shown in Figure 2.6.

RSLoad=36.65Ohm XSLoad=-308.2Ohm Fig. 2.6 Simplified equivalent circuit of the ultrasonic transducer at its operational frequency.

Model Verification

We verified the Model by performing measurements of the transducer using a vector network analyzer (VNA) (Agilent N3382A). The calibration method used here is the short open load thru (SOLT). It is used to remove the parasitic effects introduced by the Bayonet Neill Concelman (BNC) connectors.

The measured impedance of the transducer and the equivalent circuit on the Smith chart are shown in Figure 2.6. As can be seen from Figures 2.7 and 2.8, the equivalent circuit of the transducer has nearly the same impedance characteristics as the measurement values.

Impedance-tuning Topologies

Based on the modeling of the transducer in section 2.2, ultrasonic transducers can be considered as reactive components. Further, the impedance of an ultrasonic power supply is pure resistive. If the transducer is driven directly by the ultrasonic power supply, the output power P OUT can be described by

𝑃 𝑂𝑈𝑇 = 𝑉 𝑃𝑖𝑒𝑧 • 𝐼 𝑃𝑖𝑒𝑧 𝑐𝑜𝑠 𝜑 2.24
where V Piez and I Piez are the driving voltage and current, respectively. φ is the phase angle between the driving voltage and the current. We can determine that the output power reaches its maximum value when φ equals to 0. φ can be defined by 𝜑 = 𝑡𝑎𝑛 -1 (𝐵 𝑃𝑖𝑒𝑧 𝐺 𝑃𝑖𝑒𝑧 ⁄ )

2.25

Where B Piez and G Piez define the electrical susceptanc and the conductance of the transducer. If B Piez ⁄G Piez = 0, the power supply can provide the maximum power.

Otherwise, there will be a reflected power that will cause a temperature rise or even unrecoverable damage to the transducer. Therefore, impedance-tuning topologies are required to balance out the susceptance of the transducer.

The impedance-tuning network can be classified as a static-tuning network and variable-tuning network based on the structure that they use [VBA2011]. For static-tuning networks, the calculated reactive components, such as the capacitor and inductor, are used to cancel the reactance part of the transducer, so the impedance of the transducer combined with the tuning network become pure resistive. The variable-tuning network is based on the static-tuning network. However, it uses a variable inductor or capacitor instead of the static ones to cancel the reactance part of the transducer, and it has a feedback signal that is used to change the value of the inductor or capacitor. The feedback signal is usually generated by an impedance-detector circuit. The variable-tuning network can solve the impedance-drifting problem of the transducer. The analysis of these two different tuning networks is presented in this section. The static impedance-tuning network can be divided into two types, series-tuning networks and parallel-tuning networks [VBA2011]. Based on the analysis in section 2.2, the equivalent circuit of the transducer can be simplified as either parallel or series. The corresponding tuning network is shown in Figure 2.12. The parallel-tuning network uses a shunted reactive component to cancel the susceptance part of the transducer. In addition, the reactive component, which has an opposite reactance to that of the transducer, is used in the series-tuning network. The parallel-tuning network is usually used for high output-impedance power supplies [VAA2008]. In addition, the introduction of a parallel-tuning network positively affects the receive voltage sensitivity (RVS), yet it has no effect on the transmitting voltage response (TVR) [SCH2007]. The series-tuning network is commonly used for low output-impedance power supplies. The use of series-tuning networks causes an increase in the TVR, while not affecting the RVS [VAA2008, SCH2007]. In our case, to ensure the power efficiency, the output impedance of the power supply is required to be as low as possible, and the transducer is used to emit acoustic waves which usually has high impedance. Therefore, in this thesis, we used the series-tuning network. The above-mentioned tuning networks usually use a single inductor or a capacitor to compensate the susceptance or reactance of the transducer.

Basic Impedance-tuning Network

However, the tuning network cannot match the resistance part of the transducer to the output resistance of the power supply. In order to match both the resistance part and reactance part of the transducer, we introduce a tuning circuit that consists of an inductor and capacitor. There are several different basic inductor-capacitor tuning networks, such as the L match, Γ match, T match, and П match. V S is the power supply and R S is the output resistance of the power supply. The characteristics of these tuning networks are shown in the following table. In our thesis, the impedance of the power supply is chosed to be less than 10 mΩ to obtain a high power efficiency. From section 2.2, we know that the impedance of the transducer is much greater than the output impedance of the power supply. The circuit can be seen as a high-low-impedance transform system. Thus, the L tuning network is suitable for our application. In this thesis, we focus mainly on the analysis of the L tuning network. Z Piez is the impedance of the transform and Z O is the output impedance of the power supply. To ensure that the impedance of the transducer is well matched to the power supply, the following equation must be true.

𝑍 𝑂 = 𝑗𝑋 𝐿 + 1 𝑗𝐵 𝐶 +1 (𝑅 𝑃𝑖𝑒𝑧 +𝑋 𝑃𝑖𝑒𝑧 ) ⁄

2.26

By solving this equation, we can obtain the following formulas:

𝐵 𝐶 (𝑋 𝐿 𝑅 𝑃𝑖𝑒𝑧 -𝑋 𝑃𝑖𝑒𝑧 𝑍 𝑂 ) = 𝑅 𝑃𝑖𝑒𝑧 -𝑍 𝑂

2.30

We can see that there are two solutions for X L and B C . When B C > 0, it is a capacitor, and where B C < 0, it is an inductor. With respect to X L , when it is greater than 0, it is an inductor, whereas when it is less than 0, it is a capacitor. In our case, the output of the power supply is a square wave. A low-pass filter is required to compensate the higher harmonics of the square wave. Thus, only the solution X L > 0 and B C > 0 can be used in our project. In other words, the LC-type L tuning network is suitable for our transducer.

As far as the variable-tuning network is concerned, it contains the components with variable values against those with constant values used in static tuning network. In addition, we applied a feedback loop to control the variation of these components.

During the working period, the temperature drift or the changing of the working The impedance-measurement circuit is divided into three different types according to the topologies: bridge method, I-V method, auto-balancing bridge method, and resonance method [NI2007]. • 𝑍 3

2.31

The advantages of the bridge method are as follows [NI2007]: High accuracy (0.1% error); wide frequency coverage by using different types of bridges (0~300MHz); low cost. However, four disadvantages make it unsuitable for our application: Needs to be manually balanced; narrow frequency coverage with a signal instrument; unfit for the grounded devices; MCU or computer is required to calculate the impedance.

The equivalent circuit of the I-V method is demonstrated in Figure 2.16(b). In a real case, the resistor R is usually replaced by a low-loss transformer to reduce the effects caused by R [NI2007]. However, the use of a transformer limits the frequency range. As can be observed from this figure, Z X can be calculated by the values of the voltage and current. The equation of Z X can be written as

𝑍 𝑋 = 𝑉 1 𝐼 = 𝑉 1 𝑉 2 𝑅 2.32
I-V method is suitable for the grounded devices. And it can also provide a real time measurement of the impedance. But the using of the transformer leads to a compatibility problems with MRI system. And the same as the bridge method, it needs MCU or computer to obtain the impedance.

Figure 2.17(a) shows the equivalent circuit of the auto-balancing bridge method.

By tuning the parameter of the R and V R , the current I X , which flows through the unknown impedance Z X , can be made equal to the current that flows through the resistor R. Then, the potential at the L point is kept at 0 V (which is called virtual ground). The impedance of Z X can be obtained by measuring the voltage at point H (V X ) and the voltage applied across R (V R ).

𝑍 𝑋 = 𝑉 𝑋 𝐼 𝑋 = 𝑉 𝑋 𝑉 𝑅 𝑅 2.33
Compared with the previous methods, the auto-balancing bridge method can provides good compatibility with grouded devices and high accuracy over a wide impdance measurement range. There is no large magnetic component used in this method. So it is well suited for the MRgFUS. However, by using this method, the unknown impedance Z X is still need to be calculated by using other parameters. In other word, a MCU is required to calculate the impedance of Z X . The equivalent circuit of the resonance method is presented in Figure 2.17(b).

When the circuit was adjusted to resonance by adjusting a tuning capacitor C, we obtained the unknown impedance values L X and R X from the test frequency, C value, and Q value. Q can be obtained by measuring the voltage applied across the tuning capacitor. Other than the direct connection shown here, series and parallel connections are possible for a wide range of impedance measurements.

For the resonance method, it has a simple structure. The measured devices is a part of the resonance circuit. And the resonance circuit can be a part of the tuning circuit.

Therefore, it can achieve an auto tuning system based on this method by adding a feedback control signal on the tunable capacitor or inductor. This method is based on the topology of resonance circuit, so the impedance of the measured components can be obtain by detecting the phase difference between the input signal and output signal of the resonance circuit. The disadvantage of the resonance method is the low impedance measurement accuracy at high operating frequency. If the operating frequency is high, there will be a distortion of the output signal. This unavoidable distortion will cause a low impedance measurement accuracy. And MCU is also required in the existing resonance impedance measurement circuits.

Summary of the Basic Impedance Tuning Networks

Although the basic impedance tuning networks provide valuable information and techniques for designing tuning network for our application, none of the existing tuning networks can offer a comprehensive solution to resolve our challenges, such as elimination of large magnetic components; compensation of impedance drifting caused by temperature, aging; small circuit surface. Hence, another approach is needed. Tables 2.3 gives out the comparation of the basic impedance tuning networks.

As analyzed in section 2.3.1, the L tuning network is suitable for our applicaton.

But it can not solve the impedance drifting of the transducer. And for the dynamic tuning networks, the resonance method is more suitable for our application than others.

It has a simple structure and the impedance measurement circuit of this method can be a part of the tuning circuit for the power amplifier. And it is suitable for realizing an auto tuning system based on this method by adding a feedback control signal on the tunable capacitor or inductor. The maximum working frequency of the resonance method is usually tens of megahertz [NI2007], which is much larger than the working frequency of the tranducer (1.25MHz). Thus, the accuracy of this method is acceptable. The only disadvantages of this method is the requirement of the MCU. So a novel auto impedance tuning system based on the resonance method will be presented in chapter 4. Power Amplifier Design

Introduction

Design of a power Amplifier for the ultrasonic transducer used in HIFU application is one of the objectives of this thesis. In this chapter, the principles of the existing power amplifiers are explained. Furthermore, the former articles about the amplifier for HIFU are reviewed and discussed. A comparison between these amplifiers is also presented in this chapter. At last, the circuit design and analysis of the power amplifier used in our project is presented. This chapter is organized as follows: Section 3.2 has a review of some typical amplifiers that can be used for our project. Section 3.3 presents several published works that relate to the design of power amplifiers for ultrasound therapy. In Section 3.4, we present a comparison of these amplifiers. Section 3.5 describes the circuit design and analysis of the proposed power amplifier. Section 3.6 gives out the prototype of the power amplifier, and the test results of this prototype is also presented in this section. Finally, a summary of the proposed power amplifier is given out in Section 3.7

Theory of Typical Power Amplifiers

Current-source Amplifiers

Current source-based power amplifiers can be classified as A, B, AB, and C based on the conduction angle and the bias. Due to the strongly non-linear behavior of the class C amplifier, it is unsuitable for our application. Therefore, it will not be discussed The waveform of the drain current in the frequency domain is illustrated in Figure 3.3.

[VAA2008] Using θ and α as the drain current angle at point x and the conduction angle, respectively, the drain current I Drain at point x can be described as in Equation 3.1.

𝐼 𝐷𝑟𝑎𝑖𝑛 (𝜃) = 𝐼 𝑄 + 𝐼 𝑠 • 𝑐𝑜𝑠 𝜃 (-𝛼 2 ⁄ < 𝜃 < 𝛼 2 ⁄ ) 3.1
And the following equations can also be easly obtained,

𝑐𝑜𝑠(𝛼 2 ⁄ ) = -(𝐼 𝑄 𝐼 𝑠 ⁄ ) and 𝐼 𝑠 = 𝐼 MAX -𝐼 𝑄 3.2
By substituting Equation 3.2 into Equation 3.1, I Drain (θ) can be rewritten as

𝐼 𝐷𝑟𝑎𝑖𝑛 (𝜃) = 𝐼 𝑀𝐴𝑋 1-𝑐𝑜𝑠(𝛼 2 ⁄ ) • [𝑐𝑜𝑠 𝜃 -𝑐𝑜𝑠(𝛼 2 ⁄ )] 3.3
The DC current I DC during the conduction period can be defined as

𝐼 𝐷𝐶 = 1 2𝜋 • ∫ 𝐼 𝐷𝑟𝑎𝑖𝑛 (𝜃)𝑑𝜃 𝛼∕2 -𝛼∕2

3.4

By solving this equation, I DC can be rewritten as Equation 3.5.

𝐼 𝐷𝐶 = 𝐼 𝑀𝐴𝑋 2𝜋 • 2 𝑠𝑖𝑛(𝛼 2 ⁄ )-𝛼•𝑐𝑜𝑠(𝛼 2 ⁄ ) 1-𝑐𝑜𝑠(𝛼 2 ⁄ )

3.5

The first harmonic I 1 of current I Drain is shown in Equation 3.6.

𝐼 1 = 1 𝜋 • ∫ 𝐼 𝐷𝑟𝑎𝑖𝑛 (𝜃) • 𝑐𝑜𝑠 𝜃 𝑑𝜃 𝛼∕2 -𝛼∕2
3.6 which can be rewritten as

𝐼 1 = 𝐼 𝑀𝐴𝑋 2𝜋 • 𝛼-sin 𝛼 1-𝑐𝑜𝑠(𝛼 2 ⁄ )

3.7

Based on Equation 3.5 and 3.7, the fundamental output power P OUT and the average DC power P DC can be described as follows.

𝑃 𝑂𝑈𝑇 = 𝑃 1 = 𝑉 𝐷𝐶 •𝐼 1 2 = 𝑉 𝐷𝐶 2 • 𝐼 𝑀𝐴𝑋 2𝜋 • 𝛼-𝑠𝑖𝑛 𝛼 1-𝑐𝑜𝑠(𝛼 2 ⁄ )
3.8

𝑃 𝐷𝐶 = 𝑉 𝐷𝐶 • 𝐼 𝐷𝐶 = 𝑉 𝐷𝐶 • 𝐼 𝑀𝐴𝑋 2𝜋 • 2 𝑠𝑖𝑛(𝛼 2 ⁄ )-𝛼•𝑐𝑜𝑠(𝛼 2 ⁄ ) 1-𝑐𝑜𝑠(𝛼 2 ⁄ )
3.9

Thus, the power efficiency of the current source-based amplifier is as follows.

𝜂 𝑂𝑈𝑇 = 𝑃 𝑂𝑈𝑇 𝑃 𝐷𝐶 = 𝛼-𝑠𝑖𝑛 𝛼 2•[2 𝑠𝑖𝑛(𝛼 2 ⁄ )-𝛼•𝑐𝑜𝑠(𝛼 2 ⁄ )]

3.10

Class A Amplifier

Class A amplifier is a very simple amplifier with a very good linearity, but its power efficiency is low.

The gate-to-source voltage V GS of the transistor M1 is greater than V TH (the threshold voltage of M1). The current flows through M1 during the whole waveform cycle, even if there is no signal being amplified. This continuous biasing method causes a loss of power and overheating. The conduction angle of a class A amplifier is 2π.

Therefore, the power efficiency of class A is

𝜂 𝑂𝑈𝑇(Class𝐴) = 2𝜋-𝑠𝑖𝑛 2𝜋 2•[2 𝑠𝑖𝑛(𝜋)-2𝜋•𝑐𝑜𝑠(𝜋)] = 50% 3.11
To achievement its theoretical efficiency, the amplifier must have a maximum signal swing without compression [LG2005]. The waste power of the amplifier changes into thermal energy. If there is no cooling facility in the amplifier, the over heating will cause a severely damage to the circuits.

Class B Amplifier

The bias point of the class B amplifier is set to the transistor's threshold voltage V TH . Thus, the drain current only flows during a half cycle of the waveform.

The transistor only turns on during the positive half cycle, so the efficiency of the class B amplifier is higher than that of a class A amplifier. The conduction angle of the class B amplifier is π. The power efficiency of class B is shown in Equation 3.12

𝜂 𝑂𝑈𝑇(𝐶𝑙𝑎𝑠𝑠𝐵) = 𝜋-𝑠𝑖𝑛 𝜋 2•[2 𝑠𝑖𝑛(𝜋 2 ⁄ )-𝜋•𝑐𝑜𝑠(𝜋 2
⁄ )] = 78.5%

3.12

The DC power that is consumed in a class B amplifier is less than that of a class A amplifier with a decreased signal amplitude. No DC current is drawn in class B as long as there is no input signal. Consequently, the degradation of the efficiency at low-signal amplitudes is not as significant as for the class A amplifier. Moreover, the energy dissipation and the heating are reduced.

Class AB Amplifier

The transistor in a class AB amplifier has a conduction angle that ranges from π to 2π. The bias point for this kind of amplifier is greater than V TH , and is lower than the bias point of the class A amplifier. Therefore, the power efficiency of a class AB amplifier is between that of a class A and a class B.

The output signal of a class AB amplifier is more than a half cycle. This type of amplifier provides a better efficiency than that of a class A amplifier, and has a smaller distortion compared with that of a class B amplifier.

Switched-mode Amplifiers

Current-based amplifiers, which are discussed in a former section, all have low power efficiency. The dissipated power is converted into thermal energy, and can severely affect the circuit. These disadvantages limit the usage of these amplifiers in current HIFU applications, such as phased-array HIFU systems. In this section, we discuss different types of switched-mode amplifiers that are suitable for HIFU applications. The switched-mode amplifier uses a transistor, which enables instantaneous switching between on and off states [VAA2008]. Ideally, the output impedance R Switch of the switched-mode amplifier is zero when the switch turns on. Moreover, when the switch turns off, R Switch changes to infinity.

Thus, both of the current flows through the switch I Switch and the voltage applied across the switch V Switch are zero in the ideal case. The theoretical power efficiency of the switched-mode amplifier can reach 100%. However, the actual resistance of R Switch is limited. The actual power efficiency of the switched-mode amplifier is about 90%. A simplified schematic of the switched-mode amplifier is demonstrated in Figure 3.5. To ensure that the transistor works in switch mode, the input signal of the amplifier must be large enough to drive the transistor into its saturation region. This leads to nonlinear input and output characteristics. Moreover, the output waveform of the switched amplifier is square wave. In order to reduce the waste power caused by the harmonics, a tuning network is required at the output stage of the switched-mode amplifier. Two primary kinds of tuning networks can be applied to the switched-mode amplifier. The simplified schematics of these two tuning networks are shown in Figure 3.6. In many applications, several tuning networks with very complex structures are applied to achieve very few harmonics in the output signal.

Currently, there are many kinds of switched-mode amplifier, such as class D, class E, and class DE amplifiers. In this thesis, we focus mainly on the switched-mode amplifier that is suitable for HIFU systems. The transistors M1 and M2 turn on alternately at a half duty cycle to charge or discharge the tuning network. Based on the Fourier analysis, the drain-to-source voltage of M2 (V DS2 ) can be described by the following equation.

Class D Amplifier

V DS2 = V DC ( 1 2 + 2 π sin θ + 2 3π sin 3θ + ⋯ ) 3.13
The tuning network that is used in this class D amplifier is the LC tuning network.

By supposing that the LC resonance has a reactance of zero at the fundamental frequency and a high impedance at the harmonics, the harmonics of the current can be ignored. In this condition, the voltage and current of R L can be written as follows,

V RL = V DC • 2 π sin θ 3.14 I RL = V DC R L • 2 π sin θ 3.15
Therefore, the maximum output power P RL can be achieved when θ equals π/2.

P RL = 2 π 2 V DC 2 R L

3.16

The DC current I DC is given by the average of I RL [VAA2008]. Since the associated Fourier transformation of a sinus function adds a factor of 1/π, we get

I DC = Max(I RL ) 1 π = 2 π 2 V DC R L

3.17

The average DC power consumption P DC can be defined as

π 2 V DC 2 R L

3.18

Finally, in the ideal case, the power efficiency of this half-bridge class D amplifier is given by η out = P RL P DC = 100%

3.19

However in real cases, the tuning net-work can not eliminate all of the harmonics.

Further, the characteristics of transistors M1 and M2 are not perfect as the ideal ones, so there will be power losses. The actual power efficiency of the class D amplifier is nearly 90%.

The schematic of the full-bridge class D amplifier, with a duty cycle of 50%, is demonstrated in Figure 3

Class E Amplifier

The Class E amplifier is another type of switched-mode amplifier that can achieve a theoretical power efficiency of 100%. However, as opposed to the class D amplifier, only one transistor is used in the class E amplifier. The simplified schematic and the equivalent circuit of the class E amplifier are presented in Figure 3.9 (left) and (right).

The current flows through the L RFC is controlled by the switching state of transistor M1.

L and C comprise the tuning network that is used to filter out the harmonics. There are two important rules that need to be satisfied in the class E amplifier: ZVS (zero-voltage switching) and ZDS (zero-derivative switching) [AM2001]. Because of these two rules, there will be no overlap between I D and V DS . In other words, there are no power losses. Therefore, the theoretical power efficiency can reach 100%.

RL M1

IDS

Based on the analysis presented in [VAA2008], the voltage applied across the load R L at the fundamental frequency can be defined as

V RL = √1 + π 2 4 • I DC • R L 3.20
Therefore, the output power of the amplifier can be described as in Equation 3.21.

P RL = V RL 2 2R L = (1 + π 2 4 ) • I DC 2 •R L 2 3.21
The power efficiency of the class E amplifier can be defined as

η out = P RL P DC = (1+ π 2 4 )• I DC 2 •R L 2 I DC 2 •R DC 3.22
theoretical power efficiency of the class E amplifier.

The major drawback of a class E amplifier is the need for an RF choke, which is used to limit the current ripples generated by switching. For a 10% current ripples, the minimum inductance of the choke is approximately 8.7 times the series resistance Rs, divided by the switching frequency.

Other Types of Switched-mode Amplifier for Transducers

Besides the basic switch-mode amplifiers that were previously analyzed, there are several switched-mode amplifiers with other topologies, such as step-up driving, flyback, and push-pull topologies [WKC2005].

The schematic of the amplifier that uses the step-up driving topology is demonstrated in Figure 3.10. There are three working periods for this amplifier. In the first period, switches S w1

and S w2 turn on, and S w3 turns off. The inductor L is charged, and the transducer is shorted by S w2 . Then, S w2 switches off, and the transducer is charged by the energy stored in L. In the last period, S w1 turns off and S w3 turns on, and the transducer is discharged. The step driving power amplifier do not need of tuning circuit, which makes it easy to realize. However, the use of three switches leads to a requirement of a very complex control circuit, and the switching times of the switches must be chosen carefully to avoid overlaps. Moreover, the use of a diode D leads to additional power losses. Afterall, it is unsuitable for our application. The flyback switched-mode amplifier is also no need of tuning network. Although, this amplifier has a very simple structure, the capacitive components of the transducer and the secondary coil can create an oscillation loop. And due to the use of transformer, this amplifier is unsuitable for MRgFUS.

The push-pull switched-mode amplifier is illustrated in Figure 3.12, and appears to be an upgraded version of the flyback amplifier. S w1 and S w2 turn on and off in a half cycle alternately. The transformer also plays a part in the impedance tuning of the transducer. The push pull switched-mode amplifier can provide very large output power.

And it has a very simple structure. However, the same as the flyback switched-mode amplifier, the use of the transformer makes it incompatible with MRI. And the working frequency is limited by the transformer.

Review of Existing Power Amplifiers

After the discussion about different amplifier topologies, in this section, we present a review of existing power amplifiers for ultrasound therapy. As discussed in the previous section, power amplifiers can be classified as current source-based amplifiers and switched-mode amplifiers. Therefore, in this section, we separately review these two types of amplifiers. First, we discuss the current source-based amplifiers, after which we review switch-mode amplifiers.

Existing Current-source Amplifiers

Shyr-Long Jeng and Yung-Cheng Tung [TYC2008] presented a multicell linear power amplifier for piezoelectric transducers by using discrete components. The circuit can provide a ±200 V output swing with a corner frequency of 100 kHz and an output current as high as 2.5A. The amplifiers used in the output stage are LM4700, which is a class AB amplifier. Although, this amplifier offers a very high output power, its low efficiency, and narrow bandwidth make it unsuitable for our application. Figure 3.13

shows the schematic of this amplifier. Kexu Sun, Zheng Gao, et al. [SK2015] proposed a class AB power amplifier with a digital feedback predistortion system to improve the power efficiency. The amplifier can drive a load of 300 pF in parallel with a 100 Ω resistor with a power efficiency of 44% and a signal swing up to 180 V p-p . This amplifier is more efficient than the former one, and it is realized using integrated circuits (ICs). However, its efficiency is still lower A high-voltage linear amplifier for integrated two-dimensional (2D) ultrasound transducer array was introduced in [GSH2013]. It is a class B amplifier with a ±25 V output swing and 6.2 MHz bandwidth. However, this amplifier was designed using a CMOS process, which limits its output power.

Dario Bianchi et al. also designed a class B amplifier for transducers [BD2014],

which was realized using BCD6-SOI technology. Its performances are as follows:

output swing 90 V p-p , power efficiency of 60% and 6.5 MHz bandwidth (80 V p-p ). The output swing and power efficiency of this amplifier is better than that in [GSH2013].

However, the required output swing is around 350 V p-p , and the power efficiency still does not meet our requirement. In this amplifier, a PMOS and a NMOS are driven separately by their gate drivers.

Existing Switched-mode Amplifiers

The on-off cycle of MOSFETs M1 and M2 will still be determined by the TTL signal.

As a result, the output signal is a square wave. Capacitors C1 and C2 and resistor R1

and R2 are responsible for the shifts in the levels of the gate signal. The tuned filter inductor L and capacitor C filter out the higher harmonics in the output signal. The advantage of this design is that it is simple and very cost effective. However, the differential drain-to-source resistance of the NMOS and PMOS may cause some distortion in the output signal.

Cheng et al. [CHL2009] proposed a 41 kHz, 42 W single-switch class E amplifier combined with a flyback converter and a power-factor correction for ultrasonic cleaning applications. Figure 3.16 shows the schematic of this amplifier. The overall efficiency of the inverter is 90%. As mentioned earlier in the section that focused on the class E amplifier, the radio-frequency choke (RFC) is an inductor with very high inductance.

This high inductance will cause compatibility problems with MRI. Therefore, this topology is not suitable for our application. Lewis and Olbricht [LJGK2008] developed a 48-W, 1.54-MHz high-intensity ultrasound system for military, medical, and research applications. The efficiency of the amplifier is 99%, as reported by the authors. Its schematic is shown in Figure 3.17. In order to achieve maximum power transfer from a standard 50 Ω power supply to a 50 Ω transducer probe, the output impedance of the amplifier must be as low as possible. The authors reported that if 99% of the voltage from the power supply must be transferred to the load, the output impedance of the power amplifier should not be greater than 0.05 Ω.

Their design was implemented using discrete components. Multiple power transistors are connected in parallel with each other to achieve very low output impedance. An RC network handles level shifting for MOSFETs. The overall design is lightweight, small, and cost effective [LJGK2008]. Its topology is similar to that in [VAA2008] without a tuned LC harmonic filter connecting the amplifier output to the transducer. Because the driver is a class D amplifier, the output waveform of the amplifier is a square wave. Driving an ultrasound transducer with a square wave will cause the acoustic pressure field to contain harmonics; therefore, this solution cannot be directly adapted to HIFU applications.

Yang and Xu [YL2007] proposed a class D full-bridge amplifier for an Audio

Beam system which is made with piezoelectric transducers. The switching frequency is 600 kHz. The schematic of its output stage is shown in Figure 3.18. Resistors R1 and R2

and an operational amplifier are part of the circuitry that cooperates with the gate driver IC to provide over currentprotection to the MOSFETs at the output stage. Inductors L Q and L P reduce the instantaneous current that goes to the transducer. The output stage of this amplifier consists of four transistors and two inductors. It is not economical to implement our design with this topology because four transistors occupy more space and inductors have to be mounted externally.

Low-intensity pulsed ultrasound (LIPUS) is an emerging technique that uses ultrasound for bone healing, dental-tissue formation, and tooth-root healing. Ang et al.

[AWT2010] fabricated a 0.8 W, 1.5 MHz integrated amplifier chip for LIPUS applications. Its schematic is shown in Figure 3.19, and it was fabricated using a DALSA 0.8 μm HV CMOS process. The overall efficiency, including the pulse generator and amplifier, is 70%.

Depending on the impedance characteristics of the piezoelectric resonator, an ultrasound transducer usually requires a high voltage and high current to produce enough acoustic power for healing purposes. In order to mitigate the electrical requirements, an external tuned LC tuning network that matches the impedance of the transducer at resonance frequency is inserted in between the output of the amplifier and the transducer. This LC filter boosts the output voltage form 2.53 V peak to 7.6 V peak and eliminates higher harmonic contents from the output signals. A level shifter was used as the power output stage as shown in Figure 3.19. The generation of pulse modulated signals is realized using a digital block. In our case, an efficiency of 70% is not acceptable, and the use of NMOS and PMOS in the amplifier will cause distortion of the output signal, which is the same as in [HT2006] and [LJGK2008].

Comparison of Power Amplifiers

Based on the analysis in the former sections, a comparison of different existing amplifiers is shown in Table 3.1.

The typical power amplifier and the published works provide valuable information and techniques for designing piezoelectric power ampliers. But none of the existing power amplifier can perfectly match our application, such as elimination of huge inductors and transformers; high working frequency; high power efficiency; small circuit surface. Therefore, a half-bridge class D power amplifier is designed in section 3.5.

Proposed Power Amplifier

The circuit design and analysis of the power amplifier used in our project is presented in this section. As discussed in previous sections, many basic power amplifiers can be used to drive ultrasound transducers. However, considering the power efficiency, the working frequency, and the compatibility with MRI, in this thesis, we present a half-bridge class D power amplifier with a square waveform input and a sinusoidal output. The diagram of the designed class D power amplifier is shown in Figure 3.20.

Anti-cross Conduction Circuit

Half Bridge Driver As can be seen from this figure, the amplifier consists of four parts: an anti-cross conduction circuit, a half-bridge MOSFET driver, two MOSFETs, and an automatic impedance-tuning circuit. This section focuses mainly on the amplifier parts. The principle of the proposed automatic impedance-tuning network and its circuit design will be given in chapters 4, 5 and 6.

Principle of the Proposed Class D Half-bridge Power Amplfier

As shown in Figure 3.20, the proposed amplifier consists of four parts. The half-bridge driver is used to generate a large current supply for the transistors. To achieve a high power efficiency, R ds(on) of the MOSFETs M1 and M2 are required to be as small as possible. Compared with PMOSs, NMOSs always have smaller R ds(on) .

Therefore, in the proposed amplifier, we use two NMOSs. Except the high power efficiency, high charging speed can also be achieved by using transistors with small R ds(on) . And by using the same type NMOSs, the following equation can be realized, 𝑅 𝑑𝑠 (𝑜𝑛) 𝑀1 = 𝑅 𝑑𝑠 (𝑜𝑛) 𝑀2

3.23

Therefore the charging and discharging of the half-bridge is completely matched.

NMOSs can also provide lower threshold voltage which makes it switch faster than PMOSs.

The transistors are driven by two out-of-phase signals, which means only one transistor turns on during the operation period. Because, the output of the half-bridge V HB is a square wave signal. A LC tuning circuit is used to filter the harmonics of V HB .

After the tuning circuit, the ouput signal V CFix is a sinusoidal signal.

As discussed in previous sections, the overlap of the transistors' control signal will cause energy loss. Therefore, we applied an anti-cross conduction circuit to solve the overlap problem.

The operation of the circuit can be described as follows:

The operation waveform of the proposed amplifier is illustrated in Figure 3.21. In order to simplify the analysis of the amplifier, we made several assumptions: R ds(on) = 0; I P (t = 0) = 0; V CFix (t = 0) = 0. As discussed in chapter 2, the switched mode power amplifiers used for HIFU applications must have impedance tuning networks, so we introduce a static L-type impedance-tuning network to enable us to perform a complete analysis of the power amplifier. Details of the proposed automatic impedance tuning system and circuit design will be presented in the following chapters. The operation analysis of the proposed half-bridge class D power amplifier is as follows.

According to Figure 3.22, the following equation can be obtained. Substitute V CFix (t=0)=0, I P (t=0)=0 into Equations 3.25 and 3.26, respectively.

𝐸 = 𝐿𝐶 𝐹𝑖𝑥

Then, V CFix (0≤t<π/ω) and I P (0≤t<π/ω) can be written as:

𝑉 𝐶𝐹𝑖𝑥 = 𝐸 -𝐸𝑐𝑜𝑠𝜔𝑡 By performing the same calculation for the following half periods, we can obtain the waveforms of the voltage applied across C Fix (V CFix ) and the current flows through L (I P ) as shown in Figure 3.25.

The following information can be obtained from the previous analysis.

1. V CFix increases by 2E during each period.

Parameters of the Ultrasonic Transducer

Based on the datasheet that is provided by the foundry and the modeling of the

Calculation of the Circuit Parameters

As shown in previous section, the series impedance of the transducer Z S at its working frequency can be described as 𝑍 𝑆 = 𝑅 𝑠 + 𝑗𝑋 𝑠 = 36.65 -308.2𝑗

3.35

Therefore, the parallel impedance of the transducer Z P is described by

𝑍 𝑃 = 𝑅 𝑃 + 𝑗𝑋 𝑃 3.36 𝑅 𝑃 = 𝑅 𝑠 (1 + 𝑄 𝑃𝑖𝑒𝑧 2 ) ≃ 2628.4Ω
3.37

𝑋 𝑃 = -𝑋 𝑠 (1 + 1 𝑄 𝑃𝑖𝑒𝑧 2 ⁄
) ≃ 312.6Ω

3.38

Then, the parallel equivalent circuit of the transducer at its working frequency can be obtained as shown in Figure 3.28

3.47

The inductance and resistance of L at 1.25 MHz were chosen to be 1.35 μH and 0.183 Ω, respectively, and it is an aircore inductor. It was developed in our laboratory.

The resistance of the inductor is much lower than the resistance of the transducer which can achieve a high power efficiency.

The resonance frequency f LC of the LC circuit can be described by

𝑓 𝐿𝐶 = 1 2𝜋√𝐿(𝐶 𝐹𝑖𝑥 +𝐶 𝑃𝑖𝑒𝑧 ) ≃ 1.25𝑀𝐻z = 𝑓 𝑤𝑜𝑟𝑘𝑖𝑛𝑔

3.48

Then, we obtain the quality factor Q Load of the LC tuning network using

Circuit Design

We implemented the power amplifier using a printed circuit board (PCB) and discrete devices. The software used to design the power amplifier is Altium Designer Release 10. The details of the circuit and PCB will be presented in this section.

Based on the circuit calculation, we designed the schematic of the proposed power amplifier. Figure 3.29 shows the schematic of the proposed class D power amplifier with a static L-type tuning network.

The half-bridge is composed of two NMOSs (SI4178). The value of R DSon (max) for the chosen MOSFET is less than 0.033 Ω when V GS = 4.5V [START_REF] Vishay | Si[END_REF], which meets our requirement. Further, the rated power of SI4178 is 5 W, which exceeds the rated power of the transducer.

Half-bridge MOSFETs Driver

Half-bridge MOSFETs Static Tuning Network [Si9912]. The dead time is larger than the switching time of the MOSFETs.

Therefore, there is no cross-conduction problem, which means that the MOSFETs of the half-bridge will never conduct at the same time.

Printed Circuit Board Design

The designed printed circuit board of the power amplifier is illustrated in the area bounded by the red dotted line in Figure 3.30. This board is a 1.6 mm double-side fiberglass PCB, and the copper foil on the printed circuit board is chosen to be 105 μm.

The area of the proposed power amplifier is only 10 cm 2 .

Prototype and Test Results of Power Amplifier

Summary of the Proposed Half-bridge Class D Amplifier

In this section a half-bridge class D power amplifier for our application is presented. The performance of the proposed power amplifier is shown in Table 3.3.

with working frequency of 1.25MHz. And the output waveform of the amplifier is sinusoidal signal that meets our requirement. In the circuit, there is no bulky magnetic compont thanks to the L-type tuningnetwork and small value air-core inductor.

Therefore, it is compatibility with MRI. The surface of the circuit is only 10cm 2 .

Moreover, the power efficiency of the presented amplifier is 82.6% which is very suitable for our application. The circuit is realized by using printed circuit board and discrete component that makes it very cheap and easy to fabricate. In other words, it has a very good cost performance ratio.

Power Supply Transducer

Power Supply 5V

Working Frequency 1.25MHz

Output Power 3W

Ouput Waveform Sinusoidal

Power Efficiency 82.6%

Total Price

Less than 10€

Chapter 4

Proposed Impedance Auto-tuning

Introduction

In order to create a focused ultrasound, the HIFU system uses different numbers of piezoelectric elements, which have the property of mechanical deformation as a function of the supply voltage. To deal with all types of tumors, it is necessary to move the focus point within the space. By using a transducer array consisting of many small independent transducers (mono-elements), it is possible to modify the spatial position of the focus point by changing the phases of the supply voltage for each element.

However, the electrical impedances of piezoelectric elements are complex, while the output impedance of power amplifiers is purely resistive. If we connect power amplifiers directly to the transducers, the reflected power will cause a defocusing of the ultrasound, increasing the temperature of the transducers or even causing unrecoverable damage to the transducer. Therefore, the impedances of the transducers must be tuned to make them purely resistive. Moreover, temperature variations, ageing, and different working mediums can cause changes of the impedance, and this impedance variation makes static impedance-tuning networks unsuitable for our application. In addition, as discussed in chapter 2, most existing variable-impedance-tuning networks require an MCU or computer to achieve automatic tuning. The use of an MCU or computer leads to a complicated and expensive tuning system. For saturable reactor auto-tuning network, the use of a bulky magnetic component cannot satisfy both the weight and miniaturization constraints of HIFU systems, and furthermore, they cannot comply with the MRI compatibility regulations.

In this chapter, a novel automatic impedance tuning system without using of MCU or computer and bulky magnetic components is presented to solve the impedance tuning and impedance drifting problems at the same time. The structure of this chapter is as follows: Section 4.2 presents the influences of the temperature and technological dispersions on the impedance of the chosen transducer. Besides, the impact of impedance variation on the power efficiency of the ultrasonic generator is also presented in this section. A recall of existing auto-tuning techniques is illustrated in section 4.3. In Section 4.4, we describe the principle of this novel automatic impedance-tuning system. Section 4.5 gives out the diagram of the proposed realization and its working operation. At last, the stability analysis of the proposed auto-tuning system will be given out in Section 4.5.

Impedance Variation of the Transducer

Impact of Temperature Drifting on Transducer's Impedance

The impedance variation of the transducer is caused mainly by fluctuations in the temperature. In this section the relationship between the temperature variation and the imaginary impedance of the transducer is studied. The schematic of the measurement circuit is presented in

Impact of Technological Dispersions on Transducer's Impedance

The impedance of the transducer is also influenced by the technological dispersions during the manufacturing process. Imaginary impedances of 256 different mono-elements in the phased-array used in our application are shown in Figure 4.4.

These impedances are measured at 25 º C. The imaginary impedances of these transducers is ranging from -346.5 (Imag(Z) min ) to -267.8 Ω (Imag(Z) max ).

As can be known from the measured data, the average imaginary impedance

Impact of Impedance variation on Power Efficiency

In sections 4.2.1 and 4.2.2, we obtained that the variations of imaginary impedance caused by temperature drifting and technological dispersion are 5% and 25%, respectively. Therefore, if both cases happen in the same time, the maximum variation of the imaginary impedance in the worst case can reach 30%.

According to Equations 2.24 and 3.52, the power efficiency of the power amplifier (η) with a static tuning network can be rewritten as, 𝜂 = 𝑐𝑜𝑠 (𝜑) • 𝜂 𝐸𝑓𝑓 = 𝑐𝑜𝑠 (𝜑) • 82.6%

4.2

where η Eff is the power efficiency of the power amplifier without impedance drifting, and cos(φ) is the power factor. Based on Equation 2.25, we can know that 𝜑 = 𝑡𝑎𝑛 -1 (𝐵 𝑇𝑢𝑛𝑛𝑒𝑑 𝐺 𝑃𝑖𝑒𝑧 ⁄ )

4.3

where B Tunned is the tuned susceptance of the transducer, and G Piez is the conductance of the transducer.

We define B TN as the susceptance that can be compensated by the static tuning network. B Piez is the suspectance of the transducer, and ∆ B Piez is the variable suspectance of the transducer. It can be known that B Tunned = ∆BPiez + B Piez + B TN . We The power efficiency curves of the power amplifier with a static tuning network is presented in Figure 4.6. As it can be seen from this figure, the impedance drifting of the transducer leads to a great reducing of the power efficiency, if we use a static tuning network. Thus, a novel auto-tuning network is presented to solve this problems in the following sections.

Recall of Existing Auto-tuning Techniques

In this section, we recall the existing auto-tuning techniques used for ultrasound therapy. A summary about these different auto-tuning techniques is also given out in this section.

Hui Xu, Erzhen Gao, and Q.Y.MA [XH2001] present a variable electrical tuning network consisting of a fixed inductor with a variable capacitor. Although, this paper is mainly focused on the piezoelectric oscillator, fundamentally this technique employed to shift the driven resonance of a piezoelectric element remains the same. It can automatically tune the imaginary impedance of the transducer over a range of 34% by varying the capacitance of the driving circuit.

The variable capacitor used in this paper is realized by using a movable metal plate and a fixed plate. When we apply different control voltages to the capacitor, the movable part changes its position accordingly, the value of the capacitance between the fixed and the movable parts also changes. However, it is difficult to achieve a high accuracy moving of the movable plate, which means the accuracy of this capacitor is low. Therefore, the accuracy of this tuning circuit is badly limited.

A switched-capacitor based auto-tuning network is presented by Si et al. [SP2005].

This tuning network was introduced for the bio-implanted application. Figure 4.7 shows the simplified configuration of this tuning system. The test results showed a power efficiency of 80% at 1 cm gap demonstrating that the proposed method is very effective in stabilizing the operating frequency, while maintaining the zero voltage switching operation. However, the working frequency of the tuning network presented in this paper is less than 100 kHz, which is much lower than the working frequency of our application (1.25 MHz). Besides, the transfer function of this tuning network is strongly non-linear, and this non-linear characteristic may lead to a stability problem. Compared with the static tuning method, this adjustable impedance tuner can offer an improvement of 1.7 dB is made in the mean power losses, and an improvement of 5.2 dB is made by considering the highest reflection. It solves the imaginary impedance and the real impedance drifting at the same time. However, this adjustable tuner needs a real-time impedance measuring circuit and a computer to generate the switch control signal. The large surface of the circuit and expensive equipments lead to a very low cost performance ratio.

An adaptive tuning network for class D amplifier is introduced by Mohamed

Gamal EI Din, et. al [EDMG2010]. Combined with the proposed adaptive tuning network, the class-D amplifier can achieve an efficiency improvement of more than 25% over an 8 dB output dynamic range in comparison with a similar amplifier with fixed matching. Although, this tuning network is compatible with our application, the complex structure makes it hard to implement and manufacture. In our application, there are 256 mono-transducers in the phased array, therefore, this tuning network is also not suitable for our project. The simplified schematic of the tuning network is shown in Figure 4.9. The power amplifier with this tuning network achieves a substantial operating frequency band from 1-1.9 GHz, with 10 W peak power, and 64%-79% peak power efficiency. However, the use of varactor diodes limits the maximum output voltage of the system. In our project, the required output voltage is 126V, which greatly exceeds the break down voltage of the varactor diodes. And the use of DSP module makes this circuit low cost performance ratio.

In the master thesis of Hayden N. Radke [RHN2013], he presents an auto-tuning system for piezoelectric transducer. This tuning system consists of switching inductor network and a control loop. Flow chart of the tuning system is demonstrated in Figure 4.10. A microcontroller and Labview are used to obtain the impedance of the transducer based on the detected current. The deviations from original impedance are corrected by using a feedback network that evaluates amplitude of impedance. A class D MOSFET amplifier is used for exciting the transducer. Also, a microcontroller system controls the feedback network. Experiments with variation of mechanical loads have shown the effectiveness of the system. The main limitation of this method is the using of bulky magnetic component in the detection circuit. This method is not compatible with MRI system.

Summary of frequency, improved power efficiency, and tuning range for the existing auto-tuning networks are shown in Table 4.1.

Needs MCU

The published auto-tuning circuit provide valuable information for designing impedance auto-tuning system. However, none of the existing auto-tuning circuit can perfectly match our application, such as, high cost performance ratio, MRI compatibility, high tuning accuracy, etc. A novel auto-tuning network is proposed in this thesis to solve these problems, and the principle of the proposed auto-tuning network is presented in section 4.4.

Proposed Auto-tuning Network

Based on the review of the existing auto-tuning networks, a novel auto-tuning network for imaginary impedance cancelling of the transducer is proposed in this section. The proposed auto-tuning network is no need of MCU or computer and bulky magnetic components. Besides, this auto-tuning network achieves very high accuracy and proper working frequency.

Principle of the Proposed Auto-tuning Network

The simplified circuit of the proposed auto-tuning network, which is named as synchronous-switched capacitor, is presented in Figure 4.11.

L CS C Fix V CFix Ip V OUT AC switch V PWM V CS I CS C EQ

Synchronization Condition of the Proposed Auto-tuning Network

To achieve the synchronization objective, it is necessary to know the values of the voltages V CFix and V CS across the capacitors C Fix and C S , respectively, just before the conduction of the AC switch. These values can be found after an examination of the first half period of the chronograms of V CFix and V CS as shown in Figure 4.12. As shown in this figure, the value of V CS at which the switched capacitor C S is charged is imposed by the instantaneous value taken by the input voltage V CFix just at the opening time of the AC switch (corresponding in Figure 4.12 to the time T 1 ). The switched capacitor C S is charged to a voltage given by 𝑉 𝐶𝑆 (𝑇 1 ) = 𝑀𝑎𝑥(𝑉 𝐶𝐹𝑖𝑥 ) • 𝑠𝑖𝑛 (𝑤𝑇 1 )

4.7

As long as the AC switch is open, the voltage across the switched capacitor C S stays constant and equal to the value given by Equation 4.7, and the voltage (V CFix ) applied on the fixed capacitor (C Fix ) vary sinusoidally.

The instantaneous voltage applied across C Fix , when the AC switch is turned on again (at a time corresponding in Figure 4.12 to the time T 2 ), can be described by

𝑉 𝐶𝐹𝑖𝑥 (𝑇 2 ) = 𝑀𝑎𝑥(𝑉 𝐶𝐹𝑖𝑥 ) • 𝑠𝑖𝑛 [𝑤 ( 𝑇 𝑃𝑒𝑟𝑖𝑜𝑑 2 -𝑇 2 )] 4.8
where T Period defines the period of V CFix . We know that the synchronization condition can be found when V CS (T 1 ) = V CFix (T 2 ). By substituting Equations 4.7 and 4.8 into this equation, we can get Equation 4.9.

𝑇 1 = 𝑇 𝑃𝑒𝑟𝑖𝑜𝑑 2 -𝑇 2

4.9

In other words, the synchronization condition can be achieved, when Equaton 4.9 is true. This synchronization condition can be translated into several design rules that should be followed. First, the PWM signal that is applied on the AC switch must have a conduction angle, which is always symmetrical with respect to the zero-crossing points of the sinusoidal voltage V CFix applied across the fixed capacitor C Fix . Second, the electrical charge of the switched capacitor C S should not be affected by any external cause (e.g., leakage resistances and switching-charge injection).

Being a symmetry condition, this synchronization condition will allow some simplifications in the derivation of the transfer function that follows.

Transfer Function of the Proposed Auto-tuning Network

As mentioned in Section 4.2, several unavoidable variations can cause a detuning of the tank circuit, and the detuned tank circuit will cause a variation of V CFix . Therefore, we cannot generate the PWM by using V CFix directly. In order to obtain a symmetrical PWM signal for the switched capacitor, we apply here an external triangular wave V Trig with the same phase and frequency as V CFix and a constant amplitude. The waveforms of the auto-tuning system that we obtained using a triangular wave are illustrated in Figure 4.13. • 𝑉 𝑂𝐸𝐴 4.17 Because of the strongly nonlinear characteristic of this transfer function, it may be the source of instabilities in the auto-tuning feedback loop. To ensure the stability of the auto-tuning feedback loop, the transfer function of the auto tuning system must be a linear function. Therefore, we need the conversion function of the PWM for the AC switch to verify the linearity of the transfer function. Figure 4.14 presents the waveform of the auto-tuning system, which was obtained using a linear transfer function.

ON OFF ON OFF ON V PWM V CFix V CS t T1 T2 T3 V T1 V T2 t t t V Trig Max(V CFixTuning ) V CS(T1) =V CS(T2) Constant Max(V CFixDetuning ) V OEA -V OEA
ON OFF ON OFF ON V PWM V CFix V CS t T1 T2 T3 t t t αV CFix Max(V CFixTuning ) V CS(T1) =V CS(T2) Constant Max(V CFixDetuning ) V OEA -V OEA V T1 V T2

4.20

The solving of the nonlinear problem allows the design of the complete

Diagram of the proposed realisation

The diagram of the proposed synchronous switched capacitor system for performing the auto tuning is shown in Figure 4.15. The proposed auto-tuning system using a synchronous switched capacitor is bounded by the green polygon. In order to facilitate its analysis, the auto-tuning system has been partitioned by dotted lines. As it can be seen from this figure, the auto-tuning system proposed in this paper consists of five functional blocks: tuning block, automatic gain control block, phase error detection block, switch signal generation block and AC switch block. These functional blocks implement all the functions presented in previous sections. This auto-tuning system does not require MCU or computer and bulky magnetic components. Therefore, it is perfectly suitable for our application.

Tuning Block

The tuning block is bounded by the orange dotted line in Figure 4.15. It consists of a static L-type tuning network and a switched capacitor C S which is connected in parallel with the capacitor C Fix used in the L-type tuning network. This switched capacitor is used to compensate the imaginary impedance drifting of the transducer.

AC Switch Block

The AC switch block is shown in the red dotted rectangle in Figure 4.15. It is used to control the connection status of C S . The AC switch block used in this thesis is realized with the classical structure [CS1994] by using two identical power MOSFETs N channel (Q3, Q4). As it can be seen from Figure 4.15, the Gate/Source voltage of the transistors used in this topology are floating, the AC switch driver used in this block is consequently realized with an isolated AC switch drive circuit. Moreover, in order to achieve a full output duty cycle, the working frequency of the isolated AC switch drive circuit is required to be much larger than the working frequency of the tuning system.

Automatic Gain Control Block

The automatic gain control block is shown in the area bounded by the green dotted line in Figure 4.15. As known in Section 4.4.3, the linearization of the transfer function is performed by comparing the output of the phase error detection block (V OEA ) to a constant amplitude waveform αV CFix , which has the same phase as the voltage across the fixed tuning capacitor (V CFix ). This function makes the automatic gain control block becoming one of the most important blocks in the proposed auto-tuning system. The proposed automatic gain control block is composed by a voltage divider and an automatic gain control amplifier. The output voltage of the tuning circuit is more than 100 V that greater exceeds the input range of the automatic gain control amplifier.

Therefore, a voltage divider is introduced in this block to attenuate the output voltage of the tuing circuit.

Phase Error Detection Block

The proposed phase error detection block is bounded by the purple dotted line in Therefore, it allows the tuning of the system by controlling a phase difference (Δφ = π/2) between the half bridge output voltage (V HB ) and the voltage across the tuning capacitor (V CFix ). The proposed error amplifier is based on the basic integrator circuit. This error amplifier is used to transfer the phase difference signal into the relevant phase error voltage (V OEA ). First, the error amplifier filters the phase difference signal to generate a phase difference voltage. Then, this phase difference voltage is compared with a reference voltage to generate the phase error voltage (V OEA ). If the phase difference between V HB and V CFix is π/2, the output signal of phase error detector V OEA is equal to

2.5V.

Switch Signal Generation Block

The proposed swtich signal generation block is illustrated in the area bounded by the purple dotted line in Figure 4.15. As known in Section 4.4.1, the switch signal generation block must ensure that the conduction angle of its output signal is always symmetrical with respect to the zero-crossing points of V CFix . We use two comparators and an inverter to satisfy this criterion. The equivalent capacitance of the switched capacitor is control by the output signal of this block. Therefore, the accuracy of the proposed tuning system is mainly influenced by the accuracy of this block. Besides, the symmetry switching condition of the AC switch is also influenced by this block.

Operation Chronograms

The operation chronograms of the proposed auto-tuning system are shown in

Stability Analysis of the Proposed Auto-tuning System

The proposed auto-tuning system can be considered as a PLL system, and the study of the stability and speed of this auto-tuning system can be changed to the study of the stability and speed of the equivalent PLL system. The equivalent PLL circuit of the The equivalent PLL circuit contains three parts: a phase detector, error amplifier, and voltage-controlled oscillator (VCO). The transfer function analyses for the three part are as follows:

Phase detector

The phase detector used in our auto-tuning system is an exclusive-OR gate (XOR).

Therefore, the transfer function of this phase detector can be written as

𝑉 𝑃𝐷 = 𝑉 𝐷𝐷 𝜋 ∆𝜃 4.21
where ∆θ is the phase difference between Q and Sgn[V CFix ]. Therefore, the discriminator sensitivity of the phase detector (K D ) is equal to V DD /π.

Error Amplifier

The error amplifier used in the proposed auto-tuning system is an integrator. The transfer function of this error amplifier is described by

𝐺 𝑃𝐷𝐸𝐴 (𝑗𝑤) = 1 𝑗𝑤𝑅 2 𝐶 1

4.22

Voltage-controlled Oscillator (VCO)

Assume that the settling time of the VCO is zero, the transfer function of the VCO can be written as ∆φ = K O V EA , where K O is the modulation sensitivity of the VCO. In addition, K O can be calculated by

𝐾 𝑂 = ∆𝜑 𝐸𝐴 𝑚𝑎𝑥 -∆𝜑 𝐸𝐴 𝑚𝑖𝑛 𝑀𝑎𝑥(𝑉 𝐸𝐴 )-𝑀𝑖𝑛(𝑉 𝐸𝐴 )

4.23

The proposed impedance tuning circuit is a LC circuit and the resistance of the inductor is defined as r. Then, the phase difference between the ouput of the tuning network V out and the input V in can be written as,

∆𝜑 = 𝐴𝑟𝑔 | 𝑉 𝑜𝑢𝑡 𝑉 𝑖𝑛 | = - 𝜋 2 -tan -1 𝑤𝐿-1 𝑤𝐶 ⁄ 𝑟

4.24

Therefore, the open loop transfer function of the equivalent PLL circuit is described by the following equation.

𝐺 𝑃𝐿𝐿 (𝑗𝑤) = 𝐾 𝐷 • 𝐾 𝑂 • 𝐺 𝑃𝐷𝐸𝐴 (𝑗𝑤) = 𝑉 𝐷𝐷 𝜋 • ∆𝜑 𝐸𝐴 𝑚𝑎𝑥 -∆𝜑 𝐸𝐴 𝑚𝑖𝑛 𝑀𝑎𝑥(𝑉 𝐸𝐴 )-𝑀𝑖𝑛(𝑉 𝐸𝐴 ) • 1 𝑗𝑤𝑅 2 𝐶 1

4.25

According to this equation, this PLL system has just one pole, the phase of the system is always equal to π/2, which means that it is a stable system. In real case, the settling time of VCO is equal to the settling time of the automatic gain control amplifier used in the proposed tuning system. Therefore, the stability of the proposed auto-tuning system is only influenced by the settling of the VCO. In other words, in order to realize a stable tuning system, the pole of the error amplifier used in the phase error detection block is required to be much less than the pole of the automatic gain control amplifier.

In this chapter, the principle of the proposed auto-tuning system for imaginary impedance of the transducer is presented. As can be seen from Figure 4.15, the proposed impedance auto-tuning network has a simplier structure than the existing auto-tuning systems. And the whole system does not require bulky magnetic components that makes it compatible with MRI system. Besides, due to lack of MCU or computer, the cost of this auto-tuning system is much less than the existing tuning systems. In this thesis, the proposed auto-tuning system is realized in two versions: printed circuit board and integrated circuit. The design of these two different versions are presented in chapter 5 and chapter 6, respectively.

Chapter 5

PCB Design of the Proposed Auto-tuning

Introduction

In this chapter, printed circuit board design (PCB) of the proposed auto-tuning system used to solve the imaginary impedance tuning and impedance drifting problems of the ultrasonic transducer, is presented. This printed circuit board version is used to verify the principle and the operation of the proposed auto-tuning system, and it also helps the design of the integrated auto-tuning system that is presented in chapter 6. This chapter is organized as follows: The proposed auto-tuning system is composed of five functional blocks. In section 5.2, the schematics of the sub-functional blocks used to realize the proposed auto-tuning system are presented, and explanations of the designs are also given out in this section. Section 5.3 presentes the test results of the printed circuit boards of each sub-functional blocks, and the stability analysis of the proposed auto-tuning system is also proposed in this section. Finally, in section 5.4, a conclusion of the printed circuit design of the proposed auto-tuning system is given out. The proposed auto-tuning circuit is composed of five functional blocks:

PCB Design of the Proposed Auto-tuning System

1) AGC block, which is used to generate a value of αV CFix that has a constant peak value.

2) Phase-error detection block, which is used to obtain the phase-error voltage signal V OEA .

3) Switch signal generation block, which is used to obtain the AC switch control signal.

4) AC switch block, which is used to switch the capacitor. 5) Tuning Block, which is composed of a static LC tuning network and a switched capacitor.

The software used to design the printed circuit board of the proposed auto-tuning system is Altium Designer Release 10. The schematics and PCB designs of each functional blocks will be presented in the following sections.

Automatic Gain Control Block

The automatic gain control (AGC) amplifier can be classified as feedforward and feedback AGCs based on their structures [PJPA2011]. The diagrams of these two different AGCs are illustrated in Figure 5 Both of these architectures have their own advantages and disadvantages, as illustrated in Table 5.1.

Advantages Disadvantages

Feedforward

AGC

The settling time only depends on the peak detector response.

It has no instability problems.

The loop must has high linearity.

Wide input dynamic range of the peak detector is required.

Feedback AGC Inherently higher linearity

Lower input dynamic range required by peak detector.

Settling time is higher than feedforward AGC.

Bandwidth is limited.

The variation of the output voltage, which is caused by the impedance detuning, has a ratio of about 20. Therefore, the designed AGC are required to have an input dynamic range of about 26 dB. In order to satisfy the required input dynamic range, the dynamic input range of the peak detector in the AGC must be greater than 26 dB, which is hard to realize with an analog circuit. To solve this problem, we can use a digital circuit to detect the amplitude level of the input signal [PJPA2011]. However, by using this solution, we need a digital signal processor (DSP) in the feed-forward loop, which will be used to generate the gain-control voltage. The use of DSP will increase the cost, and will also increase the circuit complexity. For feedback AGC, a lower input dynamic range is required by the peak detector. In other words, there will be no need of a high input dynamic-range peak detector.

For our project, the gain error is required to be lower than 1%. As is commonly known, the feedforward AGC must have a high linearity in order to verify the accuracy of the gain. This means that the loop must be well designed to meet our requirement for the gain error. For the feedback case, the AGC loop has an inherently higher linearity.

As a result, there is no need to perform a complex analysis to verify the high linearity of the AGC loop.

The gain error of the feedback AGC is only related to the error amplifier. In our study, considering the requirements of variable gain range, bandwidth, settling time, and cost performance ratio, the feedback loop AGC is chosen for our application. Therefore, in this paper, we focus on the design of a feedback AGC for our application. The The output signal of the power amplifier is as high as 125 V, which exceeds the input range of the VGA chip. Therefore, there is a need for an attenuator in the AGC.

The schematic of the attenuator is illustrated in Figure 5.4.

Voltage Divider

Voltage Follower The input signal of the attenuator is divided by the series connected resistors (R 2 and R 3 ). In order to minimize the influence of this divider, two capacitors C 1 and C 2 are separately shunted to the resistors R 2 and R 3 . A voltage follower is used in the attenuator to eliminate the effects of loading because the input impedance is infinite and the output impedance is finite for an ideal amplifier. The transfer function of the attenuator is defined by

𝑉 𝑂𝑈𝑇 𝑉 𝐼𝑁 = 𝑅 2 𝑅 2 +𝑅 3 1+𝑗𝑤𝐶 1 𝑅 2 1+𝑗𝑤𝐶 2 𝑅 3 = 𝐶 2 𝐶 1 +𝐶 2 1+𝑗𝑤𝐶 1 𝑅 2 1+𝑗𝑤𝐶 2 𝑅 3 5.1
Therefore, we see that the attenuation provided by this circuit is constant regardless of the frequency if the condition R 2 C 1 = R 3 C 2 is satisfied. The voltage follower is realized using an operational amplifier (OPA690), which has a 10 μA input bias current according to its datasheet. This operational amplifier is chosen due to its wide bandwidth (500 MHz), high slew rate (1800V/μs) and large output swing (4V) [START_REF]SBOS223[END_REF]. In order to reduce the effect of the attenuator, the current flows through R 2 and R 3 (I Res ) are required to be much larger than the bias current of the voltage follower.

In this thesis, we set I Res = 100 μA. Then, we obtain the following equation. According to the datasheet [OPA690] of OPA690, if the amplifier is directly connected as a voltage follower, there will be self-excitation problem. Therefore, a small resistor R 1 (30 Ω) is applied to avoid the self-excitation of the amplifier.

The maximum input voltage for the VGA amplifier used in our application is 1.4 V.

The attenuation of this circuit must be greater than Max(V IN )/1.4 = 90. Thus, we obtain Equation 5.3. 𝑅 2 = 706𝛺𝑅 3 = 62.8𝑘𝛺

5.4

The capacitance of C 1 is required to be much larger than the input capacitance of the voltage follower. Here, we chose C 1 = 1 nF. Therefore, the capacitance of C 2 can be calculated by

𝐶 2 = 𝐶 1 ( 𝑅 2 +𝑅 3 𝑅 3 -1) = 𝐶 1 89 ≃ 11𝑝𝐹 5.5
The time response of the AGC is determined by its gain-control function. There are two kinds of gain-control functions for the variable-gain-control amplifier used in the AGC: a linear gain-control function and an exponential gain-control function. The Simulink models of the AGCs with these two different gain-control functions are where K is a constant, G Filter is the gain of the error amplifier, and C is the capacitor used in the error amplifier. According to this figure, the settling time of this AGC should increase as the input signal decreases. Thus, as expected, the output transient response shown in Figure 5.6 validates the expected result for the linear AGC. As a result, τ depends on the input signal strength because V CTR is inversely proportional to the input level. In our project, the input dynamic range is required to be 30 dB. This means that the time constant for small signals would be about 32 times longer than the minimum τ.

As a result, the auto-tuning circuit must wait until the output of AGC is constant, the time performance of the synchronous-switched capacitor control circuit would be degraded.

The second approach employs an exponential function The same simulation conditions were employed as in the previous model. The results are shown in Figure 5.8. We observed that the settling time is almost constant and independent of any external parameter. For this reason, we chose this gain control function in this paper.

Therefore, the proposed AGC is based on the AD603, which has an exponential gain-control function. In addition, the schematic of the proposed VGA is presented in Voltage Follower Variable Gain Amplifier Voltage Level Shifter According to the datasheet of the AD603, to prevent self-excitation, it requires a voltage follower at the input of the AD603 [START_REF][END_REF]. In our application, most of the chips used in phase error detection block and switch signal generation block have a 5 V single power supply. Therefore, the output of the AGC needs to have a 2.5 V DC voltage. We applied a level shifter at the output of the AD603.

The transfer function of the VGA can be defined by Equation 5.9.

𝐺 𝑉𝐺𝐴 (𝑗𝑤) = 𝑒 4.6𝑉 𝐶𝑇𝑅 -1.38 ⋅ 1 1+ 𝑓 𝑓 𝐵𝑤 𝐴𝐷603 ⋅ ( 1 1+ 𝑓 𝑓 𝐵𝑤 𝑂𝑃𝐴690 ) 2

5.9

The settling time of the auto-tuning system is limited by the settling time of the AGC. Moreover, for the AGC, its settling is limited mainly by the detected speed of the peak detector. Therefore, we need a fast peak detector to reduce the settling time of the auto-tuning system. In this thesis, we use a reset and write peak detector. The schematic of the proposed peak detector is illustrated in Figure 5.10. From this figure, we can obtain the following equations:

𝑉 𝑂𝑃 = 𝑉 𝐶2 + 𝑉 𝐷1

5.10

𝑉 𝑂𝑃 = 𝐴(𝑉 𝑃𝐷𝐼𝑁 -𝑉 𝐶2 )

5.11

By combining these two equations, we get

𝑉 𝐶2 = 𝐴 1+𝐴 𝑉 𝑃𝐷𝐼𝑁 - 1 1+𝐴 𝑉 𝐷1 ≃ 𝑉 𝑃𝐷𝐼𝑁

5.12

Phase (T1≤t≤T2): S Write turns on, and S Reset is still off. The equivalent circuit during this period is shown in Figure 5.13. C 3 is connected to a voltage follower that is used to follow V C2 . In this period C 3 is charged to Max(V C2 )=V Peak . Phase (T3 ≤ t ≤ T4): S Write is off and S Reset turns on. C 2 is connected to the DC voltage of the input signal and discharged. The equivalent circuit during this period is shown in Figure 5.15 as follows. The peak detector is used to capture the crest of the sinusoidal signal and then keep it constant. In other words, the gain of this circuit is equal to one. In addition, the designed peak detector has a delay of about half period of the input signal. Then, the transfer function of the peak detector is described by

𝐺 𝑃𝐷 (𝑗𝑤) = 𝑒 -𝑗𝑤𝜏 𝑃𝐷 5.13 𝐴𝑟𝑔 | 𝑉 𝑃𝑒𝑎𝑘 𝑉 𝑂𝑃 | = - 180𝜏𝑤 𝜋 = -57.3 ⋅ 𝑇 𝑃𝑒𝑟𝑖𝑜𝑑 2 ⋅ 𝑤 5.14
where T Period = 1/f = 0.8 μs. Figure 5.16 shows the schematic of the switch-signal generator of the peak detector. It is composed by two CMOS logic dual retriggerable precision monostable multivibrators (74HC4538). 74HC4538 is selected due to its high operation speed and high accuracy [74HC4538]. The schematic of the error amplifier in the proposed AGC is shown in Figure 5.18.

SReset Generation Circuit

The transfer function of the error amplifier can be written as

𝐺 𝐸𝐴 (𝑗𝑤) = 𝑉 𝐸𝐴𝑂𝑈𝑇 -𝑉 𝑟𝑒𝑓 𝑉 𝑃𝑒𝑎𝑘 -𝑉 𝑟𝑒𝑓 = - 1 𝑗𝑤𝑅 2 (𝐶 1 +𝐶 2 ) 1+𝑗𝑤𝑅 1 𝐶 1 1+𝑗𝑤𝑅 1 (𝐶 1 𝐶 2 𝐶 1 +𝐶 2) ⁄

5.17

Voltage Follower Error Amplifier A voltage follower is applied before the error amplifier to minimize the influence of the error amplifier on the former circuit. As shown in Figure 5.3, the proposed AGC circuit is a closed-loop system, it is therefore necessary to study its stability and speed.

By multiplying the transfer functions of the VGA, peak detector, and error amplifier together, we can obtain the transfer function of the AGC as follows:

𝐺 𝐴𝐺𝐶 (𝑗𝑤) = 𝐺 𝐴𝐺𝐶 (𝑗𝑤) ⋅ 𝐺 𝑃𝐷 (𝑗𝑤) ⋅ 𝐺 𝐸𝐴 (𝑗𝑤)

5.18

Substituting the maximum gain of the VGA into this transfer function, we can get the gain of the system in decibels.

|𝐺 𝐴𝐺𝐶 (𝑗𝑤)| = 30𝑑𝑏 + 20𝑙𝑜𝑔(|𝐺 𝐸𝐴 (𝑗𝑤)|)

5.19 and the phase of the AGC system is described by

𝐴𝑟𝑔|𝐺 𝐴𝐺𝐶 (𝑗𝑤)| = -𝑡𝑎𝑛 -1 ( 𝑓 90𝑀𝐻𝑧 ) + (-57.3 ⋅ 𝑇 𝑃𝑒𝑟𝑖𝑜𝑑 2 ⋅ 2𝜋𝑓) + 𝐴𝑟𝑔|𝐺 𝐸𝐴 (𝑗𝑤)|

5.20

According to the principle of stability of the system, we use MATLAB to determine the frequency of a unity gain of G AGC (jw) by changing the parameters of the When the phase margin is greater than 0, the system will be stable. The results of this operation were as follows:

5.21

Obviously, the AGC system is stable. In addition, the speed of the AGC can be increased by adjusting the values of the elements of the error amplifier, but the stability of the system will be reduced.

The designed PCB of the AGC is illustrated in Figure 5.20. This board is a 1.6 mm double-side fiberglass PCB, and the copper foil on the PCB is chosen to be 105 μm. The dimensions of the proposed AGC are 7.2 cm × 5.5 cm.

Phase Error Detection Block

The schematic of the proposed phase-error detector is shown in Figure 5.21. The phase-error detector consists of a phase shifter, an XOR gate, an integrator, and an inverter.

Phase Shifter XOR Integrator Inverter

Fig.5.21 Schematic of the proposed phase error detector

The phase error should be measured between the voltage (V CFix ) across capacitor C Fix and the output of the half-bridge circuit (V HB ), but we want to prevent the connections between the high-power output signal and low-power devices. We use the switch signal of the half-bridge circuit to replace V HB . As discussed in section 3.6, there is a delay of about 50 ns between the output of the half-bridge and its input signal.

Therefore, we applied a phase shifter to cancel this delay. The capacitor C 2 used in this phase shifter is 100pF. The resistor used in this phase shifter is a variable resistor which has a maximum resistance of 1.5 kΩ. The minimum delay of the phase shifter is zero, and the maximum delay that can be offered by this phase shifter is calculated by

𝑇 𝐷𝑒𝑙𝑎𝑦 = 𝑀𝑎𝑥(𝑅 3 ) ⋅ 𝐶 2 ⋅ 𝑙𝑛(2) ≃ 104𝑛𝑠 5.22
After the cancelling of the undesired delay by the phase shifter, an XOR gate is used as a phase comparator. We applied an integrator to change the phase difference signal into a phase-error voltage. Besides, this integrator can also filter the phase-difference signal generated by XOR gate, and compare phase difference voltage with a desired reference voltage. The transfer function of this integrator is described by

𝐺 𝑃𝐷𝐸𝐴 (𝑗𝑤) = 1 𝑗𝑤𝑅 2 𝐶 1

5.23

To achieve a stable tuning system, the following inequation should be true.

𝜏 𝑃𝐷𝐸𝐴 > 𝑀𝑎𝑥(𝜏 𝐴𝐺𝐶 ) = 7 × 0.8𝑢𝑠| 𝑓=1.25𝑀𝐻𝑧

5.24

Therefore, we chose τ PDEA = 3 × Max(τ AGC ) = 16.8 μs and R 2 = 15 kΩ. Then, C 1 can be calculated by

𝐶 1 = 𝜏 𝑃𝐷𝐸𝐴 2𝜋𝑅 2 ≃ 180𝑝𝐹 5.25
The simulation results of the frequency response of the proposed error amplifier is illustrated in Figure 5.22. In order to make sure the generated switch signal has a conduction angle, which is always symmetrical with respect to the zero-crossing points of V CFix , we need a symmetrical phase error signal. Therefore, an inverter is added at the output stage of the phase error detection block.

Switch Signal Generation Block

The schematic of the proposed switch-signal generator is shown in Figure 5.23. As analyzed in section 4.4.2, the switch signal applied on the switch capacitor must has a conduction angle, which is always symmetrical with respect to the zero-crossing points of V CFix . In this paper, we used two comparators to make sure the symmetrical conduction. The output signal of the proposed AGC is compared with the phase-error voltage (V EA+ and V EA-) in order to obtain PMW + and PWM -. Then, we applied a NOR gate to combine these two signals in order to generate the switch control signal. In this way, the generated switch control signal is always symmetrical with respect to the zero-crossing points of the V CFix , which is applied across the fixed capacitor C Fix .

Two Comparators NOR The accuracy of the tuning system is affected by the accuracy for the switch control signal. As can be seen from the schematic, the accuracy of the proposed switch-signal generator relates mainly to the parameters of the comparator. The comparator used in this circuit is the MAX961, which can provide a settling time of less

AC switch Block

To minimize the effect of the AC switch and to isolate the drive circuit and the auto-tuning system, we used an isolated AC switch that consists of two NMOSs in a totem-pole configuration (source-to-source connected) and an isolated AC switch driver.

The schematic of the designed AC switch is illustrated in Figure 5.25.

We implemented the isolated AC switch driver using a 2.5 kV isolator, ADuM5401, and a 4 A MOSFET driver, ADP3654 [START_REF]Analog Devices[END_REF]. The maximum operation frequency of ADuM5201 is 12.5 MHz, which is higher than the working frequency (1.25 MHz) of the proposed auto-tuning system [START_REF] Devices | ADuM[END_REF]. In addition, it contains an integrated DC-to-DC converter that can provide an isolated ground to the MOSFETs. The MOSFET used in the AC switch is SI4472, which has an ultrasmall output capacitance (160 pF).

Test Results and Stability Analysis

In this section, we present the test results of each block of the auto-tuning system.

Then, we also present the stability of the system. Figure 5.31 is the output of the peak detector with a modulated input signal. The minimum and maximum peak-to-peak voltages of this input signal are 0.1 V and 2 V, respectively. The orange line is the input signal, and the blue line is the output signal.

Test Results of the Functional blocks Automatic Gain Control Block

Two zoomed views of Figure 5.31 are demonstrated in Figures 5.32 and 5.33. By performing calculations, we found the error of the peak detector to be less than 1.5%. The test result of the error amplifier in the AGC circuit is shown in Figure 5.34.

The orange line is the modulated input signal and the blue line is the output signal of the error amplifier. The output voltage of the error amplifier V EAOUT has a range of about 653 mV. According to the datasheet of AD603, the gain controlled by the output voltage of the error amplifier has a range of 26.12 dB. This gain tuning range is fulfil with the 20 times input ratio in our applicaton. The test results of this printed circuit board are as follows. As can be seen from Figure 5.40, the phase-error detector can detect the phase difference between the input signal and the output signal of the class D amplifier, and this phase difference is converted into a phase-error voltage. The phase-error voltage is equal to 2.5 V when the phase difference is π/2. From Figure 5.41, we see that the output signal of the switch-signal generator is symmetrical with respect to the zero-crossing points of the sinusoidal input voltage.

AC Switch Block

Figure 5.42 shows a picture of the prototype of the isolated AC switch bounded by the blue dotted line. The test result of the isolated switch driver is illustrated in Figure 5.43. As can be seen from this figure, the isolated switch driver has a very small delay. The delay is less than 12ns.

Stability Analysis

Based on the analysis in Section 4.2, the imaginary part of the transfer impedance constant resistor shunted with a variable capacitor. Figure 5.44 shows the equivalent circuit of the transducer. According to this figure, we can represent the equivalent capacitance (C Eq ) of the auto-tuning system combined with the transducer using the equation 𝐶 𝐸𝑞 = 𝐶 𝑆𝑉𝑎𝑟 + 𝐶 𝐹𝑖𝑥 + 𝐶 𝑃𝐿𝑜𝑎𝑑 + ∆𝐶 ) -𝐶 𝑃𝐿𝑜𝑎𝑑 ≃ 11.36n 5.32

As analyzed in section 4.5, the proposed auto-tuning system can be considered as a PLL system, and the study of the stability and speed of this auto-tuning system can be simplified to a study of the stability and speed of the equivalent PLL system. The equivalent PLL circuit of the auto-tuning system is shown in Figure 5.45. The open-loop transfer function of the equivalent PLL circuit is described by the following equation. The details of the derivation is presented in Appendix II.

Sgn[VCFix]

𝐺 𝑃𝐿𝐿 (𝑗𝑤) = 𝐾 𝐷 • 𝐾 𝑂 • 𝐺 𝑃𝐷𝐸𝐴 (𝑗𝑤) = 5 𝜋 • 𝜋 30 • 1 𝑗𝑤𝑅 2 𝐶 1 = 1 6𝑗𝑤𝑅 2 𝐶 1

5.33

According to this equation, this PLL system is just has one pole, the phase of the system is always equal to π/2, which means that it is a stable system. However, in real case, the settling time of VCO is equal to the settling time of the automatic gain control amplifier used in the proposed tuning system. In order to realize a stable tuning system, the settling time of the PLL is required to be much larger than the settling time of proposed the automatic gain control amplifier. The settling time of the proposed AGC is 6 μs which is much less than the settling time of the PLL 16.8 μs. Therefore, the proposed auto-tuning system is a stable system.

Summary of the Proposed PCB Circuits

The power supply of the proposed automatic gain control amplifier is ±5 V. The variable gain of this amplifier has a range of 26.12 dB, with a working frequency of 1.25MHz. The settling time of the proposed automatic gain control amplifier is less than 7 periods of the input signal, and its gain error is less than ±1.5 dB.

The proposed phase error detection block, switch signal generation block and AC switch use 5 V single power supply. The proposed phase error detection block allows the tuning of the system by controlling a phase difference (Δφ = π/2) between the half bridge output voltage (V HB ) and the voltage across the tuning capacitor (V CFix ). It also has the capability of transforming the phase difference between V HB and V CFix into a relevant voltage.

The output signal of the proposed switch signal generation block is kept symmetrical with respect to the zero-crossing points of the V CFix across the fixed capacitor C Fix thanks to the phase shifter and the proposed switch signal generation block. In other words, the physical impossibility of over current spikes (having theoretically an infinite intensity) flowing through the AC switch is perfectly eliminated by using the proposed circuit. Moreover, the phase error of the switch signal is less than 4 degree.

At last, for the AC switch block, a high frequency isolated AC switch is realized.

The working frequency of the proposed AC switch can achieve 1.25 MHz, which fulfils our requirement.

All of the functional blocks realized by using printed circuit board meet the requirements of the proposed auto-tuning system and our application. Test results of this auto-tuning system combined with the proposed half-bridge class D amplifier will be presented in chapter 7. simulation results of the proposed integrated circuits in Sections 6.6 and 6.7 respectively.

And a conclusion of this chapter is given out in Section 6.8.

CMOS Technology

We implemented the design of the integrated auto-tuning circuit using the 0.35 μm CMOS process 5 V kit (C35B4C3) developed by Austrian Micro Systems (AMS). In our application, the input range of the automatic gain control amplifier used in the Auto-tuning system is required to have a ratio of 20. To achieve this goal, as well as the high accuracy, we need 5 V transistors to implement the circuit. Also, taking into account the maturity of the CMOS 0.35µm and its acceptable price, we have chosen this CMOS technology.

Fig.6.1 AMS C35B4C3 process (NMOS, PMOS, Capacitors, Resistors). [CMP2015]

This process is a mixed-signal CMOS process that can offer two polysilicon layers, four metal layers, 5 V transistors, and highly resistive poly. The process is demonstrated in Figure 6.1. Table 6.1 shows parameters of the transistors, which were obtained from the datasheet.

The proposed AGC consists of six parts: a VGA, a fixed-gain amplifier (FGA), an output buffer, a peak detector, an error amplifier, and an exponential voltage-to-current converter. The VGA and FGA are used to provide a suitable variable gain. The output buffer is applied to transfer the differential output to single-ended output, and it is also used to make sure the DC voltage of the output signal is constant. Then, we used a peak detector to detect the amplitude of the input signal. We used an error amplifier to compare this amplitude voltage with a reference voltage V Ref to generate the gain-control voltage V Ctr . As mentioned before, the proposed AGC must has a dB linear gain control function. Therefore, an exponential voltage to current converter is introduced to obtain a dB linear gain control function. In reality, nominally identical devices suffer from an unavoidable mismatch due to uncertainties at each step of the manufacturing process. As a result, there would be a DC-offset voltage at the outputs of the amplifier, especially in the high gain setup. The large DC-offset voltage results in signal saturation at the outputs, which prevents us from successfully obtaining the desired signal. The DC offset can also be introduced by the input signal. Therefore, there must be a DC-offset cancelling circuit for the VGA and FGA.

Design Specifications of AGC

In this design, the objective of the proposed AGC is to achieve a large variable-gain range with a suitable bandwidth and dB linear gain control function.

As mentioned previously, the input dynamic of the automatic gain control voltage has a ratio of 20, which means the proposed AGC is required to have a variable gain range of more than 26 dB. Moreover, the working frequency of the proposed auto-tuning system is fixed by the transcuder used, i.e. 1.25 MHz. By taking into account of these design conditions and design margin, we fixed the following specifications for the design of the AGC, as shown in Table 6.2.

Variable Gain Amplifier (VGA)

The core cell of an automatic gain-control system is the VGA, which provides a variable gain for the AGC circuit. The diagram of the proposed VGA is illustrated in The linear input range of the Gilbert cell is usually of the order of several hundreds of millivolts, and for our application, the amplitude of the input signal ranges from 50 mV to 1.5 V, which significantly exceeds the input range of the Gilbert cell. In order to fit the linear input range of the Gilbert cell, we added an attenuation block to reduce the input signal. In addition, we used a DC-offset cancellation circuit to minimize the DC offset that is caused by the mismatch of the input transistors or introduced by the input signals.

The schematic of the attenuation block is illustrated in Figure 6 The analysis of V out-is the same as that of V out+ , and it can be defined by The core of our VGA is a Gilbert cell consisting of four identical cross-connected NMOS's (M1, M2, M3, and M4) as amplifying components, and two identical diode-connected NMOS's (M19, M20) as the load. M1 and M2 are driven by the same current I1; similarly, M3 and M4 are driven by I2. The total current is then divided equally between M19 and M20. By a rough calculation, the gain of this cell is 6.9

𝐴 𝑣 = √ (𝑊 𝐿 ⁄ )
In order to further increase the gain, we added two constant-biased PMOS loads (M17, M18) to remove a large portion of current flowing through M19 and M20. In this thesis, the currents that flow through M17 (I M17 ) and M18 (I M18 ) are chosen such that they are three times the value of the currents that flow through M19 and M20. In this way, A V is doubled.

The small dimensions of M1~M4 and M19 and M20 were chosen carefully to ensure that we obtain a desired bandwidth (at least 5 MHz in our case). The pole associated with PMOS loads (M17 and M18) is critical for determining the bandwidth [LTH2004]. By performing open-circuit time constant (OCTC) calculations,

𝑤 𝑃 = 1 𝐶 𝑔𝑑 (𝑀17,18)
•𝑟 𝑂 (𝑀17,18)

6.10

The resistors R 1,2 were utilized to increase the linear input range of the VGA [TCM2005]. In this way, we can improve the linearity of the VGA without losing any headroom.

The output DC level of the VGA should be stable in order to properly drive the The layout of the proposed variable gain amplifier is presented in Appendix III.

Fixed Gain Amplifier (FGA)

The output range of the proposed VGA circuit is very limited because the use of the attenuator in the proposed VGA. Therefore, a FGA is necessary to enable us to amplify the output signal to the required level. To do so, we proposed an FGA with a very simple structure, as shown in Figure 6.

Exponential Voltage to Current Converter

For our application, the amplitude of the input signal varies over a wide range.

Therefore, the settling time of the AGC circuit is required to be constant. The most popular solution is the introduction of an exponential gain controller in the AGC loop. As discussed in section 5.2.1, in order to make sure the stability of the proposed 134 auto-tuning system, the AGC circuit is required to have a dB linear gain control function.

There are several existing principles to achieve the dB linear gain control function [TCM2005~CHY2001]. In this design, we use the principle proposed in [CHY2001]. It is an exponential voltage to current converter. The schematic of the circuit is shown in Figure 6.9. This circuit is chosen due to its structure and capability to tune the gain of the Gilbert cell linearly from -45.82 dB to -16.27 dB. M3 operates in the linear region can be seen as a resistor, V ctr is the input control voltage, I1 and I2 are the converted currents, and will be mirrored at the tail current by M6 and M7. From our analysis, the relation between V k and V ctr can be roughly described as Equations 6.17 and 6.18 contain Taylor's series expansion form when α, k 1 , k 2 , and K P are proper. According to the Taylor theory, I1 and I2 are approximated as exponential functions with V ctr [CHY2001]. The layout of the proposed fixed gain amplifier is demonstrated in Appendix III. This peak detector has two working phase: tracking phase and holding phase. The working principle of the two-phase peak detector can be described briefly as follows.

𝑉 𝑘 =

Two Phase Peak Detector

During the tracking phase, switches S T turn on and the other switches turn off, which makes the peak detector function as the equivalent circuit shown in Figure 6.11. The operational transconductance amplifier (OTA) supplies current to the current mirror M1 and M2. The capacitor C h is then discharged by the current mirror. In this configuration, the circuit provides tracking, peak detection, and hold functions. The offset of the OPA is described as V offset , and the stored peak voltage on C h can be expressed as 𝑉 𝑐ℎ = 𝑉 𝑜𝑓𝑓𝑠𝑒𝑡 + 𝑉 𝑝𝑒𝑎𝑘

6.19

give the peak detector a very fast following speed.

The switch-control signals of this two-phase peak detector are generated automatically using the voltage at the point V k that is shown in Figure 6.10. The schematic of the switch-control signal generator is presented in Figure 6.13. Based on the analysis of the operation of the proposed two-phase peak detector, we can obtain the its chronograms, which are shown in Figure 6.14. The output stage of this comparator is composed of transistors M7~M10. In this way, the designed comparator can provide a class AB-type of driving capability.

INV Comparator V DC V IN V K V com Comparator S Reset
The schematic of the OTA used in this peak detector is illustrated in Figure 6.16.

The OTA uses the folded cascode structure because it can offer a high output gain with a wide input and output range. Moreover, this amplifier can achieve a wide bandwidth.

The poles of the OTA are described by where R out is the output impedance and C L is the load capacitor of the OTA. C Folding defines the capacitance of the folding stage. To achieve a high-frequency characteristic, the second pole of the OTA must be far from the first pole. The gain of the amplifier can be described by 𝐴 𝑣 = 𝐺 𝑀 𝑅 𝑜𝑢𝑡 ≃ 𝑔 𝑀1 [(𝑔 𝑀9 𝑟 𝑜9 𝑟 𝑜3 ) ∥ (𝑔 𝑀7 𝑟 𝑜7 𝑟 𝑜1 ∥ 𝑟 𝑜5 )]

6.25

The input common-mode range is defined by the following equation.

𝑉 𝐷𝑆6 + 𝑉 𝑇𝑁 ≤ 𝑉 𝐼𝑁 ≤ 𝑉 𝐷𝐷 -𝑉 𝑆𝐺13 -𝑉 𝑆𝐺2 -𝑉 𝑇𝑃

6.26

and this amplifier has an output swing of this amplifier that presented in Equation 6.27.

𝑉 𝐷𝑆6(𝑠𝑎𝑡) + 𝑉 𝐷𝑆8(𝑠𝑎𝑡) ≤ 𝑉 𝑂𝑈𝑇 ≤ 𝑉 𝐷𝐷 -𝑉 𝐷𝑆4(𝑠𝑎𝑡) -𝑉 𝐷𝑆10(𝑠𝑎𝑡) 6.27 Depending on the bandwidth and slew rate requirements, the current flowing through each branch can be estimated. Based on the estimated current, the width-to-length ratios of the transistors can be calculated by

𝐼 𝐷 = 1 2
𝜇 𝑛 𝐶 𝑐𝑜𝑥 𝑊 𝐿 (𝑉 𝐺𝑆 -𝑉 𝑇𝐻 ) 2

6.28

The layout of the proposed peak detecotr is shown in Appendix III.

structure as the OTA used in the designed peak detector. Further, the analysis of the first stage is the same as discussed in Section 6.25. The second stage of the amplifier is a common-source PMOS amplifier with an NMOS current source load. The gain of the second stage can be described by 𝐴 𝑣2 = 𝐺 𝑀 𝑅 𝑜𝑢𝑡 = 𝑔 𝑀11 (𝑟 𝑜11 ∥ 𝑟 𝑜12 )

6.29

The output swing of this stage can be written as 𝑉 𝐷𝑆12(𝑠𝑎𝑡) ≤ 𝑉 𝑂𝑈𝑇 ≤ 𝑉 𝐷𝐷 -𝑉 𝐷𝑆11(𝑠𝑎𝑡) -𝑉 𝐷𝑆12(𝑠𝑎𝑡) 6.30 In order to ensure the stability of the amplifier, we added a Miller capacitor Cc between the first and second stages in order to improve the phase margin of the amplifier. The poles of the designed OPA can be described by

𝑃 1 = 1 [(𝑔 𝑀9 𝑟 𝑜9 𝑟 𝑜3 )∥(𝑔 𝑀7 𝑟 𝑜7 𝑟 𝑜1 ∥𝑟 𝑜5 )]𝐶 𝑐 𝐴 𝑣2 6.31 𝑃 2 = 𝑔 𝑀12 𝐶 𝐿

6.32

The layout of the proposed output buffer is presented in Appendix III.

Error Amplifier of the AGC

The simplified schematic of the error amplifier used in the proposed AGC is shown in Figure 6.19. The peak detector used in the AGC is a negative peak detector, and therefore, the error amplifier designed for the AGC is a positive integrator. In this The voltage of the capacitor C 1 is defined as V C1 . If the input signal V in is not equal to V ref , C 1 is charged by the current (I R1 ) that flows through R 1 . I R1 can be described by 𝐼 𝑅1 = 𝑉 𝑖𝑛 -𝑉 𝐶1 𝑅 1

integrator, R 1 = R 2 = R and C 1 = C 2 = C.

6.33

Then, the equation of V C1 can be obtained as

𝑉 𝐶1 = 1 𝐶 1 ∫ 𝐼 𝑅1 𝑑𝑡 = 1 𝑅 1 𝐶 1 ∫ (𝑉 𝑖𝑛 -𝑉 𝐶1 )𝑑𝑡 6.34
and this equation can be rewritten as

𝑉 𝐶1 + 1 𝑅 1 𝐶 1 ∫ 𝑉 𝐶1 𝑑𝑡 = 1 𝑅 1 𝐶 1 ∫ 𝑉 𝑖𝑛 𝑑𝑡 6.35
According to the "virtual short" of the amplifier,

V -= V + = V C1 . The current flowing through R 2 (I R2 ) is equal to (V C1 -V ref )/R 2 . The voltage across C 2 is defined as 𝑉 𝐶2 = 1 𝐶 2 ∫ 𝐼 𝑅2 𝑑𝑡 = 1 𝑅 2 𝐶 2 ∫(𝑉 𝐶1 -𝑉 𝑟𝑒𝑓 )𝑑𝑡 6.36
The output voltage of the error amplifier is obtained as

𝑉 𝑜𝑢𝑡 = 𝑉 + + 𝑉 𝐶2 = 𝑉 𝐶1 + 1 𝑅 2 𝐶 2 ∫(𝑉 𝐶1 -𝑉 𝑟𝑒𝑓 )𝑑𝑡 6.37
By substituting Equation 6.33 into Equation 6.35, V out can be redefined as 𝑉 𝑜𝑢𝑡 = 1 𝑅𝐶 ∫(𝑉 𝑖𝑛 -𝑉 𝑟𝑒𝑓 )𝑑𝑡

6.38

The output voltage of the error amplifier is related to the difference between its input signal and the reference voltage. As discussed in our analysis in chapter 5, the values of R and C must be carefully chosen to guarantee the stability of the AGC circuit.

As calculated in section 5.2.2, the capacitance of C is about few nF, which is too large to be realized by using integrated circuit. Therefore, this capacitor is realized by using out-chip component.

The layout of the proposed error amplifier used in the AGC is shown in Appendix III.

Integrated Phase-error Detector

Design of the Phase-error detector

As shown in Figure 6.20, the phase-error detector circuit consists of two parts: a phase-difference detector circuit and an error amplifier. In the phase-difference detector circuit, we first use a comparator to compare the input signal with its DC voltage V DC in order to obtain its sign signal. Then, we used an XOR gate to obtain the phase difference of this sign signal and the clock signal. Next, to generate a phase error signal, we used an error amplifier to compare the phase-difference signal with a reference voltage, which represents a π/2 phase difference.

To guarantee the stability of the system, the error amplifier needs to be carefully designed. The settling time of the phase-error amplifier needs to be larger than the settling time of the AGC. Based on the calculation, the capacitance of the capacitor used in the error amplifier is a few nF, which is too large to be realized using an IC, so we used an out-chip capacitor here. The comparator used in this circuit is the same as that used in the switch-control signal generator of the two-phase peak detector. The layout of the phase error detector is shown in Appendix III. resolution of the comparator is presented in Appendix I. In this thesis, we use an external clock signal as the control signal (clk) of the latch stage, the frequency of the external signal is chosed to be ten times as the output signal of the AGC.

Bandgap Voltage and Current Reference Circuit

Schematic Design of the Bandgap Reference Circuit

We used the bandgap reference circuit to provide a temperature-independent power supply to the designed IC. The principle of the bandgap voltage reference is to balance the negative temperature coefficient of the temperature PN junction (V BE ) with the positive temperature coefficient of the thermal voltage, V t = kT/q. The current mirror (M3, M4) maintains the identical currents in BJTs Q1, Q2, and Q3. Thus, we obtain the following equations:

𝑉 𝐵𝐸1 = 𝐼 2 𝑅 1 + 𝑉 𝐵𝐸2 6

6.43

The OPA used in this circuit is the same as the one used in the output buffer. The bandgap circuit requires a startup circuit to ensure that the circuit is not stuck at its "zero" operating point. The designed startup circuit is presented in the area bounded by the red dotted line in Figure 6.24. The designed bandgap voltage and current reference circuit can operate with a supply voltage between 3 V~5 V, and at temperatures between -20°C and 100°C. The designed circuit can generate a 1.222-V reference voltage and a 50-μA reference current with a maximum temperature coefficient of 15 ppm/°C.

Pre-layout Simulation Results

The proposed auto-tuning system was designed using AMS CMOS 0.35 μm technology. For a voltage supply of 5 V, the simulation results are given below.

Automatic Gain Control Circuit

The The frequency response of the proposed VGA with the DC-offset cancellation (DCOC) circuit is illustrated in Figure 6.27. As can be seen from this figure, the VGA provides a variable gain that ranges from -45.82 dB to -7.03 dB with a -3 dB bandwidth from 37 kHz ~ 54 MHz. In addition, the DC gain of the VGA is from -52 dB to -36 dB, which means that the DC offset is well decayed by the DCOC circuit. The frequency response of the proposed OPA used in the output buffer is shown in Figure 6.30. This OPA can offer a gain of 126.5 dB with a 48-MHz bandwidth and 59° phase margin. The simulated slew rate of the designed OPA is presented in Figure 6.31.

The slew rate of the proposed OPA is 169.6 V/μs. The slew rate of this OTA is 206.3 V/μs. The simulation result of the slew rate is demonstrated in Figure 6.37.

Figure 6.38 shows simulation results of the peak detector with several sinusoidal input signals that have different frequencies and amplitudes. In our applicaton, the working frequency of the auto-tuning system is 1.25MHz, but the designed integrated AGC has a wide working frequency range, which is from 125kHz~3MHz. We can assume that if the proposed AGC works well in its working frequency range (125k~3MHz), it can also work well at 1.25MHz. amplitude is 50 mV. Figure 6.55(b) is the simulation result obtained using a 3 MHz modulated sinusoidal input signal. The amplitude range of the input signal is the same as the previous one.

As can be seen from this figure, the settling time of the proposed peak detector is less than one period for different input frequencies. The output error of this peak detector is shown in Figure 6.56. The maximum output error of the proposed peak detector is less than 16 mV. The offset of the AGC circuit is significantly reduced by the output DC-offset cancellation circuit, and the maximum output DC offset is only 3 mV.

Phase-error Detector

The post-layout simulation results of the phase-error detector are presented in

Bandgap Reference Circuit

The post-layout simulation results of the proposed bandgap reference circuit are illustrated in Figure 6.61.

Conclusion of the Proposed Integrated Auto-tuning System

In this chapter, an integrated version of the proposed auto-tuning system is designed and presented. The surface area of the proposed integrated auto-tuning system is only 0.42 mm 2 without the out-chip components, which is much smaller than the PCB version (110 cm 2 ). Therefore, it is perfectly suitable for our HIFU application which needs 256 auto-tuning feed-back loops.

The proposed integrated AGC used for the auto-tuning system has a -3 dB bandwidth which is ranging from 37.5 kHz to 8.36 MHz. Because the proposed AGC has a dB-linear gain control function, the settling time of the AGC is nearly constant.

According to the post-layout simulation results, the maximum settling time of the proposed AGC is less than 15 periods. Besides, it can provide 38.51 dB variable gain with a gain control voltage from 0.35 V to 3.5 V.

The same as the PCB version, the integrated phase-error detector designed in this chapter, allows the tuning of the system by controlling a phase difference (Δφ = π/2) between the half bridge output voltage (V HB ) and the voltage across the tuning capacitor (V CFix ). It also has capability of transform the phase difference between V HB and V CFix into a relevant voltage.

The latched comparator used in the the integrated switch signal generator achieves a resolution of 0.5mV, and the relevant phase error of the generated AC switch control signal is less than 0.4°. The output switch control signal of this integrated circuit is always symmetrical with respect to the zero-crossing points of the V CFix , which is applied across the fixed capacitor C Fix . In other words, the physical impossibility of over current spikes (having theoretically an infinite intensity) flowing through the AC switch is perfectly eliminated by using the proposed circuit.

Moreover, because all of the proposed integrated circuits have wide working frequency range, the proposed integrated auto-tuning system can be used HIFU applications with other working frequency. The close-loop test of the proposed auto-tuning system combined with the proposed power amplifier will be presented in chapter 7. The equivalent circuit of the test circuit is shown in Figure 7.1. The input signal of the half-bridge driver is a pulse signal with a 50% duty cycle and 5 V peak level, and the power supply of the half-bridge circuit is also 5 V. The frequency of the input signal is 1.25 MHz.

For an ultrasonic transducer, the variation of its imaginary impedance is usually a process of slow change, and this variation is hard to control. In this case, we use a switch controlled error capacitor C Error in the test circuit instead of the real transducer. This error capacitor is controlled by a square wave signal (PWM E ). By this way, it provides a sudden changing of the imaginary impedance. In this thesis, we set the value of C Error to 50 pF, and PWM E used in this thesis is a 5 kHz square wave signal.

Test results

The test results of the proposed ultrasonic generator are shown in Figure 7. As can be seen from the figure, the phase error caused by C Error is eliminated, and the phase difference between the output signal of the power amplifier and the output signal of the auto-tuning circuit is forced to π/2. In other words, the ultrasonic generator is well tuned.

Simulation Results of Ultrasonic Generator (IC)

In this section, we present the simulation results of the ultrasonic generator with an IC auto-tuning circuit.

Pre-layout Simulation Results

The pre-layout simulation results of the proposed ultrasonic generator with the integrated auto tuning circuit are shown in Figure 7.5. As can be seen from this figure, the post-layout simulation of the auto-tuning system is nearly the same as the pre-layout simulation results.

The curves of the power efficiency versus the phase error with or without the auto-tuning circuit are illustrated in Figure 7.9. As can be seen from this figure, the power efficiency can be greatly improved using our proposed auto-tuning system, which can result in an average power savings of nearly 20% compared to the power amplifier without the auto-tuning circuit. The power consumption curve of our circuit is shown in Chapter 8

Conclusions and Future Work

Conclusions

The objective of this thesis was to design an ultrasonic generator for MRI-guided HIFU applications. The proposed ultrasonic generator is composed of a power amplifier and an auto-tuning system. There were several challenges in the design of the proposed ultrasonic generator:

1. In the real HIFU application, there usually 256 ultrasonic transducers in the phased array. Therefore, the area of the proposed ultrasonic generator needs to be as small as possible.

2. In this thesis, we mainly focus on the MRI guided HIFU system. MRI systems are not compatible with highly magnetic components, and therefore, the use of bulky magnetic components, such as transformers and large inductors, must be avoided.

3. A power amplifier is needed to realize a high efficiency because if the efficiency of the designed power amplifier is low, there will be an overheating problem.

4. The power that is required for the transducer is 3 W, and the peak-to-peak voltage of the power supply is required to be about 260 V. The working frequency of the transducer is 1.25 MHz, so the power amplifier is required to be sufficiently fast.

5. The resettling time of the automatic impedance-tuning network must be as small as possible in order to prevent the reflected power and protect the transducer.

In this thesis, we proposed a half-bridge class D amplifier, which is capable of providing 3 W power with a working frequency of 1.25 MHz and 5 V power supply.

The power amplifier was fabricated by using printed circuit board and discrete components that makes it very cheap and easy to fabricate. In other words, it has a very good cost performance ratio. The total price of the proposed circuit is less than 10 €.

The power efficiency of the presented amplifier is 82.6% with a total surface area of 10 cm 2 . Without using of the bulky magnetic components, it is more compatible with MRI guided HIFU system than the traditional amplifiers.

Besides, we built an electrical model of the ultrasonic transducer, and based on this model we also realized a fast auto-tuning system. The proposed auto-tuning system is based on the topology of synchronous-switched capacitors instead of self inductors or self capacitors. In addition, the inductor used in this auto-tuning system is a small air-core inductor that is compatible with MRI systems. Moreover, this novel auto-tuning system does not require MCUs or PCs for the detection of the impedance variation of ultrasonic transducers.

We presented two versions of auto-tuning systems. The first version was realized using discrete components and a PCB. Test results confirm that this auto-tuning system can effectively compensate the variations of the imaginary part of the transducer's impedance. For this version, the working frequency can reach 1.25 MHz which is the working frequency of the transducer. However, because of the use of discrete components, the area required for the first version of auto-tuning system is 110 cm 2 , which is unsuitable for the phased-array HIFU applications. In addition, the power consumption of this version is about half of the saved power, which is uneconomic for our application. Therefore, we designed a second version of the proposed auto-tuning system using an integrated circuit. The proposed integrated auto-tuning circuit consists of three parts: an AGC amplifier, a phase-error detector, and a switch-signal generator. It replaces the AGC board and the phase-error detector board in the first version.

The proposed AGC amplifier has a dB linear gain tuning function, and the variable gain is ranging from -8.82 dB to 29.97 dB with a -3 dB bandwidth from 36 kHz to 8.75

MHz. Moreover, the phase-error detection block combined with the switch signal generation block can transfer the phase error difference into a switch control signal.

This switch control signal is always symmetrical with respect to the zero-crossing points of the output signal of the tuning circuit. In other words, the physical impossibility of over current spikes (having theoretically an infinite intensity) flowing through the AC switch is perfectly eliminated by using the proposed circuit.

The area of the proposed integrated auto-tuning circuit is only 0.42 mm 2 instead of 80 cm 2 in the first version. This chip can also offer a wide operation frequency range, which is from 125 kHz to 3 MHz. The power consumption of the IC is only 137 mW, which is also a significant improvement.

Future Work

The layout of the designed integrated auto-tuning system was sent to the AMS foundry for fabrication via CMP on September 14 th , 2015, and the fabricated circuit is expected to be returned towards the end of 2015. The fabricated chip will be tested to verify its performance. In next step, we will optimize the design of the integrated circuit to minimize its surface as well as the power consumption. Moreover, to minimize the area of the whole ultrasonic generator, we will also design the power amplifier used in it by using integrated circuit. In addition to this, we will setup of the test bench in order to test the ultrasonic generator with the real transducer. After the test, if it is possible, we will make a prototype of the power supply to the phased-array HIFU system, and test it with the MRI equipment to verify the performance and compatibility. APPENDIX III.

The proposed design has been implemented in a CMOS 0.35µm technology (C35B4C3) provided by Austrian Micro Systems. We have chosen this technology for its maturity, its accessibility by universities and its reasonable price of fabrication.

Automatic Gain Control Amplifier

The proposed AGC consists of six parts: a VGA, FGA, output buffer, peak detector, error amplifier, and exponential voltage-to-current converter. The layout design of the proposed VGA combined with the FGA, AC coupling circuit, and exponential voltage-to-current converter is illustrated in Figure 3. We matched the differential pairs and current mirrors used in the VGA, FGA, DCOC, and CMFB circuits by using the common-centroid layout technique [HA2006], and we added a connected dummy in order to obtain extra matching. The layout of the output buffer designed for the AGC is demonstrated in Figure 5.

The designed OPA is shown in the area bounded by the red dotted line, and the resistors used in this output buffer are located within the blue dotted line.

Phase Error Detector

The phase-error detector of the auto-tuning system is composed of a phase detector and a phase-error amplifier. The layout of the phase-error detector is displayed in Figure 7. The designed comparator of the phase detector is shown by the red rectangle, and the XOR gate is shown in the blue rectangle. The error amplifier of the phase-error detector is shown in Figure 8. The OPA used in this error amplifier is the same as the one used in the error amplifier of the peak detector. The resistors of this error amplifier are displayed by the blue dotted line.

The capacitors used in this error amplifier are also out-chip capacitors.

Bandgap Reference Circuit

The layout of the bandgap reference circuit is shown in Figure 10. The PNP BJTs used in the bandgap reference are centrosymmetric, and all of the current mirrors used in this bandgap circuit are matched by using the connected dummy.

Fig. 2

 2 Fig.2 Prototype de l'amplificateur de puissance classe D proposé e.

Fig. 3

 3 Fig.3 Chronogrammes de sortie de demi-pont VHB et sortie de l'amplificateur de

Fig. 4 Fig. 5

 45 Fig.4 Sché ma de principe de systè mes d'accord automatique, qui est basé sur le capacité

Fig. 6

 6 Fig.6 Diagramme de la réalisation d'auto-ré glage system basé sur condensateur commuté synchrone.

Fig. 7

 7 Fig.7 Prototype de l'auto-ré glage system en circuit é lectrique imprimé . Le circuit é quivalent du circuit de test est illustré dans la Figure 8. On utilise un condensateur d'erreur C Error (15%C S ), qui est contrôlé par un signal à onde carré e de 5

Fig. 8

 8 Fig.8 Essai é quivalent circuit du gé né rateur d'ultrasons avec l'auto-ré glage circuit en

Fig. 9

 9 Fig.9 Les ré sultats des tests du gé né rateur d'ultrasons avec l'auto-ré glage circuit en circuit é lectrique imprimé . Ch1 (orange): Signal de sortie du circuit en demi-pont VHB: 5V/div. Ch2 (vert): Erreur signal de commande du condensateur PWME: 5V/div. Ch3 (bleu): Erreur de phase de tension VOEA gé né ré e par le bloc deteciotn: 500mV/div. Ch4 (rose): Signal de sortie de l'amplificateur de puissance VCFix: 100V/div.

Fig. 10

 10 Fig.10 Post-layout de l'auto-ré glage system en circuit inté gré . Le circuit é quivalent du circuit de test est illustré dans la Figure 11. On utilise un condensateur d'erreur C Error (15%C S ), qui est contrôlé par un signal à onde carré e de 16.7 kHz, pour simuler le plus mauvais é tat d'impé dance le drift. Pour la version d'IC, pour simplifier et accé lé rer la simulation de l'ensemble du systè me, nous avons utilisé un amplificateur de puissance é quivalente et circuit de l'interrupteur de AC au lieu de la vraie.

Fig. 11

 11 Fig.11 Essai é quivalent circuit du générateur d'ultrasons avec l'auto-ré glage circuit en circuit inté gré .

Fig. 12 Fig. 13

 1213 Fig.12 Ré sultats de simulation de l'auto-ré glage circuit en circuit inté gré .

Figure 13 Fig. 14

 1314 Figure 13 est le ré sultat de la simulation de la consommation é lectrique de l'auto-ré glage circuit en circuit inté gré . Les é conomies d'é nergie contre les erreurs de phase avec ou sans circuit de ré glage automatique est illustré dans la Figure 14.

ACKNOWLEDGEMENTI

  would like to express my great appreciation to Professor Robert Sobot and Professor Luc Hebrard for agreeing to take the time to review my PhD. thesis. I am particularly grateful to Professor Patricia Desgreys and Professor Nicolas Mauduit for accepting to examine my thesis. I would like to express my deepest appreciation to all those who provided me the possibility to complete this dissertation. A special gratitude I give to my supervisor Professor Ming Zhang, who has guided, advised and helped me to go through the whole PhD study in many ways. I'd like to offer my great thanks to all the supports provided by Romain Denié port and Professor Francis Rodes. I would like to express my great appreciation to China Scholarship Council (CSC), who provide the financial support during my PhD study. My deepest thanks I give to my parents and my girlfriend, your love, support and tolerance have always been my source of courage and momentum to keep going.

Table 6. 1 FiguresFig. 1 . 1 Fig. 1 . 2 Fig. 1 .

 111121 Fig.1.1 Diagrams of piezoelectric transducer (a), capacitive transducer (b) and magnetostrictive transducer (c). ................................................................................................Fig.1.2 Pictures of a real USgFUS (Left) and MRgFUS (Right). .............................................Fig.1.3 The temperature characteristics and pressure sound wave of HIFU. ........................

Fig. 2 . 1

 21 Fig.2.1 Structure of the ultrasonic transducer used in HIFU applications. .........................

Fig. 2 . 2

 22 Fig.2.2 Model of the ultrasonic transducer. [GM1997] ..........................................................

Fig. 2 . 3

 23 Fig.2.3 Simulink model of the ultrasonic transducer. [SM2008] ...........................................

Fig. 2 . 4

 24 Fig.2.4 Equivalent circuit of the piezoelectric element near its resonance frequency. [VAA2008] ..................................................................................................................................

Fig. 2 . 5

 25 Fig.2.5 Equivalent circuit of the ultrasonic transducer used in this thesis. ..........................

Fig. 2 . 6

 26 Fig.2.6 Simplified equivalent circuit of the ultrasonic transducer at its operational frequency. ...................................................................................................................................

Fig. 2 . 7 Fig. 2 .

 272 Fig.2.7 Measured impedance of the transducer (Red) and the impedance of the equivalent circuit on the Smith chart (Blue).............................................................................................. Fig.2.8 (a) Real parts of the measured impedance (Red) and the equivalent impedance (Blue). (b) Imaginary parts of the measured impedance (Red) and the equivalent impedance (Blue). ......................................................................................................................

Fig. 2 .

 2 Fig.2.9 (a) Phase curves of the measured impedance (Red) and the equivalent impedance (Blue). (b) Module value of the measured impedance (Red) and the equivalent impedance (Blue). .........................................................................................................................................

Fig. 2 .Fig. 2 .Fig. 2 .Fig. 2 .

 2222 Fig.2.10 Simplified diagram of the static impedance tuning network ultrasonic transducer. ..................................................................................................................................................... Fig.2.11 Simplified equivalent circuits of the transducer. ......................................................

Fig. 2 .Fig. 2 .Fig. 2 .Fig. 2 .

 2222 Fig. 2.14 Diagram of the L tuning network for the transducer. ............................................Fig.2.15 Diagram of the variable-tuning network for the transducer. .................................Fig.2.16 Equivalent circuits of (a) the bridge method and (b) the I-V method. ...................Fig.2.17 Equivalent circuits of the auto-balancing method (a) and resonance method (b).

Fig.3. 1

 1 Fig.3.1 Simplified schematic of class A, B, and AB power amplifiers. ..................................

Fig.3. 2

 2 Fig.3.2 Operating points of class A, B and AB amplifiers. [VAA2008] .................................

Fig. 3 . 3 Fig. 3 . 4

 3334 Fig.3.3 Waveform of the drain current in time domain. ........................................................Fig.3.4 Switch method of the transistor in a switched-mode amplifier. [VAA2008] ............

Fig. 3 . 5

 35 Fig.3.5 Simplified schematic of the basic switched-mode amplifier. .....................................

Fig. 3 . 6

 36 Fig.3.6 Simplified schematics of the parallel LC tuning network (left) and the series LC tuning network (right). .............................................................................................................

Fig. 3 . 7 Fig. 3 . 8

 3738 Fig.3.7 Simplified schematic of half-bridge class D amplifier with a duty cycle of 50% (left), and the equivalent circuit of this amplifier (right). ................................................................Fig.3.8 Simplified schematic of half bridge class D amplifier with a duty cycle of 50%. ...Fig.3.9 Simplified schematic of class E amplifier (left) and the equivalent circle of this amplifier (right). ........................................................................................................................Fig.3.10 Schematic of switched-mode amplifier with step-driving method. ........................

Fig. 3 .

 3 Fig.3.11 Schematic of switch-mode amplifier using flyback topology. .................................

Fig. 3 .

 3 Fig.3.12 Schematic of switch-mode amplifier using push-pull driving method. ..................

Fig. 3 .

 3 Fig.3.13 Schematic of the multicell linear-power amplifier. [TYC2008] ..............................

Fig. 3 .

 3 Fig.3.14 Diagram of the class AB power amplifier with predistortion system [SK2015]. ...

Fig. 3 .Fig. 3 .

 33 Fig.3.15 Schematic of the class D power amplifier with an inverter MOSFETs [HT2006]. Fig.3.16 Schematic of class E amplifier combined with a flyback converter [CHL2009]. ..Fig.3.17 Schematic of Class D amplifier for military applications [LJGK2008]. ................

Fig. 3 .Fig. 3 .Fig. 3 .Fig. 3 .

 3333 Fig.3.18 Schematic of the full-bridge class D amplifier for Audio Beam [YL2007]. ...........

Fig. 3 .Fig. 3 .Fig. 3 .Fig. 3 .

 3333 Fig.3.22 Simplified schematic of the proposed half-bridge class D power amplifier with a static impedance tuning network. ............................................................................................Fig.3.23 Equivalent circuit of the amplifier during the first operating cycle (0≤t<π/ω). Fig.3.24 Equivalent circuit of the amplifier during the second cycle (π/ω≤t<2π/ω). .........Fig.3.25 Chronogram of output voltage of half-bridge (VHB), voltage applied across CFix (VCFix) and the current flows through L (IP). ...........................................................................

Fig. 3 .

 3 Fig.3.26 Measurements of the series impedance of the ultrasonic transducer. ....................

Fig. 3 .

 3 Fig.3.27 Series equivalent circuit of the ultrasonic transducer at its working frequency. ..

Fig. 3 .Fig. 3 .Fig. 3 .

 333 Fig.3.28 Parallel equivalent circuit of the ultrasonic transducer at its working frequency.59 Fig.3.29 Schematic of the proposed class D power amplifier with a static L-type tuning network....................................................................................................................................... Fig.3.30 Designed printed circuit board of the proposed class D power amplifier. .............

Fig. 3 .Fig. 3 .Fig.4. 1 Fig.4. 2 Fig.4. 3 Fig. 4 . 4

 3312344 Fig.3.31 Prototype of the proposed class D power amplifier. ................................................Fig.3.32 Chronograms of the gate-control signal OUTH and OUTL generated by the half-bridge driver with a 1.25 MHz, 5 V input signal. ...........................................................Fig.3.33 Chronograms of the half-bridge output signal VHB and the output of the power amplifier with a 1.25 MHz, 5V input signal. ........................................................................... Fig.4.1 Schematic of the impedance-measurement circuit. ...................................................Fig.4.2 Measured curves of the imaginary part of the transducer's impedance versus temperature................................................................................................................................ Fig.4.3 Imaginary impedances of transducers that are tuned by a static-tuning network.Fig.4.4 Imaginary impedances of different mono-elements in the phased-array used in this thesis. ..........................................................................................................................................

Fig. 4 . 5

 45 Fig.4.5 Histogram of the measured imaginary impedances. ................................................. Fig.4.6 Power efficiency curve of the power amplifier with a static tuning network ..........

Fig. 4 . 7 Fig. 4 . 8 Fig. 4 . 9

 474849 Fig.4.7 Simplified configuration of the auto-tuning network proposed in [SP2005]. ..........

Fig. 4 .

 4 Fig.4.10 Flow chart of the auto-tuning network presented in [RHN2013]. ..........................

Fig. 4 .Fig. 4 .Fig. 4 .Fig. 4 .Fig. 4 .

 44444 Fig.4.11 Simplified circuit of the proposed synchronous switched capacitor. ...................... Fig.4.12 Waveform of the synchronous switched capacitor. ..................................................Fig.4.13 Waveform of the auto-tuning system with a non-linear transfer function. ...........Fig.4.14 Waveform of the auto-tuning system with a linear transfer function. ...................Fig.4.15 Diagram of the realization of the proposed auto-tuning system based on synchronous switched capacitor. ..............................................................................................Fig.4.16 Chronograms of the proposed auto-tuning system. .................................................Fig.4.17 Equivalent PLL circuit of the auto-tuning system. ..................................................

Fig. 4 .

 4 Fig.4.18 Relationship between the phase difference ∆θ and the phase error voltage VPD. ..

Fig.5. 1 A

 1 Fig.5.1 A half bridge class D amplifier tuned by a synchronous switched capacitor. ..........

Fig.5. 2

 2 Fig.5.2 Simplified diagram of feedforward (left) and feedback (right) AGC circuit. ..........

Fig. 5 . 3 Fig. 5 . 4 Fig. 5 . 5 Fig.5. 9 Fig. 5 .Fig. 5 .

 535455955 Fig.5.3 Diagram of the proposed automatic gain congrol amplifier. ....................................Fig.5.4 Schematic of the output signal attenuator. .................................................................Fig.5.5 Simulink model of AGC with linear gain function [PJPA2011]. ...............................Fig.5.6 Time response of linear AGC for diffrent stepwise functions. .................................. Fig.5.7 Simulink model of AGC with exponential gain function [PJPA2011]. .....................Fig.5.8 Time response of exponential AGC with different stepwise functions. ....................Fig.5.9 Schematic of the proposed variable gain amplifier. ...................................................Fig.5.10 Schematic of the proposed peak detector. .................................................................Fig.5.11 Chronogram of the proposed peak detector. ............................................................

Fig. 5 .

 5 Fig.5.12 Equivalent circuit of the peak detector during period (0 ≤ t ≤ T1). ...............

Fig. 5 .

 5 Fig.5.13 Equivalent circuit of the peak detector during period (T1 ≤ t ≤ T2). .............

Fig. 5 .

 5 Fig.5.14 Equivalent circuit of the peak detector during period (T2 ≤ t ≤ T3). ............. Fig.5.15 Equivalent circuit of the peak detector during period (T3 ≤ t ≤ T4). .............

Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .Fig. 5 .

 555555555555555555 Fig.5.16 Schematic of the switch signal generator of the peak detector. ............................

Fig. 5 .

 5 Fig.5.39 Simplified schematic of the proposed phase error detection block combined with switch signal generator. ...........................................................................................................

Fig. 5 .

 5 Fig.5.40 Test results of the phase-error detector. ..................................................................

Fig. 5 .Fig. 5 .Fig. 5 .Fig.6. 1 AMSFig.6. 2 Fig. 6 . 3 Fig. 6 . 4 Fig. 6 . 5 Fig. 6 . 8 Fig. 6 . 9 Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig.7. 1

 5551263646568696666666666666666666666666666666666666661 Fig.5.41 Test result of the switch-signal generator. ............................................................... Fig.5.42 Prototype of the AC switch in the area bounded by the blue line......................... Fig.5.43 Test result of the isolated switch driver of the AC switch. .....................................

Fig.7. 2

 2 Fig.7.2 Test results of ultrasonic generator with the proposed printed circuit board auto-tuning circuit. ..................................................................................................................

Fig. 7 . 3 Fig. 7 . 4 Fig. 7 . 5 Fig. 7 . 6 Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 1 Fig. 1 . 1

 73747576123456789111 Fig.7.3 Zoomed views of the simulation results of ultrasonic generator with the proposed printed circuit board auto-tuning circuit. .............................................................................

Fig. 1 . 2

 12 Fig.1.2 Pictures of a real USgFUS (Left) and MRgFUS (Right).

Fig. 1 .

 1 Fig.1.3 The temperature characteristics and pressure sound wave of HIFU. The temperature characteristics and pressure sound wave of a HIFU system are illustrated in Figure 1.3. The focused zones usually have a width of 1-3 mm, length of 8-10 mm, and height of 1-3 mm [DTJ2008].

Fig. 2 .

 2 Fig.2.3 Simulink model of the ultrasonic transducer. [SM2008]

Fig. 2 . 5

 25 Fig.2.5 Equivalent circuit of the ultrasonic transducer used in this thesis.

Fig. 2 .

 2 Fig.2.7 Measured impedance of the transducer (Red) and the impedance of the equivalent circuit on the Smith chart (Blue).

  Figure 2.9 (a) shows impedance phase curves of the measured data and the equivalent circuit. And the module value of the measured impedance and the equivalent impedance is ploted in

Figure 2 .

 2 Figure 2.9 (b).

Fig. 2 .Fig. 2 .

 22 Fig.2.8 (a) Real parts of the measured impedance (Red) and the equivalent impedance (Blue). (b) Imaginary parts of the measured impedance (Red) and the equivalent impedance (Blue).

Figure 2 .Fig. 2 .

 22 Figure 2.10 shows the simplified diagram of the static impedance-tuning network for ultrasonic transducers.

Figure 2 .

 2 Figure 2.11 shows the simplified equivalent circuit of the transducer.

Fig. 2 .

 2 Fig.2.11 Simplified equivalent circuits of the transducer.

Fig. 2 .

 2 Fig.2.12 Parallel tuning network of the transducer (a) and series tuning network of the

Figure 2 .Fig. 2 .

 22 Fig.2.13 Schematics of the L tuning network (a), Γ tuning network (b), T tuning network (c) and П tuning network (d).

Fig. 2 .

 2 Fig. 2.14 Diagram of the L tuning network for the transducer.

Fig. 2 .

 2 Fig.2.15 Diagram of the variable-tuning network for the transducer.

Fig. 2 .

 2 Fig.2.16 Equivalent circuits of (a) the bridge method and (b) the I-V method.

Figure 2 .

 2 Figure 2.16(a) presents the equivalent circuit of the bridge method. Z X is the unknown impedance and Z 1, Z 2, and Z 3 are the known impedances. If there is no current flow through the detector D, the value of Z X can be obtained by 𝑍 𝑋 = 𝑍 1 𝑍 2

Fig. 2 .

 2 Fig.2.17 Equivalent circuits of the auto-balancing method (a) and resonance method (b).

Fig.3. 1 Fig.3. 2

 12 Fig.3.1 Simplified schematic of class A, B, and AB power amplifiers. The relationships between the drain to source voltage V DS and the drain current I Drain of the class A, B and AB power amplifiers operating point are plotted in Figure 3.2

Fig. 3 . 3

 33 Fig.3.3 Waveform of the drain current in time domain.

  Fig.3.4 Switch method of the transistor in a switched-mode amplifier. [VAA2008]

  Fig.3.5 Simplified schematic of the basic switched-mode amplifier.

  Fig.3.6 Simplified schematics of the parallel LC tuning network (left) and the series LC

  Based on the structure, there are two types of Class D amplifiers, namely the class D half-bridge voltage-switched amplifier and the full-bridge voltage-switched amplifier [NMA2007]. There are currently many different operating methods for class D amplifiers. In this thesis, we focus on the class D amplifier with a duty cycle of 50%. The schematic and equivalent circuit of the half-bridge class D amplifier are illustrated in Figure 3.7 (left) and (right), respectively.

  Fig.3.7 Simplified schematic of half-bridge class D amplifier with a duty cycle of 50% (left), and the equivalent circuit of this amplifier (right).

  Fig.3.8 Simplified schematic of half bridge class D amplifier with a duty cycle of 50%.

  Fig.3.9 Simplified schematic of class E amplifier (left) and the equivalent circle of this amplifier (right).

Fig. 3 .

 3 Fig.3.10 Schematic of switched-mode amplifier with step-driving method.

Figure 3 .Fig. 3 .

 33 Figure3.11 shows the schematic of the amplifier using the flyback method. The flyback topology uses a transformer with a signal switch to amplify the signal. The switch is connected to the primary coil, and the transducer is connected to the secondary coil.

Fig. 3 .

 3 Fig.3.12 Schematic of switch-mode amplifier using push-pull driving method.

Fig

  Fig.3.13 Schematic of the multicell linear-power amplifier. [TYC2008]

  Fig.3.14 Diagram of the class AB power amplifier with predistortion system [SK2015].

Fig. 3 .

 3 Fig.3.15 Schematic of the class D power amplifier with an inverter MOSFETs [HT2006].

Fig. 3 .

 3 Fig.3.16 Schematic of class E amplifier combined with a flyback converter [CHL2009].

Fig. 3 .

 3 Fig.3.17 Schematic of Class D amplifier for military applications [LJGK2008].

Fig. 3 .

 3 Fig.3.18 Schematic of the full-bridge class D amplifier for Audio Beam [YL2007].

Fig. 3 .

 3 Fig.3.19 Schematic of the class D amplifier for LIPUS [AWT2010].

Fig. 3 .

 3 Fig.3.20 Diagram of the half-bridge class D power amplifier proposed in this thesis.

Fig. 3 .Fig. 3 .

 33 Fig.3.21 Operation waveform of the proposed half-bridge class D power amplifier. The simplified schematic of the half-bridge class D power amplifier with a static impedance tuning network is illustrated in Figure 3.22.E

Fig. 3 .

 3 Fig.3.23 Equivalent circuit of the amplifier during the first operating cycle (0≤t<π/ω).

Fig. 3 .

 3 Fig.3.24 Equivalent circuit of the amplifier during the second cycle (π/ω ≤t <2π/ω).

2 .Fig. 3 .

 23 Fig.3.25 Chronogram of output voltage of half-bridge (VHB), voltage applied across CFix (VCFix) and the current flows through L (IP).

Figure 3 .Fig. 3 .Fig. 3 .

 333 Figure3.26 shows the series impedance of the ultrasonic transducer at its working frequency. RSLoad is the resistance and XSLoad is the reactance. Therefore, the equivalent circuit of the ultrasonic transducer at its working frequency can be described as Figure3.27.

Fig. 3 .

 3 Fig.3.28 Parallel equivalent circuit of the ultrasonic transducer at its working frequency.As the rated power of the transducer is 3W, so the required voltage supply of the transducer can be obtained as follows

  substituting V supply(peak) and Q Load into Equation 3.33, we can obtain the value of E.

Fig. 3 .

 3 Fig.3.29 Schematic of the proposed class D power amplifier with a static L-type tuning

Fig. 3 .

 3 Fig.3.30 Designed printed circuit board of the proposed class D power amplifier.

Figure 3 .

 3 Figure3.31 shows a prototype of the proposed power amplifier. The power amplifier is located in the area bounded by the dotted line. We tested and verified the

Fig. 3 .Fig. 3 .Fig. 3 .

 333 Fig.3.31 Prototype of the proposed class D power amplifier.

FigureFig.4. 1 Fig.4. 2

 12 Fig.4.1 Schematic of the impedance-measurement circuit.

Figure 4 .Fig. 4 . 3

 443 Figure 4.3 shows the simulation results of the tuned transducer obtained using the static-tuning network presented in Chapter 3. From this figure, we can clearly see that the static-tuning network cannot solve the problem of the impedance drift of the transducer that is caused by the increased temperature. The imaginary part of the impedance remains, and the output power does not reach its maximum value.

Fig.4. 4

 4 Fig.4.4 Imaginary impedances of different mono-elements in the phased-array used in this

Figure 4 .Fig. 4 . 5

 445 Figure 4.5 shows the histogram of these different imaginary impedances. The imaginary impedances of these mono-elements are mainly between -310 and -300 Ω.

Fig. 4 . 6

 46 Fig.4.6 Power efficiency curve of the power amplifier with a static tuning network

Fig. 4 . 7

 47 Fig.4.7 Simplified configuration of the auto-tuning network proposed in [SP2005].

Fig. 4 . 9

 49 Fig.4.9 Simplified schematic of the adjustable impedance tuning network presented in

Fig. 4 .

 4 Fig.4.10 Flow chart of the auto-tuning network presented in [RHN2013].The working frequency of this tuning network is limited by the using of relays in the switching inductor network. And a computer and MCU are needed in this tunning network. Therefore, it can not meet our requirement. F. J. Arnold, et al.[AFJ2015] develop a circuit for a laboratory bench. The operation of this circuit is based on detection of magnitude of current in the transducer.

Fig. 4 .Fig. 4 .

 44 Fig.4.11 Simplified circuit of the proposed synchronous switched capacitor.The proposed auto-tuning technique is a variable-capacitor-based approach. But instead of using a varactor, which is voltage-limited as mentioned previously, a capacitor with a fixed value Cs is used and it is added in parallel with the fixed capacitor used in the static resonant circuit, as shown in Fig.4.11. The connection of the added capacitor Cs to the circuit is synchronoursly controlled by a signal that has the same frequency as the input signal of the circuit. As it can be observed from Figure4.11, the equivalent capacitance C EQ of the switched capacitor C S can vary between two limits:

Fig. 4 .

 4 Fig.4.13 Waveform of the auto-tuning system with a non-linear transfer function.The equivalent capacitance C EQ of the synchronous-switched capacitor can be determined by:

Finally

  , substituting Equation 4.17 in Equation 4.16 yields the complete transfer function of the synchronous-switched capacitor.𝐶 𝐸𝑄 = 𝐶 𝑆 • 𝑠𝑖𝑛 [

Fig. 4 .

 4 Fig.4.14 Waveform of the auto-tuning system with a linear transfer function.As seen in this figure, the triangular signal V Trig is replaced by a sinusoidal waveform αV CFix , which has a constant amplitude and the same phase as V CFix .Therefore, the conversion function of the PWM converter becomes

Fig. 4 .

 4 Fig.4.15 Diagram of the realization of the proposed auto-tuning system based on synchronous

Figure 4 .

 4 Figure 4.15. It consists of a phase difference detector and an error amplifier. The proposed phase difference detector is realized by using an exclusive-OR gate (XOR).

Figure 4 .Fig. 4 .

 44 Figure 4.16. V CFix is the output voltage of the tuning network, and kV CFix is the attenuated V CFix . αV CFix defines the output signal of the automatic gain control block.

Fig. 4 .

 4 Fig.4.17 Equivalent PLL circuit of the auto-tuning system.

Fig. 4 .

 4 Fig.4.18 Relationship between the phase difference ∆θ and the phase error voltage VPD.

Figure 5 . 1

 51 Figure 5.1 shows the diagram of the proposed synchronous-switched capacitor system in order to perform the auto tuning of a 1.25 MHz power supply for the ultrasound transducer.

Fig.5. 1 A

 1 Fig.5.1 A half bridge class D amplifier tuned by a synchronous switched capacitor.

Fig.5. 2

 2 Fig.5.2 Simplified diagram of feedforward (left) and feedback (right) AGC circuit.

diagram of the proposed AGC is illustrated in Figure 5

 5 Fig.5.3 Diagram of the proposed automatic gain congrol amplifier.

Fig. 5 . 4

 54 Fig.5.4 Schematic of the output signal attenuator.

  5.3 into Equation 5.2, we obtain the values of R 2 and R 3 as follows:

Fig. 5 . 5

 55 Fig.5.5 Simulink model of AGC with linear gain function [PJPA2011].As known from[PJPA2011], the time response of the AGC with the linear gain-control function is described by:

Fig.5. 6

 6 Fig.5.6 Time response of linear AGC for diffrent stepwise functions.

  [PJPA2011] G(V CTR ), which is given in Equation 5.7 to obtain a constant settling time, as shown in Equation 5.8. The Simulink model of the AGC with exponential gain control function is shown in Figure 5.7. 𝐺(𝑉 𝐶𝑇𝑅 ) = 𝑁 2 𝑒 𝑁 1 𝑉 𝐶𝑇𝑅 5.7 𝜏 𝑒𝑥𝑝-𝑙𝑜𝑔 = 𝐶 𝐺 𝐹𝑖𝑙𝑡𝑒𝑟 𝑁 1 𝑁 2 5.8 where N 1 and N 2 are constants, and G Filter and C are fixed.

Fig. 5 . 7

 57 Fig.5.7 Simulink model of AGC with exponential gain function [PJPA2011].

Fig. 5 . 8

 58 Fig.5.8 Time response of exponential AGC with different stepwise functions.

Figure 5. 9 .

 9 Figure 5.9. The gain range of the AD603 is from -11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to +51 dB with a bandwidth of 9 MHz [AD603]. In our application, we chose the -11 dB to +31 dB gain range. The gain is controlled at a high impedance (50 MΩ) and low bias (200 nA) differential input; the scaling factor is 25 mV/dB, requiring a gain-control voltage of only 1 V to cover the 40 dB of the gain range that fulfills our requirements.

Fig.5. 9

 9 Fig.5.9 Schematic of the proposed variable gain amplifier.

Fig. 5 .Fig. 5 .Fig. 5 .

 555 Fig.5.10 Schematic of the proposed peak detector.The chronogram of this peak detector is illustrated in Figure5.11.

Fig. 5 .FigureFig. 5 .

 55 Fig.5.13 Equivalent circuit of the peak detector during period (T1 ≤ t ≤ T2).

Fig. 5 .

 5 Fig.5.15 Equivalent circuit of the peak detector during period (T3 ≤ t ≤ T4).

Fig. 5 .Fig. 5 .

 55 Fig.5.16 Schematic of the switch signal generator of the peak detector.

Fig. 5 .

 5 Fig.5.18 Schematic of the error amplifier in the proposed AGC.

Fig. 5 .

 5 Fig.5.19 Frequency response of the error amplifier in the proposed AGC. As can be seen from this figure, when f = 162 kHz, |G AGC (jw)| = 0 db, and the phase margin of the AGC is calculated by

Fig. 5 .

 5 Fig.5.20 Printed circuit board of designed AGC.

Fig. 5 .

 5 Fig.5.22 Frequency response of the error amplifier in the phase-error detector.

Fig. 5 .

 5 Fig.5.23 Schematic of the switch-signal generator of the proposed auto-tuning system.

than 2 .

 2 3 ns with a resolution of 4 mV by using 5V power supply [MAX961]. The propagation delay of MAX961 is only 8.5 ns in the worst case [MAX961]. The analysis of the phase error caused by the resolution V R of the comparator is shown in Appendix I. The designed PCB of the phase-error detector combined with the switch-signal generator is presented in Figure 5.24. The dimensions of this PCB are 7.2 cm × 5.7 cm.

Fig. 5 .

 5 Fig.5.24 Printed circuit board of designed phase-error detector combined with switch

Fig. 5 .

 5 Fig.5.25 Schematic of the proposed isolated AC switch. The PCB of the AC switch is shown in the area bounded by the blue dotted line in Figure 5.26. The proposed AC switch block contains two isolated switchs (SW A and SW B ). SW A is used to control the switched capacitor in the auto-tuning system, and SW B is used to control the error capacitor used in the testing-circuit proposed in Chapter 7.

Fig. 5 .

 5 Fig.5.26 Printed circuit board of the AC switch in the area bounded by blue dotted line.

Figure 5 .Fig. 5 .Fig. 5 .

 555 Figure 5.27 is a prototype of the AGC. We tested and verified the proposed AGC, and the test results are as follows.

Fig. 5 .

 5 Fig.5.29 Chronograms of the switch-signal generator circuit in the peak detector. Ch1 (orange): Input signal of the switch signal generator VPDIN: 5V/div. Ch3 (blue): Reset signal generated by the switch signal generator SReset: 5V/div. Ch4 (pink): Write signal generated by the switch signal generator SWrite: 5V/div.

Fig. 5 .

 5 Fig.5.30 Waveform of VC2 in the switch signal generator. Ch1 (orange): Input signal of the switch signal generator VPDIN: 500mV/div. Ch3 (blue): Voltage applied across capacitor (C2) VC2: 500mV/div.

Figure 5 .

 5 Figure 5.29 shows the test results of the switch signal generator circuit in the peak detection block with a 2 V peak-to-peak input signal. The orange line is the input signal. S Write is the pink line and S Reset is the blue line. The orange line in Figure 5.29 is the input signal of the peak detection block, and the blue line is the voltage applied across capacitor C 2 in Figure 5.10. Figure 5.30 shows the tested waveform of V C2 .

Fig. 5 .

 5 Fig.5.31 Output signal of the peak detector with a modulated input signal. Ch1 (orange): Input signal of the switch signal generator VPDIN: 500mV/div. Ch3 (blue): Output voltage of the proposed peak detector VPDOUT: 500mV/div.

Fig. 5 .

 5 Fig.5.32 Zoomed view of the output signal of the peak detector at the rising edge.

Fig. 5 .

 5 Fig.5.33 Zoomed view of the output signal of the peak detector at the falling edge.

Fig. 5 .

 5 Fig.5.34 Test result of the error amplifier with a modulated input signal. Ch1 (orange): Input signal of the proposed AGC VAGCIN: 500mV/div.

Figures 5 .

 5 Figures 5.35, 5.36, and 5.37 show the test results of the AGC circuit. The blue line is the output signal of the AGC, and the pink line is the output waveform of the peak detector. The input signal of the AGC is shown as the orange line.

Fig. 5 .

 5 Fig.5.35 Test results of the AGC circuit with a modulated input signal. Ch1 (orange): Input signal of the proposed AGC VAGCIN: 500mV/div. Ch3 (blue): Output voltage of the proposed AGC VAGCOUT: 1V/div. Ch4 (pink): Output voltage of the proposed peak detector VPDOUT: 1V/div.

Fig. 5 .Fig. 5 .

 55 Fig.5.36 Zoomed view of test results of the AGC at the falling edge.

  Figure 5.40 illustrates the test results of the phase-error detector, and Figure 5.41 shows the results of the switch-signal generator.

Fig. 5 .

 5 Fig.5.40 Test results of the phase-error detector. Ch1 (orange): Output voltage of the proposed AGC VAGCOUT: 1V/div. Ch2 (green): Output voltage of the proposed phase shifter QPS: 5V/div. Ch3 (blue): Output voltage of the error amplifier VEA+: 1V/div. Ch4 (pink): Output voltage of the XOR gate VXOR: 5V/div.

Fig. 5 .

 5 Fig.5.41 Test result of the switch-signal generator. Ch3 (blue): Control signal of the switched capacitor SW: 5V/div. Ch4 (pink): Output voltage of the power amplifier VCFix: 100V/div.

Fig. 5 .

 5 Fig.5.42 Prototype of the AC switch in the area bounded by the blue line.

Fig. 5 .

 5 Fig.5.43 Test result of the isolated switch driver of the AC switch. Ch2 (green): Control signal of the switched capacitor SW: 5V/div. Ch3 (blue): Output voltage of the proposed isolated AC switch driver: 5V/div.

Fig. 5 .

 5 Fig.5.44 Equivalent circuit of the auto-tuning system with a variable-impedance

  discussed in section 3.5, C PLoad = 407.3 pF, and we obtain the variable capacitance of the transducer as ∆C = 40% × C PLoad ≈ 163 pF. Therefore, the variable capacitance of ∆C SVar must obey the following equation. of the AC switch C ACSW = 2C OSS = 320 pF. By substituting C ACSW into Equation 5.28, we obtain the value of C S as proposed auto-tuning network is based on LC tuning circuit, we obtain the following equations.

  our application, f Working = 1.25 MHz and C PLoad = 407.3 pF; therefore, we obtain the values of C Fix using

Fig. 5 .

 5 Fig.5.45 Equivalent PLL circuit of the auto-tuning system.

Figure 6

 6 Figure 6.3. This VGA consists of three parts: an attenuation circuit, a Gilbert cell, and a DC-offset cancellation circuit.

Fig.6. 4 (

 4 Fig.6.4 Schematic of the attenuation block. Two NMOS source followers, which are composed of M11, M12, M15 and M16 are applied after the attenuators to ensure that the DC levels of V out+ and V out-are equal to 2.5 V. The current of transistor M11 can be defined by 𝐼 𝑀11 = 1 2 𝐾 𝑁 ( 𝑊 𝐿 ) 𝑀11 (𝑉 𝑜+ -𝑉 𝑜𝑢𝑡+ -𝑉 𝑇𝑁 ) 2

Fig. 6 . 5

 65 Fig.6.5 Schematic of the proposed Gilbert cell.

  next stage. Therefore, we require a common-mode feedback (CMFB) circuit. The schematic of the CMFB circuit for the proposed VGA is illustrated in the area bounded by the red dotted line in Figure6.5. In the CMFB circuit, the four transistors M21~M24 have the same width-to-length ratio. For the differential-mode input signals, the currents that flow through M21 (I M21 ) and M24 (I M24 ) have the same value, but opposite directions. Therefore, the currents of M22 (I M22 ) and M23 (I M23 ) are constant, and the output voltage of the CMFB circuit V CMFB is also constant. For the common-mode input signal, when the common-mode output level (V CMFB ) of the VGA increases, I M21 and I M24 also increase, which will lead to an increasing of the currents flowing through M25 (I M25 ) and M26 (I M26 ). However, I M22 and I M23 will decrease, which will result in an increase in the output of the CMFB circuit. Then, V CMFB will decrease and vice versa. It can be seen that this common-mode signal of the VGA can be balanced with almost no effect on the differential-mode signal.

Figure 6 .

 6 Figure6.6 shows the DC-offset cancellation circuit used to minimize the DC offset that was caused by the mismatch of the input transistors or that was introduced by the

Fig. 6 . 8

 68 Fig.6.8 Schematic of proposed FGA.The variable gain of the proposed VGA was set from -45.82 dB to -7.03 dB. The designed FGA has a 25 dB output gain. The gain-adjustment range of the proposed VGA combined with the FGA is from -20.82-17.97 dB. After the FGA stage, we used an AC coupling circuit to cancel the DC offset of the FGA. The layout of the proposed fixed gain amplifier is also illustrated in Appendix III.

Fig. 6 . 9

 69 Fig.6.9 Schematic of the exponential V/I converter.

Figure 6 .Fig. 6 .

 66 Figure 6.10 shows the schematic of the peak detector used in this paper, and which was proposed in [DGG2002P. 1, DGG2002P. 2]. It is a negative peak detector. The core of this peak detector is a current-mirror-based peak detector. However, the structure can

Fig. 6 .

 6 Fig.6.13 Schematic of the switch control signals generator designed for the peak detector.

Fig. 6 .

 6 Fig.6.14 Chronograms of the two phase peak detector used in the proposed AGC.

Figure 6 .Fig. 6 .

 66 Figure 6.15 shows the schematic of the comparator used in the switch-control

Fig. 6 .

 6 Fig.6.16 Schematic of the OTA used in the designed peak detector.

Fig. 6 .

 6 Fig.6.19 Simplified schematic of the error amplifier used in the AGC.

Fig. 6 .

 6 Fig.6.20 Diagram of the phase error detect circuit.

  Figure 6.23 illustrates the general principle of the bandgap reference circuit. The reference voltage of the bandgap circuit is described by 𝑉 𝑅𝑒𝑓 = 𝑉 𝐵𝐸 + 𝐾𝑉 𝑡 6.39

Fig. 6 .Fig. 6 .

 66 Fig.6.23 General principle of the bandgap reference circuit [RB2002].The CMOS technology that was used in our project has only a substrate PNP bipolar-junction transistor (BJT). The schematic of the CMOS bandgap reference that used this kind of bipolar transistor is shown in Figure6.24.

Fig. 6 .

 6 Fig.6.25 Direct transfer characteristics of the designed VGA without attenuators.

Figure 6 .Fig. 6 .

 66 Figure 6.26 shows the DC characteristics of the VGA with the attenuation block, and we can see that the linear input range of the VGA is further extended by the attenuation block, which ranges from -1.5 V to 1.5 V.

Fig. 6 .

 6 Fig.6.27 Frequency response of the designed VGA with the DCOC circuit.

Figure 6 .Fig. 6 .

 66 Figure 6.28 shows the frequency characteristics of the proposed FGA. The bandwidth of this FGA is 2.79 GHz with a 78° phase margin. It can offer a 25 dB fixed gain.

Figure 6 .Fig. 6 .Fig. 6 .

 666 Figure 6.29 shows the frequency response of the VGA combined with this FGA. The gain adjustment range of the proposed VGA with the FGA is from -20.82 dB to 17.97 dB with a -3 dB bandwidth of 36 kHz ~ 51 MHz.

Fig. 6 .Fig. 6 .

 66 Fig.6.31 Simulated slew rate of the designed OPA.

Figure 6 .Fig. 6 .Fig. 6 .Fig. 6 .Fig. 6 .

 66666 Figure6.32 is the frequency response of the proposed VGA combined with the FGA and output buffer. There is an AC coupling circuit between the FGA and the output buffer, and the DC offset introduced by the mismatch in the FGA and the input signal is cancelled. However, the bandwidth is limited by this AC coupling circuit. The total gain output gain of the AGC now ranges from -8.82 dB ~ 29.97 dB. In addition, the -3 dB bandwidth of the AGC is from 36 kHz to 8.75 MHz.The relationship between the gain-control signal V ctr and the output signals V ex1 and V ex2 is demonstrated in Figure6.33. As observed from this figure, V ctr has a linear relationship with ln(V ex1 -V ex2 ) in the range from 0.3 V to 3.7 V.

  Figure 6.38(a) shows the simulation result of the peak detector with a 125 kHz, 50 mV sinusoidal input signal, while Figure 6.38(b) shows the simulation result with a 125 kHz, 2 V sinusoidal input signal. The simulation result with a 3 MHz, 50 mV sinusoidal input signal is presented in Figure 6.38(c), and the result with a 3 MHz, 2 V sinusoidal input signal is shown in Figure 6.38(d). switch-control signals for the different input signals are shown in Figure 6.39. Figures 6.39(a)-(d) shows the simulation result of the generated switch control signals with the sinusoidal input signals 125 kHz/50 mV, 125 kHz/2V, 3 MHz/50 mV, and 3MHz/2V, respectively. The switch control signals are generated using the voltage at the point V K . The frequency response of the error amplifier designed for the AGC circuit is illustrated in Figure 6.40. For the 3 MHz input signal, the capacitances of C1 and C2 used in the error amplifier are chosen as 100 pF. The cutoff frequency of the error amplifier is 159.24 kHz. For the 125 kHz input signal, the capacitances are set to be equal to 1.6 nF. The cutoff frequency is now changed to 9.95 kHz.

Fig. 6 .Fig. 6 .Figure 6 Fig. 6 .

 6666 Fig.6.40 Frequency responses of the error amplifier designed for the AGC. The simulation results of the proposed AGC with different sinusoidal input signals are shown in Figure 6.41. For the four sinusoidal input signals above, the simulation results are shown in Figure 6.41(a)~(d), respectively.

Fig. 6 .Fig. 6 .

 66 Fig.6.45 Frequency responses of the proposed phase error detector circuit

Figure 6 .Fig. 6 .Figure 6 .

 666 Figure 6.47 shows the simulation results of the bandgap reference circuit with different supply voltages, which range from 3-5 V. As can be seen from this figure, the

Fig. 6 .Fig. 6 .

 66 Fig.6.48 Post-layout simulated DC transfer characteristics of the proposed VGA.

Fig. 6 .Fig. 6 .

 66 Fig.6.50 Post-layout simulated slew rate of the OPA.

Figure 6 .Fig. 6 .Fig. 6 .

 666 Figure6.51 shows the post-layout frequency response of the proposed VGA combined with the FGA and output buffer. The total output gain of the AGC ranges from -9.04 dB to 29.47 dB, and the -3 dB bandwidth of the AGC ranges from 37.5 kHz to 8.36 MHz.The post-layout simulation results of the gain-tuning curve are demonstrated in Figure6.52. The same as the pre-layout simulation result presented in section 6.6.1, The proposed AGC has a approximately linearly gain tuning range of 39 dB with a gain control voltage ranging from 0.35 V to 3.5 V

Fig. 6 .Fig. 6 .

 66 Fig.6.56 Post-layout simulated output error of the peak detector.

Fig. 6 .

 6 Fig.6.58 The DC offset voltage Monte Carlo histogram of the proposedAGC.

Figure 6 .Fig. 6 .

 66 Figure 6.59. The Simulation results is nearly the same as the pre-layout simulation results. The phase difference between the input signals V inA and V inB is detected and transferred into a relevant voltage. As shown in this figure, when the phase difference is π/2, the output phase error voltage V Err is 2.5 V.

Fig. 6 .

 6 Fig.6.60 Post-layout simulation results of the comparator used in the Switch signal

Fig. 6 .

 6 Fig.6.61 Post-layout simulation results of the bandgap reference circuit.We set the supply voltage to 5 V with a temperature variation ranging from -20°C to 100°C . The designed temperature coefficients of the output reference voltage and current are 15.3 ppm/°C and 15.16 ppm/°C, respectively. The output reference voltage is 1.222 V at a temperature of 27°C, and the output current is 50.07 μA at the same temperature.

Fig.7. 1

 1 Fig.7.1 Equivalent test circuit of the ultrasonic generator with the proposed printed circuit

  2. The orange line is the output signal of the power amplifier. The green line is PWM E . The output signal is the pink line in this figure, and the phase-error voltage is shown as the blue line.

Fig.7. 2

 2 Fig.7.2 Test results of ultrasonic generator with the proposed printed circuit board

Fig.7. 3

 3 Fig.7.3 Zoomed views of the simulation results of ultrasonic generator with the proposed

Fig. 7 . 4

 74 Fig.7.4 Equivalent simulation circuit of the ultrasonic generator with the proposed

Figure 7 .

 7 Figure 7.5 (left) shows the output of the voltage divider in the ideal case (The phase difference between V OUT and V CFix is π/2).Figure 7.5 (right) shows the simulation

  Figure 7.5 (right) shows the simulation results in an actual situation. PWM E is the red line, the orange line is the phase-error voltage, and the purple line is the output of the voltage divider in the actual case.

Fig. 7 . 5

 75 Fig.7.5 Input and output of the tuning circuit in the ideal case (left) and the simulation

Fig. 7 . 6

 76 Fig.7.6 Details of the simulation results for the ultrasonic generator with the proposed

Figure 7 .Fig. 7 . 9 Fig. 7 .

 7797 Figure 7.10. The average power consumption of the auto-tuning system in the worst case is only 137 mW, which is much smaller than the saved power and the power consumption of the PCB version (874 mW).

Fig. 3

 3 Fig.3 Layout of the proposed VGA combined with FGA and exponential voltage to current converter.The layout of the proposed VGA is within the area bounded by the red dotted line, while the FGA is bounded by the blue dotted line. The area bounded by the purple dotted line is the AC coupling circuit, and the proposed exponential voltage-to-current converter is illustrated in the area bounded by the green dotted line.

Fig. 4

 4 Fig.4 Layout of the proposed peak detector used in the proposed AGC.

Figure 4

 4 Figure 4 is the layout of the designed peak detector. The area bounded by the blue dotted line shows the proposed OTA combined with the current mirror and the capacitors C h used in the peak detector. The switch-control signal generator of the peak detector is illustrated by the red dotted line. The output buffer of the proposed peak detector is shown by the area bounded by the green dotted line.

Fig. 5

 5 Fig.5 Layout of the output buffer used in the proposed AGC.

Figure 6

 6 Figure 6 illustrates the layout of the error amplifier. The OPA is surrounded by the red dotted line. The resistors used in this error amplifier are illustrated in the area bounded by the blue dotted line. The capacitors of the error amplifier are realized using an external capacitor.

Fig. 6

 6 Fig.6 Layout of the error amplifier used in the proposed AGC.

Fig. 7

 7 Fig.7 Layout of the phase detector.

Fig. 8

 8 Fig.8 Layout of the error detector designed for the phase-error detector.Switch Signal GeneratorThe layout view of the switch-signal generator of the auto-tuning system is shown in Figure9. This circuit is composed of two comparators, a unity-gain inverting amplifier, and a NOR gate. The unity-gain inverting amplifier is demonstrated in the blue rectangle, and the comparators combined with the NOR gate are shown in the red rectangle.

Fig. 9

 9 Fig.9 Layout of the error detector designed for the phase-error detector.

Fig. 10

 10 Fig.10 Layout of the proposed bandgap reference circuit.

Table 2 .1 Transformation formulas for the electrical and mechanical models. [GM1997]Table 2 .2 Characteristics of the different static tuning networks. [VBA2011

 22 ] ....................

Table 2 .3 Comparison of the basic tuning networks

 2 . .............................................................

Table 3 .1 Comparisions of existing power amplifiers for ultrasound applications

 3

.............

Table 3 .2 Parameters of the ultrasonic transducer used in this thesis

 3

. .................................

Table 3.3 Performance of the proposed power amplifier. ...................................................... Table 4.1 Summary of existing auto-tuning networks suitable for ultrasonic transducer.. Table 5.1 Summary of main AGC loop control characteristics. ...........................................

and breast [HK2007-QB2010]. These treatment attempts have met with various degrees of success, and the FDA has approved HIFU for the treatment of prostate cancer [HGR2009].

	promise with respect to HIFU technology. It was used to treat patients having
	Parkinson's disease in combination with craniotomy and local anesthesia [MR1959,
	BJW1956]. However, the long treatment times and the absence of a high-precision
	imaging technique HIFU was instead used based on neurological medicinal treatments
	during the 1970s [ZYF2011]. In this period, HIFU technology has started to ebb.
	During the 1980s and 1990s, with the development of medical imaging
	technology, HIFU underwent a period of rapid development. The high-resolution
	medical imaging and monitoring technique, which improved the identification and
	visualization of internal tissue, gave the HIFU larger development space. The technique
	used for the production of ultrasound transducers also simultaneously underwent
	significant improvements. This improvement enabled the development of more
	powerful and smaller HIFU systems. Then, in the late 1990's the phased-array technique
	was first applied for use in HIFU technology [EES1991, USI1989]. Using a suitable
	control system, this phased-array HIFU (pHIFU) can generate more than one focal point,
	and the location of the focus can be easily controlled [EES1989-CE2009]. During this
	period, HIFU was used in many human trials for the treatment of diseases and disorders
	including uterine fibroids, essential tremors, and cancers of the bladder, kidney, liver,
	brain, pancreas,
	The use of high-intensity focused ultrasound (HIFU) technology as a therapeutic
	modality can be traced back to the 1920s. Robert Woods and Alfred Lee Loomis found
	that high-power ultrasound beams have the capability of killing cells and tiny fish
	[WRW1927]. In 1942, John Lynn discovered that focused ultrasound can result in
	localized tissue damage [LJG1942]. In the late 1950s, the Francis Fry group
	commenced research into the use of HIFUs on animals and humans [FWJ1953,
	FWJ1955]. During the 1950s and 1960s, the number of experiments showed significant

2.2.1 Structure of Ultrasonic Transducer

	transducer. This element is enclosed within a casing. For transducers used in medical
	applications, the piezoelectric active element is usually made of lead zirconate titanate.
	Two electrodes are applied to the top and bottom surfaces of the element. Coaxial cable
	is connected to the electrodes of the piezoelectric element to transmit signals from the
	power amplifier to the piezoelectric element. The piezoelectric element and the internal
	connections are protected by the outer case, which can also provide air backing for the
	piezoelectric element. As opposed to other ultrasonic transducers, the transducers used
	in the HIFU application have no matching layers in front of the piezoelectric elements.
	Figure 2.1 shows a simple structure of the ultrasonic transducer [QZ2014], which
	has the similar structure as the transducer used in our project. The transducer consists of
	four parts: piezoelectric active element, transducer casing, backing layer, and coaxial

Signal Cable Casing Electrodes Piezoelectrical Element Backing Layer Connections Fig.2.1 Structure of the ultrasonic transducer used in HIFU applications.

m m VP RP CP im i k b xP FPi FLoad -FPi Electrical model Mechanical model Fig.2.2 Model of the ultrasonic transducer. [GM1997]

	is depicted in Figure 2.2.
	As can be seen from this model, the capacitance caused by the piezoelectric
	material is represented as C p . In addition, the dielectric losses formed by the oxides are
	given as R p . Usually, R p can be neglected because of its very high value. The equivalent
	electrical model of the current flows through C p can be described as
		𝐶 𝑃	𝑑𝑉 𝑃 𝑑𝑡	= 𝑖 -	𝑉 𝑃 𝑅 𝑃	-𝑖 𝑚	2.1
	i is the current generated by the external applied voltage V P . And i m is the current
	flowing through the mass m. The mechanical model of the piezoelectric element is
	described by,
		𝐹 𝑃𝑖 = 𝑉 𝑃 • 𝑄 𝐹𝑜𝑟𝑐𝑒	2.2
		𝑖 𝑚 =	𝑑𝑥 𝑃 𝑑𝑡	• 𝑄 𝐹𝑜𝑟𝑐𝑒	2.3
	𝑚	𝑑 2 𝑥 𝑃 𝑑𝑡 2 + 𝑏	𝑑𝑥 𝑃 𝑑𝑡	+ 𝑘𝑥 𝑃 + 𝐹 𝑃𝑖 = 𝐹 𝐿𝑜𝑎𝑑	2.4
	where F Pi is the force of the piezoelectric active element excited by the voltage V P ,
	and the external load is defined as F Load . Q Force is a coefficient to link the applied
	voltage to the equivalent mechanical force. We can also call it a force factor between the
	The well-known equivalent model of a electrical model and the mechanical model. The Simulink model of the piezoelectric
	piezoelectric transducer, which is based on its electrical and mechanical characteristics, active element, which is shown in Figure 2.3, can be obtained from Equations 2.1~2.4.

Table 2 .1 Transformation formulas for the electrical and mechanical models. [GM1997] Mechanical Parameters Electrical Parameters Relation

 2

	Mass m	Inductance L	m	𝐿 𝑚 = 𝑚 𝑄 𝐹𝑜𝑟𝑐𝑒 2 ⁄
	Damping b	Resistance R m	𝑅 𝑚 = 𝑏 𝑄 𝐹𝑜𝑟𝑐𝑒 2 ⁄
	Stiffness k	Capacitance C	m	𝐶 𝑚 = 𝑄 𝐹𝑜𝑟𝑐𝑒 2	𝑘 ⁄
	Force F Pi	Voltage V P		𝐹 𝑃𝑖 = 𝑄 𝐹𝑜𝑟𝑐𝑒 • 𝑉 𝑃
	Displacement x P	Charge q	m		𝑑𝑞 𝑚 𝑑𝑡	= 𝑖 𝑚 = 𝑄 𝐹𝑜𝑟𝑐𝑒 •	𝑑𝑥 𝑃 𝑑𝑡
	Assuming no external load, the model of the piezoelectric element can be replaced
	by an equivalent circuit, as shown in Figure 2.4.
	As can be seen from this figure, the piezoelectric element can be described by two
	parallel branches of R P and C	P , and several series resonant branches of L	mn , C	Mn , and
	R mn , which represent the mass parts (m) of the model. R p can be neglected because of its
	very high resistance.

VP RP CP im i iCp iRp Rm1 Cm1 Lm1 … Rm Cm Lm Rmn Cmn Lmn Fig.2.4 Equivalent circuit of the piezoelectric element near its resonance frequency. [VAA2008]

	𝑌 𝐸𝑞 (𝑗𝑤) = 𝑗𝑤𝐶 𝑃 +	1 𝑍 𝑚 (𝑗𝑤) = 𝑗𝑤𝐶 𝑃 +	𝑗𝑤𝐿 𝑚 +	1 𝑗𝑤𝐶 𝑚 1	+𝑅 𝑚
	Therefore, the equivalent circuit is described by the following equations:
	𝑉 𝑃 = 𝐿 𝑚	𝑑 2 𝑞 𝑚 𝑑𝑡 2 + 𝑅 𝑚	𝑑𝑞 𝑚 𝑑𝑡	+	𝑞 𝑚 𝐶 𝑚	2.5
	𝑖 = 𝐶 𝑃	𝑑𝑉 𝑃 𝑑𝑡	+	𝑑𝑞 𝑚 𝑑𝑡	+	𝑉 𝑃 𝑅 𝑃	2.6
	Then, the impedance of the series resonant branches can be obtained by
	𝑍 𝑚 (𝑗𝑤) = 𝑗𝑤𝐿 𝑚 +	1 𝑗𝑤𝐶 𝑚	+ 𝑅 𝑚	2.7
	If the frequency of the driving signal V P equals the mechanical resonance
	frequency of the piezoelectric element, the series resonant branches behave as a purely
	resistive load R m . The mechanical resonance frequency f m is calculated by
			𝑓 𝑚 =	1 2𝜋√𝐿 𝑚 𝐶 𝑚	2.8
	Thus, the impedance of the equivalent circuit at its mechanical resonance
	frequency (Z m //C P //R P ) is described by
	𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 =	𝑅 𝑚 1+𝑗𝑤 𝑚 𝐶 𝑃 •𝑅 𝑚	2.9
	Solving for R m and C P ,
	𝑅 𝑚 =	2 |𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 | 𝑟𝑒𝑎𝑙(𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 )	2.10
	𝐶 𝑃 =	-𝑖𝑚𝑎𝑔(𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 ) 2𝜋𝑓 𝑚 |𝑍 𝐸𝑞 (𝑗𝑤)| 𝑤=𝑤 𝑚 | 2	2.11
	and the admittance of the equivalent circuit is defined by

Table 2 .2 Characteristics of the different static tuning networks. [VBA2011]

 2

	Power Supply	Transducer	Tuning network
	Low Impedance	High Impedance	L Tuning Network
	High Impedance	Low Impedance	Γ Tuning Network
	Low Impedance	Low Impedance	T Tuning Network
	High Impedance	High Impedance	П Tuning Network

Table 2 .3 Comparison of the basic tuning networks. Topologies Impedance Transformation (Power-Load) Comments Static Tuning Network [VBA2011]

 2

	L Tuning Network	Low-High Impedance	Simple structure
	Γ Tuning Network	High-Low Impedance	Simple realization
	T Tuning Network	Low-Low Impedance	Cannot eliminate
	П Tuning Network	High-High Impedance	the impedance drifting
		Working	MRI
	Topologies			Comments
		Frequency	Compatibility
				Non-real time
	Bridge Method	0~300MHz	No
				Unfit for grounded devices
	Dynamic			Real time
	I-V Method	10k~100MHz	No
	Tuning			Needs transformer
	Network			Real time
	Auto-balancing	20~110MHz	Yes
	[NI2007]			Complex structure
	Resonance			Real time
		10k~70MHz	Yes
	Method			Simple structure

Table 3 .1 Comparisions of existing power amplifiers for ultrasound applications

 3

		Output	Working	Power	Output
	Ref	Class				Comments
		Waveform	Frequency	Efficiency	Power
						Low efficiency,
	[TYC2008]	Class AB Sinusoidal	20kHz	32%	330W
						needs cooling facility
						Low efficiency,
	[SK2015]	Class AB Sinusoidal	3MHz	44%	30W
						needs cooling facility
						Acceptable efficiency,
	[GSH2013]	Class B Sinusoidal	1~6MHz	57%	<1W
						low output power
						Needs tuning network,
	[BD2014]	Class B Sinusoidal	3MHz	>60%	20W	acceptable efficiency,
						needs cooling facility
						Needs tuning network,
	[HT2006]	Class D Sinusoidal	1MHz	>90%	20W
						needs MOSFETs with same Rdson
						Needs tuning network,
	[CHL2009]	Class E Sinusoidal	40kHz	93%	42W
						needs high inductance choke
		Square				Square output waves
	[LJGK2008]	ClassD	1.5MHz	90%	48W
		wave				needs MOSFETs with same Rdson
						Needs four transistors,
	[YL2007]	ClassD Sinusoidal	20~60kHz	91%	44W
						needs tuning network
						Needs tuning network
	[AWT2010]	ClassD Sinusoidal	1.5MHz	>70%	<1W	needs MOSFETs with same
						Rdson,

Table 3 .2 Parameters of the ultrasonic transducer used in this thesis.

 3

	Working Frequency	Rated Power	RSLoad	XSLoad
	1.25MHz	3W	36.65 Ω	-308.2 Ω

  Based on the analysis in section 2.3, we know that the reactance of the inductor L and the susceptance of the capacitor C Fix in the static L-type tuning network can be calculated by the following equations. Piez =X SLoad and R Piez =R SLoad , and Z O is the output impedance of the power amplifier which equals the value of R dson of the power transistor. In this thesis, we choose NMOS transistors with R dson less than 0.04 Ω to reduce the energy losses of the power amplifier. By solving Equations 3.42 and 3.43, Then, we can obtain the values of the inductor and capacitor of the tuning network.

	𝐵 𝐶𝐹𝑖𝑥 =	𝑅 𝑃𝑖𝑒𝑧 2 𝑋 𝑃𝑖𝑒𝑧 +√𝑅 𝑃𝑖𝑒𝑧 𝑍 𝑂 ⁄ √𝑅 𝑃𝑖𝑒𝑧 +𝑋 𝑃𝑖𝑒𝑧 2 2 +𝑋 𝑃𝑖𝑒𝑧 2	-𝑍 𝑂 𝑅 𝑃𝑖𝑒𝑧	3.42
	𝑋 𝐿 =	1 𝐵 𝐶𝐹𝑖𝑥	+	𝑋 𝑃𝑖𝑒𝑧 𝑍 𝑂 𝑅 𝑃𝑖𝑒𝑧	-	𝑍 𝑂 𝐵 𝐶𝐹𝑖𝑥 𝑅 𝑃𝑖𝑒𝑧	3.43
	where X 𝐵 𝐶𝐹𝑖𝑥 ≃ 0.091	3.44
				𝑋 𝐿 ≃ 10.61	3.45
			𝐶 𝐹𝑖𝑥 =	𝐵 𝐹𝑖𝑥 2𝜋𝑓	≃ 11.6𝑛𝐹	3.46
			𝐿 =	𝑋 𝐿 2𝜋𝑓	≃ 1.35𝜇𝐻
				1 𝟐𝜋𝑓 𝑠 𝑋 𝑃	≃ 407.3𝑝𝐹	3.41

  The gate-source threshold voltage V GS(th) and input capacitor C iss of the MOSFET are 2.8 V and 405 pF, respectively, according to the datasheet. Because of the input capacitor C iss , we require a MOSFET driver circuit that is capable of providing sufficient current to the transistors. In this thesis, we use the half-bridge MOSFET driver SI9912 to drive the transistors. The switching frequency of this driver can reach 1.25 MHz, and the drive current I Drive can reach 1 A[Si9912]. Therefore, the switching time of the transistors t Switch , which is realized by using this driver, can be calculated Switch is much less than half of the period of the input signal (0.5 μs). In addition, SI9912 can offer a 25 ns dead time between the gate-control signals OUT H and OUT L

	using
	𝑡 𝑆𝑤𝑖𝑡𝑐ℎ = 𝐶 𝑖𝑠𝑠	𝑉 𝐺𝑆(𝑡ℎ) 𝐼 𝐷𝑟𝑖𝑣𝑒	= 1.134𝑛𝑠	3.51
	where t

Table 3 .3 Performance of the proposed power amplifier.

 3

Table 4 .1 Summary of existing auto-tuning networks suitable for ultrasonic transducer.

 4

		Working	Improvement of the	Tuning
	Ref				Comments
		Frequency	Power Efficiency	Range
	[XH2001]	17.7~20MHz	-	34%	Low accuracy
	[SP2005]	69.5~-87kHz	-	20%	Low working frequency
					Needs Computer and external
	[DOPL2009]	1.5MHz	-	28.9%
					impedance measuring circuit
					Complex structure Hard to
	[EDMG2010]	1GHz	25%	-
					implement and manufacture.
					Maximum output voltage is limited
	[CK2012]	1~1.9GHz	15%	-	by using of varactor diodes.
					Needs DSP module
					Needs computer and external
	[RHN2013]	15~20kHz	-	-
					impedance measuring circuit
					Needs bulky magnetic components
	[AFJ2015]	28~30kHz	-	-	in the impedance detecting circuit.

  .2. As presented in the figure, the input signal V IN is amplified by a variable-gain amplifier (VGA), which can offer a variable gain.The gain of the VGA is controlled by a gain-control voltage V CTR , which is generated by the feedforward or feedback loop. First, the feedforward or feedback loop detects the amplitude level of the input or output signal V in /V out by using a peak detector. Then, it compares the amplitude voltage with a reference voltage V REF , after which we used a loop filter or error amplifier to filter and generate the required gain-control voltage.

Table 5 .1 Summary of main AGC loop control characteristics.

 5

Table 6 .2 Design specifications of the automatic gain control amplifier.

 6

	Parameter	Value
	Process	AMS HitKit C35B4C3 COMS process
	Power Supply	5 V
	Input Range	50mV~1.5V (30 Times ratio)
	Gain Range	0~30 dB
	-3dB Bandwidth	5 MHz

  𝑘 1 𝑉 𝑐𝑡𝑟 + 𝑘 2 𝑉 𝑐𝑡𝑟

		2	6.15
	Therefore, when M3 operates in the linear region, the voltage V SD3 can be depicted
	by
	𝑉 𝑆𝐷3 =	𝐼 𝐵𝑖𝑎𝑠 2𝐾 𝑝 (𝑘 1 𝑉 𝑐𝑡𝑟 +𝑘 2 𝑉 𝑐𝑡𝑟 2 -|𝑉 𝑇𝑝 |)	+ 𝛼𝑉 𝑐𝑡𝑟	6.16
	where K P is the transconductance parameter of M3, and α, k 1 , and k 2 are
	proportionality factors. The currents I1 and I2 flowing through M2 and M3 can be
	derived by
	𝐼 1 = 𝐼 𝑏 2 ⁄ -𝛼𝐾 𝑝 |𝑉 𝑇𝑝 |𝑉 𝑐𝑡𝑟 + 𝛼𝑘 1 𝐾 𝑝 𝑉 𝑐𝑡𝑟 2 + 𝛼𝑘 2 𝐾 𝑝 𝑉 𝑐𝑡𝑟 3 -𝑉 𝑠𝑑2 2	2 ⁄ 6.17
	𝐼 2 = 𝐼 𝑏 2 ⁄ + 𝛼𝐾 𝑝 |𝑉 𝑇𝑝 |𝑉 𝑐𝑡𝑟 -𝛼𝑘 1 𝐾 𝑝 𝑉 𝑐𝑡𝑟 2 -𝛼𝑘 2 𝐾 𝑝 𝑉 𝑐𝑡𝑟 3 + 𝑉 𝑠𝑑2 2	2 ⁄ 6.18

  R 2 , and N. Then, we used an OPA to generate I Ref from V Ref . The equation of I Ref is

					.40
	𝐼 2 =	𝑉 𝑡 𝑅 1	𝑙𝑛(𝑁)	6.41
	Therefore, the output reference voltage (V Ref ) of this bandgap circuit can be written
	as
	𝑉 𝑅𝑒𝑓 = 𝑉 𝐵𝐸3 + 𝐼 2 𝑅 2 = 𝑉 𝐵𝐸3 +	𝑅 2 𝑅 1	𝑉 𝑡 𝑙𝑛(𝑁)	6.42
	The desired value of K in Equation 6.39 can be achieved by carefully designing R 1 ,
	𝐼 𝑅𝑒𝑓 =	𝑉 𝑅𝑒𝑓 𝑅 3

From Figure 5.36, we see that the settling time of the designed AGC at the falling edge of the modulated input signal equals seven periods of the input signal. From Figure 5.37 we can see that the settling time of the designed AGC at the rising edge of the modulated input signal is about five periods of the input signal. A recall of the simplified schematic of the proposed phase error detection block is Chapter 6 IC Design of the Proposed Auto-tuning

Phase Error Detection Block Combined with Switch Signal Generation Block

Introduction

For general HIFU applications, there are often more than 100 ultrasonic generators in a phased array. In our application, the ultrasonic phased array consists of 256 transducers. In other words, 256 auto-tuning feedback loops are required for our HIFU system. Therefore, the surface of the AGC should be designed to be as small as possible.

The surface area of the PCB version of the auto-tuning system that was presented in Chapter 4 is about 110 cm 2 , which is much less than that of existing auto-tuning systems.

However, in our application, the need for 256 auto-tuning feedback loops implies that 256 PCBs are needed, which is still too many for our project. Further, the use of discrete components also results in wasted power. In this case, there is a real need for the design of an auto-tuning system in integrated circuits (ICs). Except the smaller circuit dimension, the using of the integrated circuit can also reduce the power consumption of the proposed auto-tuning system and enhance the performance of the circuit.

In this chapter, we present the design of an integrated automatic impedance-tuning circuit to minimize the surface area of the auto-tuning system and to reduce the power consumption. This chapter is organized as follows: In Section 6.2, we present the design of the integrated AGC circuit. In Section 6.3, we show the design of the phase-error amplifier. In Section 6.4, we illustrate the PWM circuit that was used to generate the AC switch-control signal. The design of the bandgap reference circuit is discussed in

Development Environment

The software tools that were used to design and simulate the integrated circuit are Cadence Virtuoso ® AMS Designer Environment, Spectre ® Circuit Simulator and Assura ® Physical Verification.

Design of the Integrated AGC

In this section, we present an integrated AGC circuit that was used for the auto-tuning system. As mentioned in the previous chapter, we have chosen a decibel linear AGC, it can therefore offer a constant settling time. As a result, the auto-tuning system can have a good response time and an excellent stability. The diagram of the proposed AGC is presented in Figure 6.2. During the holding phase, switches S H turn on and the other switches turn off. The equivalent circuit of the peak detector during this phase is shown in Figure 6.12. The peak detector is isolated from the input signal V in . Switch S W3 , which is shunted with M1, is closed. The transistor M1 is shorted by this switch to ensure that no leakage current flows through C h . In this way, the voltage V Ch remains unchanged. In addition, the OTA is connected as a voltage follower, with V Ch as its input signal. As a result, C o will be charged to V Ch . Further, during this phase, because the OTA is used again as a voltage follower, the offset of the OTA is cancelled. The output voltage can be written by 𝑉 𝑐𝑜 = 𝑉 𝑐ℎ -𝑉 𝑜𝑓𝑓𝑠𝑒𝑡 = 𝑉 𝑜𝑓𝑓𝑠𝑒𝑡 + 𝑉 𝑝𝑒𝑎𝑘 -𝑉 𝑜𝑓𝑓𝑠𝑒𝑡 = 𝑉 𝑝𝑒𝑎𝑘 6.20 After the holding phase, a reset signal is sent to switch S Reset , and the voltage of C h is quickly reset to V DC , which means that V Ch is reset to V DC after each period. This will

V-

Output Buffer

Because the output signal of the FGA is a differential signal, we require an output buffer to transfer this differential output into a single ended output. The diagram of the output buffer is illustrated in Figure 6.17. The DC level of the output signal is fixed by V DC , which in our case is equal to 2.5 V. In this output buffer, R 1 = R 2 = r, and R 3 = R 4 = 4r. Therefore, this output buffer can also provide a 12-dB output gain. The total gain of the AGC then ranges from -8.82 dB to 29.97 dB. The schematic of the OPA used in the output buffer is presented in Figure 6.18. It is a two-stage folded cascade amplifier. The first stage of this OPA has the same 6.4 Integrated Switch Signal Generator

Schematic Design of the Switch Signal Generator

The diagram of the switch signal generator of the auto-tuning system is presented in Figure 6.21.

V OEA- Inverting amplifier The proposed Switch signal generator is composed of two comparators and a unity-gain voltage inverter. In this circuit, we used the comparator proposed in [FPM2004] because of its small delay, high resolution, and simple structure. As can be seen from Figure 6.22, the comparator is composed of three stages, a preamplifier, latch stage, and output stage. The maximum clock frequency of the comparator used in this paper can reach 100 MHz, and the transit delay is approximately 2.5 ns; its resolution is 0.5 mV. Therefore, by using this comparator, the As can be seen from this figure, the designed peak detector has a very good accuracy and speed. The error of the peak detector is less than 6% in the worst case, and the settling time of the proposed peak detector is less than one period. As can be seen from this figure, the proposed AGC can amplify the input signal to a target voltage V ref = 1 V. The settling time of this AGC is less than 11 periods with a gain error of less than 0.25%.

Phase-error Detect Circuit

The frequency-response curve of the proposed phase-error detector circuit is illustrated in Figure 6.42. As analyzed in the former sections, the settling time of the phase-error amplifier needs to be greater than the settling time of the AGC. The maximum settling time of the proposed AGC circuit is 11 periods. Therefore, for a 1.25 The slew rate of the post-layout OTA is changed to 186.9 V/μs. The simulation result of the slew rate is demonstrated in Figure 6.54.

Introduction

In this chapter, we present the results of the complete ultrasonic generator system including the test of the PCB realisation and the simulation of the IC design and combining together the proposed power amplifier combined with the proposed auto-tuning system. The structure of this chapter is as follows: In Section 7.2, we present the test results of the ultrasonic generator with a PCB auto-tuning system. In Section 7.3, first, we show the simulation results of this generator with the integrated design of the auto-tuning circuit, and then, we then give the analysis of these results.

Test of Ultrasonic Generator with PCB Realisation

This sectin presents the test of the ultrasonic generator with PCB realisation. It consists of two parts: test conditon and test results.

Test Condition

To test the functionality of the auto-tuning system, we added a C Error , which is controlled by PWM E (5-kHz square wave).

Post-layout Simulation Results

The post-layout view of the auto-tuning system is demonstrated in Figure 7.7. The circuit in the purple dotted rectangle is the AGC part of the auto-tuning system, while the phase-error amplifier and PWM comparator are illustrated in the red dotted rectangle and blue dotted rectangle, respectively. The circuit illustrated by the green line is the biasing source. The surface area of the proposed AGC circuit is 0.13 mm 2 . Other parts of the proposed auto-tuning system take up an area of 0.29 mm 2 , and the total surface area of the proposed auto-tuning system is 0.42 mm 2 . In Figure 7.8, we present transient post-layout simulation results PWM E is the green line, the red line is the phase-error voltage, and the blue line is the output of the voltage divider in an actual situation.

APPENDIX I.

For the PCB version phase error detector, the comparator used in it is MAX961 which has a resolution of 4 mV by using 5V power supply [MAX961]. So, we can known that the phase error caused by the resolution V R of the comparator can be described by 𝜑 𝐸𝑟𝑟 = 2(sin -1 (𝑉 𝐸𝐴 ) -sin -1 (𝑉 𝐸𝐴 -𝑉 𝑅 )) where V PDErr is the output signal of the phase-error detector. Figure 1 shows the curved surface of the phase error caused by the resolution of the comparator with a different V PDErr . The maximum phase error of the switch-control signal is less than four degrees.

And for the integrated version phase error detector, the comparator used in it has a resolution of 0.5 mV. So, based on Equation (1), we can get the phase error curve caused by the resolution of the integrated comparator. Figure 2 shows the phase error curve. The maximum phase error of the switch-control signal is less than 0.4°. (3) Max(V EA )=5V and Min(V EA )=0V. And the corresponding C SVar are 324pF and 161pF, respectively. Considering that the proposed impedance circuit is an LC circuit, so the phase difference between the ouput of the tuning network V out and the input V in can be written as,

where C= C Fix +C PLoad + C SVar , and r is the equivalent resistance of the tuning circuit. According to Equation 3.48, r can be described by, 𝑟 = 𝑅 𝐿 + 𝑍 𝑂 + 1 (𝑅 𝑃𝑖𝑒𝑧 (2𝜋𝑓 𝑤𝑜𝑟𝑘𝑖𝑛𝑔 𝐶 Piez )

2 ) ⁄ = 0.268 (5) Then ∆φ EAmax -∆φ EAmin can be obtained as follows.

∆𝜑 𝐸𝐴 𝑚𝑎𝑥 -∆𝜑 𝐸𝐴 𝑚𝑖𝑛 ≃ (15.17°+ 14.88°) • Besides, without using bulky magnetic components, this auto-tuning system is completely compatible with MRI equipment. The PCB version was designed to verify the principle of the proposed automatic impedance tuning system, and it is also used to help the design of the integrated circuit. The PCB realization occupies a surface of 110cm 2 . The test results confirmed the expected performance. The proposed auto-tuning system can perfectly cancel the imaginary impedance of the transducer, and it can also compensate the impedance drifting caused by unavoidable variations (temperature variation, technical dispersion, etc.). The IC design of the auto-tuning system is realized in a CMOS process (C35B4C3) provided by Austrian Micro Systems (AMS). The die area of the integrated circuit is only 0.42mm 2 . This circuit design can provide a wide working frequency range while keeping a very low power consumption (137 mW). According to the simulation results, the power efficiency can be improved can up to 20% by using this auto-tuning circuit compared with that using the static tuning network.

Ultrasonic generator for surgical applications and non-invasive cancer treatment by high intensity focused ultrasound