Renée El

Melhem Bat

Blaise Pascal

R Gourdon

M Jean

Marc Lancelin

M Gérard Scorletti
email: gerard.scorletti@ec-lyon.fr

Isabelle Mme

Von Bueltzingloewen

Nicolas Pascale

Phillipe

Alexandre, Samuel, Julien, Benoît Florian Thomas

Minicho, Marc, Chloé Maxime Gomart

Power delivery network 13 System in package 14 Power management integrated circuits

This was a pleasure to share a beer, a bottle of wine, a glass of whiskey

Abstract

Mobile and multimedia devices offer more and more innovations, enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise so fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switchedcapacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the digital SoCs manufacturing process. This thesis focuses on the design of embedded power supplies architecture using switched-capacitor DC-DC converters.

Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3 -1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply. Power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable, linear regulation and hysteretic control are analyzed. Prototypes were fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW /mm 2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to design a negative SC converter for bodybiasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application.

Résumé

Les appareils multimédias portables nécessitent toujours plus d'innovation pour satisfaire les besoins des utilisateurs. Les fabricants de système-sur-puces font donc face à une forte demande en capacité de calcul jusqu'à lors réservée aux ordinateurs de bureau. Ce transfert de performance se répercute inévitablement sur la consommation de ces appareils alors que dans le même temps la capacité des batteries n'est pas en mesure de répondre à cet accroissement. De nombreux compléments matériels et logiciels sont mis en places afin d'économiser l'énergie au maximum sans toutefois dégrader les performances. La modulation de la fréquence de fonctionnement et de la tension d'alimentation est certainement la plus efficace mais reste néanmoins limitée par les coûts et les contraintes d'encombrement exigées par la taille des appareils. La réponse à un tel problème passe nécessairement par l'intégration d'une partie de l'alimentation dans la puce. La conversion DC-DC basée sur des convertisseurs à capacités commutées est prometteuse car elle permet de garder un maximum de compatibilité avec les process CMOS actuels. Cette thèse explore donc la conception d'une architecture d'alimentation utilisant des convertisseurs à capacités commutées.

Un étage de puissance avec une tension d'entrée est de 1.8 V et des ratios programmables permet d'obtenir le rendement maximum pour une plage de tension de sortie allant de 0.3 V à 1.2 V . La tension de sortie peut varier en fonction du point de fonctionnement requit par le système. Afin d'assurer le maximum de compatibilité avec la conception du circuit numérique à alimenter, une architecture modulaire basée sur les capacités MIM est privilégiée. Les capacités sont placées au dessus de la fonction numériques et les interrupteurs de puissance sont insérés à sa périphérie. Cette architecture permet également d'entrelacer les cellules de conversion afin de réduire l'ondulation de la tension de sortie. La fréquence de commutation du convertisseurs est communément utilisée pour réguler la tension de sortie et des stratégies de contrôles linéaires et non linéaires sont donc explorées.

Un prototype de convertisseur présentant une densité de puissance de 310 mW /mm 2 pour un rendement de 72.5% a été fabriqué dans la technologie 28nm FDSOI de STMicroelectronics. La surface requise pour le convertisseur nécessite que 11.5% de la surface du circuit à alimenter. La méthodologie de conception du convertisseur a finalement été appliquée à un régulateur de tension dans le domaine négatif pour des applications de polarisation de caisson à basse consommation.

Introduction

The mass market of multi-media devices exhibits products with ever increasing functions in number and complexity. Behind this offer is hidden a world of powerful integrated circuits. For instance Fig. 1.1 pictures the evolution in computing power and reference clock frequency of various products. To serve these products IC manufacturers employ advanced technology nodes with benefit in density and velocity. Unfortunately these advanced CMOS 1 nodes are not progressing in term of power losses. Jointly the lithium-whatever batteries are indeed progressing in term of energy density but not enough to balance the net increase in power consumption of the circuits. Energy management has thus become a major concern.

The valuable functions in products are designed inside ever growing circuits called For instance the power supply voltage of each blocks is different and the time pattern is also different. This in fact conducts to a situation where a lot of voltage levels have to be fed to a given SoC. At board level this requires to produce the voltage levels from the unique battery voltage level. A bunch of converters have to be implemented on board. Fig. 1.2 depicts the board of a standard smart-phone.

A small number of SoCs appears and a large number of passive devices and other small active circuits are inserted in between, dedicated to voltage converters. The total footprint of the energy conversion aspect is quite huge.

Basically the power solution is to deliver as much as necessary voltage levels as required by each SoC. When the voltage levels may not be shared, additional converters have to be implemented with the necessary passive devices. Moreover a lot of IOs 3 are sacrificed in the SoC package to accommodate the voltage grid. This is described in Fig. 1.3. There is an antagonism between the growth of a SoC set of functions and the available number of IOs as more functions call for more voltage levels and more dedicated IOs. There is clearly a limit to this power supply approach.

A change of paradigm is explored with the idea to disseminate part of the energy converters inside the SoC with only a limited number of external power supply lines.

Ultimately one can think to install only one main board converter of the battery voltage to deliver one fixed input voltage to SoCs. The required voltage levels for 2 System on chip 3 Inputs-outputs • Chapter 2 reviews the published techniques of power management of blocks in a SoC. The switched-capacitor converter is compared to inductive SMPS 5 to highlight its main advantages. The chapter ends with a list of specifications for the solution to be demonstrated.

• Chapter 3 details the fundamentals of SC 6 converter. A modeling approach is introduced and various models are constructed. The losses mechanism is presented to optimize the efficiency of the converter. Then the regulation principle is depicted as well as various control strategies.

• Chapter 4 exposes the implementation of frequency modulation control with linear and non-linear schemes.

• Chapter 5 presents the proposed power stage and the design in 28nm FD-SOI process. A test-chip is then characterized and measurement results are successfully compared to simulation ones. A feedback loop scheme is then implemented to complete a final demonstrator attached to an emulator of a digital macro block. A test-chip is designed in the 28nm FDSOI technology and measured in steady-state and transient conditions.

• Chapter 6 details the application of a SC converter to the specific assistance in 28nm FDSOI so-called body biasing. The interest is in the negative voltage level.

• Conclusion and perspectives are given in chapter 7. 4 Fully depleted silicon on insulator 5 Switch-mode power supply 6 Switched-capacitor CHAPTER 2

Literature review 2.1 Sources of power consumption

The power consumption of a digital circuit comes from two fundamental contributions: the static power consumption and the dynamic power consumption [START_REF] Michael Keating | Low Power Methodology Manual[END_REF].

Hardware functionalities in modern digital CMOS ICs 1 are implemented with a lot of digital gates. CMOS logic gates are made of MOSFET 2 transistors and the gates of the transistors are charged or discharged when a transition occurs. The rate of the transition is determined by the operating frequency and a high frequency yields a fast execution. Fig. 2.1 depicts the switching behavior of a simple inverter. When the input of the inverter falls to 0 V , the PMOS transistor is turned on and the NMOS is turned off. This causes the output to rise to V dd . The current that charges the output node is denoted I c . The average value of this current depends on the 1 Integrated circuits 2 Metal oxide semiconductor field effect transistor 6 Chapter 2. Literature review capacitor at the output node, C, the value of V dd and the switching frequency, f .

Vdd C V A V Y I s I c
Considering the charge of the capacitor, the power consumption, P c , and the energy consumption, E c , normalized over a switching cycle are:

P c = C • V 2 dd • f (2.1) E c = C • V 2 dd (2.
2)

The power depends on the digital clock frequency while the energy does not. Autonomy of battery powered systems is determined by the energy losses and the thermal aspects.

The energy required for a number of cycle, n, is sometimes introduced as follows:

E = n • C • V 2 dd (2.3)
An efficient digital design must perform an instruction set with the lowest value of n.

In addition to the consumption induced by the charge of capacitive nodes, a rush current occurs at each transition because NMOS and PMOS are both conducting during a small lapse of time. This is the so-called shoot-through current, denoted I s in Fig. 2.1. The energy dissipated during the transition is written in a first approximation as:

E t = t s • I s • V dd (2.4)
Where t s is the duration of the short circuit and I s its value. The total dynamic power consumption is obtained by:

P dynamic = P c + E t • f (2.5)
The static power dissipation is considered when the logic state does not change.

This consumption is the result of the leakage currents in the MOS transistors. The total leakage current includes the sub-threshold current, the gate leakage current and the junction leakage current in the transistor. The sub-threshold current is written in a first approximation as follows:

I sub = µC ox W L V 2 th exp V dd -V t n V th (2.6)
where W is the width of the transistor, L its length, µ the mobility, C ox the oxide capacitance, V t the threshold voltage, V th = kT q and n is a technology factor. The static power consumption can be written as:

P static = I static • V dd (2.7)
Power vs performance 7

Where I static is the sum of the leakage currents like the one in (2.6).

Finally the total power consumption, P , is a function of the dynamic and the static power consumptions:

P = P static + P dynamic (2.8)

Power vs performance

Designers are concerned by the performances as well as the power consumption.

However simultaneous improvements of both aspects is quite complicated. The dynamic power consumption is reduced when the power supply and the clock frequency are reduced as shown by (2.1) and (2.4). However the on-current of the MOS transistor is also reduced (2.9):

I DS = µC ox W L (V GS -V t ) 2 2 (2.9)
where W is the width of the transistor, L its length, µ the mobility, C ox the oxide capacitance, V t the threshold voltage and V GS is the gate-source voltage depending on the voltage supply. Reduction of the threshold voltage increases the current of the transistor resulting in a higher speed but static power is increased too. Generally the sub-threshold current increases with on-current as described by (2.6) and

(2.9).

Energy-delay product has been introduced to provide a good metric of the improvement of speed and consumption [START_REF] Gonzalez | Energy dissipation in general purpose microprocessors[END_REF]. Power-delay product is less used due to the clock frequency dependency. Reducing the clock frequency reduces the power consumption but the digital circuit is not better. This figure of merit can be used to compare technology and architecture and demonstrates the best improvements.

The technology scaling

Scaling the technology is profitable regarding performance and integration. That is the reason why high performance digital circuits are usually fabricated in the most advanced nodes. Two opposing approaches of scaling exist: constant field scaling and constant voltage scaling [START_REF] Syed | Sensors and Low Power Signal Processing[END_REF]. Constant field scaling preserves the electrical field in the transistor while its dimensions are scaled down. The power-delay product is reduced but the power supply must be scaled down as well. Constant voltage scaling is preferred to keep compatibility of the voltage between each generation. The dimensions are scaled down too but the doping densities are increased to preserve the transistor performances. The electrical fields increase leading to the 8 Chapter 2. Literature review well-known short channel effect (velocity saturation, hot carrier, mobility degradation,...). Leakage current and power density are also increased. New processing techniques that disrupt the traditional approaches have been introduced. Gate stack using high-k dielectric has been developed to improve the leakage current. Siliconon-insulator substrate offers also a better efficiency and performance trade-offs than the bulk counter part. SOI 3 technology provides lower parasitic capacitances as well as latch-up immunity due to the buried oxide isolation.

Technological aspects are essential to propose both high performance and low power digital circuits. However the rapid growth of the number of functionalities provided by SoCs has called for low power design methodology. These low power techniques are detailed in next Section.

Low power techniques 2.4.1 Design for energy efficiency

Smart and power-oriented architectures have emerged to make more energy efficient SoCs. Clock gating technique has been firstly introduced during the design phase to save part of dynamic power consumption. A large amount of power is indeed consumed by the clock tree and the clock can be turned off when it is not required [START_REF] Michael Keating | Low Power Methodology Manual[END_REF]. This is performed during RTL 4 coding in the design flow of digital blocks. Libraries with multiple threshold devices are also available in advanced technology platforms. Synthesis tools are able to choose a low-threshold voltage device when the performance is critical and a high-threshold voltage device when it is not compromising [START_REF] Noel | Multi-Vt UTBB FDSOI Device Architectures for Low-Power CMOS Circuit[END_REF][START_REF] Shigematsu | A 1-V high-speed MTCMOS circuit scheme for power-down application circuits[END_REF]. The overall leakage current is therefore reduced. Similar approaches use poly-biasing to modulate the gate length of the transistor to optimize the static power consumption [START_REF] Yeric | Technology roadmaps and low power SoC design[END_REF][START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF]. Optimal architecture choice can result in considerable power savings. A SoC usually comprises a processing core. Many functionalities are then implemented with software approaches. The best way to achieve performances and power optimization is to introduce dedicated IP 5 blocks to replace the software functionalities at the cost of area penalty. These hardware accelerators are widely used in multimedia mobile applications [START_REF] Woo | High performance SOC for mobile applications[END_REF]. Pipelining is also an efficient feature that improves the energy-delay product [START_REF] Gonzalez | Energy dissipation in general purpose microprocessors[END_REF].

ARM, a microprocessor design company, goes further with heterogeneous processing architecture. This is the so-called Big.LITTLE technology [START_REF] Arm | White paper: big.LITTLE Technology: The Future of Mobile[END_REF]. Two types of processor are co-integrated: one is optimized for high computing performances and the other one is designed for power efficiency. The tasks are dynamically allocated 3 Silicon on insulator 4 Register transfer language 5 Intellectual property to the proper processor depending on the performance requirement. This is particularly interesting to address the need for a wide range of performances in mobile devices.

Power gating

Power gating is a technique that turns-off unused digital blocks to save static power consumption. Power switches are implemented to cut-off the power supply of a block. A header PMOS power switch is used when Vdd path is cut-off while a footer NMOS power switch is required to cut-off the ground path [START_REF] Shi | Sleep Transistor Design and Implementation -Simple Concepts Yet Challenges To Be Optimum[END_REF]. Header switch configuration is usually preferred in SoC design because ground is common.

The gated blocks are isolated from the powered blocks with a simple pull-down transistor that clamps signals to ground. There are two options for the architecture level implementation: the ring or the distributed approach. Fig. 2.2 depicts the ring implementation. The power switches are inserted around the power-gated blocks.This is thus a suitable option for existing IP blocks. However significant IRdrop can occur in the center of the domain. This voltage drop degrades the block performances. The grid configuration shown in Fig. 2.3 can address this issue. The power switches are distributed through the domain close or inside the standard cells to minimize the IR-drops [START_REF] Shi | A Power Network Synthesis Method for Industrial Power Gating Designs[END_REF]. Unfortunately this requires dedicated standard cell libraries or a specific synthesis flow. As a consequence, the grid configuration has to be included during the design architecture phase and cannot be applied to existing blocks. Furthermore, the distributed approach is more area efficient than the ring approach.

The design of the devices in power gating approach is essential. The I on /I of f ratio is used to evaluate the efficiency of a switch. A good switch is therefore a switch with a low leakage current and a high on-state current (low resistance). The area overhead is also an important metric in SoC design. Literature has covered several improvements of the power switch. Body effect can be used to decrease the leakage current [START_REF] Chowdhury | Innovative power gating for leakage reduction[END_REF]. Dynamic threshold tunning is also offered in SOI process to improve the leakage current [START_REF] Le-Coz | Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec[END_REF]. Super-cut-off scheme is used for low voltage supply system [START_REF] Kawaguchi | A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current[END_REF].

The control voltage of the PMOS switch is raised above the supply voltage in order to reduce the leakage current.

Latency and power integrity are also critical aspects in power gating design. The power supply has to be turned off as often as possible to achieve the lowest static dissipation with fast wake-up and small sleep-time to not alter block operation.

Unfortunately the turning-on of the power switches causes a large inrush current.

The power supply collapses and the operation of the neighbor blocks is disturbed.

The power switches are then progressively turned-on in order to limit the current surge [START_REF] Kim | Understanding and minimizing ground bounce during mode transition of power gating structures[END_REF]. A technique using two power line distribution network is proposed in [START_REF] Kawasaki | A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support[END_REF].

The inrush current is reduced and the wake-up time is improved but at the cost of a complex power grid.

Power gating in the most effective method to reduce the static power dissipation during standby mode of digital blocks. That is the reason why this technique is widely used in low power systems.

Voltage scaling

Voltage scaling is certainly the most aggressive power reduction technique. The dynamic power and the static power drastically scale with the supply voltage. Unfortunately the reduction of power supply is correlated to the operating frequency.

The supply voltage is indeed determined by the critical timing path. When considering a single voltage supply, the highest voltage must be applied to the whole circuit to meet the performance constraints. However some IPs or blocks may run at lower voltage at the same time. Voltage scaling allows to partition the SoC into different voltage domains to optimize performance objectives. The major implementations are static voltage scaling, multi-voltage scaling, dynamic and adaptive voltage scaling.

Static Voltage Scaling This is the simplest approach of voltage scaling. The SoC is partitioned into a small number of power domains powered by a fixed voltage supply [START_REF] Lackey | Managing power and performance for system-on-chip designs using Voltage Islands[END_REF]. An example is given in Fig. 2.4. The most demanding blocks require the maximum voltage sustained by the technology. The other IP blocks can work at a lower voltage supply and lower frequency. The number of power domains can be increased to save more power but the power grid becomes more complex. It is also limited by the number of off-chip regulators.

Multi-Voltage Scaling This extension of the static voltage scaling offers supply voltages to vary with discrete values. This is so-called Vdd-hopping or Vdddithering in literature. Strategy with two supply voltages demonstrates good results [START_REF] Calhoun | Ultra-dynamic voltage scaling using subthreshold operation and local voltage dithering in 90nm CMOS[END_REF] and is applied to a multi-processor chip in [START_REF] Cheng | Dynamic voltage and frequency scaling circuits with two supply voltages[END_REF]. The concept is depicted in Fig. 2.5. The voltage levels are generated off-chip and selected by a controller with a power line multiplexer. Two operating frequencies are also associated with the operating voltage. The number of external power supplies can be maintained as low as with the static voltage scaling. An area overhead of 12% but an improvement by 48% in energy consumption is reported in [START_REF] Cheng | Dynamic voltage and frequency scaling circuits with two supply voltages[END_REF]. Application of multi-voltage scaling has been applied to SRAM 6 in low power SoCs. Memory arrays can be large 6 Static random access memory and only some blocks such as CPU and GPU can be properly addressed.

Body-biasing

Body-biasing uses the body effect of the transistor to adjust the threshold voltage.

The body of the transistor is often called the back-gate. The back-gates of an inverter are represented in Fig. 2.7. No body-biasing scheme is applied when V bbp and V bbn are respectively equal to vdd and gnd. Otherwise two cases are considered:

the reverse body-biasing (RBB) and the forward body-biasing (FBB).

• RBB: V bbp > vdd and V bbn < gnd. The threshold voltage is increased. This decreases the current capability of the transistor and the leakage current as well. The speed performances are reduced and this configuration is mostly applied to low power mode such as standby mode.

• FBB: V bbp < vdd and V bbn > gnd. Body-biasing is also used to compensate process variations or temperature deviation in digital circuits [START_REF] Tschanz | Adaptive body bias for reducing impacts of die-to-die and withindie parameter variations on microprocessor frequency and leakage[END_REF][START_REF] Chen | Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation[END_REF][START_REF] Kamae | An area effective forward/reverse body bias generator for within-die variability compensation[END_REF]. This is the so-called adaptive body-biasing. On-die process monitoring is required to determine the proper biasing scheme. This is particularly interesting for sensitive design such as ultra-low voltage circuits.

Power delivery

The objective of a power delivery network is to dispatch the voltage supply from the energy sources to the consumers in the most efficient and cleanest manner.

Performances of a power delivery network depends on the design of the PCB 7 , the packaging technology of the circuit and the power management strategy. A classical power delivery is represented in Fig. 2.8. The primary source of energy is a battery.

The voltage level is adapted by the voltage regulator module located on the board.

The regulated voltage is then routed to the on-die load through the board tracks, the balls or the pins of the package and the on-die power grid. Each elements and discontinuity in the power delsivery network introduce parasitic effects. The parasitic effects are responsible for voltage fluctuation within the power delivery network.

These effects are mitigated by a proper package, board and decoupling strategy. It involves the analysis of the power delivery performances. Power delivery network can be modeled with lumped RLC network [START_REF] Gupta | Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network[END_REF][START_REF] Hockanson | Power Delivery for High Performance Processor Packages -Part I[END_REF]. Power grids and connections are represented with RL networks such C4 8 bumps, package balls, etc. Decoupling capacitors are modeled with the equivalent series-resistance and series-inductance with RLC network. The performances of the power delivery network are evaluated by extracting the impedance of the power net [START_REF] Altera | AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology[END_REF][START_REF] Petillon | Power Delivery Network Analysis[END_REF]. Objectives are defined for each element to meet the performance constraint and the targeted impedance :

Z target = V supply • ∆V % I max (2.10)
Where V supply is the voltage level needed for the application, ∆V % is the maximum allowed voltage fluctuation in percent and I max is the maximum transient current surge. The first elements that respond to the current surge are on-die and onpackage decoupling capacitors. Then comes the board decoupling capacitors and finally, the voltage regulators. Several types of capacitor are combined to optimize the frequency response as much as possible.

The packaging technology has a strong impact on the power delivery network and on the power management strategy. Even more IOs are required to meet power density and memory requirements [START_REF] Stanley-Marbell | Pinned to the walls: Impact of packaging and application properties on the memory and power walls[END_REF]. Integration remains the biggest challenge.

Packaging solution is determinant to achieve both high performance and energy efficient SoC. Fig. 2.9 shows the competitive edge of Samsung in packaging technology. Flip-chip assembly with BGA 9 package is one of the technique that provides the highest number of IO resources. Nonetheless 3D structures have emerged to increase the integration level but the complexity is prohibitive for low-cost solutions.

Power supply

Nowadays, digital SoC for mobile applications always include a power management companion chip. The power management circuit has several goals. First, the battery cannot maintain a constant voltage during the whole operating time. The voltage of a battery also depends on the technology uses for the electrochemical cell. Moreover many voltages level are required for multi voltage strategy. Therefore some

- + V o I o V bat V ref
Φ 2 Φ 1 Φ 2 Φ 1 C f ly C load + - V bat V o
η LDO = V in I out V out (I out + I q ) (2.11)
The quiescent current, I q , is relatively low and can be neglected if I out is high, generally true when LDO is regulating. Hence the efficiency depends on the output voltage to input voltage ratio. Poor efficiency is therefore achieved for large dropout and this is not suitable for high power load.

Inductive DC-DC converter are preferred to supply large power load. A step-down converter is shown in Fig. [55] [START_REF] Seeman | An ultra-low-power power management IC for energy-scavenged Wireless Sensor Nodes[END_REF] [57]

[58]

[59]

[60]

[61] SoCs continue to increase while the voltage tend to decrease to mitigate the power consumption. The impedance of the PDN 12 must decrease as well to keep the same performances [START_REF] Francesco | Power supply on chip: from R&D to commercial product[END_REF]. Moreover complex power delivery and bus speed limit the timing transition between different operating points.

Area of targeted performances

Power density [W/mm

Recent advances in magnetics [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF] and packaging technologies offer new platforms with high integration level. Power supply manufacturers integrate passive devices on the die (homogeneous architectures) or using SiP Fully or partially integrated voltage regulation appears as a suitable approach to increase DVFS usage. A recent growth of literature demonstrates the interest of such methods [START_REF] Amelifard | Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips[END_REF][START_REF] Zeng | Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation[END_REF][START_REF] Gjanci | A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)[END_REF][START_REF] Kose | Emerging and Selected Topics in Circuits and Systems[END_REF][START_REF] Vaisband | Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies[END_REF]. The linear voltage regulator is certainly the simplest approach since no passive devices are required. Such an approach is presented in [START_REF] Gjanci | A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)[END_REF][START_REF] Vaisband | Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies[END_REF] and a practical implementation for the POWER8 microprocessor is demonstrated in [START_REF] Toprak-Deniz | 5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor[END_REF].

The comparator-based voltage regulator allows fast transition with a maximum efficiency of 90%. Efficiency decreases at low voltage but is still sufficient to enhance power consumption saving. A power density of 34.5 W /mm 2 is reported that is appropriate for server-class microprocessor. Per-core voltage generation is interesting in these systems in terms of cost and area but thermal limitations and efficiency can only be improved by switching voltage regulators. 3D integration through stacking voltage regulator die above the IC is a possibility [START_REF] Onizuka | Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs[END_REF] but semiconductor manufacturers have also developed and integrated magnetic devices and high density capacitors in their process to enable inductive and capacitive voltage regulation on the die. Efficiency versus power density is one of the most frequently used performance metric to compare DC-DC converters. Other figures of merit offer the possibility for a more detailed analysis [START_REF] Neveu | Review of high frequency, highly integrated inductive DC-DC converters[END_REF][START_REF] Villar-Pique | Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach[END_REF][START_REF] Sanders | The Road to Fully Integrated DC:DC Conversion via the Switched-Capacitor Approach[END_REF]. A landscape of the most recent and relevant works on integrated conversion is depicted in Fig. 2.13. The challenge is to achieve both high efficiency and high power density at an acceptable cost or in a manner compatible with the synthesis of the circuit to be powered. The usual common value for the SoC power density is 1 W /mm 2 but a small silicon area penalty would require in fact a density of 10 W /mm 2 for the DC-DC converter. The quality of the passive devices is essential. As expected the highest performances are achieved by Intel Haswell architecture with non-magnetic core inductance but the technology is unaffordable for many applications [START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]. Some DC-DC converters using air core inductors on package exhibit acceptable efficiency near 1 W /mm 2 [START_REF] Schrom | A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm 2 Using Air-Core Inductors[END_REF][START_REF] Hazucha | A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package[END_REF][START_REF] Huang | A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction[END_REF][START_REF] Ishida | 3D stacked buck converter with 15 um thick spiral inductor on silicon interposer for finegrain power-supply voltage control in SiPs[END_REF][START_REF] Bergveld | A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration[END_REF][START_REF] Sun | 3D Power Delivery for Microprocessors and High-Performance ASICs[END_REF] while those using on-die air core inductors still suffer from lower power density [START_REF] Kudva | Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range[END_REF][START_REF] Wens | A Fully Integrated CMOS 800-mW Four-Phase Semiconstant ON/OFF-Time Step-Down Converter[END_REF][START_REF] Wibben | A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors[END_REF][START_REF] Abedinpour | A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18 µ SiGe process[END_REF]. Switched-capacitor (SC) converters demonstrate a high efficiency at a density mainly limited by the density of the capacitors [50-55, 58-60, 74]. The limit in power density featured in [START_REF] Somasekhar | Multi-phase 1GHz voltage doubler charge-pump in 32nm logic process[END_REF] clearly calls for high density capacitors. Deep trench capacitors have been Proposed architecture 21 introduced and enable a peak efficiency of 85 -90% up to 1 W /mm 2 [START_REF] Andersen | A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at Chapter References 90% efficiency using deep-trench capacitors in 32nm SOI CMOS[END_REF][START_REF]A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF][START_REF] Chang | A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2[END_REF]. Architectures distributed across digital core also bring a relevant point [START_REF] Jain | A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS[END_REF]. The flying capacitors are distributed over the digital core and the area penalty is limited to the one of the power switches and the controller. Generally SC converters present the best trade-off for low-cost monolithic integrated solution and they are more and more investigated [START_REF] Sanders | The Road to Fully Integrated DC:DC Conversion via the Switched-Capacitor Approach[END_REF]. Resonant SC converters or cascaded SC converters with inductive converters are also explored to take advantages of both capacitors and inductors. Resonant SC converters use an inductor in series with the flying capacitor to produce a resonant energy transfer [START_REF] Stauth | Resonant Switched-Capacitor Converters for Sub-module Distributed Photovoltaic Power Management[END_REF][START_REF] Kesarwani | Resonant Switched-Capacitor Converters for Chip-Scale Power Delivery: Design amp; Implementation[END_REF]. Efficiency can be improved for a given power density but inductors remain costly. SC converters cascaded with inductive converters seems promising [START_REF] Pilawa-Podgurski | Merged two-stage power converterarchitecture with softcharging switched-capacitor energy transfer[END_REF]. An unregulated SC converter is used to convert the high input voltage to a lower one. Then an inductive converter achieves a fine regulation. This combination allows large voltage step-down and high bandwidth regulation.

Proposed architecture

Earlier was mentioned the monitoring of voltage through power switches connected between the digital block unique power lines and a quite complex power grid. The silicon area of the power switches is in the range of 3% to 10% of the digital block area. The power grid consumes as much IOs as voltage levels. The change of paradigm proposed here is to limit the IO consumption to one input voltage level (due to IR-drop more than one IO will be needed). The area dedicated to the power switches in a conventional approach will be diverted to implement a full voltage converter. For the sake of integration, the SC converter is the suitable candidate. Fig. 2.14 illustrates the targeted implementation. The converter silicon area should be restricted to the reasonable value of 10% of the one of the digital block. It is obvious that capacitors cannot fit a so constrained area. An economic and none complex solution is to consider MIM 17 capacitors to be located above the digital core. Referring to Fig. 2.14 it is expected the following performances:

• Peak efficiency will be over 75% for a targeted power density of 1 W /mm 2

• The digital core design flow should not be affected by the SC converter implementation.

• The transient performances should be sufficient to afford a DVFS application. Obviously the pointed target area in Fig. 2.14 cannot be reached. The objective of the demonstrator is then to join the best-in-class literature results based on MIM capacitors. The idea is to provide better performances and systematic design approach at a similar cost. A demonstrator in FDSOI 28nm will add a relevant and original point in the landscape in 2.13.

CHAPTER 3

Fundamentals of Switched-capacitor converter

The chapter summarizes the behavior of a SC converter, evaluation of losses and modeling of dynamics toward control design.

Principles

SC converters are a part of switched-mode converters. They are built only with capacitors and switches. Flying capacitors are charged and discharged between the input and output nodes during operation. The configuration of both switches and The total available energy is:

S 1 S 2 S 3 S 4 C f ly V out C load V in
E 1 = 1 2 C 1 v 2 1 + C 2 v 2 2 (3.1)
Then these capacitors are connected in parallel though a resistance R. The charges are redistributed and the voltage across each capacitor equilibrates at a voltage v 3 :

v 3 = C 1 v 1 + C 2 v 2 C 1 + C 2 (3.2)
The energy available is now:

E 2 = C 1 + C 2 2 v 3 (3.3) = (C 1 v 1 + C 2 v 2 ) 2 2 (C 1 + C 2 ) (3.4)
The difference between the initial energy, E 1 and the final energy, E 2 , is the energy lost by the system:

E loss = C 1 C 2 2 (C 1 + C 2 ) (v 1 -v 2 ) 2 (3.5)
The system has less energy than in initial state. This energy is dissipated in the resistance but does not depend on its value.

The 2:1 SC converter will be used for illustration purpose throughout the chapter.

The various parameters of this converter are gathered in Table 3.1. The nominal input voltage is V in , the nominal load current is I load , the flying capacitor is C f ly , the output capacitor is C load , the on-state resistance of the switches, R on , is identical for each switch and the duty-cycle of the charging topology is DC.

Parameter V in C f ly R on C load I load DC Value 2 V 200 pF 10 Ω 10 nF 5 mA 50 %

Modeling

Various methods are proposed in literature. Historically SC filters have been explored first. The time-domain and frequency-domain analysis are performed with state equation formulation [START_REF] Fang | Time-and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables[END_REF] or nodal analyses [START_REF] Tsividis | Analysis of switched capacitive networks[END_REF]. Special purpose simulators have been also proposed to easily perform the analysis [START_REF]The SWITCAP Website[END_REF]. SC filters usually operate at a fixed switching frequency and in the slow switching region while SC converters have variable frequency and operate toward the boundary of the fast switching region. The latter regions are explained here after. That is the reason why further analyses have been recently extended to SC converters. The next sections details the most relevant.

Static model

The static model of a SC converter is depicted in Fig. 3.3. The ratio of the topology is represented by an ideal transformer and a turning ratio. An output resistance is inserted to symbolize the voltage drop when the converter is loaded. The method developed in [START_REF] Seeman | Analysis and Optimization of Switched-Capacitor DC-DC Converters[END_REF] provides a powerful framework to determine the ratio and the output resistance of any topology. This method is based on the charge flow analysis.

+ - V in m : n R out V out
Two operation regions are defined according to the switching frequency: the Slow Switching Limit (SSL) and the Fast Switching Limit (FSL). A charge/discharge time-constant is formed by the on-state switch resistance and the flying capacitors.

When the switching period is large compared to this time-constant, the converter operates in the SSL region. On the contrary, when the switching period is small regarding the time-constant, the converter is in the FSL region. The charge balance analysis is used to determine both the output resistance in the SSL and FSL regions.

In the SSL region, the switching frequency is low and the flying capacitor is completely charged and discharged in each phase. Thus the resistive effect can be neglected. A set of charge multiplier vector, a n , is defined to represent the charge flow when the switches are closed for the n phase of the converter.

a n = -q n in q n c,1 . . . q n c,i q n out (3.6)
where q in is the charge at the input, q out at the output and q n c,i the charge accumulated in the i-th capacitor. The charge multipliers of the capacitors are gathered in a vector a n c and the input and output ones in a n in and a n out respectively.

a n = a n in a n c,i a n out (3.7)
The charge multiplier vectors are normalized with respect to the total charge at the output, q out

a n = a n in a n c,i a n out /q out (3.8)
The ratio of the topology is given by the ratio between the total amount of charge at the input and the total amount of charge at the output:

m n = - q in q out (3.9)
The output resistance in SSL is then computed using the results in [START_REF] Seeman | Analysis and Optimization of Switched-Capacitor DC-DC Converters[END_REF]:

R SSL = i∈caps n j=1 a j c,i 2 2 • C i • f sw (3.10)
The charging/discharging phase in not completed in the FSL region and the resistive effects cannot be neglected. Similarly to the SSL analysis, switch charge multipliers, a n r,i are introduced to represent the charge flowing in the switches i during the phase n.

a n r = a n r,1 . . . a n r,i (3.11)

Modeling 27

The output resistance is derived as follows [START_REF] Seeman | Analysis and Optimization of Switched-Capacitor DC-DC Converters[END_REF]:

R F SL = i∈switches n j=1 R i D j a j r,i 2 (3.12)
where R i is the on-state resistance of the i-th switch and D j the duty-cycle of the phase j. The output resistance in both operating regions have been introduced.

However the output resistance must be determined for any switching frequency.

The output resistance can be approximated using a combination of the resistance in the two regions:

R out ≈ R 2 SSL + R 2 F SL (3.13)
The method is applied to the 2:1 SC converter in Fig. 3.1. The charge multipliers in the SSL region are:

a 1 = -0.5 0.5 0.5 (3.14)
a 2 = 0 -0.5 0.5 (3.15)
The value of the ratio is given by (3.9)

m n = - -0.5 1 = 1 2 (3.16)
and the output resistance in SSL is

R SSL = 0.25 C f ly f f sw (3.17)
Then charge multipliers of the switches are derived in the FSL region:

a 1 r = 0.5 0.5 0 0 (3.18) a 2 r = 0 0 -0.5 -0.5 (3.19)
The output resistance in FSL is calculated with a duty-cycle of 50%:

R F SL = 2R on (3.20)
The output resistance and the two asymptotic limits are evaluated with the parameters in Table 3. (a) Current in the flying capacitor

Modified static model

The previous model does not take in account the impact of the output capacitor on the output resistance of the converter. The previous model is valid for large output capacitance value but when this value is small regarding the flying capacitors, the model is not accurate [START_REF] Van Breussegem | Accuracy improvement of the output impedance model for capacitive down-converters[END_REF]. The charges are transfered between the input and the output nodes. The discrete behavior imposes the usage of an output capacitor to maintain the output node during the charging phase. The output capacitor is discharged by the load during operation. Therefore an amount of charge is transfered from the flying capacitors to the output capacitor. As previously explained, charge transfers are lossy and the latter mechanism is no exception. The demonstration in [START_REF] Van Breussegem | Accuracy improvement of the output impedance model for capacitive down-converters[END_REF] shows that the output resistance in the SSL region can be written with respect to the output capacitor, C load as:

R SSL = i∈caps n j=1 C load C load + C i • a j c,i 2 2 • C i • f sw (3.21)

Non linear averaged model

The previous method is suitable to determine the ratio and the output resistance of a complex topology. However the approximation of the output resistance cannot yield an accurate model. That is the reason why average modeling approaches have been introduced [START_REF] Evzelman | Average-Current-Based Conduction Losses Model of Switched Capacitor Converters[END_REF]. The charging and discharging phases are represented using RC networks as in Fig. 3.7 where ∆V i represents the voltage across the switch before it is closed, R i gathers the resistive effects in the switches and the interconnection parasitics, C i is the total capacitance and i denotes the corresponding phase. The

+ - ∆V i R i i(t) C i
P R i = k 2 i • I 2 o • 1 2f sw C i • coth β i 2 (3.
R e i = k 2 i • 1 2f sw C i • coth β i 2 (3.23)
The whole resistance is simply calculated summing the partial resistance in each phase of operation

R out = n i=1 R e i (3.24)
This method also offers to derive the equivalent output resistance of resonant converters [START_REF] Evzelman | Average-Current-Based Conduction Losses Model of Switched Capacitor Converters[END_REF].

The method is applied to the 2:1 SC converter in Fig. 3.1: k 1 = k 2 = 0.5 and

β 1 = β 2 = 1 4R on C f ly f sw . R e 1 = R e 2 = 1 8f sw C f ly • coth 1 8R on f sw C f ly (3.25) Finally R out = 1 4f sw C f ly • coth 1 8R on f sw C f ly (3.26)
The output resistance and the two asymptotic limits are evaluated with the parameters in Table 3.1 and the results are plotted in Fig. 3.8. The average model is more accurate than the static model because the static model relies is an approximation of the resistance in the SSL and FSL region.

Sampled-data modeling

As suggested in [START_REF] Verghese | A General Approach to Sampled-Data Modeling for Power Electronic Circuits[END_REF], the modeling of switched-mode converters is usually specific.

Sampled-data modeling has been introduced as a practical and uniform approach.

DC-DC converters are variable discrete structures and hybrid automaton is a convenient method for representation and simulation purpose [START_REF] Cliquennois | Unified modeling of Switched-mode Power supplies in Matlab using state-space representation[END_REF][START_REF] Cliquennois | A New Architecture Simulator for Integrated Switched-Mode Power Supplies Circuits Based on Symbolic Calculus Tools[END_REF]. A cyclic hybrid automaton with N states is represented in Fig. 3.9. The dynamics of a state is This dynamics corresponds to the continuous behavior while the discrete behavior takes place when a transition between two states occurs. In Fig. 3.9, the first state, The classical sampled-data modeling approach detailed in [START_REF] Fang | Sampled-Data Analysis and Control of DC-DC Switching Converters[END_REF] is now formulated for a cyclic hybrid automaton. In this thesis, dynamics of each states are described with state-representation and linear-time invariant (LTI) elements as follow

S 1 S N S N -1 S 2 t = d 1 t = d 2 t = T n t = d N -1
S
S 1 : ẋ = A 1 x + B 1 U y = C 1 x + D 1 U for t ∈ [t n , t n + d 1n ] (3.27)
. . .

Chapter 3. Fundamentals of Switched-capacitor converter

S i : ẋ = A i x + B i U y = C i x + D i U for t ∈ [t n + d (i-1)n , t n + d in ] (3.28)
. . .

S N : ẋ = A N x + B N U y = C N x + D N U for t ∈ [t n + d (N -1)n , t n + T n ] (3.29)
where x represents the state-vector, U , the input and y, the output. The state vector, x i , corresponding to the state i of the hybrid automaton is determined for an initial state-vector, x 0 by

x i (t, x 0 ) = e A i t x 0 + t 0 e A i (t-σ) dσB i u (3.30)
At time t i , (3.30) becomes (3.31)

x i (t i , x 0 ) = Φ i x 0 + Γ i u (3.31)
where,

Φ i = e A i t i (3.32) Γ i = t i 0 e A i σ dσB i (3.33)
Two distinct mathematical cases occur when Γ i is analytically derived. If A i is nonsingular, its inverse exists and

Γ i = e A i t i -I A -1 i B i (3. 34
)
Where I is the identity matrix.

If A i is singular, its inverse does not exist analytically and we use the Jordan Form to rewrite A i as

A i = P i L i 0 0 M i P -1 i (3.35)
Where L i is strictly upper triangle and M i is nonsingular. Then

Γ i = t i 0 e A i σ dσB i (3.36) = P i t i 0 e L i σ dσ 0 0 M -1 i e M i t i -I P -1 i B i (3.37)
Let's now evaluate the value of the state vector at each switching instant using (3.31) to assure the continuity between each state of the hybrid automaton. The cycle-tocycle dynamics can be thus determined with a recurrence function by sampling the Modeling 33

x 0 (0)

x 0 (T )

x 0 (d N -1 )
x 0 (d 2 )

x 0 (d

x n+1 = f (x n , u n , τ n ) = Φx n + Γu n y n = Cx n + Du n (3.38)
where

Φ = N k=1 Φ k (3.39) Γ = N -1 k=1   N -k j=2 Φ j   Γ k + Γ N (3.40) τ n =       d 1n . . . d N n T n       (3.41)
The matrices C and D are used to determine outputs of the system at the end of the cycle.

The steady-state operation of the automaton corresponds to a T-periodic solution in the sampled-data model. The system describes a periodic orbit as depicted in Fig. 3.10. The solution x 0 (0), U, τ is called the fixed point. The steady-state operation is reached when x n+1 = x n and the fixed point satisfies

x 0 (0) = f x 0 (0) , U, τ (3.42)
x 0 (0) = Φx 0 (0) + ΓU (3.43)

Chapter 3. Fundamentals of Switched-capacitor converter

Finally the periodic solution of the state vector is

x 0 (0) = (I -Φ) -1 ΓU (3.44)
Sampled-data modeling offers a powerful framework to analyze switched-mode converter. The converter can be modeled with the parasitics elements. The dead-time of switching can be represented with an extra state in the hybrid automaton. Finally sampled-data modeling offers the description of interleaved converters. This method is thus widely used along the thesis due to its uniform and systematic approach. The first application is the output resistance determination introduced in [START_REF] Henry | Practical Performance Analysis of Complex Switched-Capacitor Converters[END_REF]. The sampled-data model of the converter is

x n+1 = f (x n , u n , τ n ) v outn = Ex n (3.45)
The output voltage of the converter, v outn , is isolated by the vector E when the converter has an ideal output capacitor. The output voltage is indeed the state variable representing the output capacitor voltage. The authors in [START_REF] Henry | Practical Performance Analysis of Complex Switched-Capacitor Converters[END_REF] propose to evaluate it for any SC converter with a turning ratio n m as follows:

R out = n m V in -V out I load (3.46) = n m V in -Ex 0 (0) I load (3.47)
For illustration purpose the sampled-data modeling is derived for a 2:1 SC converter and a 4-interleaved 2:1 SC converter. The diagram of the interleaved converter is depicted in Fig. 3.15 and the interleaving strategy is detailed in Section 3.5.

The first step involved in the methodology is to extract the state-space matrices of each states. However manually deriving the state-space model using Kirchoff laws requires a lot of efforts. Fortunately dedicated tools have been developed to address this issue. A state-space model generator for SC converter is proposed in [START_REF]Switched-Capacitor Converter State Model Generator[END_REF] and considerably simplifies the derivation but still requires some manual

interventions. An automated extraction tool called HySim is therefore introduced.

The extractions are perform using Spice circuit netlists with LTI elements avoiding any hand derivation mistakes. Therefore the complexity of the model does not depend on the number of elements and the time required for the derivation. HySim is presented in Appendix A. The state-space representation for the 2:1 SC converter

where

τ 1 = R on C f ly and τ 2 = R on C load is A 1 =     -1 2τ 1 -1 2τ 1 -1 2τ 2 -1 2τ 2     , A 2 =     -1 2τ 1 1 2τ 1 1 2τ 2 -1 2τ 2     Modeling 35 B 1 =     0 1 2τ 1 -1 C load 1 2τ 2     , B 2 =   0 0 -1 C load 0   C 1 = C 2 = E = 0 1 , D 1 = D 2 = 0 U =    I load V in    , x =    v C f ly v C load    , τ =    d T   
Mathematical issue is encountered for this case. The determinant of the matrix A 1 and A 2 are

det[A 1 ] = -1 2τ 1 -1 2τ 2 - -1 2τ 1 -1 2τ 2 = 0 (3.48) det[A 2 ] = -1 2τ 1 -1 2τ 2 - 1 2τ 1 1 2τ 2 = 0 (3.49)
As a consequence the matrices are singular. The Jordan decomposition is used to compute the matrices Γ 1 and Γ 2 :

A 1 = P 1 J 1 P -1 1 = -1 τ 2 τ 1 1 1 • 0 0 0 -τ 1 +τ 2 2τ 1 τ 2 • -τ 1 τ 1 +τ 2 τ 2 τ 1 +τ 2 τ 1 τ 1 +τ 2 τ 1 τ 1 +τ 2 (3.50) A 2 = P 2 J 2 P -1 2 = 1 -τ 2 τ 1 1 1 • 0 0 0 -τ 1 +τ 2 2τ 1 τ 2 • τ 1 τ 1 +τ 2 τ 2 τ 1 +τ 2 -τ 1 τ 1 +τ 2 τ 1 τ 1 +τ 2 (3.51)
The matrices Γ 1 and Γ 2 are given using (3.37)

Γ 1 = d 0 e A 1 σ dσB 1 (3.52) = P 1 •   d 0 0 -2τ 1 τ 2 τ 1 +τ 2 e -d τ 1 +τ 2 2τ 1 τ 2 -1   • P -1 1 B 1 (3.53) Γ 2 = (T -d) 0 e A 2 σ dσB 2 (3.54) = P 2 •   T -d 0 0 -2τ 1 τ 2 τ 1 +τ 2 e -(T -d) τ 1 +τ 2 2τ 1 τ 2 -1   • P -1 2 B 2 (3.55)
Numerical integration can be used instead. 3.2: Parameters for the evaluation of the sampled-data model

= R on C load is A 1 =                   -1 2τ 1 0 0 0 -1 2τ 1 0 -1 2τ 1 0 0 1 2τ 1 0 0 -1 2τ 1 0 1 2τ 1 0 0 0 -1 2τ 1 -1 2τ 1 -1 2τ 2 1 2τ 2 1 2τ 2 -1 2τ 2 -2 τ 2                   , A 2 =                   -1 2τ 1 0 0 0 -1 2τ 1 0 -1 2τ 1 0 0 -1 2τ 1 0 0 -1 2τ 1 0 1 2τ 1 0 0 0 -1 2τ 1 1 2τ 1 -1 2τ 2 -1 2τ 2 1 2τ 2 1 2τ 2 -2 τ 2                   A 3 =                   -1 2τ 1 0 0 0 1 2τ 1 0 -1 2τ 1 0 0 -1 2τ 1 0 0 -1 2τ 1 0 -1 2τ 1 0 0 0 -1 2τ 1 1 2τ 1 1 2τ 2 -1 2τ 2 -1 2τ 2 1 2τ 2 -2 τ 2                   , A 4 =                   -1 2τ 1 0 0 0 1 2τ 1 0 -1 2τ 1 0 0 1 2τ 1 0 0 -1 2τ 1 0 -1 2τ 1 0 0 0 -1 2τ 1 -1 2τ 1 1 2τ 2 1 2τ 2 -1 2τ 2 -1 2τ 2 -2 τ 2                   B 1 =                  0 1 2τ 1 0 1 2τ 1 0 0 0 0 -1 C load 1 τ 2                  , B 2 =                  0 1 2τ 1 0 0 0 0 0 1 2τ 1 -1 C load 1 τ 2                  B 3 =                  0 0 0 1 2τ 1 0 1 2τ 1 0 0 -1 C load 1 τ 2                  , B 4 =                  0 0 0 0 0 1 2τ 1 0 1 2τ 1 -1 C load 1 τ 2                  Modeling 37 V in C f ly R on C load I load f sw
x =                v C f ly1 v C f ly2 v C f ly3 v C f ly4 v C load                , U =    I load V in    , τ =            d 1 d 2 d 3 T            C 1 = C 2 = C 3 = C 4 = E = 0 0 0 0 1 D 1 = D 2 = D 3 = D 4 = 0
Three cases are considered for the sampled-data model evaluation: the 2:1 SC converter, a 4-interleaved 2:1 SC converter with equal interleaving times and a 4interleaved 2:1 SC converter with non-equal interleaving times. The fixed point solution x 0 (0), U, τ (1) denotes the 2:1 SC converter case, x 0 (0), U, τ (2) the 4interleaved with equal interleaving times and x 0 (0), U, τ (3) in the case of non-equal interleaving times. The parameter values for each case are given in Table 3.2.

x 0 (0), U, τ

=          (1)
x 0 (0) = 0.375 0.373

U = 5 • 10 -3 2 τ = 5 • 10 -8 1 • 10 -7
x 0 (0), U, τ

=          (2)
x 0 (0) = 0.3751 0.3751 1.6249 1.6249 0.3749

U = 5 • 10 -3 2 τ = 2.5 • 10 -8 5 • 10 -8 7.5 • 10 -8 1 • 10 -7
x 0 (0), U, τ

=          (3)
x 0 (0) = 0.3751 0.3751 1.6249 1.6249 0.3749 This comes from the approximation in the output resistance.

U = 5 • 10 -3 2 τ = 2 • 10 -8 5.

Losses

The losses and the efficiency of a SC converter are evaluated with non ideal devices.

The switches are implemented with MOSFET transistors and the capacitors are implemented with devices available in the CMOS process. The equivalent model used for losses derivation is shown in Fig. 3.16a for a CMOS switch and in Fig. 3.16b for the flying capacitor . The on-state resistance is R on and C gate corresponds to the equivalent capacitance charged/discharged when the switch is turned on/off. The flying capacitor exhibits an equivalent series-resistance, R ESR , accounting the

S 1 S 2 S 3 S 4 C f ly V in S 1 S 2 S 3 S 4 C f ly V in S 1 S 2 S 3 S 4 C f ly V in S 1 S 2 S 3 S 4 C f ly V in C load V out
P Rout = R out I 2 load (3.56)
In the SSL region, the losses are associated to the capacitor and the switching frequency. Let W c be the width of the flying capacitor, L c the length of the flying capacitor and C 0 c the density of the flying capacitor:

C f ly = W c L c C 0 c (3.57)
The losses in the SSL are expressed as

P SSL ∝ 1 W c L c C 0 c f sw (3.58)
On the contrary the losses are dominated by the resistive losses in the FSL region.

The derivation of the output resistance includes the on-state resistance, R on , as well as the equivalent series-resistance of the capacitor, R ESR . The equivalent seriesresistance is expressed with W c , L c and σ c , the resistivity of the plate in Ω / :

R ESR = L c W c σ c (3.59) 42
Chapter 3. Fundamentals of Switched-capacitor converter

Power loss C 0 c W c L c α top α bot σ c C 0 g W s L s σ s f sw D P SSL ↓ ↓ ↓ - - - - - - - ↓ - P F SL - ↓ ↑ - - ↑ - ↓ ↓ ↑ - ↓ P gate - - - - - - ↑ ↑ ↑ - ↑ - P top - ↑ ↑ ↑ - - - - - - ↑ - P bot - ↑ ↑ - ↑ - - - - - ↑ -
Table 3.3: Wrap-up of the parameter influences on the losses Similarly the on-state resistance is defined as:

R on = L s W s σ s (3.60)
where W s is the width of the transistor, L s the length and σ c the resistivity in Ω / .

The power losses of the output resistance in the FSL region are:

P F SL ∝ L c σ c W c D + L s σ s W s D (3.61)
The parasitic losses of the switches and the capacitors are included in addition to the output resistance losses. The switching losses of the gate capacitance are computed as follows:

P gate = C gate V 2 gate f sw (3.62)
Let C 0 g be the density of the gate capacitance of the switch, (3.62) becomes:

P gate = W s L s C 0 g V 2 gate f sw (3.63)
Then the power losses of the parasitic capacitances are:

P top = C bot V 2 top f sw (3.64) = α top C f ly V 2 top f sw (3.65) = α top W c L c C 0 c V 2 top f sw (3.66)
where V top and V bot are the voltages across C top and C bot respectively, α top and α bot are the ratios between the parasitic capacitances and the flying capacitance.

The influence of each parameters on the various losses are shown in

Efficiency optimization

The output power of the converter is determined by the load requirement and the efficiency can be maximized. The output power constrains the output impedance as follow:

V max = n m V in -R out I max (3.68) R out = n m V in -V max I max (3.69)
where I max is the maximal load current and V max is the maximal output voltage at I max . The optimization involves to reach the output resistance target while minimizing the power losses. The characteristic of the components (C 0 c , α bot , α top , σ c , C 0 g and σ s ) are determined by the type of selected devices and the design parameters are thus W c , L c , W s and L s . The area constraint is included in the optimization method. The area is often determined by the flying capacitor in fully integrated SC converters. The area available for the capacitors is set as well as the form factor (W c and L c ) for a given capacitor type. Then the switches are selected and L c is set to the minimal possible value. The length of the switches can be increased for ultra low power target to reduce the leakage current and increase the I on /I of f ratio. However the leakage current has a small impact on the efficiency in high power conditions whereas the gate capacitance increases the associated losses. Thus the two design variables, W s and f sw are swept to achieve the highest efficiency for the targeted output power. Different figures of merit are generated using Seeman's framework [START_REF] Seeman | Analysis and Optimization of Switched-Capacitor DC-DC Converters[END_REF][START_REF] Seeman | A Design Methodology for Switched-Capacitor DC-DC Converters[END_REF] to illustrate the optimization trade-off for various flying capacitor specifications. The first figure of merit shown in Fig. 3.17 is the efficiency of the converter versus the area of the flying capacitor for a fixed output current. Each point corresponds to the optimal efficiency achieved for a given switching frequency and a switch width. The highest efficiency is always achieved for the highest area of capacitor for a given specification. The efficiency is here limited by the capacitor parasitic ratio (α top and α bot ). The optimal efficiency decreases when the area decreases and the capacitor density is a major parameter. The second well-known figure of merit 44 Chapter 3. Fundamentals of Switched-capacitor converter presented in Fig. 3.18 is the efficiency versus the power density. The power density is defined as the output power to silicon area ratio. High power density design requires high density capacitors and low ESR values while low power density ones must consider low parasitic ratio values. The efficiency versus the current density value is an alternative to the previous one. The output current is divided by the area and the results are depicted in Fig. 3.19. The corresponding output voltage is added in Fig. 3.20. Finally, the optimal switching frequency and the optimal area of the switches in term of efficiency are given versus area in Fig. 3.21 and Fig. 3.22 respectively. The switching frequency decreases almost linearly with the area. Thus the switching losses are reduced and the width of the switches can be increased to lower the resistive losses. As a consequence, an increase in area benefits the efficiency point of view. However the parasitic ratio limits the efficiency value in this region. As a conclusion regarding area constrained design with high power density, the designer has to choose high capacitor density with low ESR values.

Ripple reduction technique

The inherent charge transfer of a SC converter causes output voltage ripple. The noise of the output voltage could alter the behavior of the powered blocks. An output capacitor is usually used to mitigate the issue. The current in the capacitor is the difference between the instantaneous current delivered by the converter, I out and the instantaneous current consumed by the load, I load . This difference is integrated by the output capacitor over a switching period yielding a voltage ripple. The value of the output voltage ripple is approximated by:

∆V out ∝ I load f sw • C load (3.70)
Where C load is the output capacitor and f sw is the switching frequency. [START_REF] Jain | Distributed Power Conversion -An answer to Power Delivery Challenges in SoCs?[END_REF] has reported that the output voltage ripple value can be improved with proper on-state switch resistance. Fundamentally, the output capacitor value should be increased to reduce the output voltage ripple. However in compact and fully integrated solution, the output capacitor costs an area penalty and this solution is not suitable. Inter-

Efficiency [%] C=5fF/um 2 , ESR=0Ω, α=1% C=20fF/um 2 , ESR=0Ω, α=1% C=20fF/um 2 , ESR=0.5Ω, α=1% C=20fF/um 2 , ESR=0Ω, α=10%
Efficiency [%] C=5fF/um 2 , ESR=0Ω, α=1% C=20fF/um 2 , ESR=0Ω, α=1% C=20fF/um 2 , ESR=0.5Ω, α=1% C=20fF/um 2 , ESR=0Ω, α=10%
] V out [V] C=5fF/um 2 ,
V out = n m • V in -R out (C f ly , f sw , R on , D) • I load (3.71)
Two control strategies come from (3.71): either the converter ratio or output resistance can be adjusted. The reconfiguration of ratio requires multi-ratio topologies and a gear-box with a control to properly choose the ratio [START_REF] Van Breussegem | A fully integrated gearbox capacitive DC/DC-converter in 90nm CMOS: Optimization, control and measurements[END_REF]. This allows only a coarse regulation and it is required in case of wide input/output voltage range.

The converter can operate close to the best ratio to maintain the efficiency as high as possible. The output resistance modulation offers a fine grain regulation capa-bility but it cannot be achieved without any power dissipation. This is identical to linear regulator where the efficiency is limited by the ratio between the output and input voltage. Thus the output resistance modulation is realized through capacitance modulation or frequency modulation when the converter operates in SSL while pulse width modulation or conductance modulation is used in the FSL region.

Capacitance modulation

Capacitance modulation modifies the value of the flying capacitor dynamically. This can be achieved with scalable capacitors. The net value of capacitor is selected by a digital control [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF]. Unfortunately the capacitor value can only be varied with discrete value step. Fine grain regulation is therefore quite complicated. Moreover the switching frequency is kept constant in such control and the switching losses become significant at light load condition.

Frequency modulation

Frequency modulation is a very popular technique. The switching frequency can be varied over a wide range to achieve fine grain regulation. The switching frequency also scales with the load current and the efficiency of the converter can be maintained constant for a given regulated output voltage. Such a regulation in the SSL region implies a proportional dependency of the output voltage ripple to the switching frequency and the load current. Non constant frequency may cause trouble to radio-frequency systems.

Pulse width modulation

Pulse width modulation is widely used in inductive DC-DC converter. This control can be used in the FSL region because the resistive losses are the main contributors to the output resistance losses. This techniques is highly limited to a small range of duty cycle [START_REF] Lim | Control design and closed-loop analysis of a switched-capacitor DC-to-DC converter[END_REF].

Conductance modulation

Conductance modulation is performed playing on the on-state resistance of the switches. As for capacitance modulation scalable switches can be implemented.

The width of the transistors is varied with discrete values [START_REF] Jain | Distributed Power Conversion -An answer to Power Delivery Challenges in SoCs?[END_REF]. An adaptive gate driver is required to achieve continuous regulation [START_REF] Ng | A High-Efficiency Wide-Input-Voltage Range Switched Capacitor Point-of-Load DC:DC Converter[END_REF][START_REF] Jain | A 200mA switched capacitor voltage regulator on 32nm CMOS and regulation schemes to enable DVFS[END_REF]. This techniques has demonstrated good results on the output voltage ripple. The voltage ripple is significantly reduced at light load condition as well [START_REF] Jain | Distributed Power Conversion -An answer to Power Delivery Challenges in SoCs?[END_REF].

The frequency modulation is the most suitable control to fulfill the fine grain wide 50 Chapter 3. Fundamentals of Switched-capacitor converter regulation control and high efficiency requirements. Chapter 4 will detail the implementation of a frequency modulation control.

Small-signal behavior

The frequency response of a converter is essential to understand the input-to-output relation as well as to design a controller. The small-signal model of switched-mode converters is not straightforward. The switching behavior must be described with a discrete system or approximated with a continuous model.

The continuous models are described using the output voltage relation (3.71) and the Laplace block diagram in Fig. 3.24. The input voltage, V in and the output current,

n m 1 R out 1 C load s V out V in I load - - Figure 3
.24: Representation of SC converter dynamics I load are the inputs of the system while the output voltage, V out , is the output. In case of perturbations in the input voltage, the output current contribution is set to zero yielding the audio susceptibility:

vout (s) vin (s) = n m 1 1 + R out C out s (3.72)
Then output impedance is derived when a perturbation is applied to the output current while the input voltage is set to zero:

vout (s) îload (s) = R out 1 + R out C out s (3.73)
The system is a first order type with a pole determined by the output resistance and the output capacitor. The value of R out depends on the operating point. Therefore analysis toolbox. We propose to linearize the sampled-data model around the fixed point solution to derive the small-signal dynamics [START_REF] Fang | Sampled-Data Analysis and Control of DC-DC Switching Converters[END_REF]:

xn+1 ≈ ∂f ∂x n xn + ∂f ∂u n ûn + ∂f ∂τ n τn (3.74) xn+1 ≈ Φ 0 xn + Γ u ûn + Γ τ τn (3.75) ŷn ≈ C xn + Dû n (3.76) with ∂f ∂x n = Φ 0 = N k=1 Φ k (3.77) ∂f ∂u n = Γ u = N -1 k=1   N -k j=2 Φ j   Γ k + Γ N (3.78) ∂f ∂τ n = Γ τ = Γ d 1 Γ d 2 . . . Γ d N -1 Γ T (3.79) = Γ τ = ∂f ∂d 1n ∂f ∂d 2n . . . ∂f ∂d (N -1)n ∂f ∂T n (3.80) ∂f ∂d in = Γ d i = N k=i+1 Φ k (A i -A i+1 ) x 0 (d i ) + (B i -B i+1 ) U (3.81) ∂f ∂T n = Γ T = Φ N A N x 0 (d N -1 ) + B N U (3.82)
The linearized dynamics is derived in discrete time. The input-to-output transfer functions are

y(z) u(z) = C • (zI -Φ 0 ) -1 • Γ u + D (3.83)
The switching instant-to-output transfer functions in z-domain are:

y(z) d i (z) = C • (zI -Φ 0 ) -1 • Γ d i (3.84) y(z) T (z) = C • (zI -Φ 0 ) -1 • Γ T (3.85)
The z-domain transfer functions are useful for discrete control design but the sdomain expression is required for continuous control. The zero-order hold method is suitable since the inputs are assumed to be constant over two sampling instants and the output signal is sampled without band-limiting anti-aliasing filter [START_REF] Fang | Sampled-Data Analysis and Control of DC-DC Switching Converters[END_REF][START_REF] Pagano | Sampled-Data Modeling of Hysteretic Converters Accounting for Intracycle Waveform Propagation[END_REF].

We propose to illustrate the small-signal model derivation for the 2:1 SC converter.

The operating point is defined by a switching frequency of 100 M Hz and a dutycycle of 50% where

x 0 (0) x 0 (d) x 0 (T ) ẋ0 (T + ) ẋ0 (d -) ẋ0 (d + ) ẋ0 (T -)
∂f ∂x n =Φ 0 = Φ 2 Φ 1 (3.89) ∂f ∂u n =Γ u = Φ 2 Γ 1 + Γ 2 (3.90) ∂f ∂d n =Γ d = Φ 2 ( ẋ0 (d -) -ẋ0 (d + )) (3.91) ∂f ∂T n =Γ T = ẋ0 (T -) (3.92)
The expression of Γ d and Γ T are reduced with the expression of the time derivatives of the state-space vector x 0 (t) evaluated at various switching instants. The periodic solution of the state vector is shown in Fig. 3.25 with the derivatives. These expressions will be widely used throughout the thesis to compact the equation expression.

ẋ0 (d -) = A 1 x 0 (d) + B 1 U = Φ 1 A 1 x 0 (0) + B 1 U (3.93) ẋ0 (d + ) = A 2 x 0 (d) + B 2 U (3.94) ẋ0 (T -) = A 2 x 0 (0) + B 2 U = Φ 2 A 2 x 0 (d) + B 2 U (3.95) ẋ0 (T + ) = A 1 x 0 (0) + B 1 U (3.96)
• The audio susceptibility is

T ov (z) = vout (z) vin (z) = E • (zI -Φ 0 ) -1 Γ u 2, * (3.97)
• The output impedance is

T oi (z) = vout (z) îload (z) = E • (zI -Φ 0 ) -1 Γ u 1, * (3.98)
• The switching instant d n to the output voltage transfer function is

T d (z) = vout (z) d(z) = E • (zI -Φ 0 ) -1 Γ d (3.99)

Conclusion

53

• The duty-cycle-to-the output voltage transfer function is

T D (z) = vout (z) D(z) = T d (z) • T (3.100)
• The switching instant T n to the output voltage transfer function is

T T (z) = vout (z) T (z) = E • (zI -Φ 0 ) -1 Γ T (3.101)
• The switching frequency-to-the output voltage transfer function is

T f (z) = vout (z) f (z) = -T T (z) • T 2 (3.102)
The transfer functions obtained by the sampled-data model linearization are second order transfer functions. The components of the state vector are the voltages across the capacitors. Therefore the system has only real poles. The poles of the sampleddata model are given by the Eigenvalues of the sensitivity matrix, Φ 0 (parameters are listed in Table 3.1):

λ 1 = 9.1249 • 10 -12 ≈ 0 (3.103) λ 2 = 0.9231 (3.104)
The value of λ 1 is close to zero and the system can be reduced to a first order system with the eigenvalue, λ Frequency modulation: controller implementation On-off control scheme is often the method that comes to mind in SC converter context. The converter operates with a high switching frequency when the output voltage is lower than the reference voltage. Then it is turned-off when the output voltage raises above the reference voltage but this technique is not as good as it seems. First an hysteresis band must be introduced to avoid chartering behavior. This contributes to increase the output voltage ripple. Second a small output capacitor yields fast charging that can increase the chartering behavior. Last but definitely not least, the hopping between OFF and ON mode does not track the optimal efficiency. The efficiency is not a linear law with respect to the switching frequency except in the SSL region. Unfortunately, the ON-mode is in the FSL region, i.e. high switching losses. Despite that, good hysteretic controls have been reported. The single bound approach is the most essential. This technique is illustrated in Section 4.1. Frequency modulation has also been explored with a linear approach. As an example a voltage controlled oscillator is used to tune the switching frequency of the SC converter [START_REF] Breussegem | A 82% efficiency 0.5% ripple 16-phase fully integrated capacitive voltage doubler[END_REF]. Combined with a burst mode, a fast response can be achieved [START_REF] Le | A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm 2 at 73% efficiency[END_REF]. In [START_REF] Samir | A 90-nm CMOS high efficiency on chip DC-DC converter for ultra-low power low cost applications[END_REF] a SC converter is cascaded with a low-drop-out regulator. Optimal control law is also proposed through a combination of FM 1 and a pulse width modulation [START_REF] Ling | Combined optimal pulse width modulation and pulse frequency modulation strategy for controlling switched mode DC-DC converters over a wide range of loads[END_REF]. The design of a linear frequency modulation with a voltage loop is proposed in Section 4.2. The burst mode technique is dismissed because it yields an unexpected and unpredictable behavior. An extra current feedback loop is proposed in Section 4.3. Finally, as suggested in [START_REF] Van Breussegem | Monolithic Capacitive DC-DC Converter With Single Boundary Multiphase Control and Voltage Domain Stacking in 90 nm CMOS[END_REF] but not deeply analyzed,

Conclusion

Single bound hysteretic control

The single bound hysteretic control or also called the lower bound hysteretic control has been patented by Intel [START_REF] Michael Seeman | Single-bound hysteretic regulation of switchedcapacitor converters[END_REF]. This control is depicted in Fig. 4.1. The output voltage raises. This mechanism is well described in [START_REF] Van Breussegem | Monolithic Capacitive DC-DC Converter With Single Boundary Multiphase Control and Voltage Domain Stacking in 90 nm CMOS[END_REF]. The sampling frequency is chosen much higher than the maximal steady-state switching frequency otherwise subharmonics oscillations may occur. Furthermore the ripple frequency increases with the interleaving factor. The sampling frequency may become very large with interleaved converter. The steady-state criterion proposed in [START_REF] Jain | A 200mA switched capacitor voltage regulator on 32nm CMOS and regulation schemes to enable DVFS[END_REF] is:

D Q D Q D Q D Q Φ 0 Φ 1 Φ 2 Φ 3 clk - + v out (t) V ref
Φ 3 Φ 2 Φ 1 Φ 0 clk
T delay < T clk < T ripple (4.1)
where T delay is the delay between the output of the comparator and the next charge injection into the output node (i.e. the propagation time), T clk is the sampling period and T ripple is the maximum period of the voltage ripple. The latch sense amplifier saves static power consumption over a simple comparator but the dynamic power consumption can be high in case of high sampling rate.

The single bound control is tested on the 2:1 SC converter. The sampling frequency The single bound hysteretic control has been successfully implemented in [START_REF] Andersen | A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at Chapter References 90% efficiency using deep-trench capacitors in 32nm SOI CMOS[END_REF][START_REF] Jain | A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS[END_REF][START_REF] Van Breussegem | Monolithic Capacitive DC-DC Converter With Single Boundary Multiphase Control and Voltage Domain Stacking in 90 nm CMOS[END_REF].

However during a load transient, the switching frequency of the converter is very high and the switching losses are significant when the recovery time is important (around 200 ns in [START_REF] Andersen | A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at Chapter References 90% efficiency using deep-trench capacitors in 32nm SOI CMOS[END_REF]).

Linear frequency modulation with a voltage loop

The linear frequency modulation with a voltage loop is depicted in Fig. Voltage sensor

V ref V err V out -
f osc V ctrl f 0 f min f max V max V min
f osc (t) = K vco • V ctrl (t) + f 0 (4.2)
The output frequency,

f
V ctrl -to-f osc is fosc (s) vctrl (s) = K vco (4.4)
The power stage linearization is performed using the sampled-data model in Section 3.6.2. The linearization requires the computation of an operating point (fixed point).

The operating point is usually the targeted output voltage and we can write:

Ex 0 (0) -V target = 0 (4.5)
The fixed-point solution x 0 (0), U, (d, T ) , is determined by solving the set of equation (3.44) and (4.5). The so-called Trust-Region Dogleg algorithm [START_REF] Nocedal | Numerical Optimization[END_REF] gives

x 0 (0) = 0.6022 0.6 (4.6)

d = 3.1824 • 10 -8 (4.7) T = 6.3649 • 10 -8 (4.8)
Then the system is linearized around the fixed point to build the transfer functions of the plant. The switching frequency-to-the output voltage transfer function exhibits one pole yielding a transfer function of the plant as:

H(s) = G 0 1 + τ 0 s (4.9)
Where G 0 is the static gain depending on K vco and τ 0 , the time constant of the plant. The pole is 1 /τ 0 and τ 0 is equal to R out • C load where R out is the static output resistance and C load , the output capacitor.

The first order behavior of the plant calls for a proportional-integral (PI) compensator. The transfer function is:

C(s) = K p • 1 + 1 T i s (4.10)
K p is the proportional gain and T i is the time integral constant. Then the open-loop transfer function, L o (s), is established:

L o (s) = C(s) • H(s) = K p (1 + T i s) T i s • G 0 1 + τ 0 s (4.11)
as well as the closed-loop L c (s):

L c (s) = 1 + T i s 1 + T i 1 + 1 G 0 • K p s + τ 0 • T i G 0 • K p s 2 (4.12)
Linear frequency modulation with a voltage loop 63

In case of a closed-loop first order behavior, the denominator of the plant is simplified by the numerator of the compensator in (4.11). Let 1 + T i s = 1 + τ 0 s, the open loop is now:

L o (s) = K p • G 0 T i • s (4.13)
and the associated closed-loop, L c (s) is:

L c (s) = 1 1 + T i K p • G 0 s = 1 1 + τ c s (4.14)
Where

τ c = T i K p • G 0
is the time-constant giving the closed loop behavior. The controller parameters are then :

K p = τ 0 G 0 • τ c (4.15) T i = τ 0 (4.16)
The integration constant, T i , is equal to the time-constant of the system, τ 0 . The gain, K p , is chosen regarding the desired closed-loop time-constant, τ c .

In case of a second order closed-loop behavior, (4.12) is expressed with the undamped angular frequency, ω 0 and the damping factor ζ 0 .

L c (s) = 1 + T i s 1 + 2 • ζ 0 • s ω 0 + s 2 ω 2 0 (4.17)
The compensator set two poles in the closed-loop. The identification of the denominators in (4.12) and (4.17) gives

ω 2 0 = G 0 • K p τ • T i (4.18) 2 • ζ 0 ω 0 = T i • 1 + 1 G 0 • K p (4.19)
The undamped angular frequency, ω 0 , sets the time response while the damping ratio, ζ 0 , dictates the overshoot in the case of a step response. Finally the PI2 parameters are expressed with G 0 and τ 0 and the feedback requirements, ω 0 and ζ 0 :

T i = 2 • ζ 0 • ω 0 • τ 0 -1 ω 2 0 • τ 0 (4.20) K p = ω 2 0 • T i • τ 0 G 0 (4.
•ω 0 ≥ 1 2 • τ 0
. As a starting point, ω 0 can be chosen equal to the inverse of the plant timeconstant, τ 0 . The dynamic speed is increased with ω 0 until the system saturates.

Regarding ζ 0 , a small overshoot is achieved with ζ 0 = 0.7 and no overshoot comes with ζ 0 ≥ 0.9.

A voltage loop control is designed for the 2:1 SC converter as an illustrative example.

The reference voltage is Finally the sampled-data dynamics is linearized around the fixed-point and the various transfer functions are computed in z-domain and expressed in s-domain.

V ref = 0.6 V
The transfer function of the plant including the VCO is thus:

H(s) = G 0 1 + τ 0 s = 2.57 7.95 • 10 -7 s + 1 (4.22)
A second order behavior is set with ζ = 0. Sampled-data modeling has been extensively used to offer a comprehensive stability analysis against an averaged approach. Subharmonic oscillations and other bifurcations can occur. These bifurcations can be predicted with sampled-data model where the averaged approach fails [START_REF] Fang | Sampled-Data Analysis and Control of DC-DC Switching Converters[END_REF]. This is primarily because the sampled-data model yields a periodic solution depending on the switching instants while the average model has a continuous solution. The stability analysis requires to build the closed-loop model using sampled-data modeling. The stability is checked from the Eigenvalues of the sensitivity matrix. The system is asymptotically stable if all the Eigenvalues are inside the unit circle [START_REF] Khalil | Nonlinear Systems[END_REF].

The sampled-data modeling approach of a frequency-modulation control is applied to the SC converter. The operation of the SC converter is considered within a cycle [t n , t n + T n ]. The duration of the nth-cycle is T n which is the instantaneous switching period of the converter. The instantaneous switching frequency is then f n = 1/T n . We assume that the inputs are constant over a cycle and perturbations are introduced at the beginning of a cycle. Due to the discrete operation, the switching instants in the coming cycle are considered to be determined at t = t n , the beginning of the cycle. The state-space representation of each states of the converter including the controller is:

S 1 :        ẋ = A 1 x + B 1 u v err = Cx + Du v out = Ex for t ∈ [t n , t n + d n ] (4.24) S 2 :        ẋ = A 2 x + B 2 u v err = Cx + Du v out = Ex for t ∈ [t n + d n , t n + T n ] (4.25)
Where v err is the error signal driving the VCO. During a cycle, the VCO delivers a square wave, with a 50% duty cycle. As a consequence the switching instant d n is the half of the switching period T n . The VCO continuous time-domain model is

f sw (t) = K vco • V err (t) + f 0 (4.26)
Sampling (4.26) at the beginning of each cycle yields the discrete time-domain operation of the VCO

f sw (t n ) = K vco • v err (t n ) + f 0 (4.27) f n = K vco • v err (t n ) + f 0 (4.28)
The switching instants d n and T n are then determined by the following expressions :

T n = 1 K vco • v err (t n ) + f 0 (4.29) d n = 0.5 K vco • v err (t n ) + f 0 (4.30)
Reciprocally the error signal, v err at the beginning of the cycle can be expressed as

a function of T n v err (T n ) = h(T n ) = 1 T n • K vco - f 0 K vco (4.31)
and we have

V err (t n ) = Cx(t n ) + Du n (4.32)
We can establish the constraint function that determine the switching instant from (4.31) and (4.32)

g (x n , u n , τ n ) = Cx n + Du n -h(T n ) = 0 (4.33)
and the sampled-data dynamics is

x n+1 = f (x n , u n , τ n ) (4.34) = Φx n + Γu n (4.35) v outn = Ex n (4.36)
The dynamics is constrained by (4.33) and the steady-state operation of the SC converter with FM control is reached when the averaged output voltage value is equal to the reference voltage. The solution is a periodic orbit and the fixed-point in the sampled-data dynamics is

x 0 (0) = f (x 0 (0), U, τ ) (4.37) g(x 0 (0), U, τ ) = 0 (4.38)
Finally the fixed point solution,

x 0 (0), U, (d, T ) is
Γ u = ∂f ∂u n - ∂f ∂τ n ∂g ∂τ n -1 ∂g ∂u n (4.44) ∂f ∂x n = Φ 2 Φ 1 (4.45) ∂f ∂u n = Φ 2 Γ 1 + Φ 1 (4.46) ∂f ∂τ n = Φ 2 ( ẋ0 (d -) -ẋ0 (d + )) ẋ0 (T -) (4.47) ∂g ∂x n = CΦ 2 Φ 1 (4.48) ∂g ∂u n = C (Φ 2 Γ 1 + Φ 1 ) + D (4.49) ∂g ∂τ n = CΦ 2 ẋ0 (d -) -ẋ0 (d + ) C ẋ0 (T -) -ḣ (4.50)
The closed-loop model is determined for the frequency modulation with a PI controller. The ideal controller can be included in the state-space representation with the following relation:

verr (s) vref (s) -vout (s) = verr (s) ˆ (s) = K p (1 + 1 T i s ) (4.51)
However some practical mathematical problems occur when the fixed point is solved. The integral term is infinite except in steady-state. Since the algorithm tries to find the steady-state solution by iteration the state of the controller cannot be determined a priori. The integral term must have a finite value to let find solution. This is always the case in practice because the controller saturates. One way

verr (s) ˆ (s) = k 0 • s + z 0 s + p 0 (4.52)
For the ideal PI control, we have k 0 = K p T i , z 0 = 1 T i and p 0 = 0. We introduce a value limiting the integral value, A 0 so that

k 0 = A 0 K p 1 + A 0 + K p (4.53) z 0 = 1 T i (4.54) p 0 = K p T i 1 1 + A 0 + K p (4.55)
The value of A 0 is set to 1000, K p and T i have the value previously calculated. The ideal and the non-ideal PI controllers are compared in Fig. 4.12. The DC gain is limited to A 0 , 60 dB in the Bode diagram. The higher gain the lower the static error. The state-space for the 2:1 SC converter with the non-ideal PI controller

where τ 1 = R on C f ly and τ 2 = R on C load and x c the state of the controller, is:

A 1 =         -1 2τ 1 -1 2τ 1 0 -1 2τ 2 -1 2τ 2 0 0 p 0 -z 0 -p 0         , A 2 =         -1 2τ 1 1 2τ 1 0 1 2τ 2 -1 2τ 2 0 0 p 0 -z 0 -p 0         B 1 =         0 1 τ 1 0 -1 C load 1 2τ 2 0 0 0 z 0 -p 0         , B 2 =        0 0 0 -1 C load 0 0 0 0 z 0 -p 0        E = 0 1 0 , C = 0 -k k , D = 0 0 k U =    I load V in V ref    , x =    v C f ly v C load x c    , τ = d T
The determinant of the matrices A i are:

det[A 1 ] = -1 2τ 1 • -1 2τ 1 • -p 0 - -1 2τ 1 • -1 2τ 1 • -p 0 = 0 (4.56) det[A 2 ] = -1 2τ 1 • -1 2τ 1 • -p 0 - 1 2τ 1 • 1 2τ 1 • -p 0 = 0 (4.57)
The matrices are singular and the Jordan form decomposition may be used. The fixed-point solution x 0 (0), U, (d, T ) , is determined solving the set of equation λ 2 = 0.9508 + 0.0605i

λ 3 = 0.9508 -0.0605i
The system is reduced to a second order system because λ 1 is close to zero. The eigenvalues λ 2 and λ 3 are conjugate and inside the unit circle. The system is thus asymptotically stable. We can analyze the robustness of the system using the unit circle and the margin stability definition. The unit circle with constant damping factors lines and natural frequency lines is depicted in Fig. 4.15. For illustration purpose, two areas are defined: one area delimits the location where the poles have a higher angular frequency than 0.2π/T and an other location where the poles have a damping factor above 0.6. The intersection of the two surfaces is the dark gray area where the design point will fulfill both specifications. Sensitivity analysis to the reference voltage is performed first and the results are presented in Fig. 4.16. The lowest value of V ref gives an eigenvalue with the fastest frequency but with also the lowest damping factor. When the voltage reference increases the Eigenvalues move toward low frequencies and the real axis. The system has a first order behavior for V ref = 0.75 V and V ref = 0.8 V . Therefore the stability is improved but the system is slower. Then a similar analysis is performed against the load current variation in Fig. 4.17. As well as for the voltage reference variation, the lowest load current yields a fast eigenvalue with a low damping factor. This is the worst case in term of stability margin while the highest current value gives a first order system.

The reactivity and the stability cannot be achieved at the same time for different operating points. If the controller is designed for the worst case (lowest current and lowest reference voltage values), the controller will always fulfill the damping factor requirement but the bandwidth will always be small. Finally the robustness is analyzed for controller parameter variations of ±20% in Fig. 4.18. The bandwidth of the system is maintained when the parameter values vary in the same way. The worst case of damping factor is determined when ∆T i = -20% while K p impact the Eigenvalue frequency.

.8 0.9 1 -0.2 -0.1 0 0.1 0.2 ζ=0.6 ω=ω 0 V ref =0.3 V V ref =0.35 V V ref =0.4 V V ref =0.45 V V ref =0.5 V V ref =0.55 V V ref =0.6 V V ref =0.65 V V ref =0.7 V V ref =0.75 V V ref =0.8 V
∆T i =-20%, ∆K p =-20% ∆T i =0%, ∆K p =-20% ∆T i =20%, ∆K p =-20% ∆T i =-20%, ∆K p =0% ∆T i =0%, ∆K p =0% ∆T i =20%, ∆K p =0% ∆T i =-20%, ∆K p =20% ∆T i =0%, ∆K p =20% ∆T i =20%, ∆K p =20%
V ref V err V ctrl V out I out -
F (s) = V sens (s) I out (s) = G sens R shunt 1 + τ s (4.61)
The behavior of the current loop is analyzed using the diagram of Fig. 3.24. The output resistance of the converter is modeled using the non-linear average model in Linear frequency modulation with voltage and current loops 79

S 1 S 2 S 3 S 4 C f ly R shunt V out C load V in
R out = 1 4f sw C f ly • coth 1 8R on f sw C f ly + R shunt (4.62)
This model is implemented and simulated in Matlab/Simulink. The operating point is found for the targeted output voltage, V target = 0.6 V and the load current,

I load = 5 mA with: R out (f sw ) - 0.5V in -V target I load = 0 (4.63)
The non-linear averaged model is linearized around this operating point and the small-signal block diagram is shown in Fig. 4. [START_REF] Tschanz | Adaptive body bias for reducing impacts of die-to-die and withindie parameter variations on microprocessor frequency and leakage[END_REF]. The open-loop expression is therefore:

H open (s) = K vco • H f i (s) • F (s) (4.64) = K vco • as s + b • G sens R shunt 1 + τ s (4.65)
The transfer function of the control voltage, V ctrl , to the switching frequency, f sw , is now:

H cf (s) = K vco 1 -H open (s) (4.66)
The stability of the system is checked looking to H open (s). This transfer function is a bandpass filter like as shown in Fig. 4.22. The value of the bandwidth is defined by

B w = b - 1 τ
and the gain value is K vco G sens R shunt a. Therefore the time constant of the filter, τ , must be higher than the time constant of the converter, 1/b. Otherwise 80 Chapter 4. Frequency modulation: controller implementation As a consequence the system will be stable in closed loop if the gain in H open is less than 0dB, i.e. K vco G sens R shunt a < 1. The control-to-switching frequency transfer function is:

V ctrl K vco V osc H f i H f v f sw F F G V sens Z o I load V out
H cf (s) = K vco • τ s 2 + (1 + τ b)s + b τ s 2 + (bτ -G sens K vco R shunt a + 1)s + b (4.67)
The system thus behaves like the VCO in low and high frequency. The frequency response of H cf is shown in Fig. 4.23. The switching frequency also depends on the load current. The transfer function of the load current-to-the switching frequency is:

H if (s) = G(s) • F (s) • H cf (s) (4.68)
The results are plotted in Fig. The control-to-output voltage transfer function shown in Fig. 4.25 is a second order type with a zero:

H cv (s) = H cf (s) • H f v (s) (4.69) = K vco • G 0 • s + 1 τ (s + b) s 2 + bτ -GsensKvcoR shunt a+1 τ s + b τ (s + b) (4.70) = K vco • G 0 • s + 1 τ s 2 + bτ -GsensKvcoR shunt a+1 τ s + b τ (4.71)
No resonance is visible in the Bode diagram in Fig. 4.25 and the decomposition of the denominator of (4.71) gives the damping factor, ζ 0 and the natural angular frequency, ω 0 :

ζ 0 = bτ -G sens K vco R shunt a + 1 τ • √ b 2 √ τ (4.72) ω 0 = b τ (4.73)
The evaluation of the damping factor is 1.06 and the system can be decomposed with two separate real poles due to over-damping:

H cv (s) = K vco • G 0 • s + 1 τ (s + p 1 ) (s + p 2 ) (4.
p 1 = ζ 0 + ζ 2 0 -1 • ω 0 (4.75) p 2 = ζ 0 -ζ 2 0 -1 • ω 0 (4.76)
Several compensation strategies are possible depending on the targeted closed-loop behavior. A PID implementation can be used to simplify the denominator of the plant transfer function by the numerator of the corrector and to set a second order behavior. When the frequency of the zero of the plant is much larger than the natural angular frequency of the plant, a simple PI can be used. Finally if the desired crossover frequency is set to a lower value than the one of the dominant pole of the plant, an integrator can achieve enough phase margin.

H open (s) = K vco • G 0 • K p • s + 1 τ s + 1 T i (s + p 1 ) (s + p 2 ) s (4.77)
We can simplify the dominant pole, p 2 by the zero of the corrector with

T i = 1 p 2 yielding: H open (s) = K vco • G 0 • K p • s + 1 τ (s + p 1 ) s (4.78)
The value of K p is now determined either by the open-loop phase margin or by the closed-loop behavior.

• The phase margin can be expressed as a function of the crossover frequency, ω 0dB , itself depending on K p :

ω 0dB (K p ) = √ 2 2 p 2 1 -(βK p ) 2 + p 2 1 + (βK p ) 2 2 + 2 βK p τ 2 (4.79) with β = K vco G 0 .
Then the phase margin is a function of ω 0dB (K p ):

P M (ω 0dB ) = 90 -arctan ω 0dB p -1 -arctan (ω 0dB τ ) • 180 π (4.80)
By injecting (4.79) into (4.80) we obtain the phase margin as a function of

K p .
• The damping factor is determined by the closed-loop:

H closed (s) = K vco G 0 K p s + 1 τ s 2 + (K vco G 0 K p + p 1 )s + KvcoG 0 Kp τ (4.81)
and the damping factor is a function of

K p ζ 0 (K p ) = K vco G 0 K p + p 1 2 KvcoG 0 Kp τ (4.82)
The phase margin and damping factor versus K p are plotted in Fig. 4.27 and

Sliding-mode with loop-delay modulation

Sliding mode controls are non-linear controls well known for their robustness and dynamic performances. Recently sliding-mode controls have been successfully introduced in inductive DC-DC converters because the switching control law can directly drive the power stage [START_REF] Tan | An Evaluation of the Practicality of Sliding Mode Controllers in DC-DC Converters and Their General Design Issues[END_REF][START_REF] Labbe | An Integrated Sliding-Mode Buck Converter With Switching Frequency Control for Battery-Powered Applications[END_REF]. Sliding-mode control operates at variable switching frequency by nature. This could be harmful to EMI sensitive load as RF circuits and switching frequency regulation has been introduced to address this issue. Sliding-mode control can thus be proposed for SC converters. To understand how sliding-mode can be applied to SC converters, let's analyze the voltage across the flying capacitor in a 2:1 SC converter. The steady-state operation is depicted in Fig. 4.33. The flying capacitor is ideally charged to V in -V out and ideally discharged to V out with exponential behavior. At the beginning of the charging phase, the voltage across the flying capacitor is V min . The capacitor charges to

V in -V out yielding V out V min V max V in -V out V in 2 0 T 2 T 3T 2
f ly (t) = V in -V out + (V min -V in + V out )e -t/(2RonC f ly ) (4.83)
Then the system switches to the discharging phase at t = T /2. The initial voltage across the flying capacitor is V max . The capacitor is thus discharged to V out . The cycle finishes at t = T and the voltage across the flying capacitor is now V min . The equation of the voltage is

V (2) f ly (t) = V out + (V max -V out )e -(t-T /2)/(2RonC f ly ) (4.84)
Due to the continuity of the voltage across the flying capacitor, in steady-state, we can write

V (1) f ly (1/(2f sw )) = V max (4.85) = V in -V out + (V min -V in + V out )e -1/(4fswRonC f ly ) (4.86) 90
Chapter 4. Frequency modulation: controller implementation

V (2) f ly (1/f sw ) = V min (4.87) = V out + (V max -V out )e -1/(4fswRonC f ly ) (4.88)
The voltage ripple across the flying capacitor is ∆ V = V max -V min . (4.86) and (4.88) yields

∆ V (f sw ) = (V in -2V out ) 1 -e -1/(4fswRonC f ly ) 1 + e -1/(4fswRonC f ly ) (4.89)
The flying capacitor voltage ripple is null when the converter operates at very high switching frequency. Let's compute the averaged voltage value across the flying capacitor during steady-state operation:

V f ly = 1 T T /2 0 V (1)
f ly dt + T T /2 V ( 2
)
f ly dt (4.90) = 1 T T V in 2 + 2R on C f ly (1 -e (T /(4RonC f ly )) )(V max + V min -V in ) (4.91)
from (4.86) and (4.88)

V max + V min = V in (4.92)
Thus (4.91) is

V f ly = V in 2 (4.93)
The averaged voltage value across the flying capacitor in steady-state does not depend on the switching frequency. We propose a sliding -mode control based on this statement. The SC converter and its variable state-space structure is represented in Fig. 4.34 with an hybrid automaton. State 1 corresponds to the charging phase and State 2 the discharging phase. The automaton switches from the charging phase to the discharging phase when the voltage across the flying capacitor is above V in 2 and return to the charging phase when this voltage is bellow

V in 2 .
The converter motion is thus described by the following switching condition:

g(x) = x 1 - V in 2 (4.94)
where x 1 is the voltage across the flying capacitor. The system is constrained on a surface in the state space, the sliding surface, g(x). Considering the switching behavior, the system dynamics is represented by: are derived from the state-space representation where x is the state-space vector,

ẋ =    f 1 (x) if g(x) < 0 f 2 (x) if g(x) > 0 (4.95) ẋ = f 1 (x) ẋ = f 2 (x) g(x) > 0 g(x) < 0
x 1 is the voltage across the flying capacitor and x 2 the voltage across the output capacitor:

f 1 (x) = - x 1 2C f ly R on - x 2 2C f ly R on + V in 2C f ly R on (4.96) f 2 (x) = - x 1 2C f ly R on + x 2 2C f ly R on (4.97) Since ∂g ∂x = 1, it comes ∂g ∂x f 1 (x) = f 1 (x) (4.98) ∂g ∂x f 2 (x) = f 2 (x) (4.99)
The sliding motion implies for g(x) < 0

f 1 (x) > 0 (4.100) - x 1 2C f ly R on - x 2 2C f ly R on + V in 2C f ly R on > 0 (4.101) V in -x 1 -x 2 > 0 (4.102) x 1 + x 2 < V in (4.103)
and for g(x) > 0

f 2 (x) > 0 (4.104) - x 1 2C f ly R on + x 2 2C f ly R on < 0 (4.105) 92
Chapter 4. Frequency modulation: controller implementation

x 2 -x 1 < 0 (4.106) x 2 < x 1 (4.107)
These conditions are systematically verified during the operation of the converter because the output voltage is lower than the flying capacitor voltage and their sum is lower than the input voltage. The switching dynamics is now

ẋ =          f 1 (x) if g(x) < 0 f s (x) if g(x) = 0 f 2 (x) if g(x) > 0 (4.108)
Regularization of the sliding mode implies to find the continuous vector function f s such that the state trajectory remains on the switching surface. The application of the Filippov's continuation method [START_REF] Utkin | Sliding Modes in Control Optimization[END_REF] gives

f s = αf 1 + (1 -α)f 2 (4.109) α ∈ [0, 1] : ∂g ∂x f s = 0 (4.110) with α = ∂g ∂x f 2 ∂g ∂x (f 1 -f 2 ) = x 1 -x 2 V in -2x 2 (4.111) 1 -α = ∂g ∂x f 1 ∂g ∂x (f 1 -f 2 ) = V in -x 1 -x 2 V in -2x 2 (4.112)
and

∂g ∂x f s = f s (4.113) = x 1 -x 2 V in -2x 2 V in -x 1 -x 2 2C f ly R on + V in -x 1 -x 2 V in -2x 2 x 2 -x 1 2C f ly R on (4.114) = 0 (4.115)
The hybrid automaton with the induced mode is given in Fig. 4.35. The switching frequency of the sliding mode control is infinite. However the delay of the loop limits the frequency value in practice. Since the switching frequency is very high the converter will operate in the FSL region. The output voltage will be closed to the ideal conversion ratio for small value of load current. The switching frequency of the sliding mode must be regulated to allow output voltage regulation. The switching frequency can be regulated with a controllable delay. This is called loopdelay modulation. Another technique is based on the ripple of the flying capacitor The error signal is provided to a compensator to set the proper delay in the loop.

ẋ = f s (x) ẋ = f 1 (x) ẋ = f 2 (x) g = 0 g < 0 g < 0 g = 0 g < 0 g > 0
The controllable delay is modeled by a linear function

φ(t) = K φ • V ctrl + φ 0 (4.116)
where K φ is the gain of the delay cell and φ 0 corresponds to the minimum delay when the control voltage, V ctrl is null. Sampled-data modeling is used to determine the frequency response of the loop to a change in the loop-delay. The sliding motion imposes an infinite switching frequency and the switching instants are now determined by the delay of the loop. The dynamics over a state S i from (3.31) including the loop delay, φ is

x i (t, φ) = Φ i x 0 + Γ i u (4.117) with Φ i = e (A i φ) and Γ i = [e (A i φ) -I]A -1 i B i .
The sampled-data model is built and linearized around a fixed point as in Section 3.6.2. The small-signal dynamics is 94 Chapter 4. Frequency modulation: controller implementation

- + V f ly (t) V in 2 SC converter V f ly (t) V out (t) - PI V ref Figure 4
= Φ 0 = Φ 1 Φ 2 (4.121) ∂f ∂u n = Γ 0 = Φ 2 Γ 1 + Φ 2 (4.122) ∂f ∂φ n = Φ 2 (A 1 + A 2 ) x 0 (d) + (B 1 + B 2 ) U (4.123)
The transfer function of the loop-delay-to-output voltage is

v out (z) φ(z) = C • (zI -Φ 0 ) -1 • Γ φ ( 4
H(s) = K delay • v out (s) φ(s) = G 0 1 + τ 0 s (4.126)

Sliding-mode with comparator hysteresis band

The chattering effect of sliding mode can be addressed introducing an hysteresis band at the comparator output instead of a controllable delay. The control is redefined as follows

ẋ =    f 1 (x) if g(x) < -k f 2 (x) if g(x) > +k (4.127)
The value of k set the hysteresis band. The converter operates in the charging phase when g(x) < -k and in the discharging phase when g(x) > +k. As a consequence no switching occurs in the region -k < g(x) < +k and the converter remains in the previous state. The switching frequency is therefore defined by the hysteresis band.

The relation between the switching frequency and the hysteresis band is developed in [START_REF] Utkin | Sliding Modes in Control Optimization[END_REF]. The operation of the sliding mode is represented in Fig. 4.39. The duration

g(x) = 0 f 2 (x) f 1 (x) g(x) = +k g(x) = -k f 1 ∆t 1 f 2 ∆t 2 ∆x Figure 4
.39: Diagram of the sliding mode operation with an hysteresis band of the vector f 1 to move from the lower bound to the upper bound is ∆t 1 . In the Sliding-mode with comparator hysteresis band 97 same way, ∆t 2 is the duration of the vector f 2 to move from the upper bound to the lower bound. As demonstrated in [START_REF] Utkin | Sliding Modes in Control Optimization[END_REF] with ∇g = ∂g ∂x :

∆t 1 = 2k ∇g • f 1 = -4R on C f ly k x 1 + x 2 -V in (4.128) ∆t 2 = -2k ∇g • f 2 = -4R on C f ly k x 1 -x 2 (4.129)
The average velocity in the sliding mode is given by

f 0 = ∇g • f 1 ∇g • (f 1 -f 2 ) f 1 - ∇g • f 1 ∇g • (f 1 -f 2 ) f 2 (4.130) = - (x 1 -x 2 )(x 1 + x 2 -V in ) R on C f ly (V in -2x 2 ) (4.131)
At the equilibrium f 0 = 0 therefore

f 0 = 0    x 1 = y, x 2 = y if g(x) = -k x 1 = V in -y, x 2 = y if g(x) = +k (4.132)
Thus for a given value of k, the value of the flying capacitor, V f ly is equal to the output voltage, V out near g(x) = -k and to V in -V out near g(x) = +k. At the end of each cycle, the output voltage reaches the value y demonstrating that the output voltage can be set despite a constraint on the flying capacitor voltage. The durations ∆t 1 and ∆t 2 are expressed as

∆t 1 = 4R on C f ly k V in -2y (4.133) ∆t 2 = 4R on C f ly k V in -2y (4.134)
The instantaneous switching frequency is respectively. The output voltage is stabilized around 0.6 V after the reaching mode.

f sw = 1 ∆t 1 + ∆t 2 = V in -2y 8R on C f ly k (4.135) If k = 0,
In case of a small step of load current a very small undershoot is visible. However in the case of a larger step, an undershoot is visible and the output voltage exhibits a static error. The sliding mode is based on the flying capacitor voltage. When 98 Chapter 4. Frequency modulation: controller implementation We propose to use the sampled-data modeling to build the small-signal behavior of the control loop.

- + V f ly (t) V in 2 SC converter V f ly (t) V out (t) + - V ref
Let's consider the dynamics of the converter within the n-th cycle. The cycle duration is the switching period T n . The switching instants between the charging and discharging phases is denoted t n + d n and the switching instant between the discharging and charging phase is denoted t n + T n . The dynamics is given by the state-space model:

S 1 :        ẋ = A 1 x + B 1 u v out = Ex v f ly = Cx for t ∈ [t n , t n + d n ] (4.136) S 2 :        ẋ = A 2 x + B 2 u v out = Ex v f ly = Cx for t ∈ [t n + d n , t n + T n ] (4.137)
The switching instants are constrained by the hysteresis band and the sliding surface as follow

v f ly (t n + d n ) = Cx(t n + d n ) = V in 2 + k (4.138) v f ly (t n + T n ) = Cx(t n + T n ) = V in 2 -k (4.139)
The sampled-data model is constructed by sampling the state x at t n :

x n+1 = f (x n , u n , τ n ) ( 4
v outn = Ex n (4.142) v f lyn = Cx n (4.143)
The constraint equations are

g (x n , u n , τ n , k n ) = v f ly (t n + d n ) -V in 2 -k v f ly (t n + T n ) -V in 2 + k (4.144) = Cx(t n + d n ) -V in 2 -k Cx(t n + T n ) -V in 2 + k (4.145) = 0 (4.146)
The fixed point is now x 0 (0), U, (d, T ) , k and satisfies

x 0 (0) = f x 0 (0), U, (d, T ) (4.147) g x 0 (0), U, (d, T ) , k = 0 (4.148)
The fixed point is determined for a targeted output voltage with Ex 0 (0) -V target = 0 (4.149)

The equations (4.147), (4.148) and (4.149) are solved for a given value of U using the Levenberg-Marquardt algorithm implemented in Matlab. The solutions are:

x 0 (0) = 0.6022 0.6 (4.150)

d = 3.
∂f ∂x n = Φ 2 Φ 1 (4.161) ∂f ∂u n = Φ 2 Γ 1 + Φ 1 (4.162) ∂f ∂τ n = Φ 2 ( ẋ0 (d -) -ẋ0 (d + )) ẋ0 (T -) (4.163) ∂f ∂k n = 0 (4.164) ∂g ∂x n = CΦ 1 CΦ 2 Φ 1 (4.165) ∂g ∂u n = CΓ 1 C (Φ 2 Γ 1 + Φ 1 ) - 0 0.5 0 0.5 (4.166) ∂g ∂τ n = C ẋ0 (d -) 0 CΦ 2 ẋ0 (d -) -ẋ0 (d + ) C ẋ0 (T -) (4.167) ∂g ∂k n = - 1
+1 (4.168)
The stability of the system is checked looking at Eigenvalues of Φ 0 :

eig[Φ 0 ] = 0.0118 0 (4.169)
The system is thus a first order system with an Eigenvalue module of 0.0118.

This value is closed to zero leading to a fast transient behavior. The control-tooutput voltage transfer function as well as the audio susceptibility and the output impedance are derived in the z-domain from (4.157)

T oc (z) = vout (z) k(z) = E(zI -Φ 0 ) -1 Γ k ( 4
T oi (z) = vout (z) îload (z) = E(zI -Φ 0 ) -1 Γ u 1, * (4.171)
T ov (z) = vout (z) vin (z) = E(zI -Φ 0 ) -1 Γ u 2, * (4.172)
Then the transfer functions are expressed in s-domain using the Zero Order hold Sliding mode control with hysteresis window modulation demonstrates good performances but the linear loop introduced to cancel the static error modifies the startup behavior and saturates the loop. An anti-windup is a possible solution to deal with the error accumulation during saturation. A lower integration time constant could help but the transient behavior would be slower. Moreover the sliding surface is defined for V in /2 but it is usually implemented with a voltage reference. If this voltage reference is inaccurate the charging and discharging phases will not be balanced leading to more charge transfer losses. Another implementation is therefore proposed to address these issues.

Sliding-mode with relative hysteresis band

In the previous section the switching frequency of the sliding mode operation is modulated through the hysteresis of the comparator. The motion of the converter is defined with (4.132). The induced mode shows for a given value of k that:

V f ly =    V out for g(x) = -k V in -V out for g(x) = +k (4.173)
As a consequence the voltage across the flying capacitor can be set by two independent boundaries, V l and V h to force the induced mode:

V l = V ref (4.174) V h = V in -V ref (4.175)
The schematic implementation of such a control is depicted in Fig. the converter returns to the discharging phase. By this way the sliding surface is the same but the sliding mode operation is now independent of the averaged value of the flying capacitor. As well as in the previous Section, the converter can be

C f ly V top + V bot - - + V f ly - + V in + V ref - R S Q
v f ly (t n + d n ) = Cx(t n + d n ) = V in -V ref (4.176) v f ly (t n + T n ) = Cx(t n + T n ) = V ref (4.177)
The sampled-data model is constructed by sampling the state x at t n :

x n+1 = f (x n , u n , τ n , v refn ) (4.178) v out = Ex n (4.179) v f ly = Cx n (4.180)
the constraint equations are thus:

g (x n , u n , τ n , v refn ) = v f ly (t n + d n ) -V in + V ref v f ly (t n + T n ) -V ref (4.181) = Cx(t n + d n ) -V in + V ref Cx(t n + T n ) -V ref (4.182) = 0 (4.183)
The fixed point, x 0 (0), U, (d, T ) , V ref , is determined for a given targeted output voltage, V target , by the following set of equations:

x 0 (0) = f x 0 (0), U, (d, T ) (4.184)

Sliding-mode with relative hysteresis band 107

g x 0 (0), U, (d, T ) , V ref = 0 (4.185) Ex 0 (0) -V target = 0 (4.186)
The Levenberg-Marquardt algorithm gives:

x 0 (0) = 0.6022 0.6 (4.187)

d = 3.
= CΓ 1 C (Φ 2 Γ 1 + Φ 1 ) - 0 1 0 0 (4.195) ∂g ∂v refn = +1 -1 (4.196)
The audio susceptibility and the output impedance are given by (4.171) and (4.172)

respectively and the control-to-output transfer function is At startup the integrator output is null, the hysteresis window is wide and the converter starts slowly. One good practice to decrease the starting time is to use 110 Chapter 4. Frequency modulation: controller implementation

T oc (z) = vout (z) vref (z) = E(zI -Φ 0 ) -1 Γ r ( 4
C f ly V top + V bot - - + V f ly - + V in + V ref + V out - - R S Q

Conclusion

Linear and non-linear control have been analyzed. Linear frequency modulation with a voltage loop is very simple to implement since it requires an operational amplifier and a VCO. The transient performances can be increased by adding a current loop. Nonetheless the current loop control is more difficult to design and the implementation is also complex. The robustness is therefore lower. Sliding mode control can drastically improve both transient behavior and robustness but requires a voltage observer for the flying capacitor. Finally voltage loop control works for an interleaving architecture when a multiphase VCO is considered while sliding mode control cannot address this need for now.

Architecture description

The power supply strategy described in Section 2.8 calls for a modular architecture.

The power stage

Converter cell

A multi-ratio cell is necessary in order to maximize the efficiency over a wide range of output voltage and load current. Efficiency is always higher and the output resistance always lower for SC converters having a reduced number of flying capacitors.

A large number of flying capacitors means a large number of switches to arrange the capacitors over the various ratios leading to more switching losses. Series-parallel topologies make better use of the capacitors than Ladder or Dickson structures [START_REF] Seeman | Analysis and Optimization of Switched-Capacitor DC-DC Converters[END_REF].

Capacitor density is often the most important parameter in SC converter design and that is the reason why Series-parallel topologies are widely used. An output voltage range of 0 V to 1.2 V from an input voltage of 1.8 V requests four converter ratios: switches are easily controlled between 0 V and 1.8 V . The P-well is not isolated and directly tied to ground through the substrate for the sake of space. A special configuration is used for the N-well. The flip-well architecture is also selected to provide a low threshold voltage devices and the gate is connected to the back-plane.

V out V in V out V in V out V in V out V in Phase 2 V out V out V out V out
By the way when the transistor is turned-on, a voltage of 1.8 V is applied to the N-well. The transistor is forward-biased so that threshold voltage is lowered. On the contrary when the transistor is turned-off, the back-plane is tied to ground and the threshold voltage raises-up to the nominal value. This configuration is so-called the dynamic threshold scheme. Table 5.1 shows the performances of the switch configurations in terms of Ion /I of f , R on and C gate for the normal, forward biased and dynamic threshold voltage schemes. The results are extracted from circuit simulations for each configurations. The dynamic threshold voltage configuration exhibits the highest Ion /I of f ratio while maintaining a low on-state resistance of the switches.

The forward-biasing technique is not suitable since the Ion /I of f ratio is degraded.

The dynamic threshold voltage scheme increases the parasitic capacitance of the gate due to the BOX and the N-well and P-well junctions. C gate increases by 28%

while R on decreases by 32% and the Ion /I of f ratio increases by 21% compared to normal voltage scheme. This implementation delivers an efficient switch with an ultra low-threshold voltage around 100 mV . Thanks to the flip-well architecture, no triple-well scheme is required and the silicon area is preserved. Moreover the floating switches can be driven between 0 V and 1.8 V without any special assistcircuit. The power switches are driven by an inverter chain. A nand gate enables or disables the switches depending on the selected ratio. The unit switch is depicted 118 Chapter 5. Proprosed SC converter in Fig. 5.7. Several units are associated in parallel to produce a discrete variable transistor width.

Power grid and MIM capacitor implementation

The MIM and the power grid routing are a major concern for this architecture.

MIM capacitors are situated between the top thickest metal levels in the 28nm FDSOI process. The typical capacitor density is 20 f F /µm 2 . The top metal levels exhibit a low sheet-resistance that is necessary to build the power grid of digital blocks. The plates of the MIM capacitors are connected only to the upper levels instead of both lower and upper level in order to save a mask. Since MIM capacitors are primarily used for decoupling strategy, it does not alter the power grid design.

Unfortunately the usage is not exactly the same for the SC converter. The plates must be connected to switch cells instead to the power supply rail. The bottom plate exhibits a low sheet-resistance allowing connection at the edge of the capacitor close to the switch cell. This is not the case regarding the top plate sheet resistance. The . The coupling effect between the plate and the power grid is small because of the inter-metal dielectric value and thickness. A bottom plate parasitic capacitor between 1% and 3% has been reported for the process.

Frequency generation

The switching frequency is generated by a ring oscillator. The proposed diagram for the oscillator is given in Fig. The description of the layout and the pin mapping is given in Fig. 5.14.

Prototype

Experimental validation

The test-chip is tested on a board presented in Fig. 5.17 3:1 51%@0.52 V 63%@0.49 V 56%@0.44 V 47%@0.35 V 2:1 70%@0.82 V 80%@0.81 V 78%@0.77 V 73%@0.74 V 3:2 72%@1.09 V 80%@1.08 V 75%@0.97 V 69%@0.91 V 4:3 73%@1.21 V 79%@1.2 V 71%@1.03 V 66%@0.97 V anymore. At the maximal switching frequency the power consumption is 454 µA and only 3.5µA at the minimal switching frequency.

The efficiency of the power stage is then characterized for the various ratios and various load currents. The supply voltage of the ring oscillator is swept and the measurements are reported in Fig. 5.21, Fig. 5.22, Fig. 5.23 and Fig. 5.24. Table 5.3 presents the measured peak efficiency and the corresponding output voltage for the different ratios and over various output current values. Efficiency is lower at 1 mA than at 10 mA because the parasitic capacitor losses dominate at low power.

At the maximal output current of 250 mA, efficiency is close to 70% for both the 2:1 and the 3:1 ratios. The converter cannot deliver more than 1 V at this current level even using the 4:3 ratio. This ratio is not efficient at high power due to the The process deviation degrades also the on-state switch resistance and it is difficult to separate its contribution in the FSL region. The characteristic that shows the resistive effect impacts is shown in Fig. 5.27. The load current is swept from 100 mA to 250 mA by step of 50 mA. After several iterative simulations the value of the resistance that fits with the measurement results is 8 Ω. The value extracted from the model was 6 Ω which was a good approximation considering its simplicity. The de-embedding of the parameter is also checked for the other ratios and confirm the results as shown in Appendix C.

The frequency modulation control

Control loop design

The PI controller is implemented using an operational amplifier and a feedback network (Fig. 5.28). The feedback components R 11 , R 21 and C 21 are evaluated from (5.1):

R 21 = T i C 21 R 11 = T i K p C 21 (5.1)
The controller can be configured in follower mode when F = 1. This mode can be used for debugging and for the start-up of the converter. The converter enters in the regulation mode for F = 0. Programmable resistance are used to select various PI parameters. This is useful to compensate the process variation and uncertainty of the model.

- + C 21 R 21 F F R 11 V f b V ref V ctrl
M 13A M 13B M 2A M 2B M 14 M 12A M 12B M 2C M 3A R M 12C M 1A M 1B M 2D Vinp Vinm M 3D M 4B M 3C M 4A M 6A M 7A M 7C M 7B M 2F M 8A M 8B M 2E M 9A M 9B M 3B M 6B M 6C M 3E M 10B M 11B M 11A M 10A M 6D M 7D Cp Rp Cn Rn Vout Vbiasn Vbiasn Vbiasn Vbiasp Vbiasp 1.8 V

Experimental validation

A second test-chip including the power stage, the controller and a digital load has been fabricated to evaluate the converter. The layout of this test-chip keeps the pin-to-pin compatibility with the board in Fig. 5.17. The supply voltage of the controller is isolated from the 1.8 V voltage rail used by the IO ring. A clock sensing has been replaced by a biasing input for the amplifier. The pin can be used to provide an external biasing current in case of a failure of the GmR structure. The other clock sensing is still available to monitor the switching frequency of the converter.

In addition to the controller, a digital load has been implemented over the available area. This load comprises inverter chains distributed as programmable slices. An The oscillator is first characterized as it was the case for the previous test-chip.

The amplifier is configured in the follower mode and the SC converter is disabled.

The amplifier serves as a buffer which drives the oscillator according to the value The results are reported in Fig. 5.33. Simulations do not fit with the experimental results. The frequency is constant above a reference voltage of 1.6 V because the Efficiency as function of the load current for various regulated output voltages is plotted in Fig. 5.36. The efficiency is almost constant over the current range but decreases at light load because of the leakage of the current source. The efficiency starts to decrease at larger value of load current for 0.4 V , 0.9 V , 1 V and 1.1 V because the converter operation get close to the FSL region. The switching frequency does not increase linearly and the switching losses drastically increase.

The accuracy of the regulated output voltage depends on the amplifier mismatch.

More precisely a mismatch in the differential pairs introduces an offset. The mismatch is mitigated by a larger size of transistors and can be evaluated using statistical models. 1000 runs of Monte-Carlo simulations are performed on the converter for a reference voltage of 600 mV and a load current of 100 mA for the 2:1 ratio.

The distribution of the output voltage is given in Fig. 5.37 and σ = 0.8371 mV .

Simulations establish an accuracy of ±2.5 mV . All chip samples ( 45) are then characterized for the same operating point. Repeatability of the measurement has been checked and measurements are performed one after another. The distribution is plotted in Fig. 5.38 and σ = 2.005 mV . The measured accuracy is ±6 mV that is larger than the one obtained from simulation. The process support team has mentioned that the mismatch models were quite optimistic and some improvements are in progress.

Load transients are performed with the embedded digital load because current steps cannot be applied externally due to the inductive parasitics of the socket.

Moreover this digital load allows to emulate the current surge of real digital core.

The setup of a load transient is the following. For a negative load step, a constant current is applied with a current source and the sensing clock of the oscillator is disabled. A clock of 100 M Hz is fed to the digital load but all the slices are disabled.

The oscilloscope is set in the single acquisition mode. The sensing clock and the slices are turned-on simultaneously and the event is triggered on any sensing clock edge. For a positive load step, a constant current is applied and the digital load The ripple voltage is a sensitive specification in SC converter. The switching frequency, the load current and the output capacitor value are the major parameters.

Efficiency [%] V ref =0.3V V ref =0.4V V ref =0.6V V ref =0.7V V ref =0.8V V ref =0.900V V ref =1.000V V ref =1.100V
For instance, the voltage ripple value is 100 mV in the 2:1 ratio at 130 mA and for a reference voltage of 600 mV . The ripple measurement is partially polluted by inductive noise but most part of this large ripple value can be explained by the architecture implementation. The lateral length of the oscillator is larger than the horizontal length. It becomes quite complicated to maintain equal delays between cells while the spacing between some delay cells is different. In other words, the interleaving of the clock is not ideal. The charges are not delivered as uniformly as expected, causing an increase in the output voltage ripple. This ripple could also alter the stability of the loop because it can be found on the error signal which drives the oscillator. The impact of the ripple can be measured on the jitter of the clock. The jitter is measured for the 2:1 ratio at a load current of 50 mA and a voltage reference of 600 mV as shown in Fig. 5.45. The load current is increased to 150 mA in Fig. 5.46. In Fig. 5.45 the converter operates in the SSL region where the ripple is high and a peak-to-peak jitter value of 34.8 ns is measured for a period [55] [START_REF] Seeman | An ultra-low-power power management IC for energy-scavenged Wireless Sensor Nodes[END_REF] [57]

[58]

[59]

[60]

[61]

This work

Discussion

The converter can be compared to previous art in terms of efficiency versus power density as shown in Fig. 5.47. A peak efficiency of 72.5% at the power density of 310 W /mm 2 is considered for the 2:1 ratio. This point is located on the trend of other SC converters and close to [START_REF] Jain | A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS[END_REF] for the same output voltage which also uses MIM capacitors above digital core. Those points are still far from deep trench capacitor based converters [START_REF] Andersen | A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at Chapter References 90% efficiency using deep-trench capacitors in 32nm SOI CMOS[END_REF] or from the converter using only MOS capacitors as presented in [START_REF] Le | A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm 2 at 81% efficiency[END_REF]. This difference can be explained by the design constraints. The series resistance of MIM capacitors strongly limits both efficiency and power density. New form factor would improve the performances. Table 5.5 gives some comparison points with relevant published works. The proposed solution exhibits the widest output voltage range 0.2 -1.1 V for an input voltage of 1.8 V . Lower input voltage does not reduce significantly the input current.

The DVFS capability is the highest reported and around ten times larger than [START_REF] Lu | 20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors[END_REF].

However load transient performances are quite weak but the control strategy is promising regarding the performances in [START_REF] Lu | 20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors[END_REF]. Higher crossover frequency for the PI controller could improve the undershoot and the recovery time. The large output voltage ripple is also an important issue. Design efforts in the ring oscillator design and higher interleaving level should address this issue. Besides the solution remains area efficient since the silicon area penalty is only 11.5% of the digital block area. This feature is larger than the 3.6% in [START_REF] Jain | A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS[END_REF] mainly because of the analog nature of the controller rather than an hysteretic one. Peak efficiency 82.7%@1 V 85.1%@1.1 V 78.5%@1 V 77.5%@1.05 V 78%@1.1 V 86.4%@0.85 V 90%@1.1 V 68%@0.55 V 74%@0.7 V 71%@0.8 V 84%@1.1 V 71.5%@3.1 V 73%@3.6 V 45.5%@0.34 V 72.5%@0.72 V 68.5%@0.9 V 65%@0.96

Ref

.8 V 1.6 -2.2 V 1.8 V 1.23 V 3 -4 V 1.8 V Output voltage 0.7 -1.1 V 0.6 -1.2 V 0.7 -1.1 V 0.45 -1 V 1 V 0.2 -1.1 V
V Power density W /mm 2 1.9@1 V 3.2@1.1 V 0.06@1 V 0.062%@1.05 V 0.065%@1.1 V 2.17@0.85 V 3.71%@1.1 V 0.062@0.55 V 0.1@0.7 V 0.126@0.8 V 0.242@1.1 V 0.19@3.1 V 0.19@3.6 V 0.146@0.34 V 0.31@0.72 V 0.386@0.9 V 0.412@0.96 V Area over- head 1 W /

CHAPTER 6

Body-bias generator When vbb is positive, transistors are forward-biased and when vbb is negative, transistors are reverse-biased. Since the substrate is grounded, the deep N-well bias voltage, denoted vdds must be always greater than 0 V to avoid any substrate current flow. However it is obvious that the junction formed between P-well and N-well layers on one hand, P-well and deep N-well layers on the other hand and the drain/source junction, will conduct during forward biasing. This current is significant on large circuit and limits the benefits of this technique. The value of forward biasing is commonly limited to 300 mV . Similarly reverse biasing is limited when the GIDL 1 becomes significant. The leakage current is reduced in reverse biasing except GIDL. When GIDL is the major contributor to leakage current, reverse biasing is not effective to reduce the leakage current. Moreover the range of vbb is limited by the voltage range sustained by the junctions (≈ 6 V ) and does not exceed -3 V in practice to keep safe margins in most bulk technologies. It is also important to note that body-biasing increases the latch-up sensitivity in bulk technology because Motivations and context 151 the carriers injected can turn-on the well known parasitic thyristor structure.

FDSOI technology has been recently introduced by STMicroelectronics in the 28nm

node. An ultra thin non-doped body is isolated from the substrate by a thin buried oxide. This way the drain/source junctions are removed and the associated leakage current as well. P-well and N-well are implemented under the thin oxide of the NMOS and the PMOS respectively. The bias voltage of those wells can be used to control the threshold voltage of the transistors. It can be considered as a second gate, the so-called back-gate. The cross section of a CMOS inverter in FDSOI is shown in Fig. 6.2.

This device architecture constitutes the regular threshold devices of the technology. Similarly to bulk technology, a body-biasing strategy requires a deep N-well to isolate the P-well from the substrate. A wide reverse body-biasing schemes (up to -3 V ) can be applied until the breakdown voltage of the well junctions (≈ 6 V ).

FDSOI reduces the GIDL because the channel is electrically isolated by the BOX.

Forward-biasing is also extended but in a lower amount. The well junctions start to conduct for a voltage around 300 mV . This case occurs when vbb is equal to vdd 2 + 150 mV . The Flip-well architecture has been developed to offer full forward capability [START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF]. This architecture is presented in Fig. 6.3. A N-well is implemented under the NMOS transistor instead of a P-well and conversely for PMOS transistors.

The devices exhibit a lower threshold voltage compared to the conventional architecture. Due to the well configuration, vdds and gnds are both tied to ground to keep all the junctions reverse-biased during normal operation. Body-biasing imposes gnds = vbb and vdds = -vbb to avoid substrate current flow. Reverse body-biasing is effective up to vbb = -150 mV because the voltage across the junctions is equal to 300 mV and the junction current starts to increase. In the forward mode, all the junctions are reversed biased and vbb is only limited by the breakdown voltage. The threshold voltage can be strongly reduced with the Flip-well architecture.

The voltage range in the various cases and the operating regions are summarized in Fig. 6.4.

The challenge for the designer is to find voltage regulators that exploit the bodybiasing capability. Voltage regulators with bipolar features are required regarding the body-bias range in Fig. 6.4. Moreover integration constraints and costs call for fully integrated solutions to apply the body-biasing techniques to a large number of blocks. A body-bias generator with reverse and forward capabilities is presented in [START_REF] Kamae | An area effective forward/reverse body bias generator for within-die variability compensation[END_REF]. Low output impedance DACs are used to provide the positive voltage and charge-pump level shifters are employed in reverse mode. Despite low silicon area overhead of the proposed solution, systems using a buffer amplifier are preferred for faster transient response [START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF][START_REF] Sumita | Mixed body bias techniques with fixed Vt and Ids generation circuits[END_REF][START_REF] Meijer | A forward body bias generator for digital CMOS circuits with supply voltage scaling[END_REF][START_REF] Kamae | A body bias generator compatible with cell-based design flow for within-die variability compensation[END_REF]. A modular output buffer is implemented 152 Chapter 6. Body-bias generator

Large leakage breakdown vbb range 0 vbb BULK +300 mV +3 V 0 -300 mV -3 V 0 vbb RVT V dd 2 + 150 mV +3 V 0 -3 V 0 vbb LVT +3 V 0 -150 mV -3 V Forward Reverse Figure 6
.4: Body biasing range in bulk process (Fig. 6.1), FDSOI regular well (Fig. 6.2) and FDSOI Flip-well architectures (Fig. 6.3) in [START_REF] Meijer | A forward body bias generator for digital CMOS circuits with supply voltage scaling[END_REF] in order to address a wide range of digital circuit area. However the power consumption is critical for ultra low power purpose and a reverse-bias generator based on a low-drop out regulator and a negative SC converter is proposed in [START_REF] Pique | A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias[END_REF].

A current consumption of 350 nA is reported. We propose first to design the same architecture but dedicated to forward body-biasing scheme for Flip-well FDSOI technology instead of reverse scheme in bulk technology. The available generator for this purpose is detailed in [START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF] and the architecture is depicted in Fig. 6.5. Two class AB amplifiers are used to buffer the voltages coming from the two digital-toanalog converters. The voltage of the N-well is gnds and the voltage of the P-well is vdds. Since vdds is negative, a fully integrated SC converter is used to convert the main supply voltage level of 1.8 V to a negative rail of -1.8 V . A capacitor of 1 µF is implemented off-chip to hold the negative voltage during current surge.

The negative converter is only designed to provide the static current consumed from the -1.8 V rail. This architecture is able to change the voltage level in less than 1 µs at the cost penalty of a large power consumption and a large silicon area. This architecture is not suitable for ultra low-power and low-cost circuit.

Proposed architecture

The negative SC converter in 6.5 is unregulated what imposes a large value of tank capacitor. This capacitor is thus off-chip due to its large value. The power delivery network, the board and package design is more complex. Moreover a part of the Proposed architecture 153

- + DAC -1.3 to 0 V - + DAC 0 to 1.3 V Negative SC converter C ext 0 V +1.8 V -1.8 V gnds vdds Figure 6
.5: Possible architecture of a high performance body-bias generator in 28nm FDSOI [START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF] power consumption comes from the transient requirements. Ultra low-power SoC exhibits less aggressive specification. We propose to design a fully integrated and regulated negative voltage regulator which will directly drive the P-well. By the way one of the main contributors to the power consumption, the class-AB amplifier in 6.5 is removed. The integration level is increased since the external capacitor is removed too. The positive generator can then be a simple low-drop out regulator as in [START_REF] Pique | A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias[END_REF].

The architecture of the proposed negative voltage regulator is depicted in Fig. 6.6.

The output voltage is regulated using a frequency modulation voltage loop through a VCO and a PI controller. A bandgap reference voltage provides the reference level to the PI controller. Since the regulation must be performed in the positive domain, a voltage sensor is used to convert the negative output voltage to a positive voltage fed to the PI controller. The selection of the output voltage level is achieved with a programmable feedback network included in the voltage sensor. The common mode voltage of the PI controller is also maintained equal to the voltage reference level independently of the output voltage. This considerably simplifies the constraints on the design of the PI controller. In addition the digital-to-analog converter in 6.5 is not required. The architecture in Fig. 6.6 is therefore compact what is essential in order to achieve a low-power consumption and high integration factor.

The physical implementation of each blocks is detailed in the next Sections. 154 Chapter 6. Body-bias generator

Programmable voltage sensor

The objective of the programmable voltage sensor is three-fold. It translates the negative output voltage into the positive domain. Second it is involved in the selection of the desired output voltage. Finally it ensures a minimal power consumption in the SC converter necessary to perform the control. This voltage sensor is based on a programmable resistive divider as depicted in Fig. 6.7. The intermediate node of the resistive divider is connected to the feedback node, V f b using transmission gates. The expression of the voltage V f b is:

V f b = (1 -K) • V neg + K • 1.8 (6.1)
The value of K depends on the resistance values and the selected node in the divider. Each resistance comprises a set of unit resistance for matching purpose.

The targeted value is achieved by placing the proper number of unit resistances in parallel. The unit resistance value determines the current consumed by the resistive divider. A large value results in a low consumption but the area overhead becomes more important. Unfortunately the current consumption depends on the negative voltage value and can be very small near the ground voltage. The values of K are given in Table . 6.1.

Negative SC converter 6.4.1 The power stage

Negative SC converters have been already reported in literature for audio power supply [START_REF] Neri | A novel series-parallel inverting charge pump topology in 40nm CMOS technology[END_REF] and analog purposes [START_REF] Liu | A CMOS negative supply for large dynamic range high-bandwidth analog circuits[END_REF]. The power stage chosen for the bodybias generator is implemented with a cross-coupled structure [START_REF] Pelliconi | Power efficient charge pump in deep submicron standard CMOS technology[END_REF] as depicted in Fig. 6.8. In a first phase, the flying capacitor, C A , is charged to the input voltage,

V in , through P 2A and P 1A while the flying capacitor, C B , is connected between ground and the output node through N 2B and N 1B. On the contrary, in a second phase, C A is now discharged into the output node through N 1A and N 2A and

R 0 R 1 R N -1 R N 1.8 V V neg S 0 S 0 S 1 S 1 S N -1 S N -1 S N S N V f b
V neg [mV ] K 1 -K 1 - 100
N 1A P 1A N 2A P 2A C A N 1B P 1B N 2B P 2B C B clk2 clk1 clk1 clk2 N R clkr N A C N A clk2 N B C N B clk1 C P A P A clk1 C P B P B clk2 V out V in
N 2A 1 0 1 0 P 1A 0 1 0 1 N 1A 1 0 1 0 P 2B 1 0 1 0 N 2B 0 1 0 1 P 1B 1 0 1 0 N 1B 0 1 0 1 N R 0 1 0 1 0 1 0
V B = C N A (V s + 1.8) + (Cg N B1 + Cg N A ) V s C N A + Cg N B1 + Cg N A (6.2) If C N A Cg N B1 + Cg N A
, the voltage at node B is equal to V s + 1.8 V and the transistor N A is turned on. Similarly to the first phase of operation, the capacitor

C N B is charged to V s though R
V D = C P B (V s -1.8) + (Cg P B1 + Cg P A ) V s C P B + Cg P B1 + Cg P A (6.3)
if C P B Cg P B1 + Cg P A , the voltage at node D becomes V s -1.8 V . The transistor P A is thus turned-on and the capacitor C P A charges to V s -1.8 V through R on and Rb. The voltage at node C is equal to V s and the transistor P B remains off. The cycle is repeated and the transistors P A and P B are driven between V s and V s -1.8 V , independently of the value of V s . The NMOS and PMOS bootstrap drivers require that the bootstrap capacitors are larger than the ones of the transistor gates. The on-state resistance, R on and the output resistance of the buffer, Rb must be kept as low as possible. Small values will increase the tracking capability of V s but too small values will result in large parasitic capacitors.

The bootstrap scheme allows a reliable operation of the power stage in Fig. 6.8.

This power stage can be used as a voltage doubler without redesign. The source of the transistors P 1A and P 1sB becomes the output node while the previous one is put to ground. The power stage can be implemented with thin oxide devices if the clock signals ensure a proper voltage operation. 160 Chapter 6. Body-bias generator

A B C N B N A clk2 C N A N B clk1 V S Cg N A1 Cg N B1 CgNA CgNB
C N B Rb 1.8 V C N A Rb V S R on Cg N A1 Cg N B1 CgNB CgNA
C N B Rb C N A Rb 1.8 V R on V S Cg N A1 Cg N B1 CgNB CgNA

Flying capacitor selection

The choice of the flying capacitors depends on the capacitor density and the parasitic capacitors. The FDSOI technology offers MOM 2 capacitors, MOS capacitors and MIM capacitors. MIM capacitors cannot sustain more than 1.4 V while the application requires 1.8 V . It is important to mention that MOS capacitors can be only used in strong inversion in FDSOI. A charge recycling scheme is applied to reduce the parasitic losses [START_REF]A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF]. The transistor N R in Fig. 6.8 shorts the top plate of the flying capacitors during deadtimes. A similar scheme can be applied to the bottom plate of the flying capacitors but the control of the switch would therefore be more challenging and the complexity of the circuitry would result in a higher consumption than the saving in losses. Charge recycling of the bottom plate parasitic capacitance is useful for MOM capacitors since they exhibit the same parasitic coupling from the top and the bottom plates.

Various configurations are explored for the PMOS and the NMOS over regular and low-threshold voltage devices. The configurations are compared in terms of area, capacitor values and parasitics capacitors. The top plates and the bottom plates are respectively tied to 1.8 V and 0 V in the charging phase. In the discharging phase, the top plates are now connected to ground and the bottom plate to the negative voltage. For the NMOS, the top plates are thus connected to the gate and the bottom plates to the source/drain to maintain the transistor in strong inversion.

For the PMOS, the top plates are connected to the source/drain and the bottom plates to the gate of the transistor. The results of the analysis are given in Table 6.2. and Fig. 6.16c, the parasitic capacitor is formed by the P-well-deep N-well junction and its value is minimized because the junction is reversed biased between -1.8 V and -1.8 V + V neg . The parasitic capacitors can be minimized by applying a floating voltage to the well [START_REF] Le | A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm 2 at 73% efficiency[END_REF]. Nonetheless this scheme is not explored due to ESD issues in SoC environment. Generally the BOX capacitor is very small compared to the MOS capacitor. Configurations with BOX capacitor as a parasitic capacitor are better and smaller. Schemes employing several wells always increase the area and the parasitic. A charge recycling scheme can be applied when the parasitic capacitor is connected to the top plate. It is tempting to use the configuration with the largest value of capacitor but the value of parasitic capacitors is also decisive.

The bottom parasitic capacitance has indeed a strong impact on the output resistance of the converter and its output voltage [START_REF] Andersen | A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF]. A sampled-data model of the negative SC converter with a bottom parasitic capacitance is derived and the different topologies are depicted in Fig. 6

R on .
During the charging phase, in Fig. 6.18a, the flying capacitor charges to the input voltage and the bottom parasitic capacitor is discharged to ground. Then in the discharging phase, the flying capacitor is discharged to the output node. The charges are distributed over the output node, the flying capacitor and the bottom plate parasitic capacitor. All the charges are not transfered to the output node and a small amount is lost in the parasitic capacitors. The output impedance is increased compared to an ideal case [START_REF] Andersen | A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF].

The output resistance is evaluated from the sampled-data model as shown in Fig. 6.19. The output voltage is computed and plotted in Fig. 6.20. The difference between the two curves in the SSL region is explained by the difference in the output resistances. However the difference increases significantly in the FSL region.

An explanation is given in Fig. 6.21. The ratio of the SC converter is extracted from the sampled-data modeling using the DC value of the audio susceptibility (Section 3.6.2). A constant difference appears in the SSL region due to the charge redistribution. Under no load condition, the ratio n of the converter is given by:

n = C f ly C f ly + C bot (6.4)
This expression is true in the SSL region where the charges are totally transfered.

In the FSL region the converter ratio decreases. A current proportional to the switching frequency is wasted to ground. It has been introduced as an equivalent resistance in [START_REF] Andersen | A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF]. It is clear from Fig. 6. [START_REF] Cheng | Dynamic voltage and frequency scaling circuits with two supply voltages[END_REF] The oscillation frequency of the current-starved VCO is given by [START_REF] Baker | CMOS: Circuit Design, Layout, and Simulation[END_REF]:

f osc = I D N • C o • V supply (6.5)
Where I D is the current provided by the current sources, C o is the equivalent capacitance seen at the output node of each inverter, N is the number of inverters in the chain and V supply is the supply voltage of the oscillator. A resistance, R, is inserted between the source of N C and ground to linearize the gain of the VCO.

The frequency is indeed proportional to the current but this current is controlled by the gate voltage of the transistor N C. The current of a transistor is related to the square of the gate-source voltage and with a source resistance, the controlled current I D becomes:

I D = g m 1 + R • g m • V ctrl (6.6)
where g m denotes the transconductance of the transistor N C. If R 1 gm , (6.6) becomes:

I D = 1 R • V ctrl (6.7)
The current is now proportional to the control voltage and the gain of the VCO is determined by the value of the resistance, R.

The frequency range of the VCO is imposed by the transfer characteristic of the SC

Voltage loop design

A frequency-modulation with a voltage-loop control is selected. A non-linear average model is build in order to determine and simulate the small-signal behavior of the loop. The output impedance of the converter as a function of the switching frequency is:

R out = 1 2C f ly f sw coth 1 16R on f sw C f ly (6.8)
Chapter 6. Body-bias generator The switching limits are R SSL = 1 2C f ly f sw (6.9)

N 1Z P 1Z R N C P 1Y N 2A P 2A P 1A N 1A N 2B N 2B P 1B N 1B N 2C P 2C P 1C N 1C N 2D P 2D 1.8 V V ctrl V clk
R F SL = 1 16R on (6.10)
The output voltage evaluation including the impact of parasitics is

V neg = - C f ly C f ly + C bot V in + R out (f sw ) (6.11)
The VCO is linearized according to the characteristic in Fig. 6.26:

f sw = 1.756 • 10 6 • V ctrl -729 • 10 3 (6.
12)

The classical PI controller with an operational amplifier and a feedback network is shown in Fig. The amplifier has a high DC gain to satisfy the output voltage accuracy better than ±1 mV over the various operating points and process and temperature variations.

A slew-rate of 4 V /µs is required to avoid the saturation of the loop during large reference tracking. The output stage of the amplifier is able to drive the VCO over its whole linear range. The compensation network and the slew-rate are carefully evaluated with the characterization of the input capacitance at the control voltage 174 Chapter 6. Body-bias generator

- + R 21 C 21 R 11 V ref V f b V ctrl

Conclusion

The power supply scheme of complex digital SoCs is facing a wall. Implementation of DVFS scheme to increase the efficiency of the digital payload implies multiple power domains which cannot be addressed from outside the package. The increase in the number of IOs and the footprint of the external voltage regulators become prohibitive. The change of paradigm is to embed the power supply within a digital block where all resources operate at the same instantaneous voltage.

The challenge is then to embed a local and dedicated voltage regulator at no silicon penalty but mandatory performances to accommodate DVFS. The switchedcapacitor DC-DC converter is by now the best candidate from integration and cost point of view. Better figure of power density may be achieved with inductive DC-DC converters but this calls for a very complex back-end technology. The choice here is to demonstrate the capability of a SC converter integration within the design flow of the digital block. The main stream idea is to stack the necessary capacitors on top of the digital gates. The active power switches must fit into a peripheral area to the digital gates where a standard approach consists to place the actuators of the power gating scheme.

From practical point of view, the job comprises the definition of a suitable SC elementary cell. A methodology must be selected to support the analyses necessary for the closed-loop design. Finally a practical demonstrator must be designed and the selected technology is CMOS FDSOI 28nm.

Chapter 2 has established the bottle neck of power supplying SoCs. Obviously the SC converter receives a lot of attention and a landscape describes the distribution of main literature results between efficiency and power density. There is a limit Chapter 7. Conclusion in power density that cannot be overcome without a proper capacitor technology but with a huge cost penalty. This explains the difference between literature results based on trench capacitors and MIM capacitors. The former capacitors offer better results but the latter ones open many possibilities to low cost devices. This cost constraint explains the choice of MIM capacitors. As a consequence the maximum efficiency will be in the range of 75% to 80% for a successful design.

Chapter 3 summarizes the fundamentals of SC converters. Unlike most literature the sampled-data modeling is considered first to established a simulation model.

Second a linearized small-signal model is systematically derived to represent the SC converter dynamics. The interests of the method are discussed. The models compare in a satisfying manner to the ones obtained from now well-known approaches.

However sampled-data modeling offers more insights in the SC converter behavior in particular with respect to closed-loop control.

Chapter 4 details the closed-loop control of SC converter with frequency modulation. This scheme is compatible with a multiphase structure but this issue is not fully discussed. Various approaches of control are explored to establish the pros and cons of each methods for a final choice. Sampled-data modeling is extensively used as a uniform and systematic approach.

Short-term perspectives :

• A more complete measurement campaign will cover a temperature dependency evaluation of the silicon test-chip.

• The gearbox concept must be applied with full respect of the digital design flow.

Long-term perspectives :

• The graal of this work is to verify the effectiveness of the multiphase SC converter to supply a genuine digital block. The digital block should be augmented to provide inputs to the DVFS scheme which is related to the gearbox.

The measurement of the digital performances will ultimately confirm the proposal with respect to the new paradigm of power supply.

APPENDIX B

State space model B.1 Model of a 2:1 SC converter with off-state resistance

A 1 =     - R of f + R on 2 R of f τ 1 - R of f -R on 2 R of f τ 1 - R of f -R on 2 R of f τ 2 - R of f + R on 2 R of f τ 2     , A 2 =     - R of f + R on 2 R of f τ 1 R of f -R on 2 R of f τ 1 R of f -R on 2 R of f τ 2 - R of f + R on 2 R of f τ 2     B 1 =     0 1 2 τ 1 -1 C load 1 2 τ 2     , B 2 =     0 R on 2 R of f τ 1 -1 C load R on 2 R of f τ 2     C 1 =    - R of f + R on 2 R on R of f - R of f + R on 2 R on R of f 0 1    , C 2 =    - R of f + R on 2 R on R of f R of f -R on 2 R on R of f 0 1    D 1 =    0 1 2 R on 0 0    , D 2 =    0 1 2 R of f 0 0    U =    I load V in    , x =     v C f ly v C load     With τ 1 = R on C f
A 1 =      - 1 2 τ 1 0 0 - 1 C load      , A 2 =      - 1 2 τ 1 - 1 2 τ 1 - 1 2 τ 2 - 1 τ 2      B 1 =      0 1 2 τ 1 1 C load 1 2 τ 2      , B 2 =      0 0 1 C load 1 2 τ 2      C 1 = 0 1 , C 2 = 0 1 D 1 = 0 0 , D 2 = 0 0 U =    I load V in    , x =     v C f ly v C load     With τ 1 = R on C f ly and τ 2 = R on C load .

B.3 Model of a negative SC converter with bottom plate parasitic capacitance

A 1 =          - 1 τ 1 0 - 1 τ 1 0 0 0 - 1 τ 3 0 - 2 τ 3          , A 2 =           - 1 τ 1 0 - 1 τ 1 0 - 1 τ 2 1 τ 2 - 1 τ 3 0 - 2 τ 3           B 1 =           0 1 τ 1 1 C load 0 0 1 τ 3           , B 2 =          0 0 1 C load 0 0 0         
Model of a negative SC converter with bottom plate parasitic capacitance 201

C 1 = 0 1 0 , C 2 = 0 1 0 D 1 = 0 0 , D 2 = 0 0 U =    I load V in    , x =         v C f ly v C load v C bot         With τ 1 = R on C f ly , τ 2 = R on C load and τ 3 = R on C bot .

APPENDIX C

Extra measurement results La réduction des consommations dynamique et statique entraîne une dégradation des performances du circuit numérique. Par exemple la diminution de la tension d'alimentation réduit la consommation mais diminue aussi le courant à l'état passant du transistor (2.9). Le courant de conduction sous le seuil peut être réduit en augmentant L ou V t dans (2.6) mais varie à l'opposé de (2.9). Afin d'évaluer le compromis performance et consommation d'un process, on introduit le produit énergie-retard [START_REF] Gonzalez | Energy dissipation in general purpose microprocessors[END_REF].

La mise à l'échelle de la technologie permet d'améliorer le facteur d'intégration mais aussi les performances du transistor. On différencie la technique qui consiste à garder le champ électrique constant dans le transistor de celle qui garde la tension d'alimentation constante [START_REF] Syed | Sensors and Low Power Signal Processing[END_REF]. La deuxième technique est préférée car elle permet de garder la compatibilité entre des puces issues de différentes générations.

Malheureusement le champ électrique augmente: les effets dit de canaux courts apparaissent, entraînant une augmentation de la densité de puissance et des courants de fuite. Des matériaux à forte constante diélectrique sont donc utilisés pour réaliser les grilles des transistors. L'apparition des substrats sur isolant autorise également des facteurs d'amélioration. Néanmoins la proportion des fonctionnalités assurées par un circuit numérique sont telles que la majorité des progrès proviennent des méthodologies de conception orientées vers la basse consommation.

D.2.2 Les techniques orientées énergie

La problématique de la consommation est considérée très tôt dans la réalisation d'un circuit numérique. La consommation dynamique de l'arbre d'horloge est par exemple économisée grâce au clock-gating. Une simple instruction est ajoutée dans le code de la fonction pour suspendre l'activité de l'horloge quand la fonction n'est pas utilisée [START_REF] Michael Keating | Low Power Methodology Manual[END_REF]. Les plateformes de fabrication disposent également de librairies de portes logiques avec différentes tensions de seuil. L'outil de synthèse peut donc sélectionner des portes à faible tension de seuil pour les chemins critiques et des tensions de seuil plus élevées pour économiser des fuites sur les chemins moins critiques [START_REF] Noel | Multi-Vt UTBB FDSOI Device Architectures for Low-Power CMOS Circuit[END_REF][START_REF] Shigematsu | A 1-V high-speed MTCMOS circuit scheme for power-down application circuits[END_REF]. La longueur de grille des transistors peut également être ajustée en suivant les même consignes [START_REF] Yeric | Technology roadmaps and low power SoC design[END_REF][START_REF] Jacquet | A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization[END_REF]. Les fournisseurs de microprocesseur proposent également des architectures dédiées. L'architecture big.LITTLE de ARM co-intègre un processeur optimisé pour la consommation énergétique et un autre pour les performances [START_REF] Arm | White paper: big.LITTLE Technology: The Future of Mobile[END_REF]. Les tâches sont donc exécutées à bon escient sur l'un des deux processeurs. L'implémentation matérielle plutôt que logicielle est aussi privilégiée quand cela est possible car cela présente un meilleur compromis comme pour les accélérateurs graphiques.

Chapter D. Résumé étendu

La technique la plus rependue pour économiser la consommation statique est le power-gating. On utilise un interrupteur pour couper l'alimentation d'une fonctionnalité quand celle-ci n'est pas utilisée [START_REF] Shi | Sleep Transistor Design and Implementation -Simple Concepts Yet Challenges To Be Optimum[END_REF]. L'interrupteur est réalisé par un ensemble de transistors disposés soit en anneaux autour de la fonctionnalité (Fig. 2.2) soit directement distribués à l'intérieur de celle-ci (Fig. 2.3). La configuration distribuée est plus contraignante car elle doit être intégrée dès la conception de la fonctionnalité mais elle permet de limiter les chutes de tension dans la grille d'alimentation.

La configuration en anneaux s'adapte elle à toutes les fonctionnalités déjà existantes mais présente un impact sur la surface de silicium beaucoup plus grand car elle ne limite pas autant les chutes de tension. Les principaux enjeux du power-gating concerne la conception d'interrupteurs efficaces tout en autorisant des temps de réveil et d'endormissement toujours plus faibles. L'ajustement de la tension de l'alimentation est la technique la plus agressive car l'énergie décroît avec le carré de la tension. Malheureusement, la fréquence de fonctionnement doit être également diminuée car les transistors deviennent moins rapides. Afin de ne pas impacter tout le circuit, ce dernier est segmenté en différents domaines de tension [START_REF] Lackey | Managing power and performance for system-on-chip designs using Voltage Islands[END_REF]. La tension et la fréquence sont ajustées en fonction du besoin de chaque tâche. Le Static Voltage Scaling applique des niveaux de tension fixes avec des régulateurs placés la plus part du temps à l'extérieur de la puce (Fig. 2.4). Des valeurs discrètes peuvent être utilisées et on parle alors de Multi-Voltage Scaling (Fig. 2.5) [START_REF] Calhoun | Ultra-dynamic voltage scaling using subthreshold operation and local voltage dithering in 90nm CMOS[END_REF]. La solution la plus aboutie est appelée Dynamic & Adaptative Frequency Scaling (Fig. 2 Les implémentations de capacités peuvent être comparées en surface comme sur

D.7 Conclusion

La complexité actuelle de l'alimentation d'un système-sur-puce comportant de nombreux domaines de tension avec des régulateurs externes n'est pas tenable. L'intégration de l'alimentation s'impose pour répondre au challenge de consommation et Le chapitre 6 démontre l'application de la modulation de fréquence à un convertisseur à capacités commutées pour générer des tensions négatives pour des applications de polarisation de caisson en FDSOI. Les résultats de simulations établissent la pertinence de l'approche.

En conclusion, les contributions énoncées valident la proposition originale de l'architecture. Les performances sont en ligne avec l'état de l'art même s'il reste encore de nombreuses voies à explorer. Il reste notamment à concevoir un système de gestion et de sélection instantanée du ratio du convertisseur. Les caractérisations en température doivent aussi permettre de valider plus en profondeur la régulation analogique. Finalement, l'implémentation de cette architecture conjointement avec un vrai bloc numérique confirmerait définitivement la pertinence de la proposition.

AcronymCMOS 1 2 . 3 2 . 4

 12324 Complementary metal oxide semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . SoC System on chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sources of power consumption . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Power vs performance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 The technology scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Low power techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.1 Design for energy efficiency . . . . . . . . . . . . . . . . . . . 8 2.4.2 Power gating . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.3 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.4 Body-biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 Power delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Challenges in advanced SoC power management . . . . . . . . . . . 18 2.8 Proposed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Fundamentals of Switched-capacitor converter 23 3.1 Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.1 Static model . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.2 Modified static model . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3 Non linear averaged model . . . . . . . . . . . . . . . . . . . 29 3.2.4 Sampled-data modeling . . . . . . . . . . . . . . . . . . . . . 31 3.3 Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 Ripple reduction technique . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 Control & regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.1 Regulation principle . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.1.1 Capacitance modulation . . . . . . . . . . . . . . . . 49 3.6.1.2 Frequency modulation . . . . . . . . . . . . . . . . . 49 3.6.1.3 Pulse width modulation . . . . . . . . . . . . . . . . 49 3.6.1.4 Conductance modulation . . . . . . . . . . . . . . . 49 3.6.2 Small-signal behavior . . . . . . . . . . . . . . . . . . . . . . 50 3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 i CHAPTER 1

Figure 1 . 1 :

 11 Figure 1.1: Evolution of embedded processor performances over the last decade

3 Figure 1 . 3 : 2 Figure 1 . 4 :

 313214 Figure 1.3: Schematic of power solution at board level of the system in Fig. 1.2

Figure 2 . 1 :

 21 Figure 2.1: Switching behavior of a simple inverter

Figure 2 . 3 :

 23 Figure 2.2: Ring implementation of power gating

Figure 2 . 4 :Figure 2 . 6 :

 2426 Figure 2.4: Example of multi-voltage power domain

Figure 2 . 7 :

 27 Figure 2.7: Body-biasing of PMOS and NMOS transistors

Figure 2 . 8 :

 28 Figure 2.8: Power delivery network representation

Chapter 2 .Figure 2 . 9 :

 229 Figure2.9: Samsung's competitive edge in packaging technology[START_REF]Samsung's package informations[END_REF]

Figure 2 . 10 :CFigure 2 . 11 :

 210211 Figure 2.10: Diagram of a classical PMOS LDO V bat

Figure 2 . 12 : 18 Chapter 2 .

 212182 Figure 2.12: Diagram of a capacitive DC-DC converter

  2.11. The battery voltage and the ground are alternatively fed to the inductance by the power switch bridge. The voltage of the bridge is filtered across a low pass LC filter. Energy is stored into the inductor during one phase and restored during the other one. The efficiency is ideally 100% but the parasitic losses including resistive losses and switching losses reduce the efficiency at the nominal load conditions. Special modes such as the discontinuous conduction mode are implemented to improve the efficiency at light load. The output voltage is controlled by the duty-cycle of the switching action. On the contrary to linear regulator they offer step-up and inverting capabilities instead of step-down only. Display requires for instance bipolar supply of ±5V while the battery voltage can be 3.6 V in lithium-ion technology. Audio devices also need bipolar supply. The downside of inductive DC-DC converter are the cost due to the external components (inductor and capacitor). Capacitive DC-DC converter (Fig. 2.12) are sometimes used in audio power management but they are still little used in power management platform. Capacitive regulators are detailed in Chapter 3.2.7 Challenges in advanced SoC power managementReduction in the power consumption in advanced SoC is challenging. Power management techniques have significantly changed the design of SoCs. The most promising strategy is massive DVFS to deliver power according to performance requirements. DVFS is widely used for the most demanding blocks in a SoC such as CPU but cannot be further extended to other blocks for various reasons. Traditional architectures are based on off-chip power supplies. Each domain is independently powered by a voltage regulator with low impedance connection. Increasing the number of power domains will increase the number of regulators and increase the board area. It becomes difficult to optimize routing on constrained board. The power Challenges in advanced SoC power management 19

Figure 2 . 13 :

 213 Figure 2.13: Peak efficiency vs power density of recent published integrated inductive and capacitive DC-DC

Figure 2 .

 2 Figure 2.14: Paradigm

Figure 3 . 1 : 1 - 2 Figure 3 . 2 :Fig. 3 . 2 .

 31123232 Figure 3.1: SC converter

Figure 3 . 3 :

 33 Figure 3.3: SC converter static model representation

28 Chapter 3 .

 283 Figure 3.4: Output impedance diagram

Figure 3 . 5 :

 35 Figure 3.5: Current and voltage waveforms in the flying capacitor in the SSL region for the converter in Fig. 3.1 (f sw = 10 M Hz)

VFigure 3 . 6 :

 36 Figure 3.6: Current and voltage waveforms in the flying capacitor in the FSL region for the converter in Fig. 3.1 (f sw = 400 M Hz)

Figure 3 . 7 :

 37 Figure 3.7: Instantaneous representation of the RC network

Figure 3 . 9 :

 39 Figure 3.9: Hybrid automaton of a DC-DC converter

Simple 2 V

 2 200 pF 10 Ω 10 nF 5 mA 10 M Hz 4 interleaved structure 2 V 50 pF 40 Ω 10 nF 5 mA 10 M Hz Table

Figure 3 . 14 :

 314 Figure 3.14: Output resistance diagram

1 linear 40 Chapter 3 .

 1403 Piecewise Fundamentals of Switched-capacitor converter

Figure 3 . 15 :Figure 3 . 16 :

 315316 Figure 3.15: SC converter interleaved with 4 sub-cell

  leaving schemes have been introduced to address this issue. The initial converter is split in N subsets of converter where N is the so-called interleaving factor. The converter subsets operate in parallel and the clocks are shifted by T sw /N , where T sw is the switching period seen by the capacitor. Thus the values of the flying capacitors may be divided by N and the on-state resistance would be multiplied by N . Small amounts of charge are delivered regularly during the switching period rather than a large amount with less recurrence. The operation of interleaving is described in Fig.3.23. The ripple voltage is theoretically almost canceled with a large 0

Figure 3 . 17 :Figure 3 . 18 :

 317318 Figure 3.17: Efficiency vs flying capacitor area for various flying capacitor specifications

Figure 3 . 19 :

 319 Figure 3.19: Efficiency vs current density for various flying capacitor specifications

Figure 3 . 22 : 48 Chapter 3 . 4 Φ 3 Φ 2 Φ 1 TFigure 3 . 23 :

 3224834321323 Figure 3.22: Output voltage vs current density for various flying capacitor specifications

3. 6

 6 Control & regulation 3.6.1 Regulation principle SC converter are represented by transformer model and an output resistance. The input voltage is converted by the transformer ratio. The output voltage never reaches the ideal ratio due to the voltage drop on the output resistance under nonzero load condition. Thus the output voltage, V out , is a function of the converter ratio and the output resistance drop as follows

  the pole value will change according to the operating point resulting in a non linear behavior. Moreover this model does not offer straight derivation of the control-tooutput transfer function. A linearization must be performed around an operating point when the output resistance is written as R out = f (f sw , D). The expression of the output resistance can be either the static model in Section 3.2.1 or the non linear average model in Section 3.2.3. Then the block diagram of Fig. 3.24 can be implemented in Matlab/Simulink to compute the transfer functions using the linear Control & regulation 51

Figure 3 . 25 :

 325 Figure 3.25: Periodic solution with the derivative

2 .

 2 The transfer functions are expressed in s-domain after the reduction and compared to the linearization of the continuous models. The Bode diagram of the audio susceptibility, the output impedance, the duty-cycle-tooutput voltage transfer functions and the switching frequency-to-the output voltage are shown in Fig. 3.26, Fig. 3.27, Fig. 3.28 and Fig. 3.29 respectively.

54 Chapter 3 .Figure 3 . 29 :

 543329 Figure 3.26: Audio susceptibility

1 modulation 57 58 Chapter 4 .

 1584 Frequency Frequency modulation: controller implementation sliding mode control appears to be a possible alternative. Sliding mode controls are covered in Section 4.4, 4.5 and 4.6.

Figure 4 . 1 :Fig. 4 . 2 .

 4142 Figure 4.1: Diagram of the single bound hysteretic control[START_REF] Michael Seeman | Single-bound hysteretic regulation of switchedcapacitor converters[END_REF]

Figure 4 . 2 :

 42 Figure 4.2: Time diagram of the single bound hysteretic control operation

of the comparator is set to 1 . 5

 15 GHz. The transient results are shown in Fig. 4.3. The load current is increased to 5 mA at 2 µs and decreased to 1 mA at 4 µs. No voltage drop is visible and the output voltage is regulated to 0.6 V value of he reference voltage. The same simulation is performed with a sampling frequency of 500 M Hz. The results are shown in Fig. 4.4. Subharmonic oscillations occur after the load transient and disappear when the load current returns to the nominal value.

4 . 5 . 60 Chapter 4 .Figure 4 . 3 :Figure 4 . 4 :

 456044344 Figure 4.3: Transient simulation results of the output voltage under single bound control

Figure 4 . 5 :

 45 Figure 4.5: Diagram of a linear frequency modulation with a voltage loop

Figure 4 . 6 :

 46 Figure 4.6: Transfer characteristic of a linear VCO

62 Chapter 4 .

 624 osc , is proportional to the control voltage, V ctrl . The gain of the VCO, K vco , represents the sensitivity of the oscillation frequency to a voltage change and f 0 corresponds to the zero voltage oscillation frequency. The frequency range of the VCO, ∆ f = [f min , f max ], is chosen according to the frequency excursion of the power stage. The control voltage range ∆ V = [V min , V max ], depends on the maximal excursion of the controller. Thus the gain K vco can be set to ∆ f ∆ V and f 0 = f min -K vco • V min as shown in Fig. 4.6. The expression in the frequency domain of (4.2) is: fosc (s) = K vco • vctrl (s) (4.3) Frequency modulation: controller implementation hence, the transfer function of

6 T.

 6 and the nominal load current is I load = 5 mA. The parameter of the VCO are K vco = 100 M Hz /V and f 0 = 1 M Hz. Then the large signal sampled-data dynamics is evaluated and the fixed point is x 0 (0) = 0.6022 0.The switching period is T = 63.64 ns (f sw = 15.71 M Hz).

Figure 4 . 7 : 66 Chapter 4 .Figure 4 . 8 :Figure 4 . 9 :Figure 4 . 11 :

 476644849411 Figure 4.7: Bode diagram of the voltage loop control of the 2:1 ratio SC converter with target of a second order behavior

Figure 4 . 12 :

 412 Figure 4.12: Bode diagram comparison of the ideal and the non-ideal controller

( 4 .

 4 [START_REF] Schrom | A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm 2 Using Air-Core Inductors[END_REF] and(4.38). The Trust-Region Dogleg algorithm gives x 0 (0) = 0.5960 0.5939 1.8512 (4.58)d = 3.2318 • 10 -8 (4.59) T = 6.4636 • 10 -8 (4.60)The system is linearized around the fixed-point solution and compared to the linear model with respect to the transfer functions and the transient simulations. Fig. 4.13 shows the load transient simulation. The closed-loop from the sampled-data model takes into account the ripple of the output voltage since the output voltage is sampled at the beginning of each cycle. On the contrary, the linear model is insensitive to the ripple and the output voltage value is averaged. Both models are also impacted by the non-linear behavior of the converter lost during the linearization step. The small-signal closed-loops are compared in Fig. 4.14 and the models are in good agreement. The stability is checked evaluating the modules of the Eigenvalues of the sensitivity matrix Φ 0 . The system comprises a compensator tuned for a closedloop second order behavior. The closed-loop sampled-data model has three state variables hence three Eigenvalues: λ 1 = 7.5253 • 10 -8

74 Chapter 4 .Figure 4 . 13 :Figure 4 . 15 :

 744413415 Figure 4.13: Transient simulation of the closed loop from sampled-data model and linear model

Figure 4 . 16 :

 416 Figure 4.16: Diagram of Eigenvalues dispersion against the reference voltage variations

Figure 4 . 18 : 78 Chapter 4 .

 418784 Figure 4.18: Location of Eigenvalues against variation in T i and K p , parameters of the controller

Figure 4 . 19 :

 419 Figure 4.19: Diagram of a linear frequency modulation with a voltage loop assisted of a current loop

Figure 4 .

 4 Figure 4.20: SC converter with a shunt resistance

Figure 4 . 21 :Figure 4 . 22 :

 421422 Figure 4.21: Block diagram of the small-signal model of the current loop

  4.24. The transfer function of control-to output voltage is compared with and without the feedback loop in Fig. 4.25 as well as for the load current-to-output voltage transfer function in Fig. 4.26. The controlto-output voltage transfer function exhibits a higher bandwidth with the current feedback than without it. The output impedance of the current feedback is lower than without it at low frequency.

Figure 4 .Figure 4 . 24 :Figure 4 . 26 :

 4424426 Figure 4.23: Control-to-switching frequency transfer function

Fig. 4 .

 4 Fig. 4.25 shows that the zero has a large frequency and we propose to use a PI control and the open-loop is therefore:

Fig. 4 . 86 Chapter 4 .Figure 4 . 27 :Figure 4 . 28 :Figure 4 . 29 :Figure 4 . 30 : 88 Chapter 4 .Figure 4 . 31 :Figure 4 . 32 :

 4864427428429430884431432 Fig. 4.28 respectively. The value of K p required to achieve a phase margin of 60˚is 0.7542 and 0.7406 to set a damping factor of 0.6. Both values are very closed because P M ≈ 100 • ζ 0 . The Bode diagram of the open-loop transfer function is plotted in Fig. 4.29 with the transfer function of the plant and the one of the PI controller. Transient simulations are performed. A current step of 5 mA is applied at 10 µs and relaxed at 20 µs in Fig. 4.30. The voltage undershoot in 5% of the voltage reference and the recovery is 500 ns. The solution offers a better cross-over frequency than previous controllers and the transient results are better (as compared to Fig. 4.9 for example). Fig. 4.31 and Fig. 4.32 show the dispersion of the control-to-output voltage transfer function for load range from 1 mA to 10 mAand a reference voltage range from 0.5 V to 0.8 V respectively. The load current variation has the same impact as in the voltage mode control. A phase margin degradation at low load current is expected. On the contrary the voltage reference has a strong impact. A resonance appears at the lowest voltage reference (0.5 V ) meaning that the PI control strategy will be inefficient. A PID controller would be required to mitigate this effect. As a conclusion the control using a positive current feedback scheme is less robust than the voltage mode strategy. Nonetheless, robustness is similar regarding the load current.

2T 5T 2 Figure 4 . 33 :

 2433 Figure 4.33: Steady-state voltage across the flying capacitor with sliding-mode control

Figure 4 . 34 :

 434 Figure 4.34: Hybrid automaton of the sliding mode

Figure 4 . 35 :

 435 Figure 4.35: Hybrid automaton of the sliding mode with the induced mode

  , the model is derived for the 2:1 SC converter. The targeted output voltage is 0.6 V and the load current is 5 mA. The Bode diagram of the transfer function of the loop-delay-to-output voltage is shown in Fig. 4.37 in the s and z domain respectively. The transfer function has one pole and the PI controller must be selected similarly as for the linear frequency modulation. The design of the controller follows the same steps as in Section 4.2. The transfer function of the plant is

Figure 4 . 37 :Figure 4 . 38 :

 437438 Figure 4.37: Bode diagram of the loop-delay-to-output voltage transfer function

  the converter will operate at an infinite switching frequency and the trajectory will be maintained on the sliding line g(x) = 0. The value of the switching frequency is decreased when the hysteresis window is increased. The control is implemented in Matlab/Simulink with a fixed hysteresis to evaluate the sliding mode behavior. The simulations are performed for k = 0.4. A load transient of 1 mA and 5 mA is applied at 1 µs and relaxed at 2 µs in Fig.4.41 and Fig. 4.42

Figure 4 . 40 :

 440 Figure 4.40: Diagram of the loop delay modulation of the sliding mode control with an hysteresis band and rejection of output voltage static error

Figure 4 . 41 :Figure 4 . 42 : 100 Chapter 4 .

 4414421004 Figure 4.41: Transient simulation with a load transient of 1 mA

Figure 4 . 43 :

 443 Figure 4.43: Control-to-output transfer function

Figure 4 . 44 :Figure 4 . 45 : 104 Chapter 4 .

 4444451044 Figure 4.44: Audio susceptibility of the sliding-mode without the external loop and of the open-loop power stage

Figure 4 . 46 :Figure 4 . 47 : 106 Chapter 4 .

 4464471064 Figure 4.46: Load transient simulation (sliding mode in Fig. 4.40) with a 5 mA load step

Figure 4 . 48 :

 448 Figure 4.48: Diagram of control through the steady-state voltage across the flying capacitor

Figure 4 . 50 :Figure 4 . 51 :

 450451 Figure 4.49: Control-to-output transfer function

Figure 4 . 52 :

 452 Figure 4.52: Diagram of control through the steady-state voltage across the flying capacitor with a linear loop

Figure 4 . 53 :Figure 4 . 54 : 112 Chapter 4 .Figure 4 . 55 :UTBB 1 Figure 5 . 1 : 114 Chapter 5 Figure 5 . 3 :

 4534541124455151114553 Figure 4.53: Load transient simulation with integral external loop

FlexibilityFigure 5 . 4 :

 54 Figure 5.4: Diagram of the multiphase ring oscillator.

Figure 5 . 5 :Figure 5 . 6 :Figure 5 . 7 :

 555657 Figure 5.5: Configurations of the flying capacitor over the different ratio

  large value of resistance requires an extra metal rail in the top level to maintain the ESR as low as possible. The insertion of the MIM capacitors modifies the sharing of the power grid metal resources. The selected power grid is shown in Fig.5.8 and the MIM pattern in 5.9. The upper metal level is routed vertically and the lower metal level is routed horizontally. The MIM is thus regularly opened in order to connect the two metal levels. This degrades the MIM area and as a consequence the flying capacitor values. The assembly of the MIM capacitors and the power grid is presented in Fig.5.10. This configuration allows fast routing because the MIM and the power switch cells have the same pitch. The width of MIM is fixed and determined by the pitch while the length depends on the value of L in Fig.5.4. The performances of the converter depends on the ESR value of the MIM capacitors but also on the parasitic coupling. The value of the flying capacitors and the parasitic capacitances must be evaluated using Q3D Extractor, a 3D electromagnetic field simulator[105]

5 . 11 .Figure 5 . 8 :Figure 5 . 9 :Figure 5 . 10 :Figure 5 . 11 :Figure 5 . 12 :

 5115859510511512 Figure 5.8: Layout of the power grid

AFigure 5 . 14 : 1 V

 5141 Figure 5.13: Diagram of the test-chip

Figure 5 . 16 :

 516 Figure 5.16: Cross section of the circuit

Figure 5 . 17 :Figure 5 . 18 :Table 5 . 3 :

 51751853 Figure 5.17: Board for chip testing

Figure 5 . 19 :Figure 5 . 20 :Figure 5 . 21 :Figure 5 . 22 : 3 Figure 5 . 23 : 3 Figure 5 . 24 :Fig. 5 .

 519520521522352335245 Figure 5.19: Oscillation frequency versus the voltage supply of the ring oscillator

Figure 5 . 25 :Figure 5 . 26 :Figure 5 . 27 :

 525526527 Figure 5.25: Switching current of the driver as a function of the switching frequency for various sizes of switch

Figure 5 . 28 : 132 Chapter 5 .

 5281325 Figure 5.28: Diagram of the PI controller with programmable feedback network and follower mode

Figure 5 . 29 :

 529 Figure 5.29: Schematic of the AB amplifier and its biasing circuit

32 TheFigure 5 . 30 :

 32530 Figure 5.30: Layout and pin map of the second test-chip

  of the reference voltage. The reference voltage is swept from 0.4 V to 1.8 V and the oscillator frequency is measured. 45 samples are evaluated and the results are presented in Fig.5.33. The start-up of the bench follows a special sequence. The amplifier starts first and the oscillator is activated a few µs latter. Otherwise the oscillator can enter in an unstable operation with non-uniform square waves and a high frequency due to the propagation of a glitch through the ring.. The parametric tests indicate a typical trend of corner fabrication and the spread of the measurements can be interpreted as a mismatch. The measurement setup is simulated with a typical corner and post layout extractions (resistor and capacitor).

Figure 5 . 31 :Figure 5 . 32 :

 531532 Figure 5.31: Picture of the second test-bench

3 Figure 5 . 34 :

 3534 Figure 5.33: Frequency versus reference voltage

3 Figure 5 . 35 :

 3535 Fig. 5.40 respectively. The recovery time of the negative load transient is around 200 ns.

Figure 5 . 36 :Figure 5 . 37 :Figure 5 . 38 :Figure 5 . 40 :

 536537538540 Figure 5.36: Efficiency versus output current for various voltage references

Figure 5 . 41 :

 541 Figure 5.41: Rising reference tracking for the 2:1 ratio from 0.5 V to 0.8 V at I load = 100 mA, output voltage and reference voltage

Figure 5 . 42 :Figure 5 . 43 :Figure 5 . 44 :Figure 5 . 46 :

 542543544546 Figure 5.42: Falling reference tracking for the 2:1 ratio from 0.8 V to 0.5 V at I load = 100 mA, output voltage and reference voltage

Figure 5 . 47 :

 547 Figure 5.47: Peak efficiency vs power density of recent published integrated inductive and capacitive DC-DC converters

6. 1

 1 Motivations and contextBody-biasing has been introduced as an assist technique in Section 2.4.4. The body effect of the transistor is exploited to speed-up the digital block or to decrease the leakage current. The configuration of body-biasing in CMOS bulk technology is depicted in Fig.6.1. NMOS and PMOS transistors are in a P-well and in an N-well respectively. The P-well is isolated from the substrate through a deep N-well to apply separated voltages to the NMOS P-well and to the grounded substrate. The deep N-well exhibits the same bias voltage as the one of the PMOS N-well. The body biasing voltage is denoted vbb.

Figure 6 . 1 :Figure 6 . 2 :Figure 6 . 3 :

 616263 Figure 6.1: Cross section of a CMOS inverter in bulk technology.

CFigure 6 . 6 :

 66 Figure 6.6: Diagram of the proposed architecture for a negative voltage regulator

Figure 6 . 7 :

 67 Figure 6.7: Schematic of the voltage sensor with a programmable resistive divider

Figure 6 . 8 :

 68 Figure 6.8: Schematic of the proposed architecture for the negative voltage regulator

Figure 6 . 9 : 8 N

 698 Figure 6.9: Timing diagram of the clocks and the transistor states in the negative SC converter in Fig. 6.8

  on and Rb. The voltage at node A is equal to V s what maintains the transistor N B off. Thus the voltage at nodes A and B are alternatively switched between V s and V s + 1.8 V , ensuring that transistors N 1A and N 1B are properly driven independently from the value of the output voltage. The PMOS bootstrap driver depicted in Fig. 6.13 has a similar behavior. The capacitors C P A and C P B are initially discharged. The gate capacitors of transistors P 1A, P 1B, P A and P B are represented by Cg P A1 , Cg P B1 , Cg P A and Cg P B respectively. During the first phase of operation, clk2 = H (1.8 V ) and clk1 = L (0 V ). The voltage at node C is pulled to ground through the resistance of the clock buffer, Rb, as shown in Fig. 6.14. The voltage at node D is equal to 1.8 V since C P B is discharged. The transistor P B is thus turned-on imposing that the transistor P A remains off. The capacitor C P B charges to V s -1.8 V through R on and Rb. Then in the second phase of operation, clk2 = L (0 V ) and clk1 = H (1.8 V ). Similarly to node D in the first phase, the voltage at node C is tied to 1.8 V since the capacitor C P A is discharged. This causes the transistor P B to turn off. The voltage at node D is evaluated from the charge redistribution between Cg P B1 , Cg P A and CP B as shown in Fig. 6.15 and

Figure 6 . 10 :

 610 Figure 6.10: Diagram of the low-side NMOS driver

Figure 6 . 11 :

 611 Figure 6.11: Equivalent circuit of the low-side NMOS driver during the first phase of operation

Figure 6 . 12 :Figure 6 . 13 :Figure 6 . 14 :Figure 6 . 15 :

 612613614615 Figure 6.12: Equivalent circuit of the low-side NMOS driver during the second phase of operation

Fig. 6 .Fig. 6 .

 66 Fig. 6.17b. Their implementations require only a P well biased with the same voltage as the substrate what minimizes the area. The bottom plate parasitic capacitor is the BOX capacitor. The BOX capacitor can be added to the MOS capacitor by connecting the gate (top plate for NMOS and bottom plate for PMOS) to the back gate (bottom plate for NMOS and top plate for PMOS) as shown in Fig. 6.16d, Fig. 6.16f, Fig. 6.17c and Fig. 6.17e respectively. The configuration of the PMOS in Fig. 6.17c is not suitable because the junction formed by the substrate and the Nwell conducts when the bottom plate is tied to the negative voltage. The same issue arises for the low threshold voltage NMOS transistor in Fig. 6.16e. In Fig. 6.17e

Figure 6 . 16 :Figure 6 . 18 :

 616618 Figure 6.16: NMOS Capacitor configurations

Figure 6 . 19 :Figure 6 . 20 :Figure 6 . 21 :

 619620621 Figure 6.19: Output resistance of the ideal negative SC converter or with a bottom plate parasitic ratio of 10%

Figure 6 . 22 :Figure 6 . 23 :Figure 6 . 24 :

 622623624 Figure 6.22: Equivalent capacitance of the converter load as a function of the diode voltage over process corner and temperature variations

Figure 6 . 25 :Figure 6 . 26 :

 625626 Figure 6.25: Schematic of the current-starved oscillator

  6.27. The output of the controller drives the input of the VCO, V ctrl . The feedback voltage is connected to the positive input while the reference voltage is fed to the input of the feedback network. The signals are inverted regarding the classical implementation because of the negative voltage. During the operation, if the negative voltage increases, the feedback voltage will increase. The error signal defined as V f b -V ref will increase and by the way the switching frequency as well. The output voltage will decrease to reach the targeted value. A bandgap voltage reference gives an nearly constant reference voltage of 1.2 V over temperature. This reference fixes the common mode voltage of the operational amplifier and calls for a NMOS input differential pair. The operational amplifier is depicted in Fig. 6.28. The differential pair N M and N P is cascaded with a simple common source amplifier P 3. An RC network compensates the amplifier to ensure enough stability margin. The biasing is performed by transistors N 1, N 2 and N 3 and the biasing current is determined by the resistance, R bias . A large value is required to set a low biasing current but this solution avoids any complex biasing circuit at the expense of the silicon area for the resistance, R bias . The specification of the operational amplifier are determined by the performances the frequency modulation loop. The PI parameters are K p = 10.1 and T i = 86.2 µs. The bandwidth of the amplifier is 10 M Hz what ensures enough stability margin over process and temperature variations. The Bode diagram is shown in Fig. 6.29.

Figure 6 . 27 :Figure 6 . 28 :Figure 6 . 29 :Figure 6 . 30 : 6 Figure 6 . 31 :Figure 6 . 32 :

 6276286296306631632 Figure 6.27: Schematic of the PI controller

Chapter 5

 5 is dedicated to the design of a SC converter power stage in CMOS 28nm FDSOI. The architecture is compatible with a digital design flow in the technology. Experimental results confirm the satisfying operation of the power stage and a good figure of efficiency. Then the implementation of a multiphase SC converter with a linear frequency-modulation voltage-loop control is covered. Experimental results confirm the theoretical statements and established satisfying transient behaviors. Chapter 6 presents a side work to the PhD mainstream. The application of a dedicated SC converter to the body-biasing function is successfully demonstrated. Results are satisfying and highly promising for a low power implementation of the body-biasing function on a large scale implementation. Sampled-data modeling was used again to support the design. As a conclusion the above-mentioned contributions validate the proposal of an original structure of SC converter compatible with a digital block design. The electrical performances are in line with the best-in-class results using MIM capacitors. An underlying contribution is related to the successful application of sampled-data modeling to the case of the SC converters. A pertinent contribution is then established in CMOS 28nm FDSOI with respect to local power supply of large digital SoCs. The PhD results are scalable with silicon technology and capacitor technology. Unfortunately the duration of the PhD work has let several issues unattended. The SC converter offers a multi-ratio cell that must be adequately selected depending on the instantaneous voltage reference and load current. A dynamic selector (gear box) is needed. From theoretical point of view, sampled-data modeling is useful to study the stability of a closed-loop system subject to bifurcation and chaos as the SC converter. It is important to be able to confront instable conditions to experimental confirmations what means to fabricate voluntarily badly designed converters.

Figure A. 1 :

 1 Figure A.1: HySim flow

Figure C. 1 :Figure C. 2 :Figure C. 3 :Figure C. 4 :Figure C. 5 :Figure C. 6 :Figure C. 7 : 1 Figure C. 8 :Figure C. 9 :Figure C. 13 :Figure C. 17 :Figure C. 21 :Figure C. 33 :

 123456718913172133 Figure C.1: Switching current of the driver as a function of the switching frequency for various size of switch: ratio 3:2

Fig. 3 .

 3 11, Fig. 3.12 et Fig. 3.13. La résistance de sortie est comparée avec les autres modèles en Fig. 3.14. Le modèle échantillonné et moyen donnent les mêmes résultats. D.3.2 Bilan des pertes et optimisation Le bilan des pertes permet de calculer le rendement du convertisseur et par la suite de l'optimiser. Les pertes proviennent d'abord de la dissipation d'énergie dans la résistance de sortie. Ces pertes dépendent de la valeur de la résistance et croissent avec le carré du courant de sortie. Les principaux contributeurs dans la limite basse fréquence sont les valeurs des capacités volantes et dans la limite haute fréquence, ce sont les effets résistifs (résistance à l'état passant des interrupteurs et résistances séries des capacités) qui dominent. Les effets parasites dus à l'implémentation physique des capacités et des interrupteurs viennent s'ajouter. Les transistors introduisent des pertes en commutation par leurs capacités de grille. Ces pertes sont proportionnelles à la taille des transistors et à la fréquence de découpage. Les ca-Conversion DC-DC à capacités commutées 233 pacités présentent des couplages entre le substrat et leurs électrodes. Ces couplages sont pris en compte par des capacités parasites qui sont chargées et déchargées au cours du fonctionnement. Ces pertes sont proportionnelles à la taille des capacités et à la fréquence de découpage. Toutes les capacités ne présentent pas les mêmes couplages suivant le type d'implémentation. Le tableau 3.3 donne qualitativement la variation des pertes en fonction des dimensions et des paramètres de fonctionnement.On peut ainsi optimiser le rendement du convertisseur pour un objectif de résistance de sortie donné. Cet objectif dépend de la valeur maximale du courant de sortie et de la tension de sortie désirée. Généralement on commence par fixer la valeur de la capacité volante car c'est elle qui détermine la surface occupée dans le cas d'un convertisseur entièrement intégré. On fait ensuite varier conjointement la fréquence de découpage et la taille des transistors pour atteindre le point optimal.

Fig. 3 .Fig. 3 .Fig. 4 .D. 5 DémonstrateurFig. 6 . 6 .

 334566 Fig. 3.17. Le convertisseur est optimisé pour plusieurs type de capacités et pour plusieurs valeurs de surface. La densité de puissance est aussi une figure de mérite très répandue car elle permet une comparaison et une mise en évidence des compromis. La Fig. 3.18 montre ainsi que la densité de la capacité est primordiale pour obtenir des rendements élevés à forte densité de puissance. En revanche à faible densité de puissance les couplages parasites deviennent prépondérants.

  de performance. Les convertisseurs à capacités commutées sont d'excellents candidats grâce à leur potentiel d'intégration et leur faible coût, bien que les convertisseurs inductifs, qui nécessitent des technologies spécifiques, obtiennent de meilleurs rendements. L'architecture retenue consiste a placer les capacités volantes au dessus du coeur numérique et les interrupteurs de puissance autour, afin de limiter la surface de silicium consommée. Le chapitre 2 dresse l'état de l'art des techniques à faibles consommations utilisées dans les systèmes-sur-puces. Il permet d'établir les problématiques mais aussi les défis quand à l'intégration d'une alimentation. Le chapitre 3 expose les fondamentaux de la conversion à capacités commutés en allant de la modélisation du comportement jusqu'à l'analyse des pertes en passant Conclusion 241 par l'analyse en petits signaux. Le chapitre 4 détaille la régulation de tels convertisseurs. L'implémentation ainsi que les méthodologies de dimensionnement de régulations linéaires et en mode glissant sont présentées. La modélisation dites échantillonnée est largement utilisée pour les démonstrations. Le chapitre 5 présente l'architecture du convertisseur dans la technologie 28nm FDSOI de STMicroelectronics. Des prototypes ont été fabriqués pour évaluer le rendement mais aussi les performances d'une régulation linéaire avec une modulation de fréquence.

  Relative sizes of inductors tend to decrease while the switching frequency of the DC-DC converters increases. Since the switching losses increase, a lot of efforts are made to improve or maintain high efficiency. TPS8267 series by Texas Instrument are examples of commercial product where a 600 mA step-down DC-DC is integrated along with the inductor and input/output capacitors. A maximum efficiency of 90% is reported as well as a quiescent current of 17 µA during PFM 15 operation. Those PMICs significantly reduce the BOM16 and board area.

	20	Chapter 2. Literature review
	presented in [63].
		13 (heterogeneous ar-
	chitectures). A comparative analysis of commercial PMICs 14 published in 2010 is

Table 3 .

 3

1: Parameter of the 2:1 SC converter considered as an illustration vehicle

  1 , starts at t = t n . Then the automaton jumps to state S 2 at t = t n + d 1n , to the state S N at t = t n + d (N -1)n and finally returns to the state S 1 at t = t n + T n . Thus the nth-switching cycle is denoted [t n , t n + T n ] where T n is the duration of the nth

	cycle. The switching instants between the state are set manually in open-loop or
	imposed by a control law in closed-loop. Thus linear or hysteresis controls can be
	described with this uniform approach without any restrictions.

  = t n . We denote x n and x n+1 , the state vectors at time t n and t n + T n respectively. The input vector, U is assumed constant over a cycle (this is generally true since we consider power supplies are established) and at t n becomes u n . The output vector is denoted y n . The sampled-data model is

	S 1	1 )	S 2
	S N		S N -1
	Figure 3.10: Periodic orbit in steady-state operation
	system at t

11.4 11.5 11.6 11.7 11.8 11.9 12 0.36 0.37 0.38 0.39 0.4

  5 • 10 -8 7.5 • 10 -8 1 • 10 -7

	Chapter 3. Fundamentals of Switched-capacitor converter
		0.4
			SDM
		0.35	PWL
		0.3
		0.25	0.4
	Vout [V]	0.2	0.39
		0.15	0.38
		0.1	0.37
		0.05	0.36
			11.2	11.3	11.4	11.5	11.6	11.7	11.8
		0
		0	2	4	6		8	10
					time [µs]
	Figure 3.11: Transient simulation of a simple 2:1 SC converter: PWL model and
	sampled-data model
		0.4
			SDM
		0.35	PWL
		0.3
		0.25
	Vout [V]	0.2
		0.15
		0.1
		0.05
		0
		0	2	4	6		8	10	12
					time [µs]
	Figure 3.12: Transient simulation of a four phases 2:1 SC converter with equal
	interleaving times: PWL model and the sampled-data model
		0.4
			SDM
		0.35	PWL
		0.3
		0.25
	Vout [V]	0.2
		0.15
		0.1
		0.05
			11
		0
		0	2	4	6		8	10	12
					time [µs]

.4 11.5 11.6 11.7 11.8 11.9 12 0.36 0.37 0.38 0.39 0.4 Figure

	Losses			39
		10 3
			R out static model
			R out non linear average model
			R out SDM
			R SSL
	Rout [Ohm]	10 2	R FSL
		10 1
		10 7 10 0	10 8	10 9
			Switching frequency [Hz]

3.13: Transient simulation of a four phases 2:1 SC converter with non-equal interleaving times: PWL model and the sampled-data model

Table 3

 3

	.3. A

  . The system has two switching instants, d n and T n , and the system is

	52	Chapter 3. Fundamentals of Switched-capacitor converter
	written as follow
		xn+1 ≈	∂f ∂x n	xn +	∂f ∂u n	ûn +	∂f ∂d n	dn +	∂f ∂T n	Tn	(3.86)

  .36: Diagram of the loop delay modulation of the sliding mode control

	now
	xn+1 ≈	∂f ∂x n	xn +	∂f ∂u n	ûn +	∂f ∂φ n	φn	(4.118)
	xn+1 ≈ Φ 0 xn + Γ u ûn + Γ φ φn		(4.119)
	vout ≈ C xn + Dû n				(4.120)
	with
	∂f
	∂x n

Table 5 .

 5

		Ion /I of f	R on	C gate
	Normal	13.8 10 6 8.5 Ω 100 f F
	Foward biasing 17.6 10 3 5.8 Ω 100 f F
	DT scheme	17.3 10 6 5.8 Ω 128 f F

1: Ion /I of f ratio, R on and C gate values comparison for the various configurations of the power switch with dynamic threshold in 28nm FDSOI age up to 1.8 V with the flip-well architecture in Fig. 5.3. The high-side PMOS

Table 5

 5

	.2

used for the thin and thick oxide logic respectively. Special care is brought for the power routing. The ground and the output voltage are connected to lateral pins using a strong horizontal Alu-cap grid. The digital power grid is thus connected

Table 5 . 2

 52

		Upper thick metal
	Top plate	Vias
	Bottom plate	Lower thick metal

: Area summary Figure 5.15: Pictures of the fabricated test-chip

Table 5 . 4

 54

	The frequency modulation control	135
	MIM cap area	0.4148 mm 2
	PG area	0.5640 mm 2
	Core area	0.5224 mm 2
	Switch area	0.0420 mm 2
	AB area	0.0040 mm 2
	Network area	0.0140 mm 2
	Total area	0.6543 mm 2
	MIM effective density	73%
	A switches/A digital	8%
	A Active/A digital	11.5%

: Area summary amplifier operates near its supply voltage and requires at least a margin of 200 mV

  mm 2

	31.2%	15×	26.9%	3.6%	5×	11.5%

Table 5 .

 5 5: Comparison with state-of-the-art

Table 6 .

 6

			0.3158 0.6842
	2	-200	0.3000 0.7000
	3	-300	0.2857 0.7143
	4	-400	0.2727 0.7273
	5	-500	0.2609 0.7391
	6	-600	0.2500 0.7500
	7	-700	0.2400 0.7600
	8	-800	0.2308 0.7692
	9	-900	0.2222 0.7778
	10	-1000	0.2143 0.7857
	11	-1100	0.2069 0.7931
	12	-1200	0.2000 0.8000
	13	-1300	0.1935 0.8065

1: Parameter values of the resistive divider

  .18. The state-space model of the negative SC converter is given in Appendix B.2 and the model with a bottom plate parasitic capacitor in Appendix B.3. The flying capacitor is denoted C f ly , the bottom plate parasitic capacitance is C bot and the on-state switch resistances are indicated as

  and Fig.6.21 that the parasitic capacitance modifies the output resistance by a constant value and the converter ratio becomes frequency dependent. Therefore the bottom plate parasitic capacitor must

	164			Chapter 6. Body-bias generator
	Top
	Configuration Bot	Fig.	C	Cp	Area	Comments
	NMOS RVT P + N +	6.16a N +	C M OS	C BOX	+
	NMOS LVT	6.16b	C M OS	C BOX	-
	NMOS RVT Bottom-back-gate P-SUB P-WELL 6.16c	C M OS	Deep N-well P-well	--	reverse biased Junction highly
	NMOS RVT Top-back-gate	6.16d	C M OS + C BOX	P-well Deep N-well	--	Charge recycling
	NMOS LVT Bottom-back-gate	6.16e	C M OS	P-sub N-well	-	Diode conduction
	NMOS LVT Top-back-gate	6.16f	C M OS + C BOX	P-sub N-well	-	Charge recycling
	PMOS RVT	6.17a	C M OS	C BOX	-
	PMOS LVT	6.17b	C M OS	C BOX	+	Charge recycling
	PMOS RVT Bottom-back-gate	6.17c	C M OS + C BOX	P-sub N-well	-	Diode conduction
	PMOS RVT Top-back-gate	6.17d	C M OS	P-sub N-well	-	Charge recycling
	PMOS LVT Bottom-back-gate	6.17e	C M OS + C BOX	P-well Deep N-well	--	Junction highly reverse
	PMOS LVT Top-back-gate	6.17f	C M OS	P-well Deep N-well	--	Charge recycling
		Table 6.2: Capacitor configurations

  ly and τ 2 = R on C load .

	200	Chapter B. State space model
	B.2 Model of a negative SC converter

  .6). Des points de fonctionnement définis par une fréquence et un niveau de tension permettent d'adapter le besoin énergétique et celui de la performance de manière beaucoup plus fine. Les changements s'opèrent dynamiquement grâce à un contrôleur. La température et le type de process sont mesurés afin de sélectionner les points de fonctionnement. L'usage de cette technique est limité par les temps de transition entre chaque point et reste la plupart du temps utilisé pour les blocs qui consomment beaucoup. Plus généralement, ces techniques restent limitées par le nombre de régulateurs externes car le système peut rapidement devenir complexe. Afin de réduire le courant de conduction sous le seuil ou d'augmenter le courant à l'état passant du transistor, les caissons des transistors peuvent être polarisés pour exploiter le body effect. Un exemple est donnée en Fig. 2.7. On considère la polarisation inverse quand V bbp > vdd et V bbn < gnd. La tension de seuil des transistors est augmentée réduisant le courant de fuite et les performances. Cette technique s'utilise principalement dans les modes de non utilisation. Au contraire pour ac-W /mm 2 est régulièrement prise comme référence pour un systèmesur-puce standard. Un convertisseur qui occuperait seulement 10% de la surface du circuit numérique doit donc présenter un densité de puissance de 10 W /mm 2 . Il est à la fois difficile d'obtenir une densité de puissance et un rendement élevé. Conversion DC-DC à capacités commutées 231 et S 4 sont allumés dans la première phase alors que les interrupteurs S 1 et S 3 sont éteints. La capacité volante se charge entre l'entrée et la sortie. Dans la seconde phase, les interrupteurs S 2 et S 4 sont éteints et S 1 et S 3 s'allument. La capacité volante est maintenant connectée en parallèle avec la sortie. Si l'entrée et la sortie sont interverties, le convertisseur devient un doubleur de tension. Le rendement de ce type de convertisseur ne peut pas idéalement atteindre 100% à cause des pertes par transfert de charge. En effet lorsque deux capacités initialement chargées à des valeurs différentes sont connectées en parallèle (Fig. 3.2), les charges sont réparties et l'énergie disponible est réduite. L'énergie perdue est donnée par (3.5). L'exemple de ce convertisseur abaisseur est utilisé tout au long du manuscrit. Les valeurs des paramètres sont donnés dans le tableau 3.1. Un convertisseur à capacités commutées peut être représenté par un transformateur avec une résistance série à sa sortie (Fig. 3.3). Le ratio de transformation est donné par la topologie du convertisseur et la résistance de sortie symbolise la chute de tension à la sortie quand le convertisseur est chargé. La valeur analytique de cette Cette résistance symbolise les pertes par transfert de charge. Pour calculer la résistance dans la limite haute fréquence, on ne néglige plus cette fois-ci les effets résistifs. Résumé étendu un circuit RC et une source de tension (Fig. 3.7). La valeur de la source de tension dépend de la tension avant que les interrupteurs de chaque phase ne se ferment. En calculant la puissance instantanée dissipée dans chaque phase, on peut déduire la résistance équivalente par phase (3.23). La résistance en fonction de la fréquence est enfin la somme des résistances par phase (3.24). Le résultat est comparé avec le modèle précédent en Fig. 3.8 et montre clairement une meilleure précision.

	État de l'art 230	229 Chapter D. Résumé étendu
	D.2.3 L'alimentation d'un circuit et ses défis le facteur d'intégration des convertisseurs. Des stratégies d'alimentation avec de la
	conversion DC-DC intégrée ont également vu le jour comme dans le cas du pro-
	Le réseau de distribution de la puissance dans un système-sur-puce constitue une cesseur POWER8 d'IBM [69] où des régulateurs linéaires assurent l'ajustement de
	partie essentielle compte-tenu de l'augmentation significative de la densité de puis-la tension d'alimentation. Malgré leur faible efficacité énergétique, ils contribuent
	sance. Ses performances dépendent de la conception de la carte électronique, du à améliorer le profil énergétique du système. Des convertisseurs inductifs et capac-
	choix du boitier et de la stratégie d'alimentation. Une illustration est donnée en itifs totalement intégrés apparaissent aussi dans l'état de l'art. La Fig. 2.13 donne
	Fig. 2.8. La puissance est acheminée depuis la batterie jusqu'aux consommateurs le rendement en fonction de la densité de puissance pour les points de l'état de La modélisation des convertisseurs à découpage est souvent très spécifique [83].
	par l'intermédiaire des régulateurs de tension, des pistes de la carte, des boules du l'art les plus pertinents. D'autres figures de mérite peuvent être utilisées [71-73] La modélisation échantillonnée a donc été introduite comme une approche uni-
	boitier et de la grille de distribution dans le circuit. A chaque apparition d'une dis-mais celle-ci donne un bon critère d'évaluation en première approche. La densité forme et généralisée. Un convertisseur à découpage est en effet un système hy-
	continuité, il y a des effets parasites de type résistifs et inductifs qui sont compensés par l'ajout de capacités de découplage. Le réseau de distribution de puissance est contraint par l'objectif d'impédance (2.10) imposé par les performances du circuit. Le choix du boitier est crucial car le nombre d'entrées/sorties conditionne le maxi-mum de puissance admissible. Le choix d'une architecture hétérogène ou homogène ainsi que 3D se fait en fonction des performances et des coûts comme montré en Fig. 2.9. bride (Fig. 3.9) où chaque état de l'automate peut être décrit par des équations différentielles. Une telle modélisation est détaillée en [86] et peut donc être ap-de puissance de 1 Les convertisseurs à capacités commutées constituent le meilleurs compromis con-pliquée aux convertisseurs à capacités commutées. On représente chaque état de
	cernant le coût, l'intégration et la performance. La Fig. 2.14 illustre le choix
	d'implémentation. Les interrupteurs de puissance du convertisseur sont situés en
	fonctions analogiques et radio-fréquences. Ils se limitent aux petites puissances car périphérie du bloc à alimenter à la manière du power gating et les capacités sont
	leur rendement est limité par le rapport de la tension de sortie à la tension d'entrée situées au dessus du bloc grâce à l'utilisation de capacités MIM. Autant de con-
	(2.11). On retrouve parfois des convertisseurs capacitifs pour les applications audio vertisseurs que nécessaire peuvent être déployés grâce à une alimentation externe On introduit les multiplicateurs de charge des interrupteurs (3.11). Ils représentent
	mais leur usage reste minoritaire. commune de 1.8 V . les charges qui circulent dans les interrupteurs à chaque phase de fonctionnement.
	Continuer à améliorer le profil énergétique des systèmes-sur-puces avec ce type La valeur calculée est donnée par (3.12) et la résistance réunissant les deux com-
	d'architecture semble difficile. D'abord il est compliqué d'augmenter le nombre de régulateurs externes alors même que la place disponible est de plus en plus réduite. posantes du convertisseur en fonction de la fréquence de découpage est donnée par D.3 Conversion DC-DC à capacités commutées (3.13). Le graphique en Fig. 3.4 donne l'allure de la résistance pour les paramètres
	Par ailleurs les ressources des boitiers ainsi que le réseau de distribution ne sont pas D.3.1 Principe et modélisation du tableau 3.1.

croître la vitesse, la polarisation directe est utilisée: V bbp < vdd et V bbn > gnd. La tension de seuil diminue et le courant à l'état passant augmente.

Les vendeurs de système-sur-puce accompagnent toujours leurs circuits d'un circuit dédié à la gestion d'énergie. C'est le circuit compagnon. Il contient les régulateurs de tension nécessaires pour faire fonctionner le circuit sous n'importe quelle tension de batterie. L'autonomie de la batterie est également mesurée et un chargeur permet de lui restituer de l'énergie à partir d'une prise secteur. Un bus de communication lui permet de dialoguer avec le système-sur-puce notamment lors des requêtes de changement de niveau de tension. Parmi les régulateurs de tension, on retrouve principalement des convertisseurs inductifs pour les grosses puissances car ils assurent théoriquement un rendement de 100%. Dans la réalité le rendement chute à cause des effets résistifs et des pertes par commutation. Ces derniers permettent également d'élever la tension quand cela est nécessaire. Des régulateurs linéaires à faible tension de déchet sont utilisés pour les blocs sensibles tels que les en mesure de délivrer tous les niveaux de tension requis et la complexité est telle que la réactivité de la chaîne d'alimentation se dégrade. Les avancés récentes dans le domaine des composants magnétiques et de mise en boitier ont permis d'augmenter L'architecture Haswell d'Intel

[START_REF] Burton | FIVR -Fully integrated voltage regulators on 4th generation Intel Core SoCs[END_REF]

est celle qui s'approche le plus de cet objectif avec un rendement supérieur à 90% grâce à des inductances à coeur magnétique directement fabriquées sur la puce. Les convertisseurs utilisant des inductances à air démontrent des résultats intéressants pour des densités autour de 1 W /mm 2 alors que les inductances sur silicium proposent de faible densité [43-46]. La densité de puissance des convertisseurs à capacités commutées est essentiellement définie par le type de composant passif utilisé [50-55, 58-60, 74]. Les capacités en tranchée étant les plus denses, elles donnent les meilleurs points dans l'état de l'art [47-49]. Une architecture basée sur des capacités MIM distribuées au dessus du coeur numérique présente un point intéressant [57]. L'état de l'art relate également des convertisseurs résonants [75, 76] et des architectures de convertisseurs cascadés notamment pour tenir de fortes tensions d'entrée [77]. Les convertisseurs à capacités commutées sont composés uniquement de capacités et d'interrupteurs. Un abaisseur par deux est décrit en Fig. 3.1. Les interrupteurs S 2 résistance peut être calculée de différentes manières. La méthode décrite en [74] permet, grâce à l'analyse de la circulation des charges, de calculer le ratio de conversion et les deux limites asymptotiques de la résistance. On peut différencier deux limites de fonctionnement : la limite basse fréquence et la limite haute fréquence. On peut en effet représenter chaque phase par un circuit RC, correspondant à la résistance à l'état passant des interrupteurs et aux capacités volantes. Ainsi quand la période de découpage est faible devant la constante de temps ainsi formée, le convertisseur fonctionne dans la limite haute fréquence et, inversement, quand celle-ci est grande au regard de la période de découpage, le convertisseur opère dans la limite basse. Pour calculer la résistance dans la limite basse fréquence, on néglige tout les effets résistifs. On défini les multiplicateurs de charge des capacités (3.6) pour représenter la quantité de charge en transit quand les interrupteurs se ferment. On déduit ainsi le ratio de conversion (3.9) et l'expression de la résistance interne (3.10). L'équation (3.13) est une approximation de la résistance. Le modèle moyen proposé en [82] est plus précis. Les phases de charge et de décharge sont représentées par 232 Chapter D. l'automate avec la représentation d'état. En échantillonnant le système à chaque transition de l'automate, on peut déterminer la dynamique du système en temps discret (3.38). Connaissant le cycle de l'automate, on peut alors calculer la solution périodique en régime établi dite point fixe (3.44). Comme suggéré dans [87], on peut ainsi déterminer la résistance de sortie avec l'équation (3.47). L'extraction du modèle est faite grâce à un outil propriétaire appelé HySim (Annexe A). Cette méthodologie permet notamment de modéliser des convertisseurs entrelacés. Pour démontrer la pertinence de l'approche, nous avons extrait le modèle pour le convertisseur abaisseur simple, pour le convertisseur abaisseur entrelacé quatre fois avec des temps d'entrelacement égaux ou arbitraires. Les simulations de l'automate et du modèle échantillonné sont données en

Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2015ISAL0043/these.pdf © [T. Souvignet], [2015], INSA de Lyon, tous droits réservés

Low drop-out Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2015ISAL0043/these.pdf © [T. Souvignet], [2015], INSA de Lyon, tous droits réservés

Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2015ISAL0043/these.pdf © [T. Souvignet], [2015], INSA de Lyon, tous droits réservés Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2015ISAL0043/these.pdf © [T. Souvignet], [2015], INSA de Lyon, tous droits réservés

Proportional-integral Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2015ISAL0043/these.pdf © [T. Souvignet], [2015], INSA de Lyon, tous droits réservés

Acknowledgments

APPENDIX A

HySim

HySim is a CAD tool developed by STMicroelectronics. Architectural simulation of switched structures through traditional spice simulator is not easy. Behavioral languages with mixed signal extension such as VHDL-AMS or Verliog-AMS are usually used to achieve fast and accurate modeling. Some behavioral tools like Matlab/Simulink or Scilab are sometimes preferred for architecture description. Hybrid simulations are available in such tools but the model descriptions based on statespace representation is still hard to derive. Manual derivation is also painful and is affected by many errors. HySim is a tool that provides a fully integrated simulation environment for switched systems accessible to electrical design community. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility.

HySim is composed of several parts as described in

Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm 2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application.

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