Les travaux de thèse rapportés dans ce manuscrit sont le fruit de recherches menées au laboratoire IMS, en collaboration avec l'Université de Bordeaux et Thales.

Je tiens en premier lieu à remercier les membres du jury pour l'intérêt qu'ils ont porté à ces travaux et les échanges scientifiques pertinents Je souhaite également remercier les différentes personnes qui ont relu le manuscrit et contribué à cette version finale.

Je remercie chaleureusement Yann, pour ces trois merveilleuses années, très riches sur le plan scientifique, culinaire et culturel. J'en garderai des souvenirs impérissables.

Je tiens à adresser mes sincères remerciements à François, pour notre étroite collaboration qui a rythmé le déroulement de la thèse dans un esprit de plaisiriosité Monkienne de tous les instants.

Merci à tous mes collègues du laboratoire IMS et de l'Enseirb-Matmeca d'avoir contribué à l'excellente ambiance de travail. Je remercie en particulier les membres de l'équipe CAS.

Un grand merci à tous mes amis, dont le fameux groupe CSI '12 (promotion cheval), pour les très bons moments passés ces dernières années, et les nombreux autres à venir.

Je salue et je remercie mes parents pour l'ensemble de leur oeuvre, mon frère et ma bellesoeur qui m'ont promu au rang de Tonton Mouton, et ma "grande soeur" adorée. J'ai passé un merveilleux premier quart de siècle dans une famille formidable, et le prochain s'annonce sous les plus heureux auspices.

Contents

List of Tables

Introduction

The air interface that connects the mobile terminals to the wired network is subject to a rigorous regulation enforced through various communication standards. Next generation wireless communications require a smart and agile use of the spectral resources to increase the data handling capacity of the network.

This trend put severe constraints on the design of mobile device transceivers. They should deal with high data rates, multiple carrier frequencies and various modulation schemes within a very restricted power budget imposed by the limited energy storage of handset terminals.

Chapter 1 exposes the radio communication paradigm and the evolution of radio transmitter architectures. It underlines the trend to increase the flexibility of the wireless transmitters through an increasing use of digital electronics according to the Software Radio principle. The major gain in flexibility is contrasted by a prohibitive energy consumption, especially within the digital to analog conversion operation. The classical conversion schemes are studied and challenged.

Chapter 2 proposes the theoretical study of disruptive conversion schemes together with a suited digital to analog converter topology. It borrows the principle of Delta modulation involved in some data compression systems. The data conversion process deals with the temporal variations of the signal through a differentiating digital coding to significantly improve the conversion efficiency. The signal reconstruction is performed thanks to a custom integrating digital-to-analog converter named the Riemann Pump. The performances of the proposed system are assessed toward radio frequency signal generation.

Chapter 3 describes the design of the Riemann Pump in two targeted integrated technologies.

The first one is a GaN technology dedicated to military applications. The second one is a 65 nm silicon technology adapted to the consumer electronics market. The design of the two circuits is detailed and post-layout simulations are presented to validate the compatibility of the proposed architecture with the chosen technologies and to assess its performances Chapter 4 presents the measurements carried out on the demonstrator realized in the 65 nm silicon technology. The obtained results bring a physical proof of concept. An extension of the test bench testing capabilities is required to go further in the characterization of the prototypes.

Prospects are envisioned to develop a complete transceiver based on the Riemann Pump. Key words: RF transmitters, Data conversion schemes, Software radio, 5G

" The very small value of 10 -16 of negentropy required per bit of information plays, however, a very important role in modern life, and it makes possible to communicate information at a negligible cost. "

Leon Brillouin, Science and Information theory, 1956

In the 50s, Brillouin stated that modern life relies on the possibility to deal with large quantities of information for a minimal cost. In the same decade, the development of the transistor in Bell laboratories led to a physical media allowing to get closer to the theoretical cost of information described by Brillouin. After several decades during which the electronic industry endeavored to follow the Moore's law, standalone devices that can exchange a billion of bits per second fit in one's hand. However, conventional transceiver architectures cannot support the pressing digital convergence while satisfying customer expectations in terms of quality of service, device cost and battery life.

Wireless communication paradigm

In the 2010s, the global amount of information exchanged is still in huge growth, even though it tends to decelerate. In the same time, the proportion of mobile data is rapidly increasing; the connection to the internet becomes more and more nomadic.

Radio frequency transceivers architecture

The connection of wireless terminals to the network is provided by the mean of radio-frequency (RF) electromagnetic waves. Those terminals are able to transmit and receive information carried at high frequencies, while ensuring the compatibility to various standards which set the traffic rules. The data to be transmitted is conditioned within the transmitter chain to be radiated by the antenna, while the receiver chain recovers the data from the signal picked up by the antenna. The classical simplified architecture of RF direct conversion transceivers is represented in Fig. 1.2.

The transmission chain is composed of four main blocks:

• A baseband processor

• A digital to analog converter (DAC)

• A mixer to convert the signal up to the carrier frequency

• A power amplifier The baseband processor encodes the user digital information which is then converted into the analog domain thanks to the DAC. The analog signal is up converted to RF within the analog front-end, and then amplified and transmitted through the antenna.

The receiver chain is composed of dual blocks:

• A low noise amplifier

• A mixer to down convert the signal to baseband

• An analog to digital converter (ADC)

• A baseband processor The RF signal is picked up by the antenna, and amplified by the low noise amplifier. It is then mixed with the carrier frequency so as to recover the baseband data, which is computed by the processor and sent to the user interface. This transceiver architecture is commonly used and implemented in mobile terminals to provide a link to the network.

The growing number of connected terminals and the increasing amount of exchanged data raise congestion issues in the wireless communication space.

Yoan VEYRAC, IMS Laboratory -December 2015

Wireless communication media capacity

The medium used to convey wireless data is the air. This medium is shared between users along three principal axes, to avoid interferences:

• Geographic areas: the wireless data transmission uses radiofrequency signals transmitted thanks to antennas. The received power decreases with the distance to the transmitter.

The network is organized with a cellular pattern, to isolate geographic areas.

• Frequency allocation: the frequency spectrum is divided into channels dedicated to specific services. Several frequency bands are allocated to mobile communications, and those ones are subdivided into channels to handle different users at the same time.

• Time sharing: communications on the same channel in the same area can occur by sharing the time. Different portions of time are assigned to users.

Time slot

Frequency channel

Geographic area

Communication slot The intersection of those three axes defines a communication slot, depicted in Fig. 1.3. To avoid interferences, communication slots must be allocated only once. The capacity and the efficiency of a network depend on the number of communication slots offered, and its adequacy with the local needs. In order to enhance the handling capacity of the wireless network, improving the use efficiency of those three resources will be needed.

• The geographic areas obviously depend on the local density of users; cities need a finer mesh than countryside areas. The setting of cells of different size, associated with different transmitting power, allows to locally adapt the capacity of the network to the need.

• The frequency allocation is the key resource, controlled and delivered by dedicated authorities. Within the whole spectrum, only a few RF bands are allocated to mobile communications. Those bands are shared between several mobile access providers. Those successive divisions result in relatively narrow bands available for users, in the range of several MHz. The re-allocation of frequency bands will help to meet the need of mobile data communications.

• The time is the last dimension to be shared between users. In a same channel, multiple communications can occur thanks to time allocation. However, in the case of intense exchange of data at a given moment, the channel can be saturated. The dynamic allocation of frequency resources along time could improve the traffic fluidity. Instead of the stringent partitioning of frequency bands, those resources could be dynamically re-allocated when needed. It would grant much wider bands when the traffic is sparse, and help to fully use the resources when it is crowded.

Such a radio network is based both on smart network supervision and adaptive radio transceivers.

Mobile terminal transceivers compatibility

The classical transceiver architecture depicted in Fig. 1.2 suffers from a lack of flexibility inherent to the conversion performed in the analog front-end. Such a transceiver usually addresses a given standard, corresponding to a relatively narrow frequency band. However, the increase of the access bandwidth relies on the use of large frequency bands distributed all over the RF spectrum.

Their introduction comes regularly with new standards and their own requirements. Mobile terminals use different transceivers to address the various standards. This trend to increase the number of parts in the chipset of mobile terminals faces pressing limits related to the industry directions and the consumer expectations.

• Bandwidth: transceivers for handsets have to support more and more data rate, on various frequency bands distributed over a multi-GHz frequency range. They have to ensure an adequate resolution over a very wide frequency band.

• Energy consumption: transceivers are one of the most power hungry part of mobile terminals. They must operate at low power to improve battery life of handsets.

• Cost: to address mass market, the transceivers should be low cost. The cost of a chip is related to the die area and the technology used.

The stacking of chips involved in the handset terminals to address different frequency bands and gather data bandwidth cannot conciliate the previous constraints. The cumulated die area of all

Yoan VEYRAC, IMS Laboratory -December 2015 the transceivers turns out large, which impacts the total price of the chips and their integrability in the small volume of a handset terminal. Furthermore, enhancing the total bandwidth thanks to the addition of transceivers would substantially increase the energy consumption since the analog front-end is duplicated for each transceiver. Classical transceivers architectures suffer from a lack of flexibility and they are no more suitable for the expected ubiquitous network.

Our purpose is to develop a disruptive architecture of radio transmitter that can take up the challenge.

The next section describes the evolution of wireless transmitter architectures in the past few decades, and the state-of-the-art trends and realizations that tend to overcome the requirements of tomorrow. Then, a come back to the basics of digital to analog conversion will help to apprehend the limits of the commonly used conversion schemes. It raises the need to develop innovative architectures of transmitters.

1.2 Software radio transmitters 1.2.1 Software radio background

Principle

In order to meet the need of versatility raised by the new wireless communication perspectives, [START_REF] Mitola | The software radio architecture[END_REF] proposed a new paradigm with the notion of software radio (SR) twenty years ago. The idea is to move the limit between the baseband domain and the RF domain within the digital processor, so as to get rid of the rigid analog front-end. The corresponding ideal architecture is depicted in Fig. The ideal SR architecture is composed of 3 blocks:

• A baseband/RF processor

• A wideband digital to analog converter (DAC)

• A wideband power amplifier This architecture proposes to directly compute the modulated signal (or even a combination of multiple signals) within the digital processor, and to convert the whole transmitting band of several GHz to the analog domain thanks to a wideband converter. The output of the converter then needs to be amplified before transmission through the antenna. Software radio offers a perfect flexibility, since it is virtually compatible with all the existing standards falling into the RF domain, and any new standard can be supported thanks to a simple software update.

Furthermore, it allows concurrent transmission of different standards and agile reconfiguration.

Applications

The works on software radio transceivers are motivated by many applications, involving huge markets.

Military market

The flexibility of SR transceivers finds a lot of military applications.

• Interoperability: the US military has been seeking a way to improve the ease and flexibility of communications within and between the services. A huge program called joint tactical radio systems (JTRS) has been launched, without success at the time [START_REF] Goeller | A Technical Review of Software Defined Radios: Vision, Reality, and Current Status[END_REF].

• Secure communications: the intrinsic flexibility of SR transceivers offers a perfect support to operate dynamic changes of the standards to secure communication links in the battlefield.

• Radar: SR transmitters are able to generate various waveforms, including radar signals.

The accurate control of the waveforms allows to enhance the performances of detection [3].

• Electronic Warfare: To control the electro-magnetic spectrum in a battlefield, the use of versatile transceivers is an asset. A lot of applications rely on the use of agile signals generation (jamming, stealth, countermeasures) [4].

Yoan VEYRAC, IMS Laboratory -December 2015

Civil market

The next generation of wireless communication standards (5G) is expected to offer ubiquitous immersive connectivity, relying on a software upgradable platform. Several researches on the network and communication architectures and techniques are led at the moment [5], [START_REF] Pirinen | A brief overview of 5g research activities[END_REF]. The infrastructures would rely on an heterogeneous network with cells of different sizes [START_REF] Bangerter | Networks and devices for the 5g era[END_REF]. The use of device to device communication is envisioned to virtually densify the network [START_REF] Tehrani | Device-to-device communication in 5g cellular networks: challenges, solutions, and future directions[END_REF], and content caching to reduce data duplication [START_REF] Wang | Cache in the air: exploiting content caching and delivery techniques for 5g systems[END_REF]. As for frequency resources, 5G is expected to use as much spectrum as possible [START_REF] Mitola | Accelerating 5g QoE via public-private spectrum sharing[END_REF], divided into 3 frequency ranges for different applications (Fig. 1.5).

100 MHz 1 GHz 10 GHz 100 GHz The sub-6 GHz frequency range ensures a favorable transmission in the air; a data rate higher than 1 Gbps is expected on this band thanks to carrier aggregation. It will be based on an extension of the LTE standard and used by all the devices.

IOT LTE & Wifi evolution

New radio access

The mmW band has a reduced range and could serve in smaller cells [START_REF] Roh | Millimeter-wave beamforming as an enabling technology for 5g cellular communications: theoretical feasibility and prototype results[END_REF], giving access to wide data bandwidth.

The internet of things (IoT) will be deployed in the same time, using the sub-GHz frequency band. The number of connected wireless devices will be in huge growth. Equipping those devices with reconfigurable and low-power transceivers presents a major industrial asset [START_REF] Surligas | Empowering the IoT Heterogeneous Wireless Networking with Software Defined Radio[END_REF].

SR transceivers are in agreement with the implementation of those various techniques which necessitate a high flexibility. Sub-6 GHz and IoT applications are privileged targets for full software radio transmitters. Wireless communication handsets represent the most lucrative market, involving billions of units. It also constitutes one of the most challenging applications.

Chapter 1. Transmitters for ubiquitous network [START_REF] Gilmore | Towards the 5g Smartphone: Greater system capacity, more bands, faster data rates, advanced applications and longer battery life[END_REF] reminds the technical and technological difficulties to reach high bandwidth and high performances at a reduced power to ensure a longer battery life, and above all with a low cost solution.

A lot of researches are oriented toward the evolution of wireless transmission architectures in the direction of flexible solutions.

Directions of research for flexible transmitters

Digital core Analog Front-end

Reconfigurable transmitters

An intermediate step toward SR is software defined radio (SDR), where the analog front-end is reconfigurable thanks to a digital command. SDR transmitters are based on a baseband or intermediate frequency digital to analog conversion, before a final up-conversion in the analog domain. In those architectures, the reconfigurability of the analog front-end is the tricky point [START_REF] Darabi | Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial[END_REF]. Various realizations of SDR transmitters are reported in the literature. [START_REF] Craninckx | A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13 µm CMOS[END_REF] proposes a software defined radio transceiver based on direct conversion with a fractional PLL, enabling carrier frequency reconfiguration. The channel bandwidth is tuned up to 16 MHz thanks to reconfigurable low-pass filters.

[16] exhibits a multiband multimode transmitter dedicated to several wireless communication standards. Multiple paths are specifically tailored to meet the precise requirements of the 2G, 3G and 4G standards; only one band group is activated at once. [START_REF] Analui | A 50 MHz -6 GHz, 2x2 MIMO, reconfigurable architecture, software-defined radio in 130nm CMOS[END_REF] presents a reconfigurable monolithic transceiver working over GHz] frequency band. The transmitter operates with direct up conversion for the highest part of the band, and two-step up conversion for the lower part, to filter the local oscillator harmonics. [START_REF] Yin | A 0.1 -6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS[END_REF] exposes a SDR transmitter covering the [100 MHz -6 GHz] band thanks to two distinct paths. The maximal signal bandwidth of 100 MHz can be used to support intra-band dual carrier aggregated signals. [19] proposes a direct digital to RF modulator to up-convert a 200 MHz sigma-delta coded baseband signal at 5.25 GHz. An auto-tuned passive band-pass reconstruction filter is placed at the output to cancel the digital images.

[20] implements an all-digital RF signal generator using low pass sigma delta modulation and digital mixing. It employs redundant logic and non-uniform quantization, and also proposes to use image bands to reach higher frequencies.

[21] discloses a fully digital multimode polar transmitter. It implements a cartesian to polar converter and a RF-DAC made of current-mode mixers. The local oscillator is generated thanks to a digital PLL. [START_REF] Lu | A 24.7dbm all-digital RF transmitter for multimode broadband applications in 40nm CMOS[END_REF] presents an all-digital quadrature transmitter where I and Q paths are up-converted within power cells thanks to a digital local oscillator. The two paths are then combined into a differential load.

[23] addresses the issue of full duplex operation within an RF IQ transmitter. It proposes an embedded FIR filtering of out of band quantization noise to ease full duplex operation.

[24] employs a digital IQ transmission scheme with 13 bits resolution on each path. The baseband digital signals are digitally mixed and converted into the analog domain thanks to digital to RF amplitude converters. Most of the presented works target specific standards. They propose fully integrated solutions, including the power amplification operation. However, the flexibility of the system remains limited and the bandwidth and consumption performances are not sufficient to address forthcoming applications like 5G.

All-digital transmitters

Another trend consists in removing most of the analog front-end to propose all-digital architectures. The advancement of CMOS technologies makes digital architectures attractive [START_REF] Liang | Digital transmitter design for mobile devices[END_REF]. The development of FPGA motivated a lot of works on the digital architectures.

[26] uses a pulse width modulation scheme to process the baseband signal and a digital IQ upconversion to carry the signal at 800 MHz. This transmitter architecture is implemented on a FPGA and outputs a 1-bit waveform.

[27] implements an innovative digital architecture and assesses it on a very high speed data signal generator. The idea is to represent a given modulation thanks to a finite state machine and to store all the possible symbol transitions in look-up tables. The baseband bit stream moves within the state machine and triggers the right sequences that are outputted as a 1-bit sequence.

A sigma-delta like scheme is employed to perform noise shaping. This approach relies on heavy computational optimizations, but it supposes that the signal is representable by a finite state machine, which limits its applicability.

[28] describes an FPGA-based 1-bit all-digital transmitter using a sigma-delta modulator before digital up-conversion. It demonstrates real-time processing on an FPGA for a signal bandwidth of 2 MHz centered at 0.8 GHz.

[29] implemented a transmitter architecture with sigma-delta baseband processing and digital up-conversion. The baseband scheme is performed with an FPGA which outputs are fed to a multiplexer, together with a high speed clock generated with an external clock generator. The output is then amplified with a switched mode power amplifier.

Most of the presented architectures rely on the use of a digital 1-bit FPGA output to drive a switch-mode power amplifier, with the implementation of different kinds of digital signal conditioning. They demonstrate the interest of such digital techniques to address reconfigurable radiofrequency transmission. On those all-digital transmitters, the digital up-conversion is performed with a multiple of the baseband or intermediate frequency clock, so that the output RF frequency has an integer relationship with the working frequency. This issue has been noticed by [START_REF] Roverato | A configurable sampling rate converter for all-digital 4g transmitters[END_REF]; in this reference, a sampling rate adapter is proposed. This constraint of sampling rate and carrier frequency mitigates the flexibility of the system, especially when it comes to multi-standard and multi-band concurrent transmission. Furthermore, the total available bandwidth is limited because the conversion before the digital up-sampling is performed at baseband or intermediate frequency, often involving sigma-delta modulation.

All digital transmitters are attractive because they remove most of the analog components.

The proposed architectures are easily implementable and portable to new technological nodes.

However, the signal bandwidth is still limited to several tens of MHz, and most of the presented circuits are dedicated to a specific standard. The consumption of the transmitters is difficult to assess because of their implementation on an FPGA.

RF-DACs

Even though reconfigurable analog and all-digital transmitters turn out to exhibit features of software defined radio, that is, digital reconfigurability and a relative flexibility, they do not manage to deal with wideband modulated signals or concurrent transmission of a large number of signals in different bands. Those features could be offered by full software radio transmitters, giving an ideal platform to develop large cognitive radio networks [START_REF] Balasubramanian | Ultimate Transmission[END_REF].

To achieve this kind of architecture, the digital to analog stage has to convert the whole band of transmission, of several GHz. In this way, the complete RF waveform is transmitted, containing any combination of signals with any kind of modulation schemes and bandwidth. Referring to the software radio transmitter basic architecture (Fig. 1.4), it needs a performant digital pro- cessing core, a wideband digital to analog converter, and a power amplification stage.

The digital to analog converter is particularly critical since it has to ensure a good signal quality over the whole RF spectrum with a low power operation. Plethora of DACs are presented in the literature, with diverse operating frequency and number of bits in the conversion.

[32] implements a 12b current-steering DAC, with specific circuit implementation to limit the mismatching and keep the non-linearities under the LSB level. A segmented architecture is chosen, with 6 binary and 6 unary weighted input bits.

[33] proposes a pseudo segmented current-steering DAC working at 28 GSps, with 6 bits, that implements a time-interleaving technique. This is one of the highest switching frequencies of the state-of-the art. The ENOB falls down to 4.6 bits for the highest part of the band.

[34] uses a 14 bits segmented architecture implemented in a BiCMOS process. Each resampling switch operates on an equivalent current source. A weighting of the 10 LSBs is done through an R-2R ladder.

[35] proposes a current steering DAC architecture, with 14 bits. It implements digital signal conditioning and high speed serialization to control the current array which outputs the differential RF analog signal into resistive loads.

[36] presents a 13 bits current steering DAC working at 9 GSps. It uses specific techniques within the current cells array to reduce code-dependant output capacitance, and a pre-distortion lookup table to improve INL performances.

[37] exhibits a multimode transmitter based on a segmented current steering DAC. The high speed digital interface is embedded to feed the DAC with high speed data.

All the presented DACs except one are designed in CMOS technologies. They all implement current-steering topologies, mostly with segmented architectures. Current steering topology is known to be best suited to high speed operation [START_REF] Albiol | Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure[END_REF]. [START_REF] Yoder | Accuracy and speed limitations in DACs across CMOS process technologies[END_REF] studied the limitations of this architecture in terms of accuracy and speed, the two main characteristics of DACs. The use of time interleaving is an interesting track [START_REF] Deveugele | Parallel-path digital-to-analog converters for Nyquist signal generation[END_REF][31] [START_REF] Noli | ∆Σ time interleaved current steering DAC with dynamic elements matching[END_REF] to relax the speed of each single path.

The large majority of the DACs presents a too elevated consumption for handset applications, Conversion efficiency (mW.s/Gbit)

Nyquist BW (GHz) [START_REF] Xiao | A 13-Bit 9GS/s RF DAC-based broadband transmitter in 28nm CMOS[END_REF] [32]

[35]

[37]

[33]

[34] The DAC realized in BiCMOS process exhibits a substantially higher consumption. The DACs realized in CMOS process are much more efficient, and they have an average conversion efficiency of several mW.s/Gbit. The resulting consumption for a 5 GHz bandwidth 12 bits DAC is around 500 mW, which is far too much for the DAC alone. The power budget of the DAC should be limited to a few tens of mW.

The broadband DAC approach to convert the whole transmitting band is still not integrable in handset terminals, because of a too high power consumption of the DAC itself.

Conclusion

Transmitter architectures tend to move from reconfigurable systems still relying on a complex analog front end to more digital solutions. Direct digital-RF transmitters and all-digital transmitters are in constant evolution, and they address present standards. However, the bandwidths are still bounded to several tens of a few hundreds of MHz, and the flexibility is limited. Multiband concurrent transmission is not always supported.

The development of full SR transmitters would provide the bandwidth and agility required for the future standards. Those systems are based on high speed data processing and a suited RF-DAC. The consumption of state-of-the-art DACs is unfortunately too high to allow the implementation of a full SR transmitter in a handset device. A new kind of RF-DAC is needed to lower the power consumption. It requires an innovative digital to analog conversion scheme to lower the cost of conversion in terms of energy.

In the next section, we propose to come back to digital/analog conversion theory basics. The most classical conversion schemes, involved in the referenced state of the art works, are studied to underline their features toward multi-GHz operation.

Data conversion schemes

Quantization is the operation which separates the analog world from its digital counterpart.

An analog signal evolves in a 2 dimensions continuous environment, where one is the time. A digital signal is made of a collection of points with discrete coordinates, thus allowing easy representation and storage. The discretization of time is associated with the notion of clock; changes can occur only on clock events. When the clock frequency is constant, the time vector can simply be an index. The binary representation of discrete quantities appears to be the most suitable to electronic implementation. The discretization of quantities thus relies on the use of bits (Fig. 1.8).

The accuracy of the digital representation of an analog signal is tightly related to the involved coding scheme. The two key parameters that drive the accuracy of a conversion are:

• the sampling frequency f s Increasing those two parameters may result in an enhancement of the accuracy of the conversion, at the cost of a higher complexity of the system. As for the electronic implementation, this complexity induces higher component count, energy consumption, die area and design subtlety.

A bandwidth limited analog signal of maximum frequency f max can be perfectly described by an infinite resolution digital signal sampled at the Nyquist frequency (f s = f N yquist ) which is twice f max (Nyquist-Shannon theorem). That is to say the original analog signal can be recovered without any additive noise; provided the digital signal has a perfect accuracy and the sampling images are ideally filtered (Fig. 1.9). This is theoretically achievable with an infinite number of bits to code the sampled analog levels. Such a signal would exhibit an infinite signal to noise ratio (SNR). The most popular data coding schemes used for digital-to-analog conversion will be presented hereafter, together with the related quantization noise. Those two widespread techniques are:

• Pulse code modulation (PCM)

• Pulse density modulation (PDM)

Pulse code modulation

Nyquist rate pulse code modulation

The most spontaneous way to encode an ideal digital signal with a finite number N of bits is to quantize each sample thanks to a N-bit word at the Nyquist frequency, with a pulse code modulation (PCM) scheme (Fig. 1.11). (2 N -1) , this length being called the quantum q. Thus, the error e q made when quantizing an input sample belongs to [-q/2, +q/2]. The assumption that the probability density function of eq is uniform over this interval is done, which is generally acceptable for full scale signals (e.g modulated signals) [START_REF] Wagdy | Validity of uniform quantization error model for sinusoidal signals without and with dither[END_REF]. The quantization error can thus be seen as a noise with a power given by:

N bits quantizer

σ e 2 = ∞ -∞ e q 2 .
p(e q ) de q = q 2

q 2 e q 2 . 1 q de q = q 2 12 (1.1)

For a large enough N, the quantum q is approximated by 2V 2 N , so that the power of the quantization noise is expressed as:

σ e 2 ≈ V 2 3.2 2N (1.2)
This noise is in the general case considered as a white noise lying on the [ -fs 2 , +fs 2 ] frequency band [START_REF] Borodachov | Asymptotic White noise Hypothesis for PCM quantization[END_REF]. For further calculations, we consider that the digital input signal represents a full scale sine wave, carrying a power σ x 2 of V 2 2 once reconstructed in the analog domain. The maximum signal to quantization noise ratio (SQNR), is then calculated:

SN R dB = 10log 10 ( σ x 2 σ e 2 ) ≈ 6.02N + 1.76 (1.3)
This well-known formula is used as a reference to calculate the effective number of bits (ENOB) of converters. Such a SNR could be achieved on the analog output signal with an ideal DAC and an ideal LPF that cuts the frequencies over f max .

fmax fs -fmax

Frequency Spectrum amplitude fs = 2.fmax Quantization noise Figure 1.12: Spectrum of a Nyquist rate quantized signal Most common DAC architectures operate as zero-order holds which generate a staircase signal [START_REF] Myderrizi | Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling[END_REF]. From the frequency viewpoint, the zero-order hold multiplies the digital signal spectrum by the cardinal sine function whose first zero is 2.f N yquist . This has the beneficial effect of providing a first low pass filtering which helps cutting high frequency images. However, it also causes a mild roll-off of gain at the highest frequencies of the desired band, thereby degrading the SNR.

An analog low-pass filter is generally added to further attenuate the out-of-band signal, with the same harmful effect on the wanted signal. The technique of oversampling tackles this problem, Yoan VEYRAC, IMS Laboratory -December 2015 through the use of a higher sampling frequency; this opens a frequency gap between f max and fs 2 which enables, inter alia, cleaner filtering.

Oversampling

Compared to the previously described Nyquist-rate-DD conversion, the oversampled version involves an up-sampling filter that adds samples up to a rate of 2 r .f N yquist [START_REF] Roza | Recursive bitstream conversion: the reverse mode[END_REF]. This operation is considered as ideal, so that it provides samples with infinite resolution without adding any kind of noise.

N bit

Pulse density modulation

Another way to encode signals is pulse density modulation (PDM), where the relative density of pulses over time represents the amplitude of the corresponding analog signal. Such a modulation can be implemented through the sigma-delta process [START_REF] Aziz | An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution[END_REF]. It generally uses a one-bit quantizer that outputs a stream of ones and zeros depending on the input signal. A high density of ones corresponds to a high value of the signal and vice versa. The quantization error produced is fed back in the sigma-delta process so that every error is taken into account into the next sample quantization. This results in the averaging out of the quantization error, so called noise shaping. The description of this phenomenon for a DD sigma-delta modulator is usually done thanks to a linear z-transform block diagram.

Yoan VEYRAC, IMS Laboratory -December 2015 The input signal X corresponds to the output of the up-sampling filter, which is considered ideal as above; this signal is at a rate of 2 r .f N yquist , with a virtually infinite resolution. The integrator that sums the difference between X and Y is represented as an adder associated with a delay element. The quantizer is modeled by an additive noise E. The output Y can be calculated versus the two inputs, respectively the wanted signal X and the quantization noise E:

+ + + Z -1 + + + + + - X(z) Y(z) E(z)
Y (z) = X(z).z -1 + E(z).(1 -z -1 ) (1.5)
The wanted signal is simply delayed by a sample period, whereas the quantization noise is shaped by a high pass transfer function. The total quantization noise of the system is the one of a one-bit quantizer of dynamic [-V, +V ]; it exhibits a quantum q of 2V. The quantization noise power equals q 2 12 , i.e:

σ e 2 = q 2 12 = V 2 3 (1.6)
The spectral distribution S e (f ) of this noise power for the open loop version would be uniform

in the range [ -fs 2 , +fs 2 ]
.

S e (f ) = σ e 2 f s (1.7)
In the sigma-delta configuration, this noise is shaped instead, with the previously calculated noise transfer function. This transfer function can be expressed in the frequency domain as:

N T F (f ) = 1 -e -j2π f fs (1.8)
Yoan VEYRAC, IMS Laboratory -December 2015

It leads to:

|N T F (f )| 2 = (1 -e -j2π f fs )(1 -e j2π f fs ) = 4sin 2 (π f f s ) (1.9)
The in-band quantization noise, i.e the part of the noise which lies on the frequency band [-f max , f max ], is given as:

σ n 2 = fmax -fmax S e (f ).|N T F (f )| 2 df = σ e 2 f s fmax -fmax 4sin 2 (π f f s ) df = 2.σ e 2 [ 1 OSR - 1 π sin( π OSR )]
(1.10)

Assuming a large enough OSR, the Taylor series expansion of the sinus function can be used, so as to simplify the previous equation:

sin(x) ≈ x - x 3 3! + x 5 5! + ... + (-1) N x 2N +1 (2N + 1)! (1.11)
And, The maximum SNR theoretically achievable with an ideal low pass filtering -when the input corresponds to a full scale sine wave -is thus given as:

σ n 2 ≈ σ e 2 ( π 2 3.OSR 3 ) (1.
SN R dB = 10log 10 ( σ x 2 σ x 2 ) ≈ 9.03r -3.41 (1.13)
It is to note that using an N-bit quantizer has the same effect as on the PCM architecture, that is enhancing the maximum SNR of 6 dB per additional bit. Compared with the PCM architecture, the maximum SNR highly improves with the OSR. However, this works only under the Yoan VEYRAC, IMS Laboratory -December 2015 assumption of a high enough SNR. Indeed, in the in-band quantization noise calculation, the inversely proportional to OSR term can be cancelled by the first term of the sinus Taylor series only if the argument of the sinus is small enough. In the case of a low to moderate SNR, this assumption falls and the resulting term lowers the SNR compared with the calculated formula.

This observation is relevant with all the more reason for higher order sigma-delta modulatorswhere the SNR depends even more on the OSR -since their principle is based on the cancellation of the successive terms of the sinus Taylor series.

This architecture is likely to be efficient for baseband signals conversion, up to several tens or hundreds of MHz (cf. Tab. 1.3). Large frequency band conversion (over the GHz range) implies a relatively low OSR because of technological limitations. As a consequence, the frequency gap between f max and fs 2 is likely to be thinner than a decade, which makes it difficult to fully benefit from noise shaping. The major problem of this topology under these conditions is that the total quantization noise does not wane as OSR is increasing, it remains constant instead. The global efficiency of a digital to analog architecture mainly comes from two origins:

• The coding scheme: the efficiency of a coding scheme can be assessed through the quotient of the actual information content of the encoded signal (EN OB.bandwidth) by the data rate involved in this code (N.f s ). The global data rate directly impacts the consumption and complexity of the digital processing block.

• The digital to analog conversion: the efficiency of the conversion mainly depends on the DAC topology and implementation. It can be described by the ability of the DAC to convert a given digital data volume into an analog signal. The efficiency is thus the ratio of the power consumption and the input total data rate (N.f s ).

The global efficiency of the digital to analog conversion is then the multiplication of the two described efficiencies. It is representative of the tradeoff between conversion performances (bandwidth, resolution), and power consumption.

The two major conversion methods are related to the two dimensions associated with quantization: time resolution and amplitude resolution.

• PDM takes advantage of time resolution; it needs a high oversampling ratio to reach the requirements in terms of resolution. It faces technological limitations in terms of maximum working frequency. Furthermore, the use of a high oversampling ratio rapidly degrades the coding efficiency.

• PCM is associated with high resolution RF-DACs. The conversion efficiency of state-ofthe art DACs remains a stumbling block for handset applications.

• A combination of these approaches can be implemented with a multi-bit sigma-delta architecture. It combines the features of the two conversion schemes, with the same bottlenecks.

Table 1.5: Key features of the classical conversion schemes. PDM -1 bit SDM Time r 9

Conversion scheme Key axis

1+ 3r

Conclusion

The media convergence, the user habits and the density of devices induce a huge increase of wireless data volume. Changes must occur on the network structure to bear this appetite for data. In order to ensure the compatibility with an upcoming heterogeneous and ubiquitous network, mobile terminals transceivers should satisfy the 3 major constraints:

• Low cost solution to address mass market. The flagship technology is CMOS.

• Low power operation, to cope with the electrical energy storage constraints.

• High bandwidth capabilities, to enable transmission of high data rates, and to dynamically address existing and forthcoming standards.

SR transmitters based on the direct conversion of a wide frequency band appear as good candidates to provide an absolute flexibility; however, the consumption of RF-DACs prevents this solution from being integrable in portable devices. The realization of a suitable transmitter needs a disruptive approach of digital to analog conversion, to improve the conversion efficiency and to overcome the bottlenecks associated with the handsets stringent requirements.

We propose to explore a disruptive approach of digital to analog conversion, involving both the coding scheme and the DAC topology.

Chapter

2

Differential digital to analog conversion

The conversion efficiency introduced in the conclusion of Chapter 1 reflects the ability of a conversion architecture to describe an analog signal accurately with the most optimized number of digital information. All the classical conversion architectures used in the state of the art converters and transmitters rely on the absolute digital encoding of the wanted signal. We propose to encode the relative variations of the signal instead of the signal itself in order to alleviate the quantity of digital information required for the coding. It consists in operating the conversion through the derivative of the signal. The conversion scheme involved in this architecture is described in this section.

Differential Pulse Code Modulation (DPCM): Riemann

Differential coding schemes, such as differential PCM (or delta modulation in the case of a 1-bit quantization) are sometimes used in data compression for imaging and audio applications [START_REF] Waltrich | Digital video compression-an overview[END_REF], [START_REF] Oliveira | CMOS Imager With Focal-Plane Analog Image Compression Combining DPCM and VQ[END_REF]. Nevertheless, this technique remains barely used in communication systems [START_REF] Mansour | Simulation of DPCM and ADM Systems[END_REF], and even less in SR applications. The principle of DPCM is to quantify with N bits the relative variations of the input signal instead of its absolute value. The coded output thus represents the derivative of the signal and has to be integrated in order to recover the wanted signal.

Yoan VEYRAC, IMS Laboratory -December 2015

• A first option consists in quantifying at each step the difference between the current input sample and the previous one (Fig. 2.1). This simple structure presents an important drawback: the quantization error is cumulative and once recovered after decoding (a simple integration), the output signal may drift.

N bit quantizer ∞ bits The quantizer does not need to cover the whole signal dynamic since the quantity to be quantized is related to the difference between successive samples. Indeed, it simply has to follow the maximum variations of the input signal to avoid overload distortion. The quantizer dynamic is thus closely related to the input signal maximum frequency.

f nyq N bits 2 r .f nyq D-D conversion Digital Input Upsampling filter ∞ bits 2 r .f nyq Δ - + Delay DAC LPF Analog Output
In order to convert any bandwidth limited signal (of maximum frequency f max ) with an N-bit DPCM scheme operating at the frequency f s , the dynamic of the quantizer must fulfill the mentioned constraint. The largest level of the quantizer has to be larger than the maximum variation of the said signal so as to follow the input signal variations. wave at the maximum allowed frequency f max , the maximum of the derivative equals 2V πf max ; the maximum potential variation over a time step is 2V π fmax fs . The largest positive level is thus set at this value. The larger negative level is then set at the opposite value -2V π fmax fs . SR applications deal with modulated signals that cover a significant part of the dynamic range [-V, +V ], and with high enough frequency components. Under these conditions, the quantization error power is minimal when the quantization levels are uniformly distributed between the extreme ones (see Annex 4.1). The quantization error e q (k) corresponds at each step to the difference between the ideal sample of the input signal y s (k) and the estimated value of this signal y r (k) at the output of the decoder. The interval of length 4V

q k k+1 Signal level Time y s (k) y r (k) y s (k+1) y r (k+1) fs / 1 2.V.π.f max /f s -2.V.π.f max /f s 0 e q (k+1)
π fmax fs is subdivided into 2 N -1 intervals of identical length q. q = 4V πf max (2 N -1)f s = 2πV (2 N -1)OSR (2.1)
The quantization error can be considered as a quantization noise with a total power:

σ e 2 = q 2 12 ≈ 3V 2 (2 2N -2 N +1 + 1).OSR 2 (2.2)
It is to note that this power is inversely proportional to the OSR squared, which comes from the differential coding. The z-transform block diagram of the described conversion scheme (Fig. 2.4)

enables to assess the frequency distribution of the quantization noise. The quantizer is modeled as an additive noise, and is followed both on the feedback path and on the forward path by adders. The one on the forward path corresponds to the signal recovery integration performed by the DAC, and it is necessary to model it so as to evaluate the transfer function with respect to the signal and not its derivative. The calculations give:

+ + + + + + - X(z) Y(z) E(z) + Z -1 + + + Z -1 + U(z)
U (z) = X(z)(1 -z -1 ) + E(z)(1 -z -1 ) (2.3)
And with a further integration:

Y (z) = X(z)z -1 + E(z)z -1 (2.4)
The transfer function is the same with respect to the signal X(z) and to the noise E(z) and it simply operates as a delay; no noise shaping is performed. Thus the quantization noise calculated previously can be considered as an unshaped white noise lying on the frequency band [-fs 2 , fs 2 ]. Assuming the out-of-band noise (i.e. the noise over f max ) could be filtered out perfectly, the remaining in-band quantization noise is:

σ n 2 = σ e 2 OSR (2.5)
The signal to quantization noise ratio (SQNR) for a full scale sine wave is thus calculated as:

SQN R dB ≈ 6.02N + 9.03r -7.78 + 10log 10 (1 - 1 2 N -1 + 1 2 2N ) (2.6)
In formula 2.6, the dependence of the SQNR on the OSR has a double origin. The main effect comes from the differential coding. Any doubling of the sampling frequency divides by 2 the range to be covered by the quantizer, as well as the quantum. Thus, it brings a factor 6.02r in the SQNR, corresponding to a decrease of the total quantization noise generated. The additional factor 3.01r comes from the filtering out of the noise lying on the band [f max , fs 2 ]. Considering RF applications, the OSR is inherently low and its effect does not mainly depend on the filtering of the out-of-band quantization noise; the requirements on the analog output filter are thus relaxed. This topology of DA conversion is optimized for low OSR applications, in order to cover a large frequency band without a complex and resource intensive architecture.

In the following sections, the Riemann conversion refers to the DPCM DD conversion architecture presented in this paragraph.

Noise Shaping Riemann conversion (NSR)

Starting from the Riemann architecture, it is possible to add a quantization error compensation feature, by taking into account the error made in any sample to calculate the next one. Given the ideal samples y s (k) and y s (k + 1), and the step-k-calculated sample y r (k), it is now to determine the next quantized sample y r (k + 1). The principle of error compensation is to aim a corrected sample y s,corr (k + 1) instead of the real sample y s (k + 1) ( Fig. 2.5). The corrected sample integrates the previous error.

y s,corr (k + 1) = y s (k + 1) -e q (k) (2.7)
Yoan VEYRAC, IMS Laboratory -December 2015

y s (k) y s (k+1) y r (k) y s,corr (k+1)
e q (k) e q (k) In this way, when the effective sample y r (k + 1) is calculated (as an approximation of y s,corr (k + 1)), the average error done between two successive samples is lowered. Considering the DD conversion principle, the value to be quantized to produce the y r (k + 1) sample is now y s (k + 1) -(y r (k) + e q (k)). The Z-transform block diagram of this version of DD conversion can thus be drawn by adding the quantization error within the feedback loop. The transfer function of the derivative U with respect to the input signal X and to the quantization error E can thus be calculated, giving:

y s (k) y s (k+1) y r (k) e q (k) e q (k) y r (k)+e q (k) (a) (b)
+ + + + + + - X(z) Y(z) E(z) + + + + + U(z) + Z -1 Z -1 Z -1 + + - + + Noise shaping loop
U (z) = X(z)(1 -z -1 ) + E(z)(1 -z -1 ) 2 (2.8)
And, when referring to the output signal Y:

Y (z) = X(z).z -1 + E(z).z -1 .(1 -z -1 ) (2.9)
The signal path simply presents a unit delay, whereas the noise transfer function corresponds to a delay and a high pass characteristic. The latter exhibits exactly the same modulus as the first order sigma delta topology and thus the same noise shaping is performed. Assuming an ideal analog low-pass filtering, the quantization noise power can be reduced by a factor proportional to the OSR cubed. The in-band quantization noise is determined by the same equation:

σ n 2 ≈ σ e 2 π 2 3.OSR 3 (2.10)
i.e:

σ n 2 ≈ V 2 .π 2 (2 2N -2 N +1 + 1).OSR 3 (2.11)
The expression of the corresponding SNR in dB is given by: SN R dB ≈ 6.02N + 15.05r -13 + 10log 10 (1 -

1 2 N -1 + 1 2 2N ) (2.12)
The filtering of out of band noise thus improves the OSR by 9.03r instead of 3.01r in the case of non-shaped white noise. The overall SNR in dB depends on the OSR through the term 15.05r,

Yoan VEYRAC, IMS Laboratory -December 2015 the first part (6.02r) being related to the reduction of the quanta within the quantizer and the additional 9.03r coming from the filtering out of the shaped noise. Referring to equation 2.10, the noise shaping loop adds a π 2 3 factor in the expression of the in band quantization noise; the negative constant term in the expression of the SNR is thus emphasized up to -13 dB. This offset is easy to compensate in the case of a large OSR, or for a medium OSR and a sharp analog filtering.

One can notice this topology exhibits a first order noise shaping function. It is also possible to implement higher order noise shaping topologies by adding feedback loops that take into account more samples of the input signal. The result would be exactly the same than on sigma delta topologies: a high improvement of the SNR with respect to the OSR, but only in the case of high enough OSR. Furthermore, it would increase the system complexity, and degrade the stability of the conversion.

The Noise Shaping Riemann architecture described in this paragraph will be referred as NSR in the following sections of the manuscript.

RF conversion schemes summary

The differentiating conversion schemes presented in this section are compared together with the conventional schemes used in literature, in the domain of high speed DACs and flexible transmitters. Those schemes are decomposed according to their constitutive techniques, namely oversampling, noise-shaping and differentiating. The impact of the number of bits N involved in the conversion is the same for all the exposed schemes: an improvement of 6 dB in the SNR per extra bit. However, the effects of the OSR are different for all of them, and they are listed in Table 2.1. The conversion schemes can be decomposed according to 3 methods:

• Oversampling: it provides a slight improvement of the SNR and eases the filtering of the digital replicas by spreading the quantization noise floor on a larger frequency band.

• Noise shaping: it shapes the quantization noise out of the band of interest and provides a high improvement of the SNR, but it works properly with a high enough OSR and an efficient filtering. Only first order noise shaping is considered because the drawbacks are even more penalizing for higher order in the case of low OSR. Oversampling is a prerequisite to use noise shaping techniques.

• Differentiating: it brings an additional benefit that is compatible with the oversampling and noise shaping techniques. The only cost is a slight change in the quantization process and several precautions in the quantization and reconstruction process.

i = C dv dt (2.13) Or: ∆v = 1 C i∆t (2.14)
Considering a low consumption system in recent integrated technologies, a coarse estimation of the range of the different terms in equation 2.14 gives:

• ∆v # V • C # pF • i # mA • ∆t # ns (GHz)
Those orders of magnitude are compatible with the integrated technologies capabilities. The developed DAC architecture relies on the integration of a digitally controlled current generator and a capacitive load. The current generator is composed of binary weighted complementary switched current sources. The corresponding topology of the digital to analog conversion architecture is depicted in Fig. 2.8; it is composed of 2 main parts.

• a DD conversion block, where a differentiating coding is performed onto a digital representation of the wanted signal.

• a DAC which converts the digital bit streams representative of the derivative of the signal into a proportional analog current thanks to complementary switched current sources. The resulting current is integrated into a capacitor to generate the wanted signal.

Analog reconstruction features

The spectrum of a digital signal is made of the baseband signal and replicas centered in the multiples of the sampling frequency f s . The operation of digital to analog conversion acts as a reconstruction filtering, with most of the time a low pass characteristic. The impact on the spectrum is represented in Fig. The frequency response of this reconstruction scheme is the Fourier Transform of the impulse response, illustrated in Fig. 2.12. The first order hold reconstruction process performed by the Riemann Pump results in a squared cardinal sinus filtering. Most common DAC architectures operate as zero-order holds which generate a staircase signal. A comparison between zero order and first order holds is presented in Fig 2 .13, and summarized in Table 2.2. The first-order hold provides a sharper filtering than the zero order hold; it results in a slightly reduced bandwidth.

H f oh (f ) = F {h f oh (t)} = ( e iπf T -e -iπf T i2πf T ) 2 = sinc 2 ( f f s ) (2.15) f s Frequency H foh (f) = sinc²(f/f s ) -f s 2*f s -26.4 dB 0.32f s -0.32f s -3 dB
f s Frequency |H zoh (f)| 2*f s f s Frequency |H foh (f)| 2*f s 0.44f s 0.32f s -26.4 dB -13.2 dB t h foh (t) T -T T=1/f s t h zoh (t) T 0 T=1/f s -3 dB -3 dB
To limit the roll-off of the highest frequency components of the wanted signal (near f max ), a high enough OSR is to be used. The OSR parameter r should be higher than 1.5 to ensure an attenuation lower than 1 dB. The filtering profile of the first order hold however provides a better filtering of the out of band noise and of the digital images. It results in a cleaner output spectrum and relaxes the constraints on a further low-pass filtering.

Simulation of the Riemann Pump architecture

The theoretical expressions of the SNR calculated previously are reminded, both for the Riemann and for the NSR conversion.

SN R Riemann ≈ 6.02N + 9.03r -7.8 + 10log 10 (1 -

1 2 N -1 + 1 2 2N ) (2.16) SN R N SR ≈ 6.02N + 15.05r -13 + 10log 10 (1 - 1 2 N -1 + 1 2 2N ) (2.17)
The theoretical features of the presented architectures encompass both the conversion scheme (DD) and the analog reconstruction (DA) process; they are listed in Table 2.3. Those characteristics are to be validated thanks to system simulations. In the following section, the system simulation flow is presented, including the signal generation process and the SNR calculation method. The simulation results are then compared to the theoretical performances, both for the Riemann and the NSR coding schemes. Finally, the ability to address concurrent transmission will be assessed through the application to sub-6

GHz 5G transmission schemes.

System simulation flow

Signal generation process

The system simulations are performed thanks to digital calculations, with the software Matlab. • Ideal signal generation: the wanted signal is generated with a high digital resolution and a short time step, so that it can be considered as an ideal analog signal. • Riemann code calculation: the Riemann (or NSR) algorithm is applied to the wanted signal, with a resolution of N bits at the working frequency f s . This block generates the N bit streams corresponding to the sequence of slope which represents a piecewise linear approximation of the wanted signal.

• Discrete signal generation: this signal is the sampled version of the wanted signal.

It corresponds to the discrete values of the piecewise linear signal at the sampling times.

The spectrum of this signal contains the unfiltered quantization noise generated by the coding algorithm

• Piecewise linear interpolation: it corresponds to the linear interpolation of the previous discrete signal. It is representative of the voltage obtained by the ideal integration of the current steps into the output capacitor. This operation is equivalent to a first-order hold. It operates as a squared cardinal sine filter on the discrete signal spectrum.

SNR calculation

The SNR is the key metric to assess the signal generation performances. It is expressed as the ratio of the power of the useful signal P s divided by the power of the noise P n , with a logarithmic scale.

SN R dB = 10log(

P s P n ) (2.18)

Temporal dimension

As far as signal generation is concerned, the noise can be considered as the error between temporal representations of the wanted signal y and the actually generated signal y r . In this case, the power of the noise P n is the power of the error signal e = y -y r (Fig. The power of the signal P s over a time interval T is given by:

P s = 1 T T y 2 dt (2.19)
The power of the noise P n is calculated as:

P n = 1 T T (y -y r ) 2 dt (2.20)
Yoan VEYRAC, IMS Laboratory -December 2015

The resulting SNR equals:

SN R dB = 10log( P s P e ) (2.21)
For a sampled signal, the integral is replaced by a discrete sum:

SN R dB = 10log kmax k=1 y( k fs ) 2 kmax k=1 (y( k fs ) -y r ( k fs )) 2 (2.22)
This formula of the SNR calculates the overall quantization noise. This temporal approach is used to determine the total quantization noise of the presented conversion schemes. However, it does not allow to assess the spectral distribution of the quantization noise and to distinguish the in-band from the out-of-band noise.

Frequential dimension

The usual conversion between the time and the frequency domain is performed by the Fourier transform (FT). It allows to obtain the spectrum of time varying signals (Fig. 2.16), which is noted: The energy of a signal does not depend on the chosen representation: temporal or frequential.

X(f ) = F T {x(t)} (2.23) f s Frequency f max 0 f 1 |X(f)|² P(f 1 ) P(noise)
This assertion is known as the Parseval identity, and is expressed as follows:

E = (|x(t)| 2 dt = (|X(f )| 2 df (2.24)
The SNR of a signal which represents a continuous wave can thus be calculated as its power at the fundamental frequency divided by the power at all the other frequencies. Let y r be the temporal approximation of a sine wave at the frequency f 1 , and Y (f ) its FT. The SNR of this signal can be calculated as:

SN R = |Y (f 1 )| 2 [0,∞]\f 1 |Y (f )| 2 df (2.25)
It is also possible to calculate the SNR with respect to the in-band quantization noise only, by limiting the upper boundary of integration interval to f max .

SN R inband = |Y (f 1 )| 2 [0,fmax]\f 1 |Y (f )| 2 df (2.26)
This frequential approach is used to determine the quantization noise of a generated signal within a given frequency band. It allows to get rid of the out-of-band noise in the calculation of the SNR.

SNR performances: simulation results versus theory

The SNR is calculated for the generation of a full scale sine wave of frequency f out . It is assessed for different values of the key parameters (r, N and f out ), as represented in Fig. 2.17.

SNR versus the number of bits N

The resolution of a converter is usually expressed in effective number of bits (ENOB). 1 effective bit corresponds to 6.02 dB in the SNR. Usual converters exhibit a SNR which depends on 6.02N. The two presented conversion schemes (Riemann and NSR) present a similar dependence, plus an additional 10log 10 (1

-1 2 N -1 + 1 2 2N
). This extra term becomes negligible when N is greater than 3.

• Riemann

A sine wave is generated thanks to the Riemann algorithm, with an OSR set to r=2 and a variable number of bits N. Results exposed in Fig. 2.18 compare the simulations to the theoretical formula of the SNR established previously for the Riemann algorithm. The total quantization noise is calculated onto the discrete signal with samples given at the frequency f s . The in-band noise is calculated onto the piecewise linear reconstructed signal by integration of the spectral power density up to f max . The SNR including the total quantization noise perfectly fits the theoretical formula. The in-band noise related SNR is also consistent with the formula. It confirms the claims about the uniform distribution of the quantization noise over the frequencies.

• NSR Fig. 2.19 exposes the same study for the NSR algorithm. The impact of N on the SNR is also consistent with the theory for the NSR algorithm, both considering the total and the in-band noise.

The slope of 6.02N is common to all the classical conversion schemes. The actual benefit of the presented ones is related to the OSR.

SNR versus the oversampling factor r

• Riemann

The Riemann conversion benefits from the differential coding through a term 6.02r, plus an additional 3.01r when restricting to the in-band noise.

The discrete signal reaches the expected value of SNR (Fig. 2.20). The in-band noise results in a SNR which has the same behavior as in theory. It is comprised in a +/ -1dB interval.

Yoan VEYRAC, IMS Laboratory -December 2015

• NSR

The impact of the oversampling on the SNR is expressed through the term 15.05r in the SNR theoretical formula. This behavior is confirmed by the simulations presented in Yoan VEYRAC, IMS Laboratory -December 2015

The system simulations confirm the expected impact of the OSR on the conversion performances in terms of SNR; it validates the claims of conversion efficiency.

SNR versus output frequency

For a given set of parameters (r,N), the output bandwidth is f max = fs 2 r+1 . The SNR is calculated for the generation of sine waves up to f max in order to assess the performances of the system versus frequency. It is assessed for the generated signal at 3 stages:

• Discrete signal: it contains all the quantization noise.

• Piecewise linear signal: it contains all the quantization noise filtered by a first order hold reconstruction filter (sinc 2 ).

• Band limited piecewise linear signal: it contains only the quantization noise in the

[0 -f max ] band.
This study is led both for the Riemann and NSR conversion schemes. The quantization noise is distributed over the whole sampling frequency band and the noise situated near f s is significantly attenuated. As a result, the SNR of the linearly interpolated signal is significantly higher than the one of the discrete signal. Furthermore, this SNR is not constant over the whole band but it varies along the frequency axis. It is related to the nature of the generated signal: a continuous wave (CW). The quantization noise could be uniformly distributed over the frequencies for a random signal but CW are all but random. The arithmetic relationship between the sampling period t s = 1 fs and the output CW period T out = 1 fout plays an important role in the spectral repartition of the quantization noise. If there is an integer relationship, a greater part of the global power is located at the harmonic and intermodulation frequencies. The amount of spurious tones filtered by the reconstruction operation thus depends on the frequency of the CW.

• Riemann

The in-band noise depends even more on the frequency, because the spurious are likely to be situated inside and/or outside of the band of interest. Nevertheless, the simulations lead most of the time to more favorable results than the theoretical formula, while being situated around the expected level of SNR.

• NSR Fig. 2.24 presents the similar study for the NSR conversion. The quantization noise is pushed to the highest frequency (i.e fs 2 ) as represented in Fig. 2.25. The sampling image centered in f s has also a shaped quantization noise close to fs 2 . The major part of the quantization noise is thus situated around this frequency, where the sinc 2 ( f fs ) filtering is not severe. The reconstruction step does not significantly improve the SNR with respect to the discrete signal.

When considering only the in-band noise, the SNR jumps around 34 dB over the whole frequency band, which is the theoretical value. The dependence in frequency is weaker than in the previous case, because it is masked by the noise shaping.

Conclusion

The SNR performances have been assessed through the generation of CW. Matlab simulations of signal reconstruction validate the theoretical study developed previously, both for the Riemann and the NSR conversion. It endorses the proposed formulas of SNR for those two architectures.

It helps to set the parameters of the system -namely N and r-to reach the specifications of potential standards.

Concurrent transmission

This section proposes to assess the ability of the developed architectures to address concurrent transmission of modulated signals. The case of sub-6 GHz 5G carrier aggregation schemes is considered in the following. The performances of the Riemann and the NSR are compared toward this application.

Sub-6 GHz 5G technical features

Generation of 10 aggregated carriers

A reference signal composed of 10 aggregated carriers modulated with 64-QAMs is generated with Matlab. The piecewise linear approximation of this composite signal is then computed, either with the Riemann or the NSR algorithm, with a given set of parameters (r,N). The synchronization of the carriers is inherently ensured because the modulated signals are generated all together in a single waveform. The spectrum is then computed to collect the SFDR; it is given by the difference of level in dB between the modulated signals and the noise floor. The 10 modulated signals can be demodulated with a suitable chain coded with Matlab to obtain their constellation and the associated error vector magnitude (EVM).

• Riemann conversion

The spectrum obtained with the Riemann conversion for a sampling frequency of 50 GHz and a number N of 6 bits is displayed in Fig. of SFDR is barely reachable with the maximum simulated settings, f s =50 GHz and N=6.

• NSR conversion

The same study has been led with the NSR algorithm. The obtained spectrum and constellations are displayed in Fig. 2.29. The spectrum matches with the 5G requirements in terms of SFDR with 67 dB of SFDR. The EVM is approximately 0.9%.

Yoan VEYRAC, IMS Laboratory -December 2015 The sweep of the sampling frequency f s and the number of bits N is exposed in Fig. 2.30.

The obtained SFDR values also fit the theoretical SNR behavior with a dependance in 6N and 15r. The noise shaping provides a significantly better SFDR than the classical Riemann conversion for the highest sampling frequencies.

Variation of the number of carriers

The configuration with 10 carriers is the worst case; the system could operate with an arbitrary number of carriers. The SFDR is reported versus the number of carriers, for both the Riemann and the NSR conversions with the parameters (f s , N)=(50 GHz, 6).

Yoan VEYRAC, IMS Laboratory -December 2015 The power of the useful signal is shared between the channels. The SFDR is improved by 3 dB when the number of channels is halved. The improvement of the SFDR in dB with respect to the 10 carriers configuration follows the equation 2. [START_REF] Venkataraman | An All-Digital Transmitter With a 1-Bit DAC[END_REF].

SF DR M channels = SF DR 10channels + 10log( 10 M ) (2.27)
The simulations are consistent with the theoretical features; it enables to adjust the parameters of the system to address the requirements of the application. In the case of sub-6 GHz 5G, the NSR conversion with a number of 6 bits is needed, with a working frequency between 40 GHz and 50 GHz.

Conclusion

Efficient DA conversion schemes based on differentiating coding have been exposed. They take advantage of a relative coding, eventually combined with noise shaping, to improve the conversion performances. It leads to a more favorable trade-off between system complexity and conversion performances than usual conversion schemes implemented in state of the art RF DACs. The underlying theory has been developed, and validated thanks to system simulations; it allows to set the key parameters of the system, namely the number of bits N and the OSR, for a given application with its own specifications.

The system has been assessed for the expected sub-6 GHz 5G stringent requirements. The generation of 10 intrinsically synchronized aggregated carriers with a SFDR of 60 dB could be addressed with the following characteristics:

• Conversion scheme: Noise Shaping Riemann

Integration in GaN technology

The generation of specific waveforms is of particular interest for RADAR applications. A signal generator based on the Riemann Pump architecture would provide an absolute flexibility for the generated waveform.

GaN technology

B C N Al Si P

Features Assets

High mobility

Riemann Pump in GaN technology

A first version of the Riemann Pump is designed in GaN with a technology from UMS, using ADS simulation environment. The purpose is to drive a Power Amplifier (PA) directly with the pump in order to integrate the whole analog part of the transmitter into a single chip. In this configuration, the capacitive input impedance of the power amplifier replaces the output capacitor of the Riemann Pump. The circuit described herein solely corresponds to the Riemann Pump alone.

Regarding circuit design techniques, the most important feature is related to the nature of the transistors. Only normally-on N-type transistors are available which impacts the circuit design.

Furthermore, those transistors have a negative threshold of several Volts and a consequent size, limiting their switching speed. Those constraints help us to choose the parameters r and N that will be used for the GaN circuit. A trade-off between circuit complexity and conversion performance leads to a number N of 3 bits. The frequency limitations enable a switching frequency of 8 GHz, allowing the generation of signals up to 1 GHz with an OSR of 4 (i.e. r=2).

Yoan VEYRAC, IMS Laboratory -December 2015

In the following, the couple of parameters (r,N) = (2,3) will be used. 3 coding bits enable to define a set of 8 slopes corresponding to the values of the DPCM quantizer. The steepest ones (respectively positive and negative) are calibrated with respect to the wanted dynamic and the switching frequency used. The 6 intermediate slopes are then distributed uniformly in between.

Slope

0 0 0 7 0 0 1 5 0 1 0 3 0 1 1 1 1 0 0 -1 1 0 1 -3 1 1 0 -5 1 1 1 -7 (a) (b) (c) V supply C out 7i 0 i Cout 2i 0 4i 0 8i 0 7 5 3 1 -1 -3 -5 - 7
8.i 0 4.i 0 2.i 0

Slopes Topology Currents

Transistor level design

The transistor level schematic is depicted in Fig. 3.6. This representation can be divided into 4 main blocks.

• Top rail current generation

• Bottom rail current generation

• Switching stage

• Mean voltage regulation

Yoan VEYRAC, IMS Laboratory -December 2015

Input buffers are required to ensure the interface between the bit stream generator and the switches of the Riemann Pump.

Top rail current generation

The top rail current generation block is depicted in Fig. 3.7. The goal of this block is to generate a constant current i out for any output voltage V out (within the wanted dynamic centered in Vcc 2 ). The lower part of the block is dedicated to the generation of current through 2 cascoded current sources (respectively formed by T r 1 , T r 2 and T r 3 , T r 4 ). The resistors R 1 and R 2 provide the appropriate gate voltage for the cascode stage. The resistors R 3 and R 4 give the right gate to source voltage so as to generate the wanted current in each of the 2 branches. The left branch pulls a constant reference current iref. The upper part realizes the function of a current mirror with only N-type transistors. The differential pair (T r 5 , T r 6 ) has a large enough gain so that the voltage V ref remains almost equal to the voltage V out when this latter varies. The 2 branches (R 5 , T r 7 ) and (R 6 , T r 8 ) being symmetric, the current iout turns out to be constantly equal to the reference current iref in the desired range of the output voltage V out .

Yoan VEYRAC, IMS Laboratory -December 2015

V cc /2 ² V cc V out V ref i ref i out

Switching stage

V cc /2 V cc /2 V cc /2 1-1+ 2-2+ 3-3+ C out 2.i 0 4.i 0 8.i 0 R 9 R 10
W 1 /L W 1 /L W 1 /L W 1 /L W 1 /L W 1 /L

Mean voltage regulation

The output voltage is averaged thanks to the low pass filter (R 11 , C 1 ). The obtained voltage is compared to the middle value Vcc 2 through a differential pair (T r 14 , T r 15 ), polarized with the current source formed by the transistor T r 13 and the resistor R 12 , and charged by the resistors The circuit layout is disclosed in Fig. 3.12, detailing all previously presented blocks. The overall die area is 5.5 mm 2 and the consumption of the core pump (without interface buffers) is slightly lower than 200 mW from a 15 V supply voltage. The routing of the circuit is ensured by a single metal layer, and the use of air-bridges allows crossroads. The components assembly is optimized to fit this constraint of interconnections. The graph of the circuit (where the components are the vertices and the interconnection lines are the edges) is thus designed to be as planar as possible. It reminds the design of monolayer printed circuits boards which should be described by a planar graph, with additional local exceptions allowed by air bridges. EM models of the lines are calculated thanks to ADS tools and taken into account for circuit simulations.

Input buffers

V cc /2 R17 V mid C3 In- R18 V hstl R19 R20 R21 R22 R23 In+ Out+ Out- C4 Tr16 Tr17 Tr18

Simulation results

Robustness

The output voltage is proportionnal to the charge of the output capacitor. The addition of a regulation loop counteracts efficiently the implementation and temperature discrepancies. The output voltage drift is as low as 1% in the whole temperature range. This is an important feature as soon as the applications targeted with this GaN technology are due to operate in harsh environments.

Signal generation

The performances of the circuit in terms of signal quality is assessed thanks to the generation of a signal of interest for RADAR applications: a linear chirp. Those kind of signals are generated

Yoan VEYRAC, IMS Laboratory -December 2015 to perform pulse compression; the general equation of a linear chirp waveform is given by the equation 3.1.

x(t) = Asin(2π(f 0 - ∆f 2 + ∆f 2T ).t), t ∈ [0; T ] (3.1)
The following parameters are used:

• Central frequency f 0 = 625 MHz

• Frequency dynamic ∆f = 2 MHz

• Chirp duration T = 250 µs

The Riemann code corresponding to the wanted chirp is computed with Matlab. The 3 bit streams corresponding to the slopes sequence are set as inputs for the circuit designed with ADS.

The pump is calibrated to generate a maximum frequency of 1 GHz with an input frequency of 8 Gbps, which corresponds to an oversampling parameter r=2. The output waveform generated onto the capacitor is then saved and the corresponding spectrum is displayed in Fig. 3.13. The theoretical SNR for the set (r,N)=(2,3) equals 27 dB for the Riemann conversion. The actual SNR achieved with the circuit simulation is solely 1 dB under the theoretical formula including layout related effects. It suggests that the practical implementation will not significantly affect the signal quality; the quantization noise remains the main contributor to the overall noise.

Conclusion

The design of a prototype of the Riemann Pump in a GaN technology presents a significant interest for the generation of peculiar waveforms in harsh environments. It simplifies greatly the traditional circuitry and performs the generation of any kind of signal within a reduced power budget, with the potential of a direct co-integration with a PA in the same technology. The intrinsic resilience of GaN devices to EM disturbances, high voltages and heating is combined with circuit design techniques to ensure robustness of the system in harsh environment. It finds natural applications in the military domain where the reliability is mandatory and the flexibility a strategical asset. Post-layout simulations validate the integrability of the Riemann Pump in a GaN technology.

Yoan VEYRAC, IMS Laboratory -December 2015

Integration in CMOS technology

The major target for the developed architecture is the mobile devices market and the associated consumer electronic products. The constraints of these applications are radically different from the military applications. Handset terminals need high bandwidth to support high data rates, low consumption to respect the limited energy budget imposed by the battery capacity and low cost to address a mass market. All these requirements should be met, eventually at the expense of durability and robustness: CMOS technologies are the most appropriate.

Architecture in CMOS technology

Sizing

The target technology is a 65 nm CMOS low power from the foundry TSMC. The sizing of the system is tightly related to the performances of this technology. The targeted features are the following:

• Number of bits N=3

• Sampling rate f s =25 GHz

• Output BW > 3 GHz (r=2)
The core pump is an integrating RF-DAC. The proposed architecture (Fig. • Integrating: the capacitive load of the pump is made of a differential PPA stage. It allows to perform an integration of the output current of the pump while amplifying the signal and feeding 50Ω differential loads.

• Differential current steering: the generated currents are steered to one side or the other of the differential load. It doubles the dynamic range compared to a single ended topology and provides inherent cancellation of even order harmonics.

• Complementary: complementary current branches optimize the current use. All the current flows carry information.

The current steering topology is extremely common in the field of RF-DACs. It allows to reach the highest performances in terms of speed because the generated currents are not cut but just steered in one side or the other [START_REF] Yoder | Accuracy and speed limitations in DACs across CMOS process technologies[END_REF]. A topology which relies on switching on and off the current sources would result in a lower power consumption but a lower working frequency. The constraints of the targeted application require a very high switching speed. Hence, the current steering topology is privileged.

Yoan VEYRAC, IMS Laboratory -December 2015 The overall circuit is presented in Fig. 3.15. Its sizing and design start from the output stage, namely the PPA.

Core pump circuit design

c c i out 1+ 1+ 1+ 1+ 1- 1- 1-1- 2+ 2+ 2+ 2+ 2- 2- 2-2- 3+ 3+ 3+ 3+ 3- 3- 3-3- x1 x2

Pre-Power Amplifier (PPA)

The PPA is a simple differential pair with 50Ω loads (Fig. 3.16). The target is to ensure a differential 1 V pp output voltage on those loads. The size of the transistors is thus set in accordance with this goal. The size of the switches sets the output capacitance of the current pump. The normalized capacitance of those transistors is plotted versus frequency in Fig. 3.17.

Yoan VEYRAC, IMS Laboratory -December 2015

Vcc Vcc

V out V bias V in i pump

Current sources

The current sources are derived from a reference branch via current mirrors, so that both the top and bottom rail current sources depend on a same reference (Fig. 3.19).

Vcc

Current sources matching

Matching issues in current steering DACs have been studied in [START_REF] Albiol | Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure[END_REF]. In particular, the formula used to describe the relative variance σI I of the current source due to random process mismatch is given by:

σ I 2 I 2 = 1 2W L (A β 2 + 4A V t 2 V 2 od ) (3.3)
A β and A V t are the mismatch process constants for the transistor gain and threshold voltage respectively. V od is the overdrive voltage, it equals V gs -V t . W and L are the width and length of the transistor. The mismatch constants are fixed by the process, the overdrive voltage depends on the design but it cannot be tuned significantly because the output voltage dynamic of the current sources is constrained. The only design levers are (W, L) of the transistors. The area is to be maximized so as to limit the mismatch between the sources. Hence, W and L of the involved transistors are large. In particular, the highest possible channel L is chosen for those transistors. W is then set to obtain the target current. This current is calibrated with respect to the target bandwidth and the output capacitance. The system is intended to address approximately 3 GHz bandwidth. The output capacitance is set by the PPA and is in the pF range. The signal dynamic is fixed by the input dynamic range of the PPA, so as so operate in linear region; it is approximately 300 mV pp .

Referring to the equation 2.1 in Chapter 2, the voltage quantum is determined thanks to the signal dynamic, the number of bits and the OSR. The calculation of the unit current quantum is then set by the loading capacitance, fixed by the size of the PPA differential pair.

I q = qf s C load (3.4)
The current quantum is thus calculated and the corresponding unit current source transistor width is consequently set.

Current sources I-V curves

The Riemann Pump is based on the integration of currents in an output capacitance whose voltage is varying. The current sources must present a high enough output impedance to ensure a proper operation over the wanted output dynamic. For this purpose, the designed current sources entail two cascode stages. The obtained current source characteristic (for the bottom rail) is displayed in Fig. 3.20 and compared with two other configurations, with only one and without cascode transistor, respectively.

Switches

The designed switches (Fig. 3.22) have the following characteristics :

• Differential: the current steering topology imposes the use of differential switches to steer the current toward one way or the other. It improves the working frequency.

Yoan VEYRAC, IMS Laboratory -December 2015

1+ 1+ 1+ 1+ 1- 1- 1-1- i out i push i pull

Regulation loop

The current sources and the switches are designed to be as balanced as possible. Nevertheless, any imbalance of the rails can cause a drift of the output common mode voltage through the integration of an error current in the output capacitance. The output voltage would drift toward one rail or the other until it stifles the corresponding current sources to reach an equilibrium point. This scenario is not desirable since it would cause extra distortion in the Riemann Pump and the PPA. To avoid such a drift, a regulation loop (Fig. 3 The loop works as follows:

• The voltage of a branch of the output is sensed and compared to the wanted common mode Vcc 2 thanks to a differential pair.

• The output of the comparator is filtered through an RC filter and biased with a decoupled resistor bridge.

• This voltage controls the gate of a transistor placed into the current reference branch of the top rail current sources in order to balance the pushed and the pulled currents.

• A pass gate transistor enables to open or close the regulation loop.

The regulation loop is presented by the following block diagram (Fig. 3.25). The loop is composed of a comparator of static gain K, a first order low pass filter, a choking transistor acting as a transconductance and an integrator corresponding to the output capacitance. The overall open loop transfer function can be written as:

K C out V out V ref K.ΔV 1/(1+j.R1.C1.ω) V ch i out 1/j.ω.C out g ch ip V ch i n i p
H(jω) = K.g ch . 1 Cjω . 1 1 + jRCω (3.7)
The static gain is infinite due to the presence of a pure integrator. The static output current of the top rail i p with respect to the output voltage V out is plotted in Fig. 3.26 and compared to the current generated by the bottom rail. The phase margin is approximately 10 degrees. This relatively low phase margin is mainly due to the capacitive output impedance which behaves like a pure integrator. Nevertheless, the stability has been ensured thanks to transient response to pulses. Furthermore, the pass gate transistor inserted in the loop allows to decrease the gain of the loop by controlling its gate voltage, thereby increasing the phase margin of the system. This transistor can also be completely cut off to virtually open the loop.

Yoan VEYRAC, IMS Laboratory -December 2015

Riemann Pump layout

The layout of the core pump is presented in Fig. 3.28. The core pump and the PPA are associated and RC parasitic elements are extracted from the overall circuit, to take into account the layout implementation.

Post-Layout Simulations (PLS)

The performances of the designed circuit are assessed thanks to PLS. The simulation flow is described in Fig. 3.30.

Theoretical signal generation

Riemann or NSR code computation

Riemann Pump PLS Spectral analysis N Digital processing (Matlab) 65 nm CMOS PLS (Cadence Virtuoso)

Temporal analysis The wanted signal is generated with Matlab and the Riemann (respectively NSR) algorithm is computed to determine the sequence of slopes giving the best approximation of this signal.

Yoan VEYRAC, IMS Laboratory -December 2015

These N bit streams serve as inputs for the designed circuit, clocked at 25 GHz. PLS is done with Virtuoso and the output voltage of the PPA is saved and analyzed with Matlab. CW generation is simulated to assess the impact of the circuit design with respect to the theoretical performances. Simulations of modulated signals concurrent transmission are then carried out.

CW generation

Spectra

The generation of CW at different frequencies is simulated with both the Riemann and the NSR algorithm. The spectra of 3 GHz generated CW are plotted in Fig. 3.31 • The SFDR corresponds to the difference of level between the CW and the strongest spurious in the band of interest. This parameter enables to spot inter-modulation products or distortion due to circuit non-linearities at specific frequencies.

• The SNR is calculated as the ratio of the CW power and the noise power, integrated over the [0 -3.125 GHz] band. This metric is representative of the overall noise generated by the system.

Yoan VEYRAC, IMS Laboratory -December 2015

The SFDR and SNR are extracted for the generation of CW of various frequencies, distributed over the [750 MHz -3 GHz] range.

SFDR

The SFDR values are compared with the SFDR obtained for an ideally generated piecewise linear approximation with the same parameters (r,N), for the two algorithms. The results are reported in Fig. 3

SFDR (dBc)

Output frequency (MHz)

SNR

The SNR values are reported and compared with the theoretical formulas in Fig. 3.33. Values obtained with PLS are consistent with the theoretical values: the PLS SNR are included in a +/-1 dB interval with respect to the theoretical formulas for both of the 2 conversion schemes.

PLS of the Riemann Pump does not result in a noteworthy degradation of the key performances.

They are still limited by the quantization noise.

-1 0 1 -1 0 1 Channel Q (A.U) QPSK -900 MHz 16-QAM -2.6 GHz Channel Q (A.U) Channel I (A.U) EVM : 1,2% QPSK -2.45 GHz -1 0 1 -1 0 1 Channel I (A.U) EVM : 1% -1 0 1 -1 0 1 Channel Q (A.U) Channel I (A.U) EVM : 0,8% (a) (b)

Conclusion

The design and implementation of the Riemann Pump in a 65 nm CMOS technology and the associated PLS simulations confirm the feasibility of the overall architecture. The overall performances should be limited by the parameters (r,N) of the implemented circuit and the associated quantization noise rather than the circuit non-idealities. However, all previous simulations are led to assess the performances of the Riemann Pump itself, i.e the DAC. The control bit streams are considered ideals so far. Nevertheless, an actual implementation of a global transmitter would require the generation of high speed bit streams to control the Riemann Pump, and the adequate interfaces. The following section deals with the realization of the chip which implements several environments for the Riemann Pump, with various digital interfaces.

Yoan VEYRAC, IMS Laboratory -December 2015

Chip design -PAULINA

A chip called PAULINA (Pumping Aggregative Uniform LINear Approximation) was designed.

As hinted by the layout techniques relative to the core pump and the PPA design, the chip layout considers additional factors, regarding the device, the block, and the chip scale. Those considerations have an important impact on the layout design.

• Current density: the interconnections have to respect maximum current densities, to limit self-heating effects and ensure reliability. It impacts the width of metal traces, the one of transistor's fingers, and the number of vias.

• Path length matching: differential signals are to be conveyed by symmetric and precisely matched traces. Furthermore, the length of the 3 differential input traces has to be matched.

• Parasitic elements: all the parasitic elements related to the interconnections should be taken into account. It impacts especially the high speed digital blocks which are sensitive to parasitic capacitances and resistances.

• Ground return: the paths should be carefully placed and distributed to ensure a proper cold ground.

• Decoupling: the decoupling of the cold points filters out the noise induced by the current flows. The cohabitation of digital and analog blocks imposes an efficient decoupling.

Supply and ground planes provide a distributed decoupling over a wide frequency band.

• Cross talk: when signal paths are coupled by parasitic elements, cross talk can occur between them. To limit these effects, differential signals are isolated by supply/ground planes and are as little contiguous as possible.

The prototyped chip global layout is shown in Fig. 3.36. 4 circuits are embedded, 1 per corner of the chip, each one corresponding to the implementation in a specific I/O environment.

CKT3 CKT2 CKT1 CKT4

1.92 mm

CKT1: Standard pump

The standard version of the pump is embodied into the chip by CKT1. The corresponding overall architecture is displayed in Fig. 3.37. The command bit streams are generated thanks to an FPGA equipped with high speed serial transceivers, using HSTL standard. The differential 50Ω termination is designed on-chip, with a common mode voltage of Vcc 2 . This first circuit is not limited in terms of frequency height, provided the input bit streams can be generated at a very high speed. The lengths of the high speed input traces are matched, but the channel (PCB, package) can induce disparities. To tackle this issue, a re-synchronization interface is implemented in CKT2.

It uses a fourth input channel which is a clock from the FPGA, at the same frequency as the 3 input bit streams. A frequency doubler allows to create a new clock signal on chip which is used to synchronize the 3 inputs thanks to differential DFFs.

Table 3.6: CKT2 operating currents.

Block Current

Pump 700µA

PPA 20mA

Digital interface 20mA

The design of the high speed digital interface is sensitive to the parasitic elements related to the layout. More precise block diagrams, transistor level circuits and layout views of the digital blocks are provided in Annex 5. The implementation of the core pump together with the PPA sets a minimum frequency for the input. Indeed, the loading capacitance of the pump is fixed by the size of the PPA and a minimum frequency is needed to avoid saturation. CKT3 implements a non-frequency-limited version of the pump. The input frequency range is determined by the off-chip load.

Yoan VEYRAC, IMS Laboratory -December 2015 Table 3.7: CKT3 operating currents.

Block Current

Pump 700µA

This version allows to assess the behavior of the pump over several frequency decades and eventually to replace the capacitive load by a resistive load to measure the mismatching between the current sources.

CKT4: Autonomous pump

A last version of the Riemann Pump is associated with an on-chip high speed digital generator in CKT4. Each data lane has an 8 bits LUT which is perpetually read and fed to the pump switches. The LUTs are loaded thanks to a FIFO which operates as a serial to parallel interface.

Block Current

Pump 700µA

PPA 20mA

Pattern generator 10 -25mA

The pulse generator frequency is tunable within almost an octave around 10 GHz. It allows to store simple 8 slopes patterns and to output the resulting signal. Details about the design of the pulse generator, the FIFO and the LUTs are available in Annex 5.2.2.

Conclusion

The Riemann pump has been designed in 2 completely different technologies for different applications. RADAR applications are targeted by the GaN design which has high power capabilities and robustness. Wireless communication massive market is targeted by the CMOS circuit which benefits from low power devices, high integrability and high speed to face the stringent requirements of next generation mobile terminals.

A lot of techniques have been used and developed in the two designed chips, covering both the analog and digital domains. PLS evidence a virtually transparent impact of the physical implementation since the performances are not distinctly degraded with respect to the theory.

It confirms the adequacy between the proposed architectures and the electrical implementation.

It also suggests that more complex versions of the Riemann Pump should be designed in the targeted technologies, with higher parameters (r,N) to improve the performances and address next generation standards.

Among the 2 designed chips, only the CMOS version has been manufactured. Chapter 4 presents the measurement results carried out on PAULINA.

Printed circuit board (PCB)

A custom two layer PCB has been designed for measurement purposes. Different versions of a single generic PCB are derived for each of the circuits. They differ by the filing of the component footprints. The PCB designed for the test of the standalone circuit is presented in Fig. 4.2 together with the experimental setup.

The supplies are provided through voltage regulators, and decoupled with banks of capacitors as close as possible to the chip. Reference and control voltages are tunable thanks to potentiometers. RF lines are routed differentially, with 50 Ω grounded coplanar wave guide topology.

All the input differential pairs are matched in length so as to insert an equivalent delay.

Serial data analyzer

The output signal of the tested circuit is monitored thanks to a 40 GSps serial data analyzer.

The acquisition of the differential outputs of the circuit is performed independently. The two channels are recombined through a mathematical subtraction within the analyzer. The skew between the 3 bit streams generated by the FPGA is measured on the serial data analyzer in a plane corresponding to the input of the test board. The edges of the 3 bit streams are included in a 30 ps interval.

Matching of current sources

The static DAC characteristics of the Riemann Pump are assessed thanks to DC measurements. • +1 level: a high level on the positive branch and a low level on the negative branch results in a +1 level. The current source controlled by the corresponding bit has a positive contribution on the output current.

• -1 level: a low level on the positive branch and a high level on the negative branch results in a -1 level. The current source controlled by the corresponding bit has a negative contribution on the output current.

• 0 level: if there is a high impedance on both inputs, the two branches are balanced and the corresponding contribution on the output current is null. The system is supposed to work only with the +1 and -1 levels for each of the 3 bits, so as to define 8 distinct output currents. However, the third state allows to generate extra levels between the expected output levels. It gives additional information on the matching of the current sources and the linearity of the system. Different input codes have been tested in order to generate levels from -6 to +6 by step of 1; it is to note that the actual LSB corresponds to 2 steps. The results are reported in Table . 4.2 and the DAC transfer characteristic is plotted in Fig. 4.8.

The worst case DNL is approximately 0.25 LSB, while the worst case INL is as low as 0.13 LSB.

The matching of the current sources results in a linearity which does not degrade significantly the static ENOB.

Yoan VEYRAC, IMS Laboratory -December 2015

Variation of the oversampling factor r

The impact of the oversampling factor on the signal generation quality is assessed. The test bench imposes the same limitations as previously:

• Limited analog frequency for the HZ analyzer inputs

• 40-bit patterns outputted at 8 Gbps for the input streams

The generation of a 400 MHz CW is chosen as the reference to assess the impact of the over-Yoan VEYRAC, IMS Laboratory -December 2015 sampling factor r. The Riemann code of such a sine wave is computed with Matlab in two configurations:

• f s = 8GHz and f max = 1GHz, OSR = fs 2.fmax and r = 2.

• f s = 8GHz and f max = 400M Hz, r = 3.32.

The output spectrum of the two signals generated with Matlab are plotted in Fig. 4.11. The theoretical impact of the oversampling factor is an improvement of 9 dB of the SNR per doubling of the OSR, which also translates into a 9 dB decrease of the quantization noise floor in the spectrum. Among those 9 dB, 6 dB are related to the differential coding and the associated reduction of the quantization error, while the extra 3 dB are related to the spreading of the noise floor. This last effect is valid only when the quantization error is random enough to be considered as a quantization noise with a uniform spectral distribution. The generated signal is defined by a 40-bit pattern, and its frequency has an integer relationship with the working frequency f s . As a consequence, all the power of the quantization error is located in the harmonics of the generated signal. The SNR is thus related to harmonic distortion.

In the present case, the third harmonic is the main contributor in the noise power. The third harmonic level is reduced by 8 dB while the oversampling factor goes from 2 to 3.32. It corresponds to a dependence in 6r in the SNR, which is consistent with the theory. The same signals have been generated by the actual circuit, measured and presented in Fig. 4.12. The level of the third harmonic with respect to the fundamental tone is reported and compared to the theoretical signals in Table The measured levels appear to be lower than the theoretical ones because of the low-pass filtering behavior of the analyzer inputs. However, the relative levels are consistent with the theory and validate the impact of the oversampling factor r. One can notice the presence of the second harmonic in the measured signals whereas it should not appear theoretically. It is due to a mismatch between the two differential outputs.

The measurements on the standalone pump are restricted in frequency and configuration of input signals because of the measurement setup. However, major characteristics have been extracted

and validated:

• DAC features: static linearity and high speed operation with low power consumption.

• Architecture features: impact of the OSR, carrier aggregation.

Yoan VEYRAC, IMS Laboratory -December 2015

Autonomous pump measurements

The second circuit to be tested is the autonomous pump. This circuit is made of an integrated digital pattern generator with 8-bit depth on each of the 3 channels, a Riemann Pump, and a pre-power amplifier which acts as the capacitive load of the pump.

Test bench

The autonomous pump is controlled thanks to a custom 3 bit serial interface driven by an Arduino (Fig.

Power consumption

Table 4.5: Autonomous pump operating current.

Supply voltage 1.2 V

Measured operating current 48 mA

The consumption of the core pump is negligible in the front of the digital interface and the PPA, which draw approximately 20 mA each for a total power consumption of 58 mW.

Triangle waveform generation

The 8-bit patterns enable the generation of simple waveforms. The chosen signal is a triangle wave made of 8 slopes, to evidence the integration of the switched currents into the capacitive input impedance of the PPA. The signal is programmed in the Arduino, sent to the CKT4 serial to parallel digital interface and then loaded in the internal latches. The signal obtained at the output is depicted in Fig. 4.14, both in the time and the frequency domain. Nevertheless, in a similar way as the previous circuit measurements the second harmonic is present and reflects a mismatch in the differential architecture. The signal waveforms obtained on single output branches with schematic simulations exhibit second harmonics with a -15 dBc level but the differential recombination cancels it properly. In the actual measurements, the level of this second harmonic equals -20 dBc in differential mode, which corresponds to a decrease with respect to the single branches, but not a complete cancellation. It could be related both to the circuit operation and the channel mismatches (including bondings, package, PCB traces, connectors and coaxial cables).

Pattern generator operating frequency

The internal oscillator frequency is tunable through an external voltage. The same triangle signal is generated while the frequency tuning voltage is swept from 200 mV to 700 mV. The The operating frequency of the pattern generator decreases as the tuning voltage increases.

The tendency observed in measurements is similar to the simulations, but a frequency shift is observed. The actual oscillator is slower than targeted with schematic simulations, but faster than expected after parasitic extractions. The implemented topology is an 8-stage differential ring oscillator made of differential CMOS inverters. The running frequency is not locked and it is substantially dependent on the transit time of the inverters, the capacitive parasitic elements and the temperature. The obtained frequencies remain in the targeted range of 10 GHz, with a tuning interval of almost 3 GHz. The measurements of the autonomous pump validates the compatibility of the Riemann Pump with a complete transmission chain:

• The co-integration with an uphill high speed digital conditioning block.

• The direct interfacing with a downhill capacitive power amplification stage.

Yoan VEYRAC, IMS Laboratory -December 2015

Prospects

Complete transmitter architecture

The realization of a complete transmitter based on the Riemann Pump requires a digital processing core and a power amplification stage (Fig. 4.16).

Digital processing

Riemann Pump N PA • Redundancies simplification: a modulated signal corresponds to a symbol sequence carried at a specific frequency. For the most common modulation schemes, a given symbol sequence can be associated to its temporal waveform (which solely depends on the carrier phase at the origin) and hence its Riemann or NSR slope sequence. The up-conversion operation is thus highly redundant. Several waveform samples corresponding to symbol sequences should be calculated only once, stored in memories, and addressed by the baseband symbol stream. It would result in a substantial relief of the calculations.

Yoan VEYRAC, IMS Laboratory -December 2015

Power amplification stage

The Riemann Pump architecture is able to generate signals over a wide frequency range. A complete transmitter requires a broadband power amplifier to reach the required output power.

As far as handset devices are concerned, the PA is subject to a trade-off between bandwidth, linearity and efficiency. Depending on the applications, the overall transmitter architecture can include a single wideband PA or several narrowband PAs with a suitable recombination (Fig. 4.18).

Riemann

Generator Wideband PA f f 1 f 2 f f 1 f 2 Riemann Generator f f 1 f 2 PA PA f f 1 f 2 f f 1 f 2 f f 1 f 2 (a) (b)

Riemann receiver

The principle exposed and exploited all along this manuscript is applied to the transmitter side

Conclusion

The characterization of PAULINA validates the principle of an RF transmitter based on the Riemann Pump. The standalone pump circuit is a kind of RF-DAC.

Conclusion

The conversion between the digital data and the analog signal suited for radio transmission is a key enabler for the development of wireless technologies. A lot of researches deal with next generation converters. It mostly involves classical data conversion schemes implemented in recent silicon technologies. This approach is not able to address the stringent expectations of forthcoming standards.

This thesis proposes a disruptive architecture of transmitter that operates the conversion via the derivative of the signal before an integration in the analog domain performed by a DAC named the Riemann Pump. The underlying conversion scheme benefits from the OSR to improve the SNR; a doubling of the sampling frequency results in a 9 dB increase, plus an additional 6 dB with the insertion of a 1st order noise shaping loop within the quantization block.

The design of the Riemann Pump in a 65 nm silicon technology from TSMC underlines its high speed operation capability, with digital command up to 25 Gbps, and its sub-mW consumption.

The resulting ENOB is approximately 5. e q (1) e q (2)

s ) and the steepest negative slope s(1), with the same probability. The quantization error e q (k+1) is thus calculated as the minimum distance between the aim y s (k+1) and each reachable point y r (k) + s(l) fs , where l belongs to [1, 2 N ]; the point that achieves this minimum, chosen as y r (k + 1).

The example given (Fig. ] so that its integral over the whole interval is one. The quantization error e q produced is plotted (solid line) versus ∆y. This error can be expressed as a quantization noise; the distribution of slopes that produces the minimum quantization noise power has then to be determined. This power can be expressed as:

σ 2 e = s(2 N ) s(1)
e 2 q (∆y).p(∆y)d∆y = It gives a total power of:

σ 2 e = 1 12.I tot 2 N -1 m=1 J m 3 (5.3)
Previous problem is equivalent to finding the interval subdivision that minimizes the sum:

J j 3 + J k 3 < J j 3 + J k 3 (5.9)
Let us consider the subdivision that replaces the intervals I j and I k by the interval I j and I k .

This subdivision is noted (I j , I k , I 1 , I 2 , ..., I M ), with respective length (J j , J k , J 1 , J 2 , ..., J M ). The calculation of the quantity S gives:

Yoan VEYRAC, IMS Laboratory -December 2015

Digital circuits details

CKT2: re-clocked pump

The synchronization of input data streams is performed thanks to a reference clock coming from the same bit streams generator. A frequency doubler is designed (Fig.

CKT4: autonomous pump

A digital pattern generator is implemented to feed the Riemann Pump with 8 bit depth periodic streams (Fig. 5.8). This generator receives the wanted bits from an external generator operating at low frequency, through a FIFO. The received data are then loaded in parallel into latches.

The 8 stored bits are sequentially outputted to the Riemann Pump input switches, thanks to a pulse generator (Fig. 5.9). The generation of pulses is illustrated by a timing diagram resulting from a PLS simulation (Fig. 5.10). 8 pulses are generated sequentially to address the 8 stored bits. Nous proposons d'explorer une approche innovante de conversion numérique/analogique, qui concerne à la fois le schéma de codage employé et la topologie sur mesure du convertisseur qui lui est associé.

Résumé du chapitre 2

Une conversion numérique/analogique efficace fondée sur des codages différentiateurs est exposée. Ils bénéficient du codage de la dérivée, éventuellement associé à une mise en forme du bruit de quantification, pour améliorer leurs performances de conversion. Cela mène à un compromis entre la complexité du système et les performances de conversion qui est meilleur que celui des schémas de conversion classiques implémentés dans les convertisseurs numérique/analogique rencontrés dans l'état de l'art. La théorie sous-jacente a été développée et validée grâce à des simulations du système. Cela permet de régler le jeu de paramètres du système, à savoir le nombre de bits N utilisés dans la conversion, ainsi que le facteur de sur-échantillonnage, en fonction de l'application visée.

Le système a été évalué pour les contraintes rudes attendues pour le standard 5G. La génération de 10 porteuses agrégées et intrinsèquement synchronisées, avec une dynamique de 60 dB, peut être effectuée avec les caractéristiques suivantes :

1. 1

 1 Performances of reconfigurable transmitters. . . . . . . . . . . . . . . . . . . . . . 1.2 Performances of direct digital-RF transmitters. . . . . . . . . . . . . . . . . . . . 1.3 Performances of all-digital transmitters. . . . . . . . . . . . . . . . . . . . . . . . 1.4 Performances of RF-DACs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Key features of the classical conversion schemes. . . . . . . . . . . . . . . . . . . 2.1 Modulation features involved in the presented conversion schemes and the related impact of the OSR on the SNR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Features of the zero th and the first-order holds. . . . . . . . . . . . . . . . . . . . 2.3 Conversion architectures theoretical features summary. . . . . . . . . . . . . . . . 2.4 SFDR versus the number of aggregated carriers -(f s , N)=(50 GHz,6). . . . . . . 3.1 GaN principal features for RF electronics. . . . . . . . . . . . . . . . . . . . . . . 3.2 Deviation of the output mean voltage with and without regulation loop. . . . . . 3.3 Output impedance of various current source structures. . . . . . . . . . . . . . . 3.4 Features of the concurrently generated modulations. . . . . . . . . . . . . . . . . 3.5 CKT1 operating currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 CKT2 operating currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 CKT3 operating currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 CKT4 operating currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Standalone pump operating current. . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Standalone pump DC linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Dual carrier spectral components -measurements versus theory. . . . . . . . . . . 4.4 Third harmonic level -measurements versus theory. . . . . . . . . . . . . . . . . 4.5 Autonomous pump operating current. . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Triangle signal harmonic level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 State-of-the-art of RF-DACs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 List of Notations f max Maximum frequency of a useful signal f nyq Nyquist frequency f s Sampling frequency of a DA conversion N Number of bits involved in a DA conversion P n Power of the noise P s Power of a useful signal q Quantum of a DA conversion scheme r Oversampling factor: OSR = 2 r V Voltage amplitude of a CW

1 . 1 1 . 2 1 . 3 Chapter 1 .

 1112131 Wireless communication paradigm . . . . . . . . . . . . . . . . . . . . 1.1.1 Radio frequency transceivers architecture . . . . . . . . . . . . . . . . . 1.1.2 Wireless communication media capacity . . . . . . . . . . . . . . . . . . 1.1.3 Mobile terminal transceivers compatibility . . . . . . . . . . . . . . . . . Software radio transmitters . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Software radio background . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Directions of research for flexible transmitters . . . . . . . . . . . . . . . Data conversion schemes . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Pulse code modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Pulse density modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Conversion efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitters for ubiquitous network Chapter 1 presents the architectural trends for next generation RF transmitters. The first part introduces the wireless communication paradigm. It highlights the forthcoming requirements for handset terminal transceivers and the associated technological bottleneck. The second part presents the tracks which tend to overcome this stumbling block, in relation with the state of the art of flexible transmitters. Finally, the associated conversion schemes efficiency is questioned, claiming for disruptive approaches.

Figure 1 . 1 :

 11 Figure 1.1: Global mobile data traffic (source: Gartner 2015)

Figure 1 . 2 :

 12 Figure 1.2: Classical direct conversion transceiver architecture

Figure 1 . 3 :

 13 Figure 1.3: Venn diagram of the 3-dimensions wireless communication space

Figure 1 . 4 :

 14 Figure 1.4: Software radio transmitter architecture

Figure 1 . 5 :

 15 Figure 1.5: Technology tracks of 5G era

Figure 1 . 6 :

 16 Figure 1.6: From software defined to software radio transmitters

Figure 1 . 7 :

 17 Figure 1.7: Wideband DAC SotA -Conversion efficiency Vs Nyquist bandwidth

•

  the resolution (number of bits used in the conversion) N

Figure 1 . 8 :

 18 Figure 1.8: Quantization -the DA interface

Figure 1 . 9 :Figure 1 . 10 :

 19110 Figure 1.9: Spectrum of an ideally sampled signal

Figure 1 . 11 :

 111 Figure 1.11: Nyquist PCM DAC architecture

Figure 1 . 15 :

 115 Figure 1.15: First order sigma delta block diagram

Figure 1 . 16 :

 116 Figure 1.16: First order sigma delta z-transform diagram

Figure 1 . 18 :

 118 Figure 1.18: Efficiency of global digital to analog conversion

Figure 2 . 1 :Figure 2 . 2 :

 2122 Figure 2.1: Open loop DPCM diagram

Figure 2 . 3 :

 23 Figure 2.3: Quantization error for DPCM

Figure 2 . 4 :

 24 Figure 2.4: DPCM z-transform block diagram.

Figure 2 . 5 :

 25 Figure 2.5: Noise Shaping Riemann conversion process.

Figure 2 . 6 :

 26 Figure 2.6: Noise Shaping Riemann Z-transform block diagram.

Figure 2 . 7 :

 27 Figure 2.7: Signal integration principle.

Figure 2 . 8 :Figure 2 . 9 :

 2829 Figure 2.8: Riemann Pump Architecture.

Figure 2 . 10 :Figure 2 . 11 :

 210211 Figure 2.10: Impact of the DA reconstruction on the spectrum.

Figure 2 . 12 :

 212 Figure 2.12: Frequency response of the first-order hold.

Figure 2 .

 2 Figure 2.13: zero th and first-order holds impulse and freuency responses.

Fig. 2 .

 2 Fig. 2.14 presents the Matlab signal generation flow, which is decomposed in 4 steps.

Figure 2 . 14 :

 214 Figure 2.14: Matlab signal generation.

Figure 2 . 15 :

 215 Figure 2.15: Temporal calculation of the SNR.

Figure 2 . 16 :

 216 Figure 2.16: Spectral representation of a CW signal.

Figure 2 . 18 :

 218 Figure 2.18: SNR of the Riemann conversion versus N / r=2.

Figure 2 . 19 :

 219 Figure 2.19: SNR of the NSR conversion versus N / r=2.

Figure 2 . 20 :

 220 Figure 2.20: SNR of the Riemann conversion versus r / N=3.

Fig. 2

 2 Fig. 2.21.

Figure 2 . 21 :

 221 Figure 2.21: SNR of the NSR conversion versus r / N=3.

Fig. 2 .Figure 2 . 22 :Figure 2 . 23 :

 2222223 Fig. 2.22 presents the results for the Riemann conversion.

Figure 2 . 24 :

 224 Figure 2.24: SNR of the NSR conversion versus frequency (r,N)=(2,3).

Figure 2 . 25 :

 225 Figure 2.25: Piecewise linear CW spectrum -NSR conversion.

Figure 2 . 26 :

 226 Figure 2.26: First phase of the sub-6 GHz 5G spectral mask.

2 . 27 .

 227 The noise floor is flat over the whole band and located at 55 dB under the level of the channels, the SFDR for this signal is thus 55 dB. The constellation obtained after the demodulation of the channel centered at 3.5 GHz is presented in the same figure. The obtained EVM is approximately 1%, which represents a good figure for usual modulations used in wireless communications.

Fig. 2 .Figure 2 . 27 :

 2227 Fig. 2.28 displays the SFDR obtained with the Riemann algorithm versus the number of bits N and the sampling frequency f s . The behavior of the SFDR for the generated signal is exactly the same as the SNR, i.e an improvement of 6 dB per additional bit and 9 dB per doubling of the sampling frequency. The assumption of a uniform distribution of the quantization noise floor over the

Figure 2 . 28 :

 228 Figure 2.28: SFDR for 10 aggregated channels -Riemann conversion.

Figure 2 . 29 :

 229 Figure 2.29: Spectrum of 10 aggregated channels -NSR conversion (f s , N)=(50 GHz, 6).

Figure 2 . 30 :

 230 Figure 2.30: SFDR for 10 aggregated channels -NSR conversion.

Figure 3 . 1 :

 31 Figure 3.1: GaN atomic composition

  realization of heterostructures AlGaN/GaN enables the development of HEMT transistors [50] [51] [52]. The heterojunction forms a Schottky contact and spontaneous piezoelectric polarization induces the accumulation of a 2 degrees electron gas. It forms a channel close to the interface, in the GaN layer as represented in Fig. 3.2.

Figure 3 . 2 :

 32 Figure 3.2: GaN HEMT sectional view

Figure 3 . 3 :

 33 Figure 3.3: Electrical characteristics of N-type HEMTs

Figure 3 . 4 :Figure 3 . 5 :

 3435 Figure 3.4: Slope set generation

Figure 3 . 6 :

 36 Figure 3.6: GaN circuit schematic view

7 Figure 3 . 7 :Figure 3 . 8 :

 73738 Figure 3.7: Top rail current generation

Figure 3 . 9 :

 39 Figure 3.9: Switching stage

R 1 Figure 3 . 10 :

 1310 Figure 3.10: Regulation loop

Figure 3 .Figure 3 . 12 :

 3312 Figure 3.11: Input buffer

Table 3 . 2 :

 32 Technological dispersion and temperature changes can cause mismatching between the current sources and induce an imbalance between the rails. The errors being cumulative, the output voltage can drift and provoke the saturation of the signal. The regulation block is in charge of balancing those discrepancies and ensure a proper operating point for the pump. The impact of temperature and technological dispersion on the output average voltage is assessed through the generation of a sine wave. The temperature is swept from -25 o C to +75 o C. As for technological dispersion, a Gaussian distribution is applied over the typical values, with respect to the parameters provided with the DK. Different runs corresponding to a random selection of all the parameters are then launched. The output average voltage dispersion is reported, with and without the regulation loop. Deviation of the output mean voltage with and without regulation loop.

Figure 3 . 13 :

 313 Figure 3.13: Power spectral density of the generated chirp

  3.14) takes advantage of the specificities offered by the target CMOS technologies to optimize the performances in terms of working frequency, power consumption and dynamic range. The designed Riemann Pump has an integrating complementary differential current steering topology.

Figure 3 . 14 :

 314 Figure 3.14: Topology of the Riemann Pump in CMOS technology

Figure 3 . 15 :

 315 Figure 3.15: Schematic view of the core Riemann Pump in CMOS technology

Figure 3 Figure 3 . 17 :

 3317 Figure 3.16: PPA schematic

Figure 3 . 18 :

 318 Figure 3.18: Static voltage characteristic of the PPA

Figure 3 . 19 :

 319 Figure 3.19: Bottom and top rail current sources

Figure 3 . 20 :

 320 Figure 3.20: Current sources characteristics

Figure 3 . 21 :

 321 Figure 3.21: Top and bottom rails current source characteristics

Figure 3 .

 3 Figure 3.22: Switching stage

Fig. 3 .Figure 3 . 23 :

 3323 Fig. 3.23 exhibits the temporal evolution of the output current when the inputs are switched. The implemented structure with complementary switches is compared with a non-complementary structure, composed of only NMOS on the bottom rail and PMOS on the top rail. The simple structure suffers from the phenomenon of charge injection during the switching; it causes large spikes in the output current which are integrated in the loading capacitance. Charge injection occurs when a switched transistor is turned off; the carriers released from the channel induce a charge transfer. In the designed complementary MOS switches, an NMOS and a PMOS of same width are associated in parallel. When they are turned off, the negative charges released by the NMOS are compensated by the positive charges released by the PMOS.

Figure 3 . 24 :

 324 Figure 3.24: Common mode regulation loop

Figure 3 . 25 :

 325 Figure 3.25: Block diagram of the regulation loop

Figure 3 . 26 :

 326 Figure 3.26: Loop transconductance gain

igure 3 . 27 :

 327 Bode diagram of the open loop transfer function

Figure 3 . 28 :Figure 3 . 29 :

 328329 Figure 3.28: Layout of the core pump

Figure 3 .

 3 Figure 3.30: PLS flow

Figure 3 . 31 : 3

 3313 Figure 3.31: 3 GHz generated CW -PLS -(a) Riemann and (b) NSR

Figure 3 .

 3 Figure 3.32: SFDR -PLS Vs theory -Riemann and NSR

Figure 3 . 33 : 3 . 2 . 4 . 2 4 Table 3 . 4 :

 3333242434 Figure 3.33: SNR -PLS Vs theory -(a) Riemann and (b) NSR

Figure 3 . 34 :

 334 Figure 3.34: Spectra of the concurrently transmitted signals -(a) Riemann and (b) NSR

Figure 3 . 35 :

 335 Figure 3.35: Eye patterns and constellations for the concurrent modulated signals -(a) Riemann and (b) NSR

Figure 3 . 36 :

 336 Figure 3.36: PAULINA layout view

FPGA 2 Figure 3 Figure 3 .

 233 Figure 3.37: CKT1 Architecture

  Figure 3.39: CKT3 Architecture

Packaging

  Yoan VEYRAC, IMS Laboratory -December 2015 Chapter 4 presents the experimental results obtained with the chip. The prototypes are presented together with the test bench developed to perform the characterization. Several aspects are validated, both concerning the theoretical aspects of the DA conversion and the implementation of the circuit in silicon. The co-integration of the Riemann Pump with a digital control interface and an amplification stage is also demonstrated. Prospects toward the development of a complete transmitter are discussed. System level topologies and the implementation in advanced silicon technologies are envisioned. Key words: Characterization, Chip, DAC, Measurement, Prototype The prototyped chip PAULINA was designed in a 65 nm CMOS low power technology from TSMC. Chips are packaged in 64-pin sealed lids QFN package. A picture of the chip in an open QFN64 package is presented in Fig. 4.1, together with a microphotograph of the chip and the associated pinout.

Figure 4 . 3 :Figure 4 . 5 :

 4345 Figure 4.3: Test bench of the standalone pump

Figure 4 . 6 :

 46 Figure 4.6: DC measurement test bench

Figure 4 . 7 :

 47 Figure 4.7: DC measurement input configuration

Figure 4 . 8 :

 48 Figure 4.8: Standalone pump transfer function

Figure 4 . 10 :Frequency

 410 Figure 4.10: Dual carrier spectrum

Figure 4 . 11 :

 411 Figure 4.11: Variation of the oversampling factor r -theoretical spectra

  .

4 . 4 .

 44 Yoan VEYRAC, IMS Laboratory -December 2015

Figure 4 . 12 :

 412 Figure 4.12: Variation of the oversampling factor r -measured spectra

Figure 4 . 13 :

 413 Figure 4.13: Test bench of the autonomous pump

  the level of the first two harmonics and compares it with simulation results.

Figure 4 . 14 : 3

 4143 Figure 4.14: Triangle signal spectrum and waveform

frequency of the oscillator equals 8

 8 times the frequency of the output triangle. The obtained frequencies are presented in Fig.4.15, together with the schematic and post-layout simulations.

Figure 4 . 15 :

 415 Figure 4.15: Oscillator frequency versus tuning frequency

Figure 4 . 16 :Figure 4 . 17 :••

 416417 Figure 4.16: Complete transmitter based on the Riemann Pump

Figure 4 . 18 :

 418 Figure 4.18: Power amplification stage topology (a) single wideband PA (b) multiple-path PA

  of a transceiver. All the exposed theoretical features concerning the DA conversion schemes are compatible with the receiver side, where is becomes AD conversion. The variations of a received signal are quantized and sampled instead of its absolute value. The corresponding architecture is depicted in Fig.4.19.

Figure 4 . 19 :

 419 Figure 4.19: Differentiating receiver based on the Riemann Pump

5 . 1 Fig. 5 .

 515 Fig. 5.1 depicts the principle of signal reconstruction. The wanted signal is represented in solid line.

Figure 5 . 1 :

 51 Figure 5.1: Riemann reconstruction process

5

 5

. 2 )Figure 5 . 2 :

 252 Figure 5.2: Quantization error versus the relative position of the next targeted point (∆y)

1 )

 1 Let us note I m = [ s(m) fs ; s(m+1) fs ] of length J m = s(m+1)-s(m) fs , andJ tot = s(2 N )-s(1)fs .The function e q over each interval I m is a triangular shaped function with unity slope with respect to ∆y. The power of the quantization noise integrated over any interval I m is thus:

2 N - 1 m=1 J m 3 ,Figure 5 . 3 :

 1353 Figure 5.3: Intervals re-arrangement

5 . 4 )Figure 5 . 5 :Figure 5 . 7 :

 545557 Figure 5.4: Frequency doubler block diagram

Figure 5 . 8 :Figure 5 . 9 :

 5859 Figure 5.8: Block diagram of the pattern generator

Figure 5 . 10 :Figure 5 . 11 :

 510511 Figure 5.10: Generation of the pulses -PLS

Figure 5 . 12 :

 512 Figure 5.12: Layout of the pattern generator

  Index terms: Digital to analog converter, Waveform generator, Software radio.Contribution à l'étude et à la réalisation d'un générateur de signaux radiofréquences analogiques pour la radio logicielle intégraleRésumé: Une utilisation intelligente de l'espace Hertzien sera nécessaire pour permettre au nombre croissant d'objets sans-fil connectés de communiquer dans le même espace de propagation. Ces travaux de thèse proposent une architecture d'émetteur radiofréquence flexible, faible coût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur est fondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétique de la conversion de l'information. Un convertisseur numérique analogique compatible avec cette architecture est présenté et ses performances sont évaluées dans le cadre de la génération de signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé en technologie CMOS 65 nm apporte la preuve du concept. Mots clés: Convertisseur numérique-analogique, Générateur de signaux, Radio logicielle intégrale. Résumé étendu L'espace Hertzien qui relie les terminaux connectés au réseau filaire est régulé par de nombreux standards. La prochaine génération de communications sans-fil requiert une utilisation intelligente et flexible des ressources spectrales afin d'augmenter la capacité de trafic de données du réseau. Cette tendance impose des contraintes sévères sur la conception des émetteurs/récepteurs mobiles. Ils doivent supporter des débits de données élevés, des larges gammes de fréquences et des schémas de modulations variés, tout en arborant une consommation réduite en accord avec les faibles quantités d'énergie stockées dans les terminaux mobiles. Le chapitre 1 expose le paradigme des communications radio et l'évolution des architectures d'émetteurs/récepteurs. Il souligne la tendance à améliorer la flexibilité des émetteurs sans-fil par le biais d'une utilisation accrue de l'électronique numérique, selon le principe de la radio logicielle. Le gain de flexibilité important est modéré par la consommation énergétique trop élevée, en particulier en ce qui concerne l'opération de conversion numérique/analogique. Les schémas classiques de conversion de données sont étudiés et leurs limites sont abordées. Le chapitre 2 propose l'étude théorique de schémas de conversion en rupture avec les méthodes traditionnelles, ainsi que celle d'une topologie de convertisseur numérique/analogique adapté. Ces techniques de conversion sont fondées sur le principe de la modulation Delta, mise en jeu dans certains systèmes de compression des données. Le processus de conversion traite les variations temporelles du signal, grâce à un codage numérique différentiateur qui permet d'améliorer l'efficacité de conversion de manière significative. La reconstruction du signal est réalisée grâce à un convertisseur numérique/analogique intégrateur sur mesure, que l'on appelle la Pompe de Riemann. Les performances du système proposé sont évaluées vis-à-vis de la génération de signaux radiofréquences. Le chapitre 3 décrit la conception de la Pompe de Riemann dans deux technologies intégrées. La première est une technologie GaN dédiée aux applications militaires. La seconde est une technologie silicium 65 nm adaptée au marché de l'électronique grand public. La conception de deux circuits est détaillée, et des simulations post-routage sont présentées. Elles valident la compatibilité de l'architecture proposée avec les technologies ciblées, et permettent d'en estimer les performances. Le chapitre 4 présente les mesures menées sur le démonstrateur réalisé en technologie silicium 65 nm. Les résultats réalisés apportent la preuve du concept. Une amélioration des capacités du banc de test est requise pour aller plus loin dans la caractérisation des prototypes. Des pistes sont proposées pour développer un émetteur complet autour de la Pompe de Riemann. Résumé du chapitre 1 Yoan VEYRAC, IMS Laboratory -December 2015 La convergence technologique, les habitudes des utilisateurs et la densité des appareils connectés impliquent une augmentation massive du volume de données sans-fil. La structure du réseau doit changer significativement pour assumer cet afflux de données. Les émetteurs/récepteurs de terminaux mobiles doivent satisfaire 3 contraintes majeures afin d'assurer leur compatibilité avec un réseau qui sera hétérogène : • Bas coût : une solution peu onéreuse est nécessaire pour s'adresser à un marché de masse. La technologie la plus approprié est le CMOS • Faible consommation : les systèmes de communications doivent assurer un fonctionnement à faible puissance, pour sauvegarder la durée de vie de la batterie • Bande passant large : les débits de données mis en jeu seront très important, il faut donc assurer une large bande passante Les émetteurs radio logicielle fondés sur la conversion directe de larges bandes de fréquence semblent être de bons candidats pour fournir une flexibilité absolue. En revanche, la consommation importante des convertisseurs radiofréquences les rend difficilement intégrables dans les appareils mobiles. La réalisation d'un émetteur qui serait compatible avec les contraintes de consommation nécessite une approche de conversion en rupture avec les architectures conventionnelles, afin d'améliorer l'efficacité de conversion et de passer outre cette pierre d'achoppement majeure.

6 •Résumé du chapitre 3 LaRésumé du chapitre 4

 634 Yoan VEYRAC, IMS Laboratory -December 2015 • Schéma de conversion : conversion de Riemann avec mise en forme du bruit • Nombre de bits N : Fréquence de conversion : f s =40 GHz Ces caractéristiques peuvent être compatibles avec les dernières technologies CMOS. Cependant, notre objectif est d'apporter une preuve du concept. Le chapitre 3 expose le flot de conception des démonstrateurs de la Pompe de Riemann dans plusieurs technologies. Il présente les schémas électriques et les plans de routage, ainsi que les résultats de simulation associés. Pompe de Riemann a été conçue dans deux technologies complètement différentes, pour des applications différentes. Des applications RADAR sont envisagées avec le circuit an GaN, avec de fortes puissances et une grande robustesse. Le circuit en CMOS cible le marché des communications sans-fil. Grâce à sa faible consommation, sa grande bande passante et sa petite taille, il est en adéquation avec les contraintes de la prochaine génération des terminaux mobiles. De nombreuses techniques ont été utilisées lors de la conception des deux puces, relevant à la fois du domaine analogique et du domaine numérique. Les simulations post-routage mettent en évidence un impact réduit de l'implémentation physique, en ce sens que les performances ne sont pas dégradées de manière significative par rapport à la théorie. Cela confirme l'adéquation entre l'architecture proposée et son implémentation électrique. Cela suggère également que des versions plus complexes de la Pompe de Riemann peuvent être conçues dans les technologies utilisées, avec un nombre de bits plus élevé afin d'améliorer les performances et de pouvoir s'adresser aux standards de nouvelle génération. Parmi les deux puces développées, seule la version en CMOS a été fondue. Le chapitre 4 présente les résultats de mesure obtenus avec la puce baptisée PAULINA. La caractérisation de la puce PAULINA valide le principe d'un émetteur radiofréquence fondé sur le principe de la Pompe de Riemann. Le circuit caractérisé peut être vu comme un CNA radiofréquence. Le facteur de mérite (FdM) choisi pour évaluer ce convertisseur est le coût énergétique de la conversion (en picojoule par pas de conversion).

F dM = P 2

 2 Rés .BP(5.12) Avec: P la puissance consommée, Rés la résolution en nombre de bits effectifs, et BP la bande passante du convertisseur Yoan VEYRAC, IMS Laboratory -December 2015 La Pompe de Riemann, associée à un schéma de codage avec mise en forme du bruit de quantification, permet d'obtenir une efficacité de conversion de 5.1 fJ par pas de conversion. De plus, la surface active du circuit est restreinte, avec 0.2 mm 2 pour le prototype réalisé. Cela met en lumière le potentiel de la technologie présentée, dans le cadre du développement d'un émetteur radio logicielle bas coût et basse consommation pour les prochaines générations de communications sans-fil.ConclusionLa conversion entre les données numériques et les signaux analogiques mis en oeuvre pour les émissions radio est un point clé du développement des technologies sans-fil. De nombreuses recherches traitent des convertisseurs de nouvelle génération. Ils emploient principalement des schémas de conversion classiques, implémentés dans des technologies silicium récentes. Cette approche n'est pas à même de répondre aux attentes exigeantes des standards à venir. Ce travail de thèse présente une architecture originale d'émetteur, qui opère la conversion via la dérivée du signal avant une intégration dans le domaine analogique réalisée grâce à un CNA que l'on baptise la Pompe de Riemann. Le principe de conversion sous-jacent tira avantage du sur-échantillonnage pour améliorer le rapport signal sur bruit. Un doublement de la fréquence d'échantillonnage permet d'améliorer le rapport signal sur bruit de 9 dB, et de 6 dB supplémentaires grâce à l'insertion d'une boucle de mise en forme du bruit de quantification du premier ordre. La conception de la Pompe de Riemann en technologie silicium 65 nm souligne sa propension à travailler à haute fréquence, avec une commande numérique pouvant aller jusqu'à 25 Gbps, et sa consommation inférieure au milliwatt. La résolution qui en découle vaut 5,4 bits effectifs, pour une bande passante supérieure à 3 GHz. Le coût énergétique de conversion du circuit développé se classe dans les meilleurs de l'état de l'art des convertisseurs radiofréquences, avec une efficacité de 5 fJ par pas de conversion. Un démonstrateur de la Pompe de Riemann a été fabriqué puis caractérisé. Les résultats obtenus apportent une preuve du concept. La co-intégration avec un bloc de calcul numérique et un amplificateur en sortie est également démontrée. Les prochaines générations de standards de communication sans-fil seront censées regrouper des spécifications techniques irréalistes, avec une amélioration d'un facteur 10 dans toutes les performances clés (dont le débit de donnée et la consommation). Cela va nécessiter de véritables percées dans la course à la réduction du coût de l'information en termes d'énergie. L'implémentation d'architectures classiques dans les technologies les plus avancées ne sera pas suffisante pour atteindre de tels objectifs. L'approche développée dans thèse s'inscrit dans la tendance du « Design by Mathematics ». Elle propose de développer des circuits et systèmes originaux grâce à l'adéquation entre des principes mathématiques et leur implémentation électronique. Yoan VEYRAC, IMS Laboratory -December 2015

Table 1 . 1 :

 11 Performances of reconfigurable transmitters.

		Bandwidth	RF range	Consumption	CMOS node
		(MHz)	(GHz)	(mW)	(nm)
	[15]	16	0.15 -6	100	130
	[16]	20	0.7 -2.7	200	90
	[17]	40	0.05 -6	900	130
	[18]	100	0.1 -6	103	65
	1.2.2.

2 Direct digital-RF transmitters

Direct digital-RF transmitters try to merge the DAC and the mixer operation, with only digital inputs. It simplifies the analog front-end and tries to give more flexibility through the increased use of digital signals. A lot of silicon chips realizations confirm the feasibility to integrate it into handset terminals.

Table 1 .

 1 2: Performances of direct digital-RF transmitters.

		Bandwidth	RF range	Consumption	Implementation
		(MHz)	(GHz)	(mW)
	[19]	200	5.25	187	130 nm CMOS
	[20]	50	0.05 -1	120	90 nm CMOS
	[21]	4	0.9 & 1.9	250	-
	[22]	80	2.2	510	40 nm CMOS
	[23]	20	2.4	515	65 nm CMOS
	[24]	150	0.06 -3.5	560	65 nm CMOS

Yoan VEYRAC, IMS Laboratory -December 2015

Table 1 .

 1 3: Performances of all-digital transmitters.

		Bandwidth	RF range	Architecture	Implementation
		(MHz)	(GHz)
	[26]	20	0.8	PWM	FPGA
	[27]	-	1 -13	SDM-LUT	Instrumentation
	[28]	2	0.8	SDM	FPGA
	[29]	2	2.5	SDM	FPGA + instrumentation

Table 1 .

 1 4: Performances of RF-DACs.

		Data rate	Resolution	Consumption	Efficiency
		(Gsps)	(bits)	(mW)	(mW.s/Gbit)
	[36]	9	13	360	3.1
	[32]	2.9	12	188	5.4
	[35]	6	14	600	7.1
	[37]	5	9	375	8.3
	[33]	28	6	2250	13.4
	[34]	7.2	14	4600	45.6

ranging from hundreds of milliWatts to the Watt level. The consumption efficiency (mW.s/Gbit) is displayed in Fig.

1

.7 versus the Nyquist bandwidth of the listed DACs. It corresponds to the power consumption divided by the data rate involved in the conversion.

The Riemann Pump Contents 2.1 Differential digital to analog conversion

. . . . . . . . . . . . . . . . . 2.1.1 Differential Pulse Code Modulation (DPCM): Riemann . . . . . . . . . 2.1.2 Noise Shaping Riemann conversion (NSR) . . . . . . . . . . . . . . . . . 2.1.3 RF conversion schemes summary . . . . . . . . . . . . . . . . . . . . . . 2.2 The Riemann Pump: an integrating DAC . . . . . . . . . . . . . . . 2.2.1 Implementation of the digital to analog integration . . . . . . . . . . . . 2.2.2 Analog reconstruction features . . . . . . . . . . . . . . . . . . . . . . . 2.3 Simulation of the Riemann Pump architecture . . . . . . . . . . . . . 2.3.1 System simulation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 SNR performances: simulation results versus theory . . . . . . . . . . . 2.3.3 Concurrent transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 2. The Riemann Pump Chapter 2 presents conversion schemes based on the digital differentiation of the encoded signal and their integration within the DAC operation. Theoretical features of those conversion schemes are studied and modeling SNR equations are obtained. The Riemann Pump is presented as the integrating DAC needed to recover the analog signal. Its reconstruction characteristics are exposed. Finally, system simulations are led to assess the validity of the theory with respect to the key parameters of the architecture. The application to sub-6 GHz 5G transmission schemes is highlighted and a suited sizing of the architecture parameters is proposed. Key words: Carrier aggregation, Concurrent transmission, Differential Pulse Code Modulation (DPCM), Quantization noise, Riemann Pump, Signal to Noise Ratio (SNR), Sub-6 GHz 5G

Table 2 .

 2 1: Modulation features involved in the presented conversion schemes and the related impact of the OSR on the SNR.

		Oversampling	1 st order Noise Shaping	Differentiating	TOTAL (dB)
	Impact on the SNR (dB)	3r	6r	6r
	Pros	Ease the filtering of the replicas	High impact on the SNR	Reduction of the total quantization noise
			Need of a	Potential
	Cons		minimum OSR and efficient	overload distortion and
			filtering	output drift
	PCM	x			3r
	SDM	x	x		9r
	Riemann	x		x	9r
	NSR	x	x	x	15r

The use of differential codes is totally missing in the RF wireless transmitters field. The benefits of this kind of coding can help to reduce the complexity of the DAC for a given accuracy, so as to meet SR transmitter constraints in terms of power consumption. The OSR that is affordable is related to the technology used and the wanted bandwidth. Depending on its value, noise shaping can be added in the conversion. The implementation of this technique simply impacts the digital computation block; it remains compatible with the same topology of DAC. For all these reasons, we propose an architecture which relies on differentiating codes. The next section considers DAC features that are induced by the choice of this architecture and exposes the development of a suited RF-DAC topology, called the Riemann Pump.

Yoan VEYRAC, IMS Laboratory -December 2015 2.

2 The Riemann Pump: an integrating DAC 2.2.1 Implementation of the digital to analog integration

  The presented differentiating conversion schemes generate bit streams that are representative of the derivative of the wanted signal. In the overall digital to analog conversion architecture, the DAC has to generate an analog version of the wanted signal by integration of its input digital signal. From an electronic point of view, the relation integral/derivative is embodied by the basic reactive passive components: capacitor and inductance. Those components are modeled by first order differential equations between the current i and the voltage v. Capacitors are easier to implement in integrated technologies and show better quality factors. Their fundamental equation is:

  2.10.

	Ideal low pass DA reconstruction	Spectrum	Typical DA reconstruction
	Digital signal		amplitude
	spectrum
	-fs	-fs/2	fs/2	fs	Frequency
	DA reconstruction
		Spectrum	Reconstructed
		amplitude	analog signal
	-fs	-fs/2	fs/2	fs	Frequency

Table 2 . 2 :

 22 Features of the zero th and the first-order holds.

		Zero order	First order
	Impulse response	Square	Triangle
	Frequency response	sinc( f fs )	sinc 2 ( f fs )
	-3dB bandwidth	0.44f s	0.32f s
	-1dB bandwidth	0.26f s	0.18f s
	Corresponding r	0.94	1.5
	1 st lobe level	-13dB	-26.4dB

Table 2 .

 2

	Coding		Dependence of the SNR	Reconstruction
	scheme		Total noise	/	In-band noise	filter
	Riemann	6N	6r		3r	sinc 2 ( f fs )
	NSR	6N	6r		9r	sinc 2 ( f fs )

3: Conversion architectures theoretical features summary.

Table 2 .

 2 4: SFDR versus the number of aggregated carriers -(f s , N)=(50 GHz,[START_REF] Pirinen | A brief overview of 5g research activities[END_REF].

	Number of carriers	2	4	6	8	10
	SF DR Riemann (dB)	62	59	57	56	55
	SF DR N SR (dB)	74	71	69	68	67

Circuits design and Implementation Contents 3.1 Integration in GaN technology

  Chapter 3. Circuits design and ImplementationChapter 3 presents the integration of the Riemann Pump in two technologies. The first one is a GaN technology, dedicated to military applications. The second one is a 65 nm CMOS technology, dedicated to address the mobile market requirements. For each target technology, the design of the Riemann Pump is exposed from the topology to the layout. Post layout simulations are exhibited to assess the impact of the implementation and determine the key performances in terms of area and consumption.

• Number of bits: 6 • Conversion frequency: f s =40 GHz Those features could be compatible with the latest CMOS technologies capabilities. However, our purpose is to bring a proof of concept. Chapter 3 exposes the design flow of Riemann Pump demonstrators implemented in different technologies. It presents the schematic and layout design, with the associated simulation results. Yoan VEYRAC, IMS Laboratory -December 2015 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . 3.1.1 GaN technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Riemann Pump in GaN technology . . . . . . . . . . . . . . . . . . . . . 3.1.3 Transistor level design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Integration in CMOS technology . . . . . . . . . . . . . . . . . . . . . 3.2.1 Architecture in CMOS technology . . . . . . . . . . . . . . . . . . . . . 3.2.2 Core pump circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Riemann Pump layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Post-Layout Simulations (PLS) . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Chip design -PAULINA . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key words: Circuit design, CMOS, GaN, Layout, Post-layout simulations, RF-DAC

Table 3 .

 3 1: GaN principal features for RF electronics.

Table .

 .

	3.3

Yoan VEYRAC, IMS Laboratory -December 2015

Table 3 .

 3 3: Output impedance of various current source structures.

	Relative variations of I V out ∈ [0.4V -0.8V ]	Output impedance
	Simple source	15.2%	40kΩ
	1 cascode stage	1%	640kΩ
	2 cascode stages	0.12%	8M Ω
	The 2 stage cascoded structure is then implemented, both on the bottom rail with NMOS
	transistors and on the top rail with PMOS transistors. The 2 current source characteristics are
	displayed together in Fig. 3.21.

  .32.

	50
	48				NSR Matlab
	46				NSR PLS
	44
	42
	40
	38
	36
	34
	32
	30				Riemann Matlab
	28				Riemann PLS
	500	1000	1500	2000	2500	3000

Table 4 .

 4 1: Standalone pump operating current.

	Yoan VEYRAC, IMS Laboratory -December 2015

Table 4 .

 4 2: Standalone pump DC linearity.

	A(MSB)	B	C(LSB)	Code	Current (µA)	INL	DNL
	1	1	0	6	223	0.13	0.15
	1	0	1	5	178	-0.02	0.106
	1	0	0	4	148	0.03	0.04
	1	0	-1	3	110	-0.01	0.08
	1	-1	0	2	70	-0.09	0.01
	0	1	-1	1	34	-0.11	0.02
	0	0	0	0	-1.6	-0.12	-0.25
	0	-1	1	-1	-18.3	0.13	0.2
	-1	1	0	-2	-67	-0.07	-0.05
	-1	0	1	-3	-97	-0.02	-0.14
	-1	0	0	-4	-121	0.13	0.08
	-1	0	-1	-5	-162	0.05	0.06
	-1	-1	0	-6	-201	-0.02	0
	Note: Each configuration contains at least one high impedance input. Only two inputs could be
	forced (at a +1 or -1 level) at the same time because of hardware issues with the FPGA outputs.

Table 4 . 4 :

 44 Third harmonic level -measurements versus theory.

	f max (GHz)	Oversampling factor r	Theoretical signal (Matlab)	Measured signal
	0.4	3.32	-35 dBc	-38 dBc
	1	2	-27 dBc	-30 dBc
			∆ : 8dBc	∆ : 8dBc

  Table. 4.14 gathers

	Yoan VEYRAC, IMS Laboratory -December 2015

  Table.4.7 compares the Riemann Pump with the state-of-the-arf RF-DACs. The figure of merit chosen to compare the DACs is the energy cost of the conversion step (in fJ/conv):

	F OM =	P ower 2 EN OB .BW	(4.1)

Yoan VEYRAC, IMS Laboratory -December 2015

Table 4 .

 4 7: State-of-the-art of RF-DACs.

	Reference	ENOB*	BW* (GHz)	Consumption (mW)	Process	Active area (mm 2 )	FOM (f J/conv)
	[33]	6	14	2250	90 nm CMOS	0.28	2511
	[37]	9	2.5	375	40 nm CMOS 1.65 (chip)	293
	[34]	14	3.6	3600	BiCMOS	112	78
	[32]	12	1.45	188	65 nm CMOS	0.31	31.6
	[35]	14	3	600	180 nm CMOS	28.5	12.2
	[36]	13	4.5	360	28 nm CMOS	1.16	9.7
	Riemann Pump -NSR conversion	5.4	3.125	0.68	65 nm CMOS	0.2	5.1

* Measured values are not available for all the references. The ENOB and bandwidth are the nominal theoretical values.

The Riemann Pump associated with the NSR coding scheme exhibits the best figure of merit, with 5.1 fJ per conversion step. Furthermore, the active area of the presented circuit is the smallest of the reported chips. It highlights the potential of the presented topology to develop a low power and low cost software radio transmitter for the next generation of wireless communications.

Yoan VEYRAC, IMS Laboratory -December 2015

r+1 Yoan VEYRAC, IMS Laboratory -December 2015

Remerciements

Chapter 4. Measurement results and prospects

The approach developed in this thesis is in the trend of Design by Mathematics philosophy. It proposes to develop disruptive circuits and systems thanks to the adequacy between mathematical principles and their electronical implementation.

Yoan VEYRAC, IMS Laboratory -December 2015

List of Abbreviations

Characterization of the prototypes

The characterization of the Riemann Pump is done along 2 axes associated to 2 different circuits:

• Characterization of the standalone pump (CKT3) is done to assess the performances of the Riemann Pump itself.

• Measurements on the autonomous Pump (CKT4) evaluate the potentiality of a cointegration of the Riemann Pump with an input digital logic stage and an output amplifier stage.

Dual carriers

The carrier aggregation principle is assessed with the concurrent generation of 2 sine waves. The test bench is the same:

• FPGA: 40-bit patterns outputted at f s ≈ 8GHz : f max = 1GHz for an oversampling factor r = 2. The generated signal periods must have an integer relationship with the 40-bit pattern.

• Serial data analyzer: 1M Ω//16pF analyzer input impedance. The high input impedance mode is to be used to sense the output voltage with as low as possible disturbances. However, it results in a limited analog bandwidth (≈ 1GHz).

Taking into account these limitations and constraints, the frequency of the generated sine waves 2 ns / div 5 mV / div

157

Lemma 1: Given any real interval I of length J, the subdivision in two intervals I 1 and I 2 of respective length J 1 and J 2 that minimizes the quantity J 3 1 +J 3 2 is the uniform subdivision, such that J 1 = J 2 .

Demonstration:

Let x be a real such that J 1 (x) = x, and J 2 (x) = J -x, x ∈ [0, J]. The quantity of interest is: 3 (5.4)

The calculation of the derivative gives:

The first derivative vanishes for:

x 2 = (J -x) 2 (5.7)

Provided J = 0, the unique solution of the equation gives x = J 2 , that corresponds to an extremum of the function S; this extremum being a minimum since the second derivative of S is always positive. The quantity J 3 1 + J 3 2 is thus minimized when J 1 = J 1 = J 2 , i.e. for a uniform subdivision.

Let us now demonstrate the following proposition.

Proposition: Given any real interval I of length J, the subdivision in M intervals I 1 , ..., I M of respective length J 1 , ..., J M that minimizes the quantity J 3 1 + ... + J 3 M is the uniform subdivision, such that J 1 = ... = J M .

Demonstration (reduction ad absurdum):

Let us assume the subdivision that minimizes the quantity S = J 3 1 + ... + J 3 M is not the uniform subdivision. Let (I 1 , I 2 , ..., I M ) of respective length (J 1 , J 2 , ..., J M ) be this subdivision; it thus provides a minimal S. Two integers j and k exist such that J j = J k . The starting assumption is then false and it is demonstrated that the subdivision that minimizes the quantity S = J 3 1 + ... + J 3 M is the uniform distribution.