Ayrat Galisultanov
email: ayrat.galisultanov@cea.fr

Yann Perrin

Hatem Samaali

Hervé Fanet

Philippe Basset

Gaël Pillonnet

Contactless four-terminal MEMS Variable Capacitor for Capacitive Adiabatic Logic

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Introduction

Despite the nanoscale size of the modern transistors, the dissipation per logic operation in digital circuits is of order of 10's aJ [START_REF] Nikonov | Overview of beyond-CMOS devices and a uniform methodology for their benchmarking[END_REF]. It is four orders of magnitude higher than the theoretical limit introduced by Landauer (3 zJ at 300 K) [START_REF] Landauer | Irreversibility and heat generation in the computing process[END_REF]. In a static CMOS circuit, the energy provided by the voltage source Eprov is dissipated in each switching event. The amount of the dissipated energy Ediss equals to the signal energy 2

/2 sig DD E CV 
, where C is the capacitor at the output gate(s) and VDD is the voltage supply. This effect is represented in Figure 1a for the CMOS buffer. The ramping time T here is much greater than the RC time constant, where R is the resistance of the charging path. In order to characterize energy loss in the calculation, we can introduce a fractional energy efficiency parameter η (where 0≤η≤1) for the charging-discharging "0"→"1"→"0" loop:

1/ diss prov EE   . ( 1
)
The energy efficiency of the static CMOS circuit is zero, as all provided energy is dissipated to heat. However, there is no fundamental limitation to dissipate less than signal energy Esig. Adiabatic (smooth) switching between logic states is the basis for many approaches to energy recovery [START_REF] Frank | Approaching the physical limits of computing[END_REF]. In other hand, it leads to a decrease in the operating frequency by smoothing logic state transition. As presented in Figure 1b, this approach allow us to recover the signal energy and suppress dynamic dissipation 2 DD CV . On CMOS-based irreversible adiabatic logic, the dissipation per logic operation decreases by a factor of ten as shown in [START_REF] Houri | Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications[END_REF]. Further improvement is limited by an inherent trade-off between the dynamic and leakage losses caused by the internal properties of the FET transistor, i.e. the subthreshold slope [START_REF] Teichmann | Adiabatic logic: future trend and system level perspective[END_REF]. To suppress this inherent trade-off, electromechanical relays have been introduced in the literature [START_REF] Spencer | Demonstration of integrated micro-electromechanical relay circuits for VLSI applications[END_REF]. As they are based on metal-metal contact instead of a semiconductor junction, the leakage becomes almost negligible except in the case of nm-scale electrostatic gap [START_REF] Houri | Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications[END_REF]. Unfortunately, the main bottleneck of the relay-based adiabatic logic is the mechanical reliability and performance limit of the scaled switches, due to adhesion force of contact interface [START_REF] Pawashe | Scaling limits of electrostatic nanorelays[END_REF]. To overcome this limitation, we recently proposed a new logic family called Capacitive Adiabatic Logic (CAL) [START_REF] Pillonnet | Adiabatic capacitive logic: a paradigm for low-power logic[END_REF][START_REF] Galisultanov | Capacitive-based adiabatic logic[END_REF]. Due to smooth switching process in adiabatic logic, the resistive elements (transistors, relays) in a voltage divider circuit can be replaced by capacitive ones.

Let us consider four-terminal voltage-controlled capacitance CDS(VG). In this paper, we keep the FET transistor notations, i.e. the input control voltage is applied between the gate (G) and the ground (GND). These two terminals are isolated from the drain (D) and source (S) terminals, which form an output with a capacitance CDS. There are two possible behaviors of capacitance as a function of the input voltage. The curve CDS(VG) can have a positive or negative slope, as presented in Figure 2a. The former case is called positive variable capacitance (PVC) and the latter, negative variable capacitance (NVC). PVC and NVC voltage-controlled capacitors could play the same role in CAL as NMOS and PMOS in FET-based logic, respectively.

Based on these two elements, we can easily construct a CAL inverter, which is shown in Figure 1b. All other basic logic gates are presented and discussed in [START_REF] Pillonnet | Adiabatic capacitive logic: a paradigm for low-power logic[END_REF][START_REF] Galisultanov | Capacitive-based adiabatic logic[END_REF]. The output voltage is defined by the capacitance ratio and the power supply voltage VPC(t) such that:

() ( ) ( ) ( ) ( ) NVC IN OUT PC PVC IN NVC IN CV V t V t C V C V   . ( 2
V PC /V DD E sig E diss E prov E/(CV 2 DD /2) t/T
Two cases emerge, which are: when the input voltage is lower than the low logic level VIN<VL, the proper CL, CH, and VPC(t) selection can guarantee that the output voltage is higher than the high logic level VOUT >VH; when the input voltage is higher than the high logic level VIN>VH, the proper CL, CH, and VPC(t) selection can guarantee that the output voltage is lower than the low logic level VOUT <VL.

The basic device of CAL consists of two electrically isolated and mechanically coupled capacitors. The gap-closing MEMS variable capacitor could be a good candidate for this purpose as it offers large capacitance variation if the actuation voltage is higher than pull-in voltage [START_REF] Rebeiz | RF MEMS: theory, design, and technology[END_REF]. However, a mechanical contact is required in order to have a high capacitance variation. Consequently, this solution suffers from high non-adiabatic loss, which is independent of the operating frequency and cannot be suppressed by the ramping time increasing [START_REF] Galisultanov | Capacitive Adiabatic Logic based on gap-closing MEMS devices, Power And Timing Modeling[END_REF]. On the contrary, the comb-drive MEMS variable capacitor avoids electrical and mechanical contacts [START_REF] Perrin | Contactless capacitive adiabatic logic[END_REF]. CMOS-based adiabatic logic circuits basically operate with two types of architecture: Bennett clocking, called also retractable, and four-phase quasi-adiabatic pipeline [START_REF] Fanet | Ultra Low Power Electronics and Adiabatic Solutions[END_REF]. The power supplies, called power clocks (PC's), are quite different for these two architectures. The common thing is that these two types of power supply can provide and recover energy, i.e. realize charge recovery. In this work, we use both type of power clocks. Retractable logic can be seen as asymptotically reversible logic, but it requires N different PC's for a N-deep logic chain. Additionally, retractable PC is more slow, as during byte transfer through a chain of inverters (c.f. Figure 3a), the chain is blocked for other information, as presented in figure 3b. On the contrary, quasi-adiabatic pipeline PC requires only four different PC's with a π/2 phase shift and can change input each 4T (cf. Figure 3c). PC's synchronize the speed of transfer and processing of information. The energy losses in the reversible PC's are out of the scope of this paper, but can be found in [START_REF] Hänninen | Design and fabrication of a microprocessor using adiabatic CMOS and Bennett clocking[END_REF][START_REF] Vs Bhaaskaran | Energy recovery performance of quasi-adiabatic circuits using lower technology nodes[END_REF][START_REF] Jeanniot | Investigation of the power-clock network impact on adiabatic logic[END_REF][START_REF] Maksimovic | Clocked CMOS adiabatic logic with integrated single-phase power-clock supply[END_REF]. The design of the MEMS variable capacitor must be optimized for energy efficient charging and discharging processes. On the other hand, a logic gate based on this element must be capable to differentiate "0" and "1" logic states. Furthermore, as shown in Figure 2b, the logic gate must be able to receive the logic state from the previous gate, process it and transmit the result to the next gate, i.e. to be cascadable. In other words, input and output states have to be capable to plug the gates in series.

The aim of this work is to demonstrate energy recovery capability of comb-drive MEMS device and discuss its fundamental limitations. In the next section, we introduce our MEMS topology to implement four-terminal PVC and describe analytical and numerical simulation approaches.

Methods

The proposed microelectromechanical element consists of the two electrically isolated and mechanically coupled capacitors. In order to avoid any contact between the electrodes, we use contactless interdigitated comb transducers for both capacitors. This paper extends the proposal of [START_REF] Perrin | Contactless capacitive adiabatic logic[END_REF].

Design of the MEMS variable capacitors

The MEMS realization of voltage controlled capacitor CDS is based on two comb-drive transducers, as shown in Figure 4a. The proposed electromechanical element consists of the moving mass with two insulated electrodes and two fixed electrodes. The two pairs of fixed and moving electrodes form an input and an output comb-drive capacitive transducers. The input (left) transducer has an initial overlap Lin between the fixed and the moving electrodes. The output transducer (right) is symmetrical and does not have an initial overlap. An initial gap Lgap is present between the fingers of the output transducer. The input capacitor CG forms an actuator and is used for control of value of the output capacitor CDS as function of input voltage VG. The capacitance value CDS also depends on voltage across it VDS. In order to avoid self-actuating the capacitance CDS is symmetric and is not affected by VDS, when input voltage VG is low. We assume that the device is made of SOI wafer, with Si (100) structural layer having a thickness t equal to 40 μm. The buried oxide with 2 μm thickness provides insulation and rigid mechanical connection between GND and D electrodes of the moving part. The parameters of the comb actuators are shown in Figure 4a. The gap space g between comb-drive fingers is 2 um, the width of the finger w is 2 um, and the finger pitch p is 8 um. The gap space g and the width of the finger w values are established on the basis of the typical optical lithography capabilities.

The Coventor MEMS+® contactless comb-drive model of variable capacitance is presented in Figure 5. The left comb-drive actuator corresponds to the input, and the right comb-drive actuator forms the output. Input and output transducers form input CG and output CDS capacitances, respectively. The moving mass is suspended by four identical springs.

MEMS+® results

The mechanical parameters extracted from MEMS+® simulations are presented in Table 1. The resonant frequency of the device is around 1.2 kHz. The received displacement and the capacitance CV curves are shown in Figure 6. The initial overlap of input transducer Lin = 15 um and the initial gap between the fingers of the output transducer Lgap is 1 um. Lin and Lgap values are selected in order to have initial capacitance ratio between the input and the output capacitances of about 1.4. Due to different number of input Nin and output Nout fingers, this ratio decreases during actuation and reaches unity when VG ≈ 30 V. This variation allows us to define low and high states.

In this design, low and high states can be distinguished by the moving mass displacement x as compared with the the initial gap Lgap. If the input voltage VG is lower than the threshold input voltage VTH = 10 V, as represented in Figure 6, there is no overlap in the output transducer (-Lgap ≤ x ≤ Lgap) and, consequently, the voltage VDS does not affect the position nor the capacitance ratio, as the output combs are symmetrical (c.f. Figure 4a). For VG higher than the threshold input voltage VTH, an overlap appears in the left part of the output (x < -Lgap.), as shown in Figure 4b. In that case, an increase of VDS moves the mass to the left, and changes the capacitance ratio in the voltage divider circuit.

Analytical compact model

This electromechanical system has two electrical ports and one mechanical port. The developed model includes both electrical and mechanical parts of the system. The electrical part consists of four electrical terminals described in Figure 4 (G, GND, D, S). The mechanical part is a simple massspring-damper system and can be described by the following equation of motion: mẍ=-bẋ-kx+FeG+FeDS, (3) where input FeG and output FeDS electrostatic attractive forces are calculated from:

2 10 / , if 0, if G in in eG in V N t g x L F xL          , ( 4
)
2 20 2 20 / , if 0, if / , if DS out gap eDS gap DS out gap V N t g x L F x L V N t g x L               , ( 5
)
where 1 = 1.18 and 2 = 1.09 are the fitting parameters extracted from MEMS+® results, and ε0 = 8.854•10 -12 F/m is the vacuum permittivity. According to Equation [START_REF] Jones | Electromechanics and MEMS[END_REF], the charging and discharging current through the MEMS variable capacitor is a sum of two components. The first one is the familiar capacitive current. The second one is the motional current, which describes the transfer of energy from the electrical to the mechanical domain and vice versa.

( ) ( ) ( ) ( ) dV t dC x dx i t C x V dt dx dt  (6)
The input CG and output CDS capacitances are calculated from:

10 2 ( ) / , if , if Gp in in in G Gp in C N t L x g x L C C x L            , ( 7
)
20 20 2 ( ) / , if , if 2
C N t L x g x L C C x L C N t x L g x L                   . ( 8
)
The input CGp and output CDSp parasitic capacitances are extracted from MEMS+® simulations and equal 0.12 and 0.56 pF, respectively. The CG definition ( 7) is not entirely accurate in the region without overlap (x≥Lin). However, this displacement range is out of normal operation regime. Consequently, this definition does not affect the accuracy of the model.

We use a Verilog-A hardware description language to realize this analytical compact model of MEMS device. The simulated CV and mechanical characteristics obtained from MEMS+ are used to fit a Verilog-A analytical compact model. The comparison between Verilog-A compact model and MEMS+® simulations is presented in Figure 6. This approach allows us to include the MEMS device compact model in the electrical simulator and speed-up the transient simulation of cascaded gates.

Results

In an electromechanical system such as CAL, the total dissipation is the sum of the losses in the electrical and mechanical domains [START_REF] Jones | Electromechanics and MEMS[END_REF].The smooth transition needed in any adiabatic logic family reduces the operating frequency. To suppress the power dissipation, the ramping time T should be more than both the electrical RC and mechanical relaxation time Q/(fres) constants.

Energy analysis in the four-terminal device

In order to study the dynamical behavior of the four-terminal variable capacitor, we performed transient electromechanical simulation using the aforementioned compact model of the circuit depicted in Figure 7a. Only the case of high state displacement (x < -Lgap) is discussed. During the simulation, all energy components are calculated and the conservation of energy is checked. The energy components in this electromechanical system are:  Energy delivered by N th power clock (energy source) where we assume that the resistance R is equal for all charging paths, v is velocity of the moving mass, VPCN and iN are the output voltage and current of the N th PC, respectively.

0 0 ( ) ( ) NN t EL PC N E V t i t dt    Electrostatic energy stored in the input capacitance CG (recoverable) 2 1 2 G C G G E C V   Electrostatic energy stored in output capacitance CDS (recoverable)
For this simulation and model verification, we selected PC's with a ramping time T = 10 ms higher than that of the mechanical relaxation time τM=Q/(fres) = 7.58 ms and with VPC1max = VPC2max = 20 V > VTH = 10 V. The maximum PC voltage VPC1max is selected higher than the input threshold voltage VTH in order to create overlap in the output and to induce the significant displacement of the moving mass.

The simulation results during charging and discharging process are presented in Figure 7b. We use four-phase PC here. According to Equation 6, a part of the electrical energy is converted into mechanical energy during the charging process of CG and CDS. During the discharge phase, most of the electrical and the mechanical energy stored in the system are recovered in the PC's. The difference between provided and recovered energy is determined by damping and resistive losses. However, mechanical loss dominates here, as the mechanical time constant is six orders of magnitudes higher than the electrical one (the mechanical relaxation time equals τM = 7.58 ms, the RC time constant equals τ = RCDS1 ns). This means that mechanical motion is adiabatic in the electrical domain.

The fractional energy efficiency η, i.e. ratio between the recycled energy and the energy provided by PC's, is 99.8 %. The maximal energy provided by PC's is 685 pJ. The irreversible losses are caused by the damping (1.56 pJ) and resistive (0.3 fJ) losses. The energy saving law is satisfied. The main part of mechanical loss dissipation arises from the loss of the electromechanical coupling in the output transducer during the discharging phase of the output capacitance CDS. In the second graph of Figure 7b, it can be observed as free vibration from t ≥ 3.8T. The simulation results with the same parameters, but for Bennett clocking PC, are shown in Figure 7c. The fractional energy efficiency η is 99.96 %. The maximal energy provided by PC's is the same as in the case of four-phase PC's (685 pJ). The irreversible losses are caused by the damping (0.3 pJ) and resistive (0.3 fJ) losses. Retractable PC's are more energy efficient here, since there is no loss of the electromechanical coupling in the output transducer during operation. For both cases the maximal electrostatic energy is 3.8 times higher than the maximal mechanical spring energy. In the ideal electromechanical actuator these energies should be equal [START_REF] Jones | Electromechanics and MEMS[END_REF], but in our realistic device model, the electrostatic energy dominates due to presence of parasitic capacitances.

In Figure 8, we present the effect of ramping time T on the dissipated energy Ediss during one cycle for device actuated with four phase and Bennett clocking PC's. All other parameters are the same as in the previous calculations. The increasing ramping time decreases the dissipation for retractable PC's. This demonstrates the absence of any non-adiabatic losses in Bennett clocking PC's for the proposed design. However, for four-phase PC's we observe presence of the non-adiabatic losses, i.e. the losses, which do not depend on the ramping time T and cannot be recovered by PC's. These losses are caused by the loss of the electromechanical coupling in the output transducer during the discharging phase of the output capacitance CDS. The coupling disappears when x = -Lgap, and, consequently, the system losses the following mechanical energy stored at this moment:

2 /2 NA gap E kL  . ( 9
)
Lgap in current MEMS-based CAL device is analog to VT in metal-oxide-semiconductor technology.

The energy dissipated during one cycle tends to this value when the ramping time T tends to infinity. For our device, the non-adiabatic part of dissipated energy equals 1.2 pJ.

Cascadability

The cascadability of the proposed four-terminal device is demonstrated using an array of buffer elements. In CAL we can use the input capacitance of the next gate as an element of voltage divider circuit, as presented in Figure 9a. The additional complementary NVC is not needed, unlike to CMOS circuits. The buffer chain circuit is presented in Figure 9b. The output voltage is measured across constant capacitance C0 = 0.86 pF, which mimics the input capacitance of the next gate. The threshold voltage VTH for simulated design is 10 V. The input voltage amplitude is 8 V and 12 V for low and high input levels, respectively. The binary input logic word "1010" is transferred through the buffer chain, as demonstrated in Figure 9c for quasi-adiabatic pipeline PC's. The logic state in further gates is coded by the moving mass displacement x, induced by the input voltage. If the amplitude of displacement is less than Lgap value, there is no overlap and, consequently, the output capacitance CDS is not affected by the voltage VDS around it (c.f. the second graph of Figure 9c). Due to the output symmetry wrong "1" is avoided. It causes low signal level in the next gate, i.e. VGN is below VTH and is considered by (N+1) th gate as a low state. On the contrary, if the input is high (VGN > VTH ), the amplitude of displacement │x│ is higher than Lgap value. Consequently, the rise of the output voltage is able to trigger a displacement of the moving mass, transferring the high input signal to the (N+1) th gate of the buffer chain. The logic state is maintaining during holding phase (input decreasing) thanks Four-phase PC's to the output electrostatic force FeDS of the next gate. This inherent memory effect simplifies CAL circuit. The effect is shown in the fourth graph of Figure 9b. The energy efficiency parameter η equals 99.1 % for the selected PC's voltage level when devices operate at 25 Hz. The "0" and "1" states can be distinguished, even if the voltage difference between them is a few volts. In the third graph of Figure 9c we can observe the absence of voltage degradation during signal transfer throw the buffer chain due to power clock, which provides energy in the same level along the chain. For this design the length of the buffer chain is not limited. The system demonstrates cascadability for the maximal PC amplitude VPCmax ranging from 22 to 25 V. Voltage, V

V TH =10 V C G3 C DS2 V G2 V PC4 V OUT V I N x, m t/T x 3 x 2
of the first buffer VOUT (first graph), CDS2 and CG3 (second graph), VG2 and VG3 (third graph), displacement of the second x2 and the third x3 MEMS elements over time for retractable PC's. We used the following parameters: T = 10 ms, R = 1 kΩ, VPCmax = 24 V, C0 = 0.86 pF.

The non-recoverable energy is mainly dissipated by mechanical damping during the changing of state from high to low (i. e. byte erasing) and can be removed by using retractable PC's, as presented in Figure 9d. The signal is transferred due to controlled capacitance variation, as for former case with four-phase PC's, however retractable PC's form an asymptotically reversible logic. Due to this the nonadiabatic loss ( 9) is suppressed as clearly seen in the fourth graph of the Figure 9c. The energy efficiency parameter η increases from 99.1% to 99.97 %.

Scalability trend

For this mm-scale device the energy dissipated during one cycle is of the order of one pJ per operation. This is still far from the energy dissipated by a nm-scale FET transistor, which is of the order of 10's aJ. However, constant field scaling scenario is available, as there is no adhesion force limitation, unlike to nanorelay [START_REF] Pawashe | Scaling limits of electrostatic nanorelays[END_REF]. The energy dissipation for the contactless design decreases proportionally to the cube of the size. As presented in Figure 10, the "optimistic" scalability trend is limited by the two factors. First factor is the Landauer limit for irreversible logic ln 2 B kT (3zJ@300K) [START_REF] Landauer | Irreversibility and heat generation in the computing process[END_REF]. The second is the tunnelling current, which cannot be neglected for nm-scale electrostatic gap [START_REF] Binnig | Tunneling through a controllable vacuum gap[END_REF]. For the scaled design, the level of dissipation in the electromechanical MEMS device can be decreased up to 100's of zJ. It should be noted that the total dissipated energy is affected by the energy losses within the reversible power supplies, which are not taken into account here.

Discussion

As we mentioned in the introduction, the energy efficiency η of the static CMOS circuit is zero, as all provided energy is dissipated to heat [START_REF] Frank | Approaching the physical limits of computing[END_REF][START_REF] Houri | Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications[END_REF]. The part of the provided energy Eprov can be reused due to smooth changing between logic states and special type of power supply that can recover the signal energy Esig. However, the main drawback of this approach is the decrease in the operating frequency.

The second problem is the energy recovery in a circuit operating with four-phase PC's. As a memory is needed in holding phase, the provided energy is not fully recoverable. The energy of the signal is divided into two parts. First part of the energy is recoverable and equals (Esig -Edist), the second part being the distinguish energy Edist, which separates low and high logical states. In presented contactless electromechanical device it equals 2 /2 gap kL . The distinguish energy also exists in CMOS and equals 2 /2 T CV . This energy cannot be recovered in irreversible logic and causes non-adiabatic energy loss. In other word, the maximal energy efficiency of irreversible quasi-adiabatic logic is limited by ratio:

1 / ,

dist prov E E for T      . ( 10
)
The distinguish energy Edist is limited below by the Landauer limit ln 2

B kT [START_REF] Landauer | Irreversibility and heat generation in the computing process[END_REF]. Additionally, Edist must be significantly higher than kBT to be robust in thermal environment in order to prevent spontaneous change of state. The noise margin needs to be at least higher than 100 kBT [START_REF] Kish | Energy requirement of control: Comments on Szilard's engine and Maxwell's demon[END_REF], this level is shown in Figure 10. Once again, we would like to note that Esig is not the energy which separates logic states. This principle demonstrates the limits of irreversible adiabatic logic and the interest to reversible calculation. We will build reversible MEMS CAL gates in the near future.

Conclusion

A contactless design of a variable MEMS capacitor for CAL has been successfully developed, tested, and verified. Our design avoids leakage losses, in contrast to CMOS-based adiabatic logic, and resolves the contact reliability problem of a nanorelay solution. An analytical compact model of the electrostatically-actuated four-terminal variable capacitor has been developed. The analysis of loss mechanisms have been done for a single device and for a cascade of buffer chain. The binary input logic word "1010" is successfully transferred through chain of buffers. The energy efficiency η equals 99.1 % when devices operate at 25 Hz with quasi-adiabatic pipeline PC's. For this type of architecture the non-adiabatic dissipation has been demonstrated for the presented MEMS device. This energy can be recovered by using retractable PC's.

For this mm-scale device the energy dissipated during one cycle is of the order of one pJ per operation for four-phase PC's. This is still far from the energy dissipated by a nm-scale FET transistor, which is of the order of 10's aJ. However, scalability has been studied and the energy dissipation for the contactless design decreases proportionally to the cube of the lithography resolution until nanoscale parasitic effects. MEMS-based CAL could be of interest as energy efficient alternatives to CMOS transistors for low-power adiabatic circuit applications.

Figure 1 .

 1 Figure 1. a) Static CMOS logic (RC << T). Normalized input voltage VIN/VDD (first graph), normalized provided Eprov, dissipated Ediss, and signal energy Esig (second graph). b) Adiabatic CMOS logic. Normalized power supply voltage VPC/VDD (first graph), normalized provided Eprov, dissipated Ediss, and signal energy Esig (second graph).

)

Figure 2 .

 2 Figure 2. a) Capacitance-voltage (CV) characteristics and symbols for positive variable (PVC, dotted line) and negative variable (NVC, solid line) capacitors. The low and high voltage levels are denoted as VL and VH, respectively. The same notation (CL and CH) is used for capacitance levels. b) Electrical schematics of simple CAL inverter circuit and cascadability conditions.

Figure 3 .

 3 Figure 3. a) Cascade of two inverters. b) Data and energy transfer in Bennett (retractable) power clock. c) Data and energy transfer in four-phase quasi-adiabatic pipeline power clock.

Figure 4 .

 4 Figure 4. Two states of MEMS element as function of the moving mass displacement x. a) Low state: -Lgap ≤ x ≤ Lgap. Parameters of the comb-drive actuator are presented in the insert. b) High state: x < -Lgap.

Figure 5 .

 5 Figure 5. Top view of the contactless four-terminal MEMS element. Length of the structure is 1.2 mm, width is 1 mm, number of input fingers Nin is 110, number of output fingers Nout is 220.

Figure 6 .

 6 Figure 6. a) Moving mass displacement as a function of the input voltage VG. b) Input CG and output CDS capacitances as a function of the input voltage VG. Verilog-A model and MEMS+® simulation results are drawn as solid and dashed lines, respectively.



  Energy dissipated in the N th resistor (irreversible loss)

Figure 7 .

 7 Figure 7. a) Test circuit. b-c) Evolution of voltages applied to the four-terminal MEMS element (first graph), moving mass displacement (second graph), electrical energy provided by PC's (third graph), electrical energy stored in capacitances and mechanical spring energy (fourth graph), and dissipated energy (fifth graph) over time for test circuit operated with b) four-phase and c) Bennett clocking PC's. We used the following parameters: T = 10 ms, R = 1 kΩ, VPCmax = 20 V.

Figure 8 .

 8 Figure 8. Simulated dissipated energy Ediss according to inversed ramping time T -1 for device operated with four-phase and Bennett clocking PC's.

Figure 9 .

 9 Figure 9. a) Electrical circuit simplification due to using the input capacitance of the next gate as an element of voltage divider circuit. b) Electrical diagram of the cascade of four buffers. c) Spice simulation results: input voltage VIN, VPC1, output of the first buffer VOUT (first graph), CDS2 and CG3 (second graph), VG2 and VG3 (third graph), displacement of the first x1 and the fourth x4 MEMS elements over time for four-phase PC's. d) Spice simulation results: input voltage VIN, VPC1, output

Figure 10 .

 10 Figure 10. Simulated minimal dissipated energy trend Ediss for the ramping time tends to infinity according to lithography resolution r for device operated with four-phase PC's. Here we assume that Lgap = r/2.

Table 1 .

 1 Extracted from MEMS+ simulation mechanical characteristics of MEMS element.

	Parameter	Value
	Mass m, kg	4.41•10 -8
	Spring constant k, N/m	2.39
	Resonant frequency fres, Hz	1173
	Damping coefficient b, kg/s	1.16•10 -5
	Quality factor, Q	28


Yann Perrin

Ayrat Galisultanov

Hatem Samaali

Philippe Basset

Hervé Fanet

Gaël Pillonnet

Contactless Capacitive Adiabatic Logic

Keywords: Low-power electronics, MEMS, Adiabatic architectures, Capacitive logic gates, Energy efficiency

come

INTRODUCTION

Adiabatic logic is a promising approach explored in order to reduce the energy of computation. [START_REF] Koller | Adiabatic switching, low energy computing, and the physics of storing and erasing information[END_REF][START_REF] Athas | Low-power digital systems based on adiabatic-switching principles[END_REF][START_REF] Snider | Minimum energy for computation, theory vs. experiment[END_REF] The principle of adiabatic logic is to limit the dynamical losses by using smooth transitions between the logic states. [START_REF] Paul | Optimal charging of capacitors[END_REF] This generally implies to work at lower operating frequencies. However, adiabatic operation of CMOS circuits exacerbates the leakage loss intrinsic to field-effect transistors (FET). [START_REF] Chandrakasan | Minimizing power consumption in digital cmos circuits[END_REF] In addition, the non-linearity of FETs leads to an unavoidable energy loss. [START_REF] Athas | Low-power digital systems based on adiabatic-switching principles[END_REF] In order to avoid leakage loss, circuits based on MEMS nanorelays have been investigated. [START_REF] Houri | Comparing CMOS-Based and NEMS-Based Adiabatic Logic Circuits[END_REF][START_REF] Ayala | Ultra-low-energy adiabatic dynamic logic circuits using nanoelectromechanical switches[END_REF] Although nanorelays are a promising approach for implementing adiabatic logic, the electrical contact at the nanometer scale raises serious reliability issues. [START_REF] Pawashe | Scaling limits of electrostatic nanorelays[END_REF] V dd In earlier works, we presented a disruptive approach, where combinational functions are performed with variable capacitors: [START_REF] Pillonnet | Adiabatic capacitive logic: a paradigm for low-power logic[END_REF][START_REF] Galisultanov | Capacitive-based adiabatic logic[END_REF] combinational CMOS gates, such as the inverter depicted in Figure 1, can also be seen as a circuit with voltage-controlled variable resistors. The output voltage is then determined by the resistances values. The logic function also might be performed by variable capacitors (see Fig. 1). Capacitive logic should avoid the dissipation caused by leakage currents. When driven adiabatically (Capacitive Adiabatic Logic, CAL) the energy dissipated by the gate becomes almost negligible. A variable capacitor can simply be obtained by coating the plates of a nanorelay with a dielectric layer. However, the hysteretic behaviour of this system causes an unavoidable dissipation. [START_REF] Galisultanov | Capacitive-based adiabatic logic[END_REF] In this study, we present a new approach which does not involve mechanical contact, and that could be a good candidate for implementing adiabatic dynamic logic (ADL) architectures. [START_REF] Dickinson | Adiabatic dynamic logic[END_REF]

V out V in C 1 C 2 V dd V out V in V dd V in R 1 R 2 V out

VOLTAGE CONTROLLED CAPACITANCE

The elementary device for capacitive adiabatic logic (CAL) consists of a two-terminals variable capacitor that can be controlled by an external voltage. This can be achieved in a solid state device (eg. varicap diode), or electromechanically by using for instance comb-drive actuators. Comb-drive actuator [START_REF] Tang | Laterally driven polysilicon resonant microstructures[END_REF] is probably the most popular device employed for MEMS. It allows to create significant electrostatic forces, while involving extremely low electric currents. It consists of two insulated parts in electrostatic influence (See Figure 2a). The electrostatic coupling is enhanced by the presence of interdigitated fingers, overlapped by a length denoted x. When the fringing electric field is ignored, the capacitance of this comb-drive writes:

two-terminals comb-drive actuator

ε 0 t w g x V a) b) V x F F C
C(x) =        2n 0 tx g if x ≥ 0 0 otherwise. (1)
where 0 , t, n and g are respectively the vacuum permittivity, the thickness of the device, the number of fingers and the gap between them. C(x) increases with the displacement x. As a consequence, when a voltage V is applied between the two combs, an electrostatic attractive force F arises. Its magnitude can be calculated by differentiating the electrostatic energy with respect to x:

F (x, V ) =        ∂ ∂x E = 1 2 ∂C ∂x V 2 = nt g 0 V 2 if x ≥ 0 0 otherwise. (2)
If one (or both) combs are able to move along the x direction, F (x, V ) leads to a mechanical displacement which increases C(x). Therefore, comb-drive actuator is a variable capacitor.

Four-terminals variable capacitor

The two-terminals capacitor described above cannot provide the external control of the capacitance, which is required to perform logic functions (see Fig. 1). To this purpose, we must add another pair of electrodes connected mechanically to the first one. On the device depicted in Figure 3a, the left electrodes correspond to the input, and the right electrodes to the output. By analogy with FET transistors, input and output capacitances (resp. voltages) are denoted C G (resp. V G , gate) and C DS (resp. V DS , drain-source). The output comb-drive is symmetric ; the interest of this design is that the system becomes insensitive to the effect of V DS (when V G =0). This property is verified even when considering fringing fields. In our design, input and output comb-drives have initial overlaps denoted x 0 and x 0 when x = 0. The capacitances C G (x) and C DS then write:

V G V DS x k R C G V RG V G R C DS V RDS V DS a) b) i i
C G = 2n 0 t g (x + x 0 )H(x + x 0 ) C DS = 2n 0 t g [(x + x 0 )H(x + x 0 ) + (x 0 -x)H(x 0 -x)] (3)
Where H(x) corresponds to the Heaviside step function, which equals 0 if x < 0 or 1 if x ≥ 0. n depicts the number of fingers in the output comb-drive. In order to enhance the variation of C DS capacitance, the numbers of fingers is usually greater in the output (n > n).

Considering damping and inertia, the mechanical dynamic equation of the system writes:

d 2 x dt 2 + ω 0 Q dx dt + ω 2 0 x + F (x, V G , V DS ) m = 0 ( 4
)
where m is the mass of the rotor, ω 0 = k m its angular frequency, and Q the quality factor of the oscillator (this includes the mechanical damping). F (x, V G , V DS ) corresponds to the total electrostatic force resulting from input and output comb-drives. Equations ( 2),( 3) and (4) allow the calculation of the output capacitance C DS for a set of applied voltages (V G , V DS ). For the calculations presented in this paper, the parameters are set to the following values:

• Thickness: t=40 µm

• Gap: g=2 µm Numbers of fingers: n=100, n =200 • Initial overlaps (for x=0): x 0 =5 µm, x 0 =-2 µm • Spring stiffness: k=2 N.m -1 • Resonant frequency ω 0 2π =10 kHz • Quality factor Q = 10
• Vacuum permittivity:

0 = 8.85 × 10 -12 F.m -1
This high thickness is required in order to obtain significant capacitances values, making the system insensitive to parasitic capacitances. The gap is set by the precision of the fabrication process. The number of fingers n and n is must be sufficiently high in order to permit actuation voltages in the range of 10 volts. These features are compatible with realistic device which are commonly used, eg. as gyroscopes. [START_REF] Yazdi | Micromachined inertial sensors[END_REF] Figure 4 clearly show that V G provides a fine tuning of C DS for values greater than 10 V. This offset is due to the negative initial overlap

x 0 =-2 µm which has been designed on the output comb-drive. This choice will be discussed further. V G (V)

x (µm) In order to simulate accurately the system and the dissipation, we also must consider the electrical aspects. The electrical diagram consists of simple RC circuits, in which the electric current i expresses:

i(t) = 1 R (V G (t) - q(t) C(t) ) ( 5
)
where C refers to the capacitance C G or C DS , and q to the charge stored inside. q is calculated by integrating the current:

q(t) = t 0 i(t)dt (6)
Equations ( 5) and ( 6) fully describe the electrical evolution of the system. The link between electrical and mechanical equations originates from the variation of the capacitances and the electrostatic forces. In the following paragraph, the electromechanical model is solved numerically for a more complex system.

CASCADED BUFFERS

We now consider a circuit composed of four cascaded CAL buffers. The equivalent electric diagram is depicted in Figure 5. While keeping the numerical parameters detailed above, we study the dynamical response of the circuit to an input logic sequence 0 1 0 1. According to adiabatic dynamic logic (ADL) principles, [START_REF] Dickinson | Adiabatic dynamic logic[END_REF] the four power clocks signals V P C1 to V P C4 have a trapezoidal shape (see Fig. 6a). In addition, a phase-shift about π 2 is introduced between each clock. Different approaches for generating such signals have already been investigated, such as resonant circuits or switched capacitors. [START_REF] Jeanniot | Investigation of the power-clock network impact on adiabatic logic[END_REF][START_REF] Raghav | Investigation of stepwise charging circuits for power-clock generation in adiabatic logic[END_REF] R Figure 6b depicts the dynamical response of the circuit for a specific input. The output signal clearly shows two different logic states, respectively at 2 V ("0" state) an 15 V ("1" state). The logic sequence in the output corresponds to the input, which is the expected behaviour for cascaded buffers. The output is delayed by one time period ; this feature is intrinsic to ADL operation. For the proper functioning of the gate, the operating frequency must be lower than the mechanical resonant frequency (10 kHz). In addition, the parasitic oscillations that occur after a "1" state must be damped before the next clock pulse. These constrains limit the operating frequency up to approximately 1 kHz. t (ms) t (ms) We verified that the systems works properly for an operating voltage V dd > 20 V. Under this value, "1" states are converted into "0" states. This is due to the negative overlap x 0 =-2 µm, which requires a motion of at least 2 µm in order to transmit "1" states. One could conclude that removing this overlap might allow to work at lower voltages. However, the voltage that corresponds to "0" state (2 V) triggers a motion in the following comb-drive. This motion must not trigger a "1" state in the circuit. Therefore, the negative overlap is required order to secure the system against fluctuations associated to "0" states.

C G1 V PC1 DS1 R C G2 V PC2 C DS2 R C G3 V PC3 C DS3 R C G4 V PC4 C DS4 V IN V OUT R C Load
V PC1 (V) V PC2 (V) V PC3 (V) V PC4 (V)
V IN (V) V OUT (V) x 4 (µm) E Loss (pJ) E Joule E vis 1 0 1 0 1 1 0 1 0 a) b)
We finally address the question of the energy dissipation in the circuit. Two sources of dissipation are considered: the Joule dissipation E Joule in the resistances (R is set to 2 MΩ), and the damping loss E vis in the moving parts (Q = 10). Both dissipation terms appears in the last graph of Figure 6b over the time. Most of the dissipation occurs when a "1" state is transmitted, as it is associated to large displacements and high capacitances variations. With the conditions of Figure 6, the energy per operation E op is about 7.5 pJ. We point out that this dissipation is only a small fraction (5%) of the energy involved in the process. During the rise of the clock pulse, the power clock provides energy which is stored electrically in the capacitances and mechanically in the springs. During the decrease of the pulse, this energy is substantially recovered by the power clock. In the simulation in Figure 6, the ratio of recovered energy is about 95%. This ratio assumes a perfect (lossless) power clock.

In our system, E op is far beyond the state of the art of conventional nanoscale CMOS circuits (in the order of the fJ). However, this dissipation should vanish for extremely low operating frequencies, i.e. when the system is driven adiabatically. Furthermore, the energy per operation dramatically decrease with the size of the device (E op scales in g -3 ). Therefore, passing from a microscale device to nanoscale might lead to a reduction of E op by six orders of magnitude (in the order of aJ).

CONCLUSION

This paper introduces an original approach for implementing adiabatic dynamic logic with contactless MEMS devices. Our design avoids leakage losses, which are the biggest limitation for adiabatic circuits based on fieldeffect transistors. The elementary device presented here is based on comb-drive actuators which allows the realisation of a voltage-controlled variable capacitor. Based on an electromechanical model, we show how these components can be arranged in order to perform a basic combinational function (buffer pipeline). Further studies will be dedicated to other functions (inverter, AND, OR...) that can be performed with capacitive logic.

Figure 1 .

 1 Figure 1. A conventional CMOS inverter (left) can also be seen as a bridge of variable resistors (middle). By analogy, a bridge of variable capacitors should also perform the logic function (right).

Figure 2 .

 2 Figure 2. a) Image depicting a typical comb-drive actuator, composed of two conducting parts with interdigitated fingers. An electrostatic attractive force arises when a voltage difference is applied to the combs. b) Detailed schematics of the fingers, showing the notations employed in this paper. Only the red area is taken into account for the calculation of the capacitance.

Figure 3 .

 3 Figure 3. a) Sketch of the four-terminal variable capacitor studied in this paper. The blue elements are anchored to the substrate and are electrically insulated. The red part is free to move along the horizontal axis. A spring with a stiffness k creates a restoring force F k = -kx. It tends to bring back the rotor to the position x = 0. The left comb-drive corresponds to the input electrodes. The right comb-drive (output) is mechanically connected to the first one, but both are electrically insulated. The green square depicts the insulating mechanical link. b) Equivalent electric diagram, showing the two electric loops coupled mechanically.

Figure 4 .

 4 Figure 4. Graphs depicting the influence of the input voltage VG on the output capacitance CDS and the position of the rotor x.

Figure 5 .

 5 Figure 5. Electrical diagram of the four cascaded buffers considered in this section. The capacitance C Load connected on CDS4 imitates the input of a following circuit.

Figure 6 .

 6 Figure 6. a) Graphs showing the four phases power clock signals employed in the simulations. The circuit is driven with an operating frequency about 632 Hz. b) Response of the circuit to an input signal carrying the logic sequence 1-0-1-0-1 (first graph). The output signal (second graph) is shifted by one time period (1.58 ms) and shows the expected logic sequence. This sequence is also visible on the position of the last comb-drive device (third graph).

Further author information: E-mail: gael.pillonnet@cea.fr