As silicon CMOS technology is approaching fundamental scaling roadblocks, alternative channel materials like Ge and III-V based devices have attracted a lot of attention and have been the subject of active research during the last 10 years. While these new materials have very promising transport properties, studies have shown that they have worse short channel performance than the Si counterparts. Hence there is a strong need to evaluate the impact of change in the channel material on the device performance in terms of the short channel effects. In this work, first some issues with conventional modeling of double gate MOSFETs are dealt with. A new analytical model of the built-in potential is proposed and shown to correct the errors due to wrong boundary conditions. The roles of quantum confinement effects, material parameters and architecture of nanoscale III-V MOSFETs on the electrostatic integrity in terms of SCEs are thoroughly examined. A modified parameter to capture the drain induced barrier lowering is used to predict the performance degradation in the post-threshold region of the MOSFETs. Impact of the source to drain tunneling on the subthreshold behavior and hence the scalability of III-V devices is also analyzed in this thesis.

Résumé

Les technologies CMOS à base de silicium approchants les limites fondamentales de la miniaturisation, de nouvelles options sont nécessaires pour continuer la feuille de route de l'industrie de semi-conducteurs. Les matériaux III-V et le germanium sont actuellement très étudiés à ces fins, pour remplacer le silicium en tant que matériau canal des transistors MOSFETs. Bien que les propriétés de transports de charges de ces matériaux soient très fortes dans les substrats massifs, les performances des composants à base de III-V présentent actuellement de fortes dégradations par rapport à ce qui pourrait être attendus. En conséquence, il est nécessaire d'évaluer théoriquement l'impact du changement de matériau de canal sur les performances de ces dispositifs. Dans ce travail, les problèmes de modélisation des effets de canaux cours des composants MOSFET à base de III-V ont d'abord été étudiés. Un nouveau modèle analytique du potentiel électrique dans le canal du MOSFET est proposé et démontré afin de corriger des erreurs dues aux mauvaises conditions limites. Les rôles des effets quantiques de confinement, des paramètres des matériaux ainsi que le rôle de l'architecture des MOSFET III-V sur les effets de canaux courts sont ensuite examinés. L'impact de l'effet tunnel dans la direction source-drain est également analysé dans la dernière partie cette thèse.

At the outset I would like to thank my thesis advisors Quentin Rafhay and Georges Pananakakis, for accepting and welcoming me as a PhD student at IMEP-LAHC, and for their expert guidance. I would like to thank Gérard Ghibaudo, the director of the lab, for all his help during the three years. I express my gratitude to the the Erasmus Mundus India4EU scholarship program for providing the funding for the PhD.

I would like to thank the members of my jury: Prof. Francis Calmon for presiding over the jury; Dr. Fabien Pregaldiny and Prof. Jean Luc Autran for reviewing my thesis and providing their valuable feedback. Special thanks to Quentin for everything he has done for me in the three years I have been here. For his help in getting acclimatised to the new environment, aiding me through the beaurocratic processes, and above all his committed role as my thesis advisor. I have learnt many things from him: his tremendous zeal and methodical approach to scientific research. I thank him for his patience, for keeping his door always open for discussions despite his busy schedule. I appreciate my advisor Raphael Clerc for his guidance during the time he was at IMEP. Thanks to Georges for his help with the administrative processes, reviewing my writings and all the discussions. I was fortunate to have meetings with Frédéric Boeuf and Stéphane Monfray at STMicroelectronics, Crolles where we discussed our III-V device research. To get the industrial perspective was really useful while deciding the direction of my thesis work. I would like to thank Valérie and Annaick at IMEP management section for help in organising my travels. Many thanks to Bénédicte Flauxa from the EEATS doctoral school for her help in keeping track of the thesis defense procedures and documentation.

Over the three years I have met many interesting people, made many friends. It's these people that made my stay in Grenoble a memorable experience. Thanks to Pierre for his friendship, French lessons, tennis sessions, many discussions and excursions. Tong for being a gentle and friendly colleague at both the offices I worked from at IMEP. Ramin the new guy at the office for his friendship and his openness. Thanks to all of them for chipping in the many philospohical and socio-psychological discussions! Thanks to Isil for her friendship and help many times.

I would like to thank Raj, Subbu, Manan, Santhosh, Rakhi, Ana and many other friends for their support. Thanks to Saurav for the Satsangs. It was a nice experience to play in our Indo-French band with Manan, Koce, Antoine and Guillaume! Keep rocking guys! There are so many people I met in the Erasmus program; it was a real international experience. Special thanks to my Brazilian friends. Thanks to the many Indian restaurants in the city where I visited often. Thanks to my friends in the lab who helped in the organization of the pot de thèse. Last, but not the least, I would like to thank Isère and Bastille, for being there!! The gate stripe extends a distance W g perpendicular to the figure. L g is the gate length, T ox the gate dielectric thickness, and T w the thickness of the In-GaAs/InP quantum well . . . . . . . . . . . . . . 17

List of Figures

I d -V g characteristics of

List of Tables

State of the art in transistor industry

The transistor industry has come a long way since the invention of the point-contact transistor in 1947 by John Bardeen, William Shockley and Walter Brattain at Bell Labs through today's generation of nanometric MOSFETs in multiple flavors. This growth of the transistor industry has been accompanied by miniaturization of the devices in order to increase device density on integrated circuits. During the last four decades, the trend of scaling down of the MOSFET channel length has been following the so-called Moore's law [START_REF] Moore | Cramming more components onto integrated circuits[END_REF] that states that the transistor density on an integrated circuit doubles roughly every 18-24 months, resulting in increased functionality and performance and reduction in production costs. In the recent past we have seen technology nodes of 45 nm going into production in 2007, 32 nm in 2009, and 22 nm process for 3-D tri-gate transistors in 2011 [2]. For sustaining the Moore's Law as device dimensions continue to shrink to physical limits, technological innovations are constantly needed. Traditional MOSFET scaling meant a reduction in the physical dimensions: L g , t ox and the Source/Drain contacts, and also the supply voltage V DD and increase in the substrate doping, N a . The era of conventional scaling of device dimensions came to an end in the 1990s, primarily due to the inability of the SiO 2 gate oxide (1.2 nm for 90 nm technology [START_REF] Chau | Gate dielectric scaling for high-performance CMOS: from SiO 2 to high-k[END_REF]) to undergo further scaling and gate leakage becoming a critical issue. In the nanoscale regime, there exist tight trade-offs between the three main metrics that are used to qualify a field effect transistor's performance: on current (I on ), power consumption (P DD ), and Short-Channel Effects (SCEs). Figure 1.2 by Takagi et al. [START_REF] Takagi | Carriertransport-enhanced channel CMOS for improved power consumption and performance[END_REF] depicts the tradeoff correspondence and the physical or device parameters that affect them. For example, power-supply voltage V DD , threshold voltage V t , and the efffective oxide thickness (EOT) affect both the I on and P DD , and hence there is a trade-off between these two metrics. The physical mechanisms causing the tradeoffs are shown inside the boxes. Device speed and power are two important parameters in the semiconductor device industry. The intrinsic switching delay of a MOS transistor is dependent on the gate capacitance (C g ), the supply voltage (V DD ) and the on-current (I on ) as:

Limits of scaling

τ d = C g V DD /I on (1.1)
The power consumption in a digital circuit is a sum of three components (with reference to an inverter): dynamic power (used during charging and discharging the inverter load), subthreshold leakage power and short circtuit power [START_REF] Pop | Energy dissipation and transport in nanoscale devices[END_REF] [6]:

P = C L V 2 DD αf + I leakage V DD + P SC (1.2)
where α is activity factor, C L is load capacitance and I leakage is the subthreshold leakage current.

In the conventional scaling regime, with the introduction of each new technology node, the intrinsic delay was reduced and hence, the maximum intrinsic switiching speed 1/τ d improved with device scaling leading to higher clock speeds in the integrated circuits.

However, in recent years the microprocessor clock speed has saturated at around 4 GHz. This is ascribable to the enormous increase in power dissipation at high clock frequencies and hence the dissipated power density in modern CPUs is constrained to hover around 100 W cm -2 as shown in Figure 1.3 (taken from [START_REF] Pop | Energy dissipation and transport in nanoscale devices[END_REF]). Beyond this limit, power dissipation in a Si MOSFET has became difficult to scale down as we have entered this regime of "Power constrained scaling" [START_REF] Frank | Power-constrained CMOS scaling limits[END_REF], and hence reduction in supply voltage is needed to stop excessive heating. But, the supply voltage scaling has also slowed down because reduction in supply voltage causes degradation of the Si MOSFET performance as the drive current, I on decreases with decrease in V DD . The ITRS 2012 update [8] has projected the gate length of Si MOSFETs to be 6 nm in 2026, with device power consumption being considered to be the limiting factor instead of speed as from circuit design perspectives speed requirement can be relaxed.

Short Channel Effects

In a long channel MOSFET, the channel potential profile is a function of the gate voltage only, and it is more or less flat along the channel direction. When the gate length is reduced and becomes comparable to the depletionlayer widths of the source and drain junctions, the applied drain voltage starts to affect the channel potential and becomes 2 dimensional (sometimes assumed to be parabolic [START_REF] Young | Short-channel effect in fully depleted SOI MOSFETs[END_REF]). The potential barrier is lowered due to the proximity of the source and drain and hence it becomes difficult to properly switch off the device as more carriers can diffuse from the source to the drain even at gate voltages lower than the threshold voltage, producing subthreshold current flow in the device.

Essentially seen as a source of off-state current degradation, Short Channel Effects (SCEs) are used to quantify influence of the drain bias and the loss of gate control on the device electrostatics. • Drain Induced Barrier Lowering (DIBL): When the drain bias is increased, the source to channel potential barrier is found to reduce in a short channel device, as shown in Figure 1.5. Conventionally it is measured as the reduction in threshold voltage per unit increase of drain voltage.

DIBL = V t (V d = V DD ) -V t (V d = 0.05V ) V DD -0.05V
• Threshold Voltage Roll-Off: V t roll-off is the reduction in threshold voltage as we go from long channel device to shorter channel ones. The shorter gate lengths would cause worsened short channel effects: higher subthreshold slope, higher DIBL and increased threshold voltage roll-off, leading to increased off currents in the devices. In this work, only the DIBL and the subthreshold slope will be used as figure of merit of SCEs, as they are the main causes of leakage increase.

Long

Heterogeneous Scaling and Technology Boosters

The constant-field scaling as elucidated in [START_REF] Dennard | Design of ion-implanted MOSFETs with very small physical dimensions[END_REF], consisted of scaling the device dimensions and voltages by constant factors while moving from one technology generation to the next. In contrast to this "Happy Scaling" era of homogenous scaling (similar materials and device structures), in the early years of the last decade, the industry moved towards heterogeneous scaling where different materials and new device architectures began to be used to -1 .

-1 .

-1 .

-0 .

-0 .

-0 .

-0 .

-0 .

-0 .

-0 .

-0 .

-0 . V d = 0.9 V, and curves without symbols represent the

V d = 0 V case)
achieve the expected benefits of scaling [START_REF] Bohr | The evolution of scaling from the homogeneous era to the heterogeneous era[END_REF]. Some of the limitations of traditional scaling have been conquered using new technological breakthroughs, sometimes called as "technology boosters". Two such boosters have been the use of Strain and High-κ Metal Gate.

In the last two decades a lot of research and eventually real application of strained Si provided a major boost to the carrier mobility in Si MOSFETs, starting with the 90 nm technology node, without the need of any radical change from the existing Si process flow. When Si is epitaxially grown on relaxed Si 1-x Ge x , the lattice mismatch between Si and SiGe results in biaxial strain in Si layer. The amount of strain can be varied by changing the Ge content [START_REF] Hoyt | Strained silicon MOSFET technology[END_REF]. Uniaxial strain in the Si channel of MOSFETs can be induced during device processing [START_REF] Thompson | Uniaxial-processinduced strained-Si: extending the CMOS roadmap[END_REF], and is particularly useful for boosting hole mobility. Application of strain changes the band structure and results in altered band structure with reduced effective mass and less scattering for the electrons as well as holes leading to higher mobility, while keeping the same channel material [START_REF] Lee | Strained Si, SiGe, and Ge channels for high-mobility metaloxide-semiconductor field-effect transistors[END_REF]. Both experimental and theoretical demonstrations have shown that the application of strain has the possibility to enhance on-currents by factors of around 4.5X in Si pMOSFETs and around 2X in nMOSFETs without a significant increase in leakage current [START_REF] Chu | Strain: A solution for higher carrier mobility in nanoscale MOSFETs[END_REF].

An important reason for using Si in the IC industry is the reliance on the easy fabrication of the Si/SiO 2 channel/dielectric system which is stable and of very high quality compared to combinations other channel materials and their native oxides. In recent years the SiO 2 has been replaced by gate oxides with higher dielectric constants. For example, using high-κ HfO 2 (κ ∼20-25) or hafnium silicon oxynitride (HfSiON) to replace SiO 2 (κ = 3.9) or SiON, and metal gate electrodes to replace doped polysilicon has helped to avoid succumbing to the physical limits of conventional scaling [START_REF] Frank | High-k/metal gate innovations enabling continued CMOS scaling[END_REF]. Higher gate capacitance can be obtained compared to a SiO 2 system while suppressing the gate leakage [START_REF] Houssa | High-κ Gate Dielectrics[END_REF]. A metal gate avoids poly depletion effects, offers lower gate resistance, lower phonon scattering and easy V t engineering by work function tuning. A high-κ metal gate system results in much higher mobilities compared to a high-κ polysilicon gate [START_REF] Chau | High-κ metal-gate stack and its MOSFET characteristics[END_REF]. Figure 1.6 shows how these two technology boosters helped maintain the technology improvement trend. Planar Fully Depleted Silicon On Insulator (FDSOI) MOSFETs (Figure 1.8) have been well known for a long time for their advantages over the bulk counterpart: good electrostatic control enabling lower V DD (for example [START_REF] Shang | 0.25 V FDSOI CMOS technology for ultra-low voltage applications[END_REF]), undoped/lightly doped channel leads to reduced random dopant fluctuations and hence reduced process variability, reduced source-substrate leakage due to presence of buried insulator layer, and most importantly, maintaining consistency with existing fabrication processes (e.g. the 28 nm bulk technology).

At the same technology node, Ultra Thin Body and Buried oxide (UTBB) FDSOI transistors allow to have shorter channel lengths than bulk devices. Body biasing (applying voltage to the substrate) the FDSOI device effectively makes it act like a double gate device (thanks to the very thin buried oxide layer) leading to much lower leakage and improved performance. Even in recent years the FDSOI MOSFETs have been the subject of active research [21] [START_REF][END_REF] and considered as viable alternatives to bulk CMOS, offering competition to other new technologies like FinFETs [START_REF] Faynot | Planar FDSOI technology for sub 22 nm nodes[END_REF].

A major deviation from the planar transistors are the Multi-Gate MOS-FETs, either bulk or SOI. Mulitple gates, particulalry the double and triple gate SOI FinFETs were the topic of extensive exploration in the last decade, although other possibilities: like quadruple gates, gate-all-around (GAA) MOS-FETs and bulk FinFETs have also been researched [24] [25]. Figure 1.9 shows three dimensional schematics of double and triple gate FinFET devices on fabricated on SOI. These devices, due to the presence of more than one gate,

Fin

BOX

Triple Gate

FinFET

III-V MOSFETs

ITRS 2011 lists alternative channel materials (ACM), namely III-V and Ge based MOSFETs as currently being pursued with a goal to enter production in the next 5-10 years [8]. Indeed, of late, a lot of research has been directed towards using these high mobility materials as MOSFETs channels. For example, Figure 1.10 depicts the increase in the number of publications concerning III-V MOSFETs in the last few years, hinting at the serious consideration of these devices by the academia as well the industry.

Motivation for ACM/Why III-V?

There has been, in fact a long interest in alternative channel materials for replacement of Si as channel material in transistors. The first transistor realized (point contact type) in 1947 was germanium based. As early as 1966, InAs channel transistors were proposed [START_REF] Brody | A high gain InAs thin-film transistor[END_REF] and in 1991 Ge CMOS was demonstrated [START_REF] Ransom | Gate-Self-Aligned N-Channel and P-Channel Germanium MOSFETs[END_REF]. But the growth of III-V/Ge CMOS for logic remained hindered because of several technological problems (e.g. Fermi level pinning), and high mobility materials were rather mostly used for HEMT devices (which are impractical for use as logic devices due to their large gate leakages). In the last decade, they have made a comeback as some of the stumbling blocks have been dealt with (for example unpinning the Fermi level using Ga 2 O 3 /Gd 2 O 3 as gate oxide [START_REF] Hong | Novel Ga 2 O 3 (Gd 2 O 3 ) passivation techniques to produce low D it oxide-GaAs interfaces[END_REF][START_REF] Zheng | Ga 2 O 3 (Gd 2 O 3 )/Si 3 N 4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion[END_REF], achieving good quality thermally grown GeO 2 [START_REF] Matsubara | Evidence of low interface trap density in GeO 2 /Ge metal-oxide-semiconductor structures fabricated by thermal oxidation[END_REF] etc.).

As explained in subsection 1.1.1.1 there is a need to lower V DD , while maintaining, or if possible, increasing the device speed. A channel material having higher carrier mobility compared to Si can achieve this goal. In this view, III-V/Ge MOSFETs are strong candidates for high performance (HP) logic as they can offer lower power (approaching V DD = 0.5 V) at speeds similar to, or even higher than the Si counterparts due to their inherent good transport Comparison of HP (high performance), LOP (low operating power), LSTP (low standby power), and III-V/Ge Technologies according to ITRS 2012 report [8] is shown in Table 1.1 in terms of device speed, dynamic power and static power dissipation. III-V/Ge devices with their higher speed and lower dynamic power, are expected to outperform Si HP devices.

ACM Trade-offs

Table 1.2 lists some material properties of certain materials as candidates for MOSFET channel material. As can be seen, what makes germanium and III-V compound semiconductor materials attractive is their much lower effective masses and higher carrier mobilities. Following Natori's ballistic model [START_REF] Natori | Ballistic metal-oxide-semiconductor field effect transistor[END_REF], the injection velocity of electrons in the device is related to the effective mass under non-degenerate conditions as follows [START_REF] Lundstrom | Essential physics of carrier transport in nanoscale MOSFETs[END_REF]:

v inj = 2κ B T /πm * (1.3)
Hence channel materials with lighter effective masses can provide higher injection velocity, v inj in ultra scaled MOSFETs. It has been demonstrated that these materials present greatly improved transport properties with respect to unstrained and even strained silicon [START_REF] Sze | Physics of Semiconductor Devices[END_REF].

III-V materials generally have multi-valley bandstructures: A primary Γ valley with low-effective-mass and satellite valleys (L and X) with higher effective mass for electrons. Many III-V materials, for example In x Ga 1-x As grown lattice matched to InP or InAs grown lattice matched to AlSb have very low effective masses in Γ valley as well as large inter-valley energy separations (∆ Γ-L , ∆ Γ-X which can be increased by increasing the In content) reducing the chances of spillover of electrons from Γ to L valley. This could lead to achieving higher mobilities at both low as well as high applied fields. However, III-V materials have some issues too. The low effective masses lead to low Density of States (DOS) as

DOS 2D = 2m * π 2 n v (1.4)
where m * is the DOS effective mass (for electrons in 2D, m * = √ m t * m t = m t ), n v is the valley degeneracy and the factor 2 accounts for spin degeneracy. This "DOS Bottleneck" can limit the maximum I on in the ballistic limit [START_REF] Fischetti | Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10 nm gate length[END_REF].

The contrast of the impact of the effective mass (m * ) on the v inj and the DOS as seen from equations 1.3 and 1.4 signifies the trade-off inherent in these materials. In addition, the band gaps (E g ) of most of the high mobility channel materials are considerably low. Therefore the leakage currents in these devices are expected to increase exponentially. Also, the high dielectric constant of Ge and III-V materials will result in easier encroachment of the drain electric field into the channel, thereby causing more relative loss of gate control on the channel electrostatics and hence poor device characteristics.

Material

Current Status of ACM Devices

Following the technological improvement and the potential performance increase of devices with Ge and III-V channels, successful fabrication of these high mobility material MOSFETs has already been achieved.

III-V MOSFET Architectures

During the course of the last few years, different architectures have been pursued by different academic and industrial groups for utilizing III-V compounds as channel materials. Some of the device structures are described below.

• Inversion Mode III-V MOSFETs (Surface Channel): It is a version of the bulk Si MOSFET with Si being replaced by III-V material, and the operating principles remain the same. Below the channel and source/drain implant layer, there exists a buffer layer followed by the substrate. Most devices demonstrated experimentally have been InGaAs based [START_REF] Lin | High-performance self-aligned inversion-channel InGaAs metal-oxide-semiconductor field-effect-transistor with AlO/GaO(GdO) as gate dielectrics[END_REF][START_REF] Xuan | High-performance inversion-type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm[END_REF][START_REF] Lin | Plasma PH 3 -passivated high mobility inversion InGaAs MOSFET fabricated with self-aligned gate-first process and HfO 2 /TaN gate stack[END_REF][START_REF] Goel | Addressing the gate stack challenge for high mobility In x Ga 1-x As channels for NFETs[END_REF], although other channel materials like GaAs based MOSFETs have also been fabricated [START_REF] De Souza | Inversion mode n-channel GaAs field effect transistor with high-κ/metal gate[END_REF]. Figures 1.12 and 1.13 show the schematics of such MOSFETs. This architecture is well known and understood in the mainstream silicon manufacturing community, hence it can be easily adapted to newer channel materials and it should have scalability similar to a bulk silicon MOSFET.

But it has an obvious major issue: the presence of the inversion channel at the gate dielectric/III-V interface can result in a lower mobility due to interface roughness scattering. Another issue is that of the appreciably lower thermal budget of III-V layer ion implantation annealing process (higher temperatures would cause As outdiffusion resulting in degraded channel) leading to lower possible source/drain doping level and hence higher source/drain contact resistance [START_REF] Thayne | Review of current status of III-V MOSFETs[END_REF], especially for thin channels. • QWFET (Quantum Well FET) with Regrown Source/Drain Architecture: The inherent problems with ion implanted S/D regions in a typical inversion mode device make it difficult to control the stoichiometry of the III-V channel, as mentioned in the previous section. To avoid this, one proposal is to keep essentially the same working principle, but have a fabrication process in which the S/D regions are formed by epitaxial growth after the patterning of the gate-stack, formation of gate dielectric sidewall spacers and etching out of the channel material in the desired S/D regions [START_REF] Rodwell | Technology development & design for 22 nm InGaAs/InPchannel MOSFETs[END_REF]. Also a high bandgap barrier layer is patterned below the channel layer for carrier con-finement (hence the name QWFET, Quantum Well Field Effect Transistor). The cross section of a MOSFET with regrown InGaAs S/D regions is shown in Figure 1.14. However, this structure also suffers from the degradation of the channel mobility due to it being at the surface. 2.4x10 12 cm -2 (n s = 2.3x10 12 cm -2 ). Taken from [START_REF] Passlack | Implantfree high-mobility flatband MOSFET: principles of operation[END_REF].

.

• Flatband QWFET (Implant Free): This architecture is derived from the conventional HEMT device structure, where the high mobility, low band gap channel is buried between higher band gap materials, creating a quantum well channel. The spatial separation of the channel from the gate dielectric helps to avoid the mobility degradation due to poor quality of the gate/channel interface and Coulomb scattering. These devices are called "Flatband" QFETs because the device is in on-state under flatband condition ( E = 0 in the gate oxide). For an n-channel device, as the gate voltage is lowered below the threshold voltage, the channel goes into depletion. These are majority carrier devices and do not utilise the surface inversion concept of minority carrier channel formation. An example of the layered epitaxial section is shown in Figure 1.15. While this architecture relaxes the need for a superior quality gate dielectric/channel interface, the ultimate scalability of this architecture is questionable due to the insertion of barrier layer between the gate and channel and the presence of δ-doping above the channel. • QWFET with Recessed Gate Architecture: This architecture has an undoped quantum well heterostructure layer, with gate-recess. For example the QWFET layer structure in Figure 1.16 consists of a In 0.52 Al 0.48 As buffer layer (undoped), a thin In 0.7 Ga 0.3 As strained quantum well (undoped), a In 0.52 Al 0.48 As top barrier layer (undoped), and a capping layer of n + In 0.53 Ga 0.47 As. All these layers are grown on a semi-insulating InP substrate by molecular beam epitaxy (MBE) [START_REF] Sun | Enhancement-mode buried-channel In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As MOSFETs with high-κ gate dielectrics[END_REF]. The n + cap layer is selectively etched to form a gate recess area. Being a buried channel device, it is less affected by the gate-oxide/semiconductor interface non-idealities. Also, unlike the Flatband QWFET, it does not use δ doping layer, hence the vertical scalability is better. This scheme has been used in conjunction with high-κ dielectric stack

InAlAs bottom barrier

InP Layer 2 nm

Gate Source

InGaAs QW Channel 10 nm n ++ InGaAs 20 nm

TaSiO x

Drain

Figure 1.17: Schematic of planar, thin body, High-κ/Metal Gate In 0.7 Ga 0.3 As MOSFET [START_REF] Dewey | III-V field effect transistors for future ultra-low power applications[END_REF] and metal gate to realize planar, tri-gate MOSFETs as well as TFETs, demonstrating excellent performance [START_REF] Dewey | III-V field effect transistors for future ultra-low power applications[END_REF]. Figures 1.16 and 1.17 show examples of this kind of MOSFETs.

In this work, the considered device structure has been primarily a double gate MOSFET with a non silicon channel for the sake of modeling and understanding.

III-V and Si Heterogeneous Integration

To utilize the well established Si processing platform and for heterogeneous integration with other Si based components, one possibility worth considering is that of growing new high-mobility materials epitaxially on Si substrate. For example, [START_REF] Takagi | Advanced CMOS technologies using III-V/Ge channels[END_REF] classifies the possibilities into the following different configurations:

• The 'More Moore' approach refers to continuing scaling and is geared towards achieving higher drive currents and has the prospects of Ge CMOS on insulator, III-V CMOS on insulator and III-V NMOS and Ge PMOS on insulator with silicon as the substrate.

• The 'More than Moore' approach is concerned with functional diver-sification for non-digital content. It allows technology incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law", but provide additional value in different ways. Some examples are: III-V/Ge-on-insulator-on Si optical devices, ultra fast analog devices, sensors and MEMS.

• Going beyond CMOS, III-V/Ge tunnel FETs are also being pursued.

Figure 1.18 shows these options currently being researched: for both More Moore as well as More than Moore approaches.

Need to evaluate SCEs in III-V MOSFETs

III-V devices for logic applications are projected to be introduced beyond the 16 nm gate length according to PIDS 2011 predictions [8]. The short channel effects worsen and limit the device performance as we keep scaling. The impact of the extremely small separation between the source and the drain on the device performance can be analyzed through analytical modeling and numerical simulation techniques.

Although III-V compounds offer higher mobilities, the impact of different effective masses and material parameters compared to Si needs to be investigated, so as to predict the scalability and margin of benifit compared to Si technology. The advantage of power consumption reduction possible with III-V technology against the degradation in short channel effects and increased leakage needs to be analyzed; and optimum channel lengths for introduction of III-V channels need to be determined.

Aim of the Thesis

The aim of this thesis, thus, is to examine these issues of MOSFETs with alternative channel materials from a modeling and simulation perspective. While doing so, the current technlogical limitations with regard to III-V device fabrication, stability and reliability will be ignored so as to treat a best case scenario, assuming the limitations will be overcome by the industry in the coming years, as has been done for Si technology in the past.

Organization of the Thesis

The rest of the thesis is organised as follows: The second chapter deals with modeling of the 2D channel potential in a double gate MOSFET. Then follows the main work of this thesis: the study of the role of quantum effects on SCEs in MOSFETs with alternative channel materials is described in chapter 3. The impact of source-to-drain tunneling on the scalability of III-V devices is examined in chapter 4. Finally, conclusions are drawn and some future perspectives are discussed in chapter 5.

Chapter 2

Modeling of the channel potential in a MOSFET

Introduction

The development of the transistor industry has always been accompanied by a need to develop physics based models, which can predict the behavior of the transistors while giving insight into the underlying physical phenomena in the devices. Analytical models make it easy to understand the change in input and output characteristics as one varies different parameters of the device. It is particularly useful when one considers scaling the device: be it geometrical or V DD or changing electrical parameters. Also, analytical models come in handy when we need MOSFET models for use in circuit simulators. Physically based analytical models of MOSFET channel potential are essential for rigorously capturing short channel effects [START_REF] Liu | Threshold voltage model for deep-submicrometer MOS-FETs[END_REF], evaluating scaling behavior [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF] and are required to evaluate subthreshold leakage [START_REF] Rafhay | Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs[END_REF].

The focus of this chapter is to look at some of the major techniques to model the channel potential, select an analytical model, demonstrate its efficacy for predicting the short channel effects (SCEs). We then discuss an issue with the boundary conditions in the existing models due to non inclusion of the Source/Drain regions of the MOSFET in the analysis, that results in erroneous evaluation of channel potential. The impact of the source and drain on the the potential and hence on the short channel effects (drain induced barrier lowering and subthreshold slope) will be investigated at first. A correction to the boundary conditions is proposed and incorporated into the channel potential model. The concept is then validated using numerical simulations.

Channel Potential Modeling

This section describes the analytical model of the channel potential developed by Tsormpatzoglou et al. [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] as an example of modeling the channel potential in a double gate MOSFET and the associated short channel effects.

Analytical Modeling

The schematic of the cross section of the device with the coordinate system used is shown in Figure 2.1 In the weak inversion region of operation, the channel potential can be described by the Poisson's equation as:

∂ 2 V (x, y) ∂x 2 + ∂ 2 V (x, y) ∂y 2 = qN a ε Si ; 0 ≤ x ≤ t Si , 0 ≤ y ≤ L (2.1)
where N a is the p-type doping concentration in the channel, ε Si is the dielectric constant of silicon, t Si is the channel thickness and L is the channel length.

For low values of drain voltage, the potential in the channel can be assumed to be a parabolic function:

V (x, y) = c 0 (y) + c 1 (y)x + c 2 (y)x 2 (2.2)
where c 1 , c 2 and c 3 are functions of y alone. Since the potentials at the top and bottom channel/oxide interfaces are equal because of the symmetry of the device structure,

V s (y) ≡ V (0, y) ≡ V (t Si , y) (2.3)
And the boundary conditions are:

dV (x, y) dx x=0 = ε ox ε Si V s (y) -V g t ox (2.4a) dV (x, y) dx x=t Si = ε ox ε Si V g -V s (y) t ox (2.4b)
where

V g = V g -V F B , V g is the applied gate voltage, V F B
is the flatband voltage and ε ox and t ox are the dielectric constant and thickness of the gate oxide.

On solving the system of equations (2.2), (2.3) and (2.4), the coefficients c i can be obtained as:

c 0 = V s (y) (2.5a) c 1 = ε ox ε Si V s (y) -V g t ox (2.5b) c 2 = ε ox ε Si V g -V s (y) t ox t Si (2.5c)
Substituting coefficients from (2.5) in (2.2):

∂ 2 V (x, y) ∂x 2 = 2c 2 = 2 ε ox ε Si V g -V s (y) t ox t Si (2.6a) ∂ 2 V (x, y) ∂y 2 = ∂ 2 c 0 ∂y 2 + x ∂ 2 c 1 ∂y 2 + x 2 ∂ 2 c 2 ∂y 2 (2.6b) = ∂ 2 V s (y) ∂y 2 + x ε ox ε Si 1 t ox ∂ 2 V s (y) ∂y 2 -x 2 1 t ox t Si ∂ 2 V s (y) ∂y 2 (2.6c) = ∂ 2 V s (y) ∂y 2 1 + x t ox ε ox ε Si - x 2 t ox t Si ε ox ε Si (2.6d) Using (2.6) in (2.1): 2 ε ox ε Si V g -V s (y) t ox t Si + ∂ 2 V s (y) ∂y 2 1 + x t ox ε ox ε Si - x 2 t ox t Si ε ox ε Si = qN a ε S i (2.7) ⇒ ∂ 2 V s (y) ∂y 2 1 + x t ox ε ox ε Si - x 2 t ox t Si ε ox ε Si -2 ε ox ε Si V s (y) t ox t Si = qN a ε S i -2 ε ox ε Si V g t ox t Si (2.8) ⇒ ∂ 2 V s (y) ∂y 2 ε Si t ox t Si + xt Si ε ox -x 2 ε ox -2ε ox V s (y) = qN a t ox t Si -2ε ox V g (2.9)
Thus, finally we get the following differential equation:

d 2 Vs(y) dy 2 -αV s (y) = β (2.10)
where

α = 2ε ox ε Si t ox t Si + t Si ε ox x -ε ox x 2 β = qN A t ox t Si -2ε ox V g ε Si t ox t Si + t Si ε ox x -ε ox x 2
The auxiliary equation is: r 2 -α = 0, whose roots are: ± √ α Hence, the eneral solution is of the form:

V s (y) = Ae √ αy + Be -√ αy
and the particular solution is of the form:

z(y) = κ
Hence we have: z = κ, z = 0 and z = 0 Using this in equation (2.10):

-ακ = β ⇒ κ = -β/α
Hence the complete solution is:

V s (y) = Ae √ αy + Be -√ αy -β/α Since V s (y) is evaluated at x = 0, let V s (y) = Ae y/λ 1 + Be -y/λ 1 -β/α (2.11)
where

λ 1 = 1/ √ α x=0 = ε Si t ox t Si 2ε ox (2.

12)

Let

A 1 = κ = -β/α = V g - qN a t Si t ox 2ε ox (2.13)
Now the following boundary conditions are applied for finding A and B:

V s (y) y=0 = V bi (2.14a) V s (y) y=L = V bi + V d (2.14b)
where

V bi = k b T ln N a N d n 2 i (2.15)
with k b the Boltzmann constant, T the temperature, N a the substrate doping, N d the S/D doping, and n i the intrinsic carrier concentration of the channel semiconductor material.

So we have:

V bi = A + B + A 1 ⇒ A = V bi -A 1 -B (2.16a) V bi + V d = Ae L/λ 1 + Be -L/λ 1 + A 1 ⇒ (V bi -A 1 -B)e L/λ 1 + Be L/λ 1 = V bi + V d -A 1 ⇒ B = V bi + V d -A 1 -(V bi -A 1 )e L/λ 1 e -L/λ 1 -e L/λ 1 (2.16b)
Using (2.16) in (2.11):

V s (y) = V bi -A 1 - V bi + V d -A 1 -(V bi -A 1 )e L/λ 1 e -L/λ 1 -e L/λ 1 e y/L + V bi + V d -A 1 -(V bi -A 1 )e L/λ 1 e -L/λ 1 -e L/λ 1 e -y/λ 1 + A 1 = A 1 + (V bi -A 1 )e y/λ 1 + V bi + V d -A 1 -(V bi -A 1 )e L/λ 1 e -L/λ 1 -e L/λ 1 e -y/λ 1 -e y/λ 1 = A 1 + (V bi -A 1 )e y/λ 1 + V bi + V d -A 1 -(V bi -A 1 )e 2L/λ 1 e 2L/λ 1 -1 e y/λ 1 -e -y/λ 1
Rearranging, the expression for the surface potential V s (y) is thus obtained as:

V s (y) = 1 e 2L λ 1 -1 (V bi + V d -A 1 ) e L+y λ 1 -e L-y λ 1 + (V bi -A 1 ) e 2L-y λ 1 -e y λ 1 +A 1 e 2L λ 1 -1 (2.17)
Here λ 1 can be recognized as the natural channel length as proposed by Yan et al. [START_REF] Yan | Scaling the Si MOSFET: from bulk to SOI to bulk[END_REF] and is used to characterize the short channel effects in a MOSFET. Now for finding V (x, y) from, (2.5) and (2.17) are used in (2.2):

V (x, y) = V s (y) + ε ox ε Si V s (y) -V g t ox x + ε ox ε Si V g -V s (y) t ox t Si x 2 (2.18)
Consider a point at a depth x = t Si /n(n = 0) and a given distance y along the channel. The 2D potential V (x, y) ≡ V x (y) becomes:

V (x, y) = V s (y) 1 + ε ox t Si ε Si t ox n - ε ox ε Si t Si t ox n 2 + V g ε ox ε Si t Si t ox n 2 - ε ox t Si ε Si t ox n (2.19) = V s (y) 1 + ε ox t Si ε Si t ox n -1 n 2 + V g ε ox t Si ε Si t ox 1 -n n 2 (2.20) Hence V s (y) = V (x, y) 1 + ε ox t Si ε Si t ox n -1 n 2 -1 + V g εox ε Si t Si tox n-1 n 2 1 + εoxt Si ε Si tox n-1 n 2 (2.21) = k 1 V (x, y) + k 2 V g (2.22) = k 1 V x (y) + k 2 V g (2.23)
where

k 1 = 1 1 + εoxt Si (n-1) ε Si toxn 2 , k 2 = 1 1 + ε Si toxn 2 εoxt Si (n-1) (2.24)
Now, going back to the differential equation obtained for V s (y), from equation (2.10)

d 2 Vs(y) dy 2 -αV s (y) = β ⇒ k 1 d 2 Vx(y) dy 2 -αk 1 V x (y) -αk 2 V g = β ⇒ d 2 Vx(y) dy 2 -αV x (y) = β + αk 2 V g k 1 (2.25)
Let's define:

α = α(x = t Si /n) (2.26) = 2ε ox ε Si t Si t ox + εoxt Si 2 n -εoxt Si 2 n 2
(2.27)

β = β + αk 2 V g k 1 x=t Si /n
(2.28)

= qNatoxt Si -2εoxV g ε Si toxt Si + t Si εoxt Si 2 n - εoxt Si 2 n 2 + 2εoxk 2 V g ε Si t Si tox+ εoxt Si 2 n - εoxt Si 2 n 2 k 1 (2.29)
Thus we now have the following differential equation for V x (y):

d 2 Vx(y) dy 2 -α V x (y) = β (2.30)
To solve (2.30) we use the boundary conditions:

V x (y) y=0 = V bi V x (y) y=L = V bi + V d
Since equation (2.30) is similar to equation (2.10), the solutions should be similar. We have

λ 2 = 1/α = ε Si t ox t Si + εoxt 2 Si n - εoxt 2 Si n 2
2ε ox (2.31a)

A 2 = - β α = 2ε ox (1 -k 2 )V g -qN a t ox t Si 2ε ox k 1 (2.31b) V x (y) is obtained as: V x (y) = 1 e 2L λ 2 -1 (V bi + V d -A 2 ) e L+y λ 2 -e L-y λ 2 + (V bi -A 1 ) e 2L-y λ 2 -e y λ 2 +A 2 e 2L λ 2 -1 (2.32)
Finally, we reexpress V x (y) as V (x, y) by using (2.32) and (2.31), and switching from (t Si /n) to x:

V (x, y) = 1 e 2L λ 3 -1 (V bi + V d -A 3 ) e L+y λ 3 -e L-y λ 3 + V S bi -A 3 e 2L-y λ 3 -e y λ 3
+A 3 e 2L λ 3 -1

(2.33)

where

A 3 = V g -qN A ε Si t ox t Si + ε ox (t Si -x) x 2ε ox ε Si (2.34a) λ 3 = ε Si t ox t Si 2ε ox 1 + ε ox ε Si x t ox - ε ox ε Si x 2 t ox t Si (2.34b)
Here, A 3 can be shown to be the long channel surface potential and λ 3 is the scale length.

Concept of the extra potential in a short channel MOSFET

A short channel MOSFET's potential distribution can be seen to be incremented by an extra amount relative to the long channel case. The potential in the short channel case, V (x, y) is reduced to the long channel case, V long (x) = A 3 (which can be obtained on solving (2.1)-(2.4) under the assumption of constant potential in the direction along the channel.) Thus there is a 2D extra potential, ∆V (x, y) = V (x, y) -V long (x) which is attributed to the SCEs and can be expressed as:

∆V (x, y) = 1 e 2L λ 3 -1 (V bi + V d -A 3 ) e L+y λ 3 -e L-y λ 3 + (V bi -A 3 ) e 2L-y λ 3 -e y λ 3
(2.35)

FlexPDE Numerical Simulation

The partial differential equation solver FlexPDE was used for carrying out the numerical simulations. FlexPDE is a "scripted finite element model builder and numerical solver" [START_REF]FlexPDE User Guide[END_REF]. A symbolic equation analyzer expands defined parameters and equations, performs spatial differentiation, and symbolically applies integration by parts to reduce second order terms to create symbolic Galerkin equations. It then symbolically differentiates these equations to form the Jacobian coupling matrix. Its mesh generation facility generates an unstructured a triangular finite element mesh over a two-dimensional problem domain (as in this work). The finite element numerical analysis module selects the appropriate solution scheme. The adequacy of the mesh is consistently evaluated by an adaptive mesh refinement procedure and the mesh is refined whenever there is large error. The system iterates the mesh refinement and solution until a user-defined error tolerance is achieved. It has graphical output facility for plotting the output and a data export facility to write the solution data to text files. The mesh density can be user controlled. The typical structure simulated looks like the one in Figure 2.

2 ch L Si t g fb V V V = - bi d V V V = + 0, g fb V x V V V ∂ = ∂ = - bi V V = ox t Figure 2.2: FlexPDE Simulation Structure
In this work the main equations solved in the FleXPDE simulations are:

Poisson's Equation:

∇ • (∇V ) = - ρ ε (2.36)
Drift Diffusion:

∇ • qnµ∇V n = 0 (2.37)
Drain Current :

I d = qnµdV n L (2.38)
The following Boltzmann distributions were assumed for the charge:

In the source region:

ρ = q p 0 e -(V -V bi -V d )/kT -n 0 e (V -V bi -V d )/kT + N d
In the channel:

ρ = q p 0 e -V /kT -n 0 e V /kT -N a
In the drain region:

ρ = q p 0 e -(V -V bi )/kT -n 0 e (V -V bi )/kT + N d

Comparison: Model Vs Numerical Simulation

The analytical model for the channel potential is compared with the potential obtained from numerical simulation. They are found to be in agreement, validating the model for good L g /t Si ratios. Figure 2.3 compares the center channel potential and the surface potential for a MOSFET with 25 nm gate length, while Figure 2.4 shows the comparison of the minimum surface potential (or top of the barrier) as a function of the gate length for three different channel thicknesses.

The Question of Boundary Conditions

Recently, a detailed review and critic of these models has been published in [START_REF] Xie | Review and critique of analytic models of MOSFET short-channel effects in subthreshold[END_REF], showing that, even 40 years after the first SCEs analytical models,

(t Si =5 nm, V g =0.5 V, V d =0 V, V f b =0.2 V)
(V g =0.5 V, V d =0 V, V f b =0.2 V, t Si =5 nm, 7.5 nm, 10 nm)
no consensus has been reached regarding the most efficient and rigorous approach. In this review however, Xie et al. have classified different types of models and in particular, the models based on polynomial description or based on the analytical solution of the 2D Poisson equation have been identified has the most suitable to reproduce SCEs, as they capture the impact of the oxide thickness [START_REF] Xie | Review and critique of analytic models of MOSFET short-channel effects in subthreshold[END_REF]. All these models [START_REF] Liu | Threshold voltage model for deep-submicrometer MOS-FETs[END_REF][START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] use the built-in potential as boundary condition for the potential at the source/channel and drain/channel interface, thus allowing to neglect the role of source and drain on the potential, assuming source drain as very highly doped or almost metallic. Implicitly, this type of boundary condition assumes that there are no voltage drops in the source and drain and hence that the doping of the source and drain is very high.

To evaluate short channel effects, numerical simulations are at first carried out using the 2D partial differential equation solver, FlexPDE. Poisson and drift-diffusion equations are self-consistently solved in two cases: the first one includes the source/drain regions and boundary conditions for the potential are set as V bi and V bi +V d respectively, at the beginning of the source and at the end of the drain, as shown in Figure 2.5. The second one does not take source and drain into account. As shown in Figure 2.5, in this case, V bi and V bi + V d are applied as boundary condition for the potential, at the source and drain end of the channel respectively, as assumed by all SCE models [START_REF] Xie | Review and critique of analytic models of MOSFET short-channel effects in subthreshold[END_REF] The devices used in the study are double gate MOSFETs with gate lengths of 10, 15 and 20 nm and channel thicknesses of 3, and 5 nm with 2 nm thick gate oxides. Doping levels in the source and drain are set between 10 24 to 10 25 m -3 in the simulations.

Impact of the Source/Drain regions on SCEs

The DIBL and the subthreshold slope (SS) of the double gate devices simulated using the self-consistent solution of the DD and Poisson equation are shown in Figure 2.6. Cleary, excluding the source/drain region by applying V bi and V bi + V d as potential boundary conditions at the edges of the channel, results in a huge overestimation of the SCEs. The DIBL and SS are found to be lesser in the case where S/D regions are included, with V bi and It can be seen that the slopes of the V min Vs V g plots are weaker when the S/D region are excluded than when they are included. This difference is enhanced for shorter gate lengths.

V bi + V d V g V bi V bi +V d Gate Oxide Channel V g Source Drain V bi V bi +V d Gate Oxide Gate Oxide Channel V g V g Drain Channel Gate Oxide Gate Oxide
Further, as shown in Figure 2.9, ∆V min is the change in the minimum channel potential as the drain voltage changes from V d =0 V to V d = 0.9 V.

∆V min = V min (V d = 0.9V ) -V min (V d = 0V ) (2.39)
Hence ∆V min can be seen as an indirect estimation of the DIBL. The variation of this change in the minimum of the potential, ∆V min per unit of the shift in drain voltage (∆V d = 0.9 V) has been plotted as a function of the gate length in Figure 2.10 (the same device geometry has been used). It can be seen that it is larger when the source/drain region are neglected, and smaller when the source/drain region are included in the simulation.

D i s t a n c e a l o n g t h e c h a n n e l ( n m )

V g = -0 . 4 V

V g = -0 . 2 V V g = 0 . 0 V V m i n ( V g )

G a t e v o l t a g e ( V ) O n l y e l e c t r o s t a t i c s ( P o i s s o n E q ) T S i = 5 n m W i t h S / D

P o t e n t i a l ( V )

V d = 0 V V d = 0 . 9 V These two results demonstrate that the overestimation of the SCEs obtained by applying V bi and V bi + V d as potential boundary conditions at the edges of the channel in the self-consistent solution of the DD and Poisson simulation originates from purely electrostatic effects.

D i s t a n c e a l o n g t h e c h a n n e l ( n m )

Effective Built-In Potential, V ef f bi

Two strategies are then possible to include the impact of the source/drain regions in the analytical modeling of the channel potential. Either new analytical models need to be developed, which would include the S/D in the solution of the Poisson equation. Or, the same modeling structure could be kept and new boundary conditions at the edge of the channel could be used in order to fit the simulations which include the S/D regions.

To evaluate the feasibility of the second strategy, Poisson simulations of the architecture without S/D have been carried out with arbitrarily modified It can be seen that, when using two modified built-in potential values, designated here as V ef f,S/D bi , the channel potential obtained neglecting the S/D matches with the potential obtained while including the S/D. This result suggests that it is possible to fit the results obtained including the S/D region, by using the right boundary conditions. Therefore, an analytical model of the effective build-in potential should be sufficient to correct the already existing analytical models of the channel potential and hence of the short channel effects. To model V bi ef f , the voltage drop ∆V bi at the source/channel and channel/drain junction needs to be found, as:

G a t e L e n g t h ( n m ) W i t h o u t S / D

V ef f,S/D bi = V bi -∆V S/D bi (2.40)
The Poisson simulation carried out in section 2.3 indicates that the charge in the S/D region mainly results from depleted layers. Therefore, the field at the source/channel and channel/drain interface, but still in the S/D region, is simply given by [START_REF] Sze | Physics of Semiconductor Devices[END_REF]:

F x = 0 -= 2q εs N d ∆V S bi F x = L + g = -2q εs N d ∆V D bi (2.41)
where q is the elementary charge, ε s the semiconductor dielectric constant. ∆V bi S and ∆V bi D are different voltage drops as they depend on the applied source/drain voltages as seen in Figure 2.11.

∆V bi S/D can then be found by equating the field on each side of the junctions. This is easily accomplished by using closed form analytical model of the channel potential. In this work, the model proposed in [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] has been used to find ∆V bi . This can however be also be done with other models, such like the often quoted Liu model [START_REF] Liu | Threshold voltage model for deep-submicrometer MOS-FETs[END_REF].

The equation of V(x,y) given by equation (2. [START_REF] Sze | Physics of Semiconductor Devices[END_REF]) is used at first. The equation of the field can then be obtained as:

|F | = 1 e 2L λ 3 -1 λ 3 V D bi + V D -A 3 e L+y λ 3 -e L-y λ 3 + V S bi -A 3 e 2L-y λ 3 -e y λ 3
(2.42)

From (2.42), it is found that:

F x = 0 + = (V S bi -A 3) λ 3 F x = L - g = - (V D bi +V D -A 3) λ 3
(2.43)

By equating (2.41) and (2.43) at x = 0 and x = L g , an expression of ∆V bi is obtained as:

∆V S/D bi = V bi + V S/D -A 3 + λ 3 2 q ε s N d   1 -1 + 2(V bi + V S/D -A 3 ) λ 3 2 q εs N d   (2.44)

Impact of the Source/Drain doping

Self-consistent DD and Poisson simulations are carried out for two different source/drain doping concentrations, N d using the same simulation framework and same template structure as in section 2.3.The DIBL and SS obtained are reported in Figure 2.12. It can be seen that higher value of the doping concentration slightly reduced the difference between the two. It means that using the conventional boundary conditions result in more erroneous results as the source/drain doping is reduced. It can be explained as an increse in the effective channel length of the MOS-FETs since at conditions of low doping levels and depletion in source/drain regions, the channel-source/drain boundary shifts from the ideal case of degenerate doping in the source/drain. And the increased effective channel length leads to improved short channel effects. This can be very relevant for SCE calculations for some III-V devices where it's difficult to highly dope the source/drain regions due to limited thermal budget, as mentioned previously in section 1.2.3

D I B L ( m V / V ) G a t e L e n g t h ( n m ) W i t h o u t S / D W i t h o u t S / D W i t h S / D

Further, using the model derived in the previous section, ∆V bi was calculated for different channel materials (different dielectric constants and band gaps) as a function of source/drain doping concentrations. The results are plotted in Figure 2 1 .

.

1 . for each material till a doping concentration of around 10 23 m -3 and starts to decrease afterwards, but with different slopes, the steepness of the slopes being proportional to the bandgaps of the materials. It's because the V bi for each material can be represented as function of the band gaps as:

.

D V b i ( V ) l o g ( N d ) S i G e G a A s I n G a A s

V bi (∆E g ) = kT q ln N a N d n i,Si 2 + ∆E g where (2.45) ∆E g = E g,sc -E g,Si (2.46)
This, in conjunction with the doping levels, affects the V F B , and hence V g and A 3 , and finally ∆V bi .

Corrected Short Channel Effects

The short channel effects of the same template structure used in section 2.3 have been recalculated using the corrected effective built-in potential, given by equations (2.40) and (2.44), for the architecture excluding the S/D region. As shown in Figure 2.14, the results obtained by neglecting the S/D region but using the built-in potential correction are now perfectly fitting the results obtained with the architecture including the S/D. This demonstrates that the overestimation of the short channel effects, caused by neglecting the voltage drop resulting from the depletion layer in the source and drain, can be simply corrected by using the effective built-in potential formula obtained in (2.40) and (2.44). This also allows to correct most of the already proposed analytical models of the short channel effects.

W i t h o u t S / D , V b i W i t h o u t S / D , V b i e f f S S ( m V / d e c ) G a t e L e n g t h ( n m ) W i t h S / D , V b i W i t h o u t S / D , V b i W i t h o u t S / D , V b i e f f D I B L ( m V / V ) G a t e L e n g t h ( n m )

Conclusion

In this chapter, the effect of the inclusion of the source/drain regions of a MOSFET on the channel potential modeling has been investigated. It has been found that in the conventional modeling approaches, the exclusion of the S/D regions leads to an overestimation of the SCEs. It is hence essential to include the S/D regions for obtaining realistic values of the potential distribution and the SCEs. This can be achieved by using an already existing model, but by replacing the built-in potential value by a modified one, proposed in this chapter. This approach can be extended to other models and devices (e.g. TFETs)

Chapter 3

Origin of SCE increase in III-V MOSFETs

SCEs in III-V MOSFETs

The replacement of silicon as channel material by III-V semiconductors has emerged as a realistic option for the end of the roadmap of CMOS as discussed in Chapter 1. However, simulations and experimental results have shown that III-V technologies are subject to enhanced short channel effects, including larger V t roll-off, larger drain induced barrier lowering and subthreshold slope than the silicon devices [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF][START_REF] Radosavljevic | Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gateto-source separation[END_REF][START_REF] Pethe | Investigation of the performance limits of III-V doublegate n-MOSFETs[END_REF][START_REF] Hwang | Investigation of scalability of In 0.7 Ga 0.3 As quantum well field effect transistor (QWFET) architecture for logic applications[END_REF], which might compromise their use for the end of the roadmap of CMOS devices [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF]. In particular, references [START_REF] Pethe | Investigation of the performance limits of III-V doublegate n-MOSFETs[END_REF] and [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] have shown by numerical simulation and analytical modeling that the subthreshold slopes of Ge and III-V MOSFET were larger than in Si, and [START_REF] Hwang | Investigation of scalability of In 0.7 Ga 0.3 As quantum well field effect transistor (QWFET) architecture for logic applications[END_REF] has demonstrated that In 0.7 Ga 0.3 As Quantum Well FETs present poor scalability for the same reason.

In addition to the increased SCEs, it has been shown by the means of simulation that quantum confinement in III-V channel is enhanced [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] O'regan | Calculation of the capacitance-voltage characteristic of GaAs, In 0.53 Ga 0.47 As, and InAs metal-oxide-semiconductor structures[END_REF]. Indeed, due to the smaller effective masses and hence the smaller density of states (DOS) of these semiconductors, a larger degradation of the gate coupling with the channel is expected with respect to silicon channel [START_REF] Pal | Influence of bandstructure and channel structure on the inversion layer capacitance of Si and GaAs MOSFETs[END_REF]. This effect is shown to result in an increased electrical Equivalent Oxide Thickness (EOT) with respect to the physical oxide thickness, phenomenon also called dark space [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] O'regan | Calculation of the capacitance-voltage characteristic of GaAs, In 0.53 Ga 0.47 As, and InAs metal-oxide-semiconductor structures[END_REF][START_REF] Rafhay | Impact of channel orientation on ballistic current of nDGFETs with alternative channel materials[END_REF]. The concept of dark space has been explained in section 3.2.1

Recently published results [START_REF] Wu | Impact of quantum confinement on short-channel effects for ultrathin-body germanium-oninsulator MOSFETs[END_REF][START_REF] Yu | Impact of quantum confinement on subthreshold swing and electrostatic integrity of ultra-thin-body GeOI and InGaAs-OI n-MOSFETs[END_REF] have stated that the quantum effects could impact the short channel effects in the subthreshold regime. However, these results are questionable as the approach used in these works consists in comparing a classical simulator, an analytical model based on Poisson-Schrödinger fitting and quantum corrected TCAD simulation. These different codes are known to show some significant divergences and should be carried out with care, as done in [START_REF] Palestri | Comparison of modeling approaches for the capacitance-voltage and currentvoltage characteristics of advanced gate stacks[END_REF] for different quantum confinement codes or in [START_REF] Palestri | Comparison of advanced transport models for nanoscale nMOSFETs[END_REF] for different codes of transport in nanoscale nMOSFET. Moreover, SCEs have been shown to have a detrimental impact on inverter performances in the strong inversion regime. Indeed, it has been shown in [START_REF] Gwoziecki | 32 nm device architecture optimization for critical path speed improvement[END_REF][START_REF] Deng | Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities[END_REF] that the SCEs in strong inversion regime, and especially the non saturation of the drain current caused by the Drain Induced Barrier Lowering (DIBL) could severely degrade the delay and propagation time of inverter and ring oscillator. Therefore, a comprehensive evaluation of the impact of SCEs in III-Vs should not be limited to the subthreshold regime only, as carried out in [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF][START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF][START_REF] Pethe | Investigation of the performance limits of III-V doublegate n-MOSFETs[END_REF][START_REF] Hwang | Investigation of scalability of In 0.7 Ga 0.3 As quantum well field effect transistor (QWFET) architecture for logic applications[END_REF][START_REF] Batail | Germanium-On-Nothing (GeON): an innovative technology for ultrathin Ge film integration[END_REF], but should also include strong inversion. In this regime however, the impact of quantization on the inversion charge is no longer negligible, which raises the question of role of quantum effect on the DIBL in strong inversion. Two questions hence still remain open:

• Do quantum effects impact the short channel effects in the subthreshold regime?

• Do quantum effects impact the DIBL in the strong inversion regime?

Therefore, SCEs in subthreshold regime will be investigated in section 3.2 of this chapter, with and without including quantum effects. Impact of material parameters is explored in section 3.3. Finally, section 3.4 will then present the role quantum effects on the DIBL in strong inversion regime. 3.2 Quantum Effects and SCEs in Subthreshold Regime

Concept of Dark Space

When quantum confinement in the channel is taken into account, lesser inversion charge is obtained at the same gate overdrive and this effect can be modeled as an artificial increase of the Equivalent Oxide Thickness (EOT) of the gate dielectric. This incremental EOT is called the "dark space" thickness, DS [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF].

It is well known that as a result of quantization of the inversion layer in a MOSFET, electron density is found to vanish at the channel/gate oxide interface while reaching the maximum value at some distance into the semiconductor, away from the interface [START_REF] Ando | Electronic properties of twodimensional systems[END_REF], in contrast to the classical case where the maximum electron density is expected at the interface. Figure 3.5 shows this phenomenon. There is lesser coupling of the gate voltage with the inversion charge. It is especially important in modern nanometric MOS devices where the oxide thickness is very small and is comparable to the extent of inversion layer penetration into the channel [START_REF] Lopez-Villanueva | Effects of the inversion layer centroid on MOSFET behavior[END_REF]. The dark space is proportional to the distance of the inversion charge centroid from the channel/gateoxide interface. The inversion charge centroid, z inv can be expressed as [START_REF] Lopez-Villanueva | Effects of the inversion layer centroid on MOSFET behavior[END_REF] [58]:

z (nm) n(z) (cm -3 )

z inv = ∞ 0 zρ inv (z) dz ∞ 0 ρ inv (z) dz (3.1)
On changing the effective mass of the channel material, the charge centroid shifts and hence the dark space is altered. The impact of this phenomenon on different channel materials is discussed in the next subsections.

Simulation Methodology

To investigate the potential effect of quantum confinement on short channel effects, several previous works have compared the results obtained using classical simulator with results obtained with an analytical model and quantum corrected TCAD simulator [START_REF] Wu | Impact of quantum confinement on short-channel effects for ultrathin-body germanium-oninsulator MOSFETs[END_REF][START_REF] Yu | Impact of quantum confinement on subthreshold swing and electrostatic integrity of ultra-thin-body GeOI and InGaAs-OI n-MOSFETs[END_REF]. However, as mentioned in the preceding section, this simple approach is not reliable. Therefore, to avoid the above mentioned issue of inconsistencies across different simulators, the results presented in this section have been obtained using the same tool, i.e. the NanoMOS [71,[START_REF] Ren | NanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs[END_REF] simulator suite, which self consistently solves the Poisson-Schrödinger (PS) equations, along the channel, with different transport models. Indeed, although NanoMOS being better known for its Non Equilibrium Green Function (NEGF) transport model, it also includes a Ballistic Transport Model (BTM) model and a Drift Diffusion (DD) model, which are all self consistently solved with the PS equations [71]. The NEGF model in NanoMOS is a ballistic transport model (called the Quantum Ballistic Transport Model, QBTM) which accounts for all source-drain tunneling components, and in particular the subthreshold source-to-drain tunneling, which has been shown to be significant for ultra short channel (< 15 nm) III-V nMOSFETs [START_REF] Rafhay | Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs[END_REF][START_REF] Cantley | Performance analysis of III-V materials in a double-gate nano-MOSFET[END_REF]. There is another transport model (called the Classical Ballistic Transport Model, CLBTM) which, although takes into account the quantum confinement in the vertical direction, neglects the source-drain tunneling component of the drain current. The DD model available in NanoMOS differs from conventional drift diffusion model as the charge is rigorously calculated using a Poisson-Schrödinger solver. As an example, the simulation scheme for the full quantum ballistic transport calculation in NanoMOS is shown in Figure 3.6. The schematic of the device structure simulated in NanoMOS is shown in Figure 3.7.

To study the impact of quantum effect on subthreshold SCEs, NanoMOS simulations have been performed while changing the effective masses, in order to artificially modify the strength of quantization by:

• increasing the subband splitting through the decrease of the confinement effective mass, • reducing the DOS in the conduction band through the decrease of the density of state effective mass [START_REF] Takagi | Sub-band structure engineering for advanced CMOS channels[END_REF], and

• dark space variation These effects will therefore highlight any dependency of SCEs with quantum confinement and especially of the dark space [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] O'regan | Calculation of the capacitance-voltage characteristic of GaAs, In 0.53 Ga 0.47 As, and InAs metal-oxide-semiconductor structures[END_REF][START_REF] Rafhay | Impact of channel orientation on ballistic current of nDGFETs with alternative channel materials[END_REF].

Simulation Results

The devices considered in this section are template double gate MOSFETs with a 5 nm film thickness, 1 nm EOT and 10 nm source/drain length. The device parameters are listed in Table 3.1. To avoid any confusion with the increase of subthreshold slope due to the SCEs, source-to-drain tunneling has been ignored by using the Drift-Diffusion model for carrier transport. Three gate lengths (L g ) have been considered: 10, 15 and 20 nm and, as explained, the density of state effective mass of the channel material has been varied from 0.05m 0 to 1m 0 . The carrier mobilites have been kept fixed as in the template MOSFET with Si channel during the simulations as it is not a factor in studying the relative subthreshold performance of the device and we are not concerned with exact values of drain currents in the simulated devices. For the same reasons, channel/gate oxide interface states are also neglected. The obtained DIBL and subthreshold slope are shown in Figure 3.8.

Contrary to [START_REF] Wu | Impact of quantum confinement on short-channel effects for ultrathin-body germanium-oninsulator MOSFETs[END_REF][START_REF] Yu | Impact of quantum confinement on subthreshold swing and electrostatic integrity of ultra-thin-body GeOI and InGaAs-OI n-MOSFETs[END_REF], who argued that quantization does affect the SCEs in subthreshold regime, the results obtained here with NanoMOS do not show any modification of the DIBL or the subthreshold slope when the density of states effective mass is changed. These results have also been obtained when considering different values of the confinement effective mass, which mainly influence the value of the long channel threshold voltage, but do not modify the subthreshold slope or the DIBL. Therefore, neither the subband splitting induced by the reduction of the confinement effective mass, nor the increase of dark space induced by reduced DOS effective mass modifies the SCEs. In the weak inversion regime, the channel potential is hence still mostly controlled by geometry, the built-in potentials and the depletion charges.

Impact of Material Parameters

Classical simulation can therefore correctly capture the SCEs. To illustrate further the impact of the channel material parameters on the short channel effects, the double gate devices have been simulated with varying energy bandgaps and varying dielectric constants, by self-consistently computing the Poisson and Drift-Diffusion equations using FlexPDE. These double gate devices feature a film thickness (t sc ) of 5 nm and an EOT of 1 nm. The same three gate lengths (10, 15 and 20 nm) have been simulated.

The DIBL and subthreshold slope have been firstly extracted for varying values of bandgap, as the channel potential profile depends on the built-in potential between the source/drain and channel pn junctions, and hence on E g [START_REF] Skotnicki | The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects[END_REF][START_REF] Batail | Impact of scaling on electrostatics of germanium-channel MOSFETanalytical study[END_REF]. These results are shown in Figure 3.9 and compared with the results obtained from the analytical model presented in [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF]. It can be seen from Figure 3.9 that the subthreshold slope of the double gate device is independent of the bandgap value of the semiconductor. Results obtained by simulation and the model have been found to be in agreement, without fitting procedures. DIBL however seems to be a weak function of the bandgap, mostly in devices featuring large SCEs (e.g. L g = 10 nm and t sc = 5 nm). The discrepancy between the model and the simulations becomes larger for values of L g /t sc smaller than 2, which correspond to the limit of validity of the model [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF].

Similar simulations have been performed for varying dielectric constants of the channel material. The DIBL and subthreshold slope obtained from these simulations are plotted in Figure 3.10, which shows, as expected that DIBL and subthreshold slope are much stronger functions of the dielectric constant [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] than of the bandgap. Both DIBL and subthreshold slope significantly increase when the dielectric constant ε sc goes from 12ε 0 (∼ ε Si ) to 17ε 0 (∼ ε InSb ). These results are also in agreement with the model proposed in [START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF] and the simulation results. It confirms that the main cause of short channel effect increase in III-V technologies is related to their larger dielectric constants.

DIBL in Strong Inversion Regime

Effective current and DIBL

Conventionally, in the expression for gate delay CV /I, the current is taken to be the on-current, I on = I D (V g = V d = V DD ). However, the current never reaches I on during the switching process, and it has been argued that it is necessary to take into account the linear characteristics of the device in addition to the saturation current for circuit speed calculations [START_REF] Ng | Effective on-current of MOSFETs for large-signal speed consideration[END_REF]. It has been shown [START_REF] Na | The effective drive current in CMOS inverters[END_REF] that using an "effective on current", I ef f instead of I on leads to more accurate estimation of CMOS inverter delays. I ef f is given by:

I ef f = (I L + I H ) /2 where (3.
2)

I L = I d (V g = V DD /2, V d = V DD ) and (3.3
)

I H = I d (V g = V DD , V d = V DD /2) (3.4)
Even at the same I on and I of f , a technology with higher DIBL will result (Taken from [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF])

in lesser I ef f [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF]. Figure 3.11 explains this graphically using the switching trajectories for two devices having different DIBLs. DIBL and the switching frequency (f = I ef f /CV ) can be roughly related as [START_REF] Skotnicki | How can high mobility channel materials boost or degrade performance in advanced CMOS[END_REF]:

∆f f = ∆I ef f I ef f = - 2∆DIBL V DD -V t (3.5)
It implies that a higher DIBL translates to lower I ef f and hence lower switching frequency.

Dark space and DIBL in strong inversion

The previous section has confirmed that the confined minority carriers could be neglected when solving the Poisson equation in subthreshold regime. However, in the inversion regime, the inversion charge has to be taken into account in the Poisson's equation, and hence quantum effects should be included. Besides, the DIBL is also known to be a function of the oxide thickness. In subthreshold condition and using the Voltage-Doping Transformation model [START_REF] Skotnicki | The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects[END_REF][START_REF] Batail | Impact of scaling on electrostatics of germanium-channel MOSFETanalytical study[END_REF], the DIBL can be simply reduced to:

DIBL = t ox 4qN a ε sc φ f ε ox ε sc qN a L 2 g (3.6)
where N a is the channel doping concentration, 2φ f the surface potential at threshold, q the elementary charge, ε sc and ε ox the silicon and oxide dielectric constant, L g the gate length, and t ox the EOT. The DIBL may hence be impacted by the dark space, which increases the effective t ox in strong inversion.

Next, subsection 3.4.3 will first present a definition and an extraction method for the DIBL in the strong inversion regime. Then, subsection subsection 3.4.4 will use this definition and extraction method to study the impact of quantization on the DIBL in strong inversion.

Definition and extraction method of the DIBL in strong inversion regime

V DIBL t (V d ) = V t -λV d (3.7)
where V d is the drain voltage, V t the threshold voltage at low V d , V DIBL of I d -V g curves obtained for two drain voltages. This extraction procedure is no longer relevant in strong inversion regime. One way to generalize the extraction of DIBL to all regimes is to use the approach presented in [START_REF] Ghibaudo | Critical MOSFET operation for low voltage/low power ICs: Ideal characteristics, parameter extraction, electrical noise and RTS fluctuations[END_REF][START_REF] Fikry | Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs[END_REF], which extends the conventional definition of the DIBL given by equation (3.7). This extraction method is based on the parasitic increase of the drain current related to the drain voltage variation.

As shown in Figure 3.13, the increase of current δI d resulting from the increase of drain voltage δV d is equal to the product of the transconductance δI d /δV g and the shift in gate voltage λδV d . Hence, λ can be defined as:

λ = δI d δV d δI d δV g = g d g m (3.8)
where g d is the conductance and g m , the transconductance. Equation (3.8) hence enables an extraction of the DIBL, not only in subthreshold regime, but in all regimes, either from measurements or simulations results. Moreover, it is easy to show that the calculated value in subthreshold regime coincides with the value of the conventional DIBL. m as a function of the gate voltage, for different drain current (higher than the saturation current) obtained from simulation of a double gate MOSFET using the Drift Diffusion transport model, featuring an EOT of 0.7 nm, a 5 nm thick silicon channel and a gate length of 20 nm. It can be seen that the extracted DIBL from g d /g m is indeed constant in the subthreshold regime but that its value increases in the strong inversion regime. In addition, a increase of g d /g m for increasing value of V d (higher than the saturation drain voltage) is also obtained from the drift diffusion simulation.

Gate voltage

δI d d g I V ∂ ∂ λ•δV d Drain Current d d d d g m g I I V V g ∂ ∂ λ = = ∂ ∂

Impact of quantum effects and dark space on the

DIBL in inversion

Equation (3.6) shows, with a simple model, that the subthreshold DIBL is a linear function of the oxide thickness. However, in strong inversion regime and in presence of quantum confinement, the equivalent oxide thickness is increased with respect to the physical oxide thickness t ox , by a value called the dark space [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] O'regan | Calculation of the capacitance-voltage characteristic of GaAs, In 0.53 Ga 0.47 As, and InAs metal-oxide-semiconductor structures[END_REF][START_REF] Rafhay | Impact of channel orientation on ballistic current of nDGFETs with alternative channel materials[END_REF], which is induced by the displacement of the charge centroid away from the insulator/semiconductor interface [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF] and by the reduction of the density of state due to the presence of subband level [START_REF] Pal | Influence of bandstructure and channel structure on the inversion layer capacitance of Si and GaAs MOSFETs[END_REF]. This dark space is generally in the order of 3 Å in Si, but larger in the case of III-V semiconductors, as obtained by quantum simulation in [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] O'regan | Calculation of the capacitance-voltage characteristic of GaAs, In 0.53 Ga 0.47 As, and InAs metal-oxide-semiconductor structures[END_REF]. Therefore, quantum effects may have an impact on DIBL in the strong inversion regime.

To clarify that point, two sets of simulation have been performed. The first set of simulations have been carried out using quantum corrected Drift Diffusion simulations in FlexPDE, while the second set have been carried out with the NanoMOS suite with the Drift Diffusion model. In the quantum corrected numerical simulations, the Hansch model [START_REF] Hansch | Carrier transport near the Si/SiO 2 interface of a MOSFET[END_REF] has been implemented as a first order quantum correction, in order to mimic the displacement of the charge centroid. Although not being able to fully capture the carrier quantum degeneracy as well as Poisson-Schrödinger calculation, the Hansch model manages to introduce an apparent additional oxide thickness in strong inversion as in the quantum case. In addition, the dark space obtained with the Hansch model can be easily tuned, by simply changing the value of Hansch's length [START_REF] Hansch | Carrier transport near the Si/SiO 2 interface of a MOSFET[END_REF] in:

n H (x) = n 0 (x) 1 -exp - x L H 1 -exp - t Si -x L H (3.9)
where n H (x) is the corrected charge profile, n 0 (x) the classical profile, t Si the semiconductor film thickness and L H , the Hansch's length. On the contrary, the NanoMOS simulator rigorously accounts for quantum degeneracy, but the value of dark space can only be indirectly tuned through the variation of the density of state effective mass. Therefore, at first, quantum corrected drift diffusion simulation of an FD-SOI MOSFET has been performed with different L H to extract λ using equation (3.8). Figure 3.15 shows the corresponding extracted DIBL, λ as a function of the gate voltage, for three different Hansch's length (L H = 1, 2 and 4 nm). It can be seen that in subthreshold regime, λ is unchanged, as the total charge is fixed by the geometry, the depletion charge. In strong inversion regime, on the contrary, L H increases the value of λ, thus indicating that the DIBL is a function of the dark space, which depends, in this model, on Hansch's length.

To investigate further this effect with a more accurate treatment of quantum confinement and transport, the NanoMOS simulation suit has then been used to compute λ in double gate MOSFETs, featuring 10 nm gate length, 5 nm film thickness and 0.7 nm EOT. In this case also, the density of state effective mass has been varied to change the strength of the quantum confinement. The drift diffusion transport model coupled with Poisson-Schrödinger solution of the charge has been used with a constant mobility, in order to avoid the impact of the effective mass on carrier transport, normally included in the two other transport model [71]. Two effective masses have then been used (0.1m 0 and 1m 0 ) to artificially emulate two different dark spaces in these devices. These different dark spaces consequently lead to the I d -V g characteristics shown in Figure 3.16, which present a more degraded coupling in the case of the 0.1m 0 simulation than in the case of the 1m 0 one. As no absolute extraction of the dark space is possible with the NanoMOS suite, the impact of varying dark space is evidenced by plotting the ratio of the drain current for m d = 0.1m 0 to the drain current for m d = 1.0m 0 (I d0.1m 0 /I d1m 0 ). This ratio, plotted in Figure 3.17, hence corresponds to the dark space increase of m d = 0.1m 0 with respect to the dark space for m d = 1m 0 .

The λ obtained with m d = 0.1m 0 and m d = 1m 0 have been calculated using the resulting I d (V g , V d ) characteristics and equation (3.7). The same trend as in Figure 3.15 has been obtained, i.e. λ has been found to be larger for m d = 0.1m 0 than for m d = 1m 0 , confirming that the larger dark space induced larger λ in the inversion regime.

As λ is expected to be proportional to t ox , while the drain current I d in the linear regime is inversely proportional to t ox , the ratio λ 1.0m 0 /λ 0.1m 0 as been

Ratio of drain currents and ratio of λ

Gate voltage overdrive V g -V t (V)

Ratio of drain current Ratio of λ Figure 3.17: Ratio of the drain current and ratio of DIBL as a function of the gate voltage overdrive. The noise in the simulation is due to the multiple ratios and derivatives required to obtain λ 1.0m 0 /λ 0.1m 0 plotted in Figure 3.17 and compared to the ratio I d0.1m 0 /I d1.0m 0 . It can be seen that λ 1.0m 0 /λ 0.1m 0 follows the trend of I d0.1m 0 /I d1.0m 0 , thus confirming that λ is increased in presence of quantization in the same extent than the drain current degradation due to quantum confinement and increased dark space. This result therefore shows that a part of the DIBL in the strong inversion regime, defined by λ, is due to the presence dark space and quantum confinement and that the larger dark spaces obtained in the case of III-V MOSFETs [START_REF] Rafhay | Dark space, quantum capacitance and inversion capacitance in Si, Ge, GaAs and In 0.53 Ga 0.47 As nMOS capacitors[END_REF][START_REF] Pal | Influence of bandstructure and channel structure on the inversion layer capacitance of Si and GaAs MOSFETs[END_REF] may cause further enhancement of the DIBL in the strong inversion regime compared to silicon devices.

Impact of the architecture on the SCEs

The different architectures of III-V MOSFETs have been discussed in Chapter 1. The impact of different architectures on SCEs needs to be evaluated to determine their worthiness.

Impact of barrier layers: QWFET Vs thin films

As discussed in the introduction section, III-V heterostructure devices, also called Quantum Well FETs have attracted a lot of attention(for example [START_REF] Radosavljevic | Advanced high-k gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications[END_REF]). All the proposed QWFET architectures include III-V barrier layers (generally InP) on top of the channel (often In x Ga 1-x As). The wide band gap barrier layers are required for carrier confinement in the lower band gap quantum well, to limit mobility degradation due to interface defects [START_REF] Zhao | Factors enhancing In 0.7 Ga 0.3 As MOSFETs and tunneling FETs device performance[END_REF][START_REF] Nagaiah | Mobility and remote scattering in buried InGaAs quantum well channels with high-k gate oxide[END_REF] and also for reducing junction leakage and off-state leakage currents. In this section the impact of the barrier layer above the channel is explored.

A simplified structure of such category of mulitlayered MOSFET structures is illustrated in Figure 3.18. This section examines the impact of this barrier layer on the SCEs of III-V QWFETs. thin enough with respect to the channel thickness, no charge was transferred from the channel to the barrier under reasonable bias conditions. Hence, the barrier layer could be simply considered as an additional dielectric layer.

To illustrate the impact of this layer, the DIBL has been reported as a function of the dielectric constant of the barrier material in Figure 3.19(a), for two gate lengths (15 and 20 nm) and for two barrier thicknesses (5 and 2 nm). It can be seen that, as expected, the DIBL is increased in the presence of a barrier layer and that thinner barrier layer would lead to weaker DIBL. For larger dielectric constant and thinner barrier layer, the DIBL is reduced and the equivalent oxide thickness of the barrier stack is essentially independent of the barrier layer thickness. However, the previous results have been obtained by applying Neumann boundary conditions to the barrier layer, as in the case of conventional dielectric layer. In fact, the potential on the left and right side of the barrier layer is set by the source and drain voltage, and the S/D boundary condition should rather be of Dirichlet type. The difference between these two types of boundary condition is reported in Figure 3. 19(b), which also plots the DIBL as a function of barrier dielectric constant (T bar = 2 nm). It can be seen that the DIBL is increased by when Dirichlet boundary condition are used, which means that SCEs are degraded when the barrier layer is in contact with the source and drain. In addition, an increase of barrier dielectric constant slightly increases DIBL, which shows that the drain voltage and the channel potential are in fact coupled by the barrier layer, hence acting as a fringing capacitor. Therefore, the barrier layer of the QWFET architecture not only increases DIBL by increasing the EOT, but also due to fringing capacitance.

Leakages in Nanoscale MOSFETs

Maintaing a high I on /I of f ratio is essential while miniaturising transistors. Different leakage mechanisms contribute to the off current in a MOSFET which can be categorized as follows

• Source to Drain Leakage: It consists of the off state currents along the lateral direction along the channel:

-Thermionic Current: Electrons in the source side with thermal energy greater than the potential barrier can escape into drain region.

-Subthreshold Leakage: It is the diffusion current in the channel due to minority carriers when the applied gate voltage is less than the threshold voltage, V g < V t , increasing exponentially with V g . It is enhanced by the drain induced barrier lowering effect (DIBL) as the drain voltage is increased.

-BTBT (Band to Band Tunneling): It is caused due to the electrons tunneling from the valence band to the conduction band (or vice versa).

-SDT (Source to Drain Tunneling): It is the direct tunneling of the conduction band electrons in the source to the drain through the channel potential barrier. This has been discussed in detail in the next section.

-GIDL (Gate Induced Drain Leakage): It occurs when the gate is biased at zero or negative voltage and drain bias, V D is high creating a high-field p + -n + junction at the gate/drain overlap region and electrons can tunnel across it through mechanisms of band to band tunneling and trap assisted tunneling, leading to increased drain current and its impact can be seens as observed the upward bending of I d -V g curves below threshold [85] [86]. • Gate leakage: It consists of leakage currents in the gate-to-channel direction.

-Fowler-Nordheim Tunneling: Tunneling of electrons from the channel into the gate oxide layer through a triangular barrier -Direct Tunneling: It takes place in very thin oxide layers (when t ox is less than 3-4 nm) and the electrons tunnel directly into the gate region through the forbidden energy gap of the oxide layer.

-Hot carrier Injection: If the electric field at channel/gate oxide layer interface is too high, electrons can gain enough energy to cross above the potential barrier from substrate to gate insulator [START_REF] Taur | Fundamentals of Modern VLSI Devices[END_REF]. In the previous chapters, where the goal was to focus mainly on the electrostatics and quantum confinement effects in the perpendicular direction to the channel, source-to-drain leakage currents were ignored. But since in short channel devices source drain leakage plays an important role by tunneling mechanisms, it is important to evaluate its impact on the short channel effects and explore if source-to-drain tunneling can set the scaling limit for Si and ACM devices. In this chapter the impact of the source-to-drain tunneling is studied, without taking into account any gate leakages.

n + Gate Oxide p substrate E C E C E V E v e E C E C E V e E V

Source to Drain Tunneling

As the MOSFET gate lengths get smaller with each new technology generation, due to increased proximity of the source and drain regions, quantum mechanical tunneling of carriers from source to the drain starts to play a significant role in the off state leakage and is a possible determinant of the ultimate transistor scaling limits [88] [89]. This source drain tunneling through the channel barrier can be a lot more detrimental in MOSFETs with alternative channel materials like III-V compounds as they have smaller effective masses, leading to higher off currents and poor switching characteristics.

The WKB approximation

The Wentzel-Kramers-Brillouin (WKB) approximation is a way to find an approximate solution to the time independent Schrödinger equation [START_REF] Ferry | Quantum Mechanics: An Introduction for Device Physicists and Electrical Engineers[END_REF]. The tunneling through a barrier can be described using the tunneling probability or transparency obtained using the WKB method as given by:

T (E x ) = exp -2 x 2 x 1 2m * (E barrier (x) -E x ) dx (4.1)
where m * is the effective mass of the electron, E barrier (x) is the channel potential energy barrier between source and drain, E x is the electron energy with E barrier (x) > E x in the tunnel region as shown in Figure 4.3. x 1 and x 2 are the classical turning points ( E barrier (x) = E x at x = x 1 , x 2 ).

From first order perspectives, it can be readily predicted from (4.1) that a lighter effective mass corresponds to a higher value of the transparency and hence increased source-drain tunneling.

Effective barrier size modulation

As the gate length is reduced, the effective barrier width reduces and hence the source drain tunneling current increases. As shown in Figure 4.4 the effective barrier width is found to reduce with increased channel thicknesses. So thicker devices have increased tunneling. So this puts further constraint on the t sc requirement to be made thinner, than simply worsened electrostatics. Also, this narrowing of the channel barrier is also dependant on the applied drain bias. Higher drain voltage causes more thinning of the barrier along with its lowering (DIBL) as the conduction band is pulled down with increased drain voltage is pulled down as depicted in Figure 4.5 for an InSb device with 10 nm long gate and 2 nm thick channel. As a result the SD tunneling is expected to increase because of this two fold effect of DIBL. (L g =10 nm, t sc =2 nm, 4 nm, V d =0.1 V, 0.2 V, 0.5 V, 0.8 V)

Source Drain Tunneling and ACM

Simulations have been performed for different channel materials by varying their effective masses and dielectric constants, once including and then excluding source-to-drain quantum tunneling by using different transport models in NanoMOS, while keeping other parameters the same. In the following simulations, the devices considered are double gate MOSFETs as in the previous chapters. In [START_REF] Wang | Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?[END_REF] it was shown that S/D tunneling is negligible in devices with channel lengths greater than 10 nm for a Si device. In this study it is intended to find if the same holds true for alternative channel material MOS-FETs. Ballistic transport has been assumed in the devices using the NEGF approach. The narrowing of the potential barrier for different materials is shown in Figure 4.6. It is seen that the narrowing of the barrier is more for channel materials with lighter masses. Hence the SD tunneling is expected to be more in case of III-V devices.

In the simulations carried out in this section, the first ballistic transport model includes quantum confinement in the vertical direction by solving the one dimensional Schrödinger equation. And the carrier transport in each resulting subbands is then calculated using thermionic component only while ignoring any tunneling [71]. In the second ballistic transport model, the carrier transport is evaluated in each of the subbands by solving another set of one dimensional Schrödinger equation in the channel direction using the nonequilibrium Green's function (NEGF). In the latter model, the source-to-drain tunneling is accounted for.

The following channel materials were considered: Si, GaAs, InGaAs, InAs and InSb. Simulations are carried out for three channel thicknesses of 2, 3 and 4 nm and different channel lengths, ranging from 7 nm to 40 nm. The expected increased BTBT in these low bandgap devices can be compensated by using optimized architectures and the use of thin channels where quantum confinement leads to widening of the band gaps [START_REF] Krishnamohan | High-mobility low band-to-band-tunneling strainedgermanium double-gate heterostructure fets: Simulations[END_REF], and have been neglected in the following simulations for simplicity. The channel-source/drain junctions are considered abrupt as in previous chapters of this thesis. Subthreshold slope variation in MOSFETs with different channel materials has been plotted in Figure 4.7 without considering source-to-drain tunneling, and in Figure 4.8, including source-to-drain tunneling. As already described in chapter 3, when S/D tunneling is ignored, the vertical quantum confinement alone does not alter the subthreshold slope and hence curves in Figure 4.7 are seen to huddle together. On the contrary, when S/D tunneling is taken into account, it is seen that the subthreshold slopes degrade rapidly with decreasing effective mass and increasing dielectric constant as we go from a silicon device to an InSb device.

It can also be seen that the subthreshold slopes of GaAs and InGaAs based MOSFETs deviate from the Si values at gate lengths around 15 and 20 nm respectively, while for other channel materials with lighter effective masses this length is well above 20 nm. So while SD tunneling is not a critical factor for Si devices for gate lengths larger than 10 nm, as has been reported in published literature, for example [START_REF] Wang | Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?[END_REF], it can cripple device operation at fairly large gate lengths if the channel material is changed to be Ge or a III-V material.

Figure 4.9 shows the variation of subthreshold slope with the channel thickness for devices with 10 nm gate lengths for the five different materials. It is seen that even with extreme geometries like t sc =2 nm and L g =10 nm which guarantee a good electrostatic control by the gate, SD tunneling is very damaging and leads to rapid degradation of the subthreshold slope in alternative channel materials.

Quantum Confinement and SDT

Confinement effective masses depend on crystal orientation as well as the thickness of the MOSFET channel. In the previous analyses, the effective masses used were that of the bulk semiconductors. However, it is known that an increase in the transport effective mass in thin semiconductor films is found compared to bulk material and this effect is observed more as channel thickness (t sc ) is scaled thinner and thinner. Using a tight binding approach, Liu et. al [START_REF] Liu | A tightbinding study of the ballistic injection velocity for ultrathin-body soi mosfets[END_REF] have shown that in Si, although not much significant, this increase has been found to be around 10% for a 3 nm thick channel, causing m t to rise to 0.22m 0 from 0.19m 0 . Figure 4.10 shows the variation of the transport effective mass, m t with the silicon channel thickness. In III-V materials this effect is much more pronounced due to the strong non-parabolicity of the Γ valley [START_REF] Cantley | Performance analysis of III-V materials in a double-gate nano-MOSFET[END_REF][START_REF] Liu | Band-structure effects on the performance of III-V ultrathin-body SOI MOSFETs[END_REF][START_REF] Zhu | Modeling study of InSb thin film for advanced III-V MOSFET applications[END_REF][START_REF] Pal | NEGF analysis of InGaAs schottky barrier double gate MOSFETs[END_REF]. For example, it has been demonstrated in [START_REF] Liu | Band-structure effects on the performance of III-V ultrathin-body SOI MOSFETs[END_REF], the effective mass model with parabolic bandstructure utilising the bulk effective mass is not valid in cases of strong quantum confinement, and full band calculations reported significant increase of the effective mass with channel thickness scaling. The increase in the confinement effective mass in the Γ valley of GaAs and InAs as a function of the body thickness is plotted in Figure 4.11 (taken from [START_REF] Liu | Band-structure effects on the performance of III-V ultrathin-body SOI MOSFETs[END_REF]). Table 4.1 displays the efffective masses in bulk and in a semiconductor body with 3 nm thickness.

While increased effective masses of electrons can reduce the injection velocity and hence the on current, it can also help reduce the leakage current by reducing the tunneling transparency. Its impact on the SD tunneling leakage was hence studied to assess how this increase in the effective mass affects scalability in terms of the gate length. For this, a critical length is proposed to quantify the impact of tunneling. The critical gate length, L crit has been defined as the gate length at which the subthreshold slope worsens by 2% due to source-to-drain tunneling.

Further simulations were carried out with the increased masses listed in Table 4.

Conclusions

The impact of source-to-drain tunneling is more severe in III-V MOSFETs than in Si devices. The channels with lower effective mass materials have worse subthreshold slopes. And this behaviour with different effective masses is displayed at longer gate lengths in III-V devices than expected in Si devices. Thus source-to-drain tunneling makes the devices with high mobility materials like III-V and Ge less scalable than a Si device, causing less aggressive shrinking of gate lengths along the roadmap beyond the 15-20 nm technology nodes. In other words, III-V devices can achieve higher on current and comparable short channel performance compared to a Si device only when the channel lengths are larger than the critical lengths.

Finally, when the increase in the effective masses with channel thickness scaling is taken into account, an improvement in the critical gate lengths is found, signalling a more optimistic scenario compared to the cases where bulk effective masses are used in the simulations.

Conclusions

In this PhD thesis, the current state of non silicon channel MOS devices was ascertained through extensive literature survey, and then the short channel behaviour of these devices was explored via modeling and simulation. We began by providing a correction to the boundary conditions as applied in conventional potenial modeling schemes in MOSFETs. In the existing modeling approaches, the voltage drops in source and drain regions are ignored. It was found that this can lead to huge over-estimation of SCEs. To correct this, a model for an effective built-in potential was proposed, which when applied to the conventional models, is able to account for the impact of source and drain regions on the channel potential and hence the SCEs. III-V devices display worse short channel behaviour than their silicon counterparts. The main focus of this dissertation work was on understanding the origin of the short channel effects (subthreshold slopes and drain induced barrier lowering). It was found that the quantum confinement does not have any impact on the SCEs, as long as tunneling leakages are neglected in the analysis. The detorioration in SCEs is mainly due to the worsened electrostatics of the short channel devices. Higher dielectric constants and smaller bandgaps are accountable for the SCE degradation. The off-state characteristics of the devices are not affected by quantum effects, and hence classical simulations are able to capture them. However, in the strong inversion regime of the device where the minority carriers are taken into account, quantum effects have to be considered. The increased dark space (due to smaller effective mass) in III-V devices results in an increase in the effective oxide thickness, which in turn increases the DIBL effect in the on-state. This was concluded using both quantum simulations with DD transport as well as DD simulations with quantum corrected charge profile using the Hansch model.

Simulations clearly showed that increased dielectric constant leads to an increase in the DIBL and the subthreshold slope, and that the DIBL is a weak function of the material's bandgap. Thus this part of the research work showed that the SCE degradation is very fundamental to III-V devices and is ascribed to their higher dielectric constants and smaller effective masses. Also, the incorporation of barrier layers in QWFET architecture was shown to cause further degradation of the SCEs.

In the final part of the thesis, the goal was to investigate the impact of the source-to-drain tunneling on the SCEs in III-V devices and predict the critical gate lengths at which its inclusion leads to significant difference compared to the case where tunneling is ignored. The impact of the increase of the effective mass due to carrier confinement in ultra thin films is also studied and it was concluded that the source-to-drain tunneling causes further degradation in the SCEs, but when the increased effective masses are used for calculations, we have more leeway and the scalability is not as bad as predicted when calculations are performed by taking the bulk effective masses instead. Thus, to take advantage of the excellent transport properties of III-V/Ge materials, it is imperative to control the loss in terms of short channel effects. Hence device structures that offer tighter gate control, like the triple gate and gate all around/nanowire MOSFETs are good candidates for the introduction of alternative channel materials.

Future Perspectives

Some suggested future works are as follows:

• The impact of the quantum confinement and material parameters on

the threshold voltage roll-off in III-V devices can be pursued to get a more complete picture of SCE degradation.

• The on-state performace is impacted by the DIBL deterioration as demonstrated in this work. Its effect on the transistor delays can be studied to get some insights into circuit design issues that can come up with alternative channel material MOSFETs.

• The study can be repeated for III-V devices in different multi gate architectures other than the double gate: e.g. triple gate, Ω-gate, nanowire structures etc and quantify the advantages of better electrostatic control in such devices.

• While in this thesis the dielectric/channel interface imperfections were ignored, the inclusion of such non-idealities in the analysis can be done to see how much do they impact the device performance.

• Finally, comparison of the results of modeling and simulation results needs to be done with experimentally measured values.

Figure

  Figure 1.1 Simplified MOSFET Structure . . . . . . . . . . . .

1 . 1

 11 Figure 1.1 Simplified MOSFET Structure . . . . . . . . . . . .

Figure 1 . 2

 12 Figure 1.2 Tradeoff factors among on-current (I on ), power consumption (P DD )/leakage current(I of f ), and SCEs under simple device scaling and possible solutions to mitigate the issues. . . . . . . . . . . . . . . . .

Figure 1 . 3

 13 Figure 1.3 The steep increase of CPU power density in the previous generations has now somewhat saturated around 100 W cm -2 with the introduction of multicore CPUs . . . . . . . . . . . . . . . . . . . . . . .

Figure 1 . 4 Figure 1 . 5

 1415 Figure 1.4 Schematic representing the impact of short channel effects on the I d -V g characteristics of an nMOSFET Figure 1.5 Demonstration of DIBL . . . . . . . . . . . . . . .

Figure 1 . 6

 16 Figure 1.6 Technology Boosters: Strain and High-κ Metal Gate Figure 1.7 PIDS (Process Integration, Devices, and Structures) Projection, ITRS 2011 . . . . . . . . . . . . . . . .

Figure 1 . 8 FDSOI

 18 Figure 1.8 FDSOI MOSFET Structure . . . . . . . . . . . . .

Figure 1 . 9

 19 Figure 1.9 Double and Triple Gate FinFET Structures . . . .

Figure 1 . 10

 110 Figure 1.10 Number of publications concerned with III-V MOS-FETs in IEEE TED and EDL . . . . . . . . . . . .

Figure 1 . 11

 111 Figure 1.11 Band structure of InGaAs . . . . . . . . . . . . . .

Figure 1 . 12

 112 Figure 1.12 Schematic cross section of an In 0.53 Ga 0.47 As inversion mode MOSFET with TiN metal gate and Al 2 O 3 /Ga 2 O 3 (Gd 2 O 3 ) dual-layer dielectric . . . . . . . .

Figure 1 . 13

 113 Figure 1.13 Schematic of an In 0.53 Ga 0.47 As-channel inversion mode MOSFET with Gold-free ohmic contacts . . . . . .

Figure 1 .

 1 Figure 1.14 Cross-section of InP-based MOSFET with regrown extrinsic N+ InGaAs/InAs source and drain regions. The gate stripe extends a distance W g perpendicular to the figure. L g is the gate length, T ox the gate dielectric thickness, and T w the thickness of the In-GaAs/InP quantum well . . . . . . . . . . . . . . 17

Figure 1 . 18 Figure 1 . 16 19 Figure 1 20 Figure 1 Figure 2 . 1 25 Figure 2 33 Figure 2 . 3 35 Figure 2 . 4 35 Figure 2 . 5

 11811619120121252332335243525 Figure 1.15 Cross-sectional schematic illustration of an implantfree enhancement mode MOSFET . . . . . . . . . . 18 Figure 1.16 Schematic cross-sectional diagram of an enhancementmode In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As MOSFET with 7nm ALD Al 2 O 3 (short channel device) or 10 nm MBE HfO 2 (long-channel device) . . . . . . . . . . 19 Figure 1.17 Schematic of planar, thin body, High-κ/Metal Gate In 0.7 Ga 0.3 As MOSFET . . . . . . . . . . . . . . . . 20 Figure 1.18 Possibilities for heterogeneous integration of ACM devices (III-V/Ge) on Si . . . . . . . . . . . . . . . 21

Figure 2. 6

 6 Figure 2.6 DIBL and SS as functions of channel length with or without S/D, for two channel thicknesses (DD simulations) . . . . . . . . . . . . . . . . . . . . . .

Figure 2. 7

 7 Figure 2.7 Variation of V min with gate voltage, V g at fixed drain voltage (excluding S/D ). . . . . . . . . . . . . . .

Figure 2. 8

 8 Figure 2.8 Minimum of the channel potential as a function of gate voltage (the slope being the SS equivalent) for two different channel lengths in the two cases of with/without S/D inclusion . . . . . . . . . . . . .

Figure 2. 9

 9 Figure 2.9∆V min is the difference in the minimum channel potentials at V d =0 V and V d =0.9 V (excluding S/D) .

Figure 2. 10 ∆V

 10 Figure 2.10 ∆V min per unit of ∆V d (DIBL equivalent) as a function of channel length, in two cases of with or without S/D inclusion, and two channel thicknesses, while solving only Poisson's equation . . . . . . . . . . .

Figure 2. 11

 11 Figure 2.11 Channel potential in three cases: S/D included with V bi , S/D excluded with V bi , and S/D excluded with V ef f bi , (V g = 0V ) . . . . . . . . . . . . . . . . . . . . Figure 2.12 Variation of DIBL and SS with channel length with different N d . . . . . . . . . . . . . . . . . . . . . .

Figure 2. 13

 13 Figure 2.13 Variation of ∆V bi with N d (m -3 ) for different channel materials . . . . . . . . . . . . . . . . . . . . . . .

Figure 2. 14 3 Figure 3 . 1

 14331 Figure 2.14 Comparison of SCEs obtained in the three cases: S/D included with V bi , S/D excluded with V bi, , and S/D excluded with V bi ef f . . . . . . . . . . . . . .

Figure 3 . 2

 32 Figure 3.2 SCEs as reported by Pethe et al. . . . . . . . . . .

Figure 3 . 3

 33 Figure 3.3 SCEs as reported by Tsormpatzoglou et al. . . . . .

Figure 3 . 4 53 Figure 3 . 5 54 Figure 3 . 6 56 Figure 3 . 7 56 Figure 3 . 8 58 Figure 3 . 9 60 Figure 3 60 Figure 3 . 11 61 Figure 3 . 12 63 Figure 3

 34533554365637563858396036031161312633 Figure 3.4 Evolution of the Effective Current, I ef f under impact of the different effects . . . . . . . . . . . . . . 53

Figure 1 . 2 :

 12 Figure 1.2: Tradeoff factors among on-current (I on ), power consumption (P DD )/leakage current(I of f ), and SCEs under simple device scaling and possiblesolutions to mitigate the issues. Taken from[START_REF] Takagi | Carriertransport-enhanced channel CMOS for improved power consumption and performance[END_REF]

Figure 1 . 3 :

 13 Figure 1.3: The steep increase of CPU power density in the previous generationshas now somewhat saturated around 100 W cm -2 with the introduction of multi-core CPUs[START_REF] Pop | Energy dissipation and transport in nanoscale devices[END_REF]

Figure 1 .

 1 4 summarizes the modifications of the I d -V g and I d -V d characteristics of a MOSFET induced by short channel effects. SCEs are usually investigated in subthreshold regime and are expressed in terms of the following quantities: • Subthreshold Slope (SS) : It is defined as the inverse slope of the log I d Vs V g curve. SS = dV g d log I d in mV/dec. SS increases with the shortening of the channel.

Figure 1 . 4 :

 14 Figure 1.4: Schematic representing the impact of short channel effects on the I d -V g characteristics of an nMOSFET

Figure 1 . 5 :

 15 Figure 1.5: Demonstration of DIBL: While the surface potential distribution in a longer channel double gate MOSFET (100 nm gate length) does not vary with the applied drain voltage, drain induced barrier lowering is observed in the shorter channel device with 15 nm gate length. (t Si = 5 nm, open symbols correspond to V d = 0.9 V, and curves without symbols represent the V d = 0 V case)

Figure 1 . 6 :

 16 Figure 1.6: Technology Boosters: Strain and High-κ Metal Gate. (Taken from [19])

Figure 1 .

 1 Figure 1.7 shows the ITRS future projection about different technological innovations in different stages of growth: research required, development underway, pre-production and further continuous improvement. As already discussed, in the last decade, the following technology innovations were successfully incorporated in the existing silicon process flow: enhanced mobility and high-field transport via strain, enhanced quasi-ballistic transport (via short gate length and strain), high-κ gate dielectric, metal gate electrode, and Fully depleted SOI MOSFET.

Figure 1 . 7 :

 17 Figure 1.7: PIDS (Process Integration, Devices, and Structures) Projection, ITRS 2011 [8]

Figure 1 . 9 :

 19 Figure 1.9: Double and Triple Gate FinFET Structures

Figure 1 . 10 :

 110 Figure 1.10: Number of publications concerned with III-V MOSFETs in IEEE TED and EDL

Figure 1 .Figure 1 . 11 :

 1111 Figure 1.11: Band structure of InGaAs [34]

Figure 1 . 12 :Figure 1 . 13 :

 112113 Figure 1.12: Schematic cross section of an In 0.53 Ga 0.47 As MOSFET with TiN metal gate and Al 2 O 3 /Ga 2 O 3 (Gd 2 O 3 ) dual-layer dielectric [36]

Figure 1 . 14 :

 114 Figure 1.14: Cross-section of InP-based MOSFET with regrown extrinsic N + InGaAs/InAs source and drain regions. The gate stripe extends a distance W g perpendicular to the figure. L g is the gate length, T ox the gate dielectric thickness,and T w the thickness of the InGaAs/InP quantum well[START_REF] Rodwell | Technology development & design for 22 nm InGaAs/InPchannel MOSFETs[END_REF]

Figure 1 .

 1 Figure 1.15: Left: Cross-sectional schematic illustration of an implant-free enhancement mode MOSFET. Ohmic-contact metal is deposited after gate-oxide removal, and the contacts are formed using conventional Ni/Ge/Au metallurgy. Right: Epitaxial-layer structure and energy-band diagram of an implant-free enhancement-mode MOSFET. δ-doped layers are placed at a certain distance below (bottom δ-doping) and/or above (top δ-doping) the In 0.3 Ga 0.7 As channel layer as indicated by dashed lines. A representative energy-band diagram is shown for thermal equilibrium and under flatband conditions for t ox = 18 nm and N s =2.4x10 12 cm -2 (n s = 2.3x10 12 cm -2 ). Taken from[START_REF] Passlack | Implantfree high-mobility flatband MOSFET: principles of operation[END_REF].

Figure 1 . 16 :

 116 Figure 1.16: Schematic cross-sectional diagram of an enhancement-mode In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As MOSFET with 7-nm ALD Al 2 O 3 (short channel device) or 10 nm MBE HfO 2 (long-channel device) [45]

Figure 1 . 18 :

 118 Figure 1.18: Possibilities for heterogeneous integration of ACM devices (III-V/Ge) on Si (Taken from [47])

Figure 2 . 1 :

 21 Figure 2.1: Device cross section with coordinate system

  e n t i a l ( V ) D i s t a n c e a l o n g t h e c h a n n e l ( n m )

Figure 2 . 3 :

 23 Figure 2.3: Comparison of the potential at the center and at the surface of the channel showing the agreement between numerical solution of 2D Poisson's equation and the analytical model(t Si =5 nm, V g =0.5 V, V d =0 V, V f b =0.2 V)

Figure 2 . 4 :

 24 Figure 2.4: Comparison of the minimum surface potential as a function of the channel length obtained using numerical solution of 2D Poisson's equation and the analytical model for three values of channel thickness. Solid curves correspond to the model and the symbols correspond to the numerical simulations.(V g =0.5 V, V d =0 V, V f b =0.2 V,t Si =5 nm, 7.5 nm, 10 nm)

Figure 2 . 5 :Figure 2 . 6 :

 2526 Figure 2.5: Boundary conditions applied to a MOSFET in two cases of analysis: including the S/D region and excluding the S/D region

Figure 2 .

 2 Figure 2.7 shows the potential distribution at different gate voltages and the movement of the minimum of the potential, V min . The value of V min , obtained with the same simulated devices, has been plotted as a function of the gate voltage in Figure 2.8. The variation of V min with V g can be seen as an indirect evaluation of the subthreshold slope.

Figure 2 . 7 :

 27 Figure 2.7: Variation of V min with gate voltage, V g at fixed drain voltage (excluding S/D ).

Figure 2 . 8 :

 28 Figure 2.8: Minimum of the channel potential as a function of gate voltage (the slope being the SS equivalent) for two different channel lengths in the two cases of with/without S/D inclusion

Figure 2 . 9 :

 29 Figure 2.9: ∆V min is the difference in the minimum channel potentials at V d =0V and V d =0.9 V (excluding S/D)

Figure 2 . 10 :

 210 Figure 2.10: ∆V min per unit of ∆V d (DIBL equivalent) as a function of channel length, in two cases of with or without S/D inclusion, and two channel thicknesses, while solving only Poisson's equation

Figure 2 . 11 :

 211 Figure 2.11: Channel potential in three cases: S/D included with V bi , S/D excluded with V bi , and S/D excluded with V ef f bi , (V g = 0V )

Figure 2 . 12 :

 212 Figure 2.12: Variation of DIBL and SS with channel length with different N d

. 13 .

 13 It can be seen that the ∆V bi increases with the N d , at the same rate

Figure 2 . 13 :

 213 Figure 2.13: Variation of ∆V bi with N d (m -3 ) for different channel materials

3 Figure 2 . 14 :

 3214 Figure 2.14: Comparison of SCEs obtained in the three cases: S/D included with V bi , S/D excluded with V bi, , and S/D excluded with V bi ef f

Contents 3 . 1 57 3. 3 59 3. 4 . 1 62 3. 4 . 3 65 3. 5 69 3. 5 . 1

 31573594162436556951 SCEs in III-V MOSFETs . . . . . . . . . . . . . . . . . . . . 49 3.2 Quantum Effects and SCEs in Subthreshold Regime . . . . . 53 3.2.1 Concept of Dark Space . . . . . . . . . . . . . . . . . 53 3.2.2 Simulation Methodology . . . . . . . . . . . . . . . . 55 3.2.3 Simulation Results . . . . . . . . . . . . . . . . . . . Impact of Material Parameters . . . . . . . . . . . . . . . . . 58 3.4 DIBL in Strong Inversion Regime . . . . . . . . . . . . . . . Effective current and DIBL . . . . . . . . . . . . . . 59 3.4.2 Dark space and DIBL in strong inversion . . . . . . . Definition and extraction method of the DIBL in strong inversion regime . . . . . . . . . . . . . . . . . . . . . 62 3.4.4 Impact of quantum effects and dark space on the DIBL in inversion . . . . . . . . . . . . . . . . . . . . . . . Impact of the architecture on the SCEs . . . . . . . . . . . . Impact of barrier layers: QWFET Vs thin films . . . 69

Figure 3 . 1 :

 31 Figure 3.1: SCEs in Ge and Si as reported by Batail et al. [68]

Figure 3 . 2 :

 32 Figure 3.2: SCEs as reported by Pethe et al.[START_REF] Pethe | Investigation of the performance limits of III-V doublegate n-MOSFETs[END_REF]

Figure 3 . 3 :Figure 3 . 4 :

 3334 Figure 3.3: SCEs as reported by Tsormpatzoglou et al. [51]

Figure 3 . 5 :

 35 Figure 3.5: Electronic charge density obtained using classical and quantum calculations for an inversion layer

D r a i n i n d u c e d b a r r i e r l o w e r i nFigure 3 . 8 :

 38 Figure 3.8: Drain induced barrier lowering and subthreshold slope as a function of the density of state effective mass, obtained with NanoMOS using the drift-diffusion model, for three different gate lengths (L g = 10, 15 and 20 nm) of double gate MOSFET featuring a channel thickness of 5 nm and an EOT of 1 nm.

Figure 3 . 9 :Figure 3 . 10 :

 39310 Figure 3.9: Drain induced barrier lowering (a) and subthreshold slope (b) as a function of the bandgap of the channel material, for three different gate length (L g = 10, 15 and 20 nm) of double gate MOSFET featuring a channel thickness of 5 nm and an EOT of 1 nm. Closed symbols correspond to classical simulation resultsand open symbols correspond to results obtained with the model presented in[START_REF] Tsormpatzoglou | Semi-analytical modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs[END_REF]

Figure 3 . 11 :

 311 Figure 3.11: Impact of the DIBL on effective current: Technology with higher DIBL (red dotted line) will have lesser I ef f than that with lower DIBL (blue dotted line)

Figure 3 .

 3 Figure 3.12 shows how DIBL affects the I d -V d curves in the saturation regime differently for a long and a short channel MOSFET. The conventional definition of DIBL is based on the threshold voltage shift induced by a drain voltage, as:

tFigure 3 . 12 :

 312 Figure 3.12: Schematic plot of the I d -V d characteristic for a long and a short channel MOSFET, showing the impact of DIBL on the saturation regime.

Figure 3 . 13 :S u b t h e s h o l d v a l u e o f t hFigure 3 . 14 :

 313314 Figure 3.13: Scheme of the impact of DIBL on the subthreshold I d -V g characteristics of an nMOSFET, illustrating the relation between the transconductance, the drain current current increased due to DIBL, and the corresponding gate voltage shift.

Figure 3 .

 3 Figure 3.14 shows such extraction of g d /g m as a function of the gate voltage, for different drain current (higher than the saturation current) obtained from simulation of a double gate MOSFET using the Drift Diffusion transport model, featuring an EOT of 0.7 nm, a 5 nm thick silicon channel and a gate length of 20 nm. It can be seen that the extracted DIBL from g d /g m is indeed constant in the subthreshold regime but that its value increases in the strong inversion regime. In addition, a increase of g d /g m for increasing value of V d (higher than the saturation drain voltage) is also obtained from the drift diffusion simulation.

Figure 3 . 15 :

 315 Figure 3.15: Generalized DIBL parameter λ as a function of the gate voltage, for three Hansch's lengths, obtained by quantum corrected drift diffusion simulation of FDSOI MOSFET, featuring a gate length of 20 nm, a film thickness of 10 nm and an EOT of 0.7 nm and a buried oxide thickness of 50 nm.

Figure 3 . 16 :

 316 Figure 3.16: I d -V g characteristics at V d = 10 mV, obtained with NanoMOS using the Drift Diffusion transport model, for two density of state effective masses inducing two different dark spaces.

Figure 3 . 18 :

 318 Figure 3.18: Simplified scheme of a heterostructure Quantum Well FET.

B a r r i e r l a y e r d i e l e c t r i c c o n s t a n t 1 LFigure 3 . 19 :

 1319 Figure 3.19: DIBL as a function of the barrier layer dielectric constant. (a) For different barrier thicknesses, using Neumann boundary condition. (b) for Dirichlet -correct (solid) boundary conditions and for Neumann -incorrect (open)

Figure 4 .

 4 Figure 4.1 shows the dominant leakage currents in the source-drain direction in a MOSFET that contribute to the net off state current.

Figure 4 .

 4 Figure 4.2 shows the first two types of gate tunneling mechanisms.

Figure 4 . 1 :

 41 Figure 4.1: Main leakage current mechanisms in the longitudinal direction of the device: subthreshold diffusion current, SD tunneling and BTBT )

Figure 4 . 2 :

 42 Figure 4.2: Gate Tunneling mechanisms in a MOSFET: (a) FN tunneling (b) Direct tunneling

Figure 4 . 3 :

 43 Figure 4.3: WKB Approximation

  t a n c e a l o n g t h e C h a n n e l ( n m ) t s c = 4 n m

Figure 4 . 4 :Figure 4 . 5 :

 4445 Figure 4.4: Reduction of the barrier width with increase in channel thickness.InSb channel device. L g =10 nm, t sc =2 nm, 4 nm), V d =0.01 V

Figure 4 . 6 :

 46 Figure 4.6: The narrowing of the potential barrier for two different materials: GaAs (red), InSb (blue) at two different channel thickness: 2 nm (closed symbols), 4 nm (open symbols)

Figure 4 . 7 :

 47 Figure 4.7: Subthreshold slope variation in MOSFETs with different channel materials, without considering source-to-drain tunneling (t sc = nm to ensure good electrostatics)

Figure 4 . 8 :

 48 Figure 4.8: Subthreshold slope variation in MOSFETs with different channel materials, including source to drain tunneling (t sc = 3 nm to ensure good electrostatics)

Figure 4 . 9 :

 49 Figure 4.9: Subthreshold slope variation with channel thickness in MOSFETs with different channel materials, with and without considering source to drain tunneling (L g = 10 nm)

Figure 4 . 10 :

 410 Figure 4.10: Variation of the transverse effective mass m t with the Si body thickness [92]

Figure 4 . 11 :

 411 Figure 4.11: Confinement effective mass of electrons in the Γ valley as a function of the channel thickness for GaAs and InAs double gate MOSFETs [93]

Figure 4 . 12 :

 412 Figure 4.12: Critical gate lengths (in nm) calculated with m * Bulk and m * T B

5 . 1

 51 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2 Future Perspectives . . . . . . . . . . . . . . . . . . . . . . . 89

Table 1 .

 1 1 ITRS Comparison of HP, LOP, LSTP and III-V/Ge Technologies . . . . . . . . . . . . . . . . . . . . . . Table 1.2 Physical properties of some Alternative Channel Materials at 300 K . . . . . . . . . . . . . . . . . . . .

Table 3 .

 3

1 Template MOSFET device parameters used in the NanoMOS simulations . . . . . . . . . . . . . . . . Table 4.1 Comparison of the bulk effective mass and the effective mass taking into account the quantum confinement, calculated using a tight binding approach for Si . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Criticial gate length (defined as the gate length at which inclusion of source to drain tunneling degrades the slope by 2%) for different channel materials . . Table 4.3 Criticial gate lengths (in nm) calculated with bulk effective mass and effective mass obtained from Tight Binding bandstructure calculations and the percentage improvement . . . . . . . . . . . . . . . . . . . Introduction Contents 1.1 State of the art in transistor industry . . . . . . . . . . . . . 1 1.1.1 Limits of scaling . . . . . . . . . . . . . . . . . . . . 2 1.1.2 Heterogeneous Scaling and Technology Boosters . . . 6 1.1.3 Possible Solutions in the Roadmap . . . . . . . . . . 9 1.2 III-V MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 Motivation for ACM/Why III-V? . . . . . . . . . . . 12 1.2.2 ACM Trade-offs . . . . . . . . . . . . . . . . . . . . . 13 1.2.3 Current Status of ACM Devices . . . . . . . . . . . . 15 1.3 Need to evaluate SCEs in III-V MOSFETs . . . . . . . . . . 21 1.4 Aim of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 Organization of the Thesis . . . . . . . . . . . . . . . . . . . 22

Table 1

 1

		HP LOP LSTP III-V/Ge
	Speed (I/CV)	1	0.5	0.25	1.5
	Dynamic Power(CV 2 ) 1	0.6	1	0.6
	Static Power(I off )	1 5x10 -2 1x10 -4	1
	.1: ITRS Comparison of HP, LOP, LSTP and III-V/Ge Technologies
	properties.

  / Si Ge GaAs In 0.53 Ga 0.47 As Table 1.2: Physical properties of some Alternative Channel Materials at 300 K (Taken from [34])

					InAs	InSb
	Property
	m * ef f	0.19 0.08 0.067	0.041	0.023	0.014
	µ n (cm 2 /V s) 1400 3900 8500	12,000	40,000 77,000
	µ h (cm 2 /V s) 450 1900	400	300	500	850
	E g (eV )	1.12 0.66 1.42	0.74	0.354	0.17
	ε r	11.7 16.2 12.9	13.9	15.15	16.8

Table 3 . 1 :

 31 Template MOSFET device parameters used in the NanoMOS simulations

Acknowledgements

Si GaAs InAs Bulk Effective Mass, m t,Bulk 0.2 0.067 0.023 Tight Binding Effective Mass, m t,T B 0.22 0.17 0.12 Table 4.1: Comparison of the bulk effective mass and the effective mass taking into account the quantum confinement, calculated using a tight binding approach for Si [START_REF] Liu | A tightbinding study of the ballistic injection velocity for ultrathin-body soi mosfets[END_REF], GaAs and InAs [START_REF] Liu | Band-structure effects on the performance of III-V ultrathin-body SOI MOSFETs[END_REF]. The comparison of the critical gate lengths obtained using bulk effective masses and the effective masses obtained from tight binding calculations available in existing literature, and the corresponding percentage decrease in the criticial length have been shown in Table 4.3. The critical gate length, L crit is found to decrease by 29% for GaAs and by 52% for InAs MOSFETs, thus enabling more physical scaling of channel length than that predicted by previous calculations using bulk effective masses. Figure 4.12 shows the result graphically.

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