S Guagliardo

Frédéric Wrobel

Ygor Quadros De Aguiar

Jean-Luc Autran

P Leroux

Frédéric Saigné

Vincent Pouget

Antoine D Touboul

Y Q Aguiar

Effect of Temperature on Single Event Latchup Sensitivity

Keywords: Single-Event Latchup, TCAD simulations, Cross section. I

ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

have investigated, considering a specific range of temperatures, how temperature affects the effect of each parameter. In order to achieve our goal, we have calculated SEL cross sections, following a 2D approach. As a result, more detailed information on the device SEL sensitivity are available. Beside the crosssection curves, it was also estimated the in-orbit SEL rate for GEO. The structure of the paper is the following: in Section II we explain the methodology used and in Section III how we performed TCAD simulations and how we calculated SEL cross section curves. In Section IV results are presented and discussed, and finally Section V includes our conclusions.

II. METHODOLOGY

As aforementioned, we have taken into consideration three parameters: doping profile of the whole structure, well and substrate taps placement and anode to cathode spacing (A-C spacing). Each parameter has been evaluated for a set of values and for a range of temperatures. Then, cross section has been calculated for every case. In order to achieve our goal, we have performed 2D TCAD simulations. Despite the threedimensional nature of the SEL mechanism, we decided to perform 2D simulations. In fact, it has been demonstrated that 3D simulations follow the same trend as in 2D simulations [START_REF] Hutson | The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology[END_REF], [START_REF] Moreau | The latchup risk of CMOStechnology in space[END_REF].

Rue Saint-Priest, Bat. 5, F-34097, Montpellier, France (corresponding author email: guagliardo@ies.univ-montp2.fr Thus, considering that we are interested in the trend of cross section, we have chosen to perform 2D simulations using Sentaurus Synopsys tool. TCAD simulations have been extensively used in the literature and thanks to them, it is possible to investigate mechanism of SEL by providing an insight view of the device. Due to the well-developed physical models available in TCAD tools, it is also possible to retrieve data that are useful to calculate parameters that are strictly related to radiation sensitivity, like cross section.

Here, we focused our analysis on the effects of temperature for A-C spacing, doping profiles variation and substrate and well taps placement. The aim is to verify to what extent SEL dependence on each parameter is highly influenced by the temperature variation. Additionally, we have calculated crosssection curves from 2D simulations and from them we have estimated SEL rate. In this way, we have analyzed the sensitivity of the device for the whole linear energy transfer (LET) range and not only in term of threshold LET. Hence, when specific parameters are selected for a design, these results can indicate if temperature variation will strongly modify the behavior of SEL sensitivity.

III. TCAD SIMULATIONS

A. Device structure and simulation setup

The first step was to design a CMOS inverter using design data for a commercially available bulk 65nm technology with Cadence Virtuoso. Based on the physical layout of the minimum-sized inverter, an NPNP structure (Fig. 1) has been retrieved. This structure is formed by the PMOS and the NMOS source and it is the basic structure required to investigate SEL mechanisms [START_REF] Bruguier | Single Particle Induced Latchup.pdf[END_REF]. Firstly, we have chosen the range of temperature to use for simulations. Temperatures of 350 K, 375 K, 400 K and 425 K have been chosen. As we know, SEL is more likely at higher temperature, so we have chosen a set of temperature in which it was more likely to obtain Single-Event Latchup. Secondly, we have chosen five values for each parameter to explore a broad range of possibilities. Thus, for substrate and well taps placement we considered their distance and we have chosen 1.05, 1.25, 1.55, 1.85 and 2.15 µm, moving taps symmetrically further from the center. Doping profile of the whole structure has been modified by multiplying a reference value, based on a commercial bulk 65nm process, times 0.75, 0.85, 1.15 and 1.25. Its value was changed across the whole structure. Eventually, these five values have been chosen for A-C spacing: 0.25, 0.27, 0.32, 0.37 and 0.40 µm.

In order to perform simulations on Sentaurus Synopsys we needed to choose physical models. We have chosen proper models for a 65 nm technology and they have been based on previous literature [START_REF] Youssef | Analysis of low temperature on single event Latchup mechanisms by TCAD simulations for applications down to 50K[END_REF], [START_REF] Gawlina | Transient 3D Simulation of Single Event Latchup in Deep Submicron CMOS-SRAMs[END_REF], [START_REF] Artola | Single-Event Latchup Modeling Based on Coupled Physical and Electrical Transient Simulations in CMOS Technology[END_REF]. The hydrodynamic model has been chosen along with Fermi statistics as carrier transport model. The mobility was modelled with the built-in model by Arora [START_REF] Arora | Electron and hole mobilities in silicon as a function of concentration and temperature[END_REF], which is a doping and temperature dependent model. For recombination the doping dependent Shockley-Read-Hall, Auger recombination and avalanche generation have been chosen. Finally, bandgap narrowing for high doped region has been selected.

Ion track has been generated through the built-in tool on Sentaurus Synopsys. A range of 2.3 µm in order to cover the entire structure with a constant linear energy transfer has been selected. The radial distribution has been set with a Gaussian profile with a 50 nm radius, according to previous works [START_REF] Youssef | Etude par modélisation des évènements singuliers (SET/SEU/SEL) induits par l'environnement radiatif dans les composants électroniques[END_REF], [START_REF] Artola | Single-Event Latchup Modeling Based on Coupled Physical and Electrical Transient Simulations in CMOS Technology[END_REF].

B. Cross section calculation

In order to calculate cross section, we followed the approach as reported in [START_REF] De La Rochette | Simulation of heavy ion latchup cross section curves[END_REF]. At first, threshold LET was obtained for different positions along the device and a chart was created, as the one in Fig. 2. From this chart, it is then possible to calculate for every LETx value, which portion (that we call "sensitive zone") of the device is sensitive to Single-Event Latchup for that value of LET. By multiplying the sensitive zone by the width of the component, the cross section is calculated. The width is in the order of magnitude of µm. An example of cross section curve is shown in Fig. 3.

IV. RESULTS AND DISCUSSION

A. Threshold LET

First, in Fig. 4, the threshold LET trend for doping profiles is shown. More specifically, it is shown the trend for the range of temperature considered. As expected, threshold LET decreases as the temperature increases and increases as the doping profile increases [START_REF] Rezzak | Single Event Latch-Up Hardening Using TCAD Simulations in 130nm and 65nm Embedded SRAM in Flash-Based FPGAs[END_REF]. Moreover, it is interesting to focus on the trend. If we consider the condition in which the device design is more favorable to induce Single-Event Latchup, as the worst-case scenario (lowest threshold LET, i.e. lower doping level) and the best-case scenario as the opposite, we can observe that the threshold LET difference for each single doping case, increases as the conditions become less favorable to SEL. In fact, in the worst-case scenario, the difference between threshold LET at 425 K and at 350 K is 50%, meanwhile in the best-case scenario a difference of 60% is reached between 425 K and 375 K. Moreover, at 350 K, no SEL is observed for x1.15 and x1.25 case, which are thus the best condition for immunity.

In Fig. 5, threshold LET curve for substrate and well taps placement are shown. Thresholds decrease as the temperature decreases and it is higher as taps are placed closer to the center of the device, which is confirmed by literature. Furthermore, temperature influence can be also seen in this case. In the worstcase scenario, the difference between 350 K and 425 K is 50% and as we have seen previously, in the best-case scenario the difference becomes higher. Indeed, threshold LET is increased by 75% just between 425 K and 375 K and at 350 K SEL is not even achieved.

Eventually, in Fig. 6 threshold LET curves for anode to cathode spacing are shown. The trend that has been observed for the previous parameters is also confirmed for the A-C spacing. Regarding this condition, in the worst case, threshold LET between the lower and the higher temperature increases by 58%, meanwhile in the best-case scenario threshold increases by 53% between 425 K and 375 K and SEL is not reached for 350 K. In this case, the difference is smaller with respect to previous examples. The reason may be that the effects of anode to cathode spacing variation is lower with respect to the other parameters.

In conclusion, for all the conditions investigated, temperature influence on SEL sensitivity is lower when conditions are more favorable to SEL and increases as parameters are modified to make the component less sensitive.

B. SEL rate

To further investigate this trend, we have calculated the SEL rate for a specific orbit, using OMERE, a free software dedicated to space environments [START_REF] Varotsou | [END_REF]. Cross sections calculated with the 2D approach (Fig. 3) have been used to calculate the SEL rate. Regarding the doping profile, in Fig. 7, it can be seen that SEL rate follow the same trend observed for threshold LET. Considering that SEL rate takes into consideration the whole cross section, it means that the trend that has been seen for the threshold LET is present even for higher LET. Considering, 425 K as a reference, SEL rate increases from 30% to 40% for the worst case (x0.75), it increases from 40% to 80% when reference doping profile is analyzed, and increases from 70% to Fig. 4. Threshold LET vs doping profile for four different temperatures (350 K, 375 K, 400 K and 425 K). Fig. 5. Threshold LET vs substrate and well taps distance for four different temperatures (350 K, 375 K, 400 K and 425 K). Fig. 6. Threshold LET vs anode to cathode spacing for four different temperatures (350 K, 375 K, 400 K and 425 K).

97% for the best-case scenario (x1.25, which is not calculated at 350 K because SEL was not obtained). In Fig. 8, it is shown the SEL rate for substrate and well taps placement. Even in this case, the trend is confirmed. SEL rate increases from 35% to 40% for the best-case scenario and it increases from 65% to 88% in the worst-case scenario. Eventually, SEL rate for A-C spacing is presented (Fig. 9). SEL rate varies from 46% to 82% for the best case and from 37% to 54% in the worst case.

C. Discussion

From the results it can be observed that temperature plays a different role depending on the condition of the device. When conditions of the device are favorable to SEL, temperature variation is affecting threshold LET and SEL rate less relevantly than in the case if which the device is more hardened. In order to explain that, SEL triggering conditions must be considered. As aforementioned, the structure of the CMOS creates two parasitic transistors inside it. The activation of these transistors is the initial step for Single-Event Latchup. Hence, a circuit is created inside the structure as depicted by [START_REF] Bruguier | Single Particle Induced Latchup.pdf[END_REF]. Certainly, the characteristic of the circuit is related to the design of the device and then, a variation of a parameter leads to a variation of the response of the circuit and then to a variation on SEL sensitivity. Specifically, the doping profile influences the PNP bipolar current gain and the resistances inside the device [START_REF] Rezzak | Single Event Latch-Up Hardening Using TCAD Simulations in 130nm and 65nm Embedded SRAM in Flash-Based FPGAs[END_REF]. Substrate and well taps placement variation causes a modification of the resistances present inside the device. A lower resistance will reduce SEL sensitivity, meanwhile a higher resistance will increase it. Concerning the A-C spacing, if it is increased, the bipolar current gain is decreased (as similarly observed for the doping profile). Eventually, temperature modification will cause a change on the resistances and it will modify the forward bias voltage of the base-emitter junction. A variation of this parameter means a variation of the potential barrier needed to trigger SEL [START_REF] Artola | Single-Event Latchup Modeling Based on Coupled Physical and Electrical Transient Simulations in CMOS Technology[END_REF].

However, SEL sensitivity is clearly dependent to a combination of all these effects. This work shows that for all the parameters (doping profile, substrate and well taps placement and A-C spacing) a more relevant variation of threshold LET and SEL rate is obtained for the best-case scenario, with respect to the worst-case scenario. On first consideration, we can say that in the best-case scenario, conditions are already favorable to SEL immunity and then the decrease of temperature will help to increase SEL immunity of the device. Meanwhile, in the worst-case scenario, the device situation is already on SEL favor. Then, temperature will have a lower effect on SEL sensitivity. In general, it can be considered that temperature impact is not equal in all conditions and it is not independent from device design.

V. CONCLUSION

In this work a comparison between the effect of temperature on four different parameters has been made. Cross-section curves for each parameter have been calculated using 2D TCAD simulations and then SEL rate has been estimated from these curves. For each parameter, we have modified its value and then for each single case we have investigate temperature effects, for a chosen temperature range. At first, threshold LET is investigated. We have observed, for every case, that when the component is less sensitive to SEL, temperature has a stronger impact on threshold LET, with respect to the opposite case. To further investigate this trend, we have calculated SEL rate for the GEO orbit. Indeed, the same trend has been observed for SEL rate. In the extended version of the paper, we will investigate this aspect.

Fig. 1 .

 1 Fig. 1. Simplified NPNP structure used in our work. A-C spacing is depicted.

Fig. 3 .

 3 Fig. 3. Example of cross section curve calculated by 2D approach. It shows the variation of cross section (σ) for different temperatures. Fig. 2. Minimum LET value versus position along the component.

Fig. 7 .

 7 Fig. 7. SEL rate vs doping profile for four different temperatures (350 K, 375 K, 400 K and 425 K).

Fig. 8 .

 8 Fig.8. SEL rate vs substrate and well taps distance for four different temperatures (350 K, 375 K, 400 K and 425 K).

Fig. 9 .

 9 Fig.9. SEL rate vs anode to cathode spacing for four different temperatures (350 K, 375 K, 400 K and 425 K).

ACKNOWLEDGEMENT

This work was realized within RADSAGA project. The RADSAGA Innovative Training Network project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie-Skłodowska-Curie grant agreement number 721624.

This work was realized within RADSAGA project. The RADSAGA Innovative Training Network project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie-Skłodowska-Curie grant agreement number 721624.


Y Q Aguiar
email: aguiar@ies.univ-montp2.fr

Frédéric Wrobel

J.-L Autran

F L Kastensmidt

P Leroux

F Saigné

V Pouget

Antoine D Touboul

F L Autran

P Kastensmidt

F Leroux

V Saigné

A D Pouget

Touboul

Exploiting Transistor Folding Layout as RHBD technique against Single Event Transients

Keywords: Transistor Folding, Radiation Hardening by Design (RHBD), Single-Event Transient, Monte-Carlo simulation, Circuit Design

published or not. The documents may come   L'archive ouverte pluridisciplinaire

The general goal of each technique is to reduce the charge collection efficiency of a given circuit so the overall Single-Event Transient (SET) pulse can be shortened and/or the collected charge does not exceed the critical charge. For instance, it can be acquired by reducing the sensitive collecting layout area (drain regions) and the parasitic bipolar effect, or even by promoting the pulse quenching effect via charge sharing. However, due to the multi-node collection at deeply scaled technologies, the charge sharing effect might also reduce the efficiency of well-known RHBD schemes such as the DICE designs and Error-Correction Codes (ECCs) due to multiple Single-Event Upset (SEU) and multiple SET occurrences [START_REF] Black | Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction[END_REF]. Some investigation has been done towards the adoption of transistor folding technique as radiation hardening approach [START_REF] Zhao | Singleevent multiple transients in guard-ring hardened inverter chains of different layout designs[END_REF][START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF][START_REF] Chi | Characterization of single-event transient pulse broadening effect in 65 nm bulk inverter chains using heavy ion microbeam[END_REF][START_REF] Maharrey | Characterization of Heavy-Ion Induced Single Event Transients in 32nm and 45nm Silicon-on-Insulator Technologies[END_REF]. Device level simulations and laser testing have shown a reduction on the SET susceptibility of single transistors and inverters [START_REF] Zhao | Singleevent multiple transients in guard-ring hardened inverter chains of different layout designs[END_REF][START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF][START_REF] Chi | Characterization of single-event transient pulse broadening effect in 65 nm bulk inverter chains using heavy ion microbeam[END_REF][START_REF] Maharrey | Characterization of Heavy-Ion Induced Single Event Transients in 32nm and 45nm Silicon-on-Insulator Technologies[END_REF]. However, further study is needed to verify the applicability of this technique to harden a set of standardcell logic circuits, for instance.

Accordingly, this work proposes the evaluation of the impact of a widely used layout technique, named transistor folding [START_REF] Her | Cell area minimization by transistor folding[END_REF], to the SET robustness of basics logic circuits combined with diffusion splitting. The layout technique is adopted in different digital logic gates and its SET susceptibility is evaluated under heavy ions. A layout-based prediction methodology is used to calculate the SET cross-section through Monte Carlo simulations [START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF][START_REF] Aguiar | Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity[END_REF]. Further, the in-orbit SET rates are predicted with OMERE package [START_REF]The OMERE 5.3 Software by TRAD and CNES[END_REF] for heavy ions and protons in Low-Earth Orbit (LEO) and International Space Station (ISS) orbits. Proton-induced SET rates are calculated from the heavy ion data using the METIS method [START_REF] Weulersse | A Monte-Carlo Engineer Tool for the Prediction of SEU Proton Cross Section from Heavy Ion Data[END_REF][START_REF] Weulersse | Prediction of proton cross sections for SEU in SRAMs and SDRAMs using the METIS engineer tool[END_REF]. Besides exploiting the transistor folding technique, the novelty of this work also lays on the usage of transistor folding with split in the active area of the transistors on different combinational logic gates to reduce area overhead.

The paper is organized as follows: Section II presents the transistor folding layout technique and the state-of-the-art of RHBD techniques tackling the generation of SET; the sensitivity analysis methodology adopted is described in Section III; the results and discussions on the impact of folded transistor in the cross-section of standard cells, the usage of asymmetric layout and voltage variability are provided in Section IV; and, Section V summarizes and concludes this paper.

II. TRANSISTOR FOLDING LAYOUT TECHNIQUE

Transistor folding is widely used to achieve improved performance and regularity in VLSI circuits [START_REF] Her | Cell area minimization by transistor folding[END_REF]. When larger transistors need to be employed, but it exceeds the fixed cell height of a given design, the transistor folding layout technique is used. The folding technique consists in connecting parallel transistors with reduced channel width to achieve a large overall width. Given a transistor with a channel width W, the same W/L ratio, thus the same drive strength, can be achieved by connecting n transistors with width W/n. Fig. 1 presents the principle of folded transistor layouts in the case of a doublefinger transistor. This layout technique divides the drain and source area into smaller partitions depending on the number of fingers. Due to the reduced source and drain areas, the diffusion-to-well capacitance is also reduced.

Considering radiation effects, this technique provides a reduced collecting drain area maintaining the same drive strength. The transistor size of folded designs can be calculated following Eq. 1, where WF is the width of each folded transistor, NF is the number of fingers, and W is the transistor width in the original design.

𝑊 𝐹 = 1 𝑁 𝐹 × 𝑊 (1)
The transistor folding technique can be adopted along with other hardening techniques such as gate sizing or dummy transistors/gates. The work in [START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF] was the first to propose transistor folding along with gate sizing to harden a circuit against both SEUs and SETs. A 3D mixed-mode TCAD (Technology Computer-Aided Design) simulation was carried out to analyze the SET pulse characteristics considering alpha particle and heavy ions hit on the center of the drain junctions [START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF]. Different from the sizing approach, which increases the circuit drive strength at the cost of increased drain area, transistor folding is able to reduce the transistor drain area while keeping the same drive strength. The transistor sizing was able to improve the robustness only for low-energy particles while the transistor folding showed also improvement when considering high-energy particles [START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF]. In [START_REF] Chi | Characterization of single-event transient pulse broadening effect in 65 nm bulk inverter chains using heavy ion microbeam[END_REF], different well structures and layout topologies were studied to evaluate the Propagation Induced Pulse Broadening (PIPB) effect in inverter chains. Accordingly, a double-finger inverter chain was compared against a single-finger inverter chain. In agreement with [START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF], the heavy ion results show a reduction on the overall SET pulse width, but minimum influence in the PIPB effect. Inverter chains hardened with guard rings were also evaluated using single and double-finger layout configurations with laser irradiation in [START_REF] Zhao | Singleevent multiple transients in guard-ring hardened inverter chains of different layout designs[END_REF]. Again, results showed an insignificant pulsebroadening factor for the folded inverter chain, however, a wider SET pulse width average was observed [START_REF] Zhao | Singleevent multiple transients in guard-ring hardened inverter chains of different layout designs[END_REF]. The authors attributed this to the larger spacing between the drain junctions and the guard rings in the folded design, which limits the charge collection reduction provided by the guard rings. Most of the studies have provided analysis for chains of inverters, and mainly for 2-finger layout configurations. In this work, the transistor folding is adopted on an inverter, NAND and NOR gates, and analyzed through layout-based predictive Monte Carlo simulations. Furthermore, the analysis of diffusion splitting along with transistor folding is provided to overcome the area overhead of multiple-finger designs.

III. METHODOLOGY

The target circuit layouts were designed following a commercial Process Design Kit (PDK) in a bulk 65-nm technology. Additionally, all designs are compatible with a standard-cell library. Minimum width, spacing and alignment/symmetry of each layer is carefully addressed to provide compatibility among the standard cells. The cell height is set to 13 tracks of metal pitch, i.e. 2.6 µm high. To provide flexibility in cell routing, the metal 1 (M1) is primarily used for the intra-cell connections, except for some cases in which metal 2 (M2) is used horizontally. The PMOS transistor width is 760 nm while the NMOS transistor width is 540 nm. To analyze exclusively the impact of the folded layouts, the equivalent transistor sizing was kept the same for all cases. After all circuit designs are DRC (Design Rule Check) clean, LVS (Layout Versus Schematic) checked and logic and electrical characterization is performed, the collecting drain area information can be extracted from the GDS (Graphical Design System) format file and submitted to the MC-Oracle tool [START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF]. The proposed layout-based predictive simulation chain is divided into two steps: first, particle interaction simulations are performed using the Monte Carlo simulation tool, MC-Oracle [START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF][20], to calculate and generate an SET database containing all transient currents; second, SPICE electrical simulations are performed to account for the circuit response effects [START_REF] Aguiar | Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity[END_REF][START_REF] Aguiar | Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions[END_REF][START_REF] Aguiar | Radiation Hardening Efficiency of Gate Sizing and Transistor Stacking based on Standard Cells[END_REF][START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF]. All circuits were driving a fan-out 1 (FO1), i.e. an inverter was coupled to its output signal. Only the SET pulses with peak voltage higher than 0.6 V (half the supply voltage) are considered for the cross-section calculation. In addition to the double-finger designs (Fig. 1), quadruple-finger layout configurations are also considered in this work (Fig. 2). However, one of the drawbacks of increasing the number of fingers in the folding technique is the increase in layout area. Thus, to overcome the area increase, a Diffusion Splitting (DS) layout technique is proposed and shown in Fig. 2. Instead of using a single strip of active diffusion, a 2-row stacked diffusion transistor is used. Besides reducing the area overhead of the folding technique, DS improves the metal connection routability maintaining the same W/L ratio and the number of gate fingers. To deepen this analysis, the impact on the in-orbit SET rates for heavy ions and protons and the effect of voltage fluctuation are also presented.

IV. RESULTS AND DISCUSSION

This work analyzes the applicability of the transistor folding layout technique to be used as an RHBD technique in standardcell libraries. The layout area information for the original design of the inverter, NAND and NOR gate along with the increase factor for its folded designs is shown in Table I. For the three cells analyzed, the double-finger layout configuration exhibited an area increase of approximately 1.5x the original single-finger layout area.

An area increase around 2.5x is expected when using quadruple-finger layout designs. However, if DS is used, the area overhead for the 4-finger designs can be reduced to the same observed in the 2-finger designs, i.e. approximately 1.5x greater than the original designs. Thus, DS provides an area reduction of 36% and 42% for the 4-finger inverter and NAND/NOR cells, respectively.

In Fig. 3, the simplified layout of the NAND designs containing only the metal1, diffusion and poly layers are shown. In standard-cell methodology, a fixed cell height is defined to provide regularity. Thus, as the number of finger is increased, the cell width is increased and, consequently, the cell layout increases. As the transistor sizing is kept the same, the diffusion splitting can be applied to reduce the impact in the layout area, as shown in the Fig. 3.

A. Impact on SET cross-section σSET

The SET cross-section σSET for the inverter designs under particle LET of 78.23 MeV.cm 2 /mg is shown in Fig. 4. The folded designs have shown similar σSET for input 1 and input 0, thus using transistor folding may reduce the SET sensitivity dependence on the input signal in the inverter design at high LET. On average, the folded designs provide lower sensitivity then the original design with the greatest σSET reduction for the 2-finger layout configuration, approximately 42%. The 4-finger inverter shows improvement solely for the input 1, however, despite the area reduction, DS also reduced the σSET. To analyze the folding impact for low particle LET irradiation, Fig. 5 presents the SET cross-section for the inverter designs considering heavy ions with LET = 5.43 MeV.cm 2 /mg. In this case, the greatest σSET reduction is observed for the 4-finger inverter with DS, about 37%. It can be observed that, for low LET, the σSET reduces with the increase of the number of fingers NF, in agreement with 3D TCAD results obtained in [START_REF] Kastensmidt | Transistor sizing and folding techniques for radiation hardening[END_REF]. As NF increases, the collecting regions are reduced and sparsely distributed along the layout, then the charge sharing at low LET is limited. Thus, less folded transistors are affected by a single particle hit, leading to an improvement in the efficiency of the technique in reducing the σSET. Fig. 6 depicts the mean SET cross-section curve for each inverter cell design considering the input 0 and input 1. Besides providing lower SET cross-section, the 4-finger designs (with and without DS) showed a higher threshold LET than the original design. For LET lower than 10 MeV.cm 2 /mg, the 4-finger inverter with DS is preferred, while for higher LET the 2-finger design is more suitable.

Considering the NAND designs, Fig. 7 presents the SET cross-section σSET under 78.23 MeV.cm 2 /mg. Except for the 2finger design, the folded designs provided a higher mean σSET.

At high LET, the hardening efficiency of folded transistors is limited due to the complex input dependence observed on the cross-section. The folded NAND designs show a stronger input dependence than the original design, leading to a similar or lower σSET only for inputs (0, 0) and (0, 1). The worst-case input scenario for NAND gates is the input (1, 1), and, in this case, transistor folding exacerbates the SET sensitivity up to approximately 62% in the 4-finger design. For input (1, 1), all PMOS devices are sensitive to a particle hit, besides the lower restoring capability of NMOS devices, PMOS transistors collect more charge due to its larger drain area [START_REF] Aguiar | Radiation Hardening Efficiency of Gate Sizing and Transistor Stacking based on Standard Cells[END_REF]. Similarly, in the NOR case, the input (0, 0) is the worst-case input scenario and it shows increased σSET when adopting folded transistors as shown in Fig. 8. This behavior is also observed for low LET as depicted in Fig. 9. To reduce the increased sensitivity at the worst-case input scenarios, transistor folding can be applied only in the pull-down (or pull-up) network to balance the overall SET sensitivity. The asymmetric designs are also considered in this work and discussed in the next subsections.

Considering LET = 5.43 MeV.cm 2 /mg in the NAND design shown in Fig. 9, the 4-finger design showed the lowest σSET, and similar sensitivity is obtained with DS. Thus, it is important to note that, for low LET, increasing the NF improves the overall SET cross-section σSET as observed for the inverter design. This behavior can be seen in the SET cross-section curves in Fig. 10 and Fig. 11, for the NAND and NOR designs, respectively. At 10 MeV.cm 2 /mg, the folded designs provide similar crosssection than the original one. Except for the 2-finger NAND, all other folded designs provided a higher threshold LET than the original design. For LET lower than 10 MeV.cm 2 /mg, the 4finger design with DS is preferred for both NAND and NOR.

To summarize the impact of folded designs under the effects of low LET particles, Table II contains the SET cross-sections for particle LET equals to 5 MeV.cm 2 /mg.

B. Asymmetric designs

As observed in the last subsection, transistor folding can induce a higher SET cross-section for the worst-case input scenario of the NAND and NOR circuits. Fig. 12 provides the transistor network of the NAND gate and its truth table. For the worst-case scenario, highlighted in red, the off transistors, which are sensitive to particle hits, are issued from the pull-up network, i.e. PMOS devices. The folding technique has been equally applied to both pull-up and pull-down networks. To study the impact of asymmetric designs, the 2-finger design and the 4-finger design with DS are explored considering the transistor folding only in one of the networks.

The folding technique was applied only in the NMOS devices for the NAND gate, and only in the PMOS devices for the NOR gate. The SET cross-sections are shown in Fig. 13 for each design considering only the worst-case input scenario, i.e. the input combination (1, 1) and (0, 0) for the NAND and NOR, respectively. The number indicates the fingers, N/P indicates when only NMOS/PMOS devices are folded, and S indicates when diffusion splitting is adopted. For instance, the F4NS circuit is the 4-finger design with only NMOS devices folded and with diffusion splitting. This nomenclature is used in the remaining of the manuscript for the sake of compactness. For the LET = 78.23 MeV.cm 2 /mg, the greatest reduction on crosssection was observed for the 4-finger designs. The NAND F4NS circuit provides a reduction of 26.5%, while the NOR F4PS circuit reduces the cross-section in approximately 29.7%. However, the asymmetric circuits are less effective when considering low LET particles as also shown in Fig. 13. Also, when adopting the asymmetric designs, not only the worst-case input SET cross-section is affected as can be seen in Fig. 14 in which the SET cross-section σSET for each input signal and the mean value are shown for the NOR gate. Due to a small increase in the cross-section for the inputs (0, 1), (1,0) and (1, 1), the mean SET cross-section reduction for the F2P and F4PS circuits are 1% and 13%, respectively. These results reaffirm the importance of considering input dependence when hardening digital logic circuits. The impact of adopting asymmetric designs is also evaluated under voltage variability and analyzed on the in-orbit SET rates.

C. Voltage Fluctuation

In addition to radiation effects, electronic circuits are susceptible to dynamic environmental variability, such as voltage fluctuations due to voltage drop and current derivative di/dt noise [START_REF] Bokar | Parameter variations and impact on circuits and microarchitecture[END_REF]. Previous works have shown that voltage variability reduces the reliability of circuits, especially when considering harsh environments under radiation effects [START_REF] Aguiar | Radiation sensitivity of XOR topologies in multigate technologies under voltage variability[END_REF][START_REF] Olowogemo | Effects of Voltage and Temperature Variations on the Electrical Masking Capability of sub-65nm Combinational Logic Circuits[END_REF]. In [START_REF] Aguiar | Radiation sensitivity of XOR topologies in multigate technologies under voltage variability[END_REF], voltage variability has shown to reduce the threshold LET of different XOR topologies in FinFET and Trigate devices. Also, a reduction in the electrical masking capability of the gates and increase in the SET pulse width is observed in [START_REF] Olowogemo | Effects of Voltage and Temperature Variations on the Electrical Masking Capability of sub-65nm Combinational Logic Circuits[END_REF]. The IR drops due to the parasitic resistance of the power grids can lead to ±10% variation on the supply voltage. Accordingly, all circuits were analyzed considering a voltage drop of -10% of the nominal supply voltage of the technology, i.e. 0.12V. The SET cross-section and the variation ∆σSET (in %) are shown for each circuit in Fig. 15. As expected, a reduction on the supply voltage of the circuits reduces the driving capability and consequently reduces the recovery efficiency, leading to a higher σSET. The usage of diffusion splitting technique induces insignificant impact on the circuit robustness to voltage variability as similar SET cross sections are obtained for the F4 and F4S circuits. However, for the 3 logic gates (inverter, NAND and NOR), the F4 and F4S circuits showed the greatest σSET increase, ranging from 50% to 70%. Thus, as the number of fingers is increased, the circuit becomes more sensitive to the voltage drops. However, the asymmetric designs have shown to reduce the impact of voltage variability on the SET cross sections.

Considering only the inverter designs, the F4S circuit shows the lowest σSET at nominal voltage but it is the most sensitive to voltage drops, along with the F4 circuit. On the other hand, the F2 circuit provides the lowest σSET at -10% of the supply voltage, and also the lowest variation on σSET.

For the NAND gate, the F4 circuit provides the lowest σSET at nominal voltage, but it increases up to 66% with 10% reduction on the supply voltage. In this case, the unhardened circuit is the least sensitive design to voltage variation, leading to approximately 24% of increase in the σSET. However, under voltage drop, the lowest σSET is still observed for the asymmetric design F4NS circuit. Compared to the unhardened NAND circuit, when the voltage fluctuation is considered, the F4NS reduced the σSET up to 35%.

For the NOR gate, similarly to the NAND gate, the F4 circuit provides the lowest σSET at nominal voltage, but high sensitivity to the voltage drops, resulting in approximately 49% increase in the σSET. However, it still provides the lowest σSET during voltage fluctuation. The diffusion splitting used in F4S increased its cross-section, but it still provides a lower σSET than the F2 circuit, with the same area overhead.

D. Prediction of in-orbit SET rates

Based on the SET cross-section curves calculated with the current database provided by MC-Oracle, the in-orbit SET rates were estimated for the Low-Earth Orbit (LEO) and International Space Station (ISS) orbits with the OMERE software. OMERE is a tool dedicated to the analysis of space environment and radiation effects on electronics developed by TRAD and CNES [START_REF]The OMERE 5.3 Software by TRAD and CNES[END_REF]. The Integral Rectangular Parallelepiped (IRPP) approach is used to predict the SET rate, i.e. it is calculated by the convolution of the heavy-ion cross section data with the particle flux in the aforementioned orbits. This approach is a standard method specified by the European Cooperation for Space Standardization (ECSS) [START_REF]Space Engineering: Calculation of radiation and its effects and margin policy handbook[END_REF]. The NASA AP8MIN trapped radiation model is used for the proton fluxes under solar minimum conditions [START_REF] Sawyer | AP-8 trapped proton environment for solar maximum and solar minimum[END_REF]. For the Galactic Comic Rays (GCR) fluxes, the international standard ISO 15390 model is used [START_REF]Space environment (natural and artificial)-Galactic cosmic ray model[END_REF]. A fixed shielding of 1 g/cm 2 is considered. The calculated heavy-ions SET rates are shown in Fig. 16. Firstly, it can be noticed that all folded designs exhibit lower rates than its unhardened version (F0 circuit) for both orbits. In the case of the inverter, the F4S circuit provides the lowest rate with a reduction of approximately 82% and 77% in the ISS and LEO orbit, respectively. Similarly, for the NOR gate, the F4S showed the lowest SET rate. The folded transistor and diffusion splitting provided about 66% and 55% of reduction on the SET rate for the ISS and LEO orbit, respectively.

On the other hand, the F2 circuit is expected to have a lower rate for the NAND gate. Although the cross-section calculations were performed for heavy ions, the protons are expected to dominate the SEE rates in the LEO and ISS orbits. Due to its improved accuracy when compared to analytical models, the METIS method [START_REF] Weulersse | A Monte-Carlo Engineer Tool for the Prediction of SEU Proton Cross Section from Heavy Ion Data[END_REF][START_REF] Weulersse | Simulation of Proton Induced SET in Linear Devices and Assessment of Sensitive Thicknesses[END_REF][START_REF] Weulersse | Predictions of Proton Cross-Section and Sensitive Thickness for Analog Single-Event Transients[END_REF] was used to predict the protoninduced SET cross section curves from the heavy ions data. The sum of the SET rate induced by heavy ions and protons are shown in Fig. 17. As expected, the overall SET rate increased considerably. However, in this case, the F4 and F4S circuits are no longer the most hardened designs. The F2 circuits have shown the lowest rate for the inverter and NAND gate, for both orbits. For the NOR gate, the asymmetric design F2P provided the lowest rate, about 10% reduction for the two orbits. Except for the F2N, one can notice that whenever the asymmetric design approach is adopted, a reduction on the overall SET rate is observed.

E. Transistor Scaling and Angular Dependence

With the increasing demand of better performance and low power in critical systems, advanced technology nodes have been studied to be employed in future missions. Due to the scaling of transistors, the hardening efficiency of these techniques might be reduced as the charge sharing effects are increased in response to the close proximity of the collecting zones in the advanced technology nodes. However, in FinFET technologies, the three-dimensional structure of the transistor impacts on the charge collection process and a reduction on the charge sharing effects might be expected as shown in [START_REF] Fang | Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAM[END_REF]. Further, if an SOI technology is adopted, the hardening efficiency would be highly improved due to the lack of the diffusion contribution in the charge collection [START_REF] El-Mamouni | Heavy-ion-induced current transients in bulk and SOI FinFETs[END_REF].

Concerning the angular effect in the charge collection, folded transistors have shown a low angle dependence as investigated in [START_REF] Atkinson | Single-Event Characterization of a 90-nm bulk CMOS digital cell library[END_REF]. In fact, only the NMOS transistors have shown an increase in the total collected charge. For the worst-case scenario, in which the particle strikes the center of the drain area with a tilt angle of 60°, the total collected charge of a 4-finger NMOS transistor can be 20% higher than the collected charge in original design, without transistor folding. Thus, a very weak angle dependence can be expected in the SET cross-section of the folded designs, especially for low LET due to the reduced charge sharing. Further, according to [START_REF] Ahlbin | The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process[END_REF], deeply scaled CMOS technologies present a marginal difference on the overall charge sharing effect between normal and angled strikes.

V. CONCLUSIONS

Physical layout design influences the main SEE mechanisms in VLSI circuits. Accordingly, RHBD techniques can be adopted at layout level. This work has analyzed the efficiency of transistor folding layout in improving the SET immunity of Fig. 16. Heavy-ions SET rate estimated with OMERE [START_REF]The OMERE 5.3 Software by TRAD and CNES[END_REF] for each circuit and its hardened version considering the LEO (800km, 98°) and ISS (400km, 51.64°) orbit. The SET cross section average of each input signal is used. Fig. 17. Total SET rate estimated with OMERE [START_REF]The OMERE 5.3 Software by TRAD and CNES[END_REF] for each circuit and its hardened version for the LEO (800km, 98°) and ISS (400km, 51.64°) orbit considering heavy ions and protons. Proton-induced SET rates are estimated with the METIS method [START_REF] Weulersse | A Monte-Carlo Engineer Tool for the Prediction of SEU Proton Cross Section from Heavy Ion Data[END_REF][START_REF] Weulersse | Prediction of proton cross sections for SEU in SRAMs and SDRAMs using the METIS engineer tool[END_REF]. The SET cross section average of each input signal is used.

digital circuits. In addition to the higher threshold LET, the results show that folded designs can provide lower SET crosssection, especially at low LET. The number of fingers were also explored. For LET lower than 10 MeV.cm 2 /mg, the hardening efficiency of the folded designs increases as the number of fingers is increased. However, at high LET, the 2-finger designs showed the best performances. Increasing the number of fingers increases greatly the final layout area. Thus, a layout technique was proposed to overcome the area overhead of multiple-finger designs. In the diffusion splitting approach, the active diffusion is split into two strips and placed vertically aligned within each other. Besides reducing the layout area, diffusion splitting may also improve the SET cross-section depending on the circuit topology, input signal and ion LET. Due to the strong input dependence of these techniques, it was also proposed to adopt asymmetric designs, i.e. applying the hardening techniques only in the PMOS or NMOS devices, depending on the worstcase input scenario of the logic gate. Voltage variability was also explored due to its impact on the reliability of deeply scaled technologies. The folded designs have shown a higher sensitivity to voltage fluctuation. However, the usage of asymmetric design showed to reduce it. And, lastly, the in-orbit SET rates were predicted for the LEO and ISS orbits. When the SET rate is only calculated for heavy ions, all the folded designs provided lower rate than the unfolded designs. However, the protons dominate the SEE rates in the LEO and ISS orbits. When protons are taken into account, the 2-finger designs (symmetric and asymmetric) and the asymmetric 4-finger design with DS are the most hardened circuits.

Fig. 1 .

 1 Fig. 1. Transistor Folding Layout technique.

Fig. 3 .

 3 Fig. 3. Simplified layout design of NAND F0 (no folding), NAND F2 (2-finger design), NAND F4 (4-finger design) and NAND F4S (4-finger design with Diffusion Splitting). For clarity, only the metal1, diffusion and poly layers are shown.

Fig. 2 .

 2 Fig. 2. Standard quadruple-finger folded transistor layout vs. folded transistor layout with Diffusion Splitting (DS) technique in which the diffusion strip is split into 2 strips and placed vertically aligned within each other.

Fig. 4 .

 4 Fig. 4. SET cross section for the inverter designs under LET = 78.23 MeV.cm 2 /mg considering input 0, input 1 and the mean value.

Fig. 5 .

 5 Fig. 5. SET cross section curve for the inverter designs under LET = 5.43 MeV.cm 2 /mg considering input 0, input 1 and the mean value.

Fig. 6 .Fig. 7 .

 67 Fig. 6. Log-Log representation of the mean SET cross section curves for the inverter designs. No event was observed in the 4-finger designs (triangle and rhombus curves) for LET lower than 5.43 MeV.cm 2 /mg

Fig. 9 .

 9 Fig. 9. SET cross section for the NAND designs at LET = 5.43 MeV.cm 2 /mg for each input signal and the mean value.

Fig. 8 .

 8 Fig. 8. SET cross section for the NOR designs at LET = 78.23 MeV.cm 2 /mg for each input signal and the mean value.

Fig. 11 .

 11 Fig. 11. Log-log representation of the mean SET cross section curves for the NOR designs. No event was observed in the folded designs for LET lower than 5.43 MeV.cm 2 /mg

Fig. 12 .

 12 Fig. 12. Transistor network of an NAND gate and its truth table. On-state and off-state are indicated for the transistors considering the worst-case input scenario, i.e. input (1, 1).

Fig. 14 .

 14 Fig. 14. SET cross section for the NOR designs at LET = 78.23 MeV.cm 2 /mg for each input signal and the mean value.

Fig. 15 .

 15 Fig.[START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF]. SET cross section considering a voltage drop of 10% over the nominal supply voltage and a particle LET of 5 MeV.cm 2 /mg. The percentage increase ∆σSET in the cross section is also shown in red line.

TABLE I TOTAL

 I AREA FOR EACH ORIGINAL CELL LAYOUT DESIGN (µM 2 ) AND THE INCREASE FACTOR FOR ITS CORRESPONDENT FOLDED DESIGNS

		Original		Folded designs
		design (µm 2 )	2-finger	4-finger	4-finger with DS
	Inverter	1.560	~1.5x	~2.4x	~1.5x
	NAND2	2.444	~1.5x	~2.6x	~1.5x
	NOR2	2.444	~1.5x	~2.6x	~1.5x

TABLE II SET

 II CROSS-SECTION FOR EACH ORIGINAL CELL LAYOUT DESIGN (10 -9 .CM 2 ) FOR PARTICLE LET = 5 MEV.CM 2 /MG AND THE DECREASE PERCENTAGE

		FOR ITS CORRESPONDENT FOLDED DESIGNS
		Original		Folded designs
		design	2-finger	4-finger	4-finger with DS
	Inverter	1.124	-20%	-35%	-37%
	NAND2	1.010	-18%	-49%	-48%
	NOR2	0.736	-5%	-41%	-33%

This work was realized within RADSAGA project and has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie-Skolodowska-Curie grant agreement number 721624.


Khalid Hachemi
email: hachemi.khalid@univ-oran2.dz

Didier Gourc
email: didier.gourc@mines-albi.fr

François Marmier
email: francois.marmier@mines-albi.fr

Optimal sizing of an automated dispensing cabinet under adjacency constraints

Keywords: automated dispensing cabinet, dispensing errors, optimal allocation, boundary conditions, algebraic model

In this paper, we focus on the problem of determining the feasibility of medication assignment in an automated dispensing cabinet. Indeed, a cabinet is made up of several drawers. Each drawer is subdivided into compartments, each capable of receiving one medication type. There are medications which should not be placed in neighbouring compartments because of the risk of confusion, according to medication similarity (lookalike/sound-alike drugs) or the pharmacological incompatibility which may lead to errors in dispensing. Then, the problem consists in determining the boundary conditions necessary for the allocation of medications to the different compartments without similar/incompatible medications in close proximity to one another. First, we developed an algebraic model that calculates the upper limit (not to exceed) of appearances of a medication in all pairs of incompatible medications. Then we formulated an efficient mixed-integer linear program that checks the existence of an acceptable solution to the assignment problem.

Introduction

The three main phases of the medication-use process are prescription, dispensing and administration. The prescription phase corresponds to the writing and the entry of the prescription with the update of the patient record. The second dispensing phase corresponds to the validation of the prescription, the preparation and the delivery of medications. The administration phase consists of the preparation and administration of the medication to the patient. Different errors can occur throughout the three phases. In this study, we will focus on the errors that occur during the dispensing phase, in an attempt to minimize them. When properly used, automated dispensing cabinets can greatly reduce medication selection errors when compared to manual dispensing. However, errors may occur during the filling of the cabinet, and improper placement of a product in the cabinet increases the likelihood that the patient will receive a wrong medication [START_REF] Hyland | Optimizing the use of automated dispensing cabinets[END_REF]. Consequently, decisions about the quantities of stored medications and their locations are the key of the reliability and safety of an automated cabinet.

To prevent the dispensing errors, it would be necessary to eliminate the causes that produce them. For example, confusing drug names due to the similarities between brand names (e.g.Sumial® and Luminal®) is a frequent cause of medication errors [START_REF] Hoffman | Medication errors caused by confusion of drug names[END_REF].Indeed, for human factors such as lack of attention, errors of dispensing can occur from mis-selection of drugs with sound-alike/look-alike (similar-looking or similar sounding names or similar-looking packaging). Some solutions and best practices are presented in [START_REF] Emmerton | Look-alike and sound-alike medicines: risks and 'solutions[END_REF]. Several techniques exist to reduce administration errors. One can mention the use of capital letters in the drug names writing [START_REF] López | Development of a list of look-alike drug names with recommended tall man letters[END_REF], as in Hydroxyzine and Hydralazine written HydrOXYzine and HydrALAzine to mark the difference. The barcode utilization to identify drugs is another means of preventing errors of administration [START_REF] Hassink | Effects of bar code-assisted medication administration (BCMA) on frequency, type and severity of medication administration errors: a review of the literature[END_REF] [START_REF] Poon | Effect of bar-code technology on the safety of medication administration[END_REF] [START_REF] Morriss | Effectiveness of a barcode medication administration system in reducing preventable adverse drug events in a neonatal intensive care unit: a prospective cohort study[END_REF]. Several research studies have investigated the impact of the introduction of automated dispensing systems in pharmacies. In a study led by [START_REF] Oswald | Dispensing error rate after implementation of an automated pharmacy carousel system[END_REF], the authors estimated error rate of filling and distribution before and after the implementation of an automated carousel system in Stanford's university hospital of 613 beds. They were able to notice the drastic reduction of the error rate. In another study [START_REF] Serrano | Introduction of an automated drug dispensing system in an intensive care unit[END_REF], the authors analyzed the impact of the automated dispensing system "Pyxis MedStation®" in the intensive care unit (ICU) both financially and in terms of human resources. By creating a list of drugs and using the management software 'Sinfohspharmacy', they showed that the monthly cost per patient with the Pyxis MedStation® system was reduced by 20.3%. The number of drugs in stock increased by 11.4%. In addition, less space was needed for storage while staff needed less time to carry out dispensing operations; reduction of 2 hours on average per day. Some researchers have studied the economic impact of the introduction of automated dispensing systems [START_REF] Chapuis | Automated drug dispensing systems in the intensive care unit: a financial analysis[END_REF]. Concerning automated dispensing cabinets, [START_REF] Pazour | A multiple-drawer medication layout problem in automated dispensing cabinets[END_REF] addressed the problem of locating medications inside the drawers of ADCs in order to minimize human selection errors. They have developed a quadratic optimization model, allowing determining the best storage locations and avoiding putting two similar drugs side by side to reduce picking errors. However, solving real-sized problems is not practical; the authors note that the solving of a problem of twelve medication and two drawers using CPLEX10.1 fails in finding an optimal solution due to memory limitations. Therefore, they proposed a heuristic solution approach. [START_REF] Hachemi | Assignment of Drugs in an Automated Drug Dispensing cabinet: An Approach Based on Petri-Net Controller Synthesis[END_REF] addressed the problem of assigning medications in an ADC by modelling the cabinet by a Petri net. Their goal was to synthesize, with a focus on control issues, a controller that prevented placing two incompatible medications side-by-side, whereas the problem considered in this paper is the prediction of the existence of an assignment solution according to the dimensions of a cabinet drawer. A 2011 survey by the American Society of Health-System Pharmacists (ASHP) concerning the evaluation of the practices and the technologies related to drug distribution and administration and which concerned 1401 hospitals in the United States, has concludes that the adoption of the new technology changes the philosophy of drug distribution, and health information is rapidly becoming electronic. Indeed, health information, including patient medication profiles, is more and more electronic, allowing easy access to patient information by all nursing staff and pharmacists. In addition, the distribution of drugs is increasingly decentralized with drugs kept close to patients [START_REF] Pedersen | ASHP national survey of pharmacy practice in hospital settings: dispensing and administration-2011[END_REF]. This study noted that 89% of hospitals used automated dispensing cabinets. The same survey conducted in 2014 found that 97% of hospitals surveyed used automated ADCs cabinets [START_REF] Pedersen | ASHP national survey of pharmacy practice in hospital settings: dispensing and administration-2014[END_REF], confirming the trend towards decentralized drug delivery systems that have the advantage of reducing delays by getting medications closer to the point of care. A recent study has further highlighted the role of ADCs in reducing dispensing errors (Fanning, 2015) by ensuring the physical separation of similar drugs, the use of alerts and light guidance technology, using Light-Emitting Diode (LED) to guide the operator to the correct compartment. In this paper, we address the problem of determining the feasibility of medication assignment in an automated drug dispensing cabinet ADC. The problem is to determine the boundary conditions necessary for the allocation of medication to the different compartments of a cabinet, knowing that there are medications which should not be placed in neighbouring compartments because of the risk of confusion that could lead to errors in dispensing. In this paper we refer by "Incompatible medications" to medications having a very similar appearance, nomenclature, packaging, dosage form, demand frequency, risk level, and dosage concentration, like mentioned in [START_REF] Pazour | A multiple-drawer medication layout problem in automated dispensing cabinets[END_REF].

Comment: An extended version of this paper will be published in ISTE book.