A Olivier Kermarrec

A Chantal

Lucile Yves

Benj Mécano A Pascal

Guigui Sans

Chrystel Gaëlle

Fred Denis

Floria Thomas

Marwa Lou

Coco Lerasta

Titi Lépec

Alex Van Der Poel

Mouss Antoine Hassan

2D two-dimensional 3D three-dimensional Al-pad aluminium pad ALD atomic layer deposition ASS active stress sensor BE back-end BEoL back-end of line BGA ball grid array CMOS complementary MOS CMP chemical-mechanical polishing CP copper pillar CPD cathodic pulse deposition CS crack-stop CSN cross-sectional nanoindentation CTE coefficient of thermal expansion CVD chemical vapour deposition CZM cohesive zone modeling Je tiens en premier lieu à remercier Rafael Estevez d'avoir accepté de diriger cette thèse, pour ses conseils, son soutien et les pauses café sur la "terrasse" du laboratoire. Je remercie également Sébastien Gallois-Garreignot pour la confiance qu'il a placée en moi. Pour toutes les fois où il a dû et su répondre à mes "Euh, excuse-moi Séb, tu as deux minutes ?". Je remercie chaleureusement Madame Hélène Frémont et Monsieur Sylvain Meille pour l'intérêt qu'ils ont montré à la relecture de ce manuscrit, ainsi que pour leurs retours critiques et instructifs. Aussi, je remercie Monsieur Yves Wouters d'avoir accepté d'examiner ces travaux, et ce, malgré les courts délais imposés par la situation sanitaire du moment. Mes amitiés à Jacqueline Cuoq et à Sylvie Champavier du laboratoire SIMaP pour leur soutien, d'une part, mais aussi pour leur disponibilité dès qu'il s'agissait de m'aider sur le plan administratif.

Je tiens à souligner le soutien que j'ai reçu de la part des différents experts des équipes R&D Crolles que j'ai eu la chance, et le plaisir, de côtoyer. Merci à Eric Sabouret de m'avoir accueilli dans son équipe, auprès de laquelle j'ai beaucoup appris sur les problématiques CPI. Merci à Grégory Imbert pour toutes les plaques

To my family To my friends xiii

General Introduction

Historically the oscillation frequency and size of transistors was the microelectronics industry goal. Since the early 2000s, however, this frequency has levelled off at around 5 GHz for purely economic reasons, then began a continual search of competitiveness, efficiency and performance, the trend being towards miniaturisation.

Miniaturisation of the micro-chip comes with smaller silicon surface, which implies smaller transistors as the available space use has to be precise and well balanced. Therefore, transistors have become so small that a physical limit (2 nm) is about to be reached 1 . The interconnection circuitry has to follow the trend, it went from a width in lithography of 8 µm in late 80s to 0.010 µm with down to 30 nm pitch 2 nowadays. Therefore, this phenomenon implies profound developments in several stages of the microchip design: materials reliability, photolithography width, integration of concepts and conception tools especially. The difficulties of the conception machines arise from this drastic shrinking of dimensions. As thin film deposits reach the atomic scale, their stacking in the interconnection manufacturing process must be done with a precision that constantly challenges these machines.

Given the growing attention of silicon industries, the fracture mechanics community has also taken an active interest in these challenges. Indeed, to reduce signal transmission delays due to capacitance phenomena -RC delays -porous materials with excellent electrical insulation properties, but mechanically weak and fragile, have been introduced: the low capacitance materials, or simply lowκ. Therefore, terms such as "mechanical stress" and "energy of adhesion" are therefore anchored in the sphere of microelectronics research, as work on these subjects of mechanical reliability is prevalent. Mechanically generated failures are thus commonly observed during qualification steps or product life.The latter must be avoided as the matter is critical for some specific applications, such as automotive or medical. The understanding and anticipation of such fails become mandatory, especially in a context of strong competition of the market. Structural and material optimisation, stress assessment, failure analyses and criteria are some examples of the research fields. This thesis work is in line with reliability issues following the introduction of low-κ materials in the production of a micro-chip. The objectives are three-fold, detailed in three chapters, the main purpose being to develop, by experimental xiv General Introduction and numerical means, methods for characterising the capacity of microelectronic products to resist cracking.

Chapter I provides a vocabulary of microelectronics which facilitates the understanding of the following chapters. We present the main manufacturing processes of an electronic device, from the definition of the transistor to the integrated circuit, and the main concerns and challenges.

Chapter II is a follow-up to previous thesis work carried out at STMicroelectronics 3 . It proposes to optimise so-called passive strain sensors, based on the strain gage principle, in order to implement them at different interconnection levels. Previous developments have also been performed on active sensors, operating on the principle of the piezoresistance of silicon. In this frame, we also carry out a parametric investigation on active sensors with regard to their dimensions and the influence of temperature conditions on the measured values.

Chapter III is in line with the issue of cracking the die might be subjected to, and which is the resistance to fracture of its seal ring structure. It is a metallic architecture surrounding the interconnects of the chip, intended to protect the interior from possible external chemical -humidity critically jeopardises the insulation properties of the low-κ materials -and mechanical attacks -micro-cracks intrusions from the singulation steps. The aim is to quantify the ability of a seal ring structure to stop a crack propagation with a simple test at silicon level, avoiding classic but cumbersome tests at package level (such as thermal cycling that takes thousands of hours). To do so, samples are specifically designed to fit the four-point bending crack method, intended to initiate and propagate cracks into the interconnects levels. Various seal rings are evaluated and experimental outputs are presented and discussed. A new bench is also specifically designed to monitor crack growth in real time. At last, we highlight, both experimentally and analytically, the importance of monitoring the crack front during its advance for the understanding and interpretation of the measurements.

Chapter IV proposes to complement the experimental work of Chapter III with a numerical approach, using cohesive zone models to study debonding phenomena. A deeper understanding of the experimental results and of the crack behaviour is thus provided. On the other hand, we also suggest to study the propagation of cracks on a local scale, that of the interconnections and the seal ring structure. The approach assumes debonding only phenomena, under small-scale yielding conditions, and is carried out to observe the impact of material parameters on crack toughness. Key parameters, design and material, are discussed. Finally, guidelines are proposed aiming to optimise a seal ring structure and thus, overall reliability.

Introduction

This chapter targets intends to relieve the reader throughout this manuscript by introducing some common vocabulary characteristic to microelectronics, also referred at as the semiconductor industry.

This subcategory of electronics principally deals with integrated circuits (ICs), or microchips. As the name suggests, the circuitry in question belongs within the framework of micrometre to nanometre-scale structures. An essential component of an IC is the transistor. Introduced in 1925 by Julius Edgar Lilienfeld [START_REF] Edgar | Method and apparatus for controlling electric currents[END_REF], his prototypes and ideas on a field-effect transistor (FET) led the first fully functional transistor invention at Bell Laboratories in 1947 [START_REF] Shockley | The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors[END_REF]. It was the size of a hand. Four decades later, after major breakthroughs in theory understanding and manufacturing means, microchips embed billions of transistors.

As the industry is in a constant need to miniaturise electronic devices, understanding reliability issues and defects assessment becomes a priority. The first section is a brief and non-exhaustive introduction to the fabrication processes of a microchip, covering several and different classes of materials, and the main issues related to the fabrication process. The second phase is a presentation of some popular packages, an interface between the microchip and the printed card board (PCB), and their respective advantages and limitations. The third and final section consists in the presentation of the objectives driving this study.

I.1 Fabrication process: the first steps

Transportation, business and manufacturing, agriculture, home appliances, and many other sectors have been revolutionised by the introduction of electronic devices:

Vehicles embark multiple sensors allowing GPS navigation, speed-limit regulation, line and proximity detection, etc. Passenger and road safety in general has significantly improved [START_REF] Xie | Key Applications of the Smart IoT to Transform Transportation Systems tech[END_REF].

Machinery networks, intelligent sensors and tracking technologies provide automation, real-time control, management and optimisation of any kind of plant or production unit [START_REF] Xu | Internet of Things in Industries: A Survey[END_REF].

Farming needs surge as population to feed keep growing. Farming drones, temperature and humidity monitoring and weather foresight are some of the solutions towards reaching this goal [START_REF] Busch | Science, technology, agriculture, and everyday life[END_REF].

Healthcare -Internet of Things (IoT) help the elderly and person with reduced mobility to remain independant by monitoring their health and daily guaranteeing their safety [START_REF] Demiris | Senior residents' perceived need of and preferences for "smart home" sensor technologies[END_REF].

I.1.1 Keeping-up with Moore's law

As the application fields and possibilities of integration keep growing, customer expectations and demands rise accordingly. In 1965 Gordon E. Moore, cofounder of Intel Corporation, publishes that "the complexity for minimum component costs has increased at a rate of roughly a factor of two per year" since their invention in 1965 [START_REF] Moore | Cramming more components onto integrated circuits[END_REF]. In 1975 Moore reassesses his predictions by stating that complexity is more a question of number of transistors in a microprocessor, and that this number is to double every two years [START_REF] Moore | Progress in digital integrated electronics in Electron Devices Meeting[END_REF]. produce a silicon-germanium-based transistor capable of oscillating at 510 GHz [START_REF] Krithivasan | Half-terahertz operation of SiGe HBTs[END_REF]. However, a condition to achieve this exploit is to perform the experiment under a cryogenic temperature, liquid helium brought down the temperature to 4.5 K, making it a non-commercial solution. Hence, it is possible to rise clock frequencies, but the cooling mechanisms would be very expensive from a consumer point of view.

1960 2010 Therefore, in order to keep-up with Moore's law and provide faster microprocessors, manufacturers tend towards doubling transistors density, parallel architectures that allow multi-thread operations and miniaturisation, see Fig.

I.2.
In parallel, the Moore's law is transitioning to a "more than Moore" strategy: instead of making better and faster chips that the application will comply to, it will consider the final application first. 3D integration, which consists in stacking different chips of different function into a connected pile, is for example a direct result of this new approach. But first of all, modern electronics started with the invention of the transistor. However, before getting to the final product, fabricating a microchip is a combination of processes and techniques that gather several disciplines: quantum, solid, and fluid mechanics, chemistry, etc. An IC is composed of two principal parts:

Front-end (FE) part is the active part of the chip, referred at as the die.

It is the silicon piece where the individual electric devices duch as the transistor, are embedded and where the input signals are processed.

Chapter I. Introduction To Reliability Challenges in Microelectronics

Back-end (BE) is the passive part of the chip. It constitutes the bridge between the FE and the system the IC is implemented in by collecting raw information and redistributing the desired outputs. The BE is also referred at as the package of the chip. The front-end itself is a combination of two core fabrication processes:

(FEoL) The Front-End of Line is the first step towards the fabrication of an IC. It consist in the implementation of the necessary unit devices for treating electric signals: transistors, resistors, diodes, capacitors, etc.

(BEoL) The Back-End of Line consists in a circuitry of metal and insulating layers above the FEoL. It is where the previously fabricated unit devices get interconnected according to the final function of the IC.

I.1.2 The Front-End of Line

Semiconductors FE parts of ICs are mainly fabricated using thin Silicon (Si) plates (usually 300 mm diameter and 775 µm thick) also called wafers, because of the semiconductive aspect of the material. Indeed, the metalloid's electric properties are halfway between those of a conductor and an insulator. Fig. I. [START_REF] Xu | Internet of Things in Industries: A Survey[END_REF] shows some common metalloids on the periodic table of elements.

A distinctive feature of a semiconductor is that it is capable to become a current conductor under certain circumstances. For instance, at temperatures higher than 0 K (T > -273.15 • C), there is creation of electron lone pairs that increase its conductivity. Another more realistic way to do so is doping. It consists in introducing foreign atoms into their crystal microstructure. The foreign body having either more or less peripheral electrons, two types of doping exist: N-type N stands for negative doping. It consists in adding the semiconductor supplementary peripheral electrons. The negative charges, as in conductors , participate in the transport of current.

P-type

In oppotision to n-type, it stands for a positive doping of the semiconductor. By bringing in atoms of lesser peripheral electrons, the positive charges represent holes or a deficiency of electrons that are capable to shift the surrounding electrons whenever an electric field is applied.

In the case of silicon, atoms of Phosphorus (P) and Arsenic (As) are used to obtain N-type Si (N-Si). They are on column XV of the periodic table of elements, thus have 5 peripheral electrons. As for P-type Si (P-Si), Boron (B) and Indium (In), with 3 outer electrons, are the main dopers.

Resistors

A direct effect of doping on silicon, is that its resistivity changes. Thus, a resistor is the simplest electronic unit. It consists in a doped region of Si. Depending on the quantity of added dopants, the electric current is accordingly slowed down [START_REF] Amemiya | Electrical trimming of heavily doped polycrystalline silicon resistors[END_REF].

P-N junctions

In the same way, another one of the smallest silicon components is the P-N junction diode. Diodes are an integral part of the functioning of a transistor that are composed of two adjacent zones of p-and n-type Si, see Fig. I.5. When these two zones meet, it gives place to a recombination phenomenon at their junction: the electrons fill in the holes. This non-neutral third zone, also called space charge region, gets its own internal electric field opposing resistance to any further diffusion of electrons or holes. Thus, in order to get a current to flow through the junction, an opposite and greater external current is necessary.

Transistors

One way to obtain a transistor, the keystone of electronics, is to reverse adjoin two p-n junction diodes. It is also referred at as the pnp or npn transistor, or bipolar (Bi). Although they are of several types, the main two branches are bipolar and field effect (FET) transistors which are respectively used in analogue and digital circuits. Either case, the overall function of a transistor is to control an input electric signal in order to produce a stronger or weaker, even null, output. In a certain way, it can act as an amplifier or a current switch in a circuit. FETs are the most common entity embedded in a digital IC, such as a microprocessor. They are used in a form of a metal-oxyde-semiconductor field-effect transistor (MOSFET or simply MOS). A MOS is composed of three parts: a gate which is the comination of and oxide and a metal, usually SiO 2 and poly-crystalline Si (poly-Si), a source and a drain. The source and drain regions are p-n junctions that supply the holes and electrons to the transistor then drain them away. When a positive tension is applied to the gate, electrons that are in minority in the P-Si body migrate towards the gate, forming a channel of electrons under the oxide. Thanks to this channel, current is able to circulate between the source and the drain. Hence the switch function of the MOS. The functioning of a pMOS is analogous: source/drain and the body are of opposite doping, thus instead of electrons, holes ensure the formation of the channel beneath the gate. Hence, combinations of nMOS and pMOS allow the creation of logic gates (NON, AND, NAND, OR, etc.), commonly referred at as complementary MOS (CMOS) technologies.

Dimensions of a transistor are of the sub-micrometre scale. In fact, the length of the MOS gate determines the technology node of the considered IC. Other designations are process node, process technology or simply node, and it refers to the manufacturing process and its design rules. In the 60s with the apparition of the first transistors, the technology node was 50 µm. As of today, most of the commercial solutions are designed in the range of 65 nm node, such as the ARM7 CPUs widely embedded in multimedia mobile applications 5 , to 10 nm, Intel 10 th generation of Icelake i3, i5 and i7 processors 6 . Some recent researches in the race to miniaturisation indicate soon to come 3 nm micro-architectures 7 .

The front-end of line components list is more exhaustive than resistors, diodes and resistors. However, what all these microscopic units have in common is that at the end of the FEoL manufacturing stages, they must be electrically connected to each other. This is done by a network of micro-wires that constitute the passive part of the silicon chip: the Back-End of Line.

I.1.3 The Back-End of Line

In the fabrication process flow of an IC, up to billions of transistors are implemented at the surface of the silicon wafer, see Fig.

Contacts

However, in the final stages of the FEoL process flow, the semiconductor unitary devices need to be electrically active after having been insulated by shallow trench isolation (STI) boxes, usually undoped silicon glass (USG), to prevent current leakage towards the neighbouring units. This is ensured by so-called tungsten (W) contacts. These are metallic lines and plugs which connect the devices together first horizontally, but also vertically to the first row of copper metal (V 1 , M 1 ). These contacts are buried in an insulating layer, usually Chapter I. Introduction To Reliability Challenges in Microelectronics phospho-silicate glass (PSG), also called pre-metal dielectric (PMD), which is ∼ 300 nm-thick in a CMOS28 technology node. As the designation implies, in order to connect a 28 nm CMOS to the first metal layer of the BEoL, the metal plug height to radius ratio is quite high (h/r > 10). For this reason, in addition to being a refractory transition metal, extremely resistant to heat and wear and inert to chemical attacks [START_REF] Blewer | Tungsten and other refractory metals for VLSI applications[END_REF], tungsten is the chosen metal. Moreover, the chemical vapour deposition (CVD) technique is very well suited to the fluorinetungsten (WF 6 ) plug process. Historically, due to early photoresist masking and plasma etching techniques, aluminium (Al) was the used conductor. As copper is a better electric conductor, efforts were made to allow its use in the interconnects, first by IBM 9 . In the same manner as the contacts, the interconnects are immersed into an insulator material referred at inter-metal dielectric (IMD).

) V 1 M 1 V 1 M 1 V 1 M 1 V 1 M 1 V 2 M 2 M 2 V 2 V 2 V 3 M 3 V 4 M 4 M 4 M 4 M 5 V 5
The number of metal levels in a BEoL stack depends on the purpose of the IC and the technology node. The lower the node (i.e. the higher the smaller the dimensions) the more the metal layers it is possible to embed. A metal level is composed of two parts:

• The via (V i ), which is usually a plug, that allows vertical connection between two metal layers.

• The line, or trench, or most conveniently referred at as metal (M i ), which horizontally connects vias. The sealing layer above the BEoL is silicon nitride and silicon oxide (SiN/SiO 2 ). The final passivation layer is a polymer of imide monomers, or polyimide (PI). The solder ball is made of tin-silver alloy (SnAg) and connects the chip to the PCB above.

As an order of magnitude, a BEoL's thickness is about 10 µm. Fig. I.8 presents a cross-section of an actual IC. We notice the abrupt scale transition firstly into the BEoL itself, between the first and the fifth metal layers, secondly between the BEoL and the BE (solder bump). Usually, the BEoL is divided into three sets of metal thickness:

• The X-levels: the first interconnect metals above the FEoL. The layers are the thinnest at these levels (20 nm -100 nm). The vias and lines width is also the smallest as these layers are the closest to the active components of the FEoL (down to 10 nm for vias). Consequently, they contain the highest metal (over dielectric) density (> 70 %).

• The Y-levels: transitional levels (100 nm -1 000 nm), they are not present in all the semiconductor devices.

• the Z-levels: the uppermost levels of the BEoL. They embed the thickest metal layers (200 nm -4 000 nm) and the widest lines and vias (100 nm -1 000 nm) that allow power distribution. Via density is the lowest (< 5 %).

From FEoL to BEoL, many processes are necessary to obtain such intricate structures. In view of the aforementioned dimensions, these involve very precise thin film deposition, photolithography and etching techniques among others.

Combinations of theses additive/subtractive techniques in successive steps put together constitute the (dual-)Damascene process.

I.1.4 The dual-Damascene process

ICs copper interconnects obtained through the Damascene process include several film deposition techniques. Of which, the most popular are chemical vapour deposition (CVD), physical vapour deposition (PVD) and electro-chemical deposition (ECD). The process contains subtraction methods as well, such as wet and dry etching and planarisation.

Chemical Vapour Deposition

Chemical Vapour Deposition is used in the semiconductor industry to produce thin solid films and coatings. Under vacuum, the substrate, a silicon wafer in this work context, is heated and placed into a chamber containing ambient and carrier, or precursor, gases. The chemical reactions between the gaseous precursors and the ambient gases near the surface of the substrate produce films. The process is versatile and offers diverse variations with respect to the desired result. For instance, for atomic layer deposition (ALD), that allows ultra-thin films a few nanometre thick, the precursor gases are introduced in pulses thus not continuously present in the chamber. Low pressure CVD (LPCVD) is another variation that allows better uniformity at the surface of the film, but however requires the substrate to be heated at a higher temperature (425 • C-900 • C). Another way to provide energy to the chemical reaction is using plasma.

Physical Vapour Deposition

Physical Vapour Deposition is also referred at as sputtering or cathodic pulse deposition (CPD). It is a deposition principle used in the metallisation steps. In a deposition chamber under vacuum, the considered condensed solid material, the target is first vaporised -usually using an Argon (Ar) plasma or an electron beam -then the resulting ions are accelerated towards the substrate thanks to the electrodes in the chamber, see Fig. I.9. Some metals deposited by PVD are aluminium pads at the uppermost metal levels of the BEoL, titanium precontact to enhance the electric connection between tungsten and the MOS gate, and Tantalum/Tantalum Nitride (Ta/TaN) metal barriers before each copper deposition.

Electro-Chemical Deposition

Copper in the BEoL interconnections is essentially dispensed using Electro-Chemical Deposition (ECD) method, or electroplating. The substrate, Si wafer, is first plunged into a copper sulphate bath (CuSO 4 → Cu 2+ + SO 2- 4 ) then connected to the cathode (+) of a current generator, see Fig. I.10. In front of the substrate, a copper plate (Cu → Cu 2+ + 2e -) is set in the same solution and connected to the anode (-). An electrochemical reaction then occurs at the surface of the silicon wafer to finally form a Cu layer of the desired thickness (Cu 2+ + 2e -→ Cu). CVD, PVD and ECD are all three additive processes. Subtractive operations are necessary to remove material and create holes and trenches that will soon be filled again by metal to become vias and lines for instance.

Cu plate

Si Wafer

Chapter I. Introduction To Reliability Challenges in Microelectronics

Photolithography

The role of the photolithography process, also called ultraviolet (UV) lithography, is to define areas on the wafer for the upcoming operations. By transferring the patterns from a mask, a set of reticles, into a beforehand deposited organic resin layer, we define the locations where dopants are to be implemented or layers are to be etched. The process is divided into three chronological steps, see Fig.

I.11.
1. Dispense: a photosensitive polymer is dispensed on the surface of interest.

2. Exposure: a laser produces a deep UV beam that transits through a set of lenses and reticles containing the desired level of metal pattern. The mask acts as a shield that blocks the UV rays.

3. Development: the negative of the mask, i.e. the exposed surfaces of the resin, is dissolved. The same pattern as the mask is then revealed.

Etching

Once the photolithography step is over, there are two ways of removing the material following the mask pattern: dry and wet etching.

Dry etching is performed with the help of a plasma beam that consists in two components: a physical one composed of positive ions, and a chemical one involving reactive materials.

1. positive ions are projected on the surface of the wafer. The impact tears off electrons from the target atoms.

2. reactive materials, in contact with the exposed surface, will chemically form volatile components. This step is selective depending on the target and the used chemicals.

Wet etching is performed using liquid/humid chemical only. This step is also necessary after each dry etch in order to drain the residuals at the surface.

A dry etch has the advantage of being anisotropic. Indeed, as the plasma beam is oriented, the subtractive operation is straight. On the other hand, a wet etch is isotropic as the liquid chemical can dispense horizontally, below the resin. Moreover, dry etching is preferred because it allows higher aspect ratios of the digging. In this case, when the depth over the width of the etch is "critical" from a dimensional point of view, an intermediate mask is deposited by PVD below the initial resin. It is usually a layer of titanium nitride (TiN), sometimes TEOS, that has a better resistance to plasma etching than the regular resin. Indeed, when the trench is narrow, there is a risk after dry etch that some particles, newly torn out from the resin, may clog the hole. This is why it is called the hard mask (HM). The removal of the HM is performed using a chemical-mechanical process, polishing. The Chemical-Mechanical Polishing (CMP) process, or planarisation, is intended to smooth and flatten the surfaces of silicon wafers. It is used especially to remove any excess of metals or oxides. CMP is also performed after etching to remove the hard mask. The process, presented in Fig. I.12 is sequential. On a rotating plate, covered by a fabric cloth, the pad, an abrasive liquid containing small silica or Cerium (Ce) balls, the slurry, is dispensed. The silicon wafer is held by a chuck, face down, then pressed against the pad. The chemical part of the slurry then "softens" the face in contact with the pad -chemical effect. The softer surface is then removed because of the friction with the slurry balls -mechanical effect.

Chemical-Mechanical Polishing

Dual-Damascene Process

Precise sequencing and repetition of the additive and subtractive techniques presented above allow the desired interconnection network to be obtained, i.e. the copper metallisation. Indeed, in the advanced technology nodes mostly, the BEoL is the result of a process called the dual-Damascene process. By analogy to the simple one, it consists in digging and filling the trench and via of a The BEoL is obtained by a dual-Damascene process flow over the entire surface of the silicon wafer. However, this complex sequence of precesses and various materials presents many reliability challenges, concerning the mechanical and electrical integrity of the stacks, of which we will be briefly presenting.

I.1.5 Front-End concerns and challenges

The main objective of the metal interconnections in an IC is to conduct and transmit electrical signals from "bottom" to "top". However, because of the miniaturisation direction taken by the modern semiconductor industry, see a Weak dielectrics for strong performance A capacitor, or condensator, is an electric device that gathers and stores electricity in a view to return it later, when needed. The simplest form of such device consists in two electrical conductors, metallic plates, separated by an insulator, a dielectric material for instance. Looking closer at Fig. I.13, we notice that the BEoL is greatly constituted of capacitors. Indeed, metal levels are filled with large copper trenches whilst separated by a dielectric. Added to this the resistance of the metal, we encounter the sketch of the notion of RC delay in the circuitry. In Fig. I.14, we propose, in a schematic approach, how the notions of Resistance R and Capacitance C arise in the BEoL. where κ is the relative permittivity, or dielectric constant, of the insulator and 0 the permittivity of free space. Because even a conductor is resistive, if we note R the resistance of the metal through which the current i flows, the time Chapter I. Introduction To Reliability Challenges in Microelectronics τ it will take for the capacitor to charge is

M N-1 M N i R V R C R i V R t A
τ = RC. (I.2)
Finally, substituting Eq. (I.1) into Eq. (I.2), we obtain an expression of τ based on the properties of the materials involved:

τ = R κ 0 A t . (I.3)
As shown in Fig. I.14, when considering billions of RC circuits in a BEoL, the accumulated delays, which is also referred at as parasitic capacitance, becomes a serious concern. According to Eq. (I.3), there are some solutions to reduce this time, such as decreasing the resistance of the interconnections. To do so, the semiconductor industry performed a switch from aluminium to copper interconnects during the 90s and early 2000s in advanced nodes [START_REF] Shwartz | Handbook of semiconductor interconnection technology[END_REF]. Indeed, copper is a better conductor as its resistivity rmρ is lower than aluminium's: Si dopant depletion and quantum-mechanical effects, the transistors emission response is influenced by its gate's capacitance. In Fig. I.15 we notice, indeed, that the lower the technology node, thus the smaller the transistor, the lower the delay. Moreover, principally because of its lower resistivity, copper interconnects are better transmitters than the aluminium ones. However, even if the delay times decrease, we notice a reversal of the trend from node 150 nm onwards.

ρ
Hence, another way of decreasing RC times in ICs which is the use of low dielectric constant. According to Eq. (I.3), the lower κ the lower τ . Indeed, we notice in Fig. I.15 the combination of said "low-κ"12 materials with copper interconnects. Is considered low-κ a material which dielectric constant is lower than 4. Sometimes, we can find the ultra-low-κ (ULK) designation when the constant is lower than 3. In general, the designations depend on the semiconductor manufacturer. Table I.1 lists some of the dielectrics used in the semiconductor industry 13 . We notice that general trend is that the lower the dielectric constant, the lower the elastic modulus E. Low Young's modulus is synonymous of inversely high compliance and ease of deformation of the material. Mechanically, it weakens the surrounding general stiffness of the interconnect. Moreover, as many low and ultra-low-κ materials are porous versions of existing materials -indeed one would "insert" holes into a bulk to lower its permittivity as κ Air 1 -these materials strength is also weakened. Indeed, these materials are brittle, with low rigidity and cohesive strength which, combined to the lowered rigidity of the structure, could present delamination issues. in terms in scaling and reliability: lower Joule heating and higher thermal conductivity, higher current densities and smaller sizes. However, the use of copper presents some challenges as well:

Patterning copper necessitates dry etching under gaseous environment assisting the plasma beam. For example, Chlorine gas forms chloride, difficult to evaporate, that lead to high copper corrosion [24]. Hence the passivation layers before and after Cu PVD that protect the metal.

Diffusion and electromigration into oxides and silicon has been widely observed and documented [25][26][27][28]. Diffusion being temperature-dependent, it consists in the penetration of copper electrons (high concentration) into the surrounding dielectrics (low concentration) and can even reach the active silicon. As for electromigration (EM), it consists in the movement of atoms of copper induced by a high current density. It results in voiding, a displacement of material that inevitably generates stress concentration at the narrowing region where material is missing [29,30].

Barrier metal, such as TaN/Ta, prevents possible copper electromigration. However, tantalum and nitrides of tantalum deposited films are highly conductive. Indeed, the barrier must prevent diffusion but ensure conduction at via to metal junctions. Thus, the effective dielectric thickness is somewhat reduced due to the deposit of these layers [31], and the capacitance is increased according to Eq. I.1.

Hillocks may appear because of diffusion and corrosion of copper [32,33]. They consist in small islets that, when vertically growing faster than the dielectric, can reach the upper metal level and cause shorts, or even stress concentration points.

c CMP drawbacks CMP is the primary technique in a dual-Damascene process to ensure planarity after metal deposition. But, because of its double nature, chemical and mechanical stress-induced defects such as dishing, oxide erosion [34] and metal corrosion [START_REF] Du | Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions[END_REF][START_REF] Ma | Corrosion Control of Copper Wiring by Barrier CMP Slurry Containing Azole Inhibitor: Combination of simulation and experiment[END_REF] have been observed and reported. Moreover, because of their low yield strength, friction can result in cracks in the dielectrics around the copper areas [START_REF] Leduc | Understanding CMP-induced delamination in ultra lowk/Cu integration[END_REF]. Fig. I.17 illustrates some of the drawbacks of failed CMP one may encounter.

With the constant evolution of microelectronics, of the additive-subtractive processes, the introduction of novel materials, the semiconductor industry is constantly finding solutions but also confronts new problems in this perpetual search for performance. However, despite the few back-end related challenges that have been introduced, the silicon wafer is still has many mechanical steps to go through in order to reach the final integrated circuit.

ILD

I.2 Packaging and related concerns: from silicon wafer to microchip

Once the wafer-scale front-end steps over, the silicon surface is active and the interconnection levels are established, the back-end process is set to start: packaging. The final stage of an IC fabrication process consists in connecting and encapsulating the silicon chip to a protective support case that is to be in contact with the surrounding ICs. The main and "classic" steps of the packaging process are thinning of the wafer, sawing to single silicon blocks, assembly of the chip onto the PCB and finally its encapsulation.

I.2.1 Thinning

In order to withstand the multiple additive steps during the IC manufacturing process -temperatures up to 900 • C, pressure on wafer during CMP or wafer handling from a chamber to another -the silicon wafer is at "full thickness", i.e. 775 µm. Therefore, in a view to provide devices that can be easily integrated into wearable and compact devices, the wafer is thinned from the back side. Indeed, as the active units are buried within the first few microns of the silicon, and the interconnections are extruded from the surface within few microns as well, a large amount of passive silicon remains on the back side of the wafer. In a process similar to CMP, a first coarse mechanical grinding step is performed, then completed by a fine polishing or chemical etching in order to reach the final thickness. The back-grinding process results in up to 90 % reduction of the wafer thickness, i.e. 80 µm.

For the same reasons than CMP, the grinding process being partially mechanical, a particular attention is to brought to the quality of the surface after polishing. In cases where the back side is poorly polished, scratched or rough, the chip "strength" has been found to be reduced [START_REF] Chen | Study on the effects of wafer thinning and dicing on chip strength[END_REF]. Moreover, as the dual-Damascene process being performed at wafer level, in different temperature conditions, the residual stresses at temperature equilibrium are overcome by the silicon stiffness, grandly relying on its thickness. Hence, thinning too much of the silicon may result in a large deflection of the wafer [START_REF] Kim | Wafer warpage analysis of stacked wafers for 3D integration[END_REF].

I.2.2 Sawing -Singulation

Sawing the wafer into single units of silicon, or die cutting, is the mandatory singulation step as its surface consists in a matrix of the same IC. Fig. I.18 shows a schematic of the sawing approach. During the BE process flow, "sawing streets" are planned between dies in order to leave a space for the diamond blade to make the cut, whenever a mechanical sawing is intended.

Usually, before sawing, two low-power laser grooves of the BEoL depth are performed, see Fig. I. [START_REF] Chen | Crystalline SiCN: a hard material rivals to cubic BN[END_REF]. Doing so, the surrounding trenches protect the die from any lateral micro-crack inclusion from the sides when mechanical sawing is performed. But, the trend of the semiconductor industry is to develop plasma dicing in order to perform the whole dicing process without any contact mechanism. Moreover, as it is laser guided, the procedure allows to cut round edges, instead of right angles because of the straight sawing streets, which can greatly reduce the stresses at the corner of the die [START_REF] Westerman | Plasma Dicing: Current State & Future Trends[END_REF].

Laser grooves

Diamond blade

I.2.3 Assembly & Encapsulation

Once the die is separated from the wafer, we perform the assembly step that is to connect to die to the surrounding electronics. To do so, we will be briefly introducing the main two assemblies that are preparing for Flip-Chip (FC) and Wire Bonded (W) packages. a Wire Bonding The procedure consists in first glueing the silicon side of the die to the surface of the substrate with a die attach material, the die is face up. We connect the BEoL and substrate metal pads thanks to very thin wires, hence the designation. The assembly is carried out under heat conditions that depend on the wire material (Au, Cu and Al are the most popular), and essentially consists in the thermosonic bonding of the wire to the two pads [START_REF] Harman | Wire bonding in microelectronics[END_REF]: downward pressure combined with a lateral ultrasonic movement.

The wire bonding process presents several advantages such as:

1. Low temperature process: Bonding is performed at quasi room temperature as heat is only brought to the wire.

Flexibility:

The wires can spread far from the die. Which means that if the package has to be redesigned, the substrate can remain the same.

3. Reworkable: If a wire connection is failed, it is possible to resume the operation.

4. Low price: Compared to a FC package for example, it is often cheaper and presents less stress issues in the BEoL.

On the other hand, the process presents limitations as well:

1. Contamination: If the atmosphere or the bonding surface is contaminated (dust, humidity, organic materials, etc.), the bonding quality is decayed.

Intermetallics:

In a dissimilar material bonding, copper wire on aluminium pad for example [START_REF] Kim | Effects of Cu/Al intermetallic compound (IMC) on copper wire and aluminum pad bondability[END_REF][START_REF] Khoury | A comparison of copper and gold wire bonding on integrated circuit devices[END_REF], intermetallic compounds form at the interface. Moreover, they tend to grow with applied thermal cycles.

3. Serial process: Indeed, the process is sequential as each wire has to be attached separately. Which can greatly affect the operation time of the bonding machine.

4. Limited I/Os: The biggest limitation is the limited I/O channels. As the die cannot be covered in metal pas, the channels are limited to its perimeter only. Hence a lower I/O density than a FC package for example.

b Flip-Chipping By analogy to wire bonding, the die is attached to the substrate upside-down using micro-bumps, or simply bumps. There are two main types used in the semiconductor industry: the solder bump and the copper pillar. Solder being historically the bumping choice when it comes to assembly, the trend switched with the advanced technology nodes. Indeed, the choice of copper pillar bumping principally relies on the fact that it allows a higher density of bumps at the die's surface. Indeed, as copper melting temperature is higher than the solder's, of ∼ 1000 • C and 230 • C for solder alloys, the spacing between consecutive pillars, the pitch, is greatly reduced. Hence a higher number on the surface of the die. Lower pitch bumping on FC packages are an advantage, compared to WB ones for example. Indeed, smaller dies allow high packaging density and small imprint on the substrate. Moreover, as the BEoL is in quasi immediate contact with the substrate copper trace, FC assemblies present better electric and thermal performances than WB ones [START_REF] Yuan | Thermal performance characteristic comparison between flipchip wirebond ceramic multichip modules[END_REF]. After bumping is performed, an insulating glue is injected to fill the space between the die and the substrate, see Fig. I.20. The underfill (UF) purpose is to prevent the die and the substrate to move sideways, as large displacement could break connections at bumps [START_REF] Zhang | Recent advances in flip-chip underfill: materials, process, and reliability[END_REF].

c Encapsulation Finally, the assembly is encapsulated into a protective case. In the WB packages, the assembly is surrounded by a moulding compound, an organic resin, that principally protects the wires from tearing. Moreover, the resin is a mechanical barrier that also keeps from chemical threats.

In the case of FC, over-moulded packages exist as well, but Fig. I.20 presents another type of encapsulation, the metal lid. It is glued on the substrate thanks to a lid attach material, sealing the edges from gases and chemicals. Usually associated with FC assemblies that embed high power ICs, thus need good heat evacuation from the system, it is in "contact" with the back side of the die through a thermal interface material (TIM) that enhances their thermal coupling.

Once the encapsulation is over, solder balls are deposited on the free side of the substrate to form a ball grid array (BGA) type substrate. There are other substrate types, such as the lead-frame of Fig. I.3, but BGAs are of the most popular in the semiconductor industry. Furthermore, another aspect that is widely studied and documented, not mentioned in this work, is the question of integration. More precisely, in order to reduce communication times between ICs of the same substrate, 2D integration, stacking dies in the out-of-plane direction, 3D integration [START_REF] Knickerbocker | 3D silicon integration in 2008 58th Electronic Components and Technology Conference[END_REF], proves to be a promising method of greater efficiency.

I.2.4 What could go wrong?

During the packaging steps presented above, we notice the wide range of temperatures at stake. As several materials are involved, the coefficient of thermal expansion (CTE) mismatch between these materials inevitably results in the structure deflection. In Fig. I.22 we present how such deflections evolve after each assembly stage of a FC package. The curves, obtained by finite element analysis (FEA) on a real-life FC product, show the overall bending along the package diagonal at room temperature (∼ 30 • C). First, as the substrate -from a package point of view as presented in Fig. I.20 -itself is a multi-layer structure. Hence an initial state that is not perfectly flat, but presenting a certain deflection instead. Then, throughout the assembly flow, the deflections switch signs, become more severe and finally fall back to a lower level.

It important to monitor such fluctuations in the package bending from different perspectives:

1. From a feasibility point of view, if certain deflection thresholds are exceeded, outside of the assembly tools specifications, the product simply cannot be manufactured.

2. The final deflection must fall within specific ranges. Otherwise, mounting on the PCB is of an unacceptable quality, even impossible.

3. From a reliability point of view, excessive bending generate stress concentration points at the edges of the die, especially at the outermost bumps location.

The last point concerns both the mechanical and the electrical reliability of the chip. Indeed, because Si is a piezoresistive material (see Chapter II), high residual stresses may affect the electric performances of the unit devices (transistors, resistors, diodes, etc.) at its surface. These elements are of course designed to work within a certain latitude, an operating range, but when this range is exceeded the chip becomes malfunctioning.

Moreover, we recall the size of a micro-bump which is in the order of tens of microns. In Chapter I. Introduction To Reliability Challenges in Microelectronics

I.3 Objectives of the study

The semiconductor industry has been continuously seeking for higher integration, synonymous of better performances, of the ICs. This has led to new integration schemes, and to the introduction of low-κ porous dielectrics of good insulation properties, but mechanically weak materials. These fragile materials present serious reliability challenges in the back-end packaging steps. The objectives of this work are therefore in line with this perspective, the development of characterisation methods in order to investigate assembly-induced stresses and fails in the back-end of line:

• In Chapter II we suggest to embed sensors both at the surface of the active silicon, working on the piezoresistivity of the material, and inside the BEoL, based on the strain gage principles. Indeed, the purpose of such sensors is to monitor and quantify in situ the stresses that are induced following the packaging of the die, thus find the critical steps and paths to reduce their impact. This work is a continuation of STMicroelectronics sponsored PhD work carried out beforehand by K. A. Ewuame [47] and B. Vianne [48]. The applications are various as (i) the trend is to include embedded sensors in real products, (ii) measure quantities that will help validate/correlate simulation work and (iii) help in the material/design selection.

• In Chapter III we investigate the four-point bending technique as a tool to initiate and propagate cracks into three different technology node samples.

The aim is to propose a new procedure to state on the seal ring robustness directly at the silicon level, without the tedious and cumbersome packaging steps, nor the time-consuming qualification steps. The cracks are set to evolve in the complex, intricate and highly heterogeneous BEoL of the samples. This, to develop a new experimental bending protocol in order to bring insight on possible parts of the die that have higher capacity to resist to the crack advance than others. For instance, the seal rings which are dense metallic structures surrounding the chips, and meant to protect the active silicon from cracks and other chemical intrusions. By monitoring the crack growth in real time, valuable insights are provided regarding the crack behaviour, its kinetics. Discussion is then proposed on the added values of such equipment, seal ring efficiency and the crack mechanism.

• Finally, Chapter IV presents a finite element modelling approach to study cracks evolving in heterogeneous media. The objectives are twofold: first help understand some aspects of the results obtained in Chapter III, then develop a local approach taking plasticity of copper into account. Thanks to this methodology, the ability of a seal ring to stop a crack propagation may be quantified, hence several design and material parameters are evaluated. Last, results are discussed, especially the requirement of a double criterion and guidelines are proposed.

Chapter

Abstract

Additionally to electrical performance drift of devices due to piezoresistance effect, dramatic delamination in the advanced interconnect levels are commonly observed, mainly due the introduction of the so-called low-k and ultralow-k materials known to have new integration schemes and poor mechanical properties [START_REF] Wu | Electrical Reliability Challenges of Advanced Low-k Dielectrics[END_REF][START_REF] Vanstreels | Mechanical Stability of Porous Low-k Dielectrics[END_REF].

With a view to characterise and monitor stress variations within integrated circuits (ICs) during the process flow, stress sensors have been developed and optimised in a view to be integrated in critical parts of the chip:

Passive stress sensors (PSS), consisting in copper lines disposed in serpentine shapes, have the advantageous capability of an integration into BEoL.

Active stress sensors (ASS) rely on the principle of piezoresistivity of semiconductors that has been widely studied for the late years [START_REF] Bridgman | The effect of homogeneous mechanical stress on the electrical resistance of crystals[END_REF][START_REF] Mason | Use of piezoresistive materials in the measurement of displacement, force, and torque[END_REF][START_REF] Kanda | A graphical representation of the piezoresistance coefficients in silicon[END_REF].

In order to explore some aspects of stress assessment at a microchip scale, this chapter first presents a brief review of the thermo-mechanical context and concerns as for the development of sensors to assess the induced stresses. The second part deals with a parametric study of different characteristic parameters of doped silicon resistors. Their influence on the piezoresistive coefficients and sensitivity to temperature are highlighted and discussed. The third part is a work of optimisation via Finite Element Modelling (FEM) on a passive sensor, a calibration process consisting in an embedding into interconnect levels of metal of a specifically designed test chip. The fourth and last part is the exploration of the use of tantalum nitride (TaN) as a new material that would improve a PSS sensitivity.

II.1 Introduction

From bare silicon wafer to essential part of any electronic component, a microchip is subjected to various thermal, chemical and mechanical loads. Indeed, within the dual damascene process that has been previously introduced, each specific step is carried out at specific temperature and pressure conditions. Added to this, the interconnect levels get denser in order sustain the growing needs of performance in the microelectronics industry. Which results in thinner and fragile layers into the back-end of line (BEoL).

The most critical problem being the different materials involved as each has its proper mechanical properties (Young's modulus, Poisson's ratio, yield strength and coefficient of thermal expansion) often resulting in cracking and and breakage into the die [START_REF] Matijasevic | Thermal Stress and Strain in Microelectronics Packaging[END_REF][START_REF] Miura | New mechanical reliability issues for deep-submicron devices in[END_REF].

A persistent challenge in the microelectronics industry is then to monitor and assess the stress fields in a chip, at any given time point during the processing.

II.1.1 On silicon properties

The advantages of using embedded stress sensors in microelectronic packages is that measurements are in-situ and non destructive. Initially, these sensors exploit the piezoresistive nature of silicon which has been widely studied since the early 1930's [START_REF] Bridgman | The effect of homogeneous mechanical stress on the electrical resistance of crystals[END_REF]. Silicon being the keystone of microelectronics, correctly processing experimental and/or finite element analyses of micro-electro-mechanical systems (MEMS) is essential. Hopcroft et al. [START_REF] Hopcroft | What is the Young's Modulus of Silicon[END_REF] raised the considerations to take into account regarding the anisotropy of silicon. The following subsection presents its main features, from a mechanical point of view. By extension, silicon wafers are also oriented. There is one commonly preferred plane in the industry, (100), such as the top surface of the wafer is the (100) crystal plane.

II

II.1.1.2 Elastic properties

Hooke's law is used to model the behaviour of an elastic material subjected to a stress (σ) in terms of deformation, or strain ( ), Eq. (II.1):

σ = C¯ , (II.1)
where C is the compliance of the material. It is written here as its fourth-order elastic moduli tensor. Such as σ and ¯ which are respectively the second order stress and deformation tensors. This formulation suits well for an isotropic material where C becomes the Young's modulus E. Eq. (II.1) becomes σ = E under uni-axial stress or strain load.

Because of the cubic symmetry of its crystal lattice, many terms in Eq. (II.1) simplify and the fourth-order tensor becomes a 6 × 6 matrix, Eq. (II.2), totally described by six components. Moreover, as it has two orthogonal planes of symmetry, it is possible to express Hooke's law using only three orthotropic constants: Taking into consideration its cubic symmetry, the anisotropic elastic tensor components of (100) non-rotated silicon that are used throughout this work are:

         σ 1 σ 2 σ 3 σ 4 σ 5 σ 6          =          c 11 c 12 c 12 0 0 0 c 12 c 11 c 12 0 0 0 c 12 c 12 c 11 0 0 0 0 0 0 c 44 0 0 0 0 0 0 c 44 0 0 0 0 0 0 c 44                   1 2 3 4 5 6          , (
        
165.7 63.9 63.9 0 0 0 63.9 165.7 63.9 0 0 0 63.9 63.9 165.7 0 0 0 0 0 0 79.6 0 0 0 0 0 0 79.6 0 0 0 0 0 0 79.6

         <100> (GP a). (II.3)
Hence, applying a tensor rotation operation of 45

II.1.1.3 Piezoresistivity

In addition to mechanical properties depending on the orientation of its crystal lattice, silicon is a piezoresistive material.

The piezoresistive effect, commonly referred at as piezoresistivity, is a change in a material's resistivity, ρ, when an external mechanical load σ is applied, Eq. (II.5).

ρ( σ) -ρ 0 ρ 0 = 6 i=1 π i (σ i -σ i 0 ), ∀i ∈ {1, 6}, (II.5)
where ρ 0 is the unstressed resistivity, σ i,0 are the initial state stresses and π i are the piezoresistance coefficients.

The relation between the resistance (R) and the resistivity (ρ) of a slender conductor is

R = ρL A , (II.6)
where L and A are respectively the length and the cross section area of the conductor.

Using Eq. (II.6) into Eq. (II.5), it is possible to determine the piezoresistance coefficients of a semiconductor by resistance measurements only. Indeed, provided the changes in geometry are negligible, i.e.

∆L L ∆S S 0, Eq. (II.5) becomes ∆R R = ∆ρ ρ = 6 i=1 π i (σ i -σ i 0 ), ∀i ∈ {1, 6}. (II.7)
Considering the anisotropy of silicon, π is usually a fourth-order tensor reduced to a 6 × 6 matrix [START_REF] Smith | Piezoresistance effect in germanium and silicon[END_REF][START_REF] Kanda | Effect of stress on germanium and silicon pn junctions[END_REF][START_REF] Bittle | Piezoresistive stress sensors for structural analysis of electronic packages[END_REF]. In the reference axes [100], [010] and [001] of the cubic crystal, the π tensor is expressed in Eq. (II.8).

Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses

π =          π 11 π 12 π 12 0 0 0 π 12 π 11 π 12 0 0 0 π 12 π 12 π 11 0 0 0 0 0 0 π 44 0 0 0 0 0 0 π 44 0 0 0 0 0 0 π 44          <100> . (II.8)
In the case of rotated silicon, the expression of π in the < 110 > system axes is

π = 1 2          π 11 + π 12 + π 44 π 11 + π 12 -π 44 2π 12 0 0 0 π 11 + π 12 -π 44 π 11 + π 12 + π 44 2π 12 0 0 0 2π 12 2π 12 2π 11 0 0 0 0 0 0 2π 44 0 0 0 0 0 0 2π 44 0 0 0 0 0 0 2(π 11 -π 12 )          <110> .
(II.9)

Eq. (II.9) is obtained by the rotation of the piezoresistive coefficients tensor by π/2 with respecte to the < 001 > direction.

Temperature, the nature of doping (n-or p-type) and the concentration of dopants are some parameters influencing the piezoresistivity of silicon. Fig. II.3 is an extract from Kanda's work [START_REF] Kanda | Piezoresistance effect of silicon[END_REF] on the piezoresistive effect of silicon. He highlighted effects of temperature, doping concentration and crystal orientation on silicon's piezoresistance. A first observation is that the higher the doping concentration, the lower the piezoresistive coefficient. Increasing the temperature leads to the same result. Moreover, the impact of temperature is less important as the doping concentration increases.

Relying of the piezoresistance phenomenon, structures as simple as a P-N junction diodes [START_REF] Kanda | Effect of stress on germanium and silicon pn junctions[END_REF] or resistors [START_REF] Mosser | Piezoresistive pressure sensors based on polycrystalline silicon[END_REF][START_REF] Suhling | Silicon piezoresistive stress sensors and their application in electronic packaging[END_REF], described in Chapter I, are usually used for stress measurement.

II.1.1.4 MOS stress sensors

In addition to Si resistors, transistors may also be used as stress sensors [START_REF] Jaeger | CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs) in VLSI Circuits[END_REF][START_REF] Chen | Multiplexed CMOS Sensor Arrays for Die Stress Mapping in[END_REF]. Indeed, subjected to an external stress σ, or strain ¯ , the drain current I D of the MOS drifts accordingly, Eq. (II.10). Note that such effects are used to boost MOS performances by applying appropriate stress components. This is referred at as "strain engineering". (After Kanda [START_REF] Kanda | Piezoresistance effect of silicon[END_REF])

I D ( σ) -I D 0 I D 0 = 6 i=1 π i (σ i -σ i 0 ), ∀i ∈ {1,
II.1.1.

Calibration of a stress sensor

However, in order to embed a stress sensor into a microchip, a calibration step is necessary to identify the piezoresistive coefficients and their dependency on temperature.

To do so, the four-point bending (FPB) test is used. Indeed, it is a displacement controlled method allowing to apply a constant bending moment between its inner pins. Thus, effects of non-perfectly centred samples are negligible, Eq. (II.12).

According to Euler-Bernoulli beam theory [65], and the nomenclature of Figure II.4, shear, |S| in absolute value, and bending moment, M z , in a FPB test are:

|S| = P 2 , ∀x ∈ [0, L] ∪ [L o -L, L o ], 0 , ∀x ∈ [L, L o -L],
(II.11)

and

M z = P 2 L , ∀x ∈ [0, L] ∪ [L o -L, L o ], P 2 (L o -x) , ∀x ∈ [L o -L, L o ].
(II.12)

Thanks to the constant moment of flexion between the inner pins, the beam is subject to a constant unidirectional traction stress equivalent to where I z is the second moment of area of the beam's rectangular section, of dimensions b × h, given by Eq. (II.14):

σ xx = M z I z y, (II.
I z = bh 3 12 . (II.14)
Combining Eq. (II.12), Eq. (II.13) and Eq. (II.14) with y = h/2, the traction stress at the top surface of the beam σ top xx at any point between the inner pins is

σ top xx = 3P L bh 2 . (II.15)
FPB is a commonly cited method in the literature for calibrating embedded silicon stress sensors [START_REF] Suhling | Silicon piezoresistive stress sensors and their application in electronic packaging[END_REF][START_REF] Jaeger | CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs) in VLSI Circuits[END_REF][START_REF] Gee | Strain-gauge mapping of die surface stresses[END_REF]. When the beam is under bending, four microprobes, connected to a Wheatstone bridge, measure the resulting variation of resistance, or electric current, Figure II.5. The four-point Kelvin measurement is performed in order to enhance the accuracy of the measure by bypassing any parasitic resistance [START_REF] Rymaszewski | Relationship between the correction factor of the fourpoint probe value and the selection of potential and current electrodes[END_REF][START_REF] Dan | Intrinsic response of graphene vapor sensors[END_REF].

A current I 0 is prescribed to circulate trough the studied sensor, points and . Between pins and , the point is to measure an electric potential, so a null current is imposed from both sides and electric potentials are measured so that the resistance value is

R = u 2 -u 3 I 0 ,
where u 2 and u 3 are to the electric potentials respectively measured at pins and . When applying a unidirectional stress using FPB, Eq.(II.15), it is possible to isolate the desired quantities in Eq. (II.7) and deduce the corresponding piezoresistance coefficient.

A V i 1 = I 0 i 2 = 0A i 3 = 0A i 4 = I 0 R 1 2 3 4

II.1.2 An overview of possible applications

Motivation for embedding stress sensors into a microchip are numerous. In order to study the residual stresses generated by thinning on a silicon wafer, Kumar et al. and their impact on the generated stress. Results showed that their method is suitable to obtain a ranking of the different structures, and that measurements were in good accordance to simulation, Fig II .7b. Ewuame et al. [47] implemented several n and pMOS rosette sensors on both sides of a Through-Silicon Via (TSV) in order to evaluate generated thermomechanical stresses induced after Cu annealing. Results, in agreement with a complementary finite element analysis, Figure II.8, showed that stresses up to 100 MPa are generated around the TSV due to copper's thermal expansion. Moreover, the authors drew up a set of guidelines for an optimisation of the sensors positioning in the microchip. They highly recommend to perform sequential in-line electrical measurements, instead of measures on split wafers, in order to bypass any inter-wafer process variability. As the chip was in a specific process flow for a further hybrid bonding, the second measures were performed after a thinning step and right after bonding. The third and final measurement took place after the packaging of the bonded chips. The authors found that from the M2 deposition step to the thinning of the chip, the generated stress field is mostly equi-biaxial, ie σ 11 ≈ σ 22 ≈ -25 MPa. However, the interpretation of the third set of measures revealed abnormally large stresses of over 1 GPa. Many reasons are evoked to explain this behaviour, such as the presence of bonding pads above the sensors and the impact of temperature reflows on the piezoresistive coefficients.

II.1.3 Objectives of the study

This chapter focuses on three different, but complementary, capabilities of assessing stresses into a microchip with the help of stress sensors. As presented in the foregoing section, there are several reasons to embed such sensors in a chip.

From an understanding point of view to assessing failure causes, the scope of possibilities is large.

In the continuity of Vianne et al. [START_REF] Vianne | Thermo-mechanical characterization of passive stress sensors in Si interposer[END_REF] and Sart et al. [START_REF] Sart | Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications[END_REF] PhD work, the first section of this chapter brings a first attention on the effects of doping levels and resistors shapes on the piezoresistive sensitivity of such sensors. Furthermore, the results of resistance measures are presented for three split wafers, subjected to different temperature flows in order to highlight the impact of temperature on a resistance value, thus on a sensor's efficiency.

Despite their good responsiveness to stress, as described in part II.1.2, active sensors implementation remain limited to the FEoL. The second part of this chapter deals with the development and optimisation of passive strain gaugelike sensors, directly embedded into the BEoL of a 28 nm technology-node test vehicle. This study points out the feasibility and efficiency of such sensors, compared to a previous work performed by Vianne et al. [76] in 65 nm technology node.

The third and last part is an investigation on the possibility of using tantalum nitride (TaN), which is until then used as a diffusion barrier for Cu metallisation, as a replacement for copper in a passive stress sensors.

II.2 Parametric study of n-type active resistorbased stress sensors

Following the work of Kanda et al. [START_REF] Kanda | Piezoresistance effect of silicon[END_REF], Vianne et al. [48] and Sart et al. [START_REF] Sart | Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications[END_REF] who raised concerns for the interpretation of resistance measurements under temperature, this section tends to bring some complementary information in order to improve our vision of the implementation of stress sensors in products of the microelectronics industry.

II.2.1 Piezoresistive stress sensor theory

In order to obtain the three components of the piezoresistive components in Eq. (II.8), Eq. (II.7) is detailed in order to understand the proper approach to adopt. Indeed, as temperature induces a change in the piezoresistivity of silicon, [START_REF] Kanda | Piezoresistance effect of silicon[END_REF], then it becomes:

R( σ, T ) -R 0 R 0 = 6 i=1 π i (T )(σ i -σ i 0 ) + n j=1 α j (T -T 0 ) j , ∀i ∈ {1, 6} (II.16)
Subscript 0 refers to the corresponding quantity measured at initial state, when no exterior load, either mechanical or thermal, is applied. Consequently, T 0 is the temperature at which resistance is first known when no stress is applied, and T is temperature at which measures are carried out. alpha j is the j th temperature coefficient of resistance (TCR). Usually, T CR = f (∆T ) is quasilinear [START_REF] Norton | Temperature coefficient of resistance for p-and n-type silicon[END_REF]. n = 2 is sufficient to accurately describe resistance change according to temperature.

As previously mentioned, the anisotropy of silicon defines its mechanical properties, Eqs. (II.3) and (II.4). Thus, it is important to understand in which coordinate system the equations are expressed in when considering rotated and nonrotated silicon. However, a focus is made on the non-rotated (100) silicon wafer, as the sensors that are studied in this chapter are embedded on this bulk.

Considering a set of three resistors in a (100) non-rotated silicon wafer, disposed in a 0 -45 -90 rosette shape, Fig. II.9, Eq. (II.16) gives the following system of equations, Eq. (II.17), expressed in the Cartesian and crystallographic coordinates system < 100 >. The whole approach is well documented in the literature, [47,[START_REF] Cordes | Optimal temperature compensated piezoresistive stress sensor rosettes[END_REF][START_REF] Suhling | Measurement of backside flip chip die stresses using piezoresistive test die in 32[END_REF]. Using the same notations as in Fig. II.9, variations of resistances under a mechanical load (σ 1 , σ 2 , σ 3 , σ 4 , σ 5 , σ 6 ) <100> are :

       ∆R 1 R 1,0 = π 11 σ 1 + π 12 σ 2 + π 12 σ 3 , ∆R 2 R 2,0 = 1 2 (π 11 + π 12 )σ 1 + 1 2 (π 11 + π 12 )σ 2 + π 12 σ 3 + π 44 σ 6 , ∆R 3 R 3,0 = π 12 σ 1 + π 11 σ 2 + π 12 σ 3 ,
(II.17)

Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses where ∆ R i stands for the measure of the variation of the resistance i (∀i ∈ {1, 2, 3}).

(100)

[110]

[100] X Considering a uniaxial load σ 100 on the [100] bar, Eq. (II.17) leads to:

       ∆R 1 R 1,0 = π 11 σ 100 , ∆R 2 R 2,0 = 1 2 (π 11 + π 12 )σ 100 , ∆R 3 R 3,0 = π 12 σ 100 .
(II.18)

Eq. (II.18) enables to find two out of the three piezoresistive coefficients π 11 and π 12 . In order to obtain the missing coefficient π 44 , the same procedure is applied on the second bar sample. Indeed, in order to do so, the applied load (σ 1 , σ 2 , σ 3 , σ 4 , σ 5 , σ 6 ) <110> and the piezoresistive tensor, Eq. (II.9), are considered in the < 110 > coordinates system. Eq. (II.17) becomes

       ∆R 1 R 1,0 = 1 2 (π 11 + π 12 + π 44 )σ 1 + 1 2 (π 11 + π 12 -π 44 )σ 2 + π 12 σ 3 , ∆R 2 R 2,0 = 1 2 (π 11 + π 12 )(σ 1 + σ 2 ) + π 12 σ 3 + (π 11 -π 12 )σ 6 , ∆R 3 R 3,0 = 1 2 (π 11 + π 12 -π 44 )σ 1 + 1 2 (π 11 + π 12 + π 44 )σ 2 + π 12 σ 3 . (II.19)
When the [110] bar sample is subjected to a uniaxial load σ 110 , Eq. (II. [START_REF] Chen | Crystalline SiCN: a hard material rivals to cubic BN[END_REF]) results in the following equations system:

       ∆R 1 R 1,0 = 1 2 (π 11 + π 12 + π 44 )σ 110 , ∆R 2 R 2,0 = 1 2 (π 11 + π 12 )σ 110 , ∆R 3 R 3,0 = 1 2 (π 11 + π 12 -π 44 )σ 110 .
(II.20)

Eq. (II.20), like Eq. (II.18), enables to find (π 11 + π 12 ) and the missing π 44 coefficient.

II.2.2 Parametric study of n-type resistors

As the primary goal of this chapter is not to study the piezoresistive stress sensor in its whole but the sole entity of the resistor, a set of four resistors has been embarked in a test chip all oriented along [100] direction, on a nonrotated (100) silicon wafer. Doing so, using Eq. (II.18) and FPB calibration immediately gives π 11 . A first observation is that the dopant concentration profiles at the center of the partially doped resistors are the same, no matter their length and width.

II.2.2.1 nSi resistors parameters

Cut line

Width

w (µm) Width w (µm) R 4 R 2 R 3 & Depth (µm)

II.2.2.2 Extraction of π 11 coefficients

Firstly, in order to determine the impact of length, width, doping and temperature, FPB calibration is performed. As resistors are implemented in only one direction, π 11 is derived by the measures from Eq. (II.18) that becomes

∆R 1 R 1,0 = π 11 σ 100 . (II.21)

Border-centre variability

One wafer containing the four resistors to study was at disposal. Kelvin measures are performed on several sites of the wafer in order to observe any effect between border and the center of the wafer. Figure II.13 illustrates this effect for the set of resistors at stress-free state2 . From the design rules of the technology node in which the test chip is in line with, recommendations as for avoiding any Joule heating, affecting the value of the resistances, are that current should not exceed 1.6 mA. In this section, measures are all performed with a current value of 900 nA. This result shows that there is no pattern in resistances values distributions at a wafer scale. However, from a general view, resistances at the centre of the wafer are higher than on its border. This phenomenon can be explained by variability in doping, etching, CMP, ... and several other processes, [START_REF] Nassif | Process variability at the 65nm node and beyond in Custom Integrated Circuits Conference[END_REF][START_REF] Pang | Measurements and analysis of process variability in 90 nm CMOS[END_REF]. As pointed out in Sart et al. and others work, residual stresses are sources of uncertainties in measurements as well, [START_REF] Kumar | Residual stress analysis in thin device wafer using piezoresistive stress sensor[END_REF][START_REF] Schmidt | Design and calibration of a microfabricated floating-element shear-stress sensor[END_REF][START_REF] Fang | Determining mean and gradient residual stresses in thin films using micromachined cantilevers[END_REF].

(a) R 1 (b) R 2 (c) R 3 (d) R 4

Calibration step to extract piezoresistance coefficients

As the resistors are implemented in the [100] direction, the wafer is diced into bar samples along this direction. Under constant room temperature, the samples are subjected to FPB in order to generate unidirectional stresses ranging from 0 to 100 MPa. Variation of resistance is recorded in order to extract values of π 11 for each type of resistor using Eq. (II.21). The experimental results are consistent with theory. Indeed, the resistances vary linearly in relation to the prescribed loadings. Moreover, different slopes are observed for each resistor. As expressed in Eq. (II.21), the slope corresponds to the value of π 11 , meaning that π 11 is different for each type of resistor. Fig. II.14 highligths the fact that doping and resistor shape influence its sensitivity to stresses. Table II.2 lists the equivalent piezoresitive coefficients according to each resistor type.

Firstly, the studies of R 1 from both Sart et al. [START_REF] Sart | Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications[END_REF] and this work are consistent with each other. Indeed, the extracted piezoresistance factors are equivalent: π 11 ∈ [-174.4, -171.925] TPa -1 . Concerning the resistance studied in Vianne et al. [48] work, dopant concentration is about 1 -2 × 10 17 atoms/cm 3 . Thus, comparing these three resistances, with the same dimensions but different dopant concentrations, it appears that the lower the concentration the higher Length (µm) A first observation is that π 11 does not depend on the resistor's width. Indeed, despite R 2 and R 4 have the same length, R 2 is twice as wide and yet, the same piezoresistive coefficient is measured for both resistors, Table II.2.

1.4e+18 1.6e+18 1.0e+20 R 2 R 3 R 4 R 1 + + N N C u t l i n e
On the other hand, R 2 and R 3 are of the same width. The calibration step showed that R 2 , which is twice as long as R 3 , is more sensitive to stress. Indeed, the derived piezoresistive coefficients are respectively -316.111 TPa -1 and -256.115 TPa -1 . At first sight, reducing the resistor's length by half results in a decrease of its sensitivity by about 20 %. It can be explained by the higher amount of N+ dopants in the larger n-well, the doping concentration being constant whatever the resistance length.

In addition to their respective piezoresistive coefficients, it is also relevant to compare the nominal values of the resistances. Indeed, the higher the resistance value, the higher the measured ∆R. According to Table II.2, R 1 and R 4 are the most resistive. Followed by R 2 and R 3 .

Influence of TCR

As raised in [START_REF] Sart | Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications[END_REF], in order to accurately interpret stress sensors resistances variations into stress variations, two parameters are necessary: the sensors temperature coefficient of resistance (TCR) and the variation of temperature. When tests are run in a controlled environment, the information about temperature is directly accessible. A specific procedure is necessary to evaluate the different temperature coefficients. To determine each of the four TCRs, measures are carried out under controlled temperature. A clean room-type tool capable of full wafer parametric measures in a temperature-controlled chamber is used. Firstly, measures of resistances at 25 • C match with the previously presented ones, Table II Listed in Table II.3, the figures show that omitting the influence of temperature, as small as 1 • C, could lead to a 400 % error in the estimation of the stress. Hence the importance of knowing each the TCR and the temperature variation profile during the experiment.

II.2.3 Outcomes

With the aim of studying the effect of several resistor parameters (doping, length and width) on the value of their longitudinal piezeoresistive coefficient, a set of four resistors was examined.

In fine, the partially doped n-type resistors derive the highest piezoresistive π 11 coefficient. Indeed, lower doping is synonymous of a higher coefficient. For a given dopant concentration, the resistor's length is the only parameter playing a part in the value of π 11 . Moreover, if width does not influence the stress sensitivity, it appears that the narrower the higher the resistance value. The outcome of the analysis is that R 4 is the best choice amongst the studied set of four resistors.

It is raised in [START_REF] Sart | Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications[END_REF] by Sart, and the phenomenon is illustrated in this section: a variation of temperature as small a 1 • C generates interpretation errors reaching 400 % for a single resistance. Spread to a whole 0 -45 -90 rosette, for example, resolution of Eq. (II.17) becomes greatly inaccurate, said the temperature shifted during the considered load.

Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses

As active stress sensors are designed for inline utilisation purpose, implementing a ring oscillator close to the sensor would be a possibility. Indeed, it is a MOS-based device whose output signal is an oscillating voltage. The frequency of the output signal is temperature dependant, which makes it a widely used temperature sensor [START_REF] Kim | CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control[END_REF]. Combining a ring oscillator with an active stress sensor would improve real-time temperature and stress measurement in a microchip.

II.3 Designing a passive stress sensor in 28 nm technology node

Despite being sensitive to stresses, active stress sensors implementation is limited to the silicon part of the chip, beneath the multi-layered part where delamination and other defects are to occur. Whereas passive ones, with the advantage of being embedded in the interconnect levels, seem to be a good choice when it comes to estimate the stress and strain fields within these layers.

Such structure has been developed by the past in a 65 nm node technology.

Results have shown some erratic behaviour from the sensors calibration as data was not exploitable [START_REF] Vianne | Thermo-mechanical characterization of passive stress sensors in Si interposer[END_REF]. In this section, we propose to optimise this kind of sensor with regards to the 28 nm denser metallisation levels and thinner copper lines and vias. Indeed, better characteristics in terms of imprints and sensitivity are expected thanks to the more advanced node used.

To do so, simulation is firstly provided to optimise the structure. A representative volume element containing a copper serpentine amid the whole interconnect layers is modelled and constraints along the three space directions are applied in order to determine their corresponding gauge factors.

Once numerically designed and then embedded in a test chip product, the second step consists of calibrating them using four-point bending method so as to correlate the data with the analytical expectations. Their performances with respect to the 65 nm technology node ones are also compared and discussed. Finally, a flip-chip ball grid array (BGA) package is simulated to illustrate the sensor abilities to be embedded in such package; from sensitivity and dimension point of view.

II.3.1 Parametric Designing of the Passive Sensor

Figure II.17: A rosette shaped passive stress sensor.

Passive stress sensors, in opposition to active ones relying on piezoresistance phenomena, are employed as extensometry gauges. Variation of current is measured between two states of stress and directly related to their deformation. Such sensors are composed of several copper serpentines, or passive resistances, set in different rosette shapes of 30 • , 45 • , 60 • or 120 • in general [START_REF] Hannah | Strain gage users' handbook[END_REF]. In this section, a rosette of four serpentines set in half a rosette shape with two different designs is considered. But for statistical purposes, they are designed in a full eight-resistance rosette shape as shown in Figure II.17, with 45 • between two consecutive resistances.

First, a preliminary design work is necessary to determine the main characteristics of the sensor so as to get the smallest yet the most sensitive structure. Indeed, compared to 65 nm technology node, 28 nm designing rules allow thinner lines, narrower pitch and smaller thicknesses. In addition to a higher sensitivity to the stress for which benefit is easily understandable, a smaller sensor would be less impacted by gradients of stress and make its integration easier. To do so, a fully parametrized finite element model has been built in order to evaluate the gauge factor according to the serpentine geometry. A portion of the model is showed in In this work, we did not consider any piezoresistive effect of the copper and the Tantalum Nitride/Tantalum diffusion barrier (TaN/Ta). As the resistance in a wire is defined by R = ρ×L S , where R, ρ, L and S respectively stand for resistance, resistivity of the material, length and section area of the wire, resistance change in a copper serpentine subjected to a stress field can be written as in Equation (II.22):

∆R R = G L σ L + G T σ T + G N σ N , (II.22)
where R stands for the resistance value, G for the gauge factor, σ for the applied stress and L, T and N respectively for the Longitudinal, Transversal and Normal directions.

σ L σ L (a) Longitudinal constraint. σ T σ T (b) Transverse constraint. σ N σ N (c) Normal constraint.
∀i ∈ {L, T, N }, ∆R i R = G i σ i .
(II.23)

II.3.1.1 Stress evaluation methodology

In order to estimate a stress field using a passive stress sensor, one can consider only four copper serpentines. For an illustration purpose, we consider this case in Figure II.20.

The active stress sensors used in the microelectronics industry include nMOS & pMOS and/or n-doped & p-doped (poly)silicon sensors [START_REF] Chen | Multiplexed CMOS Sensor Arrays for Die Stress Mapping in[END_REF]. By analogy to

Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses this case, two types of resistors are used in the rosette copper sensor. We will be referring to them as "type-I" and "type-II" similarly to p-and n-doped silicon structures. Using the extensometry method, three of the four gauges are used to determining the in-plane principal directions e I and e I I. In this newly determined coordinate system, using Equation (II.22), the linear system to solve in order to estimate an applied stress field σ = (σ 1 , σ 2 , σ 3 , σ 12 ) expressed in the chips coordinate system (x 1 , x 2 , x 3 ), Figure II.20, becomes:

R 1 ( θ 1 ) R 2 (θ 2 ) R 3 ( θ 3 ) R 4 (θ 4 ) O θ 1 = 4 5 • e I e I I x 1 x 2 Ψ 1
∆R i R i = (G i,L cos 2 Ψ i + G i,T sin 2 Ψ i )σ 1 + (G i,L sin 2 Ψ i + G i,T cos 2 Ψ i )σ 2 + (G i,N )σ 3 + (G i,L -G i,T )sin(2Ψ i )σ 12 , (II.24)
where i = 1, 2, 3, 4 refers to the corresponding resistance number, and Ψ i stands for the angle between the i th resistance and the first principal direction e I .

At this point, considering Figure II.17, it is possible to take into account eight different configurations as for the four serpentines to use in order to make them a stress sensor. At least in the Figure II.20 case, where serpentines are selected consecutive to each other, i.e. only 45 • consecutive serpentines. This is why a discussion will be held as for the interpretation of the measured data.

II.3.1.2 Optimal parameters of the PSS design

The designing process is based on several criteria. First the resistance value has to be the highest possible in order to fit equipment resolution capability. Second, the sensors dimensions must be as small as possible so that measures would not be too much affected by gradient stresses, such as the stress fields encountered under copper pillars (CPs) for instance [START_REF] Gallois-Garreignot | Chip Package Interactions: Package Effects on Copper Pillar bump induced BEoL Delaminations in[END_REF]. Finally, G L G T +G N ratio is to be maximized for better sensor efficiency and differentiate the in-plane stress orientations.

To do so, the parameters that we will be investigating are presented in Figure II.21. These parameters are unique copper line's width (w), length (l), spacing between two consecutive lines (s) and total serpentine width (w R ). In order to observe the first criterion, type-I and type-II resistances are of the same width, which is the minimum line width allowed by the 65 nm technology node design rules. Indeed, this minimum value is chosen because of the simple fact that in an electrical conductor line, the resistance value grows when its section area decreases following Equation (II. According to this simplified principle, the smaller the section area, the greater the resistance of the wire. As to the serpentines we are willing to design and embed in a test chip, some wire's geometry and dimensions features are prescribed by the designing rules of the concerned technology node. In fact, unlike the case of Figure II.22, BEoL lines and vias are square-shaped, thus the notion of width (w) that was previously brought. However, we do not have any control over the thickness of such circuit lines, being prescribed by the chip's fabrication process. Taking these conditions into account, Table II.4 gathers the different values of w R , w, s and l that were investigated. In Table II.4, arrows link w and s values because of the correlation between these parameters that is imposed by the designing rules. For instance, if a certain copper line width is set, it is not possible to pick any spacing value.

There is a table of some lengths to choose. Thus, according to this table, once a (w, s) couple is fixed, l and w R are browsed among their values. Which makes nine possible couples to investigate. Each of the serpentines was implemented in the previously described FEM model and their resistances and gauge factors were extracted and put in Table II.5. First, five out of nine couples of serpentines of which nominal resistances exceeded 100Ohm were selected. Indeed, if a resistance shift of the order of the percent is to be expected, the higher the resistance the easier it gets to catch the variation and differentiate it from the variability (errors in measure, probing station uncertainty, etc.).

Second, we had to take into account for the imprint criterion. Based on the targeted application (mainly chip/package interactions), dimensions need to be shrunk to around one order of magnitude compared to C65 sensor in order to be compatible with the bumping and pad ones. This will be discussed later in this chapter.

Comparing the final five couples of serpentines that we retained, In this case, the imprint criterion we introduced above prevailed. So, we chose Set 1 3 parameters in order to configure the passive sterss sensor in 28 nm technology node. The serpentines dimensions are recalled in Table II.6. According to these data, the newly developed sensor is expected to be more sensitive than the previous one, and its imprint has been drastically reduced by a factor of 10, which is suitable for a further implementation under a copper pad in flip-chip packaged structures.

II.3.2 Experimental characterisation

Once the optimal dimensions of the PSS determined, it has been implemented on a test chip, at the sixth level of metallisation (which includes low-κ material) in an eight-metal levels stack. The first step was to evaluate the real electric characteristics of the serpentines and their variability as compared to the expected ones.

II.3.2.1 Wafer level measures

To do so, wafer-level resistance measures have been performed on sixty six chips. As expected, two distinct resistance values have been measured, see Fig.

II.24.
At first sight, the values of the resistances differ from the targeted ones, Table II.7, especially for type-I resistance. However, variations remains in the [min,max] range of copper resistivity values given by the technology specifications. Moreover, and as observed in [START_REF] Vianne | Thermo-mechanical characterization of passive stress sensors in Si interposer[END_REF], a large morphological variability is also expected. II.8. This effect is mainly attributed to process variability (chemical mechanical polishing, photolithography, dry etch, etc.). Additional measurements on several wafers would allow to quantify the inter-wafer variability. By consequence, based on this first set of measure, it is clear that, for further studies and similarly to C65 sensor, a tracking and an identification of each sensor during the whole process flow and measurements are mandatory to bypass the variability issue observed here. In order to link electrical values and stress components, gauge factors need to be evaluated. To do so, calibration is performed. In few words, structure is subjected to a controlled stress state thanks to four-point bending tool and four manual probers to perform a Kelvin measure of the resistances. First, as compared with the previous work in 65nm technology node, the expected behaviour is well noticed in this case. Indeed, resistances are to increase when positive stresses are applied along the longitudinal direction of the copper serpentine, and to decrease when it is the transversal one. Thus, the slopes of the curves, which are, according to Eq. (II.24), the gauge factors of the measures structures, are positive in the longitudinal case and negative in the transversal one. experimental results for the 65nm technology node, only the FEM data are presented. Even though the trend has been well reproduced, some values have been overestimated by simulation of about one order of magnitude. Several hypothesis may be drawn: (i) morphological difference between numerical and experimental structures (ii) piezoresistive effects of copper or/and TaN/Ta materials (iii) material properties and behaviour law used for simulation not relevant (especially for copper). At this level of investigations, the weight of each of these items is not well identified. Experimental characterization of Cu serpentine (morphological, grain dimensions) should bring some insights on this topic and will represent the next step of our work.

II.3.3 FEM predictions of the stress field under a corner copper pillar

In order to have an idea of the circumstances under which the PSS would be loaded in perspective of an implementation under a copper pillar of a FC package, a finite element model is built. Moreover, the sensor dimensions are faced with those of the stress field induced by the copper pillar bump.

Further details and methodology description can be found in [START_REF] Gallois-Garreignot | Chip Package Interactions: Package Effects on Copper Pillar bump induced BEoL Delaminations in[END_REF] and [START_REF] Lee | Below 45nm Low-k Layer Stress Minimization Guide for High-Performance Flip-Chip Packages with Copper Pillar Bumping tech[END_REF].

It is a critical step as the mismatch of coefficients of thermal expansion among the different materials is inherent to generation of stresses, and the underfill has not been dispensed yet. Especially at the corner of the chip where the fails due to this step mainly occur, [START_REF] Suhling | Silicon piezoresistive stress sensors and their application in electronic packaging[END_REF][START_REF] Fan | Investigation of the underfill delamination and cracking in flip-chip modules under temperature cyclic loading[END_REF]. In order to embed a model of the PSS under a corner copper pillar, a multiscale approach has been adopted.

Once the problem solved for the macro-model, In order to estimate the general behaviour of the package, and evaluate the stress field in the areas of interest, the plastic behaviour of the copper material has been arbitrarily approximated by a bilinear isotropic hardening law. A value of H/3 is used as for the copper's yield stress, and E/10 for the tangent modulus, [START_REF] Pavlina | Correlation of Yield Strength and Tensile Strength with Hardness for Steels[END_REF][START_REF] Tiryakioğlu | On the relationship between Vickers hardness and yield stress in Al-Zn-Mg-Cu Alloys[END_REF]. With H and E respectively standing for in-house measured copper's hardness and Young's modulus. The result is shown in This said, they are in the range of the stresses applied by FPB in the calibration step. As seen in the previous section, the 28 nm technology node PSS discussed in this work is sensitive in this range of stresses. Moreover, according to these results, it is possible to embed the PSS, or several sensors, thanks to its small size (11µm × 11µm) in some strategical points where the gradient of stress is at its lowest; for instance alongside the CP diagonal at its corners. As for the 65nm PSS, it appears that its dimensions would not allow an accurate implementation under a CP as it would be subjected to the whole gradient of stress.

II.3.4 Outcomes

Following previous development on a passive stress sensor on 65 nm technology node, investigations have been made to optimise a new one in 28 nm technology. This work aims to describe, first, the optimisation work done by simulation to provide better characteristics (geometry, resistance value and sensitivity). Secondly, dedicated experimental measures are performed to quantify the process variability for such device and identify its in-plane gauge factors. Thanks to the 28 nm technology node design rules and the optimisation work, the sensor's dimensions have been drastically reduced compared to the 65 nm one. Moreover, results tend to show that variability remains close to the one observed in 65 nm node. However, tracking the sensor is still required to bypass this issue.

Concerning the gauge factors, calibration was performed and their values were found to be around an order below the numerical estimations. Some hypotheses have been put forward as possible explanations and, however, need to be investigated further. Finally, FEA was performed to simulate the stress field around a corner copper pillar of a flip-chip package. Results justified the range of stresses applied by FPB in the calibration step, and even highlighted some key positions to embed the PSS in order to avoid too steep gradients of stresses. Anyway, even if the sensitivity of such device is still low, their location inside the low-κ layers is an added value compared to the active passive sensors.

II.4 Investigating a TaN stress sensor

As it does not form any compound with copper, tantalum thin films are used as barriers that prevent the diffusion of copper into silicon [START_REF] Holloway | Tantalum as a diffusion barrier between copper and silicon[END_REF]. Moreover, in combination with nitrogen, tantalum nitride (TaN) may be also used as a thin film resistor (TFR). Hence, it is a well studied material in terms of conditions of deposition, whose implementation in a serpentine-like shape would not be problematic.

II.4.1 Motivations

Studying TaN as a replacement for Cu in a passive stress sensor is first motivated by its low TCR, and thus its lower sensitivity to temperature change. Indeed, where copper's temperature coefficient is about 4000 ppm/K at 20 • C [93], tantalum nitride's one is three orders of magnitude lower. In [START_REF] Au | Stability of tantalum nitride thin film resistors[END_REF], the study showed that in some conditions, TaN's TCR, in addition to being linear, is low with approximately ±5 ppm/K.

Another advantage of using TaN over Cu as a serpentine gauge is its higher resistivity. Indeed, ρ TaN = 2.5 Ω.µm3 and ρ Cu = 170 Ω.µm [START_REF] Zhang | Analysis of the size effect in electroplated fine copper wires and a realistic assessment to model copper resistivity[END_REF] at 20 • C. Thereby, for a given Cu serpentine, using TaN instead would multiply its nominal resistance by 70.

II.4.2 Determination of π L

In order to determine TaN resistance change under controlled longitudinal loading, thin layers were deposited in slender bar shapes in a test chip. Table II.11 lists the dimensions of the TaN filaments. The extraction procedure of longitudinal gauge factors is the four-point bending method. Bar samples are cut from the wafer containing the test chips in the longitudinal direction of the TaN deposits. Loading is gradually increased from 0 MPa to +100 MPa and resistance is measured using the Kelvin method between two consecutive loadings.

Kelvin measures at 20 • C of the unloaded resistances are listed in Table II.12. Measures are performed using a forced current of 900 nA, and the results match the theoretical expectations. Indeed, there is a deviation of about 11 -14% between the measured and the expected resistances. As a reminder, the previously developed Cu serpentines type-I and type-II gauge factors are respectivelely π I L = 9.5 TPa -1 and π II L = 6.5 TPa -1 , Table II.7. TaN bars are five times as sensitive than the copper serpentines. R 1 results are also plotted in Fig. II.31. The slope is almost nil. Indeed, as resistance variation is due to the change in the filament length, R 1 being square, and with small dimensions, no resistance shift is measured. In that case, other FPB tests were performed in order to sollicitate R 2 and R 3 in their transverse direction, and no changes were observed either. This result is another advantage of using TaN single bars over Cu serpentines, as they are less sensitive to transverse stresses.

II.5 Conclusion

Within an approach of developing in-situ passive stress sensors, an investigation on using tantalum nitride instead of copper is carried. In addition to having a lower temperature coefficient of resistance, TaN also has a higher resistivity. For resistance variations of the order of 0.1 %, a higher resistance is synonymous of a better measuring precision.

A four-point bending calibration on TaN single bars showed a greater longitunial gauge factor than the studied copper serpentines. Keeping everything in proportion, the advantage of the serpentines being their small spatial imprint. However, if for the 28 nm technology node, the minimum Cu line width is 50 nm, it would be intersting to obtain TaN lines the same width. As resistance is an inverse function of the section area, its value would be greatly increased.

Moreover, the advantage of using a single filament instead of a serpentine is that its transverse gauge factor is negligible. TaN, with its higher resistivity and longitudinal factor, would be a good choice for a PSS implementation.

Contents

Abstract

A seal ring (SR), or commonly referred at as crack-stop (CS), is a key component contributing to a chip's mechanical reliability during its lifespan. It consists of a metallic barrier surrounding the chip, which aims at protecting it from failure, humidity, and other chemical intrusions. Design and optimisation of such structures is quite heuristic, and their validation mainly based on long thermal cycling tests (several thousands hours), thus time consuming. In order to qualify its mechanical resistance to failure directly at silicon level, i.e. without packaging, a four-point bending (FPB) device is evaluated to track cracks into samples.

After developing a robust delamination technique using FPB, various technology node samples containing different seal ring structures are studied. By performing a deep notch on the samples back face instead of the counter-plate's, as usual, a high success rate was observed -the crack would propagate from the pre-notch into the considered BEoL instead of breaking the bar samples.

Unlike the classic FPB test evaluating the resistance to failure of a homogeneous interface in between homogeneous parts, our configuration accounts for a heterogeneous interface (in particular in the SR region). Therefore, this requires a detailed investigation of the force-displacement supplemented with a track of the crack front. To do so, a glass counter-plate is used for a direct, optical, tracking of the crack position. This has been correlated by scanning acoustic microscopy (SAM).

First, a presentation of the different samples, from different technology nodes, and their related crack-stops is given. The second part presents the FPB experimental results and their interpretation is discussed in comparison with a developed analytical model. The third section presents the interests of monitoring the crack's position thanks to a specifically designed new bench, and the steps towards achieving this goal. At last, a discussion is proposed to state on this technique regarding the initial objective.

III.1 Introduction

As introduced in Chapter I, there are various mechanical concerns surrounding the dual Damascene process and packaging steps in the fabrication of a chip. Indeed, during the packaging process, the chip is first diced and separated from the wafer. One of many steps that is prone to triggering micro-cracks at the edges of the chip [START_REF] Gatzen | Dicing challenges in microelectronics and micro electro-mechanical systems (MEMS)[END_REF]. In addition, when mounted on a package, the chip is subject to bending because of the different CTEs at stake. Glue or moulding compound intrusion are also factors emphasising the peripheral micro-cracks.

Hence the introduction of a mechanical barrier surrounding the chip, with no electrical function but to prevent the intrusion of micro-cracks, humidity and other chemicals [START_REF] Chen | Investigation on seal-ring rules for IC product reliability in 0.25-µm CMOS technology[END_REF] into the electrically active part of the chip.

III.1.1 What is a seal ring?

A seal ring, as its name suggests, is a structure surrounding a microchip and a barrier to any intrusion into the chip. Its main function is to ensure the mechanical integrity of the chip at any stage of the processing. A seal ring is then a structure, designed to warrant a chip mechanical integrity from its simple die form to the final IC product. Indeed, even at the dicing step of the fabrication process flow, defects can appear, depending on the sawing method (mechanical dicing, laser grooving, dicing + grooving, etc.). filled with copper as a seal ring. First, because of the design rules, but also because of the die size which is not extensible to the detriment of the number of chips per wafer, thus at the cost of lesser profitability.

Chip

III.1.2 Qualifying a seal ring fracture toughness

From an industrial point of view, in order to characterise the efficiency of a seal ring to arrest any (micro-)crack propagation, available experimental devices are few. Accelerated temperature cycle tests of mounted chips is an indicator of the different failure mechanisms likely to occur during the chip's functioning life [START_REF] Cui | Accelerated temperature cycle test and Coffin-Manson model for electronic packaging in Annual Reliability and Maintainability Symposium[END_REF]. Nonetheless, this approach remains very time consuming, thus expensive. Indeed, in Cui's work [START_REF] Cui | Accelerated temperature cycle test and Coffin-Manson model for electronic packaging in Annual Reliability and Maintainability Symposium[END_REF], up to 1000 cycles, of about 2 hours each, are necessary to derive a Weibull plot of the considered failure. Moreover, failure nature, occurrence, growth and location are uncontrolled and hardly monitored. The crack propagates from the triangular Berkovich tip imprint into the interconnections. In [102], depending on the path of the propagation, the adhesion between copper layers is characterised. Indeed, when delamination principally occurs into the inter-layer dielectrics (ILDs), low-κ and ultralow-κ, the interconnections have a good adhesion. Conversely, if cracking kinks into copper metals or vias, the adhesion is poor (qualitative). Thus, current thin films adhesion techniques are an alternative to investigate adhesion problems in shorter times than thermal cycling, and using standard research laboratory tools. Four-Point Bending (FPB) is well-documented in the literature as a widely used method for estimating the resistance to failure of a interface, usually delamination. As a microchip is a stack of several layers of thin films, the interest of the technique lies in its proven efficiency at the sub-micron scale, [103-106]. Moreover, the interface fracture induced by FPB occurs at the whole sample scale, therefore at a larger scale than that of the seal ring.

Nano-indentation technique has already been used to assess the propagation of micro-cracks into interconnect structures, especially at the low-κ films

w h 1 h 2 L a F/2 F/2
Film 1 Film 2

Figure III.6: Delamination along the interface between two parts, 1 and 2 of height h 1 and h 2 . a is the length of the crack, L the spacing between inner and outer pins, F is the prescribed force at any given time, h i is i th layer's thickness and w is sample width.

In Fig. III.6, we present a schematic of the FPB method used to initiate and propagate a symmetric crack between two thin layers, provided their respective thicknesses are negligible with respect to the bar samples thicknesses h 1 and h 2 .

Consider an assembly made of two parts, as in

G = f (h 1 , h 2 ) L 2 F 2 p E w 2h3 (III.1) with            f (h 1 , h 2 ) = 3η(3-3η+η 2 ) 16(1-η) 3 , η = h 1 h 1 +h 2 , h = (h 1 + h 2 )/2, E = E 1-ν 2 .
In this study, samples are either bulk silicon or chip bars directly cut from a nonthinned wafer. In the case of the diced chip bars, BEoL's thickness (< 10 µm) is negligible compared to silicon's (770 µm). It is then justified to assume that part 2 is always made of silicon. As for part 1, the counter-plate part, either silicon of glass are considered. In both cases, type 1 and 2 thicknesses are equal, h 1 = h 2 = h. Eq. (III.1) becomes

G = 21(1 -ν 2 Si )L 2 F 2 p 16E Si w 2 h 3 . (III.2)
Other beam-based delamination techniques, such as double cantilever beam (DCB) [109] and end-notched flexure (ENF) [110], could be considered. However, DCB and ENF are respectively well suited for mode I and mode II delamination. The advantage of using FPB is that the delamination behaviour at the specimens interface is in mixed mode. A combination of mode I and mode II that is representative of the type of loads the chip is subject to [111].

Regarding nano-indentation (e.g. CSN), several limitations still exist: complex 3D crack path monitoring, qualitative analysis, and the exact amount of induced loading is unknown. Thus, we decide to evaluate this configuration for the characterisation of the seal ring.

III.1.3 Objectives

The main objective of this chapter is to develop an experimental protocol to characterise the resistance of a seal ring to crack propagation. To do so, a crack is initiated and set to propagate in a chip up to the seal ring. We explore and try to characterise how the structure acts as an obstacle to failure, and attempt to determine which load level is necessary for the crack to overcome the SR and its related toughness.

The first section focuses on the elaboration of a robust and efficient FPB samples preparation method. Indeed, in order to obtain a high success rate in the experiments, it is necessary to obtain repeatable results on every type of samples. Inspired by In order to accurately interpret the FPB results, thus bring a better comprehension on the crack growth, an important information is required. Indeed, Eq. (III.1), thus Eq. (III.2), is valid only in the case where we assume that crack propagation is symmetric, and grows accordingly, which is often considered but not always verified experimentally. Wang and Siegmund [114] pointed out the importance of knowing both left and right length of the crack, and proposed the proper equations to derive the interface toughness. Considering the asymmetric crack growth, the second part of this chapter focuses on the development of a method to monitor crack position during the FPB tests.

The third and final section proposes a finite element analysis of the delamination, based on cohesive zone modelling (CZM). This simulation work tends to bring insight for the interpretation of the experimental force-displacement curves, which are more complex in this study than reported in Fig. III.7.

Chapter III. Seal Ring Toughness Characterisation by FPB Tests

III.2 Different technology node samples

In this section, we first describe the considered chip, and its corresponding seal ring, then the sample preparation. Eventually, we present the force-displacement curves obtained experimentally.

III.2.1 Characteristic dimensions per technology node

We consider different seal rings from 40 nm, 65 nm and 90 nm technology nodes in order to evaluate their resistance to a failure. Table III.1 lists some relevant parameters, differentiating the chips, that are characteristic to their respective technology nodes. Firstly, there are two type-90 chip samples where the difference can be found in their respective seal rings. Indeed, after the packaging step of type-90 I chips, a high failure rate was observed. The embedded seal ring was not suited for its dedicated application. Type-90 II seal ring was then introduced. Therefore, introducing the two samples, with a same chip but slightly different at its border, brings information on the precision of the FPB delamination test.

The three chips are made of different metal levels of lines (L x , L z ) and vias (V x , V z ). Type-40 contains 5 thin x-metal layers and 2 z-thick ones, totalling 7 layers, whereas type-65 embeds 5 thin levels as well but only 1 thick metal layer. As for type-90 samples, they embark 4 thin metal layers only. Moreover, another purpose of studying several samples is to evaluate the crack advance by FPB into different media.

In addition to the differences between the amount of their respective metal layers, the difference also lies in their seal rings. Since design rules allow larger lines and vias, the Cu density in the SR region is larger than in the rest of the chip. Finally, as design rules are not the same for each technology node, each embark a SR of a different "size"; "size" corresponding to the total width of a seal ring from a cross section point of view. Normalised by type-65 seal ring's width, types 40 and 90 ones are respectively 3.9 and 1.3 times larger.

Besides their different width, amount of metal layers and copper density, these seal rings differ in their 3D geometry. For confidentiality reasons, only parts of the structures are being shown in the next section's FIB-SEM cross sections. A FPB delamination sample is made of two parts. The first one is a dummy bar, also referred at as the counter-plate, of the same in-plane dimensions than the studied one. It is usually diced from a non-rotated and non-thinned silicon wafer. Hence, its thickness is 775 µm. Finally, in order to initiate and propagate a crack at the desired location, usually towards the weakest interface, a notch is created at the middle of the counter-plate, of several hundred microns deep. This trench is often referred at as the pre-notch. The second part of the FPB sample is diced from the wafer containing the interface of interest. Dauskardt et al. [115] noticed that in multi-layer samples, the crack aims at the weakest interface, then kinks horizontally due to the mixity that is prescribed by FPB [116]. They suggested the use of a ductile layer in order to arrest the crack that was initiated at the pre-notch, to later allow delamination along the weakest interface instead of cutting the bar sample in two halves. To do so, they deposited copper layers on both the plate and the counter-plate, then layer diffusion bonded the two parts applying a normal pressure of 12 MPa under 400 • C for 4 h. In addition, they deposited a thin carbon stripe in the middle of the samples, between the two copper layers, to act as the weakness catching the crack after initiation from the vicinity of the pre-notch. . The difference is in the plate and counter-plate bonding method, which is performed using epoxy resin. The copper layers are replaced by a tough layer of titanium (Ti) of about about 100 nm thick. A narrow and weak gold (Au) stripe of about 60 nm thick, instead of a carbon one, is deposited in order to act as the weakness under the pre-notch.

III.2.2 Samples preparation for FPB tests

When the sample is subjected to FPB, after a certain amount of loading, a crack initiates from the vicinity of the pre-notch then stops at the ductile Au region 1 . In order to grow further, the crack branches from both bottom corners of the gold part 2 then ultimately deviates along the weakest interface with further propagation along this weak interface 3 .

In A pre-notch of about 700 µm is performed at the back side of the studied sample, which is directly glued to the counter-plate using epoxy glue.

Titanium and gold layers deposition being time consuming, this second sample preparation process is preferred. Indeed, directly gluing the bar parts, including thermal cure, and performing the pre-notch at the back face of the product chip is a faster procedure. Plus, the preparation method has already been tested and verified by Raghavan et al. [113].

The initiation and propagation of the crack mechanism is similar to the previous description in Fig. III.9. Crack initiates in the vicinity of the pre-notch which is deep in the back side of the chips bar. It is performed at a depth of 700 ± 25µm of 775 µm total bar thickness. In this work, we observed that performing the deepest pre-notch greatly increased the rate of success of the FPB experiments. In that in near to 100% of the studied samples, we observed delamination into the interface of interest. This was not the case using the former methodology adopted by STMicroelectronics with a 200 to 300 µm deep notch. Table III.2 gathers the total number and dimensions of each chip per bar sample. In addition to their different BEoLs, the three samples embark different size chips and seal rings. Doing so, the spectrum of application of the FPB delamination technique is tested. . It corresponds to a 45 mm spacing between the outer pins, and 25 mm between the inner ones. However, in order to increase the maximum delamination area, which corresponds to the area defined between the inner pins, the latter distance is increased to 35 mm in order to obtain a 5 mm spacing for

III.2.3 Matrix samples

III.3.1.2 Interpretation and assumptions

The absence of a force plateau is a common feature that has been observed for all samples. Instead, we observed linear reaction forces with respect to the prescribed displacement, alternating with force drops. As the crack is expected to advance in a heterogeneous environment, a question arises to determine the signification of the drops, whether it corresponds to the moment the crack advances through a seal ring or not. Indeed, Fig. III.8 shows higher copper density at the perimeter of the chip, which could act as a bigger resistance to the crack growth. We observe that, at the SR region, the delamination mainly occurs between M 4 x and M 5 x metal layers. Meaning that the crack advances through the SR as well. Which implies that the measured signal may contain the imprint of the seal rings. Especially when it comes to the force drops, that could be induced by the crack meeting with a tough interface like a seal ring. However, assuming Chapter III. Seal Ring Toughness Characterisation by FPB Tests a force drop matches with the crossing of a SR is a strong assumption, which is necessary to confirm thanks to monitoring techniques or evaluating the forcedisplacement slopes after each drop. Indeed, due to the presence of force drops instead of plateaus, the crack position during the tests becomes a mandatory information in order to accurately postprocess the force-displacement data. The next section presents an analytical model, developed to estimate the crack length advance for a given force drop.

III.3.2 Analytic model for crack length evaluation

When studiying the bending of slender bars, it is common to consider the Euler-Bernoulli beam theory [65] assumptions: the plane section remains planar and perpendicular to the neutral axis, and the deformed beam angles are smaller than any relevant dimension of the beam.

The studied beams thickness is small compared to their length, see . Indeed, the assembly's thickness, composed of the plate and the counter-plate, is about 1.5 mm. Whereas its length is either 60 mm or 78 mm. Moreover, silicon is the main component of the beams, which is a linear elastic (orthotropic) material. We can then consider the first condition fulfilled.

As for the second condition, the experimental results showed that the maximum applied displacement is about 400 µm. Compared to the part of the assembly which is under bending between the inner pins, we consider the small deformations assumption valid as well.

The equation describing the deflection (w) of the beam subjected to bending is:

E(x)I(x) ∂ 2 w(x) ∂x 2 = M (x) (III.3)
where x is the given position along the length of the beam, E is the material's Young modulus, I is the area moment of inertia of the cross-section, and M is the bending moment.

In order to evaluate the deflection of an assembly of two beams with an asymmetric crack at the interface, we suggest the equivalent model of The cracked beam 1 parts, of length a 1 and a 2 , are considered not playing a role in the bending of the assembly. A beam with equivalent Young modulus and area moment of inertia is assumed instead. In that case, the non-cracked assembly's Young modulus and area moment of intertia are respectively E c and I c , and the cracked area (a 1 + a 2 ) mechanical parameters are those of part 2, ie E 2 and I 2 .

a 1 (E 2 , ν 2 ) (E 1 , ν 1 ) a 2 R 1 R 2 P 2 P 1 L L 0 h 1 h 2 b x z y h 2 b 1 2 3 4 5 P Pivot x =0
x =L 0 The Young modulus and area moment of inertia of a bi-material laminate are presented respectively in Eq. (III.4) and Eq. (III.5).

E c = (E 1 h 1 + E 2 h 2 )(E 2 (h 3 2 + 3h 2 h 2 1 ) + E 1 (h 3 1 + 3h 2 2 h 1 )) -6(h 1 h 2 (E 1 -E 2 )) 2 (E 2 (h 3 2 + 3h 2 h 2 1 ) + E 1 (h 3 1 + 3h 2 2 h 1 ))(h 1 + h 2 ) (III.4) I c = bh 3 1 12 + bh 1   h 1 h 2 + h 2 1 2 + E 2 E 1 h 2 2 2 h 1 + E 2 E 1 h 2 -h 2 + h 1 2   2 (III.5)
The balance of forces implies that

P 1 + P 2 = R 1 + R 2 = P,
where P is the total force measured by the cell force of the experimental setup. However, as the pins supports are mounted on pivot axes, that ensures that the efforts are equally distributed between the left and right pins, ie Chapter III. Seal Ring Toughness Characterisation by FPB Tests

P 1 = P 2 = R 1 = R 2 = P 2
                                   E c I c ∂ 2 w 1 (x) ∂x 2 = P 2 x ∀x ∈ [0, L] E c I c ∂ 2 w 2 (x) ∂x 2 = P 2 L ∀x ∈ L, L 0 2 -a 1 E 2 I 2 ∂ 2 w 3 (x) ∂x 2 = P 2 L ∀x ∈ L 0 2 -a 1 , L 0 2 + a 2 E c I c ∂ 2 w 4 (x) ∂x 2 = P 2 L ∀x ∈ L 0 2 + a 2 , L 0 -L E c I c ∂ 2 w 5 (x) ∂x 2 = P 2 (L 0 -x) ∀x ∈ [L 0 -L, L 0 ] (III.7)
Where the subscripts in w i refer to deflection of the i th part of the assembly as subdivided in Fig. III. [START_REF] Gupta | Ultra low-k dielectric mechanical property characterization in[END_REF].In order to solve Eq. (III.7) and derive the deflection shape of the assembly w(x), we consider the following continuity conditions:

                 w 1 (L) = w 2 (L) = 0 w 1 (L) = w 2 (L) w 2 ( L 0 2 -a 1 ) = w 3 ( L 0 2 -a 1 ) w 2 ( L 0 2 -a 1 ) = w 3 ( L 0 2 -a 1 ) w 3 ( L 0 2 + a 2 ) = w 4 ( L 0 2 + a 2 ) w 3 ( L 0 2 + a 2 ) = w 4 ( L 0 2 + a 2 ) w 4 (L 0 -L) = w 5 (L 0 -L) = 0 w 4 (L 0 -L) = w 5 (L 0 -L) (III.8)
Solving the system of equations is performed using SymPy4 , a Python symbolic mathematics library. Eventually, the obtained solution is presented in Eq. (III.9).

                                                                                                                                         w 1 (x) = - P 12E c I c x 3 + LP E 2 I 2 -L 0 (L -L 0 + a 1 + a 2 ) -a 2 1 + a 2 2 + E c I c L 0 (a 1 + a 2 ) + a 2 1 -a 2 2 4E 2 E c I 2 I c L 0 x w 2 (x) = - LP 4E c I c x 2 + LP E 2 I 2 -L 0 (-L 0 + a 1 + a 2 ) -a 2 1 + a 2 2 + E c I c L 0 (a 1 + a 2 ) + a 2 1 -a 2 2 4E 2 E c I 2 I c L 0 x - L 3 P 12E c I c w 3 (x) = - LP 4E 2 I 2 x 2 + LP E 2 I 2 L 0 (a 1 -a 2 ) -a 2 1 + a 2 2 + E c I c L 0 (L 0 -a 1 + a 2 ) + a 2 1 -a 2 2 4E 2 E c I 2 I c L 0 x + LP E 2 I 2 -4L 2 + 3L 2 0 -12L 0 a 1 + 12a 2 1 + 3E c I c -L 2 0 + 4L 0 a 1 -4a 2 1 48E 2 E c I 2 I c w 4 (x) = - LP 4E c I c x 2 + LP E 2 I 2 L 0 (L 0 + a 1 + a 2 ) -a 2 1 + a 2 2 + E c I c -L 0 (a 1 + a 2 ) + a 2 1 -a 2 2 4E 2 E c I 2 I c L 0 x + LP E 2 I 2 -L 2 -3L 0 a 1 -3L 0 a 2 + 3a 2 1 -3a 2 2 + 3E c I c L 0 a 1 + L 0 a 2 -a 2 1 + a 2 2 12E 2 E c I 2 I c w 5 (x) = P (-3L 0 + x) 12E c I c x 2 + P E 2 I 2 -La 2 1 + La 2 2 + L 0 L 2 -LL 0 + La 1 + La 2 + L 2 0 + E c I c L -L 0 (a 1 + a 2 ) + a 2 1 -a 2 2 4E 2 E c I 2 I c L 0 x + P E 2 I 2 -3L 2 L 0 + 3LL 2 0 -3LL 0 a 1 -3LL 0 a 2 + 3La 2 1 -3La 2 2 -L 3 0 + 3E c I c L L 0 a 1 + L 0 a 2 -a 2 1 + a 2 2 12E 2 E c I 2 I c (III.9)

III.3.2.1 Comparing the analytic model to simple experiments

We considered the four samples listed in Table III.4, subjected to bending with a pin spacing L of 10 mm. [START_REF] Su | Microstructure-mechanical properties correlation in irradiated amorphous SiOC[END_REF] presents the force-displacement curves obtained experimentally compared to the analytical predictions. The latter are obtained using w 1 (L) = w 2 (L) from Eq. (III.9), as the experimental reaction force is measured at the pins of the FPB setup.

Due to a non-linear behaviour at the beginning of the loading, we observe a slight shift of the experimental curves with respect to the analytic ones. However, the curves slopes are in good agreement with theory as they are all quasisuperimposed to Eq. (III.9) past the non-linear part. In Eq. (III.9), we considered two silicon bars with a crack of different lengths at the interface. In addition to then influence of the crack length, its symmetry is also studied. To do so, the full lines are the case where the crack is symmetric, ie the total crack length is equal to a 1 + a 2 = 2a 1 . And dashed ones are used in the case of a fully asymmetric crack, ie where a 2 = 0 mm.

The analytical predictions of the deflection show that for small crack lengths, 0 mm and 1 mm, there is no significant difference between the deflection shapes. First, the more the crack grows, the more we notice the influence of the asymmetry. Indeed, the deflected shape inclines to the side where the crack grows. In addition to being inclined, we notice that the apex in the symmetric crack case is higher than the asymmetric one. However, considering the case presented in this section, we notice that the expected deflections are of the order of less than the thickness of the assembly.

III.3.3 Crack length and energy release rate evaluation

In this section, one experimental force-displacement curve is isolated for more clarity to the reader,

III.3.3.1 Deriving the crack length using the analytic model

The evolution of the measured force, with respect to the prescribed displacement, gives a direct information on the compliance of the assembly and thus, the crack length. It consists of the value of the slope. In order to derive the evolution of the compliance of the sample presented in Fig. III.18, each linear part is extended. We observe that these extensions intersect at the same point to form a new coordinates system, which consists in a shift of the original system by about ( -----→ 12.5 µm, ----→ -1.5 N).

Doing so, it is possible to compare a "linarized" experimental data to an analytic study. Indeed, the analytic model does not take into account any non-linear phenomenon, such as the friction between the pins and the assembly for instance.

In order to estimate the crack length after each force drop, several crack lengths are considered in Eq. (III.9), and the results superimposed to the experimental curve of In Fig. III.19, the crack length is derived from the experimental force-displacement curve. We observe that no matter the symmetry of the crack, the measured force depends on its length only. However, the real crack pattern is comprised between the symmetric and the fully asymmetric analytically derived ones.

The first slope of the experimental curve corresponds to the loading on the notched assembly. As the analytic model considers either a whole assembly or a cracked state of the assembly, the case for a given notch is not considered.

Therefore, the first experimental slope is comprised between the un-cracked and the cracked assembly. The first force drop corresponds to the initiation of the crack from the vicinity of the pre-notch into the BEoL.

The same post-processing is performed on the rest of the type-65 samples. We observe that 90% of the type-65 samples failed before a prescribed displacement of 200 µm, corresponding to a crack advance of about 6 mm. This is the length of a type-65 single chip. Thus, even if we cannot determine the exact nature of the crack, Fig. III.20 suggests that most of the crack leaps are smaller than the chip length. By consequence, the crack stops several times somewhere into the chip, not specifically close to the SR.

These preliminary results suggest that the four-point bending technique may not be suited to study the seal ring's ability to resist against an advancing crack. Instead, as the cracks seem to stop in the middle of the chip, a question arises: is the nature of the BEoL (number of metal layers, density of metal, nature of dielectrics, metal thickness for instance) a decisive factor against the growth of a crack? This question is discussed in the next chapter.

III

III.3.4 Outcomes

Several chips have been assembled to counter-plates in order to study and advancing crack in their respective BEoLs, by the means of four-point bending. Despite applying a constant bending moment, experimental results showed no force plateau, synonymous of a stable crack growth. Instead, we observed a series of crack drops, describing an unstable advance of the cracks. The objective of the experiments being to study the ability of a seal ring to stop a crack growth, the question arises as to the origin of the force drops.

Knowing the crack length at each force drop is a way to bring an element of answer, an analytic model has been introduced in this purpose. The relation between a force drop and the related crack length has been established. However, in order to determine the energy release rate, the crack length is not enough. Indeed, if the advance is symmetric or asymmetric, the energy might be over estimated or underestimated by a non-negligible factor (up to 3 for type-65 samples). Thus, to push further the analysis and understand the mechanisms driving the crack kinematic, a new experimental procedure is developed.

III.4 Modified FPB test: Introducing glass counterplate

In order to interpret the experimental results, measuring the variation of the compliance during crack growth is not sufficient. Thus, in order to monitor the crack advance in real time, a transparent glass counter-plate is introduced.

III.4.1 Introduction of glass

In the manner of Wang and Siegmund [114] work, glass counter-plates are prepared in order to match types 40 and 65 samples dimensions.

The objective being to develop a simple yet efficient crack monitoring method, the first approach consisted in determining whether it is possible to observe the crack through an optical microscope.

First, a type-65 assembly surface is captured using the optical microscope through the transparent glass. The same sample is then subjected to FPB until a force occurs, and another set of captures is carried out in order to compare the surface states before and after the drop. This sequence is repeated four times, four force drops, and the results presented in Fig. III.22 Where we observe the apparition of stripes following each force drop. At this point, if we assume that the stripes correspond to the growing crack front, some conclusions are made:

1. The crack front is not perfectly straight. Indeed, as observed in 3. The crack growth is not symmetric. It advances left after the three first force drops, then right at the fourth one. Moreover, the larger the crack length, the higher the force drop.

However, these assumptions rely on the assumption that the observed stripes represent the crack front. A complementary study is carried out in order to bring elements of response concerning the nature of the stripes. Series of pictures are captured thanks to an otpical-digital microscope before and after each force drop. Black stripes, highlighted in their corresponding loading curve colour when observed.

III.4.2 Scanning Acoustic Microscopy

The previous approach using a transparent glass and an optical microscope is applied on four type-40 and 65 samples, two of each type. After some force drops, the samples are examined through scanning acoustic microscopy (SAM) in order to determine the position and the width of the crack front, by detecting shows that in every sample, the crack propagates on both sides of the pre-notch. We observe that, as previously stated, the crack front is rarely perfectly straight. Moreover, we observe that there are cases where the crack stops in the middle of a chip, and others where is seem to be pinned at its border: the crack-stop region. However, the aim of the SAM analyses is to provide insight about the nature of the optically observed stripes.

III.4.3 Real-time monitoring

Considering the promising results of the previous section, a dedicated experimental bench was set in place in order to monitor crack-growth in a FPB test in real-time. Indeed, even if it allows the location of the crack fronts, trading places of the sample between the FPB tool and the optical microscope is timeconsuming. Using a digital camera (4 M pixels, 25 mm of focal length, 24×36 mm) , we observed the same stripes on the FPB samples than when using an optical microscope, Fig. III.25. In Fig. III.26, we show the set-up that is used to record the crack growth. The camera being more maneuverable than an optical microscope, it is fixed to a support above the bending tool in order to capture the samples surfaces through the class counter-plates. Two computers compose this new bending set-up, one connected to the FPB tool, for the forcedisplacement data acquisition, and the another which the camera is connected to.

III.4.3.1 Monitoring crack growth at the interface of blanket thin films

Simple tests based on samples with blanket ultra-low-κ (ULK) film deposits are first carried out. Due to their porosity, ULK films issues are widely reported and studied in the microelectronics area. In this scope, a first series of FPB tests is carried-out on full sheet deposits samples, composed of a SiCN etch-stop layer and a SiOCH ultra-low-κ film, III.27. 1. The load is linear until a force drop corresponding to a fracture area of 369.69 mm 2 on the left of the pre-notch.

2. Follows a stable crack growth, force plateau at ≈ 20 N, until the total fracture area reaches 495.51 mm 2 (still to the left).

3. The crack stops, the loading becomes linear until another force drop, corresponding to a crack advance to the other right of about 355.4 mm 2 .

4. Another stable crack growth occurs after the force drop. The force plateau is of about 22 N, and the delaminated right area reaches 556.71 mm 2 .

5. After the growth stops, the linear force-displacement regime occurs until a final force plateau, 29 N, where the righ area attains 624.11 mm 2 before the samples breaks entirely. This pattern is observed on the four samples. The crack growth is partially stable, with alternate left-right growth. A direct benefit of using a real-time crack monitoring device is that such a FPB campaign remains exploitable. The statement that "no force plateau" means the data is useless is not true anymore. Indeed, using Eq. (III.10) knowing the left and right crack lengths allows the extraction of the corresponding energy release rate.

In this case, the ERR is found to be of 1. about 2.4 ± 0.2 J/m 2 . Which can explain that, in this study, the crack occurs into the wet ULK layer where its cohesiveness is weakened by humidity.

However, despite the homogeneity of the crack interface (ULK/ULK), we observed crack arrests even far from the inner pins. What could previously be explained by the heterogeneity of the crack interface is no longer sufficient. At this point of the study, one can raise questions about these arrests. As crack growth occurs into the ULK layer, we did not observe any kinking of the crack (thanks to several FIB-SEM cross sections). Such behaviour is however common with thin films [103, 112, 120]: sub-micron film, brittle behaviour, equipment instability among others may explain this non-stable crack growth.

III.4.3.2 Real-time monitoring of crack growth in heterogeneous interface samples

After the testing on a homogeneous interface sample (SiCN/ULK), FPB tests using glass counter-plate under camera recording are carried-out on type-65 samples. In contrast to the SiCN/ULK sample, we notice the same behaviour than with the silicon counter-plate, Fig. III.12a. However, the transparent glass and the camera bring some more information. We observe that the crack growth is indeed sequential:

1. The crack initiates at the vicinity of the pre-notch. Between chips 2 and 3.

2. At the first force drop the crack propagates to the right in the middle of chip 3.

3. At the second force drop the crack grows the other side, until the edge of chip 2.

4. A small drop as a result of a small crack advancing from chip 2 to chip 1 but on half the width of the sample. Crack growth occurs through a seal ring.

5. At the fourth drop, delamination propagates from the middle of chip 3 to the edge of chip 4. Another occurrence of crack going through a seal ring.

Moreover, we can confirm another previously stated assumption, the crack does not systematically advance from a seal-ring to another. A generally observed pattern is that the first crack drops often happen for a crack advance between chips 2 and 3. Once the crack widens from this position, it crosses a whole chip directly to the outer edge of chip 1 or 4. Unfortunately, once the crack is pined close to the SR region of chips 1 a/o 4, it gets closer to the inner FPB pins.

The samples break at this stage.

In order to evaluate the analytic model, the observed crack lengths are inserted in Eq. (III.9), and the corresponding force-displacement are compared to the experimental curve, We notice that, given the crack length, the force-displacement behaviour of the FPB sample is correctly approximated by Eq. (III.9). Consequently, for a given experimental dataset, it is possible to exract the total crack length at any given moment. Yet, the model does not provide anys information concerning the asymmetry of the crack. Hence, due to the scale of the four-point bending (millimetre scale) versus the one of the seal ring (tens of micrometres), no clear output signal has been monitored even with the help of the camera. The SR effect is somewhat lost in the BEoL of the chip.

Even if the F4P is not adapted to evaluate our SR robustness, this work provides relevant information on the crack kinematics when advancing within the BEoL, and also a lot of possible applications in the future. Thus, monitoring crack growth, and its velocity, according to environment effects , influence of patterns in structures (dedicated samples), and fatigue analysis are some of possible future fields of research.

III.5 Conclusion

In this chapter, FPB was used to initiate and propagate cracks into the BEoL of chip products. The aim of the experiments was to assess their respective seal-rings ability to resist to the growth of the cracks.

In the obtained curves, the behaviour of the force, with respect to the prescribed displacement, is a series of force drops. When the crack propagates at the interface of a bi-material, a force plateau is usually obtained due to the constant bending moment that is applied by FPB. The heterogeneity of the BEoL and the force drops suggest a sequential non-stable crack growth. In order to confirm this assumption, an analytic model, derived from the Euler-Bernoulli beam theory, is introduced. Correlations with the experimental curves showed that indeed, the crack growth was not stable, it occurred under the form of several millimetres leaps at each force drop.

As the location of the crack fronts is necessary to determine whether it grows through a seal-ring or not, transparent glass counter-plates have been introduced. Through glass, using an optical microscope, then a digital camera, we managed to build a set-up for real-time crack monitoring. The experiments showed a sequential crack growth in the chip samples, as it was predicted by the analytic model.

Consequently, although it is widely used to characterise adhesion between thin films, the four-point bending technique may not be the most relevant technique to use on chip samples. The high heterogeneity of the chip covers the presence of the seal-ring, at the point no clear specific signal of the structure was observed from the tests.

In order to exclude any effect of the BEoL, the inside of the chip, dedicated samples with seal-ring only surrounding an "empty" chip could increase the reliability of the FPB.

However, the experimental results put the instability of the crack growth to the light. Questions arise concerning the reasons of the sudden crack arrests. The next chapter focuses on the use of finite element models in order to:

1. Reproduce the FPB tests to assess the influence of the heterogeneous BEoL on the growth of a crack.

2. Adopt a local approach to study the influence of the environment surrounding the seal-ring on its capability to arrest cracks.

Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media 123

Abstract

Cohesive zone modelling(CZM) has been widely documented and implemented into the finite element method (FEM) in computational fracture studies. This technique has gained interest in the fracture mechanics community as it consists in a powerful tool to analyse crack initiation and propagation in materials and structures.

CZM is introduced to mimic the failure process in experimental four-point bending (FPB) tests, where a crack is growing into a heterogeneous path composed of the back-end of line (BEoL) of several rows of microchips. A significant assumption is studied: the crack path is composed of alternating strong and weak interfaces, respectively corresponding the the crack progressing through the die's seal ring (SR) and into the low-κ materials of the remaining back-end of line (BEoL).

Unlike the experimental force-displacement curves, the CZM driven analyses show force drops only when the crack advances along the strong interface. In order to gain insight on the ability of a seal ring to arrest the advance of a crack, a local study under small-scale yielding (SSY) conditions is performed. In a matter of strengthening the structure, several parameters are explored such as the copper to oxide ratio in the crack path and copper plasticity.

First, a modelling of the FPB crack growth is presented and the chosen cohesive zone models are discussed. The second part consists in the introduction of the 2D model, under small-scale yielding conditions, that is used for studies of crack growth into homogeneous interfaces. The plastic behaviour of copper is introduced. The third section presents the influence of the stacking pattern in a SR-type structure when considering plasticity of copper.

IV.1 Introduction

In an attempt to apprehend the resistance of a seal ring against the growth of a flaw, four-point bending experiments showed a non stable behaviour in the crack propagation. The crack jumps occurring by several millimetres at once, setting a crack close to a SR then propagating it by a few tens of microns (a SR's width) turned out to be difficult. In this chapter, we explore the possibility of using finite elements in order to bring insight on the FPB tests.

IV.1.1 Linear Elastic Fracture Mechanics

Linear elastic fracture mechanics (LEFM) is the scientific field that deals with flaws in elastic bodies using simplified models and theories. LEFM applies as long as all implied materials are elastic, except for a very small region around the crack tip.

In 1913, Inglis [121] provided the stress concentration factor of elliptical holes in "infinite" plates (the dimensions of the plate being very large with respect to the ellipse) subject to a uniaxial load, Fig.

σ V = σ 1 + 2a b . (IV.1)
The stress concentration factor is then given by the ratio σ V /σ.

We notice that when the flaw is a circle, i.e. when a = b, the stress concentration factor is equal to the well-known value of 3, determined by Kirsch [122].

Inglis' linear elastic solutions for stresses at the vicinity of an elliptical hole predict an infinite stress as the hole becomes infinitely flat and sharp to form a crack. From an atomistic point of view, a crack cannot grow unless the stress at the front exceeds the bonding potential energy of two atoms on either side characterised by a critical stress σ c E π , where E is the elastic modulus of the considered material [123]. As no material can withstand an infinite stress, nor can an infinite stress exist at a crack tip, otherwise every structure would fail under the smallest load, Griffith proposed an energy-based failure criterion to analyse cracks [124].

Consider the problem described in

U = σ : d . (IV.2)
For a linear elastic material in uniaxial tension, Hooke's law gives σ = E and Eq. (IV.2) becomes

U = E d = 1 2 E 2 = 1 2 σ 2 E . (IV.3)
U is primed as it is an energy per unit of volume.

In the case of a crack into an infinite plate, Griffith used Inglis stress analysis of elliptic holes to show that the potential energy of a crack of length 2a and is

U p = - σ 2 2E πBa 2 , (IV.4)
where B is th width of the plate.

Considering V as the plate's volume, Eqs. (IV.3) and (IV.4) add up to form the expression of the strain energy released by a crack of length 2a in an infinite plate according to Griffith:

U = 1 2 σ 2 E V - σ 2 2E πBa 2 . (IV.5)
As the crack results in the creation of two surfaces, considering γ s the surface energy of the material, the energy required to break the atomic bonds to form a crack of length 2a is

U s = 2aγ s B. (IV.6)
In fine, the total mechanical strain energy stored in the system is

U tot = U 0 + U p + U s = 1 2 σ 2 E V - σ 2 2E πBa 2 + 2γ s aB, (IV.7)
where U 0 is the energy of the un-cracked plate.

Consider the current system, an infinite plate of width B containing a crack of length 2a << B and subjected to a constant remote tensile stress σ. In order to

Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media increment the size of the crack by da, there should be enough potential energy to overcome the subsequently created surface energy. Under equilibrium conditions, total energy is independent of the crack growth, the Griffith energy balance expresses as:

dU tot da = dU s da + dU p da = 0 (IV.8)
Solving Eq. (IV.8) using expressions of Eq. (IV.4) and (IV.6) leads to the fracture stress

σ f = 2Eγ s πa . (IV.9)
Later on, Irwin [125] proposed another energy approach for fracture, based on the same principles than Griffith's, but better suited to solve engineering problems. Indeed, as the supplied energy for an increment of crack is experimentally measurable in simple cases, Irwin introduces the concept on energy release rate G expressed as

G = - dU p da , (IV.10)
that naturally leads to 2γ s = G in the Griffit energy balance (Eq. (IV.8)).

In 1957 , Irwin [126] proposed another fracture analysis approach, based on the stress fields around the crack tip by introducing the critical Stress Intensity Factor (SIF) K c defined as1

G c = K 2 c E . (IV.11)
Indeed, using Westergaard's work on the stress field surrounding a crack [127], Irwin came to the conclusion that in a linear elastic body, such fields can be expressed in a (1/ √ r) shape

σ ij = k √ r f ij (θ), (IV.12)
where subscripts i and j stand for the space components x, y and z, k is a constant, f ij are dimensionless functions of θ, r and θ are as described in Fig.

IV.2.
Thus far, we only considered a tensile stress applied perpendicular to a crack. In general, it is possible to apply a load in any direction. In that case, it is possible do decompose the load as a function of the three fundamental loading modes, Fig. As there are three modes of lading, K I , K II and K III are the stress intensity factors, relative to each mode. A convenient way to rewrite Eq. (IV.12) is to replace k by the stress intensity factor. For a given elastic and isotropic material, the modes displacement fields around a crack tip are derived from the stress fields [123]:

IV.3.
                   u x = K I 2µ

IV.1.2 Cohesive Zone Models

Nodes release [128] and virtual crack closure techniques (VCCT) [129] have been used to simulate delamination with the finite element method. However, these techniques may require very refined meshes and considerably complicate the calculations due to the stress distribution related to the release of pairing nodes. Moreover, crack morphology and locations have to be assumed. However, in other approaches, such as in the cohesive zone model (CZM) the crack tip accounts for a cohesive zone, which is not traction free along the fracture process zone. A traction opening profile mimics mechanically the underlying failure mechanism which proceeds in three stages: (i) initiation for a critical traction, (ii) thickening up to (iii) the nucleation of a crack locally for the critical opening, the latter being an intrinsic length scale in this description. This has been pioneered by Barenblatt [130,131], the popular Dugdale model [132] being a particular case.

Within a finite elements description, Hillerborg [133] first considered the formulation in civil engineering problem and later this are been reconsidered in micromechanics problems by Needleman [134,135]. The method is often considered as a crack path "post-diction" and the possible crack trajectories need to be pre-defined (plane normal to the maximum principal direction, grain boundaries, interfaces for instance) even if this can be overcome by implementing "on the fly" cohesive elements (see for instance Remmers et al. [136]) which embedded cohesive surfaces within a partition to unity framework. This is the first method, where the size of the PZ can be explicitly considered. Such description allows to realistically capture fast "unstable" or slow "stable" crack growth and has been successfully confronted to Finite Fracture Mechanics (FFM), see Doitrand et al. [137] for example.

But the main reason CZM is considered in this work, is that it accounts for a non linear-elastic zone, or a cohesive damage zone of length l cz that develops right ahead of the crack tip, and an intrinsic length-scale that allows to define real size of pieces. Moreover, it is well suited for this work as it intends to study interfacial debonding, where no voiding phenomenon is considered for instance. As described in Fig. IV.4, a cohesive zone model links the relative displacement jump, or opening δ, of two points on either side of the cohesive zone surfaces to the necessary traction t. Hence, another advantage of the CZM, is that the behaviour of the separation is governed by constitutive equations, or Traction-Separation Laws (TSLs), which mechanically mimic the localised damage process, and is then dependent on the operating mechanism. It can be assessed experimentally as an example is showed in Réthoré and Estevez [138]. As shown in Fig. IV.4, the area beneath the TSL Φ n equals the energy release rate G IC , in the case the bulk is elastic. From a FEM point of view, the most popular commercial solvers implement cohesive zone elements in a predefined crack path. Nowadays, they consist of zero thickness elements in the chosen path which traction-separation behaviour is user-controlled, see Fig.

IV.5.
Cohesive zone normal and tangential tractions can be either coupled or uncoupled. When in a coupled case, normal and tangential tractions are dependent on both normal and tangential openings. Whereas in the uncoupled case, each traction mode depends on its corresponding opening mode only. It happens when under one-mode loading only (normal for mode I and tangential for mode II). To sum up:

Uncoupled t n = f (δ n ) t t = f (δ t ) Coupled t n = f n (δ n , δ t ) t t = f t (δ n , δ t )
TS laws are largely covered in the literature, depending on specific use. They are of several shapes (polynomial, rigid-linear, bilinear, exponential, ... The exponential TSL is based on a potential Φ that depends on both normal and tangential opening, Eq. (IV.14).

Φ(δ n , δ t ) = Φ 0   1 -1 + δ n δ * n exp - δ n δ * n exp - δ 2 t δ * 2 t   (IV.14)
When the opening mode is pure normal, Φ 0 = Φ n . In an analogous way, Φ 0 = Φ t when the separation occurs in pure mode II. Normal and tangential tractions derive from the potential Φ by differentiation with respect to their respective openings. Which leads to the expressions of Eq. (IV.15):

δ * n = Φ n T n,max exp(1) δ * t = Φ t T t,max ( 1 2 exp(1)) (IV.15)

IV.1.3 Objectives

The objective of this chapter is twofold. Cohesive zone models are used, in one hand, to gain insight on the experimental four-point bend tests and interpret the drops in force-displacement responses. Indeed, we did not quantitatively observe nor measure the impact of a seal ring on the arrest of a crack. On the other hand, we investigate, at a micron-scale, how much can be expected from a seal ring when it is confronted to a crack nearby. To do so, various material parameters, such as yield stress, and designs are evaluated.

Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media

IV.2 Four-Point Bending delamination simulation

In this section, the four-point bending experiments presented in Chapter III are modelled using finite elements with cohesive surfaces laid along the delamination plane. The objective is to take a closer look to the force-displacement curves to try to bring an interpretation to the leaping crack-growth behaviour.

IV.2.1 Homogeneous bi-material interface

First, an attention is brought on the ULK/SiCN layers samples, III.4.3.1. In plane strain conditions, we reproduced the SiCN-ULK FPB samples. The APDL designations of the elements composing the model are:

plane183 elements. Which are 2D quadratic 8-node plane strain structural elements. Silicon and glass parts are modelled using these elements.

mass21 elements to model the FPB pins, represented as punctual contacts.

target169 & contact175 respectively used as slave and master elements with respect to each other, in order to model the contact of the FPB pins to silicon from one side and to glass from the other side. We consider, for simplicity sake that the contact is frictionless.

inter203 element. 2D quadratic 6-node flat cohesive zone elements. Assigned with a bilinear TSL with the parameters Table IV.1.

( Indeed, the aim of this study is not to quantify the normal and tangential contributions of the CZ model, but to understand the differences between fully symmetric and asymmetric crack propagation. Moreover, the chosen coupling of normal and tangential potentials is such as

λ = δ n δ * n 2 + β 2 δ t δ * t 2 ,
where λ is the effective displacement jump for mixed-mode fracture and β is a dimensionless weighting parameter. In this study, β = 1 in order to equalise normal and tangential contributions to the separation of the CZ elements. IV.8 presents the measured reaction force, which is normalised, with respect to the applied displacement. We notice that in both symmetric and asymmetric configurations, the same force plateau is measured. This result is in agreement with the one of Fig. III. [START_REF] Chen | Crystalline SiCN: a hard material rivals to cubic BN[END_REF], where we showed that, analytically, for a given crack length, the same force is measured in both the symmetric and fully asymmetric cases. Though, given every material property is elastic for this calculation, we

Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media indeed verified that the interface ERR derived from the magnitude of the force plateaus matched with the input surface potential of the CZM using Eq. (III.2).

From the obtained force plateau, we however notice that the crack grows faster, with respect to the applied displacement, in the asymmetric configuration. Indeed, the crack reaches the inner pin at 50 µm of prescribed displacement, whereas it still grows in the symmetric configuration. Which can be explained that in the asymmetric case, the allowable crack length is half as much as in the symmetric one.

IV.2.2 Heterogeneous interface

In this section, we examine how delamination proceeds in the case of a heterogeneous interface, actually made of strong and weak interfaces. Indeed, we reproduce the type-65 samples in order to try to clarify the origins of the force drops observed experimentally.

( We consider the symmetric model presented in Fig. IV.9 in which two CZMs represent two interfaces with different surface potentials Φ w and Φ s , where w and s respectively stand for 'weak' and 'strong' interfaces as described in Table IV.2. As we noted in Chapter III, the characterisation and, above all, quantification of the adhesion energies at heterogeneous interfaces is not straightforward. For instance, we can find in Tadepalli, Turner and Thompson work [140] experimental values for Cu-Cu bonds in the range of 3 -30 J/m 2 , depending on the deposited copper shape and patterning. Volinsky et al.

[141] provide some mechanical properties and fracture toughness of low-κ thin films in the range of 0.1 -1.4 J/m 2 . This is why, in this section, several values are chosen, as the interest of this work lies more in the study of the phenomenological aspect of a strong/weak contrast of the debonding interface, rather than in the intrinsic value of its adhesion. The corresponding separation potential, Φ w and Φ s , is, in the same manner as for the exponential TSL, the area below the traction-separation curve, as given by Eq. (IV.16).

Φ n = 1 2 ∆ max T max . (IV.16)
Using the reference parameters (in bold font) of Table IV.2, Fig. IV.11 shows sets of force-displacement curves corresponding to a symmetric crack growing either at a homogeneous interface or at a heterogeneous one. First, we notice a force plateau in each of the homogeneous cases. In the case of the weak interface, when the crack tip hits the inner pins, crack growth is no longer possible, thus the increasing force with respect to the prescribed displacement. However, the force-displacement plot in the case of a heterogeneous interface is different, we notice two force drops from A 1 to B 1 , and from A 2 to B 2 . In order to understand these drops and make the link with the strong interfaces locations, we suggest the plots shown in Fig. IV.12, where the crack length behaviour with respect to the prescribed displacement is highlighted. Thanks to Fig. IV.12, it is possible to correlate the force drops of the heterogeneous case to the moment crack grows through a strong region. Indeed, as the pre-crack -1 mm large -is laid in the weak region, a first propagation is observed with a force plateau corresponding to the homogeneous weak case at F = 2 N/mm. Then, the crack is stopped as it reaches the strong interface -at ∆a = 2 × (w D + w s ) as the crack growth is symmetric. Thus the force increases until reaching point A 1 then an abrupt crack growth, which translates into a force drop B 1 , takes place up to the next strong interface A 2 , causing a second drop B 2 . The transitions from A 1 to B 1 and from A 2 to B 2 are "instantaneous", meaning that debonding in the weak interface occurs instantaneously between consecutive strong ones. Which translates in crack growth at a constant prescribed displacement in Fig. IV.12 (quasi-vertical part of the plot). The last linear increase in the force-displacement plot corresponds to the moment the crack reaches the inner pins of the FBP set-up.

Moreover, back to Fig. IV.11, we also observe that the level of the force at failure of the first strong interface, point A 1 , is F = 5.8 N/mm, while F = 6.3N/mm in the case of the homogeneous strong interface. This is likely to originate from the ratio between the strong interface width, 2×w s = 0.2mm, and its process zone length which is Λ pz E si ∆ 2 max /(2Φ s ) 225 µm, according to the pioneering work of Barenblatt [132] on cohesive forces in a mode-I grack growth. Thus, the process zone of the strong interface is slightly "weakened" as its extent Λ pz is larger than 2× w s .

As described in Table IV.2, we considered several TSL shapes in order to observe their respective influence on the force-displacement curves. Indeed, as the opening potentials are fixed, we varied the opening values, and their respective tractions using Eq. (IV.16). Fig. IV.13 presents the force-displacement curves when the opening ∆ max is varied. [START_REF] Sun | Process technologies for advanced metallization and interconnect systems in International Electron Devices Meeting[END_REF], we notice that the lower the normal opening, the higher the force drops and their respective critical loads. Indeed, according the Eq. (IV. [START_REF] Su | Microstructure-mechanical properties correlation in irradiated amorphous SiOC[END_REF]), for a given potential of separation, the lower the separation the higher the traction. Thus, for a higher tensile stress in the TSL, a higher loading is needed to reach the necessary amount of traction. Moreover, it is worth noticing that in the case ∆ max = 1000 nm, where the critical loads at force drops are the lowest, we recover the plateau of the weak area between the drops. The energy stored during the first force increase is not sufficient to delaminate through the entire weak interface at once, as it is observed in the other cases. Therefore, provided dedicated experimental samples, this result would help calibrate the traction-separation law. The width of the strong interface w s is also discussed and the results are presented in Fig. IV.14. As the real width of a seal ring is about dozens of microns, it is computationally expensive to model it. Thus, varying w s would pull out a tendency as for reducing the parameter. Indeed, we notice that the smaller w s , the lower the critical reaction force before a force drop. In keeping with the observations and analysis of Fig. IV.11 above, we observe that when the strong region, 2 × w s = 1000 µm, is wider than the process zone length, ∼ 225 µm, the force plateau corresponding to the homogeneous crack growth in the strong interface only is reached: the larger w s the higher the peaks and the drops. However, there is no force plateau between consecutive peaks. Indeed, the crack length jumps from a die's edge to another abruptly. IV.15b, we observe a higher influence of the strong interface on the force-displacement curve. Indeed, the higher Φ s the higher the critical loads at force drops. We also notice that for the lowest Φ s , the crack does not jump from a strong interface to another.

Instead, it stops in-between in order to retrieve a stable growth until the next strong region. This behaviour was previously observed when the ratios Φ s /Φ w or σ n,s /σ n,w are small enough. On the other hand, the the value of Φ w does not have a comparable influence on the force-displacement curves. Indeed, as Φ s is high enough, the crack jumps occur from a strong interface to another. Thus, Φ w does not help slower the crack jumps, the whole force-displacement behaviour is then driven mainly by the higher interface.

Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media

IV.2.3 Discussion

From the results of the first part of this chapter, we can raise three topics to discuss:

1. The CZ parameters. We raised the issue of choosing the right set of cohesive parameters in order to reproduce the experiments with the best accuracy. Indeed, the difficulty rapidly arose when switching from the homogeneous to the heterogeneous interface of crack growth. When homogeneous, as the crack growth is energy-driven, the force plateau does not depend on the TSL parameters as long as the area beneath the curve is equal to the desired separation potential. On the other hand, when delamination occurs between two different interfaces, with one stronger than the other, the choice of the TSLs occurred to be decisive. Indeed, the extent of the process zone is Λ pz ∼ E∆ 2 max /(2Φ s ), and the failure becomes dependant of Λ pz /w s :

Λ cz /w s << 1: we obtain similar results than in homogeneous Cu-Cu case, Λ cz /w s ≥ 1: we observe a lower toughness due to the weakening of the process zone by the presence of low-κ.

A much more specific experimental work is needed in order to implement a reverse method to determine the right TSL sets. For instance, studying bar samples with exactly two interfaces of delamination, instead of the complex BEoL of a chip( see Krieger, Raghavan and Staraman work on copper-moulding adhesion for instance in [142]).

2. The CZM approach. In the continuity of the 1 st point above, the whole modelling approach puts the light on the complexity of the crack growth into a BEoL in the FPB experiments. Considering the seal ring as the only "strong" region of the chip has its limits. First as there are no specifically designed samples and experimental results to correlate on. Second as the scale of the seal ring with respect to the die size makes modelling quite challenging.

3. The FPB approach. From the experimental and the modelling results, we come to the conclusion that quantifying the ability of a seal ring to oppose to the propagation by FPB is complex. Indeed, large scale discrepancies are observed between seal ring, die and sample dimensions. One solution, in order to accurately exploit this method, would be studying specifically dedicated samples. The said samples being "empty" dies with no metal layers in the inside and only a seal ring surrounding it. However, from a feasibility point of view, it would necessitate dedicated lithography masks, thus be very expensive. Which leads to the next part of the chapter, where we introduce another approach that consists in modelling crack growth at a seal ring scale.

IV.3 Crack growth modelling at a seal ring scale

In the previous sections,we developed a model to gain insight on the origin of the force drops observed during the four-point bending experiments. However, being the main objective, we now evaluate the resistance of a seal ring to an approaching crack. As the dimensions of the structure, with respect to the experimental samples, do not allow conception of the whole seal ring during FPB, we want to adopt a modelling approach under Small Scale Yielding (SSY) conditions.

Many studies were led assuming SSY conditions in order to get closer to a linear elastic problem, and consider that there exists a region where the asymptotic solution is a good approximation of the true stress/strain/displacement field in terms of 1/ √ r, see Eq. (IV.13). The non-linear effects being confined to a small region around the crack tip.

IV.3.1 Small Scale Yielding assumptions in an elastic Kdominated field

In linear elastic fracture mechanics, a single parameter allows to describe crack tip fields: the stress intensity factor K (K I , K II or K III in case of a dominantly linear elastic material's response). The small-scale yielding, boundary layer approach, is adopted to model the local failure process in front of a mode I crack. When the non-linearity remains confined to the crack tip region, and very small compared to the surrounding structure, the J-integral, see [143,144], provides K in plane strain conditions such as

K = EJ 1 -ν 2 ,
(IV.17

)
where J is the measured strain energy release rate of the crack, E and ν the elastic properties of the considered material. In case of a cohesive zone description of failure, J is the work of separation corresponding to the area under the traction-separation curve.

J = Γ W dx 2 -t • ∂u ∂x 1 ds , (IV.18)
where W 2 is the strain energy density, t is the traction vector, u is the displacement vector and s a small portion of the contour Γ.

IV.3.2 Methodology

The objective of this section is to evaluate the resistance of a seal ring to crack propagation in mode I by accounting for various parameters related to its "architecture": patterning of strong and weak interfaces, their respective lengths, number of metal layers neighbouring the crack plane, their thickness, accounting

2 W = ¯ f 0 ( σ : d ¯ )
Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media

Using this method, one can easily derive the energy release rate corresponding to the crack growth in the process zone. Indeed, we derive G from monitoring K I , K I = f(u(R, θ)) in Eq. (IV.19), using Eq. (IV.11).

In this kind of study, it is also appropriate to monitor the crack length ∆a in order to observe the evolution of K I accordingly . K I = K I (∆a) are known as the resistance curves, or R-curves, and used to describe the nature of a crack, see Appendix A. In order to model crack growth under SSY conditions, we consider delamination occurring at alternating strong and weak interfaces, see Fig. First, both copper and low-κ materials are considered isotropic, linear elastic. Table IV.3 presents the parameters of the study. In order to get closer to the BEoL of an advanced technology node, C028, h is chosen to be equal to the minimum allowed thickness of the designing rules, which is 50 nm. The width of the copper region w Cu , is also equal to the minimum width of a copper via in the x levels of the BEoL, 50 nm. As for the low-κ region, its width w lk is varied in order to sweep through a wide range of copper densities in the analysis. According to Needleman's description [134], total decohesion occurs when equal or greater than the interatomic potential energy is brought into the system to separate the atoms by about seven times their interatomic distance. Copper has face-centered cubic (FCC) lattice with an interatomic spacing equal to 2.8 Å, which leads to an opening ∆ o ∼ 2 nm in the TSL. Therefore, we consider using a bilinear traction-separation law with ∆ max = 10 nm as reference point for both Cu/Cu and low-κ/low-κ cohesive zone models. Indeed, as the lower Patterned Media the opening the higher the tensile stress, choosing a slightly higher length reduces the maximum stress to reach during the opening, Eq. (IV.16). Moreover, ∆ max = 10nm leads to a traction T max = 3000 MPa, which may be considered as the "acceptable" upper limit for ceramics and especially metal families. In order to go on with this validation step, we investigate the influence of changing the value of the opening ∆ max . To do so, we focus on the Cu/Cu interface case with the following openings ∆ max,Cu = {10 nm, 20 nm, 30 nm}. According to Eq. (IV.16), we obtain T max,Cu = {3 GPa, 1.5 GPa, 1 GPa} as the respective maximum traction values in the TSLs. Fig. IV.21 shows the triangular-shaped TSLs chosen for Cu/Cu interfaces. Even if the TSLs are input data of the FE models, we consider that finding the desired shape in post-processing is a guarantee of confidence in a correct input for calculations such as time-step and mesh size. In Fig. IV.22 we notice that in our context, an elastic formulated problem under small-scale yielding conditions, changing the opening value in the tractionseparation law has little to no influence on the measured work of separation. Consequently, in these conditions, the process zone length does not alter the measured energy release rate. Generally, it takes the form of

IV.3.3 Crack growth modelling under SSY conditions

l cz = αE G c T 2 max , (IV.20)
where α is a coefficient that depends on the model. To mention only some papers that have already been cited in this chapter, α = π 8 in Dugdale [132] and Barenblatt [131] work on cracks in perfectly brittle materials. On the other hand, α = 1 in Hillerborg et al. [133] working on crack advance in concrete and soft elastic materials in general.

In Fig . IV.23 we seek to measure the extent of the process zone in our model. To do so, we plot the value of t Cu at the crack tip for the case {∆ max,Cu = 10 nm, T max,Cu = 3 GPa} and measure the distance, ahead of the crack tip, between the CZ elements where traction is respectively null and maximum. In this Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media case we obtain l cz = 0.21 µm. In addition, we notice that the tensile stress distribution in copper follows accordingly. Indeed, a maximum stress of 3 GPa is also measured in Cu at the cohesive zone. Under small-scale yielding conditions and considering material properties elastic, there is no loss nor dissipation in the transmitted efforts during crack growth.

b 2D heterogeneous case

In this section, we focus on a single case in order to explore and observe the possibilities available regarding the choice of TSL. We choose the case where w Cu = 50 nm and w Lk = 50 nm as well, i.e. the crack path is 50 % copper and 50 % low-κ. Therefore, since the thickness of the heterogeneous zone is 50 nm, we choose three opening values for the respective TSLs of Cu and low-κ which are of 10 nm, 20 nm and 30 nm as in the homogeneous case above. Indeed, if we showed that the process zone length did not affect the G c in homogeneous configurations, we intend to extend the conclusion to the heterogeneous case. As Cu/Cu interfaces are of a higher adhesion energy, we consider the crack tip being at these interfaces. At first, we can highlight the flat nature of the obtained R-curves. Indeed, the crack resistance is constant (∼ 8.5 J/m 2 ), thus does not depend on the crack length. Moreover, we explored 5 combinations of TSLs: the first three of which the opening of Cu and low-κ are equal, one where the opening of Cu is smaller than that of low-κ and a last one where it is the opposite. Indeed, the last two cases are investigated in order to study a potential influence of crack bridging in the value of G c . However, no matter the TSLs combinations, we observe that it remains constant.

In order to visualise the bridging during crack propagation in a heterogeneous environment, We notice that in the linear elastic conditions, and considering copper crack front as the whole heterogeneous zone crack front, bridging has little to no influence on the R-curves. Indeed, Fig. IV.26 below shows that the process zone length is more than ten times larger than the Cu part, including as many low-κ parts as well whatever the evaluated TSL parameters. Thus, the current copper pattern is sufficiently large with respect to the process zone length for being independent of it. Therefore, we have explored the parameters in Table IV At first glance, from the linear elastic input data, regardless of the Cu density, we obtain a flat R-curve. Also, the measured ERRs seem linearly dependent on the said density according to Eq. (IV.21) below:

G ef f = dΦ Cu + (1 -d)Φ Lk , (IV.21)
where G ef f is the effective energy release rate previously measured using a 2D model under small-scale yielding conditions, and d stands for copper density. However, this result is valid in this work's context only, ie considering copper parts of 50 nm wide. For a given density, increasing Cu width would eventually result in a higher ERR. Indeed, if the Cu part is several times as large as the process zone length, we would end up measuring Φ Cu . c Outcomes of the elastic modelling analysis In order to identify the CZM parameters that have the greatest influence on the G c measurement, we have varied the values of the openings δ n , and consequently T max , in order to influence the process zone lengths. In simple cases of homogeneous interfaces, we did not observe any noticeable difference in the choice of the TSL. We then carried out the same calculations on heterogeneous cases in order to highlight a probable bridging effect. This said, the conclusions remained the same. On the other hand, we noted an interesting relationship, in our case of elastic materials and small structures with respect to the size of the process zone, which follows a mixture law. The same phenomenon is observed in 3D tests under SSY conditions as well. As a result, we explore the possibility of introducing a non-linear phenomenon in the models: plasticity of copper. Patterned Media

IV.3.3.2 Accounting for copper plasticity in crack growth modelling under SSY conditions

Previously, copper behaviour law was simplified as linear elastic. However, it is expected that such an assumption may lead to unrealistic behaviour. First, the copper plasticity itself is discussed. Indeed, being geometry and integration dependent, its characterisation is tricky. Secondly, its influence on crack propagation is evaluated.

a On Copper plasticity in thin films Following studies on yielding processes and dislocations of copper crystals [148], it has been observed that a connection exists between grain size and σ y [149]. However, size and orientation of copper crystals in the BEoL depend on several factors, some of which are the nature of the tantalum-nitride (TaN/Ta) barrier, dimensions of the Chemical/Physical Vapor Deposits (CVD/PVD) and temperature of annealing (temperature budget).

In order to highlight the influence of the barrier on the nature of the copper crystal, the following is a summary of the combined results of internal studies carried out in parallel with this one at STMicroelectronics. We dispose of six wafers of the following full-sheet stack-up: 750 µm Si -30000 Å TEOS -100 Å TaN/Ta -2250 Å Cu, the difference being the use of six different barrier recipes: N vs Ta density ratios, low vs high bias deposition of Ta (300-500 W), 40 Å TaN-60 Å Ta vs 60 Å TaN-40 Å Ta, etc. For sake of clarity for the reader, and confidentiality for STMicroelectronics, the recipes are simply referred at by digits from 1 to 6. 3 analyses on 30 µm × 30 µm regions on top of each copper deposit. We observe that TaN/Ta barrier recipes 1, 2, 3 and 5 lead to larger copper grain size of about 2 µm. As for the orientation, grain orientation when using recipes 1-4 is mainly along <1 1 1> direction, and <0 0 1> for the remaining ones. We observea direct influence of the annealing recipe on the grain size and orientation with no direct correlation to the structure width. IV. [START_REF] Xu | Internet of Things in Industries: A Survey[END_REF] show that there are several factors influencing the nature of the copper crystal, and thus coppers yield stress σ y . In order to consider a plastic behaviour of copper in a finite element analysis under small-scale yielding conditions, we unfortunately do not dispose of in-house measurements. Table IV.5 presents a non exhaustive list of elastic-plastic mechanical properties of copper from the literature with respect to film thickness and width. Through a wide range of thickness (0.2 -3.3 µm) and width (5 -3000 µm), we can assume that the yield stress of copper in BEoL structures is of about 150 -400 MPa.

Tvergaard and Hutchinson [154] analytically highlight solids plasticity contribution to crack growth resistance, and Lane and Dauskardt [155] experimentally underline copper plasticity in the behaviour of adhesion in interconnection structures of the BEoL. Overall, it is noted that the plastic behaviour of solids significantly increases crack growth resistance in thin films. Here, we carry out a parametric study on the effect of plasticity on crack growth.

In order to study the influence of the plastic component of copper on structures in small-scale yielding conditions, under remote mode-I loading, we consider a bi-linear stress-strain law as illustrated in

=        σ E , σ ≤ σ Y σ Y E + σ -σ Y E T , σ > σ Y , (IV.22)
where an isotropic hardening is considered as commonly observed for copper. The tangent modulus E T = 20 GPa is constant, E = 128 GPa is the elastic modulus of copper and σ Y the yield stress. The choice of a low E T = 20 GPa is made so as to exacerbate any effect of plasticity on crack propagation. First, in order to explore the influence of the yield stress σ Y on crack growth, it would be interesting to determine the threshold stress σ Y,min beyond which (IV.23)

E E T Stress Strain

Y ε σ Y ( , )
In order to estimate the plasticity occurring during the crack growth, we consider the Von Mises criterion [156] with the effective stress σ e being

σ e = 1 √ 2 (σ xx -σ yy ) 2 + (σ xx -σ zz ) 2 + (σ yy -σ zz ) 2 + 6(τ 2 xy + τ 2 xz + τ 2 yz ) 1 2
(IV.24)

As this section deals with crack growth in mode I with a predefined straight crack path, we consider Eq. (IV.23) above in plane strain and at θ = 0:

         σ xx =σ yy = K I √ 2πr
                       σ 1 = σ xx + σ yy 2 + σ xx -σ yy 2 2 + τ 2 xy 1 2
Eq.(IV.25)

= σ yy , First, copper is linear elastic (E = 128 GPa, ν = 0.33), then two yield stresses are considered when copper is considered elastic-plastic following a bilinear strain hardening law (E T = 20 GPa). We first choose the threshold yield stress calculated above such as σ Y,min = √ 3(1 -2 × 0.33) × 1500 883 MPa , and a lower one σ Y = 100 MPa. Fig. IV.31 presents the R-curves corresponding to the mode-I crack advance into the copper medium, under small-scale yielding conditions. In the elastic and the threshold plastic (σ Y,min = 883 MPa) cases, we obtain the same behaviour: a flat R-curve at G = G 0 = Φ 0 corresponding to a brittle advance of the crack. On the other hand, we notice a rising R-curve when yielding occurs at a lower stress value (σ Y = 100 MPa) with respect to the maximum traction of the TSL (T max = 1500 MPa). Indeed, the onset of the crack is 'delayed' and the measured energy release rate G at onset is twice the value of the input surface potential Φ 0 (A-B), correspondingv to an increase in the resistance to fracture. Then, once the crack initiates, both G and ∆a grow with respect to the remote load (B-C) meaning a further resistance to crack and that a plateau is yet to reach. Usually, "dissipation" by plastic deformation is invoked, but we are going to have a closer look into this. As G corresponds to the remote energy release rate, measured at the circumference of the 2D model, see IV. where, in addition to delaying the reaching of T max , the further the crack advances, the more remote energy is necessary to achieve and fulfil the local stress criterion t n = T max , hence the increasing R-curve when σ Y = 100 MPa, see In Figures IV.31 throughout IV.36, we commented the influence of plasticity on the onset of mode-I debonding in a 2D model under small-scale yielding conditions. We observed that when plasticity occurs, part of the energy towards the crack is dissipated, or "shielded", which translates in plastic zone around the crack tip. The consequence of this is that hardening and plastic strain act as a "mechanical fuse" on the cohesive surface, so that the local traction does not attain the onset of debonding T max . Consequently, the remote loading needs to be increased to locally fulfil t n = T max and provide local failure. This analysis can be rephrased within the double criterion approach put forward by Leguillon, see [159]. It was initially devoted to elastic cases in wedges for which the stress concentration is alleviated compared to sharp notches. In that case, both energy and stress criteria need to be fulfilled, simultaneously, to manage to propagate the crack. Analogously, when plasticity occurs, we observed that the energy criterion is reached as soon as remotely J = G 0 , but the stress criterion is fulfilled for a larger load level, due to the development of the plastic zone. The stress condition is necessary as, following the traction-separation law, in order to fully fail, the cohesive element traction needs to reach T max first -over a "sufficient length" which is the process zone length -before decreasing to 0. Thus, we observed crack onset only when both criteria are satisfied: In order to extend our comprehension of the shielding effect of plasticity, we suggest setting the crack into an elastic isotropic copper material, surrounded by elastic-plastic copper stripes. Indeed, after observing the influence of plasticity on a crack evolving in a plastic environment, we propose to see if a similar effect can be found in the case of a crack evolving in an elastic one, but surrounded by plastic zones. To do so, Fig. IV.37 presents the 2D model, under plane strain and small-scale yielding conditions where, on both sides of the crack path, N L × t quantity of elastic-plastic copper is placed. So far, we observed plasticity influence in simple cases of a crack advancing in a homogeneous interface of a linear elastic and elastic-plastic material, under mode-I load and small scale-yielding conditions. Indeed, we highlighted a mechanical fuse effect of the material hardening to delay the reach of the maximum tensile stress T max and then the onset of crack growth, suggesting a double criterion approach. However, predicting crack growth in more complex circumstances is not straightforward. Indeed, when we take it back to study the seal ring of a micro-chip, there are several and different materials at stake, elastic or plastic, stacked into thin layers. Moreover, the structural positioning of the copper lines and vias make the forecast arduous. Hence, using finite element modelling in such complex cases turns to be a convenient solution, at least to improve the resistance to crack advance by optimising the structure of the metal layout. A span of various configurations could be explored and the most promising ones identified.

σ 2 = σ xx + σ yy 2 - σ xx -σ yy 2 2 + τ 2
G ≥ G 0 t n = T max (IV .
In the previous section we showed that, considering specific dimensions and cohesive parameters, plastic energy dissipation contributes to the increase in adhesion. Experimentally, this result has been observed by Tadepalli et al. [140] in the study of patterning on the interface toughness of wafer-level Cu-Cu bonds. Even though the dimensions of the patterns at stake are in the range of 2 -250 µm, the experiments showed a consequent influence when narrowing the dimensions, thus getting closer to our work's length scale (< 0.5 µm). The same phenomenon was observed by Litteken and Dauskardt [160] studying ductile polymer lines width influence on adhesion energy. Therefore, we propose a simple case to study the influence of patterning on crack growth resistance, see To do so, we resume the previous 2D model, see IV.3.3.1b, to study mode I crack growth in small-scale yielding conditions, using the following set of parameters: σ Y = 100 MPa, t = 50 nm, w s = 50nm, E w = 8 GPa. Strong and weak interfaces are respectively governed by Φ s = 15 J/m 2 , Φ w = 2 J/m 2 surface potentials, the cohesive zone model following a bilinear traction-separation law with ∆ max = 20 nm. Doing so, we will be covering several copper densities along the crack path, but adding a plastic behaviour to copper according to Eq. (IV.22), and two configurations: stacked vs. staggered copper vias.

The results are compiled in Fig. IV.41 where the values of the R-curves plateaus are reported for each structure stack. Overall, as it has been shown so far, the measure energy release rate becomes higher when considering plasticity in copper even if the debonding interface is heterogeneous. Even more, the amount of gained toughening depends on the spatial arrangement of copper vias, especially for the lower densities. Indeed, we notice a higher crack resistance when the vias are stacked rather than staggered for d ≤ 33 %. When d ≥ 33 % the debonding energies are equal but still remain higher than the elastic case.

In Fig. IV.42, we observe that the maximum PEEQ attained in both configurations is about the same, i.e. about 4 %. However, the plastic zones are different in shape. Indeed, we notice that when vias are stacked, the pastic zone is quasi in the verticality, following vias connections, of the structure. Whereas in in the staggered structure, the whole it recovers the wole lines and vias. However, we recall that the 2D model is subject to a mode-I remote loading, which can explain the plastic zone developping perpendicularly to the crack path. A direct result is that the vias from both sides of the path are somewhat strengthened by these "columns of plasticity", whereas the staggered gris dissipates a little more on the sides, and therefore reinforces the cohesive vias to a lesser extent.

So far, we have therefore shown the interest of taking into account the plastic behaviour of copper in such a study. We showed that the plastic zone that develops at around the crack tip -whether in a fully plastic or elastic environment with a plastic area around it -can become a shield to its advance. Which inevitably results in better performances when it comes to the ability to strop a crack from growing further. In addition, we carried a preliminary study on the value of a case-by-case study of possible copper dispositions that would further improve this resistance. To expand this work and improve our understanding of these phenomena, studying the effects of dimensions (different according to the technology nodes), materials (probable reinforcement by materials improving the plasticity of copper) or simply the spatial architecture (3D effects included) of the SR would be lines of development.

IV.4. Conclusion

167

IV.4 Conclusion

In this chapter, we used the cohesive zone modelling approach as a tool to bring insight into some experimentally observed crack events. Indeed, in the first part we reproduce four-point bending experiments, see Chapter III, in order to understand the force-drops and, eventually, highlight the role of the seal ring in stopping the sudden spread of the crack. That being said, we adopted a strong and weak interfaces approach, respectively representing cracking in the seal ring and in the rest of the die, which proved to be limited for the analysis of such a small structure immersed in a sample the size of several chips. Although we managed to observe force drops corresponding to the positions of the strong interfaces, but the experiments showed cracks suddenly stopping in the middle of the dies, suggesting an influence of the BEoL in addition to the seal ring. Whereas the observed phenomenon in most cases is a crack jumping from a strong interface to another, growing through the weaker ones quasi-instantly.

As a result, we focused on a local approach consisting of 2D modelling under small-scale yielding conditions. Initially, when considering linear elastic properties of the materials, we varied the ratii of strong over weak interfaces to obtain a "mixture law", see. Eq. (IV.21). However, motivated by the work of Tadepalli et al. [140] and Litteken & Dauskardt [160] on the influence of plasticity in cracking problems, we accounted for copper plasticity to show that, under small-scale yielding conditions, the resistance to crack growth increases with respect to the elastic case. More precisely we showed that, at the debonding interface, reaching the maximum tensile stress T max of the traction-separation is delayed because of the plastic zone surrounding the crack tip. The result being a delay in the crack onset until the remote loading increases enough to allow the element to fail. At this level, we have made an analogy with the work of Leguillon [159] who set out the principles of the "double criterion", see Eq. (IV.32): critical energy release rate and stress criteria along the crack path need to be fulfilled. Eventually, in addition to plasticity, we observed a structural influence of the metal arrangement in its role to oppose to crack growth.

To conclude, we have come up against the complexity of studying a structure such as the seal ring, both experimentally and analytically, but we have established results that can help to move in the desired direction and improve the resistance to failure. Indeed, it appears interesting to assimilate the problem of optimizing the SR to a structural study in which one would seek to favour the plastic zone around the structure.

General Conclusions

The trend in the microelectronics industry is towards miniaturisation, from transistors to the integrated circuit package. This miniaturisation is certainly motivated by economic reasons, but also by the perspectives to gain in performance, power and ergonomics. In early 90s, .8 µm was the transistors gate length at major semiconductor manufacturers. The length has been reduced to 6 nm with a density of integration of 125 million transistors per square millimetre. However, such a transition in not without consequences, as far as it concerns this work, it is particularly true regarding the low-κ dielectrics. This family of materials, although porous and fragile, is essential to ensure the insulation in the circuitry of an increasingly dense BEoL, with increasingly fine lithography. Besides, due to its porosity, it also has a hydrophilic behaviour which greatly reduces its insulation quality. For all these reasons, mechanical stress and integrity are of primary importance in terms of reliability. In a context of affressive competition, reliable product is a key argument for customers.

In this frame, a better understanding of the stresses induced by the fabrication process and optimisation of key structures, such as the seal ring, are mandatory. Thus, the seal ring, the copper interconnection structure that encircles the chip, was implemented to ensure (i) the mechanical integrity of its interior, containing the electrically active part of the die, and (ii) to protect it from moisture intrusion. With a view to evaluating and monitoring in-situ stress fields within the chip, but also optimising this key structure, this thesis is in line with the understanding and assessment of fracture mechanisms occurring in the BEoL. The main objective being to develop characterisation tools, both experimental and numerical, in order to quantify stress variations and study related fails in advanced technology nodes.

In the first part of this work, the accent was put on the measurement of stresses both in the active silicon, the FEoL, and into the passive interconnection layers, the BEoL. To do so, stress sensors were developed and optimised in a view to be integrated in critical parts of the chip, such as below corner bumps (in a flip-chip package type, for instance).

1. Active stress sensors: Single units of the common 6 or 8 resistor rosettelike sensor are studied. Consisting in slender n-type resistors, a parametric study was carried out to study the influence of doping, length and width over their π 11 piezoresistive coefficient. For the designs evaluated here, the outcomes of the study are that (i) we confirm tat lower doping of the resistor leads to a higher coefficient and quantify it, (ii) width does not influence it though, but the narrower the higher the measured resistance, Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media hence the higher ∆R, and (iii) the longer the higher sensitivity. Finally, an other important result was the observed temperature dependence of the resistance value, where an offset of 1 • C generates interpretation errors reaching up to 400 % for a single resistor.

Passive stress sensors:

The main advantage of a passive strain-gage like sensor is its versatility, as it can be embedded in any desired metal level of the BEoL. First, a parametric modelling analysis was performed in order to choose the optimal dimensions, for the considered CMOS28 DRM, of the copper serpentine. The objective of the optimisation problem being to get the highest in-plane gauge factors. Second, the serpentine were embedded in a real product to allow their calibration by the FPB method.

The study showed consistent results compared to CMOS65 node, even though resistance values are two orders of magnitude lower than doped silicon, its low sensitivity may be then a problem for future integration in low-stress applications.

3. TaN passive strain sensors: As a more resistive material and less sensitive to temperature variations, tantalum nitride was investigated in a view to implement serpentine like strain gauges instead of copper. Slender TaN bars, usually implemented in real products to form resistors, were subjected to FPB. Interestingly, a higher gauge factor than copper serpentine is measured, which shows a very promising alternative, provided TaN lines can be processed in the range of copper width (50 nm).

This set of parametric studies made it possible to draw up a classification of the influential parameters with regard to the design and nature (doping, material) of a stress sensor.

In the second part of this thesis, the focus was set on the four-point bending method to initiate and propagate cracks into the BEoL of samples composed of arrays of dies. The main objective of this experimental approach was (i) to observe any influence of the seal ring's presence of the propagation of the crack and (ii) to quantify its toughness. An important result of this experimental work was the developing of a robust samples preparation process that enabled quasi a 100 % success rate in the delamination tests. The two most important parameters that have been highlighted are (1) cutting the silicon wafer into bars using industry lab tools instead of manual cleavage, and (2) performing a very deep pre-notch on the back of the considered sample (and not on the dummy substrate as it is commonly considered).

Because of the high heterogeneity in the BEoL, the force-displacement results suggested an unstable crack growth, occurring in the form of jumps of several millimetres each. Hence, because of the sandwich nature of the samples, two solutions are provided in order to locate the crack front at each leap, allowing to know whether the jump occurs over a seal ring region or not.

could not be assimilated from the model, the relation between a force drop and the subsequent crack length was established.

Experimentally:

The four-point bending test was improved by the introduction of a transparent glass counter plate. Doing so, thanks to a dedicated camera set-up, it was possible to capture the crack front through the glass and monitor its growth in real time. It is an important and valuable result in the interpretation of the force-displacement curves. Specifically, when it comes to the transcription of the measured force to an energy of debonding, the information on both crack lengths, from each side of the pre-notch is crucial. Otherwise, and this was demonstrated on a case where a cohesive crack was developing into an ultra-low-κ film, the estimations are erroneous.

Because the erratic leap of the crack is not controlled, no specific signal of the seal ring structure was observed from the tests. Indeed, the force drops, observed on the force-displacement curves, do no correspond to a crack propagation through the SR. In addition, the crack stops at various chip regions without clear evidence on the SR effect, suggesting the four-point bending technique may not be the most relevant to use on chip samples. The millimetre-scale of the test versus the tens of microns of the SR width seems maladaptive to catch a clear signal: the energy released by the sample during such test greatly exceeds the one occurring for classic fails, those experienced by the SR during the product life. However, this study has lifted important obstacles related to observing the morphology of crack advance in a BEoL-like highly heterogeneous media. Future possible applications are listed after.

The final part of this work introduced cohesive modelling approaches to complement the experimental bending tests. To do so, the debonding phenomena are studied at two scales, (i) from the PFB macro-scale by replicating the experiments and (ii) from a more local view, on the basis of the small-scale yielding conditions.

1. FPB Debonding: By simplifying the experimental samples to two materials only in the BEoL, low-κ and copper, the crack occurs and advances at alternating strong (the seal ring) and weak (the rest of the die) interfaces. Moreover, a parametric study, regarding the considered cohesive law is carried out. It is shown that, because of the complexity of getting correct traction-separation law input unless with dedicated experiments, the assessment of the crack growth remained phenomenological and not quantitative. As a result, it showed that indeed, in the case of a brutal discontinuity in the energies of adhesion at the debonding path, the crack may stop (until the loading reaches a critical force) or instantaneously advance (until it reaches a stronger interface).

SSY Conditions:

The focus was put on debonding occurring at a viametal scale and mimic what occurs in the SR for instance. Under smallscale yielding conditions and elastic only assumptions, it is shown that the toughness of a structure is directly proportional to the strong/weak Patterned Media interfaces ratio. Therefore, based on documented work on the plasticity of copper in interconnection structures, its influence is assessed in a series of parametric studies where material properties (yield stress) and structures (metal patterning) were discussed. An important result of this work was to show that the plasticity of copper is directly related, at the level of the plastic deformation, to a delay in the onset of the crack, i.e. a better adhesion and ability to stop the growth of the crack. Moreover, a postulate based on a double criterion is established: in order to grow, enough energy should be brought to the vicinity of the crack, and a critical stress level has to be reached as well.

This work has highlighted the complexity of studying such an intricate structure like the seal ring, or the BEoL in general, as many interactions occur between material properties, structure design, geometry effect, complex fracture phenomena, all of that being at sub-micron level.

Perspectives

In this work, several interconnect reliability aspects were introduced and studied from the means of estimating a stress field to the optimal design of a crack-stop structure, including the development of an experimental bench for real-time crack growth monitoring. That being said, several aspects arise which constitute areas for improvement of this work. To mention but a few:

• Tantalum nitride was studied as a potential replacement for copper in the serpentine shaped rosette sensors in Chapter II. Considering the positive outcomes, higher thermal and electric resistivity and longitudinal gauge factor, this material should be able to give momentum to this type of rosette sensors to reach levels of sensitivity that would approach that of active resistors, while keeping the advantage of being embedded in the metal levels. Although, in order to gain from active resistors high sensitivity, future implementation should incorporate a coupled temperature sensor, while trying to reduce doping concentration with respect to the considered technology node.

• As a robust sampling and monitoring methodology was proposed in Chapter III to study crack growth via FPB tests, it would be insightful to apply it to pure mode-I by DCB. One can expect a better stability of the crack growth as observed by Raghavan et al. 5 . Moreover, by preparing dedicated samples with seal rings only -no metal between two consecutive structures -an answer could be given as to the toughness of the SR at the scale of a die. The proposed tracking set-up should already bring answers in future work on crack kinematics into controlled environment, such as the influence of humidity on porous low-κ materials toughness.

• Regarding the 2D modelling approach under small-scale yielding that was presented in Chapter IV, it would be interesting to extend the work to 3D cases. A potential start would be to replicate, by modelling, the work of Tadepalli, Turner and Thompson6 on the influence of patterning on the interface toughness of wafer-level Cu-Cu bonds. In concrete terms, it is a set of well-documented tests that one can have the advantage to directly exploit.

Figure I. 1 :

 1 Figure I.1: Evolution of the number of transistors in a single microprocessor during last 40 years. 1

Figure I. 1

 1 Figure I.1 shows the number of transistors embedded in a microprocessor indeed doubling every two years. In 1971 the very first microprocessor, the Intel 4004, included 2308 transistors. Whereas the 32-core AMD Epyc reached 19.2 billion in 2017. Despite the boom in their capacity of integration, microprocessors clock frequency balances around 5 GHz since early 2000. The reason being rather economical than a matter of feasibility. Indeed, Krithivasan et al. managed to produce a silicon-germanium-based transistor capable of oscillating at 510 GHz[START_REF] Krithivasan | Half-terahertz operation of SiGe HBTs[END_REF]. However, a condition to achieve this exploit is to perform the experiment under a cryogenic temperature, liquid helium brought down the temperature to 4.5 K, making it a non-commercial solution. Hence, it is possible to rise clock frequencies, but the cooling mechanisms would be very expensive from a consumer point of view.

Figure I. 2 :

 2 Figure I.2: Evolution of integrated circuits size at STMicroelectronics over 40 years of miniaturisation.

Fig. I. 3

 3 Fig. I.3 is a schematic of a dual in-line package (DIP) microchip. A hole in the product's resin mould reveals the FE and the bonding wires linking the chip's input-output (I/O) channels to the lead-frame legs.

Figure I. 3 :

 3 Figure I.3: Electronic component of type dual in-line package (left) and an STMicroelectronics microchip mounted on a printed card board (right).2

Figure I. 5 :

 5 Figure I.5: Functionning of a p-n junction diode.

Figure I. 6 :

 6 Figure I.6:Schematic of an nMOS transistor and EFTEM 3 view of an actual transistor 4 .

  I.2. The desired function of the IC is provided by the so-called interconnections presented in Fig. I.7.

Figure I. 7 : 8 Interconnections

 78 Figure I.7: Not scaled schematic cross-section structure of a "via-first" CMOS chip.8

Figure I. 8 :

 8 Figure I.8: FIB-SEM 10 cross section of an interconnect. The sealing layer above the BEoL is silicon nitride and silicon oxide (SiN/SiO 2 ). The final passivation layer is a polymer of imide monomers, or polyimide (PI). The solder ball is made of tin-silver alloy (SnAg) and connects the chip to the PCB above.

  Fig. I.9 depicts the plasma enhanced CVD (PECVD) technique, which presents the advantage of using lower temperatures (200 • C-400 • C) with respect to LPCVD. Some of the dielectrics and insulators deposited with CVD: USG, PSG, fluorosilicate glass (FSG -SiO 2 F), tetraethyl orthosilicate, or tetraethoxysilane,(TEOS -C 8 H 20 O 4 Si), silicon nitride (Si 3 N 4 ).

Figure I. 9 :

 9 Figure I.9: Plasma enhanced chemical vapour deposition 11 .

Figure I. 10 :

 10 Figure I.10: Electro chemical deposition.

Figure I. 11 :

 11 Photosensitive resin

Figure I. 12 :

 12 Figure I.12: Chemical-mechanical polishing process.

Figure I. 13 :

 13 Figure I.13: Simplified trench-first dual-Damascene process flow.

Fig. I. 2 ,

 2 BEoL structures play a key role in signal transmission time delays, thus bottleneck to the shrinking scaling logic.

Figure I. 14 :

 14 Figure I.14: Schematic projection of a BEoL part into an RC circuit.i is the electric current emitted by the FEoL and emitted through lines M N-1 and M N . A is the overalapping area between the two lines, and t the thickness of the dielectric.

Figure I. 15 :

 15 Figure I.15: Time delay in ICs depending on the CMOS technology node and the constitutive BEoL materials. (After [13])

FilmFigure I. 16 :

 16 Figure I.16: Cohesive strength as function of (SiO 2 -based) film modulus. (After [21]) Cohesive strength is normalised to 1.5 µm film thickness and at 0.1 µm/s four-point bending load rate.

Figure I. 17 :

 17 Figure I.17: Some CMP-induced chemical and mechanical stress defects.

Figure I. 18 :

 18 Figure I.18: Schematic of the sawing step Dashed white lines delimit the sawing street between dies.

Figure I. 19 :

 19 Figure I.19: Schematic of laser grooving aided mechanical sawing.

Figure

  Figure I.20: WB and FC packages schematics.

  Fig. I.21 presents close looks at cross sections of the two bumps.

Figure I. 21 :

 21 Figure I.21: Cross section at a copper pillar and a solder bump.

  Figure I.22: Typical deflections of a FC package during different assembly steps obtained by FEA and presented at room temperature.First, the substrate presents an initial deflection (red). After the FC step (∼ 230 • C) the deflection switches signs (green). The UF injection (∼ 180 • C) below the silicon die emphasises the bending (blue). Finally, once the metallic lid seals the package (∼ 160 • C) the overall deflection is somewhat flattened, except at the die's edges (black).

Figure I. 23 :

 23 Figure I.23: Cracks in the BEoL after FC assembly flow.

Figure II. 1 :

 1 Figure II.1: Silicon crystal structure. (110) crystallographic plane is highlighted.

Figure II. 3 :

 3 Figure II.3: Variation of π 11 (1 cm 2 /dyn = 10 Pa -1 ) in n-type Si with temperature and doping concentration (atoms/cm 3 ). (After Kanda [60])

Figure II. 5 :

 5 Figure II.5: Kelvin measurement of a stress sensor at different bending stages. Application to a resistance measurement.

Figure II. 6 :

 6 Figure II.6: Variation in in-plane stresses as function of wafer thickness. (After Kumar et al. [69])

( a )

 a Arrangement of the FEoL stress sensors around the copper pillar. (b) Distribution of the change in saturation current, ∆I ON , of the stress sensors for thick Al opening.

Figure II. 7 :

 7 Figure II.7: Embedded sensors arrays under different copper pillar configurations. (After Lofrano et al. [74])

Figure II. 8 :

 8 Figure II.8: Stress induced by TSV at the top of the model, experimental and numerical results. (After Ewuame et al. [47])

Figure II. 9 :Figure II. 10 :

 910 Figure II.9: Three-resistor rosette. 0 -45 -90 degrees configuration.

Figure II. 11 :

 11 Figure II.11: Cross section model of n-type active resistor. R 1 is a fully doped channel resistor, R 2 to R 4 are partially doped, l is the resistors length i.e. the distance between the Sallow Trench Isolation (STI) boxes.

Fig. II. 12

 12 Fig. II.12 shows the results of a technology computer-aided design (TCAD) simulation of the doping process of the resistors (courtesy of Julien Delalleau).A first observation is that the dopant concentration profiles at the center of the partially doped resistors are the same, no matter their length and width.

Figure II. 12 :

 12 Figure II.12: 2D TCAD simulation of doping process along resistors width. (left) R 2 and R 3 resistors of 0.40µm width, (rigth) R 4 and R 5 of 0.26µm. Concentration of dopant in atoms/cm 3 .

Figure II. 13 :

 13 Figure II.13: Wafer-level resistance measures (R in Ohms).

Figure II. 14 :

 14 Figure II.14: Relative variation of resistance as a function of the applied stress in FPB. The slope is used to derive the π 11 coefficients.

Figure II. 15 :

 15 Figure II.15: Doping profiles along resistors length. The curve of R 2 is coincident with R 4 . Dopant concentration is expressed in atoms/cm 3 .

3 R 1 R 4 R 2 Figure II. 16 :

 314216 Figure II.16: Evolution of resistance with respect to temperature and extraction of the temperature coefficients of resistance (TCRs).

  Fig. II.16 describes the behaviour of the resistance with respect to the environment temperature.

Figure II. 18 :

 18 Figure II.18: Finite element model of a copper serpentine (green) as to study resistance shift between constrained and equilibrium states. The blue layer being M3x where the sensor is to be embedded in the test chip.

Figure II. 19 :

 19 Figure II.19: Schematic of the method for determining the sensor's gauge factors. Stresses are applied along the longitudinal, transverse and normal directions of the serpentine, then resistance variations are measured in order to determine each factor separately using (II.23)

Figure II. 20 :

 20 Figure II.20: Schematic of a four-serpentine sensor and the nomenclature used in (II.24).

Figure

  Figure II.21: Characteristic parameters of a copper serpentine.

Figure

  Figure II.22: Shape change in a metallic wire under traction.Neglecting any piezoresistive effect, and applying Eq. (II.25), resistance variation from equilibrium to loaded states can be expressed as ∆R = ρ( L S -L S ).

  Figure II.23: Expression of gauge factors as a function of sets of serpentines and their type.

Figure II. 24 :

 24 Figure II.24: Resistance measurements (Ohms) at wafer level for type -I and type -II serpentines (R i according to II.20)

Fig

  Fig. II.25 and TableII.8. This effect is mainly attributed to process variability (chemical mechanical polishing, photolithography, dry etch, etc.). Additional measurements on several wafers would allow to quantify the inter-wafer variability. By consequence, based on this first set of measure, it is clear that, for further studies and similarly to C65 sensor, a tracking and an identification of each sensor during the whole process flow and measurements are mandatory to bypass the variability issue observed here.

  Figure II.26: FPB tool and micro-controllers.

69 -Figure II. 27 :

 6927 Figure II.27: Resistance variations in comparison to applied stress. From up to down: Type-I, Type-II. From left to right: longitudinal direction, transversal direction.

  Figure II.28: 3D quarter model of a FC Package. Top: Chip (blue) is mounted on a substrate (light blue) by means of copper pillars. Bottom: Imprints of the copper pillars.

  Fig. II.28, the degrees of freedom are extracted around the copper pillar of interest, then applied as boundaries conditions to the micro-model, represented Fig II.29.

  Fig. II.30.According to the symmetry of the problem, stresses along x and y directions are the same. Note that the first principal direction is alongside z direction.

Figure

  Figure II.29: FEM cross section of the micro-model. From up to down: Substrate, Copper pillar (Cu), Passivation, Aluminium pad (Al-pad), Tetraethoxysilane (TEOS), Low-κ, Pre-Metal Dielectric (PMD), Silicon (Si).

Figure II. 30 :

 30 Figure II.30: Stress fields on M6 layer and 28 nm (small 8point star) and 65 nm (big 8-point star) PSS imprints.

  Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses

FigureFigure II. 31 :

 31 Figure II.31 presents the results of the FPB for R 2 and R 3 . At first sigth, in both cases, resistance varies linearly with respect to the applied longitudinal stress. Moreover, both resistors share the same gauge factor as their respective slopes overlay. The averaged gauge factor is found to be π L = 45.7 ± 0.6 TPa -1 .

II. 1

 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . II.1.1 On silicon properties . . . . . . . . . . . . . . . . . II.1.1.1 Crystallography . . . . . . . . . . . . . . II.1.1.2 Elastic properties . . . . . . . . . . . . . II.1.1.3 Piezoresistivity . . . . . . . . . . . . . . . II.1.1.4 MOS stress sensors . . . . . . . . . . . . II.1.1.5 Calibration of a stress sensor . . . . . . . II.1.2 An overview of possible applications . . . . . . . . II.1.3 Objectives of the study . . . . . . . . . . . . . . . . II.2 Parametric study of n-type active resistor-based stress sensors II.2.1 Piezoresistive stress sensor theory . . . . . . . . . . II.2.2 Parametric study of n-type resistors . . . . . . . . . II.2.2.1 nSi resistors parameters . . . . . . . . . . II.2.2.2 Extraction of π 11 coefficients . . . . . . . II.2.3 Outcomes . . . . . . . . . . . . . . . . . . . . . . . II.3 Designing a passive stress sensor in 28 nm technology node II.3.1 Parametric Designing of the Passive Sensor . . . . . II.3.1.1 Stress evaluation methodology . . . . . . II.3.1.2 Optimal parameters of the PSS design . . II.3.1.3 Comparing 65 nm and 28 nm models . . II.3.2 Experimental characterisation . . . . . . . . . . . . II.3.2.1 Wafer level measures . . . . . . . . . . . II.3.2.2 Calibration step . . . . . . . . . . . . . . II.3.3 FEM predictions of the stress field under a corner copper pillar . . . . . . . . . . . . . . . . . . . . . . II.3.4 Outcomes . . . . . . . . . . . . . . . . . . . . . . . II.4 Investigating a TaN stress sensor . . . . . . . . . . . . . . . II.4.1 Motivations . . . . . . . . . . . . . . . . . . . . . . II.4.2 Determination of π L . . . . . . . . . . . . . . . . . II.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure III. 1 :

 1 Figure III.1: Schematic of a seal ring structure. Top view (left) of a chip surrounded by a seal ring, and a cross-section (right) example of its metallic (Cu) structure.

Figure III. 2 :

 2 Figure III.2: Cross sections of two seal rings from different technology nodes. (Scale voluntarily omitted)

  For instance, Fig. III.3 shows the peeling phenomenon: several layers come off in flakes due to the passage of the mechanical saw.

Figure III. 3 :Figure III. 4 :

 34 Figure III.3: Example of peeling, after mechanical dicing, occurring close to the chips seal ring. Optical image of the border of the chip (left) -FIB-SEM view near its seal ring (right).

  [100, 101]. It is an alternative to the thermal cycling tests to appraise the seal ring mechanical integrity. In the microelectronics community, attempts are reported such as in[102]. Fig. III.5 below is an illustration of cross-sectional nanoindentation (CSN) applied close to the interconnect levels of metals, in order to generate and observe the path of a crack (post-mortem).

Figure III. 5 :

 5 Figure III.5: CSN test performed on a 3-metal levels interconnect structure. (After Ocana et al. [102])

  Fig. III.6, subjected to pure bending in between the inner supports. In a typical force-displacement plot in the case of a uniform interface, Fig. III.7, the initial slope is directly related Chapter III. Seal Ring Toughness Characterisation by FPB Tests to the assembly compliance (A). At F = F c (B), part 1 fails at the pre-notch region and further crack propagation is deviated along the interface. A steep slope is then observed. During (C), delamination along the interface proceeds at a constant force F p , when increasing the prescribed support displacement, due to the loss in rigidity [107, 108].

Figure III. 7 :

 7 Figure III.7: Typical force-displacement curve of a FPB test in the case of a homogeneous interface. F c is the critical force at which cracking initiates. F p is the force plateau resulting in a stable crack growth.

Fig. III. 8

 8 Fig. III.8 is an example of the distribution of Cu the type-65 chip. Average data points are available for 50 µm × 50 µm areas of the considered layer. First, we notice a difference between the line and the via layers on the density levels. Indeed, M x Cu density varies in a range of 15 to 80 %, Fig. III.8a, whereas at the via layer it is below 9 %, Fig. III.8b. On the other hand, due to the presence of the seal ring and the I/O ring 3 , the density is higher on the edges than in the interior of the chip.

CharlambidesFigure III. 8 :

 8 Figure III.8: Linear copper density (d Cu ) at metal and via levels of the type-65 chip. (1 data point per 50 µm × 50 µm area)

Figure III. 9 :

 9 Figure III.9: FPB sample for multi-layer delamination. Crack initiates at the vicinity of the pre-crack 1 , stops at the gold stripe then penetrates into the multi-layer stack 2 . The crack grows at the weakest interface 3 .

Fig. III. 9

 9 Fig. III.9 presents the former STMicroelectronics samples preparation and the expected crack behaviour. The samples preparation is similar to the one introduced by Dauskardt et al. [115]. The difference is in the plate and counter-plate bonding method, which is performed using epoxy resin. The copper layers are replaced by a tough layer of titanium (Ti) of about about 100 nm thick. A narrow and weak gold (Au) stripe of about 60 nm thick, instead of a carbon one, is deposited in order to act as the weakness under the pre-notch.

Figure III. 10 :

 10 Figure III.10: Modified FPB samples preparation.A pre-notch of about 700 µm is performed at the back side of the studied sample, which is directly glued to the counter-plate using epoxy glue.

  Depending on the considered chip dimensions, samples are prepared into a grid or matrix arrangement, Fig.III.11.

Figure III. 12 :

 12 Figure III.12: FPB delamination tests Force-displacement curves of types 65 and 40 samples.

  12a

Fig. III. 14

 14 Fig. III.14 shows FIB-SEM images at a corner of a type-40 chip after delamination.First, we observe that delamination occurs into the studied chip BEoL, and not in the silicon or in glue. Knowing that, it is correct to consider that the experimental force-displacement data corresponds to the advance of the crack into the heterogeneous BEoL of the chip. Then, a distinct pattern that has been observed on all sample types, and presented in Fig. III.14, is that the crack growth is not planar. Indeed, the delamination occurs at many levels of the chip, drifting from one to another.

Figure III. 14 :

 14 Figure III.14: SEM image at the corner of a type-40 chip after delamination. A FIB cut is performed at the seal ring in order to show the crack path.

  Fig. III.10 and Fig. III.11

  Fig. III.15.

Figure III. 15 :

 15 Figure III.15: Assembly of two beams with an asymmetric crack at the interface. The assembly is subdivided into 5 parts of different area moments of inertia (I 2 , I c ), and subjected to different bending moments ( P 2 L, P 2 x).

. (III. 6 )

 6 Using Eq. (III.6) into Eq. (III.3) with the notations of Fig. III.15, we obtain:

Figure III. 16 :

 16 Figure III.16: Experimental force-displacement curves of Table III.4 samples, four of each, in comparison with Eq. (III.9).

Figure III. 17 :

 17 Figure III.17: Influence of the crack length and symmetry (full lines)/asymmetry (dashed lines) on the deflection of two assembled beams.E 1 = E 2 = 169 GPa, ν 1 = ν 2 = 0.28, h 1 = h 2 = 0.770 mm, w = 10 mm, L = 10 mm and P = 40 N.

Fig. III. 18 .Figure III. 18 :

 1818 Figure III.18: Isolated type-65 experimental result. The intersecting lines of the linear parts after each force drop intersect at the same point. It is considered the origin of the new system axes.

Fig. III. 18 .Figure III. 19 :

 1819 Figure III.19: Analytic vs experimental comparison of a forcedisplacement curve for a type-65 sample.

  Fig. III.20 is a visualisation of the halting crack advance with respect to prescribed displacement.

Figure III. 20 :

 20 Figure III.20: Crack advance with respect to the prescribed displacement on type-65 samples.

  Fig.III.22 IV, the front looks curvy, with the crack somewhat pinned at the edges of the sample. 2. The crack advances in a halted fashion, as previously suggested, in the pan of a single chip width. Which confirms the interpretation results of Fig. III.20.

Figure III. 22 :

 22 Figure III.22: Evolution of the surface state of a type-65 sample.Series of pictures are captured thanks to an otpical-digital microscope before and after each force drop. Black stripes, highlighted in their corresponding loading curve colour when observed.

Figure

  Figure III.23: SAM analysis of two type-40 and two type-65 samples after FPB and force drops. Sudden change in colour a/o contrast reveals non-contact between two interfaces, in other terms delamination.

Fig. III. 23

 23 Fig.III.23 shows that in every sample, the crack propagates on both sides of the pre-notch. We observe that, as previously stated, the crack front is rarely perfectly straight. Moreover, we observe that there are cases where the crack stops in the middle of a chip, and others where is seem to be pinned at its border: the crack-stop region. However, the aim of the SAM analyses is to provide insight about the nature of the optically observed stripes. Fig. III.24 shows the comparison of SAM and optical microscopy results over a type-65 sample, corroborating the previously stated assumption: the observed black stripes correspond to the position of the crack front. Using a transparent glass counter-plate and a common optical microscope makes tracking the growth of cracks possible.

  Fig.III.23 shows that in every sample, the crack propagates on both sides of the pre-notch. We observe that, as previously stated, the crack front is rarely perfectly straight. Moreover, we observe that there are cases where the crack stops in the middle of a chip, and others where is seem to be pinned at its border: the crack-stop region. However, the aim of the SAM analyses is to provide insight about the nature of the optically observed stripes. Fig. III.24 shows the comparison of SAM and optical microscopy results over a type-65 sample, corroborating the previously stated assumption: the observed black stripes correspond to the position of the crack front. Using a transparent glass counter-plate and a common optical microscope makes tracking the growth of cracks possible.

Figure III. 24 :

 24 Figure III.24: Comparing SAM (top) and optical microscopy (bottom) on a type-65 sample. The real crack-front, determined by SAM, and the observed stripes are superimposed.

Figure III. 25 :

 25 Figure III.25: Capture of the surface of a FPB sample after delamination occurs, using a digital camera vs SAM analysis.

Figure III. 26 :

 26 Figure III.26: Real-time monitoring set-up including a digital camera and a four-point bending tool.

Figure

  Figure III.27: Cross-section of the SiCN/ULK samples.

Fig

  Fig. III.29 presents the evolution of the crack fronts and the corresponding force-displacement curve. The observed crack-growth in the presented sample occurs as follows:

3

 3 Figure III.29: Captures of the evolution of crack growth with respect to the prescribed displacement.

Figure

  Figure III.30: FIB-SEM cross-section after FPB delamination.The crack occurs into the ULK layer, initially 260 nm thick. A platinum layer is deposited before the FIB milling operation in order to obtain a contrasting line/color for a precise thickness measurement.

  Fig. III.31 presents a typical pattern of crack advance vs prescribed displacement that was observed.

Figure III. 31 :

 31 Figure III.31: Type-65 sample crack growth and force drops vs prescribed displacement. The active chips, between the inner pins, are numbered from 1 to 4. The pre-notch is performed between chips 2 and 3.

Figure III. 32 :

 32 Figure III.32: Experimental evaluation of Eq. (III.9) for crack length forecast in the FPB tests

Figure IV. 1 :

 1 Figure IV.1: Elliptic hole in an infinite plate subjected to a uniform stress σ

  Fig. IV.1 with no hole, i.e. a = 0. The associated strain energy density is

Figure IV. 2 :Figure IV. 3 :

 23 Figure IV.2: Polar coordinates ahead of a crack tip in the xy plane.

Figure IV. 4 :

 4 Figure IV.4: Representative diagram of a body with a crack subject to a mode I remote load. Ahead of the visible crack tip, a zone governed by non linear elastic stresses develops, the cohesive zone of length l cz , where the normal stress gradually increases until it reaches t max .

Figure IV. 7 :

 7 Figure IV.7: FE Model for delamination simulation. The asymmetric delamination is presented. For the symmetric one, a half model with symmetric boundary conditions is used.

Fig. IV. 7

 7 Fig. IV.7 presents the FE model used to model the FPB test. It presents the different elements that are introduced above, and uses the mechanical properties Table IV.1. A vertical displacement is applied on the upper pins while the lower ones are constrained such as U y,lef tpin = -U y,rightpin and U x,lef tpin = U x,rightpin in order to reproduce the pivot link of the real FPB test device. Normal and tangential surface potentials are chosen to be both equal to the previously measured ERR of the cohesive delamination in ultra-low-κ, see III.4.3.1.

Figure IV. 8 :

 8 Figure IV.8: Force-displacement response to a growing crack at a homogeneous interface.

Fig.

  Fig. IV.8 presents the measured reaction force, which is normalised, with respect to the applied displacement. We notice that in both symmetric and asymmetric configurations, the same force plateau is measured. This result is in agreement with the one of Fig.III.[START_REF] Chen | Crystalline SiCN: a hard material rivals to cubic BN[END_REF], where we showed that, analytically, for a given crack length, the same force is measured in both the symmetric and fully asymmetric cases. Though, given every material property is elastic for this calculation, we

Figure IV. 9 :

 9 Figure IV.9: Symmetric FEM for FPB delamination at a heterogeneous interface.

Figure IV. 10 :

 10 Figure IV.10: Bilinear TSLs representing the strong and weak interfaces CZMs. Reference ∆ max and T max values are displayed.

2 Figure IV. 11 :

 211 Figure IV.11: Force-displacement behaviour of a growing crack through homogeneous and heterogeneous interfaces. A symmetric propagation is considered. Once the crack length reaches the distance between the inner pins delamination cannot grow further: the force increases accordingly with the prescribed displacement.

Figure IV. 12 :

 12 Figure IV.12: Crack growth with respect to prescribed displacement in studied cases of Fig. IV.11. The strong interfaces and inner pin are displayed along the crack length axis for better visualisation of the location of the crack.

  Figure IV.13: Influence of changing ∆ max on the force displacement curves.

Figure IV. 14 :

 14 Figure IV.14: Influence of changing w s on the forcedisplacement curves.

Lastly, we considered

  varying the values of both the strong and weak surface potentials, Fig. IV.15. Comparing Fig. IV.15a to Fig.

  unit width (N/mm) Prescribed Displacement (µm) Ref. -Φ s = 15 J/m² Φ s = 10J/m² Φ s = 5 J/m² Φ w = 2 J/m² Δ max = 200 nm (a) Varying Φ s . unit width (N/mm) Prescribed Displacement (µm) Ref. -Φ w = 2 J/m² Φ w = 0.1 J/m² Φ w = 0.5 J/m² s Φ s = 15 J/m² Δ max = 200 nm (b) Varying Φ w .

Figure IV. 15 :

 15 Figure IV.15: Influence of changing Φ s and Φ w on the forcedisplacement curves.

Figure IV. 16 :

 16 Figure IV.16: 2D contour of J-integral around a crack tip.

  Fig. IV.16 presents Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media a path around a crack tip, with the notations in the 2D expression of the Jintegral, which was first introduced by Rice [144], in Eq. (IV.18) below:

Figure IV. 17 Figure IV. 17 :

 1717 Figure IV.17 displays a schematic description of the small scale yielding, boundary layer approach. K-displacements are prescribed along the outer boundary R accounting for an initial crack, traction-free surface of opening b null, and a non-linear region of maximum extent r. Practically, the ratio R/r is larger than 200 to ensure the boundary layer assumption.

Figure IV. 19 :

 19 Figure IV.19: Problem corresponding to the resistance to mode I fracture of a heterogeneous interface, corresponding to successive Copper-Low-κ parts.The initial crack front is at x = 0, such as the position of the front when delamination occurs is immediately the crack length. w Cu and w lk are respectively the width of the copper and of the low-κ units. The bulk material is Silicon.

Figure IV. 20 :Δ

 20 Figure IV.20: Measured ERR in response to a mode I load under SSY conditions considering two homogeneous delamination plans: Cu/Cu and low-κ/low-κ.

Figure IV. 22 :

 22 Figure IV.22: Non-influence of the change of opening in the TSL on the measured ERR. Delamination occurs at Cu/Cu interface only. The homogeneous Cu parts are 50 nm thick. Cu and Si materials are considered isotropic and elastic.

Figure IV. 23 :Figure

 23 Figure IV.23: Fracture process zone ahead of the crack tip in the case of delamination occurring at a Cu-Cu interface. The parameters of the TSL are {∆ max,Cu = 10 nm, T max,Cu = 3 GPa}.Ahead of the crack tip, the distance between t n = 0 GP a and t n = T max = 3 GP a describes the process zone length (top). Tensile stress in copper σ yy is distributed accordingly (bottom).

Fig

  Fig. IV.25 shows the resistance curves of the considered heterogeneous case.As Cu/Cu interfaces are of a higher adhesion energy, we consider the crack tip being at these interfaces.

  Figure IV.25: Measured ERR in response to a mode I loading under SSY conditions as function of the crack advanding in a heterogenous Cu/low -κ (50 %/50 %) medium.

  Fig. IV.26 shows the traction value in the cohesive elements, in the manner of Fig. IV.23, at a randomly chosen crack length.

ẟ

  Figure IV.26: Influence of the TSL on the cohesive behaviour of the heterogeneous interface. When ∆ max,Cu = ∆ max,Lk copper and low-κ respective delaminations happen simultaneously. When δ Cu < ∆ max,Lk (resp. ∆ max,Cu > ∆ max,Lk ) copper crack-front is delayed (resp. advanced) regarding low-κ.

Figure

  Figure IV.27: R-curves corresponding to different Cu densities in the heterogeneous zone.

2 )

 2 Figure IV.28: Comparing 2D SSY model predictions of G ef f to Eq. (IV.21).

Fig

  Fig. IV.28 shows the superimposition of the measured ERRs of Fig. IV.27 to Eq. (IV.21). We notice indeed that, in this case of a 2D elastic model, the ERR responds to a 'law of mixtures'.

1 (a) 2 . 2 (b) 1 . 3 (c) 2 .

 122132 Figure IV.29: Tantalum nitride barrier influence on copper micro-structure. Each sub-figure presents average diameter and main orientation <ijk> of the grains in a 30 × 30 µm window.

Fig

  Fig. IV.29 shows the results of Electron BackScatter Diffraction (EBSD)3 analyses on 30 µm × 30 µm regions on top of each copper deposit. We observe that TaN/Ta barrier recipes 1, 2, 3 and 5 lead to larger copper grain size of about 2 µm. As for the orientation, grain orientation when using recipes 1-4 is mainly along <1 1 1> direction, and <0 0 1> for the remaining ones.

  Fig. IV.30 and described in Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media

Figure IV. 30 :

 30 Figure IV.30: Linear elastic and bilinear strain hardening elastic-plastic law.

  , σ zz =2νσ yy , τ xy =τ xz = τ yz = 0. (IV.25)The reason Eq. (IV.25) is expressed with respect to σ yy is because, considering this work conditions and hypotheses, we know that σ yy is directly linked to the tensile stress t n governing the TSL of the cohesive elements underlying the crack path. Indeed, as it is shown in Fig. IV.23 σ yy = t n .(IV.26)Introducing the three principal stresses σ 1 , σ 2 and σ 3 , presented in Eq. (IV.27) below,

  xy

1 2= ( 1 - 3 ( 1 -

 1131 Figure IV.31: R-curve of a mode-I crack advancing in an elastic-plastic copper medium, under SSY conditions. When σ Y = 100 MPa, crack initiation is delayed (A-B) to reach twice the necessary debonding energy.

Figure

  Figure IV.32: Contour along the crack path for J integral estimation.

Figure

  Fig. IV.33 presents the evolution of J estimated at the local path Γ along the crack with respect to the remote energy release rate G. First, in the elastic and threshold yield stress cases, we notice that the local and global energy quantities are equal throughout the mode-I loading. Indeed, the path independence of J is observed. However, when σ Y = 100 MPa, the assumption is no longer true. As it is investigated by Kuang and Chen in [158], J depends on the area of the plastic zone covered by the integral path.

  Figure IV.34: Equivalent plastic strain (z-axis) along the crack path [r, θ = 0] (x-axis). The remote G-load is normalised by G 0 (y-axis). ∆a is the crack length at the final G/G 0 load.

FiguresFigure IV. 35 :

 35 Figures IV.31 and IV.34 show, specifically when σ Y = 100 MPa, that even if the energy criterion is fulfilled, G ≥ G 0 , crack does not systematically grow as a non-negligible plastic zone emerges around the crack tip. Another convenient quantity to monitor in order to bring insight on what mechanisms delay crack onset would be the stress component of the traction-separation law.

Fig. IV. 35

 35 Fig. IV.[START_REF] Du | Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions[END_REF] shows the distribution of t n , with respect to the remote G-controlled mode-I load, along the cohesive elements of the debonding path (θ = 0). The elastic and threshold yield cases superimpose as the same stress distribution is observed in Figures IV.35a and IV.35b. Thus, these two configurations undergo the same stress and energy states. The third one, σ Y = 100 MPa, brings more insight about the traction evolution during loading as a determining factor in delaying crack onset. Indeed, compared to the other two cases where t n reaches T max in the early stages of the loading, at about G/G 0 = 0.25, the traction at the initial crack tip does not reach T max until G/G 0 = 1.

Fig. IV. 36 Figure IV. 36 :

 3636 Fig. IV.36 presents a closer look of Fig. IV.[START_REF] Du | Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions[END_REF] at four loci along the debonding path: r = 0, 0.5, 1, 2 µm. We observe the delay, in the plastic case, to reach T max with respect to the elastic ones. When r ∈ [0, 0.5], the elastic configurations reach T max gradually until the first cohesive element breaks. Past that, brittle crack growth is initiated, the other points ahead of the crack tip brutally reach T max then abruptly drop to 0 (debonding is completed) at G/G 0 = 1, thus the flat R-curves. We observe a slightly different behaviour in the plastic curves,

  Fig. IV.31 .

32 )IV. 3 . 3 . 3 3 Figure IV. 37 :

 32333337 Figure IV.37: 2D SSY model of a crack occurring in a perfectly elastic material surrounded by elastic-plastic copper. The interface and remote material is elastic copper Cu e (E = 128 GPa. The surrounding elastic-plastic material is also copper Cu p (E = 128 GPa, E T = 20 GPa, σ Y = 100 MPa). The thickness of a single stripe of Cu p is t = 200 nm and varied by a factor N S = {0, 1, 2, 3}.

Fig. IV. 38 Figure IV. 38 :

 3838 Fig. IV.38 presents the respective R-curves following the crack progressing at an elastic interface surrounded by different quantities of elastic-plastic copper.The influence of the plastic zone translates in a rising of the R-curve from a flat (elastic case, N S = 0) to an increasing shape. Indeed, we notice that the

Figure IV. 40 :

 40 Figure IV.39: Evolution of the traction component t n of the TSL on the debonding path with respect to the surrounding plastic material size.

Fig

  Fig. IV.40.To do so, we resume the previous 2D model, see IV.3.3.1b, to study mode I crack growth in small-scale yielding conditions, using the following set of parameters: σ Y = 100 MPa, t = 50 nm, w s = 50nm, E w = 8 GPa. Strong and weak interfaces are respectively governed by Φ s = 15 J/m 2 , Φ w = 2 J/m 2 surface potentials, the cohesive zone model following a bilinear traction-separation law with ∆ max = 20 nm. Doing so, we will be covering several copper densities along the crack path, but adding a plastic behaviour to copper according to Eq. (IV.22), and two configurations: stacked vs. staggered copper vias.

  Simplified periodic table of elements.Metalloids frames in red , silicon N-type dopants in green and P-type dopants in pink .

	1	I H 1	II	XIII XIV Metalloids	XV	XVI	XVII	XVIII 2 He
	2	3 Li	4 Be	5 B	6 C	7 N	8 O	9 F	10 Ne
	3	11 Na	12 Mg	13 Al	14 Si	15 P	16 S	17 Cl	18 Ar
	4	19 K	20 Ca	31 Ga	32 Ge	33 As	34 Se	35 Br	36 Kr
	5	37 Rb	38 Sr	49 In	50 Sn	51 Sb	52 Te	53 I	54 Xe
	6	55 Cs	56 Ba	81 Tl	82 Pb	83 Bi	84 Po	85 At	86 Rn
	7	87 Fr	88 Ra	113 114 115 116 117 118 Fl Mc Nh Lv Ts Og
				Peripheral electrons
	Figure I.4:

Table I .

 I

	1: Dielectric materials, their dielectric constants and
	elastic moduli.
	Values are estimations as they depend on the deposition recipes
	and temperature-pressure conditions
	Material Type	κ estimate	E (GPa) estimate
	Free space	1	-
	ULK -porous SiOC(-H)	2-2.5 [14]	3.98-7.42 [14, 15]
	SiOC (low-κ)	3	12 [16]
	FSG	3.3-3.9 [17, 18]	50 [18]
	TEOS,SiO 2	4.1 [18]	72 [18]
	SiCN	5	30-190 [19]
	SiN	7	180 [20]

  xx , σ yy , σ zz , σ yz , σ xz , σ xy ) ≡ (σ 1 , σ 2 , σ 3 , σ 4 , σ 5 , σ 6 ), and ( xx , yy , zz , 2 yz , 2 xz , 2 xy ) ≡ ( 1 , 2 , 3 , 4 , 5 , 6 ).

	Chapter II. Development and Optimisation of In Situ Sensors for the
	Assessment of Process and Package Induced Stresses
	with a Voigt notation of the indices where, in a given Cartesian coordinates
	system where
	(σ As many papers have discussed the elastic properties of silicon with more de-
	scription and accuracy, the main idea is to describe the reasons of the orthotropy
	of silicon.
	As previously stated, (100) silicon wafers are widely used in microchips fabrica-
	tion processes. The natural X-and Y -axes are either aligned with [110] and
	[ 110], the wafer is said to be rotated, or [100] and [010] crystal axes, the wafer
	is then non-rotated, Figure II.2. The rotation of 45 • depends on the expected
	final product as the anisotropy highly affects electrical properties as well.
	[110]
	Y	[010]	(100)
	[110] 45°F
		X
		[100]
	igure II.2: (100) rotated wafer with a notch at an edge in
	order to help identify the X and Y Cartesian directions.
			II.2)

  Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses

	y	P 2	P 2
			L o
	h 2 -h 2		x
		L	L i
	|S|
	P 2
			x
	M	z
	P 2 L
			x

[START_REF] Sun | Process technologies for advanced metallization and interconnect systems in International Electron Devices Meeting[END_REF]

Figure II.4: Four-Point Bending principle with shear and moment diagrams. h is the beam's thickness, with h L o , L o is outer pins spacing, respectively L i is inner pins spacing, L = (L o -L i )/2 and P is the total applied load.

Table II . 1 :

 II1 Length and doping parameters of the resistors.

				3 )
	[48]	4.60	0.40	1 -2 ×10 17
	[75]	4.60	0.40	1 ×10 20
	1	4.60	0.40	1 ×10 20
	2	4.60	0.40	1.586 ×10 18
	3	2.30	0.40	1.586 ×10 18
	4	4.60	0.26	1.586 ×10 18

R Length l(µm) Width w(µm) Doping (atoms/cm

Table II .

 II 2: π 11 factors per type of resistor measured at 20 • C. Rn o π 11 (TPa -1 ) Stdv (±%) R (kΩ) Stdv (±%) Which is consistent with Kanda et al. work, Fig. II.3. Moreover, by definition of the doping process of semiconductors, the lower the doping the higher the resistance, Table II.1 and Table II.2. The reason for different doping concentrations is the fact that the test chips come from different technology nodes: Vianne et al. in 65 nm node, Sart et al. and this work in a 28 nm node. Indeed, the designed resistors must be inline with the rest of the FEoL components process flow. Thus the interest in performing such analyses in different technology nodes.

	1	-171.925	1.298	1.672	2.1
	2	-316.111	1.319	1.134	1.2
	3	-256.115	1.480	0.762	0.5
	4	-322.446	1.297	1.633	0.4
	[48]	-912; -961	-	22	7.1
	[75]	-174.400	0.805	-	-
	(atoms/cm³) the stress sensitivity. Doping concentration p-well STI	Silicide	n-well	Silicide	STI
		0	2		4

As previously observed in

Fig. II.12, the partially doped resistors share the same doping profile along the width direction. In order to have a closer look at these curves, Fig. II.15 represents the doping profiles from another point of view. The cut line is at about 0.575 µm depth beneath silicon's surface, where doping level is the highest, see Fig. II.12.

  .1. Which confirms the measure by manual actuators and the four-points Kelvin technique. Data is gathered at -40 • C, 0 • C, 25 • C, 85 • C and 125 • C. In each case, resistance linearly increases as temperature rises. Compared to TableII.2, there is no direct correlation between the piezoresistance factor π 11 and the value of a resistance's TCR.As an illustration of the importance of this factor, let's consider a hypothetic case where each of the four resistors is subjected to a longitudinal stress σ 100 = 100 M P a and a variation of temperature of 1 • C. Using Eq. (II.21), considering the first order TCR α 1 only, TableII.3 below puts the light on the effect of considering the TCR (∆R/R) or not (∆R/R

* ).

Table II

 II

	R 1	-171.925	2.672	-1.719	0.953	180.5
	R 2	-316.111	1.731	-3.161	-1.430	221.0
	R 3	-256.115	1.158	-2.561	-1.403	182.5
	R 4	-322.446	2.427	-3.224	-0.797	404.3

.3: Considering a resistance's TCR in a 100 M P a [100]longitudinal load and under a 1 • C temperature variation.

Resistance π 11 (T P a -1 ) α 1 ( • C -1 ) ∆R/R * (%) ∆R/R (%) Error (%)

Table II . 4 :

 II4 Investigated features in the parametric optimisation of type-I and type-II copper serpentines.

	w s	l w R
		4 0.35
	Type-I 0.05 0.05	6 1
		8 2
	0.05 0.25 4 0.35
	Type-II 0.15 0.05 6 1
	0.15 0.075 8 2

Arrows indicate correlated width-space values

Lengths in (µm)

Table II . 5 :

 II5 Numerical calibration of the different sets of serpentines: Resistance and gauge factor extraction.

Table II . 6 :

 II6 Optimal dimensions and resistances of Type-I and type-II serpentines in 28 nm technology node.In order to compare the FEA-obtained serpentines to the ones developed in 65 nm technology node by Vianne et al.[START_REF] Vianne | Thermo-mechanical Characterization of Passive Stress Sensors in Si Interposer[END_REF], their main features are summarized in table II.7.

	II.3.1.3 Comparing 65 nm and 28 nm models
	Table II.7: Analytical feautures of 65 nm and 28 nm technology
	nodes passive stress sensors.
		Tech. node		65 nm	28 nm
		R (Ohm)		95	545
	Type-I	G L (×10 -11 P a) G T (×10 -11 P a)		1.24 -0.59	5.98 -3.70
		G N (×10 -11 P a)		-0.83	-1.06
		R (Ohm)		65	420
	Type-II	G L (×10 -11 P a) G T (×10 -11 P a)		1.22 -0.56	10.7 -4.45
		G N (×10 -11 P a)		-0.87	-1.49
		Imprint	130 × 130 µm
			Type-I	Type-II
		l(µm)	w(µm) s(µm) w(µm) s(µm)
		4	0.05	0.05	0.05	0.25
		R(Ohm)	845		420
		w R (µm)	2		2

2

11 × 11 µm 2

Table II . 8 :

 II8 Analytical feautures of 65 nm and 28 nm technology nodes passive stress sensors.In addition, TableII.8 shows that variability is a little greater than for 65 nm sensor, despite the more advanced technology node used. In the 65 nm case, measures were made on 110 PSS where type-I and type-II are respectively composed of 32 and 22 lines, versus 66 PSS in this work, and 22 and 8 lines for type-I and type-II sensors. Chapter II. Development and Optimisation of In Situ Sensors for the Assessment of Process and Package Induced Stresses II.3.2.2 Calibration step

			65 nm		28 nm
			Avg. (Ohm) Stdev. (%) Avg. (Ohm) Stdev. (%)
		R 1	95.67	4.31	1387.9	6.4
	Type-I	R 3 R 5	94.00 95.71	4.22 4.31	1403.3 1375.8	6.6 6.6
		R 7	94.03	4.23	1385.8	6.2
		R 2	65.93	4.20	336.6	8.1
	Type-II	R4 R6	66.04 66.40	4.15 4.17	331.2 337.7	11.0 8.7
		R8	66.02	4.20	329.8	8.1

Table II . 9 :

 II9 Analytical versus Experimentally measured gauge factors (×10 -11 MPa).

			28nm	65nm
		F EM	Exp. R 2 (%) F EM
	Type-I	G L G T -3.70 -0.405 5.98 1.77	97.7 96.7 -0.588 1.24
	Type-II	G L G T -4.45 -0.202 10.7 1.46	95.3 91.5 -0.559 1.22

Table

II

.9 above is a comparison between the expected FEM-obtained gauge factors versus the experimentally determined ones. As there were no relevant II.3. Designing a passive stress sensor in 28 nm technology node

Table II . 10 :

 II10 Characteristic dimensions of the FC Package Chip Substrate

	Dimension (µm) Chip Substrate CP
	Length (x) 6300	17500	-
	Width (y) 6900	17500	-
	Thickness 785.5	870 47.1
	Diameter	-	-

Table II .

 II 11: TaN deposits dimensions.

	Resistor Length (µm) Width (µm) Thickness (µm)
	R 1	2	2	0.038
	R 2	200	2	0.038
	R 3	200	4	0.038

Table II .

 II 12: TaN resistances measures at room temperature.

	Resistor R th (kΩ)	R exp (kΩ) Deviation (%)
	R 1	0.07 0.06 ±0.003	11.3
	R 2	6.58 7.53 ±0.095	14.4
	R 3	3.29 3.75 ±0.022	13.9

Table III . 1 :

 III1 Characteristic dimensions of 40 nm, 65 nm and 90 nm technology nodes. Type-65 Type-90 I Type-90 II

	Parameters Type-40 1 Number of metal levels x 5 z 2	5 1	4	4
	SR width 2 (a.u.)		3.9	1	1.3	1.3
		M x	60	50	83	83
	Cu density in the SR (%)	V x M z	16 71	4 50	5	11
		V z	21	11

  3 , the density is higher on the edges than in the interior of the chip.Type-90 SRs embark the most Cu dense thin levels, containing 83 % Cu against 60 % and 50 % respectively for types 40 and 65, TableIII.1. In all cases, proportion of copper is smaller at thin vias plies down to 16 %, 4 %, 5 % and finally 11 % respectively for types 40, 65, 90 I and 90 II . As for the only two chips with z-level metals, the same tendency is observed.

  this work, in order to study crack propagation into interconnect levels of microchips, samples preparation is inspired byRaghavan et al. work [113].

	Fig. III.10 describes a different samples preparation process that was used in
	this framework.
	Chips wafer
	Pre-notch ~700µm	Counter-plate Epoxy glue Studied BEoL

Table III . 3 :

 III3 FPB delamination test parameters

	Sample width Displacement rate Notch depth Pins spacing
	(mm)	(µm/s)	(µm)	(mm)
	10 -12	0.02	700 ± 25	5 -10
	III.3.1.1 Force-Displacement curves

  .3.3.2 Strain energy release rate of crack growth As shown in the SEM images of Fig. III.14, the crack advance occurs into the BEoL of the chip. Considering the assumptions of the analytic model Sec. III.3.2, the energy release rate for a given crack length is derived in the analytic model developed in [114] by Wang and Siegmund. The aforementioned model has the advantage of taking into account the asymmetric nature of the can be overestimated by 1.5 to 3 times its real value, if one would consider a symmetric crack growth while it is asymmetric instead.

  ). In this work, we focus on bilinear and exponential laws only as they are directly Mechanical TM R18 software is used to produce the finite element models and perform calculations. An example of an exponential TSL is presented in Fig. IV.6 as introduced by Xu and Needleman [139].Figure IV.6: Exponential traction separation law. * superscripts on δ n and δ t are the openings at which maximum traction is reached.

	Chapter IV. Modelling Interface Delamination in Heterogeneous and
							Patterned Media
			ẟ n	t n	ẟ t	t t	n	t
	Figure IV.5: 2D cohesive zone element.
	Subscripts n and t respectively stand for normal and tangential
	phenomena.
	t n t n , max implemented in ANSYS R ẟ n , max Φ n ẟ* n	ẟ n	-ẟ t , max	t t , max -ẟ* t	ẟ* t Φ t		ẟ t , max
					-t t , max

Table IV . 1 :

 IV1 SiCN-ULK FE samples properties

	Elastic properties	Silicon Glass	(E Si , ν Si ) 169 GPa, 0.29 (E gl ,ν gl ) 78 GPa, 0.28
	FPB parameters	Outer pin spacing Inner pin spacing	(L o ) (L i )	45 mm 35 mm
	Bar samples	Silicon bar thickness Glass bar thickness	(t Si ) (t gl )	0.700 mm 0.700 mm
		Surface potential	(Φ n , Φ t ) 2 J/m 2 , 2 J/m 2
	CZM parameters	Maximum opening Process zone length	(∆ max ) (l cz )	0.2 µm 150 µm
		Element size	(l e )	25 µm

Table IV . 2 :

 IV2 Type-65 FE samples propertiesWhile the die's width remains constant, w D = 6 mm, the strong interface width, Fig. IV.9 is varied in order to study its influence on the resistance to failure and related ERR. The said strong interface is at both sides of the die, in order to mimic the behaviour of the seal ring, which is, at this point of the study, allegedly the 'strongest' part of the die. Fig. IV.10 presents the triangular TSLs used for the CZM of the weak and strong interfaces.

	Elastic properties Silicon	(E Si ,ν Si )	169 GPa, 0.29
	FPB parameters	Outer pin spacing Inner pin spacing	(L o ) (L i )	45 mm 35 mm
		Silicon bar thickness	(t Si )	0.770 mm
	Bar samples	Die width	(w D )	6 mm
		Strong region width	(w s ) {0.02, 0.05, 0.1, 0.2, 0.5} mm
		Strong surface potential	(Φ s )	{5, 10, 15} J/m 2
	CZM Parameters	Weak surface potential	(Φ w )	{0.5, 1, 2} J/m 2
		Normal opening	(∆ max ) {0.150, 0.200, 0.500, 1} µm

  IV.[START_REF] Chen | Crystalline SiCN: a hard material rivals to cubic BN[END_REF]. Interfaces being respectively Copper to Copper (Cu/Cu) and Low-κ to Low-κ (lk/lk) interfaces. Being the main components of a BEoL, it makes sense to choose these two materials in a simplified representative model of crack growth into the interconnections levels, the continuum bulk having the elastic properties of a silicon part. Fig IV.19 presents the 2D plane strain model under SSY conditions that is implemented in order to evaluate adhesion at heterogeneous interfaces of low-κ and copper.

	IV.3.3.1 2D crack growth under SSY and linear elastic materials
	under plane strain conditions

Table IV . 3 :

 IV3 Material and interface properties of the 2D delamination model under SSY conditions. First, with a view to validating this model, we explore the two homogeneous cases where delamination occurs at interfaces composed of copper or of low-κ only. To do so, we use the mechanical properties and dimensions presented in TableIV.3 above. The model consists in the presented in Fig. IV.19, except there is no alternate material parts. We recall the thickness of the considered material, Cu or low-κ, is 50 nm.

		Silicon	(E Si , ν Si )	169 GPa, 0.29
	Elastic properties	Copper	(E Cu ,ν Cu )	128 GPa, 0.33
		Low-κ	(E lk ,ν lk )	8 GPa, 0.15 [145]
		Widths	(w Cu , w lk ) 50 nm, (50, 100, 150,
	Dimensions	Thickness	(h)	200, 250, 300, 350) nm 50 nm
		SSY radius	(R)	1000 µm
		Surface potential (Φ Cu , Φ lk )	15 J/m 2 , 2 J/m 2
	CZM parameters	TSL Opening Element size	(∆ max ) (l e ) 12.5 nm (4 elements in (10, 20, 30) nm
				w Cu , Fig. IV.19)
	a 2D homogeneous case

Table IV .

 IV 4 gathers results of another EBSD analysis 4 on copper structures of different dimensions and thermal budgets. Square pads of 80 µm × 80 µm and lines of 1.5, 3 and 7 µm width are deposited on two wafers then subjected to different annealing recipes A and B. The cross-section stack-up is: 750 µm Si -... -570 nm SiOC dielectric -50 nm SiN barrier -330 nm Cu.

Table IV . 4 :

 IV4 Grain average diameter and main crystallographic orientation <u> for two annealing recipes A and B in square copper pad and lines structures.

	Structure Width Annealing A		Annealing B
		(µm)	(µm)	<u>	(µm)	<u>
	Pad	80	4.4	1 1 1	3.1	1 1 1
	Line	1.5	2.3	1 1 1	-	-
		3	2.5	1 0 1	2.6	1 1 1
		7	5.5	0 0 1	4.1	1 1 1
	Fig. IV.29 and Table

Table IV . 5 :

 IV5 Some elastic-plastic mechanical properties of Cu from the literature depending on film dimensions.

	Ref.	Thickness Width Yield stress
		(µm)	(µm)	σ Y (MPa)
	Espinoza et al.	0.2	5	380
	[150]	0.2	10	380
		0.2	20	345
		1	5	160
		1	10	160
		1	20	160
	Hirakata et al.	0.2	0.3	345
	[151]	0.2	0.32	345
		0.2	0.59	345
		0.2	0.98	345
	Lane, Dauskardt	0.3	3000	180
	[152]	3.3		180
	Shen, Ramamurty 0.04	Wafer 676
	[153]	0.25
		0.4
	Eq. (IV.22) below:

Patterson, Alan(12 Sep

2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com 2 TSMC, 2017 IEEE International Solid-State Circuits Conference (ISSCC)

Ewuame, Komi Atchou. Analyse Expérimentale et Numérique des Contraintes Thermomécaniques Induites lors des Procédés Émergents de Fabrication de Puces Électroniques au moyen des Capteurs Embarqués. Diss. Paris Sciences et Lettres, 2016.

Karl Rupp, 40 years of Microprocessor Trend Data. https://www.karlrupp.net/2015/06/40-years-of-microprocessor-trend-data/

c Raimond Spekking / CC BY-SA 4.0 (via Wikimedia Commons)

Energy Filtering Transmission Electron Microscopy

STMicroelectronics internal report. Courtesy of C. Meyer and C. Borowiaak.

Samsung foundry -45 nm,

nm, 90 nm guide.[START_REF] Demiris | Senior residents' perceived need of and preferences for "smart home" sensor technologies[END_REF] Intel 2018 Architecture Day 7 Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017

c Cepheiden / CC BY-SA 4.0 (via Wikimedia Commons), modified.

"IBM Leads in U.S. Patents for Fifth Consecutive Year Capping 1997's Technology Breakthroughs," IBM press releaseJanuary 12, 1998

[START_REF] Amemiya | Electrical trimming of heavily doped polycrystalline silicon resistors[END_REF] Focused Ion Beam (FIB) to perform the milling, with Scanning Electron Microscopy (SEM) to capture the details.

Pronounced low 'k' instead of low 'kappa' by misuse of language.[START_REF] Shwartz | Handbook of semiconductor interconnection technology[END_REF] If not specified, values come from STMicroelectronics internal measurements.

In order to connect FEoL structures to the BEoL, metallic conductors, are deposited in direct contact with silicon. After annealing, deposited atoms mix with Si

to form the silicide, a transition metal on which connection vias are deposited. Examples: W Si 2 , T iSi 2 , N iSi 2 .

It is implied that no exterior load is applied through the four-point bending instrument. Internal and residual stresses, on the other hand, exist.

STMicroelectronics own material and measurement.

For more practicality to the reader, type-xx refers to a xx nm technology node sample

In order not to disclose STMicroelectronics sensitive information, seal rings widths are normalised into an arbitrary unit.

Stands for Input/Output. It consists of a bonding pad chain surrounding the chip and ensuring communication with the outside.

https://www.sympy.org

In plane stress conditions, G c = K

c /E , where E = E/(1 -ν 2 ).

Courtesy of M. Delevant and L. Clément from STMicroelectronics Crolles Physical Characterisation (CarPhy) Laboratory.

[START_REF] Xu | Internet of Things in Industries: A Survey[END_REF] Courtesy of S. Courtas from STMicroelectronics Crolles Physical Characterisation (CarPhy) Laboratory.

Analytically: Derived from the Euler-Bernoulli beam theory, an analytic model is built to evaluate the crack length given the experimental FPBmeasured force drops as input. Although the direction of the crack jump

Raghavan, S. et al. Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability. Engineering Fracture Mechanics 153, 259-277 (2016)

[START_REF] Demiris | Senior residents' perceived need of and preferences for "smart home" sensor technologies[END_REF] Tadepalli, R. et al. Effects of patterning on the interface toughness of wafer-level Cu-Cu bonds. ActaMaterialia 56, 438-447 (Feb. 2008)

Sigmund, O. On the design of compliant mechanisms using topology optimization. Journal of Structural Mechanics 25,493-524 (1997)

Remerciements

as pu me fournir.

III.3 FPB delamination tests

Types 40, 65 and 90 samples are prepared according to the previously introduced process. In this section we present the raw experimental results, the resulting force-displacement curves, and suggest interpretations as for the observe crack propagation behaviour.

III.3.1 Delamination tests results

Different parameters of the FPB delamination experiment have been studied and compared in [117] and [112]. The influence of notch depth, loading rate, sample width and pin spacing is reported. Based on their comments and suggestions, we used a displacement rate at the minimum allowable rate of the machine, which is 0.02 µm/s. Pin spacing, as defined in Fig. III.6, is either 5 mm or 10 mm. The outer pins spacing is fixed to 45 mm, whereas the inner one is either 25 mm or 35 mm. As introduced in the above section, samples width is somehow dependent on their individual chip size. It is chosen to be around 10 mm. As for the notch depth, it is recommended to be "as deep as" possible in order to reduce the initial rigidity of the assembly. A 700 µm deep notch is performed using a circular diamond saw with an accuracy of ±25 µm. The difference between types 90 I and 90 II lies in their respective seal rings. We observe that the FPB results show no clear distinction between the two types. Indeed, even if no force plateau is observed, we do not consider that there are two separate populations.

where ξ = (E 2 I 2 )/(E c I c ), and I = I c /b is the dimensionless moment of inertia of the assembly.

In Eq. (III.10) P corresponds to the force plateau at which the crack advances. However, as experimentally observed, the crack growth is unstable, resulting in halting force drops. In order to derive the corresponding energy release rate, we consider the highest force before the drop. We observe that the nature of the crack growth is critical in the evaluation of the released strain energy at each force drop. for plasticity of copper in the metal layers. To do so, we choose finite element modelling using cohesive models.

In Fig . IV.18 we present a schematic of the implemented FEM. It consists in a circle of radius R with a pre-existent flat crack of length R. As it represents the K-dominated field, it is of a linear elastic material (E, ν). Ahead of the crack tip, there is a confined inelastic region of dimensions l, t (l, t R), in which it is possible to represent the desired inelasticity (different materials (E i , ν i ), several crack interfaces Φ sep,i and plasticity). For instance, to study crack growth in a specific continuum, a seal ring for example, CZ elements are laid along a predefined crack along the crack symmetry plane. After building the model, we apply displacement boundary conditions considering a mode I crack opening, thus K II = K III = 0, and Eq. (IV.13) becomes

where µ is the shear modulus of the bulk elastic K I -dominated region, κ = 3-4ν in plane strain conditions under consideration here, ν is the bulk's Poisson's ratio and R is the boundary radius as defined in Fig. IV.18. plasticity occurs with respect to the cohesive zone parameters. Similarly to Eq. (IV.19), Eq. (IV.23) describes the stress fields ahead of a crack tip for mode-I in a linear elastic and isotropic material, [123].

Thus, using a "smooth" copper is good for the resistance to fracture. Chapter IV. Modelling Interface Delamination in Heterogeneous and Patterned Media

• Another axis of development of modelling in small-scale yielding conditions would be to deepen the definition and exploration of the most promising seal ring configurations in terms of resistance to fracture. Through a Design Of Experiment-like approach in particular, or even in the form of a topology optimisation problem 7 .

• As has been pointed out throughout this thesis, the mechanical properties are on the one hand difficult to measure, and on the other hand depend on the deposition recipes. Variability therefore exists in the literature on this subject. In fact, an inverse identification of the layer propertiescalibration via simulation of experimental curves -can only be beneficial. This could be done by indenting with a wide tip in particular, in order to take into account the porosity of the low-k or the grain size of copper for example.

Appendices

Appendix A

Resistance curve

As it is experimentally observed in the previous chapter ??, considering the stress intensity factor of a material constant, or of a medium in general, is an idealisation. Indeed, it is more suitable to write it as a function of the crack length, K = K(∆a), where K is the effective stress intensity factor, a measure of the resistance to the crack, and ∆a the extension of the crack. The plot of K(∆a) is referred at as the resistance curve, or R-curve.

Although, as parts of this work discuss crack growth along bimaterial interfaces, it is more appropriate to manipulate energies, works of separation, rather than stress intensity factors. Generally speaking, knowing that G = K 2 /E, see Eq. (IV.11), we can then plot the deriving force curves G(∆a) as opposed to the rsistance curves withough loss of generality. This being said, by misuse of language, both are referred at as R curves. In the case where the energy release rate G is greater (blue) than the critical energy G c , there is a characteristic length l ss which is needed to reach the steady state (subscript ss) crack growth. Rising . When the material shows an inelastic behaviour, a small region around the crack-tip yields, Fig. IV.17. Thus, as yielding phenomena require energy expenses, some of the energy initially intended to propagate the crack is dissipated to sustain yielding. A larger load is necessary to keep the crack growing, which translates into larger energy release rate G. This is the case of metals and other ductile materials [163,164].