Y Q Aguiar

F Wrobel

J-L Autran

P Leroux

F Saigné

V Pouget

A D Touboul

Reliability-driven pin assignment optimization to improve in-orbit soft-error rate

Electronics are increasingly susceptible to energetic particle interactions within the silicon. In order to improve the circuit reliability under radiation effects, several hardening techniques have been adopted in the design flow of VLSI systems. This paper proposes a pin assignment optimization in logic gates to reduce the Single-Event Transient (SET) cross-section and improve the in-orbit soft-error rate. Signal probability propagation is used to assign the lowest probability to the most sensitive input combination of the circuit by rewiring or pin swapping. The cell optimization can reach up to 48% reduction on the soft-error rate. For the analyzed arithmetic benchmark circuits, an optimized cell netlist can achieve from 8% to 28% reduction on the SET crosssection and in-orbit soft-error rate at no cost in the circuit design area. Additionally, as the pin swapping is a layout-friendly technique, the optimization does not impact on the cell placement and it can be adopted along with other hardening techniques in the logic and physical synthesis.

Introduction

The reliability of electronic circuits is subject to physical failures due to the influence of the environment, such as the presence of atmospheric or space radiation [START_REF] Baumann | The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction[END_REF]. The energy deposition of a single energetic particle in the sensitive areas of a circuit can lead to destructive or non-destructive failures, known as Single-Event Effects (SEE). Memory elements, such as flip-flops and SRAMs, are subject to the Single-Event Upset (SEU), i.e. the stored logic bit is flipped due to the particle hit. On the other hand, the Single-Event Transient (SET) effect is observed in logic paths as parasitic transient currents generated from a particle hit in the sensitive regions of transistors issued from combinational circuits. As SEU and SET are not destructive effects, they are also known as soft error. Due to transistor scaling, reduced logic data path and high operating frequencies, soft errors are increasingly becoming an inevitable threat even in terrestrial environment [START_REF] Ferlet-Cavrois | Single Event Transients in Digital CMOS -A Review[END_REF].

The adoption of hardening strategies is highly recommended in order to obtain a fault-tolerant and reliable system [START_REF] Nicolaidis | Design for soft error mitigation[END_REF]. Considering the Radiation-Hardening-By-Design (RHBD) techniques, the circuit designers can apply different approaches ranging from changes on the transistor layout, as the Enclosed Layout Transistor (ELT), to circuit and system design approaches, as the Triple-Modular Redundancy (TMR) schemes and Error Correction Codes (ECC). Due to the popularity of cellbased design methodology in ASIC systems, a variety of hardening strategies have been proposed to address radiation effects early in the design flow, such as in the physical and logic synthesis of standard-cell libraries [START_REF] Limbrick | Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty[END_REF][START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF][START_REF] Kiddie | Alternative standard cell placement strategies for single-event multiple-transient mitigation[END_REF][START_REF] Zhou | Gate sizing to radiation harden combinational logic[END_REF][START_REF] Aguiar | Radiation hardening efficiency of gate sizing and transistor stacking based on Standard Cells[END_REF][START_REF] Aguiar | Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity[END_REF]. For instance, a cell placement algorithm to mitigate charge sharing effects and consequently to reduce multiple SETs is proposed in [START_REF] Kiddie | Alternative standard cell placement strategies for single-event multiple-transient mitigation[END_REF]. Also, besides improving performance metrics, gate sizing has been shown to improve the radiation robustness [START_REF] Zhou | Gate sizing to radiation harden combinational logic[END_REF][START_REF] Aguiar | Radiation hardening efficiency of gate sizing and transistor stacking based on Standard Cells[END_REF].

Signal probabilities are widely used to estimate power consumption, and to perform timing analysis [START_REF] Ghosh | Estimation of average switching activity in combinational and sequential circuits[END_REF][START_REF] Pedram | Power minimization in IC design: Principles and applications[END_REF][START_REF] Liu | Signal Probability Based Statistical Timing Analysis[END_REF].

Considering the sensitivity to SET is directly related to the layout of the circuit and its operation mode, i.e. input signals and internal states, signal probability can also be used to improve the reliability of circuits [START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF]. For instance, Signal Probability based Reliability Analysis (SPRA) is another efficient tool used to analyze the reliability of VLSI circuit at gate-level [START_REF] Chakravarty | On computing signal probability and detection probability of stuck-at faults[END_REF][START_REF] Franco | Signal probability for reliability evaluation of logic circuits[END_REF][START_REF] Franco | Reliability analysis of logic circuits based on signal probability[END_REF]. In this context, the reliability of a gate or a circuit is defined as the confidence level that the output will be functionally correct given a fault probability. Initially, SPRA methods have been focused on physical defects due to wearout mechanisms or process variability [START_REF] Chakravarty | On computing signal probability and detection probability of stuck-at faults[END_REF]. However, due to the increase interest in reducing the impact of soft error rate, some works analyzing SET have been proposed as in [START_REF] Franco | Signal probability for reliability evaluation of logic circuits[END_REF][START_REF] Franco | Reliability analysis of logic circuits based on signal probability[END_REF][START_REF] Bandan | Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits[END_REF][START_REF] Du | A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits[END_REF]. Using a SPRA algorithm, the work in [START_REF] Bandan | Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits[END_REF] proposed a cell placement strategy based on the definition of bad and good pairs of logic gates referring to a measurement on how the close proximity of the standard cells would impact the circuit error rate. Similarly, [START_REF] Du | A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits[END_REF] proposed another cell placement approach based on the signal probability and its relation to the pulse quenching effect. In our work, signal probability is used to propose a reliability-driven pin assignment optimization based on the input dependence of SET sensitivity of logic gates. Accordingly, an SET characterization based on the cell layout and input stimuli is considered. In summary, a layout-based analysis is performed using the Monte Carlo method for the high-energy particle interaction simulations and the SET cross-section calculation [START_REF] Limbrick | Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty[END_REF]. Based on the SET characterization of the standard cells, pin swapping, also known as rewiring, is adopted to assign the lowest signal probability to the input pin so that the most sensitive gate input combination obtains the lowest probability of occurrence. Besides the cross-section reduction, the optimization results provide the impact on the soft error rate for single cells individually, i.e. 2-input basic logic gates and 3input complex gates, and for some arithmetic benchmark This paper is organized as follows: the pin assignment optimization to improve SET robustness is explained in Section 2; Section 3 provides the methodology of the radiation sensitivity evaluation, in which a layout-based prediction is adopted using a Monte Carlo approach; the results are presented and explored in details in Section 4; and, to conclude, Section 5 presents the final considerations and an outlook of the results.

Optimizing Pin Assignment for Single-Event Transients

Pin assignment is used in the logic synthesis to improve power and performance metrics in the design of VLSI circuits by taking advantage of the functional equivalence of input pins of logic gates [START_REF]Logic synthesis and verification[END_REF][START_REF] Khatri | Advanced Techniques in Logic Synthesis, Optimizations and Applications[END_REF][START_REF]Advanced Logic Synthesis[END_REF]. Consider the NAND gate and its truth table in Fig. 1. A symmetric input relationship is observed when both input signal are not identical, i.e. A≠B: the output signal is determined whenever one of its input is in low logic level, regardless of the input pin (a or b). The interchangeable input combinations are highlighted in Fig. 1 (red rectangular). This symmetric input relationship is observed in all 2-input basic standard cell gates. As each input pin of a logic gate presents different electrical characteristics depending on the transistor network, power-driven logic synthesis assigns the input signal with lower switching activity to the pin with higher capacitance. Similarly, a timing-driven optimization can apply pin permutation between symmetric input pins such that the latearriving signal is always connected to the input pin with the lowest intrinsic delay [START_REF]Logic synthesis and verification[END_REF]. This process is known as rewiring or pin swapping [START_REF] Khatri | Advanced Techniques in Logic Synthesis, Optimizations and Applications[END_REF][START_REF]Advanced Logic Synthesis[END_REF]. Considering that cross-section of logic gates is dependent on the input stimuli, a reliability-aware synthesis can be proposed based on the cell symmetric inputs and signal probabilities to improve the vulnerability of the circuit through optimal pin assignment.

A diagram illustrating the proposed SET-aware pin assignment optimization in a cell-based circuit design flow is shown in Fig. 2. Given a circuit description in Register Transfer Level (RTL), the logic synthesis optimizes each Boolean function and maps it to logic gates available in the Standard-Cell library. As output, a gate netlist is provided, normally optimized for timing, area and/or power. With the gate netlist information and the Standard-Cell library, the SET-aware pin assignment optimization can be performed. The first step is the Input-based SET characterization, in which the symmetric input relationship of each standard cell is identified and the SET cross-section for the interchangeable input combinations calculated. For instance, the cross-section for the input combination (0, 1) and (1, 0). The methodology used to calculate the SET cross-section and inorbit rate is explained in the next section. Based on the SET characterization results, a set of pin assignment rules is defined, i.e. there will be an input pin for each standard cell in which the net with the lowest signal probability should be connected to so the most sensitive interchangeable input combination obtains the lowest probability of occurrence. The second step, considering the switching activity of the primary inputs, the signal probability calculation can be performed for the internal net connections as illustrated in Fig. 3. Based on the Boolean function of each gate, an equation is extracted to calculate the probability of the output signal to be at logic value 1, i.e. the gate output signal probability 𝑃 !"#$ (𝑜𝑢𝑡𝑝𝑢𝑡 = 1). In this work, the Parker-McCluskey method [START_REF] Parker | Probabilistic treatment of general combinational networks[END_REF] was used considering the primary inputs as uncorrelated and with equally switching activity of 50%, i.e. signal probability equals to 0.5. Although temporal and spatial correlation is not considered in our analysis, a more complex and accurate signal probability estimation method can be easily integrated into the development flow in Fig. 2. Applying basic probability theory, the output signal probability equations for the logic gates used in the combinational circuit in Fig. 3 are shown in Table 1. For instance, consider the inverter gate. Given the input probability 𝑝(𝑎 = 1) = 1, the signal is always at logic value 1, considering its Boolean function, the probability of the output signal to be at logic value 1 is 0 (𝑃 %&' (𝑜𝑢𝑡𝑝𝑢𝑡 = 1) = 0). Thus, the signal probability equation for the inverter is:

𝑃 %&' (𝑜𝑢𝑡𝑝𝑢𝑡 = 1) = 1 -𝑝(𝑎 = 1) (1)
For clarity, the probabilities 𝑃 !"#$ (𝑜𝑢𝑡𝑝𝑢𝑡 = 1), 𝑝(𝑎 = 1), 𝑝(𝑏 = 1) will be shortened to PGATE, pA and pB. Following the signal probability calculation in the Fig. 2 is the pin swapping. In this process, with the pin assignment rules and the signal probabilities, an optimization algorithm can identify which pin should be swapped in order to reduce the occurrence of the interchangeable input combination with the higher SET cross-section. After the pin swapping, the standard design flow is performed with the optimized netlist.

Radiation Sensitivity Methodology

In order to obtain important reliability information to be addressed in the optimization process, the SET characterization methodology is aligned to the identification of the input dependence [START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF]. The sensitivity of each standard cell is extracted from the layout design in the Graphical Design System (GSDII) file. Thus, the Monte Carlo simulation tool, MC-Oracle [START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF], is used to obtain the SET currents. In MC-Oracle, the driftdiffusion model is used for the charge collection process. Based on the SET database provided by the tool, a SET analyzer is responsible to perform the SPICE simulations and calculate the SET cross-section for each cell input combination. In order to consider the input signal probabilities, the Eq. 2 is used. Given n input combinations, the overall gate SET cross-section 𝜎 ($# can be estimated from the input SET cross-section 𝜎 ($# ) and the input probability p(i):

𝜎 ($# = / 𝜎 ($# ) × 𝑝(𝑖) * )+, (2)
The input cross-section 𝜎 ($# ) is provided by the SET characterization while the input probabilities are provided by the Signal Probability Calculation in Fig. 3. Then, this equation is used in the Pin Swapping process to evaluate when the input pins assigned from the logic synthesis should be swapped to decrease the gate SET cross-section. Similarly, this process can also adopt the soft-error rate estimation for a given mission orbit. In this work, two orbits were analysed: the Geostationary (GEO) and the International Space Station (ISS) orbits. The Integral Rectangular Parallelepiped (IRPP) method is used as specified by the European Cooperation for Space Standardization (ECSS) [START_REF]Space Engineering: Calculation of Radiation and its Effects and Margin Policy Handbook[END_REF]. Additionally, a fixed shielding of 1 g/cm 2 is used and, under solar minimum, the international standard ISO 15390 [START_REF]Space environment (natural and artificial) -Galactic cosmic ray model[END_REF] and NASA AP8MIN [START_REF] Sawyer | AP-8 trapped proton environment for solar maximum and solar minimum[END_REF] flux models are used for the Galactic Cosmic Rays (GCR) and the trapped proton radiation. In this work, the standard cells are provided from the 45 nm OpenCell Library from NanGate [START_REF] Stine | FreePDK: An open-source variation-aware design kit[END_REF].

Results and Discussions

Analysis of 2-input gates

Based on the cross-section of the interchangeable input combinations, an optimized logic synthesis should prioritize the pin assignment of the lowest signal probability in such a way the most sensitive interchangeable input combination obtains the lowest probability of occurrence. The input SET cross-section for NAND, NOR and XOR gates under particle Linear Energy Transfer (LET) of 5 MeV.cm 2 /mg is shown in Fig. 4. It is possible to identify the most sensitive input combinations. Considering the interchangeable input, i.e. (0, 1) and (1, 0): the NAND gate is the only cell to show the lowest cross-section for the (1, 0), while the NOR and XOR gates present the (0, 1). It implies that, considering low particle LET, the lowest signal probability be assigned to the input B for the NAND gate, and to the input A for the NOR and XOR gates. In Fig. 5, the gate SET cross-section is calculated for the NAND and NOR gate using the Eq. 2 and considering 3 scenarios of input probabilities (Table 2 contains all the Weibull fitting parameters). Notice that, the input dependence of the SET cross-section is also dependent on the LET. It can be also observed in Fig. 6, in which the input SET cross-section is shown for 78 MeV.cm 2 /mg. Based on the SET cross-section curve, we can observe that signal probability will play an important hole for low particle LET This behavior is related to the different charge collection efficiencies and the interplay relationship between pull-up and pull-down recovery dynamics. Due to this characteristic, the in-orbit rate should be analyzed to identify the best pin assignment strategy considering the complete range of particle energy present in a given mission radiation environment. This analysis is discussed later in this paper.

Analysis of 3-input gates

When adopting 3-input logic function such as AOI21 and OAI21, it is not possible to obtain a complete symmetric input relationship as observed for the 2-input gates. It is necessary to identify the interchangeable input combinations and the controllable input pin, i.e. the pin that controls the output of the function and the pin assignment cannot optimize it otherwise it will interfere within the correct logic function of the circuit. In Fig. 7, the transistor network and truth table of the AOI21 gate is shown. In this case, A1 is the controllable input pin while two pairs of interchangeable input combination are possible: (0, 0, 1) ↔ (0, 1, 0) and (1, 0, 1) ↔ (1, 1, 0). Analyzing the transistor network, it is possible to observe that the interchangeable input signal are the ones from the series and parallel arrangement (B1 and B2). As the OAI21 gate is the complement of the AOI21 Fig. 6. Input SET cross-section for the NAND, NOR and XOR gates under a particle with LET = 78 MeV.cm 2 /mg logic function, they present the same pairs of interchangeable input combinations. The input dependence of SET cross-section for AOI21 and OAI21 is shown in the Fig. 8 for a particle LET of 5 MeV.cm 2 /mg. The interchangeable input combinations are the ones that provides the largest cross-sections. Thus, a greater impact can be expected when applying the pin assignment optimization. Among the pairs of interchangeable inputs, the input combinations (0, 1, 0) and (1, 0, 1) provides the lowest for both circuits. As observed for the 2-input gates, this input dependence is dependent on the analyzed particle LET. Thus, the SET rates are analyzed for different scenarios of input probabilities in the next subsection.

Impact on the in-orbit SET rates

After the characterization of the standard cells and the estimation of the cross-section curves using Eq. 2 for each input scenario, the in-orbit SET rate can be calculated and it is shown in Fig. 9 and Fig. 10 for the 2-input and 3-input gates, respectively. Considering the 2-input gates, the signal with the lowest probability should be assigned to the input B for the NAND gate, and to the input A for the NOR and XOR gates. This observation agrees with the cross-section obtained for low LET. As the major impact of input dependence is observed for low LET particles, it dominates the overall response in the optimization of the SET rate. The largest reduction is observed for the NAND gate operating in the GEO orbit, about 48% when the lowest signal probability is assigned to the input B.

For the 3-input gates, different conclusions can be drawn based on the signal probability of the controllable input A1: (1) if 0.1, both gates show reduced SET rate for the input scenario which B2 has the lowest signal probability; (2) if 0.5, the lowest SET rate for the AOI21 is still observed when B2 has the lowest signal probability, while for the OAI21, the reduced rate is obtained when B1 has the lowest signal probability; (3) if 0.9, both circuits show a reduced rate when B1 has the lowest signal probability. Though the higher complexity of understanding the input dependence of the 3-input gates, they provide the greater reductions on the SET rate, reaching up to 35% of reduction.

Impact on Benchmark Circuits

In order to observe the impact of the proposed optimization in circuits, two arithmetic circuits were designed and analysed, a 1-bit Full Adder (FA) and a 4-bit Binary Adder and Subtractor (BAS). Three different implementations of the 1-bit FA circuit explores the design based on: (1) only XOR and NAND gates;

(2) only NAND gates; and, (3) only NOR gates. For the 4-bit BAS, a ripple-carry adder structure is used along with a XOR gate to control the operation mode of the circuit. The 4-bit BAS architecture is illustrated in Fig. 11. An operation mode signal M is used to selected the binary operation. When M = 0, the XOR gate will evaluate to 𝐵 ) ⊕ 0 = 𝐵 ) , so the FA module will receive the B signal and the binary addition 𝐴 + 𝐵, will be evaluated. On the other hand, when M = 1, the XOR gate will evaluate 𝐵 ) ⊕ 1 = 𝐵 - 7 , i.e. the complement of B will be assigned to the FA module. As the M signal is the input carry 𝐶 )* , the BAS architecture will evaluate the binary subtraction of 𝐴 -𝐵 = (A + 𝐵 : ) + 1.

The number of gates and the percentage of reduction obtained using the pin assignment optimization is shown in Table 3. The reduction on the SET cross-section (shortened to XS) is given for a particle LET of 5 MeV.cm 2 /mg. Considering the FA architectures, the design based on XOR and NAND gates provides the highest reduction on the XS. When comparing the all-NAND and all-NOR implementations, the greatest XS reduction is observed for the former design, due to the high reduction observed for NAND gate in Fig. 4. However, due to the strong LET dependence of the improvements for the NAND and NOR gates, the technique has shown a reduction from 9% to 16% on the soft-error rate. For the 4-bit BAS architecture, the greatest reductions were observed when operating in the mode addition (M=0). This occurs due to the signal probability of the carry propagation. When the 𝑝(𝐶𝑖𝑛 = 1) = 0, a greater signal probability difference between the internal pins of the FA module is observed, leading to a greater pin assignment impact. Additionally, it should be noticed that this optimization process does not lead to any penalty in the circuit design area. Despite the high soft-error rate improvement observed in the single cells in Fig. 9, the benchmark circuits have not shown an improvement over 28%. This can be explained by the spatial correlation, which was not considered in our signal probability calculation. Thus, to improve the optimization accuracy, a more advanced signal estimation method that consider signal dependencies and reconvergent fanouts, as proposed in [START_REF] Han | Reliability evaluation of logic circuits using probabilistic gate models[END_REF], should be considered.

Conclusions

Radiation hardening strategies can be implemented in the design phase of VLSI circuits. In this work, a SET characterization of standard cells is used to perform signal probability analysis and to provide a reliability-aware pin assignment optimization and reduce the in-orbit SET rate through pin swapping. The relationship among input signal and the gate SET cross-section is dependent to the particle LET. The impact of adopting signal probability evaluation and pin assignment showed the greatest cross-section reduction for low particle LET. Considering the 2-input gates, the signal with the lowest probability should be assigned to the input B for the NAND gate, and to the input A for the NOR and XOR gates. For the 3-input gates, different conclusions can be drawn based on the signal probability of the controllable input. The impact on arithmetic benchmark circuits using the standard cells were evaluated. The overall reduction ranges from 8% to 28% depending on the circuit architecture and mission orbit. This optimization technique provides no area overhead and can be used along with other hardening techniques. Additionally, it does not impact on the cell placement and the net routing is impacted minimally and locally. a XS stands for SET cross-section and the % reduction is given for a particle LET of 5 MeV.cm 2 /mg.

Fig. 1 .

 1 Fig. 1. Transistor network and truth table of a 2-input NAND gate

  PNAND = 1 -(pA × pB) NOR 2: a, b PNOR = (1 -pA) × (1 -pB) XOR 2: a, b PXOR = pA × (1 -pB) + pB × (1 -pA) aSignal probability is the probability of the signal to be at logic value 1.

Fig. 4 .

 4 Fig. 4. Input SET cross-section for the NAND, NOR and XOR gates under a particle with LET = 5 MeV.cm 2 /mg

Fig. 5 .Fig. 7 .

 57 Fig. 5. SET cross-section curves for the NAND and NOR gate in 3 input scenarios

Fig. 8 .Fig. 9 .Fig. 10 .

 8910 Fig. 8. Input SET cross-section for the AOI21 and OAI21 gates under a particle with LET = 5 MeV.cm 2 /mg

Fig. 11 .

 11 Fig. 11. The architecture of the 4-bit Binary Adder and Subtractor (BAS) circuit. For the Full Adder (FA) module, the XOR-NAND implementation is used.

Cite this article as: Y. Q. Aguiar et al., "Reliability-driven pin assignment optimization to improve in-orbit soft-error rate," in Microelectronics Reliability, vol. 114, November 2020, doi: 10.1016/j.microrel.2020.113885. Final version is available at https://doi.org/10.1016/j.microrel.2020.113885 circuits.

Table 1

 1

	Signal Probability Estimation for the INV, NAND, NOR and
	XOR gates
	Cells	Input Signals	Output Signal Probability a

Table 2

 2 Weibull fitting parameter from the cross-section curves of Fig.5. Saturation cross-section and threshold LET correspond to Sat XS and LETTH values, respectively.

			W	S	Sat XS (10 -9 cm 2 )	LETTH (MeV.cm 2 /mg)
	NAND	I II III	13.74 14.68 14.84	1.16 1.19 1.15	3.57 4.18 3.94	1.73 1.55 2.22
	NOR	I II	15.03 16.94	1.22 1.31	5.68 5.38	2.19 1.09
		III	17.71	1.33	5.22	0.33

Table 3

 3 Results for the pin assignment optimization for different benchmark circuits

	Benchmark Circuits	# of Gates	XS a	% of reduction on GEO	ISS
		XOR-NAND	5	21.8	12.1	9.7
	Full Adder	all-NAND	9	18.0	9.6	10.6
		all-NOR	9	8.2	15.8	9.4
	4-bit	M=0	24	27.5	15.4	10.7
	BAS	M=1	24	20.1	11.1	8.3

Acknowledgments

This work was realized within RADSAGA project. The RADSAGA Innovative Training Network project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement number 721624.


Y Q Aguiar

F Wrobel

J-L Autran

P Leroux

F Saigné

V Pouget

A D Touboul

Design Exploration of Majority Voter Architectures based on the Signal Probability for TMR Strategy Optimization in Space Applications

Hardware redundancy is a well-known fault tolerance technique used in safety-and mission-critical systems. However, the hardening efficiency of such techniques relies on the robustness of the majority voter circuitry. This summary provides the design exploration of majority voter architectures to be used in radiation environments such as in space missions. An application-specific Single-Event Transient (SET) characterization based on the signal probability is proposed to optimize the Triple-Modular Redundancy (TMR) block insertion methodologies. Results show that the SET cross-section of complex-gate architectures presents low input dependence while for the NOR/NAND based architectures a higher dependence is observed due to the logical masking effects. Additionally, different from the other architectures, the NAND voter has shown a reduction in the SET rate as the signal probability is increased. Considering the signal probability p = 0.1, p = 0.5 and p = 0.9, the best design for the two analyzed orbits is the NOR, CMOS1 and NAND voter, respectively.

Introduction

Fault tolerance is increasingly necessary for advanced technology circuits due to the high complexity and susceptibility to physical defects and environment disturbances as provoked by radiation interactions [START_REF] Johnson | Fault-Tolerant Microprocessor-based Systems[END_REF][START_REF] Nicolaidis | Design for soft error mitigation[END_REF][START_REF] Kastensmidt | Fault-Tolerance Techniques for SRAM-Based FPGA[END_REF][START_REF] Baumann | Radiation-induced soft errors in advanced semiconductor technologies[END_REF]. Safety-and mission-critical systems, such as satellites and aircraft flight control systems, are the primary applications using fault-tolerance techniques to improve reliability. A system is assumed to be fault-tolerant when its functionality is preserved even with the presence of faults. Commonly, redundancy is the core foundation of fault tolerance techniques proposed in the literature [START_REF] Kastensmidt | Fault-Tolerance Techniques for SRAM-Based FPGA[END_REF]. There is a variety of approaches, according to the redundant part added to the system, ranging from hardware and software to information and time redundancy [START_REF] Johnson | Fault-Tolerant Microprocessor-based Systems[END_REF]. Hardware redundancy, also known as spatial redundancy, is widely used in space applications due to its capability of performing fault detection and/or fault correction [START_REF] Nicolaidis | Design for soft error mitigation[END_REF]. One of the most used technique is the so-called Triple-Modular Redundancy (TMR), in which the selected critical component or electronic circuit is triplicated and their outputs are connected to a majority voter (MJV) architecture, as shown in Fig. 1 [START_REF] Kastensmidt | Fault-Tolerance Techniques for SRAM-Based FPGA[END_REF]. Therefore, whenever two copies of the component are fault-free, the output of the majority voter will be also fault-free. However, if a fault occurs in the MJV, the technique fails to provide a correct function of the system.

The applicability of TMR schemes as a Radiation-Hardening-by-Design (RHBD) approach can extend from masking the effects of Single-Event Transients (SETs) in data paths or Single-Event Upsets (SEUs) in memory elements. However, the majority voter robustness against radiation effects is crucial for the fault detection and correction efficiency of TMR strategies. Few works in the literature have provided design studies on the radiation robustness of majority voters in terms of power, delay, area and SET cross-section [START_REF] Danilov | SET Tolerance of 65nm CMOS Majority Voters: a comparative study[END_REF][START_REF] Ban | A Simple Fault-Tolerant Digital Voter Circuit in TMR Nanoarchitectures[END_REF][START_REF] Aguiar | Evaluation of radiation-induced soft error in majority voters designed at 7nm FinFET technology[END_REF][START_REF] Oliveira | Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs[END_REF]. The work developed in [START_REF] Danilov | SET Tolerance of 65nm CMOS Majority Voters: a comparative study[END_REF] provides heavy-ion experimental data and proposes a relative efficiency criterion for the majority voter selection according to the TMR strategy. Two FinFET-based majority voter circuits were evaluated under the atmospheric environment in [START_REF] Aguiar | Evaluation of radiation-induced soft error in majority voters designed at 7nm FinFET technology[END_REF]. In this case, the NAND-and NOR-based voter circuits have shown a similar soft-error rate (SER) due to the symmetric sizing of the PFET and NFET devices provided by the strain engineering and width quantization at FinFET technology [START_REF] Aguiar | Evaluation of radiation-induced soft error in majority voters designed at 7nm FinFET technology[END_REF]. The work in [START_REF] Oliveira | Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs[END_REF] adopts a layout-level analysis through stick diagram to evaluate the diffusion area of majority voters and to calculate a fault masking ratio. Despite the layoutbased approach, charge sharing between internal nodes and very importantly the intra-cell charge sharing effect in the multi-level circuit implementations are not considered, which can considerably increase the voter sensitivity or reduce it through pulse quenching effect [START_REF] Ahlbin | The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process[END_REF]. Although the good fault coverage in TMR schemes, one of the main drawbacks of adopting redundancy-based hardening techniques is the considerably high increase in area and power consumption [START_REF] Johnson | Fault-Tolerant Microprocessor-based Systems[END_REF][START_REF] Nicolaidis | Design for soft error mitigation[END_REF][START_REF] Kastensmidt | Fault-Tolerance Techniques for SRAM-Based FPGA[END_REF]. Thus, it is of utmost importance to adopt optimization strategies in the TMR block insertion to selectively address the most sensitive nodes in the target design and lower the impact on the area usage and power consumption.

In this work, a design exploration of majority voter architecture robust to SET effects is presented considering the SET cross-section dependence on the input signals. A Monte Carlo based prediction methodology is used along with the physical design information of each circuit to assess its sensitivity to high-energetic particle interactions. A deeper analysis of the input dependence of the circuit sensitivity is provided. Therefore, the main contribution of this work lays on: the characterization of the input dependence of the SET crosssection in different majority voter architectures; and, the proposal of adopting signal probability analysis to provide an application-specific SET assessment of the designs and, consequently, to optimize the TMR insertion strategies in faulttolerant systems for space applications. This paper is organized as follows. The details on the circuit design and the SET assessment of the majority voter architectures are discussed in Section 2. Section 3 presents and discusses the results. Section 4 summarizes this work.

Circuit Design and Radiation Sensitivity Methodology

The four majority voter architectures shown in Fig. 2 were designed based on a commercial 65nm bulk CMOS technology. In addition, they were designed to be compatible with the standard-cell library provided by the Product Design Kit (PDK). A fixed cell height is set to 13 tracks of the metal pitch, i.e. 2.6µm high. To provide flexibility in the cell routing, intra-cell connections are primarily done using the metal 1 (M1), except for some cases in which metal 2 (M2) is used horizontally. The design of the two complex-gate majority voter followed the Euler's path graph theorem to optimize their physical layout by avoiding diffusion breaks and alleviating metal connectivity congestion [START_REF] Rekhi | Automatic layout synthesis of leaf cells[END_REF]. For the cell-based implementations, the NAND2, NAND3, NOR2 and NOR3 were designed and characterized separately, as standard cells. Logical Effort (LE) sizing approach was applied to all circuits to provide a driving capability comparable of the minimum-sized inverter of the cell library [START_REF] Sutherland | Logical Effort: Designing for Speed on the Back of an Envelope[END_REF]. The transistor sizing of the minimum-sized inverter has a PMOS/NMOS ratio of 190nm/135nm. Logical Effort approach is widely used in cell library design to achieve balanced delay performance. Accordingly, to provide means of comparison between MJV designs based on standard cells and complex CMOS implementations, only the LE sizing is adopted in this work.

The Euler's path graph theorem is commonly used as a layout design optimization in which a transistor ordering is provided in such a way that diffusion breaks are avoided and metal connectivity is optimized. In Fig. 3, the Euler's path graph theorem is applied to the CMOS2 voter. The pull-up and pull down transistor networks, i.e. PMOS and NMOS transistors, are translated into two graphs in which the vertices corresponds to the shared source/drain junctions of the circuit and the edges are the input signal of each transistor in the network. The Euler's path, in summary, is the path that goes through all the vertices Fig. 2. Circuit-and Layout-level implementations of the complex-gate and standard-cell-based majority voter architectures. For simplicity, only metal1 (blue), metal2 (orange), active diffusion (green) and poly (red) layers are shown.

in both graphs such that each edge is traversed only once. Not all transistor networks can provide a Euler's path, however, it is also possible to obtain many path solutions for a given circuit.

In the case of the CMOS2 voter represented in Fig. 3, one possible path is the ABCCB. In this work, the path ACCBAB and ABCCB are the Euler's paths used to design the CMOS1 and CMOS2 layouts, respectively.

Table 1 presents the number of transistors and the layout and drain area information for each voter architecture. Due to the reduced number of transistor provided by the logic factoring, CMOS2 voter provides the smallest layout area. However, despite the larger number of transistors, the smallest drain collecting areas are observed for the cell-based implementations, with the smallest drain area for the NAND-based MJV. The two complex-logic implementations have about 2× the drain area of the cell-based designs. As logical effort is adopted to provide comparable driving strength, the 3-transistor stacks used in the two complex-logic design implementations increase the drain collecting area as the transistor width is upsized. Only about 4% of the total layout of NAND and NOR voters represent the drain collecting area, while about 14% is expected for the CMOS1 and CMOS2 implementations. Thus, adopting complex-logic based MJV architecture provides a more compact and reduced layout design. However, an increase in the drain collecting area is expected, affecting the overall SET susceptibility of the circuit by increasing the charge collection efficiency.

An SET predictive assessment was performed to calculate the cross-section and the in-orbit rate for Geostationary (GEO) and International Space Station (ISS) orbits. The layout-based SET assessment proposed in [START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF] was adopted. A Monte Carlo predictive tool, named MC-Oracle, is used to calculate the particle interactions within the collecting volumes extracted from the layout of the majority voters [START_REF] Wrobel | MC-Oracle: a tool for predicting Soft Error Rate[END_REF]. A SET database is generated containing the radiation-induced transient current for each sensitive node of the analyzed circuit [START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF]. Using a SET analyzer, a SPICE-based multi-node current injection is performed to calculate the cross-section and the SET pulse width distribution. An SET is occurred only if the resulting radiationinduced transient voltage exceeds at least half of the nominal supply voltage of the technology, i.e. peak voltage greater than VDD/2. Due to its layout-based approach and multi-node current injection methodology, charge sharing and pulse quenching effects (PQE) are considered in this analysis [START_REF] Aguiar | Analysis of charge sharing effect in the SET sensitivity of bulk 45nm standard cell layouts under heavy ions[END_REF][START_REF] Aguiar | Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity[END_REF][START_REF] Aguiar | Radiation hardening efficiency of gate sizing and transistor stacking based on Standard Cells[END_REF]. After the cross-section calculations, the in-orbit SET rate is estimated using the OMERE tool [17]. The Integral Rectangular Parallelepiped (IRPP) method is adopted as specified by the European Cooperation for Space Standardization (ECSS) [START_REF]Space Engineering: Calculation of Fig. 10[END_REF]. The SET rate is calculated by the convolution of the crosssection curve with the particle flux obtained from the GEO and LEO (ISS) orbits. Following the European standard, a fixed shielding of 1 g/cm 2 was used in the calculations, which the international standard ISO 15390 model is used for the Galactic Cosmic Rays (GCR) [START_REF]Space environment (natural and artificial) -Galactic cosmic ray model[END_REF] and the NASA AP8MIN trapped radiation model is used for the trapped proton flux under solar minimum (solar cycle 25) [START_REF] Sawyer | AP-8 trapped proton environment for solar maximum and solar minimum[END_REF].

Results and Discussion

In this work, four majority voter architectures exploiting complex-gate and standard cells were designed based on a commercial 65nm bulk CMOS technology. The maximum, mean and standard deviation of the SET pulse width distribution is shown in Fig. 4 when considering a particle LET of 78.23 MeV.cm 2 /mg. The lowest pulse widths are observed for both complex-gate MJV, the CMOS1 and CMOS2. This is attributed to the contribution of pulse quenching effect (PQE) inherent of inversion stages in combinational circuits [START_REF] Ahlbin | The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process[END_REF]. As both CMOS1 and CMOS2 present an inverter gate in its output, the PQE is enhanced in these architecture and the overall SET distribution is shortened. Comparing the NAND and NOR based voters, the latter provides the wider distribution. This observation is agreement with the literature, as in [START_REF] Aguiar | Evaluation of radiation-induced soft error in majority voters designed at 7nm FinFET technology[END_REF] the FinFET-based NOR majority voter has also shown a wider SET distribution than the NAND implementation.

In Fig. 5, the SET cross-section for each circuit design is shown for two particle Linear Energy Transfer (LET) values, 78.23 and 9.94 MeV.cm 2 /mg. Although the two complex-gate implementations, CMOS1 and CMOS2, present reduced layout, they have showed the highest sensitivity for high and low LET.

The reduced number of transistors of the CMOS2 implementation provided by logic factoring only induced a slight reduction of about 8% on the SET cross-section for high LET. On the other hand, an increase of about 26% is observed at low LET, when compared with the CMOS1 architecture. This can be attributed to the transistor restructuring and the consequent impact on the collecting area and the internal capacitance of the circuit. Further, despite the larger design area, the lowest crosssections were obtained for the NAND and NOR architectures. As observed in the previous section, by using smaller transistor in the cell-based designs a reduced drain collecting area can be achieved compared to the complex-gate implementations. However, these results provide the average cross-section obtained for logic input high and low. To better understand the design implications on the overall sensitivity of the circuit, the next subsection provides a discussion on the input dependence of the cross-section curve for each architecture.

Input Dependence of SET cross-section curves

The SET cross-section of the MJVs for the two possible input configuration in a fault-free TMR condition is studied: all inputs equal to 1; and, all inputs equal to 0. Considering the results for the complex-gate implementations in Fig. 6, the CMOS2 circuit has shown a higher input dependence than the CMOS1. This is attributed to the sizing and symmetry/asymmetry of the pull-up and pull-down transistor networks. The CMOS1 architecture allows symmetric physical layout and consequently a balanced drain collecting area distribution. On the other hand, different sizing of each branch of the transistor networks in the CMOS2 architecture provides an asymmetric physical layout and an unbalanced distribution of the collecting areas, i.e. a considerably larger collecting area is observed for the PMOS devices than for the NMOS. Furthermore, both circuits have shown a higher cross-section for the input 1 configuration due to the larger PMOS devices and lower driving capability of NMOS devices.

For the majority voters composed by basic logic standardcells, a higher input dependence is observed as seen in Fig. 7. The nature of this variation is directly related to the logical masking effect capability of the 3-input NAND/NOR gate in the output of the circuit. For instance, when the TMR input configuration is at low logic level, i.e. all inputs equal to 0, for the NAND architecture, the output of the voter is sensitive to the SET occurrence in any of the 2-input NAND gate and the 3-input gate. On the other hand, for TMR input configuration at high logic level, i.e. all inputs equal to 1, the 3-input NAND gate is logically masking any of the SET in the 2-input NAND gates. The same phenomenon is observed for the NOR architecture, but the logical masking occurs when the TMR input configuration is set to low logic level. Thus, depending on the output signal of the triplicated blocks in the TMR, the NAND and NOR voters can provide a sensitive area only issued from the charge collection in its 3-input gate. Given the high input dependence of certain designs, the next subsection provides a signal probability analysis and discusses how it could be used to optimize the application of TMR schemes.

Signal Probability Analysis

Fig. 6. SET cross-section for the complex-gate architectures considering the two possible input configuration in a fault-free TMR scheme: all inputs in high logic level (Input 1); and, all inputs in low logic level (Input 0). The estimation of signal switching activity is widely used in circuit design to perform power analysis. However, it can also be used to perform reliability analysis as shown in [START_REF] Najm | Improved estimation of the switching activity for reliability prediction in VLSI circuits[END_REF]. For instance, consider the signal probability p as the probability of the signal to be in high logic level. And, as shown previously, the CMOS1 and CMOS2 architectures provide higher crosssections for the input-1 scenario (Fig. 6). Therefore, the TMR insertion methodology should prioritize the insertion of these architectures in the sensitive nodes with the lowest signal probability. Considering the signal switching activity of the input signals, the gate cross-section σG can be calculated using the Eq. 1 [START_REF] Aguiar | Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions[END_REF], where n corresponds to the number of input combinations, 𝜎 𝑖 is the SET cross-section for input combination i, and 𝑝(𝑖) is the input combination signal probability. However, as in a fault-free TMR condition, the 3 input signals of the voter have the same signal probability p and only 2 input combinations (n = 2), then Eq. 1 can be reformulated as Eq. 2, where σMJV is the majority-voter SET cross-section, pTMR is the signal probability of the node in which the TMR will be inserted, 𝜎 0 and 𝜎 1 are the SET cross-section calculated for the two possible input scenarios in a fault-free TMR condition, i.e. all inputs in low logic level (input-0 scenario) and all inputs in high logic level (input-1 scenario), respectively.

σ G = ∑ 𝜎 𝑖 × 𝑝(𝑖) 𝑛 𝑖=0 (1) σ MJV = 𝑝 TMR × (𝜎 1 -𝜎 0 ) + 𝜎 0 (2)
Considering the Eq. 2, the SET cross-section curves were estimated for two signal probability and shown in Fig. 8 and Fig. 9, for p = 0.1 and p = 0.9, respectively. Notice that, for p = 0.1, in contrast with what we observed in Fig. 5, the NAND architecture provides the highest cross-section curve in Fig. 8. This is explained by the considerable high SET cross-section observed for the input-0 scenario (as shown in Fig. 7) and the low signal probability, p = 0.1. On the other hand, in Fig. 9, the NAND architecture provides the lowest cross-section, while the NOR architecture provides the highest cross-section curves along with the CMOS1 and CMOS2 architectures. Thus, by considering the signal probability estimation to calculate the susceptibility of majority voter architectures, a more efficient and application-specific TMR insertion methodology can be obtained.

Impact on the in-orbit SET rate: GEO and LEO orbits

To verify the impact of a given radiation environment, Fig. 10 presents the SET rates estimated for three signal probabilities (p = 0.1, p = 0.5 and p = 0.9) and two different orbits (GEO and ISS/LEO). Two distinct trends can be observed: the increase of SET rate as the signal probability is increased; the decrease of SET rate as the signal probability is increased. Different from the CMOS1, CMOS2 and NOR architectures, the NAND voter is the only design that shows a decrease in the SET rate as the signal probability is increased. This is attributed to the lower SET cross-section for the input 1 configuration (Fig. 7) due to the logical masking effect. Additionally, the SET rate most sensitive to the input signal is observed for the NAND Fig. 9. SET cross-section curves calculated for the majority voters considering a signal probability p of 0.9, i.e. higher probability of a fault-free TMR condition in the input combination (1, 1, 1) Fig. 7. SET cross-section for the basic-logic gate architectures considering the two possible input configuration in a fault-free TMR scheme: all inputs in high logic level (Input 1); and, all inputs in low logic level (Input 0). Fig. 8. SET cross-section curves calculated for the majority voters considering a signal probability p of 0.1, i.e. higher probability of a fault-free TMR condition in the input combination (0, 0, 0).

architecture while the CMOS1 is the less sensitive, a variation of approximately 300% and 25 % from p = 0.1 to p = 0.9, respectively. In summary, considering the signal probability p = 0.1, p = 0.5 and p = 0.9, the best design for both orbits is the NOR, CMOS1 and NAND, respectively.

Conclusion

Redundancy-based hardening techniques are widely used to provide fault-tolerant systems. This work has evaluated the robustness of four majority voter architectures, which is the circuit that constitutes the critical point of failure in Triple-Modular Redundancy (TMR) methodologies. Also, a signal probability analysis is proposed as an optimization strategy for TMR block insertion algorithms. Despite the reduced layout design, complex-gate voter architectures have shown, on average, a higher SET cross-section than the implementations using basic logic standard-cell gates. As all architectures were designed to provide comparable driving strength, upsizing the stacked transistors in the complex-logic designs increases the charge collecting drain areas and, consequently, increases the SET cross-section of the circuit. Thus, aiming at a lower drawback in design area will compromise the reliability of the circuit. By evaluating the signal stimuli, a higher input dependence is observed for the basic-logic gate architectures due to the influence of logical masking effects. For the 3input gate in the output of the NAND and NOR architectures masks any SET in the 2-input gates when input scenario is high and low logic values, respectively. The SET rate for the CMOS1 architecture has shown to be the least dependent to the signal probability while the NAND voter showed the highest dependence. Furthermore, apart from the NAND voter, all the other design implementations have shown an increase in the SET rate as the signal probability is increased. Thus, to conclude, an SET assessment based on the input dependence analysis can provide further information to optimize selective TMR block insertion methodologies in the most critical nodes of a circuit based on its signal probability.

Fig. 1 .

 1 Fig. 1. Diagram of the Triple Modular Redundancy (TMR) fault tolerance technique. Faults in the voter cannot be masked, thus it constitutes the critical point of failure in the technique [7].

Fig. 3 .

 3 Fig. 3. Euler's path graph theorem for the CMOS2 majority voter layout design.

Fig. 5 .Fig. 4 .

 54 Fig. 5. SET cross-section estimation for CMOS1, CMOS2, NAND and NOR majority voter architectures considering particle LET equals to 78.23 and 9.94 MeV.cm 2 /mg.

Cite this article as: Y. Q. Aguiar et al., "Design Exploration of Majority Voter Architectures based on the Signal Probability for TMR Strategy Optimization in Space Applications," in Microelectronics Reliability, vol. 114, November 2020, doi: 10.1016/j.microrel.2020.113877 Final version is available at https://doi.org/10.1016/j.microrel.2020.113877

Table 1

 1

	Number of transistors, layout and drain area of the CMOS1,
	CMOS2, NAND-based and NOR-based majority architectures
	Voters	# of Transistors	Layout Area (µm 2 )	Drain Collecting Area (µm 2 ) a
	CMOS1	14	6.45	0.890 (13.8%)
	CMOS2	12	5.93	0.855 (14.4%)
	NAND	18	10.45	0.415 (3.9%)
	NOR	18	10.45	0.455 (4.3%)
	a The percentage of layout design that corresponds to the
	collecting drain area is also indicated

Acknowledgments

This work was realized within RADSAGA project. The RADSAGA Innovative Training Network project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement number 721624.