Vianney Lapotre

Purushotham Murugappa

Guy Gogniat

Amer Baghdadi

Jean-Philippe Diguet

Jean-Noël Bazin

Michael Hübner
email: michael.huebner@rub.de

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context

Keywords: ASIP, Multiprocessor, SoC, Dynamic reconfiguration, Wireless multi-standard receiver, Turbo decoder

The emergence of many wireless standards is introducing the need of flexible multi-standard baseband receivers. To address this issue and to face the increasing demand of higher throughput for new greedy applications on mobile devices recent works propose multi-ASIP platforms for decoding algorithms. Furthermore dynamic evolution of communication parameters combined with the reduction of latency between two data frames imposes the need for an efficient reconfiguration management of such systems. In this context, we propose to tackle reconfiguration optimizations of a multi-standard and multi-mode ASIP for turbo decoding in order to improve the global reconfiguration management of a multi-ASIP platform. A comprehensive analysis concerning the area impact and dynamic reconfiguration performance is presented. Proposed ASIP configuration optimizations lead to a low area overhead of 0.004 mm 2 in 65 nm CMOS technology. For a multi-ASIP platform in which 8 ASIPs are implemented on a same device the configuration load is divided by ten thanks to both ASIP optimizations and an efficient configuration infrastructure.

I. INTRODUCTION

The evolution of recent wireless communication standards aims at increasing the requirements in terms of throughput, robustness against destructive channel effects and convergence of services in a smart terminal. As an example, the fourth generation (4G) of cellular wireless standards aims at providing mobile broadband solution to laptop computer wireless modems, smartphones, and other mobile devices. Diverse features such as ultra-broadband Internet access, IP telephony, gaming services, and streamed multimedia are provided.

Channel decoding is a key feature of a wireless standard. Turbo codes [START_REF] Berrou | Near shannon limit error-correcting coding and decoding: Turbo-codes. 1[END_REF] are frequently adopted in the recent wireless standards to reach a low bit error rate (BER). The high throughput requirement of recent standards often imposes the efficient exploitation of different parallelism levels. In this context, multi-ASIP (Application-Specific Instruction-set Processor) architectures for turbo decoding [START_REF] Brehm | A scalable multi-ASIP architecture for standard compliant trellis decoding[END_REF], [START_REF] Vogt | A reconfigurable multi-processor platform for convolutional and turbo decoding[END_REF], [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF] is a promising approach to reach high flexibility, high throughput and energy efficiency. The high flexibility of these multi-ASIP architectures is provided by the possibility to load new configuration in each ASIP of the platform. In [START_REF] Brehm | A scalable multi-ASIP architecture for standard compliant trellis decoding[END_REF] and [START_REF] Vogt | A reconfigurable multi-processor platform for convolutional and turbo decoding[END_REF], the authors propose to implement the ASIP described in [START_REF] Vogt | A reconfigurable asip for convolutional and turbo decoding in an sdr environment[END_REF] in order to build a flexible multi-ASIP based turbo decoder for LTE requirements. This ASIP is configured through an interleaver memory, a program memory and the Dynamically Reconfigurable Channel Code Control (DRCCC). The DRCCC is a look-up table based unit which allows the configuration of the structure of the convolutional code, the internal data-path, and the configuration memory. Two configurations are stored in this unit, a working and a shadow configuration. The working configuration holds the parameters that are actually used while the shadow configuration is used to prepare the next configuration. One cycle switching can be performed between these two configurations thanks to a special instruction. However, using a specific instruction in the program to switch between two configurations limits the flexibility because the reconfiguration scenario is defined statically. In [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF], the authors present the UDec architecture. It consists of 8 ASIPs (named DecASIPs) interconnected via a Network on Chip (NoC). Within each component decoder the ASIPs are also connected by a ring network for metric exchanges. Each ASIP is configured through a program and a configuration memory. The configuration memory contains several communication parameters which are loaded in internal registers of the ASIP during an initialization step, while the program describes the control flow for the initializing loop and the decoding loops.

Previous work provides an efficient way to reach the high performance requirement of emergent standards. However, the dynamic reconfiguration aspect of these platforms is superficially addressed. All these platforms can be reconfigured through program and configuration memories of each core, but the configuration mechanisms are not optimized for an efficient implementation in a multi-core system. The perpetual increase of throughput of wireless standards reduces the reconfiguration time available between two data frames while the number of cores increases to reach high throughput. This point is particularly challenging as in many standards decoding parameters can be changed as early as one data frame ahead [START_REF]Ieee standard for local and metropolitan area networks part 16: Air interface for fixed and mobile broadband wireless[END_REF], thus it becomes mandatory to aggressively improve reconfiguration times in order to perform the reconfiguration of the whole platform within a single data frame duration. Reaching a reconfiguration time below tens of microseconds will be a key concern to face expected throughput of future communication standards. In this paper, we tackle this problem and propose several optimizations for reconfiguration of multi-ASIP architectures allowing to meet this constraint. Furthermore any possible optimization at the ASIP level will lead to a lower reconfiguration time at the platform level. Thus it is essential to target any possible improvement at the ASIP level. The proposed approach is illustrated through the flexible DecASIP core described in [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF] and highlights how our optimizations enable reaching a low reconfiguration time for a multi-ASIP platform.

The rest of this paper is organized as follows. Section II introduces the UDec multi-ASIP architecture and describes the DecASIP. Section III presents the proposed optimizations to reach an efficient configuration of the multi-ASIP platform. Section IV describes the implementation of the optimizations into the DecASIP processor and the evaluation of the (re)configuration performance. Finally, section V concludes the paper.

II. MULTI-ASIP TURBO DECODER

The turbo decoding system diagram is presented in Fig. 1. It consists of component decoders which exchange extrinsic information via an interleaver (Π) and deinterleaver (Π -1 ) processes. The component decoder 1 receives Log-likelihood ratio (LLR) from a demapper for each bit of a frame in the natural order while component decoder 0 receives LLR in interleaved order. Then, iterative decoding algorithm is performed to decode the frame. The flexibility of a turbo decoding system is reached through several configuration parameters as the interleaver law, the trellis structure, the frame size and the number of turbo decoding iterations. The UDec turbo decoder architecture [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF] shown in Fig. 2 implements the turbo decoding system previously described. It consists of two rows of DecASIPs interconnected via a butterfly Network on Chip [START_REF] Moussa | Binary de bruijn onchip network for a flexible multiprocessor ldpc decoder[END_REF]. Each row corresponds to a component decoder. In the example in Fig. 2 The configuration memory contains all parameters required to perform the initialization of the ASIP while the program memory contains the instructions in order to perform the decoding algorithm. Since the DecASIP is designed to work in a multi-ASIP architecture as described in [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF], it requires several parameters to deal with a subblock of the data frame and several parameters to configure the ASIP mode. Concerning the subblock partitioning, each ASIP is configured with the size and the number of windows it has to decode. Furthermore, the last window size can be different so it corresponds to an additional parameter. In a single binary turbo code mode, the address of the tail bits in memory, the size and the number of windows for the tail bits have to be configured. Parameters for the ASIP mode correspond to the location of the ASIP in the architecture, the number of ASIPs required, the parameter which defines if the current ASIP is in charge of tail bits or not, the target standard (3GPP-LTE, WIMAX, or DVB-RCS) and the scaling factor for extrinsic information. Finally, some seed values are necessary for address generation in order to exchange information over the NoC that connects the ASIPs of each decoder component.

In order to address the dynamic configuration of the UDec Platform through the DecASIP configuration the architecture presented in Fig. 3 is considered. It includes 4 DecASIPs that are configured thanks to a bus-based configuration infrastructure (the details of this infrastructure is out of the scope of this paper). Moreover, A Random generator associated with an Emitter produce the encoded symbols. The considered channel model is an Additive White Gaussian Noise (AWGN). The Input interface distributes the received symbols in the Input memories of each DecASIP. The configuration manager is in charge of the configuration generation. The configuration information is sent through the Master Interface to the Slaves interfaces that finally fill the configuration memory of each DecASIP. This configuration infrastructure provides an efficient solution to update DecASIP configuration memories using unicast, multicast or broadcast transfers. In [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF], authors show that the DecASIP architecture provides high performance and high flexibility. However the topic of dynamic reconfiguration is not addressed. Despite its high flexibility, it presents some lacks to offer an efficient dynamic reconfiguration. The next section points out theses lacks and proposes several solutions to implement an efficient reconfigurable DecASIP for the UDec turbo decoder architecture.

III. PROPOSED OPTIMIZATIONS

Several optimizations are proposed to reach an efficient dynamic reconfiguration of the DecASIP architecture. The first optimization is related to the storage of configuration parameters. Currently, some parameters are stored in the configuration memory and others are provided in the program instructions directly [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF]. The second optimization deals with the way used to load the configuration memory through the configuration memory organization. The third optimization corresponds to the development of a generic program independent of the configuration to be performed.

T E S T B E N C H U D E C A R C H I T E C T U R E C O N F I G U R A T I O N I N F R A S T R U C T U R E

A. Configuration parameters storage

To reach (re)configuration efficiency, we propose to move all parameters from the program memory to the configuration memory. This solution allows to (re)configure a single memory to change all the configuration parameters (instead of loading both new program memory and configuration memory). Furthermore, once the ASIP is configured, the configuration memory can be accessed without any conflict since the configuration is loaded inside internal registers of the ASIP during the initialization step. This is a key point to prepare the next configuration if necessary. Indeed, the entire next configuration can be loaded in the configuration memory during the processing of the current data frame. Thus the configuration loading can be partially or completely masked. If the configuration loading is completely masked, the configuration overhead consists in the initialization step only. However, this modification impacts the area of the configuration memory since it is necessary to store more parameters. It also impacts the number of registers inside the ASIP in order to store these parameters after the initialization step. Finally, it impacts the initialization step duration since this step consists in reading the configuration memory and then storing each parameter in the corresponding register. The program in its current form contains eight configuration parameters. So eight parameters have to be added to the configuration memory to obtain a parameter independent program memory. The next sub-section presents a way to integrate these new parameters in a smart memory organization.

B. Configuration memory organization

In order to improve the (re)configuration of the ASIP, it is essential to analyze the organization of the configuration memory. The parameters stored in the configuration memory are very specific. They can be divided in four categories: 1) domain dependent (for component decoder 0 or component decoder 1 in Fig. 1), 2) identical for all ASIPs, 3) different for all ASIPs and 4) different for the last ASIPs which decode the tail bits in a single binary turbo code mode. All these characteristics need to be taken into account in order to build a low latency configuration process. Furthermore, in a multi-ASIP context, it is necessary to only configure ASIPs required for a specific execution context (it means that only a subset of ASIPs may be required depending on the performance to be achieved). A smart memory organization should allow an efficient broadcasting of the configuration parameters to the required ASIPs. thus we propose to group the parameters depending on the previously described categories. Four groups which occupy four different parts of the configuration memory are defined.

As different memory architectures can be considered, it is important to define the best size for the memory. Table II shows that the choice of the width and depth of the memory impacts the time required to load the configuration into the ASIP and the area of the memory on the chip. We evaluate five solutions from 14 bits to 32 bits memory width. Since the number and the size of each parameter are fixed, the depth of the memory decreases when the width increases. Furthermore, in order to take into account the final implementation of the different memory alternatives, the depth and width of each memory must be a multiple of 2. It represents the minimal constraint to design the memory (this constraint is related to the memory technology considered for our design). Depending on the alternative, the level of memory usage changes. Results of Table II show that a 26 bits memory width is the most efficient one (97.3%) while a 24 bits memory width is inefficient (65.9%). The time required to configure the ASIP is proportional to the number of memory lines to be read. Each clock cycle, the ASIP reads one data from the memory and configures the corresponding register. One more clock cycle is necessary to initialize the reading loop, and another cycle is required to complete the initialization of the ASIP. For example, 12 cycles are needed to load the configuration in the ASIP with a 32 bits memory width while 24 cycles are necessary for a 14 bits memory width. Moreover, the memory width has an impact on the global multi-ASIP platform. Indeed, a large memory width increases the number of connections between each ASIP and its configuration memory and between each configuration memory and the link that is used to load the configuration parameters in the memories (Fig. 3). Thus, a trade-off between the initialization time, the memory usage and the global impact on the platform has to be found. The 26 bits memory width is an interesting tradeoff. This memory alternative offers a fast configuration time (13 cycles) and the highest memory usage efficiency (97.3%). Finally, the impact on the entire platform is low compared to the current solution that implements a 24 bits memory width. This point will be further discussed in the result section.

Table I shows the 26 bits width configuration memory organization. The memory is organized as follows: (1) from address @0 to @1, parameters can be different for each ASIP. Furthermore, to optimize the initialization step of the ASIP, the parameter Tail which indicates if the ASIP has to perform or not the tail bits is included in this group. Only the last two ASIPs are concerned by the tail bits in a single binary turbo code mode; (2) from address @2 to @6, the parameters are domain dependent; (3) from address @7 to @10, the parameters are the same for all ASIPs. This organization allows a good way for a fast reconfiguration at the platform level. Indeed, multicast mechanisms can be used to load the configuration in order to minimize the data transfers load. In this context, two multicast transfers are necessary to send domain dependent parameters to all ASIPs and one multicast transfer for parameters that are the same for all ASIPs. Finally, unicast transfers are used to load the ASIP dependent parameters.

C. Generic program

We propose to simplify the (re)configuration mechanism by using a unique generic program stored in a ROM memory. Since all parameters contained in the program memory have been moved to the configuration memory, three possibilities exist for the program: two programs for single binary turbo code and one program for duo binary turbo codes. In single binary mode, after the initialization step, the last two ASIPs have to perform the tail bits while other ASIPs execute NOP operations. So, a particular program is loaded in these last two ASIPs. In duo binary mode, data frames are decoded after the initialization step. In order to merge these three possible programs, the new unique program has to be able to tackle these three cases. For this purpose, the program which integrates the tail bits computation is used as a reference. We have chosen to modify the Fetch pipe stage of the ASIP in order to detect and replace the instructions for tail bits with NOP instructions if the ASIP is not concerned. The value of the bit Tail stored in the configuration memory (Table I) determines if the ASIP is concerned or not by tail bits decoding. In duo binary mode, no tail bits have to be decoded. So, using a unique program in this mode adds 12 extra NOP instructions before the decoding step which corresponds to tail bits computation in single binary mode. However, these extra clock cycles are negligible regarding the number of cycles required to perform the decoding on one entire data frame (for example, around 3000 cycles are necessary to execute the entire program on a 960 bits data frame in single binary mode with 8 ASIPs applying 6 iterations).

Optimizations described in this section allow to reduce the (re)configuration impact: 1) locally through the optimization of the storage of configuration parameters to efficiently use the memory capacity and 2) globally thanks to the new memory organization and the generic program which reduce the total configuration load to be transferred through the configuration infrastructure (Fig. 3) when a new configuration has to be performed. The next section presents the implementation and the impact of proposed optimizations in the DecASIP.

IV. IMPLEMENTATION AND RESULTS

A. ASIP implementation

Optimizations described in Section III have been implemented on the DecASIP presented in [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF]. To provide more flexibility for future configuration organization, input pins have been added to inform the ASIP about the size of the configuration. The ASIP was modeled in LISA language using Synopsys (ex. Coware) Processor Designer tool. Synthesis of the previous and the new cores was done with 65nm CMOS technology with a clock frequency objective equals to 500MHz. Synthesis results have been extracted to determine the impact of the optimizations on the pipeline and the register file of the ASIP.

To evaluate the impact of the new features on the ASIP area, we extracted the area synthesis results for each pipeline stage of the ASIP. This ASIP consists of 10 pipeline stages as shown in Fig. 4. The reconfiguration optimizations presented in this paper do not affect all the stages. Only three stages are impacted. Indeed, from BM1 to EXTR-CH, stages are dedicated to data computation and this part of the ASIP pipeline is not directly concerned by the configuration optimizations proposed in this work. Moreover, The pre-fetch stage is identical in the two implementation of the DecASIP. On the other hand, fetch (FE), decode (DC), and operand fetch (OPF) stages have seen their area increased compared to the previous ASIP. Table III presents area synthesis results for each impacted pipeline stage for the original ASIP and the new version. The proposed optimizations were implemented along the pipelines stages as follows:

• FE: The FE stage insures the automatic replacement of instructions for tail bits computation by NOP when the ASIP is not concerned by tail bits decoding. • DC: This stage is mainly impacted by the transfer of all flexible parameters in a unique configuration memory. Instead of a direct access to some parameters in instruction code words, parameters are now read from registers. Thus, the number of connections with the register file has been increased. • OPF: This stage is impacted by the new configuration memory organization since it is in charge of the parameter registers initialization. The area overhead comes from the increasing number of parameters in the configuration memory and by added control structures that manage the configuration size flexibility. Since more configuration parameters are read from the configuration memory, the number of connections with the register file has been increased to configure additional registers. Regarding results from Table III for the complete pipeline of the ASIP, we observe that despite of the different area overheads on the first pipeline stages caused by our optimizations, the global area overhead for the complete pipeline is 2.6% (0.002 mm 2 ). Indeed, the most complex part of the pipeline consists of the execution stages that implement the decoding algorithm.

On the register file side, this increasing is around 14.5% (0.011 mm 2 ).

Table IV cASIP and the new version optimized for dynamic reconfiguration. We observe that the global logic overhead on the ASIP is 2.3% (0.004 mm 2 ). This overhead is mainly due to the register file. So, the increasing complexity of the ASIP is mainly due to the additional internal registers used to store the configuration parameters read from the configuration memory.

B. Dynamic reconfiguration performance

In this section, we evaluate the gain of proposed optimizations on reconfiguration timing performance. For this purpose, we consider the following reconfiguration steps:

1) Memories loading: The first step of the configuration process is the transfer of the configuration parameters in the configuration memory of one or several ASIPs. 2) ASIP Initialization: When the configuration parameters are available in the memory, the ASIP can start the initialization process. During this step, the ASIP reads the configuration stored in the configuration memory and initializes the internal registers. Then, the ASIP is ready to execute the computation on the input data frame. Table V compares the configuration and program load (in bits) for the proposed ASIP, the original DecASIP presented in [START_REF] Murugappa | A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding[END_REF] and the ASIP presented in [START_REF] Vogt | A reconfigurable asip for convolutional and turbo decoding in an sdr environment[END_REF]. For one ASIP, we observe that the proposed ASIP can be configured with 286 bits instead of 976 bits thanks to the generic program described in Section III-C while 1463 bits and the complete interleaver table are required for the ASIP in [START_REF] Vogt | A reconfigurable asip for convolutional and turbo decoding in an sdr environment[END_REF]. Moreover, the new memory organization proposed in Section III-B allows the optimization of the configuration memory loading. Indeed, parameters are sent to several ASIPs through multicast mechanism presented in Section II. Thus, in a multi-ASIP context, each original ASIP has to be configured with its own configuration and program memory while configuration memory of the proposed new ASIP can be loaded using a multicast mechanism as follows: 52 bits are independently loaded in each ASIP. ASIPs that compose the same decoder component (Fig. 1) are loaded with 130 common bits. Finally, 104 configuration bits are broadcasted to all ASIPs. Thanks to this new configuration memory organization, the impact of the number of ASIPs on the configuration load is significantly reduced: n.52 bits instead of n.976 bits, where n is the number of ASIPs implemented. For example, if 8 ASIPs are implemented in a multi-ASIP platform, the configuration load to configure the 8 ASIPs is 7808 bits with the original DecASIP, 11704 bits for [START_REF] Vogt | A reconfigurable asip for convolutional and turbo decoding in an sdr environment[END_REF] plus the interleaver tables and 780 bits with the proposed ASIP. In this case the configuration load is divided by 10 and 15 compared to the DecASIP and the ASIP from [START_REF] Vogt | A reconfigurable asip for convolutional and turbo decoding in an sdr environment[END_REF] respectively. Finally, it is interesting to note that the configuration infrastructure presented in Section II providing multicast mechanism has a low area overhead that represents 1.4% (i.e. 0,01 mm 2 ) of the area of the The new configuration memory area is reduced by 7.5% (i.e. 194 µm 2 ) compared to the original implementation. Its new organization has also an impact on the initialization time of the ASIP. Indeed, for each new configuration, the ASIP reads the parameters from the configuration memory and initializes the internal registers. The new memory organization reduces the number of read accesses to the memory. Only 11 read accesses are necessary instead of 15 in the original ASIP. Thus the initialization time is reduced by 4 cycles. Thus, the ASIP can be reconfigured in 12 clock cycles if we assume that one extra clock cycle is necessary to drive the reset pin of the ASIP. Furthermore, when the initialization step is performed, the ASIP does not read the configuration memory until the next initialization. Hence, during the computation on a data frame, configuration parameters can be loaded in the configuration memory. The memory loading process can be partially or totally masked depending on when the reconfiguration order is triggered. If the loading process is masked, the complete (re)configuration of a multi-ASIP platform represents an overhead of around 12 clock cycles. This low (re)configuration time overhead allows the implementation of such an optimized ASIP in multi-ASIP architecture for future high throughput and low latency requirements.

The timing performances for turbo decoding of the new and the original version of the DecASIP are purely identical. Indeed, the pipeline architecture is still the same and both implementation are able to reach the maximum frequency of 500MHz. However, in double binary mode, the new version of DecASIP requires 12 extra clock cycles after the initialization phase to start decoding. Since the initialization phase for the new version is 4 clock cycles shorter than for the original version, the new DecASIP requires 8 extra clock cycles before the beginning of the decoding in double binary mode while it is able to start the treatments 4 clock cycles before the original DecASIP in simple binary mode. Nevertheless, we can disregard these impacts in front of the decoding time of a data frame that is identical for both version of the DecASIP.

V. CONCLUSION

Multi-ASIP architectures for turbo decoding is a promising approach to reach high flexibility and high throughput requirements imposed by new emerging communication standards. Due to the increasing throughput and the reduction of latency between two data frames, the configuration of such multi-core platforms is becoming a critical point. In this paper, we propose to optimize a multi-standard ASIP for an efficient (re)configuration in a multi-ASIP context. Results show that configuration load of the ASIP has been reduce by 70% compared to the original implementation. Furthermore, in a multi-ASIP context implementing 8 ASIPs, the proposed smart configuration memory organization allows dividing the configuration load by 10 using a multicast mechanism. Future work targets the evaluation of the power consumption in order to analyze the impact of our optimizations with respect to power and energy that are main issues.

Figure 1 .

 1 Figure 1. Turbo decoding system

Figure 3 .

 3 Figure 3. Architecture of the proposed configuration infrastructure for the UDec platform.

  shows the global area comparison between the De-

		Pipeline	Register	Total
			file	ASIP
	DecASIP	0.078	0.076	0.175
	New ASIP	0.080	0.087	0.179
	Diff.	0.002	0.011	0.004
		+2.6%	+ 14.5% +2.3%
		Table IV
	ASIP AREA COMPARISON IN mm 2

  4 DecASIPs

		Config	Prog.	1	n
		param.	mem.	ASIP	ASIPs
	New ASIP	286	-	286	n.52+260+104
	DecASIP	336	640	976	n.976
	Gain	14%	100%	70%	90% (n = 8)
	[5]	383 +	∼1080 1463 +	n.1463
		Interl.		Inter.	n.Interl.
	Gain	25%	100%	80%	93% (n = 8)
			Table V
	CONFIGURATION AND PROGRAM BIT LOAD COMPARISON IN BITS
	that are implemented in the considered UDec platform. Moreover,
	the configuration of the 4 DecASIPs are performed in 2µs.


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After African trades: changing in Cignana landscape between Late Antiquity and Medieval age.

Fabrizio

  Ducati -PhD Student, University of Palermo, Italy fabrizio.ducati@unipa.it Cignana is the name of a district 20 Km SE of Agrigento, on the southern coast of Sicily. Between the II and III century A.D., a luxurious villa with mosaics and small baths -partially excavated by the Soprintendenza of Agrigento -was built in the same place as a previous rural settlement (IV century B.C.). Since 2007, the University of Palermo has carried out surveys which show how the Villa, with regard to this area, represented the main site during the early-middle imperial age. The land around is strewn with small contemporary rural settlements, often existing since the Late-Classic or Hellenistic period. Italian sigillata, African Red Slip ware (Hayes 3, 8 and 9) and African Cooking ware (Hayes 23B, Hayes 196 and 197) are the most common finds. Starting from the last decades of the IV century, a first change occurs in the Cignana landscape: some long-life sites disappear, others grow in size and became large villages. One of these is located on the site of the Villa and endured until the VII century: it consists of many simple rectangular constructions, sometimes with outdoor working areas. However, this village does not seem to play its previous hierarchical role. There are three other similar villages located in easily accessible places, at the same altitude, close to springs and to the road network. As shown by the number and variety of African imports, V and VI centuries A.D. represent the period of huge expansion for these villages: Viticchié, Margio Canneddaro and, perhaps, Mortilli also endured until the first decades of the VII century, albeit reduced in size. This is suggested by sherds of the later typologies of African pottery, especially amphorae (Keay 61, Keay 34) and African Red slip ware (Hayes 105, 108 and 109, dish Sidi Jdidi 8). Later, we do not have reliable chronological markers until the XI-XII centuries, except in a few small sites (Casazza and Celsovecchio). The ending of big African trades has led to a gap in our information and has produced the image of an abandoned landscape, characterized by a dramatic decrease of population. However, It may be accounted for by our limited knowledge of early medieval pottery, especially common ware local production. Faint traces of life are shown by a few fragments of Rocchicella cooking pots (VIII -early IX) and amphorae with grooved handles, similar to the finds at S. Agata al Carcere in Catania. The presence of Rocchicella ware in this area of Sicily might suggest important transformations in the socio-political and cultural background. The introduction of this new typology, with specific technical and decorative features, is commonly linked with the arrival in Sicily of foreign populations, probably from the east, and allocated for military purposes.Change and Resilience: The Occupation of Mediterranean Islands in Late Antiquity Detail. Rocchicella cooking pots: fabric and decoration African Red Slip ware: Hayes 109 and Sidi Jdidi 8 Amphora with grooved handle and Rocchicella cooking pots Cignana: villages of V-VI century A.D.


Giorgia Scetta

Nathan Selles

Patrick Heuillet

Matteo Ciccotti
email: matteo.ciccotti@espci.psl.eu

Costantino Creton
email: costantino.creton@espci.psl.eu

Cyclic fatigue failure of TPU using a crack propagation approach

Keywords: cyclic fatigue, thermoplastic elastomers, energy release rate, crack propagation

Introduction

Thermoplastic polyurethanes elastomers (TPU) are an interesting class of thermoplastic materials that appeared on the market around 1960 [START_REF] Holden | Thermoplastic Elastomers[END_REF]. Soft TPUs display a rubberlike behaviour at ambient temperature without any need for chemical crosslinking. They are typically composed of long polyether or aliphatic polyester flexible chains called soft segment (SS) and short sequences containing an isocyanate linked with a short chain extender called hard segments (HS). Because of their chemical incompatibility SS and HS tend to separate in a two-phase system, while the presence of inter-hydrogen bonding between urethane units causes the HS to aggregate in small and hard domains (HD) of nanometric dimensions. These HS clusters connect the polymer chains with physical links, as schematically showed in Fig. 1 (a), and prevents them to flow at working temperature. When the softening temperature of the hard phase is reached, the polymer flows and can be easily and reversibly shaped. The properties of TPU can be tuned to achieve specific strength and elasticity by changing the chemical nature and relative proportion of either the hard-polyurethane group or the long soft segment. The HS microdomains are generally sufficient to reinforce the materials without any additional filler. Classical elastomers on the other hand (Fig. 1 (b)), need to be chemically crosslinked and filled (with carbon black and/or silica) to show the combination of reversible elasticity and toughness typical of commercial rubber.

The peculiar microstructure of TPU provides them with some advantages compared with conventional rubbers such as the possibility to be easily processed and reprocessed through rapid processing techniques as injection moulding and extrusion. Moreover, they also possess an excellent abrasion resistance as well as blood and tissue compatibility, so that they have been rapidly used in numerous applications such as footwear, medical cables, wheels or dampers. Nevertheless, the suitability of TPUs in applications requiring the material to sustain cyclical loads and to prevent sudden failure or fatigue crack growth requires a robust characterization method in cyclic fatigue. Opposite to rubbers, where cyclic fatigue resistance has been thoroughly studied [START_REF] Tee | Recent advances on fatigue of rubber after the literature survey by Mars and Fatemi in 2002 and 2004[END_REF], [START_REF] Mars | A literature survey on fatigue analysis approaches for rubber[END_REF], only few investigations have been carried out in TPUs [START_REF] Major | Characterization of Thermoplastic Elastomers for Design Efforts[END_REF]- [START_REF] Mars | Fatigue Characterization of a Thermoplastic Elastomer[END_REF]. This shortcoming mainly comes from the complex visco-plastic character of TPUs at large strains. The mechanical properties of TPUs are indeed deeply related to their complex strain-dependent morphology [START_REF] Bonart | X-ray investigations concerning the physical structure of cross-linking in segmented urethane elastomers[END_REF]- [START_REF] Yeh | In-situ studies of structure development during deformation of a segmented poly(urethane-urea) elastomer[END_REF]. The change in size and orientation of HD with the application of strain , induce mechanical hysteresis in cyclic loading and a permanent modification of the small-strain modulus and maximum extensibility of the material. Additionally, the absence of chemical crosslinking induces a significant residual plastic strain (and stress softening) that increases with cyclic sample deformation. Such complex change in structure and strain dependent properties are not straightforward to include in the common framework of fracture mechanics used to assess cyclic fatigue in rubbers that are instead mostly elastic. In this work, we use a pure shear geometry (PS) to investigate how a crack propagates in a typical commercial soft TPU submitted to a cyclic loading. We used two different testing protocols and assessed their suitability and the effect on the crack propagation rate. Finally, within the context of possible replacement of filled rubbers with soft TPU and in order to highlight the key differences between these classes of materials, we compared our fatigue results on TPU with those obtained on a filled SBR having a similar shore hardness and small-strain modulus which in principle could be used in similar industrial applications.

The classic fracture mechanics approach for cyclic fatigue in rubbers and calculation of G

Since the last century, the field of cyclic fatigue resistance was largely developed for crosslinked elastomers [START_REF] Mars | A literature survey on fatigue analysis approaches for rubber[END_REF], [START_REF] Mars | Factors That Affect the Fatigue Life of Rubber[END_REF] and two main approaches have been used to define their cyclic fatigue resistance: onset of crack nucleation [START_REF] Cadwell | Dynamic Fatigue Life of Rubber[END_REF], [START_REF] Marco | Fast prediction of the wöhler curve from thermal measurements for a wide range of NR and SBR compounds[END_REF] and crack propagation rate [START_REF] Thomas | Rupture of Rubber V Cut Growth in Natural Rubber Vulcanizates[END_REF], [START_REF] Lake | Fatigue and Fracture of Elastomers[END_REF]. The first method defines fatigue resistance as the maximum number of cycles at a given strain or stress to achieve a definite loss in strength or end of life of the material. The second one seeks to evaluate the crack growth rate of a pre-existing crack per cycle as a function of applied energy release rate G [START_REF] Rivlin | Rupture of rubber. I. Characteristic energy for tearing[END_REF]. We focused on the second approach that has in our view several advantages:

 The use of the energy release rate G (instead of strain or stress) allows to compare samples of different sizes tested under different loading conditions.  Opposite to crack nucleation, where small defects (that are potentially precursors of the macroscopic failure) are randomly distributed in the sample, in notched samples the macroscopic cut dominates over all the pre-existent defects leading to more reproducible results.  It is suitable for applications where cracks are nucleated from the start, but lifetime is limited by propagation.

Fatigue resistance is generally expressed in terms of crack propagation per cycle dc/dn vs maximum applied energy release rate G. As reported in the literature [START_REF] Lake | Fatigue and Fracture of Elastomers[END_REF], [START_REF] Lake | Mechanical Fatigue Limit for Rubber[END_REF], irrespectively of their composition elastomers typically show similar trends of dc/dn vs G, which can be summarized as follows: for values of G lower than a critical threshold G t and in the absence of any chemical attack, the crack does not propagate. For G > G t , dc/dn can be described by a monotonically growing function of G, which presents a linear region for small G, followed by a power law for larger G.

Finally, for G larger than a critical value G c , generally named "toughness" in the literature of filled rubbers, a catastrophic propagation is observed and the material ruptures in a few cycles. Following the crack propagation approach, fatigue resistance in rubbers is typically carried out using samples in the pure shear geometry (PS) [START_REF] Yeoh | Fracture Mechanics of Bond Failure in the 'Pure Shear' Test Piece[END_REF] which corresponds to a wide and thin rectangular shape. One of the main advantages of using the PS geometry is that it allows an easy evaluation of the energy release rate G() as a function of the applied stretch which is independent of crack length as shown by the seminal work of Rivlin and Thomas [START_REF] Rivlin | Rupture of rubber. I. Characteristic energy for tearing[END_REF] and can be calculated as:

(

Where is the integral under the stress-strain curve of an unnotched sample with the same geometry.

A common approach to calculate G() in filled rubbers is to pre-strain (or precondition) the unnotched sample for some thousands of cycles at higher values of than those used in fatigue testing and then to evaluate G() by cyclically straining the accommodated sample at different values of increasing stretch. In this way, most of transient effects related to Mullins damage in the first cycles are avoided in the calculation of the relevant G for long term cyclic fatigue.

Applying this method to TPUs without modification creates several challenges that are the focus of this paper. The first issue is that TPUs typically show significant residual deformation when unloaded. While the sample is cyclically loaded at a constant maximum applied stretch, the residual deformation increases during cycles, and hence the stress-stretch curve is modified and the actual energy release rate seen by the crack is not constant. Unlike conventional rubbers, the applied energy release rate G is a function of both the maximum applied stretch and the number of cycles (n): G(n). Moreover, if the sample is allowed to unload up to  min = 1, calculated using the initial height h 0 of the pristine sample, the residual plastic stretch causes an extensive buckling during unloading cycles that may induce additional undesirable damage in the sample. Furthermore, since TPUs are typically tested in cyclic fatigue at significantly larger stretch than filled rubbers (as will be showed in Section 4.3), a second important issue needs to be addressed. The well-established preconditioning procedure cannot be easily implemented to eliminate transient effects, since it would involve very large stretch that are likely to damage the sample. Also, if the sample is preconditioned to a stretch p that is only slightly larger than the cyclic stretch to be tested, the values of the energy release rate will depend on this maximum stretch: G(p) applied during the preconditioning. Defining in which conditions should the cyclic load be applied in TPU to obtain reliable and reproducible crack propagation data is precisely the objective of this work.

Materials and methods

TPU

The TPU is a polyester-polyurethane block copolymer kindly provided by BASF (commercial name: EC 60 A 10 Elastollan©). The volume fraction of hard segments = 0.24 and the average distance L=12-15 nm between hard domains was estimated from X-Ray diffraction of pristine samples using the lamellar model Fourier analysis [START_REF] Strobl | Direct Evaluation of the Electron Density Correlation Function of Partially Crystalline Polymers[END_REF], [START_REF] Koberstein | Simultaneous SAXS-DSC Study of Multiple Endothermic Behavior in Polyether-Based Polyurethane Block Copolymers[END_REF]. The glass transition temperature (T g ) of -50°C was obtained by Differential Scanning Calorimetry (DSC) at 10°/min. PS samples were injection moulded in a BOY 50M injection moulding machine (Boy machines Inc., US) at the French Rubber and Plastics Research and Testing Laboratory (LRCCP) using the procedure recommended by BASF. The temperature used in the injection procedure is summarized in Table 1. We remark that in TPUs the injection procedure may induce a preferential orientation which in turn would affect the final result. In order to overcome this difficulty, in this study all PS samples were injected so that the largest side perpendicular to injection direction.

Large strain tensile tests

Uniaxial tensile tests were performed on dog-bone samples (with a cross section of 2x4 mm cut from a square plate) using an Instron 5590 tensile machine (capacity of 2kN). The samples were deformed at constant stretch rate up to rupture or in cyclic conditions at the same . In the second case, 10 cycles were performed up to maximum stretch of 20, 40 and 100% of the stretch at break  b .

Dynamic mechanical analysis (DMA)

DMA analysis was performed on circular disks of 10 mm diameter and 2 mm thickness cut from a square plate using a METRAVIB (DMA+450 series, FR). Two cylinders are glue to three metallic supports placed in metallic grips. The middle support moves and generates an oscillatory displacement up and down between 0.005% and 100% of strain at temperature of 23°C and frequency of 10 Hz.

Fracture toughness

Fracture toughness and cyclic fatigue tests were carried out using PS samples of length = 45 mm, height (h 0 ) =5 mm and thickness= 1 mm with a single crack of 22 mm cut along the direction parallel to the sample's length. Each cut was made in non-relaxing conditions on the clamped sample and after the application of a small pre-stretch. For measuring the fracture toughness , the material was stretched stretch rate up to fracture. The minimum stretch to propagate the crack  c is determined from the point where the stress undergoes a maximum value in the stress-stretch curve of notched samples using the same procedure adopted in other works [START_REF] Zhang | Fatigue fracture of nearly elastic hydrogels[END_REF], [START_REF] Sun | Highly stretchable and tough hydrogels[END_REF]. At the crack propagation conditions the equivalence G =  holds [START_REF] Rivlin | Rupture of rubber. I. Characteristic energy for tearing[END_REF] and the value of fracture toughness is defined as where W( ) is calculated by integrating the stress-stretch loading curve of pristine PS samples between  and .

Cyclic fatigue in Styrene-Butadiene Rubber

We used SBR rubber filled with carbon black. The SBR has a mass M n of 120 kg/mol and a polydispersity of 1.94 and was provided by the Michelin research center. Its styrene content is 15 wt% and T g measured by differential scanning calorimetry (DSC at 10°C/min) is -48°C (very similar to that obtained for unfilled TPU). The detailed composition is reported in Table 2 as provided by Michelin:

All samples were prepared, moulded and cured by Michelin. For tensile tests, samples were cut in a dog-bone shape with a cross section of 2x4 mm and loaded at a stretch rate =4 s -1 . For crack propagation experiments, pure shear samples were moulded in two geometries. PS large : length = 157 mm, height = 13 mm, thickness = 2 mm and PS small : length = 35 mm, height = 6 mm, thickness = 0.8 mm. Uncracked samples were preconditioned at  max =1.27 for 1000 cycles to get rid of transient effects and used to calculate G() = .For each preconditioned sample two edge cracks and a centre crack were cut with a fresh razor blade in the direction parallel to the sample's length. Then the notched samples were strained for 50.000 cycles at values of G corresponding to  < max to accommodate the crack tip before starting the measurement of dc/dn. All tests were performed at 10 Hz.

Materials characterization 3.1 Small strain properties

The filled SBR and TPU have similar values of the storage shear modulus ' at low strain, and both materials display a decreasing modulus with applied strain accompanied by an increase of Tan δ, as shown in Fig. 2. This strain softening, known as Payne effect, is common in filled rubbers and is generally associated to the onset of damage of the filler network [START_REF] Payne | Hysteresis in rubber vulcanizates[END_REF]. The comparative analysis allows to appreciate that SBR and TPU present a similar form of damage, but it occurs at larger strains in TPU ( 10%). Moreover, the small strain regime in TPU is less dissipative (lower Tan δ). Both these observations reflect a more elastic character with limited structure modifications up to 10% strain in TPU.

Uniaxial tensile tests

Fig. 3 (a) shows representative stress-strain curves for TPU and filled SBR. The linear regime is only observed for λ<1.2 and is similar for both materials as underlined by the close values of small strain moduli estimated by calculating the linear fitting of the stress-stretch curve between  = 1 and  . The values of the modulus are reported in Table 3 (data from [START_REF] Mzabi | A critical local energy release rate criterion for fatigue fracture of elastomers[END_REF]) along with the values of strength σ b and stretch  b at break for both materials.

After the linear regime, both materials display stress-softening followed by strain-hardening although to a very different extent. Among all factors contributing to the mechanisms of crack growth, viscoelastic dissipation is known to play an important role in elastomers [START_REF] Persson | Crack propagation in rubber-like materials[END_REF], [START_REF] Morishita | Velocity transition in the crack growth dynamics of filled elastomers: Contributions of nonlinear viscoelasticity[END_REF]. In Fig. 3 (b) we show uniaxial step-strain cycles of deformation for TPU and SBR. Both materials exhibit cyclic hysteresis that is more pronounced in the first cycle and then gradually decreases in the following ones. This phenomenon also known as Mullins effect, was already observed both in filled rubbers and unfilled TPU [START_REF] Sui | Strain softening of nano-scale fuzzy interfaces causes Mullins effect in thermoplastic polyurethane[END_REF], [START_REF] Qi | Stress-strain behavior of thermoplastic polyurethanes[END_REF]. Although there is no generally accepted microscopic explanation, the Mullins effect is often attributed to structural modifications of the filler network or of the hard domains respectively for filled rubbers and unfilled TPUs [START_REF] Sui | Strain softening of nano-scale fuzzy interfaces causes Mullins effect in thermoplastic polyurethane[END_REF], [START_REF] Mullins | Softening of rubber by displacement[END_REF], [START_REF] Diani | A review on the Mullins effect To cite this version : HAL Id : hal-00773015[END_REF]. It is important to note that despite its thermoplastic character, the fraction of dissipated energy at fixed applied strain is lower for TPU than for filled SBR. This is true in the 1st cycle, characterizing damage (Fig. 4Fig. 4(a)) and in the 10th cycle (Fig. 4(b)) representing stabilized cycling conditions where an excessive hysteretic behaviour is often undesirable, since it may lead to heat build-up, reducing the material's ability to resist crack propagation.

Fracture toughness

Table 3 also reports the value of calculated for notched SBR and TPU. Despite similar linear properties of the two materials, TPU is almost one order magnitude tougher than the SBR filled rubber at 23°C indicating clearly that large strain properties (that predominate around the crack tip singularity) play an important role in the toughness.

Results and discussion

Effect of the loading conditions

The fatigue resistance of TPU samples was probed with two different loading protocols as schematically shown in Fig. 5: either a minimum value of stress min= 0 was imposed at each cycle (Protocol A) or the sample was unloaded to the displacement corresponding to its initial length (min= 1)(Protocol B), as it is classically done for SBR.

With Protocol A, the sample is strained between an imposed and a variable minimum stretch , corresponding to the imposed condition min=0, that increases in time due to residual plastic strain experienced by the sample, as illustrated in Fig. 5 (a). Therefore, the applied value of G decreases with the number of cycles until a steady-state (or shake down) is reached [START_REF] Zhang | Fatigue of double-network hydrogels[END_REF], [START_REF] Bai | Fatigue fracture of tough hydrogels[END_REF].

With Protocol B the sample is strained between imposed nominal values of both and , implying that the sample will undergo compressive stresses and buckle when the stretch decreases below the residual plastic stretch , as illustrated in Fig. 5(b).

In classical rubbers the two loading schemes A and B are substantially identical, since the residual plastic strain is generally negligible and it stabilizes after a few cycles.

Evaluation of G in TPU.

As discussed in the introduction, we did not use any pre-conditioning procedure in TPU, unlike what is classically done for filled chemically crosslinked rubbers. Fig. 6 (a) shows the stress-stretch curve for TPU at =2.2 for the 1 st , 200 th , 5.000 th and 10.000 th cycle and the corresponding values of G as a function of the number of cycles are reported in Fig. 6 (b). Most of the softening and the accumulation of plastic strain occurs over the first cycles of the experiment, the stress-stretch curve eventually stabilizes between 5.000 and 10.000 cycles and the value of G is very stable during further cycles. Even after this shake-down, the stress-stretch curve of TPU shows a residual hysteresis, as it is also the case for classical thermoset rubbers. Nevertheless, as previously indicated for uniaxial cyclic experiments, for the same value of maximum stretch the hysteresis is comparable or lower for TPU. Fig. 7 shows an example of stabilized curve of TPU obtained with the protocols A (a) and B (b). The value of elastic energy density per cycle (W()) was always calculated using the positive area below the unloading curve (shaded in Fig. 7 (a) and (b)). Interestingly, for comparable values of the maximum stretch, the unloading path of the stress-stretch curve is not much affected by the protocol (A or B) and the calculated values of W() (and thus G) overlap (as it can be appreciated in Fig. 8) while, on the other side, in case B the stress-stretch curve per cycle results in a higher hysteresis than method A. Fig. 8 reports the values of G() obtained without any pre-conditioning but using the 10.000 th unloading curve (after shake-down) for different values of increasing applied deformation for both protocols A and B. All the data can be consistently fitted with a linear relationship for the curve G(.

Fatigue Failure

Once G( ) has been experimentally calibrated on unnotched samples, crack propagation experiments under cyclic loading were carried out on notched samples for a different number of cycles at different values of applied stretch corresponding to the selected values of G(λ). For each fatigue experiment, we evaluated the crack length c during the cycles by taking images of the crack tip at regular time intervals and identifying the maximum value of the x-coordinate of the contour of the crack in the open position, as shown in Fig. 9(a). The crack profile is clearly blunted rather than sharp in TPU. To quantify the difference in crack shape between TPU and SBR in a classical cyclic fatigue experiment, we calculated the crack tip radius in the open position using a parabolic fitting (yellow line in Fig. 9(a)). Fig. 9(b) reports an example of the fitted radius for TPU (Protocol A) and SBR tested at: G 10.000 J/m 2 and G 1.800 J/m 2 respectively, corresponding to similar values of dc/dn for both materials. After a first transient stage, where the crack tip changes shape, both TPU and SBR show a constant value of the fitted radius. In similar propagation conditions, TPU shows a considerably blunted profile and a higher radius than SBR according the higher value of G (and λ) required to the propagate the crack in cyclic fatigue.

Fig. 10 (a,b) reports the crack length c as a function of the number of cycles for TPU tested either with protocol A (no buckling) or with protocol (B). In the case of protocolA, at the beginning of the experiment, the crack extension per cycle is higher and gradually approaches a steady state growth rate (constant dc/dn). This behaviour, may be related to stress accommodation: in the first cycles in fact, the stress singularity around the crack tip is more pronounced and the material is not "accommodated" yet. Moreover, in the case of TPU the residual plastic strain in the bulk is not stabilized yet. To evaluate the value of crack propagation per cycle expressed as dc/dn we only considered the data points after 10.000 cycles and we evaluated the slope of the curve c vs the number of cycles.

In the case of protocol B, the crack increases almost linearly with the number of cycles, and we also evaluated the slope of the curves above 10.000 cycles as is conventional. The final results of cyclic crack propagation for TPU tested with both protocols and for SBR, are reported in Fig. 10 (c) as dc/dn vs applied G. In case of SBR, the values of dc/dn obtained for PS small (which has dimensions comparable with those used in TPU) were took from the PhD thesis of Mzabi [START_REF] Mzabi | Caractérisation et analyse des mécanismes de fracture en fatigue des élastomères chargés[END_REF] who showed the perfect overlapping with those evaluated using PS large [START_REF] Mzabi | A critical local energy release rate criterion for fatigue fracture of elastomers[END_REF]. This result confirms the independency of G on the sample dimensions in SBR and allows a robust comparison with the data obtained in TPUs that are exclusively for small PS. In case of TPU, the values of dc/dn in the whole range of tested G are always higher for the protocol B than protocol A. This is probably a consequence of the systematic buckling of the specimen during unloading cycles, which in protocol B is likely to damage the sample along the main fold in the centre, leading to lower fatigue resistance. It is also interesting to discuss the "threshold" value G t required to propagate the crack in TPU and SBR. According to Lake and Lindley [START_REF] Lake | Mechanical Fatigue Limit for Rubber[END_REF], [START_REF] Lake | Cut growth and fatigue of rubbers[END_REF], in vulcanized rubbers G t can be estimated using the extrapolation of the linear part of the curve dc/dn vs. G. In absence of this linear regime in TPU, we decided to provide a higher bound for Gt based on the resolution of the optical system for both protocols A and B. In both cases we run at least 36.000 cycles and the resolution of the optical system was 38 m. Under this condition the minimum detectable crack growth was 1 nm. Using this definition, dc/dn < 1 nm/cy at Gt < 2600 J/m 2 for protocol A and Gt < 1000 J/m 2 for protocol B. Both these values are surprisingly high compared to classical thermoset rubbers, which generally show typical values of G t between 40 and 70 J/m 2 [START_REF] Lake | Mechanical Fatigue Limit for Rubber[END_REF], [START_REF] Lake | Fatigue of Rubber at Low Strains[END_REF], [START_REF] Bhowmick | Threshold Fracture of Elastomers[END_REF].

A remark must be done concerning the effect of preconditioning step on crack propagation. Contrary to TPU, SBR samples were cyclically strained at deformation larger than those used in cyclic fatigue at the beginning of each test. This step is likely to induce some damage in the material and to negatively affect the final value of propagation resistance. Nevertheless, the difference in terms of both G t and dc/dn vs. G between TPU (especially in protocol A) and SBR is so marked that the effect of any possible damage induced by the preconditioning in SBR can be considered negligible confirming the conclusion that TPU are highly fatigue resistant material.

The results of this paper highlight two important elements in the cyclic crack propagation behavior of TPU compared to crosslinked rubbers: a) TPUs have higher Gt than those of common elastomers, b) the linear regime in dc/dn vs. G typically found in crosslinked rubbers, is replaced by a fast transition between not propagating crack and fast propagating crack (or power law regime). We also showed that the fatigue resistance of TPU is affected by the specific testing procedure, and in case of buckling of the sample during cycles (caused in principle by the residual deformation) dc/dn is significantly increased by mechanical damage on the folding line.

The methodology presented to evaluate G is compatible with large deformations of soft materials as far as the dissipative process zone at the crack tip remains smaller than the sample's dimensions. As discussed in [START_REF] Creton | Fracture and adhesion of soft materials: A review[END_REF], the size of the process zone can be estimated from the radius of blunting of the loaded crack tip, which should remain small in front of the height of the PS sample. This condition is fulfilled in the whole regime of fatigue propagation in SBR, and also in the neighbourhood of the threshold of fatigue propagation in TPU. On the other hand, in the most sever conditions and for the highest value of G applied to TPU in present analysis (Fig. 9), the blunting radius becomes comparable with the sample height. For this very large strain regime, the independence of the crack propagation curves dc/dn vs G from sample dimension should thus be carefully checked in the future using larger samples. This was not possible in the present analysis, since it is very difficult to obtain a large, thin and homogeneous PS sample by injection, due the very high viscosity of melted TPU.

Conclusion

We have proposed an approach to evaluate cyclic fatigue resistance in TPUs using the framework of fracture mechanics as developed for cross-linked elastomers. We showed that compared to methods used for classical filled elastomers, a different protocol is required to account for time-dependent properties and permanent strain of TPUs. This must include a control in force of the minimum of each cycle to avoid the phenomenon of buckling which can in turn damage the material inducing higher dc/dn. Moreover, we demonstrated that TPUs possess typical values of fracture toughness and a cyclic fatigue threshold (where dc/dn < 1 nm/cy) almost one order of magnitude larger than those of filled SBR rubbers with similar values of small strain modulus. This implies that TPUs may either resist for more cycles than classical rubbers when similar energy release rates are applied, or may sustain larger strains with only moderate crack growth when rubbers would fail in a single cycle. This result confirms that TPUs possess the combination of high fatigue threshold and low stiffness that is strongly desirable for practical applications and still missing in conventional elastomers as proved by the numerous attempts to develop high fatigue resistance elastomers implementing different complex techniques [START_REF] Li | Fatigue-Resistant elastomers[END_REF]- [START_REF] Wang | Stretchable materials of high toughness and low hysteresis[END_REF].

Figures Captions

Fig. Fig. 8 Example of calculated G vs λ for TPU without pre-conditioning. G is calculated using the stressstretch curve of the 10.000 th cycles for each value of the increasing applied stretch. The data for method A and B overlap. ([24]). Note that N347 is a type of carbon black, Sulfur is a crosslinking agent, Struktol™ and N-Cyclohexyl-2-benzothiazole sulfenamide (CBS) are accelerators to vulcanize the rubber, and N-(1,3-dimethylbutyl)-N'-phenyl-p-phenylenediamine (6PPD) is an anti-oxidant. 3 Linear modulus, stretch and stress at break and toughness of TPU and SBR (data from [START_REF] Mzabi | A critical local energy release rate criterion for fatigue fracture of elastomers[END_REF]) All figures are to print in their original colour

1

 1 Fig. 1 Example of network organization for TPUs (the hard domains act as physical crosslinks) (a) and filled and chemically crosslinked rubbers (b).

Fig. 2 Fig. 3

 23 Fig. 2 Storage modulus (a) and Tan  (b) vs. dynamic strain amplitude for TPU and SBR at 23°C and 10Hz. Fig. 3 Uniaxial nominal tensile test at 23°C for TPU (red) and SBR (black) up to failure (a) and in cyclic experiments (b).

Fig. 4

 4 Fig. 4 Ratio between the dissipated and the provided energy in the first (a) and the 10 th (b) cycle of the uniaxial cyclic experiments.

Fig. 5

 5 Fig. 5 Schematic of minimum stretch λ min and minimum stress σ min as function of the number of cycles during a fatigue experiment for Case A (a) and B (b).

Fig. 6

 6 Fig. 6 Stress-stretch curve of TPU strained at λ =2.3 (a) and corresponding G as function of the number of cycles (b).

Fig. 7

 7 Fig. 7 Stress-stretch curve for the stabilized cycle obtained using method A (a) and B (b). The shaded area represents the stored elastic energy density used in the calculation of G.

Fig. 9

 9 Fig. 9 Example of crack profile and parabolic fitting during cycles (a) and calculated radius for TPU and SBR in a cyclic fatigue experiment.

Fig. 10

 10 Fig. 10 Crack length vs cycles for TPU tested with protocol A (a) and protocol B (b) for different values of the applied G(λ). Crack propagation per cycle (dc/dn) vs G for TPU (protocol A and B) and SBR (c).

Fig. 1

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Table 1

 1 Barrel temperature profile for the injection procedure. Zones 1 to 4 are located between the rear and the front of the barrel.

	Tables

Table 2

 2 SBR composition in PHR. Filler content and crosslinking density are reported in volumetric fraction (data from

Acknowledgements

We gratefully acknowledge helpful discussions with Gabriel Sanoja. The PhD work of G. Scetta was jointly funded by the French ANRT and the LRCCP. We are indebted to Dr. Matthias Gerst, Dr. Elke Marten and Mr. Stephan Dohmen from BASF AG for kindly providing the TPU samples. We are grateful to Stephane Delaunay for injecting the samples.

.