Monsieur Dominique Vuillaume

Tout d'abord je souhaiterais remercier

Je veux aussi remercier tout le groupe de test électrique en particulier la team des grands sages, Jacques le big boss, Patrick le Mac Gyver du BCA et Denis mon ami du 20h30 passé pour m'avoir laissé squatter de manière souvent très intensive les SIAMs. Je m'excuse par avance de l'usure anticipée du SIAM6. Je veux aussi salué la ténacité de tous mes compagnons de galères qui ont subit les mêmes lots que moi de joie mais aussi de déception devant l'écran implacable d'un 4156. Bravo à tous ces chercheurs passionnés et merci pour la jovialité partagée lors de nos discussions malgré l'adversité, l'heure avancée et les lots scrapés. Merci aussi pour les petits arrangements de créneaux que j'ai pu avoir avec beaucoup d'entre vous ! Enfin je voudrais remercier tous ceux qui ont fait ma vie quotidienne au jour le jour pendant plus de trois ans et demi. En premier, mes collègues qui font du LTMA ce cocon ou il fait bon vivre et partager : merci a Marc et Jean-François pour le café et leur idées farfelues dès 9h, Carine pour ta curiosité malicieuse et ta source de potins intarissable, Alain et Véro pour votre gentillesse et bonne humeur contagieuse, Julien pour tes bon conseils et ton goût du débat et de la discussion, Eric pour ta bonne humeur et tes talents de VRP, Gab pour ta disposition à te sacrifier en premier pour dire ou faire les conneries qui nous font tous marrer. Tous à chacun vous êtes le coeur de ce beau labo. Et puis il y a bien sûr tous les intermittents de la science qui apportent chaque fois une nouvelle facette de personnalités, d'expériences et d'anecdotes. Big up à tous mes grands frères et soeurs thésards pour leurs expériences partagées et leur bonne humeur : Joshna, Fred, Vincent, Emilie, Tizianna, Alex, Michael, Jean-Paul, Marc, Perrine, Louis, Guillaume. Une pensée particulière pour mes collègues de promo Milène et Paul-Henry aux sujets aussi «prometteurs pour le futur» et «amonts» que moi. Un merci très spéciale à Milène ma «jumelle de thèse» qui a sauvé ma thèse plus d'une fois avec ses coups de pouce PTA, les pointes AFM détruites, les lithos, les dépannes administratives et j'en passe… Merci surtout pour avoir partagé toutes ces pauses café et escapades à H1, de chouettes moments anti-déprimes obligatoires pour survivre aux thèses amonts. Et puis, je voudrais saluer tous nos suivants que j'ai pus croiser Paolo, Quentin, Gabriele, Cuiqin, Veeresh, Thomas et «Just because of the scholar system», une dédicace spéciale pour mon co-bureau Giorgio, sa TDM, nos divagations sur les oxygen vaccancies et la magnifique sculpture de rédaction.

Pendant cette thèse j'ai aussi eu la chance d'avoir été accueilli pendant 5 mois à l'autre bout du monde en Corée par des personnes d'une gentillesse et d'une attention exceptionnelles. Ils m'ont fait partager leur quotidien, leur mode de vie, mais aussi leur culture ainsi que des moments importants de leur vie. I would like to thank Professor J-G Park and Professor Shim for welcoming me in their Lab. I have been particularly glad and proud to join their researchers in Hanyang University. I would like also to warmly thank all the students who welcome me not only as colleague but also as special guest. You have been great ambassadors of your country making me discover some of your life and culture. Therefore I spent really nice time in Korea and will keep in memories my extra life shared with you. Of course I would like to thank in first my team : the PBD family with Hyun-Min, Jong-Dae, Kyoung-Cheol, Jae-Sung, Jung-Nam but also all the people I get the chance to interact Dal-Ho, In-jee, Mi-Hee, Seung-Wook,Jong-Sun, Tae-Hyun, Jong-Young, Hee-Sub, Jae-Hyung, Ji-Heon, Jae-Hyoung, Seung-Hyun, Seong-Gwang, Yeon-Hui, Du-yeong, Hyun-Ki, Dong-Hyun, Min-Ha, Myung-Jin, Jae-Woo, Hyoung-Rae. During that adventure, most of you turn in real friends and I sincerely look forward meeting you soon somewhere, someday… 감사합니다! 너, 보고싶을꺼야, 나중에 보자 Je voudrais aussi remercier tous les étudiants étrangers de la résidence universitaire que j'ai eus le plaisir de côtoyer dans mon extra-life coréenne. Merci pour m'avoir fait revivre ce formidable esprit Erasmus. Une dédicace spéciale à Max, Alexandro, Renato et mon colloc Bhuvan pour ces séances de décompression mémorables.

Enfin je dois remercier ceux qui ont toujours été là pour m'encourager et me soutenir à aller de l'avant mais aussi surtout pour m'avoir sorti la tête de la thèse et me rappeler l'essentiel : je pense à ma famille et mes amis proches. Merci à tous mes amis grenoblois pour m'avoir permis « d'estampiller fête » à gogo ces trois années. Merci au crew de l'ENSERG et associés : Mich, Laure, Jo, Edith, Alex, Isa, Amélie, Sylvain, Fab, Annick, Sven et Céline, Loubarth, Bertrand et Franscesca. Une mention spéciale pour le CBC qui m'a suppléé pendant mon escapade coréenne et pour toutes ces soirées gastronomiques et intellectuellement riches. Merci à Repi et Nanou pour cette combinaison unique Cèpes-Chazy, Scotch on the Rock, Litter-Kwitter. Merci un million de fois à Audrey et Nieu pour vos petits plats et traquenards dont je raffole. Vous avez de loin été notre deuxième maison.

Bien sûr, je voudrais remercier l'ensemble de ma famille et en particulier mes parents qui m'ont appris à aimer apprendre et découvrir toujours plus, oubliant les préjugés. Merci également à mes soeurs et mon petit frère qui ont fait de moi l'avant-garde de la fratrie et m'oblige à me tenir un peu à carreaux. Je veux aussi remercier la succursale vendéenne de Voreppe : 800km en15 min. un extra booster sur lequel j'ai pu me reposer plus d'une fois avant de repartir gonflé à bloc. Merci à tous pour votre support, les moments partagés, et votre implication jusqu'au pot de thèse qui a super assuré : en bon chauvinisme, vous êtes justes les meilleurs.

Finalement, je voudrais remercier celle à qui je dois le plus, qui a été à mes côtés depuis le début et avec qui j'ai partagé cette aventure et déjà plusieurs autres. A l'instar du pot de thèse (sans contestation le chapitre le plus réussi de ce doctorat), elle a été une clé maitresse du bon déroulement de cette thèse. Elle a su m'attendre et me supporter dans mes rêveries et aventures, a eu la tâche délicate de me déconnecter quand j'en faisais trop ou de me remotiver dans les moments plus difficiles en m'apportant son énergie, ses conseils et son aide. Merci Ha Lan.

Acronyms

General Introduction Context

During the last 10 years, non-volatile storage technologies, currently driven by Flash memories, have played a major role in the development of mobile and consumer-oriented electronic devices such as: MP3, cell-phones, smart-phones, e-books, cameras, USB sticks, solid state storage disks… In a race for enhanced performance and lower cost, solutions based on Flash memories downscaling will have to face very challenging issues in the coming years. Currently, several technologies are investigated as complementary solutions or for the replacement of conventional solutions beyond the 10nm node.

In this context, the recent developments in the field of organic electronics and the growing interest upon resistive memory technologies (RRAM) have lead to a high attention upon Polymer -Resistive Memory devices (PoRRAM) potentially offering promising electrical performance as well as low fabrication costs. Until now, many types of organic compositions have been suggested in macroscopic structures, however, detailed device operation and optimization, as well as the exact role of organic compositions regarding their impact upon integration and the involved physical mechanisms, are still unclear as for their requirements for technology viability.

PhD Thesis presentation

The work of this PhD was dedicated to the development and study of organic polymer resistive memories for Crossbar architectures. The main axes of research were: the development of materials and structures for the fabrication of organic memories suitable for the cross-bar architecture, the detailed electrical characterization of memory operation and performances, the suggestion of solutions for downscaling and integration upon CMOS and finally the advanced characterization for physical understanding of the device. The major aspects of this work are presented in this manuscript following five chapters.

The first chapter presents a global overview on Memory Technologies, introduces the interest of organic materials for electronic storage and discusses the state of the art for organic based resistive memories. The first section presents a brief history of the technologies associated with information storage and introduces the requirements and key success factors necessary for the development of memory technologies. In the context of current memory market the opportunities for alternative solutions are discussed, emphasizing the potential of so-called resistive memories. In a second part, we present the interest brought by single molecules and organic thin film approaches for memory device development. The third section is dedicated to the current state of the art in the field of Organic Thin Film Resistive Memories. Finally, our approach, suggested for polymer resistive memory development is exposed.

In chapter 2, the development of nanocomposite thin films made of Poly-Methyl-MethAcrylate (PMMA) insulating polymer resist with molecular doping of fullerenes (C60), and semi-conductive molecules is presented for memory device elaboration. The nano-composite approach and fabrication details are first introduced. The physical and chemical characterizations of fabricated layers are then discussed in a second part. The impact of annealing above the glass transition, upon the organization in the layer, has been also analyzed and preliminary results are briefly presented here. The last part deals with the description of memory devices and test structures fabricated for electrical characterization. Finally, a novel integration scheme is suggested for the integration in high-density crossbars.

Chapter 3 is dedicated to the electrical characterization of (PMMA:C60) nano-composite layers in Metal-Insulator-Semiconductor (MIS) capacitive structures. The interest, physical principle and characterization methods for MIS devices are first briefly recalled. Then, in a dedicated Metal-Organic-Insulator-Semiconductor (MOIS) structure, preliminary analysis of the reference device consisting only of the insulating polymer, are presented and then the nanocomposite layers considered for resistive devices were analyzed in terms of charge trapping.

Chapter 4 presents the electrical characterization of (PMMA:C60) layers in resistive cells with inert electrodes resulting in Metal-Organic-Metal (M-O-M) structures. The screening of the resistive memory effect is briefly introduced and the typical electrical behavior observed for devices with different material configurations (doping concentration, annealing temperature) are presented. On thermally annealed nanocomposite layers, unipolar memory behavior and Negative Differential Resistance effects have been demonstrated and a complete preliminary study on memory performances is provided. In order to assess the technological potential of these memories, studies on pulsed programming and size reduction of the memory cell are also presented. Finally an original in-depth analysis of the multilevel memory operation has been carried out and provides elements for a clear comprehension of device operation.

In order to clarify the potential role brought by oxidizable electrodes in the switching ability of organic devices, chapter 5 reports the results of electrical characterization on (PMMA:C60) nano-composite layers in the presence of oxidizable electrodes. The bipolar memory effects attributed to the presence of a bottom interfacial oxide are presented, and detailed characterization on the operation and dynamic of the devices is provided. To further determine the role of the organic layer composition in this particular behavior, and identify the possible mechanisms involved, the impact of device geometry factors such as electrode area and organic layer thickness upon the hysteresis characteristics have also been studied and presented in the third section. Finally, in the last section, we summarize the full set of experimental results collected for device understanding and discuss some of these points regarding possible operation mechanisms.

This manuscript finally ends with a general conclusion summarizing the main results provided in this study, before presenting the future prospects of this work.

Chapter I

I Non-Volatile Storage technologies and Organic electronic Memories

In this first Chapter we present a global overview on Memory Technologies, introduce the interest of organic material for electronic storage and discuss the state of the art for organic based resistive memories.

First, a brief history of information storage technologies is presented where technical and applicative key requirements for technological success are highlighted. Then, the current memory market and technological landscape is introduced. In a business model based on scaling, the challenges and potential limits encountered by Non-volatile Flash memories are then briefly described and the possible evolutions for future electronics are presented. In such context, the potential and opportunities for emerging technologies, in particular resistive based memories, is discussed.

In a second part, we present the interest brought by organic material for future electronics design. Single molecules and organic thin film approaches are presented and the challenges regarding their integration with respect to conventional technologies are discussed. In both strategies, promising demonstrations for memory device development are presented and listed, including different physical and technological principles.

The third section is dedicated to the current state of the art in the field of Organic Thin Film Resistive Memory. An overview on the investigated materials and on their electrical characteristics is presented. The development status and challenges on the main aspects such as performance, integration issues and physical comprehension are addressed. Finally, our approach suggested for polymer resistive memory development is discussed. Information storage has played a major role in human history for the transmission and spreading of knowledge as well as for the development of modern technologies. Two main elements should be considered for storing and recovering information: the STORAGE MEDIA that is the element where information is physically materialized and the INTERPRETER unit where the information is computed. Both of these elements have evolved in time, and lead to a multiplicity of storage technologies.

I NON-VOLATILE STORAGE TECHNOLOGIES AND

I.1.1.a From Early Stages to the Emergence of Machines

Information materialization was developed initially for RECOVERING or TRANSMISSION purposes. During a long period of time, before the emergence of machines, the only information interpreter was human perception. Focus was naturally given to its dominant sense: Vision1 . Information coding was performed with techniques employing differentiation through colors, shapes or positions: Cave-Painting (4000BC), Tally Stick (5000BC) and Clay Scribing by the Sumerians (3400BC). Then, developments were performed by an optimization of the memory media and its processing conditions. Papyrus and inks were introduced in 2000BC by Egyptians for lower weight and increased data density. It was then replaced in occident by Parchment or Vellum to improve durability. On the other hand, Asians who started writing on Bamboo and Silk have developed the fabrication of Paper around 100BC in order to provide a low weight and low cost medium. But high volume storage and large distribution was still strongly limited by the writing time. As a solution, woodblock printing and then moveable type printing were introduced by Chinese and further optimized by Koreans in 1230 with the first demonstration of metal type moveable printing. In 1440, J. Gutenberg introduced press printing in Europe enabling flexible and high volume production and thus revolutionizing knowledge diffusion. On the other hand, the development of CALCULATION and AUTOMATION, first introduced in mechanical systems, also required long or short-term memorization for cumulative and iterative process or for the storage of task sequences. The first mechanical calculators, presented by W. Shickard in 1623 and B.Pascal in 1645, employed moving parts and gear wheels. Later, in 1725, B. Bouchon developed a perforated paper-loop in order to automate pattern reproduction on cloth. The employed technique was further optimized in Jacquard's loom (1801) and employed in the Census machine, patented by H Hollerith, used in 1890 U.S. census. Punched card or punched tape based systems remain employed until 1980 for automatic computation. With the development of science and technology, memorization also extended to different fields of application and new memory media: the Phonograph patented by Edison in 1877, enabled voice recording through indentation and the Telegraphone presented at the 1900 Universal exposition by V. Poulsen could record voice upon a magnetic media, are the first demonstrations of these modern technologies.

I.1.1.b Emerging of Technologies for Electronics

At the beginning of 20 th century, the control and production of electricity enabled the rapid development of electrical devices. The first fully electrical calculator was presented in 1937 by J.V Atanasoff and C.E. Berry and marked the beginning of the electronics era. The main key developments in the field were the invention of the vacuum tube in 1946, the bipolar transistor in 1947 by J. Bardeen, W. Brattain and W. Shockley, and the Field Effect Transistor in 1959. The development of integrated circuits (IC) and the standardization of Metal-Oxide-Semiconductor (MOS) technologies around the 70' enabled Small Scale Integration (SSI) to Very Large Scale Integration (VLSI). In parallel, to the development of logic, appeared a growing need for memory in applications such as calculators and computers. From a technical point of view, two main considerations were taken into account for computing: first, for efficient calculation, logic required rapidly accessible memory, and on the other hand the ability to store and keep information in a quasi permanent way (long periods, powered off). This lead to two different fields: volatile and non volatile memory technologies. Some of the key devices in electrically computed memory evolution are presented on the time line displayed below on figure I.2. Table I.1: Requirements for information storage technologies and corresponding memory characteristics.

I.1.2 Current Memory Market, Technologies and Challenges

Since the 70's and its opening to public consumers, the electronics industry has known continual growth with different successive technological waves (See figure I.3): Analog, Digital, Internet, Wireless... In this context the memory technologies have supported, enabled and driven the expansion of new markets. Today the memory industry plays a major role in the technology development and represents 25-30% of IC Market (210 billion USD in 2010 [START_REF] De | Silicon Non Volatile Memories: Paths of Innovation[END_REF] ).

I.1.2.a Semiconductor Memory Technologies

The rapid development in semiconductor logic based on Transistors and supported by CMOS scaling business model, has favored the development of semiconductor-based memories during the last 40 years.

Regarding technical requirements, as introduced in Table I.1, an ideal memory device should also provide non-volatility in order to retain information (even powered off) and enables programming and reading operations with very low time and energy consumption. Unfortunately this so-called "UNIVERSAL MEMORY" has not been developed yet. In order to provide efficient solutions, several technologies were designed following the targeted application. The overview of available technologies classification is presented on figure I.4a. Nowadays, the absence of devices allowing fast writing with long term retention, splits the semiconductor memory classification in two main categories: volatile and non volatile. The volatile, also named Random Access Memories (RAMs), allow a fast programming and low access time, particularly interesting for computation and program execution. However, when the power is shut down, such devices lose their information instantaneously in the case of Static RAM (SRAM) or on a low time scale after programming for so-called Dynamic RAM (DRAM). For this purpose, Non-Volatile Read Only Memory (ROM) is also used to store information in a sustainable manner. Depending upon the application, this memory could be nonreprogrammable (Mask ROM) or reprogrammable with light (EPROM) or electrically (EEPROM). The FLASH technology has been particularly attractive because of its balanced performance in terms of density, programming ability and non-volatility (see figure I.4b).

In a computer, these different technologies are associated in order to provide complete and efficient architectures: SRAM and DRAM are coupled with nonvolatile FLASH and external high density mass storage disks (HDD). With the recent development, mobile and consumer oriented electronics require even more non-volatile capacity (see figure I.5). Consequently, FLASH memories have gained a great interest because of their ability to be easily integrated on ICs and fabricated with high density at low price (see scaling GB cost scaling on figure I.6).

I.1.2.b Evolutions & Requirements for future generations

During the past 50 years, the microelectronics industry has rooted its development upon continuous optimization towards increasing density and performance. Indeed at the early stage of IC development, D. Engelbard2 already promoted the potential of miniaturization scaling. Downscaling could enable a continuous increase in complexity along the years and thus improve circuits' performances. This concept was further popularized in 1965 and revised in 1975 by the empiric Moore's law stating that the "Number of Transistors in a microprocessor could double every two years". Industrial consortiums further regulate the technological evolution in that sense. As CMOS compatible and thanks to the constant engineering efforts and innovations, Flash and DRAM devices have successfully followed this scaling development rhythm and thus enabled always higher storage density and a decrease of fabrication cost (see figure I.6). -10-Nowadays, the semiconductor development splits in two major directions: More Moore and More Than Moore [START_REF]International Technology Roadmap for Semiconductors[END_REF] . The More Moore approach is the extension of conventional semiconductor technologies. It focuses on a continuous race for performance, involving different aspects: increase in data density (2D scaling, Multilevel Capabilities, 3D integration), reduction of power consumption and improvement of speed. On the other hand, the More than Moore approach suggests economic development through the design of application driven technologies. In that context dedicated memory technologies can find their place by enabling new operation environments (e.g. automotive [START_REF] Hiller | Infineon Technologies AG: There Is More Than Moore in Automotive[END_REF]) or new integration schemes (e.g. cointegration with logic/ display/sensor…).

I.1.2.c Limitations of Flash NVM technologies

In order to prepare future technology generations and coordinate research investment, an industrial consortium establishes every two years the state of the art and the forecast in a document entitled "International Technology Roadmap for Semiconductor" (ITRS). In this document we can point out that, despite some of the solutions that are already developed or could be engineered for next generation nodes, the scaling of Flash memories has to face very challenging issues in the coming years. Among them we found:

Technical limitations in scalability of Gate Dielectrics, limitations due to Capacitive coupling between cells or due to space available for word-lines, Questions about Lithography availability for future technological nodes, Fundamental Physical limitations such as few electron phenomena leading to high impact dispersion on characteristics, Cost limitations if by increasing the complexity to sustain scalability the benefits of scaling become disputable.

Moreover, the fundamentals of FLASH technology based upon charge-based physics and implemented with transistors, could be weaknesses regarding new requirements stated in ( §I.1.2b) such as write time improvement, voltage lowering, integration in a new environment (e.g. radiative or high temperature), innovative integration for 3D stacking or co-integration purposes. Purposely, paradigm changes are now considered for emerging memories [START_REF] Nishi | Nanoelectronic devices and integrations on silicon platform today and tomorrow[END_REF][START_REF] Jeong | Resistive memories[END_REF] .

I.1.3 Development of New Technologies & Opportunities for Resistive Memory

I.1.3.a Candidates for Emerging Memory technologies

Currently, several technologies are investigated for the replacement of conventional solutions after the 10 nm nodes or for alternative technologies [ITRS10, Jeong11]. Among the classification of solutions monitored by ITRS, two main categories can be distinguished following the principle used for information coding: Capacitive or Resistive. Whereas some changes in electrostatic configuration3 are exploited for Capacitance based devices, the Resistive technologies are based on change in conduction behavior.

In resistive devices, different materials and physics-based principles are considered: magnetic polarization (MRAM), Phase change in materials (PCRAM), mechanical nano-systems (NEMS), mechanical indentation (Nano-Probe Storage) or results from filamentary, bulk or interface conduction switching in inorganic materials (RRAM) or organic materials (PoRAM) (see figure I.7). In order to be competitive with existing technologies, an emerging technology will require improved performance at equivalent or lower cost [START_REF] Lai | Non-volatile memory technologies: The quest for ever lower cost[END_REF] . Other opportunities could be upon non-competitive or niche markets if this technology could allow new uses or new environments with sustainable development opportunities. In both of these contexts, resistive technologies seem to have several promising characteristics that could challenge FLASH technology in the future.

Charge-based Programming & Reading

I.1.3.b Opportunities for resistive memories regarding integration

From the fabrication point of view, the elementary cell in resistive technologies could be a two terminal device thus allowing simplified integration. Despite the current lack of maturity, simple integration schemes could result in potential lower fabrication cost than conventional technology and facilitate its market introduction. Moreover, the simplicity of its integration could also be a key advantage by enabling very high integration density such as crossbar architectures as displayed on figure I.8a [START_REF] Lai | Non-volatile memory technologies: The quest for ever lower cost[END_REF] . Finally non transistor based solutions and use of alternative materials than silicon could potentially enable the integration of the memory cell in Back-End Of Line of CMOS process (BEOL) thus providing stacking -ability for 3D architectures and reduced cost (see figure I.8b integration of stacked polymer memory layers [START_REF] Pinnow | Material Aspects in Emerging Nonvolatile Memories[END_REF] ).

I.1.3.c Performance of resistive memories

Despite that resistive memories are still at a development stage, few demonstrations have already presented promising characteristics in terms of memory performance. The main improvements compared to conventional Flash NVM technologies are upon switching time and operation voltage (See Appendix I.A for ITRS performances benchmark and figure I.9 for the main emerging memory prototyped). Prior to any potential replacement, such technologies could first reach a great interest by completing NAND flash technology in the classical storage hierarchy because of its balanced performance regarding non-volatility and access time. The non-volatility coupled with fast access and programming time observed in resistive RAM is particularly interesting for Storage Class Memory devices (SCM). SCM is an IBM term for solid-state non-volatile memory technologies that are capable of replacing Hard Disk Drives and complementing DRAM [START_REF] Lam | Storage Class Memory: Opportunities and Challenges[END_REF] .

As illustrated on figure I.10, by offering non-volatility and fast access time, such technologies could potentially revolutionize the classical memory hierarchy in current computing and provide new functionalities such as instantaneous wake-up.

I.1.4 Conclusions

Through this presentation on information storage technologies, we have seen that technological emergence is related to memory performance but is also strongly determined by application and environmental constraints. For such purposes, electrical based devices were particularly developed and despite the missing of "universal memory devices", the low-cost, increasing volume and high performance have maintained FLASH and DRAM technologies as market drivers for the past 30 years.

However, with drastic reduction in size towards few dozens of nanometers such conventional solutions have to face very challenging issues to sustain a business model based on planar scaling. Moreover, the new requirements considered for future electronic market could offer serious opportunities for emerging solutions such as resistive technologies.

To be introduced in the market, a new technology needs to be competitive in terms of performance, cost (no extra cost compared to conventional solutions) and ability to address new applications. Despite the promises of resistive memories, non-volatile memory technology replacement is difficult as the maturity of existing solutions is very high.

I.2 State of the Art of Organic based Memory Devices

I.2.1 Interest of organic materials for future electronics

Among the different materials investigated as alternative solutions to conventional memory technologies, figure organic materials based devices [ITRS10]. In organic based devices, the active material is made of molecules or polymers as basic building blocks. Working at the molecular level could potentially bring several strong advantages to the technology. These opportunities were already spotted since the development of microelectronics and were expressed in 1971 as being the following [START_REF] Kuhn | Systems of monomolecular layers -assembling and physico-chemical -198-behaviour[END_REF] :

1. Scalability with molecular size: a molecule is the ultimate way of controlling the position of an atom within a more complex structure, 2. Auto-assembly: intermolecular interactions can be used in order to form self-assembled structures of modified, electronic behaviour, 3. Dynamic stereochemistry: many molecules have multiple stable geometric/electronic structures resulting from the addition or removal of an electron (redox molecules) or chemical reactions (DNA), 4. Synthetic tailorability depending upon the choice of molecules.

In the area of memory technologies, where the increase of density and limitation of variability constitute difficult challenges to address future generations, the inherent scalability towards molecular size and the potential of electrical properties dictated by single molecules properties have found a direct interest. In addition, the advantages brought in terms of infinite tunability by chemical engineering and potential for alternative low-cost processing could ensure sustainable and economically viable technologies. For these purposes organic based technologies have been targeted by ITRS consortium in the emerging technologies field [ITRS10] . This classification is made up of two categories of organic materials: Polymer and Molecular Memories. The distinction originates from two different visions of molecular based electronics detailed in [START_REF] Tour | Recent Advances in Molecular Scale Electronics[END_REF] : namely "molecular scale electronics" which focus upon the use of single molecules, and "molecular materials for electronics" where devices exploit the global properties of organic thin films (polymer/small molecules thin films).

I.2.2 Molecular memory devices

Molecular-based memory devices have mainly found interest for highly scalable devices and future memory generations. In this context, some demonstrations have been developed with capacitive approach in order to explore the possibility of extending scalability within existing markets (Flash, DRAM). On the other hand, in order to reach the highest available density, the molecular resistive approach has also been specifically investigated because of its ability to be integrated in the very high-density crossbar architecture.

I.2.2.a The Capacitive Memory Approach

Change in intrinsic charge of single redox molecules has been employed for charge storage capacitor based memory technologies. Few hybrid systems employing molecules with classical -15-CMOS process have been demonstrated. Among them, the ZettaRAM TM presented in [START_REF] Kuhr | Molecular Memories Based on a CMOS Platform[END_REF] and [Venkatesan05] is a molecular DRAM that benefits from the advantages of molecules in terms of density and low operation voltages. In this structure, the classical capacitor is replaced by a molecular capacitor based on Porphyrin molecules. The basic cell and memory architecture are presented in figure I.11. In order to target highly integrated and non-volatile performances, few works also investigated molecular flash like memories [LiC04a-b, [START_REF] Pro | Investigation of Hybrid Molecular/Silicon Memories With Redox-Active Molecules Acting as Storage Media[END_REF][START_REF] Pro | From Atomistic to Device Level Investigation of Hybrid Redox Molecular/Silicon Field-Effect Memory Devices[END_REF] . As pictured on figure I.12 molecular building blocks can be used to mimic the classical floating gate architecture. Indeed, as suggested by Pro et al, redox molecules acting as storage center with very high density of charges (>10 13 cm -2 ) could be associated with chemical linker (typically Alkyl chain), replacing the tunneling oxide and preventing discharge of the molecule for nonvolatile application [START_REF] Pro | From Atomistic to Device Level Investigation of Hybrid Redox Molecular/Silicon Field-Effect Memory Devices[END_REF] . Moreover, molecular grafting and self-assembly enable bottom-up approach particularly interesting for nano-scaled fabrication. A demonstration of functional flash like hybrid devices is presented on figure I.13 where porphyrins were grafted on nano-wire transistor enable hysteresis on the transistor characteristics [Li04Cb] .

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Molecular Engineering

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I.2.2.b Resistive Memory Approach and Molecular Crossbar

In Resistive molecular memory approach the information is stored using the conductance of molecules. Despite the fact that the physical mechanisms involved are not clear (conformational changes, charge transfer in molecules or filamentary conduction between electrodes), some molecules have been presented for their ability to tune conductivity between different states when addressed between two electrodes. According to Donhauser et Al, it was suggested that the conductance switching in molecules is a result of conformational changes rather than electrostatic effects of charge transfer [Donhauser01] . Different molecules were purposely suggested in that direction with for instance phenylene ethynylene switching molecules in a dodecanethiolate matrix [Donhauser01] or rotaxane/catenane molecules [START_REF] Collier | Electronically Configurable Molecular-Based Logic Gates[END_REF][START_REF] Collier | A Catenane-Based Solid State Electronically Reconfigurable Switch[END_REF] (figure I.14).

For high-density integration and addressing of molecules, the crossbar architecture was imagined as being very promising because of its compactness. This approach is suitable for memory cells with resistive switching properties [START_REF] Luyken | Concepts for hybrid CMOS-molecular non-volatile memories[END_REF][START_REF] Sezi | Organic materials for high-density non-volatile memory applications[END_REF] . In this context molecules could potentially offer a highly scalable switching material. Using rotaxane, Green et Al demonstrated a 160kbit crossbar array with densities up to 10 11 bit/cm² [START_REF] Green | A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre[END_REF] However, the limit in terms of scalability is mainly determined by the dimensions at which the crossbar electrodes are patterned. In order to achieve very high density, special integration schemes have been suggested. Most advanced Lithographical solutions include the use of nanoimprint, as described in [START_REF] Wu | One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography[END_REF] , and [START_REF] Chen | An Access-Transistor-Free (OT/lR) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device[END_REF] . Non-lithographical Stamping techniques are also employed in [START_REF] Melosh | Ultrahigh-Density Nanowire Lattices and Circuits[END_REF] enabling metal crossbar arrays with a pitch as small as 30nm (see figure I.16). Alternative Non-lithographic solutions have also been imagined such as in [START_REF] Cerofolini | Strategies for nanoelectronics[END_REF] and [START_REF] Cerofolini | A hybrid micro-nano-molecular route for nonvolatile memories[END_REF] called the "spacer patterning technique" (see figure I.17). Finally, in molecular devices, we should point out that fabrication process is limited by the molecule's sensitivity in particular regarding the thermal budget. Different strategies are suggested to integrate molecules in cross-point cells. Molecules can be laterally grafted after the fabrication of crossbar with inert spacing oxide between lines as suggested in [START_REF] Cerofolini | A hybrid micro-nano-molecular route for nonvolatile memories[END_REF] or embedded in dedicated nano-gaps as suggested by [START_REF] Ruttkowski | CMOS based arrays of nanogap devices for molecular electronics[END_REF] (see figureI.18).

I.2.2.c Challenges for molecular scaled approach

Despite some promising demonstrations were successfully given for molecular devices especially in terms of density, research has been only achieved on elementary devices and there are still nowadays strong challenges to demonstrate the technology.

Concerning integration, low thermal budget requirements as well as environment sensitivity, strongly limits their compatibility with microelectronic process. If few interesting suggestions have been published with impressive demonstrations, the impact of integration on electrical characteristics is still to investigate. Indeed, molecules' interfacing is a very challenging task and the small molecular-sized gap between electrodes could enable various unexpected phenomena (electro-migration, strong influence of interface and native oxide) [Haik07] . In order to distinguish integration impact upon molecular behavior and to understand the electrical interaction, some dedicated studies should be carried out with specific reference molecules for the different integration schemes.

I.2.3 Organic Thin Films for Memory Devices

In the approach of "molecular materials for electronics", molecules are employed in thin films and the global electrical property of the film is considered. This latter depends upon the sum of individual properties and upon the specific configuration of the molecules. The benefit remains here the material tuning ability, through chemical engineering, which allows a wide range of physical properties. On the other hand, working with bulk materials gives access to a wider range of available fabrication processes. A good illustration of the potential interest for such an approach is given by the current success of Small Molecules based Organic Light Emitting Devices (OLED): the combination of particular and tunable optoelectronic properties with multi-surface cost affordable processing of organic thin films has enabled a new revolution in Display technologies [START_REF] Geffroy | Organic light-emitting diode (OLED) technology: materials, devices and display technologies[END_REF][START_REF] Young | OLEDs -Promises, Myths, and TVs[END_REF] . For cost, performances or either application purposes, the exploitation of molecular materials has been suggested for all types of electronic devices including optoelectronic devices, transistors, sensors and memories [Katz09,[START_REF] Heremans | Polymer and Organic Nonvolatile Memory Devices[END_REF] .

I.2.3.a The Capacitive Memory Approach

Capacitive memory could be employed in technologies where the elementary cell is a capacitor (1C) or one capacitor coupled with a transistor (1T-1C) (see figure I.19). For organic non-volatile capacitors, ferroelectric polymers have been particularly suggested [START_REF] Lovinger | Ferroelectric polymers[END_REF][START_REF] Naber | Organic Nonvolatile Memory Devices Based on Ferroelectricity[END_REF] . Among them the poly-(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (PVDF-TrFE) was found to display spontaneous ferro-electricity [START_REF] Rg | Ferroelectric, pyroelectric and piezoelectric properties of poly(vinylidene fluoride)[END_REF] and has been widely employed in research studies and recently in commercial products The capacitive approach could also be coupled with field effect transistors: the channel conduction will be impacted by capacitive configuration controlled in the gate dielectric. This includes the use of conventional or nano-floating gates with nano-particles [START_REF] Baeg | Controllable Shifts in Threshold Voltage of Top-Gate Polymer Field-Effect Transistors for Applications in Organic Nano Floating Gate Memory[END_REF] , charge trapping, electrets layers [START_REF] Singh | Nonvolatile organic field-effect transistor memory element with a polymeric gate electret[END_REF] , or Ferroelectric dipole polarization [START_REF] Naber | Organic Nonvolatile Memory Devices Based on Ferroelectricity[END_REF] . Demonstration of resulting hysteresis on transistor characteristics is presented on the figure I.20 on devices considering gold nano-particles embedded in an insulating polystyrene polymer.

I.2.3.b The Resistive Memory Approach

For resistive approach, different families of materials and devices have also been reported for their conductance switching ability (see figure I.21). Among them we found the specific ferroelectric diode employing injection modulation in semiconductor controlled by ferroelectric polarization [START_REF] Asadi | Organic non-volatile memories from ferroelectric phase-separated blends[END_REF][START_REF] Asadi | Crossbar memory array of organic bistable rectifying diodes for nonvolatile data storage[END_REF] and a wide range of organic bulk materials with various polymers or small molecules reported for their resistive switching ability. This latest class of devices and materials will be specifically presented in the following section ( §I.3).

Polymer & small molecules Organic Bistable Devives

I.2.4 Perspectives for organic memory devices

As presented in paragraph ( §I.2.1) compared to conventional technologies working with molecules could offer several new advantages for electronics. However, electrical interfacing, integration and device physical understanding remain a serious challenge for these completely new materials in microelectronics field. Nevertheless, as illustrated through publication statistics pictured reported by Q.D Ling on figure I.22 and the rhythm of recent reviews [Bozanno05, Scott07, Ling08, Prime09, Ouyang10, Heremans11, ChoB11] , the research interests in this field are continuously increasing highlighting a real potential for future organic resistive technologies. Indeed, the molecular approach could be one of long-term solutions to sustain ultimate scaling in the next decades, not currently reachable in the race to scaling with conventional technologies (see figure I.23). On the other hand, at a short or medium term, organic thin film could enlarge the range of properties, fabrication processes and possible suitable environments, thus enabling new applications and markets (i.e. plastic, flexible, organic, multi-surface, large area electronics) (see figure I.24). In this context the development of organic based alternative electronics will necessarily require the emergence of compatible memory devices.

I.3 Development of Organic Thin Film Resistive Memories

As introduced in paragraph ( §I.1), resistive memories are very attractive for their integration simplicity but also for their potential promising performance.. Since integration and hybridizing of molecules remains a big challenge [START_REF] Haick | Electrical Contacts to Organic Molecular Films by Metal Evaporation: Effect of Contacting Details[END_REF] , high focus is currently given upon organic bulk materials such as polymers or small molecules potentially offering higher fabrication flexibility. This class of memory devices is often described under acronyms such as OBD (Organic Bistable Devices), ONBM (Organic Non volatile Bi-stable Memory) or PoRRAM (Polymer Resistive RAM) memory devices. We present in this section a brief overview on the basics and current research in this Field.

I.3.1 Materials and Device Integration

I.3.1.a Organic composition

During the last 40 years, a large panel of organic materials has been investigated for their resistive switching ability [START_REF] Ling | Polymer electronic memories: Materials, devices and mechanisms[END_REF] . Depending upon the targeted mechanisms (presented later in paragraph §I.3.3), different systems have been suggested. They include various elementary components such as polymers, small molecules, mobile ions, donor-acceptor complexes or the incorporation of nano-particles. As illustrated on figure I.25, these building blocks can be organized in different configurations to form electrically active layers: Stacked: This is for example the case in so-called three-layer devices consisting of metal or metallic nano-clusters sandwiched between two layers of small molecules [START_REF] Bozano | Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles[END_REF][START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] .

Blended:

In these configurations nano-particles, small molecules, ions or polymers are dispersed in a global material through co-evaporation or solution processing [START_REF] Ouyang | Programmable polymer thin film and nonvolatile memory device[END_REF][START_REF] Heng-Tien Lin | Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device[END_REF][START_REF] Cho | Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer[END_REF].

Chemically Linked: The organization can also be done at the molecular scale in engineered macromolecules with different embedded or grafted functional groups [ling07] .

Metal Nanocluster

L.D. Bozano et Al Adv Func

I.3.1.b Electrodes

The nature of the electrodes is an important parameter that can affect devices according to the following aspects: electrically, chemically and morphologically Electrically, two major parameters are usually considered concerning metallic electrodes: mobility and work function. This latest parameter has a strong influence in semiconductor device design and often dictates the electrical properties of devices [START_REF] Sze | Physics of Semiconductor Devices -Chapter 4 Metal-Insulator-Semiconductor Capacitors[END_REF] (rectifying ratio for schottky junction, threshold voltage for transistors with metallic gate, injection efficiency for optoelectronic devices...)

Chemically:

The chemical stability of electrodes is also essential. Their ability to get oxidized could have a major influence through the introduction of an interfacial oxide that can disturb or induce a particular electrical behavior. The ability towards diffusion and ionization in bimetallic configuration enabling electroforming has also to be considered [START_REF] Heremans | Polymer and Organic Nonvolatile Memory Devices[END_REF] .

Morphologically: As suggested in [START_REF] Vilkman | Negative differential resistance in polymeric memory devices containing disordered block copolymers with semiconducting block[END_REF][START_REF] Kwan | Understanding the switching mechanism of polymer memory[END_REF], in the hypothesis of filamentary based switching, the influence of the electrode shape introduced by roughness or grain boundaries could also play a fundamental role upon the localization of the electric field (see figure I.26 where irregularities on electrodes have been suggested in the filament initiation). Unfortunately in literature, strong focus is given to the organic composition whereas the influence of electrodes is poorly addressed. Most of the electrodes employed are made of oxidizable materials (mostly Al or Ti, ITO...) thus making device understanding more complex.

I.3.1.c Memory cell Scaling

Whereas it is common in microelectronic processes to pattern a metal masked by a polymer resist and further remove the organic mask, patterning a metal deposited on organic layers is not trivial with conventional process. For this purpose most devices presented in bibliography employ the shadow evaporation technique enabling a direct and non-damaging patterning of electrodes. However, such a technique is limited in resolution and most reported devices mostly range from several millimeters to few hundred micrometers. process have been suggested. With the PFN-C photo-crosslinkable polymer presented on figureI.27a, Kwan and Al have used the direct patterning properties and employed the lift-off process to demonstrate the fabrication of cells with 4µmx4µm dimensions [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] . However, this approach strongly reduces the choice in suitable organic compositions. In order to be compatible with a larger range of organic compositions, the GIST group suggested an original approach considering the deposition of electrodes through a direct metal transfer technique [START_REF] Kim | A direct metal transfer method for cross-bar type polymer non-volatile memory applications[END_REF] . This stamping technique, illustrated on figureI.27c, enables fabrication of 8x8crossbar arrays with 4x4 µm² devices. A via-hole structure was also introduced to study the electrical characteristics at very low dimensions [START_REF] Kim | Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure[END_REF] : this exotic structure described on figureI.27b employed conformational deposition of polymers in a via-hole scalable down-to 200nm in diameter with Ptype doped silicon bottom electrode.

I.3.1.d Memory Layer Stacking (3D)

In their prospective paper Pinnow and Al highlighted the potential of organic memory device towards low cost stacking of crossbar memory layer as illustrated on figure I.28a. This approach enables increase in data density up to 4F²/n (where F is the technological pitch and n is the number of layers) [START_REF] Pinnow | Material Aspects in Emerging Nonvolatile Memories[END_REF] . In the case of small molecules based devices, the organic deposition through shadow evaporation techniques provides inherent stacking ability. Park and Al have reported a good demonstration where functionality and reproducibility in device behavior was particularly highlighted (see figure I.28b) [START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] .

In polymer or nano-composite approach where materials are obtained through solution processing, this stacking ability is not inherent since the solvent used for top layer deposition can potentially damage underling layers. In order to solve this problem, particular polymer matrix has been employed. Cho et Al suggested the use of thermally cured polyimide (PI) polymer matrix [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] . Song et Al. also employed this approach for the demonstration illustrated on figure I.28d with three stacked crossbar layers (3x64 bits) [Song10] . A photo-crosslinkable polymer approach was also suggested by Kwan and Al in [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] (see figure I.28c).

a) a) a) a) b) b) b) b) c) c) d) d) d) d)

I.3.2 Electrical Performances

We introduce here the basic requirements for resistive memories and present the memory cell characteristics observed in experimental organic based devices and their performances.

I.3.2.a Resistive switching

To electrically store the information, the device first requires the ability to change its resistive state upon the application of an electrical stimulus (Amount of Charge injected, Current or Voltage applied). This change in electrical behavior called resistive or conductance switching is observable trough as a hysteresis upon the Current-Voltage (I-V) characteristic of the resistive cell. The main typical cases described in [START_REF] Prime | Overview of organic memory devices[END_REF] and in [START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF] are shown below and illustrated with schematics in

I.3.2.b Retention

In information storage technologies, retention describes the stability of the programmed state in time. Two different cases could be clearly distinguished:

Non-Volatile Memory (NVM):

After the programming and even if the device is powered off, the device remains in a stable state4 until the presence of a specific external stimulus inducing RESET operation, Volatile Memories: For so-called volatile devices, the programmed state is not stable but naturally returns to its original state with time in the case of Dynamic Random Access Memory (DRAM) or, if the power is turned off, in the case Static Random Access Memory (SRAM).

I.3.2.c Reversibility

In the case of Random Access Memory (RAM) key requirement for memory cell is its ability to have high endurance. Reversibility of the switching is required through a so-called RESET operation. We could also point out here various types of behaviors:

Irreversible: After the first transition, the changes occurred in the device are irreversible. In this case this type of device is either described as Read Only Memory (ROM) or Write Only Read Many (WORM), Bipolar: Reset is obtained only when the device is biased with opposite voltage, Unipolar: Reset could be obtained by biasing the device in the same polarity, Unconstrained: If switching is constrained by external electrical conditions to break avalanche and avoid breakdown. For some devices, removing the constraint (compliance/serial resistance) and further polarization may enable Reset operation. This transition could be obtained in Bipolar or Unipolar mode.

I.3.2.d Programming window and reproducibility

The programming window corresponding to the On/Off current ratio characterizes the ability to distinguish the difference between programmed states. In an ideal case, a great On/Off ratio is preferred but ratio over a factor of 10 could be sufficient [START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF] . However this ratio should take into account the variability in device behavior at the wafer level, as well as the reproducibility of current and switching voltage in devices from cycle-to-cycle. Reproducibility and statistical distribution are poorly addressed in bibliography [START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF] . Nevertheless, few papers highlight this problem [Scott07, [START_REF] Vilkman | Negative differential resistance in polymeric memory devices containing disordered block copolymers with semiconducting block[END_REF][START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] and have published some results or suggestion to improve this point. Recently, Statistical distribution of device characteristics regarding On, Off current and Switching Voltage were presented for 3 layer crossbar memories made of 192 bits, enabling clear judgment on technology potential [Song10] (see figure I.29).

I.3.2.e Multilevel capability (MLC)

An interesting property for storage application is the ability of the devices to be programmed in several states. If these multilevel states are stable and can be clearly distinguished, it enables to store higher density of information in one physical device. Different groups have demonstrated Multi bit programming of Organic Devices. In particular in the case of NDR based devices [Lauters06, ChoBO06, Reddy09, Park09] the ability of conductance tailoring through different voltages in NDR region has been severally reported. Programming was obtained through subsequent I-V sequences, stopped in different conditions [Lauter06] or either with several pulse programming schemes [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] . In the case of small (Alq3) molecules based devices embedded with Ni nanocrystals, Park and al. demonstrated that multilevel programming through NDR was stable in time, with data retention on four different levels over 10 4 s [START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] (see figure I.30). Stable multilevel retention was also demonstrated over more than 800h [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] .

I.3.2.f Endurance

Endurance characteristics are often the weakness of organic resistive devices. Typical endurance characteristics range from hundreds to thousands of cycles. This performance is poor regarding actual specifications for Flash memories going up to 10 6 cycles. However, a few demonstrations reported promising endurance [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] or optimizable endurance with adapted programming schemes [START_REF] Kwan | Understanding the switching mechanism of polymer memory[END_REF] . In order to have clear judgment of the technological potential and optimize this point, wafer level statistics upon the influence of the programming scheme (On/Off current, voltage polarity and programming time) and materials are still required.

I.3.2.g Access Time

Regarding access time, very promising demonstrations have been reported by Kwan and Al in [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] . On the transient characteristics reported on figure I.31a-c it was observed that pulsed measurements enabled READ, SET and RESET operation below 500ns. Some demonstrations also reported switching with times below 10 nanoseconds, however as observed on figure I.31d existence of dead times or delay times have also been highlighted experimentally, limiting programming for reproducible operating to milliseconds or hundreds of milliseconds [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF][START_REF] Joo | Embossed structure embedded organic memory device[END_REF] .

I.3.3 Mechanism of conductance switching in organic thin films

From different available reviews [Scott07, Ling08, Heremans11, ChoB11], we point out that clear identification and classification of physical mechanisms in experimental devices remains unclear. Nevertheless, different families of hypothesis were suggested in order to explain the conductance switching observed in organic thin film devices. Following the structure and materials employed, it was suggested that switching:

• Could result from an intrinsic change in molecules.

• Occurs through a global change in device electrical configuration or involves changes in ionic distribution. • Is related to metallic or carbon-rich filament formation.

• Is provided by switching effects in electrodes interfacial oxide.

I.3.3.a Molecular mechanisms

Molecular changes such as isomerization, charge transfer or oxydo-reduction reaction that could occur in molecules, have been suggested for some devices to be potentially responsible for the resistive switching observed by changing the intrinsic molecular conduction [START_REF] Ling | Polymer electronic memories: Materials, devices and mechanisms[END_REF] .

Among the different materials, conformable molecules have been widely investigated for their potential resistive switching. Indeed, few molecules such as Rose-Bengal (RB) have been already reported for their photo-izomerization ability, leading to molecular configurations with different inherent conductivities (see figure I.32a). It has been suggested that such conformational changes could be electrically driven and thus suitable for organic resistive memories [START_REF] Bandyopadhyay | Multilevel conductivity and conductance switching in supramolecular structures of an organic molecule[END_REF][START_REF] Rath | Resistive switching in Rose Bengal and other Xanthene molecules is a molecular phenomenon[END_REF] . Similar hypothesis was also suggested for poly(9-2(9H-carbazole-9-yl)ethyl methacrylate (PCz) molecules where rearrangement in face-to-face configuration could improve the current transport through the Carbazole groups [START_REF] Ling | Nonvolatile Polymer Memory Device Based on Bistable Electrical Switching in a Thin Film of Poly(N-vinylcarbazole) with Covalently Bonded C60[END_REF] .

Charge transfer (CT) molecules or polymers have been also deeply investigated. In such materials, it is claimed that the external Field applied to the device can induce a charge transfer between groups in molecules, resulting in conduction changes. This hypothesis was particularly developed in the case of copper-teracyanoquinodimethane (CuTCNQ) organo-metallic molecules where oxidation reaction could switch TCNQ -anion in neutral TCNQ exhibiting higher conductivity (see figure I.32b) [Potember79,[START_REF] Müller | Organic CuTCNQ nonvolatile memories for integration in the CMOS backend-of-line: Preparation from gas/solid reaction and downscaling to an area of 0.25 µm2[END_REF] . Other original examples of charge transfers with Donor-Acceptor (DA) based materials have been reported by Yang et Al where charge transfer could occur from Gold nano-particles (G-NP) to semi-conductive small molecules (8HQ,P3HT) (see figure I.32c) [START_REF] Ouyang | Organic Memory Device Fabricated Through Solution Processing[END_REF][START_REF] Prakash | Polymer memory device based on conjugated polymer and gold nanoparticles[END_REF][START_REF] Ouyang | Application of nanomaterials in two-terminal resistive-switching memory devices[END_REF] or by Ling and Al where Carbazole groups of poly-(N-vinylcarbazole) (PVK) could transfer charge to grafted fullerene (C60) moieties (see figure I.32d) [START_REF] Ling | Nonvolatile Polymer Memory Device Based on Bistable Electrical Switching in a Thin Film of Poly(N-vinylcarbazole) with Covalently Bonded C60[END_REF] .

I.3.3.b Electronic mechanisms

Electronic mechanisms have been also suggested to explain some resistive switching observed in organic materials. Indeed, the electrical configuration of the devices could be strongly influenced by localized charge trapping, formation of space charged areas or either ionic migrations. These changes in the bulk or at the interfaces could further modulate the electrical conduction in the device. In the case of three-layer devices, Bozano and Al concluded in the functional role of nano-particles as charge trapping elements. Their observations were similar to the phenomenon described in inorganic diodes by Simmons and Verderber [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF] and explain it in terms of space charge field induced by charge trapping [Bozanno05] . Concerning nanocomposite devices, different configurations have been suggested. By employing PCBM molecules in polyimide (PI), Cho and Al suggested that PCBM could drive conduction through the LUMO levels of molecules. In the PI matrix the PCBM also acts as a deep trapping center where electrons could be captured thus raising the potential hills around the traps and hindering the transport of electrons [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF]. In their Model Lin and Al expressed the conduction in terms of space charge limited current and consider the influence of deep traps brought by gold nanoparticles, suggesting here that conduction could be enhanced when traps are filled with electrons [START_REF] Heng-Tien Lin | Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device[END_REF] .

I.3.3.c Formation of Metallic or Carbon rich Filaments

The formation of highly conductive filaments has also been suggested. This filament could originate form degradation of organic materials in the carbon rich phase [START_REF] Carchano | Bistable Electrical Switching in Polymer Thin Films[END_REF] or from metallic migration of electrodes [START_REF] Joo | Study on Threshold Behavior of Operation Voltage in Metal Filament-Based Polymer Memory[END_REF][START_REF] Vilkman | Negative differential resistance in polymeric memory devices containing disordered block copolymers with semiconducting block[END_REF][START_REF] Kwan | Understanding the switching mechanism of polymer memory[END_REF] . As illustrated on figure I.33, under electric field or trough thermal consideration, a conductive channel can be established in the organic layer leading to low conductive state. This filament could be further destroyed or dissolved with thermal effect or by reversing the applied electric field [START_REF] Ling | Polymer electronic memories: Materials, devices and mechanisms[END_REF] . Despite the fact that such a phenomenon could be difficult to control [ Vilkman09], different suggestions have been reported to improve their reproducibility for metallic based filaments. It includes pre-ionization of electrodes before filament formation [START_REF] Joo | Study on Threshold Behavior of Operation Voltage in Metal Filament-Based Polymer Memory[END_REF] , as illustrated on figure I.34, incorporation of metallic ions in the organic layer [START_REF] Billen | A comprehensive model for bipolar electrical switching of CuTCNQ memories[END_REF] or dynamic programming schemes [START_REF] Kwan | Understanding the switching mechanism of polymer memory[END_REF].

I.3.3.d Switching in Interfacial Oxide

It was pointed out in the previous section ( §I.3.1b) that most demonstrations of switchable devices reported in bibliography usually employ oxidizable metal as electrodes. Consequently, the formation of interfacial oxide has great chance to occur at the interface with organic materials. Some papers suggested that enhancing the formation of this oxide layer could be necessary [START_REF] Cölle | Switching and filamentary conduction in non-volatile organic memories[END_REF][START_REF] Yook | Transparent organic bistable memory device with pure organic active material and Al/indium tin oxide electrode[END_REF] or could improve the electrical memory characteristics [START_REF] Verbakel | Reproducible resistive switching in nonvolatile organic memories[END_REF][START_REF] Cho | Rewritable Switching of One Diode-One Resistor Nonvolatile Organic Memory Devices[END_REF] . However, a large number of metal oxides are currently deeply investigated for their own resistive switching ability [START_REF] Sawa | Resistive switching in transition metal oxides[END_REF][START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF]. Moreover, devices employing semiconducting polymers and aluminum electrodes such as Al/PVK:Au/Al [START_REF] Lai | Influence of electrical field dependent depletion at metal-polymer junctions on resistive switching of poly(N-vinylcarbazole) (PVK)-based memory devices[END_REF][START_REF] Lai | Ultrahigh on/off -Current Ratio for Resistive Memory Devices With Poly(N-Vinylcarbazole)/Poly(3, 4-Ethylenedioxythiophene)–Poly(Styrenesulfonate) Stacking Bilayer[END_REF] also demonstrate very similar electrical characteristics to oxide based memories as for instance in TiN/AlOx/Pt [START_REF] Wu | Low-power TiN/Al2O3/Pt resistive switching device with sub-20 µA switching current and gradual resistance modulation[END_REF] (see respectively figure I.35a-b). These observations strongly raise the question of exact origin for switching in organic devices made of oxidizable electrodes. In some cases it was found that interchanging or suppressing organic layers does not affect switching characteristics in the presence of an interfacial oxide [Karthäuser06] . It was shown for example that in the case of Rotaxane molecule based devices using a Ti electrode; the switching could be rather related to the TiO2 oxide layer5 [START_REF] Williams | How We Found The Missing Memristor[END_REF] . The functional role of interfacial oxide and organic layer regarding device switching ability remains unclear in most cases and is still a topic of discussion [Vilkman09, ChoB10 and Heremans11].

I.3.3.e Summary

In the research for organic resistive based devices, the focus has been mainly given on organic layer design with demonstration of new original compositions. The possible hypothesis explaining resistive switching in organic based devices are summarized on figure I.36.

Among them we found intrinsic switching in molecules, particular electronic configurations or extrinsic switching considering filament formation or switching in interfacial oxide layers. For experimental understanding, it should be considered that electronic devices are a combination of organic thin films and electrodes, and consequently several of these mechanisms could potentially occur within a single device.

I.3.4 Requirements & Challenges for Organic Resistive Memory Technologies

In this part we briefly introduce the main issues for the development of organic-based resistive memory devices. Indeed, in order to find interest towards industrial applications, a memory device should provide convincing arguments on numerous requirements. Among them we find the Memory Performances but also the ability to be fabricated and electrically operated in simple and cost affordable ways. Finally and nonetheless, it should enable optimization for future generations. This latest point absolutely requires the physical comprehension of device laws and mechanisms.

Details on the different points to consider are presented below in the Table I.3:

-34-

MEMORY PERFORMANCES INTEGRATION SCALABLE &SUSTAINABLE TECH. STATIC & DYNAMIC PERFORMANCES

• Large Programming Windows.

• Multilevel capability.

• Long Retention Time.

• Low access time (Read/Write/Erase) Until now, a large number of organic compositions have been investigated and promising characteristics regarding resistive switching as well as possible low fabrication cost have been demonstrated. However, there are still strong challenges towards the development of an organic resistive memory technology.

First of all, a deeper electrical characterization is required to correctly judge the memory potential in terms of performances. If I-V hysteresis, current ratio, switching voltage and dataretention are often presented, there are only a few papers commenting on the reproducibility of devices from cycle-to-cycle or device-to device. Endurance properties and environmental stability (Humidity, Temperature) are also poorly addressed.

Regarding scalability and integration issues, only few demonstrations have been presented. Crossbar and stacking ability have been demonstrated in the case of macro-cells. However, patterning electrodes at low dimension on organic layers remains challenging below the shadow mask resolution. Few approaches have been suggested (Lift-Off, Direct Metal Transfer) but solutions closer to conventional CMOS process are still required.

Concerning device understanding, although several mechanisms have been suggested to explain the resistive switching in organic two terminal devices ( §I.3.3), identification and corresponding physics has not been clearly demonstrated yet for experimental devices. We can also point out that device characterization and integration issues are poorly decoupled. Indeed, most of the studies investigate electrical properties in cross-point configuration with deposition of organic layer on a previously patterned bottom line creating non-uniform topography. Moreover, electrodes are mostly oxidizable and introduce uncontrolled native oxides at interfaces, making the device comprehension more complex (see §I.3.3e).

I.4 Our Approach

For this thesis work entitled "Development & Study of Polymer Organic Resistive Memory for Crossbar Architectures" the focus was given on four main objectives:

1)

Develop polymer resistive memory cells suitable for crossbar architecture.

2)

Provide a detailed electrical characterization on memory operation, performances, reproducibility and stability.

3)

Address the issues of scaling and integration of memory cells for CMOS

4)

Provide advanced characterization for device understanding

In our approach we have focused our study on a nano-composite material made of PolyMethyl-MethArcylate (PMMA) polymer doped with buckminsterfullerene molecules (C60) and experimented this material following different approach addressed in parallel.

I.4.1.a Process selection

Since the scope of our study focused on CMOS, the first requirement was to ensure the compatibility in terms of process and materials with the CMOS environment. In this context, polymeric based materials were preferred. Indeed, such materials enable the spin-coating process widely employed in conventional microelectronics for lithography resist processing: well known, well calibrated and available in all clean-room environments.

In this context, two different options are available: dedicated macro-polymers with specific properties tailored by chemical synthesis or composites made of polymer blends, Nano-particles, Small-Molecules or Ion doping. This latest class of materials was particularly chosen for its simplicity in terms of materials synthesis but also for the wide flexibility in the choice of organic components. Moreover, nano-composite strategies enabled reference devices and progressive tuning witch could be a key advantage for device optimization and mechanism understanding.

I.4.1.b Material composition

Among the different nano-composites studied in bibliography, we can distinguish all organic systems and hybrid systems incorporating inorganic materials (mainly nano-particles). For our study we have particularly chosen an all-organic approach for full compatibility with clean-room and CMOS requirements6 . Among the compositions, fullerene molecules have been suggested in polymer matrix such as Polystyrene (PS) [START_REF] Majumdar | Fullerene-based bistable devices and associated negative differential resistance effect[END_REF] or polyimide (PI) [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF]Song10] . In our study we purposely introduced C60 molecules in PolyMethyl-MethAcrylate (PMMA) polymer. The PMMA polymer is widely employed as lithographic resist in microelectronics and is consequently well known, fully compatible and could potentially be interesting for its patterning properties.

I.4.1.c Characterization strategy

In our study we decided to decouple as much as possible electrical characterization and integration issues. Macro-sized resistive test structures with full sheet low roughness bottom electrode and top pad electrode were used to ensure good organic film uniformity for a straight forward electrical characterization of organic layers. Two different configurations were studied -36-including inert and oxidizable electrode in order to investigate the potential role of native oxide in switching characteristics. In parallel, advanced structures were developed to demonstrate the advanced integration and scalability of memory cells.

Finally, we also decided to study the organic layer through different angles in order to improve its physical understanding. In parallel of electrical characterization in resistive structures, we also developed material characterization and electrical characterization in alternative structures such as the capacitive ones.

Materials Studies

Capacitive Studies

Resistive Studies (inert and oxidizible)

Materials Studies

Capacitive Studies

Resistive Studies (inert and oxidizible)

I.5 Conclusions of Chapter I

The historic introduction of storage technologies has illustrated the requirements and factors of success responsible for emerging, success and decline of technologies. We have highlighted two different axes of development: improvement of memory media performance and innovations for better suitability with targeted applications. This context enlightened the success of nonvolatile semiconductor FLASH technology in current memory market and its possible limits regarding future evolution. Among the alternative solutions investigated, we have highlighted the strong advantages brought by resistive memories in terms of integration simplicity, allowing higher data density and performance, and potential for complementing or replacing Flash memories.

In the second part, we presented the potential of organic materials for future electronics. Despite the fact that the single molecules approach could be particularly interesting for scaling towards molecular size, integration is still a major challenge with respect to conventional technologies. Promising demonstrations with dedicated integration schemes have been suggested, but compatibility with standard process and control of electrical interface remain highly challenging for the development of new technologies. On the other hand, working with organic thin films could take advantage of organic molecules benefits with alternative tunable properties and bring more flexibility for hybridization with microelectronics. Several demonstrations for memory device development have been briefly presented for this approach. Finally, we have seen that organic memories have a strong potential on a long term for molecular scaling, but also upon a short term for applications requiring low-cost, large-area flexible or printed organic electronics.

In the third section we have presented the current state of the art in the field of Organic Thin Film Resistive Memories. We have pointed out that a large variety of organic materials and device configurations have been presented for their resistive switching ability. In such structures, different physical mechanisms have been suggested, including the functional role of electrodes and integration impacts regarding the switching behavior. From an electrical point of view, the different electrical characteristics observable in organic resistive memory devices have been introduced and some demonstrations at the state of art presented here seem very promising with high on-off ratio, multilevel capabilities and fast programming times. However we pointed out that reproducibility and endurance are still poorly addressed in the current bibliography. The advanced integration has also to be developed even if few original or exotic demonstrations have been presented for downscaling and 3D stacking of memory cells.

Finally, in the last section, regarding the requirements for viable memory technology and the current state of the art, we have presented our research approach for polymer resistive memory development and study. We propose in this thesis work, the study of organic nano-composites made of (PMMA) insulating polymer resist and (C60) fullerene semi-conductive molecules. A transversal approach including material characterization and electrical characterization in complementary structures is also suggested in order to provide a global overview on the devices and their characteristics.

Chapter II

II

Fabrication & Material Characterization of (PMMA:C 60 ) Nanocomposites for Memories

In this Chapter, the development of nanocomposite thin films of Poly-Methyl-MethAcrylate (PMMA) insulating polymer resist with molecular doping of fullerene (C60) semi-conductive molecules is presented for memory device fabrication.

In the first section ( §II.1) we introduce the composite approach and present a basic material description. The recipes and experimental processes employed for the nanocomposite (PMMA:C60) elaboration are also detailed.

Then, in a second Part ( §II.2), the material characterization of fabricated layers is discussed. The impact of (C60) molecular doping upon the composite layer morphology as well as its influence on the thermal properties is presented. Since (C60) doping is expected to dictate the electrical behavior, the quantification and distribution of fullerene molecules in the layer are specifically investigated. Moreover, since (PMMA) was introduced for its direct patterning capabilities, lithographic processes have been experimented on the (PMMA:C60) modified resist.

The third section ( §II.3) is dedicated to thermal annealing of nanocomposite layers. Through microscopy we observe that annealing above the glass transition temperature (Tg) induces a reorganization of the composite phase with aggregation of (C60) in large clusters.

The fabrication of electrical devices is presented in the last section ( §II.4). Regarding challenges and interrogations from bibliography we have fabricated here different configurations for complementary electrical studies. Finally, a novel integration scheme is also suggested for high-density integration. As science and technology have developed, materials have been mixed in order to create advanced components or structures or blended in order to obtain the hybridizing or association of their intrinsic properties. At the material scale, two main configurations can result from the mixing of two or more components (A, B…). The first alternative is through REACTION: the components chemically react with one another and form a new material (C) that has its own intrinsic properties. The second alternative is when the considered components are not miscible: they are not prone to react and cannot be mixed together. This case leads to a JUXTAPOSITION of the components in a global material called a "Composite" (A:B). The composite's final properties would be a combination of its parent's individual properties.

For a composite, the advantage could potentially result in an optimized material where the strength of one component could compensate its co-component's weakness. However, juxtaposition of components can be realized in different configurations. Resulting of this association, the composite properties are strongly related to the final configuration that depends upon the RELATIVE QUANTITY of materials A and B and on the ORGANIZATION of the different phases. On the other hand, due to the non-miscibility, segregation can occur within the global material, if it undergoes a sufficiently large constraint in time and amplitude.

II.1.1.b Interest of organic nanocomposite approach for experimental studies

For the work of this thesis, we decided to study an organic nanocomposite based on an insulating polymer matrix doped with semi-conductive organic molecules. The ability to tune the material with different mixing conditions is a key advantage in order to study the role of the different organic components. Antagonistic materials were specifically chosen in order to easily differentiate the electrical role of both phases: an insulating polymer was used as supporting matrix, combined with a conductive or semi-conductive material doping in order to adjust the conduction properties. Semi-conductive organic molecules were specifically chosen instead of inorganic nano-particles in order to avoid metal potentially contaminant for the CMOS process. In semiconductor research and industry, polymers are widely used as lithographic resist for material patterning. In this context, PMMA has been particularly employed as an extremely high resolution resist in the electron beam lithography process [MicroChem] . As described in the schematic of figure II.1.b: exposure to deep UV light or X-rays creates a chain scission within the (PMMA), allowing for the selective removal of exposed areas by a chemical developer, making it a positive photo-resist. With the development of organic electronics, (PMMA) is also employed for its electrical properties as insulating dielectric layer for organic transistor devices For the work of this thesis, two different types of (PMMA) were employed: PMMA-950K-A2: It is a commercially available lithographic resist purchased from MicroChem with high molecular weight (Mw = 950K) dissolved in Anisole (2 mg/mL).

PMMA-96K:

The PMMA (Mw = 96K) was purchased in powder from Sigma-Aldrich and home-dissolved in toluene (purity 99%) with solution heating at 50° and sonication during 24h and finally filtered with micro-filter (2 µm).

II.1.1.d Fullerene (C60) semi-conductive spherical molecules

In order to bring electrical properties to the composite, we introduced (C60) fullerenes (sub nanometer semi-conductive molecules) in the polymeric matrix. Since their discovery in 1985 by H. Kroto and R. Smalley [START_REF] Kroto | C60: Buckminsterfullerene[END_REF] , (C60) fullerene molecules have been the center of a considerable amount of attention Indeed, their interesting semi-conductive properties as well as unique spherical geometry, make this molecule a promising building block for nanotechnologies and have been widely associated with polymers to form composite materials [START_REF] Wang | Polymers containing fullerene or carbon nanotube structures[END_REF] . As shown on figure II.2, fullerene (C60) has a super aromatic chemical structure consisting of 60 Carbon atoms, with a diameter of about 0.7 nm.

The molecule is chemically and physically stable and exhibits a semi-conductive behavior with distinct Highest Occupied Molecular Orbitals (HOMO) and Lowest Un-occupied Molecular Orbitals (LUMO). Consequently, it is currently widely used as a semiconductor acceptor type material in organic electronics [Sigma]. Moreover, from an electrical point of view, its ability towards electron trapping has been previously reported, suggesting that single (C60) molecules could store up to 6 electrons [START_REF] Haddon | The Fullerenes: Powerful Carbon-Based Electron Acceptors [and Discussion[END_REF][START_REF] Echegoyen | Fullerenes: Chemistry, Physics, and Technology[END_REF]. It has also been purposely employed in organic memory devices [Ling07, Mabrook09

II.1.2 Solution synthesis of organic Nanocomposites

Since polymeric materials can be processed through solvent dissolution, the composite elaboration was lead by mixing the different components in a common solution, before deposition and thermal treatment steps. In these experiments, the (PMMA) and (C60) molecules were dissolved separately in distinct solvent solutions (Toluene or Anisole). Then, both solutions were mixed with desired proportion in order to obtain the targeted C60 compositions. The C60 content in the PMMA is chosen to be defined by the mass ratio of C60 to PMMA (ρ) defined by equation (Eq. 2.1). However, depending upon the targeted doping concentration (ρ), the amount of fullerene mother solution (C60: Toluene) introduced will be different and thus modify the global ratio of polymer over solvent (wPMMA/solvent). In order to obtain the targeted amount of (C60) and keep a controlled polymer/solvent ratio in the final compositions, the nanocomposite solution is further compensated in our process with extra solvent.

The solvent and mixing conditions for solution elaboration corresponding to the experiments presented in this thesis are detailed in the Sample Description Table in Appendix II-A.

II.1.3 Thin-Film Processing

Through solvent dissolution, polymeric materials enable a wide range of processes for material deposition (spin-coating, spray-coating, deep-coating, xerography, ink-jet printing…). In this thesis work we particularly employed the spin-coating technique, widely used in micro and nanofabrication because of its ability to form very uniform thin films on flat surfaces. This method, illustrated in inset on figure II.4, consists in homogeneous spreading of fluid on flat surfaces thanks to the centrifugal force brought by rotation of the substrate. During and after spinning, the solvent evaporates, leading to thin films of dried material. This evaporation process could be enhanced by subsequent "baking" of samples in oven or on hotplate.

Nano-composite Solution Elaboration (A 11 )

-47-The full process used for the fabrication of the nano-composite thin film is described on figure II.4. The final film thickness depends mainly upon the rotation speed used and on solution viscosity (function of molecular weight of solid, material to solvent ratio and solvent used). In order to obtain good reproducibility for electrical devices behavior, high focus is given to the quality of the spin-coating process: after sonication the nano-composite solution was spincoated on 200mm Si base-wafers and dried at 120°C for 90s on a TEL MK8 industrial Track. The film thickness was further controlled by ellipsometry (Prometrix UV1280).

II.2 Material characterization of nanocomposite films

In this section we first monitor the impact of the doping with (C60) on the final nanocomposite film properties. Then to go further, different physical and chemical characterization techniques have been investigated in order to provide feedback upon (C60) and (PMMA) quantification in the layer and to understand the composite organization. Finally, since PMMA has been employed also for its patterning properties, the composite films capacity to be patterned by different lithographic techniques is studied.

II.2.1 Physical properties of (PMMA:C60) thin film

II.2.1.a Surface Roughness

The question of (C60) distribution in the film and possible aggregation in the layer is fundamental to understand its properties. Consequently, by using Atomic Force Microscopy (AFM) imaging techniques, we first analyzed the sample surface and observed how the (C60) doping could impact the layer roughness. AFM measurements were carried out with a Veecco in clean-room environment. The results obtained for both pure PMMA (PM00: PMMA:C60 -ρ=0wt%) and highly doped PMMA (PM20: PMMA:C60 -ρ=20wt%) are presented on figure II.5. Both samples seem to present flat surfaces with low roughness profiles. The roughness for different doping ratios up to ρ=20 wt% is reported on figure II.6. We observe stable and low roughness. This result suggests that fullerenes distribution is rather in volume and does not display visible aggregation on its surface.

II.2.1.b In -film distribution

In a second time, we have studied the impact of (C60) doping on the film uniformity and thickness. Indeed, by modifying the composition, introduction of fullerene molecules can potentially disturb the process condition. The Film morphology has been monitored with Transmission Electron Microscopy (TEM) imaging technique in a stack made of thermally oxidized silicon wafer as substrate and Aluminum as Top electrode. In this experiment the PMMA matrix used was a PMMA-96K with a ratio of polymer to solvent of 3wt%. After sample preparation through Focused Ion Beam (FIB) etching, the cross-sections of the samples was imaged in different doping conditions (ρ = 0, 5, 10 wt %). On theses pictures reported on figure II.7, we can observe a good uniformity of film thickness without any aggregation evidence. Moreover, thicknesses extractions show that the fullerene doping ratio has a minor impact on the film thickness, confirming that doping does not influence the process within the considered range.

FIGURE II.7:

TEM imaging on Si/SiO2/PMMA:C60/Al devices with different doping ratios (ρ = 0, 5, 10 wt %).

II.2.1.c Thermal properties

Thermal analysis is a field of material characterization where different physical properties are monitored as a function of the temperature. For polymeric materials, these techniques could be used to study different phenomena such as: degradation, glass transition, crystallization, crosslinking, etc.

We first investigated the impact of C60 concentration on the glass transition temperature by using Differential Scanning Calorimetry (DSC). This technique monitors the heat flow associated to the thermodynamic transitions in the materials during a change in temperature. Our experiments were carried out with DSC 2920 measurement tools from TA Instruments. The thermal profiles obtained for different doping conditions are presented on figure II.8a. On all these curves, we can observe a drop of the Heat Capacity Characteristics (Cp). This particular behavior characterizes a thermodynamic change in the material called vitreous transition. Above the corresponding temperature called glass transition temperature (Tg), the polymer chain gains enough energy to increase the degrees of freedom in the system. By enabling internal rotations, the mobility of polymer chains is strongly increased and the material is in so called plastic state. The glass transition temperature (Tg) extracted with different doping conditions is reported on figure II.8b. We can observe that the introduction of (C60) nano-molecules in the PMMA matrix increases the (Tg). This observation translates a global reduction of the chain mobility. This phenomenon could be explained by a decrease of the intrinsic free volume (available space between polymer chains) due to the occupation of polymer interstitials by isolated C60 molecules. Inshii et Al have also suggested such a reduction of the free volume in the PMMA polymer by C60 molecules in similar nanocomposites where the etching resistance of films was found to be increased with C60 introduction in the PMMA resist [START_REF] Ishii | C 60-Incorporated Nanocomposite Resist System[END_REF] . Our experiments completed here their observations and support the hypothesis of uniform distribution of single molecules or very small domains of C60 in the free volume of PMMA matrix. Indeed, on contrary, large clusters composed of several molecules of (C60) would rather increase the free volume and reduce Tg.

-51-We also investigated the thermal degradation of the composite by Thermo Gravimetric Analysis (TGA) with TGA 2950 from TA Instruments. This technique consists in monitoring the sample mass during temperature changes. Results are reported in figure II.9. We can observe that thermal degradation temperature (Td) corresponding to a drastic decrease in mass, is improved when nano-molecules are introduced: for samples containing up to 20wt% of (C60) we measured Td= 350°C with respect to Td=374°C for the sample containing 0%. In conclusion, with Thermal Analysis, we have shown here that C60 seems to be uniformly distributed in the PMMA matrix. By filling the free volume space it enhances the glass transition temperature (Tg). We also observe that C60 does not degrade the thermal stability but rather enhances the degradation temperature of the global material.

II.2.2 Quantification and in-layer Distribution

As introduced in paragraph ( §II.1.1a), the properties of composite materials are strongly dependent on the relative quantity of each component and on the organization of their distribution in the global material. Thus, we address in this paragraph the quantification and the distribution of (C60) molecules into the PMMA polymer matrix. Indeed, such information is of great interest to further understand and explain the electrical behavior of the samples. In order to do this, different physical and chemical characterizations were performed.

II.2.2.a UV-Vis Spectroscopy -Quantification

In the material characterization field, spectroscopic techniques are widely employed for nondestructive identification and quantification of chemical species. Depending upon the employed wavelength, different techniques have been developed, allowing to extract different types of information. Among the different available techniques, the UV-visible spectroscopy seems particularly interesting for the quantification of (C60) in (PMMA) matrix. Indeed, (PMMA) is well known for its good transparency in the visible spectra whereas (C60) is expected to have higher absorption on this range7 enabling a good contrast between the two species. The measurements were carried out on thin films by reflectance with a Woollam M2000 rotating compensator ellipsometer in the range of 190-1700 nm wavelength. Spectra were recorded at three angles of incidence: 65°, 70° and 75°. Both refractive indexes (n) and extinction coefficients (k) were then calculated in the ultraviolet range using mathematical inversion. The spectra obtained are reported on figure II.10 for samples including different contents of (C60) doping. We can observe that doping impacts on both index and extinction coefficients. When (C60) is progressively introduced, we observe an increase in the absorption peak around λ =215,261,233nm on extinction spectra. According to literature, these peaks around λ =213,260,230 nm are attributed to signals associated with (C60) molecules as previously reported [Hare91, LeeTW02]. On figure II.10c we have reported the extinction coefficient related to this peak at 261nm regarding the amount of (C60) introduced in solution. We can observe a linear dependence confirming that extinction on this range is directly related to the ratio of (C60) introduced in the film. These results demonstrate the ability of UV Visible spectroscopy techniques for quantification of (C60) loading rate in our nanocomposite films.

II.2.2.b ToF-SIMS -Quantification & Distribution

Concerning distribution issues, the all-organic nature of the studied nano-composites makes the discrimination of (C60) potentially complex. Indeed, the scale (individual fullerene = 0.7 nm) and lack of contrast between both carbon-based components disables an efficient discrimination through TEM or EDX imaging (see §II.2.1B). Considering the physical robustness of (C60) we have employed mass spectrometry techniques. Indeed, with a unit made of 60 atoms of carbon, the fullerene molecules have a characteristic signature in mass-spectrum around m/z = 720. For this reason, mass spectrometry has been the first tool employed to evidence experimentally (C60) production [START_REF] Kroto | C60: Buckminsterfullerene[END_REF] . We used here the Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) technique that is widely used on inorganic layers for material profiling during progressive abrasion. The sample under study is etched with a primary ion beam. Upon impact, clusters from the sample of the analyzed material are scattered. Some of them are ionized and then collected and analyzed in a Time of Flight mass spectroscopy unit. In our experiments, the samples were profiled with an ION ToF-SIMS V, using a 25 keV Bi3+ analysis beam and a 250 eV Cs+ sputtering beam both incident at 45° [START_REF] Py | Investigation of fullerene depth distribution in PMMA:C60 blends using dual beam ToF-SIMS[END_REF] . The mass-spectra for doped samples (PMMA:C60 -ρ=10wt%) are presented on figure II-11. From this global signature, we successfully tagged peaks related to (PMMA) and (C60) Respectively (C5H9O2 -) (m=101 u) for the PMMA monomer, and (C60 -) (m= 720 u) for fullerene derivative ions. The only difference detected between mass spectra of pure PMMA and composite layers consisted of this (C60) related mass group present in the high mass zone of the spectrum (See figure II.11d). This observation certifies the correlation with (C60) presence in the blend but also shows very little fragmentation of the fullerenes under abrasion and analysis beams.

In those conditions, the continuous analysis during progressive sample abrasion enables the extraction of depth profiles for species in the sample. Indeed, after identification of the peaks related to the targeted species, the profile consisting in species related signals regarding abrasion time could be extracted. By monitoring the interface position and suggesting homogenous abrasion velocity in the sample, this profile could be further displayed with depth position in abscissa. The result obtained in the case of (PMMA:C60 -ρ=10wt%) layer is reported on figure II.12a. For (MMA -) and (C60 -), we found extremely stable signals in the estimated nanocomposite region confirming very little damage of the organic layer while profiling (see reference [START_REF] Py | Investigation of fullerene depth distribution in PMMA:C60 blends using dual beam ToF-SIMS[END_REF] for details). In order to confirm the validity of extracted signals as representative information for nanocomposite organization, we also monitored the ratio of these signals in different doping conditions. The extracted ratios are displayed on figure II.12b and the ratios calculated from experimental data are displayed as a function of doping ratio introduced in solution. On a large full range -from very low doping concentration to work condition doping ratio-we show a linear behavior. This result confirms the ability of ToF-SIMS to precisely quantify (C60) weight ratio in the nanocomposite.

Moreover, the stable and constant (C60 -) signal observed in the nanocomposite region concludes on uniform depth distribution of (C60) in the (PMMA) polymer matrix.

II.2.3 Nano-patterning capabilities

As introduced in paragraph ( §II.1.1.c), the employed polymer, PMMA, is widely used for high resolution positive resist for e-beam lithography (EBL). Its thermal and optical properties make it also suitable for nano-imprint lithography (NIL). As presented later on in ( §II.4.4), the ability of the nanocomposite for direct patterning could be a key advantage for further integration in advanced electrical structures. In this section we investigated the patterning capabilities of (PMMA:C60) blends with thickness and doping concentration targeted for electrical application.

II.2.3.a Through E-Beam Lithography

E-beam exposure tests were carried out on un-doped and doped PMMA samples. Resist patterns were written using VB6 ultra high resolution (UHR) LEICA Gaussian beam equipment with an acceleration voltage at 100 kV and a beam current of 1 nA. Spot measurements at 100 keV indicate a size of 5 nm using Si/SiGe dense grating method. Isodens patterns (CD in the range 200nm -30nm) were exposed at 500µC/cm2 -700µC/cm2 and then developed during 120s in 3:1 IPA : MIBK solvents. On figure II.13a is reported a 3D-AFM picture of (PMMA:C60) patterned film with ρ=10wt%. The exposure dose was 660µC/cm 2 . We clearly observe the successful development of 200 nm lines / 200 nm space patterns. To go further, smaller 50 nm lines / 50 nm space patterns were also observed through SEM microscopy and reported on figure II.13b. After development, we obtained patterned lines with ~30 nm estimated width.

No significant increase of the Line Edge Roughness (LER) was observed making this observation consistent with the hypothesis of single (C60) or very small clusters uniformly dispersed in the matrix.

II.2.3.b With Nano-Imprint Lithography process

-56-Thanks to its thermal properties, the PMMA polymer is also suitable for Nano-Imprint Lithography (NIL) process. In opposite to EBL process, nano-imprint is a very promising process for low-cost patterning at the nano-scale. Despite the fact that this technique is still under development, its compatibility with various substrates makes it particularly interesting for low cost flexible electronic applications [Guo08,[START_REF] Rothländer | Nanoimprinted Complementary Organic Electronics: Single Transistors and Inverters[END_REF] . The principle of the NIL process is based on thermal and mechanical moldering as described on figure II.14a. A SEM picture after NIL Patterning of a 250nm wide line pattern on (PMMA: C60) film with ρ=10wt% of (C60) is reported on figure II.14b.

II.2.4 Conclusions on Nanocomposite Characterization

In first paragraphs we have presented that, the (C60) molecules could be considered as doping of (PMMA) matrix with minor impact on film processing. Indeed, through AFM and TEM imaging, no roughness or either thickness variation could be observed. The thermal analyses concluded on an enhancement of thermal properties rather than degradation when samples are doped with C60 molecules within the considered range. Moreover, since no aggregation or large clusters were found in all of the analyzed samples, the hypothesis of uniform distribution of single molecules or small clusters could be raised.

Since C60 is expected to dictate the electrical behavior of the composite, we were interested in the quantification and distribution analysis. Through optical spectroscopy and mass spectrometry, we were able to characterize very precisely the distributed amounts for each composite component. Moreover, with ToF-SimS depth profiling, we also demonstrated that C60 is uniformly distributed in the layer.

Finally, since PMMA polymer matrix has been particularly chosen for patterning capabilities, we have also demonstrated that the presence of (C60) does not affect this property within the considered range.

II.3 Impact of Thermal annealing above the glass transition

As it will be presented further in chapter IV, we proved that the thermal annealing of the nanocomposite at temperatures higher than that of the glass transition temperature (Tg) have a critical impact upon the electrical characteristics of inert electrode based devices. This thermal annealing is required in the device process to make it functional for memory usage. In order to understand this phenomenon, we investigate in this section the impact of thermal annealing on the morphology of nanocomposite layers.

II.3.1 Aggregation of C60 above the Tg

In the case of resistive devices with inert electrodes we evidenced that thermal annealing with a temperature above the Tg such as a bake of 30min at 180°C in inert atmosphere has an impact on the electrical characteristics and enables observation of negative differential resistance effect suitable for unipolar memory application (see Chapter IV). In order to clarify this point, AFM imaging has been carried out on nanocomposite layers before and after annealing above the Tg with different doping conditions: Pure PMMA and highly doped PMMA (ρ=20wt). Threedimensional pictures of the monitored surfaces are represented on figure II.15.

Without Thermal Annealing (spincoating bake only 120°C/120s)

With extra Thermal Annealing (180°C/ 30 min) PMMA ρ=0wt%

5µmx5µm 5µmx5µm 5µmx5µm 5µmx5µm

PMMA:C60 ρ=20wt% 5µmx5µm 5µmx5µm 5µmx5µm 5µmx5µm

FIGURE II.15: Three-dimensional picture of AFM scan obtained on pure PMMA (ρ=0wt%) and highly doped PMMA (ρ =20wt) before and after annealing at 180°C during 30 min in inert atmosphere (N2). The scan area is 5 µm x 5 µm.

-58-Whereas no significant variation of surface roughness is observed for the reference device made of pure PMMA, we clearly observe the formation of peaks and a very strong increase in global surface roughness in the case of C60 doped PMMA. Following this observation, optical confocal microscopy has been employed in order to have a global view on the materials after annealing. Optical picture obtained for pure PMMA and highly doped PMMA (ρ=20wt) after a thermal annealing consisting in 180°C during 30 min in oven with inert atmosphere (N2) are represented on figure II.14. On these pictures we clearly observe the formation of C60 Islands.

Before Annealing Before Annealing

II.3.2 Conclusions and Perspectives on Nanocomposite organization study

After observation of the functional role of thermal annealing on the electrical characteristics, this point has been preliminarily investigated with AFM and confocal optical imaging techniques. We have observed that annealing above the glass transition temperature induces strong modifications in the organic layer organization. In particular, the results obtained highlight the growth of C60 aggregates. Similar aggregation phenomenon has been observed in the case of PCBM fullerene derivative molecules introduced in thick polystyrene layers (~200-300nm) [START_REF] Laiho | Resources and growth orientation as predictors of firm growth[END_REF] . The agglomeration of PCBM in large clusters has been observed through TEM imaging and it has been demonstrated that control of the clusters morphology could tune the electrical characteristics of resistive memory devices. In order to go further toward the understanding and optimization of device characteristics, a detailed study (not presented in the scope of this manuscript) has been started in order to understand the kinetics of this phenomena in terms of Temperature, Annealing Time and Doping ratio. This study has also been coupled with electrical characterization of devices.

We have evidenced here the presence of large aggregates of C60 related to the functionality of the devices presented in chapter IV. This observation is a key element and should be taken into account for device understanding.

II.4 Test Devices for electrical characterization

II.4.1 Top electrodes processing on organic materials

Shadow evaporation is a widely employed process in the literature, in order to overcome the problem of electrode patterning on organic materials. In our experimental studies, we have also used this method for the fabrication top electrode fabrication. After thin-film spin coating and backing of nanocomposite upon a given base-wafer, the sample is loaded in a vacuum chamber where a metal is condensed on unmasked areas of the sample. For our experiments we used either a commercial metallic foil or a homemade silicon mask (see Appendix II-B) with pattern sizes ranging from 100 µm to 2 mm. Two different evaporation machines were used: a PLAYSYS-500S with e-beam evaporation and work pressure around 10 -7 Torr for LETI experiments and a MINILAB thermal Evaporator with work pressure around 7.5*10 -8 Torr [START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] for experiments carried out in Hanyang University. The process conditions used for the top electrode deposition are summarized in the Sample Description Table in Appendix II-A.

II.4.2 Macrostructures for straight-forward electrical characterization

As introduced in chapter I ( §I.4.3.C) and illustrated on figure II.17, different device stack configurations have been considered during this work for the electrical characterization of (PMMA:C60) nanocomposite layers. Indeed, in our studies we tried to decouple as much as possible the effect of integration such as non-uniformity or oxidation of electrodes.

Chapter III-MIS

BW : Si/Si0 The nanocomposite electrical properties have been first analyzed in optimized Metal-Insulator-Semiconductor (MIS) capacitive structures illustrated on figure 17ab. For this purpose, the (PMMA:C60) layers were deposited on thermally controlled oxidized Silicon and inert Platinum top electrodes were used. Details on sample fabrication are given in the Sample Description Table (Appendix II-A) and electrical results presented in chapter III.

For resistive structures, the cross-point configuration is usually employed in literature, this latest being the final architecture suggested in practical applications. However, in its simplest form, the cross-point involved organic depositions on top of shadow evaporated bottom lines and the resulting topology could impact the uniformity of organic layers spin-coating. This point could potentially complicate device characterization. In order to exclude this variable in our studies, we decided to focus the work on PAD structures with full-sheet bottom electrodes as illustrated in figure 17b-c. This approach ensured good film quality for enhanced reproducibility and straight forward characterization. In order to study the impact of electrode oxidation two main structures were fabricated. The resistive behavior of (PMMA:C60) composite layers was first studied with inert electrodes. Si-Base wafers (200mm) with 100nm of platinum deposited by Physical Vapor Deposition (PVD) on thick thermal oxide (500nm) were fabricated for this purpose. The corresponding electrical results are presented in chapter IV. Structures using oxidizable electrodes consisting of full-sheet Aluminum-Si bottom electrodes deposited on thick thermal oxides (500nm) and Aluminum top electrodes have also been experimented. The resistive behavior of such structures is presented in chapter V.

II.4.3 Structures for electrical downscaling

In order to improve the understanding of the physical mechanism involved and experiment the scaling limit of the fabricated devices, dedicated structures were fabricated for electrical scaling studies. Since in basic fabrication schemes, the top electrode size is limited by the shadow evaporation limit (~100µm) we developed a complementary test structure for this purpose. In those devices, electrical scaling is not brought anymore by top electrode reduction, but rather by the scaling of the bottom electrode made of buried lines and contact plugs as described in figure 18. In order to contact the bottom electrode, an opening in the oxide layer, out of the top electrode Area, was realized prior to the polymer deposition. Following the polymer deposition, macro-sized top electrodes were obtained by shadow evaporation. Additionally, in order to provide inert electrodes for device characterization, a 10 nm platinum coin was also introduced on top of the tungsten plug8 . This base-wafer enabled the fabrication of sub-micron polymer resistive devices and inert electrodes with electrical sizes ranging from 1.8 µm to 300 nm.

1mm -150 µm

II.4.4 Design of Advanced structures towards integration

In order to investigate polymer memory integration, different aspects should be checked such as inclusion in crossbar structures, encapsulation and 3D stacking. However, as introduced in the state of the Art paragraph ( §I.3.4), integration of organic materials is strongly limited by the process compatibility: patterning of electrodes on top of the organic layer is the main limiting factor for advanced integration. For this purpose, we have suggested in this thesis work the use of PMMA polymer resist as matrix for a direct patterning approach. It was demonstrated in paragraph ( §II.2.3), that the nano-composites fabricated for memory application were also suitable for high-resolution direct patterning through nano-imprint or e-beam lithography. Based on this particular ability we are able to suggest here an original integration scheme for the nanocomposite encapsulation (see figure II.19). In the case of buried bottom lines, the polymer could be deposited in a via or on plug connected to the bottom line. After the direct patterning of the organic layer, the top metal layer is deposited and encapsulates the organic material.

Base wafers with plug

Polymer deposition in Via & direct patterning

Metal deposition & standart etching

Polymer deposition in Via & direct patterning

Metal deposition & standart etching

Base wafers with buried line and vias

Base wafers with plug

Polymer deposition in Via & direct patterning

Metal deposition & standart etching

Polymer deposition in Via & direct patterning

Metal deposition & standart etching

Base wafers with buried line and vias FIGURE II.19: Original integration scheme in the case of a buried bottom line with via or contact plug. This scheme enables organic materials encapsulation and further patterning of electrodes with a standard etching process with respect to the thermal budget allowed by the organic matrix.

Thanks to encapsulation, the organic materials are protected bellow the top metal electrode, reducing the risk that the etching process impacts the underlying organic material. In such condition standard manufacturing process9 (wet/dry etching) could be employed for the top metal electrode definition at low dimension for high-density crossbar architecture (see figure II.20). Moreover, encapsulation will protect the organic materials from the environment, and ensure enhanced stability.

II.5 Conclusions of Chapter II

In this chapter, we presented the recipes and experimental process used for the (PMMA:C60) nanocomposite layers fabrication. The organic nanocomposite approach was chosen specifically -62-in this thesis work for its ability to tune the material with different mixing conditions. An insulating polymer (PMMA) polymer was used as polymeric matrix and doped with semiconductive (C60) fullerene molecules to rule out its electrical properties.

Then we evaluated the impact of (C60) molecules doping on the thin film properties. No roughness, thickness variation or either evidence of aggregation or large clusters could be found in our analyses after classical baking, indicating that in the considered range (C60) molecules have minor impacts on polymeric film processing. On the other hand, the thermal analyses conclude on an enhancement of thermal properties rather than degradation when (C60) molecules are introduced. Since (C60) is expected to dictate the electrical behavior of the composite, we investigated its quantification and distribution in the layers. Through optical and mass spectrometry, we were able to characterize very precisely the relative amount for both components in the composite and perform depth profiling, showing a uniform distribution of (C60) in the layer. With E-beam and Nano-Imprint lithographic processes we have also demonstrated that (C60) doping on the considered range does not affect the patterning capabilities of the PMMA matrix.

Thermal annealing above glass transition temperature has been used in chapter IV to enable memory operation in the device. A microcopy analysis was performed in order to link this electrical behavior with possible change in the material. Theses experiments emphasized the formation of C60 aggregation in the material with annealing above the glass transition.

Finally in the last section we briefly describe the fabrication of electrical devices. For basic test structure, full-sheet bottom electrodes and shadow evaporated top pads were chosen for a low damaging and uniform process. Different stack structures were suggested to investigate the electrical properties: Metal Insulator Semiconductor (MIS) Structures were designed for charge trapping ability studies and Metal Insulator Metal (MIM) with inert or oxidizable electrodes were investigated to conclude on the role of native oxide in the device properties. Advanced structures for electrical scaling studies were also fabricated and an original integration scheme based on direct patterning and encapsulation suggested for high-density integration of polymer resistive cells was proposed10 .

APPENDIX II.A: SAMPLE DESCRIPTION

MIM-PP1-PM00 0 MIM-PP1-PM02 2 MIM-PP1-PM05 5 MIM-PP1-PM10 10 Chap. IV ( §IV.1.1) MIM-PP1-PM20 Si/SiO2/Pt/- (Φ 200mm) 950K-A2 20 2.00/ Anisole 0.66/Toluene 120°C;120s MIM-PPT18-PM00 0 MIM-PPT18-PM02 2 MIM-PPT18-PM05 5 MIM-PPT18-PM10 10 Chap. IV MIM-PPT18-PM20 Si/SiO2/Pt/- (Φ 200mm) 950K-A2 20
MIM-AA1-PM00 96K 0 MIM-AA1-PM05 96K 5 Chap. V MIM-AA1-PM10 Si/SiO2/Al/- (40x40mm²) 96K 10 1.50/Toluene 120°C;120s + 120°C; 30min (Vaccum) MIM-AA2-PM00 96K 0 MIM-AA2-PM05 96K 5 Chap. V ( §V.3.2) MIM-AA2-PM10 Si/SiO2/Al/- (40x40mm²) 96K 10 2.00/Toluene 120°C;120s + 120°C; 30min (Vaccum) MIM-AA3-PM00 96K 0 MIM-AA3-PM05 96K 5 Chap V ( §V.3.2) MIM-AA3-PM10 Si/SiO2/Al/- (

APPENDIX II.B: FABRICATION OF SILICON SHADOW MASK

For this thesis work, homemade silicon shadow mask have been realized. The process flow for fabrication is described below on Theses masks have been fabricated with 4'' inch silicon wafers and different patterns have been employed. These masks have been employed for parallelization of sample fabrication (in order to have different splits with exactly same process conditions in top electrode depositions), fabrication with different electrode area and fabrication of electrodes with shapes adapted to the base wafer (specific shape and pitch was required to fit the bottom electrode structure employed for electrical downscaling).

Chapter III

III Capacitive Characterization on (PMMA:C 60 ) in MOIS Structures

In this Chapter, the electrical behavior of nano-composite layers fabricated from (C60) doped PMMA is investigated in Metal -Insulator-Semiconductor (MIS) capacitive structures.

The first section ( §III.1) briefly described the physical principle and characterization methods for MIS devices. Through Capacitance-Voltage (C-V) measurements, such devices are particularly interesting for the material characterization and also enable interface and bulk charge-trapping analysis.

In the second section ( §III.2) we introduce Metal -Organic-Insulator-Semiconductor (MOIS) test structure for a straight forward electrical characterization of the organic layer in capacitive configuration. The C-V characteristic of reference device made of pure PMMA in MOIS device is discussed.

Finally in the last section ( §III.3), we analyze the impact of progressive doping of PMMA by the (C60) molecules. Since charge trapping has been suggested to occur in nano-composite being potentially responsible for resistive switching, these organic layers were especially investigated regarding their charge trapping ability. As presented in paragraph ( §I.3.2), the mechanisms involved in resistive memory are still unclear because of possible complex physical mechanisms and lack of identified basic physical behavior of the structures. The role of charge trapping in organic compounds has been pointed out as a possible driving factor to explain the resistive memory behavior [Bozano05, ChoBO06, Ling08]. In bibliography, Nano-composite systems based on metallic nano-particles or molecules have been purposely designed [START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF][START_REF] Son | Carrier transport mechanisms of organic bistable devices fabricated utilizing colloidal ZnO quantum dot-polymethylmethacrylate polymer nanocomposites[END_REF][START_REF] Cho | Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer[END_REF] . In order to study the charge trapping ability in our nano-composite, electrical characterizations of (PMMA:C60) layers were carried out in Metal -Insulator -Semiconductor (MIS) capacitive structures. The MIS structure is considered as one of the basic devices in microelectronics and its electrical behavior has been deeply investigated during the past 30 years [START_REF] Nicollian | MOS (Metal Oxide Semiconductor) Physics and Technology[END_REF] . Capacitance-Voltage (C-V) electrical behavior, have been particularly studied, theorized and modeled [START_REF] Sze | Physics of Semiconductor Devices -Chapter 4 Metal-Insulator-Semiconductor Capacitors[END_REF] . From this powerful characterization technique, information upon the material characteristics such as stack thicknesses, doping concentration in the semiconductor, insulator/semiconductor interface and bulk charge trapping properties can be extracted.

III CAPACITIVE CHARACTERIZATION ON (

III.1.2 Electrical C-V behavior for ideal MIS structure

We recall here briefly the basics of C-V characteristics for Metal-Insulator-Semiconductor (MIS) devices in the case of P-type semiconductors. The MIS Structure is described on figure III.1a. For C-V characterization, a simple ideal electrical model is the serial circuit described on figure III.1b composed of an insulator capacitance (CI) in series with the semiconductor capacitance (CSC.). The insulator capacitance C I is fixed and determined by equation (Eq 3.1). However, the semiconductor capacitance C SC and the voltage drop within the semiconductor (V SC ) will depend upon the voltage applied to the Gate (V G ).

Semiconductor

Semiconductor substrate substrate

Gate Electrode For an ideal structure, both Fermi levels (EF) for Metal and Semiconductor are aligned when VG=0 (ΦM = ΦSC). At the equilibrium, the carrier density in the semiconductor is depending on the band configuration and could be described by the following equation:

0 V V G Insulator Insulator d, d, ε ε r r Semiconductor Semiconductor substrate substrate Gate Electrode 0 V V G Insulator Insulator d, d, ε ε r r V G V SC C I C SC V G V SC C I C SC ε I : Relative permittivity of insulator ε 0 : reference vacuum permittivity d: Insulator Thickness d 0 ε ε ⋅ = i Ci (3.1)
) exp( p ) exp( n p0 p0 kT q p kT q n BP p BP p Ψ ⋅ - ⋅ = Ψ ⋅ ⋅ =

ACCUMULATION (VG < 0):

The electrical field distorts the energy band level and bends it upward at the oxide-semiconductor interface. This bending reduces the energy gap (EF-EV) close to the interface. According to the expression of charge density reported on (Eq. 3.2), it will exponentially increase the number of majority carriers (holes for P-Type). In this configuration, almost all of the voltage is applied on the insulator. The total Capacitance could be considered as exclusively coming from the insulator CI.

I C 0) ( ≈ > G V C
FLAT-BAND (VG = 0): For an ideal structure (ΦM = ΦS) consequently when VG=0 energy bands are aligned and the semiconductor is at equilibrium. The total capacitance is only dependent upon the material parameters. This characteristic capacitance dependent upon doping considerations (see Eq3.3) is called Flat-Band Capacitance (CFB) and its corresponding voltage VFB (null for an ideal structure).

C 0) ( = = = FB G V V C with ) ( C 2 FB q N T k d A s i sc sc i ⋅ ⋅ ⋅ ⋅ + ⋅ ⋅ = ε ε ε ε ε ε i ,
0 V V G Insulator Insulator -------------- + ++ ++ ++ ++ ++ + + + + Si Si--P P Gate Electrode 0 V V G Insulator Insulator -------------- + ++ ++ ++ ++ ++ + + + + Si Si--P P Gate Electrode 0 V V G Insulator Insulator + ++ ++ ++ ++ ++ + + + + -- -- --- -- - - Si Si--P P Gate Electrode 0 V V G Insulator Insulator + ++ ++ ++ ++ ++ + + + + -- -- --- -- - - Si Si--P P Gate Electrode 0 V V G Insulator Insulator + ++ ++ ++ ++ ++ + + + + -- -- --- -- - - ------------ + ++ ++ ++ ++ ++ + + + Si Si--P P Gate Electrode 0 V V G Insulator Insulator + ++ ++ ++ ++ ++ + + + + -- -- --- -- - - ------------ + ++ ++ ++ ++ ++ + + +

DEPLETION (VG>0):

A small downward bending of the valence band reduces the density of holes at the interface. This regime is called depletion or desertion. Indeed, the majority carriers are pushed back in the bulk of the semiconductor substrate. Only the fixed charge brought by the doping acceptor ions remains at the interface creating a space charge region. The total capacitance is equivalent to the insulator capacitance in series with the semiconductor capacitance CSC corresponding here to the capacitance of depleted area (CDEP). The width of space charge region (WD) is increased by voltage and thus progressively reduces the total capacitance to reach a minimum CMIN.

D DEP SC SC I W 0 C C with C 1 C 1 1 0) ( ε ε ⋅ = = + = > SC G V C ↓ > ⇒ ↓ = ⇒ ↑ ⇒ ↑ ) 0 C( C C W SC DEP D G G V V (3.4)

INVERSION (Vg>>0):

When the field is strongly increased in positive voltage, the gap between Fermi level and Conduction band (EC-EF) becomes smaller than for Valence band (EC-EV). According to (Eq. 3.2) the initial minority carriers will now dominate at the interface and repopulate the space charge area. Almost all of the voltage is applied upon the insulator and the total Capacitance corresponds to the insulator CI. However, this phenomenon called inversion is frequency dependent. Indeed the electrons, originally minority carriers, are thermally generated in the bulk or at the interface and consequently such inversion layer does not have time to be formed at high frequency.

Low Frequency (V G >>0) ~ C I High Frequency 1/C(V G >>0) ~ 1/C I +1/C DEP

Consequently, the qualitative behavior of Capacitance-Voltage (C-V) characteristics for an ideal MIS structure with P-Type semiconductor is displayed on figure III.4.

III.1.3 C-V characteristics for Non-ideal MIS Structures

In non-ideal structure, the exact nature of the gate, insulator and interface with the semiconductor should be taken into account.

III.1.3.a Metallic Gate, with charge free insulator and interface

In non-ideal structure metallic gate and semiconductor could have different work-functions (ΦM ≠ ΦS).As shown on figure III.5, this difference induces a band bending at equilibrium (Fermi level aligned). A supplementary voltage is required to achieve the Flat Band regime (VFB≠0).

SC M MS FB V Φ - Φ = Φ = ∆ (3.

III.1.3.b Non-ideal Insulator

Concerning the insulator, some Fixed or mobile charge (respectively QF and QM) could be initially present in the insulator trapped (QT) under a specific voltage. According to figure III.6 and equation (Eq. 3.6), the presence of charge will screen the applied electrical field and results in a flat band voltage shift with a shift of the C-V characteristic in Voltage scale. Band bending for VG = 0 due to electric field screening by charge in the insulator (QI ≠ 0). (c) Flat band configuration when a voltage shift is applied to compensate the charge influence.

I T M F MS FB C Q Q Q V + + - Φ = (3.6) Q F, Q M , Q T : Fixed,

III.1.3.c Defects at the semiconductor/insulator Interface

At the semiconductor/insulator interface, interfacial defects (Dit) can behave like trapping centers at fixed energy, which can be charged or discharged progressively upon the device polarization. The total amount of charge effectively trapped at the interface (Qit) is function of voltage and also dependent upon the frequency as a specific time is required to fill the traps. In figure III.7 is reported an equivalent circuit that takes into accounts the influence of interface defects. By contributing to the global capacitance with a frequency dependent component (CIT), the Dit can result in a distortion of C-V characteristics, depending upon the measurement frequency, as illustrated on figure III.8b.

V G V SC C I C It R It C D V G V SC C I C It R It C D ² ² 1 it It D p C C C τ ω ⋅ + + = And ² ² 1 it it It p C G τ ω τ ω ω ⋅ + ⋅ ⋅ = (3.7)

III.1.3.d Impact of charge on C-V characteristics

Finally, the different effects of non-ideality in the MIS structures are summarized through the schematic C-V characteristics displayed on figure III.8. Metal gate work function and charge in the insulator have a direct influence upon C-V flat-Band voltage and is frequency independent. The impact of interface defects is characterized by a global distortion that depends upon the frequency. These differences would enable a clear characterization of the materials through the C-V measurement technique. -73-

III.2 Characterization of PMMA in MOIS devices

III.2.1 Structure for charge trapping analysis

In order to lead to a straightforward study of the nano-composites' electrical properties, we propose the introduction of thermally grown Silicon oxide (Si02) with 5.5nm in thickness at the Polymer-Semiconductor interface and the use of an inert top electrode.

The thermal silicon oxide avoids the formation of uncontrolled native oxide and ensures a wellcontrolled interface upon the semiconductor. This thick oxide acts from an electrical point of view as a blocking layer that suppresses charge injection on the Si side. Consequently, injection evidence and charge trapping extracted from electrical behavior can be largely attributed to Gate injection.

The inert top electrode ensures a controlled and stable interface quality at the gate interface.

Finally, the structure suggested here for experimental study, displayed on the figure III.9, could be described as Metal -Organic -Insulator -Semiconductor (MOIS) device.

III.2.2 C-V Characterization of PMMA reference devices

We are now presenting and discussing the measurements carried out on the reference device made of a pure PMMA organic layer introduced in the MOIS structure.

III.2.2.a C-V characteristics and unusual inversion behavior

Double sweep measurements were used here to monitor the C-V characteristics: the voltage was first applied from inversion region (VG>0) to accumulation (VG<0) and then swept back to inversion. The C-V characteristics obtained for High and Low frequency on the range [+8;-8V] are presented respectively on figure III.10a and III.10b.

We can observe that global behavior is in accordance with classical MIS behavior with three distinct regimes ACCUMULATION, FLAT BAND and INVERSION. However, some points strongly differed from the ideal behavior presented on figure III4. These characteristics are compared and discussed below: ACCUMULATION: The capacitance value CI extracted for the PMMA device (CLF=70pF and CHF=65pF for capacitance area~0.18 mm²) is in agreement with the expected stack capacitance. These slightly lower values, in High Frequency, could be explained by the well-known serial resistance effect. The Flat Band voltage (VFB) extracted here (VFB_PMMA=-3.8V) is much lower than the expected value considering Pt Gate and P type Silicon (N=10 16 cm -3 ) (VFB_Pt ~0-0.3V See [Sze02]). According to equation (Eq. 3.5) this shift of flat-band voltage in negative results from the presence of positive charge brought with the introduction of the organic layer. The common flat-band behavior observed for both Low and High Frequency characteristics without any Dit effect, shows that the charge involved here are located in the bulk rather than at the interface11 . Finally, no hysteresis is observed in the flat-band region between forward and reverse sweeps. This latter point means that the positives charges considered here are fixed, and are not impacted by the electric field applied in accumulation.

Inversion behavior: At low frequency, for Vg >> VFB, the C-V characteristic exhibits high inversion capacitance. The value CINV ~ CI is a typical Low Frequency inversion behavior (see figure III.4) but should not be observed at High frequency. However, we observe at 1MHz, upon forward sweep, the presence of an uncompleted inversion behavior, whereas a plateau behavior at CMIN should be expected (See figureIII.4). Moreover, we also observe at both Low and High frequencies, a hysteresis on the rise of this inversion peak between the forward and backward sweeps.

These preliminary measurements show that inclusion of a PMMA layer in the MOIS structure has several impacts on the C-V characteristics. Whereas the device behavior remains classical in accumulation and flat band region if we consider the serial resistance effect and PMMA layer as a positively fixed charged insulator, the inversion behavior seems however particularly unusual. Indeed even with high frequency we observe inversion capacitance peak where a plateau would be expected. Moreover, this inversion is not C-V static since it seems influenced by the sweep direction.

III.2.2.b Unexpected Frequency Behavior

In order to clarify the unexpected inversion behavior at high frequency, C-V measurements have been carried out at different frequencies and reported on figure III.11a. The ratio of inversion capacitance, regarding the stack capacitance is reported on figure III.11b.

In classical MIS devices the inversion regime is related to the carrier lifetime and thermal generation rate in the silicon substrate (See §III.1.2). This effect is observed only at low frequencies where recombination-generation rates of minority carriers can follow the small-signal variation of the voltage applied [START_REF] Sze | Physics of Semiconductor Devices -Chapter 4 Metal-Insulator-Semiconductor Capacitors[END_REF] . Experimentally, it is reported that for metal-SiO2-Si MIS devices the attenuation of inversion appears on the range between 5 Hz and 1 kHz [START_REF] Sze | Physics of Semiconductor Devices -Chapter 4 Metal-Insulator-Semiconductor Capacitors[END_REF] . This trend is reported on the chart figure III.11b. For frequencies higher than 1 kHz inversion rapidly vanish on inversion ratio stick on a value depending only of device consideration (oxide capacitance and depletion capacitance depending on substrate doping see Eq. 3.4). Indeed at such frequency, the minority carriers do not have time to be generated from the deep bulk and should not result in inversion peak on capacitance observed here. However considering inversion observed here in experiments at high frequency, the comparison with simulation clearly highlights that minority carriers could not originate from the bulk of the semiconductor (time constant is longer). These electrons could neither originate from the gate stack since thermal oxide (SiO2 5.5nm) has been purposely introduce at interface to block charge injection. The only possible hypothesis to explain this phenomenon at such high frequencies is to consider the presence of an alternative source of minority carriers (here electrons) that would have lower time dependence to provide the mobile charge for the formation of the inversion layer.

Such observations were also reported by [START_REF] Beylier | PhD Manuscript « Etude des dielectriques du pre metal et de leurs influences sur les dispositifs actifs[END_REF] in amorphous hydrogenated silicon nitride (a-SiNx:H) dielectrics and explained by a phenomenon called permanent inversion layer [Nicollian65, 82] .

III.2.2.c Model of Permanent Inversion Layer

In this model, Nicollian suggest that minority carriers could be attracted at the semiconductor interface by charge of the opposite sign initially stored in the dielectric. In those conditions it will create a permanent inversion layer at the interface witch could interfere with classical MIS behavior [Nicollian65,82].

In our experiments the conditions for this assumption are indeed combined: we have a P-type substrate with electrons as minority carriers and the negative flat band voltage extracted from C-V measurements indicates the presence of positive charge in the insulator. During device operation, the charges located under the electrodes are directly influenced by the gate polarization. However, as illustrated on figure III.12, the inversion layer remains permanent around the gate, and thus provides a carrier tank around the capacitor edge, (creating a fictive source-drain). With such proximity, these available electrons could reach deserted region and achieve a partial inversion even at high frequency.

Si Si--P P

0 V DEPLETION + + + + + + + + -- -- - + Si Si--P P 0 V V G < < V fb + ++ ++++ + ++ + + ------- ACCUMULATION ------ + + + + + + + + + + + --- ------ --- + + + + + + + + + + + + + + + + + + + + --- - ----- --- + + + + + + + + +

Si Si--P P

INVERSION (LF)

+ + + + -- -- - + + + + + + + + + + --- - ----- --- + + + + + + + + + - --- 0 V + + + + V G ~Vfb V G >> V fb - Si
Si--P P

INVERSION (HF)

+ + + + -- -- - + + + + + + + + + + --- - ----- --- + + + + + + + + + - - - 0 V + + + + V G >> V fb -- - - -- - Minority carrier tank Si Si--P P 0 V DEPLETION + + + + + + + + -- -- - + Si Si--P P 0 V V G < < V fb + ++ ++++ + ++ + + ------- ACCUMULATION ------ + + + + + + + + + + + --- ------ --- + + + + + + + + + + + + + + + + + + + + --- - ----- --- + + + + + + + + +

Si Si--P P

INVERSION (LF)

+ + + + -- -- - + + + + + + + + + + --- - ----- --- + + + + + + + + + - --- 0 V + + + + V G ~Vfb V G >> V fb - Si
Si--P P

INVERSION (HF)

+ + + + -- -- - + + + + + + + + + + --- - ----- --- + + + + + + + + + - - - 0 V + + + + V G >> V fb -- - - -- - Minority carrier tank
FIGURE III.12: Schematic of device operation with permanent inversion layer considering the PMMA organic layer as a positively charged insulator -Attracted by the positive charge from the PMMA, the permanent electron layer around the gate area could act as a carrier tank for the inversion or partial inversion from the edge to the deserted area.

III.2.2.d Influence of Device Area

In order to confirm the hypothesis of fictive source-drain edge effect brought with permanent inversion layer, we investigated here the influence of electrode Area on the inversion behavior. Indeed, considering that inversion at high frequency is mainly provided from the edge as displayed on figure III.13 and determined by the diffusion distance achieved by electrons from this fictive source drain (λ), the device area should have major impact on inversion ability. We have shown in Appendix III.B that inversion ratio defined as capacitance measured in inversion (CINV) over the insulator capacitance (Cox) could be express as:

1 1 1 C C ox inv α α β α + ⋅ + + = = r with tot inv D S S and C = = β α OX C (3.8)
The coefficient alpha is determined by the stack configuration (COX) and the semiconductor configuration fixing the length and capacitance of the depleted region (CD).

-77- However we observe in equation (Eq. 3.8) the influence of coefficient beta witch characterize the surface ratio of inverted area from the edge (Sinv) over the total Gate surface (Stot). By considering inverted area is function of diffusion distance achieved (λ) from fictive source drain mostly determined by the transit time fixed by frequency we have demonstrated in Appendix III.A that beta could be expressed as function of the gate area (A) as followed:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - Bottom View Lateral View Si Si--P P + + + + - - - + + + + + + + + + + + + + + + + + + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + + Total Gate Area (S tot =A) - Inverted Area (S inv ) Permanent Inversion Layer Permanent Inversion Layer Inverted Area (S inv ) Deserted Area - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - Bottom View Lateral View Si Si--P P + + + + - - - + + + + + + + + + + + + + + + + + + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + + Total Gate Area (S tot =A) - Inverted Area (S inv ) Permanent Inversion Layer Permanent Inversion Layer Inverted Area (S inv ) Deserted Area (a) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - Bottom View Lateral View Si Si--P P + + + + - - - + + + + + + + + + + + + + + + + + + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + + Total Gate Area (S tot =A) - Inverted Area (S inv ) Permanent Inversion Layer Permanent Inversion Layer Inverted Area (S inv ) Deserted Area - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - -- - - - -- -- --- - - -- - - - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - - - - --- --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- -- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - --- - - - - - - - - - - - - - - - --- - - - - - - - --- - - - - - --- ---- - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- - - - - - - - - - -- - - - - - --- - - - - - - - --- - - - - - - - - --- - - - - - - - --- - - - - - --- - - - - - - - - - - - - - - - - ----- - - - -- -- --- - - - - -- -- --- - - - -- -- --- - -- - - --- -- - -- - - - - - - - -- Gate diameter (d) Diffusion distance from edge (λ) - - - - - - - - - - Bottom View Lateral View Si Si--P P + + + + - - - + + + + + + + + + + + + + + + + + + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
A a λ π λ ⋅ = = 4 x (Circle) Α = = λ λ a x (Square) tot inv S S = β ) 1 ( 4 x x - ⋅ = β with Α ⋅ ⋅ + = ⋅ + = λ λ 2 ) 2 (1 ) 2 (1 x a (Triangular)
Resulting from these considerations we observe that increasing the device Area should decrease the beta coefficient and thus reduce the inversion ratio In order to check this hypothesis in our devices, C-V measurements have been performed with different Gate Area. These results obtained at high frequency (100 kHz) are presented on figure III.14.

III.2.2.e Hysteresis & Voltage Dynamic in Inversion

We have also previously observed the presence of hysteresis on inversion capacitance slope between forward and backward sweeps whereas accumulation and flat band behavior remained unchanged. In order to clearly understand this dynamic we have measured and reported on figure III.16 the C-V characteristics at Low frequency (1 kHz) with variable voltage boundaries in accumulation region (VACC). The device was swept from Inversion to Accumulation and brought back to Inversion three times in order to check the reproducibility of the observed behavior. We could observe that the accumulation voltage VACC has a direct impact on the inversion slope for backward sweep. With higher VACC the inversion capacitance peak seems to be "voltage-delayed" and a hysteresis window is progressively increased.

The influence of the positive voltage boundary was also studied. We considered a fixed accumulation voltage and a variable initial and final polarization in inversion (VINV). The effect of this variation upon CV hysteresis is shown in the plots presented on figure III.17. By starting with higher voltage in inversion, the hysteresis window induced by the negative polarization in accumulation has less impact and the hysteresis window is reduced. Finally, we observe here that the C-V characteristic in inversion is strongly influenced by the considered voltage range applied. The polarization in accumulation seems to induce a "voltagedelay" effect on the inversion behavior. On the other hand, an initial polarization in deep inversion reduces this influence. However, no visible consequences on the accumulation behavior (CI value) or on the Flat-Band behavior (VFB) could be observed. This latter point suggests that the electrical configuration of the stack remains unchanged between forward and backward sweeps. In conclusion, this hysteresis, observable on C-V inversion, translates here a memory effect controlled by the previous polarization applied in accumulation and inversion. However, the physical modification responsible for such a behavior seems to not occur in the gate stack since accumulation and flat-band region remains unchanged. Considering that the source of inversion behavior is an edge effect related to permanent inversion layer we can suggest that observable hysteresis could be related to edge modulation of the lateral carrier tank and do not deal with electrical modification in the Gate stack.

Voltage V g (V) Vinv = + 4 V Forward 1/2/

III.2.3 Conclusion for PMMA reference device

The global C-V characteristic of reference MOIS device with pure PMMA is in agreement with classical MIS behavior. However, we have observed an unusual behavior regarding inversion behavior. The unexpected frequency behavior and the presence of memory effect observed on inversion slope could be explained with the model of permanent inversion layer suggested by Niccollian. The validity of such hypothesis has been confirmed in our devices with frequency and area dependences as well as voltage dynamic influences studies. Such phenomenon is not linked directly to the presence of an organic layer in the gate stack but is rather an edge effect related to a particular configuration of the structure. On the other hand, from accumulation and flat-band behavior we concluded that PMMA could be considered as a positively charged ideal insulator.

III.3 Charge trapping memory effect controlled by C 60 doping

According to assumptions where resistive switching could be obtained due to charge trapping ability of the organic layer [ChoBO06, SonDI10], we have purposely introduced C60 fullerene molecules in the PMMA. Indeed, C60 molecules have been proposed in several polymer matrixes for electron trapping ability [START_REF] Kim | Effect of Fullerene Concentration on Flat-Band Voltage Shift of Capacitance-Voltage Curve in Organic Memory Devices Fabricated Using Hybrid Poly(4-vinyl phenol) Active Layer Containing Fullerene[END_REF]Mabrook10]. We are studying here the impact of C60 doping on the C-V characteristic for PMMA based MOIS devices.

For experimental study, the nano-composite strategy enables a preliminary investigation of the un-doped device before starting to monitor its progressive evolution when the concentration of dopant is increased. In our study, nano-composites containing ρ= 0 (pure PMMA), 5 and 10 wt% of C6012 were integrated in MOIS structures as described on figure III.18 with 50 nm polymeric film thickness.

Si

III.3.1 Hysteresis on C-V characteristics with C60 doping

According TEM picture presented for equivalent devices in section ( §II.4), we have observed that a (C60) inclusion does not have significant impact on film thickness within the considered ratio. Consequently, electrical measurements will be compared here under same voltage conditions for device PM00, PM05 and PM10. The capacitance-voltage (C-V) characteristics with respective ρ= 0, 5 and 10wt% of (C60) are reported on figure III.19 considering double sweeps performed from inversion region to accumulation on the range [+9V -14V +9V].

As previously reported in section ( §III.2), the C-V measurements performed on the reference device made of pure PMMA (ρ =0wt %) is consistent with an insulating behavior without Flat Band Voltage variation (∆VFB) between forward and backward sweeps. On the other hand, the progressive inclusion of C60 in samples PM05 and PM10 clearly induced a clockwise hysteresis behavior increased with the doping ratio.

-81- The flat band voltages extracted considering [+15 -15V +15V] measurements sequences are reported on figure III.20 In the case of doped device, positive shifts of VFB were observed with respectively ∆Vfb5wt% = + 1.12V and ∆Vfb10wt% = + 12.85 V. According to the equation Eq. 3.4, this positive shift is consistent with the trapping of negative charge with C60 doping. This observation is in agreement with previous reported studies [KimHJ08, HamJH08, LeeDI09, Mabrook10] suggesting C60 molecules as negative charge trapping centers. In the case of the MOIS structure the mechanism responsible for this reproducible hysteresis could be clearly identified. Indeed the charge is considered as coming exclusively from the gate, due to current blocking oxide placed purposely on substrate side to hinder injection from semiconductor. The electrical configurations in accumulation and inversion region are illustrated on qualitative band diagrams figure III.21a-b (Despite exact HOMO/LUMO level are not precisely reported PMMA gap is reported as EG_PMMA=5.6eV [START_REF] Hagen | Enhanced emission efficiency in organic light-emitting diodes using deoxyribonucleic acid complex as an electron blocking layer[END_REF] ; C60 energy gap is neighboring environment dependent but DFT calculation reports EG_C60= 2.88eV for single molecule [START_REF] Ling | Nonvolatile Polymer Memory Device Based on Bistable Electrical Switching in a Thin Film of Poly(N-vinylcarbazole) with Covalently Bonded C60[END_REF] ). The charging and discharging mechanisms are explained as followed:

In strong accumulation, the electrons could flow from the gate to the deep bulk by hopping or tunneling between isolated C60 clusters.

Due to lower gap of C60 regarding PMMA, the injected electrons could remain trapped when the electric field is decreased.

When field is strongly increased in inversion regime, this phenomenon could be further reversed and electrons are released towards the gate.

Thanks to MOIS structure, the clockwise hysteresis observed here is clearly identified as coming from injection and trapping of electrons coming from the gate in accumulation.

III.3.3 Time-Voltage Dependence

For charge trapping engineered materials, the effective charges stored in the media is related to the stress time and voltage applied and could be characterized with stress C-V (SCV) measurements [START_REF] Buckley | Investigation of SiO2/HfO2 gate stacks for application to non-volatile memory devices[END_REF] . Such experiments consist in sequential cumulative polarization with increasing stress time. The Flat band voltage is then monitored with C-V measurements between the programming pulses as illustrated on figure III.22a in the case of PMMA with ρ=5wt % under VPROG=-20V. These experiments could be repeated for different voltage conditions starting with pristine devices and sum-up to give a complete time-voltage programming characteristic. The results obtained for device PM00, PM05 and PM10 with respectively ρ= 0, 5 and 10wt% of C60 are displayed on figure III.19b-d and discussed below: DEVICE PM00 (PMMA -ρ =0wt %) -The initial negative Flat-Band voltage (VFB0) suggests the presence of positive charge as previously discussed. The time-voltage characteristics show that pure PMMA devices do not display any significant change in VFB on the full tested range from + 30V to -30V with stress time up to 5 seconds. It confirms here a pure insulator behavior without any charge exchange possibilities (trapping/releasing). PM00 : PMMA only ρ=0 wt% PM05 : PMMA:C60 ρ=5wt%

V PROG = 0 V PROG = [+5V to +30V step 5V] V PROG = [-5V to -30V step -5V]
V PROG = 0 V PROG = [+5V to +30V step 5V] V PROG = [-5V to -30V step -5V] Flat-Band Voltage V FB (V)
Cumulative Stress Time t PROG (s) DEVICE PM05 (PMMA:C60 -ρ =5wt %) -With voltage VG=-15V and below, we start to observe the evidence of negative charge trapping (∆VFB>0). A smallest negative shift (∆VFB<0) could be also observed at voltages above 20V, suggesting also positive charge trapping ability. DEVICE PM10 (PMMA:C60 -ρ =10wt %) -On C-V series without any polarization, we observe a positive shift along the sequence even if the device is not stressed with the pulse. This means that with such an amount of C60, the C-V measurement sequence starting at -10V already injects some electrons in the layer. A positive stress progressively counterbalances this effect by positive charge trapping. For stronger voltage it can result in a global negative shift for voltage programming above 15V. For negative voltage with polarization below -10V, the VFB drastically increases with a high voltage shift even with short stress time (ie VPROG=-20V and tPROG =100µs > ∆VFB~12V).

To summarize, PMMA organic layer that could be considered as a positively charged insulator, can become strongly negatively charged with inclusion of C60 and application of stress voltage. The polarization enables a charge transfer in the layer with electron injection in accumulation regime and electron trapping with C60 when voltage is released. We observe between 5 and 10wt% a strong increase in trapping ability. This point suggests that available trap number brought by C60 (only doubled between Device PM05 and PM10) is not the major parameter indicating also strong change in injection ability.

Moreover for ρ =10wt % we also observe that the monitoring C-V sequence at low field could inject electrons even in low accumulation regime. This observation proves that increasing doping ratio enhances injection by lowering the barrier between C60 molecules. High doped configuration improve injection and trapping ability of layer however it could also induce a loss of charge upon the time or during Reading operation at low-field.

III.3.4 Conclusions & Perspectives

In conclusion, with the MOIS device structure we have demonstrated that PMMA could be strictly considered as an insulator without any charge trapping ability. On the other hand, the introduction of C60 molecules in the polymer layer brings both injection and trapping capabilities. Indeed, through Flat Band voltage variation in MOIS configuration we clearly identified that C60 was able to store electrons in the layer. However, the balance between injection and trapping seems strongly dependent on C60 content ratio.

To go further in understanding charging and storage mechanisms, current-voltage transient characteristics during injection and releasing operation could be investigated and retention measurements carried out. In order to experiment the amount of stored charge without requiring the gate polarization that modify the electrical gate stack configuration, a transistor approach could also be employed. In such configuration the presence of trapped charge could be monitored on the transistors' channel conduction.

III.4 Conclusions of Chapter III

In this chapter, we have first studied the electrical behavior of (PMMA:C60) nano-composite in capacitive structure. For experimental study, a dedicated test structure was fabricated including the organic layer and a blocking oxide at the bottom interface leading to Metal-Organic-Insulator-Semiconductor (MOIS) structure.

In the first section, the interest of Metal-Insulator-Semiconductor (MIS) structure for electrical characterization was presented. We briefly recalled the basic behavior for an ideal MIS device and the main impacts brought by non-ideality in experimental devices regarding C-V characteristics.

Then in the second section, a reference device made of pure PMMA was first characterized. Its Capacitance-Voltage (C-V) characteristics have been discussed, regarding the expected MIS behavior. Despite an unexpected inversion behavior that was further explained in terms of edge effect with permanent inversion layer phenomenon, the C-V behavior of the gate stack is consistent with the MIS device behavior. From these characteristics we deduce that PMMA could be considered in MOIS as a positively charged insulator.

In the last section, we have studied the impact of progressive C60 doping of PMMA. Whereas no trapping ability could be observed for the pure PMMA, we have observed a clockwise hysteresis in the case of doped PMMA. In the particular configuration of MOIS, this effect has been clearly identified as charge injection and trapping in accumulation regime brought by C60 molecules.

Finally, as a first step of electrical characterization, C-V measurements on capacitive structure concluded on good interface quality without visible effect of top electrode deposition and good insulating properties of PMMA. With the progressive introduction of C60, our study highlights the potential of the developed nano-composite layer for electron injection and storage13 . The resulting trapping ability of the layers seems to be balanced by amount of C60 introduced: C60.providing potential traps for electron but also dictating the injection and loose of charge by controlling the transport in the layer.

+ + + + + + + + + + + + + + + + + + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + +
+ + + + + --- - --- - -- - -- -- - --- - -- - -- + + + + + -- - --- - -- - -- --- - --- - -- - -- + + Total Gate Area (S tot =A) - Inverted Area (S inv ) Permanent Inversion Layer Permanent Inversion Layer Inverted Area (S inv ) Deserted Area (a)

III.B.a Expression inversion ratio

The inversion ratio defined as capacitance measured in inversion (CINV) over the insulator capacitance (Cox) could be express as function of depletion capacitance (CD) and geometric considerations:

III.B.b Expression of beta coefficient for different geometry

We consider basic geometries (Circle, Square and isosceles right triangle) with a total area defined by the side or diameter distance (a) and an inverted area defined by the diffusion distance of carriers from the edge (λ). Thus beta coefficient could be express as following:

A a λ π λ ⋅ = = 4 x (Circle) Α = = λ λ a x (Square) tot inv S S = β ) 1 ( 4 x x - ⋅ = β with Α ⋅ ⋅ + = ⋅ + = λ λ 2 ) 2 (1 ) 2 (1 x a (Triangular)
-87-

Chapter IV

IV Unipolar Multilevel Resistive Memory Effect in (PMMA:C60) with inert electrodes.

In this Chapter, the electrical behavior of nano-composite layers fabricated from (C60) doped PMMA is investigated in Metal-Organic-Metal (M-O-M) resistive structures with inert electrodes.

In the first section ( §IV.1), the screening of resistive memory effect is briefly introduced and the typical electrical behavior observed for devices with different material configurations (doping concentration, annealing temperature) are presented. Nonlinear resistive behavior without memory effect is evidenced in (PMMA:C60) layers fabricated with a standard baking recipe. On the other hand, for nanocomposite layers annealed above the glass transition temperature, the appearance of a hysteresis is observed above a critical voltage, as well as a Negative Differential Resistance (NDR) behavior.

In the second section ( §IV.2) the unipolar memory effect associated to Negative Differential Resistance is demonstrated and a preliminary overview of the basic memory characteristics is provided. Multilevel ability, retention, reproducibility, endurance and distribution of measured characteristics are presented. Pulsed programming and downscaling of the memory cell has been also specifically studied in order to benchmark the potential of the developed devices for memory applications.

The third section ( §IV.3) is dedicated to an original in-depth analysis of the multilevel memory operation. The good device reproducibility enabled a detailed and statistical analysis of the different operation regimes and their boundaries. These experiments provided elements for a clear comprehension of the device operation and the data extracted has been employed for the elaboration of simple quasi-static behavioral model.

IV UNIPOLAR MULTILEVEL RESISTIVE MEMORY EFFECT

IV.1 Resistive behavior of (PMMA:C 60 ) layers in MOM Structures

In order to investigate the potential of (PMMA: C60) layers for resistive memory applications, electrical Current-Voltage (I-V) characterization was carried out on Metal-Insulator-Metal (M-I-M) structures with organic nanocomposites as insulator (M-O-M). In order to exclude the formation of interfacial oxide and rule out metal oxide switching phenomena upon electrical characteristics, we consider in this chapter devices using Platinum electrodes, whose inert nature allows to rule out any effects that could originate from metallic oxidation.

IV.1.1 Screening for Current hysteresis

In order to identify resistive memory behavior, a full set of Current-Voltage (I-V) characteristics were measured upon several samples in order to monitor the presence of current hysteresis. These measurements were carried out upon multiple devices (5-10 devices for each composition and specific test) in order to obtain characteristics of intrinsic nature. For each device, unipolar and bipolar voltage sequences with increasing amplitude (double measurements consisting in forward and backward sweeps) were applied until breakdown.

IV.1.1.a Influence of C60 doping upon leakage current

Unipolar Current-Voltage characteristics, measured upon devices with platinum electrodes and (PMMA:C60) layers with different C60 doping conditions (ρ = 0,2,5,10 and 20 wt%), are presented in figure IV.1 (See in Appendix II.A for fabrication details -samples MIM-PP-PMxx xx being the doping ratio). The observed characteristics do not show any evidence of significant resistive switching hysteresis. Nevertheless, it is found that the C60 doping has a direct impact on the conduction in the nanocomposite layer., A pure insulating behavior with leakage current below 10pA is found on pure PMMA, whereas the most highly doped sample (ρ=20 wt %) exhibits a up to milliamp leakage before breakdown around 30V. -90-This increase in conduction brought by the (C60) is in agreement with the observations made on similar compositions, using fullerene (C60) or fullerene derivatives (C60-PCBM) in insulating polystyrene (PS) [START_REF] Majumdar | Fullerene-based bistable devices and associated negative differential resistance effect[END_REF]Baral08] . However, in these works, the (C60) doping also induced hysteresis and Negative Differential Resistance (NDR) behavior. Such observations were not evidenced in devices with (PMMA:C60) layers and platinum electrodes.

IV.1.1.b Electrical behavior of thermally annealed nanocomposite layers

On the fullerene based devices exhibiting hysteresis and NDR effect, it has also been reported that the thermal anneal of the organic layer above glass transition (TG) could enhance the agglomeration of fullerenes in the layer and allow to tune the electrical characteristics [START_REF] Laiho | Tuning the electrical switching of polymer/fullerene nanocomposite thin film devices by control of morphology[END_REF] . In order to investigate the impact of thermal annealing on the electrical behavior of (PMMA:C60) layers, samples have been annealed in oven with different temperatures and time after spincoating and before the deposition of top electrode.

The Current-Voltage characteristics were monitored until breakdown in both polarities and on several devices, for samples without thermal annealing and thermally treated samples during 30min at 180°C. The results obtained for pure PMMA (ρ=0 t%) and (PMMA:C60) with ρ=2,5,10 and 20wt% are reported on figure IV.2. On the reference sample made of pure PMMA, the impact of the thermal treatment was of minor influence with respect to the other samples (Breakdown voltage slightly lower, current level of the same order). In the case of C60 doped samples, we observed a strong increase of the current level and decrease of the breakdown voltage. This observation confirms here the effect of thermal annealing upon electrical characteristics tuning. The screening methodology employed on un-annealed (PMMA:C60) layers in ( §IV.1.1a) were applied upon a series of thermally treated samples with different times and temperatures. The -91-results obtained with thermal annealing at 180°C in nitrogen during 30 minutes were reported on figure IV.3. We report here the electrical behavior of the sample under multiple voltage sweep sequences with increasing maximum voltage.

The obtained results do not show any significant hysteresis for a pure PMMA reference device, and low-doped samples (ρ=2 and 5wt %). However, for samples doped with ρ=10 and 20 wt %, when no hysteresis is monitored on double sweep sequences with maximum voltage lower than 15V, we observe that sweeping the voltage until +/-15V, triggers the appearance of a current behavior with Negative Differential Resistance (NDR). In conclusion, the extensive screening of device characteristics, allowed to evidence specific conditions for obtaining doped nano-composite based devices, showing a hysteresis behavior upon the I-V characteristics.

Doping concentration ρ (wt%)

IV.1.2 Conditions for Hysteresis and NDR behavior

In our devices, made of (PMMA:C60) layers with Platinum electrodes, we found that specific material processing conditions and specific electrical conditions are required to evidence the presence of hysteresis and Negative differential behavior.

IV.1.2.a Specific material processing conditions

In our experiments, hysteresis and NDR behavior were found only in doped samples after thermal annealing above the glass transition temperature. This observation is illustrated in figure IV.4, with appropriate I-V sequences ([0→15V→0V]). Indeed, in absence of (C60) doping, the device exhibits only an insulating behavior and without thermal annealing doped sample does not exhibit any resistive switching. The process fabrication point, chosen for the study of memory ability is the combined use of a nanocomposite doped with ρ=10wt% and thermal annealing above the Tg (180°C, 30min) enabling hysteresis and stable NDR behavior.

IV.1.2.b Specific electrical conditions-The forming operation

In order to observe the hysteresis behavior, a specific electrical forming operation is required. As shown on figure IV.5 with successive sequence and different maximum voltage, no hysteresis is observed if the device is biased below a critical voltage called the forming voltage (Vforming). Above this threshold, the device exhibits a current hysteresis with Negative Differential Resistance behavior (NDR) in a certain voltage range (VNDRmin → VNDRmax).

-93-

V MAX = 15V V MAX = 14V V MAX =13 V V MAX = 12V Voltage V g (V)

IV.1.3 Negative Differential Resistance behavior

After the first hysteresis, called in this manuscript "Forming Operation", the subsequent measurements made of double sweep measurements starting form 0V and bring back to 0V show a reproducible quasi-static behavior. At low-field, [0; VNDRmax] the device exhibits an ohmic behavior until a critical voltage value VNDRmax is reached, where the current progressively decreases with a so called Negative Differential Resistance (NDR) behavior within a certain range [

(V) Sweep 1 [0V > 8V > 0V] Sweep 2 [0V > 8V > 0V] Sweep 3 [0V > 8V > 0V] Sweep 4 [0V > 8V > 0V] Sweep 5 [0V > 8V > 0V]
(V) Sweep 6 [0V >-8V >0V] Sweep 7 [0V >-8V >0V] Sweep 8 [0V >-8V >0V] Sweep 9 [0V >-8V >0V]

IV.1.4 Conclusions on the electrical behavior of (PMMA:C60) layers with Platinum electrodes

It has been reported in the literature that devices made of aluminum electrodes and an organic composition based on fullerene molecules and insulating polymers such as (PS:C60) [START_REF] Majumdar | Fullerene-based bistable devices and associated negative differential resistance effect[END_REF] , (PS:PCBM-C60) [Baral08] or (PI:PCBM-C60) [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] could exhibit enhanced conduction, current hysteresis and Negative Differential Resistance behavior brought by the fullerene doping.

For the screening of current hysteresis, an extensive electrical study has been carried out here with different materials and electrical conditions (doping concentrations, different voltages and polarities applied). In our experiments with (PMMA:C60) layers using Pt electrodes, devices with different doping concentrations only exhibited enhanced conduction with the C60 doping and no significant hysteresis or Negative Differential resistance was observed.

However, if the organic layer is treated with a specific thermal anneal above the glass transition temperature, we found that the devices can exhibit Negative Differential Resistance (NDR) after the application of an initial forming sequence. This NDR behavior was found to be symmetrical and particularly reproducible following successive measurements.

IV.2 Memory Operation for NDR based devices

In literature, devices exhibiting Negative Differential Resistance (NDR) behavior have been reported for their ability toward unipolar memory effect [START_REF] Bozano | Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles[END_REF][START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF][START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] . In devices referenced as MIM-PP-PM10T18014 , made of (PMMA:C60) nano-composites doped and thermally annealed above the glass transition (TG) and inert electrodes, we have evidenced in the previous paragraph ( §IV.1.3) reproducible and quasi-static NDR behavior after the forming operation. We present in this section the associated multilevel unipolar memory ability and a benchmark of the basic memory characteristics.

IV.2.1 Unipolar Multilevel Memory Effect

IV.2.1.a Unipolar programming through polarization in NDR

For NDR-based memories, a polarization is applied in the NDR region in order to program the device at different resistance levels [START_REF] Bozano | Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles[END_REF] . Typically, such polarization is obtained with single sweep measurements stopped in NDR region [0 VNDR] as illustrated with the sweep 10 on the figure IV.7a. Indeed, we observed that this final polarization at VNDR= +8V induced a high resistive behavior at low field on the subsequent measurement sweep (sweep 11). Once programmed, the operation of the device upon the NDR region appeared again after an abrupt transition from the high resistance characteristic at a given threshold voltage called switching voltage (Vsw). By stopping again abruptly the polarization at VNDR= +8V, similar high resistance behavior is observed at low field on sweeps 12 and 13. With several measurements in both polarities, we found in figure IV.7b that the programming in high resistive State (HRS) through single sweeps is symmetrical and does not depend upon the voltage polarity. -96- The reproducibility and symmetry of this unipolar programming is illustrated on figure IV.8 where current level and switching voltage are monitored over 25 sequences with sequences in both polarities.

IV.2.1.b Multilevel operation

By using various single sweeps to polarize the device in the NDR region (0V → VProg) we found that the subsequent low-field resistance could be set at different levels ranging from a low resistive state (LRS) here being 325Ω to High Resistive State (HRS) here 1.5MΩ, strictly controlled by the value of VProg in NDR. (See figure IV.9). This unipolar multilevel ability through NDR polarization is in agreement with other reports on compositions with NDR operation [Bozano05, Terai06] . Moreover, we point out here a clear increase of the switching threshold voltage Vth, with higher initial low-field resistance (this point is discussed late in §IV.3.3). Finally it is important to highlight here that such devices enable a sufficiently large window to allow a multiplicity of resistive states. The extracted current levels in time are reported on figure IV.11 in the case of a device programmed at three different levels and monitored continuously over 3.10 4 seconds. In the case of different devices programmed at 5 different states monitored over 3 days, it was found that the multi-levels are stable in time, making the devices suitable for Non Volatile Memory (NVM) applications.

IV.2.3 DC Memory cycling

Following the unipolar multilevel programming observations, it was determined that the device could be programmed (SET) and erased (RESET) upon the same or reverse voltage polarity by using appropriate voltage sweep sequences.

-98-

The RESET was performed by biasing the device in the NDR region above VNDRmin while SET operation was performed by sweeping the device above Vth to reach the NDR region, before sweeping back to a higher current value still within the NDR until leaving NDR at VNDRmax. As illustrated in figure IV.12a, DC cycling sequences were performed here with [0→+10V] for RESET and [0→-8V→0V]15 for SET. The stacked I-V characteristics obtained on 125 subsequent Program/Erase DC cycles are presented below in figure IV.12b. Once again, we can point out the good maintaining of the quasi-static resistive levels and switching behavior.

IV.2.4 Reproducibility and variability

If hystereses, on current and conductance switching have been demonstrated in a large number of compositions, the reproducibility of the observed behavior is poorly addressed in the literature upon polymer resistive memories. However, this point is critical to judge the potential for memory application required for device and technology development [Bozano07, and Vilkman09] . Nevertheless, few papers highlighting this problem have published statistical distributions and suggestions such as the use of self-assembled monolayer [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] or enhancement of interfacial oxide [START_REF] Cho | Rewritable Switching of One Diode-One Resistor Nonvolatile Organic Memory Devices[END_REF] have been proposed. In our original configuration where Pt inert electrodes were used in order to rule out the parasitic interfacial metal oxide we have observed good reproducibility on I-V characteristics. In order to document this point, we present here statistical distributions in current levels and switching voltages, on multiple device characteristics.

IV.2.4.a Cycle-to-Cycle distributions

For statistical purposes, multiple I-V characteristics were collected over more than 500 Program/Erase DC cycles, with the measurement methodology presented in figure IV.12. From these results, the current levels in both On (LRS) and Off (HRS) states have been extracted and are reported upon the cycle number in figure IV.13a. The HRS current level is observed to be very stable, demonstrating a robust RESET operation process. For the ON state, we can observe few intermediate levels, suggesting failure of the SET operation. I-V characteristics -99-corresponding to the "MIS-SET" are reported in the inset of figure IV.13b. In those cases, we can observe that the switching process towards NDR is reliable. However, during the reverse sweep, a random set could occur in the NDR region, leading to medium resistive states. Statistically, this phenomenon occurred rather rarely and appeared to be accelerated by the cumulative electrical stress applied along the cycles: 0 cases within the first 150 cycles, 16 cases within the first 400 cycles (< 5%) and 45 cases in the last 150 cycles (< 8% of total) before the breakdown of the device after 590 cycles 16 . From these data, we have also extracted and reported the Cumulative probability of current levels in programmed states and histogram distributions of the switching voltage respectively on figure IV.14a and IV.14b. Excluding the SET failures, (observed in DC cycling and strongly activated by cumulative electrical stress) we can observe tighter distributions with a potential large on/off ratio (~10 7 ) and grouped switching voltage distributions. 16 For these experiments the devices was continuously stressed over more than 15 hours.

IV.2.4.b Device-to-Device distributions

In order to be suitable for memory application, low variability between individual memories cells at the wafer level are also preferred. In order to address this point, preliminary measurements have been carried out on 56 devices programmed in three different configurations with respectively Vprog = 2, 4.5 and 8V (6 of them were initially shorted or broken during the forming operation). The corresponding I-V characteristics obtained for the 50 devices are shown in figure IV.15.a-c. The distributions for resistances extracted at 0.3V have also been reported on figure IV.15.d. Despite few errors (probably resulting from an incomplete forming process), we can observe distinguishable distributions for the three different states (HRS, MRS, LRS). These preliminary results, obtained without any feedback control or specific programming scheme are very promising for potential multilevel operation 17 .

IV.2.5 Pulse programming & Endurance

Specific pulsed programming schemes are specifically suggested to improve the endurance of the memory cells. Indeed, pulses with adapted amplitude and width could enable simple programming, for cells switching as well as reduced electrical stress applied to the devices. 17 Moreover, we can state that in practical applications, feedback control and correction algorithms could be implemented in order to optimize or correct the current level distribution. In theses devices, the voltage-controlled programming, the stable data-retention and large on-off ratio associated with adaptive programming schemes could potentially enable highly multilevel memory devices.

Pulsed programming of organic resistive devices has been demonstrated severally in the literature [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF][START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] , however the influence of pulse amplitude and length has neither been investigated nor commented. We report here preliminary results in order to bring a global overview upon these aspects.

IV.2.5.a Pulse Amplitude

In the case of programming with DC I-V sequences, we have previously shown that resistive switching occurs within the NDR region. Once programmed in a certain resistive state, the applied voltage should be increased above the switching voltage to reach again the NDR and enable new programming. Starting from the High Resistive State (HRS), the programming window is limited by this threshold voltage. Indeed, as illustrated on the current-voltage characteristic on figure IV.16a, with a single pulse value of the switching voltage for HRS (VswHRS~ 4V) enables only the programming in the middle of the NDR, leading to a Medium resistive state (MRS). LRS could not be fully reached, thus decreasing the memory window. Nevertheless, the threshold voltage being lower for MRS (VswHRS~ 2.6 V), the use of a second SET pulse as suggested on figure IV.16b allowed the enlarging of the memory window (See cycling characteristic on figure IV.16c), useful for multilevel operation. The RESET operation at higher voltage can be done with a single pulse.

IV.2.5.b Pulse Length

Lowering the pulse length could enable lower write/erase access time but also improve the endurance of cells by reducing the electrical stress applied to the devices. Indeed, in several papers, it has been reported that the switching could occur at hundreds of nanoseconds [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] . However, it has also been reported that such devices are prone to dead times [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF] , a period of time which the devices cannot be reprogrammed, and thus could suffer from large variation in the switching time, with delays in the order of microseconds or seconds [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF][START_REF] Joo | Embossed structure embedded organic memory device[END_REF] .

In order to investigate the practical switching time of our devices, 20 subsequent ERASE/READ/WRITE/READ cycles have been monitored for each pulse length and the average logarithmic current has been calculated. The impact of programming pulse length upon the average current is reported on figure IV.17a-c for the different transitions: (a) SET from HRS to MRS, (b) SET from MRS to LRS and (c) RESET from MRS to HRS. We can observe that operation speed is strongly limited by the SET switching duration with critical switching time, increasing with greater initial resistive state (tHRS->MRS = 25ms > tMRS->LRS = 100µs). On the other hand, the RESET was found to work in the nanosecond to microsecond range. In order to improve endurance ability, one of the critical points in the field of polymer resistive memories, we have selected from our results the most appropriate pulse length ensuring reproducible switching as well as lowest electrical stress upon the device. As presented in figure IV.18, by working at low current level and with the reduction of pulse length we were able to demonstrate endurance of the cell up to 10 5 cycles (128k).

N um ber of W /E C ycles (#)

Current (A)

IV.2.6 Electrode Area Downscaling

Integration of organic devices with standard microelectronics process remains challenging because of the sensitivity of organic layers to conventional etching steps. Up to now, only few works have reported upon the downscaling of the electrode area (see §I.3.5a): For WPF-oxy-F bipolar devices, T.W Kim et Al employed exotic deposition methods [START_REF] Kim | A direct metal transfer method for cross-bar type polymer non-volatile memory applications[END_REF] or "via-hole" bottom electrodes [START_REF] Kim | Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure[END_REF] and in the case of NDR based devices the only available demonstration was provided by Kwan et Al where lift-off process was used for the patterning of the top electrodes down to 4µmx4µm [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] In order to investigate this critical aspect, different devices have been characterized in this work with macro-size and submicron size cells scaling down to 300nm. As illustrated on figure IV.19a-b two different approaches were employed: top electrode scaling with the shadow mask evaporation technique enabling devices ranging from 150µm to 1mm in diameter and bottom electrode scaling with specific base wafers fabricated with buried lines and plug bottom electrodes ranging from 1.8µm to 300nm18 in diameter (see §II.4.3 for fabrication details). I-V characteristics monitored on a cycle with Low and High Resistance-States are presented in figure IV.20 for different devices with macrosize and submicron size electrodes down to 300nm. We can observe that all of these devices exhibit NDR behavior and large memory margin. We also observe a progressive evolution of NDR shape and increase of the memory window. In order to highlight this point, the current levels in LRS and HRS have been extracted and reported upon the area scaling in figure IV.21a. In agreement with observations reported by Kwan et Al on a lower range of areas [START_REF] Kwan | Multi-layer stackable polymer memory devices[END_REF] , these results show that LRS levels are not significantly impacted by scaling whereas a lowering of current levels in HRS is observed when areas are downscaled. The independence of Low Resistive State upon the Area indicates that the mechanism involved in the switching may be filamentary. For downscaling purposes, filamentary mechanisms are particularly interesting since the localization of the switching may suggest that the switching mechanisms could remain functional even in ultra-scaled devices. Finally, we show here that in NDR-PoRRAM the device area scaling down to deep submicron dimensions is favorable to memory window amplitude, increasing the ON/OFF ratio. Since multilevel ability remains active in scaled devices as demonstrated on the 700nm devices figure IV.21b, the scaling could enable higher physical density and also higher information density per cell by increasing the memory window and thus the number of programmable states in the cell.

IV.2.7 Conclusion and Overview on performances

In their review paper Scott et Al suggested a list of performance requirements for the development of polymer resistive memories [START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF] . Among them, several points are still poorly addressed or remain challenging. As reported in Table IV.1, we have investigated in our study several of these aspects in order to provide a clear overview on the global performances of our devices. We have reported high on-off ratio favorable for the multilevel operation. Our study also covers device reproducibility and pulsed programming optimization. From these analyses, we were able to demonstrate here stable and reproducible characteristics and highly improved endurance characteristics.

STATE OF THE ART for NDR based devices

LETI

Characteristics and estimated maturity factor regarding visibility and performance

Typical Best Reported

Memory Windows ++

Ion/Ioff ~10

IV.3 Detailed Characterization for behavioral understanding

The good uniformity in our devices enables us to perform an original in-depth analysis of the multilevel operation. These experiments provide a clear comprehension of the device operation and bring key-elements for the understanding of the physical mechanisms involved.

IV.3.1 Identification of device behavior

The first step in device understanding is a clear identification of the different operation regimes. During the device's electrical history, different quasi-static behaviors or irreversible transitions could be pointed out. These specific behaviors are reported on the schematic in figure IV.22. Initially, the device exhibits a PRISTINE behavior with non-linear quasi-static resistive behavior. Then through the FORMING transition, when the voltage is dropped over a certain voltage (Vforming), we observed the opening of a hysteresis on the I-V characteristics and Negative differential resistance (NDR) behavior on the backward sweep. This quasi-static NDR behavior is stable when voltage is slowly decreased. However, with voltage polarization in NDR and abrupt decrease to 0V, different subsequent low field resistance states could be induced. These multilevel STEADY STATES (SST) are stable until a threshold voltage (Vsw) is reached, then the current abruptly reaches the NDR through the SWITCHING Transition (SWT).

IV.3.2 Quasi-static Forming and Negative Differential Resistance

In paragraph ( §IV1.2b) we have presented that an initial forming voltage was required in order to induce Negative Differential Resistance Behavior on the Current-Voltage characteristic. Such forming operation has been reported for inorganic diodes [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF][START_REF] Thurstans | The electroformed metal-insulator-metal structure: a comprehensive model[END_REF] but has not been clearly commented to our knowledge on organic devices.

IV.3.2.a Impact of forming operation on NDR

In order to study the dynamic of the forming operation and the resulting NDR, a forming cycle consisting in double sweep measurements has been applied, considering different delay times for the measurements at each step of the sweep. These results, reported on figure IV.23a show a poor dependence upon the sweeping speed rather suggesting a quasi-static behavior. On the other hand, the influence of light reported on figure IV.23b also poorly influenced the forming and subsequent NDR behavior. However, as illustrated on figure IV.23c the shape and current levels of the NDR characteristics strongly depend upon the forming voltage.

(a)

0 3 6 9 1 2 1 5 1 0 -1 2 1 0 -1 0 1 0 -8 1 0 -6 1 0 -4 1 0 -2 Current (A) V oltage V g (V )
D e la y 0 m s D e la y 1 0 0 m s D e la y 5 0 0 m s D e la y 1 s (b)

0 3 6 9 12 1 5 1 0 -1 2 1 0 -1 0 10 -8 10 -6 10 -4 10 -2 Current (A) Voltage V g (V) D a rk D a rk D a rk L ig h t O n (c) 0 3 6 9 1 2 1 5 1 8 1 0 -1 2 1 0 -1 0 1 0 -8 1 0 -6 1 0 -4 1 0 -2 Current (A) V o lta g e V g (V ) V F o rm in g = + 1 4 V V F o rm in g = + 1 5 V V F

IV.3.2.b Reproducible Quasi-Static NDR characteristics

In order to investigate the quasi-static stability of the NDR behavior, a series of double sweep measurements have been performed in both polarities over 80 cycles. On these I-V characteristics, reported on figure IV.24, we observed that the NDR behavior is slightly noisy in the bottom of the NDR valley but is very reproducible upon the cycles. We can also point out a slight increase in current for the whole NDR with the electrical stress applied upon the cycles.

IV.3.3 On Multilevel Steady States

IV.3.3.a Resistance programming trough NDR

The relationship between the programming in NDR and the subsequent Steady STates (SST) has been statistically investigated here. According to the schematic presented in inset on figure I.25, the device has been programmed with DC sweep sequences abruptly stopped in the NDR region at various programming voltages (VPndr). After programming, the subsequent resistance is monitored with a READ sequence at low field [0 500mv]. For each programming voltage, four Program/Read cycles are measured in order to provide information on the reproducibility. The subsequent low-field resistances obtained upon the programming voltage are reported on figure IV.25. We can observe here a monotone trend giving access to a full range of low-field resistances ranging from 200Ω to 10 MΩ strictly controlled by the value of VPndr. Moreover, concerning the lower range of resistances (200 Ω -1MΩ), we highlight a quasilinear trend with very good control and reproducibility of the programmed states. However, for high resistive states, the programming dynamic starts to saturate and the reproducibility of programmed state becomes less accurate. This experiment clearly highlights the direct, monotone and accurate link between the programming voltage and the resistance observed on subsequent sweeps at low field.

IV.3.3.b Conduction Characteristics for Steady States

Based on I-V characterizations, different laws have been suggested in the literature to model the conduction in the multilevel steady states. Historically, in electroformed diodes where NDR and memory effect have been particularly studied [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF][START_REF] Thurstans | The electroformed metal-insulator-metal structure: a comprehensive model[END_REF] , the low field multilevel states have been described with the following law: It was found that all the different resistances displayed at low field could be fitted with such a law, considering parameters that depend only upon the programming voltage and less upon temperature [START_REF] Thurstans | The electroformed metal-insulator-metal structure: a comprehensive model[END_REF] . Despite the fact that such fitting was found to be relevant upon the experimental data, physical based expressions have also been suggested. In the conduction analysis reported by Park et Al, it has been observed that the low field steady states correlate well with Space Charge Limited Current (SCLC) that is a typical current conduction mechanism in organic materials [START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF][START_REF] Petty | Molecular Electronics from principles to practice[END_REF] . The SCLC described the evolution of current density when the amount of injected charge overcomes the amount of intrinsic charge. It has been demonstrated that in presence of traps this injection current could be approximated with the Mott-Gurney law [START_REF] Bartnikas | Electrical properties of solid insulating materials[END_REF] as follows: At very low voltages (from 0 to 250 mV) we observe that the current follows an Ohmic Law (as observed at low field in SCLC conduction model where current is driven by intrinsic carriers). However, above 250mv and below the switching voltage (Vsw~2-4V) we found that the current evolution is not anymore linear and can be fitted with a power law of the voltage as following: In this expression, β and α are two parameters that characterize the conduction of the steady state. The parameter α has been extracted on a large range of I-V sequences, considering different initial resistive states, reported on figure I.26b. We observe here that the programming in NDR does not only modulate the range of resistances (~1/β) but also progressively changes the conduction mode with a parameter α depending upon the level of the programmed state. Indeed, we observe a voltage dependency ranging from a quasi-ohmic behavior in the case of Low resistive State (LRS) to a power law with coefficients higher than two for the High resistive state (HRS).

) sinh( V k K I ⋅ ⋅ =
3 2 0 d V 8 9 ⋅ ⋅ ⋅ ⋅ = θ µ ε J (4.2) J,
In conclusion, these observations point out here that the programming process in NDR does not only change the resistance of the cell but also impacts the conduction mechanisms. Moreover this change in conduction mechanism is not a binary (like switching between two different states) but displays rather a continuous range of states resulting from an equilibrium forced at a certain programming voltage.

IV.3.3.c Common conduction characteristic for NDR and Steady State

In order to go further in the understanding of the relationship linking the NDR and the steady state (SST), we have plotted on figure I.27 the experimental I-Vs for three different resistive states and their NDR characteristics. The Low, Medium and High resistive states have been fitted with the power law from (Eq. IV.3). On this chart, we can point out that the set programming conditions (I&V) and the subsequent programmed state are located on common power law characteristics. Finally, these observations, allow to clearly conclude upon the direct link between the NDR and the current levels programmed in SST region. It has been established here that the polarization in NDR forces a conduction mode well described by the (Eq IV.3) and characterized by two parameters (α, β) depending upon programmed polarization in the NDR.

-111-After programming in NDR and abrupt release of polarization, this conduction mode is frozen and remains fixed at low fields below the threshold voltage.

IV.3.4 Details of switching transitions

The switching transition is also investigated. This irreversible transition characterizes the transition from stable steady states to NDR region.

IV.3.4.a Dynamic dependence

The first question to answer regarding the threshold voltage is about the dependence upon the measurement methodologies. Indeed, for instance in threshold voltages observed for RRAM memories it has been reported that the ramp speed used for the device polarization can have a strong impact upon the value of the measured threshold voltage [START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF] . Usually, for dynamic dependent threshold voltages higher stress time induces lower switching voltages [START_REF] Park | Effects of Switching Parameters on Resistive Switching Behaviors of Polycrystalline SrZrO3:Cr-Based Metal-Oxide-Metal Structures[END_REF][START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF] . In order to study the dynamic dependence of the switching voltage in our devices, measurements for different I-V ramp speeds ranging from 0.005V/s to 2.5V/s have been performed. As displayed on figure I.28a, each series of measurements consists in five subsequent I-V sweeps, starting from the High Resistive State, a switch in the NDR, and reprogramming in the High resistive state by stopping the measurements at 7V. The extracted switching voltages have been reported upon sweep speeds in figure I.28b. We can observe that the switching voltage is stable over three decades, even with long stress time and can thus be considered in our DC experiments as being intrinsic with respect to the cell characteristic.

IV.3.4.b Dependence upon the initial resistance

However, on the multilevel characteristics reported in figure IV.29a, where I-V characteristics for different initial resistive states are plotted, we can observe a large variation of the switching voltage. In order to characterize this dependency, switching voltages have been extracted and reported in figure IV.29b for a full set of resistive states ranging from 200Ω to 10 MΩ. Once again we can observe here a progressive evolution of this parameter upon the initial resistance (itself function of the programming voltage). Greater is the initial resistance greater is the switching voltage. This trend is not linear and the voltage variation is increased for the highest resistive states.

IV.3.5 Quasi-static description of device operation

IV.3.5.a Hypothesis for conduction modeling

The observations brought by the electrical characterizations presented in ( §IV.3) and ( §IV.4) provide a clear overview of the device behavior. Based on these results, we can raise simplified hypothesis to describe the quasi-static behavior of the devices: Hypothesis (i) Below a certain threshold voltage, called the switching voltage, Vsw, the system is stable and follows a conduction model described by equation (Eq. 4.3):

α β V ⋅ = I
where the conduction parameters (α,β)SST have been fixed by the previous programming voltage applied in the NDR (VPNDR).

Hypothesis (iii):

Resulting from hypothesis (i) and (ii) we should consider that above the threshold voltage (Vsw) the conduction mode is described by equation (Eq. 4.3), but conduction parameters change according to the applied voltage. By increasing the voltage bias, β is found to strongly decrease and α slightly increase (data collected on SST see ( §IV.4.3a-b) giving rise to the observed negative differential resistances. According to the hypotheses of conduction in the device, a simple quasi-static behavioral system could be suggested to describe the device operation. The different parameters and functions taken into account are presented on the schematic displayed in figure IV.30. This system considers that:

In the NDR or SST regimes, the Current in the device always results from the conduction model described by equation (Eq. 4.3) and can be calculated from the voltage applied (V) and conduction parameters (α,β),

The conduction parameters (α,β) depend upon the programming voltage (VPROG), If the device is polarized in the NDR region (V>Vsw), the programming voltage is the one currently applied (VPROG=V), If the device is in SST region (V<Vsw) the conduction mode is frozen and the considered programming voltage is the last one applied in the NDR., When the device is polarized in the NDR, and the voltage abruptly decreased, the system does not have time to follow the rapid evolution (low frequency filter) and conduction mode get frozen.

IV.3.5.c Implementation in SPICE and Simulation Results

For practical implementation of the simple behavioral system suggested in the schematic reported on figure IV.30, we have to differentiate the functions required by the system. These functions are illustrated in a second schematic on figure IV.31. In order to implement such a system in the SPICE electrical simulator, the required functions are presented and their equivalence in terms of electrical elements are listed below and illustrated on figure IV.32: Calculation and Translation: The calculation of the current and intermediate results, as well as implementation of the dependency between the different parameters could be implemented in SPICE with voltage controlled current sources (G element) and controlled current and voltage sources (see E elements). This function is illustrated in figure IV.32a where the relationship α(VPROG) is implemented with the E elements (the translation law is fixed by the polynomial coefficient of the E elements).

V PROG R 0 (V PROG ) α(R 0 ) Vsw(R 0 ) β =V 0 (1-α) /R 0 I= β.V α V V>Vsw SWITCHING INPUT OUTPUT STORAGE CALCULATION (conduction law) TRANSLATION (experimental dependence) V PROG R 0 (V PROG ) α(R 0 ) Vsw(R 0 ) β =V 0 (1-α) /R 0 I= β.V α V V>Vsw

Storage:

The Storage of the Programming voltage is implemented with a simple Capacitor Cell (see figure IV.32b) when the device is in the NDR region, the voltage applied to the device directly controls the charge and discharge of the capacitor. When disconnected this ideal capacitor keeps the voltage constant.

Switching: Switching at a certain threshold (Vsw) between NDR operation where the programming voltage corresponds to the voltage applied to the device and the SST operation where the programming voltage corresponds to the memorized value of the previously programmed voltage applied in NDR, could be implemented in SPICE with a voltage controlled switch (S element). On the sub-circuit presented on figure IV.32c, the element S closes the switch and applied input voltage on the capacitor and thus sets the value of VPROG with the current voltage value. The switch is closed when V>Vsw. (indeed the threshold voltage of S1 is 1V and the input voltage corresponds to the output of E5 equal to the voltage ratio V/ Vsw) With the basic assumptions made in paragraph ( §IV.4.4a, §IV.4.4b) and calibration obtained from experimental characterization (R0(VPROG),α(R0) and Vsw(R0) presented respectively in ( §IV.4.3) and ( §IV.3.4)) an equivalent quasi-static electrical system has been simulated with a SPICE equivalent circuit (See Appendix IV.A for details on Schematic).

The I-V single sweep stopping at different voltages employed for the experimental characterization of multilevel ability have been simulated with a temporal signal consisting in a series of ramps with different maximum voltages followed by an abrupt decrease to 0V (in 100ns) 19 . The current obtained on the transient characteristic has been plotted with respect to the voltage and the simulated results are reported on figure IV.33b. 19 From the quasi-static point of view (current level on stable voltage), the current level programmed with pulse stream stimulus (squared signal in entry) were also in agreements with experiments (data not presented here). These results are in good agreement with the experimental data reported in figure IV.33a, and confirm the validity of the hypothesis stated in ( §IV.3.5a, §IV.3.5b), considering a unique conduction model based on (Eq. 4.3) for the device.

IV.3.6 Conclusions and Perspectives

The detailed analysis of the device operation has been presented here and provides clear comprehension of the device behavior as well as clues for the mechanism understanding. Indeed we have reported several interesting dependences upon the relationship between NDR and programmable SST. We have demonstrated that both NDR and SST currents could be described with a common law (I=β.V α ), (α,β) depending upon the programming voltage. For physical understanding, these elements have now to be considered in a progressive filamentary conduction mode emphasized in ( §IV.2.6). The quasi-static characterization of switching transitions presented here with specific dependence of switching voltage upon initial resistance and the elements brought in ( §IV.2.5) upon the dynamic of SET and RESET operation are also clues for future mechanisms discrimination.

IV.4 Conclusions of Chapter IV

In the first section of this chapter ( §IV.1), we have presented the electrical characterization of (PMMA:C60) layers in Metal-Organic-Metal (M-O-M) resistive devices made of platinum inert electrodes. We observed that (C60) doping enhanced the conduction in the layer but does not provide hysteresis or Negative Differential Resistance ability as reported in the literature for comparable compositions ((PS:C60) [START_REF] Majumdar | Fullerene-based bistable devices and associated negative differential resistance effect[END_REF] , (PS:PCBM-C60) [Baral08] or (PI:PCBM-C60) [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] ). We have also studied the impact of thermal annealing upon the electrical behavior of the devices. Higher Current level and Lower breakdown voltages were pointed out for all the doped samples (ρ=2, 5, 10,20wt %) after the thermal annealing. Moreover, in specific voltage conditions it was found that the highly doped devices, (ρ=10,20wt %) thermally treated at 180°C during 30min can exhibit hysteresis and subsequent Negative Differential Resistance (NDR) behavior. The preliminary characterizations have demonstrated that the observed NDR effects are particularly reproducible, stable and symmetric in our samples.

Then, in the second section ( §IV.2), we have studied the memory potential of the devices identified for their NDR ability. Focused on devices made of (PMMA:C60) with ρ=10wt%, thermally annealed at 180°C for 30min, we have benchmarked the main aspects of performance required for memory application. We have first demonstrated unipolar multilevel ability with high on-off ratio (10 6-9 ) favorable for multi-bit memory application. The good reproducibility in device behavior from cycle to cycle and the acceptable variability at the wafer level has been illustrated with the preliminary statistical analysis. We have also particularly investigated the ability for pulsed programming. We have suggested double pulse application schemes to compensate the lowering of memory windows induced in pulse programming and provided a detailed and statistical study upon pulse length efficiency. We pointed out limitation in SET operation with critical pulse length in the order of 100µs to 25ms whereas RESET could be done in hundreds of nanoseconds. Whereas endurance remains a limitation for organic memory development, our study has enabled the choice of adapted programming pulses providing endurance up to more than 10 5 cycles. Finally, the downscaling of memory cells has been also addressed and the impact of scaling upon deep sub-micron organic MIM devices (down to 300 nm) exhibiting NDR operation have been presented for the first time. We highlighted filamentary mechanisms and show that area scaling improves memory margin (> 2 decades).

The last section ( §IV.3) has been dedicated to the detailed characterization and deep analysis of multilevel memory operation. After a clear identification of the different operation regimes we have highlighted the quasi-static behavior of the Negative Differential Resistance (NDR) region and presented statistical results demonstrating a full continuous range of programmable Steady States (SST). We also demonstrated that both NDR and SST currents could be described with a common law (I=β.V α ). Regarding the switching transition, we have shown that this critical voltage was poorly dependent upon ramp speed within the studied range, but strongly depends upon the initial resistance state. Based on these observations, a simple quasi-static behavioral model has been simulated confirming the validity of a simple conduction model and considerations in device operation. Finally, the original dependencies collected here enabled a clear comprehension of the device operation and provided clues for further mechanism understanding Chapter V

V Study of Bipolar Resistive Memory Effects in (PMMA:C60) using oxidizable Electrodes

In the literature, the role of the interfacial oxide has been raised several times to be the driver of resistive switching ability whereas the organic layer could play only a minor role. In order to clarify this point, we investigated in this chapter the electrical behavior of resistive devices made of (PMMA:C60) organic layers and oxidizable aluminum electrodes.

In the first section, by comparing the I-V characteristics with a reference structure consisting of an inert bottom electrode, we were able to demonstrate that the bottom interfacial oxide could induce a bipolar hysteresis in (PMMA:C60) based devices.

In the second section, we provided through detailed characterizations a preliminary study on this bipolar resistive memory effect. Device operation with WRITE, READ and ERASE mechanisms is presented and the influence of electrical conditions (voltage and time) upon the characteristics is also investigated.

To further determine the role of organic compositions and identify the possible mechanism involved, the impact of device geometries factors such as electrode area and organic layer thickness upon the hysteresis characteristics have been also studied and presented in the third section.

Finally, in the last section we sum-up the full set of experimental results collected for the device understanding and discussed some of these points regarding possible operation mechanisms.

V.1 Bipolar resistive switching in (PMMA:C 60 ) with oxidizable bottom electrode

V.1.1 Device structures for the study of the impact of the interfacial oxide

In this Chapter we investigate the electrical behavior of (PMMA: C60) nano-composites in Metal -Organic -Metal (M-O-M) structures with Aluminum electrodes 20 . The organic layer processing and especially baking steps would result in the formation of an interfacial oxide at the bottom electrode interface. This native oxide has been clearly evidenced with TEM pictures and XPS analysis in resistive structures incorporating Polyimide polymer and fullerene derivatives PCBM molecules between aluminum electrodes [START_REF] Cho | Rewritable Switching of One Diode-One Resistor Nonvolatile Organic Memory Devices[END_REF] . A native oxide is also formed at the interface of the top electrode processed by thermal evaporation; however, the process under dry condition should result in much thinner oxides. Consequently, the exact structure considered for this study is illustrated on figure V.1 and described as

Metal-thin insulator-Organic-Insulator-Metal (M-i-O-I-M).

As previously reported in the paragraph ( § I.3.2.D), few papers suggested that enhancing the formation of the bottom interfacial oxide layer could be indispensable for electrical switching [START_REF] Cölle | Switching and filamentary conduction in non-volatile organic memories[END_REF][START_REF] Yook | Transparent organic bistable memory device with pure organic active material and Al/indium tin oxide electrode[END_REF] or could improve the memory characteristics [Verbakel07, ChoB10]. It has been also suggested that switching could finally occur in the interfacial oxide, whereas organic layers act only as a conduction layer [START_REF] Heremans | Polymer and Organic Nonvolatile Memory Devices[END_REF] . In our experiments without thermal annealing above Tg and with inert electrodes, we have observed and reported in chapter IV that (PMMA:C60) could indeed exhibit a non linear resistive behavior without any significant hysteresis. In order to investigate the potential role of native oxide in that configuration, (PMMA:C60) nano-composite layers with annealing below the glass transition have been electrically characterized with oxidizable (Aluminum) top electrodes and both inert (Platinum) and oxidizable (Aluminum) bottom electrodes. All of the tested configurations are summarized below in the Table V

V.1.2 Resistive behavior with inert bottom electrode

Since the processing conditions for these experiments are slightly different from chapter IV21 and in order to definitively exclude the role of top oxidizable electrode in any switching characteristics, samples with top aluminum electrode and platinum bottom electrodes (M-i-O-M structures) have been first characterized here as reference devices.

A memory effect is evidenced when resistive switching is observed in the current characteristic. In order to investigate if devices present memory effects or not, a full set of I-V plots have been measured on several samples. Unipolar and bipolar voltage sequences (forward and reverse sweeps) have been applied to the devices until breakdown. The results obtained for a highly doped sample (PMMA:C60 with ρ=10wt%) are reported on figure V.2a-c. No significant hysteresis was observed when increasing the voltage or alternating the polarity. On the other hand, the current behavior has been monitored at positive voltages for devices with different doping conditions (ρ=0,5 and 10wt%) and reported on figure V.2d. The results point out the role of C60 in the conduction enhancement (three order of magnitude higher with ρ = 10 wt%). In conclusion, for the reference devices made of Aluminum top electrode and platinum bottom electrode, the electrical screening confirms here a conductive behavior of (PMMA:C60) layers without any observable memory effect. Moreover, the conduction level is ruled out by the (C60) loading rate.

V.1.3 Bipolar Hysteresis with oxidizable bottom electrode (MiOIM)

The same electrical screening methodology has been applied on equivalent samples with aluminum oxidizable bottom electrode (M-i-O-I-M structures). Whereas no hysteresis could be observed in the case of unipolar sequences (data not shown here), we observed on the sample doped with 10wt% of (C60) the presence of resistive hysteresis under bipolar sequences.

V.1.3.a Current hysteresis induced by bipolar sequences

The details on the bipolar hysteresis observed in doped samples (PMMA:C60; ρ=10wt%) in the presence of aluminum bottom electrode is highlighted below with the alternation of appropriate sequences in the range [0V +/-15V]. The sequences applied and corresponding observed behavior are reported on figure V.3 and discussed below: Sweeps 0-1: We monitored here the pristine state of the device under a positive voltage and observed its reproducibility under subsequent positive sequences (see figure V.3a sequences pristine [00] and positive after pristine [P0]).

Sweeps 2-3: However, in negative voltage range, the current level is much higher. This behavior is also reproducible under subsequent negative sequences (see figure V.3b sequences "Negative after Positive"-[NP] and "Negative after Negative"-[NN]). -126-

By repeating the alternation of sequences [NP]-[PN]-[PP]

with subsequent sweeps 7-8-9 we observed a similar hysteresis cycle with two different current behaviors in positive region (see figure V.3e sequences [PN] and [PP]). In conclusion, with the considered sequences, we have clearly evidenced here that the alternation of polarizations from positive to negative induced reproducible hysteresis in the current behavior and in the positive region

Negative Resistive State (n-RS):

In Negative region, the current level is much higher. Its behavior seems independent from the previous polarization since a common current conduction is observed for both sweeps "Negative after Positive"-NP or "Negative after Negative"-NN.

Positive Low Resistive State (p-LRS) with NDR behavior:

This state characterizes the device behavior after alternating the polarization from negative toward positive voltages ("Positive after Negative"-PN sequence).

Positive High Resistive State (p-HRS):

This state characterizes the device behavior for any positive sweep following a positive sequence ("Positive after Positive"-PP sequence).

For comparison purposes, we have also introduced some characteristic parameters as suggested in figure V.4b. First of all, regarding the current levels at high field we can clearly point out the asymmetry in M-i-O-I-M structures also induced a strong dissymmetry in the conduction upon the considered polarity: Indeed, for VHigh-F= + /-15V, the current in negative region (n-RS) is more than two orders of magnitude higher than in positive range for both p-HRS and p-LRS. On the other hand, we observe at low field, below the maximum current peak voltage (VMAX), that the current for negative resistive state (n-RS) and positive low resistive state (p-LRS) have similar behavior (in terms of trend and amplitude). However, in positive low resistive state, when the voltage is dropped above a characteristic voltage (VMAX), the current decrease with negative differential resistance behavior (NDR) until it reaches the positive High Resistive State (p-HRS) current level. In other words, the negative polarization seems to set-up here a type of conduction mode that remains active in positive region at low Field. Then, by increasing the voltage above a characteristic voltage VMAX the current progressively decreases with NDR behavior and switches back towards a stable positive lower current behavior.

In conclusion, such device clearly exhibits dissymmetric electrical behavior. However, the current levels are not only dependent upon the polarity, but also upon the history with two distinct available states in the positive region (p-LRS and p-HRS). Consequently, these devices are potentially suitable for non-volatile resistive memory applications.

V.1.4 Impacts of C60 doping concentration on Hysteresis windows

In order to understand the role of the nano-composite upon this bipolar resistive memory effect, we have analyzed the impact of doping ratio in the different devices presented on figure V.5 with organic layer including ρ = 0 (ie pure PMMA) , 5 and 10 wt % of C60. Considering that (C60) doping has a minor impact on film thickness (see § II.2.1.B), the devices are compared here under identical electrical conditions with [0V +/-15V] sequences. On the bipolar characteristics for two subsequent cycles reported on figure V.5, we can observe that (C60) doping has three major effects on the electrical behavior:

Enhanced conduction: First, by increasing (C60) doping, we could observe that current levels are increased in both polarities. This results is in agreement with the observations reported in the case of (PMMA:C60) layers with inert bottom electrode, Enhance dissymmetry: On the other hand, when symmetric insulating characteristics could be observed in a reference device (without C60 ~ ie ρ=0 wt %), a dissymmetry is slightly visible on 5% doped samples and widely enhanced for doping up to 10 wt%, Induce and modulate the hysteresis windows: linked to the dissymmetry we also observe an opening of hysteresis when increasing the doping ratio. When no memory effect could be observed on reference devices, a small hysteresis (ION/IOFF ~ 1.7) is visible for 5wt% doped samples and wider windows are observed when doping is increased up to 10wt% (ION/IOFF ~ 10). The characteristic voltage VMAX related to the shape of NDR is also impacted and decreases with the doping ratio. We extracted respectively VMAX=7V and VMAX = 3V for 5% and 10 w% doped devices.

In conclusion, this experiment highlights the functional role of the (C60) in the device characteristics. The (C60) doping of PMMA enables a memory effect where the current level under positive voltage could be modulated depending upon the previously applied polarization previously. Moreover, the amount of (C60) directly controls the shape and the intrinsic characteristics of the hysteresis windows (VMAX, ION/IOFF).

V.1.5 Conclusions on the Impact of oxidizable bottom electrode

In conclusion, we have observed in these experiments that thermally annealed (PMMA:C60) layers below the glass transition, exhibited only a resistive behavior in presence of inert bottom electrodes. The conduction in the devices is modulated by the fullerene loading rate.

On the other hand, in presence of Aluminum oxidizable bottom electrodes, we were able to demonstrate the presence of bipolar hysteresis enabled and controlled by the (C60) doping. Indeed, if no hysteresis could be observed in absence of fullerenes, a bipolar hysteresis is enabled and enhanced by the fullerene inclusion. On the doped samples, the I-V electrical behaviors are characterized by a strong dissymmetry in current level depending upon their polarity. Moreover, we observed that negative polarization induced a current hysteresis in the positive voltage region. This hysteresis is associated with the presence of negative differential resistance behavior that seems to result from a progressive transient characteristic between two different available conductions modes.

V.2 Detailed characterization in bipolar memory operation

In the previous section, the ability of the cells toward bipolar hysteresis behavior has been presented by alternating the polarity in fixed electrical conditions ([0V +/-15V]). This effect was found to be reproducible and could thus potentially be employed for memory applications. In order to deeply understand the electrical operation of the device and collect some information for mechanisms discrimination we are studying separately in this section the influence of the different electrical conditions on the memory cell behavior and its characteristics.

V.2.1 Non Volatile Resistive Memory Operation

We have presented before that the devices could be cycled between three different resistive states (RS): negative-RS (n-RS), positive Low RS (p-LRS) and positive High RS (p-HRS). This ability to display ambivalent current levels in positive region and the reproducibility cycle to cycle of this behavior make such a device potentially suitable for non-volatile memory application. Indeed, as presented on figure V.6, to the sequences involved in the hysteresis presented on fig V.1e (NP, PN and PP) we could associate the basic memory operation: WRITE/READ/ERASE.

Voltage (V) Current (A)

V.2.2 READ-ERASE -Influence of Positive sequences on hysteresis

After a negative programming, the current level in positive region first follows a Low Resistive State (p-LRS) behavior and then reaches a stable High Resistive State (p-HRS) with lower current level. Thus, during this transition the positive sequence [0V, +15V] serves both as "READ" and then as "ERASE" operation. In order to clearly identify the range of voltage considered for these operations and their boundaries, we have studied here the influence of variable Read Disturbance sequences before the full Read-Erase (R-E). The scheme of this experiment is described on figure V.7a: after a programming sequence ([0V -15V]), a variable disturb sequence is applied ([0V→ VRD]) and its influence is monitored on the subsequent positive sweep ([0V→10V]). The influence of the Read disturb sequence is clearly visible on figure V.7b: compared to reference curves (with VRD = 0 V), the current level in the second Read sequence (R-E) is progressively decreased if the maximum voltage of Read Disturb sequence is increased (VRD). The extractions of current at 1 V after programming and after first Read are reported on figure V.7c. We can observe that a single read at voltages as low as 1V already decrease the current level on second reading leading to a closure of -12% of the hysteresis windows. When the voltage is dropped above the current peak (VMAX) the hysteresis window is strongly impacted (ie closure of -50% at 4V) and above 10 V the cells could be considered as Erased (closure of -90% at 10V). A complete read disturb and erase study would also require taking into account the influence of stress time with pulse-programmed experiments. Nevertheless, with this simple experiment, we clearly highlight here the disturbance of Read process on the memory windows in the case of DC sweep operation and demonstrate the Erasing process of the cell above 10V (regarding -15V programming conditions). Region III -High Field [-12.5V;-27.5V] -Increase of post-peak current. Below -15V the trend in the post-peak region is reversed and the current is now increased when increasing the programming voltage. The current in the sub-peak region and at the peak voltage is also very slightly increased (see figure V.8c).

-30V -Breakdown (not shown here): After -30V sequence the device was found to be shorted.

-132-Concerning the understanding of negative polarization impact, we observe here a complex programming scheme where the writing sequence does not induce a direct transition from one state to the other (binary switching) nor modulate the current level in a progressive trend, but influences the shape of the I-V characteristic upon different ranges (sub/post -peak) depending upon the programming voltage. Moreover, these experiments bring two conclusions on device operation:

1. First we observe that the current peak and its corresponding voltage VMAX seems to be an intrinsic characteristic of the cell and poorly depends on programming considerations (despite a very slight evolution could be observed on the current peak voltage value when increasing the programming voltage).

2. Secondly we observe saturation in p-LRS current enhancement around (Vw ~ -15V). Above this voltage the enhancement of post-peak current induce a lowering of negative differential resistance dynamics and will thus result in an enhancement of the p-HRS current and consequently decrease of the hysteresis windows (ION/IOFF = Ip-LRS/Ip-HRS).

V.2.3.b Influence of Programming Time

We have also experimented the time-dynamic of this WRITING process. According to the schematic picture in figureV.9a, this study was carried out with Vw=-15V as writing voltage and different pulses length ranging from 500µs to 5s. The effect of stress time is monitored on the subsequent positive sweep (Read-Erase sequence). The time dependence of the writing process (with VW -15V) could be clearly observed on figureV.9b where the different Read-Erase characteristics after programming are stacked. Once again we observe only a slight evolution of the maximum current peak voltage (VMAX). The extraction of current level at the peak has been also extracted and reported upon the stress time applied on figureV.10. This experiment point out that the mechanism involved in the switching with -15V write is relatively slow with a time constant on the order of millisecond to second. Practically, in order to obtain a memory margin superior to a factor of 10, pulses longer than 50ms are required.

Write (W)

Voltage stress [-15

V; W W s] (W w = 500µs; 5ms; … 5s) Read/Erase (R/E) [0V 15V] Write (W) Voltage stress [-15 V; W W s] (W w = 500µs; 5ms; … 5s) Read/Erase (R/E) [0V 15V]

V.2.4 Conclusions on device operation

In this section we have demonstrated that M-i-O-I-M devices with C60 doped PMMA layers (ρ=10wt% here) could be potentially employed for resistive memory application. Its WRITE, READ and ERASE operations have been preliminarily investigated. The experiments carried out have provided a global comprehension of device operation and highlighted several points:

A Destructive Reading-The positive sequences serve both as Read and Erase operations. Even with reading voltage lower than the current peak voltage (VMAX), which seems to characterize the starting of the reset process, we found a significant Read disturb effect.

Complex programming on two different voltage regions -Upon the applied voltage, the negative polarization influences the current in positive region with a non-monotone trend on two different regions (sub and post peak). A characteristic parameter VMAX, independent of the applied voltage, characterizes the boundary between these two different regions.

A limited hysteresis window dynamic -By increasing the programming voltage we found saturation in the positive Low resistive state and a decrease of the negative differential dynamic responsible for the memory window.

Large time constant -The programming operation was found to be a time dependent mechanism that had a relatively high time constant (milliseconds to seconds). For a complete benchmarking of the memory performance, the programming time characteristics for different voltages could be interesting. Time dependant read disturb studies, data-retention, cycling endurance and statistical characteristic's distributions are also required.

V.3 Influence of device structure on characteristics

We have previously presented the basics of electrical characteristics and emphasis to control this bipolar characteristic by the C60 doping ratio in the PMMA layer. In this section we are studying now the impact of the cells geometry (Area, Thickness) on this electrical behavior.

V.3.1 Influence of device Area

The dependence of electrical characteristics upon device area is an interesting characteristic in the field of resistive memory. Indeed, monitoring the dependence of current level upon area could enable to discriminate between filamentary and planar conduction mechanisms. For this purpose, we have fabricated on the same wafer, different devices with a multi-size mask in the range of sizes accessible by shadow evaporation process. Their electrical bipolar characteristics have been monitored under identical electrical conditions [0V +/-15V]: we first monitored initial positive resistive state (p-IRS) and then we measured two subsequent cycles consisting of negative-positive-positive sweeps.

From these results reported in figure V.11a we observe very similar characteristics with a good reproducibility between both cycles. We can also point out that the voltage of the maximum peak voltage (VMAX) and current ratio (between p-LRS and p-HRS) seem constant and do not significantly depend upon the device area. In order to compare the respective current levels, the current and normalized current densities were extracted at +/-1 V24 for the different conduction modes reported upon the device Areas on respectively figure V.11b and figure V.11c. For the four different resistive states, the current level seems to decrease proportionally with the device area and current density is roughly stable. This strong correlation between current and device area excludes monofilamentary conduction hypothesis and rather suggests planar mechanisms.

In conclusion, on the range of fabricated devices, this study clearly emphasizes that the electrical conduction is ruled out by planar mechanisms for pristine, negative and ambivalent positive states. Maximum peak voltage and memory window characteristics are unaffected.

V.3.2 Influence of organic layer thickness

In order to understand the role of the organic layer in the device behavior, we have also investigated the impact of the nano-composite thickness on the electrical characteristics. With different dilution of PMMA in the solvent (PMMA to toluene = 3, 2, 1.5 wt %) we were able to fabricate samples with different thicknesses: ~76 nm; ~40 nm and ~25 nm 25 . The corresponding stacks and their electrical characteristics are presented on figure V.12. In order to compare these different devices, electrical characterization was carried out in several electrical conditions and further compared within the same range of electric fields (~ +/-5MV/cm).

We had previously demonstrated that the maximum peak voltage (VMAX) characterizes a threshold for the progressive transition between two conduction modes. Its values are independent of the device area ( §V.3.2) and are only slightly impacted by the polarization considerations ( §V.2.3). In this experiment, we observed a clear influence of the organic layer thickness (torg) upon this critical voltage with VMAX~ 3V, 7V and 24V for respectively torg~25nm, 40nm and 75 nm.

Vmax = 22 V Current (A) Voltage V g (V)
PMMA @3wt%~75nm -ρ ρ ρ ρ=10wt% n-RS p-LRS p-HRS FIGURE V.12: Schematic of the fabricated devices for nano-composites thickness influence analysis. Different organic layers thicknesses were studied (a) 25 nm (b) 40nm, (c) 75nm. Bipolar I-V characteristics for three devices carried out in the same range of electrical field (~ +/-5MV/cm).

-136-The extracted critical voltages (VMAX) upon the organic layer thickness are reported on figure V.13a. We can observe a nonlinear trend rather fitted with second order polynomial law. Threshold voltages are commonly observed for electric field activated mechanisms such as resistive switching in oxides [waser09]. In the case of purely field-activated phenomena, the corresponding critical field should be constant or slightly affected by the layer thicknesses. For comparison purposes in our experiments, the threshold voltage (VMAX) has been normalized by the organic layer thickness in order to extract the critical Field characterizing the change in conduction mode26 . From this experience, we observe that the critical electric field in our devices reported on figure V.13b is in the range of 1-3 MV/cm with a progressive increase when the thickness is increased respectively FMAX= 1.12, 1.55 and 2.6 MV/cm for respectively ~25nm, 40nm and 75 nm thick nano-composites. Surprisingly, we observe that this critical Field is not constant but seems rather to follow a linear trend null at the origin. These observations indicate a strong correlation of the critical field upon the organic layer thickness.

In order to understand this particular dependence, we can give a simple expression of the normalized field reported by considering a simple structure made of two layers, namely oxide and organic as illustrated on figure V.14. -137-On this system we can write the equations characterizing respectively the distribution of the voltage (Eq. 5.1) and field according to the Gauss equation (Eq. 5.2).

OX ORG TOT V V V + = (5.1) 0 ε ε ε Q F F ORG ORG OX OX = ⋅ - ⋅ (5.2)
Indeed, with these we can express the normalized field considered here as a function of the electrical field in the organic layer:

ORG org OX ox ORG org ox OX org ORG org OX ox ORG org ORG org ox OX org TOT F t t t t Q t V t t t V t t Q t V ⋅ ⋅ ⋅ + + ⋅ ⋅ = ⋅ ⋅ ⋅ + + ⋅ ⋅ = ) 1 1 ( 0 0 ε ε ε ε ε ε ε ε (5.3)
Or express it as function of electric field in the oxide:

OX org ox ORG ox OX org OX ox ORG org ox org OX OX org TOT F t t Q t V t t t V Q t V ⋅ + ⋅ + ⋅ ⋅ = ⋅ ⋅ ⋅ + + ⋅ ⋅ = ) ( 0 0 ε ε ε ε ε ε ε ε (5.4)
We have observed in our experiments the dependence of a critical normalized field expressed as FCRIT= VMAX/torg upon the organic layer thickness. In the hypothesis where this transition occurred when a critical field is reached in the organic layer or in the oxide independently of the layer thickness ( org t ∀ switching occurs when FOX or FORG = F0= constant), the equations (Eq.5.3) and (Eq 5.4) would lead in both cases to a decrease of VMAX/torg with increasing organic layer thickness (torg). However, such a result is not consistent with our experiments and a reverse trend is observed (VMAX/tORG is proportional to tORG).

In conclusion, our experiment concludes here that the phenomenon responsible for the observed change in conduction is not directly activated by a characteristic critical field either in oxide or in organic materials. It could rather result from others factors such as a critical charge density in the volume.

V.4 Discussions and perspectives

In this section, we summarize the results of the experiments carried out on Bipolar Resistive Memory effects in M-i-O-I-M structure with (PMMA:C60) nano-composite and briefly discuss the suitability of classical models suggested in literature.

V.4.1 Experimental conclusions

The Experimental results brought on the material characterization of nano-composites ( §II.3), its bipolar resistive memory ability in presence of oxidizable bottom electrode ( §IV.1), the detailed electrical characterization ( §IV.2) and the device geometry impacts analysis ( §IV.3) are summarized in the table below:

(i)

PMMA:C60 nanocomposite can be considered as a homogenous material where fullerenes are uniformly dispersed.

(ii)

In the case of MOIS structures with bottom interfacial controlled oxide, C-V measurements on (PMMA:C60) have demonstrated electrons injection and trapping ability in negative voltage.

(iii)

In the case of MIM structures with both inert electrodes, I-V measurements on (PMMA:C60) without thermal annealing above Tg exhibited nonlinear resistor behavior.

Bipolar Resistive Memory Effect with inert bottom electrode ( §V.1).

(iv) On reference samples with inert Pt bottom electrodes, nonlinear resistor behavior is observed with a slight dissymmetry at low field (v) Strong electrical dissymmetry with much higher current level in negative voltage is observed with oxidizable bottom electrode (

Negative polarization induces a current hysteresis in the positive region, with Differential Resistance behavior above a critical Voltage (VMAX).

(vii) Positive low resistive state (p-LRS) and negative resistive state (n-RS) are of the same order of current whereas Positive high resistive state (p-HRS) is lower.

(viii) C60 doping enhances the current level, electrical dissymmetry and hysteresis windows.

Details on Electrical Characteristics ( §V.2)

(ix) Positive sequences serve both as Read and Erase operation with strong Read disturb effects.

(x) Existence of critical voltage VMAX characterizing the boundary between both regions and the current behavior.

(xi) Depending on the applied voltage, the negative polarization influences the positive sweep behavior in different ways on two different regions (sub and post peak).

(xii)

The programming operation is a time dependent mechanism with relatively high time constant (milliseconds to seconds).

Geometry impacts ( §V.3) (xiii)

The scaling of device area suggests planar conduction mechanisms for pristine but also negative and both ambivalent positive states.

(xiv) The ION/IOFF ratio is constant with device area scaling.

(xv)

The ION/IOFF ratio is not significantly influenced by organic layer thickness.

(xvi) The bipolar I-V characteristics and its characteristic parameter VMAX scale down in voltage with organic layer thickness lowering.

(xvii) The change in conduction mode (at VMAX beginning of NDR) seems not to be related to any critical field threshold but rather results from others factors such as critical charge density in the volume.

TABLE V.2

List of experimental results and observations collected in section II.6, IV.1, IV.2 and IV.3 regarding bipolar memory effects observed in the presence of a bottom oxidizable electrode.

V.4.2 Discussions

The presence of resistive memory effects is necessarily related to the change in materials or the electrical configuration of the device. We have emphasized in paragraph §V.1.1 that the observed bipolar hysteresis is induced only in presence of oxidizable electrodes and is strongly influenced by the C60 doping ratio of the layer. Regarding such observations, two fundamental hypotheses can be stated:

1. Interfacial oxide provides the switching elements whereas the organic layers only play a role of nonlinear conductor enhanced by (C60) doping, 2. Interfacial oxide modifies the global electrical configuration and disturbs the conduction in the organic materials brought by (C60) or the injection at the interface.

V.4.2.a Switching in the oxide

Metal-oxide layers have been widely reported for their resistive switching ability [START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF][START_REF] Sawa | Resistive switching in transition metal oxides[END_REF] . In such devices, considering not fully stoichiometric oxide layers, it has been suggested that the electric field can induce the motion of oxygen vacancies and thus participate to the formation of conduction paths made of defects that lead to a low resistance conduction path (see Appendix V.B for details).

We have previously reported that the organic layers can exhibit a resistive behavior brought by the (C60) doping (iii-iv). Thus, we can consider the hypothesis where organic layers just act as non-linear conductor. Despite the fact that the nature of interfacial oxides is unknown, we can also suppose that such native oxides result from the degeneracy of pure aluminum to fully oxidize aluminum at the interface due to polymer deposition and backing. Consequently, two specific layers could be considered at the interface: a fully oxidized layer exhibiting high resistance in series with a non-stoichiometric layer presenting low resistance conduction through the inherent defects. In similar bi-layer structures, HP (TiO2/TiOx [Wiliam08] ) and Samsung (Ta2O5/TaOx [START_REF] Lee | A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures[END_REF] ) suggested models based upon the motion of oxygen vacancies in order to explain the bipolar switching. It was claimed that non-stoichiometric layers include availability of oxygen vacancies that could further drift in the device under the presence of an electric field [START_REF] Strukov | The missing memristor found[END_REF] . This motion could locally enhance or decrease the thickness of stoichiometric oxides and thus the resulting resistance. The supposed motion of oxygen vacancies in our device has been reported in the

V.4.2.b Switching of the organic layers

We have indeed reported that (PMMA:C60) acts as non-linear resistor in absence of oxidizable electrodes in the M-i-O-M configuration (iii) but it has also the ability to potentially store charge at negative voltages in the presence of blocking a oxide in the M-O-I-S structure (ii). Despite the fact that the exact nature of interfacial oxides is not known in the case M-i-O-I-M (Aluminum based oxides with unknown stoichiometry and unknown thickness) and is probably not exactly comparable to the blocking oxides considered in M-O-I-S (pure SiO2, 5.5 nm in thickness), we could still consider as hypothesis that both interfacial oxides could play a similar role in the charge trapping ability. Such considerations lead to assume that the electrons are trapped after a negative polarization and released at positive voltage (as observed in MOIS).

However, the link between charge trapping and resistive conductance switching is not trivial. Several arguments could account for the functional role of charge trapping in the conductance switching observed. The time dependent current programming with relatively high time constant (xii) is consistent with the charge trapping kinetic. On the other hand, the evidence of planar conduction switching mechanisms (xiii-xiv) is also in agreement with the planar distribution of charge during the trapping. But according to the analogy between M-O-I-S and M-i-O-I-M we should consider here that trapping occurs at negative voltage (ii) and that the effect on the conduction is supposed to increase the subsequent current (vi) this latter being reduced with NDR behavior when charge is released at positive voltage. Such behavior is not trivial and requires specific hypothesis to be sustained. Indeed, the reverse effect is usually considered: the charge trapping modifying the energy band diagram raises the potential of the conduction band thus decreasing the global conduction.

-142-

V.5 Conclusions of Chapter V

The question of the role of oxidizable electrodes in the resistive switching for organic devices has been raised several times but not clarified yet in most of the devices. However, this point is critical for the understanding and development of organic memories.

On composition with (PMMA:C60) thermally annealed below the Tg, we have demonstrated in the previous chapter that such layers have the ability to trap charge when included in a capacitive memory configuration in Metal-Organic-Insulator-Semiconductor (M-O-I-S) structures. On the other hand, the same organic layers do not show any resistive memory effect in Metal-Organic-Metal (M-O-M) structures with inert electrodes. In this chapter, equivalent organic layers have been studied with oxidizable electrodes. In such a configuration, the formation of interfacial oxide leads to Metal-thin_insulator-Organic-Thick_Insulator-Metal (M-i-O-I-M) structures. In order to exclude the role of the top thin interfacial oxide in resistive memory effects, an intermediate reference sample with top oxidizable electrodes and inert bottom electrodes (M-i-O-M) has been first characterized and has not evidenced any hysteresis behavior. However, by comparing electrical devices with oxidizable (Aluminum) and inert (Platinum) bottom electrodes, leading respectively to M-i-O-I-M and M-i-O-M structures, we have demonstrated that the bottom interfacial oxide could play a functional role in device behavior by enabling bipolar resistive memory effects, whereas nonlinear resistor behavior was observed with inert electrodes. This hysteresis characteristic was also found to be strongly influenced by the C60 doping ratio.

Then, through detailed characterization, we have demonstrated that such a device could be potentially used for resistive memory applications, and its WRITE, READ and ERASE operations have been preliminarily investigated. Despite the fact that a full performance benchmark is still required, including data-retention, endurance and statistical distribution, we have reported in the studied configuration that the preliminary results highlight a low current (<nA) and current ratio (~10), strong read disturb effects and programming time in the order of millisecond to second. In order to bring the elements of the discussion on possible involved mechanisms, the impacts of device geometry have also been studied. We have shown that the influence of electrode area clearly supports planar mechanisms in the resistive switching. On the other hand, the study with different organic layer thicknesses pointed out that the reset operation was not linked to a critical field but should rather result from other considerations such as critical charge density.

In conclusion, we have clearly demonstrated that the interfacial oxide resulting from the integration of organic layers on oxidizable electrodes could play a functional role by enabling memory effects in the devices, and provided here a list of observations for future mechanism discrimination.

APPENDIX V.A: ORGANIC LAYERS THICKNESSES

For studies on the influence of organic layer thickness, nano-composite solutions with various solvent concentrations have been fabricated with different ratio PMMA to toluene = 4, 3, 2, 1.5 wt %.The corresponding thicknesses have been measured with ellispometry and also extracted through capacitive measurements in Metal-Organic-Insulator-Semiconductor (M-O-I-S) structure. These thicknesses extractions methods have been controlled and calibrated with direct measurements on TEM pictures. These TEM pictures in the case of PMMA with 2, 3, 4 wt% are reported on figure V.A.1. First we consider that oxygen vacancies' motion is only dictated by the drift in a uniform electric field with a average ion mobility (µvo). Consequently according to the schematic reported on figure V.B.1 we can express the motion of oxygen vacancies function of the electric field applied in the doped region (tank for oxygen vacancies) as followed.

DOP VO F ⋅ = ′ µ (t) w with ) ( t w V F DOP DOP =
(5.5) Considering now a simple ohmic conduction in a bilayer structure with two different intrinsic resistances as illustrated on the schematic, we can express the voltage drop in the doped region function of the total voltage and resistances

ON DOP R D t w t ⋅ = ) ( ) ( R ) ( ) ( ) ( t V t R t R V TOT DOP DOP ⋅ = with 0 TOT ) ( ) ( ) ( R R t R t R t UNDOP DOP + + = OFF UNDOP R D t w t ⋅       - = ) ( 1 ) ( R (5.6)
By inserting these results in equation 5.5 we obtain:

) ( ) ( 1 ) ( (t) w 0 t V R R D t w R D t w R D OFF ON ON VO ⋅ + ⋅       - + ⋅ = ′ µ (5.7)

General Conclusions

The results presented in this thesis work have clearly demonstrated several types of memory effects with (PMMA:C60) organic nano-composites in different dedicated structures. Thus, in capacitive devices, we have demonstrated the trapping ability and injection enhancement brought by the C60 molecules. The fabricated resistive structures have shown the functional role of oxidizable electrodes in planar bipolar switching, with respect to devices fabricated with inert electrodes. Finally, in resistive cells with platinum electrodes, we emphasized that nanocomposite layers with enhanced aggregation brought by the thermal annealing could be suitable for unipolar multilevel memories. The operation of these different memory devices has been preliminarily investigated in this thesis work. In the case of unipolar multilevel memories, particularly suitable for the crossbar architecture, a complete benchmark and detailed characterizations were performed.

In the first chapter a historic introduction of storage technologies was used to illustrate the requirements and factors responsible for the emerging, success and decline of technologies. This context highlighted the success of Flash memories within the CMOS business model based upon scaling, but also its possible limits regarding the future evolution of electronics. We showed that resistive memories can bring strong advantages in terms of integration simplicity, allowing higher data density and performance, for complementing or replacing Flash memories. In terms of materials, the single molecule approach could be particularly interesting on a long term for scaling towards molecular size. However, integration remains a major challenge. Upon a short term, organic thin films could offer more flexibility for hybridization with microelectronics or for new applications requiring low-cost, large-area, flexible or printed processes. At the convergence of two promising new approaches, organic thin film resistive memories have been reviewed here. We pointed out a large variety of materials and device configurations with promising performance, low-cost integration, high on-off ratio, multilevel capabilities and fast programming times. However, reproducibility and endurance are still poorly addressed in the literature. Physical understanding remains also unclear and several potential mechanisms including the functional role of electrodes and the impact of integration upon the switching behavior were suggested. For our study an all-organic nano-composite of (PMMA:C60) and a transversal approach including material and electrical characterizations in complementary structures have been suggested.

The second chapter was first dedicated to the recipes and experimental processes employed for (PMMA:C60) nano-composite fabrication. Then, through material characterization, we highlighted a homogenous thin film without roughness, thickness variation or evidence of dopant aggregation. With optical and mass spectrometry, we were able to characterize precisely the relative amount of both components in the composite and perform depth profiling, showing a uniform distribution of (C60) in the layer. With E-beam or Nano-Imprint lithography we have demonstrated the patterning capabilities of (PMMA:C60). On the other hand, microscopy analysis emphasized the formation of C60 aggregation in the material with annealing treatments above the glass transition. Finally, we presented the fabrication of test structures for capacitive -148-studies, resistive studies with inert and oxidizable electrodes and advanced structures for electrical scaling studies. An original integration scheme based on direct patterning and encapsulation was also suggested for high-density integration of polymer resistive cells.

In the third chapter, we have studied the electrical behavior of (PMMA:C60) nanocomposites in Metal-Organic-Insulator-Semiconductor (MOIS) capacitive structures. After reminding the basic behavior of Metal-Insulator-Semiconductor (MIS) devices, we presented the Capacitance-Voltage (C-V) characteristics of a reference PMMA only sample. Despite an unexpected inversion behavior, further explained in terms of edge effects with permanent inversion layer phenomenon, we concluded that the PMMA could be considered as a positively charged insulator. With progressive C60 doping of PMMA, we observed a clockwise hysteresis clearly explained in the MOIS structure by the balance of charge injection and storage in accumulation regime brought by C60 molecules.

The fourth chapter is dedicated to the characterization of (PMMA:C60) layers in Metal-Organic-Metal (M-O-M) structures with inert electrodes. A non-linear resistive behavior without memory effect was observed. However, thermal annealing enhanced the current level and exhibited hysteresis and subsequent Negative Differential Resistance (NDR) at specific doping levels and voltage conditions. We demonstrated in these devices unipolar multilevel memory effects with high on-off ratios (10 6-9 ), stable retention, good cycle-to-cycle reproducibility and acceptable variability. A specific pulsed programming scheme was proposed to enlarge the memory window by two decades and a statistical study upon pulse length efficiency was presented, highlighting the SET operation in the order of 100µs to 25ms and RESET in 100ns. Adapted pulsed programming provided endurance up to more than 10 5 cycles. Finally, the downscaling study demonstrated down to 300 nm, highlighted filamentary conduction mechanisms with improved memory margin (> 2 decades). A deep analysis of multilevel operation was reported with original dependencies enabling a clear understanding of the device operation and providing clues regarding the involved mechanisms. The results achieved regarding the quasi-static behavior of the NDR showed that it was possible to obtain a fully continuous range of programmable Steady States (SST) as well as resistance dependent switching voltages. We demonstrated that the NDR and SST currents could be described with a common law (I=β.V α ) and a simple quasi-static behavioral model was proposed.

Finally, in the last chapter, the role of oxidizable electrodes was investigated with unannealed (PMMA:C60) layers. The presence of an interfacial oxide leaded to Metal-thin_insulator-Organic-Thick_Insulator-Metal (M-i-O-I-M) structures. Bottom oxidizable electrodes allowed bipolar resistive memory effects, whereas a nonlinear resistive behavior was observed in the case of inert electrodes. The hysteresis characteristic was also found to be strongly influenced by the C60 doping ratio. The WRITE, READ and ERASE operations associated to this memory effect have been investigated. We reported low current (<nA) and current ratios (~10), strong read disturb effects and programming times in the order of milliseconds to seconds. The impact of device geometry was also presented: the study of electrode area effect pointed out planar mechanisms in the resistive switching and different thicknesses in the obtained organic layers. The obtained results provide a preliminary study presenting a list of observations for future mechanisms discrimination.

Perspectives

Nowadays, research in the field of emerging memories for next CMOS generations, focuses specifically upon nano-PCRAM, RRAM and STT-MRAM that combine promising performance and possible higher compatibility with conventional fabrication processes. On the other hand, the recent growth in the development of organic electronics has also opened new opportunities for polymer resistive memories. However, for the emergence of this technology, two main issues remain to be addressed: TECHNOLOGICAL OPTIMIZATION: For application purposes, the unipolar multilevel memory devices fabricated here seem particularly promising for crossbar architectures. However, several points still need to be addressed. Data-retention during long time scales, as well as stability in temperature, light and humidity are still to be investigated. The reproducibility and endurance remain limiting points for the development of reliable technologies and should be engineered to fit specifications. Absence of forming requirements is also strongly recommended for simple use and the association with diodes is desirable for crossbar applications. Finally, the material and process conditions need to be adapted towards new specifications, application and fabrication flows (materials allowed, flexibility, printability…).

PHYSICAL UNDERSTANDING: Physical understanding is required for the development of technologies in order to model, optimize and prepare future evolutions. Despite the exact physical effects responsible for resistive switching, those observed in this work remain to be determined for both bipolar and unipolar switching. We have brought understanding of device operation and of their intrinsic characteristics. Three new directions are now open towards physical understanding:

Further electrical and physico-chemical characterizations: among the different aspects identified in this thesis work, specific experiments could be carried out in order to complete the current results such as: detailed material characterizations to understand the exact organization in the nanocomposite, temperature measurements to qualify the conduction in the different regimes and further electrical characterizations to complete the understanding of the quasi-static or dynamic behavior. Alternative characterization methods such as Conductive-AFM, STM, should also be considered.

Development of novel test structures:

We have also introduced different test structures for the characterization of non-annealed (PMMA: C60) (M-O-I-S, M-i-O-I-M andM-O-M). This diversification brings complementary conclusions for device understanding. These multiple approaches could be employed for the characterization of thermally treated (PMMA:C60) (only presented here in in M-O-M structure). Other competing structures could also be proposed such as devices incorporating electrons or hole blocking layers.

Screening of the materials influence:

Following the identification of device electrical behavior (eg. current levels and switching voltages upon programming voltage and NDR shape, this latest depending upon the forming voltage), this work provided preliminary results allowing to investigate the effect of electrode material (different work functions or thermodynamic properties), thermal annealing conditions, doping ratios and thicknesses. Further experiments should be conducted with new polymer matrices or other doping entities.

Chapter VI

VI

Résumé en Français

Contexte du travail de thèse

Ces dix dernières années, les technologies de stockage mémoire non-volatiles ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimédia : MP3, Smartphones, clés USB, ordinateurs ultraportables… Afin d'améliorer encore davantage les performances, d'augmenter les capacités et de diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd'hui étudiées pour pouvoir compléter ou remplacer la technologie conventionnelle Flash.

Cités par l'ITRS, les récents travaux sur les mémoires résistives polymères (PoRRAM) présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d'intégration haute densité au dessus des niveaux d'interconnexions CMOS ou sur substrat souple. Plusieurs démonstrations de compositions organiques intégrées dans des structures macroscopiques ont été présentées dans la littérature. Néanmoins plusieurs points critiques pour le développement et la viabilité des technologies mémoires polymères résistives restent encore à adresser. Le fonctionnement détaillé des cellules ainsi que les performances mémoires associées n'ont pas toujours été clairement reportés. De la même façon, le rôle exact de la couche organique au regard des facteurs d'intégration ainsi que les phénomènes physiques associés au fonctionnement des cellules restent incompris. Enfin aucune stratégie n'a été clairement proposée pour l'intégration haute densité des points mémoires organiques.

Présentation du manuscrit de thèse

Dans le cadre d'une recherche prospective pour le développement de solutions alternatives dans le domaine des technologies mémoires non-volatiles, cette thèse porte sur le développement et l'étude de points mémoires résistifs à base de matériaux polymères pour les architectures Cross-bar.

-152-Nous avons focalisé notre travail sur l'étude approfondie d'un nano-composite organique à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Quatre axes de recherche ont été menés en parallèle: le développement et la caractérisation physicochimique du matériau mémoire composite, l'intégration du matériau organique dans des structures de test spécifiques ainsi que la suggestion de solutions pour une intégration cross-bar sur CMOS, la caractérisation détaillée du fonctionnement électrique des dispositifs et de leurs performances mémoires et enfin la caractérisation électrique avancée des dispositifs afin d'apporter des éléments de compréhension physique pour l'optimisation des futures technologies.

Nous avons présenté dans ce manuscrit les points majeurs de notre étude suivant cinq chapitres.

Le Chapitre 1 présente tout d'abord un bref historique des technologies associées au stockage de l'information. Ce point permet d'appréhender les besoins et facteurs clés de succès nécessaires pour le développement des technologies mémoires et introduit le marché actuel avec ses perspectives technologiques. Dans ce contexte, les solutions alternatives envisagées sont discutées en soulignant le potentiel des mémoires dites résistives et l'intérêt des matériaux organiques. Dans une troisième partie, l'état de l'art dans le domaine des mémoires résistives organiques et l'approche adoptée dans ce travail de thèse sont exposés.

Le Chapitre 2 concerne le développement du matériau organique et des dispositifs mémoires. L'approche nano-composite ainsi que les détails de fabrication sont premièrement introduits. Les études de caractérisation physico-chimique des couches organiques et l'impact du recuit sur la structuration de la couche y sont analysés. La dernière partie porte sur la description des dispositifs et des procédés de fabrication mis en place pour les études électriques.

Dans le Chapitre 3 l'étude électrique des couches composites est abordée sous un angle capacitif. L'intérêt et les principes de fonctionnement des structures Métal-Isolant-Semiconducteur sont rappelés brièvement et une analyse préliminaire du dispositif de référence comprenant uniquement le polymère isolant a été menée. Les couches nano-composites envisagées pour les dispositifs résistifs sont ensuite analysées en termes de piégeage de charges.

Le Chapitre 4 présente la caractérisation électrique de points mémoires résistifs à base d'électrodes inertes. Un comportement mémoire unipolaire ainsi que des effets de Résistance Différentielle Négative ont été mis en évidence dans les couches organiques étudiées. L'étude des performances mémoires et la caractérisation avancée du dispositif sont présentées. Enfin pour évaluer le potentiel technologique de ces mémoires, une étude sur la diminution de taille du point mémoire et quelques pistes pour son intégration sont apportées.

Le Chapitre 5 rapporte les résultats de caractérisation électrique sur les couches nanocomposites en présence d'électrodes oxydables. Les effets mémoires bipolaires observés dans ces structures ainsi que les résultats détaillés sur la dynamique des caractéristiques obtenues sont présentés. Pour appréhender les phénomènes physiques mis en jeux ici, l'impact de la géométrie des cellules sur les caractéristiques observées est aussi discuté.

Le manuscrit se termine enfin par une conclusion générale résumant les principaux résultats apportés par cette étude, avant d'exposer les perspectives futures de ce travail.

VI.1.1 Introduction aux mémoires Non-Volatiles

Composants clés des nouvelles technologies, les mémoires non-volatiles ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimédia ces dix dernières années (MP3, Smartphone, clés USB, ordinateurs ultra-portables, …). Ce marché en pleine expansion s'est appuyé ces trente dernières années sur la technologie FLASH. En l'absence de mémoires dites « universelles » qui puissent maximiser l'ensemble des performances mémoires, la technologie Flash a apporté un bon compromis entre Non-volatilité, Programmation rapide et Faible consommation. Outre ses caractéristiques mémoires, la compatibilité des procédés de fabrication avec la filière CMOS a permis une augmentation des densités et une diminution des coûts de fabrication au cours des années garantissant ainsi la viabilité commerciale. Cependant, avec la réduction drastique de la taille des cellules vers la dizaine de nanomètres ces solutions font aujourd'hui face à des défis techniques croissants et toujours plus coûteux. De plus les exigences des nouveaux marchés électroniques (Faible consommation, Automobile, More-than-Moore) pourraient offrir des opportunités sérieuses pour les solutions alternatives telles que les technologies résistives.

VI.1.2 Emploi de Matériaux organique pour les dispositifs mémoires

Pour les futures générations de technologies mémoires, l'augmentation de la densité et la limitation de la variabilité constituent des défis aujourd'hui difficiles à aborder. Dans ce contexte, les matériaux organiques offrent plusieurs avantages [START_REF] Kuhn | Systems of monomolecular layers -assembling and physico-chemical -198-behaviour[END_REF] . Premièrement, l'utilisation de molécules comme matériau actif pourrait permettre d'étendre la miniaturisation jusqu'à l'échelle moléculaire tout en contrôlant les propriétés électriques par le choix de la molécule élémentaire. De plus, les possibilités d'ingénierie du matériau par synthèse moléculaire ainsi que des coûts de fabrication potentiellement faible pourraient garantir des technologies durables et économiquement viables. Pour ces raisons, les matériaux organiques ont été ciblés par le consortium ITRS pour les technologies mémoires émergentes [ITRS10] . Deux approches se distinguent clairement [START_REF] Tour | Recent Advances in Molecular Scale Electronics[END_REF] : «L'électronique à l'échelle moléculaire » met l'accent sur l'utilisation de molécules uniques. Quelques démonstrations de dispositifs moléculaires ont été présentées avec des densités très prometteuses allant jusqu'à 10 11 bit/cm² [START_REF] Green | A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre[END_REF] . En revanche l'interfaçage électrique, l'intégration et la compréhension physique exacte du dispositif restent de sérieux défis pour démontrer une technologie viable [Haik07,[START_REF] Williams | How We Found The Missing Memristor[END_REF] . « Les matériaux moléculaires pour l'électronique » pour lesquels les dispositifs exploitent les propriétés globales de couches minces organiques (à base de polymères ou petites molécules). Les couches minces organiques permettent d'élargir les procédés de fabrication en environnements compatibles.

VI.1.3 Développement de mémoires organiques résistives

Dernièrement, les recherches se sont accentuées sur les dispositifs résistifs à base de couches minces de polymères ou de petites molécules. Ces derniers offrent potentiellement de faibles coûts de fabrication ainsi que des performances électriques très prometteuses. Nous présentons ici un bref aperçu sur les recherches en cours pour ces mémoires parfois appelées OBD (Organiques Bi-stables Devices), ONBM (Organique Non Volatile Bi-stable Memory) ou PoRRAM (Polymer Resistive RAM).

VI.1.3.a Matériaux et dispositifs étudiés

Un large panel de compositions organiques a été rapporté ces quarante dernières années pour leur capacité de commutation résistive [START_REF] Ling | Polymer electronic memories: Materials, devices and mechanisms[END_REF] . Ces compositions comprennent divers composants élémentaires tels que des polymères, des petites molécules, des ions mobiles, des complexes donneur-accepteur ou des nanoparticules [START_REF] Heng-Tien Lin | Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device[END_REF] . Comme illustré sur la figure VI.2, ces briques peuvent alors être organisées dans différentes configurations pour former la couche électriquement active :

Empilées: C'est le cas des dispositifs dits « à trois couches » constitués de métal ou nanoagrégats métalliques interposés entre deux couches de petites molécules [START_REF] Bozano | Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles[END_REF][START_REF] Park | Multilevel Nonvolatile Small-Molecule Memory Cell Embedded with Ni Nanocrystals Surrounded by a NiO Tunneling Barrier[END_REF] .

Juxtaposées: Des nanoparticules, des petites molécules, des ions ou des polymères sont dispersés dans un matériau global en solution ou par co-évaporation [Ouyang04, LinHT07, ChoSH09].

Chimiquement assemblées: L'organisation peut être effectuée à l'intérieur de macromolécules comprenant différents groupements chimiques inclus ou greffés [ling07] .

Empilements "trois-couches"

(Couche ou nano-agrégats métalliques entre couche de petites molécules) Concernant l'intégration, quelques démonstrations de macro-cellules (dimension élémentaire : 1mm-100µm) [ChoBO06, Kwan07, Park09, Song10] en configuration Cross-bar ou matrices empilées ont été présentées. La définition d'électrodes aux dimensions inférieures à la taille critique possible par évaporation masquée (10-100µm) reste aujourd'hui problématique sur les couches organiques. Quelques approches exotiques ont été suggérées pour la définition d'électrode structurée à faibles dimensions (Lift-Off [START_REF] Kwan | Stackable Resistive Memory Device Using Photo Cross-linkable Copolymer[END_REF] , Direct Metal Transfer [START_REF] Kim | A direct metal transfer method for cross-bar type polymer non-volatile memory applications[END_REF] ou-Viasholes [START_REF] Kim | Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure[END_REF] ) mais des solutions plus adaptées aux procédés conventionnel CMOS sont requises.

Metal Nanocluster

VI.1.3.b Performances électriques

Pour stocker l'information de manière résistive, les dispositifs mémoires nécessitent une hystérésis sur leur caractéristique courant-tension (I-V) [START_REF] Prime | Overview of organic memory devices[END_REF][START_REF] Waser | Redox-Based Resistive Switching Memories -Nanoionic Mechanisms, Prospects, and Challenges[END_REF] . Différents types de caractéristiques ont été reportés et remplissent les conditions favorables pour un usage mémoire non-volatile [START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF] : ratio des courants on-off>10, tension de programmation < 10V et rétention d'information stable. Certains groupes ont même démontré la possibilité de stockage multi-bits [Lauters06, ChoBO06, Reddy09, Park09] avec la programmation de différents niveaux de courant à faibles champs (voir figure VI.4). En revanche il n'y a que peu de commentaires sur la reproductibilité des dispositifs cycle-à-cycle ou dispositif-à-dispositif. De même l''endurance des cellules et la stabilité à l'environnement (température, humidité) ont été peu étudiées.

VI.1.3.c Mécanismes de basculement résistifs dans les dispositifs organiques

A partir de différents articles-revues disponibles [Scott07, Ling08, Heremans11, ChoB11], nous pouvons observer qu'il n'y a pas d'identification claire des mécanismes physiques pour la commutation dans les dispositifs expérimentaux. Cependant suivant les structures et matériaux employés différentes familles d'hypothèses ont été proposées pour expliquer le basculement résistif :

• Une modification intra-moléculaire : Des changements moléculaires tels que l'isomérisation, le transfert de charges ou des réactions d'oxydo-réduction peuvent se produire dans les molécules et ont été proposés comme potentiellement responsables des commutations résistives observées [Ling08, Ling07 [START_REF] Cho | Rewritable Switching of One Diode-One Resistor Nonvolatile Organic Memory Devices[END_REF] le fonctionnement mémoire. D'un autre côté, il a été démontré que les oxydes métalliques peuvent fournir à eux seuls le basculement électrique [START_REF] Wu | Low-power TiN/Al2O3/Pt resistive switching device with sub-20 µA switching current and gradual resistance modulation[END_REF] avec des caractéristiques très semblables à certains dispositifs organiques [START_REF] Lai | Influence of electrical field dependent depletion at metal-polymer junctions on resistive switching of poly(N-vinylcarbazole) (PVK)-based memory devices[END_REF][START_REF] Lai | Ultrahigh on/off -Current Ratio for Resistive Memory Devices With Poly(N-Vinylcarbazole)/Poly(3, 4-Ethylenedioxythiophene)–Poly(Styrenesulfonate) Stacking Bilayer[END_REF] . Le rôle fonctionnel de l'oxyde interfacial au regard de la couche organique est incertain dans la plupart des cas et reste toujours un sujet de discussion Pour la compréhension expérimentale, il est indispensable de considérer les dispositifs comme combinaison de la couche organique et des électrodes. Par conséquent, plusieurs de ces mécanismes peuvent être potentiellement mis en cause dans les basculements résistifs observés.

VI.1.4 Stratégie de Recherche

Au vu de l'état de l'art, nous avons identifié quatre objectifs principaux pour cette thèse intitulée « Etude et Développement de points mémoires résistifs à base de polymères pour les architectures Cross-bar »:

1)

Développer des cellules mémoires résistives polymères compatibles avec l'architecture cross-bar

2)

Fournir une caractérisation électrique détaillée du fonctionnement mémoire, des performances associées, de la reproductibilité et de la stabilité des cellules

3) Adresser les enjeux de réduction de taille des cellules et d'intégration sur CMOS 4) Fournir des éléments de caractérisations avancées pour la compréhension des dispositifs

De manière complémentaire à la littérature qui rapporte une grande variété de compositions organiques étudiées mais qui manque parfois de caractérisations détaillées, nous avons choisi au début de cette thèse de concentrer nos études sur un unique matériau et d'en étudier les propriétés en détail suivant différentes approches menées en parallèle.

VI.1.4.a Choix du matériau

Afin d'assurer la compatibilité du matériau mémoire avec les contraintes et procédés de fabrication CMOS nous avons développé un matériau nanocomposite original à base de polymère PolyMethyl-MethArcylate (PMMA) et de molécules de Buckminster-Fullerène (C60). Le PMMA a été particulièrement choisi car il est couramment employé en microélectronique comme résine lithographique e-beam et pourrait être un atout pour la fabrication de cellules mémoires organiques hautes densités. Les molécules de C60 ont quant à elles déjà été utilisées dans plusieurs nanocomposites 27 reportés pour leur potentiel mémoire résistif.

VI.1.4.b Etudes expérimentales

Nous avons décidé de découpler autant que possible la caractérisation électrique du matériau des problématiques d'intégration. Pour ce faire, des structures de tests macroscopiques avec électrodes inférieures pleine couche ont été fabriquées. En minimisant la topologie et la rugosité, ces structures permettent une bonne uniformité de la couche organique déposée et une caractérisation électrique rigoureuse du matériau. Afin d'étudier le matériau organique sous différent angles, des électrodes inertes ou oxydables ont également été alternativement utilisées pour étudier l'impact de l'oxyde natif à l'interface. En parallèle des structures de tests spécifiques ont été mises en place pour démontrer la miniaturisation des cellules mémoires.

Materials Studies

Capacitive Studies

Resistive Studies (inert and oxidizible) Materials Studies

Capacitive Studies

Resistive Studies (inert and oxidizible) Le premier chapitre introduit les technologies de stockage non-volatile et souligne le succès des mémoires Flash. Au regard des limitations actuelles et des nouvelles exigences, plusieurs alternatives sont aujourd'hui à l'étude. Parmi ces dernières figurent les mémoires dites résistives qui apportent de nombreux avantages en termes d'intégration avec potentiellement de meilleures performances et densités de données. Les matériaux organiques sont aussi étudiés comme alternatives. L'approche moléculaire est intéressante à long terme pour atteindre les dimensions ultimes mais l'intégration des molécules reste à ce jour un défi majeur. A court terme, les couches minces organiques (petites molécules, polymères ou composites) apporte plus de flexibilité pour une hybridation avec la microélectronique ou pour de nouvelles applications nécessitant de faible coût ou des procédés grandes surfaces ou imprimés. L'étude de l'état de l'art sur les mémoires organiques résistives met en évidence une grande variété de compositions organiques présentées pour leur potentiel mémoire. En revanche les mécanismes physiques associés ne sont pas clairement identifiés. En particulier, le rôle des électrodes ainsi que l'impact des facteurs l'intégration (non-homogénéité, diffusion, oxydation) reste sujette à débat. Si des caractéristiques électriques prometteuses ont été reportées avec de forts ratios on-off, la possibilité de stockages multi-niveaux et des temps de programmation potentiellement rapides, on peut aussi souligner le peu de commentaires apportés sur l'endurance et la reproductibilité des cellules. Enfin une véritable stratégie d'intégration reste aussi à définir.

Au regard de la bibliographie nous avons proposé pour cette thèse l'étude d'un matériau unique nanocomposite à base de polymères (PMMA) et de molécules (C60). Nous suggérons ici une approche expérimentale transversale incluant des caractérisations physicochimiques et électriques dans différentes configurations afin d'apporter une connaissance globale sur le matériau mémoire développé et ses caractéristiques.

VI.2 Chapitre 2 -Fabrication et Caractérisation du Nanocomposite (PMMA:C 60 )

Dans le second chapitre nous présentons la fabrication et la caractérisation physico-chimique de couches minces organiques nanocomposites à base de polymères Poly-Methyl-Méthacrylate (PMMA) et de molécules de fullerène (C60) développées pour les applications mémoires.

VI.2.1 Fabrication de couches nano-composites (PMMA :C60)

La matrice du nanocomposite est un polymère isolant de Poly-(methyl methacrylate) (PMMA) obtenu par polymérisation du monomère de methyl-methacrylate (MMA). Bien connu en microélectronique ce polymère est couramment employé comme résine lithographique [MicroChem] mais aussi utilisé comme diélectrique de grille pour les transistors organiques. Afin d'apporter les propriétés électriques souhaitées au composite nous avons introduit des molécules de fullerène C60. Composé de 60 atomes de carbone, cette molécule sub-nanométrique présente des propriétés semi-conductrices et a été reportée pour sa capacité à stocker les électrons [START_REF] Haddon | The Fullerenes: Powerful Carbon-Based Electron Acceptors [and Discussion[END_REF][START_REF] Echegoyen | Fullerenes: Chemistry, Physics, and Technology[END_REF]. Elle a été employée à plusieurs reprises dans la fabrication de dispositifs mémoires résistifs organiques La première étape de caractérisation a consisté à évaluer l'impact de l'introduction du C60 sur les propriétés du film composite. Différentes techniques de caractérisation ont été employées.

Les études de topographie qui ont été menées par microscope à force atomique (AFM) n'ont pas révélé d'influences majeures du C60 sur la rugosité de surface pour toute la plage étudiée (ρ=0-20wt%). De la même manière, l'imagerie électronique par transmission (TEM) des coupes en tranche présentées figure VI.8 ne révèle pas de modifications majeures dans l'homogénéité ou l'uniformité des couches. En revanche, les propriétés thermiques étudiées par Calorimétrie différentielles (DSC) et analyses thermogravimétriques (TGA) ont montré sur les figures VI.9 une influence favorable de l'introduction du C60. En effet, les caractéristiques ne sont pas dégradées par le C60 mais montrent plutôt une amélioration de la stabilité thermique : la température caractéristique de transition vitreuse (Tg) est augmentée ainsi que la température de dégradation (Td).

VI.2.2.b Quantification et distribution dans la couche

La matrice organique (PMMA) étant isolante, les propriétés électriques sont attendues pour être fortement dépendantes de la distribution du C60. Afin de comprendre la caractéristique électrique il est donc primordial de pouvoir contrôler la quantité de C60 introduite et dans la mesure du possible de pouvoir étudier sa répartition dans la matrice.

Les mesures du coefficient d'extinction par spectroscopie U-V ont permis d'identifier plusieurs pics relatifs à la présence de C60 aux longueurs d'ondes λ =213,260,230 nm (valeurs en accord avec la littérature [START_REF] Hare | Preparation and UV / visible spectra of fullerenes C60 and -197-C70[END_REF][START_REF] Lee | Application of a Novel Fullerene-Containing Copolymer to Electroluminescent Devices[END_REF] ). Pour différentes concentrations les expériences ont montrées une bonne linéarité entre l'extraction du coefficient d'extinction au pic λ =261 nm et la quantité de C60 introduite en solution permettant ainsi une quantification non-destructive du C60 dans les couches (Voir figures VI.10a-b). Les couches composites ont également été étudiées par spectrométrie de masse ToF-SIMS. Cette technique a permis de discriminer les ions liés au PMMA et au C60 [START_REF] Py | Investigation of fullerene depth distribution in PMMA:C60 blends using dual beam ToF-SIMS[END_REF] . L'abrasion et l'analyse progressive de l'échantillon ont également permis d'établir les profils de distribution dans l'épaisseur de la couche (Voir figure VI.10c). Les signaux relatifs au C60 et au monomère de PMMA sont stables sur la profondeur de la couche et suggèrent une distribution homogène des molécules de C60 dans la couche. De plus, en relevant les ratios des différentes espèces il est possible d'obtenir une quantification précise du C60 dans l'échantillon (Voir figure VI.10d).

VI.2.3 Impact du recuit thermique au dessus de la transition vitreuse

Les études électriques des dispositifs présentés au chapitre IV ont montré une influence critique du recuit au delà de la température de transition vitreuse (Tg). Afin de comprendre ce phénomène, les mesures de contrôle des couches (microscopie, AFM, SEM) ont été comparées avant et après recuit de la couche active. Sur les mesures AFM reportées sur la figure VI.11 on peut observer une augmentation très significative de la rugosité avec l'apparition de larges pics dans le cas de l'échantillon avec C60 recuit (ρ=20wt% ; Recuit à 180°C). Ce phénomène n'a pas lieu en présence de PMMA non dopé (ρ=0wt% ; Recuit à 180°C). Ces observations préliminaires semblent suggérer une réorganisation du matériau lors des recuits au dessus de la température de transition vitreuse avec agrégation du C60.

VI.2.5 Conclusions du Chapitre 2

Dans ce chapitre nous avons présenté les composés et méthodes de fabrication des couches minces de nanocomposites (PMMA:C60). Par le biais de différentes techniques de caractérisations physicochimiques nous avons étudié l'impact du dopage de fullerène sur la couche organique. Nous avons pu conclure que dans le cas du recuit classique (120°C ; 120s), l'introduction des fullerènes dans la gamme étudiée ne semble pas modifier la morphologie des couches organiques (ni la rugosité de surface ni l'épaisseur du film). Les analyses thermiques indiquent en outre un effet stabilisant des molécules de C60 avec une amélioration significative des températures de transition vitreuse (Tg) et de dégradation (Td). Les analyses de spectroscopie optique et de masse mises en places ont permis de quantifier précisément les ratios d'espèces en présence et d'obtenir des profils de distribution dans les couches qui suggèrent une distribution homogène des fullerènes dans l'épaisseur du film. Enfin dans la gamme de dopage considérée (jusqu'à 20wt%) nous avons montré que les couches nanocomposites pouvaient être structurées par lithographie e-Beam et Nano-Imprint garantissant un atout supplémentaire pour l'intégration des couches. Il est à noter que pour des recuits au-delà de la transition vitreuse une étude préliminaire de la morphologie par AFM a permis de mettre en évidence une réorganisation qui semble induite par l'agrégation de molécules de fullerène.

Finalement en dernière partie nous avons présenté les structures de test employées pour l'étude électrique des couches Nanocomposites comprenant des structures de test avec matériau organique pleine couche en configuration MIS ou MIM pour les études électriques respectivement capacitives et résistives aux dimensions macroscopiques. Des structures spécifiques aux dimensions submicroniques ont aussi été fabriquées pour l'étude de miniaturisation.

-165-Très largement étudiée et théorisée l'allure de ces caractéristiques et les points remarquables associés permettent d'obtenir des informations détaillées sur les caractéristiques des matériaux en présence (Epaisseur de diélectrique, travaux de sortie, dopage du semi-conducteur, qualité des interfaces, charges piégées, résistance de contact, …). Nous pouvons observer un comportement classique en régime d'accumulation avec une valeur de capacité en accumulation conforme aux attentes pour la surface et l'épaisseur étudiées (Cox= 70 pF ; S=0.18mm², e= 50nm). La tension de bande plate (Vfb) observée ici est inférieure aux valeurs attendues si l'on considère le dopage du Silicium choisi et la grille en platine (VFB_Pt

VI.3.2.b Caractérisation du comportement en inversion

Afin d'étudier le comportement atypique des dispositifs en inversion, deux types de mesures ont été mis en place. Premièrement, des mesures en fréquence ont permis de mesurer l'atténuation du phénomène d'inversion en fréquence (voir figure VI.17a). On constate la présence de phénomène d'inversion au delà des fréquences usuelles pour les dispositifs MIS avec le semi-conducteur considéré. A de telles fréquences les porteurs minoritaires ne peuvent théoriquement pas provenir du semi-conducteur (constante de temps trop élevée). Une seconde étude a été alors mise en place pour étudier la possibilité d'un effet de bord. Nous avons reporté sur la figure VI.17b l'impact de la surface du dispositif sur ce phénomène d'inversion. Nous observons une augmentation de l'effet d'inversion avec la diminution de surface de l'électrode. Cette dépendance en surface met en évidence ici un effet de bord et soutient l'hypothèse d'une source extrinsèque de porteurs minoritaires à la périphérie du dispositif.

VI.3.2.c Phénomène de couche d'inversion permanente et model de Nicollian

Ce comportement inhabituel avec une inversion à haute fréquence, un hystérésis sur la bosse d'inversion et une forte dépendance en surface a été reporté également sur des couches de diélectriques inorganiques (a-SiNx:H) [START_REF] Beylier | PhD Manuscript « Etude des dielectriques du pre metal et de leurs influences sur les dispositifs actifs[END_REF] . Il a été expliqué par un phénomène dit de couche d'inversion permanente et théorisé par Nicollian

VI.3.3 Effet mémoire par piégeage de charges dans les molécules de C60

Nous avons étudié ici l'impact du dopage en C60 sur la caractéristique C-V de dispositifs MOIS (Métal-Organique-Isolant-Semi-conducteur) à base de PMMA. Nous avons étudié ici des couches nanocomposites de 50 nm avec différents taux de dopage (ρ = 0,5 et 10 wt% de C60 29 ). D'après les études morphologiques présentées au chapitre 2 nous avons pu conclure que le dopage en C60 n'a pas d'effets significatifs sur l'épaisseur des couches. Par conséquent, les différents échantillons ont été analysés à tension équivalente. PM05 : PMMA:C60 ρ=5wt%

V PROG = 0 V PROG = [+5V to +30V step 5V] V PROG = [-5V to -30V step -5V]
V PROG = 0 V PROG = [+5V to +20V step 5V] V PROG = [-5V to -30V step -5V] Flat-Band Voltage V FB (V)
Cumulative Stress Time t PROG (s) FIGURE VI.22: Caractéristiques Temps-Tension du piégeage de charges obtenues par séquences de mesure stress C-V avec des impulsions de 100µs to 5s pour les échantillons PM00(PMMA seul), PM05(ρ =5wt%) et PM10(ρ =10wt%).

Les mesures des dispositifs de référence PM00 (PMMA -ρ =0wt %) confirment un comportement purement isolant sans évidence de piégeage avec des tensions allant jusqu'à 30V et des temps de programmation jusqu'à 5s. Les dispositifs PM05 (PMMA:C60 -ρ =5wt %) montrent pour leur part une capacité de piégeage d'électrons pour les tensions inférieures à -15V ainsi qu'une possibilité plus limitée de stockage de charges positives pour des tensions supérieures à 20V. Finalement, pour les échantillons les plus dopés PM10 (PMMA:C60 -ρ =10wt %) on observe un décalage très significatif et rapide pour des tensions de programmation inférieures à -15V (ie VPROG=-20V and tPROG =100µs > ∆VFB~12V) et un décalage positif de la tension de bande plate en absence de stress indiquant que la mesure C-V démarrant à -10V participe déjà à l'injection d'électrons.

Nous avons observé ici que l'introduction de C60 permet d'augmenter la fenêtre de programmation et d'obtenir des temps de programmation équivalents plus courts. En revanche, on constate aussi sur l'échantillon le plus dopé que la quantité de charges piégées /dé -piégées est moins stable à faible champ. En effet, réduisant les barrières entre les ilots de C60, le fort dopage augmente l'injection et la capacité de piégeage mais peut aussi participer à une perte de charges en fonction du temps ou lors d'opérations de lecture à faible champ. Pour mieux comprendre ces phénomènes de chargement et de stockage, les mesures des courants de programmation, du read-disturb et de la rétention seraient nécessaires. Une structure transistor pourrait aussi être employée et permettrait d'estimer la quantité de charges piégées par la modulation de conduction du canal en dé-corrélant programmation et lecture.

VI.3.4 Conclusions du Chapitre 3

Nous avons étudié dans ce chapitre le comportement électrique des couches (PMMA:C60) par une mesure capacitive dans une structure Métal-Organique-Isolant-Semi-conducteur (MOIS) spécifiquement développée pour l'étude du piégeage de charge. Ces mesures ont permis de montrer que le PMMA pouvait être considéré comme un isolant positivement chargé sans capacité de piégeage de charges dans la gamme des tensions étudiées. Nous avons également expliqué les phénomènes atypiques observés en inversion par l'existence d'une couche d'inversion permanente. L'introduction de molécules de C60 apporte à la fois la possibilité d'injection et de stockage d'électrons. Le compromis entre l'injection et la rétention des électrons semble toutefois dépendre fortement du taux de dopage : le C60 offrant à la fois les pièges potentiels pour les électrons, mais contrôlant également le transport dans la couche et donc l'injection et la perte de charges. -173-Conformément à la littérature [START_REF] Simmons | New Conduction and Reversible Memory Phenomena in Thin Insulating Films[END_REF][START_REF] Bozano | Organic Materials and Thin-Film Structures for Cross-Point Memory Cells Based on Trapping in Metallic Nanoparticles[END_REF] , nous avons ensuite montré que ce type de dispositifs pouvait également être programmé à différent niveau de résistance en stoppant la mesure dans la plage de RDN. Cette propriété est illustrée sur la figure VI.25c -cycles 10-11 : la coupure abrupte de la tension à 8V a induit un nouvel état initial (courant plus faible) au cycle successif. On peut noter que ce comportement est reproductible puisqu'après un saut de courant abrupt vers V~3V le dispositif retrouve un comportement de type RDN et l'opération de programmation par coupure abrupte à 8V peut alors être recommencé avec les mêmes conséquences (cycle 11-12-13).

Comme illustré sur la figure VI.25d, en stoppant la mesure à différente tension dans la zone de RDN (0V → VProg) il est possible de programmer le niveau de courant successif sur une large gamme avec des résistances équivalentes variant de 325Ω à 1.5MΩ.

(V) Sweep 1 [0V > 8V > 0V] Sweep 2 [0V > 8V > 0V] Sweep 3 [0V > 8V > 0V] Sweep 4 [0V > 8V > 0V] Sweep 5 [0V > 8V > 0V]

VI.4.2.b Etude préliminaire des caractéristiques Mémoires : Rétention, Cyclage, Variabilité

Pour étudier la volatilité de l'information stockée, des tests de rétention ont été réalisés pour différents états programmés. Pour cela l'évolution du courant a été ponctuellement mesurée à faible champ au cours du temps après la programmation. Pour une lecture à 0.5V les résultats -174-tels que ceux présentés sur la figure VI.26a ont permis de mettre en évidence une très bonne stabilité de l'état programmé sur les périodes étudiées (ici 4.10 5 s ~ 12h). Afin de pouvoir utiliser ces dispositifs comme un élément de stockage mémoire il est également important de vérifier qu'ils puissent être écrits et être effacés un grand nombre de fois sans modification majeure des caractéristiques. Pour étudier l'effet de ce cyclage des séquences répétitives de mesures I-V ont été mesurées : l'effacement choisi ici comme étant la transition de l'état conducteur à forte résistance (Rfaible→Rforte) est obtenue par la séquence [0→10V] et l'écriture ou programmation à « 1 » (Rforte→Rfaible) est obtenue respectivement par la séquence [0→-8V→0V]30 . Cette dernière permet de quitter l'état haute résistance vers un fonctionnement en RDN puis de quitter la RDN dans l'état le plus conducteur. Dans ce but, nous avons en particulier étudié la programmation en créneaux des tensions. Plusieurs études en amplitude et longueur d'impulsion nous ont permis d'identifier les limites de programmation : ~25ms pour une transition d'un état haute résistance à moyenne résistance, ~ 100µs pour une transition d'un état moyenne résistance à faible résistance et <100ns pour les transitions vers l'état haute résistance (voir détails §). Ces données nous ont permis de montrer pour la première fois pour ce type de dispositifs un fonctionnement valide jusqu'à plus de 128k cycles (voir détails §).

Un pas significatif a également été franchi avec l'intégration des points mémoires sur silicium suivants les procédés back-end. Nous avons ainsi pu pour la première fois montrer des points mémoires organiques à base RDN aux dimensions submicroniques (jusqu'à 300 nm). Cette étude a par ailleurs permis de montrer un élargissement favorable de la fenêtre de programmation (Ion/Ioff) avec la réduction de taille. Cela permettrait d'augmenter d'autant plus la densité de donnée stockable en augmentant le nombre d'états potentiellement programmable en multiniveau.

VI.4.2.d Conclusions mémoires avancées

Dans leur papier de revue Scott et Al [START_REF] Scott | Nonvolatile Memory Elements Based on Organic Materials[END_REF] listent certains prérequis pour le développement des mémoires polymères résistives. Parmi ces points, plusieurs sont encore faiblement adressés ou restent encore bloquants. Dans la Table VI.1 ont été reportés les éléments de l'état de l'art ainsi que nos résultats sur les principaux critères de performances : Nous sommes ensuite intéressés à la nature des états stables. Sous la tension de basculement (V< Vsw~2-4V), nous avons montré sur la figure VI.31a que la caractéristique I-V pouvait être assimilée au premier ordre aux relations simplifiées suggérées par les équations Eq 6.1. Pour les différents niveaux programmés, l'extraction du coefficient α a été reportée en fonction du niveau de résistance initiale sur la figure VI.30b. Nous observons ici que la programmation dans la zone de RDN ne modifie pas seulement le niveau de résistance (~1/β) de la cellule mais également l'allure de la dépendance I-V (#V α ) et donc le mode de conduction. Fort de cette constatation, nous avons représenté sur la figure VI.31 les mesures I-V de trois états stables distincts (Haute, Medium et Faible résistance), leurs extrapolations par l'équation Eq 6.1 ainsi que les points de programmation correspondants dans la zone RDN. Nous avons constaté que pour chaque niveau, le point de programmation et la mesure I-V avant basculement de l'état programmé appartenaient à une caractéristique commune décrite par l'équation Eq 6.1 avec des coefficients de conduction (α, β) communs uniques fonction de la tension de programmation.

VI.4.4 Description quasi-statique de la cellule

Les observations et les dépendances extraites des caractérisations détaillées du dispositif en fonctionnement multi-niveau après préformage ont permis d'extraire plusieurs règles de fonctionnement pour une description quasi-statique de la cellule: Hypothèse (i) Sous la tension de basculement le système est stable et l'ensemble de sa caractéristique I-V peut être décrite au premier ordre par l'équation Eq 6.1b: α β V ⋅ = I dont les paramètres de conduction (α,β) sont fixés fonction de la tension qui a été employée pour la programmation.

Hypothèse (ii): Le courant de programmation dans la zone de RDN et dans les états stables obtenus peuvent être tout deux décrits par la même équation Eq 6.1b et le même couple de paramètres (α,β).

Hypothèse (iii):

Résultant des hypothèses (i) et (ii) on peut alors décrire la caractéristique I-V dans la zone de RDN par l'équation Eq 6.1b associée à des paramètres (α,β) variant avec la tension appliquée :

) ( V ) ( ) ( V V V I α β ⋅ =
(en augmentant V, β diminue fortement et α augmente sensiblement). Le système présente un mode de conduction évolutif.

Hypothèse (iv): Lorsque la tension est stoppée de manière abrupte dans la zone de RDN à une certaine tension de programmation (Vprog) le système est alors brusquement gelé. Les paramètres de conduction de l'état stable successif (α,β) correspondent alors a ceux du point de programmation dans la zone RDN (α(Vprog),β(Vprog)) .

Suivant ces hypothèses on peut alors proposer un modèle quasi-statique simplifié décrit par le schéma figure VI.34. Il consiste à prendre comme donnée d'entrée l'équation générique Eq 6.1b ainsi que trois dépendances extraites des mesures : R0(VPROG),α(R0) et Vsw(R0).

VI.4.5 Conclusions et Perspectives du chapitre 4

Dans ce chapitre nous avons présenté la caractérisation électrique de points mémoires résistifs à base d'électrodes inertes. Un comportement mémoire unipolaire ainsi que des effets de Résistance Différentielle Négative ont été mis en évidence. Nous avons inclus dans notre étude une caractérisation préliminaire des performances mémoires. Plusieurs caractéristiques faiblement commentées dans la littérature (voir scott07) pour ce type de mémoire ont ainsi été étudiées. Nous avons en particulier rapporté des ratios de programmation élevés favorables aux stockages multi-niveaux, commenté la reproductibilité et variabilité des caractéristiques, étudié l'optimisation de la programmation par impulsion et obtenus des performances d'endurance optimisée au delà de l'état de l'art.

Dans un second volet, la caractérisation quasi-statique avancée du dispositif a permis une bonne compréhension du mode de fonctionnement de la cellule et l'extraction de dépendances originales sur les caractéristiques des cellules : R0(VPROG),α(R0) et VSW(R0). Ajouté à l'hypothèse d'un mode de conduction filamentaire soutenue par les observations sur les dispositifs submicroniques présentés au §IV.2.6, ces données sont de futures clés pour l'identification des phénomènes physiques en présence.

VI.5 Chapitre 5 -Effets mémoires résistifs bipolaires avec (PMMA:C60) & électrodes oxydables

Le rôle des oxydes aux interfaces a été suggéré plusieurs fois dans la littérature comme pouvant être potentiellement responsable des effets mémoires observés. Afin de clarifier ce point nous avons reporté ici l'étude de dispositifs à base de couches (PMMA:C60) avec des électrodes oxydables d'aluminium 32 .

VI.5.1 Mise en évidence d'effet mémoire avec électrode oxydable

Ajouté à l'oxydation à l'air de l'aluminium, la déposition en voie liquide et le recuit de la couche organique va également contribuer à la formation d'oxyde interfacial isolant. De tels oxydes natifs ont été mis en évidence par des caractérisations TEM et XPS dans le cas de cellules résistives à base de (PI:PCBM) [START_REF] Cho | Rewritable Switching of One Diode-One Resistor Nonvolatile Organic Memory Devices[END_REF] . Bien qu'un oxyde natif se soit aussi probablement formé à l'interface supérieure, le procédé d'évaporation thermique sous vide devrait résulter en une épaisseur d'oxyde interfacial potentiellement moindre. Suivant ces considérations, ces dispositifs seront décrits ici sous l'acronyme M-i-O-I-M (Métal-thin insolant fin-Organique-Insolant-Métal).

VI.5.1.a Etude de la référence avec électrode inerte

Afin de discriminer le rôle de l'électrode supérieure oxydable dans notre étude, des dispositifs de référence ont été réalisés avec une électrode inférieure inoxydable (Pt). Sur ces dispositifs Mi-O-M (Métal -isolant fin -Organique -Métal), une gamme complète de caractéristiques I-V a été appliquée. Les séquences unipolaires ou bipolaires à différentes tensions (Cf. figure VI.36a pour ρ=10wt%) n'ont permis de relever jusqu'au claquage aucune hystérésis qui puisse être exploitée comme effet mémoire potentiel. En revanche comme attendu, nous avons pu constater une augmentation de la conduction avec l'augmentation du dopage en C60 (Cf. figure VI.36b). La dynamique temporelle de l'opération d'écriture a également été étudiée à l'aide de programmation par impulsions à durées variables (Vw=-15V, tW = 500µs to 5s). Les résultats obtenus sont reportés sur la figure VI.41a. Ils montrent l'augmentation du maximum de courant extrait à 2.5V et reportés sur la figure. VI.41b et l'élargissement de la zone RDN avec la durée de programmation. Cette expérience montre que la constante de temps du mécanisme de programmation est relativement élevée puisqu'il nécessite une impulsion de minimum de 50 ms pour obtenir un ratio de courant programmé/effacée supérieur à 10.

VI.5.2.c Conclusions sur le potentiel pour les applications mémoires

En conclusion, l'analyse préliminaire des conditions d'opération des dispositifs fabriqués (Mi-O-I-M à base de PMMA : C60@ ρ=10wt%) a permis de mettre en évidence quelques éléments de considération pour leur usage comme cellules mémoires. En particulier, il a été montré que la lecture était partiellement destructive, la fenêtre de programmation limitée par un mécanisme de programmation complexe autorisant un ratio de courant de l'ordre d'une décade et la cinétique de programmation est relativement lente avec une constante de temps élevée (50 ms à quelque seconde). Pour une caractérisation mémoire complète plusieurs points restent encore à adresser : temps de programmation pour différentes tensions, rétention d'information, reproductibilité, endurance du cyclage mémoire et distribution statistique des caractéristiques. VI.5.3 Influence de la structure surs les caractéristique des dispositifs VI.5.3.a Surface des électrodes Pour les mémoires résistive le suivi de la dépendance du niveau de courant en fonction de la surface du dispositif permet d'identifier si les mécanismes de commutation sont de type filamentaire ou planaire. À cet effet, les caractéristiques électriques bipolaires sur trois dispositifs de surfaces différentes ont été étudiées dans les mêmes conditions électriques [0V +/-15V]. Les caractéristiques reportées sur la figure VI.42a sont très similaires : la tension de pic (VMAX) ainsi que la fenêtre mémoire (ratio de courant on-off) n'est pas affecté par la variation de surface. -188-théorème de Gauss appliquée à la structure MiOIM décrite ci-dessous permettent d'exprimer le champ critique FMAX=Vtot/torg en fonction du champ électrique dans l'oxyde (Eq. 6.2) ou dans la couche organique (Eq. 6.3). Suivant ces équations considérer l'hypothèse d'un champ critique dans la couche organique ou dans l'oxyde comme éléments déclencheur du basculement résistifs (lorsque FOX ou FORG = F0= Constante indépendante de torg), donnerai lieu a une diminution de la valeur expérimentale mesurée Vtot/torg lorsque torg augmente. Cette hypothèse va donc a l'encontre de l'observation constatée qui montre une augmentation de la valeur Vtot/torg au basculement lorsque torg est augmentée. Cette expérience montre que le phénomène responsable du basculement résistif n'est pas directement relié à l'existence d'un champ critique dans l'oxyde ou la couche organique. Il pourrait résulter d'autres facteurs tels qu'une densité de charge critique dans le volume.

VI.5.4 Conclusion de l'étude sur les dispositifs avec électrode oxydables

En conclusion, l'étude des dispositifs avec électrodes oxydables a permis de montrer que l'oxyde interfacial résultant de la fabrication du dispositif joue ici un rôle fondamental en activant la possibilité d'effets mémoires résistifs bipolaires. En revanche la caractérisation préliminaire des caractéristiques de lecture / écriture/ effacement montre que les performances associées restent limitées : faible ratio de courant programmé, lecture partiellement destructive, programmation lente (milliseconde à seconde). Bien que le mécanisme sous-jacent ne soit pas encore clarifié, les observations et résultats d'expériences présentés ici pourront servir de bases pour la compréhension des phénomènes physiques envisageables dans ces dispositifs.

VI.6 Conclusion générale et Perspectives

Ce travail de thèse a été dédié au « Développement et à l'étude de points mémoires organiques résistifs à base de polymères pour les architectures cross-bar ». Les recherches ont été focalisées sur l'étude extensive d'un nanocomposite organique (PMMA:C60) spécifiquement choisi. Les résultats obtenus ont permis de démontrer plusieurs types d'effet mémoires dans diverses structures de test. Pour chacun d'entre eux, une compréhension claire des mécanismes d'opération ainsi que des éléments de caractérisation avancée du fonctionnement ont été apportés pour la compréhension physique des phénomènes mis en jeu. Dans le cas des mémoires résistives unipolaires particulièrement intéressantes pour les architectures cross-bar, une étude préliminaire des performances mémoires a permis de placer ces dernières à l'état de l'art. Ces travaux ont également permis la démonstration inédite de points mémoires de ce type aux dimensions submicroniques et la réalisation d'un modèle comportemental quasi-statique.

Dans le premier chapitre une introduction historique a illustré les spécifications et facteurs clés du succès et du déclin des technologies de stockage de l'information. Ce contexte a permis de souligner le succès actuel de la technologie Flash dans le modèle économique de la microélectronique CMOS mais aussi ses possibles limites futures. Pour les futures générations, les FLASH pourraient alors être complétées ou remplacées par les mémoires résistives qui apportent de nombreux avantages de part leur simplicité d'intégration à haute densité et leur performance prometteuse. En termes de matériaux, des approches moléculaires ont aussi été proposées à long terme pour la diminution de taille jusqu'à l'échelle de la molécule. Cependant ces solutions rencontrent aujourd'hui des difficultés d'intégration avec les procédés conventionnels. A court terme, les couches minces organiques offrent quant à elles plus de flexibilité pour une hybridation avec la microélectronique ou pour les applications émergentes nécessitant un faible coût, une large surface, une flexibilité ou compatibilité avec les procédés d'impression. A la convergence de deux approches prometteuses, l'état de l'art des mémoires organiques résistives a été présenté. Dans ce domaine, une large variété de matériaux et de configurations a été rapportée pour leurs performances prometteuses : faible coût d'intégration, ratio ON/OFF élevé, programmation rapide et possibilité de stockage multi-bit. En revanche la reproductibilité et l'endurance ne sont que très faiblement adressées. De même, la compréhension physique reste incomprise et plusieurs mécanismes potentiels sont suggérés incluant le rôle fonctionnel des oxydes aux interfaces. Afin de compléter au mieux l'état de l'art, une étude extensive et transversale incluant à la fois la caractérisation matériaux et la caractérisation électrique dans des structures complémentaires a été proposée dans le cas d'un nano-composite organique de (PMMA:C60).

Le second chapitre a été dédié aux recettes et procédés expérimentaux employés pour la fabrication des couches nano-composites de (PMMA:C60). Les éléments de caractérisation du matériau rapportés dans ce chapitre ont montré des couches minces homogènes sans rugosité ni variation d'épaisseur avec l'introduction des dopants. Les techniques spectrométriques de masse ou optique, ont permis de caractériser précisément la quantité relative des deux composantes dans le composite. Les profils ToF-SIMS en profondeur ont montré une répartition uniforme des molécules (C60) dans la couche. En revanche pour les échantillons soumis à des traitements de recuit au-dessus de la transition vitreuse les analyses par microscopie confocale ont montré la formation d'agrégats de C60. Les capacités de structuration apportées par la matrice polymère au nanocomposite ont également été vérifiées par lithographie E-beam et nano-lithographie. Finalement des structures des tests spécifiques ont été proposées pour les études capacitives et résistives avec électrodes inertes et oxydables ainsi que pour les études de miniaturisation du dispositif. Un schéma d'intégration original basé sur la structuration directe et l'encapsulation a également été suggérée pour la l'intégration haute densité des cellules résistives polymères.

Dans le troisième chapitre, le comportement électrique du nano-composite (PMMA:C60) a été étudié dans des structures capacitives Métal-Organique-Insolant-Semi-conducteur (MOIS). Après avoir rappelé le comportement théorique des dispositifs Métal-Insolant-Semi-conducteur (MIS), la caractéristique capacitive (C-V) de l'échantillon de référence à base de PMMA seul a été analysée. Malgré un comportement inattendu en inversion, expliqué comme résultant d'un effet de bord avec couche permanente d'inversion, les mesures ont permis de considérer le PMMA comme isolant positivement chargé. Grâce à la structure MOIS les hystérésis observées avec le dopage progressif en C60 du PMMA ont pu être expliquées comme résultant de l'injection et du piégeage d'électrons par les C60 en régime d'accumulation.

Le quatrième chapitre est dédié à la caractérisation des couches (PMMA:C60) dans la structure Métal-Organique-Métal (M-O-M) avec électrode inerte. Un comportement résistif non linéaire a d'abord été observé. L'usage d'un recuit thermique supplémentaire a permis ensuite d'obtenir dans le dispositif un niveau de courant plus élevé et l'ouverture d'une hystérésis avec un comportement de résistance différentielle négative (RDN). Il a été montré que cette propriété permet un effet mémoire unipolaire multi-niveau caractérisé par un fort ratio on-off (10 6-9 ), une rétention stable, une bonne reproductibilité cycle-à-cycle et une variabilité acceptable. Une étude statistique de la programmation par impulsion a montré l'écriture dans la gamme 100µs to 25ms et un effacement en 100ns. Ces données ont ensuite permis de démontrer une endurance record de 10 5 cycles. L'étude de miniaturisation jusqu'à 300nm a pour sa part mis en évidence l'augmentation de la fenêtre mémoire aux petites dimensions et souligné la nature filamentaire de la conduction. Une analyse approfondie du fonctionnement multi-niveaux a été rapportée pour une compréhension claire du fonctionnement de la cellule. Les dépendances originales relevées apportent également des indices pour la compréhension des mécanismes impliqués. Il a entre autre été montré qu'il est possible d'obtenir une gamme continue d'états programmables stables jusqu'à la une certaine tension de commutation variant avec la résistance. Suivant l'observation que la zone de RDN et les courants programmables pouvaient être décrits par une loi commune (I = β.Vα), un modèle comportemental quasi-statique simple a été proposé.

Finalement, dans le dernier chapitre le rôle des électrodes oxydable a été étudié dans la structure Métal-insolant_fin-Organique-isolant-Métal (M-i-O-I-M) résultant de l'oxydation aux interfaces. Il a été montré que l'oxydation de l'électrode inférieure permet un effet mémoire résistif bipolaire. La caractéristique de l'hystérésis a été trouvée fortement influencée par le dopage en C60. Les opérations d'Ecriture, Lecture et Effacement associées à cette mémoire ont été étudiées. Des ratios on-off (~ 10), et des niveaux de courant (<nA) faibles ont été relevés ainsi qu'une lecture destructive et des temps de programmation élevés de l'ordre de la milliseconde. L'impact de la géométrie du dispositif a été présenté: l'étude de l'effet de surface de l'électrode a suggéré un mécanisme de commutation planaire et l'étude de différentes épaisseurs dans les couches organiques obtenues. Les résultats de ces études fournissent une liste d'observations préliminaires pour la discrimination des mécanismes physiques envisageables.

Perspectives

Actuellement, la recherche de mémoires émergentes pour les futures générations CMOS se focalise plus particulièrement sur les technologies PCRAM, RRAM et STT-MRAM qui combinent des performances prometteuses et une compatibilité d'intégration plus aisée avec les procédés conventionnels. Par ailleurs les récentes avancées dans le développement de l'électronique organique ont aussi ouvert de nouvelles opportunités pour les mémoires polymères résistives. Néanmoins pour l'émergence de cette technologie plusieurs points restent à adresser.

OPTIMISATION TECHNOLOGIQUE: Les mémoires unipolaires multi-niveaux semblent très prometteuses pour l'intégration en architecture cross-bar. Concernant leurs performances quelques points restent encore à valider : la rétention d'information sur des périodes de temps plus longues, la stabilité en température et à l'environnement. La reproductibilité et l'endurance restent encore les points faibles pour le développement d'une technologie mémoire fiable et doivent être travaillées pour répondre aux spécifications. L'absence de préformage serait également souhaitée pour une utilisation simplifiée et l'association avec une diode désirable pour les applications cross-bar. Finalement, les matériaux et procédés de fabrication doivent aussi être adaptés aux nouvelles spécifications : matériaux autorisés, flexibilité, possibilité d'impression … COMPREHENSION PHYSIQUE: Pour le développement de la technologie, la compréhension des mécanismes physiques est indispensable dans le but de modéliser, optimiser et préparer les futures évolutions. Bien que les mécanismes physiques exacts régissant les commutations résistives unipolaires et bipolaires observées dans ces travaux restent à déterminer, nous avons apporté une compréhension détaillée du fonctionnement et des caractéristiques intrinsèques au dispositif. Trois nouvelles directions sont maintenant ouvertes :

Des caractérisations électriques et physico-chimiques avancées: plusieurs expériences spécifiques pourraient compléter ce travail de thèse telles que : la caractérisation avancée du nanocomposite pour en comprendre l'organisation exacte, des mesures électriques en température qui permettraient de qualifier les modes conduction des différents régimes ainsi que des caractérisations spécifiques du comportement quasi-statique et dynamique. Des méthodes de caractérisation alternative telles que par AFM conducteur ou STM pourraient également apporter des éléments de compréhension.

Le développement de nouvelles structures de test: Plusieurs structures de test ont été employées dans cette thèse pour les couches (PMMA:C60) sans recuit spécifique (M-O-I-S, M-i-O-I-M and M-O-M). Cette diversification a apporté des conclusions complémentaires pour la compréhension des dispositifs et pourrait être à nouveau employée pour les couches (PMMA:C60) avec traitement thermique (étudié ici seulement en structure M-O-M). Des structures avec couches bloquantes d'électrons ou de trous pourraient également être employées.

Analyse de l'influence des matériaux: l'identification des caractéristiques et dépendances intrinsèques au dispositif permet maintenant de pouvoir étudier l'impact de variations technologiques sur la nature des électrodes (travail de sortie ou propriété thermodynamique différentes), des conditions de traitement thermique, d'épaisseur ou de composition de la matrice organique et des dopants.

Notationsa

  Diameter or edge length [m] CI, CSC, CFB, CD, Cinv, CIT Insulator, Semiconductor, Flat Band, Depletion, Inversion and interfacial capacitances [F] CLF, CHF Measured Capacitance in Low and High frequencies [F] CP Heat capacitance [J.K -1 .Kg -1 ] d Insulator Thickness [m] Dit Interfacial defect EC, Ei, EF,EV, Conduction, Intrinsic, Fermi and Valence band energy level [eV] EG Semiconductor Gap [eV] Forg, Fox Field in organic and oxide layer k Extinction coefficient in Chapter II K,k Conduction coefficient in Chapter III kT Thermal energy [J]: Boltzmann constant times temperature [K] m/z Mass-to-charge ratio [-] mC60, mPMMA Mass [Kg] Mw Molecular weight [g/mol] n Refractive index in Chapter II n Index of SCLC conduction in Chapter III nP0 Electron density at the equilibrium pP0 Neutron density at the equilibrium Q Trapped charge [C] QF, QM, QT Fixed, Mobile and Trapped charge per unit area at the semiconductor interface [C] Qit Interfacial trapped charge [C] Rspeed Rotation speed [rpm] TBK Bake temperature [°C] tBK Bake time [s] Td Degradation temperature [°C] Tg Glass transition temperature [°C] torg, tox Organic and oxide layer thickness [m] VACC Voltage in accumulation [V] VFB Flat-band voltage [V] Vforming Forming Voltage [V] VG Gate voltage [V] Vmax Maximum Current peak Voltage [V] VNDRmax, VNDRmin Boundaries Voltages for NDR region [V] Vorg, Vox Voltage drop on organic and oxide layer [V] VPROG Programming voltage [V] VRD Read Voltage [V] Vsw Switching voltage [V] Vw Write Voltage [V] α, β Coefficient for the conduction mode ε I Relative permittivity of insulation ε o Reference vacuum permittivity ε o= 8.85 10 -12 [F.m -1 ] ε org , ε ox Organic and oxide layer relative permittivity ε org ~ 2.4-2.6 for PMMA [-] ε ox ~ 3.9 for SiO2 [-] ρ Doping concentration [wt%]

  ORGANIC ELECTRONIC MEMORIES............................................... 3 I.1 Overview on Non-Volatile Memory Technologies ............................................................... 5 I.1.1 History of Storage Technologies and Technical Requirements............................................................5 I.1.2 Current Memory Market, Technologies and Challenges........................................................................7 I.1.3 Development of New Technologies & Opportunities for Resistive Memory.................................10 I.1.4 Conclusions ..................................................................................................................................................13 I.2 State of the Art of Organic based Memory Devices ........................................................... 14 I.2.1 Interest of organic materials for future electronics...............................................................................14 I.2.2 Molecular memory devices........................................................................................................................14 I.2.3 Organic Thin Films for Memory Devices ..............................................................................................19 I.2.4 Perspectives for organic memory devices...............................................................................................21 I.3 Development of Organic Thin Film Resistive Memories................................................... 22 I.3.1 Materials and Device Integration .............................................................................................................22 I.3.2 Electrical Performances .............................................................................................................................25 I.3.3 Mechanism of conductance switching in organic thin films ...............................................................29 I.3.4 Requirements & Challenges for Organic Resistive Memory Technologies......................................33 I.4 Our Approach ........................................................................................................................... 35 I.5 Conclusions of Chapter I......................................................................................................... 37 Appendix I.A: ITRS Roadmap for Memory Devices................................................................ 38 -5-I.1 Overview on Non-Volatile Memory Technologies I.1.1 History of Storage Technologies and Technical Requirements

FIGURE I. 1 :

 1 FIGURE I.1: Steps of development in information storage from early stage to the emergence of machines.

Figure I. 2 :

 2 Figure I.2: Main development steps of technologies for electronics and associated memory technologies during the 20 th century.

Figure I. 3 :

 3 Figure I.3: Technological waves and semiconductor industry revenue during the last 40 years (from SemicoResearc Corp. [ICI07]).

Figure I. 4 :

 4 Figure I.4: (a) Overview of available semiconductor based memory technologies and (b) classifications of technologies following main performance criteria. (See [ITRS10])

Figure I. 5 :

 5 Figure I.5: Increase of data capacity required for non-volatile memory with technology development [Samsung08].

Figure I. 6 :

 6 Figure I.6: (a) Technology roadmap for elementary device scaling concerning Logic, DRAM and Flash NAND Devices. (b) Evolution and forecast of cost per Gigabit for HDD, NAND FLASH and DRAM technologies [Lam08].

Figure I. 7 :

 7 Figure I.7: Overview on emerging memory classification suggested by International Technology Roadmap for Semiconductors [ITRS10, Jeong11].

Figure I. 8 :

 8 Figure I.8: (a) Schematic of crossbar architecture for very high-density integration [Wong2008]. (b) Stacking of organic resistive memory in crossbar architecture above the CMOS for high density and low-cost application [Pinnow04].

Figure I. 9 :

 9 Figure I.9: Comparison of memory performance for the main emerging technologies [Numonyx09].

Figure I. 10 :

 10 Figure I.10: Evolution of storage hierarchy in computing architecture where Resistive RAM could be employed for the Storage Class Memory application [Lam09].

  Figure I.11: (a) Schematic representation of a molecular charge storage device, including the molecular capacitor, pass transistor, and bit and word lines. WE stand for working electrode, and VPL stands for plate voltage. (b) Schematic representation of a molecular capacitor cell. [Kuhr04].

Figure I. 12 :

 12 Figure I.12: Illustration of molecular flash-like memory concept. The conventional floating gate architecture (Left) consists in a charge storage center with a channel linker and controlled by the gate polarization (Central picture). With molecular approach this could be practically realized by using Redox molecules grafted on the substrate (Right) [Pro11].

  Figure I.14: (a) Side view cross section of the device that was tested. (b) A drawing of the rotaxane molecule used here. (c) Current-voltage traces for device operation. As prepared, the molecular switches are closed, and the status of the devices is probed by applying a negative voltage to the bottom electrode. The switches are opened by oxidizing the molecules at voltages greater than 10.7 V. Finally, the open switches are again measured at negative bias. The current ratio at 2.2 V between open and closed states is between 50 and 70, depending on the specific device. [Collier99].

FIGURE 15 :

 15 FIGURE 15: (a) Concept of Crossbar architecture for memory using molecular switches where information bit is stored in the resistance of molecules at each intersection of a top and a bottom bit-line (cell size is 4F²). [Luyken03] -Demonstration of rotaxane based molecular crossbar [Green07] (b) Schematic drawing of molecular crossbar with rotaxane molecules. (c) Structural formula of the bi-stable rotaxane used in the crossbar memory. (d) Image of the entire circuit. The array is made of 400 Si bottom nanowires and 400 Ti top nanowires covered by the SNAP template of 400 Pt nano-wires(scale bar is 10 mm). (e) High-resolution SEM of approximately 2,500 junctions out of a 160,000-junction nanowire crossbar circuit (scale bar is 200 nm).

Figure I. 16 :Figure I. 17 :

 1617 Figure I.16: LEFT: Process diagram to create small pitch wires. (A)The GaAs/AlGaAs superlattice, (B) after selectively etching the AlGaAs, (C) metal deposition while tilted at 36°, (D) contact of superlattice onto adhesive layer on silicon, (E) release of metal wires by etching GaAs oxide, and (F) after optional O2 plasma to remove adhesive layer. RIGHT: Electron micrograph of a few hundred Pt nanowire crossbar circuits fabricated by repeating the SNAP process. The crossbars are fabricated from Pt nanowires with pitch ranging from 20 to 80 nm. The central crossbar has a junction density of 5x10 10 cm², and the two crossbars to the lower left and right of the central one are at a junction density of 10 11 cm². Scale bar is 500 nm.[Melosh03]

  Figure I.18: (a) Schematic cross-section of a single cell including the corresponding circuit diagram (The molecular junction is modeled by a resistive switch in series with a resistor), SEM image of crossbar array with gold top electrode (vertical) and the silicon bottom electrode (horizontal) and cross-sectional TEM image of the gap area(2.5 nm high and 89 nm deep). (b) Simulated scaling behavior of the presented device. The current levels are well separated between the device without molecules (purple/no marker), the ON state (blue/cross), the OFF state with ratios of 1:10 (red/circle) and 1:100 (green/square).[Ruttkowski05]

Figure I. 19 :

 19 Figure I.19: Schematic circuit diagrams for (a) a typical 1T1C FeRAM cell and (b) a simple cross-point matrix array of FeRAM cells. (c) Charge displacement-electric field (D-E) hysteresis loop and ferroelectric capacitor polarization conditions. (d) Schematic of Chemical structure for poly(vinylidene fluoride) trifluoro-ethylene (PVDF-TrFE) copolymer[Ling08].

Figure I. 20 :

 20 Figure I.20: (a) Schematic of F8T2 floating gate memory transistor and the charge-trapping mechanism in Au NPs. (b) Transfer characteristics of F8T2-OFET devices with different Au thicknesses. [Baeg10].

FerroK.Figure I. 21 :

 21 Figure I.21: Devices for organic thin film resistive approach: Left illustration on ferroelectric diode [Asadi08], Right Illustration of polymer and small molecules resistive memories [Park09].

Figure I. 22 :

 22 Figure I.22: Statistics of publications and citations on organic and polymer memories during 1970-2007. Data derived from (a) ISI Web of Science (1980-April 31, 2007), (b) Engineering village (1899-April 31, 2007), (c) ScienceDirect (1823-April 31, 2007) and (d) SciFinder Scholar (2007). Duplicated records have been removed. The inset citation report is from ISIWeb of Science (updated on May 11, 2007) [Ling08].

Figure I. 23 :

 23 Figure I.23: Device size reduction forecast for conventional memory device regarding exponential scaling law [Buckley09] [ITRS09].

Figure I. 24 :

 24 Figure I.24:Forecast for emerging organic electronic market.[Jamet11]

Figure I. 25 :

 25 Figure I.25: (a) Schematic of chemical elements employed in [LinHT]. (b) Example of organic composition structure: Stacked [Bozano05], Blended [ChoSH09] and Chemically Linked [Ling07].

Figure I. 26 :

 26 Figure I.26: Left: SEM image of defect on the top electrode after 4000 cycles (scale bar represents 50 µm). Right: A cross-sectional view of device showing irregularities of the electrode [Kwan10].

  Figure I.27: (a) Chemical structure of photo cross-linkable polymer PFN-C employed for lift-off processing of 4 µm x 4 µm memory devices [Kwan07]. (b) Fabrication process for organic crossbar memory devices using the Direct Metal Transfer method [KimTW08]. (c) Schematic and SEM picture of a polymer memory device in a via-hole structure [KimTW09].

Figure I. 28 :

 28 Figure I.28: (a) Principal arrangement of 3D stacked organic memory [Pinnow04]. (b) Perspective view and electrical I-V characteristics of vertically double stacked small-molecule nonvolatile 4F² memory cell memory [Park09]. (c) I-V characteristics of the double-stacking memory device and typical device structure for multistack memory array [Kwan07]. (d) Schematic illustration of a 3D-stacked organic resistive memory assembly featuring an 8 × 8 crossbar structure. A total of 192 cells were produced in three active layers sandwiched between pairs of Al electrode layers. (Cured PI and PCBM used as the memory material) [Song10].

Figure I. 29 :

 29 Figure I.29: (a) Illustration of the 3D stacked memory assembly (left) and statistical distribution of the memory-operative cells (red) and the electrically shorted cells (black) in each active layer (right). (b) Cumulative probability data for all operative cells (160 operative cells out of 192 fabricated cells) (c) Statistical distribution of the threshold voltages of the operative cells in each active layer. [Song10]

Figure I. 30 :

 30 Figure I.30: (a) Electrical characteristics of small molecules based organic devices with embedded metal nanocrystals (Al/Alq3/NiO/Ni/NiO/Alq3/Al). (a) I-V characteristic after different programming sequences (b) Data-Retention characteristics after programming in four different conditions [Park09].

Figure I. 31 :

 31 Figure I.31: Pulses of 300 ns and 500 ns used to switch the device in on state (a) and off state (b). (c) Current transient response with a read pulse of 0.6 V. The two states can be differentiated in less than 500 ns [Kwan07]. (d) Delay time observe in Write-read-erase-read cycles in the pulse operation [Joo08].

Figure I. 32 :

 32 Figure I.32: (a) Schematic of chemical structure for Rose-Bengal molecules (RB) in different conformations [Pal04]. (b) Schematic of chemical reaction potentially involved in resistive switching of Cu-TCNQ organometallic films [Müller06]. (c) Schematic of Energy-level diagram and electron transfer from 8HQ to the core of the gold nano-particle [Ouyang10]. (d) Molecular structure of PVK-C60 Donor-Acceptor polymer and plausible electronic process producing the memory effect [Ling07].

Figure I. 33 :

 33 Figure I.33: Schematic illustration of the formation of (a) carbon-rich filaments and (b) metallic filaments, and the relevant switching effects [Ling08].

Figure I. 34 :

 34 Figure I.34: Formation of metal filament within polymer layer: (a) device structure, (b) ionization & drift of Copper with positive voltage, (c) metal filament formation by the reduction of copper ions, and (d) the breakdown of copper filament by joule heating [Joo07].

Figure I. 35 :

 35 Figure I.35: (a) I-V characteristics of the Al/PVK:Au NPs (120 nm)/Al devices in unipolar switching [LaiPY11].(b) Unipolar DC switching behavior of a single Pt/AlOx/TiN memory cell [WuY11].

Figure I. 36 :

 36 Figure I.36: Schematic illustration of resistive switching mechanisms possible in organic based devices.

Figure I. 37 :

 37 Figure I.37: Overview on studies for (PMMA:C60) nanocomposite characterization

  Development of (PMMA:C 60 ) nano-composites II.1.1 Materials & Components description II.1.1.a Introduction to Composite materials

  Initial materials considered for mixture. C: New material product of the reaction JUXTAPOSITION Initial materials considered for mixture. (A:B): Composite material II.1.1.c Poly-methyl-methacrylate (PMMA) Insulating Polymer matrix The insulating polymer chosen for nanocomposite organic matrix is Poly-(methyl methacrylate) (PMMA) polymer. The PMMA is obtained from synthetic polymerization of the methyl-methacrylate (MMA) monomer displayed on figure II.1a.

  FIGURE II.1: (a) Schematic of chemical structure for methyl-methacrylate (MMA) monomer and its polymerization (PMMA) (b) Illustration of PMMA use as e-beam resist for nano-patterning application. (c) Illustration of PMMA used as insulating polymer dielectric in organic transistor fabrication [Huang08].

ρ:

  C60 Doping ratio defined as the mass ratio of C60 over PMMA m C60 : Total mass amount of C60. m PMMA : Total mass amount of PMMA.

FIGURE II. 3 :

 3 FIGURE II.3: Nanocomposite elaboration process.

  w

FIGURE II. 4 :

 4 FIGURE II.4: Schematic of process used in nanocomposite solution fabrication.

FIGURE II. 5 :

 5 FIGURE II.5: AFM 3D picture and z-profile on pure PMMA (PM00: PMMA:C60-ρ=0wt%) and highly doped PMMA (PM20 : PMMA:C60 -ρ=20wt%). The scan area is 5 µm x 5 µm.

  FIGURE II.6:RMS roughness extraction from AFM picture for different C60 loading rate ranging from pure PMMA (PM00: PMMA:C60 -ρ=0wt%) to highly doped PMMA (PM20 : PMMA:C60 -ρ=20wt%).

FIGURE

  FIGURE II.8: (a) Glass Transition Temperature (Tg) obtained by Differential Scanning Calorimetry (DSC) for different material compositions. b) DSC signal for PMMA:(C60) with r=0;2;5;10;20 wt%.

FIGURE II. 9 :

 9 FIGURE II.9: (a) Thermo-Gravimetric Analysis (TGA) of pure PMMA (Black) and Highly doped PMMA:C60 (ρ=20wt%). An improvement is observed on Thermal degradation temperature (Td) with C60 inclusion.

  FIGURE II.10: (a) Refractive index (n) and (b) Extinction coefficient (k) spectra on (PMMA:C60) films with different doping ratios (ρ=0; 2;5;10; 20 wt%).(c) Extinction coefficients at 261nm as a function of weight ratio of (C60) introduced in solution if linear dependence is considered.

FIGURE II. 11 :

 11 FIGURE II.11: Schematic of ToF-SIMS Analysis principle and A-Overall surface mass spectrum of a PMMA -10 wt% (C60) blend obtained with 25 keV Bi3+. Primary ion dose is 1×10 12 ions/cm2. B-Low mass zone of the spectrum, from m/z = 0 to 105. C-Mid-mass zone of the spectrum, from m/z = 105 to 550. D-High mass zone of the spectrum, from m/z = 550 to 800. [Py10]

FIGURE

  FIGURE II.12: (a) Detailed ToF SIMS ambient temperature (25°C) profile of a PMMA:(C60) with 10wt% of (C60). (b) Intensity ratios obtained with ToF-SIMS plotted against expected (C60) composition of the material.

  FIGURE II.13:Pictures of e-Beam patterned (PMMA:C60) film with ρ =10wt% of (C60) with 660µC/cm 2 : (a) 3D AFM picture on 200 nm pitch pattern. (b) SEM picture on 50 nm line / 50 nm space patterns;

  FIGURE II.14: (a) Schematic of nano-imprint process. (b) SEM picture after NIL Patterning of 250nm width line on (PMMA: C60) film with ρ=10wt% of (C60).

  FIGURE II.16:Optical microscopy picture of samples after the thermal annealing of (a) pure PMMA (b) doped PMMA with ρ=20wt% of (C60) (scale bar is 2µm).

FIGURE II. 18 :

 18 FIGURE II.18: Schematic of test structure employed in scaling studies with Top Pad sizes ranging from 1mm to 150µm and Bottom Plug diameters from 1.8µm to 300nm. Inset: SEM image of 300nm Bottom Plug device.

FIGURE II. 20 :

 20 FIGURE II.20: Integration of encapsulated polymer resistive cell in high-density crossbar architecture.

  FIGURE II.B.1:Process flow for Si-Shadow mask fabrication (These fabrication steps were realized on 4'' wafer on the PTA platform www.pta-grenoble.com).

FIGURE II.B. 1 :

 1 FIGURE II.B.1: Picture of 4'' inch silicon shadow masks: (a) Macro-sized circular pattern (500 to 150 µm in diameter) and (b) Macro top rectangular electrode (100 µm x 1800 µm) for realization of top electrode on device with scaled bottom electrodes (300 nm -1.8 µm).

  PMMA:C 60 ) IN MOIS STRUCTURES ........................................................................... 65 III.1 Introduction to C-V Characterization on MIS.................................................................. 67 III.1.1 Interest of MIS structure for (PMMA:C60) characterization ..........................................................67 III.1.2 Electrical C-V behavior for ideal MIS structure.................................................................................67 III.1.3 C-V characteristics for Non-ideal MIS Structures .............................................................................70 III.2 Characterization of PMMA in MOIS devices ................................................................... 73 III.2.1 Structure for charge trapping analysis ..................................................................................................73 III.2.2 C-V Characterization of PMMA reference devices ...........................................................................73 III.2.3 Conclusion for PMMA reference device .............................................................................................79 III.3 Charge trapping memory effect controlled by C60 doping .............................................. 80 III.3.1 Hysteresis on C-V characteristics with C60 doping ..........................................................................80 III.3.2 A charge trapping related mechanism ..................................................................................................81 III.3.3 Time-Voltage Dependence ....................................................................................................................83 III.3.4 Conclusions & Perspectives...................................................................................................................84 III.4 Conclusions of Chapter III .................................................................................................. 85 Appendix III.A: Inversion ratio with lateral Fictive source drain ........................................... 86 III.1 Introduction to C-V Characterization on MIS III.1.1 Interest of MIS structure for (PMMA:C60) characterization

FIGURE III. 1 :

 1 FIGURE III.1: (a) Schematic of M-I-S structure (b) Equivalent capacitance circuit for C-V characterization of ideal MIS structure.

FIGURE III. 2 :

 2 FIGURE III.2:Energy Band diagram for ideal MIS at the equilibrium (VG=0;Fermi level aligned)-In metallic electrode the energy of carrier corresponds to the Fermi level (EF) and is defined from vacuum level by metal work-function (ΦM). The ideal insulator is defined by its thickness and electron affinity (χI). Finally the semiconductor is described from its electron affinity (χS), its energy band-gap (EG) positioning conduction band (EC) intrinsic level (EI) and valence band (EV) and the position of Fermi level (EF). The position of Fermi level in semiconductor is defined directly from the semiconductor work function (ΦSC) or either from the Fermi potential (ψBp) characterizing the energy shifting from intrinsic level (EI) introduced by the doping.

n p0 :

 p0 Electron densities at the equilibrium p p0 : Holes densities at the equilibrium ψ BP: Fermi potential k.T: Boltzman constant-Temperature product (3.2) However, with voltage polarization, the electric field distribution on the insulator and semiconductor will distort the energy band distribution at the semiconductor interface and impact the carrier density as illustrated on the different band diagrams figure III.3. Depending on the voltage applied to the gate (VG), four electrical configurations in the semiconductor could be identified: ACCUMULATION, FLAT-BAND, DEPLETION and INVERSION.

FB

(

  ε sc : Insulator and semiconductor permitivity d: Insulator thickness N A: Density of ionized Acceptors k.T: Boltzman constant-Temperature product t (3.3) III.1 -INTRODUCTION TO C-V CHARACTERIZATION ON MIS -69-Semiconductor Devices, 2/E by S. M. Sze Copyright © 2002 Wiley & Sons. Inc. All Rights Reserved)

FIGURE III. 3 :

 3 FIGURE III.3: (a) Band diagrams and (b) schematic of charge distribution in the stack for the different polarization regime in the case of P-Type ideal MIS structure.

FIGURE

  FIGURE III.4: C-V behavior for ideal P-type MIS device considering different frequencies: (a) Low (b) Intermediate and (c) High Frequencies.

FIGURE III. 5 :

 5 FIGURE III.5: Band diagram for P-Type MIS structure. (a) Flat band for VG=0 on ideal structure (ΦM = ΦSC) (b) Band bending for VG = 0 with non-ideal gate (ΦM ≠ ΦSC). (c) Flat band configuration when a voltage shift is applied to compensate the work function difference (ΦMS).

FIGURE III. 6 :

 6 FIGURE III.6: Band diagram for P-Type MIS structure. (a) Flat band for VG=0 on ideal structure (QI = 0) (b)

FIGURE III. 7 :

 7 FIGURE III.7: Schematic of equivalent circuit, taking into account interfacial defects, (Dit).

  FIGURE III.8: Impact of non-ideality on C-V characteristics. (a) Voltage shift of the characteristics with metallic gate and charged insulator. (b) Frequency distortion brought with interfacial defects.

FIGURE III. 9 :

 9 FIGURE III.9: Schematic of MOIS structure with blocking oxide and inert electrodes

  FIGURE III.11: (a) Frequency dependency of the C-V characteristic for 0.21mm² devices swept from inversion (+8V) to flat-band region (-4V) and swept back to inversion. (+8V) (b) Inversion ratio (CINV/CI) consisting in inversion capacitance over the full stack capacitance versus applied frequency for both experimental data and simulated data on equivalent SiO2 structure.

FIGURE III. 14 :FIGURE III. 15 :

 1415 FIGURE III.14: Picture of considered devices with different gate areas and corresponding C-V characteristics at 100 kHz

FIGURE

  FIGURE III.16: C-V characteristics at 1kHz for 3 subsequent cycles when the device is swept from Inversion (+20V) to variable Accumulation voltage (VACC) and back to Inversion (+20V).

FIGURE III. 18 :

 18 FIGURE III.18: Schematic of M-O-I-S structure under study with PMMA thin film doped with of 0, 5, 10, 20 wt% of C60.

  FIGURE III.19: C-V Measurements swept from Inversion (+9V) to Accumulation (-14V) at 1 MHz for MOIS capacitors with different weight ratios of C60 in PMMA (ρ = mC60/mPMMA). (a) ρ =0% -PMMA only (b) ρ =5% (c) ρ =10%.

FIGURE

  FIGURE III.20: C-V Measurements: (a) Extraction of Flat band voltage windows and (b) corresponding planar charge density from C-V characteristics obtained over [+15V;-15V;15V] at 1 MHz.

FIGURE

  FIGURE III.22 Schematic band structure for MOIS device in (a) ACCUMULATION and (b) INVERSION regimes (arbitrary thickness and band level).

Flat

  FIGURE III.23: (a) Electrical results for a Stress-C-V sequence on PMMA with ρ =5wt % with -20V voltage stress with pulses from 100µs to 5s. (b-c-d) Time-Voltage characteristic respectively for PM00, PM05 and PM10.

  IN (PMMA:C60) WITH INERT ELECTRODES. ............................... 87 IV.1 Resistive behavior of (PMMA:C60) layers in MOM Structures....................................... 89 IV.1.1 Screening for Current hysteresis............................................................................................................89 IV.1.2 Conditions for Hysteresis and NDR behavior ...................................................................................92 IV.1.3 Negative Differential Resistance behavior ..........................................................................................93 IV.1.4 Conclusions on the electrical behavior of (PMMA:C60) layers with Platinum electrodes...........94 IV.2 Memory Operation for NDR based devices...................................................................... 95 IV.2.1 Unipolar Multilevel Memory Effect .....................................................................................................95 IV.2.2 Low field stability and Data Retention.................................................................................................97 IV.2.3 DC Memory cycling.................................................................................................................................97 IV.2.4 Reproducibility and variability ...............................................................................................................98 IV.2.5 Pulse programming & Endurance.......................................................................................................100 IV.2.6 Electrode Area Downscaling ...............................................................................................................103 IV.2.7 Conclusion and Overview on performances.....................................................................................105 IV.3 Detailed Characterization for behavioral understanding ............................................... 106 IV.3.1 Identification of device behavior ........................................................................................................106 IV.3.2 Quasi-static Forming and Negative Differential Resistance ..........................................................106 IV.3.3 On Multilevel Steady States..................................................................................................................108 IV.3.4 Details of switching transitions ...........................................................................................................111 IV.3.5 Quasi-static description of device operation.....................................................................................112 IV.3.6 Conclusions and Perspectives..............................................................................................................116 IV.4 Conclusions of Chapter IV................................................................................................. 117 Appendix I.A: Equivalent Circuits For quasi-static behavioral modeling............................ 119

  FIGURE IV.1: Unipolar increasing sequences (positive and negative reported in the same graph) for (a) Pure PMMA (ρ=0wt%) and (b-cd-e) (PMMA:C60) with respectively ρ=2,5,10,20wt%.

FIGURE IV. 2 :

 2 FIGURE IV.2: Impact of thermal annealing 30min at 180°C on the current-voltage characteristics for different doping conditions (a) Pure PMMA (ρ=0wt%) and (PMMA:C60) with (b) ρ=5wt% and (c) ρ=20wt%.

FIGURE IV. 3 :

 3 FIGURE IV.3:Unipolar current-voltage characteristics (positive and negative sweeps reported on same graphs), for samples annealed at 180°C during 30 min.

  FIGURE IV.4:Current-Voltage (I-V) characteristics of devices considering different organic layers : doped PMMA with ρ=10wt% without any specific thermal annealing and pure PMMA and doped PMMA (ρ=10wt% ) thermally treated at 180°C during 30min.

  FIGURE IV.5:Progressive opening of the hysteresis on reverse sweep with subsequent sequences and increasing maximum voltage biased.

  VNDRmax↔VNDRmin]. Several subsequent double sweep sequences have been monitored in positive and negative voltage and the results reported respectively on figure IV.6a-b show a very reproducible and symmetrical behavior

FIGURE IV. 6 :

 6 FIGURE IV.6: Reproducible and symmetrical quasi-static NDR behavior on 5 subsequent double sweep measurements [0 Vsw 0V] measured with (a) Positive voltage Vsw =+8V and (b) Negative voltage Vsw=-8V. (Sweep rate = 1V/s)

FIGURE IV. 7 :

 7 FIGURE IV.7: (a) High resistance state (HRS) programming at low field with I-V single sweep sequences stopping in NDR region [0→VNDR=+8V]. (b) Alternating single sweep I-V sequences in both polarities.

FIGURE IV. 8 :

 8 FIGURE IV.8: Extraction of Characteristic parameters upon successive I-V single measurements in both polarities [0;+6V] and [0;-6V]. Left: Current level extracted at 1V. Right: switching voltage.

FIGURE IV. 9 :

 9 FIGURE IV.9: Multi Level Conductance after polarization in NDR region at different programming voltages (Vp).

FIGURE IV. 10 :

 10 FIGURE IV.10: Schematic diagram of the data-retention experiment (Left) and stacked I-V sequences monitored over 10 4 s for a device programmed in High Resistance State (HRS).

FIGURE

  FIGURE IV.11: (a) Left: Continuous Data-Retention for devices programmed at three different levels (Vp = 2V; Vp=6.5V; Vp= 10V). (b) Right: Data-Retention monitored at five different levels over three days.

FIGURE IV. 12 :

 12 FIGURE IV.12: (a) Programming scheme for DC cycling. (b) 125 subsequent Program/Erase cycles: SET = [0V→-8V→0V]; RESET = [0V→10V]

  FIGURE IV.13: (a) Extraction of ON (Red square) and OFF (Blue circle) currents at 0.3 V over 590 Program / Erase endurance cycles.(b) Cumulative MISSET failures upon cycles (inset: typical MIS SET I-V sequence).

FIGURE IV. 14 :

 14 FIGURE IV.14: Cycle-to-Cycle statistics on (a) High and Low resistive State current levels and (b) switching voltages over 590 DC cycles (SET: [0V→-8V→0V]; RST [0V→+10V]).

FIGURE IV. 15 :

 15 FIGURE IV.15: Stacked I-V characteristics for 50 devices each programmed in 3 different levels: (a) Low Resistive state (b) Medium Resistive state and (c) High Resistive state respectively programmed with Vprog=2/4.5/8V). (d) Device-to-device statistical distributions on three different levels for the 50 devices.

MRSFIGURE

  FIGURE IV.-16: (a) From HRS the pulse amplitude should overcome the switching Voltage (Vsw = 4V for HRS) leading to a Medium Resistive State (MRS). The lower Vsw for MRS (2.6V) enabled a second programming pulse at 2.75V to reach a LRS. (b) Double pulse programming scheme for memory windows enlarging or multilevel operation (c) Pulse programmed cycles with the use of a second SET pulse to enable programming from HRS to LRS and enlarge the memory window for multilevel operation. (d) Schematic of test bench used for pulsed programming.

FIGURE IV. 18 :

 18 FIGURE IV.18:Cell endurance characteristics up to 128k cycles programmed with pulses of 3.35V; 100ms for SET and -6.5V; 50 µs for RESET operation.

  T = P u ls e 3.3V 100 m s R E S E T = P ulse -6.5V 50 µ s R ea d V oltag e = 0.3 V d = 2 5 0 µm

FIGURE IV. 19 :

 19 FIGURE IV.19: Schematic of (a) Macro-size devices with full sheet bottom electrode and (b) sub-micron-size devices with downscaled Bottom PLUG electrode (c) Scanning Electron Microscope picture of 300nm device.

FIGURE

  FIGURE IV.21: (a) Dependence of current level in LRS and HRS region versus cell area. The lowering of HRS level increases the memory windows.(b) I-V Unipolar multilevel operation of 700nm cell. Six Different levels were programmed through NDR polarization.

FIGURE IV. 22 :

 22 FIGURE IV.22: Schematics of electrical behavior zoology in Polymer Resistive memory with NDR. We can point out quasi-static states (PRISTINE, NDR, STEADY STATE) and irreversible transitions (FORMING, SWITCHING).

  FIGURE IV.23 : Influence of (a) measurements (delay time) and (b) external parameters (light) on the Pristine Forming and resulting NDR with identical sequences ([0 15V 0]). (c) Influence of maximum Forming Voltage reached (VFORMING) on the resulting NDR Shape.

FIGURE IV. 24 :

 24 FIGURE IV.24: Stability of Negative Differential Behavior over 80 double sweep measurements with alternated polarities. ([0 +/-12V 0])

  FIGURE IV.25: Influence and reproducibility (over 4 sequences) of voltage programming in NDR on the subsequent Low Field Resistance.

  Current and Volatge K,k , : Conduction coefficient dependent on programming votage (weakly sensitive to temperature)

FIGURE IV. 26 :

 26 FIGURE IV.26: (a) I-V multilevel characteristic in Log -Log Scale. At low voltage I-V could be fitted with I#V law then I#V α before Switching Voltage.(b) Progressive evolution of slope (α) with initial resistance considering I#V a fitting before switching voltage (0.5-1.5V) for different resistive states.

  Current and Voltage β,α , : Conduction coefficient dependent upon the programming voltage

FIGURE IV. 27 :

 27 FIGURE IV.27:Fitting with I#V a law of 3 states: High, Medium and Low RS. Set programming conditions (I&V) and the programmed low field state are located on a common I#V a characteristic.

  FIGURE IV.28: (a) Dynamic behavior of the sweep sequence (0V to 7V) at different sweep rates (b) Stability of switching Voltage (Vsw) for different stress times during the sweep -Extracted from IV at different sweep rates on [0-7V].

FIGURE IV. 29 :

 29 FIGURE IV.29: (a) Zoom upon the I-V characteristics in the switching region for 6 resistive levels. (b) Dependence of the Switching Voltage (Vsw) upon the initial Low Field Resistance.

  The current in the Negative Differential Resistance region (NDR) and at Low field Steady State (SST) is ruled out by the same conduction model. This hypothesis is supported by the observations described in ( §IV.3.3.c) where the programmed steady state and programming set points were found to be upon a common characteristic with fixed conduction parameters (α,β)NDR =(α,β)SST

(

  iii) : in NDR (V>VSW) α β V ⋅ = I with (α,β)NDR= f(VPNDR)Hypothesis (iv): When the voltage is abruptly stopped or set-up below the switching voltage, the system remains frozen in the conduction mode set-up by the last polarization in the NDR region.

(

  iv): (α,β)NDR= constant if d(VPNDR)/dt is High IV.3.5.b Simple quasi-static behavioral systems

  FIGURE IV.30: Schematic of parameter interdependence considered for behavioral modeling.

  FIGURE IV.31: Schematic of the parameters interdependence considered for behavioral modeling.

FIGURE IV. 32 :

 32 FIGURE IV.32: Illustration of SPICE elements employed for the implementation of the quasi-static behavioral model and it equivalent electrical circuit (a,b) E and G element implemented for calculation and translation of inter-dependence (c) Capacitor employed for the storage (d) S element employed for switching.

FIGURE

  FIGURE IV.33: (a) Multilevel Current-Voltage characteristics obtained from Experimental characterizations (b) Multilevel Current-Voltage characteristics obtained with transient simulations considering a simple quasi-static behavioral model based on a unique conduction model stated in Eq.IV3.

FIGURE V. 1 :

 1 FIGURE V.1: Schematic of M-i-O-I-M structure in the case of MIM like structure with Aluminum Electrodes.

(

  Figure V.2: Increasing Sequences for I-V hysteresis screening: (a) Unipolar Negative (b) Unipolar Positive and (c) Bipolar. (d) Current levels monitored in positive voltage at different C60 doping conditions.

Sweep 4 :

 4 We observed that alternation of sequences Negative to Positive has induced a modified current behavior on subsequent positive sweeps (see figure V.3c sequence "Positive after Negative"[PN]). It exhibits much higher current than the pristine state observed [00-P0] and displays a Negative Differential Resistance 22 (NDR) behavior.Sweep 5-6: The latest behavior ([PN]) is not stable since a subsequent positive sweep (the 5 th ) displays a third type of behavior in positive voltage with lower current. The new current behavior is stable and reproducible under subsequent positive range (see figureV.3d sequence "Positive after Positive"[PP]).

  FIGURE V.3: I-V characteristics with bipolar sequences [0V +/-15V] on (PMMA:C60; ρ=10wt%) in M-i-O-I-M (a) Pristine (00) and subsequent positive sweep (P0). (b) Subsequent Negative sweep (NP) and its reproducibility (NN). (c) Hysteresis in the positive range, depending upon the previous sequence is negative (PN) or positive (PP). (d) Reproducibility of positive sequence behavior after a positive sweep (PP). (e) Reproducibility of hysteresis from cycle to cycle, consisting in alternating sequences: negative positivepositive negative-positive positive (NP-PN-PP).

V. 1

 1 .3.b Different available conduction modes In the device history, four main current conduction modes could be clearly identified. The corresponding I-V characteristics are plotted in figure V.4a. Positive Initial Resistive State (p-IRS): It corresponds to the current behavior on the first positive sweep for a pristine device and on the subsequent sweep in positive range (Sequences 00 and P0).

  FIGURE V.4: (a) Plotted I-V characteristics reported in absolute voltage scales for the four different electrical configurations [0V +/-15V] : Positive Initial Resistive State (p-IRS), Negative Resistive State (n-RS), Positive Low Resistive State (p-LRS) and Positive High Resistive State (p-HRS). (b) Schematic of hysteresis with typical I-V current behavior in MiOIM structure and identification of characteristic parameters for comparison study.

FIGURE V. 5 :

 5 FIGURE V.5: Schematic of the fabricated devices for doping influence analysis and corresponding Electrical bipolar I-V characteristics (two subsequent cycles composed of W/R-E/R sequences corresponding to NX-PN and NP sweeps [0V +/-15V])for three devices with different doping conditions: (a) Reference device -PMMA only (ρ = 0wt %), (b) PMMA:C60 with ρ = 5 wt%, (c) PMMA:C60 with ρ = 10 wt%.

FIGURE V. 7 :

 7 FIGURE V.7: (a) Programming schematics for Read disturbances study in three steps: Write (W), variable Read Disturb (RD) and full Read-Erase (R-E) sequences to monitor the disturb of previous Read Disturb sweep (RD) (b) Electrical I-V characteristics for Read-Erase sequences after the appliance of various Read Disturb.

  (In Disturb Sequence (2)) After Read (After Disturb Sequence(3)) V RD (V) (c) Extraction of current level at 1V after Write and after Read Disturb sequences (VW = -15, ION/IOFF ~ 11).

FIGURE V. 8 :

 8 FIGURE V.8: Impact of progressive increase of the WRITING voltage (VW) upon the subsequent positive sweep considering a pristine device. Three different main configurations could be observed (a) Increase of sub-peak current with Low Field programming. (b) Decrease of post-peak current with writing at medium field. (c) Increase of post-peak current with high field programming.

FIGURE V. 9 :

 9 FIGURE V.9: Stress time effect in WRITING process under -15V pulses: (a) Schematic of algorithm involved for experiment (b) Progressive evolution of current behavior in positive range after negative programming with -15V stress.

FIGURE V. 10

 10 FIGURE V.10Extraction of current level at 2.5 V (around VMAX) after writing with different pulse length

  FIGURE V.11: (a) Electrical bipolar I-V characteristics on [0V;+/-15V] for three devices made of PMMA:C60(ρ= 10wt %) with different top electrode areas. (b) Current and (c) Current density extractions for the four different resistive states (RS) regarding the device Area (extracted at 1V from I-V characteristics with [0V +/-15V] sweeps).

  FIGURE V.13: (a) Maximum current peak voltage extracted upon the organic layer thickness. (b) Normalized critical field at the Maximum current peak voltage upon the organic layer thickness.

Alternative

  Characterization on (PMMA:C60) without thermal annealing above Tg : Material characterization ( §II.3), Electrical characterization in MOIS ( §II.4) & MIM with inert electrodes ( §IV.1).

FIGURE V. 15 :

 15 FIGURE V.15: Schematic of the bottom interface of M-i-O-I-M devices with (PMMA:C60) organic layers with oxidized and field induced motion of oxygen vacancies.

FIGURE V. 16 :

 16 FIGURE V.16: (a) experimental IV characteristics of bipolar hysteresis.(b) simulated I-V characteristics for bipolar switching according to Strukov's model.[Strukov08]

FIGURE V.A. 1 :

 1 FIGURE V.A.1: Cross-section picture of M-O-I-S devices with PMMA thin film obtained in through spincoating in different solvent conditions.

Figure VI. 1 :

 1 Figure VI.1: Classification des technologies mémoires suggérées par le consortium de l'ITRS (International Technology Roadmap for Semiconductors) [ITRS10].

Figure VI. 2 :

 2 Figure VI.2: Exemple de structure pour les dispositifs organique: Empilement [Bozano05], Composite [ChoSH09] et polymère fonctionnalisé [Ling07].

Figure VI. 4 :

 4 Figure VI.4: Caractéristiques électriques d'une cellule mémoire à base de petites molécules empilées (Al/Alq3/NiO/Ni/NiO/Alq3/Al) [Park09] (a) Caractéristiques Courant-Tension (I-V) multi-nivaux après différentes séquences de programmation. (b) Caractéristiques de rétention des courants programmés.

Figure VI. 3 :

 3 Figure VI.3: Illustration de matrices mémoires résistives cross-bar empilées (192 cellules) [Song10].

[ Vilkman09 ,

 Vilkman09 ChoB10 and Heremans11].

Figure VI. 5 :

 5 Figure VI.5: Illustration des phénomènes physiques suggérés pour la commutation résistive.

Figure VI. 6 :

 6 Figure VI.6: Illustration schématique des caractérisations menées sur le composite (PMMA:C60)

  FIGURE VI.7: (a) Structure chimique du polymère de PMMA. (b) Représentation de la structure géométrique d'une molécule de fullerène C60.

VI. 2 . 2

 22 Caractérisation physico-chimique des couches (PMMA :C60) VI.2.2.a Caractéristiques physiques des couche minces ρ: C60 Doping ratio defined as the mass ratio of C60 over PMMA m C60 : Total mass amount of C60. m PMMA : Total mass amount of PMMA.

FIGURE VI. 8 :

 8 FIGURE VI.8:Image TEM en coupe des couches minces avec différentes concentrations de fullerène (ρ = 0, 5, 10 wt %).

FIGURE VI. 9 :

 9 FIGURE VI.9: (a) Températures de transition vitreuse pour différentes concentrations de C60 obtenues par calorimétrie différentielle DSC. (b) Analyse thermogravimétrique (TGA) avec et sans présence de C60.

FIGURE VI. 10 :

 10 FIGURE VI.10: (a) Spectre du Coefficient d'extinction coefficient (k) sur les couches (PMMA:C60) avec différents dopages (ρ=0; 2;5;10; 20 wt%).(b) Coefficient d'extinction à 261nm en fonction du ratio de C60 introduit. (c) Profils ToF-SIMS à température ambiante sur PMMA :C60 avec ρ=10wt%. (d) Ratio des intensités des signaux relatifs au C60 et MMA en fonction de la concentration de C60 introduite.

VI. 3 . 2 FIGURE VI. 16 :

 3216 FIGURE VI.16: Caractéristiques C-V sur les dispositifs de référence (surface~0.18mm²) polarisés de l'inversion (+8V) à l'accumulation (-8V) avec retour en Inversion (+8V) à faible et haute fréquence respectivement (a) à 1 kHz et (b) à 1 MHz.

FIGURE VI. 17 :

 17 FIGURE VI.17: (a) Ratio d'inversion (CINV/COX) en fonction de la fréquence pour les mesures expérimentales et résultats typiques pour un système équivalent à base d'oxyde de silicium. (b) Ratio d'inversion (CINV/ COX) pour des dispositifs de surfaces variables.

  [Nicollian65, 82] . Dans ce model, Nicollian suggère que les porteurs minoritaires sont attirés à l'interface du semi-conducteur par des charges de signes opposés fixes stockées dans le diélectrique. Dans ces conditions il va se créer une couche d'inversion permanente qui va interférer avec le

FIGURE VI. 18 :

 18 FIGURE VI.18:Illustration du fonctionnement du dispositif en considérant le PMMA comme isolant positivement chargé-Attirée par les charges positives du PMMA, une couche d'électrons permanente autour de la grille fournit un réservoir de charges pour l'inversion partielle ou totale de la zone désertée.

FIGURE VI. 21 PM00:Flat

 21 FIGURE VI.21 Diagramme de bande schématique pour la structure MOIS en régime (a) d'accumulation et (b) d'inversion (épaisseur et énergie de bande arbitraires).

Flat

  PMMA:C60 ρ=10 wt%

VI. 4 FIGURE VI. 23 :

 423 FIGURE VI.23: Caractéristiques courant-tension (I-V) et claquages pour plusieurs concentrations (ρ=0, 5,20wt%) et conditions de recuit (bleu : 120°C/120s et orange :120°C/120s+180°C/30min).(NB : Pour chaque échantillon plusieurs dispositifs (~10) ont été mesurés dans les deux polarités.)

  Sweep 6 [0V >-8V >0V] Sweep 7 [0V >-8V >0V] Sweep 8 [0V >-8V >0V] Sweep 9 [0V >-8V >0V]

FIGURE

  FIGURE VI.25: (a-b) Comportement quasi-statique de RDN reproductible et symétrique sur 5 cycles allerretour successifs [0 Vsw 0V] respectivement en tension positive (a-Vsw =+8V) et négative (b-Vsw=-8V). (c) Programmation d'un état haute résistance avec arrêt de la mesure dans la zone RDN. (d) Programmation de résistances multi-niveaux suivant le point de polarisation finale dans la zone RDN.

  FIGURE VI.26: (a) Rétention d'information mesurée pour trois niveaux de programmation (Vp = 2V; Vp=6.5V; Vp= 10V). (b) Reproductibilité cycle-àcycle pour 125 séquences successives d'écriture/effacement: en DC (SET = [0V→-8V→0V]; RESET = [0V→10V]) (c) Variabilité Dispositifs-à-dispositifs -Distribution statistiques des courants programmés sur trois niveaux pour 50 dispositifs.

  Les caractéristiques obtenues pour 125 cycles d'effacement/écriture reportées sur la figure VI.26b montrent une bonne reproductibilité du comportement. Ce type de caractérisation a de plus permis d'étudier la variation cycle-à-cycle des caractéristiques typiques : courant des états Haute résistance /Basse Resistance et tension de basculement (Voir détails au §IV.IIIxx). Finalement il est également primordialement que les différents dispositifs fabriqués présentent des caractéristiques semblables. L'étude préliminaire dont les résultats sont reportés sur la figure VI.26c a consisté à programmer 50 dispositifs différents dans trois états distincts -175-sans aucun algorithme de contrôle 31 a permis de montrer une bonne distinction des états programmés sur l'ensemble des dispositifs. VI.4.2.c Caractéristiques mémoires avancées Afin d'être compétitifs sur le plan technique une technologie mémoire doit également garantir plusieurs critères : rapidité de programmation, durée de vie élevée, compatibilité d'intégration et haute densité d'information.

  FIGURE VI.27: Illustration des cellules employées pour l'étude de miniaturisation (a) Dispositifs macroscopiques avec électrode inférieure commune (b) dispositifs submicroniques avec électrode inférieure à diamètre variable (c) Image par microscopie électronique d'un point mémoire 300nm. (d) Niveau de courant dans les états haute et faible résistance en fonction de la surface des dispositifs.

FIGURE VI. 28 :

 28 FIGURE VI.28: Caractéristique schématique du comportement électrique des cellules mémoires résistives à base de Résistance différentielle négative (RDN). La zoologie de comportement comprend des états quasistatiques (ETAT INITIAL, RDN et ETATS STABLES) et transitions irréversibles (PREFORMAGE, BASCULEMENT)

  FIGURE VI.29 :Influence des conditions de mesures sur la caractéristique courant -tension : I-V : (a) Impact de la durée de temporisation entre les points de mesure (b) Impact de la tension maximale du cycle de préformage

FIGURE VI. 31 :

 31 FIGURE VI.31: (a) Caractéristique I-V multi-niveau en échelle Log -Log S -La courbe peut être approximer par une de type loi I#V à très faible tension et une loi I#V α avant le basculement.(b) Evolution progressive de la pente (α) sous le seuil de basculement (0.5-1.5V) en fonction de la résistance initiale programmée.

  FIGURE VI.32: Superposition des caractéristiques I-V mesurées, des points de programmations correspondants dans la RDN et des approximations suivant une loi de type I#V a pour 3 états résistifs distincts : Haute, Medium et Faible résistance.

FIGURE VI. 33 :

 33 FIGURE VI.33: (a) Stabilité de la tension de basculement extraite pour des séquences [0V>7V] en fonction de la vitesse de rampe (b) Evolution de la tension de basculement en fonction de la résistance initiale programmée.

FIGURE VI. 34 :

 34 FIGURE VI.34:Illustration schématique de l'interdépendance des paramètres considérée pour la modélisation quasi-statique.

FIGURE

  FIGURE VI.35: (a) Caractéristiques I-V multi-niveaux obtenues des mesures expérimentales. (b) Caractéristiques I-V obtenues par simulation temporelle en considérant un comportement quasi-statique simple tel que décrit sur la figure IV.34 basé sur une loi de conduction décrite par l'équation Eq 6.1.

  Figure VI.36: (a) Séquences I-V bipolaires alternées pour la recherche d'hystérésis. (d) Niveaux de courant mesurés en tension positive pour différentes conditions de dopage en C60.

FIGURE VI. 40 :

 40 FIGURE VI.40:Influence de la tension de programmation (VW) sur l'allure I-V du cycle positif successif.

FIGURE VI. 41 :

 41 FIGURE VI.41:(a) Impact de la durée des impulsions de programmation à -15V sur le cycle de lecture successif. (b) Extraction du niveau de courant de pic programmé en fonction de la durée d'écriture.

  FIGURE VI.42: (a) Caractéristique bipolaire I-V sur [0V;+/-15V] pour des dispositifs PMMA:C60 (ρ= 10wt %)avec différentes surfaces. Extraction à 1V sur les séquences [0V +/-15V] (b) des courants et (c) des densités de courant en fonction de la surface des dispositifs pour les quatre états résistifs caractéristiques : p-RI (état Résistif Initial en tension Positive), n-R (état Résistif en tension Négative, p-FR (état Faiblement Résistif en tension Positive et p-HR (état Hautement Résistif en tension Positive)

VI. 6 -

 6 CONCLUSION GENERALE ET PERSPECTIVES-189-

Table I .2.

 I

Table I .2: Classification

 I

of main resistive switching behavior.

Table I .3: Non

 I exhaustive list of criteria for memory technologies development

		PROCESS COMPATIBILITY	IMPROVABLE DATA DENSITY
		• Use of materials/ structure	• Scalable solution for scaling
		compatible with application	approach
		process	• Stackable for 3D integration
			approach
	• Low power consumption
	REPRODUCIBILITY	COMPLEXITY	PHYSICAL COMPREHENSION
	• Low or improvable variability in	• Enable low complexity for	• Compression of physical
	devices from cycle-to-cycle.	electrical interfacing	mechanism
	• Low or improvable variability on	• Enable simple device operation.	• Comprehension of Material
	wafer from device to device		influence
			• Comprehension of Structure
			influence
	STABILITY	FABRICATION COST	ENLARGE APPLICATION FIELD
	• High Endurance with Low or	• Low fabrication cost	• Enable new functionalities
	corrigible evolution • Low Read disturbance effect.		• Enables new applicative environment
	• Temperature stability

, ChoSH09]. In our

	experiments, a fullerene solution was obtained by
	dissolving (C60) powder from Sigma Aldrich with high purity in Toluene (2.6 mg/mL).
	(a)	(b)
	~ 0.7 nm
	FIGURE II.2: (a) Schematic of carbon atoms distribution for the fullerene (C60) molecules. (b) Hunckels model
	for (C60) molecules with distinct Highest Occupied Molecular Orbital (HOMO) and Lowest Un-occupied
	Molecular Orbital (LUMO).

Fonctional Obtain PMMA Solution Dissolve C 60 in Solution Mix PMMA & C 60 solution Compensate in solvent PMMA 96K ( in powder) PMMA 950K-A2 (in Anisole) C60 ( in Powder) PMMA dilution conditions

			C 60 Doping ratio
			(ρ)
		PMMA in solution	(PMMA:C 60 ) with
				expected ratio
	Toluene		C 60 in solution
		Parameter description Parameter description	Environnemental / process Environnemental / process	Fonctional
	A 114 A 114	Final polymer to solvent conditions Final polymer to solvent conditions	--		w PMMA/Solvent w PMMA/Solvent
	A 113 A 113	C 60 doping ratio C 60 doping ratio	--		ρ ρ
	A 112 A 112	C 60 dilution conditions C 60 dilution conditions	w C60 (limited by C60 dissolution) w C60 (limited by C60 dissolution)	--
	A 111 A 111	PMMA dilution conditions PMMA dilution conditions	PMMA (limited by PMMA dissolution) w PMMA (limited by PMMA dissolution)	--

C 60 dilution conditions Final Polymer to solvent conditions

	Solution mixing	A 111	Solution mixing	A 113
				Solution mixing A 114
		Solution mixing A 112

Toluene A 11 (PMMA:C 60 ) solution with targeted doping ratio (ρ) and polymer to solvent condition Obtain PMMA Solution Dissolve C 60 in Solution Mix PMMA & C 60 solution Compensate in solvent PMMA 96K ( in powder) PMMA 950K-A2 (in Anisole) C60 ( in Powder) PMMA dilution conditions

		C 60 Doping ratio
		(ρ)
		PMMA in solution	(PMMA:C 60 ) with
			expected ratio
	Toluene	C 60 in solution

C 60 dilution conditions Final Polymer to solvent conditions

	Solution mixing	A 111	Solution mixing	A 113
				Solution mixing A 114
		Solution mixing A 112

Toluene A 11 (PMMA:C 60 ) solution with targeted doping ratio (ρ) and polymer to solvent condition

Table in Appendix II-A. Dispense (PMMA:C 60 ) solution Spread uniformly on substrate Substrate

				(PMMA:C 60 ) with
				expected ratio
	Seringe	A 121	Spin-Coater	Hot Plate Baking

A 12 (PMMA:C 60 ) Thin Film with targeted doping ratio (ρ) and thickness Formation Nanocompocite Thin Film (A 12 ) Evaporate Residual Solvent Viscosity Rot. Speed Bake Time Random Organization Bake Temp.

	(
	A 122	A 123

PMMA:C 60 ) solution with targeted doping ratio (ρ) and polymer to solvent condition Surface nature

		-
		-
	Surface nature	Si/Si0 2 /Pt/Al	-
	Random organization on sample	#spl	-

- - Process & Env. Constrain/ Constrained variables

		Parameter description		Functional parameter/ Process variables
	A 123	Bake Time Bake Temperature		t BK (s) T BK (°C)
		Rotation speed	-	R speed (rpm)
	A 122	Viscosity (polymer to solvent condition,Mw)	-	w PMMA/Solvent (wt%), M W_PMMA (au)
		Surface nature	Si/Si0 2 /Pt/Al	-
		Random organization on sample	#spl	-

- - Process & Env. Constrain/ Constrained variables

		Parameter description
	A 123	Bake Time Bake Temperature	t BK (s) T BK (°C)
		Rotation speed	R speed (rpm)
	A 122	Viscosity (polymer to solvent condition,Mw)	w PMMA/Solvent (wt%), M W_PMMA (au)

Functional parameter/ Process variables

SiO SiO 2 2 Thick oxide Thick oxide Al-Si Electrode

	Pt Electrode Pt Electrode		Pt Electrode Pt Electrode		Al Electrode Al Electrode
		PMMA:C60 PMMA:C60 (~50nm) (~50nm) PMMA:C60 PMMA:C60 (~50nm) (~50nm)		PMMA:C60 PMMA:C60 (~50 nm) (~50 nm) PMMA:C60 PMMA:C60 (~50 nm) (~50 nm)		PMMA:C60 PMMA:C60 (~50 nm) (~50 nm) PMMA:C60 PMMA:C60 (~50 nm) (~50 nm)
	Semiconductor Semiconductor--P P substrate substrate Semiconductor substrate substrate Semiconductor--P P	SiO SiO 2 2 (5.5nm) (5.5nm) P P--Si Si (substrate) (substrate) P P--Si Si (substrate) (substrate) SiO SiO 2 2 (5.5nm) (5.5nm)	Si substrate Si substrate SiO SiO 2 2 Thick oxide Thick oxide Si substrate Si substrate SiO SiO 2 2 Thick oxide Thick oxide Pt Electrode Pt Electrode	SiO SiO 2 2 (500 nm) (500 nm) SiO SiO 2 2 (500 nm) (500 nm) Pt Pt (100 nm) (100 nm) Pt Pt (100 nm) (100 nm)	Si substrate Si substrate Si substrate Si substrate	SiO 2 (500 nm) (500 nm) SiO 2 Al Al--Si Si (100 nm) (100 nm) Al--Si Si Al (100 nm) (100 nm)

2 Chapter IV-MIM Pt BW : Si/Si0 2 /Pt Chapter V-MIM Al BW : Si/Si0 2 /Al-Si

SiO SiO 2 2 Thick oxide Thick oxide Al-Si Electrode

	SiO SiO 2 2 (500 nm) (500 nm)

FIGURE II.17: Base wafers (BW) with PAD electrodes considered for electrical characterization.

TABLE

	Section	Sample	Base Wafer	PMMA ρ(C60)	PMMA	Rotation	Bake
		#			(wt%)	concentration	speed	(Time;Temp)
						(wt%) / solvent	(Rpm)
		MIOS-PM00			0
	Chap. III	MIOS-PM05	Si-P/SiO2/-(Φ 200mm)	950K-A2	5	2.00/Anisole 0.66/Toluene		120°C;120s
		MIOS-PM10			10

TABLE . II

 .

.21: Summary of condition process for the main electrical devices considered in this thesis work.

  Mobile and Trapped charge per unit area at the semiconductor interface C

I : Insulator Capacitance (Semiconductor Devices, 2/E by S. M. Sze Copyright © 2002 Wiley & Sons. Inc. All Rights Reserved)

Pulse width w x (s) FIGURE IV.17: Pulse

	width influence analysis on the
	transition from (a) High Resistive Sate (pulse
	programmed at 8V; 500ms) to Medium Resistive
	State (Pulse programmed at 4V; variable length), (b)
	Medium Resistive Sate (pulse programmed at 4V;
	500ms) to Low Resistive State (Pulse programmed at
	2.75V; variable length),(c) Medium Resistive Sate
	(pulse programmed at 4V; 500ms) to a High Resistive
	State (Pulse programmed at 8V; variable length).

Table IV .1:

 IV Summary of the main performance requirements for polymer memory development with estimated maturity, typical and best reported results from literature and results presented in this work.

			3-5			6-7 (10 9 for 300nm devices) Ion/Ioff ~ 10
	Reproducibility cycle2cycle	-	NC	Distribution of Vth,Ion,Ioff on 280 DC sweep cycles	[ChoB10]	Distribution of Vth,Ion,Ioff on 590 DC sweep cycles
	Variability device2device	-	NC	Distribution of Ion and Ioff on 192 devices	[Song10]	Distribution of three different resistive state on 56 devices
	Retention	++	Stable retention	Stable >800h on 2 levels Stable>10 5 s on 4 levels	[Kwan07] [Park09]	Stable >10 4 s on 3 level Stable up to 3 days on 6 levels
	Write/Erase time Single pulse	++	NC	SET < 300 ns; RST<500ns	[Kwan07]	NC
	Write/Erase time in pulse stream	-	NC	Delay time reduced to 1ms	[Joo08]	SET HRS MRS ~ 25 ms SET MRS LRS ~ 100 µs RST HRS MRS ~ 500 ns
	Endurance	---	10-100 cycles	4000 cycles	[Kwan07]	> 10 5 (125k) cycles
	Device Area	---	1 mm²	4x4µm²	[Kwan07]	Diameter 500-250µm Diameter 1.8µm -300 nm

.1: Electrodes Organic layer Annealing treatment

	Bottom	Top	Below Tg (120°C;30 min)	Above Tg (120°C;30 min)
	Inert	Inert	Non-linear Resistor until Breakdown	NDR & unipolar memory after forming
	(Pt)	(Pt)	( § IV.1.1)	(Chapter IV)
	Inert	Oxidizable	Studied here as reference sample	-
	(Pt)	(Al)	( § V.1.2)	(Not reported in this thesis work)
	Oxidizable	Oxidizable	Studied here for oxide impact study	-
	(Al)	(Al)	(Chapter V)	(Not studied in this thesis)

TABLE V . 1 :

 V1 Electrode and organic layer annealing conditions considered for electrical studies.

	0 V 0 V	V G V G
		Al -Top electrode Al -Top electrode	Thin Al2O3 interfacial oxide Thin Al2O3 interfacial oxide Thin Al2O3 interfacial oxide Thin Al2O3 interfacial oxide
			PMMA:C60 PMMA:C60 Nanocomposite Nanocomposite PMMA:C60 PMMA:C60 Nanocomposite Nanocomposite
		Al -Bottom electrode Al -Bottom electrode	Thick Al2O3 interfacial oxide Thick Al2O3 interfacial oxide Thick Al2O3 interfacial oxide Thick Al2O3 interfacial oxide
		SiO2 thick oxide SiO2 thick oxide SiO2 thick oxide SiO2 thick oxide
		Si Si--Substrate Substrate Si Si--Substrate Substrate

20

All of the work described in this chapter was performed at Hanyang University Laboratories (Seoul, KOREA) a collaboration visit in winter 2010-2011.

  Schematic of electrical bipolar I-V hysteresis (as obtained with +/-15V sequences) and associated memory operation. -The negative sequences (NP) corresponds to the WRITE operation and results in positive Low Resistive State (p-LRS) on the subsequent positive sweep (PN). This latest sequence serves both as READ and ERASE operation since the devices is further set in stable positive High Resistive State (p-HRS) on the subsequent positive sweep (PP).

	WRITE WRITE WRITE WRITE	READ READ READ READ	ERASE ERASE ERASE ERASE
	Current (A)
		Voltage (V)
	FIGURE V.6:

Potember79, Müller06 Ouyang05, Prakash06, Ouyang10] . • Une modification de la configuration électronique

  : cette dernière pourrait être fortement influencée par le piégeage de charges localisées, la formation de zones de charges d'espace ou de migrations ioniques. Ces modifications dans le volume ou aux interfaces peuvent moduler la conduction électrique dans le dispositif[

Simmons67, Bozanno05, ChoBO06, LinHT07] . • La formation de filaments conducteurs :

  Ces filaments pourraient provenir de la dégradation de matières organiques en phase riche en carbone[START_REF] Carchano | Bistable Electrical Switching in Polymer Thin Films[END_REF] ou de la migration métallique des électrodes[

Joo07, Vilkman09, Kwan10] . • Un basculement résistif dans l'oxyde interfacial : en

  effet la majeure partie des dispositifs est fabriquée à partir d'électrodes oxydables d'Aluminium. Il a été reporté que la formation d'oxyde natifs pouvait être nécessaire[START_REF] Cölle | Switching and filamentary conduction in non-volatile organic memories[END_REF][START_REF] Yook | Transparent organic bistable memory device with pure organic active material and Al/indium tin oxide electrode[END_REF] ou pouvait améliorer[START_REF] Verbakel | Reproducible resistive switching in nonvolatile organic memories[END_REF]

Structure de test pour la caractérisation électrique

  Pour l'étude électrique du composite, des structures de test où seule l'électrode supérieure est structurée par évaporation masquée ont été choisis pour garantir une bonne uniformité des dépôts. Pour les différentes études, les empilements réalisés sont présentés sur la figure VI.12 :Des structures de type Métal-Insolant-Organique-Semi-conducteur (MIOS) ont été employées pour l'étude capacitive et des structures Métal-Organique-Métal (MOM) ou Métal-Isolant-Organique-Isolant-Métal (MIOiM) ont été utilisées pour les études résistives avec électrodes respectivement inertes ou oxydables. Pour l'étude de miniaturisation, des structures spécifiques telles que présentées sur la figure VI.13 ont été fabriquées permettant l'étude originale de dispositifs submicroniques (jusqu'à 300nm)28

	VI.2 -CHAPITRE 2 -FABRICATION ET CARACTERISATION DU NANOCOMPOSITE (PMMA:C60)
		Sans Recuit Thermique >Tg	Avec Recuit Thermique> Tg
		(recuit 120°C/120s)	(recuit 120°C/120s + 180°C/ 30 min)
		5µmx5µm 5µmx5µm		5µmx5µm 5µmx5µm
	PMMA
	ρ=0wt%
		5µmx5µm 5µmx5µm		5µmx5µm 5µmx5µm
	PMMA:C60
	ρ=20wt%
	FIGURE VI.11: Images de surface 3D obtenues par imagerie à force atomique (AFM 5 µm x 5 µm) de PMMA
	seul (ρ=0wt%) et fortement dopé PMMA (ρ =20wt) avant et après recuit supplémentaire au delà de la
	température de transition vitreuse.
	VI.2.4 Chapitre III-MIOS Pt	Chapitre IV-MOM Pt	Chapter V-MIOiM Al
	Substrat : Si/Si0 2	Substrat: Si/Si0 2 /Pt	Substrat: Si/Si0 2 /Al-Si
	Pt Electrode Pt Electrode		Pt Electrode Pt Electrode		Al Electrode Al Electrode
		PMMA:C60 PMMA:C60 (~50nm) (~50nm) PMMA:C60 PMMA:C60 (~50nm) (~50nm)		PMMA:C60 PMMA:C60 (~50 nm) (~50 nm) PMMA:C60 PMMA:C60 (~50 nm) (~50 nm)		PMMA:C60 PMMA:C60 (~50 nm) (~50 nm) PMMA:C60 PMMA:C60 (~50 nm) (~50 nm)
	Semiconductor Semiconductor--P P substrate substrate Semiconductor Semiconductor--P P substrate substrate	SiO SiO 2 2 (5.5nm) (5.5nm) P P--Si Si (substrate) (substrate) SiO SiO 2 2 (5.5nm) (5.5nm) P P--Si Si (substrate) (substrate)	Pt Electrode Pt Electrode Si substrate Si substrate SiO SiO 2 2 Thick oxide Thick oxide Si substrate Si substrate SiO SiO 2 2 Thick oxide Thick oxide	Pt Pt (100 nm) (100 nm) Pt Pt (100 nm) (100 nm) SiO SiO 2 2 (500 nm) (500 nm) SiO SiO 2 2 (500 nm) (500 nm)	Al-Si Electrode Al-Si Electrode Si substrate Si substrate Si substrate Si substrate SiO SiO 2 2 Thick oxide Thick oxide SiO SiO 2 2 Thick oxide Thick oxide	Al Al--Si Si (100 nm) (100 nm) Al Al--Si Si (100 nm) (100 nm) SiO SiO 2 2 (500 nm) (500 nm) SiO SiO 2 2 (500 nm) (500 nm)
			-163-

FIGURE VI

.12: Structures de test pleine couche proposées pour l'étude électrique du composite.

1mm -150 µm SiO 2 SiO 2 1.8 µm-300 nm

	1mm -150 µm				FIGURE VI.13: Schéma des
	Pt 100 nm Pt 100 nm PMMA:C60 Pt 100 nm PMMA:C60 Pt 100 nm	Top electrode (Pt 100 nm) Top electrode (Pt 100 nm)	Bottom electrode Pt 10nm/TiN5nm Pad Bottom electrode Pt 10nm/TiN5nm Pad	structures de test employées pour les études de miniaturisation avec électrode supérieure avec
	Pt 100 nm W PMMA:C60 SiO 2 SiO 2 Pt 100 nm PMMA:C60 W	Pt 10 nm Pt 10 nm	M1 Bottom Line W 300nm PMMA:C60 300nm ~ 30nm 300nm PMMA:C60 W ~ 30nm M1 Bottom Line 300nm	SiO 2 300nm SiO 2 300nm	diamètre variable de 1mm à 150µm et électrode inferieure avec diamètre variable de 1.8µm à 300nm. Encadré : image TEM d'un dispositif avec électrode inférieure à 300nm.
	1.8 µm-300 nm

  Sze02]). Ce décalage dans les tensions négatives peut s'expliquer par la présence de charges positives piégées dans le diélectrique (Cf Eq 3.5). De plus, le double balayage en tension n'a pas mis en évidence d'effets d'hystérésis suggérant que les charges en présence sont fixes et non impactées par le champ électrique appliqué en accumulation. En revanche en tension positive, nous avons observé la présence de phénomènes d'inversions inhabituelles avec manifestation de la bosse d'inversion à haute fréquence et présence d'hystérésis lors du balayage aller-retour.

	~0-0.3V voir [
		V G V G
		Pt Electrode Pt Electrode
	PMMA:C60 PMMA:C60 PMMA:C60 PMMA:C60
	(~50nm) (~50nm) (~50nm) (~50nm)
	SiO SiO 2 2 (5.5nm) (5.5nm) SiO SiO 2 2 (5.5nm) (5.5nm)	Semiconductor Semiconductor Semiconductor Semiconductor
		substrate substrate substrate substrate
		0 V 0 V
	FIGURE VI.15: Schematic of MOIS
	structure with blocking oxide and
	inert electrodes
	-166-

  Organic and oxide layer Thicknesses ε org, ε ox : Organic and oxide layer permittivity V org, V ox : Voltage drop on Organic and oxide layer F org, F ox : Field in Organic and oxide layers

												Al -Top electrode Al -Top electrode
	V TOT V TOT TOT V	=	V ORG V OX V ORG V OX ORG V +	Al Oxide Al -Bottom Electrode PMMA:C 60 Al Oxide Al -Bottom Electrode PMMA:C 60 t org, t o, : OX t ORG ,ε ORG t OX ,ε OX t ORG ,ε ORG t OX ,ε OX V et 0 ε ε ε Q F F ORG ORG OX OX = ⋅ -⋅														(6.2)
	org TOT t V	=	ε	0	Q ⋅ ε	OX	⋅	org ox t t	+	1 (	+	ε	OX ORG ⋅ ε	t	ox	⋅	t	org 1	)	⋅	ORG F	ou	org TOT t V	=	ε	0	Q ⋅ ε	OX	⋅	+	(	ORG ox ⋅ ε ε	+	org ox t t	)	⋅	OX F	(6.3)

It is claimed that 70% of all the sensory receptors in the human body are in the eyes and nearly half of the cerebral cortex is involved in some aspect of visual processing.

Douglas Engelbard is an American inventor and an early computer and internet pioneer. It is claim that he could be one of the first to really highlight the strong potential of downscaling for complex computing around 1960[START_REF] Markoff | It's Moore's Law, but Another Had the Idea First[END_REF].

Originated from charge trapping in FLASH or dipole rearrangement for FeRAM Technologies.

(a) (b)

nm. The central crossbar has a junction density of 5x10 10 cm², and the two crossbars to the lower left and right of the central one are at a junction density of 10 11 cm². Scale bar is 500 nm. [Melosh03] (a) (b) (c)

or has an acceptable evolution within the margin allowed by applications.

This observation gives rise to the MEMRISTOR discovery popularized by HP and initiates a strong momentum for OXRAM memories research.

Metallic nano-particle especially based on noble metal could potentially disturb conventional CMOS stream.

(C60) powder has a deep black charcoal color indicating strong absorption on visible spectrum.

Choice of Tungsten in the plug fabrication is related to technological constrain.

With the respect of thermal budget required for organic nanocomposite stability (~180°C).

Crossbar and stacked structure with memory cells scaling down-to 30 nm taking advantage of direct patterning and encapsulation have been design on the IRMA mask set. Process flows were also developed for fabrication on 200 mm wafer in clean-room but have not been fabricated yet.

The Silicon oxide layer was especially introduced at the interface for this purpose. Indeed the thermalgrown SiO2 layer ensures a good interface quality and avoids the potential formation of uncontrolled native oxide during the organic deposition process. The presence of such interfacial defects and traps would influence the C-V characteristics and results in Dit behavior (see III.1.3C).

The doping ratio ρ is defined in Chapter II-1 as the masse ratio percentage (Wt %) of C60 to PMMA ρ = 100.mC60/mPMMA.

It was not the scope of the thesis work, however, the trapping ability demonstrated in such materials could be potentially interesting for Flash-like capacitive based memory devices. In order to complete the study and benchmark the potential of such storage layer, dataretention, read-disturb and endurance test should be jointly analyzed.

MIM-PP-PM10 devices are made of (PMMA:C60) nanocomposite layer with ρ=10wt%, thermally annealed at 180°C/ 30 min and platinum inert electrodes. (See Appendix II.A -Sample Description Table for details).

SET and RESET could be unipolar but have been performed here in opposite polarity to improve visibility on a common chart.

Very aggressive structure with bottom plug as small as 30 nm have been also designed in this thesis work on the mask set "IRMA". However for timing purposes this structure have not been fabricated and characterized.

Indeed for these experiments carried out in Hanyang University Laboratories (Seoul, KOREA) processing conditions were different form LETI's experiments (chapter III and IV) on several points: PMMA molecular weight, solvent employed, oven and thermal evaporation conditions (see Appendix II.A for details).

The "Negative Differential Resistance" behavior characterizes the unusual properties of a dipole to exhibit a lowering of current level when the voltage is increased (dV/dI <0).

Extraction has been chosen below Vmax ~ 2.5 V the critical point where current in p-LRS starts to decrease to reach the p-HRS.

We can point out that this normalized electrical field does not exactly correspond to the field in organic layer since the presence of interfacial oxide will induce a voltage drop at the interface. This normalized field is higher than electrical field in organic layer but the mismatch is decreased when increasing the organic layer thickness (interfacial oxide thickness is supposed to be constant or weakly dependant on organic layer thickness).

Des structures avec matrices cross-bar empilées de cellules mémoires jusqu'à 30nm ont également été dessinées sur le jeu de masque IRMA. Un flot de fabrication complet employant la propriété de structuration directe du matériau a été mis en place pour la fabrication sur substrat 200mm mais n'a pu être testé.

Minority carrier tank

VI.3.3.a Hystérésis sur la caractéristique C-V avec dopage en C6029 Le taux de dopage ρ est défini au Chapter II-1 comme étant le rapport de masse en pourcentage (wt %) du C60 sur le PMMA ρ = 100.mC60/mPMMA.

Les opérations d'écriture (SET) et d'effacement (RESET) qui peuvent être unipolaires ont été réalisées ici en tension opposée pour améliorer la visibilité des séquences sur un graphique commun.

Du point de vue applicatif, la possibilité de programmation multi-niveau contrôlée en tension permet l'usage d'algorithmes de control et de correction qui peuvent être implémenté pour optimiser ou corriger la variabilité des courants programmés.

Remerciements

-24-In order to overcome this limitation, some interesting approaches with a non-conventional

APPENDIX I.A: ITRS ROADMAP FOR MEMORY DEVICES APPENDIX III.A: Inversion ratio with lateral Fictive source drain

We considered here electrical configuration at high frequency with permanent inversion layer hypothesis and partial inversion of the deserted region brought by the lateral diffusion of carriers. This simple consideration is illustrated below in the case of circular geometry. -130-(a)

Write (W)

Read Disturb (RD) R/E after Read Disturb Sequence :

WRITE -Influence of Programming Conditions on hysteresis

In the device operation we have also presented that polarization in negative voltage directly influences the subsequent conduction in the positive region and could be identified as a WRITE operation. In order to study the dynamic of this process we have preliminary studied in this section the influence of voltage and stress time in the programming process.

V.2.3.a Influence of the Programming Voltage

The influence of the programming voltage (VW) has been investigated with Write/Read-Erase DC cycles. The negative boundaries of the write sequences have been progressively increased, and their impact was monitored on the subsequent Read Erase sequence. These results are plotted and reported in figure V.8.

schematic of figure V.15. According to these hypotheses, we can observe that negative polarization induces a lowering of the stoichiometric oxide thickness through the doping by oxygen vacancies whereas positive polarization should remove the conductive defect and increase the oxide resistance. This assumption is in agreement with the SET and RESET polarities (vi, ix) observed in our devices (see figure V.16a). For illustration purpose, bipolar resistive switching has been simulated according to the model suggested by Strukov et al and reported on figure V.16b (see Appendix V.B for details of model).

However, several points seem to not match very well with this mechanism. First of all, we do not observe in our devices the presence of any abrupt set transitions as it should be the case for the avalanche formation of conductive filaments as suggested by Strukov and al in the model for bipolar switching. Moreover, SET and RESET transitions are related to the rapid motion of oxygen vacancies above a critical electric field. However, in our experiments, with different organic layer thicknesses, the maximum peak voltage characteristic of reset transition was not found to be related to any critical field (xvii). Finally, we have observed in our devices planar switching, (xiii-xiv) whereas oxide-switching mechanisms are usually associated with filamentary conduction with off current scaling with area and on current independent from area considerations.

(2)

(3) (4)

L=10 nm; Ron=5.10 3 Ohm R0= 10 8 Ohm Roff= 10 9 Ohm

(1)

(2)

(3) (4)

(2)

(3) (4)

L=10 nm; Ron=5.10 3 Ohm R0= 10 8 Ohm Roff= 10 9 Ohm

APPENDIX V.B: MODEL FOR THE BISTABLE RESISTIVE SWITCHING IN OXIDE

This model employed for preliminary simulation is detailed by Strukov et Al in [Struckov08] the basic considerations are briefly presented here. We consider a bi-layer structure where the socalled undoped layer consist in stoichiometric oxide thus being highly insulating and a doped part where oxygen vacancies will enable high current flowing thus resulting in low resistance.

W(t).R ON /D (1-W(t)).R OFF /D

-145-Solving this differential equation will give the profile of the bi-layer upon the voltage applied and integration upon the time. Then from the doped distance w (t) we can express the current flowing in the device as:

For simulation purpose a windows function fwd(w(t)) could be introduce in order to stop the motion of oxygen vacancies when the device is fully doped or un-doped

(5.9)

The results obtained considering a sinusoidal input signal of amplitude V0 and frequency f and the parameters listed in inset is displayed on figure V.B.2.

(1)

L=10 nm; Ron=5.10 3 Ohm R0= 10 8 Ohm Roff= 10 9 Ohm

(1)

(2)

(3) (4)

(2)

(3) (4)

(3) (4)

(2)

(3) (4)

L=10 nm; Ron=5.10 3 Ohm R0= 10 8 Ohm Roff= 10 9 Ohm

(1)

(2)

(3) (4)

(2)

(3) (4)

D=10 nm; R ON = 5.10 3 Ohm R 0 = 10 8 Ohm R OFF = 10 9 Ohm FIGURE V.B.2: I-V characteristics simulated according to the model presented here (Equation 5.8 and 5.9) and the parameters listed here.

-164-

VI.3 Chapitre 3 -Caractérisation Capacitive des couches (PMMA:C 60 )

Les phénomènes de piégeage de charge ont été évoqués à de nombreuses reprises comme potentiellement responsables des commutations résistives observées dans les couches nanocomposites [Bozano05, ChoBO06, Ling08]. Pour étudier ces possibilités dans les couches composites (PMMA:C60), les études électriques ont été premièrement abordées sous un angle capacitif. Ces résultats sont présentés au Chapitre 3. L'intérêt et la caractérisation des structures Métal-Isolant-Semi-conducteur sont rappelés brièvement et une analyse préliminaire du dispositif de référence comprenant uniquement le polymère isolant a été menée. Enfin les couches nano-composites envisagées pour les dispositifs résistifs ont été analysées en termes de piégeages de charges.

VI.3.1 Intérêt et introduction de la caractérisation Capacitive C-V

Nous avons premièrement rappelé les bases physiques de la caractérisation C-V sur les dispositifs de type MIS (Métal-Isolant -Semi-conducteur). Plus largement décrite dans la section III.1 ou dans les ouvrages de références [START_REF] Nicollian | MOS (Metal Oxide Semiconductor) Physics and Technology[END_REF]Sze] , la mesure de la caractéristique capacitétension (C-V) permet de discriminer trois régimes distincts de fonctionnement appelés: Accumulation, Déplétion et Inversion. Suivant la polarisation appliquée la distribution de charges dans le semi-conducteur module en effet la capacité mesurée comme illustrée sur la figure VI.14.

ACCUMULATION

(VG < 0) -167-comportement MIS classique. Les conditions nécessaires à cette hypothèse sont bien réunies dans les dispositifs que nous avons étudiés : un substrat de type-P avec des porteurs minoritaires négatifs et une tension de bande plate négative qui indique la présence de charges fixes positives piégées dans le diélectrique. Lors de la polarisation du dispositif les charges situées sous l'électrode sont directement influencées. Cependant comme illustré sur la figure VI.18 une couche d'inversion reste permanente autour de la grille et peut alors fournir un réservoir de porteurs minoritaires qui du fait de la proximité peuvent peupler la zone désertée et participer, même à une fréquence élevée, à une inversion partielle du dispositif. --P P

Si Si--P P

INVERSION (LF)

+ + + + -----

Si

Si--P P

INVERSION (HF)

+ + + + ----- --P P

INVERSION (LF)

+ + + + -----

Si

Si--P P

INVERSION (HF)

+ + + + -----

Les caractéristiques C-V partant de l'inversion à l'accumulation avec retour en inversion [+9V -14V +9V] sont présentées sur la figure VI.19. Comme reporté dans la section précédente le comportement de l'échantillon sans C60 (ρ =0wt %) correspond à un comportement isolant sans variation de tension de bande plate (∆VFB) entre les mesures aller et retour. A l'inverse, l'introduction progressive du C60 (ρ =5,10wt %) montre clairement l'apparition d'une boucle d'hystérésis dans le sens horaire qui est favorisée par l'augmentation du dopage. D'après l'équation Eq. 3.4, le décalage de la tension de bandes plates dans les tensions positives est révélateur du piégeage de charge négative en présence de C60. Cette observation est en accord avec les études précédemment reportées sur d'autres composites à base de C60 qui présentent les molécules de C60 comme un centre de piégeages de charges négatives -169-L'emploi de la structure MOIS permet d'identifier clairement le mécanisme responsable de cette hystérésis reproductible. En effet, l'usage de l'oxyde à l'interface bloque l'injection du semiconducteur et contraint les échanges de charges qui ne peuvent avoir lieu qu'avec la grille. Dans ce contexte, l'hystérésis due au piégeage de charges négatives s'explique comme illustré sur le diagramme de bandes qualitatives présenté en figure VI.21a-b.

En accumulation forte, les électrons sont injectés par la grille et transitent dans le volume par hopping ou tunneling entre des ilots de C60 isolés.

Du fait du gap plus petit du C60 par rapport au PMMA, les électrons injectés restent piégés lorsque le champ électrique est diminué.

Enfin en régime d'inversion forte, le phénomène est renversé et les électrons relâchés dans la grille. Comme observé sur les cycles progressifs reportés sur la figure VI.24b, il est important de mentionner que l'apparition de l'hystérésis n'est pas seulement conditionnée par le matériau mais nécessite également de polariser le dispositif sur une plage de tension particulière (V>VForming). Nous observons de plus sur cet hystérésis et les cycles successifs, une plage de tension (VNDRmin → VNDRmax) pour laquelle l'allure du courant est particulièrement atypique (dI/dV <0) on parle de résistance différentielle négative (RDN).

VI.4.2 Effets Mémoires Résistifs dans les dispositifs à RDN

Dans la littérature, certains dispositifs avec électrode d'aluminium et nano-composite à base de fullerène et polymères isolants tels que (PS:C60) [START_REF] Majumdar | Fullerene-based bistable devices and associated negative differential resistance effect[END_REF] , (PS:PCBM-C60) [Baral08] ou (PI:PCBM-C60) [START_REF] Cho | Thermally robust multi-layer non-volatile polymer resistive memory[END_REF] ont été également reporté pour avoir un comportement de résistances différentielles négatives auquel ont a pu associer des effets mémoires résistifs. Nous avons ici mis en évidence pour la première fois des phénomènes similaires avec électrode inerte dans les couches (PMMA : C60) (ρ = 10wt% avec recuit thermique supplémentaire 180°C/30min) et étudié plus en détails les performances mémoire associées. Les dispositifs mémoires a base de résistance différentielle négative (RDN) sont particulièrement prometteurs pour le stockage d'information multi-bit. En effet ils offrent la possibilité d'être programmé directement en tension sur une large fenêtre de niveau de courants et montrent usuellement une rétention d'information stable. Au-delà de ces points ce travail de thèse a permis de démontré pour la première fois la fonctionnalité de dispositifs à l'échelle submicronique, des données précises la reproductibilité des phénomènes observé ont également été apportées. Enfin pour compléter l'état de l'art une étude préliminaire sur la viabilité de la programmation par impulsion a permis l'obtention d'endurance record.

VI.4.3 Caractérisation détaillée du fonctionnement

La bonne reproductibilité des phénomènes observés dans les dispositifs fabriqués a permis de mener une étude approfondie du fonctionnement multi-niveau des cellules mémoires à RDN.

VI.4.3.a Identification des différents régimes d'opération

Nous avons tout d'abord identifié les différents régimes d'opération (états quasi-statique et transition) observés au cours des cycles mémoires. Ces derniers ont été reportés schématiquement sur la figure VI.28. On distingue tout d'abord l'état INITIAL du dispositif qui semble quasi-statique si la tension appliquée reste inferieur à la tension dite de PREFORMAGE (VFORMING). Au delà de cette tension, il y a ouverture d'une hystérésis sur le cycle retour et apparition d'une zone de Resistance Différentielle Négative RDN. Le comportement RDN est reproductible et semble également quasi-statique. Apres avoir quitter la zone de RDN en diminuant la tension ou en stoppant abruptement la mesure dans la zone de RDN, on obtient sur le cycle successif des ETAT STABLES aux niveaux de courant variables. Ces états sont stables jusqu'à une tension de BASCULEMENT (VSW) au-delà duquel le dispositif retrouve un comportement RDN.

-183-Pour les dispositifs M-i-O-I-M avec électrode inferieure oxydable, la méthodologie de recherche d'hystérésis a permis de mettre évidence des effets mémoires potentiels lors de séquences bipolaires. L'enchainement de séquences positive et négative [0V +/-15V] illustré sur la figure VI.37 montre l'existence d'une hystérésis dans les tensions positives. Quatre comportements résistifs sont clairement distincts.

L'Etat Résistif Initial en tension Positive (p-RI):

Il correspond à l'état initial en tensions positives et aux cycles positifs successifs (Séquences 00 and P0).

L'Etat Résistif en tension Négative (n-R):

En tension négative le niveau de courant est plus élevé et semble indépendant de la polarisations précédentes. L'allure de courant est identiques pour les cycles "Négatif après Positif"-NP et "Négatif après Négatif"-NN.

L'Etat Faiblement Résistif en tension Positive (p-FR):

Il caractérise le comportement du dispositif après l'alternance des séquences négatives vers positives PN. Le niveau de courant initialement élevé décroit progressivement avec un comportement de Résistance différentielle Négative (RDN).

L'Etat Hautement Résistif en tension Positive (p-HR):

Il caractérise les séquences "Positive après Positive "-PP ou le comportement reste stable à un niveau de courant inférieur.

En conclusion ces dispositifs montrent un comportement électrique dissymétrique. Il a également été clairement observé que les niveaux de courant ne dépendaient pas uniquement de la polarité mais également de l'historique de polarisation. En tension positive deux comportements résistifs reproductibles sont alors distingués (p-HR et p-FR). Cette propriété associée à la présence d'électrode oxydable et d'une couche organique adaptée (Voir étude sur les concentrations de dopage §) pourrait alors être employée pour la réalisation de mémoires résistives non-volatiles bipolaires. ). On constate tout d'abord qu'une séquence parasite a déjà un impact sur la mesure successive même à faible tension (-12% sur le courant extrait à 1V pour VRD=1V). Ce phénomène s'accélère rapidement si VRD est augmenté au-delà de la tension de courant maximum (VMAX) (-50% pour VRD=4V). On obtient un effacement quasi complet (-90%) pour VRD =10V. Cette étude préliminaire qui ne prend pas en compte l'influence de la durée de programmation (Stress) permet de souligner l'effacement parasite durant les cycles de lecture.

(a) R/E after Read Disturb Sequence : -185-VI.5.2.b ECRITURE -Influence des conditions de programmation sur l'hystérésis L'influence de la tension de programmation (VW) a été étudiée par le biais de séquence de polarisation Ecriture/Lecture-Effacement avec des tensions de programmation progressivement augmentées. Les résultats obtenus sont reportés sur la figure VI.40. Un schéma de programmation complexe a été observé ou la tension de programmation n'induit pas seulement une transition entre deux états résistifs mais module progressivement l'allure de la caractéristique courant-tension sur différente région (sub/post pic). En effet, suivant la tension de programmation, trois catégories d'effets sont distinguées. A faible champ (VSW= [0V; -5.0 V]) une augmentation du niveau de courant à faible tension est observée avec l'apparition d'un pic de courant (VMAX=~2-3V) et d'une zone de Résistance différentielle négative (RDN). Pour une programmation plus forte (VSW = [-5V;-12 V]) la caractéristique I-V est impactée au-delà de la tension de pic VMAX avec une diminution du niveau de courant et donc élargissement de la zone de RDN. Enfin pour des tensions de programmation élevées (VSW = [-15V;-27.5 V]) la tendance s'inverse et le niveau courant post-pic est à nouveau augmenté.

-187-

VI.5.3.b Epaisseur de la couche organique

Pour comprendre le rôle fonctionnel de la couche organique, des dispositifs de différentes épaisseurs (torg) ont été fabriqués (torg ~76 nm; ~40 nm and ~25 nm 33 ). Afin de comparer ces dispositifs la caractérisation I-V a été réalisée dans des conditions équivalentes de champ électrique (~ +/-5MV/cm). Il a été préalablement reporté que la tension VMAX correspondant à un pic de courant lors du balayage en tension positive est une caractéristique de la cellule non impactée par la surface d'électrode et faiblement modifiée par la tension de programmation. Sur la figure VI.44a les caractéristiques I-V pour différentes épaisseurs montrent une diminution progressive du niveau de courant avec l'augmentation d'épaisseur mais également une augmentation significative de la tension de pic caractéristique VMAX (VMAX~ 3V, 7V and 24V).

Publications of the Author

Journals and Proceedings

Development and Study of Organic Polymer Resistive Memories For Crossbar Architectures

Over the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...).