Mohammed El Azhari

Mohammed El

Jordan 2023 Homomorphisms

A note on n-Jordan homomorphisms

Keywords: Jordan homomorphism, homomorphism, n-Jordan homomorphism, n-homomorphism

By using a variation of a theorem on n-Jordan homomorphisms due to Herstein, we deduce the following G. An's result: Let A and B be two rings where A has a unit and char(B) > n. If every Jordan homomorphism from A into B is a homomorphism (anti-homomorphism), then every n-Jordan homomorphism from A into B is an n-homomorphism (anti-n-homomorphism).

Preliminaries

Let A, B be two rings and n ⩾ 2 an integer. An additive map h : A → B is called an n-Jordan homomorphism if h(x n ) = h(x) n for all x ∈ A. Also, an additive map h : A → B is called an n-homomorphism or an anti-n-homomorphism if h(

n i=1 x i ) = n i=1 h(x i ) or h( n i=1 x i ) =
n-1 i=0 h(x n-i ), respectively, for all x 1 , ..., x n ∈ A. In the usual sense, a 2-Jordan homomorphism is a Jordan homomorphism, a 2-homomorphism is a homomorphism and an anti-2-homomorphism is an antihomomorphism. It is obvious that n-homomorphisms are n-Jordan homomorphisms. Conversely, under certain conditions, n-Jordan homomorphisms are n-homomorphisms. We say that a ring A is of characteristic greater than n (char(B) > n) if n!x = 0 implies x = 0 for all x ∈ A.

Results

Lemma 2.1 [4, Lemma 1]. Let A, B be two rings, n ⩾ 2 be an integer and f : A n → B be a multi-additive map such that f (x, x, ..., x) = 0 for all x in A. Then σ∈Sn f (x σ(1) , ..., x σ(n) ) = 0 for all x 1 , ..., x n ∈ A, where S n is the set of all permutations on {1, ..., n}.

By using Lemma 2.1, we have the following lemma: Lemma 2.2. Let A, B be two rings, n ⩾ 2 be an integer and h : A → B be an n-Jordan homomorphism. Then

σ∈Sn (h( n i=1 x σ(i) ) - n i=1 h(x σ(i) )) = 0 for all x 1 , ..., x n ∈ A,
where S n is the set of all permutations on {1, ..., n}.

Proof. Consider the map

f : A n → B, f (x 1 , x 2 , ..., x n ) = h( n i=1 x i ) - n i=1 h(x i ), f is clearly multi-additive and f (x, x, ..., x) = h(x n ) -h(x) n = 0 for all x ∈ A. By Lemma 2.1, σ∈Sn f (x σ(1) , ..., x σ(n) ) = σ∈Sn (h( n i=1 x σ(i) ) - n i=1 h(x σ(i) )) = 0 for all x 1 , ..., x n ∈ A.
It was shown in [START_REF] Gselmann | On approximate n-Jordan homomorphisms[END_REF] that if n ⩾ 2, A, B are commutative rings, char(B) > n and h : A → B is an n-Jordan homomorphism, then h is an n-homomorphism. The same was also proved for algebras in [START_REF] Bodaghi | n-Jordan homomorphisms on commutative algebras[END_REF] and [START_REF] Lee | Stability of n-Jordan homomorphisms from a normed algebra to a Banach algebra[END_REF]. Here we obtain this result as a consequence of Lemma 2.2.

Theorem 2.3. Let A, B be two commutative rings and char(B) > n. Then every n-Jordan homomorphism from A into B is an n-homomorphism.

Proof. Let h : A → B be an n-Jordan homomorphism. By Lemma 2.2 and since A, B are commutative,

σ∈Sn (h( n i=1 x σ(i) ) - n i=1 h(x σ(i) )) = n!(h( n i=1 x i ) - n i=1 h(x i )) = 0 for all x 1 , ..., x n ∈ A, hence h is an n-homomorphism since char(B) > n.
Now we give the following variation of a theorem on n-Jordan homomorphisms due to Herstein [4, Theorem K].

Theorem 2.4. Let h be an n-Jordan homomorphism from a ring A into a ring B with char(B) > n. Suppose further that A has a unit e, then h = h(e)τ where h(e) is in the centralizer of h(A) and τ is a Jordan homomorphism.

Proof. Since h is an n-Jordan homomorphism, h(e) = h(e n ) = h(e) n . By Lemma 2.2 and putting 1) and so nh(x) = h(e) n-1 h(x) + h(e) n-2 h(x)h(e) + • • • + h(x)h(e) n-1 (1) since char(B) > n. By multiplying on the right by f (e) both sides of the equality (1), nh(x)h(e) = h(e) n-1 h(x)h(e) + h(e) n-2 h(x)h(e) 2 + • • • + h(x)h(e) (2) Also, by multiplying on the left by f (e) both sides of the equality (1), nh(e)h(x) = h(e)h(x) + h(e) n-1 h(x)h(e) + • • • + h(e)h(x)h(e) n-1 (3) By ( 2) and ( 3), (n -1)h(x)h(e) = (n -1)h(e)h(x) and consequently h(x)h(e) = h(e)h(x) (4) since char(B) > n. Then h(e) is in the centralizer of h(A). By (1) and (4), nh(x) = nh(e) n-1 h(x) and so h(x) = h(e) n-1 h(x) (5) since char(B) > n. By Lemma 2.2, (4) and putting

x 1 = x, x 2 = x 3 = • • • = x n = e, n!h(x) = (n -1)!(h(e) n-1 h(x) + h(e) n-2 h(x)h(e) + • • • + h(x)h(e) n-
x 1 = x 2 = x, x 3 = • • • = x n = e, n!(h(x 2 ) -h(e) n-2 h(x) 2 ) = 0 and hence h(x 2 ) = h(e) n-2 h(x) 2 (6) since char(B) > n. Consider the map τ : A → B, τ (x) = h(e) n-2 h(x), τ is clearly ad- ditive. By (5), h(x) = h(e) n-1 h(x) = h(e)h(e) n-2 h(x) = h(e)τ (x) for all x ∈ A. By (6), τ (x 2 ) = h(e) n-2 h(x 2 ) = h(e) 2(n-2) h(x) 2 = (h(e) (n-2) h(x)) 2 = τ (x) 2 for all x ∈ A, thus τ is a Jordan homomorphism.
As a consequence, we obtain the following result of G. An [START_REF] An | Characterizations of n-Jordan homomorphisms[END_REF].

Corollary 2.5 [START_REF] An | Characterizations of n-Jordan homomorphisms[END_REF]Theorem 2.4]. Let A and B be two rings where A has a unit e and char(B) > n. If every Jordan homomorphism from A into B is a homomorphism (anti-homomorphism), then every n-Jordan homomorphism from A into B is an n-homomorphism (anti-n-homomorphism).

Proof. Let h : A → B be an n-Jordan homomorphism. By Theorem 2.4, h = h(e)τ where h(e) is in the centralizer of h(A) and τ is a Jordan homomorphism. If τ is a homomorphism, h(x

1 x 2 • • • x n ) = h(e)τ (x 1 x 2 • • • x n ) = h(e)τ (x 1 )τ (x 2 ) • • • τ (x n ) = h(e) n τ (x 1 )τ (x 2 ) • • • τ (x n
) since h(e) = h(e n ) = h(e) n = h(e)τ (x 1 )h(e)τ (x 2 ) • • • h(e)τ (x n ) since h(e) commutes with each τ (x) = h(x 1 )h(x 2 ) • • • h(x n ) for all x 1 , ..., x n ∈ A, hence h is an n-homomorphism. Similarly, if τ is an anti-homomorphism, then h is an anti-n-homomorphism.


Sergio Vinagrero Gutiérrez
email: sergio.vinagrero-gutierrez@univ-grenoble-alpes.fr

Pietro Inglese
email: pietro.inglese@univ-grenoble-alpes.fr

Giorgio Di Natale
email: giorgio.di-natale@univ-grenoble-alpes.fr

Elena-Ioana Vatajelu
email: ioana.vatajelu@univ-grenoble-alpes.fr

Open Automation Framework for Complex Parametric Electrical Simulations

Keywords: electrical simulation, parametric, Verilog-A, Spice

The need to achieve statistically relevant results in electrical simulations requires a large number of iterations under different operating conditions. Moreover, the nature of parametric simulations makes the collection and filtering of the results non-trivial. To tackle these issues, scripts are normally used to control all the parameters. Still, this approach is usually ad-hoc and platform dependent, making the whole procedure hardly reusable, scalable and versatile. We propose a generic, opensource framework to generate complex stimuli and parameters for electrical simulations, together with a programmable Spiceand Verilog-A-based module capable of observing and logging internal states of the circuit to facilitate further result analysis.

I. INTRODUCTION

Design complexity, ultra-low-power requirements, reliability, robustness and security are becoming increasingly important concerns when designing electronic systems. Moreover, designers are facing novel challenges related to aggressive CMOS technology scaling and the introduction of beyond-CMOS devices (CNT-FET, Memristive, Spintronic). Indeed, several issues must be considered at design time such as fabricationinduced variability, technology-dependent defects, extreme operating/environmental conditions, stochastic behaviours, aging, and possible perturbations (noise, radiations, malicious attacks).

For consecrated technologies and applications, the electricallevel issues are well-understood and easily translatable to higher levels of abstraction (RTL, micro-architectural, system), thus enabling very fast and accurate simulations. However, with the aforementioned issues faced by today's designs, electricallevel simulations are unavoidable since they allow designers to accurately model and understand the behaviour of the target system, and to extrapolate physical-level properties to a higher level of abstraction.

In order to explore the behaviour of an electrical circuit under different conditions and parameters, multiple simulations are performed with the desired setting. In today's circuits based on new technologies, the number of parameters and their interdependencies can be prohibitively large to be exhaustively studied. Monte Carlo [START_REF] Metropolis | The monte carlo method[END_REF] and parametric simulations are the classical approaches to cope with this type of problem. Nevertheless, algorithms implemented in industrial CAD tools * Institut National Polytechnique Grenoble Alpes do not offer the designer full control and observability of desired parameters. Moreover, the range and the distribution of parameters are defined in technological libraries (provided by silicon foundries). However, these data are not easily available for emerging technologies (or at least not yet embedded in industrial libraries).

We propose a unified framework which works for both statistical and parametric simulations performed independently or concomitantly. This allows the designer to fully control the range of parameters and fully observe the circuit behaviour. Moreover, it allows correlating the circuit behaviour with the parameters used at simulation time. This framework implements the following steps:

1) Define the set of parameters relevant to the study. Here we can target process variability, operating/environmental conditions, stochastic behaviours, aging, perturbations; 2) Identify the relevant signals that fully characterise the circuit behaviour; 3) The value of each parameter is generated by a userdefined function; 4) For each combination of parameters, a netlist is generated and simulated. The relevant signals provide the information required about the circuit behaviour. Another important aspect of electrical simulations is the ability to reproduce results. Indeed, there are situations when it is important to repeat the simulations with the same parameters, for instance when performing design-space exploration, defect analysis, evaluation of countermeasures in secure circuits, etc. Moreover, in the scientific research environment, the repeatability of experiments and results is of paramount importance. However, since several commercial tools exist and their manipulation and operation are not identical, it is difficult to reproduce simulations performed on one tool to another. Most commercial CAD tools provide utilities to generate parameters but in some cases, it is very difficult to replicate the environment. Moreover, there is also the problem of incompatibility between simulators and licenses. Even if the tools and license requirements are met, the aggregation of results after complex parametric simulations is cumbersome and takes a big part of the project time just to prepare the data.

In this paper, we show an open-access and open-source framework to carry out complex parametric electrical simulations and analyses. This framework is a wrapper to commercial tools, which allows researchers to perform and repeat a large 979-8-3503-3277-3/23/$31.00 ©2023 IEEE number of simulations, no matter the underlying simulation environment. The framework is implemented in Python and Verilog-A and it is licensed under the MIT License. The code and documentation can be found online [2], [START_REF] Inglese | Verilog-a state observer[END_REF].

This paper is organised as follows: the current state of the art is summarised in section II, followed by the motivation of this project in section III; In section IV the two parts of the framework are described in detail and some use cases are provided in section V.

II. STATE OF THE ART

The main format used to describe electrical netlists is called Spice [START_REF] Nagel | SPICE (simulation program with integrated circuit emphasis)[END_REF], which stands for Simulation Program with Integrated Circuit Emphasis. An electrical simulator will take the spice netlist, parse it and simulate it. The same netlist can be simulated under different compatible simulators as it is just a description of the circuit. All of the available tools for electrical simulations provide a graphical user interface to generate circuits based on a drag-and-drop mechanism which is very user-friendly. The graphical user interface can be also used to customise every aspect of the simulation to provide the necessary parameters to the simulator. However, not every available tool provides a mechanism to easily save this configuration to be used later, or on a different computer. Therefore, in order to share a project between different teams, the exact same configuration of the project and sometimes even the operating system have to be precisely copied, which is an unreasonable task to do. Moreover, this problem grows larger with the complexity of the circuit.

CAD tools automatically perform the conversion between the graphical schematic and the textual netlist. However, the other way around is not always performed. Moreover, there are some tools available online that allow parsing netlists or converting results from one file format to another, but these tools are limited since parsing netlists is contextual and simulator-dependent. The same is applied for the file formats containing simulation results as most of the time a special tool is needed to view the results, which makes aggregating results challenging. An example of an automated CAD tool is the AWR Design Environment (AWRDE), provided by Cadence, working in a custom language called SAX. This tool works via a simple interface where the user can control any aspect of the environment through code. Users have also access to powerful tools that allow them to modify part of the circuit and generate custom reports programmatically, and even perform analysis in Python. However, this tool requires an expensive licence that not everyone is able to afford and requires some time to learn to properly use its functionalities.

Other tools like PySpice [START_REF] Salvaire | Pyspice[END_REF] allow the generation of netlists and the launch of simulations directly with Python. In this way, both stimuli and configuration live under the same block of logic, which reduces the time between iteration cycles. However, this solution is limited to the NGSpice and Xyce simulators and this can have an impact on the workflow.

III. MOTIVATION

The main issues that motivated the creation of this framework are related to the complexity of generating, manipulating and analysing large parametric and statistical simulations and the repeatability of experiments.

There is a massive trend today towards the sharing of information and the enabling of reproducible science. Unfortunately, when it comes to electrical simulations, the use of proprietary CAD tools (which differ from provider to provider) and foundry-licensed device model libraries makes reproducible science almost impossible. This is mainly due to the fact that even having the full description of an electronic circuit, performing parametric or statistical electrical simulations requires CAD tool-specific configurations, which, if not set exactly, might lead to different results than originally reported. This can hinder the repeatability of experiments as scientists are not able to exactly repeat experiments if they are not provided with all the files and settings of the initial research. This framework was created to solve this issue and allow users to create configurations for projects that can easily be shared between different teams and modified to scale up the number of components by exploiting the facility of manipulating text files (Spice netlists). This also makes our framework easily usable with any CAD tool and underlying electrical simulator.

One of the advantages of our proposed framework is that new users don't need to invest time in learning how to use new simulators or get familiar with the user interface since the syntax is minimal and allows very fast results with minor modifications of the files provided by a commercially available tool.

Fig. 1: Functional diagram of the framework. The combination of templates and parameters is done with the framework outside of the simulator, while the state observer has to be placed by the user inside the netlist.

IV. DESCRIPTION OF THE FRAMEWORK

The framework is divided into two parts. The first part is a spice netlist and simulation configuration builder written in Python. The second one is a Verilog-A module to write the state of an electrical component to a CSV file. Figure 1 shows a small diagram representing how the different parts of the frameworks are combined.

A. Netlist and simulation configuration tool

The main objective of the Python tool is to facilitate the generation of complex electrical parameters as well as inject them inside predefined spice netlists and simulation configuration files, in a similar manner to a text macro system. This tool, which from now on will be referred to as builder, exploits the way electrical components are defined in spice netlists. For example, a MOSFET transistor is defined as shown below. The syntax can slightly change between different spice implementations, but the definition of the parameters is identical. This builder exploits the textual nature of netlists in order to generate the necessary stimuli for the simulations. A set of values can be generated, inserted into the stimuli templates and feed to the simulator. To achieve this, the user needs to define the different stimuli files that will be used as templates and define the functions to generate the values for each iteration. The different input files are treated as templates and processed by the Jinja [6] template engine. An advantage of using a template engine like Jinja is that logic can be embedded directly into the templates, which means that certain parts of a template can be rendered or discarded depending on the values of some variables.

The builder can be configured through a YAML or TOML config file. This file contains metadata, user-defined properties, the command to execute, the list of files to use as templates and the number of iterations to execute. These variables can be accessed directly in the templates.

In order to generate values, the user needs to define one or multiple ValueFactories in Python. These Factories receive the configuration from the YAML file and generate the values for each generation. The user can define as many Factories as desired and they will all be used for every iteration. If one of the Factories however is exhausted (i.e. it doesn't generate more values) the process is stopped. This allows stopping the iterations if some conditions have been met. The user can also define a callback that is run after the command has been executed. This callback has access to the values that have been generated for that iteration and the results of the simulation and can be used for example to perform a clean-up after the simulation.

B. State observer

The state observer is designed for Spice-and Verilog-Abased simulators. It is a sub-circuit that is placed in the schematic and is connected to the components in need of measurements.

For transients simulations, the state observer will write the state measured every time step to a CSV file, so that it can be easily loaded into any conventional software to analyse and extract information. For this reason, the simulation parameter STEP_SIZE found in the simulation environment is particularly important: it allows running the state analyser with the desired granularity. Moreover, as shown in the examples section, the state observer can be modified to save the wanted data only in certain cases, to allow a lighter and more applicationspecific log.

The idea of being able to externally save results in a userdefined file comes also useful in case we want to modify the parameters for the next simulations according to the results just obtained. As an example, we could increase or decrease the step size of parameters depending if we are close or not to the expected working behaviour.

Most of the commercially available software allows exporting simulation results into external files. This process is nevertheless carried out most of the time through a graphical user interface, which slows down the simulation iteration cycle, or the supported file types are not the desired ones.

V. EXAMPLES

A. Ring Oscillator-based Physical Unclonable Function

One example where this framework has been used is the reliability analysis of Ring Oscillator-based Physical Unclonable Functions [START_REF] Vinagrero Gutierrez | On-line reliability estimation of ring oscillator puf[END_REF]. Due to manufacturing-induced variability, the strength of the inverters in the Ring Oscillator shifts the frequency of oscillation from the nominal value. This effect gets aggravated with voltage and temperature variation. The oscillation frequency depends directly on the number of inverters in the Ring Oscillator. Normally, Ring Oscillators tend to have hundreds of inverters. The vast number of stages, as well as the different environmental conditions, make the process of generating these parametric simulations very convoluted.

In order to obtain a distribution of oscillating frequencies, it is necessary to perform multiple simulations while reproducing process variability. Source code 2 shows a small section of the spice netlist that has been converted to a Jinja template. This part generates a chain of inverters where the number of stages is determined by the user variable nstages. In this example, the variability is induced by altering the length and the V th of each PMOS and NMOS. The values are generated using a Factory that draws the values from normal distributions, as seen in the ParamFactory shown in the examples in [2]. Thanks to the Jinja templates, the number of inverters for each Ring Oscillator can be embedded in the logic and configured by the user.

Once the schematic is created, the parameters to simulate the process variability are defined in the same way they have been described in section IV-A and are inserted into the netlist.

B. State observer with VTEAM

The state observer has been highly useful in the analysis of memristive-based logic operations for Logic In-Memory-Computing (IMC) [START_REF] Inglese | Memristive Logic-in-Memory Implementations: A Comparison[END_REF], [START_REF]On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions[END_REF]. In fact, we noted that IMC with memristors is very sensitive to slight variations. To have a working operation, the IMC operations have constraints on the voltage(s) enabling the operations. Variations of the control voltage(s) and of the duration of the operations itself, as well as memristive values not reaching the nominal value, can affect the behaviour of the operation and not allow it to reach the correct result. For this, it is very important to examine the internal state of memristors at any given time to know if the operations have been properly carried out and understand what affected them in case the result is not optimum.

The VTEAM memristor model [START_REF] Kvatinsky | VTEAM: A General Model for Voltage-Controlled Memristors[END_REF] provides several parameters to simulate the behaviour of memristors. Being an open Verilog-A description model, it can be easily modified to add new terminals and provide information about interesting internal variables. For this application, it is important to obtain the internal resistance and the distance of the threshold of the doping region. The state observer saves that data, allowing to have a detailed description of the behaviour that can be used to drive in real-time the evolution of the simulation and the proper parametric settings. For all of the memristors that are connected to the state observer, the absolute time of measurement, the internal resistance and the distance of the doping region are written to a parameterised CSV file.

Source code [START_REF] Inglese | Verilog-a state observer[END_REF] shows an example of the state observer used to save the state of two memristors under the execution of Logic-in-Memory (LIM) operations. The goal of the simulation was to sweep over the control voltage(s) and the duration of the LIM operations to find the best working setting [START_REF]On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions[END_REF]. Hence, for this code, we concatenated the automatic generation of parameters with the state observer. We automatically generated the inputs and the parameters to run the simulation and we saved the simulation times at which each LIM operation is concluded. We also saved the input value(s), the expected output value and selected parameters, including the control voltage(s) and the duration of the operation. During the operation, the resulting file is read by the state observer and it is used to choose the simulation times at which it will save the wanted states. Finally, the resulting CSV generated by the state observer will have all the fields coming from the builder and the read values: This allows the user to have all the information about the executed operation in the same CSV and it supports directly performing data analysis from the collected data to assess the correct behaviour of the studied operations.

Another example where this framework could have facilitated the parametric simulations and the data analysis is in the work described in [START_REF] Fieback | PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory[END_REF], which presents an in-depth analysis of the process, voltage and temperature variability for CIM.

Since the state observer is defined in a Verilog-A file, it can also be integrated with the builder in order to automatically generate the correct number of signals depending on the userdefined configuration. This simplifies the exploration of all the possible space, as the schematic itself will be rendered according to the configuration and the values generated for each iteration.

VI. CONCLUSIONS

The framework shown in this article is able to generate complex parametric electrical simulations in a reliable and repeatable manner. This framework is open-access and opensource and works with any available commercial simulator as it doesn't require major modifications to the files used.

This framework could be further expanded by adding an automated system that can generate the state observer for a given amount of different components based on the configuration of the builder.

1 M1Source Code 1 :

 11 Spice definition of a MOSFET transistor. The slashes indicate that the definition continues in the next line

1 V0( 2 3

 12 vdd 0) vsource dc=${vdd} type=dc {% for s in range(1, props.nstages) -%} 4 I{{loop.index}} (0 net{{s}} net{{s-1}} vdd) INV \ 5 vthp={{ params['vthp'][loop.index0] }} \ 6 vthn={{ params['vthn'][loop.index0] }} \ 7 lp={{ params['lp'][loop.index0] }} \ 8 ln={{ params['ln'][loop.index0] }} 9 {% endfor -%} Source Code 2: Template to generate inverters. The Inverter subcircuit definition has been omitted.

• Provided by the builder -Input value(s), -Expected output value, -Duration of the operation, -Control voltage, -Timestamp for save action execution.• Added by the state observer -Read value(s).


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AVANT-PROPOS -FOREWORD

Alexandre Senegacnik* « Tout d'abord sur un plan purement pratique : il est bon de montrer que le droit comparé n'est pas l'affaire de rêveurs, et que le commerce international, bien au contraire, a besoin de comparatistes ».

René David 1

Le recours à la méthodologie du droit comparé en arbitrage international -le choix de ce sujet pour le premier volume de la nouvelle publication en libre accès de l'Académie internationale de droit comparé s'est imposé avec évidence. Un choix évident, mais pas nécessairement pour les raisons qui pourront venir en premier lieu à l'esprit. En guise d'introduction de ce volume, le professeur Diego P. Fernández Arroyo expose les multiples raisons qui font de l'arbitrage un domaine qui intéresse tout naturellement les comparatistes. L'arbitrage international, tous types confondus 2 , offre un terreau fertile pour des comparaisons. Nul doute que l'appel de René David il y a maintenant plus de soixante ans a été entendu : le droit comparé n'est certainement pas l'affaire des rêveurs/rêveuses, si tant est qu'il l'ait réellement été. Force est de constater qu'il existe un véritable réflexe de la comparaison tant dans la pratique que dans la doctrine.

"First of all, from a purely practical perspective: it is good to show that comparative law is not the business of dreamers, and that, quite to the contrary, international commerce needs comparatists".

René David 1

The use of comparative law methodology in international arbitration-the choice of this topic for the first volume of the new open access publication of the International Academy of Comparative Law seemed evident. An evident choice, but not necessarily for the reasons which might first come to mind. In the introduction of this volume, Professor Diego P. Fernández Arroyo recalls the many reasons which explain why arbitration is evidently a domain of particular interest for the comparatists. International arbitration, all types considered, offers a fertile ground for comparisons. There is no doubt that René David's call more than sixty years ago, has now been heard: comparative law is obviously not the business of dreamers, assuming that it ever really was. One will easily accept that there exists now a true comparative reflex in both practice and scholarship.

L'extraordinaire succès pratique de l'arbitrage international et la compétition parfois féroce qui existe entre les différents acteurs peuvent en partie expliquer ce besoin de (se) comparer. Mais l'attrait principal de l'arbitrage international pour le comparatiste réside sans doute ailleurs ; plus particulièrement dans la singulière réunion d'un ensemble divers de règles mais aussi d'acteursétatiques ou non étatiques, à l'échelon national, international et transnational. C'est la délicate articulation entre ces derniers qui peut alors assurer la résolution efficace des différends. Chaque tribunal arbitral éclaire de manière singulière les questions et concepts de droit auxquels il fait face -kaléidoscope, il peut proposer à chaque fois de nouvelles réponses et approches.

Il importe de préciser que le premier volume de Ius Comparatum n'a pas pour objectif d'offrir des recherches sur ce qu'il semble opportun d'appeler le « droit comparé de l'arbitrage ». Chaque étape de la procédure arbitrale gagne assurément à être éclairée par une analyse comparative des diverses approches législatives et jurisprudentielles (judiciaires mais aussi arbitrales) pertinentes en la matière. L'Académie ne manque d'ailleurs certainement pas de participer à cet effort de recherche aves ses Congrès 2 .

The extraordinary practical success of international arbitration and the sometimes fierce competition which exists between the different actors can explain this need to compare (oneself). But the main interest of international arbitration for the comparativist probably lies elsewhere; more particularly in the singular reunion of a diverse set of rules but also actors-state and non-state, at the national, international and transnational levels. It is the subtle articulation between these which can ultimately ensure the efficient resolution of disputes. Each arbitral tribunal sheds a unique light on the legal questions and concepts it faces-like a kaleidoscope, it can each time propose new answers and approaches.

It is important to clarify that the first volume of Ius Comparatum does not aim to propose new insights on what one may call the "comparative law of arbitration". Certainly, each stage of the arbitration procedure benefits from a comparative analysis of the diverse and relevant approaches in legislations and Case Law (judicial but also arbitral). The Academy certainly does not fail to engage in this research effort through its Congresses. 2 Il s'agit néanmoins avant tout dans ce volume de s'intéresser au recours à la méthodologie du droit comparé par l'arbitre international. C'est ainsi l'utilité du droit comparé dans le quotidien de l'arbitre international qui est ainsi en premier lieu questionnée dans les pages qui suivent. Comment, selon quelle méthodologie et à quel moment l'arbitre recourt-il au droit comparé afin d'accomplir sa mission ? Quelle est la place réelle et souhaitable pour le droit comparé dans la mission de l'arbitre ? Voici quelques questions que le présent volume ambitionne de discuter.

Le présent volume rassemble les contributions d'une conférence organisée le 8 octobre 2019 à Paris. Cette dernière a indéniablement été un succès à bien des égards. L'Académie peut en effet se féliciter d'avoir organisé, avec le soutien de l'École de droit de Sciences Po, une conférence sur un sujet qui mérite sans doute une plus grande attention. La participation record à cette conférence semble confirmer cette intuition. Le Bureau et le Secrétariat de l'Académie remercient tout particulièrement le professeur Emmanuel Gaillard pour sa leçon inaugurale qui éclaire sous un nouveau jour ce singulier tandem que forment ensemble le droit comparé et l'arbitrage international. Il ne fait nul doute qu'il était impossible de trouver une meilleure entrée en la matière. The primary aim is however in this volume to focus on the use by international arbitrators of comparative law methodology. It is thus the usefulness of comparative law in the daily life of the international arbitrator which is ultimately questioned in the following pages. How, according to what methodology and when does the arbitrator use comparative law to accomplish her mission? What is the real and recommended place for comparative law in the mission of the arbitrator? Here are some questions which the present volume aims to discuss. This volume brings together the contributions of a conference organized on October 8, 2019 in Paris. The latter was undeniably a success in many ways. The Academy can pride itself on having organized with the support of Sciences Po Law School, a conference on a topic which undoubtedly deserves greater attention. The record attendance at the conference appears to support this intuition. The Executive Committee and the Secretariat of the Academy particularly thank Professor Emmanuel Gaillard for his inaugural lesson which sheds new light on this singular tandem formed by comparative law and international arbitration. There is no doubt that it would have been impossible to find a better entrée en la matière.

Le Professeur Gaillard réussit le tour de force de discuter une majorité -si ce n'est l'intégralité -des questions soulevées par le sujet de la conférence.

L'Académie peut aussi certainement se féliciter d'avoir permis à des chercheurs et chercheuses en provenance de Professor Gaillard succeeds to discuss most-if not all-the questions raised by the topic of the conference.

The Academy can also certainly pride itself on allowing researchers from several continents to present and discuss their work for the first volume of Ius Comparatum. The Executive Committee and the Secretariat particularly welcome the dialogue initiated between these different generations of researchers.

Finally, the Executive Committee and the Secretariat particularly wish to thank Professors Sylvain Bollée and Pierre Tercier who accepted a largely unprecedented theatrical exercise to conclude our conference. The aim was to stage a discussion about the use of the comparative law methodology between two fictional arbitrators. One should certainly not question the usefulness of this little play. Far from being improvised, it was only light in tone as it offered a different way to discuss the essential questions of the very topic of the conference. It was for evident reasons not possible to include in this volume a mere transcript of this theatrical exchange.

Le lecteur ou la lectrice n'ayant pas eu la chance d'y assister se consolera néanmoins avec, en guise de conclusion, une petite illustration qui rappelle l'un des nombreux points de désaccord entre, d'un côté, l'illustre arbitre Bronson, c.-à-d. celui qui n'accorda décidemment aucune place au droit comparé, et de l'autre l'arbitre Wayne, qui au contraire défend l'idée que le recours au droit comparé est bien un exercice inhérent à la mission de l'arbitre.

Le parti pris de ce premier volume de Ius Comparatum a été de proposer une perspective de recherche originale dans un format inédit pour l'Académie. C'est un grand plaisir de pouvoir enfin partager ce premier volume. Je remercie très chaleureusement l'ensemble des auteurs et le Bureau de l'Académie. Des remerciements particuliers sont adressés au Secrétaire général pour sa confiance tout au long de l'élaboration et de la réalisation de ce projet.

Nevertheless, the reader, who has not had the chance to participate in it, will have to console herself with a little concluding illustration which evokes one of the many points of disagreement between, on the one side, the infamous Arbitrator Bronson, i.e. the one who refuses to give any room to comparative law, and on the other side, Arbitrator Wayne, who to the opposite defends the very idea that the use of comparative law is indeed an inherent exercise in the arbitrator's mission.

The aim of this first volume of Ius Comparatum was to offer an original research perspective in an unusual format for the Academy. It is a great pleasure to finally be able to share this first volume. I warmly thank all authors and the Executive Committee of the Academy. Special thanks are addressed to the Secretary General for his trust throughout the development and implementation of this project.

  Avant-propos -Foreword' Ius Comparatum 1(2020) IV-IX [International Academy of Comparative Law: aidc-iacl.org]

'Arbitrage et droit comparé' 1959 RIDC 11(1).

Les différentes contributions dans ce volume traitent à la fois de l'arbitrage international commercial, d'investissement et sportif. The different contributions in this volume deal with international commercial, investment and sports arbitration.

V. par exemple / see for instance. George A. Bermann (Dir. de publication/Editor), Recognition and Enforcement of Foreign Arbitral Awards: the Interpretation and Application of the New York Convention by National Courts, Springer, Ius Comparatum -Global Studies in Comparative Law, 2017, ISBN 978-3-319-50915-0.