Alternating current AO AND-OR gate AOI AND-OR-INVERTER gate BFX Buffer gate BSIM

Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device size, while embedding more and more complex functionalities in a single chip. However, the continuation of the device-scaling race generates a number of technology challenges. For instance, the downscaling of transistor channel lengths induce short-channel effects (drain-induced barrier lowering and punch-through phenomena); high electric field in the devices tend to increase Hot electron effect (or Hot Carrier) and Oxide Dielectric Breakdown; higher temperatures in IC products generates an increase of the Negative Bias Temperature Instability (NBTI) effect on pMOS devices. Today, it is considered that the above reliability mechanisms are ones of the main causes of circuit degradation performance in the field. This dissertation will address the Hot Carrier (HC) and NBTI impacts on CMOS product electrical performances. A CAD bottom-up approach will be proposed and analyzed, based on the Design-in Reliability (DiR) methodology. With this purpose, a detailed analysis of the NBTI and the HC behaviours and their impact at different abstraction level is provided throughout this thesis.

First, a physical framework presenting the NBTI and the HC mechanisms is given, focusing on electrical parameters weakening of nMOS and pMOS transistors. Moreover, the main analytical HC and NBTI degradation models are treated in details. In the second part, the delay degradation of digital standard cells due to NBTI, HCI is shown; an in-depth electrical CAD analysis illustrates the combined effects of design parameters and HCI/NBTI on the timing performance of standard cells. Additionally, a gate level approach is developed, in which HC and NBTI mechanisms are individually addressed. The consequences of the degradation at system level are presented in the third part of the thesis. With this objective, data extracted from silicon measures are compared against CAD estimations on two complexes IPs fabricated on STCMOS 45nm technologies.

It is expected that the findings of this thesis highly contribute to the understanding of the NBTI and HC reliability wearout mechanisms at the system level. 4.2.1 NBTI Analysis on LDPC 4.2.2 NBTI Analysis on Cortex A9 processor 4.3 CONCLUSION VII 5. CONCLUSIONS AND FUTURE WORK 5.1 CONCLUSION 5.2 FUTURE WORK

Introduction

The semiconductor industry has made great progress in the last four decades. Discrete MOS devices have been embedded into integrated circuits. Integrated circuits have gradually incorporated more and more functions on each chip. Today, it is possible to put an entire mainframe computer on a single piece of silicon. This tremendous growth is directly attributable to the scalability of the silicon MOS transistor to VLSI dimensions.

With the continued scaling of the CMOS devices into the sub-65nm, the impact of the process, voltage, temperature and other environmental variations on the performance of the digital integrated circuits has become extremely important. The increased on-chip operating temperature and the non-proportional scaling of the transistor dimensions with respect to the supply voltage have affected the reliability and the lifetime of these circuits. The accurate modeling of these variations and the accounting of their effects in the estimation of timing performance of the circuits has become one of the most critical issues in the field of IC design.

Negative Bias Temperature Instability (NBTI) and Hot Carrier (HC) are considered to be the dominant drift-related aging effects in current technologies. This thesis addresses the impact of these reliability wearout phenomena on the timing performance of the digital circuits.

In order to give a global context about the reliability mechanisms in CMOS technology, the next sections present an overview of both reliability basic concepts and wearout phenomena such as Electromigration (EM), Time dependent dielectric breakdown (TDDB), NBTI and HC.

Review of Reliability concepts

The reliability is defined as the probability that a system performs its intended function for a specified period of time under stated conditions. The purpose of the reliability is to ensure that the life of the system will be longer than the targeted life and that the failure rate during the normal operating life of the system will be below the target failure rate [START_REF] Strong | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF]. The reliability of semiconductor devices is represented by the failure rate curve (called the "bathtub curve"), which is illustrated in the figure 1-1. The curve can be divided into the three following regions: (1) infant failures, which occur within a relatively short time after a device starts to be used, (2) operating life failures, which occur over a long period of time, and (3) wearout failures, which increase as the device approaches the end of its life. Infant failures are considered to occur when a latent defect is formed in the course of the manufacturing process. For example, a defect can be formed by tiny particles in a wafer during the lithography process, resulting in a device failure later. Often the infant fails reveal technology problems that still to be addressed. These failures may manifest under the stress of the operation. The failure rate tends to decrease with time because only devices having latent defects will fail.

Operating life failures occur during the operational life of the product. In this period, the instantaneous failure rate should be small and the remaining high-quality devices should operate stably. The failures that occur during this period can usually be attributed to randomly occurred excessive stress, such as power surges, and soft errors. Wearout failures occur due to many factors such as manufacturing process and aging of devices. The failure rate tends to increase rapidly in this period. Semiconductor devices are therefore designed so that wear-out failures will not occur during their guaranteed lifetime.

Accordingly, for the production of highly reliable semiconductor devices, it is important to reduce the initial failure rate to ensure the long life, or durability against wear-out failures [START_REF]Semiconductor reliability handbook[END_REF].

Failure Mechanisms

This chapter introduces typical failure mechanisms of semiconductor devices that can be encountered in present nanoelectronic technologies.

Electromigration

Most semiconductor integrated circuits use Al, AlCu or Cu metallization wires for routing signals into and out of the chip or from one part of the chip to another, forming networks of devices on the chip. Failures on chip wiring fall into four categories: open circuit, elevated resistance, short circuit and leakage [START_REF] Sullivan | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF]. Interconnect-induced failures can be provoked by several causes including corrosion, mechanical fracture (generally generated by differences in thermal expansion between adjacent materials during thermal cycling), etc.

These phenomena can occur during chip operation life. Electromigration is a phenomenon that resulting from the movement of metal atoms due to the current flow in a metallic wire. Cu atoms move in the direction of the electron flow. A void occurs near the negative electrode increasing line resistance, eventually leading to failure of the line (cf., Fig. 12). For the case of Cu wires, the failure times usually follow a lognormal distribution with the median lifetime depending on the quality of the interface [START_REF] Hu | Scaling effect on electromigration in on-chip Cu wiring[END_REF], [START_REF] Arnaud | [END_REF].

Time dependent dielectric breakdown

The Dielectric Breakdown is the irreversible change of physical properties of a local spot in the dielectric from low conduction to higher conduction. In the other words, within the dielectric area a tiny spot develops with increased conductivity compared to the rest of the dielectric area that remains nearly unchanged. A breakdown happens after a certain amount of time during which the oxide is subjected to an electrical stress during product operation. Due to the high conductance of the spots, the electric behavior of the area where these spots are localized change drastically. This local change of properties causes the stop operation of the product in most of the cases [START_REF] Wu | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF]. For instance, when an electric field is applied on a transistor gate an injection of the holes in direction to Si bulk is provoked throughout the oxide. As consequence a larger quantity of interface traps are generated. As the number of traps increases, an electric current via the traps is observed due to hopping or tunneling. It has been reported that if the number of traps continues to increase and the traps connect between the gate electrode and the Si substrate, the connection carries a high current that causes the gate oxide film to break down [START_REF]Semiconductor reliability handbook[END_REF] (cf., Fig. 123).

Gate Si

Interface states generation + connection → Oxide break down

Hot Carrier

As CMOS device scaling continues without reducing the supply voltage proportionally, hot carrier degradation became a major problem for long-term device reliability. When a MOS transistor operates in the saturation mode, a high lateral electrical field is generated near the drain (cf., Fig. 1234). This large electrical field accelerates the carriers (electrons or holes) in the channel, driven them to become energetic or "hot". The hot carrier effects can overcome the potential barrier at the Si/SiO2 interface and penetrate into the oxide, generating a degradation of the electrical characteristics of devices such as mobility and threshold voltage [START_REF] Hu | Hot-Electron-Induced MOSFET Degradation --Model, Monitor, and Improvement[END_REF]. In the second chapter, the HC phenomenon as well as its impact on electrical performance of nMOS devices will be explained in detail. V ds V gs main physic concepts about the NBTI phenomenon as well as some analytical models at transistor level will be presented in chapter two.

Design-in Reliability

As mentioned above, besides the NBTI and HC degradation phenomena there are other mechanisms that take parts in the yield reduction of circuits such as Electromigration, TDDB, Electrostatic discharge (ESD) [START_REF] Schreier | Electrostatic Damage Susceptibility of Semiconductor Devices[END_REF]. The interaction between the different wearout mechanisms at distinct design levels have augmented the complexity of reliability analysis and in the same time have reduced the IC design margins. As a consequence, accurate reliability simulations are necessary to guarantee realistic circuit performances at a given time. Design-in Reliability (DiR) approach searches to provide an assessment and reliability improvement at all design levels. DiR methodology refers to the ensemble of models that can provide both correct simulation capability and high analysis capacity for any design. This

Motivation

HCI and NBTI effects have increased the complexity of the timing optimization process in advanced nodes at all design abstraction levels (such as transistor, gate and system levels) due to diverse device offerings and overdrive product requirements.

In this context, one of the main current needs is to propagate the timings upwards into the design hierarchy, where reliability issues can be treated as other verification corner [START_REF] Takayanagi | A dual-core 64-bit ultraSPARC microprocessor for dense server applications[END_REF], using timings originated from the low level characterization of standard cells ( §3.1). Addressing these issues, DiR methodology can be used in order to deploy NBTI and HCI effects from transistor level hierarchically up to gate and system level in advanced nodes.

Throughout this manuscript we provided details on how DiR methodology is used to develop a bottom-up reliability modeling, which is addressed to digital circuits.

Outline of the Thesis

The outline of this dissertation is organized as follows. Chapter 2 reviews the major NBTI and Hot Carrier degradation mechanisms. It also reviews the impact of these phenomena on electrical transistor performance. In the second part, a silicon-CAD combined aging analysis is presented. This analysis is carried out on two IPs: a Low-Density Parity-check (LDPC) codec circuit and a cortex-A9 ARM processor. CAD results are compared against silicon measurements obtained from experimental experiences.

Finally, it demonstrates that it is possible by a bottom-up approach to build transistor-and gate-level models with sufficient accuracy to allow direct comparison with experimental degradations at system-level.

Chapter 5 summarizes the research results of this thesis and discusses about future research work.

The references to sections are identified by the symbol " §".

Chapter 2

Transistor Reliability Modeling

In order to illustrate the NBTI and HCI phenomena and their impact on transistor performance we present an overview of the physics of these phenomena. We will focus on the correlation between the degradation of physical parameters and their impact on electrical parameters.

The first part of this chapter presents the main physical concepts about Negative Bias

Temperature Instability (NBTI). A detailed description of Reaction-Diffusion and Limited

Reaction models will be treated to explain the NBTI effects on CMOS transistors.

The second part describes the electrical implications and the physical behavior of the Hot Carrier Injection (HCI) phenomenon at transistor level. In the last part of chapter the reliability simulation models and their application in the design-in reliability context will be shown.

In the last part of the chapter we will introduce the main characteristics of the reliability simulation as well as the transistor level analytical models for NBTI and HC mechanisms.

NBTI physics overview

Negative Bias temperature Instability is a degradation phenomenon occurring in pMOS transistors at elevated temperatures when a negative voltage is applied to the transistor gate.

As a result, interface states (ΔN it ) are generated at the Si/SiO 2 interface and build up positively charged bulk defects [START_REF] Deal | Surface-State Charge of Thermally Oxidized Silicon[END_REF][START_REF] Frohman-Bentchkowsky | A fully decoded 2048-bit electrically programmable FAMOS read-only memory[END_REF]. NBTI degradation is a result of the contribution of two phenomena. First, the hole trapping and second the generation of the interface states. These mechanisms are explained in detail in the next section.

Physical mechanisms contributing to NBTI damage: Interface Traps and

Positive Charges

The NBTI-induced physical damage has two independent contributions: interface states generation (ΔN it ) and generation or activation of positively charged defects. In turn, this damage is made up of two parts ( §2.2); a permanent component (D P ) "nonrelaxable" made in equal proportion of interface states and positive fixed charges; a recoverable component (D R ), caused by the activation and neutralization of pre-existing holes traps in the oxide. Figure 2-1 shows the relative shift of the interface states generation and the V th increase normalized to 1 when NBTI stress is stopped (2500 sec). During the stress phase A (0-2500 sec), the relative N it concentration and the relative V th increase rapidly. In the relaxation phase B, a strong reduction is observed for the threshold voltage while the interface states density remains almost unchanged. The different relaxation behaviors of the N it and V th suggest the dual nature of the NBTI damage. Additionally, it can be observed that the threshold voltage does not depend only on the interface states density and that the recovery effect is associated with both neutralization of activated hole traps and repassivation of the generated interface states.

Impact of NBTI to pMOSFET electrical parameters

As mentioned early, due to the generation of interface traps and the activation or generation of positively charges defects, the NBTI damage impacts mainly two physical parameters of transistor: the flatband voltage (V FB ) and the effective channel mobility (µ eff ) . Consequently electrical parameters such as I dlin, I dsat , V th and g m are also affected. In order to describe this relation, we will consider the following expressions [START_REF] Rosa | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF][START_REF] Liang | Inversion level capacitance and mobility of very thin gate oxide MOSFETs[END_REF]:

, ( 2-1)
where N + f and N + R are fixed and recoverable positively charges, C ox is the gate oxide capacitance , ΔN D it is the donor-type portion of the interface state generated during the NBTI stress and electrically activated at time t in the pMOS under consideration. , where θ (V -1 ) is the mobility degradation coefficient, V g is the gate voltage and µ 0 is the surface mobility (this equation is only valid in the context of Spice simulations).

During the linear regime (V gs >V th,ext ), the drain current (I dlin ) can be written as [START_REF] Taur | Fundamental of Modern VLSI Devices[END_REF]:

(2-3)
where V th,ext is the extrapolated threshold voltage (assuming a long channel device).

In this relation, R sd is the total source and drain series resistances. The extrapolated V th is directly related to the flatband voltage by: ,

where (defined as Fermi potential at time zero). From equation (2-4), it can be seen that the shift in V th,ext relates to the change in V FB through the next expression:

ΔV th,ext = ΔV FB (2)(3)(4)[START_REF] Validation | [END_REF] Defining the channel resistance as and assuming that R sd << R L, it can be deduced (from the equation (2-3)) that the NBTI-induced shift of I dlin (ΔI dlin ) at a given V gs is related to V th,ext and µ eff shift by the equation , (2-6) with V th,ext0 , µ eff0 and I dlin0 representing the initial values of µ eff ,V th,ext, I dlin respectively (before stress).

Under the R ds << R L condition [START_REF] Rosa | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF], a linear dependence between the saturation current shift (ΔI dsat ) and linear current shift (ΔI dlin ) can be quantified, since:

, where 1 ≤ θ ≤ 2.

(2-7)

The above equation suggests that both I dlin and I dsat follow the same behavior in the time during the NBTI stress (cf., Fig. 2-2), nevertheless the shift of I dlin is almost twice less than the shift of I dsat . Assuming the maximum transconductance (g m ) as g m = (δI dlin / δV gs )V ds , the impact of the NBTI degradation on g m can be defined as follows:

(2-8)

In figure 2-3 it can be observed, that both V th and g m experience the same evolution with the time, showing that in this case the increase in interface states (N it ) and positively charged defects affect both parameters [START_REF] Kimizuka | NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation[END_REF]. An important requirement of any physical model for NBTI is that it should explain the NBTI physical behavior observed in experimental studies. Before presenting the main NBTI modeling approaches, the following section describes key physical aspects of NBTI damage.

Physical picture of NBTI

In order to describe the evolution of transistor parameters under NBTI stress conditions, in this section we describe some of the main NBTI physical characteristics.

Gate oxide electric field dependence

The NBTI dependence on the gate oxide field (F ox ) is clearly illustrated in figure 2

Process dependence (Nitrogen)

Despite the fact that multiple publications [START_REF] Kimizuka | NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation[END_REF] assert the forceful impact of the incorporation of nitrogen on the NBTI degradation, the role of nitrogen on the NBTI enhancement is still not well explained. In [START_REF] Hook | Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration[END_REF][START_REF] Tan | Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET[END_REF][START_REF] Fujieda | Characterization of interface defects related to negative-bias temperature instability in ultrathin plasma-nitrided SiON/Si〈100〉 systems[END_REF] authors suggest that the introduction of the nitrogen at Si/SiO2 interface generates a mechanical stress in the atomic structure. Therefore the nitrogen atoms should modify the interface states creation rate. Nevertheless Huard et al. [START_REF] Huard | NBTI degradation: From physical mechanisms to modeling[END_REF] 1 show that the interface states generation is identical for pure and nitride oxides (cf., Fig. 2-5a). On the contrary figure 2-5b shows that the incorporation of nitrogen increases the recoverable component D R of the NBTI degradation ( §2.1.1.1). Notwithstanding the nitrogen helps in the reduction of both gate leakage current and boron diffusion, nitrogen related-traps close to the Si/SiO 2 interface have a negative influence on electrical parameters of device such as ΔV th , ΔI dsat . 1 Experiments were carried out on MOSFETs with oxide thickness ranging from 1.6 nm to 10 nm. The MOSFETs have gate lengths ranging from 0.1 µm to 10 µm and typically a width of 10 µm. NBTI stress was applied with the gate electrode held at a low constant negative bias (ranging from_0.75 V to_3.5 V) under a temperature ranging from 25 _C to 200 _C while the source/drain and n-well electrodes were grounded

Temperature dependence

By definition, NBTI degradation is a thermally activated process. Figure 23456shows the influence of the temperature on the interface states generation. Two different regimes are observed. First, for low periods of stress time, the N it shift follows a power law behavior. Secondly, for long stress time, the N it reaches the saturation behavior. Figure 2-7 shows that the power law exponent increases linearity with the temperature, this implies that the activation energy E a (as determined through degradation levels in an Arrhenius [START_REF] Huard | Interface traps and oxide charges during NBTI stress in pMOSFETs[END_REF]) at a given time is not a constant value, which is in contradiction with the principles of RD model ( § 2.2.1) which assumes that the dissociation energy of Si-H bonds can be defined by a single value.

NBTI modeling

In this section, we present a description of two main analytical models for NBTI. Detailed illustrations will be provided for the Reaction-Diffusion (R-D) and the Limited Reaction (L-R) models. Based on experimental observations we detail the limitations of the RD model and explain why L-R model allows modeling the NBTI degradation in a better way.

R-D Model

In order to explain the mechanism of negative bias temperature Jeppson and Svensson proposed the first R-D model [START_REF] Jeppson | Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices[END_REF]. This is based on a structural model of Si-SiO 2 interface defects, which assumes the existence of a large number of hydrogen-terminated trivalent Si bonds Si 3 ≡Si-H at the interface (electrically inactive). When a gate voltage is applied, it provokes a field-dependent reaction at the Si/SiO 2 interface that breaks the passivated Si-H bonds generating a neutral hydrogen atom and an interface trap. An interface trap is defined as an interfacial trivalent silicon atom with a non saturated electron Si 3 ≡Si˙.

Several years later, through an extensive mathematical analysis of the charges diffusing phenomenon Ogawa [START_REF] Ogawa | Generalized Diffusion-Reaction Model for the Low-Field Charge Build Up Instability at the Si/SiO2 Interface[END_REF] proposed that the rate at which the Si/SiO 2 interfaces traps are generated is controlled by the diffusion of hydrogen released from the hydrogen passivated defect sites previously. Subsequently, Alam [START_REF] Alam | A critical examination of the mechanics of dynamic NBTI for PMOSFETs[END_REF][START_REF] Alam | A comprehensive model of Pmos NBTI degradation[END_REF] presented an analytical model including the field, temperature and process dependencies of NBTI. This model provided a method to estimate the number of interface traps for a single stress phase, followed by a relaxation phase under three main assumptions: a-) a monoenergetic dissociation of Si-H bond. b-) the breaking of the passivated Si-H bonds at Si/SiO 2 interface when a gate voltage is applied. c-) the neutrality of diffusing species. The mechanism of trap generation as well as the hydrogen diffusion through the interface is explained by the following equations:

- (x = 0) (2-9) (0< x <d) (2-10) (d< x <T PHY ) (2-11) (x >T PHY ) (2-12)
Where x denotes the distance between the interface and the gate, N it is the number of interface traps, N O is the initial number of unbroken Si-H bonds, N H is the hydrogen concentration, k F is the oxide field dependent forward dissociation rate constant, k R is the annealing rate constant, D H is the hydrogen diffusion coefficient, d is the interface thickness, T PHY is the oxide thickness and k P is the surface recombination velocity at the oxide/polysilicon interface. Initial ΔN it rate depends on Si-H bond dissociation (reaction), while the later rate depends on H removal (diffusion).

Description of the R-D model

The general solution of the R-D model in the stress phase anticipates five different regimes of time-dependent interface trap generation. The next paragraphs describe each one of these regimes.

First regime

During the initial stress phase the concentration of hydrogen atoms and interface are both very low, and there is virtually no hydrogen diffusion. Hence the term N it increases with time linearly as:

N it F N Ot (2-13)

Second regime

In this phase, the initial density of Si-H bonds is larger than the number of interface traps that are generated, so N O -N it O . This allows us to make the following approximation for the reaction equation:

k F N O R N H (x = 0)N it (2-14)

Third regime

During this stage, the hydrogen diffusion begins to control the interface traps generation. In these conditions the equation (2-11) suggests:

x = (D H t) 1/2 (2-15)
In the same way the equation (2-10) expresses:

(2-16)

Then the approximate solution is:

(2-17)

The above relation is substituted in (2-9) assuming that net trap generation is so slow that it is negligible in comparison to the right hand side of (2-9), thus it obtains:

(2-18)

Fourth regime

In this phase the hydrogen reaches the oxide/poly-interface. According to equation (2-12) the incoming flux is defined by the following expression:

(2-19)
From equation (2-10) the hydrogen concentration (N H ) becomes:

(2-20)

Substituting the latter equation in (2-9) and assuming that the traps generation is negligible ( ≈ 0), it obtains:

(2-21)

where A is defined as:

Fifth regime

At the end of the stress phase, the general solution of R-D model anticipates quasi-equality between the quantity of Si-H bonds broken and the number of interface traps generated. In

Limited Reaction model

In this subsection, we will analyze the limitations of R-D model, which was presented in the precedent part.

Forward interface traps reaction rate

The R-D model fails to explain the complex behavior of NBTI phenomenon, particularly during the recovery phase as shown in figure 2-11. where the dissociation rate k F is assumed as constant for a given oxide field. However experimental experiences in [START_REF] Huard | NBTI degradation: From physical mechanisms to modeling[END_REF] show than the dissociation rate k F is not constant (see Equation 2-24 defines in an analytical way the degradation rate of every defect, taking into account that every single bond is broken according to a first-order equation, where each of them has a specific time constant depending on their own dissociation energy.

(2-24)

Where , α=kT/σ for τ min < t <τ, T is the bond temperature and τ min is the time constant of the weakest defect.

Figure 2-13 illustrates the theoretical evolution of the interface traps generation as function of stress time, by using equation . This figure can be broken down into 3 parts. First part, represents the short periods of stress (t < τ min ), the degradation is linear, with a slope linked to the defect generation rate of the weakest dissociation energy bonds. Its slope is defined by ΔN it (t)/N 0 ≈ t/τ min . For longer stress time (second part) more and more different bonds (with more elevated dissociation energy) participate to the degradation. Finally, in the last part, the degradation rate reaches a saturation point according to the reduction of the bond numbers to be broken.

Interface generation into permanent part

Another disagreement point with the R-D model is the fact that the R-D model predicts a passivation of the interface traps (created during the stress phase) once the stress is removed.

In other words, once the stress is removed the hydrogen released by the dissociation of the Si-H bonds can diffuse back restoring their passive Si-H state. According to [START_REF] Parthasarathy | [END_REF] the permanent damage can be modeled as a power law:

(2-25)

where Vgs, T and t denote the applied gate voltage, temperature and time respectively. , Ea and n are the voltage acceleration factor ( §3.5.1), activation energy and time exponent respectively. A is a variable factor that depends of the transistor bias (i.e., V ds ) and k the Boltzmann's constant.

In the same way the recoverable damage can be modeled as follows:

, (2-26)
where, d is a time constant factor.

In the rest of this manuscript the L-R model will be used as base model of NBTI degradation to generate all our results.

Hot Carrier Overview

Hot carrier is a well known degradation phenomenon in MOSFETs, which is provoked by high kinetic energy carriers (holes or electrons). When passing through the channel, the carriers can gain enough energy and momentum to be injected into the gate and/or sidewalls oxides, which in turn affects the electrical characteristics of transistors [START_REF] Takeda | Hot carriers effects in MOS Devices[END_REF]. Taking into account the fact that HC degradation depends on both the number of carriers in the channel and their energy, it is important to understand the evolution of these two parameters with technological nodes. In order to illustrate this evolution we will use next expressions:

 lateral electric field (F lat ) is defined as follows

F lat (2-27)
 an approximate value of F lat is given by: F lat where l represents the length transistor and V dd is the supply voltage.

Between 0.5µm and 0.13µm nodes, the scaling dimensions as well as the voltage supply reduction were done in such a way that the lateral electric field remained constant. From 90 nm node, HC degradation has regained importance since supply voltage scaling has been slower despite the rapid reduction of the gate length. This happened because the difference between V th and V dd must be kept in a certain ratio in order to avoid the unwanted transistor switching (cf., Fig. 23456789101112131415161718).

On the other hand, a detailed study of the strongly dependence of the hot carrier degradation with bias polarization was performed by Takeda. In the next section we present in detail the four HC injection modes published in [START_REF] Takeda | Device performance degradation to hotcarrier injection at energies below the Si-SiO2energy barrier[END_REF].

Hot Carrier injection modes

Considering that the nature of HC damage is strongly depending of the bias conditions, four types of HC injection mechanisms can be distinguished:

I.
Channel hot electron (CHE) injection is generated by high kinetic energy electrons "lucky electrons" [START_REF] Shockley | Problems related to p-n junctions in silicon[END_REF], which have sufficient energy to surmount the energy barrier at the Si/SiO 2 interface. This mechanism occurs mainly at V gs = V ds condition.

II. Drain avalanche hot carrier (DAHC) injection .This takes place when a high voltage applied at the drain under non-saturated conditions (Vgs < Vds) results in very high electric fields near the drain, which accelerate channel carriers into the drain's depletion region.

III. Substrate hot electron (SHE) injection, which dominates at V ds = 0V, V gs > 0 and

V bs > 0. This is due to the homogeneous emission of leakage electrons from the substrate into the interface.

IV. Secondarily Generated Hot Carrier (SGHC) injection is induced by secondary impact ionization of substrate carriers [START_REF] Bravaix | Hot carrier reliability study of second and first impact ionization degradation in 0.15mm channel length N-MOSFETS[END_REF] or photon generation [START_REF] Mihnea | Direct observation of secondary ionization current in n-channel MOSFETs[END_REF]. This injection become more important at V bs < 0 condition for the nMOSFET case.

Electrical parameters degradation caused by Hot Carrier phenomenon

As mentioned early, HC impacts the MOSFETs electrical performance. This degradation is mainly produced by two mechanisms. First, the creation of N it at the Si/SiO 2 interface, and, second, the defect generation in surround oxide films silicon bulk. The HC-induced physical damage affects channel parameters such as the effective mobility (µ eff ) and the flatband voltage (V FB ), which in turn modify the parameters such as I dlin, I dsat , V th and g m .

Weak Inversion (V gs < V th,ext )

In this regime, the drain current is dominated by charge carrier diffusion through the channel.

According to [START_REF] Taur | Fundamental of Modern VLSI Devices[END_REF], I dlin can be defined as follows:

(2-29)

where W and L are the device channel width and length, respectively. C ox is the gate oxide capacitance and µ eff is the effective channel mobility. V th,ext is the extrapolated threshold voltage at the stress time t.

And, the body effect coefficient m is defined as:

(2-30)

where C dm is the bulk depletion capacitance per unit area at ψ S =2ψ B condition.

ψ S is the potential surface defined as:

,where N a and ni are the acceptor impurity density and the intrinsic carrier density, respectively.

The C dm depends on depletion (C depl ) and the interface states (C it ) capacitances as follows:

(2-31)

where C it is given by (2-32) with representing the acceptor-type N it at the Si/SiO 2 interface.

The increase of interface states number during a channel hot carrier (CHC) stress will increase the with a consequent reduction of C dm . Considering that subthreshold slope (SS) is:

. From equation (2-29), the SS can be defined by:

(2-33)

From equations (2-32) and (2-33) it can be observed that the V th,1p and V th,ext shifts are related to each other as next:

(2-34)

A large SS variation (%ss) due to an increase in N it during a CHC stress results into a large (ΔV th,1p ) for a small (ΔV th,ext ), as observed in figure 23456789101112131415161718192021.

Assuming a ΔN it = 0, C it becomes also equal a zero, and according to equation (2-31),

C dm = C depl, V th,ext can be defined as :

(2-35)

Strong Inversion (V gs > V th,ext )

In this regime, the drain current is dominated by charge carrier drift through the channel.

According to [Taur08], I dlin is given by:

(2-36)

where V ds * is defined as follows:

(2-37) R d represents the drain-source series resistance at a given stress time t. In this case we assumed that the initial source R S (0) and drain R d (0) series resistances (before stress) are negligible and, due to localized damage in the drain region, only R d is affected during the stress. Combining equations (2-36) and (2-37) we get:

(2-38)

Assuming a negligible increase in drain series resistance, this equation becomes:

(2-39)

From the latter equation I dlin can be defined at a given stress time as follows:

(2-40)

The index "0" designates the initial conditions of the different equation terms (before stress).

HC impact on mobility degradation Δµ and threshold voltage shift ΔV th

In the strong inversion regime, the effective channel mobility at (V ds <V dsat ) condition is given by:

(2-41)

where µ 0 is the channel mobility factor, and θ the channel mobility attenuation factor.

The interface states generation ΔNit can be related to channel mobility factor through According to equation (2-4), the flatband voltage (V FB ) can be defined as:

(2-43) with Ф MS is the poly to Si workfunction difference, Q f the fixed charge density, and Q it (φS) the interface states induced charge density at the surface potential φS. Taking into account that only the change of Q f and Q it contribute to the V th,ext shift during the stress, V th becomes:

(2-44)

Where α is equal to + orfor acceptor-or donor-type N it .

Hot Carrier modeling

Various hot carrier modeling approaches have been developed in order to represent in an analytical way the HC degradation modes and their implications at transistor level. In this section we will see the framework of the Lucky Electron Model (LEM) and the Energy Driven Model (EDM).

Lucky Electron model (LEM)

The injection of carriers into the SiO 2 layer has been typically described by the lucky electron approach [START_REF] Shockley | Problems related to p-n junctions in silicon[END_REF]. In the LEM model the probability that a hot electron at a distance d reach the Si/SiO 2 interface without suffering any energy-robbing collision is given by:

P(d) =e (-d/λ) , (2-45)
where λ is the scattering mean free path of the hot electron in silicon [START_REF] Tam | Lucky-electron model of channel hot-electron injection in MoSFETs[END_REF].

Bulk current in the LEM model

Considering that the bulk current is a good monitor for hot electron effects, since HC degradation is driven by the channel electric field (E lat ), authors in [START_REF] Hu | Hot-Electron-Induced MOSFET Degradation --Model, Monitor, and Improvement[END_REF] proposed a model based on drain and bulk current, which expresses the interface generation states probability as:

(2-46)

where term 1 is a constant and term 2 represents the probability that a channel electron travels a sufficient distance to gain energy without suffering collision. λ is the scattering free path of channel electron. The relation between physical damage (ΔN it ) and the channel mobility as well as V th,ext in linear conditions is described in the next section. Recently, newer energydriven theories have been introduced to generalize the ideas of the LEM, which are presented in the next section.

Energy Driven mechanisms

Experimental evidence shows that the LEM allows describing the HC degradation at elevated values of biases . However this model requires the additional energy gain mechanisms [Rauch01] above the simple model "pure" of heating caused by a high electrical field in order to explain the HC degradation that has been observed in experimental experiences for (cf., 2-24) [START_REF] Tam | Hot-Electron current in very short channel MOSFETs[END_REF]. An attempt to extent the LEM to modern technological nodes (beyond the 0.13µm) was carried out by authors in [Rauch05], which is known as Energy Driven Model (EDM). In this model Rauch included electron-electron scatterings effects and defines the hot carrier rate as follows:

(2-47)

where f(E) is the electron energy distribution function (EEDF) and S(E) is the scattering rate function, this term can be given by S ii (effective impact ionization) or S it (for interface traps generation). The integrand of Eq. (2-47) generally has one or several peak points or "knee", which are points of high curvature associated with dominant energies (Edom).

There are three major mechanisms that affect the hot electron rate. The first of them was evidenced by authors in [START_REF] Bude | Impact ionization and distribution functions in submicron nMOSFET technologies[END_REF], which showed that the EDDF has a significant knee near the maximum energy available (V EFF ) from the steep potential drop at the drain (i.e. at the pinch off point). A second knee is also observed at about 2V EFF , which is produced by the electron-electron scattering (EES).The second mechanism is the single vibrational excitation which is linked to high energy carriers, which adding energy at the system through ionization by impact of phonons with the lattice.

The third mechanism was evidenced by Hess et al.,[START_REF] Hess | Theory of channel hot carrier degradation in MOSFETs[END_REF]. They showed that the bonds may be broken by channel cold carriers (CCC) effects, through a fourth mechanism corresponding to multiple vibrational excitations (MVE). This corresponds to direct excitation of the vibrational modes of the bond by multiple carrier impacts, each of which individually have a low energy, but which can cumulatively break the bond.

Figure 2-24 Comparison between experimental lifetime (symbols) and LEM (lines). The measured TTF have been determinate for 10% I dsat [START_REF] Guerin | Hot-carrier damage from high to low voltage using the energy-driven framework[END_REF].

HU model

Figure 2-24 shows the Time-To-Failure (TTF) against V g . The classical LEM picture [START_REF] Hu | Hot-Electron-Induced MOSFET Degradation --Model, Monitor, and Improvement[END_REF] predicts monotonous increase of TTF when the gate voltage is increased above V g = V d /4, which contradicts experimental observations. Note that LEM model not considers the MVE mechanisms.

Multi-mode model

Electric Simulation

The behavior of an electric circuit depends on the individual behaviors of each one of the circuit elements. The electrical simulators use analytical models or SPICE models to represent the elements of a circuit in order to calculate their operation conditions. Based on electrical laws such as Ohm's law, Kirchhoff's law [START_REF] Dorf | Introduction to electric circuits[END_REF] simulators can carry out a complete electric analysis. Solving linear and non-linear equations, these simulators calculate currents and voltages of each circuit elements. Subsequently, this information can be observed to be observed in a graphical interface. In order to launch an electrical simulation or SPICE simulation, it is necessary to specify three input files: the circuit initial conditions, the circuit elements (Netlist) and the SPICE models. In next section we will introduce the main characteristics of STMicroelectronics (STM) reliability simulation flow, which is used to carry out all reliability simulations presented in this manuscript.

Reliability Simulation

STM Reliability simulation flow

As mentioned earlier in order to execute the reliability simulation is necessary to generate a degraded SPICE model. In the STM reliability flow this work is carried out by User Defined Reliability Module (UDRM). The UDRM is an interface application, which interacts with ELDO simulator to calculate the degradation of each circuit devices. In the first stage of the flow, ELDO computes the operating points of each circuit transistors. Subsequent this information is used by the UDRM to evaluate the amount of damage of each transistor in the circuit (ΔD). This evaluation is carried out with the same step times than ELDO simulations. This evaluation is updated at the end of every time interval and a new simulation is carried out. This process is repeated from T 0 (initial time) to Tage (final age), where the characteristics of the circuit are evaluated. These continual evaluations consume larger resources of CPU time. As consequence, a short transient simulation is chosen to be run. It represents a sample of the operating conditions, which is assumed to repeat through the circuit's lifetime. Finally, the value of the degradation is obtained by an extrapolation of these results at the total of circuit's lifetime in order to generate the degraded SPICE models. where ΔD defines the NBTI/HCI damage for each transistor in the circuit. The ΔD is defined as a function of several parameters such as (operating voltages, operating currents, temperature, stress time).

Age function

As mentioned above, a reliability simulation is performed from a degraded device SPICE model, which is calculated considering the dynamic operations of the circuit (such as stimuli, temperature, supply voltage, etc). However this practice involves the utilization of larger quantity of CPU and memory resources. In order to optimize this simulation process, only the transistor parameters affected by ageing phenomena are considered in the Age function (cf., The Age is a linear function with respect to the time, which is computed from the ΔD.

(2-50) From equation 2-50, the dynamics degradation of Spice parameters can be defined as follows:

HCI degradation into reliability simulation

The model of HC degradation incorporated in the UDRM module is defined as follows [Guerin08] ( §2.3.3.2):

(2-52) where Age1, Age2, Age3 describe the degradation for the high energy mode, medium energy mode and channel cold carriers mode respectively. Equation 2-52 can be also expressed as follows:

(2-53) Note that equation 2-52 is used to compute the HC degradation for each transistor of the circuit.

NBTI degradation into reliability simulation

According to the limited reaction model, the permanent component of NBTI degradation can be modeled for a power law in stress time and voltage which are translated in our modeling as:

(2-54)

Considering that the recovery component of NBTI follows a logarithmic law [START_REF] Tewskbury | [END_REF], this has been modeled as follows:

(2-55) where t S represents the stress time and t R defines the recovery time.

The maximum degradation after a stress time is expressed (when no recovery is considered) as follows:

(2-56) Therefore the total degradation after a stress time and a recovery time is defined as follows:

(2-57)

where ΔR represents the recovery, which depends on the recovery time.

Silicon Validation of NBTI and HC models

In the first part of this section we present some examples of ageing analysis (simulation data), which are compared with experimental data allowing us to validate both NBTI and HCI reliability models at transistor level. The figures presented in the subsections 2.5.1 and 2.5.2 are taken from the manuscript referenced in [START_REF] Parthasarathy | [END_REF].

In order to validate delay degradation predictions of the HCI and NBTI models we must increase the level of abstraction from transistor to gate level. In the second part of this chapter various ageing analysis are carried out on ring oscillator circuits and SRAM memories, the respective CAD-Silicon delay comparisons are illustrated.

Transistor characteristics: HC mechanism

CHC substrate current

CHC I-V Characteristics

For the same device as above, the figure 2-32 shows the results before and after degradation at a stress conditions of V gs = V ds = 2.1V compared to silicon results after 12000s of stress.

Note that there can be some mismatch between simulation and silicon measures even on fresh device, but the amount of degradation is seen to be the same in both silicon experiments as well as ELDO simulation. The second conclusion is that the R-D model (dashed lines) is pessimistic by about 40%, due to its inaccurate recovery dynamics modeling. A reliability analysis was performed in the SRAM with the purpose to identify the most sensitive SRAM part to degradation using our in-house reliability modeling solution ( §2.4.2.2), ( §2.4.2.3) [START_REF] Huard | Managing SRAM reliability from bitcell to library level[END_REF]. In parallel, an ebeam analysis was performed on silicon in order to cross-check simulations results with silicon measures. The ebeam analysis has been done on dedicated pads connected to inner nets at the interfaces of main blocks to obtain timing correlations (before and after stress) at block level. Electrical stress on silicon was performed at-speed in order to simulate real operating conditions. In order to speed-up the simulations 4 only the bottom and top row memory array are considered. We kept the worst case critical paths (slowest). Note that accuracy of the simulations is kept because the not used memory points are modeled by the equivalent static loads.

Two sets of electrical simulations were performed. First, only NBTI phenomenon was enabled. And, second, NBTI and HCI were considered. Table 2-1 shows CAD 5 -Silicon timing correlation calculated on the SRAM critical paths. All values presented in this table are expressed in picoseconds. Note that the precision of ebeam measure is +/-50ps, which is equivalent to a relative error of 5.01%. Timing paths are divided in seven parts. Each part has an initial point and an end point. These points were chosen in order to represent both the write and the read cycles. In figure 2-35 these points are illustrate by the numbers [( 1)-( 8)].

For instance, the operation read "0" at bottom row cycle starts in the point (1), which represents the CLK node (clock) in the control block. The clock signal enables seven sub blocks (designated by the points 2, 3, 4, 5, 6, 7, 8), which allow collecting in the right memory point the data asked. The columns three and four show the comparison between the CAD and Silicon data at two points, before and after the stress, respectively. Finally the columns five and six show the relative error of Eldo simulations with respect to silicon measures (fresh and ageing, respectively). Let us note that this table is a simplified representation of the real SRAM data table, which is shown in the Appendix B.

Three main conclusions are arising from this analysis. The first conclusion is that the degradation was generated largely by NBTI; however the HCI contribution is not negligible (in the experimental experiences). Note that the electrical stress was performed with an external clock at high frequency in order to reproduce a real activity, thus the HC mechanism was activated.

In spite of some cases the relative error reaches a maximum of 16%, we considered that the timings monitored by ebeam technique on the SRAM are well reproduced by ageing simulations. This error can be explained by the fact that the process variability of the silicon wafer in which the measures were done was not properly center with respect to the CAD corners defined for this technology node. 2),( 4),(7)

(5),(6) (8) The third conclusion is that the control logic block was the more impacted by the degradation than the memory points. For instance is widely known that the NOR gates are more sensitive to NBTI degradation (because they have pMOS stacks). Therefore they are more sensitive to a stimuli low (ZERO logic) than the inverters.

HC validation: RO

It is worth to notice that the RO do not have the same number of elements, for example the smallest RO has 8 stages and the bigger has 134 stages.

Summary

In this chapter, we have reviewed the physics of the NBTI and HCI degradation. We have illustrated the main analytical models for NBTI and HCI wearout mechanisms throughout of the last decades. In particular, we have explained the main characteristics of NBTI L-R model and the HC multimode model (in-house models). In the last part of this chapter we presented the silicon validation of the NBTI L-R and HC multimode models at transistor level.

Additionally, a CAD-Silicon timing checking section was presented in order to validate the delay degradation predictions of these two models. In the next chapter we will describe the NBTI and HCI impact at gate level.

Overview of gate level reliability

The layouts of both analog and digital basic cells are designed in a compact manner in order to obtain a best optimization in terms of area, timing and power consumption. Each layout is packed into an abstract representation called a standard cell (SC) and a group of these cells form a standard cell library.

In It is widely known that the propagation delay follows a nonlinear behavior with respect to the capacitance and the operating conditions. During the last two decades several delay analytic models have been proposed in [START_REF] Wang | Scalable delay model for logic and physical synthesis[END_REF], [START_REF] Jeppson | Modeling the influence of the transistor gain ratio and the input-tooutput coupling capacitance on the CMOS inverter delay[END_REF], [START_REF] Maurine | Transition time modeling in deep submicron CMOS[END_REF]. In order to explain the propagation delay concepts in detail, we present the delay analytical model for a CMOS inverter proposed by Lasbouygues in [START_REF] Lasbouygues | Logical effort model extension to propagation delay representation[END_REF]. Despite the fact that the illustration of this approach is only based on the CMOS inverter, most of the formulations and performance factors can be used to other cells (i.e. NAND and NOR). In the following paragraphs, delay model general concepts and its parameters are described.

Propagation delay model at gate level

According to [START_REF] Mead | Introduction to VLSI systems[END_REF], the basic switching process of a CMOS inverter cell can be considered as an exchange of charges between the intrinsic cell and its output loading In order to extend the ideal output transition time metric to the real domain (delay), it is necessary to consider the dynamic of the inverter electrical currents. Following [START_REF] Sakurai | Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas[END_REF],

the current flow supplied by an inverter during the switching process depends of the slope input signals (slow or fast). In figure 3-1, we can observe that the switching current is not constant. In fact, its dynamic evolves over time according to both the charge and the operation conditions. V dd /2

Slow Ramp

ramp signal; the faster the input ramp, the sooner the N transistor will be OFF and the P transistor will be able to charge the output capacitance with a maximum current. For the slow slope input signal ramps, the short circuit period is much longer than for the fast input ramps.

Thus the discharge current is much lower (cf., Fig. 3-1b). Taking into account all these considerations, the delay of an inverter cell can be defined as follows [START_REF] Lasbouygues | Logical effort model extension to propagation delay representation[END_REF]:

(3-2)
where α HL,LH is the Meyer coefficient [START_REF] Tsividis | Operation and Modeling of the MOS Transistors[END_REF], τ IN is the input signal ramp, A HL,LH is a fitting parameter, V th is the threshold voltage (N or P transistors), C IN is the input capacitance, C load is the load capacitance, C DIFF is the diffusion parasitic capacitance and represent the transition time for the fast and slow input signal ramps, respectively.

Impact of ageing phenomena on standard cells delay

It was already shown in the chapter 2 that induced-NBTI/HC damage in CMOS devices is caused by the degradation of physical parameters such as mobility (µ), flatband voltage (V FB ), etc, which in turn affect the electrical performance of transistors. Therefore the electrical performance at standard cell level is also impacted; the performance can be degraded or improved depending of the standard cell environmental factors (operation conditions and design parameters). In order to illustrate how these factors modify the standard cell degradation behavior, an ageing analysis was carried out, where both values of the interface states shift (ΔN it ) and its rate of generation during the stress phase were monitored.

NBTI and HC degradation dependence on Signal Probability, Input Ramp

and Load Capacitance.

In the first part of this subsection we will use the stress monitor function [Parthasaraty06], to describe the differences between the NBTI and HC behaviors during the stress phase.

Subsequently we will present the ageing evolution with both design parameters and operation conditions. Considering the difference between the HC and NBTI behaviors, the next section will address the influences of input ramp for both phenomena. Signal probability ( §3.2.1.3) impact will be analyzed only for NBTI. And, finally the Fan-Out effect on the delay will be consider. N transistors) are in saturation zone (ON state). In this case the two transistors are affected by the degradation. In order to analyze in detail the effect of each phenomenon in the simulation tool we enabled individually each one of the degradation modes. First, let us consider only the NBTI mode (i.e., pMOS device is degraded). The output fall transitions become faster than before (negative change) since nMOS can discharge faster and the output rise transitions are slower, because the PMOS is weaker. On the other hand, if HC mode is considered only, the situation is inverted. Thus the output rise transitions become faster.

Input slope signal on delay degradation

For the fast ramp case of input signal (cf., Fig. 3-3b), the ageing impact on delay is only determined by one transistor because the fast input ramps turn ON a transistor and OFF the other one. In this case, the total degradation in delay is dominated by the damage generated on the stressed transistor, the nMOS in the case of the input toggling down and the pMOS in the case of input toggling up. Figure 3-3c illustrates the difference in the levels of NBTI and HCI degradation for fast and slow input ramps. As we observe in this figure, the HC damage dominates on the NBTI damage for the slow input ramps. On the contrary for the fast input ramps, the HC and NBTI damages have almost the same level. Note that the NBTI degradation increase is due to the augment of duration of the input signal low state. degradation has a weak dependence of FO. This is explained by the fact that NBTI damage is generated only during the input signal stable states (the low state) and considering that the value of the FO slightly affects the duration of the low state signal, we can assume that NBTI is not dependent of FO. Note that the delay degradation increase is due to the driver of the inverter under consideration. As the inverter driver (defined as physical size of the cell) decreases, the electrical capacity to charge a large load capacitance diminishes. > 1,6 < 1,5 < 1,3 < 1,1 < 0,9 < 0,7 < 0,5 < 0,3 < 0,1

Fan-Out impact in the degradation

NBTI delay degradation dependence on Signal Probability

As it is widely known, the NBTI delay degradation is strongly dependent on input cell signal probability [START_REF] Kumar | NBTI-Aware Synthesis of Digital Circuits[END_REF]. On the contrary, HC degradation is not influenced by signal probability. Figure 34567represents an example of inverter delay degradation dependence with the signal probability (defined as the probability that the input signal of a cell is high and denoted by SP) at given S I and C L values. The SP provokes a maximum damage at SP100% and a null damage at SP0% (for the inverter cells). Overall, the curve shows an upward trend of degradation with SP.

Standard Cell Library Characterization Flow

Standard cell library characterization flow generates a complete description of standard cells electrical behavior. Timing (delay performance) and power consumption are characterized for a given technological node specifications, SPICE models and operating conditions. In this manuscript we focus on timing characterization. The standard cells are characterized by applying a ramp voltage source at the input of the cell and an explicit load capacitance at the output of the cell. Then several circuit simulations (Eldo in our case) are executed varying the transition time of the ramp and the value of the load capacitance in order to calculate both the propagation delay and the output transition time (or output signal ramp) for each pair of (S I , C L ). These results are stored in a table, which is used in the subsequently design steps such as the synthesis, place and route, etc ( §4.1).

The PVT (Process, Voltage, Temperature) corner approach is widely used in timing library characterization. It is widely known that the timing performance dynamic depends strongly on this triplet. This method evaluates the performance of cells in three configurations: worst case, nominal case and best case in order to validate the timing performance for all possible combinations of the PVT triplet. For instance, a high voltage, low temperature and a fast Increasing S I process will favor the timing performance (best case), than a low voltage, high temperature and slow process. This assertion is based on three facts. First, as the voltage increases, the available carrier numbers for the switching process increases as well. Second, the low temperature reduces the carrier-phonon scattering, and finally, the fast process ensures a device fast timing response.

Due to the large amount of possible PVT combinations per cell, the characterization of a standard cell library takes time (probably more than a six months) supposing the availability of a huge memory space. As an example a typical cell library can be constituted by at least 500 cells.

The corner method has two main disadvantages. First it consumes a lot of CPU resources.

And, second, this method is not very accurate. Due to the impossibility to simulate all possible combinations of PVT and design parameters present in an IC, in most of the cases an interpolation is done to calculate the delay for certain conditions. This interpolation may induce a significant error in the timing analysis. There are several models used to calculate the delay by interpolation method such as Non-Linear Delay Model (NLDM), Composite Current Source model (CCS), etc [START_REF]Library Compiler: Modeling Timing, Signal Integrity and Power in Technology Libraries User Guide, version F-2011.09[END_REF] (cf., Fig. 3456789). For instance, the NLDM uses lookup tables with C L and S I as indexes. Due to the fact that its accuracy is proportional to the table size, this approach needs larger tables to provide a correct accuracy delay calculations. This can lead to memory blow-out. Moreover, with this approach voltage and temperature are linearly de-rated.

Limitations of STM standard cell library characterization flow: Fresh and Ageing PVTs

Long-term functionality of circuits is based on the reliable operation of each component (cells). In order to assure the correct operation of the circuit, variations introduced by the interaction between environmental parameters (PVT, C L , S I , etc.) and ageing phenomena have to be taken into account in the characterization flow. However testing a large number of configurations is impractical in current industrial practice. As such, in the current STM

Interpolation result

standard cell characterization flow, the effects of ageing phenomena are considered for several combinations of PVT, C L and S I , however only one ageing condition is taken into account. For this condition the value of SP is worth 50%.

Each cell has a specific margin of yield (after stress) imposed by the technical specifications of circuit (mission profile). The mission profile defines the operation mode of a circuit i.e. frequency, voltage, power consumption, etc. A circuit can have different mission profiles depending on the applications in which it will embedded (i.e., smart phone, computers, etc).

For instance, the table 3-1 shows some application profiles for the ARM Cortex-A9 processor ( §4.2.3). capacitance of the gate under consideration. Once the timing degradation for the gate under consideration is computed (from the NBTI -aware library), this timing is added to the intrinsic delay of the gate (delay without NBTI effects) and a final gate delay is obtained.

Authors in [START_REF] Kang | Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance[END_REF] focus their approach in the effect of random dopant fluctuation (RDF) on NBTI degradation. Using a RD-based ΔV th model, the authors developed a statistical NBTI model to predict the impact of the degradation on lifetime circuit performance which is defined as follows:

(3-4)

where σ Nit and µ Nit represent the mean and the standard deviation of Nit generation, which are modeled as Poisson random variables. µΔV th is the nominal (mean) V th degradation due to NBTI, where ΔV th with respect to the time is defined as:

Finally, A G represents the effective channel area.

Approaches in [START_REF] Lorenz | Aging analysis of circuit timing considering NBTI and HCI[END_REF], [START_REF] Paul | Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits[END_REF] are based on static Timing Analyzer methodology to calculate degradation impact at circuit level. The two frameworks provide the degraded gate performance for a given operating condition sets over lifetime circuit.

Unlike what is proposed in the last four approaches by the authors we consider that the R-D model is not the correct physical base to reproduce the NBTI behavior and we will use the model presented in ( §2.2.2).

State of art of HCI gate models

In order to predict the HC damage on a circuit several macromodels have been developed

based on transistor level simulation [START_REF] Weber | Dynamic degradation in MOSFETs-Part II: application in the circuit environment[END_REF], [START_REF] Tu | BERT-Berkeley Reliability Tolls[END_REF], [START_REF] Kuo | Simulation of MOSFET lifetime under AC hot-electron stress[END_REF]. However the reliability simulation is inertly slow, since the transient electrical simulations incorporate the ageing of device parameters during the computation, which results in a larger computational CPU time.

The macromodel methodologies offer a solution to this problem, increasing thus the computational efficiency of reliability analysis.

In this section, two such approaches based on algorithms and look-up tables will be examined.

iRULE: Fast Hot Carrier reliability diagnosis method

iRULE method [START_REF] Teng | iRULE: fast hot-carrier reliability diagnosis using macro-models[END_REF] avoids simulation during the reliability analysis. It employs netlistand geometry-based rules to determine the potentially critical transistors in a circuit. It uses a macromodel (look-up) table, which contains hot carrier degradation values as a function of circuit operation conditions. These tables are generated from a library characterization framework ( §3.3). The physical basis of this approach is the average bond-breaking substrate current method (I BB *) 1 .The authors consider that I BB * over one period of time (T) provides an accurate measure of the dynamic device degradation.

This method transforms series transistors in multi-input logic into an equivalent transistor for simplification. Despite the fact that this framework can handle larger circuits than transistorlevel ones, it is still difficult to consider the behavior of the multi-input logic and the complex logic correctly.

Timing simulation methodology

Kawakami et al., propose a gate aged timing simulation methodology, which is made-up from a ratio based model explained in [START_REF] Yonezawa | Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits[END_REF], [START_REF] Kawakami | Gate-level aged timing simulation methodology for hot-carrier reliability assurance[END_REF] and an unique algorithm, in which the hot carrier degradation timing library is automatically created during the library characterization step ( §3.3) by running the transistor-level simulator. According to the authors, this approach unlike the above one, can easily handle a full chip with multi-input logics. The developed algorithm consists of three parts. First, a fresh simulation is performed by using transistor-level models. Second, all circuits gates are decomposed into primitives.

For instance, AND gate is composed by two primitives a NAND gate and an inverter (primitive-level). In this state each primitive is analyzed in order to calculate their respectively HC-induced damage. Then this stage provides primitive delays and ratios (α).

Finally, in the last stage after recombining primitive data to be gate data, aged timing (T aged ) is obtained by scaling fresh timing (T fresh ) with above ratio according to the next expression:

1

, where I BB represents the substrate current, which is calculated using the model devised by Kuo et al., [START_REF] Kuo | Simulation of MOSFET lifetime under AC hot-electron stress[END_REF]. Following Leblebici et al., [START_REF] Leblebici | An integrated hot-carrier degradation simulator for VLSI reliability analysis[END_REF] the degradation of I-V characteristics nMOS devices is attributed primarily to generation of interface states (ΔNit), which in turn is defined in terms on I BB . In the others words, the power law with the stress time is kept despite the complexity of certains inverters under consideration (such as IVX106 and IVX284, which are composed by various parallel stage of pMOS and nMOS devices). From these results we propose a 3-parameters simplified ageing model for the inverter cells, which is defined as follows:

(3-6)

where S represents the sensitivity of the inverter to ageing, which mainly depends on S I and C L . The second parameter is the power-on time (POT) which is the equivalent stress time with respect to the product mission profile and the nominal voltage. The third parameter is the time exponent n, assuming a power law dependence for the delay degradation.

Two elements form the basis of this methodology. The first element is a well-established ageing dynamics, which is calculated from two PVT corners (a PVT fresh and a PVT aged), since it is impossible to calculate the ageing effects (with enough accuracy) on a standard cell from a single PVT corner ( §2.1.2 and §2.3.2). The second element is a robust procedure to determine the delay of the standard cell for given PVT corners. We use physics-based models to calculate the delay for fresh and ageing PVT ( §2.4.2.2 and §2.4.2.3), since uncorrelated reliability transistor models with silicon physics means a larger reduction of performance at system level [START_REF] Amador | Bottom-up digital system-level reliability modeling[END_REF].

A library characterization-based methodology is the heart of this approach. The parameters S and n are obtained from the ageing dynamics (cf., Fig. 34567891011121314). On the other hand, the POT parameter is calculated from the generic mission profile (cf., Table 3-4). The generic mission profile is calculated from the Early Life Failure Rate (ELFR) method defined in [START_REF]Early Life Failure Rate Calculation Procedure for Semiconductor Components[END_REF], which is used to test the early life failure rate of a product (silicon experiences). The acceleration models with respect to voltage and temperature parameters are defined by equations 3-7 and 3-8 respectively. These models are used to calculate the acceleration factor (A) for the Early Fails Failure (ELF).

(3-7)

where A V defines the voltage acceleration factor, K represents the electric field constant (which is determined experimentally), X defines the thickness of stressed dielectric, γ V is defined as the ratio (K/X) [V -1 ], V A is the stress voltage in accelerated ELF test and V U represent the voltage at normal use conditions.

(3-8)

where A T defines the temperature acceleration factor, E aa represents the apparent activation energy (eV), K is the Boltzmann's constant (eV/°K), T U defines the junction temperatures at normal use conditions of the product (°K) and T A represents the junction temperatures at accelerated conditions (°K).

Precisely, the acceleration factor A is defined as the product of voltage acceleration and temperature factors, An important point to relieve is the difference between the behaviors of parameters S and n. On the other hand, the distribution of n parameter has a small sigma (σ) (cf., Fig. [3][4][START_REF] Validation | [END_REF][6][7][8][9][10][11][12][13][14][15][16][17]. From this result it can be seen that the time exponent n has a weak dependence with the design inputs.

In order to simplify the calculation, a single value of n was assumed. Using (3-6), the degradation delay was evaluated taking into account this approximation. As observed in The new delay degradation results (calculated on the inverter family) agree very well with the original values (cf., Fig. 3456789101112131415). The maximum error obtained for t 3 and t 1 points is the 1.872%.

Therefore the total error generated by the model after n approximation is ~ 1.9%. Retaking our last example, for 10% of mean delay degradation, gate model is accurate within 0.19%.

Extension of the gate analytical model to more complex standard cells

Following the approach presented in the previous section, a data base was built considering the NAND, AND, NOR and AO standard cells. The conditions of the ageing simulations remain identical to section 3.5.1. Linearity analysis was applied on the new data base in order to corroborate the observed results on the inverter family. The data base is composed by 4470 As we observe in figure 3-21, the sigma of the S parameter population is larger. This is due to the strong dependence of S parameter with both standard cell architecture and timing arcs.

Consequently, we consider that all delay degradations of standard-cells library must be characterized by simulators type SPICE in order to ensure an adequate accuracy level in the computes of timing estimations. transistor level models for the t 1 (cf., Fig. 3.22a) and t 3 (cf., Fig. 3-22b). As we can see, the trend observed in the above section is conserved. The maximum error in the calculation is made for t1 point (at n-imposed condition). The largest error of model for this population is 2,636% on the delay degradation. Therefore if we retake the example of 10% of mean delay degradation, the gate level model is accurate within 0.267%. Despite the extra error introduced by the hypothesis made on n parameter (n fixed), we consider this level of accuracy satisfactory to yield accurate timing analysis at gate level.

NBTI analysis on 32 nm CMOS technology

In this section, we present the application of NBTI gate model on CMOS 32nm standard cells. The NBTI gate model can be applied to any technology node since the gate model ageing dynamics is based on physical transistor models. Table 3- AFZF01, AFZR00, AFZR11, AFZF10, BFZF01, BFZR00, BFZR11, BFZF10, CFZF01, CFZR00, CFZR11, CFZF10 Table 3-5 Timing arcs of several standard cells In this table A, B, C, D denotes the input pins of the cell under consideration and Z denotes the output pin. F represents falling edge and R defines a rising edge. Finally 1 and 0 defines the values of the other pins of the cell. For example a vector AFZR1 for a gate of two inputs means that the pin A is set to zero (AF), the pin B is set to one (1) and the output predicted is one (ZR). Due to the complexity of certain gates such as XNOR3X4, which allows a large number of possible combinations of pin values, only the NBTI worst cases are chosen. In the other words the timing arcs presented in this table were chosen in such a way to generate the maximum NBTI delay degradation of the gate. NBTI gate model results are compared with reliability simulation data. In figure 3-23 it can be seen that there is a very good agreement between the gate model predictions and simulations. The maximum error introduces by the model is 2.45%. This result ascertains that the model accuracy was not affected by the change of technological node. The second reason is of this behavior is the strong dependence of HC degradation with respect to the design parameters (i.e., C L and S I ). From this figure it can be observed that the time power law is not conserved at gate level for all timing arcs cases. This is due to the strong electrical parameters influence on delay degradation (especially for the larger values of C L and smaller values of S I ). Then a linear model is not the best representation of the HC degradation. Nevertheless the maximum margin of the relative error (with the reference Eldo simulations) introduced by the equation (3-6) is 2.15% (cf., Fig. 3-25). Note that in this case the order of magnitude of the data sample is picoseconds. In the others terms, the maximum absolute error made by the model is 0.442ps at a nominal degradation of 17.7ps.

Inverter and Buffer standard cells HC characterization

As mentioned early, the HC damage is generated during the periods of switching signals, therefore this phenomenon is highly dependent of the operation frequency of the circuit. As a consequence, we focus our work on Inverters and Buffers, which are very used in circuit clock paths.

Inverter case

We see in figure 3-26 that the gate model predictions are optimistic in most of the cases (in this example) with respect to the transistor model. This can be explained by the fact that HCI degradation decreases at longer stress times, indicating a tendency towards the saturation.

Therefore the HCI degradation previsions of the model can be pessimistic or optimistic depending on the characteristics of the PVTs (i.e., age) used to feed the gate model (Eq. 3-6).

HC characterization for Buffer gates

This section presents the relative error of the gate model for a buffer family (several drivers) carried out in 32nm CMOS technology. In this case we considered various libraries of standard cells for low power applications. Each library was designed with a different type of MOSFET, which changes the speed conduction of the transistor.

Buffer cells

In order to model the HC degradation, a second analytical approach was studied, which is based on the degradation power trend with the ratio of S I /C L .

This approach is also valid for inverters cells. As it can be seen in the figure 3-28, a buffer is composed by certain X number of inverters. Therefore this cell can be analyzed as a single structure or as group of structures. In our case we decided to analyze it as a group of inverters. This type of methodology is widely used because it reduces the complexity of the delay degradation analysis. The C LI values are ranged between 12.6fF and 13.4fF while the C LZ values are ranged between 3.50fF and 13.8fF. The S IA range is defined between 3ps and 18ps and for the S IN between 7.61ps and 9.53ps.

On the other hand, it should not be forgotten that the switching process is strongly dependent of the slope ( §3.1.1). Figure 3-31 focuses on the output inverter data. In this figure it is clearly observed two populations of ramps, fast ramps (light circle) and slow ramps (dark circle). The degradation generated by the slow ramps tends to be lower than the fast ramps;

this can be explained by the fact that the electric current level, available during the switching process for the slow ramps is not the maximum current level as it is the case for the fast ramps. This approach is proved impracticable as S IA , C LI and the switching electrical current are impossible to obtain from the STM library characterization flow. Therefore this approach was not completely developed; this point cannot be explained more in details because we should need to discuss technical aspects, which are protected by an agreement Confidentiality.

Summary

In the first part of this chapter we explained the influence of the design parameters on delay degradation. A detailed description of the standard library characterization flow was presented in the section 3.3.

In the sections 3.5 and 3.7 we proposed a framework to model the timing degradations provoked by NBTI and HCI phenomena, respectively.

In the next chapter, we will address the validation of the gate model at system level.

Static Timing Analysis

Timing analysis is one of the most important verification steps in IC design since it checks the speed specifications of the design, prior to the fabrication [START_REF] Sakallah | Timing verification and optimal clocking of synchronous digital circuits[END_REF], [START_REF] Jouppi | Timing analysis and performance improvement of MOS VLSI designs[END_REF], [Burks 95]. Static Timing Analysis (STA) is a method for computing the expected timing of a design without requiring simulation by checking all possible paths for timing violations ( §4. 1.3).

This technique is pattern independent, which means that it allows the verification of all signal propagations throughout the design, and is applicable to very large designs.

The aim of STA is to find the critical paths in the design. Critical paths are those signal propagation paths that determine the maximum operating frequency of the design. For instance, in a microprocessor, the critical paths are mainly located between the cache memory and the CPU logic. In order to determine the critical paths, STA tool follows the next steps.

Starting at the inputs of the circuit, the latest time at which signals arrive at a node in the circuit is determinated from the arrival times ( §4.1.2) at a certain fan-in (defines as the capacitance of inputs nodes) nodes.

This latest arrival time is then propagated toward the primary outputs. At each primary output, we obtain the latest possible arrival time of signals and the corresponding longest path.

If the longest path does not meet the timing constraints imposed by the designer, then a violation is observed. Alternatively, if the longest path meets the timing constraints, then all other paths in the circuit will also satisfy the timing constraints.

Timing Graph

The

Arrival Times

Given the times at which the signals at the primary inputs of the circuit are stable (or storage elements to primary output), the minimum (earliest) and maximum (latest) arrival times of signals at all the nodes in the circuit can be calculated with a single breadth-first pass through the circuit in topological order. The early arrival time t Ae (c) is the smallest time by which signals arrive at node c from a certain node (i.e., a node) (cf., Fig. 4-1) and is given by: Given the earliest and the latest signal arrival times at the sink nodes, the required times at all other nodes in the circuit can be calculated by processing the circuit in reverse topological order considering each node only once.

The late required time R l (c) at the node c (or the time before which a signal must arrive at a node c) is given by: (4-3)

Similarly, the early required time R e (c) is the required time on the early arriving signals (or the time after which the signal must arrive) and it is given by: (4-4)

In the above equations, FO(c) defines the set of fan-out nodes of c (i.e., the nodes to which there is a timing arc from node c), R l (a) is the late required time at the node a, d ac is the delay of an edge from node a to node c, R e (a) defines the early required time at the node a.

The difference between the late required time and the late arrival time at the node c is defined as the late slack at that node and is given by: (4-5)

Similarly, the early slack at node c is defined by: (4-6) Let us evoke that a flip flop is a register, in which the output (Q node) follows the previously input stored data when the clock signal is high 1 (positive-edge-triggered).

98

In order to assure that the F-Fb stores a correct new data, this data should arrive and hold to a stable level (data arrival) for a certain period of time before (Setup) and after (Hold) the rising edge of CLK (data required). In the more recent technologies (32nm and 28nm) the value of this time period is very small (around some picoseconds).

For instance, when a F-F has been affected by NBTI the timing balance between data arrival and data required can be broken provoking an error in the logic function of the circuit. In the section 4.1.6 it will present a practical example of this timing balance on a typical critical path.

Interconnection Parasitic and STA

The effect of interconnects on circuit performance have to be considered in order to carry out an accurate STA. The interconnect (or interconnect parasitic) represents the effective load seen by the driving gate in terms of resistances and capacitances allowing to calculate the delay of a given path. Let us evoke that a STA is done after the place and route step [START_REF] Kilts | Advanced FPGA Design: Architecture, Implementation and Optimization[END_REF] in order take into account in the circuit delay compute the delay contribution of the interconnect parasitic.

Process and Environmental Variations

Unavoidable variations in the environmental parameters (such as temperature, supply voltage, etc), provoke variations in circuit performances. Moreover, the disturbances present in IC R C 1 C 2 99 manufacturing processes also cause variations in device parameters and circuit performances [START_REF] Zhang | Yield and variability optimization of integrated circuits[END_REF]. As a result, STA have to consider the effect of process and environmental variations. Typically, statistical process and environmental variations are considered by performing analysis using the PVT approach ( §3.3). Usually, STA is performed for three cases: worst case, nominal case and best case in order to check the circuit performance in whole range of conditions.

Timing analysis

At standard cell level the analysis is carried out by using the lookup table generated during the library characterization step, in which the timing arcs from the inputs to the outputs of all library gates are characterized (cf., Fig. 4-4). Using these data, STA commercial tools (such as Synopsys Primetime®) calculate the path delays of a given design. In order to calculate the reliability impact on STM designs two STA are done. First, a fresh STA (at time t= 0), which does not considers the ageing phenomena. Secondly, an aged STA, which includes the ageing impacts on the timing. The results of the STA are presented by Primetime (PT) as a timing report 2 . Note that STA are performed considering signal probability (SP)3 at 50%. Figure 4-4 shows an example of a timing report generated from of a fresh STA and an aged STA (at time t= t age ) [START_REF][END_REF]. A timing report provides detailed timing information about any number of requested paths. Note that in this example we analyzed only one path. The report includes the start and end pin names of the path under consideration, the delays of the gate path (Incr.

column) and the sum of all gate delays (Path. column). This report is divided in three parts. In the first part, the data path information is presented and the total delay of the data path is represented by the line data arrival time. Second part describes the clock path. The total delay of the clock path is defined by the line data required. Finally, in order to verify if the path under consideration has a timing violation, the slack is calculated (third part). In this case, the data arrival time is smaller than the data required, thus the slack is positive after stress (non timing violation).

In the third column of the timing report (cf., Fig. 4-4) we can observe the intrinsic delay (time propagation) of the different path cells (at time t= 0) and in the fifth column we can see these same delays at time t= t age . We can observe that the cell delays have increased on an average of 4% after stress, which does not provoke a timing violation since the slack is positive; however this reduces the speed performance of this circuit path. It is worth to notice that in this example we only illustrate a small portion of a circuit block, however a real product is composed by thousands of blocks, thus although the NBTI does not cause an error in the functionality of the block, the progressive lost of performance in chain of block can induce an error in the logic function of the product. These histograms were calculated using the gate model for 60.000 more critical DATA paths (focusing on paths with setup violations). For the sake of comparison, we also include the experimental F max degradation data (vertical lines). We can observe that the F max degradation is very well aligned with the mean delay degradation of the whole critical path population under consideration. Thus, we consider that this approach provides an accurate way to predict product macroscopic feature (such as F max ) degradation.

NBTI Analysis on Cortex A9 processor

The ARM Cortex™-A9 processor provides high levels of performance and power efficiency.

It is usually used in applications such as: cellular phones, PDAs and games consoles. The A9 processor supports the configuration of 16, 32 or 64KB four way associative L1 caches, with up to 8MB of L2 cache through the optional L2 cache controller. On a 45 nm (STM standard y = 0,9675x + 0,1742 R² = 0,9989 This IP was stressed at 3 different conditions including several stress time, which represent a real mission profile (up to 1000hrs) for a total of 160 parts tested. (c) Figure 4-9 Delay degradations normalized with respect to average of measured F max for the slowest 8825 critical paths of A9 IP for three different stress conditions (POTs). The experimental F max degradation for similar stress conditions is well reproduced. 4-10 shows the correlation between the mean of the F max degradations with respect to the CAD mean for the A9 and LDPC critical path populations. This shows that our modeling approach can be used successfully to analyze complex databases.

Figure 4-10 Correlation plot between the mean delay degradation for both LDPC and A9 set of critical paths and the mean CAD, which was calculated from NBTI gate level

Conclusion

In this chapter, we have presented the application of the NBTI model methodology on complex digital applications. We have demonstrated that it is possible by a bottom-up approach to build a gate-level model with sufficient accuracy to allow direct comparison with experimental degradations at system-level.

Conclusion

This thesis presents a reliability study on CMOS technologies addressing digital applications.

Two major topics are considered in this manuscript, the NBTI and HCI reliability effects at gate level. The NBTI gate analytical model was analyzed in details and used in order to propagate the timing degradation upwards into the design hierarchy.

In the first part of the thesis a deep-analysis is carried out on a large data base of standard cells with the purpose of understanding the influences of the electrical and design parameters in the delay degradation at gate level. From this study, a three parameter analytical approach was proposed to model NBTI effects at gate level. In the same way, a HC dedicated database was also analyzed in order to provide the performance delay degradation caused by HC phenomena, this data base is based on 45 nm and 32 nm standard cells. From of these results, a HC analytical model was proposed in the chapter 3 (section 3.7).

The second part of the manuscript discussed the NBTI impact at system level. The gate level NBTI model was used to compute the effects of NBTI degradation on two IPs: a Low Density Parity Check (LDPC) codec circuit and a cortex A9 processor. Several analytical reliability Static Timing Analysis were calculated using the gate model and subsequently were compared with the experimental data measured on silicon. The NBTI gate level approach was validated with respect to silicon and was showed that the model is accurate to reproduce the NBTI degradation behaviour at system level.

Future Work

This study contains broad reliability analysis at three levels: transistor level, gate level and system level for the NBTI wearout mechanism. However, the characterization framework of the HC phenomena at system level was not carried out. A substantial amount of efforts is still needed between different teams (design and electrical characterization) to achieve the reliability analysis.

Suggestions on the future work are listed below:

The study of the interaction of HC and NBTI phenomena should continue at different abstraction levels, but especially at system level.

In the near future, STM CMOS bulk technology will be replaced by the FDSOI. In this perspective, the influences of the wearout mechanisms on IC performance will probably change. It is mandatory that the new behavior of the wearout phenomena be carefully analyzed. However, the reliability modeling framework presented in this thesis should be able to be integrated with a little effort the new FDSOI reliability analysis.

Finally, some research efforts should be done with the purpose of integrating the Time-Dependent Dielectric Breakdown (TDDB) impacts in a three-part gate model (HC, NBTI and TDDB). given by the electrical conduction aspects of the inverter cell ( §3.1.1) ( §3.2.1.1). This degradation in the delay is not defined by the NBTI phenomenon.

Modélisation de la fiabilité de transistor

L'objective de cette section est d'introduire les notions générales à propos des phénomènes NBTI et HCI. Ensuite nous présenterons leur impact sur les performances du transistor. Ces deux phénomènes seront décrits ici de manière succincte, pour plus de détails je vous invite à consulter le chapitre 2 du manuscrit qui présente ces mécanismes de manière plus exhaustive.

Porteurs Chauds

La réduction de la taille du transistor a permis de réaliser des circuits de plus en plus complexes et rapides. Malheureusement, cette réduction dans taille des transistors comporte aussi des conséquences négatives. Une des plus graves est l'apparition du mécanisme Hot Carrier, qui est devenu un problème majeur pour la fiabilité à long terme du dispositif.

II. L'injection de porteurs chauds au drain en mode d'avalanche (Drain Avalanche

Hot Carrier DAHC). Elle a lieu quand une tension haute est appliquée au drain sous conditions de non saturation (V gs < V ds ). Comme résultat on peut observer la génération des forts champs électriques très près du drain qui accélèrent les porteurs dans la région de déplétion du drain.

III. L'injection des porteurs chauds du substrat (Substrate Hot

Carrier SHC), qui est dominante à V ds = 0V, V gs > 0V et V bs > 0V. Elle est due à l'émission homogène d'électrons (courants des fuites) du substrat à l'interface.

IV.

L'injection des porteurs chauds secondaires (Secondarily generated Hot Carrier SGHC). Elle est induite par l'ionisation par impact secondaire des porteurs dans le substrat [START_REF] Bravaix | Hot carrier reliability study of second and first impact ionization degradation in 0.15mm channel length N-MOSFETS[END_REF]. Elle peut être assiste aussi par des photons [START_REF] Mihnea | Direct observation of secondary ionization current in n-channel MOSFETs[END_REF]. Cette injection devient plus importante lorsque la condition V bs < 0 est vraie.

NBTI

Le mécanisme de dégradation NBTI se produit seulement dans les dispositifs pMOS. Lorsque Puissance de la dégradation du délai par rapport au temps de stress reste valable pour les Inverseurs. Nous incluons également les valeurs expérimentales de la dégradation de la F max du LDPC (lignes verticales).

F max degradation inline with mean critical paths behavior

Nous pouvons observer que la moyenne de la dégradation de la F max est très bien alignée avec la moyenne CAO des dégradations du délai de la population des chemins critiques. Ainsi, nous considérons que cette approche offre un moyen précis pour prédire la dégradation de la F max, qui est une des principales caractéristiques macroscopiques analysées au niveau système et produit. Comme nous pouvons observer les prédictions du modèle au niveau porte ont une corrélation très proche de 1:1 avec les observations expérimentales. Le modèle NBTI au niveau porte reproduit les dégradations du délai avec une marge d'erreur de 2% de la dégradation totale. Donc si la moyenne de la dégradation du délai vaut 10%, l'erreur commise par le modèle est de 0,2 %.

Analyse de l'impact de la dégradation NBTI sur un processeur Cortex-A9

Le processeur ARM Cortex-A9 ™ est généralement utilisé en applications telles que:

2. 5 . 1

 51 Transistor characteristics: HC mechanism 2.5.1.1 CHC substrate current 2.5.1.2 CHC I-V Characteristics 2.5.2 Transistor characteristics: NBTI mechanism 2.5.3 NBTI validation: Ringo Oscillators 2.5.4 NBTI and HCI validation: Static Random Access Memory (SRAM) 2.5.5 HC validation: RO 2.6 SUMMARY3. GATE LEVEL RELIABILITY MODELING3.1 OVERVIEW OF GATE LEVEL RELIABILITY3.1.1 Propagation delay model at gate level3.2 IMPACT OF AGEING PHENOMENA ON STANDARD CELLS DELAY 3.2.1 NBTI and HC degradation dependence on Signal Probability, Input Ramp and Load Capacitance 3.2.1.1 Dependence on Input ramp signal 3.2.1.2 Role of Fan-Out in the degradation VI 3.2.1.3 NBTI dependence on Signal Probability 3.3 STANDARD CELL LIBRARY CHARACTERIZATION FLOW 3.3.1 Limitations of STM standard cell library characterization flow: Fresh and Ageing PVTs 3.4 OVERVIEW OF AGEING MODELS AT GATE LEVEL 3.4.1 NBTI gate models 3.4.2 HCI gate models 3.4.2.1 iRULE: Fast Hot Carrier reliability diagnosis method 3.4.2.2 Timing simulation methodology 3.5 GATE LEVEL NBTI ANALYTICAL MODEL 3.5.1 First stage: Inverter 3.5.2 Extension approach to more complex standard cells 3.6 NBTI ANALYSIS ON CMOS 32NM 3.7 HC GATE LEVEL ANALYTICAL MODEL 3.7.1 HC characterization for Inverter and Buffer cells 3

1

  INTRODUCTION ................................................................................................................................................................. 1.1 REVIEW OF RELIABILITY CONCEPTS .................................................................................................................................. 1.2 FAILURE MECHANISMS ..................................................................................................................................................... 1.2.1 Electromigration ..................................................................................................................................................... 1.2.2 Time dependent dielectric breakdown .................................................................................................................... 1.2.3 Hot Carrier ............................................................................................................................................................. 1.2.4 Negative Bias Temperature Instability .................................................................................................................... 1.3 DESIGN-IN RELIABILITY .................................................................................................................................................... 1.4 MOTIVATION .................................................................................................................................................................... 1.5 OUTLINE OF THE THESIS ...................................................................................................................................................

Figure 1 - 1

 11 Figure 1-1 Reliability bathtub curve, a hazard failure rate plot in units of fails per time

  2 a. EM failure mechanism; schematic illustration. b. Electromigration example in Cu wire

Figure 1 - 3 .

 13 Figure 1-3. TDDB failure mechanism

1 . 2 . 4

 124 4 (a) Illustration of hot carrier stress configuration for an nMOSFET. (b) Lateral electric field in the channel [Guerin08] Negative Bias Temperature Instability NBTI occurs only in PMOS devices. When the gate of pMOSFET is under a negative bias (at high temperature condition), holes in the channel dissociate the Si-H bonds at the Si/SiO2interface generating interface states (cf., Fig.1-5a). The accumulation of these defects (N it ) leads to an increase of the PMOS threshold voltage (cf., Fig.1-5b). Removal of the voltage stress can partially anneal the interface traps (recovery part), but the permanent NBTI component remains, thus the electrical performance of pMOS devices is deteriorated. The

Figure 1 -

 1 Figure 1-5 (a) NBTI DC stress electric configuration. (b) V th shift (squares) and N it -induced V th shift (circles) during an NBTI DC stress [Huard04]

  manuscript addresses only NBTI and HCI reliability wearout mechanisms into the context of DiR methodology [Huard07b]. Several approaches have been proposed since 90's [Minehane00] [Zhihong06]. An example [Leblebici93] of design for reliability flow is showed in figure 1-6. As shown in the figure,the design for reliability flow follows a standard implementation with an exception. The main difference between the standard design flow and that for reliability consists in a reliability feed back into the electrical simulation and circuit design stages. An early ageing analysis allows validating the design characteristics (i.e., topology, size of gates, etc) in order to ensure the life of the circuit.

Figure 1 -

 1 Figure 1-6 VLSI design approach with design for reliability

Chapter 3

 3 focuses on NBTI and Hot Carrier reliability modeling at gate level. Lasbouygues's propagation delay model is detailed here. It also explains the relationship between the reliability simulations and the design flow. In the second part of this chapter, we propose a new framework to propagate the timing degradations upwards into the design hierarchy while considering the mission profile of design under consideration. Chapter 4 addresses the NBTI reliability modeling at system level. Basic definitions and terminology about Static Timing Analysis (STA) are presented in the first part of this chapter.

  NBTI mainly impacts device electrical parameters such as threshold voltage (V th ), linear (I dlin ) and saturation (I dsat ) drain currents, and transconductance (g m ), therefore NBTI is a potential threat in current technologies and designs. Due to the aggressive CMOS scaling trend adopted from 0.13 µm technological node, an enhancement of NBTI degradation has been observed [Alam03]. This fact is mainly explained by the following reasons: a-The introduction of dual poly-process to replace buried channel (n + poly gate) with surface channel (p + poly) pMOSFET and to reduce short channel effects with the transistor scaling trend. b-Slower scaling of the supply voltage compared to more aggressive scaling of oxide thickness produces the gate oxide electric fields increases to values large enough to accelerate the NBTI damage. c-Power supply reduction increases the circuit sensibility to electrical parameters shifts caused by NBTI (i.e. V th ). d-The introduction of nitrogen at the Si/SiO 2 interface of surface channel pMOSFETs to reduce leakage current and boron penetration in p + poly has made NBTI worse.

Figure 2 - 1 .

 21 Figure 2-1. Relative shifts of interface states density (open squares) and threshold voltage (filled squares) [Huard03]

Figure 2 - 2 .

 22 Figure 2-2. I dlin and I dsat evolution as function of time during and NBTI stress [Krishnan03]

Figure 2 - 3 .

 23 Figure 2-3. Vth shift and Gm degradation induced by NBTI.

- 4 [

 4 [START_REF] Huard | NBTI degradation: From physical mechanisms to modeling[END_REF]. Figures2-4a and 2-4bshow the threshold voltage and interface trap density dynamics with the stress time, where the gate voltage (V g ) is changed in a way to keep (V g -V th ) holding almost constant the channel hole population. It is observed that both ΔV th (Fig.2-4a) and the ΔN it (Fig 2-4b) variations rise with increase in F ox[START_REF] Mitani | NBTI mechanism in ultra-thin gate dielectric -nitrogen-originated mechanism in SiON[END_REF].

Figure 2 - 4 .

 24 Threshold voltage shifts (a) and interface state generation (b) as a function of stress time for different bulk biases V b =0V(squares), V b =2V(triangles) and V b =4V (circles) at 125°C. (E ox ≡ F ox )

  5. (a) Oxide field dependence of the interface traps creation for p-MOSFETs for pure and nitride oxides with large oxide thickness range [Huard06]. (b) Nitrogen impact on NBTI behavior. Recoverable part is affected by the nitrogen incorporation into gate while permanent part remains unchanged.

Figure 2 -Figure 2 - 7 .

 227 Figure 2-6. Interface traps density shift at a constant gate voltage stress for temperatures ranging from 50°C to 200°C [Huard06]

Figure 2 -

 2 Figure 2-8. Frequency-independent AC NBTI voltage acceleration is equivalent to the DC NBTI voltage acceleration [Fernandez06]

Figure 2 -

 2 Figure 2-9. Schematic description of the reaction-diffusion model

Figure 2 -

 2 Figure 2-9 shows a description of the R-D model used to interpret interface state generation during NBTI stress. Broken Si-H bonds at the Si/SiO 2 create Si + (interface traps) and H.

  addition, this value becomes constant: → N it ≈ N o = Constant. The five stages of R-D model are represented in figure 2-10. Note that each regime has a different value of slope.

Figure 2 -

 2 Figure 2-10. Five regimes of time dependent interface-trap generation as obtained from the general solution of the reaction diffusion equations during NBTI stress phase

Figure 2 -

 2 Figure 2-11. Models benchmarked against experiments for both the stress and the recovery phases using four devices under tests (DUTs) per stress/recovery conditions (12 DUTs in this case) [Huard07b]

Fig 2 -

 2 Fig 2-12) but distributed as Fermi derivative distribution g(E, σ) defining as follows:

Figure 2 -

 2 Figure 2-12. Forward dissociation rate k F as a function of No [Huard06]

Figure 2 -Figure 2 -

 22 Figure 2-13. Evolution of theoretical degradation rate (filled symbols) with stress time with a disorder-induced variation of dissociation energies for a given temperature, as defined by equation (2-24) [Huard06]

Figure 2 -

 2 Figure 2-14. Interface states generation density shift for constant gate voltage stress (symbols) and fits according to equation 24 (lines) for a temperature range given [50°C-200°C] [Huard06]

Figure 2 -

 2 15 shows that though N it level holds constant after one week of recovery, Vth shifts decrease to the constant N it level (after one week). This experience indicates that the interface traps do not get passivated in this timeframe and are the main contributor of the permanent part [Huard07].

Figure 2 -

 2 Figure 2-15. ΔVth and ΔNIT during NBTI recovering phase. For various stress conditions (stress voltage, dc/ac, and stress time) [Huard07]

Figure 2 -

 2 Figure 2-16. General scheme of the NBTI degradation made up of permanent and recoverable parts [Huard07].

Figure 2 -

 2 Figure 2-17 describes the MOSFET HC-induced wearout process [Rauch09]. The three mechanisms involved in this process are:

Figure 2 -

 2 Figure 2-17. Representation of the physical mechanisms contributing to HC degradation for the nMOSFET case.

  18. (a) Vdd scaling and channel length trends (b) Lateral electric field evolution as function of channel length from equation (2-28) These data are those of Intel until 2003 [Moore03], they were supplemented by those of STMicroelectronics until 2009. [Guerin08]

Figure 2 -

 2 Figure 2-19 2 describes the I dlin evolution as function of V gs at different stress time. It can be observed that the HC degradation reduces the I dlin subthreshold slope, which in turn increases the V th (see figure2-19a). In addition, we can be seen that the V th extrapolated (V th,ext ) experiments a small shift during the stress (cf.,2-19b).

Figure 2 -

 2 Figure2-20 illustrates the I dlin degradation in percentage, which follows a power law dependence in stress time (n ≈ 0.5). This behavior is generally associated with the degradation mobility, which is provoked by the channel ΔNit generation. The parallel evolution of the I d variation (%I d ) with the time between testing at V g ≈ V th and V dd is a further indication that in this case, the HC-induced damage is controlled by the generation of interface states. In order to explain the correlation between the physical and electrical parameters we will analyze an nMOSFET (in 0.25µm CMOS technology).

Figure 2 -Figure 2 -

 22 Figure 2-20. I dlin degradation in percentage as function of stress time at both (V gs ≈ V th ) and (V gs = V dd )conditions[START_REF] Rauch | Reliability Wearout Mechanisms in Advance CMOS Technologies[END_REF]

Figure 2 -

 2 Figure 2-21. Idlin evolution versus V gs . Linear drain current is plotted on both logarithmic and linear scale. [Rauch09]

Figure 2 -

 2 Figure 2-22 gives an example of CHC impact on I ds for nMOSFET device. The N it generation reduces the drain saturation current I ds and the mobility in the channel [Bravaix09]. The relation between physical damage (ΔN it ) and the channel mobility as well as V th,ext in linear conditions is described in the next section.

Figure 2 -

 2 Figure 2-22. Correlation between the degradation of linear parameters as Ids reduction is directly proportional to the mobility reduction and V th shift at the stress bias of maximum I s [Bravaix09].

Figure 2 -

 2 23illustrate the injection hot carrier process as well as the relation between the parameter d, the electron kinetic energy and the hot electron emission energy barrier. An electron at x = d has just enough kinetic energy qV(x) to overcome energy barrier for emission, if it can travel from x = d to the interface at x = 0 without encountering energy-losing collision. That is, qV(d) represents the effective energy barrier for emission[START_REF] Taur | Fundamental of Modern VLSI Devices[END_REF].

Figure 2 -

 2 Figure 2-23. Illustration of the hot electron traveling towards the Si/SiO 2 interface

  Based on the above mechanisms, a HC degradation multi-mode model for CMOS device was introduced in[Guerin08]. This uses quantum-mechanical models to explain the process of carriers gaining energy, through three different mechanisms: I. High-energy channel hot carriers based on direct electron excitation (DEE). This regime is characterized by a low drain current, i.e. low V g . The generated hot holes are attracted to the interface due to negative oxide field generated at (~V g -V d ) condition, with sufficient energy to break interface Si-H bonds. II. Medium energy electrons which is based on electron-electron scattering. In this regime the value of drain current is moderated i.e. moderate energy V d and V g . Most of the carriers induced by impact ionization have not enough energy to break the Si-H bonds. Nevertheless, through carrier-carrier interactions, some of them can access higher energies and thus being able to break the bonds. III. Channel cold carriers based on multiple vibrational excitation (MVE). In this regime distinguish by a high drain current i.e. high V g , the carriers do not have enough energy to break a Si-H bond in a single direct excitation. Besides, their density increases rapidly with V g close to the interface. Due to confinement, the electron density close to the interface strongly increases, which favors the low-energy interactions between electrons and bonds by MVE. Therefore this model defines the hot carrier rate as follows: Rate = , where τ is the device lifetime. Rate = (2-48)where the three terms represent the HC degradation in the high-energy mode, the mediumenergy mode and channel cold carriers, respectively. C 1 , C 2 and C 3 are constants.

Figure 2 -

 2 Figure 2-25 shows the HCI degradation calculated by the equation (2-48). As we can observe, the experimental data have a good agreement even in transition regions between the different degradation modes. Note the strongly dependence of degradation with V d .

Figure 2 -

 2 Figure 2-25 Comparison of multi-mode model (lines) with different regimes to experimental lifetimes (symbols) at five V d different conditions [Guerin07b]

Figure 2 -

 2 Figure2-27, shows a typical reliability flow. First, a "fresh simulation" (before stress) is done with the fresh and original SPICE models using an analog circuit simulator such as ELDO (Mentor Graphics TM ), or HSPICE (Synopsys TM ). In the fresh simulation the circuit activities of devices are evaluated in order to calculate their impact on circuit lifetime. In the second stage flow an "age simulation" (which is divided in two parts: stress phase and characterization phase) is carried out with a new device model "a degraded SPICE model", which is calculated from NBTI/HCI transistor models

Figure 2 -

 2 Figure 2-27 Reliability simulation flow and reliability model generation

Figure 2 -

 2 Figure 2-29 NBTI impact on inverter electrical response [Parthasarathy06]

Figure 2 -

 2 Figure 2-29 illustrates the STM simulation reliability flow. ΔP represents the degradation of the Spice transistor model parameters and it is defined as follows:

Fig 2 -

 2 Fig 2-30). The Age function describes the ageing of each circuit transistor i.e. degradation of V th or µ. From this information the simulator calculates the degradation of the whole circuit.

( 2

 2 -51) As we can see in figure 2-30, compact models have a larger quantity of parameters; this has increased the complexity level of electrical simulations as well as the CPU time. As consequence, the Age function solely considers the electrical parameters affected by NBTI/HCI.

Figure 2 -

 2 Figure 2-30 Compact models evolution

Figure 2 -

 2 Figure 2-31 illustrates the comparison between the simulation results (ELDO simulations) and the experimental measures. As we can observe, the correspondence between the CAD data and silicon data is good for this study case (2.1nm gate oxide nMOS (10mm/0.1mm) in 90nm technology).

Figure 2 -

 2 Figure 2-31 I b /I d matching between SPICE simulations and silicon data. Symbols represent silicon measures and the lines correspond to simulation data

Figure 2 -Figure 2 -

 22 Figure 2-32 Correlation between Eldo simulations and silicon results before and after stress for 2.1nm gate oxide 10/.1 mm NMOS: I d -V ds for large V gs

Figure 2 -

 2 Figure 2-33 Correlation between simulation results (triangles) and silicon data (data points) [Parthasarathy06].

Figure 2 -

 2 Figure 2-34. Frequency drifts from 200+ standard cells-based ring oscillators separated in various sets measured on silicon

Figure 2 -

 2 Figure 2-35 SRAM schematic including wrapped control logic

Figure 2 -

 2 36 illustrates a typical case of the difference between CAD and Silicon corners. As we can clearly observe the definition of the CAD corners depends on several factors such as the die variability, wafer variability, etc.

Figure 2 -

 2 Figure 2-36 Comparison between the CAD and Silicon Corners (defined with respect to threshold voltage of pMOS and nMOS devices) of a given technological node

Figure 2 -

 2 Figure 2-37 shows frequency evolution of 27 RO, which are composed by different cells such as Inverter, NOR and NAND. These RO were carried out in 40nm technology and were stressed at several conditions (including different stress voltages and stress times) [Huard12].In order to favor the HCI degradation all stresses were performed at 25°C. As it can be

Figure 2 -

 2 Figure2-37 Frequency drifts from specific delay chains stressed at various frequencies ranging from 10Mhz to 3GHz. Some chains (blue circle) are blocked (i.e. no oscillation) during life tests[START_REF] Huard | A predictive hierarchical approach to digital system reliability[END_REF]

  In the first part of this chapter we address NBTI and HC reliability effects at gate-level. The influence of design parameters on the standard cell electrical performances is explained in detail in the sections 3.1 and 3.2. Section 3.3 presents the characterization flow of standard cells focusing in the timing characterization aspects. In sections 3.5 and 3.7 we present a novel methodology to model NBTI and HC phenomena at gate level.

3.7. 2 . 1

 21 Buffer cells ................................................................................................................................................... 3.8 SUMMARY ......................................................................................................................................................................

  order to understand how the NBTI and the HC mechanisms affect the electrical performance of the digital standard cells, it is necessary to take into account in the reliability analysis all design parameters of the circuit. Some examples of design parameters are: input signal waveform transition time (fall/rise edge), load capacitance, input signal frequency, etc. The delay is the main characteristic analyzed during the reliability characterization, since NBTI and HC solely affect the timing performance of standard cells. Multiple designs factors, as well as the individual transistor ageing degradation impact the delay propagation of the signals through the combinational and sequential gates. Before introducing the impact provoked by the NBTI and the HC phenomena on the gate delay, we present an overview of the delay modeling of gates.

  capacitance. The output transition time (defined as the transition time of the ideal inverter output signal voltage (V OUT ) can then be directly obtained from the model of charging/discharging current process that occurs during the switching of the cell between two stables states [High-to-Low (HL) or Low-to-High (LH)] and from the amount to charge (C load_total *V dd ) to be exchanged with the output node such as, (3-1)In the equation 3-1 C load_total is the cell output total capacitance, which is given by the sum of internal load, C INT , and fan out load, C EXT . The first term C INT is the sum of the coupling capacitance, C M , between the inputs and output nodes [Tsividis03] and of the transistor diffusion parasitic capacitance C DIFF [Taur98]. Finally I Pmax and I Nmax are the maximum values of the discharging currents in the inverter output node generated by the pMOSFET and nMOSFET devices, respectively.

Figures 3 -Figure 3 - 1

 331 1a and 3-1b show the waveform of the inverter input voltage υ IN , for a fast transition time (fast ramp) and for a slow transition time (slow ramp), Voltage and Current evolution as a function the time for a CMOS inverter, showing an example of a slow ramp and fast ramp For the charging up-case (high-to-low switching), we can observe that for the fast input signal ramp (cf., Fig 3-1a ), V OUT reaches the V dd level very fast, since the short circuit period is shorter [Daga99]. The short circuit inverter mode has a stronger dependence on the input

Figure 3 -

 3  illustrates the N it generation rate for both NBTI and HCI stress calculated on an inverter (45nm technology) by the transistor models ( §2.4.2.2), ( §2.4.2.3) using the stress monitor function of the Eldo simulator. As it can be observed, the degradation HC is produced during the toggling input signal, in contrast to the NBTI degradation that appears when the input signal Vin is stable (cf., Fig.3-2a), more specifically during the high input state. It is worth to note that in order to generate HC damage it is necessary to have a flow of electrons in other words a current, on the contrary NBTI can be caused solely by a voltage.

  figure 3-3.

Figure 3 - 3

 33 Delay shifts provoked by HC on nMOSFET and NBTI on pMOSFET showing that the degradation is strongly dependent of the circuit operation conditions. (a) Slow input ramps. (b) Fast inputs ramps. (c) Summary of total degradation (NBTI+HCI) observed on an inverter [Parthasaraty06]It can be observed that the total degradation depends on the input signal ramp. If the ramp is slow (cf., Fig.3-3a) NBTI and HC effects on delay are opposite, since the two devices (P and

Figure 3 -

 3 Figure 3-4 shows the impact of the Fan-Out (defined as the ratio of load capacitance to input capacitance, FO= C load /C in ) on the HC degradation for an inverter carried out in 32 nm CMOS technology. As discussed by [Leblebici93], [Huard09] the HC physical damage has a strong dependence on the transition shape, which in turn depends of FO and input ramp. As we can see in figure 3-4b, as the FO increases, the defect generation rate augments too.

Figure 3 -

 3 Figure 3-5 shows the delay degradation caused by the NBTI versus the FO for a group of five inverter cells in 45nm CMOS technology. As we can observe in this figure the NBTI

Figure 3 - 5

 35 Figure 3-5 Representation of delay degradation versus CL. This result allows assuming non-NBTI degradation dependence with FO

Figure 3 - 6

 36 Figure3-6 Degradation of nMOSFET in a CMOS inverter cell (45 nm) as a function of input ramp and capacitance load. For this case the HC impact on delay was calculated for a time t =10 years. 0 , 0 0 0 0 , 0 0 2 0 , 0 0 4 0 , 0 0 6 0 , 0 0 8 0 , 0 1 0 0 , 0 1 2

Figure 3 - 7

 37 Figure 3-7 Delay degradation (input vector: IN_falling_OUT_rising) as a function of SP. For a 45 nm CMOS technology inverter

Figure 3 -

 3 Figure 3-8 shows the delay degradation dynamic for several S I values at C L given. It can observe that the upward trend is conserved. Here, the degradation dependence on S I is clearly observed.

Figure 3 - 8

 38 Figure 3-8 Rise delay of an inverter as a function of SP, including the effects of S I (45 nm CMOS technology)

Figure 3 - 9

 39 Figure 3-9 Interpolation absolute error considering a non-linear model for a table of [5X5]; five load capacitances and five input ramps.

Figure 3 -

 3 9 shows an example of the C L (pF) S I (nS) Δ Delay(nS) absolute error induced by the NLDM method [STA00] for a lookup table of [5X5]. For instance, the error induced by this method is 5ps for S I = 1nS and C L = 0.2pF. A second example of the use of the NLDM is illustrated in the figure 3-10. In this case we need to calculate the propagation delay of a certain cell for a pair (S I = 0.32, C L = 0.05) at a given PVT, assuming that this pair was not characterized by simulation. It is therefore necessary to do an interpolation from the nearest neighbor data. The dots in this figure represent index values defined in output file of the library characterization. The delay calculation is carried out as follows. The input ramp, S I = 0.32, falls between the index values 0.098 and 0.587, and the load capacitance C L = 0.05 falls between index values 0.03 and 0.06. These index values correspond to the next x and y coordinates of the four neighboring table points as shown in figure 3-10 (circles). Using the interpolation method the value of z coordinate (delay) is 0.275nS (dashed circles) [Synopsys11].

Figure 3 -

 3 Figure 3-10 Result of delay calculation. Delay value is calculated by two-dimensional interpolation method

Figure 3 -

 3 Figure 3-11 Example of a critical path (smart phone circuit)

Figure 3 -

 3 Figure 3-12 Power law delay degradation (provoked by NBTI) as a function of stress time. A linear trend is clearly observed between delay degradation (Δd) and stress time variables

Figure 3 -

 3 Figure 3-13 shows a histogram of the linearity coefficients calculated on the data base. The data base is composed of 594 elements (represented in the figure as N 594). Note that only the LOW-to-HIGH (L-to-H) input vector was considered in this case. It can be observed that the linearity coefficient histogram confirmes accurately the results shown in the figure 3-12.

Figure 3 -

 3 Figure 3-13 Linearity coefficient histogram obtained from a sample of 594 L-to-H vectors

Figure 3 -

 3 Figure 3-14 Library characterization schematic, showing the computation method of model parameters: sensitivity to ageing (S) and time exponent (n)

( 3

 3 Power-On-Time parameter is defined as the sum of the result of the multiplications of the A factor and of the Equivalent Life Active (ELA) [seconds] for a certain number of modes. (3-10) Note that the acceleration factors are extracted from the High-Temperature Operating Lifetests (HTOL).

Figure 3 -

 3 Figure 3-16 shows the distribution of S parameter calculated from equation (3-6) for the inverter family. As we can observe this distribution presents a wide range of variation. This fact can be explained by the strong dependence of S with electrical parameters (C L , S I ).

Figure 3 -

 3 Figure 3-16 Sensitivity S histogram, showing the strong dependence of S with timing arcs

figure 3 -

 3 figure[3][4][START_REF] Validation | [END_REF][6][7][8][9][10][11][12][13][14][15][16][17][18], the relative error between the gate predictions (with fixed n) and Eldo simulations is smaller.

Figure 3 -

 3 Figure 3-17 Time exponent n histogram, showing the weak dependence of parameter n with timing

Figure 3 -

 3 18 Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 (a) and t 3 (b) time points assuming a unique value of n parameter

  N 4470). As we can see in figure3-19, the coefficient of linearity allows extending the time law power of the degradation NBTI at gate level.

Figure 3 -

 3 Figure 3-19 Histogram of the linearity coefficients for a simple of 4470 timing arcs

Figure 3 -

 3 Figure 3-20 Time exponent n histogram

Figure 3 -Figure 3 -

 33 Figure 3-21 Sensitivity S histogram

Figure 3 -

 3 22 NBTI Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 (a) and t 3 (b) time points, assuming a unique value of n parameter

  [START_REF] Validation | [END_REF] summarizes the standard cells chosen for this study and their corresponding timing arcs.Gate (Xxx denotes the cell driver)

Figure 3 -

 3 Figure 3-23 Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 PVT assuming a unique value of n parameter

Figure 3 -

 3 24 (a) Histogram of the linearity coefficients for a simple of 4470 timing arcs, showing the non-linearity of HC degradation with stress time for larger values of C L and smaller values of S I . (b) Time exponent n histogram. (c) Sensitive parameter histogram As a consequence, the acceleration characteristic factors of each library are represented in this sample ( §2.3.3.4) (cf., 3-24c).

Figure 3 -

 3 Figure 3-25 Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for different values of stress time [10h, 48h, 168h, 500h]

Figure 3 -

 3 Figure 3-26 Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 time point assuming a unique value of n parameter. The negative values of relative error show the optimistic trend of gate model with respect to transistor model (or Eldo simulations)

Figure 3 -

 3 Figure 3-27 shows the relative error of the gate model compared with the transistor model (ELDO simulations). As we can observe in the figure, the maximum error margin of the model is 0.55% on the mean delay degradation. For instance if the standard cell degradation calculated by Eldo is the 2.5% (which is already quite large with current product usage) gate model prediction will be 3.05%.

Figure 3 -

 3 Figure 3-27 Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 time point assuming a unique value of n parameter

Figure 3 -Figure 3 -

 33 Figure 3-28 Schematic representation of a buffer

Figure 3 -

 3 Figure 3-29 HCI Delay degradation with the ratio (S I /C L ) for a buffer driver 4 carried out in 45nm

Figure 3 -

 3 Figure 3-30 HCI delay degradation in percentage as a function of the ratio (S I /C L ) for input inverter (delay on internal node) and output inverter (delay on Z node)

Figure 3 -

 3 Figure 3-31 HCI delay degradation in percentage as a function of the ratio (S I /C L ) output inverter (delay on Z node)

  elementary structure in STA is the timing diagram. The timing diagram is a graphical representation of the design, where each vertex in the diagram corresponds to an input or an output node of the design. Each timing arc has a direction defined by the type of transition at the input and output nodes. For example, there are two timings arcs from the input to the output of an inverter: one corresponds to the IN_rising_OUT_falling and the other to IN_falling_OUT_rising. Each timing arc in the diagram is annotated with the propagation delay of the signal from the input to the output. Figure 4-1 shows the timing diagram for a small combinational circuit. (a) (b) Figure 4-1 Basic diagram with delays and arrival times (a), showing the signal timing arcs (b) Assuming that a and b are 0, the dotted line arcs correspond to rising input transitions at nodes a1, b1 and falling output transitions at node c. The solid line time arcs represent the falling input transitions at nodes a1, b1 and the rising output transitions at node c when a and b are set 1.

Figure 4 -

 4 Figure 4-2 illustrates the concepts of arrival time (i.e., data arrival), required time (i.e., data required) and slack in the context of the STA. In this figure we can observe an example of static timing verification between the signals of the data node (represented in the figure as D)

Figure 4 - 2

 42 Static timing verification of F-Fb. a) Circuit schematic of .b) Diagram of timing: data and clock signals 1 In typical flip-flops, the input data is stored either on the rising edge (low-to-high transition) or on the falling edge (high-to-low transition) of the clock signal. These flip-flops are known as positive-edge-triggered and negative-edge-triggered, respectively. Arrival time i.e, Data arrival

Figure 4 -

 4 3 shows the representation RC of a wire of metal between two cells.

Figure 4 - 3

 43 Figure 4-3 Illustration of the interconnect load for static timing analysis

Figure 4 - 4

 44 Figure 4-4 Primetime report timing generated from STA fresh (without NBTI effects) and a STA age (with NBTI effects, showing the timing library characterization values (orange circles). This report timing is based on the circuit described in figure 4.2. Both STA are carried out at 50% of SP

Figure 4 -

 4 Figure 4-6, shows the histogram of the delay degradation at five different values of POTs.

Figure 4 - 6

 46 Figure 4-6 Histograms of delay degradations based on gate model for the most 60000 critical paths of LDPC IP with respect to the setup violations for various stress conditions (POTs); POT1<POT2<POT3<POT4<POT5

Figure 4 - 7 Figure 4 -

 474 Figure 4-7 Correlation plot between the mean delay degradation for the LDPC set of critical paths under consideration and the mean CAD

  technology) it reaches a clock frequency of 800 MHz [Arm09] (cf., Fig 4-8).

Figure 4 -

 4 Figure 4-8 The ARM Cortex™-A9 processor core

Figure A- 1

 1 Figure A-1 NBTI impact on inverter electrical response

  Lorsqu'un transistor MOS fonctionne dans le mode saturation, un champ électrique latéral très élevé est généré près du drain (cf., Fig. 1-4). Ce vaste champ accélère les porteurs (électrons ou trous) dans le canal en les conduisant à devenir énergiques. L'injection de porteurs chauds dans l'oxyde modifie les caractéristiques électriques du transistor MOS puisqu'elle produit des défauts dans l'interface Si/SiO 2 . 1 (a) Configuration de stress «Porteurs Chauds» pour un diapositif nMOS. (b) Champ électrique latéral dans le canal d'inversion dans un transistor nMOS [Guerin08] La figure 1-2 décrit le processus de dégradation produit par le mécanisme HC dans un nMOSFET [Rauch09]. Les trois mécanismes impliqués dans ce processus sont : dégradation HC est générée par les porteurs qui traversent le canal d'inversion (V gs > V th ), lesquels peuvent acquérir assez d'énergie pour traverser le point de pincement du canal [Sze81]. b -Les porteurs énergétiques peuvent perdre leur énergie par ionisation par impact [Pagey03], contribuant ainsi à augmenter la valeur du courant du substrat. c -Les porteurs chauds peuvent acquérir suffisamment d'énergie pour casser les liaisons d'hydrogène à l'interface Si/SiO 2 générant des états d'interface (ΔN it ). Ces défauts entraînent un changement des paramètres électriques du MOSFET. Cette instabilité dans le transistor peut générer des défaillances à long terme dans les circuits ou ces transistors sont localisés [Rauch09].

Figure 1 - 2

 12 Figure 1-2 Représentation des mécanismes physiques qui contribuent à la dégradation HC pour le cas un transistor nMOS

  le transistor est soumis à une polarisation négative (à haute température), les trous dans le canal de conduction dissocient les liaisons Si-H à l'interface Si/SiO 2[START_REF] Deal | Surface-State Charge of Thermally Oxidized Silicon[END_REF][START_REF] Frohman-Bentchkowsky | A fully decoded 2048-bit electrically programmable FAMOS read-only memory[END_REF] générant des états d'interface (Fig.1-3a). L'accumulation de ces défauts (N it ) entraîne une augmentation de la tension de seuil du transistor (Fig.1-3b). Avec la suppression de la contrainte de tension une relaxation de la dégradation NBTI est observée. Cela est due à l'auto guérison partielle des pièges générées dans l'interface (composante recouvrable du NBTI), mais la composante permanente du NBTI reste, ainsi le rendement électrique des dispositifs pMOS est détérioré.

Figure 1 -

 1 Figure 1-3 (a) Configuration électrique de un stress NBTI de type DC. (b) Evolution du V th (carres) et du N it (circles) pendant un stress NBTI DC [Huard04]

2. 1 . 2 . 1 . 1

 1211 Modèle analytique de NBTI niveau porteDans cette section, nous allons proposer un nouveau modèle de la dégradation NBTI au niveau porte. Tout d'abord, nous analyserons l'effet du NBTI sur la porte la plus simple «l'inverseur». Une extension du modèle est présentée dans la section 3.5.2 du manuscrit, qui est validée pour des cellules plus complexes tels que XNOR, AOI, NAND, etc. De la même façon, cette méthodologie est valide pour modéliser les effets provoqués par la dégradation HC. Pour avoir plus de détails, le lecteur peut s'adresser au chapitre 3 du manuscrit ( § 3.7) Première étape: L'Inverseur Diverses simulations de vieillissement ont été effectuées à différents conditions de stress (en tenant en compte une grande gamme de valeurs de C L et S I ). Nous avons cherché à vérifier si la Loi de Puissance de la dégradation NBTI par rapport au temps de stress observée au niveau transistor reste vraie aussi au niveau porte. Nous avons défini trois temps de stress, t 1 = 0.02 années, t 2 = 2 années et t 3 = 20 années1 . Figure1-5 montre l'évolution de la dégradation du délai par rapport au temps de stress. Comme nous pouvons l'observer, le délai (Δd) augment linéairement avec le temps de stress. Conséquemment, on peut affirmer que la Loi de 1 Afin de calculer l'impact du NBTI dans ces trois points nous avons utilisé le modèle L-R ( §2.4.2.3).

Figure 1 - 5 1

 151 Figure 1-5 Loi de puissance de la dégradation du délai (provoquée par le NBTI) en fonction du temps de stress.

Figure 1 - 6

 16 Figure 1-6 Histogramme de coefficient de linéarité obtenu à partir d'un échantillon de 594 vecteurs (L-H)

Figure 1 - 7

 17 Figure 1-7 Schématique de la caractérisation de bibliothèque de portes (ou Standard Library) montrant la méthode de calcul des paramètres du modèle: sensibilité au vieillissement (S) et le exposant (n)

( 1 - 5 )

 15 définit le facteur d'accélération en tension, K représente la constante de champ électrique (qui est déterminée expérimentalement), X définit l'épaisseur du diélectrique stressé, γ V est défini comme le ratio (K/X) [V -1 ], V A est la tension de stress dans le test accéléré «Early Fails Failure ELF» et V u représentent la tension d'alimentation dans les conditions normales d'utilisation. définit le facteur d'accélération en température, E aa représente l'énergie d'activation apparente (eV), K est la constante de Boltzmann (eV/°K), T U définit la température de jonction à des conditions normales d'utilisation du produit (°K) et T A représente la température de jonction à des conditions d'accélération (°K). Précisément, le facteur d'accélération A est défini comme le produit du facteur d'accélération en tension et le facteur d'accélération en température, paramètre POT est défini comme la somme des résultats des multiplications du facteur A et de l'équivalent de vie active (Equivalent Life Active ELA) [secondes] pour un certain nombre de modes. ∑ Notez que les facteurs d'accélération sont extraits des tests de fonctionnement en haute température et tension (High-Temperature Operating Lifetests HTOL).

  Afin d'obtenir la dynamique de dégradation du délai des chemins critiques un STA «frais» (définie comme une STA à un temps t = 0) et un STA «âgé» (à t=t 1 ) ont été exécutées sur les deux bases de données. Ces STA ont été calculés en utilisant le modèle au niveau transistor présenté dans le chapitre 2 ( §2.4.2.3). Par la suite les différentes conditions de stress des tests HTOL effectués sur les deux IPs ont été converties en ses équivalents Power-On Time (POT) ( §3.5.1). En suit le modèle au niveau porte a été nourri avec les valeurs POT et les valeurs des paramètres S et n (obtenues à partir des STA) afin de calculer l'impact de la dégradation NBTI sur les chemins critiques.

3. 1

 1 Analyse du NBTI sur un LDPC Le circuit LDPC a été fabriqué en technologie CMOS 45nm. Ce circuit est couramment utilisé pour décoder les signaux qui voyagent dans des canaux de transmissions bruyants. La vue du haut niveau du circuit et l'architecture du décodeur du LDPC sont présentés dans la figure 1-8. Cette IP a été stressée à 10 différentes conditions, dont plusieurs temps de stress (jusqu'à 1000hrs) pour un total de 1200 pièces testées. (a) (b) Figure 1-8 (a) Vue du haut niveau du circuit LDPC. (b) Architecture micro décodeur du LDPC La figure 1-9, montre l'histogramme de la dégradation du délai à cinq valeurs des POTs (on montre seulement cinq de dix valeurs dans la figure pour des raisons de visibilité). Ces histogrammes ont été calculés en utilisant le modèle NBTI au niveau porte pour 60.000 chemins de données (en mettant l'accent sur les chemins avec violations de temps de setup).

Figure 1 - 9 JTAG

 19 Figure 1-9 Histogrammes des dégradations du délai calculés à partir du modèle porte pour 60.000 chemins critiques du LDPC pour différentes conditions de stress (POTs). POT1< POT2< POT3< POT4< POT5

Figure 1 -

 1 Figure 1-10 Corrélation entre les moyennes de la dégradation de la F max et les moyennes CAO pour 10 conditions de stress (LDPC)

Figure 1 -

 1 Figure 1-11 Processeur l'ARM Cortex-A9 ™

Figure 1 -

 1 Figure 1-12 Corrélation entre les moyennes de la dégradation de la F max et les moyennes calculées à partir du modèle NBTI au niveau porte (CAO) (LDPC et A9).

TABLE OF CONTENTS

 OF Electrical parameters degradation caused by Hot Carrier phenomenon 2.3.2.1 Weak Inversion (V gs < V th,ext ) 2.3.2.2 Strong Inversion (V gs > V th,ext ) 2.3.2.3 HC impact on mobility degradation ∆µ and threshold voltage shift

	___________________________________________________________________________ 1. INTRODUCTION 2.3.2 ∆V th
	1.1 REVIEW OF RELIABILITY CONCEPTS 2.3.3 Hot Carrier modeling
	1.2 FAILURE MECHANISMS 2.3.3.1 Lucky Electron model (LEM)
	1.2.1 Electromigration 2.3.3.1.1 Bulk current in the LEM model
	1.2.2 Time dependent dielectric breakdown 2.3.3.2 Energy Driven mechanisms
	1.2.3 Hot Carrier 2.3.3.3 Multi-mode model
	1.2.4 Negative Bias Temperature Instability 2.4 ELECTRIC SIMULATION
	1.3 DESIGN-IN-RELIABILITY 2.4.1 Reliability Simulation
	1.4 MOTIVATION 2.4.2 STM Reliability simulation flow
	1.5 OUTLINE OF THE THESIS 2.4.2.1 Age function
	2.4.2.2 HCI degradation into reliability simulation
	2. TRANSITOR RELIABILITY MODELING 2.4.2.3 NBTI degradation into reliability simulation
	2.1 NBTI PHYSICS OVERVIEW 2.5 SILICON VALIDATION OF NBTI AND HCI MODELS
	2.1.1 Physical mechanisms contributing to NBTI damage :Interface Traps and
	Positive Charges
	2.1.2 Impact of NBTI to pMOSFET electrical parameters
	2.1.3 Physical picture of NBTI
	2.1.3.1 Gate oxide electric field dependence
	2.1.3.2 Process dependence (Nitrogen)
	2.1.3.3 Temperature dependence
	2.1.3.4 NBTI frequency independence
	2.2 NBTI MODELING
	2.2.1 R-D Model
	2.2.1.1 Description of the R-D model
	2.2.2 Limited Reaction model
	2.2.2.1 Forward interface traps reaction rate
	2.2.2.2 Interface generation into permanent part
	2.3 HOT CARRIER OVERVIEW
	2.3.1 Hot Carriers injection modes
	V

  Finally Input/Output block is the communicator channel of the SRAM. The operation in the clock cycle is calculated by the control block. When read or write cycle is performed, the address is chosen by the decoder block, subsequently the right word is chosen inside the memory array. In parallel, the input/output block (I/O) collects the data from the memory array for a read cycle or from outside (environment memory, i.e., processor bus) the new data to be saved in the memory array (write cycle).

Figure 2-35 shows a typically SRAM memory, which is mainly divided in 4 parts. Control block leads the control signals i.e. clock, enable, reset, etc. Decoder block selects the address inside memory array for both read and write cycles. Memory array block is composed by all memory points.

Table 2 -

 2

	OPERATION	TIMING PATH	(Silicon/CAD) Fresh(t=0) Ageing	Relative Error(%) Fresh(t=0) Ageing
	WRITE 0 AT	(1) to (4)	970/835	936/880	-13,9	-6,0
	BOTTOM
	ROW	(3) to (6)	1410/1330	1269/1370	-5,7	8,0
	READ 0 AT	(1) to (4)	630/601	774/641	-4,6	-17,2
	BOTTOM
	ROW	(3) to (8)	1450/1459	1341/1510	0,6	12,6
	WRITE 1 AT	(1) to (4)	885/822	873/862	-7,1	-1,3
	TOP ROW	(3) to (6)	1230/1314	1188/1353	6,8	13,9
	READ 1 AT	(1) to (4)	630/604	747/644	-4,1	-13,8
	TOP ROW	(3) to (8)	1475/1457	1305/1509	-1,2	15,6

1 Silicon measures versus CAD data (Eldo simulations) for a SRAM

  .1 OVERVIEW OF GATE LEVEL RELIABILITY ......................................................................................................................... 3.1.1 Propagation delay model at gate level .................................................................................................................. 3.2 IMPACT OF AGEING PHENOMENA ON STANDARD CELLS DELAY ......................................................................................... 3.2.1 NBTI and HC degradation dependence on Signal Probability, Input Ramp and Load Capacitance. ...................3.2.1.1 Input slope signal on delay degradation ........................................................................................................ 3.2.1.2 Fan-Out impact in the degradation ............................................................................................................... 3.2.1.3 NBTI delay degradation dependence on Signal Probability ......................................................................... 3.3 STANDARD CELL LIBRARY CHARACTERIZATION FLOW ................................................................................................... 3.3.1 Limitations of STM standard cell library characterization flow: Fresh and Ageing PVTs ................................... 3.4 OVERVIEW OF AGEING MODELS AT GATE LEVEL ............................................................................................................... 3.4.1 State of art of NBTI gate models ........................................................................................................................... 3.4.2 State of art of HCI gate models ............................................................................................................................. 3.4.2.1 iRULE: Fast Hot Carrier reliability diagnosis method .................................................................................. 3.4.2.2 Timing simulation methodology ................................................................................................................... 3.5. GATE LEVEL NBTI ANALYTICAL MODEL ........................................................................................................................

3 GATE LEVEL RELIABILITY MODELING .................................................................................................................. 33.5.

1 First stage: Inverter .............................................................................................................................................. 3.5.2 Extension of the gate analytical model to more complex standard cells ...............................................................

3.6 NBTI ANALYSIS ON 32 NM CMOS TECHNOLOGY ............................................................................................................ 3.7 HC GATE LEVEL ANALYTICAL MODEL ............................................................................................................................. 3.7.1 Inverter and Buffer standard cells HC characterization ....................................................................................... 3.7.1.1 Inverter case.................................................................................................................................................. 3.7.1.2 HC characterization for Buffer gates ............................................................................................................ 3.7.2 Slope/Capacitance approach ................................................................................................................................

Table 3 -

 3

1 Cortex A9 processor example application profiles

Table 3 -

 3 (from the table. In this mode, both CLK and DATA signals are set to "zero", thus the input signals of cells a, b and e are "zero" for 100% of the time (represented in the figure3-11 whit the dark color). Note that D node of the flip-flop (g cell) is also set to zero. As consequence, cells a, b, e and g are stressed under a NBTI DC stress condition

	(100% of SP).
	Now let us consider that the smart phone is activated in mode number 2 at a time= t1, the
	CLK and DATA signals change to "one" (represented in the figure with light color). In this
	new scenario, the timing performance is affected by the electrical weakness of pMOS
	transistors of a, b, e and g cells, thus the delay in the data path becomes negative (it has
	become faster than previous case). On the contrary, the clock path delay remains stable, this
	situation augments the probability of setup violations ( §4.1.3)
	Mode	Mode name	Lifetime	Voltage	Temperature
	number		% active	mode	in transistor
				[Vdd]	junction [°C]
	1	Cellular Voice	10	0.85	75
	2	Music playback	5	0.85	75
	3	Messaging (SMS, email)	15	1.00	86
	4	Internet navigation	5	1.15	100
	5	Cellular standby	55	0.6	30

2 shows an example of a smart phone mission profile. As it can be observed, each mode has a different stress profile, which in turn may generate different degradation levels. In order to illustrate this concept we give an example in the next paragraph. Consider the figure 3-11, which shows a critical path of a small circuit existing in a smart phone. Let us assumes that the operation mode of the smart phone (during 50% of the time) is the number five

Table 3 -

 3

2 Smart phone example mission profile

Table 3 -

 3 3 summarizes the main characteristics of this inverter group. Several ELDO simulations were performed at various scenarios (including several stress voltage, SP, temperatures, supply voltage for a wide range of [C L , S I ] pairs). Subsequently, least squares method was used to estimate the linearity correlation between the delay degradation values and the stress time values.

	Inverter	Pmos number	Pmos W (nm)
	IVX2	1	0.22
	IVX4	1	0.41
	IVX7	2	0.61
	IVX9	2	0.79
	IVX22	3	0.68
	IVX31	4	0.71
	IVX40	5	0.73
	IVX71	8	0.81
	IVX106	12	0.81
	IVX284	32	0.81
	Table 3-3 Standard cell general characteristics (Inverter family)

Table 3 -

 3 4 Generic mission profile equivalent computation from a smart phone mission profile (Note that this example is not a real mission profile)In order to check the validity of the proposed gate model, a comparison with ELDO-gate model was performed. With this purpose, two extra ageing PVT corners (t 1 , t 3 ) were characterized for the inverter family (note that these extra corners are not part of the STM flow). Thousands of ELDO simulations were performed at two values of the stress time (t 1 , t 3 ), including several stress voltages and a wide range of operating conditions [temperature, supply voltage, C L , S I ]. The value of SP chosen for this study was 50% 2 . Parallel, the equation (3-6) was used to calculate the delay degradation on the inverter family at t 1 and t 3 corners based on the available PVT corners in STM characterization flow.POT maximum margin of error of 1.809% of the total degradation (cf., Fig.3-15a). For example, if the mean delay degradation is 10% gate-level model is accurate within 0.1809%. Relative error of the gate model delay degradation predictions with transistor model (Eldo simulations) for t 1 (a) and t 3 (b) PVT corners. Gate-level model is slightly pessimistic with transistorlevel model by about 1.81% of the degradation

	Figure 3-15 shows the gate model relative error with respect to Eldo simulations. This

analysis shows that the gate-level model is accurate to reproduce delay degradations with a 2 This is the SP value considered in STM characterization flow ( §3.

3.1)

Chapter 4 Reliability Modeling at SoC level

  This chapter describes the reliability estimation at system level using the NBTI gate model presented in chapter 3. It in this context, we present two reliability analyses carried out on a Low-Density Parity-check (LDPC) codec circuit and a Cortex-A9 ARM IPs ( §4.2) in order to verify the accuracy predictions of the gate model at system level. HCI phenomenon is not considered at this level, this point is explained in detail in appendix A.In order to carry out the verification of gate model predictions at system level, several timing analyses were performed using the Static Timing Analysis (STA) tools. Therefore, in the first part of this chapter, a Static Timing Analysis framework is presented, in which the main basic concepts of STA are explained. The basic definitions of this subsection were taken out of the book referenced in[START_REF] Dharchoudhury | The VLSI handbook -Timing and Signal Integrity Analysis[END_REF].

Modèle du NBTI et du HC à niveau Porte A

  Ce flot suit une implémentation standard avec une exception. Cela consiste en une bouclé de feedback entre l'étape «simulation de fiabilité» et l'étape de «conception du circuit». Une première analyse du vieillissement permet de valider les caractéristiques de conception (telles que: la topologie, la taille des transistors à l'intérieur des portes, etc.) afin d'assurer une durée de vie utile du circuit. Si le circuit est conforme aux spécifications de fiabilité, il peut être envoyé à fabrication. cause de la vaste gamme des applications et des sur exigences demandés aux circuits, les phénomènes HC et NBTI ont augmenté la complexité du processus d'optimisation de la conception des circuits dans les noeuds avancés. Dans ce contexte, un des principaux besoins actuels est de propager les délais du transistor vers le haut dans la hiérarchie de conception[START_REF] Takayanagi | A dual-core 64-bit ultraSPARC microprocessor for dense server applications[END_REF], afin de prévoir l'impact de la dégradation au niveau porte ( §3.1) et système.Nous utiliserons la méthodologieDiR afin de déployer les effets du NBTI et du HCI (en commençant au niveau transistor) hiérarchiquement au niveau porte et système. Tout au long du manuscrit nous fournissons des détails sur comment la méthodologie DiR est utilisée pour développer une modélisation des effets de la dégradation du type «bottom-up». Cette méthodologie s'adresse aux circuits numériques.

	2
	Technology Development	Design Rules
		Circuit Design
		and Verification
	Design Update
		Reliability
		Simulation
		Fabrication
	1.3 Design-in Reliability	Test
	Figure 1-4 Méthodologie de conception pour des circuits du type VLSI en tenant en compte la notion
		de fiabilité
	L'interaction entre les mécanismes de vieillissement est différente dans chaque niveau
	d'abstraction du design (ou conception). Cela augmente la complexité de l'analyse de fiabilité
	et en même temps réduit les marges de conception des IC. Par conséquent, les simulations de
	fiabilité doivent être précises pour pouvoir prévoir des performances «réalistes» du circuit à
	un temps donné. Design in-Reliability est une méthodologie qui se propose à améliorer
	l'évaluation de la fiabilité à tous les niveaux de conception des IC. Cette méthodologie
	renvoie à l'ensemble des modèles qui peuvent fournir une simulation et une capacité d'analyse
	élevées et précises pour n'importe quel produit. Cette thèse porte sur la modélisation des effets
	vieillissement NBTI et HCI dans le cadre de la méthodologie DiR présenté en [Huard07b].

Plusieurs approches ont été proposées depuis les années 90 [Minehane00] [Zhihong06]. Un exemple du flot de conception de fiabilité est montré dans la figure 1-4 [Leblebici93].

  Tableau 1-2 Profil de mission générique pour un smart phone (Notez que cet exemple n'est pas un véritable profil de mission) Ce chapitre décrit l'estimation de la fiabilité au niveau système en utilisant le modèle porte, qui a été présenté en la section antérieure. C'est dans ce contexte que nous présentons les analyses de fiabilité effectués sur deux IPs: un détecteur/correcteur d'erreur de type LDPC (Low Density Parity Check) et un Cortex-A9 ( §4.2), afin de vérifier la précision des prédictions du «modèle porte» au niveau système. Le phénomène HC n'est pas analysé à ce niveau, ce point est expliqué en détail dans l'annexe A. Afin de valider le «modèle NBTI au niveau porte» au niveau système, une analyse combinée de vieillissement Silicium-CAO a été effectuée. Nous avons utilisé les résultats des rapports de qualification (tests HTOL) des deux IPs (le LDPC et le processeur Cortex-A9) afin de comparer les valeurs de la F max (définit comme la dégradation de la fréquence maximale d'opération des IPs (ΔF) provoquée par le NBTI) mesurent sur Silicium avec les estimations CAO obtenues à partir du modèle NBTI au niveau porte ( §4.2). Chaque rapport de qualification des IPs contient les mesures HTOL (lesquels ont été réalisés à diverses tensions de stress, temps de stress et températures).

	3 Modélisation NBTI au niveau Système
		I	II	III	IV	V	VI	VII	VIII	IX
		Mode	Mode	Lifetime	Equivalent	Voltage	Temperature in	A T	A V	Normalized
		number	name	(% )active	Life active	mode	transistor			Stress time
					(seconds)	[Vdd]	junction [°C]			at a
										condition
										(V and T°)
										VII*VIII*IV
		1	Cellular Voice	10	18x10 6	0.85	75	0.116	1.325	2.77x10 5
		2	Music playback	5	9x10 6	0.85	75	0.075	1.54	1.49x10 6
			Messaging
		3	(SMS,	15	27x10 6	1.00	86	0.00153	0.0009	3.72x10 6
			email)
		4	Internet navigation	5	9x10 6	1.15	100	0.1284	1.55	1.79x10 6
		5	Cellular standby	55	99x10 6	0.6	30	0.0002	0.00	0.000
	Total	Generic Mission Profile	100	Equivalent stress time at given condition (voltage and temperature)	35.56x10 6
										POT

For a nMOSFET of the 0.25 µm CMOS technology with source and drain design made up of a single shallow. As drain (8.0E14, 10 Kev) and halo BF2 (2.4E13, 55 Kev,

301).

For instance in a SRAM (512 words x 32 bits) the memory array is composed by 16384 memory points. As a consequence the simulations have become slow since the larger number of transistors.

The CAD data used in this correlation were calculated, taking into account both reliability phenomena (NBTI and HCI).

PT is the STA tool used in this manuscript.

In the STM characterization flow the value of the SP is set to 50%.

Acknowledgement

I would like to express my gratitude to Ing. Vincent Huard and Prof. Lorena Anghel, my thesis advisors. They not only gave me important guidance, but also allowed me to explore various approaches and topics freely during various stages of this project. I am indebted to Prof. François Marc to Prof. Alain Bravaix to Ing. Nadine Buard and Ing. Michael Nicolaidis to spend their valuable time in serving in my thesis committee. I am grateful to Ing. Xavier Federspiel, Ing. Emmanuel Pion, Ing. Florian Cacho, Ing. Emmanuel Vincent, Ing. Remy Chevallier, Ing. Sylvain Landelle, Ing. Pierre F. Ollagnon, Ing. Sylavin Engels, Ing. Maryline Parra, Ing. Manuel Sellier and Ing. Etienne Maurin of STMicroelectronics. They have provided great help on this project.

DATA 0/1 f 1 f 2 Chapter 5 Conclusions and Future Work

5 CONCLUSIONS AND FUTURE WORK ....................................................................................................................... 5.1 CONCLUSION ................................................................................................................................................................ 5.2 FUTURE WORK .............................................................................................................................................................

Consequently, we have developed an ageing gate model, which allows estimating the timing degradation considering every single product mission profile from a fresh PVT and an aged PVT. The background of the delay model at gate level as well as our approach will be detailed in the following sections.

Overview of ageing models at gate level

In order to quantify the impact of NBTI and HCI on the temporal delay of standard cells, several CAD frameworks for managing CMOS wearout mechanisms have been developed in the last years. Wang et al.,[START_REF] Wang | The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis[END_REF] presented an analytical model based on the Reaction-Diffusion (R-D) framework. For a given set of environmental conditions (i.e., supply voltage, temperature, etc) the authors utilize a NBTI transistor model defined by equation to compute the threshold degradation (ΔV th ) of a given transistor in a certain gate. , where β t is the fraction parameter of the recovery, T clk represents the time period of one stress-recovery cycle, α defines the SP, ξ 1 and ξ 2 are constants, n is the time exponent parameter, which is worth 1/6 (in this case) and K V is a complex parameter, which depends on electrical field and temperature (among others).

State of art of NBTI gate models

With the degraded threshold voltage (ΔV th ), the authors employ SPICE simulations to extract the propagation gate delay (t P ) under discrete working conditions (i.e., discrete values of ΔV th ). The discrete values of t P (calculated by SPICE simulations) are then connected by fitting Chebyshev polynomial series in order to obtain a gate delay model depending on ΔV th .

Subsequently authors use an algorithm of circuit timing analysis (considering NBTI effects), to evaluate the timing degradation due to NBTI for each gate (i) in a circuit. The inputs of this algorithm are: input signal probability, the slew rate of the input signal and the load (3)(4)[START_REF] Validation | [END_REF] where m, t fresh and t aged are the number of primitives in the target gate, fresh and aged input-tooutput delays at primitive-level respectively.

We consider that the physical model in which these last two approaches are based fails to explain the complex features of HCI degradation, which were presented in ( §2. 3.3.2).

Therefore we will use the multi mode model ( §2.3.3.3) as base of our HCI gate model.

Gate level NBTI analytical model

In this subsection we will propose a new gate level NBTI model, which will be described in detail. First we will analyze the NBTI effect on the simplest standard cell "the Inverter". An extension of the model is presented in section 3.5.2, which is validated for more complex cells such as XNOR, AOI, NAND, etc. In these equations FI(c) represents the set of all fan-in nodes of c, i.e., all nodes that have and edge to c, d ac is the delay of an edge from a to c.

First stage: Inverter

These equations can be used to calculate both the arrival times and the delays at node c from its fan-in nodes. A breadth-first pass through the timing graph using Eqs. 4-1 and 4-2 will yield the arrival times at all nodes in the circuit.

In order to illustrates the concept of arrival time let us consider the timing graph of the figure 4-1a, and assuming that the arrival times at the primary inputs a and b are 0. Let's define the maximum arrival time for a rising signal at node a1 as t Al,r = 1, and the maximum arrival time For instance if the node a is set 0 and the node b is set 1 we can calculate the total latest arrival time at node c using Eq. 4-2. For this condition, the t Al at node c is given by the b path delay (d bc ), which is defined as t Al,r,b (c)= 1+ 3+ 2= 6 (longest path) while that the a path delay is given by t Al,r,a (c)= 1+ 1+ 2= 4. Note that in this case we considered that nodes a and b are the firsts nodes of the circuit and we assume the input delays as t Al,f,r (a,b)= 0.

Required Times and Slacks

Usually the constraints are placed on the arrival time of signals at the primary output nodes of a circuit based on performance or speed requirements. Additionally, the timing constraints are imposed on the clocked elements inside the design such as flip-flops, latches, etc. These timing constraints allow checking the correct functionality of the circuit in terms of speed.

The nodes in the circuit where the timings checks are done are called sink nodes.

As mentioned earlier, due to the technical difficulties in terms of CPU and engineer time, in the industrial ambit is impractical to execute the reliability STA for each one of the mission profile scenarios. Therefore, we use the gate model in order to estimate analytically the reliability impact on the design (or reliability STA) taking into account the mission profile.

Next section illustrates the application of NBTI gate level model on complex designs.

Evaluation of NBTI degradation at system level

In order to validate the NBTI gate modeling approach at system level, a silicon-CAD combined ageing analysis was performed. We used the accelerated stress results from

NBTI Analysis on LDPC

The LDPC circuit was carried out in a 45nm Low-Power bulk technology. This LDPC codec supports the 12 modes required by the 802.11n standard (Wifi). This circuit is commonly used to decode noisy transmission channel. The top circuit and the LDPC decoder micro For the NBTI analysis the fresh and the reliability simulations can be executed for the worst case pair C L , S I (in terms of timing degradation) and only the characterization simulations are performed for the whole range of (C L , S I ) previously defined in the technical specifications.

This consideration is based on weak dependence of NBTI with C L , S I (cf., Fig. A-1). In this way all library is analyzed and its performance is ensured. On the other hand in HC analysis these three types of simulations must to be executed for the same pair (C L , S I ). This requires larger CPU resources and involves larger execution time. 1 The simulation of characterization uses the degraded SPICE models.

It is worth noting that the conditions of characterization simulation are exactly the same as the conditions of the fresh simulation.

Appendix B SRAM Silicon/CAD comparison table

In the table B-1 the first column defines operation (i.e., write or read) under consideration.

The second column shows both the initial and the end points of the timing path. Columns three and four show the data measured on silicon, before and after the stress, respectively.

Finally the columns five and six describe the data obtained by Eldo simulations (fresh and ageing, respectively). Les grandes lignes de la thèse sont précisées par la suite. La première section examine les principaux mécanismes de la dégradation NBTI et Porteurs Chauds. Elle présente aussi l'impact de ces phénomènes sur le rendement électrique du transistor. La section 2 met l'accent sur la modélisation des phénomènes NBTI et Porteurs Chauds au niveau «porte logique». Dans cette partie, nous proposons un nouveau modèle de propagation de la dégradation de délai des portes logiques vers le haut dans la hiérarchie de conception (niveau système) tout en tenant compte le profil de mission de la porte considérée. La section 3 porte sur la fiabilité NBTI au niveau système. Dans cette section nous présentons une analyse combinée de vieillissement (Silicium-CAO). Cette analyse est effectuée sur deux IPs: un détecteur/correcteur d'erreur de type LDPC et un processeur ARM cortex-A9. Des résultats CAO obtenus par simulations sont comparés à des mesures, qui ont été obtenues à partir des expériences expérimentales sur Silicium.

OPERATION

Finalement la section 4 présente les conclusions de cette thèse.

Les références aux sections sont identifiées par le symbole « § ».