P Hagenmuller

M Pouchard

J C Grenier

NONSTOICffiOMETRY IN OXIDES: EXTENDED DEFECTS IN PEROVSKITE-RELATED PHASES*

Formation of point defects in oxides corresponds to balance between enthalpy provided for creating vacancies or inserting interstitial atoms into the lattice and the resulting entropy increase. In fact, pairing or clustering of the defects minimizes free energy and may lead, if they are numerous enough, to micro-and even macrophases. An excess of defects will give rise to a second phase. For perovskite or perovskite related oxides extended defects may lead to cation ordering, introduction of intennediate Na Cl-type slabs, or, if they involve oxygen vacancies, to new coordination polyhedra of the B-cations. Their various configurations depend on the electronic structure of B. Specific physical properties may result, e.g. superconducting behavior in some copper oxides.

A notion which is quite important for understanding the behavior of oxides is the concept of defect pairing. 2 If, f o r instance, Wvv is fonnally the interaction energy of two anion vacancies (wvv is negative when the defects attract each other) one may show that there is a critical temperature Tc= -Wvv/2k above which the vacancies are randomly distributed, but below which the y tend to order. If the def ects are sufficiently numerous and lwvvl large enough, for T < Tc two possibilities may occur:

(a) formation of a unique ordered phase; (b) separation into two distinct phases. The structural mechanism is actually f o rmation of local clusters (wvv involving several neighboring cations) which, if sufficiently large, will nucleate a novel "microphase" with less anions. A second phase will appear for a critical composition representing the maximum number of vacancies the structure is able to accommodate. Both phases may be related in fact by an intergrowth phenomenon if they have structural analogies.

When the vacancy clusters develop enough to give rise to a microphase with rearrangement of the remaining anions, formation of "extended defects" is observed. Appearance of shear planes (Wadsley defects) as in the Magneli W 0 03 0 .1 or W 0 03 0 . 2 oxides, or alignment of the point defects in fluorite-type vacancy oxides are classical examples.

As far as Ml decreases due to ordering of the defects into regular arrays and may largely compensate for decreasing configuration entropy, particularly at low temperature, a sequence of ordered phases will be often more stable than a single phase with wide compositional variations. To understand the defect association mechanism choice of appropriate formulations and annealing process will be useful as.well as electron diffraction and HREM characterization. Nonstoichiometry of oxides of cubic perovskite-type and related structures is of particular interest due to the diversity of the crystallographic features, but also to their impact on many different properties (e.g. magnetic, electronic, dielectric, optical, catalytic). 3

It is well known that cubic symmetry for an AB03 perovsk:ite corresponds to a so-called Goldschmidt tolerance factor equal to 1 or slightly smaller. If t decreases enough (smaller A or bigger B cation) cation displacements and tilting of corner sharing B06

--vvv

Ba 2 Ca 2 (Tl Cu 3 )0 9

Similarities of the framework structures of LaCa2Fe:30g, YBa2Cu307 and Ba2Ca2(11Cu3)09. In the latter phase distorted "TIO" layers appear between the tops of the square-based Cu-pyramids, analogous to the tetrahedra layers between the octahedra sheets in LaCa2Fe:30g. Besides corner sharing square planar Cu04 groups form intennediate copper-oxygen layers between the pyramid bases.

La2-xSrxCuO 4 and La2-xBaxCuO4 are superconducting for small values of x close to metal-insulator transition. Tc is in fact small (i.e. in the 20-40 K range) but these materials have a historical importance as they were the first discovered high Tc oxides, giving rise afterwards to many investigations.56-60 Possible superconducting behavior has been recently suggested for the homologous La2-xSrxNiO 4 series (x 0.2).9 1

• La2CuO4 is a non-superconducting insulator, but a small excess of oxygen introduced either by anodic oxidation in a basic aqueous solution or by application of high oxygen or fluorine pressures leads to metallic behavior at room temperature and to a superconducting transition close to 40 K. The extra oxygen atoms occupy new tetrahedral sites in the NaCl layers of the K2NiF4 structure, inducing an anionic rearrangement. The presence in the perovskite layers of elongated copper octahedra is consistent with formation of some Cu 3+ , but the short 0-0 distances resulting form the anion excess evidenced by neutron diffraction (1.64 A) do not exclude temporary occurrence of peroxide species. 9 3, 94 Ba2 YCu3O7_ 0 bas a superconducting behavior which depends on o, as far it is orthorhombic, with Tc often exceeding 90 K. The decreasing values of Tc (Fig. 15) at rising 8 may be related to cutting of the square chains resulting from oxygen departure. The plateau observed in the 0.2 < 8 < 0.4 range which is also reflected by magnetic and electric layer structures, as far as they will be determined in detail, the present disagreement being lifted, should allow to formulate the hypothesis that superconductivity results simultaneously from an equilibrium involving Cu + and Cu 3+ as well as Bi 3+ and Bis+ (or TI+ and TI 3+ ). Presence of Pb 2+ seems to enhance slightly the superconductivity of the thallium oxides.72 Rising number of copper-oxygen planes apparently increases also Tc but multiplication of the Cu-O layers makes more difficul_ t growing single crystals with homogeneous stacking and leads quickly to saturation of such possibilities. 69

G Ba

Layer structures proposed for some recent bismuth or thallium superconducting oxides. For most of these phases the oxygen positions are still controversial.

The occurrence of two disproportionation mechanisms in the bismuth and thallium cuprates, so far it would be confinned, could account for the larger resistivity dropping domain observed at decreasing temperature for the concerned oxides.

The crystal chemical developments in this area, where phonon electron interactions are essential, are delayed by the difficulty to obtain pure phases, stable temperature and with a crystal quality sufficient to allow precise structural detenninations, at least by TEM.

Despite complexity of the conduction mechanism the present copper • oxides are narrowly related to the defect perovskite-like oxides previously investigated. The type of defects differs indeed with the formulation, the prevailing factor being the electronic configuration of the B cation. The fact that the only 3d-element leading unambiguously to superconductivity is copper and that in the superconducting oxides substitution of copper by homologous cations leads quickly to vanishing of the phenomenon may be attributed to a relatively unique feature, most likely the mentioned activation energy-free disproportionation mechanism favored by the crystal structure. Such a coïncidence probably explains why so few superconducting oxide series have been found and why most of the layer type materials concerned have strong structural similarities. [START_REF] Pouchard | Proc. MRS Meeting, High Tc Oxide Symp[END_REF] The recent breakthrough in the field of superconducting copper oxides emphasizes in any case two general rules in solid state chemistry: the necessity never to renounce to prepare new materials and the importance not to separate new phenomena from their scientific background.

  FIG. 6 Idealized representation of the manganese-oxygen framework in CaMnQi.s. Other members of the series are Ca2LaFe3Og, Ca3Fe2TiOg (n=3) and C84,Fe2Ti2O11 (n=4) with layer sequences ootoot and oootooot, respectively (Fig. 7). Intergrowth phases have been reported. If they have a relevant composition and if the corresponding slabs are thin enough a regular succession of the previous motives may be detected by HREM. Ca5Fe4TiO13 and C84 YFe5O13 (n=2.5) contain for instance altematively n=2 (otot) and n=3 (ootoot) sheets. 3 0 Ca7Fe 6 TiO1 8 (n=2.33) should be characterized by an ototoot sequence, but many stacking faults actually appear due to the complexity of the expected packing (Fig. 8). Isolated point defects occur only in iron oxides for a very small number of oxygen defects. As their number increases they result in the formation of tetrahedra rather than bipyramids as already expected 10 years ago from conductivity vs. oxygen pressure measurements. 8 6 The tetrahedra align easily for a rising proportion of oxygen vacancies these files may form planes, which in turn tend to order. But when Fe 4+ is present, for example in CaxLa1-xFeO3 -Y. samples (0.25 � y < 0.5) prepared in air at 1400 °C, whereas x-ray diffraction seems to characterize a cubic perovskite-type structure (a� 3.85 A), electronic diffraction and HREM show actual formation of three dimensionally oriented intergrown microdomains of brownmillerite or Ca2LAFe3Og (grenierite) bulk compositions. The dimension of the

e

  FIG.17


Garret Sobczyk
email: garretudla@gmail.com

Calculus of Compatible Nilpotents

Keywords: AMS Subject Classification: 05C20, 15A66, 15A75 Clifford geometric algebra, Grassmann algebra, Lorentzian spacetime

come

Introduction

The concept of compatible null vectors reflects in many ways the standard definition of dual vector spaces in linear algebra, with one important difference. Whereas the usual concept of duality between vector spaces ties together the structure of these distinct vector spaces in a unique way, the concept of compatible null vectors ties together properties between two geometric algebras defined on the same vector space. The purpose of this work is to further explore the strange properties that reveal themselves when a canonical basis of null vectors is chosen instead of the standard basis of orthonormal vectors in a geometric algebra of a Minkowski space defined by a Lorentz metric [START_REF] Sobczyk | Talk: Geometric Algebras of Compatible Null Vectors[END_REF][START_REF] Sobczyk | Geometric Algebras of Compatible Null Vectors[END_REF].

Section 1, defines and characterizes the properties of the algebra of positive and negatively correlated nilpotents of the geometric algebras G 1,n and G n,1 . Whereas linear algebra has deep roots in the works of Grassmann, Hamilton, Clifford and Cayley, the importance of early works of Grassmann and Clifford have not been not been fully recognized until fairly recently [START_REF] Hestenes | The Design of Linear Algebra and Geometry[END_REF], [START_REF] Sobczyk | Conformal Mappings in Geometric Algebra[END_REF]. Whereas the invention of multiplication of matrices by Cayley permeates elementary linear algebra today, it is shown here that linear algebra could have developed from Grassmann algebra together with the quite different Multiplication Tables of compatible null vectors.

Section 2, develops the basic properties of the vector derivative or gradient operator, the basic tool of calculus that has been developed in the early works [START_REF] Hestenes | Clifford Algebra to Geometric Calculus: A Unified Language for Mathematics and Physics[END_REF], [START_REF] Sobczyk | New Foundations in Mathematics: The Geometric Concept of Number[END_REF], and other authors [START_REF] Lounesto | Clifford Algebras and Spinors[END_REF], and by the Clifford analysis community [START_REF] Delanghe | Clifford Algebra and Spinor-Valued Functions: Function Theory for the Dirac Operator[END_REF]. A more detailed history can be found in [START_REF] Lounesto | Clifford Algebras and Spinors[END_REF]. Whereas usually the vector derivative is employed in the geometric algebra of a Euclidean space, here its properties are developed in the geometric algebra of a Lorentz-Minkowski space. It is shown how a slight perturbation of the metric on Minkowski space leads to a Euclidean structure on the corresponding geometric algebra, perhaps offering a new mathematical formalism for quantum mechanics.

Section 3, sets down basic differential formulas for elementary functions of the position vector x, expressed in the basis of compatible null vectors. All of the formulas developed previously in the geometric algebra of Euclidean space, appropriately modified, can be used in the setting of the geometric algebra of the Lorentz-Minkowski space.

1 The geometric algebras G n,1 and G 1,n

• Nilpotents are algebraic quantities x = 0 with the property that x 2 = 0. They are added together using the same rules for the addition and multiplication by scalars F, as the real or complex numbers. The trivial nilpotent is denoted by 0.

• A set of nilpotents A n := {a 1 , . . . , a n } F is said to be multiplicatively uncorrelated over F, if for all a i , a j ∈ A n ,

a i a j + a j a i = 0. (1)
A set of uncorrelated nilpotents over a field F are called null vectors, and generate a Grassmann algebra G n (F), provided they are linearly independent over F, satisfying

a 1 ∧ • • • ∧ a n = 0, (2)
[9]. More general fields F can be considered as long as characteristic F = 2.

• A set A ± n+1 := {a 1 , . . . , a n+1 } of n + 1 null vectors is said to be positively or negatively correlated if

a i a j + a j a i = 2a i • a j = ±(1 -δ ij ), (3)
respectively. They generate the 2 n+1 -dimensional Clifford geometric algebras G 1,n and G n,1 , [START_REF] Clifford | Applications of Grassmann's extensive algebra[END_REF].

a i a j a j a i a i 0 a i a j 0 a i a j a j a i 0 a j 0 a i a j a i 0 a i a j 0 a j a i 0 a j 0 a j a i Table 2: NC Multiplication table. a i a j a i a j a j a i a i 0 a i a j 0 -a i a j a j a i 0 -a j 0 a i a j -a i 0 -a i a j 0 a j a i 0 -a j 0 -a j a i
Given below are the multiplication tables for sets of positively (PC), or negatively (NC), correlated null vectors a i , a j , for 1 ≤ i < j ≤ n + 1, [START_REF] Sobczyk | Geometric Algebras of Light Cone Projective Graph Geometries[END_REF]. For a set of positively or negatively correlated null vectors {a 1 , . . . , a n+1 }, define

A k := k i=1 a i .
The geometric algebra

G 1,n := R(e 1 , f 1 , . . . , f n ),
where {e 1 , f 1 , . . . f n } is the standard basis of anticommuting orthonormal vectors, with e 2 1 = 1 and [12, p.71]. Alternatively, the geometric algebra G 1,n can be defined by

f 2 1 = • • • = f 2 n = -1,
G 1,n := R(a 1 , . . . , a n+1 ) = A + n+1 ,
where {a 1 , . . . , a n+1 } is a set of positively correlated null vectors satisfying the multiplication Table 1. In this case, the standard basis vectors of G 1,n can be defined by

e 1 = a 1 + a 2 = A 2 , f 1 = a 1 -a 2 = A 1 -a 2 , and for 2 ≤ k ≤ n f k = α k A k -(k -1)a k+1 , (4)
where

α k := - √ 2 √ k(k-1)
.

The geometric algebra

G n,1 := R(f 1 , e 1 , . . . , e n ),
where {f 1 , e 1 , . . . e n } is the standard basis of anticommuting orthonormal vectors, with f 2 1 = -1 and e 2 1 = • • • = e 2 n = 1. Alternatively, the geometric algebra G n,1 can be defined by

G n,1 := R(a 1 , . . . , a n+1 ) = A - n+1 ,
where {a 1 , . . . , a n+1 } is a set of negatively correlated null vectors satisfying the multiplication Table 2. In this case, the standard basis vectors of G n,1 can be defined by

f 1 = a 1 + a 2 = A 2 , e 1 = a 1 -a 2 = A 1 -a 2 , and for 2 ≤ k ≤ n e k = α k A k -(k -1)a k+1 , (5)
where

α k := - √ 2 √ k(k-1)
.

It is well-known that Clifford's geometric algebras G p,q are algebraically isomorphic to matrix algebras over the real or complex numbers, [START_REF] Sobczyk | Matrix Gateway to Geometric Algebra, Spacetime and Spinors[END_REF]Ch.4]. For this reason, matrices over geometric algebra modules is well defined and fully compatible with the usual rules of matrix multiplication and addition.

Change of basis formulas for

G 1,n      a 1 a 2 • • a 8      = T 8      e 1 f 1 • • f 7      for T 8 =                1 2 1 2 0 0 0 0 0 0 1 2 -1 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 2 √ 3 2 0 0 0 0 1 0 1 2 1 2 √ 3 2 3 0 0 0 1 0 1 2 1 2 √ 3 1 2 √ 6 √ 5 2 √ 2 0 0 1 0 1 2 1 2 √ 3 1 2 √ 6 1 2 √ 10 3 5 0 1 0 1 2 1 2 √ 3 1 2 √ 6 1 2 √ 10 1 2 √ 15 √ 7 2 √ 3                , and
     e 1 f 1 • • f 7      = T -1 8      a 1 a 2 • • a 8      , for T -1 8 =                  1 1 0 0 0 0 0 0 1 -1 0 0 0 0 0 0 -1 -1 1 0 0 0 0 0 -1 √ 3 -1 √ 3 -1 √ 3 -2 √ 3 0 0 0 0 -1 √ 6 -1 √ 6 -1 √ 6 -1 √ 6 3 2 0 0 0 -1 √ 10 -1 √ 10 -1 √ 10 -1 √ 10 -1 √ 10 2 2 5 0 0 -1 √ 15 -1 √ 15 -1 √ 15 -1 √ 15 -1 √ 15 -1 √ 15 5 3 0 -1 √ 21 -1 √ 21 -1 √ 21 -1 √ 21 -1 √ 21 -1 √ 21 -1 √ 21 2 3 7                 
, [START_REF] Sobczyk | Geometric Algebras of Light Cone Projective Graph Geometries[END_REF].

We now turn our attention to the study of geometric calculus in the algebra of nilpotents A + n+1 ≡ G 1,n over the real numbers R.

Gradient operators in

A + n+1 = {a 1 , . . . , a n+1 }
Note, from here-on null vectors are not denoted in bold face. Let A + n+1 be a set of n + 1 linearly independent, positively correlated null vectors, satisfying (2) and ( 3). The positive compatibility property

a i a j + a j a i = 2a i • a j = (1 -δ ij ),
guarantees that a i are null vectors, with the inner product of distinct pairs equal to 1 2 , and in addition, they satisfy the multiplication Table 1. For simplicity, we only consider F := R the real number system.

Given any two distinct a i , a j ∈ A + n , let e := a i + a j and f := a i -a j . It easily follows that

e 2 = (a i + a j )(a i + a j ) = a 2 i + (a i a j + a j a i ) + a 2 j = 1, (6)
and

f 2 = (a i -a j )(a i -a j ) = a 2 i -(a i a j + a j a i ) + a 2 j = -1. (7)
Furthermore, the orthonormal vectors e and f are anticommutative,

ef = (a i + a j )(a i -a j ) = a j a i -a i a j = -(a i a j -a j a i ) = -f e. (8)
Once the seed null vectors a i and a j are chosen determining e and f , the other null vectors a k used to define the successive vectors f k 's can randomly be chosen using the recursive definition (4).

The fundamental gradient operator ∇ in G 1,n is defined by

∇ := e 1 ∂ s1 - n i=1 f i ∂ si+1 , (9)
for the position vector

x = s 1 e 1 + n i=1 s i+1 f i ∈ G 1 1,n , (10)
from which it follows that

∇x = n + 1 ⇐⇒ ∇ • x = n + 1, and ∇ ∧ x = 0.
Regardless of whether the gradient, or vector derivative, is defined in terms of the Euclidean metric in R n+1 of the geometric algebra G n+1 , or in terms of the Lorentz metric in R1,n of the geometric algebra G 1,n it is characterized by two fundamental properties:

ONE: The gradient ∇ has the properties of a vector

x ∈ G 1 p,q and ∇x = p + q (11)

the dimension of R p+q , independent of the metric in which it is calculated. TWO: The v-directional derivative is the scalar differential operator v • ∇, and applied to the vector

x ∈ G 1 p,q gives v • ∇x = v ∈ G 1 p,q , (12)
independent of the metric in which it is calculated. 1 Applied to the position vector x ∈ R n+1 of G n+1 or a position vector x ∈ R 1,n of G 1,n , the gradient of x counts the dimension of the space,

∇x = ∇ • x + ∇ ∧ x = n + 1 =⇒ ∇ ∧ x = 0, (13)
independent of the metric employed. Similarly, Given a vector

v ∈ G 1 n+1 or v ∈ G 1 1,n , respectively, v • ∇x = v, (14)
independent of the metric employed. It follows that all differentiation formulas worked out in any one metric apply equally to any other metric, [6, p.63-66] The gradient ∇ is closely related to two other vector derivatives which make their appearance in A + n+1 . The null gradient

∇ := n+1 i=1 a i ∂ i , (15)
where ∂ i := ∂ ∂xi , for the position vector

x = n+1 i=1 x i a i ∈ A + n+1 . (16)
It follows that ∇x = 0, or equivalently, ∇ • x = 0 = ∇ ∧ x. The additive dual sum gradient

∇ ∨ := n+1 i=1 ∨ a i ∂ i , (17)
where ∨ a i := A n+1 -a i for 1 ≤ i ≤ n + 1. For example,

∨ a 3 = A 3+1 -a 3 = a 1 + a 2 + a 4 .
In working in the calculus of the algebra A + n+1 , the partial differential sum operator,

∂ (n+1) := n+1 i=1 ∂ i = ∂ 1 + • • • + ∂ n+1 (18)
is of fundamental importance. Noting that for

v = v 1 a 1 + • • • + v n+1 a n+1 , v • A n+1 = n+1 i=1 v i a i • A n+1 = n+1 i=1 n 2 v i = n 2 ∨ v,
where we have introduced the dual-like notation

v ∨ := n+1 i=1 v i and v i ∨ := v 1 + • • • + v i-1 + v i+1 + • • • + v n+1 , (19)
for the vector

v = v 1 a 1 + • • • + v n+1 a n+1 ∈ A + n+1 . Whereas v is a vector, its dual v
∨ is a scalar, but both v i and its dual v i ∨ are scalars. Noting that

∂ (n+1) x = A n+1 , and A n+1 • ∇ = n 2 ∂ (n+1) , (20)
it follows that

A n+1 • ∇x = n 2 A n+1 and ∂ (n+1) x • A n+1 = (n + 1)n 2 .
Another calculation gives the basic result

∇ ∨ x = n + 1 2 := (n + 1)n 2 .

Basic decomposition formulas

The dual sum and null gradients satisfy the basic property

∇ ∨ + ∇ = A n+1 ∂ (n+1) , (21)
which easily follow from the definitions. In view of (21), we introduce the vector partial dual sum gradient

∇ (n+1) := A n+1 ∂ (n+1) , (22)
giving the fundamental relationship

∇ ∨ + ∇ = ∇ (n+1)
between the three vector derivative operators. Squaring this last equation gives

∇ ∨ + ∇ 2 = ∇ ∨ 2 + 2∇ ∨ • ∇ + ∇2 = ∇ 2 (n+1) = (n + 1)n 2 ∂ 2 (n+1) , (23)
where ∇2 = 1≤i<j≤n+1 ∂ i ∂ j , (24)
∇ ∨ 2 = n+1 i=1 a ∨ i ∂ i 2 = n(n -1) 2 n+1 i=1 ∂ 2 i + (n 2 -n + 1) n+1 i<j ∂ i ∂ j , (25)
and

∇ ∨ • ∇ = n 2 n+1 i=1 ∂ 2 i + (n -1) n+1 i<j ∂ i ∂ j . ( 26
)
In doing the above calculations for ( 23)-( 26), we have used the fundamental relationships

∂ 2 (n+1) = ∂ 1 + • • • + ∂ n+1 2 = n+1 i=1 ∂ 2 i + 2 n+1 i<j ∂ i ∂ j (27)
and

a ∨ i 2 = n(n -1) 2 , n+1 i<j a ∨ i • a ∨ j = n 2 -n + 1 2 . ( 28
)
The directional dual sum and directional null gradients are given by

v•∇ ∨ = n+1 i,j=1 v i a i •a j ∨ ∂ j = n+1 i,j=1 v i a i •A n+1 -v i a i •a j ∂ j = n 2 v ∨ ∂ (n+1) -v• ∇, ( 29
)
and

v• ∇ = n+1 i=1 1 2 v 1 ∨ ∂ 1 +• • •+ v n+1 ∨ ∂ n+1 = 1 2 v ∨ ∂ (n+1) -v 1 ∂ 1 +• • •+v n+1 ∂ n+1 , (30
) respectively. Applying ( 29) and (30) to the position vector x, gives

v • ∇x = 1 2 v ∨ A n+1 -v = ∇x • v, (31)
and v • ∇ ∨ x = n -1 2 v ∨ A n+1 + 1 2 v = ∇ ∨ x • v, ( 32
) since ∇ ∧ x = ∇ ∨ ∧ x = 0.
Taking the sum of these last two expressions, gives

v • ∇ (n+1) x = n 2 A n+1 - 1 2 v = ∇ (n+1) x • v, (33)
for the directional derivative of the dual sum gradient, since ∇ (n+1) ∧ x = 0. We are now in a position to state the fundamental relationship between the dual sum and null gradients to the gradient (9) in G 1,n ,

∇ = 2∇ ∨ - 2(n -1) n ∇ (n+1) = -2 ∇ + 2 n ∇ (n+1) = ∇ ∨ -∇ - n -2 n ∇ (n+1) . ( 34
)
Other relationships between the three gradients that easily follow are

∇ = - 1 2 ∇ + 1 n ∇ (n+1) , and
∇ ∨ = 1 2 ∇ + n -1 n ∇ (n+1) .
The Laplacian ∇ 2 can now be expressed in terms the scalar differential operator ∂ (n+1) and the dual-null Laplacian ∇2 , [12, p.121]. Using (34),

∇ 2 = 4 n 2 ∇ 2 (n+1) - 8 n A n+1 • ∇∂ (n+1) + 4 ∇2 = 2 n (n + 1)∂ 2 (n+1) -4 ∂ 2 (n+1) + 4 ∇2 = 4 ∇2 - 2(n -1) n ∂ 2 (n+1) . (35)
It follows that the Laplacian reduces to 4 times the null Laplacian for any function f (x) with the property that ∂ 2 (n+1) f (x) = 0. In addition, the Laplacian factors into the product of two first order differential operators:

∇ 2 = 2 ∇ + 2(n -1) n ∂ (n+1) 2 ∇ - 2(n -1) n ∂ (n+1) , (36)
opening the door to a new class of solutions to the Laplace equation in G 1,n , [START_REF] Sobczyk | Spheroidal Domains and Geometric Analysis in euclidean Space[END_REF][START_REF] Sobczyk | Spheroidal Quaternions and Symmetries[END_REF][START_REF] Boyer | Symmetry and Separation of Variables for the Helmholtz and Laplace Equations[END_REF].

For n = 2, ∇ 2 = 2 ∇ + ∂ (3) 2 ∇ -∂ (3) , (37)
and for n = 3, the case of Dirac algebra of spacetime, (36) reduces to

∇ 2 = 4 ∇ + 1 √ 3 ∂ (4) ∇ - 1 √ 3 ∂ (4) , (38)
giving a new factorization of the Laplacian in A + 4 .

The Euclidean geometric algebra G n+1

Using the dual-like notation introduced in ( 19), the geometric product of two vectors v, w ∈ A + n+1 takes the interesting form

vw = 1 2 n+1 i,j=1 v i w j (1 -δ ij ) + n+1 i<j (v i w j -v j w i )a i ∧ a j = 1 2 v ∨ w ∨ - n+1 i=1 v i w i + n+1 i<j (v i w j -v j w i )a i ∧ a j . (39)
It follows that

v • w = 1 2 (vw + wv) = 1 2 v ∨ w ∨ - n+1 i=1 v i w i = 1 2 n+1 i<j (v i w j + v j w i ), (40)
and

v ∧ w = 1 2 (vw -wv) = n+1 i<j (v i w j -v j w i )a i ∧ a j . (41)
Using (40) of G 1,n , a new Euclidean inner product v, w can be defined,

v, w := n+1 i=1 v i w i = v ∨ w ∨ -2v • w = v ∨ w ∨ - n+1 i<j (v i w j + v j w i ). ( 42
)
Using this -inner product the -geometric algebra G n+1,0 makes its appearance by defining the -geometric product of v, w ∈ G n+1 by

v w := v, w + v ∧ w = v ∨ w ∨ - n+1 i<j (v i w j + v j w i ) + n+1 (v i w j -v j w i )a i ∧ a j ,
or more simply,

v w := (v ∨ w ∨ -2v • w) + v ∧ w = (v ∨ w ∨ -3v • w) + vw, (43)
for which case the basis null vectors {a 1 , . . . a n+1 } ∈ G 1,n take on the roll of the orthonormal basis vectors of G n+1 .

It is interesting to note that the grading of the elements of these respective geometric algebras remains the same, i.e., a k-vector in G 1,n remains the same k-vector in G n+1 , but the algebras have completely different structures. Other interesting issues arise as well. Recalling the definition (1) of a null vector, as well as the random selection of the seed null vectors a i and a j in ( 6) and [START_REF] Lounesto | Clifford Algebras and Spinors[END_REF], new possibilities arise. In Hestenes' STA algebra G 1,3 , algebraically isomorphic to the Dirac algebra, each time-like unit vector e = γ 0 determines a unique rest frame or inertial system in Minkowski spacetime [START_REF] Hestenes | Space-Time Algebra[END_REF].

At the level of the even Pauli sub-algebra, choosing a γ 0 determines a unique splitting of the algebra into the relative components of a vector and a bivector of an observer [12, p.123], [START_REF] Baylis | Relativity in Clifford's Geometic Algebras of Space and Spacetime[END_REF][START_REF] Doran | Geometric algebra for Physicists[END_REF], [START_REF] Sobczyk | What's in a Pauli Matrix[END_REF][START_REF] Sobczyk | Spacetime Vector Analysis[END_REF]. On the other hand, the scalar inner product structure in (42) of such a splitting determines the star Euclidean geometric algebra G 4 , [START_REF] Sobczyk | Special relativity in complex vector algebra[END_REF][START_REF] Sobczyk | Spinors in Spacetime Algebra and Euclidean 4-Space[END_REF]. The intriguing question arises whether this might be the missing link to the interpretation of the wave-particle dual nature of matter in quantum mechanics, and in addition provide the key to unification of quantum mechanics with Einstein's general relativity? See Figure 1. Further speculation suggests interpreting the geometric algebra G 3,1 ≡ A - 3,1 as being related to antimatter, [START_REF] Santilli | Isodual Theory of Antimatter with Applications to Antigravity, Grand Unification and Cosmology[END_REF][START_REF] Roldao Da Rocha | Isotopic liftings of Clifford algebras and applications in elementary particle mass matrices[END_REF].

Figure 1: The bottom left side is the even sub-geometric algebra of the rest frame of an observer (particle side). The right side is the quantum mechanical Euclidean geometric algebra of that rest frame (wave side).

Differentiation of basic functions

In the previous section, basic relationships between the four fundamental differential operators, the gradient or vector derivative ∇, the null or hat gradient ∇, the dual sum gradient ∇ ∨ , and the scalar sum partial derivative ∂ (n+1) have been established. In order to efficiently proceed, differential formulas for elementary functions need to be developed.

We begin with a sample of formulas which have been developed elsewhere for the vector derivative ∇ in Euclidean space, [6, p.66]. In adapting the formulas in this reference, the dimension of the space R 1+n is taken to be n + 1, for the position vector

x = x 1 a 1 + • • • + x n+1 a n+1 ∈ A +
n+1 , and the unit vector

x := ∇|x| = x |x 2 | ⇐⇒ x = |x|x, (44)
where |x| := |x 2 |. The absolute value |x 2 | is necessary because only in the case of the positive definite Euclidean space is x 2 ≥ 0 for all x ∈ R n+1 . For simplicity, the formulas given here are only valid for more general spaces R p+q when x 2 ≥ 0, when x is a point in the positive light cone of the metric space.

∇|x| k = k|x| k-1 x, ∇|x| k x = (n + k + 1)|x| k . ( 45
) v • ∇|x| k = k|x| k-1 v • x, v • ∇|x| k x = k|x| k-1 v • x x + |x| k v. (46
The same sample of differential formulas is now given for the null, dual sum gradients, as well as scalar differential sum operator. For the null gradient ∇, with the help of (32) and (34), we first calculate ∇x 2 = x ∨ A n+1 -x. It follows that

∇|x 2 | = ∇x 2 = x ∨ A n+1 -x = 2|x| ∇|x| ⇐⇒ ∇|x| = x ∨ A n+1 -x 2|x| ( 49
)
whenever x is on the positive light cone for which case x 2 > 0. If we evaluate the right side of (49) at x = A n+1 + y 1 a 1 , for a constant y 1 ∈ R, we find that ∇|x| = (n + 1 + y 1 )A n+1 -A n+1 -y 1 a 1

2|A n+1 + y 1 a 1 | = (n + y 1 )A n+1 -y 1 a 1 2|A n+1 + y 1 a 1 | , (50)
which is quite different than the definition of the unit vector x found in (44). Using that (A n+1 + y 1 a 1 ) 2 = A 2 n+1 + 2y

) ∇ ln |x| = x |x| 2 ,

 2 ∇e x = e x + n sinh |x| |x| . (47) ∇vx = -(n -1)v, ∇(v ∧ w)x = (n -3)v ∧ w.

Table 1 :

 1 PC Multiplication table.

	a i	a j

  1 a 1 • A n+1 = )A n+1 -y 1 a 1 2|A n+1 + y 1 a 1 | = (n + y 1 )A n+1 -y 1 a 1

						1 2	n(n + 2y 1 + 1) ,
	it follows that (50) simplifies to
	∇|x| =	(n + y 1 √	2 n(n + 2y 1 + 1)	.	(51)
	It is also interesting to calculate
	( ∇|x|) 2 =	(n + y 1 ) n 2 + (1 + y 1 )n -y 1 4(n + 2y 1 + 1)	,	(52)
	which reduces to n 2 4 when y 1 = 0 and x = A n+1 . In this case
		∇|x|	x=An+1	=	√ √ 2 nA n+1 √ n + 1	.
	With (49) and (51) in hand, similar formulas like (45)-(48) easily follow for
	the other vector derivative operators.

The idea of the gradient ∇, or vector derivative, being a fundamental tool in the study of linear algebra was first developed in my doctoral thesis at Arizona State University(1971).I have published it on my website at https://www.garretstar.com/secciones/publications/publications.html

Acknowlegment

The Zbigniew Oziewicz Seminar on Fundamental Problemes in Physics, organized by Professors Jesus Cruz and William Page has played an important role in the development of this work in relation to Category Theory and the Theory of Graphs, [25,26].


Lilian Bossuet

Andres Carlos
email: carlos.lara@univ-st-etienne.fr

Lara-Nino

Carlos Andres

Advanced Covert-Channels in Modern SoCs

Keywords: Covert channels, Frequency modulation, Multi-cluster, SoC-FPGAs, Zynq ultrascale+

ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Introduction

A covert channel is, as the name suggest, an information pathway which is not evident to those unaware of the nature of the system. We might be familiar with a typical example found in classical media: morse code. In that case, the parties employ blinking patterns, quiet sounds, or discrete movements to transfer information stealthily. The channel being either the air or the light. In the context of circuits, the use of blinkers [START_REF] Guri | LED-it-GO: Leaking (A Lot of) Data from Air-Gapped Computers via the (Small) Hard Drive LED[END_REF] or noise [START_REF] Guri | Acoustic Data Exfiltration from Speakerless Air-Gapped Computers via Covert Hard-Drive Noise ('DiskFiltration')[END_REF] might be difficult to exploit. However, within a circuit there are other channels which can be used to the same end.

A typical system-on-a-chip (SoC) is an heterogeneous array of processing and memory elements. These components might be implemented within the same die or in different chips, but they generally share two kinds of wires: supply power and clocks. These lines are supposed to carry only DC components and square waves, respectively. But that does not mean that such signals cannot include additional information. As a practical example we might refer to smart grid applications [START_REF] Ma | Smart Grid Communication: Its Challenges and Opportunities[END_REF]. In the case of clock signals, a modulation of the frequency of the wave or the duty cycle of the period can be used to encode a message covertly. For DC components, small power fluctuations can be induced in the signal to create a pattern which would encode the message. These strategies can be leveraged by different elements of the SoC to create a covert channel and transfer information, even if they are not supposed to communicate with each other.

The sender of the message is potentially a spy process which somehow manages to retrieve critical information from its surroundings (i.e. details from applications running in the same processor, activation signals, and even memory contents under certain scenarios). The receiver is then another application or circuit which can take advantage of this information to perform some processing or a different kind of attack. The entity which the channel aims to be hidden from is usually the owner of the platform; who would restrict the interaction between suspicious applications and circuits. As to where the sender and receiver might come from, some prime suspects include: kernel modules, drivers, third-party accelerators, hardware trojans, libraries, and binaries. The overseer would be the designer of the architecture, in charge of putting everything together. As the complexity of circuits increases, these scenarios result much more feasible since the use of foreign components becomes a necessity for speeding-up the design process.

Previous works on covert channels on SoCs [BB18; GER19; Gna+21; Mie+18] have focused on earlier technologies for these platforms. However, the design of newer devices has shifted towards an heterogeneous approach. Given the slowdown in Moore's Law [START_REF] Eeckhout | Is Moore's Law Slowing Down? What's Next?[END_REF] it became evident that monolithic computing nucleus could no longer bear the burden of processing. Since then, we have seen the emergence of multi-core architectures. At the same time, as proposed by Amdahl's Law [START_REF] Hill | Amdahl's Law in the Multicore Era[END_REF], optimizing the performance of the platform becomes more complex as the number of processors in the cluster grows. For this reason, the latest generations of SoCs now feature multiple processing clusters of different capabilities. Modern SoCs feature low-power processors, application processors, hardware accelerators, and even reconfigurable nucleus, which make it possible to integrate a diverse group of operating systems and applications in the same chip.

The goal of this work is to explore different approaches for creating frequencybased covert channels in heterogeneous SoCs. We study the interaction between different processor clusters of these platforms leveraging the reconfigurable fabric as the shared resource for the implementation of covert channels. These interactions are achieved by modifying some of the divider values with the intent of producing a change in the clock network. This clock tree is used as the channel for the covert transmission of data. Our main contributions can be summarized as follows:

1. We propose, for the first time, the creation of covert channels between different processor clusters of the SoC 2. We evaluate the performance of these attacks using a clear and well understood methodology 3. We demonstrate, also for the first time, the feasibility of implementing frequency-based covert-channels in the Zynq Ultrascale+ family of devices

The rest of the paper is structured as follows. In Section 2 we describe our experiments and methodology to evaluate the different covert channels in the Zynq Ultrascale+ SoCs. In Section 3 we provide our conclusions and final remarks.

Threat model

In [START_REF] El | DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoC[END_REF], the authors used frequency modulation to create covert channels in the Zynq-7000 SoC. That work demonstrated that these architectures are vulnerable to these attacks even when the ARM TrustZone protections are enabled. In their case, a total of four covert channels were implemented, showing that the DVFS mechanisms available in SoCs could be used to bypass some ARM TrustZone protections. Other works, like [START_REF] Giechaskiel | Leakier Wires: Exploiting FPGA Long Wires for Covert-and Side-Channel Attacks[END_REF] have demonstrated that it is possible to employ the electromagnetic emanation within the chip to implement covert channels. The authors exploited the cross-talk between long-wires to implement covert channels with transmission rates up to 6 Kbps in different FPGAs. More formally, voltage-based covert channel attacks were reported by [START_REF] Dennis | Voltage-Based Covert Channels Using FP-GAs[END_REF], also for the Zynq-7000 SoCs. In that work, the authors managed to employ a power-waster circuit to generate fluctuations in the power supply of the circuit. Then, a sensor implemented in a different part of the reconfigurable fabric was used to retrieve the message. That work demonstrated that it was possible to implement power-based covert channels with transmission rates up to 8 Mbps.

The Zynq Ultrascale+ SoCs allow to use the RPU and the APU independently. The real time cores generally would run a real-time operating system like RTOS [START_REF] Iturbe | Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)[END_REF] or simply run standalone applications. The application cores, on the other hand, are complex and their full potential can usually only be achieved through the use of a kernel like Linux. Our work employs this model, which is based on reasonable assumptions about the use cases of the Ultrascale+ technology.

These systems also include a power management unit which is in charge of performing the monitoring and configuration of the Power Distribution Network. It includes anti-tampering characteristics which increase the difficulty of modulating the power supply of the chip directly. That is, we might be able to induce a power fluctuation, but there is a chance that the SoC will go into lock-down. On the other hand, modifying the frequency of different clocks used in the architecture can be achieved through simpler mechanisms. By design a modification of the system frequency will be accompanied with a corresponding voltage scaling. Thus, the proposed covert channels target the frequency of the SoC but also affect its voltage.

In Fig. 1 we illustrate part of the clock tree in the Zynq Ultrascale+ SoCs. Four main reference clocks are available to source the five main PLLs of the architecture. To generate the output of these oscillators, the reference sources are multiplied by a small constant. Subsequently, the output of the PLLs is divided by up to two six-bit constants to produce multiple clocks for different parts of the architecture. From the same figure, it can be seen how there are three main power domains in these chips. The Low Power Domain will source the RPU, the peripherals, the on-chip memory, and one of the interconnect switches. The Full Power Domain will supply the APU, the memory management unit, the memory controller, and the central interconnect switch. And the PL Power Domain will supply the reconfigurable fabric. For each the low and full power domains, the five main PLLs can be used to generate clocks after applying one or two divider values. And for the FPGA, only three of the PLLs can be used to generate the four clocks available to this component (which come from the processing system, as it is also possible to use external clocks). Hence, modifying most of the clocks in the platform is just a matter of editing the value of the main multipliers or any of the dividers.

Materials and Methods

Our work assumes that the spy process can gain access to phase locked loops (PLL) which can modify the oscillators in the SoC. We propose this assumption since the target scope of our work includes the Zynq Ultrascale+ SoCs which feature these components. Next, the receiver must be able to sample the channel to retrieve the message. This is achieved with the use of a sensor module which can be implemented in the reconfigurable fabric. We must note that our work does not investigate a concrete scenario for these attacks to take place, but rather we intend to demonstrate the vulnerabilities present in this technology in order to mitigate such threats.

This work uses the TE0802 SoC (xczu2cg-sbva484-1-e) as target system. Compared to other Ultrascale+ SoCs, this board offers a reduced set of features. However, it can be used to demonstrate a wide range of vulnerabilities in this family of devices. We employ the AMD-Xilinx 2021.1 toolchain to design and implement the hardware architecture, as well as to develop and deploy the applications. The library xtime l.h was used to obtain our time measurements.

Target platform

The Zynq Ultrascale+ SoC is an interesting case study for heterogeneous SoCs. These chips feature a main processing unit (APU), powered by an array of ARM Cortex-A53 cores. The secondary processing system (RPU) includes an array of ARM Cortex-R5F cores. Each one of these processors has independent instruction and data caches, and up to L2 cache in the case of the APU. The main memory of the SoC is an external DDR unit, driven by a silicon-based on-chip memory controller. There is also a smaller on-chip memory which can be shared by the different cores, and a memory management unit which performs the necessary assignments. What sets these architectures apart from other SoCs is the availability of an FPGA: an array of reconfigurable elements and silicon accelerators. The interconnection between processors and accelerators follows the AMBA-AXI specification through two main switches. The reconfigurable fabric of the SoC offers the possibility of implementing a wide range of customized accelerators.

In Fig. 1, in blue, we illustrate part of the clock tree in the Zynq Ultrascale+ SoC-FPGAs. A main reference clock (PSS REF CLK) is used to source the five main PLLs of the architecture (RPLL, IOPLL, APLL, VPLL, DPLL). To generate the PLL output, the reference clocks are multiplied by a constant. The resulting oscillators are then divided by one or two six-bit constants to produce specific clock domains for the different parts of the architecture.

From Fig. 1 it can also be seen how there are three main power domains in these Ultrascale+ SoCs. The Low Power Domain will source the RPU, the peripherals, the on-chip memory, and one of the interconnect switches. The Full Power Domain will supply the APU, the memory management unit, the memory controller, and the central interconnect switch. The PL Power Domain will supply the reconfigurable fabric. The goal for this separation of power domains is to improve the energy footprint of the system by allowing to shut down complete areas of the SoC when these are not required.

For the low and full power domains, the five main PLLs can be used to generate clocks. For the FPGA, only three of the PLLs (RPLL, IOPLL, DPLL) can be used to generate the four clocks available to the fabric (from the processing system, since it is also possible to use external clocks.)

Ultrascale+ SoCs allow to use the RPU and the APU independently. The cores in the RPU would normally run a real-time operating system like RTOS [START_REF] Iturbe | Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)[END_REF] or simply run standalone applications. The cores in the APU, on the other hand, are more complex and their full potential can best be drawn through the use of a kernel like Linux. In this work, we presume that both clusters can be operated independently. We implement bare metal applications in the RPU and linux-based applications in the APU. These chips also feature a power management unit which is in charge of performing the monitoring and configuration of the power distribution network. It features anti-tampering characteristics which increase the difficulty of modulating the power supply of the chip.

Covert transmission of data

The proposed covert channels exploit the potential of the RPU and the APU for modifying the oscillators that source the FPGA. The frequency of the different clocks in Ultrascale+ SoCs can be modified by editing its multiplier or divider values. The multiplier register will affect the PLL output, and in turn modify the frequency of all the SoC components which rely on that given oscillator. In contrast, the divider registers are specific for a given clock and modifying them will only modify the frequency of a particular clock signal. There are clocks which use one divider and there are clocks which use two. All the dividers are stored as a six-bit section of a 32-bit register. To modify the frequency of an oscillators it is then necessary to edit the contents of these control registers.

At low level, like in bare-metal applications, the control registers of the SoC can be edited through direct access operations. For example using the xil io library. However, to edit one of these control registers it is necessary to edit multiple security and configuration registers so that the frequency change is enacted. Furthermore, the application performing the operation must have the appropriate exception level.

In the presence of a kernel this task can be simplified with the help of drivers which allow to request the modification of specific clocks. For example, the processor clocks (by using the cpufreq driver of Linux) or the FPGA clocks (by using the fclk drivers of Xilinx). This scenario is more favorable for attackers since the complexity of the kernel allows to hide malicious applications more easily.

The SoC platforms utilized are by default protected with the ARM Trust-Zone firmware. The fabric is protected by an extension of this technology which allows to declare an IP as trusted. However, neither of these protections prevent the use of the clock drivers (cpufreq, fclk) so long as the application has root access.

Internal sensors

A delay sensor is a circuit created with digital components which can measure the variation in the propagation delay of a digital signal. These fluctuations are generated from variations in the power dissipation, electromagnetic coupling, and thermal fluctuations of the circuit [START_REF] Zick | Low-Cost Sensing with Ring Oscillator Arrays for Healthier Reconfigurable Systems[END_REF]. For this reason, such sensors have been employed to perform internal monitoring of the chip [ZS18; Gra+20]. The main types of such sensors are based in TDCs and ROs. The former are generally more accurate and provide greater resolution in the sampling, but must be calibrated precisely and placed directly in the platform. In contrast, the RO-based sensors (RO-S) do not require any fine-grained implementation directives and provide sufficient information when enough samples are available. Our work focuses on the latter.

The main components of a RO-S are shown in Fig. 2. In this case, the ring of inverters provides a consistent oscillatory wave whose period fluctuates according to the nominal operation of the circuit. This signal is then used to source a binary counter which is subsequently sampled by an external clock to produce a measurement. The number of counts retrieved in a sampling period is thus correlated to the frequency of the ring, and in turn to the operation of the circuit. In a conventional binary counter we must consider the problem of carry propagation, which can drastically affect the critical path of the design. This problem, together with the need to reset the counter after each measurement, causes that the use of conventional counter designs derives into sensors with very low sampling rates. Both of these limitations were addressed by [START_REF] Gravellier | High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs[END_REF], who proposed to employ a carry-less ring counter which produces a Johnson encoding. This updated design is used in our work. However, we are more interested in the sampling clock of the sensor. By modifying this signal we can obtain an offset in the measurements due to the periodicity of the ring-counter.

As main sensing module we use the RO-S from [START_REF] Gravellier | High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs[END_REF]. This design features an acquisition rate over 350 Msps thanks to the highly optimized counter. The output of the sensors can be quantified with just ten bits, using the average of multiple sensors to mitigate the quantization error. The output of this module can be read directly from the FPGA, or retrieved from either the RPU or the APU through an AXI channel.

Physical characteristics of the channel

To understand the limits of the proposed covert channels we first characterized the behavior of a PLL in the target platform. Using a digital oscilloscope we sampled the time-response of these components when requesting a change in the output frequency. As reference, we generated a digital trigger through the processor's GPIOs. We then measured the width of these pulses. We also captured the activation of the MSB bit in the output of the RO-S (See Fig. 2). In Fig. 3 we illustrate our observations for this experiment.

Our findings suggest that the minimum response time for a frequency change is approximately 600ns. That is the time elapsed from the moment one of the RPU cores modifies the register until the output of the sensor is updated (t R5F toF P GA ). Therefore, assuming that we could transfer one bit per transition, the maximum bandwidth for the proposed channels would be 1.6 Mbps. Note that this is the theoretical limit, without considering the necessary delay to achieve a consistent transmission (low-error rate).

We observed that the response time to transition from a lower to a greater frequency differs from the time required to perform the opposite change. However, explaining this behavior falls out of the scope of our work; we simply take the maximum of both measurements to determine the minimal maximumbandwidth. As we will demonstrate latter in the paper, this asymmetry does not weight on the feasibility of the proposed attacks.

Next, we intended to characterize the RO-S which would be used in our experiments. For this, we implemented a matrix of 64 RO-S and sampled it using different frequencies. Results for this experiment are provided in Fig. 4. At first glance it was possible to clearly differentiate between the multiple sample Figure 2: The architecture of the RO-S used in our work. This module is composed of three main groups of components. A group of sensors that produce a digital output in function of the operation of the circuit. An encoder for each sensor, which quantify the output of the counters. And an adder, whom merges all the encoders' outputs to mitigate the quantization error. There are also three main elements within each sensor: a ring oscillator (in yellow), a Johnson ring-counter (in red), and a register (in cyan). The acquisition rate is defined with an external sampling clock.

Q D FDCE O I0 LUT6 Q D FDCE Q D FDCE Q D FDCE Q D FDCE Q D FDCE Q D FDCE Q D FDCE O I0 I1
windows. However, for some cases, this separation would not be so apparent for a computer. The problem being that multiple sample values would overlap for different sampling frequencies. The outliers can be appreciated in the box diagrams included in Fig. 4. This kind of analysis was useful to identify the most adequate frequencies for implementing the proposed attacks. We selected frequencies that would simplify the implementation of the covert channels without requiring any filtering (100 MHz, 150 MHz, 300 MHz).

Covert channels between the RPU and the FPGA

The first class of covert channels we studied were those where an application running in the RPU (Cortex-R5F@533 MHz) acted as the transmitter, and a circuit implemented in the FPGA was the receiver. This scenario is illustrated in Fig. 5. Such attacks might be found in systems which use third party applications or accelerators. To perform the frequency modulation, the RPUbased application simply needed to access the CRL APB module and overwrite In our experimentation, these tasks were performed using the xil io.h library. Under this attack model, the bandwidth will be limited by the delay for the application to modify the target oscillator (t ′ R5F toF P GA ). This delay is composed of the time required for a Cortex-R5F processor to modify a CRL APB register (t R5F ), plus the transition delay of the PLL (t P LL ), and the time for the RO-S to update its output (t RO-S ). This model is given in Equation 1.

t ′ R5F toF P GA = t R5F + t P LL + t RO-S (1)
We went even further and decided to retrieve the output of the sensor from the processing system. This experiment sought to minimize t ′ R5F toF P GA while maintaining an error rate of zero over the transmission of 12KB of data. For this, we used the modulation strategy in Alg. 1. This approach relies on three different frequencies: two that will represent ones and zeros and a third one that will act as a separator. By using three symbols it is possible to minimize the number of samples per window, as long as the different windows remain clearly differentiable. The results for this experiment are illustrated in Figure 6.

The samples shown in Fig. 6 were retrieved from the RPU by reading the output of the RO-S through an AXI link. Experimentally, we determined that t ′ R5F toF P GA ≈ 1.83 µs. Whereas the FPGA could sample the output of the sensors with a rate of 333 MSps (t F P GAtoF P GA = 3 ns), the RPU could only read the same output with an additional delay (t F P GAtoR5F ). Our experiments found that t F P GAtoR5F = 498 ns. It follows that t R5F toR5F = t ′ R5F toF P GA + t F P GAtoR5F = 2.33 µs. This is the latency for a Cortex-R5F core to communicate with the other Cortex-R5F through a covert channel which uses the FPGA as shared resource. The corresponding bandwidths are calculated in Equation 2.

B R5F toF P GA = 1 2t ′ R5F toF P GA = 1 3.66 µs ≈ 273 Kbps B F P GAtoR5F = 1 2t F P GAtoR5F = 1 995 ns ≈ 1 M bps B R5F toR5F = 1 2(t ′ R5F toF P GA + t F P GAtoR5F ) ≈ 215 Kbps (2) APU A53 0 A53 1 RPU R5 0 R5 1 DDR4 DDRC L2

Covert channels between the APU and the FPGA

The second type of covert channels under evaluation were those that originated from an application executed in the APU (Xilinx' Linux on Cortex-A53@1.3GHz). As in the previous attack, our intended receiver was the RO-S in the FPGA. This scenario is depicted in Fig. 7.

A regular Linux kernel, if configured properly, will feature the cpufreq driver which allows to modify the frequency of the underlying system. This might be leveraged to implement a covert channel between different cores controlled by the same operating system. In the case of the Xilinx' distribution of Linux, the kernel also features a set of APIs (/sys/devices) which allow to modify the frequency of the FPGA clocks. These two mechanisms use configuration files which can be managed from the application space. Thus, performing the modification of some oscillator is a matter of locating the adequate file, opening it, modifying its contents, and closing it again (the file must be closed for the change to be detected). Evidently, this is much more time intensive than writing a register. Therefore, for these attacks the bandwidth of the covert channel will be limited by the delay for the application (operating system) to modify the Algorithm 1 A frequency-modulation strategy for low-width windows Require: f 1 , f 2 , f 3 : A given set of frequencies.

for byte in message do for bit in byte do if bit then oscillator (t OStoF P GA ). This model is given in Equation 3.

fclk ← f 1 else fclk ← f 2 end if fclk ← f 3 end for end for APU A53 0 A53 1 RPU R5 0 R5 1 DDR4 DDRC L2 Cache SCU I/D
t OStoF P GA = t OS + t P LL + t RO-S (3)
In this case, since we expected t OStoF P GA to be much greater than t R5F toF P GA we used the frequency modulation strategy in Alg. 2. Unlike the previous model, when there is a large number of samples it is possible to differentiate a transmitted zero from a one by adding a small delay (δ) in the transmission. If a divider value with minimum delay (t bit ) is used to separate the windows, then only two frequency values are required. The advantage of the new modulation strategy is that only three windows are used to encode two bits, rather than four. This results critical when the windows contain many samples. The results for an experiment with this type of channels are presented in Fig. 8.

For this experiment we saw it necessary to add a delay in the acquisition (ζ = 10 µs) to reduce the number of samples collected. The data was retrieved using the RPU with a sampling period t ′ F P GAtoR5F = t F P GAtoR5F + ζ (it was experimentally corroborated that t ′ F P GAtoR5F = 11.05 µs). We observed that t bit = 33 × t ′ F P GAtoR5F = 365 µs and t bit + δ = 39 × t ′ F P GAtoR5F = 431 µs, so Algorithm 2 A frequency-modulation strategy for large sample-windows Require: f 1 , f 2 : A given set of frequencies.

for byte in message do for bit in byte do if bit then fclk ← f 1 wait(δ) else fclk ← f 1 end if fclk ← f 2 end for end for δ ≈ 66 µs (in practice δ was implemented as usleep(1)) and t OStoR5F = t bit . It follows that t OStoF P GA = t bit -t F P GAtoR5F ≈ 354 µs. As suspected, the transmission delay for this covert channel was about 200 times greater than the delay between the RPU and the PL (t R5F toF P GA ). The corresponding bandwidths are given in Equation 4.

B OStoR5F = 1 2t bit + 0.5δ = 1 795.94 µs ≈ 1.31 Kbps B OStoF P GA = 1 2t bit + 0.5δ -t F P GAtoR5F ≈ 1.33 Kbps (4)
As it can be observed, the bandwidth for these covert channels is much lower than in the previous cases. However, modifying the clock frequency from the kernel space has two evident advantages: arguably it would easier to introduce malicious applications in a piece of software as large as Linux and the attacker does not need any specific knowledge of the architecture under attack. Which increases the range of potential targets.

Covert channels between the APU and the RPU

The experiments in the previous Subsection assumed that the transmitter in the Linux-enabled Cortex-A53 would use the /sys/devices APIs to perform the frequency modulation of the FPGA clocks. However, this is not necessary if the application has access to the physical registers. To achieve this goal we can map the kernel memory through the devmem utility, then a register value can be read and written as any pointer from a C-language application.

Revisiting the case where a transmitter in the Cortex-A53 intends to send data covertly to an application in the Cortex-R5F (illustrated in Fig. 9), we now expected the number of samples per window to be much lower. Thus we continued to use the encoding from Alg. 1. Again, the APU transmitter would perform the frequency modulation but now through direct access to the PLL dividers. Then the RO-S in the FPGA would detect the frequency change, and its output would be read from the RPU. The total delay for the revisited covert channel from the APU to the RPU is modeled in Equation 5.

t A53toR5F = t A53 + t P LL + t RO-S + t F P GAtoR5F
(5)

Experimentally, we determined that it was possible to achieve a zero-error transmission over 30 KB of data with a small delay (η). In this case, the sender required to wait η after editing the register value. On the other hand, the receiver could continuously read the RO-S output.

It results difficult to accurately measure t A53toF P GA from the kernel space, however, using the data in Fig. 10a we can estimate that t A53toR5F ≈ 3 × t F P GAtoR5F . With a conservative guess, we can then calculate the bandwidth for this cover channel as provided in Equation 6.

B A53toR5F = 1 6t F P GAtoR5F = 1 2.99 µs ≈ 335 Kbps (6)
This experiment contributed to demonstrate that both the Cortex-R5F and the Cortex-A53 cores can read and edit the registers in the CRL APB module. Which means that we could simply create a register-to-register channel without the need to wait for the activation of the PLL. The results for this experiment are shown in Fig. 10b. With this approach the accuracy in the transmission increases considerably, to the point it is possible to use more complex modulation strategies, for example to increase the difficulty of detection, like the one in Alg.

3.

Formally, the difference in the register-register covert channel is that the Cortex-R5F application didn't have to retrieve the data from the FPGA (a difference of ∼ 90 ns). This is reflected in the delay model of Equation 7. Nonetheless, it remained difficult to estimate t A53 accurately.

t ′ A53toR5F = t A53 + t P LL + t RO-S + t R5F (7)
Then, from Fig. 10b, since the sampling period can be considered equivalent to t R5F and there are approximately five samples per bit transmitted, t ′ A53toR5F ≈ 5 × t R5F . The updated bandwidth is given in Equation 8.

B ′ A53toR5F = 1 5t R5F = 1 2.04 µs ≈ 490 Kbps (8)
Finally, we revisited the case where the transmitter would be the application in the Cortex-R5F and the receiver would be an application in a Linux-enabled Cortex-A53. In this case both applications could operate without any additional delay. We could measure the transmission delay for the channel, and by using the average number of samples per window estimate the delay for the Cortex-A53 to access a register in the CRL APB module. Figure 11 illustrates some results for this experiment. From this evaluation we estimated that t A53 = 243 ns, and by consequence B ′ R5F toA53 ≈ 750 Kbps. The limiting factor being t R5F .

Algorithm 3 A more complex frequency-modulation strategy Require: f 1 , f 2 , f 3 : A given set of frequencies.

for byte in message do for bit in byte do if bit then

fclk ← f 1 fclk ← f 2 wait(δ) else fclk ← f 2 fclk ← f 1 end if fclk ← f 3 end for end for

Summary

In this Section we have described multiple covert channels which can be implemented between different clusters of the SoC and the reconfigurable fabric.

For each experiment we have sought to maintain zero transmission errors and to estimate the minimum delay. While the performance results vary considerable between some of the attacks, it is necessary to remember that they have different use cases and advantages. In Table 1 we summarize our findings. We have also retrieved results for selected works in the literature, which have implemented covert channels in SoCs and FPGAs. A direct comparison should be avoided since the implementation technologies differ. It is important to note that the qualitative characteristics of the channel should outweigh quantitative criteria such as the bandwidth.

In [START_REF] El | DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoC[END_REF], the authors used frequency modulation to create covert channels in the Zynq-7000 SoC. That work demonstrated that these architectures are vulnerable to these attacks even when the ARM TrustZone protections are enabled. In their case, a total of four covert channels were implemented, showing that [START_REF] Dennis | Voltage-Based Covert Channels Using FP-GAs[END_REF], also for the Zynq-7000 SoCs. In that work, the authors managed to employ a power-waster circuit to generate fluctuations in the power supply of the circuit. Then, a sensor implemented in a different part of the reconfigurable fabric was used to retrieve the message. That work demonstrated that it was possible to implement power-based covert channels with transmission rates up to 8 Mbps.

Final remarks

In this work, we have explored different alternatives for implementing covert channels in heterogeneous SoCs. Through experimentation we have demonstrated that it is possible to create covert channels between different components of these platforms. Using the Zynq Ultrascale+ SoCs as case study, we managed to create covert channels which achieved different transmission rates, going from a few Kbps to 750 Kbps. At the same time, we modeled the transmission delays and transmission bandwidth of the different covert channels adjusting the data with our empirical observations. These findings can be used to design more effective countermeasures for potential attacks based on covert channels.

As an additional contribution we characterized the response times of the PLLs in the Zynq Ultrascale+ SoCs. We demonstrated how these circuits have an asymmetric behavior as a function of the requested transition. For an ascending change from 100 MHz to 150 MHz we observed a transition delay of 600ns; the equivalent descending change showed a slightly shorter transition delay.

We can conclude that, from an efficiency point of view, writing and reading the registers directly is the best option to implement covert channel communications. However, this assumes that the attacker has a) the necessary access level to read/write the control registers of the SoC and b) precise knowledge of the architecture under attack. These assumptions limit the application of these kind of covert channels. On the other hand, performing frequency modulation from the kernel space is not so efficient, but it allows to mitigate these limitations. For the point a), it is much easier to sneak a malicious application into a large component like an operating system, and for the point b), the kernel will make sure that the drivers and APIs are pointing to the appropriate control registers regardless of the platform.

When comparing our results against the state of the art it is possible to reach mixed conclusions. However, we note that it is difficult to come up with a fair metric for comparison. First, because the implementation technologies and underlying phenomena are fundamentally different. And second, because the main goal of a covert channel is not to transfer a lot of data, but to do it stealthily. Finally, our work is not incremental to the related research; they are complementary. The vulnerabilities identified in this paper are architectural in nature, thus it would be possible to combine our work with other circuit-level principles for covert transmissions.

As future work, we intend to explore the impact of the modulation of the sampling frequency in the fine-output of the RO-S, which was not used in this work. We also intend to explore the possibility of creating the same covert channels when more restrictive control policies are implemented in the SoC, for example under trusted execution environments and power management software. Lastly, it might also be interesting to evaluate the application of the proposed covert channels under different SoCs which might not necessarily include an FPGA. This could be achieved through the use of hardware components which can be used to implement delay sensors [START_REF] Gravellier | SideLine: How Delay-Lines (May) Leak Secrets from Your SoC[END_REF].

Figure 1 :

 1 Figure 1: The clock tree and power domains of a Zynq Ultrascale+ SoC

  Transition from 100 to 150 MHz

Figure 3 :

 3 Figure 3: The time-response of a PLL in the Zynq Ultrascale+

Figure 4 :

 4 Figure 4: Characterizing the output of the RO-S as a function of the sampling frequency. The selected frequencies range from 375 MHz (which is the result of dividing the output of the IOPLL at 1.5 GHz by four) to 75 MHz (the result of dividing the same oscillator by 20). Each observation consists of 40,000 samples.

Figure 5 :Figure 6 :

 56 Figure 5: The information flow through a covert channel between the RPU (Sender) and the FPGA (Receiver)

Figure 7 :

 7 Figure 7: The information flow through a covert channel between the APU (Sender) and the FPGA (Receiver)

Figure 8 :

 8 Figure 8: The transmission of a stream of bits over a covert channel from the Linux kernel to the FPGA. In this channel the modulation is performed according to Alg. 2, with f 1 = 150 MHz, f 2 = 300 MHz and δ ≈ 66µs.

Figure 9 :

 9 Figure 9: The information flow through a covert channel between the APU (Sender) and the RPU (Receiver) using the FPGA in the middle

  Figure 10: The transmission of a stream of bits over a covert channel from the APU (Cortex-A53) to the RPU (Cortex-R5F). In this case the modulation is performed according to Alg. 1, with f 1 = 100 MHz, f 2 = 300 MHz and f 3 = 150 MHz.

Figure 11 :

 11 Figure 11: The transmission of a stream of bits over a covert channel from the Cortex-R5F to the Cortex-A53 using the registers of the CRL APB module as the shared resource. As in the previous experiment, we do not sample the output of the RO-S but the value of a register. For this channel the modulation is also performed according to Alg. 1, with f 1 = 100 MHz, f 2 = 300 MHz and f 3 = 150 MHz.

Table 1 :

 1 Summary of the proposed covert channelsthe DVFS mechanisms available in SoCs could be used to bypass some ARM TrustZone protections. Other works, like[START_REF] Giechaskiel | Leakier Wires: Exploiting FPGA Long Wires for Covert-and Side-Channel Attacks[END_REF] have demonstrated that it is possible to employ the electromagnetic emanation within the chip to implement covert channels. The authors exploited the cross-talk between long-wires to implement covert channels with transmission rates up to 6 Kbps in different FPGAs. More formally, voltage-based covert channel attacks were reported by

	Ref. Sender	Receiver	Shared resource Bandwidth (Kbps)
	[BB18] Cortex-A9	Spectrum analyzer PDN	333
	[BB18] Cortex-A9	Cortex-A9	PLL	60
	[BB18] Cortex-A9	FPGA	PLL	125,000
	[BB18] FPGA	Cortex-A9	PLL	-
	[GER19] FPGA	FPGA	Long wires	6
	[Gna+21] FPGA	FPGA	PDN	8,000
	This work Cortex-R5F	FPGA	PLL	273
	This work Cortex-R5F	Cortex-R5F	FPGA	215
	This work Cortex-A53 (API) FPGA	PLL	1.33
	This work Cortex-A53 (API) Cortex-R5F	FPGA	1.31
	This work Cortex-A53	Cortex-R5F	FPGA	335
	This work Cortex-A53	Cortex-R5F	Register	490
	This work Cortex-R5F	Cortex-A53	Register	750

Acknowledgments

The authors acknowledge the support of the French Agence Nationale de la Recherche (ANR), under grant ANR-19-CE39-0008 (project ARCHI-SEC).