Da Mathieu
email: mathieu.da-silva@lirmm.fr

Marie-Lise Silva

Giorgio Di Flottes
email: flottes@lirmm.fr

Bruno Natale
email: dinatale@lirmm.fr

Rouzeyre
email: rouzeyre@lirmm.fr

Experimentations on Scan Chain Encryption with PRESENT

Keywords: Test and Security, Scan Attacks Countermeasure, Light Encryption I

Crypto-processors are vulnerable to scan attacks. Using the scan chain, an attacker is indeed able to observe intermediate encryption states and steal secret data closelyrelated to the key. However, scan design is the most powerful mean for test and diagnostic purpose. Several countermeasure approaches have thus been proposed for securing scan designs while preserving test efficiency, diagnosis and debugging abilities. One solution is to encrypt test patterns thanks to extra block ciphers preventing control and observation of plain texts in the scan chain. The goal of this paper is to experiment this scan chain encryption approach on different designs in order to evaluate test efficiency and costs in terms of area and test time.

INTRODUCTION

Manufacturing testing allows distinguishing between fault-free and faulty circuits prior to shipping and ensures a high level of quality. Design-for-Testability (DfT) is a design approach aimed at improving circuit testability. The most popular DfT solution dedicated to logic circuits is the scan design. Scan design provides full control/observation of internal states at test time and thus reduces test pattern generation complexity, provides high fault coverage, simplifies fault diagnostic and support debug facilities. Scan design consists in replacing original registers by scan registers, i.e shift registers controlled/observed from/through primary IOs. However, an attacker can use observability and controllability offered by the scan registers to leak secret on the circuit, especially on crypto-processors [START_REF] Yang | Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard[END_REF] [START_REF] Da Rolt | Scan Attacks and Countermeasures in Presence of Scan Response Compactors[END_REF]. Therefore, full control and observation have to be avoided to preserve data confidentiality.

Several countermeasures have been proposed to prevent these scan attacks [START_REF] Yang | Secure Scan: A Design-for-Test Architecture for Crypto Chips[END_REF][4] [START_REF] Da Rolt | Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison[END_REF][6] [START_REF] Chiu | A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores[END_REF][8] [START_REF] Silva | Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits[END_REF] [START_REF] Dworak | Don't forget to lock your SIB: hiding instruments using P1687[END_REF]. The most common industrial practice consists in disconnecting test accesses after manufacturing test by using fuses. This lowcost solution does not impact manufacturing test activities but raises significant maintenance issues in the field. Indeed, even if probing techniques can be used for controlling and observing disconnected test signals, they also offer new perspectives for attackers.

A countermeasure that would prevent the use of fuses is proposed in [START_REF] Yang | Secure Scan: A Design-for-Test Architecture for Crypto Chips[END_REF]. It consists in resetting scan registers when the circuit switches from mission mode to test mode. Secret data stored on the round register of a crypto-processor for instance becomes unusable for an attacker. However, some scan attacks [START_REF] Subidh | New scan-based attack using only the test mode[END_REF] rely only on the test mode, thereby sidestepping the reset countermeasure.

Further countermeasures rely on non-classical design flows. Technique presented in [START_REF] Hely | Scan design and secure chip[END_REF] consists in setting the scan flip-flops (FFs) order only in test mode. In mission mode, the scan FF order is dynamically and randomly set, preventing possible analysis of data scanned out. Test time and test generation effort are not affected by scan chain re-ordering, unfortunately, area overhead and power consumption increase in mission mode (+7%) is an issue. Another technique to limit attack through scan chain observation is the use of a secure embedded comparator as proposed in [START_REF] Da Rolt | Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison[END_REF]. Instead of the scan chain content, the circuit only outputs the comparison result between the test responses stored in the scan chain and the expected ones. Test time and test coverage are not impacted but diagnostic complexity increases. Therefore, debug with secure comparator cannot be done easily. Another solution is the use of a different DfT approach, the Built-In Self-Test (BIST) [START_REF] Doulcier | AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis[END_REF]. It limits external scan chain control and observation but compromises diagnostic since the test procedure returns a compressed procedure.

Others solutions consist in using secure test wrappers [START_REF] Chiu | A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores[END_REF]. Only trusted user can access to test facilities thanks to a locking mechanism that stops the attacker if she/he cannot provide the test key. Secure protocols require managing test keys. To protect the test wrapper, the authors in [START_REF] Rosenfeld | Attacks and Defenses for JTAG[END_REF] propose to encrypt the content of the JTAG communication using stream cipher. To guarantee a high security, a hash function and a message authentication code are needed, affecting area cost.

The countermeasure described in [START_REF] Silva | Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits[END_REF] consists in using light block ciphers for scan encryption. Assuming a cryptoprocessor embedded with key management and storing, the same key storage present in the circuit under test is used to store the scan chain encryption key. No additional key management policy is needed, compared to a solution such as [START_REF] Dworak | Don't forget to lock your SIB: hiding instruments using P1687[END_REF] where the solution implies to manage the key that is shifted in the scan chain for tester authentication. With scan chain encryption, trusted users have full control and observation for test and debug facilities, while an attacker cannot control the data scanned in the scan chain, nor observe circuit internal states because of the encryption. This solution does not cause any constraint on debugging, it is ensured without authentication protocol compared to countermeasures based on password or challenge/response, which involves shifting operations before any debugging operation. This paper intends to evaluate costs involved by the solution proposed in [START_REF] Silva | Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits[END_REF] on several circuits examples. Two variants of the original scheme are evaluated showing that test time overhead due to scan chain encryption can be largely offset with low cost extra DfT.

The remainder of this paper is organized as follow. Section II presents the scan chain encryption approach. Section III details the cost of the proposed secure test scheme on several examples. Eventually, Section IV concludes the paper.

II. PRESENTATION OF SCAN CHAIN ENCRYPTION

The countermeasure proposed in [START_REF] Silva | Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits[END_REF] targets circuits embedding at least one crypto-core. We assume a tamperresistant memory to store secret-keys and a key management policy (no additional key management policy is required). The countermeasure implementation consists in adding light block ciphers at the input and the output of the scan chain (Fig. 1). Without the knowledge of the key, it is not possible to set the circuit to a desired state, nor to read plain circuit states. Input Scan Cipher prevents control-based scan attacks, Output Scan Cipher prevents observation-based scan attacks. This solution ensures a protection while keeping debug facilities. The developer wanting to debug an application can read and write on the registers of the processor.

The whole test procedure is described in Fig. 1. The first step consists in generating test patterns for the original circuit under test, and collecting expected test responses to these patterns from simulation. The generated test patterns are then encrypted off-chip. At test time, each encrypted test patterns is first scanned in the device then decrypted using the Input Scan Cipher before to be shifted in the scan chain of the Circuit Under Test (CUT). The test response to this pattern is stored in the scan chain of the CUT. While shifting out that test response, the Output Scan Cipher encrypts the data before circuit scan out. Eventually, encrypted test responses are decrypted off-chip to be compared with expected ones.

Each block cipher relies on an N-bits round register with two operating modes, parallel-load and shift. The parallelload mode allows encrypting/decrypting CUT test data. The number of iteration for encryption/decryption depends on the implemented block cipher. The shift mode allows to serially deliver test data to the CUT scan chain (input block cipher), or to read out CUT scan chain content (output). N must be chosen according to the chosen block cipher.

Concerning test coverage, the original circuit is tested without any loss by using scan chain encryption since original test patterns are actually applied to the CUT after decryption. However, the additional test infrastructure has to be tested as well. Clearly, it is not possible to use classical scan design for the additional scan ciphers because, otherwise, scan attack would be possible on that ciphers.

III. EXPERIMENTS

In the following experiments, two PRESENT block ciphers are used for the implementation of the Input/Output block ciphers, as also described in [START_REF] Bogdanov | PRESENT: An Ultra-Lightweight Block Cipher[END_REF]. This decision was guided by the low implementation costs, for a sufficient obtained security level. If more security is required (for instance to cope with side-channel attacks) a solution is proposed in [START_REF] Poschmann | Side-Channel Resistant Crypto for less than 2,300 GE[END_REF].

In this considered solution, the PRESENT encryption block size is 64 bits (N=64) and the encryption/decryption is done in 32 cycles. Experiments are conducted thanks to the synthesis tool Design compiler [START_REF]Design Compiler[END_REF] and the ATPG tool TetraMAX [START_REF] Synopsys | [END_REF].

A. Area cost

Both scan ciphers share some common parts, especially the key expansion and the finite state machine controlling the operations. The total area of the proposed solution is 2081 combinational cells and 396 FFs. This area overhead is to be compared to the original circuit where the solution is implemented. Table 1 reports the overhead on 5 circuit examples: a triple-DES core, a pipelined AES core with the 128-bits and 256-bits version, a RSA 1024 bits core and a LEON3 processor. For each circuit, line Cell area reports the area of the original circuit after regular scan insertion (Scanned Circuit) and the overhead (%) induced by scan encryption. In case of very large circuit like LEON3 processor, the proposed solution induces only 0.57% overhead. This overhead represents 5.74% for the smallest circuit Triple-DES.

B. Test coverage

In order to prevent any scan attack on the two extra scan ciphers, we prevent these extra blocs to be scanned out while storing an intermediate encryption state. The controller implemented to perform scan encryption on the original circuit involves full encryption (32 rounds) of every test pattern/test response for the original circuit, and control the scan enable signals allowing to shift PRESENT round registers. There is no "regular" scan chain procedure implemented for scan ciphers.

Circuit

Triple The regular procedure would involve a control of their initial state and direct observation of their round register right after storage of an intermediate encryption state. Instead, the scan input-cipher's final state, i.e. the state achieved after one 32-rounds encryption, is only observable after several steps: (i) propagation through the scan chain of the original design, (ii) execution of one clock cycle for storage of the circuit response to that pattern, and (iii) full encryption through the output scan cipher. A similar procedure prevents the control of the output scan cipher: its initial state results from a decrypted pattern through the input scan cipher, and its final state is scanned out only after full encryption (32 rounds).

In order to provide test results on those extra ciphers we propose to evaluate test coverage achieved on those blocks thanks to the test procedure implemented for the original circuit. Test patterns, and respectively test responses, of the original circuit are indeed propagated and processed by the scan ciphers. These data are CUT dependent and thus can be regarded as random data w.r.t the scan ciphers' faults. Due to obfuscation and diffusion properties of cryptographic algorithms, it is expected that such circuit can be easily tested with random data [START_REF] Di Natale | Self-Test Techniques for Crypto-Devices[END_REF] [START_REF] Schubert | On random pattern testability of cryptographic VLSI cores[END_REF]. Both scan ciphers have thus been fault simulated while processing CUT test data. Input scan cipher is stimulated with encrypted CUT test data, the output scan cipher is stimulated with CUT test responses. Fault Coverage (FC) are reported in Table 1, line Encrypt. Test Coverage, and show that 100% FC have been achieved on the extra test circuitry on every case study. The number of test pattern/responses processed by the scan ciphers is reported in line #Patterns, and corresponds to the number of test patterns of the CUT. We can see that maximum fault coverage is also achieved with a short random sequence of only 77 patterns. Block ciphers are thus fully and "freely" tested during CUT test procedure.

C. Test time cost 1) Basic scan implementation

Each scan cipher implements one N-bits round register to realize shifting and encrypting/decrypting operations. Every N clock cycles, an interruption of shift operations happens and the scan cipher must encrypt or decrypts the register content. In order to save test time, we implemented a second round register per scan cipher (see Fig. 2). While one of the two register is in shift mode in order to scan-in (respectively scanout) CUT test data (resp. CUT test response), the other register is used for decryption/encryption. With this optimization, Fig. 3.a shows the complete time diagram of shift operations with scan chain encryption. The circuit has F=S•N+R flip flops, where:

-F the total number of FF in the original circuit -S the number of N-bit segments -R = F modulo N

For the example presented Fig. 3, two N-bits segments (S=2) and a non-zero segment R compose the scan chain. Several patterns are used to test the circuit:

-𝐼 𝑗 𝑘 (respectively 𝑂 𝑗 𝑘 ) the j th segment (with 0≤j≤S=2) of N bits of the k th test pattern (respectively response) provided to (and obtained from) the circuit -E(x) the encrypted value of a segment x. To ensure the test of the original circuit, it's necessary to pad patterns to have N-bits length segment, corresponding to block size cipher. That's why the first segment of each pattern 𝐼 0 𝑘 is divided into a part of R bits 𝐼 0 𝑘 𝑅 and a part of N-R bits 𝐼 0 𝑘 𝑁-𝑅 . N-R bits complete each test pattern to have a length multiple of N. As it can be seen in the Fig. 3.a, at the step preceding the functional clock cycle (i.e., when the scanenable signal is not anymore asserted and the flip-flops are going to sample the actual response of the circuit), the scan chain content is correctly filled with the input test pattern. However, concerning the first segment 𝐼 0 1 , R bits are on the scan chain of the original circuit, while N-R are already entered in the Output Scan Cipher. At T=7×N+1, these N-R bits encrypted are shifted out and they have no impact on the response. The tester retrieves the same data sent in the input of the scan chain circuit.

Regarding the responses, two N-bits segments 𝑂 0 𝑘 , 𝑂 1 𝑘 and a R-bits segment 𝑂 2 𝑘 𝑅 form each response. The response is shifted out in the Output Scan Cipher for encryption. Fig 3 .a presents the case of the first response 𝑂 1 : the two first Nbits segments 𝑂 0 1 and 𝑂 1 1 are encrypted and shifted outside the circuit. For the remaining R bits response 𝑂 2 1 𝑅 , the next input test pattern 𝐼 2 completes the register filling. Indeed the N-R bits 𝐼 0 2 𝑁-𝑅 fill the output register with the R bits response 𝑂 2 1 𝑅 at T=8×N+1. The Output Scan Cipher encrypts the R-bits response with the additional part 𝐼 0 2 𝑁-𝑅 . The register content is then shifted out. On the received response, the tester can discard the N-R bits part. In the next operations, the others patterns are treated in the same way: the first N-R bits of input test pattern complete each last segment response of R-bits length.

Concerning the test time overhead, we have 2xN additional shift operation at the very beginning of the test procedure in order to feed the pipeline. The same additional shift operation is present at the end of the test to clean the pipeline. Moreover, we need N-R additional shift operations for each test pattern when R>0. More formally, by defining T the number of clock cycles for the original circuit to be tested without scan attack countermeasure, and K the overall number of test patterns, the number of clock cycles 𝑇 𝑓 required to test the circuit with the encryption of the scan chain is shown in equation ( 1

𝑇 𝑓 = { 𝑇 + 2 • 2𝑁 𝑖𝑓 𝑅 = 0 𝑇 + • 2𝑁 + (𝑁 -𝑅)(𝐾 + 1) 𝑖𝑓 𝑅 > 0 (1)
On each circuit, we determine the test time cost. Tab. 1 resumes the results: line #SFF reports the number F of scan FF, line #Patterns reports the number K of patterns needed to test the circuit, line Test Cov reports the test coverage of the original circuit. Line Test Time reports for each circuit the test time of the original implementation in terms of clock cycles, and the overhead induced by the encryption of both test patterns and test responses. In the case of pipelined AES 256 core, scan length 12736 FF is a multiple of N=64. Therefore, the test time overhead is only of 2x2N=256 cycles for scan-in initialization and last scan-out, which represents only 0.01% of the original test time. At the opposite, the pipelined AES 128 core has 7873=123×64+1 SFF. Therefore, the number of additional shift operations on each patterns is N-R=63 additional clock cycles. It's the worst case in terms of cost on each pattern. However, even in this case, the test time overhead is limited to 0.81%. For the others circuits, the number of additional clock cycles in each pattern is 24 for Triple-DES, 53 for RSA and 2 for LEON3 processor.

The number of patterns found by ATPG achieves only 70% of stuck-at fault coverage on that CUT because we stopped test pattern generation due to limitation in terms of memory allocation (line Test Cov in Table 1).

2) Using extra bits for testability improvment

Time diagram in Fig. 3.a, shows extra N-R bits on every test pattern for synchronization with the PRESENT cipher. These bits are scanned in the Output Scan Cipher and processed with following test responses without participating to the CUT test. We propose to use these extra bits for testability improvement. These N-R bits are thus stored into N-R dummy scan FFs appended to the original CUT scan chain instead of being scanned out in the output scan cipher. The implementation involves extra costs in terms of area overhead. This cost is relative to the number of SFFs in the original CUT. For instance, LEON3 processor needs two extra FFs to pad its scan chain. The cost is only 2 FFs over 107518 FFs (<0.002%). In the worst case, 63 FFs are added to AES-128 core, i.e. 0.8% compared to the original scan chain with encryption. For Triple-DES (resp. RSA) circuit, dummy FFs represent an increase of 0.27% (resp. 0.32%) on the total scan chain. Tab 3. reports the overall cost of these designs compared to the original scan designs.

We now explain how these extra FFs can be used for testability improvement and, consequently, test time optimization.

Test point insertion is a classical Ad Hoc DfT procedure which consists in adding extra control or observation points to the circuit logic in order to improve its testability. Observation points in particular allows improving propagation of test responses to observable points, i.e. scanning FFs. Observability improvement usually results in reducing the test sequence length (less test patterns for same fault coverage).

The DfT tool Tetramax was used for selection of observation points in the circuit logic. We constrained the tool to use only the N-R extra FFs for testability improvement. After selection, observation points drives extra XOR trees ending on the proposed extra FFs, thus allowing their observation at test time. The XOR-trees configuration depends on the number of signals to observe. The number of test points per tree is user-defined and is ranging from 1 (only one observation point feeds the extra FF), to 8 (8 observation points drives an 8-input XOR tree feeding the extra FF).

To choose the best implementation, the eight cases are studied on each circuit. Tab. 2 presents the results for AES-128 core. As explained before, 63 extra SFF can be added to this circuit scan chain without affecting its test time. We iteratively experimented observability improvement with V. CONCLUSIONS Scan chains offer facilities to realize scan attacks. A countermeasure proposed in [START_REF] Silva | Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits[END_REF] is based on the encryption of the scan chain content making test data unemployable for an attacker. Embedded scan cipher realize encryption and decryption operations with the key already present in the circuit. We need no additional key management policy. This secure solution can be used for test, diagnostic and debug.

In this paper, experimental results on several circuits show that this solution affects the original circuit with a marginal cost on area and test time. We have also proposed an optimization of the solution applicable on most of the circuits to minimize or even fully compensate extra test time due to longer shifts in the scan chain.

Fig. 1 .

 1 Fig. 1. Scan chain encryption scheme

Fig. 2 .

 2 Fig. 2. Scan cipher optimized with two registers: (a) R1 receive shifted data while block cipher encrypts R2 content; (b) R2 receive shifted data while block cipher encrypts R1 content.

Fig. 3 .

 3 b details shift operations with N-R extra scan FFs. All 'last segment' of each pattern 𝑂 2 𝑘 now includes N bits in this new implementation. It does not affect the test time compared to the former implementation (see III.C.1) since the number of shift operations remains the same.

Fig. 3 .

 3 Fig. 3. Time Diagram of shift operations: (a) case where scan chain length isn't a multiple of N, (b) case where additional FF pad the scan chain

  ):

			Pipelined AES-128 (𝑭 = 𝟕𝟖𝟕𝟑 = 𝟏𝟐𝟑 × 𝟔𝟒 + 𝟏)
		Scan	Encrypt		Optimized version overhead (+63 FF) + Encrypt
			overhead (%)				(%)
	#observation			1	2	3	4	5	6	7	8
	points per FF
	#Patterns	246	246	242	245	237	238	239	235	236	236
	Area	367 926	+2.92	+3.10	+3.17	+3.23	+3.30	+3.36	+3.43	+3.51	+3.58
		Tab. 2. Impact on number of observation points per flip-flops for test time optimization on Pipelined AES-128 circuit

  1to-8 observation points per XOR tree. For instance, with only one observation point per extra FF, the ATPG tool reduces the test sequence from 246 to 242 patterns. The best implementation corresponds to 6 observation points per extra FF, saving 11 patterns. Scan chain encryption applied on this implementation implies only 0.013% of test time overhead compared to 0.81% for scan chain encryption on original circuit. In other words, the extra test time due to the required synchronization with PRESENT encryption/decryption, and leading us to add extra shifts on every pattern, is compensated by the reduction of the total number of patterns to achieve the same fault coverage. The extra cost of scan chain encryption for test point insertion is +3.43% compared to original scanned design, with +2.92% for scan encryption without testability optimization, i.e without 63 extra FFs and 6-inputs XOR trees.Experimental results on test time optimization and costs are presented in Tab. 3. For each circuit, the number of scanned flip-flops, the number of patterns, the test time (in clock cycles) and the area (cell area) are given for four versions: the original circuit with scan chain (row Circuit), the circuit with the scan chain encryption (row Circuit+Encrypt), optimized version with added scan FF connected to observability points (row Optimized) and optimized circuit with the scan chain encryption (row Optimized+Encrypt). Test time results for Circuit+Encrypt are compared to original test time (Circuit) while results for Optimized+Encrypt are compared to test time with test point insertion (Optimized). Area of original scanned circuit (Circuit) is the comparison reference for both Circuit+Encrypt and Optimized+Encrypt versions. When two implementations lead to the same pattern optimization, we choose the implementation with the smaller impact in area.Concerning optimized Triple-DES circuit, four observe points per FF are used on the 24 added SFF. Test time overhead decreases from 0.31% for scan encryption applied on original circuit by 0.038% for scan encryption applied on optimized circuit. However, the area cost of scan chain encryption increases from 5.74% when applied on original circuit to 5.87% when applied on optimized circuit. For LEON3 processor, 107 patterns achieve a test coverage of 70%. With 4 observe points on the 2 added SFF, this number of patterns decreases by 5 patterns. For scan encryption on LEON3 with test points, test time increases only by 0.002%, while for scan encryption on original LEON3, test time increases by 0.004%. The area cost is almost the same (0.57%) than the non-optimized scan chain encryption due to the large size of the CUT.Unfortunately, insertion of test points doesn't allow reducing the number of test patterns on RSA. The AES-256 is not reported here since it is already optimized (its scan chain length is a multiple of 64). Extra test time for scan encryption is only 0.01% increase over non-encrypted scan test (see Tab.2).

	Circuit			#SFF	#Patt Test time	Area
		Circuit		8808	77	687101	187 494
	Triple-
	DES	Circuit+Encrypt	8808	77	+0.31% +5.74%
		Optimized	8808+24 74	662730
		Optimized+Encrypt 8808+24 74	+0.038% +5.87%
		Circuit		7873	246	1944877 367 926
	Pipelined
	AES 128	Circuit+Encrypt	7873	246	+0.81% +2.92%
		Optimized	7873+63 235	1873131
		Optimized+Encrypt 7873+63 235	+0.013% +3.43%
		Circuit		16459	2393 39405239 468 415
		Circuit+Encrypt	16459	2393 +0.33%	+2.30%
	RSA 1024
		Optimized	16459+53 2393 39532121
		Optimized+Encrypt 16459+53 2393 +0.001% +2.51%
		Circuit		107518 107 11612051 1902095
		Circuit+Encrypt	107518 107	+0.004% +0.57%
	LEON3*
		Optimized	107518+2 102 11074662
		Optimized+Encrypt 107518+2 102	+0.002% +0.57%
	Tab. 3. Cost to use optimized scan chain encryption with test points
	regarding several circuits
	*: for LEON3, test time and number of patterns are evaluated to obtain a
	test coverage of 70%
			IV. ACKNOKLEDGEMENT
	This project has been funded by the French Government
	(BPI-OSEO)	under	grant		FUI#20	TEEVA
	(Trusted Execution EVAluation).


Da Mathieu
email: mathieu.da-silva@lirmm.fr

Marie-Lise Silva

Giorgio Di Flottes
email: flottes@lirmm.fr

Bruno Natale
email: dinatale@lirmm.fr

Rouzeyre
email: rouzeyre@lirmm.fr

Paolo Prinetto
email: paolo.prinetto@polito.it

Marco Restifo

Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits

Keywords: Test and Security, Scan Attacks Countermeasure, Light Encryption I

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same time, to preserve test efficiency, diagnosis and debugging abilities. We propose to use the secret-key management policy embedded in the device under test in order to encrypt both control and observed data at test time. This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time.

INTRODUCTION

Testing is used for weeding out bad products before they reach end-users and is considered as a necessary task in the IC production process to ensure quality. When it comes to the area of digital testing, many research works have been dedicated to this task for ending up today in an acceptable tradeoff between efforts dedicated to test pattern generation and Design for Testability (DfT). Most popular DfT methods rely on scan design. This structured approach consists in replacing original registers by scan registers, connecting these scan registers into one or several scan chains, where extra serial input/output provide a mechanism for serially controlling and observing registers' states at test time. Scan design greatly reduces the complexity of test pattern generation from sequential to combinatorial tests, much easier to generate.

While testability is positively impacted by full control and observation on internal states, the confidentiality of processed data is negatively affected by this design technique for exactly the same reasons. Free control and observation of IC internal states related to a secret have therefore to be avoided. Scan attacks indeed exploit facilities offered by the scan chain to retrieve the secret data [START_REF] Yang | Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard[END_REF] [4]. These attacks target secure circuits implementing a cryptographic algorithm and storing a secret key. They rely on the possibility for hackers to shift out the scan chain's content while the circuit state is correlated with the secret, i.e. the key. As a first line of defense, it is commonly assumed that the secret key must not be used at test time. The key register is thus not part of the scan chain for preventing direct observation of the secret. For the same reasons, a key-for-test is used at test time when internal states can be fully observed. This second constraint prevents observation of circuit states while processed information are related to the secret. These two conditions are however not sufficient for preventing scan attacks, which rely on the possibility to switch the device from mission mode, where the data are related to the secret, to test mode, where the data can be observed through shift out operations. The attack is possible because the scan chain allows observing the intermediate states of the crypto-processor. Observing the final state, i.e. the cypher text, would not provide useful information on the secret key even with the knowledge or control of the plain text on crypto-processor inputs. Cryptanalysis is indeed assumed not computationally tractable on current encryption standards. However, observation of intermediate states provides useful information on the key. Crypto-algorithms rely on two fundamental properties, obfuscation and diffusion. The first one reflects a desire to make cypher texts and the keys relation as complex as possible, the second aims to prevent statistical analysis between cypher and plain texts. These properties are carried out by dedicated operations between data-to-encrypt and key bits, and, iterations over these operations. Test facilities are used to break these expected iterations, and thus decrease obfuscation and diffusion. Thanks to the scan chain, the intermediate state of the crypto-processor can be observed, for instance right after first operations involving the secret key. At that time, plain text, key and cipher text relations are not too complex and key bits can be retrieved from plain-text control and observation of the intermediate state stored in the scan chain.

The main difficulty in scan-attack prevention stems from the need to maintain both data security and hardware quality provided by test, diagnostic and debug activities. The cost of the scan attack prevention in terms of circuit characteristics (performances, area), insertion in the design flow, test quality and test time are important issues. While several solutions have been proposed to prevent these scan attacks, no proposal is available for providing at low cost both high security and test / diagnostic / debug facilities to a trusted user.

The goal of this paper is to present a secure and cost efficient mechanism for full control and observation of the scan chain content. The main idea is to exploit the knowledge of the secret key originally embedded in a security-dedicated circuit in order to encrypt the scan chain itself. This way, only trusted users with the appropriate access rights, i.e., ones having access to the secret key, are able to encrypt (respectively decrypt) the bit stream shifted-in (respectivelyout from) the scan chain. The knowledge of the secret key is therefore sufficient for performing all required activities, without sacrificing test efficiency, diagnostic, or debug facilities.

The remainder of this paper is organized as follow. Section II summarizes the known attacks exploiting the scan chains and related countermeasures. Section III presents the proposed secure test scheme. Section IV details related algorithms and reports on optimized implementation of the solution. Finally, Section VI concludes the paper.

II. KNOWN SCAN-ATTACKS AND COUNTERMEASURES

In order to retrieve secret information (e.g., a secret key) from processed data, the attacker targets registers storing internal states of the embedded crypto-core. For instance, the round-register of a core implementing the Advanced Encryption Standard (AES [START_REF] Daemen | The Design of Rijndael[END_REF]) is used when performing scan attacks on that crypto algorithm. A 128-bits AES involves a 128-bits key and proceeds on 128-bits data block, executing 10 iterations called rounds before to deliver the cipher text. The attack principle consists in observing the data stored in the round-register thanks to a scan out operation after the execution of the first AES round. It is assumed that the details of the encryption algorithm are known to the attacker since the security only relies on the secret key. It is also assumed that test access mechanisms are available (JTAG port, scan chains, test control), the attacker can choose the plaintext and is able to run exactly one round before to switch to scan out operation.

Such attacks have been first presented in [START_REF] Yang | Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard[END_REF] for DES and in [START_REF] Yang | Secure scan: a design-for-test architecture for crypto chips[END_REF] for AES. They are based on differential analysis on observed states and because the algorithm, the input plaintext, and the result the 1 st round operation are known to the user, it is possible to retrieve the secret key added to the plaintext during the first round. These attacks require to first understand the scan chain architecture, i.e., determine all the data that was the result of the round operation among all the data scanned out of the device. Improved scan attacks have been proposed to deal with more advanced DfT approaches such as scan response compactors, X-masking, partial scan [4], [START_REF] Darolt | Are advanced DfT structures sufficient for preventing scanattacks?[END_REF] where round operation data are not necessarily entirely observed on scan-out pin.

Several counter-measures have been proposed to face these scan attacks. An industrial practice consists in letting the test access mechanism unbound after manufacturing test. This solution does not affect production testing, DfT flow, nor the design itself but prevents maintenance in the field. Moreover, probing techniques can be easily set to re-connect to scan-in and scan-out pins by an attacker.

Resetting the round register when the circuit switches from mission mode to test mode has also been explored as countermeasure. The scan attacks presented above indeed do not stand if the switch implies a reset of the round register, since there is no meaningful data to observe. However, the attacker can either prevent the reset operation by acting on the scan-enable signal for shifting out the data without setting up the test mode (e.g., using probing), or she/he may implement a test-mode-only attack. The attack presented in [START_REF] Subidh | New scan-based attack using only the test mode[END_REF] for instance circumvents the reset countermeasure since it proceeds in test mode only, without requiring any switch from the mission mode. The plaintext used all along the attack is set thanks to the scan in operation. However, it is important to note that the procedure assumes that the secret key used in mission mode is also used in test mode.

Built-In Self-Test (BIST) [START_REF] Doulcier | AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis[END_REF] seems to be a very attractive solution since scan chains are no longer accessible for external control and observation. However, besides possible loss in terms of fault coverage, this DfT approach compromises diagnostics and debugging.

A further solution proposed in literature is the use of secure test wrappers [START_REF] Chiu | A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores[END_REF] where the access to the test mechanism is protected by a locking mechanism. Only authorized users with the test session key are granted test access. In addition to the area penalty introduced by this solution, issues on manageability of test-session keys must still be solved.

The solution proposed in [START_REF] Hely | Scan design and secure chip[END_REF] consists in fixing the scan chain structure (FFs' ordering) only during the test mode. In mission mode, the FFs are dynamically and randomly assigned to different positions in the scan chain. This scrambling operation prevents analysis of the data observed on the scan-out pin since there is no possibility to know which data is observed at any moment. This solution provides a high level of security and is compliant with usual design flow, but the mechanism for scrambling the scan chain data seriously impacts the device area and increases power consumption in mission mode.

Other architectures have been explored for preventing scan based attacks by implementing a 'secret' combinational or sequential function within the scan chain to obfuscate its content [START_REF] Fujiwara | Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers[END_REF]. The tester has to be aware of the specific hidden procedure and test data has to be processed before being compared to expected data. This solution is based on the assumption that the attacker has no way to get the information on the scan chain's implementation. However, such 'securityby-obscurity' approach goes against Kerckhoffs' doctrine and is not considered as strong.

A secure embedded comparator is proposed in [START_REF] Rolt | Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison[END_REF] for preventing states observation. The basic idea is to compare the actual circuit test response with the expected one within the chip boundaries instead of scanning-out the response for external comparison. Test data fed to the circuit include both test vectors and expected test responses. The comparison result is not bitwise delivered to the ATE, but stored inside the chip until the last bit of the whole response vector has been compared, making thus any attack based on the observation of test responses inefficient. With this solution, there is no impact on test coverage or test time. Diagnostic can still be done thanks to a fault dictionary where test responses are stored for modeled faults. However, this procedure requires much longer processes since all pre-computed faulty responses must be uploaded in the circuit in order to be on-chip compared with the actual, but unknown, ones. Because there are potentially as many faulty responses than faults detected by the pattern under evaluation, the diagnostic process requires #detectedfault-per-pattern iterations for each unexpected response. Debug is also affected by the lack of observability.

In [START_REF] Rosenfeld | Attacks and Defenses for JTAG[END_REF] the authors propose the use of a stream cipher in order to encrypt the content of the JTAG communication. The authors decided not to use a block cipher due to expected large area overhead and potential supplementary test time for testing the extra bloc cipher. However, they resort also to a hash function and a message authentication code in order to set-up a secure protocol to exchange the secret key used for the stream cipher.

In this paper we will show that the use of a light block cipher can reduce the additional area overhead. Moreover, we propose a scheme where the block cipher introduces a constant delay in the overall test scheme, without requiring non-standard test protocols. In addition, this extra delay may be offset by introduction of low cost observation points.

III. PROPOSED SOLUTION

The proposed solution applies for integrated circuits embedding at least one crypto-core, a secret key stored in a non-volatile memory, and a secret key management policy. We also consider that the circuit implements scan-based DfT and that some FFs of the scan chains belong to the crypto-core, thus being the target of a possible scan attack. Moreover, we consider that the circuit will be used for applications where there is the need of a debugging facility implemented through the access to the scan chain. For instance, the circuit could be a microprocessor with a crypto co-processor, and the developer of the final application might need to access the content of the registers of these processors to debug the application.

The main idea is to encrypt the content of the scan chain with a block algorithm. Assuming a key management policy already embedded in the secure device, the system integrator chooses to provide one initial key, or ideally distinct initial keys, for mission, debug and test modes on system's cores. Key extension circuitry must be designed according to the chosen scan cipher, i.e. PRESENT in this paper. The test data is ciphered/deciphered with the key currently known and used by the person accessing the circuit, the developer in charge of a debug procedure for instance.

The proposed test procedure (as shown in Fig. 1) consists of the following steps: 1. Generate test patterns for the circuit under test and compute expected 'fault-free' test responses; 2. Off-chip encrypt the test patterns with the chosen cryptographic algorithm and the secret key related to the current activity; 3. Scan-in an encrypted test pattern, which is first on-the-fly decrypted using the additional Input Scan Cipher, then scanned in the circuit under test; 4. On-the-fly encrypt the test responses using the additional Output Scan Cipher before shifting-out the encrypted circuit response;

5. Off-chip decrypt the encrypted test responses to obtain the actual responses of the circuit and compare with expected ones.

As shown in Fig. 1, two block-ciphers are to the original circuit. These two ciphers have an N-bit round register (R) with two operating modes, parallel load and shift. The Input Scan Cipher decrypts data provided by the ATE, while the Output Scan Cipher encrypts the test response before transmission to ATE.

Every N clock cycles, the shift operation must be interrupted in order to allow the scan ciphers to encrypt/decrypt the N-bit data. By assuming that the encryption operation lasts D clock cycles, this solution would require D additional clock cycles for every N bits, and would result in an excessive test time overhead. To reduce this overhead, we propose the use of two registers in each scan cipher (see Fig. 2). These extra registers allow interleaving the shift operation and the encryption process. While one of the two registers (e.g., R1) is serially loaded with new data, the other one (i.e., R2) is used in the meantime to encrypt the data stored during the N previous clock cycles. Fig. 3 shows the detailed timing of the shift and ciphering operations for the input scan cipher. In this example, the bitstream feeding the scan chain is split in 4 segments of N The test time is thus impacted by 2xN extra clock cycles used at the beginning of the test procedure for loading R1 and R2 registers before to feed the original scan chain. A similar procedure is executed at the output of the circuit and the same additional offset of 2xN extra clock cycles is required at the end of the test procedure in order to read-out last data stored in R1 and R2 of the Output Scan Cipher.

Fig. 3. Timing of scan operations

A controller is in charge of enabling the correct sequence of operations based on the value of the scan enable signal. Whenever a scan operation is required, the controller enables the two scan ciphers to prevent any clear bitstream to be inserted or observed.

Finally, managing these operations with scan chains whose length is not a multiple of N is not an issue. Following the same regular N-shifts scheme the controller can correctly feed the scan chain at the cost of additional clock cycles used to complete the shift operation on the smaller-than-N segment. Fig. 4 shows the complete time diagram of shift operations in the case of a circuit having F=S•N+R flip flops, where:  F the total number of FF in the original circuit  S the number of N-bit segments  R = F modulo N  𝐼 𝑗 𝑘 (respectively 𝑂 𝑗 𝑘 ) the j th segment (with 0≤j≤S) of N bits of the k th test pattern (respectively response) provided to (and obtained from) the circuit;  E(x) the encrypted value of a segment x;  decrypt() and shift() the two operations inside a block cipher.

As shown in Fig. 4, at the step where the first segment of the second pattern I0 2 is decrypted (row 7), the scan chain is actually set to the first test pattern value: Ix 1 (N bits) … I1 1 (N bits) I0 1 (R bits), while N-R first bits of the first scanned-in segment I0 1 have been shifted in the Output Scan Cipher register. Row 12 in the time diagram shows that the N-R bits of the second pattern-first segment I0 2 , "ddd", are encrypted and shifted out as part of the last R-bits test response.

Concerning the test time overhead, we have 2xN additional shift operations at the very beginning of the test procedure in order to feed the pipeline and, in the case of R>0, we need N-R additional shift operations for each test pattern. More formally, by defining T the number of clock cycles for the original circuit to be tested without scan attack countermeasure, and K the overall number of test patterns, the number of clock cycles 𝑇 𝑓 required to test the circuit with the encryption of the scan chain is shown in equation 1:

𝑇 𝑓 = { 𝑇 + [2 • 2𝑁] 𝑖𝑓 𝑅 = 0 𝑇 + [2 • 2𝑁 + (𝑁 -𝑅)(𝐾 + 1)] 𝑖𝑓 𝑅 > 0 (1)
In section IV.B we propose an optimization that allows reducing the overall test time at the cost of R additional FFs.

IV. EXPERIMENTS

In this section we present an implementation of the proposed solution, where the PRESENT block cipher [START_REF] Present | An Ultra-Lightweight Block Cipher[END_REF] is used for test data encryption and decryption. PRESENT has been chosen because of its low cost implementation. It encrypts and decrypts data blocks of 64 bits (i.e., N=64) in 32 clock cycles (i.e., D=32).

A. Implementation

We implemented the finite state machine controlling the two scan ciphers and optimized the design by sharing common parts in both scan ciphers, i.e., the key expansion and the PRESENT control unit.

Both PRESENT ciphers and their control represent a total of 2081 combinational cells and 396 FFs (10,760 equivalentcell area). This overhead is to compare with the original circuit under test. According to the number of extra gates/FFs for implementing the PRESENT ciphers, this secure scan chain solution is clearly dedicated to large designs. However, as we assumed in Section III, for circuits embedding a microprocessor and one (or more) cryptographic cores, this solution has a very small impact since the same PRESENT block ciphers can be used to encrypt the scan chain content of the whole original circuit.

We applied our solution to test a pipelined AES core with one scan chain composed of 7873 FFs (total area = 367,926 equivalent-cell area). The area overhead related to the proposed secure scan infrastructure is of 2.92%. According to the block size handled by the PRESENT algorithm, the 64-bit segment decomposition of the AES scan chain leads to F=7873=123x64+1. The scan chain is thus composed of S=123 segments of N=64 bits each, plus one extra segment of length R=1. This example corresponds to the worst-case scenario where the smaller-than-N segment requires the longest relative test time overhead. Indeed, N-R=63 extra clock cycles are added to the shift operation of each test pattern in order to implement the constant 64-bits shift operation on every segments. As an example, the Automatic Test Pattern Generation Tool we used provided us with a test set of K =1148 test patterns to achieve 100% of Fault Coverage. This test set results in a test time of T = (7873+1)x1,148+7873=9,047,225 clock cycles for the original AES. The final test time for the proposed architecture represents an overhead of (eq. 1): 2x2x64 + (64-1) (1148+1) = 72,643 clock cycles, i.e. only 0.8% of the original test time.

B. Optimization

The additional clock cycles that are wasted in order to synchronize the encryption scheme using constant segmentlength N can be exploited to increase the testability of the original circuit.

On every pattern, N-R extra clock-cycles are used to shift N-bits data on a regular manner. By adding N-R dummy flip flops to the original scan chain, we can use these extra FFs for observing internal signals, without any impact on the test time. The insertion of these observation points increases the circuit testability and can reduce the number K of test patterns to achieve a given fault coverage. This optimization on the pipelined AES example allows saving 29 test patterns, thus a time saving of 1.74% compared to the test time of the original circuit without protection. The proposed scheme including the two PRESENT input/output ciphers, the controller, and 63 extra scan FFs for observation represents an area overhead of 3.26% compared to the unprotected scanned AES. This optimization is therefore attractive because with a small additional cost in terms of area (in the worst case 63 FFs are added) it can reduce even the original test time, by still protecting the scan chain against scan attacks.

C. Test of the test infrastructure

The proposed technique allows testing the original circuit without any loss in terms of test coverage. However, the test infrastructure must be tested as well. The input and output scan ciphers require a different test approach. Indeed, it is necessary to test the scan ciphers without transforming them into a classical scan design, otherwise the overall security would be jeopardized (the scan attack could be applied on these scan ciphers). Therefore, the solution is to test the scan ciphers with functional test patterns.

As previously shown in [START_REF] Di Natale | Self-Test Techniques for Crypto-Devices[END_REF] and [START_REF] Schubert | On random pattern testability of cryptographic VLSI cores[END_REF], the test of circuits implementing cryptographic algorithms is effective even by using random test patterns. Indeed, random data and possible errors are easily propagated through typical operations involved in such encryption algorithms thanks again to their obfuscation and diffusion properties. Experiments perform on PRESENT show that 100% fault coverage of stuck-at faults can be achieved with 1000 random patterns of N=64 bits.

Testing the original circuit provides us with patterns (and responses) processed through the PRESENT ciphers. These patterns can be seen as random patterns with respect to these PRESENT ciphers and should therefore be able to test them without requiring any additional patterns. We have validated this assertion using the S35932 benchmark. We used this circuit instead of the AES because this circuit is much smaller and it requires a lower number of test vectors to be fully tested. If, by using the vectors for the S35932 benchmark, the proposed architecture is also tested, then it will be also tested with bigger circuits (requiring more test patterns to be tested), The test sequence for the S35932 is composed of 55 patterns of 1728 bits. These data are equivalent to 1485 random patterns of 64 bits applied to the PRESENT Scan input cipher, while 1485 test responses from S35932 are applied to the Scan output cipher. As expected, while the sequence is applied in the first instance for detection of the S35932 faults, the sequence also covers 100% stuck-at faults in the proposed test infrastructure. No additional test patterns are needed to test the scan chain encryption.

D. Security

With scan chain encryption, scan-based attacks are not possible. Indeed, input decryption prevents control-based scan attacks since it is not possible to set desired values in the scan chain of the device under test without knowledge of the key. For the same reason, output encryption prevents observationbased attacks since internal states of the device under test cannot be analyzed without decryption.

If the scan-enable is disabled during an encryption (i.e., in the middle of a shift operation), all the registers of the proposed controller and scan ciphers are frozen. The FSM controlling block ciphers goes to a hold state and resume to the previous state when the scan-enable is asserted again. The encryption resumes where it lefts off and no unencrypted data is shifted-in or shifted-out. Concerning FSM vulnerabilities, no signals connected to FSM are directly accessible because its test is ensured without scan chains. Therefore, it is not possible to bypass the encryption by altering FSM control signals.

A possible attack imagined on the proposed test infrastructure could be to reset the FSM before the end of R1 filling. This reset operation would lead the FSM to start again shift operations on R1 and unencrypted data would be shifted out. For this reason, registers R1 and R2 are reset whenever the FSM is reset.

Regarding the security of PRESENT block cipher, security analysis is performed in [START_REF] Present | An Ultra-Lightweight Block Cipher[END_REF]. It is proven that this block cipher is resistant to differential cryptanalysis. Concerning side-channels attacks, a resistant version of PRESENT exists in [START_REF] Poschmann | Side-Channel Resistant Crypto for less than 2,300 GE[END_REF]. Therefore, PRESENT have a good security level and is one of the smallest block cipher.

To our knowledge, other proposed block ciphers have either a larger implementation than PRESENT or a prohibitive latency or do not guarantee a sufficient security level. Nevertheless, it is clear that if a better block cipher is proposed, it can replace PRESENT in the proposed test infrastructure.

V. CONCLUSIONS

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data. In this paper we proposed a solution based on the encryption of the scan chain content. This scheme applies to integrated circuits that embed at least one cryptographic core and thus a secret key management policy. The main idea is to cipher the content of the scan chain with a secret key developed for the current activity. In debug mode for instance, the developer must be aware of the secret key used in mission mode and thus, the same key could be used for deciphering/ciphering operations on scan chain input and output. The solution allows using the scan chains for both manufacturing test purposes as well as debugging the circuit at mission time, without the need of different test access protocols. Experimental results showed a marginal impact on both area and test time.

Fig. 1 .Fig. 2 .

 12 Fig. 1. Basic proposed scheme


Didier Mazel

Shahriar Mobashery

Antibiotics as physiological stress inducers and bacterial response to the challenge

The rise of antibiotic resistance and its dissemination among Gram-negative and Grampositive bacteria present challenges to treatment of infections. As the need for new antibacterials is presently great, it is essential to understand what led to this inexorable selection over the past 50 years. This knowledge will guide us in arriving at policies to address the clinical problem and to define strategies to reverse the disconcerting trend [START_REF] Bush | HI Tackling Antibiotic Resistance[END_REF]. Whereas the scope of the problem is daunting and the options for remedies limited, in this issue of Current Opinions in Microbiology we have seven articles that discuss the state of the art in knowledge on several important facets of this incredibly complex and yet important scientific challenge.

Significant knowledge is in hand on transposable elements, plasmids and other mobile genetic elements, and on their synergic interactions for the capture and dissemination of resistance determinants. However recent studies have revealed that selection for resistance could be more complex than previously thought. The review by Hughes and Andersson analyzes the difference between the selection of resistance phenotypes and the evolution of bacteria, when confronted with either lethal concentrations of drugs or with the more frequent non-lethal concentrations encountered in the environment. They present evidence that mutations are rapidly enriched, and selected de novo, at very low antibiotic concentrations and discuss how this can contribute to the stepwise development of antibiotic resistance.

Another important issue is the role played by antibiotics as triggers of genetic diversification. The review by Blázquez and colleagues examine another facet of the effect of sub-lethal concentrations of antibacterials: their role as promoters of genetic variation. The authors argue that antibiotics, especially when present at non-lethal concentrations, are responsible for increased genetic variation, and therefore, paradoxically participate in the emergence of antibiotic resistance. Antibiotics may cause genetic changes by different pathways. These involve an increase of free radicals inside the cell or oxidative stress that induces the SOS response and its attendant triggering of the error-prone polymerase action. They can also lead to imbalance in nucleotide metabolism or act directly on DNA. In addition, antibiotics have been shown to induce horizontal gene transfer of antibiotics resistance encoding ICEs (Integrative and Conjugative Elements) and gene cassette capture in integron. The authors discuss in detail the relevance of these phenomena within the context of antibiotic-resistance development.

The review by Charpentier, Polard and Claverys debates the role of antibiotics as inducers of competence for genetic transformation, which has recently been observed in the distantly related species Streptococcus pneumoniae and Legionella pneumophila. In particular, they discuss the role that can be played by this competence induction in bacteria that lack the SOS response, and draw a parallel with the SOS induction by antibacterials in other bacteria. They propose that competence is a stress response that can substitute for SOS in bacteria defective for it and discuss it the context of convergent evolution.

The review by Dantas and Sommer deals with a crucial question arising from metagenomic studies and the resistome definition. Recent studies have revealed a wealth of genetic resources in terms of resistance genes in bacteria sharing the same ecological niche. Nonetheless, it is hard to predict which genes will be shared in isolates of remote species that share the niche. This reveals a highly diverse and complex network for genetic exchange among bacteria, especially among pathogens and environmental organisms, where one can identify the identical resistance genes and mobile elements. To complicate the situation, in some cases, clinically relevant resistance genes might have been acquired from organisms in which their native function would not be manifestation of antibiotic resistance. In their review, the authors attempt to distinguish the resistance phenotype from the resistome genotype, and explain why this distinction is important to understanding the relevance of environmental niches that contribute most to clinical problems associated with antibiotic resistance.

As mentioned above, acquisition of exogenous genetic material is the main route for the development of resistance to numerous classes of antibacterial drugs in a wide range of pathogenic bacteria. However, characterization of a novel mechanism of resistance to ceftazidime in Burkholderia pseudomallei has revealed that resistance can also occasionally come about by gene loss. This scenario is likely not common, as most antibiotics target essential cellular functions for which there is no functional redundancy. In their review, Török, Chantratita and Peacock narrate the steps of this Finally, the review by Bagnoli and colleagues examine the interplay between vaccines and antibiotics treatments, and the possible role of new vaccines as a promising solution to the rise of antibiotic resistance in most pathogenic bacteria. They present a thoughtful perspective on the different selective forces exerted by vaccines and antibiotics, which impact the manner in which bacteria escape their action. In particular they draw parallels and contrasts in the observation that emergence of antibiotic-resistant pathogens is inexorable, whereas efficacious vaccines have never been shown to elicit vaccine-resistant strains. They also discuss the fact that vaccines are contributing to the reduction of antibiotic usage through the establishment of herd immunity by limiting transmission of pathogenic bacteria to potentially susceptible individuals and therefore limiting the numbers of infections in the overall population.

The static view of antibacterials as mere toxic compounds to bacteria that simply bind a target and kill is refuted. The biological response by bacteria to exposure to antibiotics is multifaceted from the physiological point of view and the response in the form of mechanisms of resistance that are selected and disseminate are complex. The reviews in this issue describe other, sometimes unexpected, outcomes to the various effects of sublethal concentrations of antibiotics on bacterial physiology and evolution, in complement to transcriptional activation events reviewed earlier in Current Opinion in Microbiology [START_REF] Davies | The world of subinhibitory antibiotic concentrations[END_REF]. The understanding of these processes has gained additional poignancy in light of significantly diminished activity in the pharmaceutical industry over the past two decades in discoveries of new drugs for treatment of bacterial infections. Only time will tell, if humanity would keep one step ahead of evolution of antibiotic resistance in bacteria.

2 1

 2 Institut Pasteur, Unité Plasticité du Génome Bactérien , CNRS UMR3525, Département Génomes et Génétique, 75724 Paris cedex 15, France; 2 Department of Chemistry & Biochemistry, University of Notre Dame, Notre Dame, Indiana 46556, USA. Didier Mazel is professor at the Pasteur Institute, Head of the Unité Plasticité du Génome Bactérien and director of the department "Genomes and Genetics". His research group works on gene capture, horizontal gene-transfer mechanisms, and Vibrio genomics, with a particular focus on integrons. Shahriar Mobashery holds the Navari Chair in the Department of Chemistry and Biochemistry at the University of Notre Dame. He leads a multidisciplinary group of scientists. His research interests span studies of the mechanisms of antibiotic resistance, design of new classes of antibiotics and investigations of bacterial cell wall.

  discovery and discuss what rendered it possible in this specific context. The review by Mediavilla and colleagues examines the epidemiology of communityassociated methicillin-resistance Staphylococcus aureus (CA-MRSA) strains, which are increasingly implicated in nosocomial infections, and may eventually displace hospitalassociated MRSA strains in hospitals. They review the current molecular epidemiology of the different CA-MRSA sequence types, as defined from MLST, with respect to genetic diversity, global distribution, and factors related to their emergence and spread. They present data showing that distinctions based on clinical epidemiology and susceptibility are becoming less relevant, arguing in favor of genotypic definitions, which would reflect better the continuously emerging "waves" of MRSA evolution.