Keywords: GaN HEMT, Trapping effects, LF S-parameter measurements, Noise measurements, TCAD physical simulations, Analytical modeling, Thermal modeling

Table of Figures

List of Tables

Introduction

In recent years, the development of advanced communication standards and modern digital telecommunication systems demands a continuous improvement of the RF performances in terms of output power, bandwidth, efficiency and signal fidelity. The most crucial part of any communication system is the active transistor which is capable of predicting the performances of the complete system. Therefore, the focus on the microwave transistors have been significantly increased over the last few years, and much of the research activities have been specifically devoted to the development of suitable device technology that would meet the everincreasing demands of the future electronic innovations. For instance, higher efficiency, higher speed, low power and wider band-width are intensely required for wireless portable communication systems whereas satellite based systems and TV broadcasting require device technology which is capable of operating at higher frequencies and higher output power, in order to reduce the overall size of the complete system.

The semiconductor industry has been dominated by silicon technology for more than a decade and the major factor contributing to the growth of the industry is the scaling of devices.

Currently, 11/10-nm node technology is considered to use in industrial applications and 7-nm node is expected to appear in RF market by the year 2018, and 5-nm node by 2020. Moreover, the easy availability of Si by nature is another reason for its huge success in semiconductor industry. The scaling of device leads to the improvement in device RF performances, however the Si based devices are rapidly approaching their maximum theoretical limit of operation and therefore, they are not capable of delivering the performance demanded by the future RF and microwave applications. Furthermore, the low carrier mobility and saturation velocity impedes its suitability for modern electronic applications such as TV broadcasting and mobile communications. Hence, a research on new materials such as SiGe, SiC and group III -V semiconductors have been investigated to replace the existing silicon technology. The conventional group III -V materials has already demonstrated its remarkable success in optical applications. However, the narrow bandgap property of these materials limits their ability for high power and high temperature applications. Moreover, group III -Nitrides promises improved performance advantages over conventional group III -V semiconductors because of their direct and wide bandgap. Among group III-Nitrides, GaN material has been considered as the promising material for both optical and microwave high power applications. Although GaN-based optical devices have been widely used in commercial applications, GaN-based microwave device technology is relatively immature until today that restrains the widespread commercialization of these devices. However, GaN-based devices have demonstrated remarkable performances to meet the ever-increasing demands of the communication market.

The superior electron transport properties of GaN material makes this GaN technology feasible for applications ranging from commercial to military.

The AlGaN/GaN High Electron Mobility Transistors (HEMTs) have been emerged as the promising candidates for high-power microwave and mm-wave applications. The superior physical properties of GaN material along with its potential to create hetero-structure device makes this device capable of operating at higher frequencies. Moreover, the presence of spontaneous and piezoelectric polarization charges increases the two-dimensional electron gas (2DEG) density in the channel, without the requirement of any intentional doping in the device.

The large bandgap offset formed between the AlGaN and GaN materials forms a quantum potential well like structure to accommodate the 2DEG closer to the hetero-junction interface.

Therefore, the electrons present in the quantum well possess extreme high mobility, due to the absence of doping which causes the increased ionized impurity scattering effects. The 2DEG sheet carrier density (ns) achieved in GaN HEMTs is well above 10 12 -10 13 cm -2 which is very much higher compared to other group III -V semiconductors. Furthermore, the improvement in the DC and RF performances of GaN HEMT devices, over the years, has been widely reported in the literature.

Over the years, there has been remarkable progress dedicated to the growth of GaN HEMT device technology including improving the quality of hetero-structure epitaxial layers, passivation layers and materials used for passivation, selecting the best substrate materials, optimizing the barrier thickness, implementing gate-recess techniques and adoption of fieldplates, either gate or source connected. All these technological improvements further extend the boundaries of GaN HEMT device performance. However, the presence of traps in the structure significantly degrades the device performance and also detriments the device reliability. The origin of these traps and their physical location in the device remains unclear. Trapping effects in the device causes current collapse, output admittance dispersion, transconductance dispersion, gate-lag, and drain-lag and also contribute to low frequency noise. Moreover, the presence of traps also causes increased gate-leakage, hot-electrons based device degradation and stress-induced defect generation.

In this thesis, a part of the research activities has been specifically devoted to understand the trapping mechanisms and its physical locations in the device structure using experimental characterization and physics-based TCAD Sentaurus device simulations. The experimental techniques such as Low-Frequency S-parameters measurement, Low-Frequency Noise (LFN) measurement and drain-lag characterization have been used for characterizing the traps existing in GaN/AlGaN/GaN HEMT devices. Furthermore, we have used TCAD physical simulations to identify the physical location of traps in the device.

The second part of the thesis is focused on characterizing the AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrates. As the demand for high frequency performance of GaN-based HEMTs are increasing over time, it is often necessary to implement ultra-short gate lengths and using of thin AlGaN barrier. However, these processes significantly degrade the performance of AlGaN/GaN HEMT devices. Therefore, AlN/GaN HEMT devices are receiving much attention these days and also considered to be a suitable alternative to replace conventional AlGaN/GaN HEMT devices. The AlN/GaN HEMT devices is capable of delivering high drain current (~2A/mm), high breakdown voltage and lower on-resistance (RON), even using ultrathin AlN barrier. The second part of the thesis is composed of three different research sections.

(i) The first section focusses on investigating the impact of GaN channel traps on the performance of AlN/GaN/AlGaN HEMT devices using two-dimensional (2D) TCAD-based physical simulations. (ii) Obtaining a lower RON after an OFF-ON switching event is a critical requirement for power switching applications. Moreover, the temperature has also a significant influence on RON. Therefore, we attempt to extract the temperature-dependent RON of the AlN/GaN/AlGaN HEMT devices using on-wafer measurements and TCAD-based device simulations. Furthermore, we propose a simplified technique to extract the temperature-and bias-dependent channel sheet resistance and parasitic series contact resistances of this device technology. (iii) In the third section, we have made a comprehensive evaluation of thermal behavior of AlN/GaN/AlGaN HEMTs grown on Si and SiC substrates through threedimensional (3D) TCAD thermal simulations and on-wafer measurements. Using pulsed I-V measurements, the thermal resistance (RTH) for various device geometries have been extracted. Furthermore, TCAD thermal simulations have been performed for the similar device geometries and the RTH have been extracted and verified with measurement results.

The organization of the thesis is described as follows:

Chapter 1 introduces the physical properties of GaN material, importance of GaN HEMT technology compared to other existing device technologies. The key challenges and reliability issues of GaN-based devices such as current-collapse, gate-lag, drain-lag, self-heating and hotelectrons degradation effects and gate-leakage have been described in detail. The extraction of activation energy and cross section of the traps existing in the device using LF measurements have been explained. The TCAD physical simulation model calibration procedure has been discussed in detail. The identification of physical location of traps using TCAD physical simulations have been discussed.

Chapter 4 explores the influence of GaN channel traps on the performance of AlN/GaN/AlGaN HEMTs grown on SiC substrate using TCAD-based physical device simulations. The impact of both donor-like and acceptor-like traps on the device performance have been studied. In the second part of this chapter, the temperature dependent study of on-resistance of this device technology have been analyzed using on-wafer measurements and TCAD simulations.

Moreover, a simple methodology to extract the temperature and bias-dependent parasitic channel sheet resistance and contact resistance of the device have been proposed.

Chapter 5 investigates the thermal resistance extraction of AlN/GaN/AlGaN HEMTs grown on different substrates using on-wafer pulsed I-V measurements and 3D-TCAD thermal simulations. The thermal resistances extracted using measurements and TCAD simulations have been discussed in detail. Then, the simulated transient thermal behavior of the device and its respective modeling using modified recursive network have been described.

Finally, the results obtained in previous chapters have been summarized and the necessary conclusions are drawn. It also outlines the scopes of the future work based on the results obtained in this thesis.

Chapter 1

Introduction to basics of GaN HEMT Technology Introduction to basics of GaN HEMT Technology

General Introduction

Modern wireless communication systems such as portable mobile devices and base stations require an RF power amplifier with high linearity and efficiency. The most crucial component of any RFPA is the active device, which is capable of determining the performances of RFPA in terms of gain, output power, efficiency, bandwidth and linearity. The dominant technology currently in use for the design of high power RFPAs is the Si LDMOSFET. However, the development of modern communication systems demands the active device to operate at higher frequencies with higher output power. The established Si based LDMOS device technology in the current RF market is capable of covering only a frequency range from few hundred Mega hertz (MHz) up to a maximum of 3.8 Giga hertz (GHz) [1.1], [1.2]. Hence a good deal of research on new semiconductors such as SiC, GaAS and GaN and other wide band gap materials has been undertaken in recent years to replace the conventional Si technology at high frequencies. The GaAS MESFET devices are capable of operating at high frequencies due to their bulk high electron mobility value, but the thermal conductivity is approximately only one third, when compared to Silicon that makes this technology feasible only for low power applications [1.3]. SiC MESFETs are also suited for high temperature and high voltage operations due to its material properties. However, the SiC devices lack the potential of forming a hetero-junction and hence have low electron mobility which impedes their capability for high frequency applications. Among others, Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) device technology has proven to be the best and most successful device for microwave high power and RF applications so far. The superior material properties of GaN together with the hetero-structure device make GaN technology capable of operating from a few hundreds of MHz to 100 GHz [1.4].

Brief History of GaN HEMTs

GaN HEMTs are still considered to be relatively immature technology when compared to conventional GaAs HEMTs and Si LDMOSFET technologies. However, most of the recent research work has been primarily focused on the improvement of GaN HEMT technology, in order to become a disruptive technology for RF and microwave power applications. Khan et al. [1.5] reported the first AlGaN/GaN hetero-junction transistor in 1992, the two-dimensional electron density (2DEG density) in the channel was observed in the order of 10 11 cm -2 and the electron mobility was in the range of 400-800 cm 2 /V.s. Moreover, they were the first group to report the DC and RF performance of GaN HEMTs in the consecutive years, 1993 and 1994, respectively [1.6], [1.7]. The saturation drain current of 40 mA/mm was reported for 0.25-µm gate length device [1.7]. In 1996, Wu et al. [1.8] reported a RF power density of 1.1 W/mm at 2 GHz for AlGaN/GaN HEMT. Over the years, the improvement in the performances of AlGaN/GaN HEMTs have been largely reported in the literature. The power density of 40 W/mm at the operating frequency of 4 GHz was reported in [1.6]. An extreme high output power of 500 W at L-band was reported in [1.9]. Moreover, in recent years, some remarkable combinations of high output power (Pout), high power-added efficiency (PAE), high break-down voltage, maximum cut-off frequency (fT) and maximum oscillation frequency (fmax) have been reported. Kimura et al. [1.10] reported 43% PAE with an output power of 60-W at X-band, and Yamasaki et al. [1.11] demonstrated 68% PAE with 100-W output power at C-band. A maximum current density of 750 mA/mm with a current gain cut-off frequency of 90 GHz has been reported [1.12] for a 0.1-µm gate length AlGaN/GaN HEMT grown on Si substrate. For a 0.9-µm AlGaN/GaN HEMT on Si substrate, fT and fmax of 100 and 206 GHz, respectively have been reported in [1.13]. The break-down voltage (VBR) of 1500 V has been reported for AlGaN HEMT on Si substrate in [1.14]. Similarly, the highest break-down voltage of 1700 V has been reported for AlGaN HEMT grown on Sapphire substrate in [1.15]. A PAE of 34.2%, Pout of 2.5 W/mm, fT of 149 GHz and fmax of 285 GHz have been reported at 87 GHz in [1.16]. Moreover, the state-of-the-art of AlGaN/GaN HEMTs for LNA and RF power amplifier applications have been reported in [1.17]- [1.19]. Regardless of the reported performances, the commonly observed output densities are in the range of 12 W/mm and the drain current is in the range of ~1 A/mm, respectively. The performance of the AlGaN/GaN HEMT devices can be further improved by implementing the ultra-short gate lengths and using of thin AlGaN barrier. However, reducing the thickness of the AlGaN barrier below a certain extent (10-nm) causes the strongest degradation of 2DEG density in the channel [1.20]. Therefore, in recent years, AlN/GaN HEMT devices are gaining much attention because of their capability of achieving higher current density (2A/mm), using an ultra-thin AlN barrier [1.20]. The maximum drain current (IDmax) of 3 A/mm, with fT and fmax of 454 and 444 GHz, respectively has been reported [1.21] for 20-nm gate length AlN/GaN HEMT device grown on SiC substrate. A PAE of > 33% and Pout of 2.3W/mm at 40 GHz have been reported [1.22] for 0.1-µm AlN/GaN HEMT devices grown on Si with an ultra-thin AlN barrier of 6-nm. The IDmax of 1.5 A/mm and with fT of 370 GHz have been reported for 0.3-µm InAlN/AlN/GaN HEMT devices in [1.23]. In summary, the last decade has witnessed the substantial amount of research work has been devoted to GaN HEMTs and hence the performance has improved significantly.

Material Properties of GaN and other Related Technologies

The material properties of devices for RF high power applications are listed in Table 1.1 [1.19].

The GaN material has high band gap energy and high electric break down strength, which can translate into high transistor operating voltages and high breakdown voltages of GaN devices [1.18]. The high saturation velocity causes the high output power delivered from small sized GaN devices, which makes this GaN technology more compatible for high power applications. The small size devices further implies that these devices have higher input and output impedances and it eases the low loss impedance matching [18]. The GaAs material has a high electron mobility and large electron saturation velocity, however the break-down electric field is limited to 0.4 MV/cm and hence, it is suitable only for medium power applications.

Moreover, GaN-based HEMTs can achieve higher electron mobility than GaN MESFETs due to the isolation of dopants far away from the 2DEG channel, attributed to reduced impurity scattering effects. Johnson's figure of merit (JM) represents the power-frequency limit of the material. A JM value of < 3 implies that the material is suitable only for low power applications.

It is evident from Table 1.1, GaN material has the highest JM which makes them ideal for high power and high frequency applications. The high carrier concentration and high electron mobility lead to a lower on-resistance (RON) which is crucial for power switching applications.

All these unique material properties of GaN devices are the primary reason for their better performance compared to the Silicon RF MOSFETS. However, the GaN technology is relatively immature and is quite expensive. The commercially available GaN HEMT devices either use Silicon (or) Silicon Carbide (SiC) as a substrate material. The GaN-on-SiC HEMT demonstrates superior performance than GaN-on-Si HEMT due to the high thermal performance of the SiC substrate which allows efficient heat dissipation. This is particularly important for high power and high frequency applications. However, in recent years, the stateof-the-art has also been reported for the AlGaN/GaN HEMT devices grown on Si substrate [1.13].

AlGaN/GaN High Electron Mobility Transistor (HEMT)

A High Electron Mobility Transistor is an heterostructure device composed of two different layers in which the wide band gap material is grown over the narrow band gap material. The energy band diagram of the HEMT device before forming the hetero-junction is shown in Fig. It is widely known that built-in electric fields formed due to polarization induced charges in the GaN crystal and this plays a crucial role in determining the electrical and optical properties of GaN-based devices. There are two kinds of polarization namely spontaneous and piezoelectric polarization that contribute to the formation of 2DEG in the AlGaN/GaN HEMT device [1.24].

The spontaneous polarization refers to the built-in polarization field existing in an unstrained GaN crystal. This polarization field exists because the crystal lacks its symmetry and the resulting bond between two atoms is not purely covalent. This results in the displacement of the electron towards one of the atoms in the crystal bond and this cause the accumulation of surface charges of opposite polarity across both the ends of the crystal [1.26]. In an ordinary GaN crystal, the polarization charges do not accumulate because the oppositely charged charges tend to cancel each other. However in case of AlGaN/GaN heterostructure, the GaN crystal suddenly ends and AlGaN crystal begins to grow, so there is an abrupt change at the hetero- The lattice constants of a0 and c0 for GaN material are slightly larger than that of AlN material and hence, the thin AlGaN barrier layer grown over the GaN buffer experiences a tensile strain and it is shown in Fig. 1.4. The amount of tensile strain produced is directly proportional to the thickness of the grown AlGaN barrier layer. However, the GaN is normally relaxed due to the thick grown buffer region on the selected substrate. Moreover, in case of the nitride system, the piezoelectric constants are at-least ten times higher than those of typical III-V semiconductors and this results in large polarization field [1.24], [1.26]. Therefore, a large magnitude of polarization charges are induced at the hetero-junction interface. Fig. 1.6 shows the electric field and piezoelectric polarization charges existing in a conventional AlGaN/GaN HEMT structure grown on c-plane, in a Ga-face crystal structure.

The strain induced due to piezoelectric polarization can alter the band structure and thus changes the sheet carrier concentration in the channel region. Hence, the strain induced polarization provides an additional way of engineering, through which the HEMT device characteristics can be improved. In a typical doped AlGaN/GaN HEMT structure, the doped AlGaN barrier layer supplies electrons to the hetero-junction interface. However, intentional doping is not essential for the AlGaN/GaN HEMT devices due to the high polarization charges induced in the device structure, capable of producing a sheet carrier concentration of 10 13 atoms/cm 2 at the hetero interface region [1.30]. Moreover, the contribution of the doped AlGaN barrier layer to the formation of 2DEG at the hetero interface region has been reported to be less than 10% due to the polarization nature of GaN material [1.30] The typical structure shown in Fig. 1.7 has suffered from major problems such as DC-RF dispersion which is related to surface and bulk traps and high leakage current [1.19], [1.34].

The DC-RF dispersion describes the difference in the output power estimated from DC-IV curves and from the load pull power measurements [1.35], [1.36]. These problems severely limit the operation of GaN HEMT, especially for microwave high power applications. The DC-RF dispersion problem has been reduced by the introduction of SiN passivation [1.37], [1.38] in the device structure and thereby the significant improvement in the output power can be achieved [1.39], [1.40]. Moreover, the SiN passivation also helps to increase the breakdown

Substrates

The AlGaN/GaN epilayers are widely grown on sapphire, SiC and Si substrate due to the significant cost and complications involved in producing a large amounts of GaN wafers.

However, GaN can be the ideal substrate as there would be no lattice mismatch and this would reduce the number of defects generated in the device. Recently, diamond have been considered

as another choice due to its high thermal conductivity but still it is expensive to use. One of the major role of the substrate is to conduct and efficiently dissipate the heat generated during the device operation. Table 1.2 gives some important properties of substrate which must be considered while fabricating high frequency electronic devices.

Sapphire

Sapphire is an insulating material with a poor thermal conductivity and it also has the largest lattice mismatch with GaN, compared to other commonly used substrate materials. Depending on the relative orientation with GaN, the lattice mismatch generally varies between 14% and 23%. The large lattice mismatch would cause the large number of defects (10 10 cm 2 ) generated in the GaN layers. This lattice mismatch also has influence on reducing the carrier mobility, reducing the life time of minority carriers in the device, decreasing the overall thermal conductivity and all of these effects would degrade the device performance. However, this substrate is economically viable and available in large size wafer diameters. Therefore, GaNon-sapphire has been the most commonly used substrate over the years, for evaluating the performance capability of GaN-based devices in high frequency applications.

Substrate

Silicon (Si)

Si is probably the most attractive substrate among all others due to the availability of large diameter wafers and low cost. The lattice mismatch between GaN and Si is 17% and the lattice constant is higher than GaN. Therefore, GaN layers grown on Si substrate experience a tensile stress, which leads to generation of crystal defects and dislocations, degrades the performance of the device. However, Si material has a moderate thermal conductivity of 1.54 W/cm K. In recent years, a significant amount of work has been devoted to the development of GaN-on-Si substrate. The state-of-the-art has also been reported for the AlGaN/GaN HEMT devices grown on Si substrate in [1.13], [1.14].

Choice of Buffer Configuration

The electrical properties of the GaN buffer layer is significantly important for the realization of high efficient GaN HEMT devices [1.44]. The presence of deep levels in this highly resistive buffer layer are a necessary requirement to reduce the leakage current and also the short-channel effects [1.44] [1.45]. Such deep levels can be due to either intrinsic defects or by introducing external dopants such as iron (Fe) or carbon (C) [1.45]. However, the high density of defects in the buffer induces the trapping mechanism [ref] and are strongly correlated with the device operation. The iron doping in the GaN buffer result in Fermi level pinned to the upper half of the bandgap whereas the carbon doping pin the Fermi level in the lower half and thereby, causing significant current-collapse [1.45]. As a suitable alternative, the AlGaN back barrier double hetero-junction devices have been considered recently, and they demonstrate high electron confinement, high frequency performance and low trapping effects [1.46]. However, the presence of AlGaN back barrier has a negative impact on the thermal performance.

Moreover, the thermal conductivity of the back barrier decreases with increase in Al mole fraction and thus, results in poor device performance [1.46]. Furthermore, higher gate leakage current is commonly observed in AlN/GaN/AlGaN HEMT back barrier devices. Therefore, selecting a suitable buffer configuration plays a vital role in obtaining desired device performance from GaN HEMT technology.

Key Challenges of GaN HEMT Technology

Although GaN HEMT devices have demonstrated the state-of-the-art performance for RF and microwave power applications. Trapping effects are one of the major factor that limits the performance of AlGaN/GaN HEMT devices till today [1.30]. The presence of material defects due to the growth of AlGaN/GaN epilayers on a lattice mismatched substrate, or the distortion of crystal lattice due to the formation of hetero-junction interface, create deep levels inside the device that act as traps for charge carriers. Fig. 1.9 shows the possible location of traps in the AlGaN/GaN HEMT devices. The parasitic charges moving in and out of these traps located on different regions of the device degrade the device dynamic performance and also their reliability [1.47]. The different locations of traps inside the device causes different parasitic effects that degrade the DC performances, dynamic transconductance, on-resistance (RON) or the RF output power [1.47], [1.48]. Furthermore, it is important to note that the definite correspondence between the parasitic effect and the associated location of traps inside the device is not well completely understood. However, many papers reported in the literature by several research groups show consistent results relating the parasitic effect along with its physical location of traps in the device.

The following sub-sections describe the commonly observed parasitic effects in the GaN-HEMT devices and its influence on the device performance.

Current Collapse

Current collapse is the widely reported parasitic effect in GaN HEMTs that causes the significant reduction of output power at high frequency. The current collapse has also been referred as current slump, DC/RF dispersion or current compression [1.26], [1.34]. It is basically the discrepancy observed between the DC and RF measured output power of the device. It causes a reduction of the dynamic saturation drain current compared to the DC-ones and therefore, increases the access resistance. This also results in reduction of the device dynamic transconductance, increase of knee-voltage (VKnee) and further, leads to reduction of RF gain and the measured output RF power [1.34], [1.36]. Moreover, the current collapse also increases the high-frequency distortion and reduces the efficiency. The current collapse can be described using the following equation [1.26]:

  out DS,max Breakdown Knee 1 P *I * V V 8   (1.1)
Where IDS,max and VBreakdown are the measured maximum drain current and breakdown voltage of the device at DC conditions, respectively.

To explain the lower RF output power, IDS,max is supposed to decrease whereas VKnee will be increased, compared to the measured DC values and this has been illustrated in Fig. 1.10. This parasitic effect is correlated with the existence of traps in the device. Although traps can be located in the buffer layer or the barrier layer or at the surface of the device, several research studies suggest that surface traps cause much of the dispersion observed in measurement [1.30].

However, it has been reported in [1.45] that current collapse occurs also due to bulk traps in the buffer region. The phenomenon of current collapse due to the surface traps can be described using the concept of the virtual gate model [1.26]. Fig. 1.11 shows the schematic explanation of the current collapse trapping mechanism. When the negative gate bias voltage (region I) i.e. below pinchoff voltage is applied to the gate, the high electric field is induced in the device, typically the peak value is located at the drain side edge of the gate. This results in leakage of electrons between the gate and drain and, can fill the ionized donor states located on the surface close to the gate terminal of the device. It is important to note that these positively charged ionized donors (surface donors) are essential to balance the electrons (2DEG) existing in the potential well. Therefore, the charging of ionized surface donors, forces the surface potential to become negative and as a consequence, the channel under the part of the drain access region next to the gate terminal is completely depleted out of electrons. The extended depletion region due to the negative surface potential that acts as negative biased virtual gate is shown in Fig. 1.11 (c). Therefore, under this condition, the current along the channel is controlled by two gates: the usual gate terminal, controlled by the applied external gate bias voltage, and the virtual gate, controlled by amount of charges trapped on the surface.

In region II, the gate bias is assumed to be positive, the channel under the gate turns-on immediately, and however, the virtual gate controlling the channel under the drain access region is slow to respond (Fig. 1.11 (d)). The amount of delay in responding to the applied gate bias strongly depends on the de-trapping transient of the surface traps. The deep level traps and the low electron mobility values under this region are responsible for the degradation of drain current. Although, the gate bias is changed to positive, the drain access region is still depleted out of electrons and hence, possesses a low carrier concentration. This induces a highly resistive drain access region and most of the applied potential drops across this region and therefore, the drain current remains low. However, the captured electrons are eventually emitted from the traps after some period of time (region III) and thereby, the drain current reaches the steady state value (Fig. 1.11 (e)). Therefore, for high frequency operation, if the electric field is sufficiently high to fill the surface traps, the device operation strongly depends on the obtained maximum drain current, considering the slowest phenomena between the RF sweep and the trapping/de-trapping transients of these surface traps and not based on the maximum obtainable DC performances [1.26]. In pulsed operation, the device operation is significantly influenced by the trapping effects depending on the applied quiescent bias point, and by the de-trapping transient obtained after the turning on-pulse. The current collapse phenomenon can significantly degrade not only the dynamic RF performance of the devices, but also the high-power switching applications. The increase in the drain access resistance and knee voltage can considerably increase the power dissipation even under switch-OFF conditions. Therefore, to minimize the current collapse mechanism, different techniques such as surface passivation and the adoption of field-plates have been reported in the literature [1.39], [1.41]. The surface passivation creates an optimal dielectric-semiconductor interface that prevents the filling of ionized surface traps by the electrons leaking from the gate and hence, reduces the current collapse mechanism. The field-plate in the device structure allows the lateral distribution of electric field over the drain access region and thereby, preventing the peak electric field located near the drain side of the gate edge. This will limit the electron trapping and emission process and hence, prevents the increase of the current collapse effect.

Gate-Lag

The gate-lag is used to describe the slow transient response observed in the drain current measurement when the applied gate voltage of the device is changed abruptly. The device pulsed I-V characteristics have been measured under two biasing conditions: one at VGSq, VDSq = (0 V, 0 V) and the other at VGSq, VDSq = (-5 V, 0 V). The pulse width and pulse period applied to the drain terminal are 900-ns and 900-µs, respectively. Pulsing the device from steady state biasing conditions ( 0 V, 0 V) results in an ideal I-V characteristics, however, a drastic reduction in drain current due to gate-lag mechanism is observed under (-5 V, 0 V) biasing conditions.

Drain-Lag

The term drain-lag is used to describe the slow transient observed in drain current measurement when the applied drain voltage of the device is pulsed abruptly and a high negative bias (below Vpinch-off) is applied to the gate terminal of the device. Therefore, drain-lag effect is the combined response of the applied gate and drain biasing conditions. Fig. 1.14 shows the schematic explanation of drain-lag mechanism observed in GaN HEMTs. A very high negative bias applied to the device induces the gate-lag effect due to the leakage of electrons on the surface of the device and this modulates the electrons available in the 2DEG channel. Moreover, pulsing the drain terminal to a higher biasing conditions results in an increased electric field across the device. Fig. 1.15 shows the drain-lag measurements of GaN/AlGaN/GaN HEMT grown on SiC substrate under the same conditions as shown in Fig. 1.13. The pulsed I-V characteristics have been measured under two biasing conditions: one at VGSq, VDSq = (-5 V, 0 V) and the other at

VGSq, VDSq = (-5 V, 15 V), to show the influence of drain-lag effects. Therefore, the electrons in the channel gets excited due to the applied higher drain biasing conditions and those excited electrons can escape from the channel and gets trapped in the buffer region of the device [1.30],

and thereby causes the significant reduction of drain current.

Reliability Issues

Although the GaN HEMT device excellent performances have been widely reported, the reliability issues still persist and this limits the commercialization of these devices. The following sub-sections discuss the important degradation device mechanisms which affects the reliability of GaN HEMTs.

Self-Heating and Hot-Electrons Degradation Effect

Self-heating (SHE) and hot-electrons effects [1.50]- [1.52] are the major issues that are strongly correlated and adversely affect the device performance and its reliability. The high power density and large breakdown electric field allows device operation even with the concurrent existence of very high electric field and high density of electrons in the channel. The applied high biasing conditions induce the high electric field in the device structure and particularly, the peak electric field is located at the drain side gate edge. Fig. 1.16 shows the schematic cross section of AlGaN/GaN HEMT device describing the high electric field region. The high electric field results in large amount of heat generated as well as a large current in the channel region of the device. Therefore, the electrons flowing in the channel acquires high energy and becomes hot carriers [1.53]. These hot carriers travel in an in-elastic mean free path of the channel region before they transfer the acquired high energy to the crystal lattice and hence, the channel temperature increases drastically, in turn accelerates the phonon scattering [1.50]. This will degrade the carrier mobility and thereby, the drain current. The negative slope observed in the drain current characteristics is due to the self-heating effect [1.50]. The hot electrons generation in the channel is particularly important for sub-micron gate length devices. These hot electrons can easily overcome energy barriers, can transfer the acquired high energy by colliding with the crystal lattice and they can create defects or dangling bonds inside the device layers which act as traps for charge carriers. The traps can be either generated in the channel, in the barrier or at the interface regions, depending on the kinetic energy of the hot electrons. In addition, the electrons may directly tunnel from the channel to the gate or to the AlGaN barrier or GaN buffer, may get captured in preexisting traps inside the device [1.50].

Therefore, this process partially depletes the 2DEG channel and leads to degradation of drain current. The main consequences of hot electrons degradation effect are the shift of pinch-off voltage, reduction of transconductance and the increase of on-resistance of the device [1.50], [1.52].

In GaAs HEMTs, the hot electron induced degradation can be identified by monitoring the increase in gate leakage current, caused by the collection of holes generated by impactionization process [1.52]. However, in GaN HEMT devices, the impact-ionization rate is considered to be negligible and the gate leakage current is generally controlled by the electron tunneling process (tunneling through AlGaN barrier). Therefore, the hot electron degradation effect in GaN HEMTs is usually characterized using electroluminescence (EL) measurements [1.54] .

Gate-Edge Degradation

When the GaN HEMT device is operated in the off-state, the gate-drain Schottky junction is degraded due to the applied reverse biasing conditions and this mechanism is referred to as gate-edge degradation. The higher reverse biasing applied to the gate-drain Schottky junction induces the high electric field in the device, thus enhancing the tensile strain and the stored elastic energy (converse piezoelectric effect) of the gate-drain access region considered to be the dominant mechanism responsible for higher gate leakage at higher operating temperatures. However, Fowler-Nordheim (FN) tunneling is also been observed at very low operating temperatures [1.62]. Moreover, the bias dependence gate leakage can be described using thermionic emission and trap-assisted tunneling mechanisms [1.63].

Thermionic Emission Model

In forward bias, the gate leakage at the Schottky junction is predominantly due to thermionic emission (TE). Fig. 1.17 shows the conduction band diagram of metal/AlGaN interface illustrating the thermionic emission process. The current density-voltage characteristics of a Schottky gate junction is given by [1.63]:

TE TE0 th V J J exp 1 V                  (1.2) 2 b TE0 th J A*T exp V          (1.3)
where JTE0 is the reverse saturation current density, A * is the effective Richardson's constant, T is the absolute temperature, ɸb is the Schottky barrier height, V is the applied potential, η is the ideality factor and Vth is the thermal voltage, respectively.

Poole-Frenkel Emission Model

The reverse gate leakage current of GaN HEMT devices is significantly higher than that predicted by thermionic emission model. It is due to the existence of traps in the device and it plays an important role in determining the gate leakage component of these devices [1.58]. In the low reverse gate bias region, the current conduction is due to Poole-Frenkel (PF) emission.

The with: α = -ɸt/Vth and β = (q/πεs) 1/2 /Vth.

C is the parameter dependent on the concentration of traps, ɸt is the barrier height for the electron emission from the trap state to the dislocation and εs is the dielectric permittivity of the semiconductor, respectively.

The electric field at the metal-AlGaN barrier can be computed using (1.5) [1.62]:

  b s q n E    (1.5)
where σb is the sum of the piezoelectric polarization charge in the AlGaN barrier and the difference between spontaneous polarization charge in the barrier and the GaN buffer, ns is the 2DEG concentration at the AlGaN/GaN hetero-junction interface and ε is the dielectric permittivity of the AlGaN material.

Fowler-Nordheim (FN) Tunneling Model

If the high reverse bias is applied to the gate, the electric field across the AlGaN barrier increases drastically and this results in thinning of the barrier height at the metal Fermi level.

Therefore, it facilitates the carriers to tunnel across the triangular barrier as shown in Fig. 1.19.

The increase in electric field reduces the tunneling barrier width and causes the increasing FN tunneling leakage current. However, this process must be independent of temperature. The relation between current density and electric field for FN tunneling mechanism is expressed

using (1.6) [1.62]: 2 FN B J A.E .exp E      (1.6)   3 * n eff 8 2m q B 3qh    (1.7)
where A is the constant, m * n is the conduction band effective mass in semiconductor, ɸeff is the effective barrier height and h is the Planck's constant.

Trap-Assisted Tunneling (TAT) Model

In low-reverse gate bias region, TAT becomes important since it compensates the non-zero PF current at zero gate-biasing conditions. In general, the electric field across the AlGaN barrier saturates for voltages well below pinch-off voltage of the device when 2DEG sheet carrier concentration ns becomes negligible compared to σb [1.62]. The electric field across the barrier is not zero at zero gate-biasing conditions due to the fact that polarization charge is higher than ns. Therefore, the current flows from gate to the channel through a trap-assisted tunneling (Fig. 1.20) to compensate for the PF emission current flowing from the channel to the gate near zero bias. Moreover, it is demonstrated that trap-assisted tunneling has the same temperature dependence as PF emission.

Therefore, the current density for trap-assisted tunneling mechanism is given by (1.8) [1.62]:

  0 TAT TAT0 2 th VV J J exp 1 V                   (1.8)
where JTAT0 is the reverse saturation current density, η2 is the ideality factor, V is the applied potential and V0 is the fitting parameter, respectively.

Physics Based Analytical Device Modeling and TCAD Physical Simulations of AlGaN/GaN HEMTs

Analytical Device Modeling

Introduction

The AlGaN/GaN HEMT has emerged as the most deserving candidate for high temperature, high power and high speed electronic circuits for microwave and mm-wave applications [2.1], [2.2]. This is due to the superior material properties of GaN such as wide bandgap, high thermal conductivity, high saturation velocity and large breakdown field [2.1], [2.3]. The AlGaN/GaN HEMT heterostructure device possesses superior electron transport properties due to the presence of high sheet carrier density at the heterojunction interface produced by the built-in polarization electric field [2.4]. The two-dimensional electron gas density (2DEG) achieved in the GaN HEMT device is well above 10 13 cm -2 [2.5], [2.6], without the requirement of any intentional doping in the device [2.6]. The presence of spontaneous and piezoelectric polarization charges are responsible for such high value of 2DEG sheet carrier density.

Furthermore, the increase of Al mole fraction in the AlGaN material will deepen the quantum well and hence facilitate more electrons to be confined in the channel. Therefore, the polarization charge density and bandgap discontinuity can be controlled using the Al mole fraction. This offers the flexibility of optimizing the HEMT device characteristics [2.7].

The progress of AlGaN/GaN HEMT has been quite impressive over the years and nowadays it is widely used in practical applications. Therefore, an accurate model of this device is highly desirable. The numerical calculation of the device characteristics is possible by self-consistently solving (2.4) and (2.6). However, the simulation takes a long time and it is difficult to integrate with modern circuit simulators. Therefore, it is advantageous to develop an analytical model which can be integrated with circuit simulators. Some analytical models of this device have been already reported in the literature [2.7]- [2.11]. These models are rather complex as they often require the calculation of the Fermi level [2.7] for each region of device operation and thus the sheet carrier density is obtained with a suitable approximation.

In this section, we have formulated a simple analytical model of current-voltage characteristics of AlGaN/GaN HEMTs, valid for both intrinsic and extrinsic device. The proposed model accounts the polarization charge density in estimating the 2DEG sheet carrier density. The influence of Al mole fraction and AlGaN barrier thickness in determining the pinch-off voltage variation and current characteristics is discussed in detail. The effect of source and drain parasitic resistances have also been incorporated to accurately predict the extrinsic HEMT characteristics.

Analytical Model Formulation

A cross-sectional view of the AlGaN/GaN HEMT structure used for modeling is shown in Fig. 2.1. In general, the HEMT structure consists of two layers in which the material with wider bandgap is doped and the material with narrow bandgap energy is normally un-doped. The principle of HEMT operation involves the transfer of electrons from ionized donors into a narrow bandgap energy material to form a conducting layer [2.7]. The transfer of electrons takes place owing to difference in electron affinity values of the two material. The potential well formed at the hetero-junction interface is narrow enough to accommodate the accumulated electrons. The high value of 2DEG sheet density obtained in a HEMT device, cannot be attributed only to the bandgap discontinuity but it is dominantly determined by the polarization electric fields at the hetero-interface. The spontaneous and piezoelectric coefficients of the GaN material are generally quite high, which is an added advantage. The total polarization charge density (σ(m)) as a function of Al mole fraction (m) at the hetero-junction interface is given by [2.7]:

        sp m 1 m sp pz m 1 m pz (m) P Al Ga N P GaN P Al Ga N P GaN        (2.1)
The GaN material is considered to be fully relaxed and thus the piezoelectric polarization is zero. Therefore, the total polarization component of GaN contains only the spontaneous polarization. The strain induced piezoelectric polarization of AlmGa1-mN along the [001] direction can be specified by [2.7]:

          13 xy 31 33 pz _ AlGaN m 33 cm P 2 e m e m cm            (2.2)
Where:

      xy a 0 a m am   (2.

Parameter

Expression Unit

Ɛ(m) (-0.5m +9.5) × 8.854× 10 -12 cm -1 V -1 ΔEc(m) 0.7({6.13m + 3.42 (1-m) -m(1-m)} -3.42) eV Φm(m) 1.3m + 0.84 eV c13(m) 5m + 103 GPa c33(m) -32m + 405 GPa a(m) (-0.077m + 3.189)× 10 -10 m e13(m) (-0.11m -0.49) cm -2 e33(m) (0.73 + 0.73) cm -2
Psp(AlGaN) (-0.052m -0.029) cm -2

Modeling of Sheet Carrier Concentration (ns)

The 2DEG sheet carrier density can be calculated from the solution of Schrodinger's and

Poisson's equations in the quantum well, considering the first two sub-bands in the GaN conduction band. A self-consistent solution of ns can be expressed as [2.12]:

    F 0 F 1 s t t t E E E E D ln 1 exp 1 exp V n V V                                            (2.4) 2/3 2/3 0 1 0 1 s s , n n E E     (2.5)     s F G OFF d s (m) (m) V(x) VV n E q dd       (2.6)
where D is the density of states, Vt is the thermal voltage, VOFF(m) is the polarization dependent pinch-off voltage and is given by,

  2 Dd m C OFF d s q (m) Nd (m) (m) (m) V d d E 2 (m) (m)           (2.7)
Here, ε(m) is the dielectric permittivity of AlGaN, dd and ds are the thickness of doped AlGaN barrier layer and un-doped AlGaN spacer layer, respectively. V(x) is the channel potential at a distance 'x' from the source end of the channel, Φm(m) is the Schottky barrier height of the gate metal and σ(m) is the polarization dependent charge density.

The polynomial dependence of Fermi level (EF) as a function of gate-source voltage (VGS)

proposed by Dasgupta [2.12] is used for estimating sheet carrier concentration.

F 1 2 s 3 s n E K K n K    (2.8)
where K1, K2, and K3 are temperature dependent parameters which are obtained for three different values of ns and by simultaneously solving corresponding EF equation as in [2.12].

The corresponding calculated values of K1, K2, and K3 for ns = 2 × 10 The values of ns are chosen in such a way as to cover all regions of device operation i.e., from sub-threshold to strong conduction region. The polynomial approximation of the dependence of EF and ns makes the model simple as it is valid for all regions of device operation. Now, substituting the EF equation in (2.6) and solving for ns, we obtain:

2 2 2 4 2 G1 s 4 4 V(x) K K K V (x) n 2K                  (2.9)
where: VG1 = VGS -VOFF(m) -K1, K4 = K3 + qd/ε(m), and d = dd + ds is the total thickness of the AlGaN layer.

By using the binomial expansion formula, eqn. (2.9) can be expanded and approximated closely as (2.10),

s (x) V(x) n    
(2.10) Where:

G1 G1 4 4 2 V 11 V K K            (2.11) 4 2 4 2 G1 1 1 4 K 1, 1 K K V              
(2.12)

Drain Current Model

The drain current can be expressed as:

D D s q.n .W. I   (2.13)
where W is the channel width and υd represents the drift velocity of electrons in the channel.

The modified velocity-electric field relation has been used in the model and it can be given as,

C C C for E 2E E E 1 d 2 E for E 2 sat E               (2.14)
where E is the channel electric field, µ is electron mobility, EC is critical electric field, υsat is the electron saturation velocity, and EC = υsat/ µ. Substituting (2.10) and (2.14) in (2.13) with E=dV/dx and integrating from source end of the channel (x=0) to drain end (x=L), we have

  V V L 2 2 D D s C 0 V V 1 1 I I .dx Wq n x dV dV 2E       (2.15)
The equivalent circuit of an AlGaN/GaN HEMT is shown in Fig. 2.2 which illustrates the upper and lower limits of integration. It is clear from the figure, the voltage at nodes V2 and V1 are given by V1 = ID RS and V2 = VD -ID RD, respectively.

Applying the limits and ns approximation in (2.15), we have:

    V 2 D D D D S D C V 1 I L Wq V(x) dV V I I R R 2E              (2.16)
Integrating the R.H.S of the above equation and solving for ID, it leads to a quadratic equation as given below:

        2 2 2 D D S D S D S LD D D D D D - I 2 2V V I R R R R R R 2 2 0 V V V R                       (2.17)
where VL = L.EC denotes the channel potential.

Eqn. (2.17) represents the generalized expression for current-voltage characteristics of extrinsic and intrinsic HEMT. The equation is of a quadratic form (ax 2 +bx + c) with:

        2 2 D S D S D S D L D D D D sat a - R R R R b 2 2V V V R R R c 2 Wq V V                            (2.18) Fig. 2.2.
Equivalent circuit of an extrinsic HEMT.

Intrinsic Drain Current Model

For intrinsic HEMT, substituting RD =RS = 0 in eqn. (2.17) gives the general expression for intrinsic HEMT current.

1) Linear Region (VD < VDsat):

The solution of (2.17) for ID in linear region yields (2.19).

Some of the coefficient values are negligible in (2.19) and this lead to linear variation of drain current as a function of applied drain voltage.

2 D D D L D 2 V V I 2V V      (2.19)
2) Saturation Region (VD ≥ VDsat): For saturation region, the channel electrons saturate at a velocity defined by υsat. Then from (2.13), we have

D s sat q (x) W I n   (2.20) Also substituting VD = VDsat in (2.19) gives, 2 Dsat Dsat D L Dsat 2 V V I 2V V      (2.21)
On solving (2.20) and (2.21), we obtain VDsat and IDsat,

L Dsat L 2 V V 2V      (2.22) 2 Dsat L I 2V       (2.23)
where VDsat and IDsat represents the voltage and current in saturation region of intrinsic HEMT operation.

Extrinsic Drain Current Model

In extrinsic HEMT, the voltage drop across the parasitic resistances is considered to be large and no longer can be neglected.

Let VDmin represents the minimum drain voltage required to saturate the HEMT in extrinsic case, considering the drop in parasitic resistances.

1) Linear Region (VD < VDmin):

The solution of (2.17) for extrinsic HEMT in linear region can be given by,

2 D b 4ac b I 2a     (2.24)
where a, b and c are similar to that of the equation given in (2.18).

The solution of the above quadratic equation can be approximated accurately as,

    D D D D S D L D D 2 c V V I b 2 2V V V R R R                    (2.25)

2) Saturation Region (VD ≥ VDmin):

The voltage required to saturate the intrinsic HEMT in extrinsic device operation is denoted by VHsat and is given by,

  Dsat D S Hsat Dmin V VI R R    (2.26)
Substituting the value of ns at V(x) = VHsat from (2.10) in (2.20), we have

  Dsat Hsat V I      (2.27)
Substituting the value of VHsat and solving for IDsat yields,

    D min Dsat D S V I 1 RR             (2.28)
Also we know that from (2.25):

    Dmin Dmin Dsat D S D L Dmin Dmin 2 V V I 2 2V V V R R R                   (2.29)
Solving for VDmin using (2.28) and (2.29), we obtain the following quadratic equation,

      2 2 D S D D min D min L DS L 22 V V V R R R 2 0 V RR                     (2.30)
The solution of quadratic equation becomes,

2 D min B 4AC B V 2A     (2.31) With:     2 D S D L D S L A R R B 2 2 V R C2 V R R                    (2.32)
Therefore, using (2.25), (2.28) and (2.31), the extrinsic HEMT drain current characteristics can be obtained.

Results and Discussions

The analytically calculated sheet carrier density are compared with numerical solution result obtained by simultaneously solving (2.4) and (2.6).

TCAD Sentaurus Simulation Methodology

The simulation tool used for the two-dimensional device simulations is Technology Computer Aided Design (TCAD) Sentaurus from Synopsys Corporation [2.16]. TCAD Sentaurus is capable of simulating a wide range of devices ranging from very deep sub-micron silicon MOSFETS to a large bipolar power transistors. In addition, it is also beneficial for simulating heterostructure devices such as SiC-MESFETs, GaN-MOSFETs and AlGaN/GaN HEMTs. It incorporates advanced physical models and robust numerical methods for simulating the electrical behavior of semiconductor devices. The main scope of the device simulations is to describe the physical process occurring inside the device structure and to understand the underlying physics behind them. This will be more helpful to enhance the performance of the new-generation devices and to improve the next-generation devices. The physical models used in the simulation are required to understand the physical mechanisms occurring in semiconductor devices. In general, the physical models available in the simulation tool are not calibrated [2.14]. Therefore, it is essential to calibrate the simulation models with the physical parameters in order to obtain the reliable prediction of the device characteristics.

In TCAD Sentaurus simulation, the real semiconductor device is represented as a virtual device (2D/3D), with physical properties that are discretized onto a non-uniform mesh of nodes.

Therefore, this virtual device is an approximation of real device. The physical simulation methodology of TCAD Sentaurus is shown in Fig. 2.8. Sentaurus Device Editor (SDE) [2.17] is used to create the structure of the device, including the electrodes, doping and thermodes.

Once the device structure is created, the next step is to mesh it efficiently using Sentaurus mesh [2.18]. The device structure is divided into a number of grid points (nodes). These nodes are the points where the electrical characteristics of the device such as electric field, voltage and currents, etc. will be computed using the numerical simulations. Therefore, the meshing process has a significant influence on the device simulation. Increasing the mesh density in the simulation increases the precision of calculation, however it has a negative impact on the simulation time. It is therefore essential to make a compromise between the precision and simulation time in order to achieve the maximum benefit from physical simulation. For the case of heterostructure devices like GaN HEMT, the channel region is the AlGaN/GaN hetero-junction interface. Therefore, the mesh density must be sufficiently tight around this hetero-junction interface where the large variations in the charge carrier concentrations are observed. Sentaurus device [2.14] tool is used to define the necessary physical models required for the simulation and their associated physical material parameters. It composed of two files, a material file and the command file. The material file provides the physical parameters required for each material defined in the device structure. The command file is used to define the device contacts and the physical models to be used in the simulation. The physical models defined can be global or for the specific region or material used in the simulation. Sentaurus device will simulate the structure and the output can be visualized using either Inspect [2.19] or Svisual [2.20] tools. Tecplot was also used in the past, however it has been replaced by Svisual for visualizing the interior of the device structure under different simulation conditions.

TCAD Physical Models

TCAD Sentaurus offers a large number of physical models to describe the physical behavior of semiconductor devices as accurately as possible to the real device. Such models need to be included in our device simulations in order to obtain some reliable predictions about the real device characteristics. In this section, the various important physical models used in the simulations are described.

Carrier Transport

The semiconductor equations that govern the transport of charge carriers are the Poisson's equation, which is used to solve the electrostatic potential (Ψ) self-consistently with the current continuity equations for electrons and holes and the electron and hole concentrations, n and p, respectively. The Poisson equation is given by [2.21], [2.22],

.     (2.33) Where ε is the electrical permittivity and ρ is the charge density.

The charge density is given by [2.21],

  D A trap q p n N N        (2.34)
With ρtrap = q nt for donor trap and ρtrap = q (nt -NT) for acceptor trap, respectively.

Where q is the electronic charge, n and p are the electron and hole densities, ρtrap, nt and NT, NA and ND are the charge density contributed by traps, number of occupied traps, total number of traps, concentration of acceptors and donors, respectively.

Therefore, Poisson's equation can be written using (2.33) and (2.34),

  D A trap . q p n N N         (2.35)
The time dependent current continuity equations for electrons and holes are given by [2.14]

[2.21], n n n n 1 G R .J t q       (2.36) p p p p 1 G R .J t q       (2.37)
Where Jn and Jp are the electron and hole current densities, Gn and Gp are the electron and hole generation rates due to external excitation, Rn and Rp are the electron and hole recombination rates, respectively.

In a steady state condition, eqn. (2.36) and (2.37) becomes, n p .J .J 0     (2.38) In order to achieve the self-consistent solution of Poisson's equation and the current continuity equation along with electron and hole concentrations, it is necessary to calculate the current densities, Jn and Jp from the electrostatic potential and the charge concentrations, n and p. It can be achieved by using one of the current transport models explained in the following sections.

Drift-Diffusion (DD) Model

The Drift-Diffusion (DD) is the TCAD Sentaurus default model which is based on approximating the semiconductor device equations in a drift-diffusion approximation to the Boltzmann transport equation (BTE). In this model, the carrier flow inside the device is due to the drift and/or diffusion under the presence of externally applied lateral or longitudinal electric field simultaneously with the generation and recombination of charge carriers. The DD model incorporated in TCAD Sentaurus numerically solves Poisson's equation and the current continuity equation self-consistently in order to obtain electron and hole concentrations, and the electrostatic potential at all the mesh nodes defined in the device structure, assuming constant temperature (carrier temperature and the lattice temperature are considered to be in equilibrium), steady state and assuming full ionization of the introduced impurities.

The current density due to the drift of carriers under the influence of applied external electric field can be given by [2.14] [2.21],

  drift n p J q n p E     (2.39)
Where E is the electric field and µn and µp are the electron and hole mobility.

When the charge carriers are distributed unevenly inside the device where they can move freely or due to the force exerted on them by an electric field, the carriers move from the region of higher gradient to the region of lower gradient. This process is called diffusion and the associated current is known as diffusion current. Diffusion current can be either in the same direction or opposite direction of drift current. Therefore, the current density due to the diffusion of charge carriers can be given by [2.14],

  diff n p J q D n D p     (2.40)
Where Dn and Dp are the diffusion coefficients of electrons and holes, respectively.

In the absence of any external applied electric field, the combination of diffusion and drift current inside the semiconductor must be equal to zero.

n n kT D q   (2.42) p p kT D q   (2.43)
Under thermodynamic equilibrium conditions, the Fermi energy level for both electrons and holes are the same. However, for non-equilibrium conditions, it is not valid and therefore, quasi-Fermi levels are assumed for electrons and holes. Therefore, the relation between quasi-Fermi level, electrostatic potential and the carrier concentrations, n and p can be expressed using the following equations [2.21]:

n i kT n ln q n           (2.44) p i kT p ln q n           (2.45)
Where ϕn and ϕp are the respective quasi-Fermi level for electrons and holes.

Therefore, by substituting the Einstein's relationship into the drift and diffusion current equations and using the quasi-Fermi levels definition, the total current density due to the summation of drift and diffusion current density can be given by,

n n n J nq     (2.46) p p p J pq     (2.47)

Thermodynamic Model

The thermodynamic model (TD) is an extension of the DD model to include the self-heating effects in the device by solving the lattice heat flow equation [2.23] in addition current continuity equations and thereby estimating the impact of the temperature gradient on the current densities, assuming a single temperature for electrons, holes and the lattice of the device. This model is very useful for simulating the hetero-structure devices such as GaN HEMTs where the large amount of heat generated inside the device, due to the applied biasing conditions and therefore, analyzing the impact of this generated heat on the charge carriers is critically important. The current density equations involving the temperature gradient can be expressed as [2.14], [2.22],

  n n n n J nq P T       (2.48)   p p p p J pq P T       (2.49)
Where T is the lattice temperature and Pn and Pp represents the thermal power generated inside the device.

Hydrodynamic Model

Hydrodynamic (HD) models utilize a different approach to calculate the charge carrier transport in the semiconductor devices. HD describes carrier transport based on energy balance equations to describe the non-equilibrium conditions and the energy of each type of carrier is estimated based on its own temperature conditions, and assuming a different lattice temperature [2.24].

HD model solves, self-consistently, Poisson's equation and the continuity equation along with energy balance equations for electrons, holes and the lattice. HD model is more accurate than DD model, since DD model is incapable of reproducing the velocity overshoot effects, often observed in III-V semiconductor devices [2.25], [2.26], with sub-micron gate lengths. This is because the effect of hot electrons [2.27] is not taken into account while solving for electron and hole current densities. Moreover, it often overestimates the effect of impact ionization. Therefore, for sub-micron devices and with short gate lengths, DD model shows some discrepancies and the HD model may be more appropriate. However, the HD model is rather complex and it requires more computational effort. It often faces convergence issues and the simulation time is also often long compared to the DD model.

Density Gradient Method

The modern semiconductor devices such as MOSFET and GaN HEMTs have their channel lengths and oxide thickness are in quantum-mechanical scale lengths. Therefore, the wave nature of charge carriers can no longer be neglected. Moreover, in the case of AlGaN/GaN HEMT devices, the bandgap discontinuity at the hetero-junction interface forms a triangular quantum well (2DEG channel region) for the high electron mobility electrons to confine. This results in the quantization of energy levels inside the 2DEG channel. Therefore, it is essential to include the quantization model in the simulation to accurately predict the electron distribution in the channel. Unfortunately, the Schrodinger equation solver used for quantization in TCAD Sentaurus is only available for 1D simulation [2.14]. However, TCAD offers another model, density gradient method, to include the quantization effects in the simulation [2.22]. This model considers the distribution of conduction and valance band energies as discrete-like energy levels which can be used as quantization. The quantization effects are included by incorporating an additional quantization term (Ʌn) in the carrier concentration and the respective equations used in the density gradient method are expressed as [2.22]:

F,n c n c 1/2 n E E n N .F kT           (2.50) 2 2 n n h n 6m n     (2.51)
Where Ʌn is the additional term used for the density gradient method, γ is the fitting factor, and Tn is the electron temperature and mn is the effective mass of an electron.

The density gradient simulation is quite long compared to DD model, since it needs an additional iterative step to compute the density gradient solution.

Generation-Recombination Process

Generation-recombination (G-R) processes are the processes by which electron-hole pairs are created by exciting an electron from the valence band of the semiconductor material to the conduction band and thereby, creating a hole in the valence band. Both carriers eventually disappear in this process. The energy difference between the initial and final state of the electron leads to different possible classification of the recombination process. In the case of radiative recombination process, the energy is released in the form of a photon whereas for non-radiative recombination, the energy is passed on to one or more phonons. There are some standard TCAD models available to describe the Generation-recombination process and are explained in the following section.

SRH-Recombination Model

The SRH model [2.28] describes the recombination process of electrons and holes in semiconductors occurring through the process of trapping. SRH or Trap-assisted recombination refer to the process where an electron falls into a trap, the trap gets filled and it cannot accept further electron. The electron occupying the trap moves into an empty valence band to release the captured electron thereby completing the recombination process. Therefore, this process follows two-step transition, an electron from the conduction band reaches the trap state and then to the valence band. These traps existing in the semiconductor device are due to the presence of impurities or the defects created during the crystal growth. The net recombination rate for trap-assisted recombination process is given by [2.28]:

    2 SRH i,eff net p 1 n 1 np n R n n p p        (2.52)
Using Fermi statistics, the SRH recombination rate can be modified to [2.28]:

    2 n p i,eff SRH net p n 1 n p 1 np n R n n p p            (2.53)
Where ni,eff is the effective intrinsic carrier concentration and τn and τp are the electron and hole lifetimes, respectively.

with

, c F,n n C EE n exp N kT         (2.54) F,p v p V E E p exp N kT         (2.55) F,n c C 1/2 E E n N F exp kT         (2.56) v F,p V 1/2 E E p N F exp kT         (2.57) T C 1 C 1 2 EE n N F exp kT         (2.58) V T 1 V 1 2 EE p N F exp kT         (2.59)
Where NC and NV are the effective density of states for electrons and holes, F1/2 is the Fermi-Dirac integral of order ½, EC and EV are the conduction and valence band energy levels, ET is the trap energy level and EF,n and EF,p are the quasi Fermi energy levels for electrons and holes, respectively.

Auger Recombination Model

Auger recombination is a process in which an electron and hole recombine in a band-band transition. The resulting energy arise from this process is given to another electron or hole and therefore, the involvement of third particle affects the recombination rate. The corresponding rate of band-to-band Auger recombination rate is given by [2.14]:

   A 2 net n p i,eff R C n C p np n    (2.60)
Where Cn and Cp are Auger coefficients.

The temperature dependent Auger coefficients can be expressed by [2.14]:

  2 n A,n A,n A,n n 0 0 0,n T T n C T A B C 1 H exp T T N                                 (2.61)   2 p A,p A,p A,p p 0 0 0,p T T p C T A B C 1 H exp T T N                                 (2.62)
Where T0 = 300K (room-temperature).

2DEG Formation-Surface Donors

In case of a non-ideal surface i.

  D C CR pol E E d q.      (2.64)
where ε is the dielectric constant of the AlGaN and ΔEC is the conduction band offset between AlGaN and the GaN material.

The 2DEG density as a function of AlGaN barrier thickness for d > dCR can be given by [2.30]:

  pol CR s 1d q.n d    (2.65)
The 2DEG sheet density increases rapidly for d > dCR and with further increase in AlGaN barrier thickness (d » dCR), the 2DEG density gradually approaches σpol/q, since the electric field in the AlGaN barrier approaches zero for d » dCR [2.30]. In other words, as the thickness of AlGaN barrier thickness increases (d > dCR), all the electrons from the surface states have already moved to the AlGaN/GaN hetero-junction interface and at a certain value of dCR, the 2DEG density saturates approximately equals to surface trap density.

TCAD Simulation: 2DEG Formation -Ideal Surface

In order to understand the principle of formation of the 2DEG in an AlGaN/GaN HEMT heterostructure, two-dimensional (2D) TCAD physical simulations have been performed. The conventional AlGaN/GaN structure used in the simulation are shown in Fig. 2.12 (a). The gate length (LG) and width (WG) of the device are 0.25 and 600 µm, respectively. The polarization charges defined in the physical simulator at each material interface is shown in Fig. 2.12 (b).

The Al mole fraction (m) of the AlGaN material is assumed to be 20%. The value of σ1 is set to

TCAD Simulation: 2DEG Formation -Surface Donors

The TCAD simulations have been performed by including the donor-like traps at the surface by using the same structure as shown in Fig. 2.14 (a). The polarization charges defined in the simulation is shown in Fig. 2.17 [3.7] and optimizing the AlGaN barrier thickness [3.6]. Also, in order to eliminate short-channel effects in nano-scale devices, it is necessary to render the GaN buffer semi-insulating by either using intrinsic defects or extrinsic deep-level dopants such as iron (Fe) or Carbon (C) [3.8] [3.9]. These deep level dopants are used to confine the charge carriers in the channel [3.9] and also they suppress buffer leakage, punch-through and other short-channel effects [3.9]. All these technological improvements have enabled GaN HEMT technology to act as a disruptive technology for high-power microwave and mm-wave applications [3.10]. Therefore, GaN HEMT device is capable of delivering high breakdown voltage, high switching speed and low on-resistance (RON), which makes it ideal for power switching applications [3.11].

Although GaN HEMT devices have demonstrated their superior performance [3.3], [3.6], the presence of deep levels in the structure degrades the dynamic device performance [3.12]. Indeed, the density of two-dimensional electron gas (2DEG) at the heterostructure interface is altered due to the capture of electrons by the deep traps either present at the surface, or barrier or buffer layer [3.12] . Moreover, these traps are slow in nature and thus undermine the device reliability [3.13], [3.14]. Several types of trapping effects have been reported in the literature [3.11]- [3.13]. However, the origin and properties of these traps remain unclear. Trapping effects cause current collapsea recoverable reduction in drain current after the application of high biasing voltage, transconductance-frequency dispersion, gate lag, drain lag, and restricted microwave output power [3.11]. Several studies have also demonstrated that the presence of an Fe-doped GaN buffer causes an enhancement in the current collapse mechanism [3.15] and thereby the device deviates from expected microwave performance. Therefore, the analysis of This chapter investigates the trapping effects in the GaN HEMT devices using low frequency measurements and TCAD-based physical device simulations. The chapter is divided into three sections. In the first section, we describe the experimental methodology used for characterizing the GaN buffer traps and also discusses the extraction of trap parameters from LF S-parameters measurements. Furthermore, we also present the TCAD physics based simulation results to validate our measurement technique. In the second section, characterization of GaN buffer traps using LF noise measurements and simulation studies have been explained. In the final section, we attempt to investigate the influence of trapping effects such as gate and drain-lag on the simulated I-V characteristics using transient simulations.

Traps

Traps are generally created due to material defects, dislocations formed during the crystal growth, lattice mismatch between two materials, the difference in thermal expansion coefficients between substrate and the epilayers, the presence of impurities in the crystal lattice and the existence of dangling bonds on the surface of the crystal structure [3.19]- [3.21]. These defects and dislocations can acts as the potential charge carrier traps and creates a localized trap levels inside the bandgap of the material. The majority of the trapping mechanisms would result in similar effect of degradation on the device characteristics, especially at high frequencies.

However, the characteristics time of the emission process in GaN HEMTs can range from a few nanoseconds to several seconds [3.21]. As a consequence, the trapping mechanisms could limit the device performance even at low frequencies. Moreover, these trapping effects could contribute significantly to the low-frequency noise [3.21]. It is also important to note that the different fabrication process technique results in inducing various trapping centers. Therefore, it is essential to understand the phenomenology of these traps, their physical location and the mechanisms involved, in order to optimize the future performance of GaN HEMT device technology.

Traps can be classified into two types: donor-like and acceptor-like traps. A donor-like traps is considered to be positive if empty and neutral if filled with an electron, whereas an acceptorlike traps is neutral if empty and negative, if occupied. A trap can be defined by its energy level inside the bandgap, which is associated with the following parameters:

The probability of trap occupation under equilibrium conditions is given by the Fermi function [3.23]:

t,eq T Fo 1 f E E 1e kT          (3.1)
Similarly, the probability of trap occupation under non-equilibrium conditions can be given using the quasi-trap Fermi level [3.23]:

  t,non eq T FT x,y,z 1 f E E 1e kT           (3.2)
Where EF is the Fermi energy level, k is the Boltzmann constant (eVT -1 ) and T is the temperature

(K).
The trap can be defined by using the electron (σn) and hole (σp) cross section parameters, respectively. The relationship between the trap cross section and electron (hole) capture probability coefficient (cn, cp) can be given by [3.23]:

n n thn c    (3.3) p p thp c    (3.4)
Moreover, the electron (hole) emission probability can be related to the electron (hole) capture probability coefficient (en, ep) by the following equations [3.23]:

T C n n C 1/2 EE e c N F kT         (3.5) V T p p V 1/2 EE e c N F kT         (3.6)
Where NC, NV are the effective density of states for electron and holes, EC, EV are the conduction and valence band energies and F1/2 is the Fermi function of order ½. Where NT is the total number of traps and nT represent the number of occupied traps. Therefore, the generation-recombination rate can be given by [3.23],

    t t t n n p p n f U N R G R G t t           (3.13)     t t n. t p t n t p t n N c n. 1 f e . 1 f e .f c .p.f t             (3.14)
In steady state conditions, the occupation probability of generation-recombination centers can be given by: Therefore, the electron emission rate (τn) of traps can be obtained by solving the above equations:

2 a n n n 1 E e .A.T exp kT            (3.16)
Where τn represents the electron emission time constant and A is a constant and its corresponding equation is given in (3.17).

With:

  3/2 2 * c 3 2.M . 3 2 k m A h   (3.17)
The capture rate is proportional to the number of electrons in the conduction band, whereas the emission rate has a strong dependence on temperature. This suggests that emission time constant is of several magnitude longer than the capture time constant. In order to obtain the physical properties such as activation energy and the cross section of traps present in the device structure, it is essential to plot the Arrhenius characteristics of traps using any of the measurement technique described in the section 3.1.

Experimental Characterization

Device Structure

The GaN/AlGaN/GaN HEMTs were grown by metal-organic chemical vapor deposition (MOCVD) on a SiC substrate. The epilayers consist of 1.7-µm thick GaN buffer layer, 22-nm thick AlGaN barrier layer, with Al (m) = 25% followed by a few nm thin GaN cap layer and a 50-nm Si3N4 passivation layer. The fabricated devices have a gate length (LG) of 0.25-µm and widths, WG of 450 and 600-µm (fingers, n= 6 and 8), whereas the nominal gate-source (LSG) and gate-drain (LGD) spacings are 0.8 and 2.7-µm, respectively. A field-plate is placed from the middle of the gate electrode and extends a distance LFP (field-plate length) of 1-µm towards the drain electrode. Iron (Fe) doping are incorporated in the GaN buffer region of the device.

Pulsed I-V Characterization

The schematic of the pulsed I-V measurement setup used for GaN HEMT characterization is shown in Fig. 3.2 (a). The AMCAD BILT pulsed I-V system consists of power supplies, pulse generators, input/output measurement units, gate and drain probe heads. The gate and drain probe heads are used to provide short pulses, down to 200 ns. Moreover, it is also used to improve the pulse shape even in the case of drastic variation of drain current. The internal impedances of these I-V probe heads are low (gate -10 Ω and drain -0.5 Ω) compared to the conventional high-power pulse pattern generators. The measurement test bench is equipped with a thermal chuck which allows the measurement of I-V for different temperature ranging from -65ºC to 200 ºC. The principle of pulsed I-V measurement is illustrated in Fig 3 .2 (b). In general, the measurement are performed under quasi isothermal condition. The gate and drain are pulsed from the initial quiescent bias point (VGSQ, VDSQ) to the measurement bias point (VGSM, VDSM). In order to minimize the influence of self-heating effects on the pulsed I-V measurement, the pulse width for both drain and gate are selected as small as possible.

However, the pulse period must be longer than the pulse width. This ensures that the device would return to its steady state conditions. The pulsed IF carried out on the GaN/AlGaN/GaN HEMT grown on SiC substrate. The gate and drain terminals are terminals of the device pulsed at VGSQ, VDSQ = (0 V, 0 V) and the pulse period is set to 900 µs (0.1 % duty cycle).

Low Frequency Characterization

The measurement setup used for measuring the LF S-parameters of the device is shown in Fig. In the traditional small signal equivalent circuit of the device, the effect of trapping mechanism on the frequency dispersion of output admittance and transconductance can be modeled by using an additional parasitic RC network [3.25] as shown in Fig. 3.6. At low frequencies, the output transconductance and output admittance can be represented by using the following equations [3.25]:

          2 mn n mn n 21 m 2 2 n n g g Y g j 1 1                   (3.18)             2 mn n n mn n n 22 d 2 2 n n g g g g Y g j 1 1                     (3.19) with n n n c g  
Where τn represents the emission time constant associated with the trapping mechanism.

The time constant (τn) can be extracted using the frequencies fRinf and fIpeak that corresponds to the inflexion points and peak value of the real and imaginary part of Y22 parameter, respectively.

The corresponding equations can be derived using eqns. (3.18) and (3.19) and are expressed by [3.27]

: 22 R inf Real[Y ] n 1 f f 23    (3.20) 22 I,peak Imag[Y ] n 1 f f 2    (3.21)
Indeed, it is important to note that the number of inflexion points or the number of peaks observed in the measured real and imaginary part of Y22 parameter signifies the number of traps present in the device, unless the emission time constants of traps are close to each other. The capture time constant of traps is much smaller than the emission time constant and hence, it can be neglected at low frequencies. However, as the temperature increases, the electron emission rate increases, hence the emission time constant decreases which causes the peak value of Y22 parameter shift towards higher frequencies. Therefore, the activation energy (Ea) and cross section (σn) of the traps can be determined using the Arrhenius equation given below [3.27]:

a n n n 2 E e .A exp T g k.T          (3.22) with C th n 2 N .V A T  and n n 1 e  
where en is the trap emission rate, T is the temperature, σn is the capture cross section of traps, NC is the effective density of states of electrons in the conduction band, Vth is the thermal velocity of electrons, g is the degeneracy factor (g =1), Ea is the trap activation energy and k is the Boltzmann constant.

Experimental Results

The Extracted Arrhenius plot using Y22-parameter.

Literature Review on Traps Location and its Activation Energy

In order to understand the physical origin and location of the traps extracted using LF measurements, a comprehensive analysis of the traps characteristics reported in the literature for GaN devices have been reviewed. The majority of the research groups utilizes different characterization techniques to identify the traps existing in the device. However, these measurement techniques provide only qualitative description of trapping mechanism and often lead to conflicting explanations of the physical location of the traps. Therefore, it can be concluded that complete understanding of trapping mechanism and their physical location in the device structure is still under investigation. Table 3.1 shows the summary of the traps characteristics reported in the literature for Fe-doped GaN devices. The summary of the traps characteristics identified for various GaN-devices have been listed in Appendix I.

Trapping Investigation using TCAD Physical Simulations

Introduction

Physics based simulations offer an efficient way for analyzing the experimental device characteristics. However, in order to make the 2D simulations physically more meaningful, it is essential to calibrate the TCAD physical models used in the simulation to reproduce the experimentally measured characteristics. Moreover, the calibration process is not relatively straightforward. The parameters of interest for the calibration are the polarization charges defined at the hetero-junction interface, surface donors, interface charge, mobility and saturation velocity of the GaN material, Schottky work function of the gate metal and contact resistances of source and drain contacts respectively. Some of these parameters can be independently measured or the parameter values can be taken from the literature. The polarization charges defined at the hetero-junction interface can be computed using the eqns.

(2.1) -(2.3) as explained in Chapter 2. The interface charge is used as a fitting parameter and moreover, this interface charge is compensated by the donors-like traps introduced at the surface of the device. Furthermore, it is important to note that the simulation performed with these reported or calculated values could not reproduce the experimentally measured characteristics of our device. Hence, these values can be considered as the reference values for our calibration process. Moreover, each of these parameters has a distinct impact on different regions of the measured I-V characteristics.

The calibration process can be divided into several regions. The initial calibration is performed by adjusting the Schottky gate work function in order to fit the pinch-off voltage in simulation to experimentally measured characteristics. Then, by varying the low field mobility and saturation velocity, the linear and saturation region drain current characteristics are calibrated.

Moreover, the AlGaN/GaN HEMT devices are used mainly for high power and high voltage applications due to their excellent high electron drift velocity and large bandgap. This drift velocity would be the limiting factor for device operation under high electric field conditions.

Under high electric fields, the carrier velocity is no longer proportional to the electric field strength, but saturates to a finite value. In order to account for the velocity saturation in the simulation, the most commonly used Caughey Thomas field dependent mobility model is used.

The relation between the velocity, mobility and the electric field can be expressed by [3.39]

, low n,p low sat 1/ .E 1 V                      (3.23)
Where Vsat represents the saturation velocity, µlow is the low-field mobility, µn,p denotes the mobility of electrons/holes, respectively and β is the fitting parameter (i.e., 2.9 for electrons in GaN) that controls the smooth transition between the linear and saturation region of the dependence of velocity on the electric field.

The velocity as a function of electric field can be expressed by using the following relation: The temperature-dependent carrier mobility values are calibrated using a generic model [3.40],

      n,p low 0 0 , T T T T          (3.25)
Where T0 is 298 K, α and γ are the temperature dependent fitting parameters for electrons (2.3) and holes (2.1), respectively for the GaN material.

Calibration of GaN/AlGaN/GaN HEMT

Fig. 3.9 (a) shows the cross section of the structure used for physical simulations. The nominal thickness of all layers detailed in device structure section are used in the simulation except for the case of SiC substrate. The SiC substrate thickness is assumed to be 3 µm, in order to speed up the simulation time. Moreover, it is determined in the simulation, that any further increase in thickness of the SiC substrate after 3 µm will have no significant effect on the simulated DC characteristics. The electric field induced due to the piezoelectric and spontaneous polarization contributes to the formation of 2DEG sheet density at the AlGaN/GaN hetero-junction interface, even without the requirements for any intentional barrier doping [3.41]. In the absence of externally applied fields, the polarization charges induced are of course, equal in magnitude and opposite in sign to maintain the overall charge neutrality of the device. The theoretical method used for the calculation of polarization charges has been described in Chapter 2. Fig.

(b) shows the polarization charges defined at each material interface in the physical

simulator. The values of σ1 and σ2 are ± 1.23× 10 13 cm -2 and -2.0× 10 12 cm -2 , respectively.

According to surface donor theory [3.42], the surface donors are responsible for the formation of 2DEG sheet density in GaN HEMT devices. Hence, surface donors (σD + ) with a density of 1.0× 10 13 cm -2 and a specified energy level of 0.2 eV below the conduction band are introduced at the GaN-cap/SiN interface. Electron (σn) and hole (σp) capture cross sections are assumed to be 1.0× 10 -18 and 1.0× 10 -20 cm 2 , respectively. Fe-doping (p-type) are introduced uniformly in the GaN buffer with a uniform concentration (Nbuffer) of 3.0× 10 16 cm -3 .

. In addition, we consider acceptor-like traps in the GaN buffer whose trap energy is placed at 0.4 eV below the conduction band and the assumed trap concentration (NTA) is 5.0× 10 16 cm -3 .

Electron (σn) and hole (σp) capture cross sections of GaN buffer traps are assumed to be 3.2× 10 -18 and 1.0× 10 -20 cm 2 , respectively. For the simulation, constant mobility and field dependent mobility models are included for electrons and holes and Shockley-Read-Hall recombination model is used for carrier generation and recombination. gives the best match with experimental results. The calibrated TCAD simulation model is used to simulate the I-V characteristics of 6×75 µm device and obtained simulation results are compared with the measured pulsed I-V characteristics (Fig. 3.12). Good agreement is achieved between the measurement and simulation results, this confirms that calibrated simulation model is also valid for the 6×75 µm device. (c) Extracted Arrhenius plot using simulated Y22-parameter.

Calibration Results

Acceptor-like traps are placed at 0.6 eV below the conduction band whereas donor-like traps are placed at 0.3 eV below the conduction band. Electron and hole cross sections for both these traps are assumed to be σn = 3.2× 10 -18 and σp = 1.0× 10 -20 cm 2 and the assumed trap concentration (NT) is 1.0× 10 16 cm -3 , respectively. The traps introduced in the AlGaN barrier does not cause any frequency dispersion in the simulated Y22 parameter. Moreover, when the traps are introduced in both the AlGaN barrier (both acceptor and donor-like traps) and GaN buffer (ETA = 0.4 eV, NT = 5.0× 10 16 cm -3 , σn = 3.2 × 10 -18 and σp = 1.0× 10 -20 cm 2 ), dispersion occurs in the simulated admittance parameter (Fig. 3.16 (b)) and the activation energy value extracted from the Arrhenius plot (Fig. 3.16 (c)) corresponds to the trap energy level value used in the GaN buffer. This result demonstrates that if the traps are present in the AlGaN barrier, low-frequency admittance measurements could not be useful for detecting the traps. However, traps in the AlGaN barrier can be identified via different measurement techniques such as gate lag transients which will be confirmed with the aid of physical simulations in section 3.9.

Influence of Donor Traps on the Simulated Y22 Parameter

In order to understand the influence of donor traps on the Y22 parameter, donor-like traps are introduced in the GaN buffer, whose concentration is NT = 1.0× 10 16 cm -3 and the trap energy level is placed at 0.4 eV below the conduction band. The electron and hole cross sections are assumed to be σn = 1.0× 10 -15 and σp = 1.0× 10 -20 cm 2 , respectively. Fig. 3.17 shows the simulated Y22 parameter for varying temperature ranges between 25 o C and 125 o C and for the gate and drain bias conditions of VGS = -1 V and VDS = 20 V, respectively. For the donor-like traps, the simulated Y22 parameter does not show the frequency shift as the temperature increases, instead the peak amplitude increases with temperature. This kind of similar behavior has been observed in our LF measurement of AlN/GaN HEMT device. Fig. 3.18 shows the measured Y22 parameter of 4×50 µm AlN/GaN HEMT device for varying temperatures ranging between 25 o C and 125 o C, illustrating the existence of both acceptor-like and donor-like traps. It can be seen that donor-like traps effects are visible only at higher frequencies and therefore, the thermal effects may not significantly influence the measured characteristics. This could explain the reason for no frequency shift observed for donor traps. From the simulations, if the donor-like traps are present in the device, the measured imaginary part of Y22 parameter will cause the peak amplitude increase whereas the existence of acceptor-like traps will cause the peak value of Y22 parameter shift towards higher frequencies as the temperature increases. This is the first time such an effective way of identifying the type of traps, either acceptor or donor-like traps, using the measured LF admittance parameter, has been reported.

Trapping Investigation using LF Noise Measurements

Introduction

The term "noise" is often related with an unwanted or undesirable random signal that must be reduced as much as possible. This undesired noise component could limit the performance of devices. Therefore, it is of significant importance to understand the origin of these noise sources in order to reduce their level and to improve the performance of the device. Moreover, the origin of these noise sources are often strongly related with the basic physical mechanisms governing the device operation. Therefore, the study of noise characteristics can provide valuable information about the different physical process occurring in the device. Among various origins of noise sources, some are unavoidable and irreducible noise such as thermal noise, shot noise, and the diffusion noise. However, the low frequency (LF) generation-recombination (GR) noise and 1/f noise of the semiconductor component is a reducible noise [3.44]. Low frequency noise (LFN) characterization is known be to an extremely powerful tool for determining the quality of the device process and studying the device reliability [3.16]. Moreover, it is also useful for identifying the traps existing in the device. The LFN characterization also helps to improve the technological process by tuning the physical parameters of the device such as layer thickness, doping levels, etc., to minimize the noise levels [3.16]. It also helps to model the electrical behavior of the noise sources, which predict the optimal noise characteristics such as phase noise of the oscillator circuits.

The background of noise sources found in semiconductor devices is explained in the next section.

Low Frequency Noise Sources

Irreducible Noise Sources

These noise sources contribute to the lower limit of noise level in the semiconductor materials or devices and therefore, they cannot be reduced.

Diffusion and Thermal Noise:

The diffusion noise is related to the diffusion process that results from non-uniform distribution of charge carriers inside the semiconductor material. The physical origin is the fluctuations in the carrier velocity caused by collisions. Moreover, during the diffusion process, the electrons are scattered via collisions with other ionized impurity atoms or with the lattice. These scattering process are completely random and hence the associated instantaneous value of the diffusion current is also random. The noise spectrum of the diffusion noise is relatively flat.

In contrast to diffusion noise, thermal noise is related to the thermal random motion of charge carriers in the semiconductor material. The statistical nature of the scattering of free charge carriers causes random changes in their average carrier velocities and this contributes to random microscopic diffusion currents. Under equilibrium conditions, the charge carrier motion has an average energy of ½ kT.

Under low electric field, the diffusion noise is equivalent to the thermal noise as long as the mobility obeys the following Einstein's relation [3.45]:

n n D kT q   (3.26)
Where Dn and µn are the diffusion constant and mobility of the charge carriers under low electric field condition. Under these conditions, the power spectral density of diffusion noise is same as that of thermal noise (eqn. 3.33).

Diffusion noise is the more generalized noise process than thermal noise. However, if Einstein's relation holds, diffusion noise becomes thermal noise. The noise power spectral densities can be expressed using [3.45]:

I 4kT S R  (3.27) V S 4kTR  (3.28)
Where k is the Boltzmann's constant and Δf is the bandwidth in Hertz.

These noise sources are independent of operating frequency and hence, they are also called as white noise sources.

Shot Noise:

The charge carriers in the semiconductor material or device often flows across a potential barriers. For example, the random motion of electrons or holes in a PN-junction diode or electrons drifting across a potential barrier. These charge carriers cause the fluctuations in current and the corresponding power spectral density of shot noise can be represented using Where q is the electronic charge and I represents the current flowing across the potential barrier.

Shot noise is independent of frequency (white noise) and increases proportionally with the current flowing across the potential barrier.

Reducible Noise Sources

These noises can be reduced by improving the technological process i.e. by reducing the defects or improving the quality of materials.

1/f Noise:

The 1/f noise is also called flicker noise [3.45], [3.46], refers to the spectrum that shows a noise power spectral density inversely proportional to frequency (1/f γ ). When γ = 1, the noise is strictly called 1/f noise. This noise source has been found in different types of materials and systems including semiconductor materials and devices, fluid dynamics and optical systems.

Interestingly, this type of noise was identified very early, however the origin of this 1/f noise is still under investigation. The 1/f noise could be originated due to material and device microscopic degrees of freedom interacting with quantum variables of nano-devices. It could be related to the fluctuations in the conductivity of the material. Moreover, the conductivity of the material depends on both the mobility and the number of free charge carriers, there are two theoretical approaches to describe the 1/f noise: the McWhorter [3.44] and (number fluctuation model) Hooge [3.46] models (mobility fluctuation model).

Generation-Recombination (GR) noise:

Generation-recombination noise arises due to the existence of traps that randomly capture and emit carriers acting as generation-recombination centers [3.44] For a two-terminal semiconductor sample, the noise power spectral density arising from GR noise can be expressed by [3.44],

  2 V N R 2 2 2 2 2 N S S S 4 R V N N 1        (3.31)
Where R is the resistance of the sample, V is the applied bias voltage, SR, SV and SN are the power spectral densities of resistance, voltage and number of carriers, respectively. This type of spectrum is called Lorentzian noise spectrum. If there are only one trap located in the bandgap of the semiconductor, then the variance can be given by [3.44],

2 n p 1 1 1 1 N X X N     (3.32)
Where Xn is the average number of traps occupied states and Xp is the average number of empty traps. Thus, the variance approximates the smallest of the quantities N, Xn and Xp.

Low Frequency Noise Characterization Setup

The LF noise of the semiconductor devices can be carried out as equivalent input voltage and current noise sources or in terms of input gate short-circuit current and output drain short-circuit current noise sources as shown in Fig. 3.19. The transistor is modeled as a noiseless transistor with noise current sources at both the ports and their corresponding input and output noise spectral densities are denoted as SIin and SIout, respectively. In order to measure the noise current sources, different setups have been proposed in the literature [3.47]. It is based on either connecting the voltage amplifiers (VAs) or transimpedance amplifiers (TAs) at the transistor terminals and by accounting for the input and output impedances and biasing conditions. Figure 3.20 shows the simplified schematic of two available setups [3.47] to measure the LF noise of the semiconductor devices.

V _ meas i i 2 ati S Z Z e i S S 2 R S S Z Z Z Z                (3.33)
Where Z=Zeq/R, eati, iati and Zati are the voltage, current noise sources and impedances of the voltage amplifier. SV_meas and Sir are the measured noise voltage spectral density and the thermal noise spectral density associated with the bias resistor R, respectively.

Low Frequency Noise Measurement Results

The low-frequency noise measurements of 6×75 µm GaN/AlGaN/GaN HEMT on SiC substrate When the temperature increases the peak value of the Lorentzian spectrum shifts toward higher frequencies due to the thermal dependent behavior of GR noise. This allows the extraction of the cut-off frequency for each measurement temperature associated with the GR noise in the device. Thus, the activation energy (Ea) and cross section (σn) of these trap levels can be obtained using the Arrhenius equation.

Intepretation Based on Physical TCAD Simulations

In order to identify the physical location of these traps in the device structure, two-dimensional physical simulations have been performed using the schematic structure shown in Fig. 3.9. The polarization charges defined in section 3.6.2 have been used in noise simulations. Two traps are introduced in the GaN buffer which is close to the GaN channel region. It can be seen from the The thickness of the first two sections are 0.211-µm each, and the third section is 1.275-µm, respectively. In the first section, acceptor-like traps with a density of 5.0× 10 16 cm -3 , having an energy level of 0.51 eV (T2) below the conduction band are introduced. Electron and hole capture cross sections of traps are assumed to be 5.0× 10 -16 and 1.0× 10 -20 cm 2 , respectively. In the second section of GaN buffer, acceptor-like traps having a concentration of 5.0× 10 16 cm -3 and at the specified energy level of 0.57 eV (T1) below the conduction band are defined.

Electron and hole capture cross sections of traps are assumed to be 2.0× 10 -16 and 1.0× 10 -20 cm 2 , respectively.

Intepretation Based on TCAD Physical Simulations

Two-dimensional physical simulations have been carried out by using the schematic structure shown in Fig. 3.9 (a). The polarization charges described in section 3.6.2 have been used in our simulations. Moreover, the surface donors are introduced at the GaN cap layer/SiN interface in order to form the 2DEG in the GaN channel. Donor-like traps with a density of 1.0× 10 13 cm -2 , having an energy level of 0.2 eV below the conduction band are used. In addition, acceptorlike traps, having an energy levels of 0.51 and 0.57 eV are introduced in the GaN buffer and the assumed density of both traps is 5.0× 10 16 cm -3 , respectively. Electron and hole capture cross sections of both these traps are assumed to be 5.0× 10 -16 and 1.0× 10 -20 cm 2 , respectively.

In the AlGaN barrier region, acceptor-like traps, having a concentration of 5.0× 10 16 cm -3 and at the specified energy level of 0.5 eV are introduced. Electron and hole capture cross sections of barrier traps are assumed to be 1.0× 10 -18 and 1.0× 10 -20 cm 2 , respectively. This demonstrates that if the traps exist in the AlGaN barrier and if the drain voltage is pulsed from one bias to another (drain-lag measurement), it may not affect the measurement characteristics. However, if the gate voltage is pulsed, it will have significant influence on the transient characteristics (section 3.9). Therefore, the transient behavior observed in measurement can be reproduced by simulations providing that donor-like and acceptor-like traps are placed at the surface and in the GaN buffer. Hence, the traps are either located in the GaN buffer or at the surface. In order to further identify the location of the traps in the device, the surface traps have been replaced with an equivalent fixed charge, whose concentration is assumed to be 0.8× 10 13 cm -2 , respectively. This particular value is assumed because, this does not affect the calibrated TCAD simulation model and reproduces the experimentally measured I-V characteristics.

Gate -Lag TCAD Simulation Study

In the section 3.6.5, traps in the AlGaN barrier cannot be identified using low-frequency admittance measurements. However, they can be identified using gate-lag transient measurement. In this section, the impact of AlGaN barrier traps on the transient drain current characteristics have been investigated using TCAD physical simulations. Moreover, the deeper the energy level of acceptor-like traps, greater the possibility of ionization of acceptors and the longer the time required to reach the steady state drain current. The donorlike traps have less influence (verified using several simulations) on the simulated transient characteristics as they are located far away from the channel. This result suggests that traps in the AlGaN barrier can be identified using gate-lag measurements.

Summary

In this chapter, the activation energy and cross section of the traps present in the GaN buffer of the GaN/AlGaN/GaN HEMT device has been extracted using LF S-parameter and noise measurements. Moreover, the TCAD physical simulation results of the device have been presented. The TCAD physical models and calibration procedure have been described in detail.

Using the calibrated TCAD device model, LF admittance simulations have been performed.

Good agreement has been achieved between the simulated and measured Y22 parameter. This strongly suggests that LF admittance measurement is an effective tool for characterizing GaN buffer traps. Similarly, using the noise simulation results, it has been confirmed that traps exist in the GaN buffer of the device. Good agreement has been achieved between the simulated and measured output drain noise spectral density for device temperatures between 25ºC and 100ºC.

The simulation results demonstrate that LF noise measurement is an effective tool for identifying the traps present in the GaN buffer. Time-domain drain lag measurements have been carried out using the DCTS measurement technique. Traps in the GaN buffer cause the shortterm reduction in drain current when the drain bias is varied, and as the time increases, the drain current recovers slowly to the steady state drain current. The TCAD simulation results reveal that traps in the GaN buffer are responsible for this observed drain-lag phenomenon. The simulation results also reveal that traps in the AlGaN barrier cannot be identified using LF measurements. It could be possible through gate-lag measurements. Therefore, the simulation results presented in this chapter establish a correlation with measurements in order to identify the location of traps in devices and this could provide an efficient feedback mechanism for improving the GaN HEMT technology and thereby its RF performances.

Acknowledgement

The The limitations of conventional semiconductors for RF and microwave power applications have paved the way for wide-band gap group III -V materials such as GaN, SiC etc. Among these, GaN material receives much attention due to its superior material properties [4.1] such as high electron mobility, high saturation velocity and high breakdown electric field. AlGaN/GaN High Electron Mobility Transistors (HEMTs) have proven to be an excellent candidate for high power microwave and mm-wave applications [4.2]. Moreover, in recent years, the demand for high frequency performance of AlGaN/GaN HEMT devices are steadily increasing [4.3]. In order to extend the frequency of operation of these devices, it is necessary to implement ultrashort gate lengths and using of thin AlGaN barrier [4.4]. However, reducing the thickness of AlGaN barrier below a certain limit (about 10 nm) results in a strong degradation of the twodimensional electron gas density (2DEG), and thus poor device performance [4.5]. Although increasing the Al content in the AlGaN barrier layer can improve the 2DEG density, it also increases the lattice mismatch between the AlGaN and GaN layers, thereby degrading the quality of the heterostructure [4.6]. Furthermore, implementing the gate recess technique on these devices is difficult and this generally induces high gate leakage and reliability problems [4.5]. In recent years, AlN/GaN HEMT technology has become popular owing to its high theoretical 2DEG density of 6× 10 13 cm -2 [4.7]. This is due to the high spontaneous polarization value of AlN material [4.8] and its wide-band gap of 6.2 eV compared to GaN (3.42 eV). It has been demonstrated [4.9] that the replacement of the conventional AlGaN barrier layer by AlN/GaN layers offers much higher 2DEG density, allowing the achievement of high drain current (~2A/mm), even using ultrathin AlN barrier layer thickness well below 10 nm. Furthermore, the AlN/GaN HEMT devices achieve high breakdown voltages and lower onresistance [4.10]. This could be a suitable alternative to replace the existing conventional AlGaN/GaN HEMT technology for high frequency applications.

Although this AlN/GaN HEMT technology has made substantial progress over the last few years [4.11], the performance is still limited by the presence of electronic traps in the device structure. The traps may present at the surface, bulk or at the interface, causing effects such as current collapse, transconductance frequency dispersion, gate lag and drain lag.

Moreover, only a very limited number of publications are available to describe the influence of traps in these device structures. Therefore, the analysis of trapping effects on the device performance is significantly important in order to provide an appropriate feedback for the future technological improvements.

In this first section of this chapter, we study the impact of GaN channel traps on the performance of AlN/GaN/AlGaN HEMT using two-dimensional TCAD Sentaurus physical device simulation. Traps specifications used for TCAD simulations are adopted from the data reported in the literature [4.12]. In the second section of this chapter, we investigate the temperature dependency of on-resistance of AlN/GaN/AlGaN HEMT devices grown on SiC substrate through dc and low-frequency S-parameter measurements. A simple methodology to extract the temperature and bias dependent channel sheet resistance and parasitic contact resistance of GaN HEMT technology have been proposed.

Experimental and Numerical Device Simulation Structure

The AlN/GaN/AlGaN heterostructure field-effect transistors (HFETs) were grown by metalorganic chemical vapor deposition (MOCVD) on a 380-µm SiC substrate. The epilayers consist of a 1.5-µm thick Al0.08Ga0.92N buffer layer, 150-nm thick GaN channel layer followed by a 6nm ultrathin AlN barrier layer and 3-nm in-situ grown Si3N4 cap layer. Ni/Au Schottky gate contact and Ti/Al/Mo/Au metal stack for ohmic source and drain contacts were deposited directly on top of the AlN barrier layer by etching the in-situ Si3N4 layer. The in-situ Si3N4 layer allows for handling strain relaxation resulting from the high tensile stress induced in the device structure because of the growth of AlN barrier layer on top of the GaN channel layer and thereby giving rise to a high surface quality [4.5].

The devices with different gate widths, WG of 25 µm, 50 µm and 100 µm, each with two fingers (n=2) were fabricated on the same wafer. The gate length LG of the devices is 0.2 µm, source-gate separation (LSG) were fixed to 0.4 µm and different gate-drain distances (LGD) of 1, 2 and 3 µm, respectively, were used for the fabrication of devices. Room temperature dc-IV characteristics of the fabricated device are measured using an Agilent B1500A semiconductor device parameter analyzer. The cross section of the structure used for the simulation is shown in Fig. 4.1. The nominal thickness of all layers are used except for the case of SiC substrate.

The SiC substrate thickness is considered to be 5 µm, in order to speed up the simulation time.

Moreover, it is determined in the simulation that any further increase in thickness of the SiC substrate after 5-µm will have no significant effect on the simulated dc-IV characteristics.

Numerical TCAD Device Simulations

Two-dimensional physics based numerical simulations have been carried out using the commercially available TCAD Sentaurus software (formerly ISE-DESSIS) from Synopsys Inc.

Poisson's equation, and continuity equations for both electrons and holes, and the drift-diffusion (DD) model transport equations are solved self-consistently. The electric field induced due to the piezoelectric and spontaneous polarization contributes to the formation of 2DEG density at the AlN/GaN heterojunction interface, even without the need for doping [4.8]. In absence of externally applied electric fields, the polarization charges formed are of course, equal in magnitude and opposite in sign to maintain the overall charge neutrality of the device [4.13].

The theoretical method used for the calculation of polarization charges was described in [4.8].

However, in the case of AlN/GaN HEMT heterostructure, the theoretically calculated polarization charges are slightly higher than the experimentally measured sheet carrier concentration. A positive fixed sheet charge (+σpol) having a density 2.0× 10 13 cm -2 is defined at the AlN/GaN interface, which is in agreement with the experimental value [4.10]. The equivalent negative charge (-σpol) having the same density is placed at the AlN/SiN interface.

According to surface donor theory [4.14], the surface donors are responsible for the 2DEG channel formation in GaN HEMT devices. Hence, donor-like traps (σTD) having a density of 3.5× 10 13 cm -2 , with an energy level of 0. and output characteristics for varying VGS between 0 V and -2.5 V in steps of 0.5 V.

Impact of Traps on Simulated dc-IV Characteristics

Traps can be categorized into two types: donor-like and acceptor-like traps. An acceptor-like trap is considered to be neutral, if empty (unionized) and negative, if occupied (ionized), whereas a donor-like trap is positive, if empty and neutral, if filled with an electron. The ionization or non-ionization of traps inside the device depends strongly on the location of its energy level (ET) with reference to Fermi-energy level (EF). Acceptor traps ionizes only when ET is below EF and donor traps ionizes for ET above EF.

This will cause ionization of all acceptor traps in the GaN channel and thereby degrade the drain current, whereas the donor traps remain unionized. after switching from a high-voltage OFF state to a low-voltage ON state is a critical requirement in power electronics applications [4.15]. The higher electron mobility in the two-dimensional quantum well presents a low RON value that enhances the RF power-added efficiency performance [4.16]. In RF power GaN HEMT devices, dynamic switching issues occur due to current collapse, gate lag and drain lag effects, which deteriorates the RF power performance [4.17]. In power switching applications, this issue is visible, where the RON remains high for a period of time after an OFF-ON switching event [4.18]. In addition, the temperature has a significant impact on RON. The reduction of the 2DEG mobility with the increase of temperature contributes to the increase of RON [4.19]. Moreover, a power switching transistor usually operates at a relatively high temperature. Therefore, the analysis of the temperature dependent RON is an active research topic to explore. There are numerous papers reported in literature Additionally by applying a simple technique, to extract the temperature and bias dependent channel sheet resistance (Rsh) and parasitic series contact resistance (Rse) of this technology.

The proposed method could be applied to any device technology in order to extract the channel sheet resistance and parasitic contact resistances. In this paper, we attempt to study only the static RON of the device. The drain bias voltage used for the measurements is very low which implies that there is no visible trapping effect. However, under high biasing and hightemperature operating conditions, the presence of electronic traps in the device structure gets

LF-S Parameter Measurements

The low frequency S-parameters measurements in the frequency range of 100 Hz to 100 MHz A detailed description about LF-S parameter measurements can be seen in chapter 3 (section 3.3.3). The S-parameters measurements have been performed at cold-FET condition [4.33] (VGS > Vpinch-off and VDS = 0 V). The S-parameters measured are converted into the equivalent Zparameters and after the addition of parasitic resistances and inductances, the Z22 parameters can be expressed as [4.33], [4.34]:

22 s d ch s d d s 1 1 Z R R R j L L C C                  (4.1)
Where Rs, Rd, and Rch represent the source, drain and channel resistances, Ls and Ld are the parasitic source and drain inductances, and Cs and Cd represent the parasitic source and drain capacitances. Therefore, the on-resistance (RON) can be determined from the real part of the measured Z22 parameter and it is given by: Temperature dependence fitting parameters, α, β and γ values are assumed to be 1.7, 2.1 and 2.6, respectively for the GaN material. Moreover, based on our in-house measurements, the temperature-dependent ohmic source and drain contact resistances RC(T) are modeled using the following equation which is used in the simulation:

  22 Re ON s d ch Z R R R R     (4.2)
      ref ref C C T T T R R T     (4.3)
where RC(Tref) is the contact resistance (1.080 Ω-mm) at the reference temperature of 0 o C and λ is the temperature dependence fitting parameter, whose value is 0.0026.

Channel Sheet Resistance Extraction Methodology

The temperature dependent RON (T) can be described as the sum of the parasitic series contact resistance Rse (T) and the channel resistance Rch (T) as shown in Fig. 4.14 [4.36] . Here, Rse (T)

is the sum of the source (Rs) and drain (Rd) contact resistances. As shown in Fig. 4.14, the channel between source and drain can be subdivided into three regions: source-gate, underneath gate, and gate-drain region. Therefore, the total channel resistance can be expressed as a series combination of RshLSG/WG, RshLG/WG and RshLGD/WG, where Rsh is the sheet resistance or square resistance (Ω/) of the channel.

The resistance term (RshLG/WG) under the gate is a function of VGS, due to the depletion of Schottky gate contact. For a constant gate bias, RON (T) can be expressed as follows [4.37]:

      SG G GD ON se sh G L L L R R R T T T nW           (4.4)         sh sh sh ref ref dR T R R T T T T dT    (4.5)         se se se ref ref dR T R R T T T T dT    (4.6)
where, LSG, LG, and LGD are the source-gate, gate and gate-drain length, respectively. Following the linear variation of RON with temperature (Fig. 4.13), the Rsh (T) and Rse (T) can be expressed using a linear approximation as given in (4.5) and (4.6). Here, Rsh (Tref) and Rse (Tref) are the reference sheet resistance and contact resistance at a reference temperature Tref, respectively.

The source-drain length is given by, LSD = (LSG + LG + LGD). Differentiating (4.4) with respect to T, The corresponding extracted values are given as function of VGS in Table 4.2. Fig. 4.17 (a) and 4.17

      SD ON se sh G L dR dR dR T T T nW dT dT dT        

Summary

In the first part of this chapter, we systematically studied the influence of GaN channel traps on the performance of AlN/GaN/AlGaN HEMTs through two-dimensional TCAD numerical simulations. The simulation model is calibrated using the experimentally measured dc-IV characteristics and the calibrated TCAD simulation model is used for our traps study. Our simulation results indicate a significant influence of acceptor-like traps on the simulated dc-IV characteristics, whereas the donor-like traps have no considerable influence on the device performance. Moreover, it is demonstrated that deeper the energy level of acceptor-like traps, large the degradation in dc-performance of the device.

In the second part of this chapter, we first studied the temperature dependency of onresistance RON of AlN/GaN/AlGaN HEMTs grown on SiC substrate, for various device geometries through DC and low frequency measurements. We have also presented the 2D In recent years, AlN/GaN HEMT technology has attracted a great deal of attention for high power microwave and mm-wave applications [5.1] because of its superior performance [5.1] compared to conventional AlGaN/GaN HEMT devices. Indeed, this device technology has already delivered many of the promises made over the last few years [5.2], [5.3] , however the self-heating and charge-trapping effects still remain as a critical factor in limiting the device performance and its reliability. Moreover, the reliability of the device depends on the operating channel temperature [5.4]. The channel temperature can reach several hundred degrees above ambient base temperature when the device is operating in high power condition. It degrades the maximum power density achievable and accelerates the device failure [5.4]. The thermal resistance (RTH) plays a significant role in estimating the channel temperature of the device.

Lower thermal resistance can enhance the device performance and indeed proved to be useful in accomplishing the effective thermal management. Furthermore, the thermal resistance of the device depends on the thermal conductivity of the substrate material. The commercially available GaN HEMT devices are grown either on Silicon carbide (SiC) or Si substrates. The GaN HEMTs grown on SiC substrate offer a lower thermal resistance, owing to the high thermal conductivity of SiC. However, the SiC substrate is extremely expensive and the availability of the large size wafers is limited. Hence, Si substrate is considered as a suitable alternative due to its low cost and easy availability [5.5]. The higher thermal resistance associated with the lower thermal conductivity of Si substrate would significantly affect the device performance, especially at high power dissipation condition. Therefore, the systematic analysis of thermal behavior of the GaN HEMT devices grown on Si and SiC substrates is an active research area to explore.

A number of experimental techniques such as Raman spectroscopy, electrical measurement techniques, IR thermal imaging, thermo-reflectance thermography and infrared microscopy have been used with some extent but are limited either by spatial or temperature resolution [5.4]. Numerical simulation offers also an efficient alternate approach to evaluate the thermal behavior of devices [5.6] [5.7]. However, electro-thermal simulations based on the finite element method (FEM) are time consuming and rather complex. Therefore, in this chapter, we focus mainly on the thermal behavior of AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrates through pulsed I-V measurements and three-dimensional TCAD based thermal simulations. In addition, AlN/GaN/AlGaN HEMT devices grown on sapphire substrate have also been studied using 3D-TCAD thermal simulations.

Thermal Parameters Definition

The temperature rise in integrated circuits (ICs) occurs due to the following reasons [5.8]: (i) Self-heating effects (SHE) in the device due to dc-power dissipated inside the device and (ii) thermal coupling between neighboring components. The SHE is the most dominant one and this causes the variation of temperature inside the device. However, the distribution of temperature inside the device is non-uniform. Moreover, this SHE causes the transfer of heat from the heat source (channel region) to the back side of the substrate. In general, the back side of the substrate is connected to the external environment and the temperature is ideally assumed to be ambient temperature. Therefore, the transfer of heat to this substrate region results in temperature rise inside the device above the ambient temperature. The amount of heat transfer to the substrate is strongly dependent on the thermal conductivity of the substrate material used.

Moreover, the heat flow from the heat source to the top of the device via interconnect metallization is assumed to be negligible [5.8].

Thermal Resistance (RTH)

The temperature rise influences the device/circuit behavior is strongly dependent on the power dissipated inside the device. It is more convenient to represent a quantity that can describe the steady-state thermal behavior, independent of the dissipated power. Therefore, the thermal resistance (RTH) can be defined as the ratio of temperature increase (ΔT) over ambient temperature (Tamb) to dissipated power (Pdiss) [5.9]:

j amb TH diss diss T T T R P P     (5.1)
Where Tj is the junction temperature, Tamb is the ambient temperature and Pdiss is the power dissipated in the device. RTH is the thermal resistance (also called self-heating thermal resistance) of the device that depends on the material properties and geometry of the fabricated device structure.

The power dissipation in the device can be calculated using the following formula: Where ID and VDS are the drain current and drain-source voltage, respectively.

The thermal resistance is sufficient to describe the relationship between temperature and the power dissipated in the device under steady state conditions. However, for transient response, the thermal capacitance (CTH) is used and it can be expressed using [5.10]

: TH C
.c.V  (5.3) Where c is the specific heat capacity, ρ is the density and V is the volume of the material.

Thermal Impedance (ZTH)

It is a physical quantity that can be used to model the dynamic behavior of the device temperature. In time domain, it can be defined as the thermal transient response to the unitary power step. For instance, if the dissipated power increases instantaneously from 0 to Pdiss at time, t = 0, the thermal impedance can be given by [5.11]:

    j amb TH diss diss T t T Tt Z P P     (5.4)
Where Tj(t) is the time evolution of junction temperature during the applied power step.

The thermal resistance corresponds to the steady state value of ZTH(t):

  TH TH Z R   (5.5)
The two another major factors which can describe the dynamic thermal behavior, are the rise time, tR and the thermal cut-off frequency fTH. The rise time represents the time interval between two points where the transient response attains the 10% and 90% of the steady state RTH value, respectively. The thermal cut-off frequency is defined as the frequency at which the magnitude of ZTH reduces to the value of RTH/ (2) 1/2 .

Thermal Conductivity (κ)

In general, thermal conductivity is assumed as a constant parameter for a material. However, this assumption is not completely true for many semiconductor materials since they show a temperature dependence of thermal conductivity. Therefore, the temperature dependent thermal conductivity can be expressed by using the following equation:

  0 0 T T . T           (5.6)
Where κ0 is the thermal conductivity at the reference temperature T0 = 300 K, T is the temperature and α is the temperature-dependent fitting parameter.

In TCAD Sentaurus simulator, the temperature dependent thermal conductivity is given by the following equation [5.12]:

  2 a b c 1 T T T        (5.7)
For silicon, κa = 0.03 cmKW -1 , κb = 1.56 ×10 -3 cmW -1 and κc = 1.65 ×10 -6 cmW -1 K -1 . The range of validity is from 200 K to well above 600 K. The temperature independent thermal conductivity of silicon can be defined with the following parameters: κa = 1.54 cmKW -1 , κb = 0 cmW -1 and κc = 0 cmW -1 K -1 , respectively.

Lattice Heat Capacity (CL)

In TCAD Sentaurus simulator, the temperature dependent lattice heat capacity is modeled by the following empirical function [5.12]:

2 3 L C cv cv _ b.T cv _ c.T cv _ d.T     (5.8)
For silicon, a constant lattice heat capacity can be defined using the following parameters: cv = 1.63 J/Kcm 3 , cv_b = 0 J/K 2 cm 3 , cv_c = 0 J/K 3 cm 3 and cv_d = 0 J/K 4 cm 3 , respectively.

Experimental Structure

The AlN/GaN/AlGaN heterostructure field-effect transistors (HFETs) were grown by metalorganic chemical vapor deposition (MOCVD) on a 550-µm Si and SiC substrates. The epilayers consist of a 1.

Thermal Resistance (RTH) Extraction Using On-wafer Pulsed I-V Measurements

In this work, the method proposed in [5.13] is used to extract the thermal resistance (RTH) of the devices using on-wafer pulsed I -V measurements. The measurement technique consists of two steps [5.9] [5.13]: a calibration step (Fig. 5.1 (a)) and a measurement step (Fig. 5.1 (b)). In the calibration step, the quiescent point selected is VGS = VDS = 0 V in order to ensure that there is no dissipated power in the device. Hence, at this condition the channel temperature and chuck temperature are considered to be almost identical.

TCAD Thermal Simulation Methodology

The most accurate means of estimating the RTH, heat flux and temperature is possible through the use of finite-element simulations [5.6]. The most commonly used simulation tool for performing thermal and electro-thermal simulations is the ANSYS software. However, TCAD Sentaurus tool is also equally capable of performing both thermal and electro-thermal simulations. Moreoever, in this thesis work, TCAD Sentaurus simulation tool [5.12]

    n n p L n p p T . T T T C J J P P t                 (5.12)
where κ and CL represents the thermal conductivity and lattice heat capacity of the material.

The function T denotes the temperature of the body. In our simulations, we have considered only the thermal phenomenon inside the device structure. Moreover, we assume that the device body obeys the heat equation and it generates its own heat (H) at the specific place called "heat source". Therefore, the temperature T satisfies the following equation [5.8], [5.15]

: L T . T H C t       (5.13)
where H can be the steady state, transient or dynamic power generated by the heat generator.

The generated heat is applied at the heat source, which then dissipates the heat into the device structure obeying the heat flow mechanism.

The following boundary conditions are assumed in the simulations:

(i)
The outer surface of the Si/SiC block is considered to be adiabatic and therefore, no heat flows from the device to the external surroundings.

(ii)

The back-side of the wafer is an isothermal surface and initially kept at ambient temperature (300 K) (iii)

The heat transport from metallization to external surroundings is not considered for simplifying simulation. The width of the heat source is assumed similar to the device width, respectively. (iii) Regions where the thermal gradients are expected to be high. Moreover, the mesh density has been optmized in every region in order to decrease the simulation time with sufficient accuracy. Fig. 5.9 (a) and 5.9 (b) show the mesh refinement of the complete device and the region close to the placement of heat source. A higher mesh density is clearly observable around the heat source regions where the thermal gradients are generally high. We assume a temperature independent thermal conductivity (κ) and specific heat capacity (CV) such that the physical simulations are linear. Table . 5.1 gives the thermal conductivity and layer thickness of the different materials used in the thermal simulations. LG and 6 LG) have been considered from the source-side gate edge towards drain-side in order to achieve a match between the simulated and experimentally measured thermal resistance. A good compromise is obtained only when the LHS is chosen to be twice the gate length of the device. This signifies the location of maximum electric field and therefore the hot spot is at the drain-side gate edge.

Alternatively, if we allow the simulator to solve equation (5.12), it computes the heat dissipation area accordingly and therefore the optimization of LHS is not necessary. However, the simulation time will be very high.

The steady state distribution of lattice temperature (TLattice) inside the HEMT grown on Si/SiC/Sapphire substrate is shown in Fig. 5.11. The applied dc power is 0.125 W per heat source and the device width is 50 µm. A significant difference in finger temperature is observed between different devices. It is worthwhile to note that for the same applied dc power, the lattice temperature at the epilayers/substrate interface is higher in case of Sapphire substrate when compard to Si and SiC substrate (Fig. 5.12 (b)). The ratio of increase in the lattice temperature at this interface is proportional to the ratio of the thermal conductivity values of materials. The respective ratio values are given in Table 5.2. In 3D-TCAD thermal simulations, the thermal resistance is extracted by dividing the increment in lattice temperature by the total power applied across the heat source. In order to validate the simulation results, RTH extracted from pulsed I-V measurements are compared with simulation results. The comparison of the simulated and measured thermal resistances are shown in Fig. 5.13 (a). An excellent agreement is achieved between the measured and simulated thermal resistances for various geometries of the devices and using different substrates.

However, it is important to note that there is no significant difference observed in obtained RTH values of AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrates. This is due to the lower thermal conductivity of the AlGaN buffer used in these devices [5.16]

Thermal Modeling Using Electro-Thermal Networks

Electrical Representation of Thermal Systems

In general, the propagation of heat in any system occurs via three different ways, i.e. convection, heat radiation or conduction. However, for electronic systems, the heat propagation take place essentially through heat conduction which is described by a partial differential equation for the case of homogeneous isotropic medium [5.10]: Where c is the specific thermal capacitance, ρ is the density of the material, κ is the specific heat conductance, T is the temperature and x represent the co-ordinates in the direction of heat propagation.

The electrical analog model for heat conduction can be the transmission line model, although its physical properties are described by a complex equation [5.10]:

  2 2 ' ' ' ' ' ' ' ' 2 2 U U U C .L. C .R G .L G .R .U x t t           (5.15)
Where C ' , R ' , G ' and L ' are the capacitance, resistance, conductance and inductance per unit length, respectively.

The equations (5.14) and (5.15) describes two different physical process and hence they have no direct physical relationship between them. However, if we consider the fact that, the heat conduction in solid media, there is no equivalent term for the electrical parameters of inductance and such that a volume element cannot cool itself. This can be described using L ' = G'=0 and therefore, the transmission line equation can be reduced to [5.10]:

2 '' 2 U U C .R x t      (5.16)
Therefore, equations (5.14) and (5.16) can have the same form. Moreover, Kirchhoff stated that "two different forms of energy behave identically when the basic differential equations which describe them have the same form and the initial and boundary conditions are identical [5.11]".

According to equations (5.14) and (5.16), the process of heat conduction can be therefore modeled using a transmission line equivalent circuit consisting of R and C elements only. The analogy between electrical and the thermal parameters are given in Table 5.

Electro-thermal Network Topologies

The thermal network representing the complete layout of the device tend to be very large, therefore it increases the complexity of modeling, increasing the simulation time and leading to numerical convergence issues. However, this would provide extensive information on temperature parameter in various regions of the device. Nowadays, the most widely used modeling approach in commercial electro-thermal simulators is to use mono-dimensional networks [5.11], in specific, a single RC network is used to model thermal behavior using the junction temperature and the dissipated power in the device. Some of the widely used electrothermal network topologies are explained in this section. (5.17)

Where p is the Laplace variable.

The first order self-heating model can be given by the dynamic relationship between instantaneous power dissipation (Pdiss(t)) and the rise in device temperature [5.14]:

  rise t T t T 1 exp               (5.18)
Where ΔT= Pdiss(t).RTH is the magnitude of the temperature step and τ =RTH.CTH is the time constant.

The model shown in Fig. 5.15 (a) is the reduced form of the generalized thermal equivalent circuit (Foster network) shown in Fig. 5.15 (b). In general, the diffusion process in the medium is described as the superposition of infinite number of modes. Moreover, each mode can be characterized by its Eigen function and its associated time constant τi. Therefore, the precise solution of the heat transform problem can be expressed using the following form [5.14]:

  n rise i i1 i t T t T 1 exp                   (5.19)
Where ΔTi= Pdiss(t).RTHi and τi =RTHi.CTHi.

The Foster Network

The Foster network shown in Fig. 5.15 (b) is based on infinite set of exponential time constants equivalent to a step response with zero initial conditions. Each time constant is simply equal to the product of the resistance and the capacitance of each cell in the network. Typically, four time constants are adequate to describe the thermal impedance of the system with sufficient accuracy. Therefore, the transfer function of a Foster network in time domain, by [5.11]:

  n TH THi i1 i t Z t R 1 exp                  (5.20)
and in frequency domain by [5.11]:

  1 1 .2 . .     n THi TH i i R Zf jf  (5.21)
The transfer function using Laplace network to the response of the network in time domain is given by [5.14]:

  1 1     n THi TH i THi THi R Zp pR C (5.22)
The Foster network is very simple to implement, however it can be used to describe only the thermal behavior at the input node and therefore, the internal nodes do not have a physical meaning. In fact, changing the order of RC cells in the Foster model does not affect the overall response of the system and this indicates that there is no physical relation between the device structure and an individual RC cell. Moreover, this network cannot be used to determine the temperature distribution within the device.

The Cauer Network

The Cauer network is more convenient way to describe physically the thermal behavior of the system. The element values of the Cauer networks can be determined by employing the heat equation [5.14]. Unlike the Foster network, the Cauer network can describe the internal temperature distribution of the system since the thermal capacitances are connected to thermal references (electrical or thermal ground). Moreover, each cell of the Cauer network is the physical representation of heat-conducting structure layers and therefore, each cell can contribute to the total thermal impedance of the system.

In contrast to Foster network, there is no direct relation between time constants τi and thermal parameters (RTHi and CTHi) for Cauer network shown in Fig. 5.16. Indeed, the time constant of each cell depends on all the thermal parameters of the system, leading to a complex mathematical representation of the system. The transfer function of the Cauer network using Laplace transforms can be expressed as [5.11]:

          1

Modified Recursive Network

It is basically a Cauer type network where the RC elements are placed in recursive order. The recursive network treats that every element is a heat generating sphere [5.14]. Therefore, the time-dependent heat diffusion can be modeled using the circuit shown in Fig. 5.17 where the respective thermal resistance element decreases and the capacitance element increases and these have been modeled using different recursive factors, Kr (<1)and Kc (>1), for resistance and capacitance, respectively. The transient variation of device temperature is modeled by CTH, however, under steady-state conditions, CTH has no physical meaning [5.8]. Therefore, the thermal resistance can be expressed as the sum of resistances of each recursive cell existing in the circuit. It is worth to note that, higher the number of cells may provide better accuracy, however it suffers from large simulation time.

The thermal resistance of the modified recursive network under steady-state conditions can be expressed using [5.8]:

0 .    N n TH ri n R K R (5.24) i = 1,2, … m.
Where N represent the number of cells in the recursive network. Therefore, the dynamic self-heating response of the device could not be modeled properly with a traditional single-pole network, since it is associated only with a single time constant [5.8].

Therefore, we have considered the modified recursive network shown in Fig. 5.17 thermal impedance of 2×100µm device grown on Si substrate using recursive thermal network.

Summary

In this chapter, we first extracted the thermal resistance of AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrates through on-wafer pulsed I-V measurements. Then, we studied the thermal behavior of the same AlN/GaN/HEMT devices grown on different substrates through 3D-TCAD thermal simulations. The thermal resistances extracted for various geometries of the devices using TCAD thermal simulations are compared with measurements and found to be in excellent agreement. Then, we investigated the thermal behavior of these devices by applying the transient pulse across the heat source of the device. The obtained transient thermal characteristics of the devices are modeled using the modified recursive network and an excellent agreement is obtained between TCAD simulations and the recursive thermal model. This will ease the circuit designers to integrate the thermal model while developing the large signal model (LSM) of device.

Conclusions

GaN HEMT device technology demonstrates a great deal of potential for all high frequency and high power microwave and RF applications which pushes the limits of conventional Si or GaAs based devices. However, these GaN HEMT devices are considered to be relatively immature However, the donor-like traps gets ionized only at high negative gate biasing and only for shallow trap energy level lies inside the conduction band. Therefore, it can be concluded that acceptor-like traps have a significant influence on the simulated dc I-V characteristics whereas the donor-like traps have no considerable influence. Moreover, the simulation results also suggest that deeper the energy level of acceptor-like traps, more the possibility of ionization of these traps and hence, larger the reduction in drain current performance of the device.

In the second part of chapter 4, we first studied the temperature dependency of on-resistance (RON) of AlN/GaN/AlGaN HEMT devices grown on SiC substrate through dc and lowfrequency S-parameters measurements. The RON has been extracted from the dc I-V and LF Sparameters measurements for various device geometries of the devices grown on SiC substrate.

A good agreement has been obtained between the two methods demonstrate that the proposed extraction procedure remains valid for various geometries of the device. Moreover, using the calibrated 2×100µm device simulation model, the RON has been simulated for various operating device temperature. A good agreement has been observed between the measurement and TCAD simulation over the temperature range of 0ºC to 150ºC. Then, we have proposed a simple methodology for extracting the temperature dependence of channel sheet resistance (Rsh) and parasitic series contact resistance (Rse) of the device technology. The detailed procedure for extracting sheet resistance and contact resistance has been illustrated with the aid of flowchart.

The proposed methodology has been applied on 2×50µm device low frequency measurement data with different gate-drain distances (LGD) of 1.0, 2.0 and 3.0 µm, respectively. The corresponding Rsh and Rse have been extracted as a function of gate bias voltages and operating device temperature. Moreover, the extracted value of sheet resistance is in agreement with the already reported value of this device technology. The proposed extraction procedure has also been verified using TCAD device simulations. The variation observed in the extracted Rsh and Rse between measurements and TCAD simulations are only due to the calibration error, because the 2×100µm device calibrated parameters have been used for 2×50µm device simulations.

Therefore, it can be concluded that this proposed methodology can be applied to any device technology in order to extract the channel sheet resistance and parasitic contact resistances.

Chapter 5 investigates the thermal behavior of AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrates through on-wafer pulsed I-V measurements and three-dimensional (3D)

TCAD-based thermal simulations. The thermal resistances have been extracted for various device geometries using measurements and TCAD thermal simulations and found to be in excellent agreement. In thermal simulations, the external heat source is assumed and the generated heat is applied at the heat source, which then dissipates the heat into the device structure obeying the heat flow mechanism. The length of the heat source (LHS) is optimized in order to achieve a match between the simulated and experimentally measured thermal resistance. A good match is obtained when the LHS is chosen to be twice the gate length of the device and this implies that hot spot is located at the drain-side gate edge. Then, we have investigated the thermal behavior by applying the transient pulse at the heat source of the device. The obtained transient thermal characteristics have been modeled using modified recursive network and an excellent agreement is achieved between TCAD simulations and thermal model, for various device geometries of the devices grown on Si and SiC substrates.

Therefore, the developed thermal model will be handful for circuit designers to integrate this thermal model while developing the large signal model (LSM) of the device.

Scope of Future Works

A number of possible improvements can be added to the work presented in this thesis in order to completely understand the degradation mechanisms of GaN HEMT device technology. This would benefit both the device fabrication individuals and RF circuit designer's community to gain the knowledge on physical degradation mechanisms and its impact on device/circuit performance. The possible scopes of future works are summarized below:

(

1) Extension of physics-based analytical modeling

The analytical drain current model presented in this thesis is capable of predicting the extrinsic HEMT characteristics of the device with reasonable accuracy for the case of long channel devices. However, the proposed model does not include some physical effects like channel length modulation, self-heating, short channel effect and mobility degradation. These physical effects must be included into the developed model in order to accurately predict the device characteristics, especially for sub-micron gate length devices. Moreover, the existence of traps in the GaN HEMTs significantly influence the device characteristics. Therefore, the trapping effects need to be incorporated into the physical model. Then, the developed physical model can be integrated with the modern circuit simulators and this would greatly benefit the circuit designers to predict the device performance for high frequency and high power applications.

(

2) Characterization of Barrier Traps

In the chapter 3 of this thesis, we attempt to characterize the traps existing in the GaN buffer region of the device using different measurement techniques and TCAD physical simulations.

However, the traps may also exist in the AlGaN barrier of the device structure. Therefore, it is essential to characterize the barrier traps and also to understand their influence on device performance. The following two possible ways could be useful for characterizing the barrier traps: (1) performing the LF input gate noise measurements of the device at various operating temperatures and this would allow to identify the type of traps and their corresponding physical properties such as activation energy (Ea) and cross section (σn). ( 2) performing I-DLTS measurement of the device by pulsing the gate bias voltage well below pinch-off to ON state and at fixed drain potential. This would allow to extract the time constant of traps and therefore, repeating this measurement at different temperatures, and then by using Arrhenius equation, the physical properties of traps can be determined. Then, by using TCAD physical simulations it is possible to physically confirm the location of traps in the device.

(

3) Gate Leakage Characterization

Gate leakage becomes significantly important in determining the power dissipation and reliability of these devices. Moreover, for the case of AlN/GaN HEMT devices, the barrier layer is very thin and this causes the high electric field across the barrier and this results in increased electrons tunneling through the barrier, leading to larger gate leakage current. Therefore, it is important to measure the gate leakage characteristics of these devices. Moreover, using TCAD physical simulations, it is crucial to understand the leakage current mechanisms of the device over a wide range of bias and temperature. Indeed, TCAD physical simulations would help to identify the type of leakage mechanisms (Poole-Frenkel emission, Fowler-Nordheim tunneling or Trap-Assisted-Tunneling) occurring in the device. Furthermore, it is also helpful to examine the impact of AlGaN barrier traps on the gate leakage performance of the device.

(4) Poole-Frenkel Assisted Traps Emission

The emission rate of traps is not only dependent on temperature but also strongly dependent on applied drain biasing (electric field in the device). Therefore, it would be useful to analyze the bias dependent admittance characteristics.

(

5) Electro-thermal Simulations

In the thermal simulations of AlN/GaN/AlGaN HEMT devices presented in chapter 5, we assumed an external heat source to dissipate the required heat into the device structure. The width of the heat source is assumed to be the gate width and the length of the heat source is optimized in order to achieve a good match between the simulated and measured thermal resistance. Therefore, the simulations performed are purely thermal. However, TCAD simulation tool is capable of solving self-consistently the basic Poisson's equation along with the lattice heat flow equation to generate the heat dissipation inside the device. This would automatically compute the heat dissipation area (hot spot) accordingly and eliminates the need of assumption of an external heat source and the associated optimization process. Indeed, the simulation will be purely electro-thermal and could offer better understanding of device characteristics.

(6) Large Signal Model (LSM)

The development of LSM including trapping mechanisms, low frequency noise sources and thermal effects would significantly benefit the RF designer's community.

Simulations physiques et mesures du composant de technologie GaN HEMT pour les applications d'amplificateur de puissance RF

Résumé: Depuis plusieurs années, la technologie de transistors à effet de champ à haute mobilité (HEMT) sur Nitrure de Gallium (GaN) a démontré un potentiel très important pour la montée en puissance et en fréquence des dispositifs. Malheureusement, la présence des effets parasites dégrade les performances dynamiques des composants ainsi que leur fiabilité à long-terme. En outre, l'origine de ces pièges et leur emplacement physique restent incertains jusqu'à aujourd'hui. Une partie du travail de recherche menée dans cette thèse est axée sur la caractérisation des pièges existant dans les dispositifs HEMTs GaN à partir de mesures de paramètre S basse fréquence (BF), les mesures du bruit BF et les mesures I(V) impulsionnelles. Parallèlement, nous avons effectué des simulations physiques basées sur TCAD afin d'identifier la localisation des pièges dans le transistor. De plus, notre étude expérimentale de caractérisation et de simulation montre que les mesures BF pourraient constituer un outil efficace pour caractériser les pièges existant dans le buffer GaN, alors que la caractérisation de Gate-lag pourrait être plus utile pour identifier les pièges de barrièredes dispositifs GaN HEMT.. La deuxième partie de ce travail de recherche est axée sur la caractérisation des dispositifs AlN/GaN HEMT sur substrat Si et SiC. Une méthode d'extraction simple et efficace de la résistance canal et de la résistance de contact a été mise au point en utilisant conjointement la simulation physique et les techniques de caractérisation. Le principe de l'extraction de la résistance canal est basée sur la mesure de la résistance RON. Celle-ci est calculée à partir des mesures de courant de drain IDS et de la tension VDS pour différentes valeurs de températures En outre, nous avons procédé à une évaluation complète du comportement thermique de ces composants en utilisant conjointement les mesures et les simulations thermiques tridimensionnelles (3D) sur TCAD. La résistance thermique (RTH) a été extraite pour les transistors de différentes géométries à l'aide des mesures et ensuite validée par les simulations thermiques sur TCAD.

Mots clés: HEMT GaN, Pièges, mesure de paramètres-[S] BF, mesures de bruit BF, simulations physiques sur TCAD, modélisation analytique, modélisation thermique.

Fig. 1 . 1 . 29 Fig. 1 . 2 . 30 Fig. 1 . 3 . 31 Fig. 1 . 4 . 32 Fig. 1 . 5 . 32 Fig. 1 . 6 . 33 Fig. 1 . 7 . 33 Fig. 1 . 8 . 35 Fig. 1 . 9 . 38 Fig. 1 . 10 . 39 Fig. 1 . 11 . 40 Fig. 1 . 12 . 42 Fig. 1 . 13 . 43 Fig. 1 . 14 . 44 Fig. 1 . 15 . 44 Fig. 1 . 16 . 45 Fig. 1 . 17 . 47 Fig. 1 . 18 . 48 Fig. 1 . 19 . 49 Fig. 1 . 20 . 50 Fig. 2 . 1 .Fig. 2 . 2 .Fig. 2 . 3 .Fig. 2 . 4 .Fig. 2 . 5 .Fig. 2 . 6 .Fig. 2 . 7 .Fig. 2 . 8 .Fig. 2 . 9 .Fig. 2 . 10 .Fig. 2 . 11 .Fig. 2 .Fig. 2 .Fig. 2 .Fig. 2 . 15 .Fig. 2 . 16 .Fig. 2 .Fig. 2 .Fig. 2 . 19 .Fig. 2 . 20 .Fig. 2 . 21 .Fig. 2 . 22 .Fig. 2 . 23 .Fig. 3 . 1 .Fig. 3 . 2 .Fig. 3 . 3 .Fig. 3 . 4 .Fig. 3 . 5 .Fig. 3 . 6 .Fig. 3 . 7 .Fig. 3 . 8 .Fig. 3 . 9 .Fig. 3 . 10 .Fig. 3 . 11 .Fig. 3 . 12 .Fig. 3 . 13 .Fig. 3 . 14 .Fig. 3 . 15 .Fig. 3 . 16 .Fig. 3 . 17 .Fig. 3 . 18 .Fig. 3 . 19 .Fig. 3 . 20 .Fig. 3 . 21 .Fig. 3 . 22 .Fig. 3 . 23 .Fig. 3 . 24 . 126 Fig. 3 . 25 . 126 Fig. 3 . 26 .Fig. 3 . 27 .Fig. 3 . 28 .Fig. 3 .Fig. 3 . 30 .Fig. 3 .Fig. 3 . 32 .Fig. 3 . 33 .Fig. 3 . 34 .Fig. 3 . 35 .Fig. 3 . 36 .Fig. 3 . 37 .Fig. 4 . 1 . 147 Fig. 4 . 2 .Fig. 4 . 3 .Fig. 4 . 4 .Fig. 4 . 5 . 151 Fig. 4 . 6 . 151 Fig. 4 . 7 .Fig. 4 . 8 .Fig. 4 . 9 . 153 Fig. 4 . 10 .Fig. 4 .Fig. 4 . 12 .Fig. 4 . 13 .Fig. 4 . 14 .Fig. 4 . 15 .Fig. 4 . 16 .Fig. 4 . 17 .Fig. 4 . 18 .Fig. 4 . 19 .Fig. 5 . 1 .Fig. 5 . 2 .Fig. 5 . 3 .Fig. 5 . 4 .Fig. 5 . 5 .Fig. 5 . 6 .Fig. 5 . 7 .Fig. 5 . 8 .Fig. 5 . 9 .Fig. 5 . 10 .Fig. 5 . 11 .Fig. 5 . 12 .Fig. 5 .Fig. 5 . 14 .Fig. 5 .Fig. 5 . 16 .Fig. 5 . 17 .Fig. 5 . 18 .Fig. 5 . 19 .Fig. 5 . 20 .

 11291230133114321532163317331835193811039111401124211343114441154411645117471184811949120502122232425262728292102112222152162221922022122222331323334353637383931031131231331431531631731831932032132232332412632512632632732833303332333334335336337411474243444515146151474849153410441241341441541641741841951525354555657585951051151255145516517518519520 Fig. 1.1. (a) Energy band diagram of AlGaN/GaN HEMT illustrating band gap discontinuity (a) before forming the hetero-junction (b) band bending due to hetero-junction formation (c) 2DEG at the hetero-junction interface. .................................................................................. 29 Fig. 1.2. Electric field and polarization charge present due to spontaneous polarization mechanism in GaN and AlGaN crystals grown on c-plane (Ga-face crystal) [1.26]. .............. 30 Fig. 1.3. Spontaneous polarization coefficients of group III-V nitrides [26]. ......................... 31 Fig. 1.4. Strain induced piezoelectric polarization in the AlGaN/GaN heterostructure. (a) Band gap values vs. lattice constant c0 of group III-V materials. (b) Lattice structure illustrating the tensile strain [1.26]. .............................................................................................................. 32 Fig. 1.5. Piezoelectric polarization coefficients of group III-V materials [1.26]..................... 32 Fig. 1.6. Electric field and polarization charge present due to piezoelectric polarization mechanism in AlGaN crystals grown on c-plane (Ga-face crystal). ....................................... 33 Fig. 1.7. Schematic cross section of conventional AlGaN/GaN HEMT. ................................ 33 Fig. 1.8. Modified field plate structure of AlGaN/GaN HEMT device (a) gate connected (b) source connected. ................................................................................................................. 35 Fig. 1.9. Schematic cross section of GaN/AlGaN/GaN HEMT device describing the possible physical location of traps. ..................................................................................................... 38 Fig. 1.10. Theoretical representation of current collapse mechanism. .................................... 39 Fig. 1.11. Schematic representation of current collapse mechanism. Timing waveform illustrating the different regions of device operation (a), Zero-biasing conditions (b), Traps behavior when the voltage below device pinch-off (c) and positive bias (d) are applied to the gate and once the device is completely turned-on (e). ........................................................... 40 Fig. 1.12. Schematic description of gate-lag mechanism. Two possible mechanisms (i) surface trapping and (ii) trapping under the gate. .............................................................................. 42 Fig. 1.13. Measured pulsed I-V characteristics of the GaN/AlGaN/GaN HEMT device grown on SiC substrate illustrating the gate-lag effect. .................................................................... 43 Fig. 1.14. Schematic representation of drain-lag mechanism. High negative bias applied to the gate cause tunneling of electrons from gate to the surface and high drain bias cause the excitation of channel electrons and those electrons could easily get trapped in the buffer. ..... 44 Fig. 1.15. Measured pulsed I-V characteristics of the GaN/AlGaN/GaN HEMT device grown on SiC substrate illustrating the drain-lag effect. ................................................................... 44 Fig. 1.16. Schematic cross section of AlGaN/GaN HEMT describing the high electric field region. The hot electrons create defects in the different device layers and capture the electrons. ............................................................................................................................................. 45 Fig. 1.17. Gate leakage mechanism -Thermionic Emission. ................................................ 47

Table 5 . 1 .Table 5 . 2 .Table 5 . 3 .

 515253 Thermal conductivity and layer thickness of the materials used in thermal simulations. ........................................................................................................................ Ratio of thermal conductivity of different substrate materials and the associated lattice temperature obtained in thermal simulations. ............................................................ Analogy between thermal and electrical parameters. ..........................................

Chapter 2

 2 describes the physics based analytical modeling of current-voltage characteristics of AlGaN/GaN HEMT devices. A generalized drain current model, valid for predicting both intrinsic and extrinsic characteristics have been presented. Chapter 2 also provides an overview of the TCAD Sentaurus simulation tool used in this thesis. The basic semiconductor equations and different kind of physical models existing in the simulation tool have been described. The illustration of formation of the two-dimensional electron gas (2DEG) in AlGaN/GaN HEMT device using TCAD physical simulations have been provided. The comparison of simulation results of different kind of simulation models have also been discussed. Chapter 3 investigates the trapping mechanisms of GaN/AlGaN/GaN HEMTs grown on SiC substrate using Low-Frequency measurements and TCAD-based physical device simulations.

1. 1 Fig. 1 . 1 .

 111 Fig. 1.1. (a) Energy band diagram of AlGaN/GaN HEMT illustrating band gap discontinuity (a) before forming the hetero-junction (b) band bending due to hetero-junction formation (c) 2DEG at the hetero-junction interface.

  junction interface. This contributes to an electrically charged region in the vicinity of the junction. The surface charge formed due to the spontaneous polarization in a Ga-face crystal of GaN and AlGaN grown on c-plane is shown in Fig. 1.2. Fig. 1.3 shows the spontaneous polarization coefficients (Psp) of the group III-V nitride materials [1.26]. The piezoelectric polarization charge is formed due to the presence of a polarization field resulting from the distortion of the crystal lattice.

Fig. 1 . 2 .

 12 Fig. 1.2. Electric field and polarization charge present due to spontaneous polarization mechanism in GaN and AlGaN crystals grown on c-plane (Ga-face crystal) [1.26].

Fig. 1 . 3 .

 13 Fig. 1.3. Spontaneous polarization coefficients of group III-V nitrides [26].

Fig. 1 . 4 .

 14 Fig. 1.4. Strain induced piezoelectric polarization in the AlGaN/GaN heterostructure. (a) Band gap values vs. lattice constant c0 of group III-V materials. (b) Lattice structure illustrating the tensile strain [1.26].

Fig. 1 . 5 .

 15 Fig. 1.5. Piezoelectric polarization coefficients of group III-V materials [1.26].

Fig. 1 . 6 .Fig. 1 . 7 .

 1617 Fig. 1.6. Electric field and polarization charge present due to piezoelectric polarization mechanism in AlGaN crystals grown on c-plane (Ga-face crystal).

Fig. 1 . 8 .

 18 Fig. 1.8. Modified field plate structure of AlGaN/GaN HEMT device (a) gate connected (b) source connected.

Fig. 1 . 9 .

 19 Fig. 1.9. Schematic cross section of GaN/AlGaN/GaN HEMT device describing the possible physical location of traps.

Fig. 1 . 10 .

 110 Fig. 1.10. Theoretical representation of current collapse mechanism.

Fig. 1 . 11 .

 111 Fig. 1.11. Schematic representation of current collapse mechanism. Timing waveform illustrating the different regions of device operation (a), Zero-biasing conditions (b), Traps behavior when the voltage below device pinch-off (c) and positive bias (d) are applied to the gate and once the device is completely turned-on (e).

.

Fig. 1 . 12 .

 112 Fig. 1.12. Schematic description of gate-lag mechanism. Two possible mechanisms (i) surface trapping and (ii) trapping under the gate.

Fig. 1 .Fig. 1 . 13 .

 1113 Fig. 1.13 shows the gate-lag measurements of GaN/AlGaN/GaN HEMT grown on SiC substrate with the gate length (LG) of 0.25-µm and gate width (WG) of 600-µm (eight fingers, n=8), respectively.

Fig. 1 . 14 .

 114 Fig. 1.14. Schematic representation of drain-lag mechanism. High negative bias applied to the gate cause tunneling of electrons from gate to the surface and high drain bias cause the excitation of channel electrons and those electrons could easily get trapped in the buffer.

Fig. 1 . 15 .

 115 Fig. 1.15. Measured pulsed I-V characteristics of the GaN/AlGaN/GaN HEMT device grown on SiC substrate illustrating the drain-lag effect.

Fig. 1 . 16 .

 116 Fig. 1.16. Schematic cross section of AlGaN/GaN HEMT describing the high electric field region. The hot electrons create defects in the different device layers and capture the electrons.

  [1.55],[1.56]. Once a critical value of tensile strain or elastic energy is reached at the drain side gate-edge, this stress is relaxed through the formation of crystallographic defects in the AlGaN barrier region. This promotes the injection of electrons from the gate metal into the AlGaN barrier, through a trapassisted tunneling mechanism, creating parasitic paths for the leakage current to flow. It results in the increase of gate leakage current in the device and also contributes to other trapping related effects. The major consequences of the gate-edge degradation effect are the increase of gate leakage current, worsening of current collapse, increase of parasitic drain (source) resistance and a decrease of saturated DC drain current (IDSS). The gate-edge degradation can be investigated through several measurement techniques such as Transmission Electron Microscopy analysis (TEM), Electroluminescence microscopy and Destructive Physical Analysis (DPA)[1.56].1.9. Gate LeakageGate leakage is one of the major issue that affects the performance of GaN HEMT devices. It refers to leakage of current through the gate by electron tunneling process which degrades the RF and noise performance of the device [1.57]-[1.59]. The 2DEG channel of the GaN HEMT device is controlled by the Schottky gate contact and higher negative bias is generally applied to turn-off the device. Therefore, the gate leakage becomes significantly important in determining the performance and reliability of these devices. An extensive research has been conducted to analyze the temperature and bias dependencies of gate leakage in AlGaN/GaN HEMT devices [1.60]-[1.62]. It has been suggested that Poole-Frenkel (PF) emission is

Fig. 1 . 17 .

 117 Fig. 1.17. Gate leakage mechanism -Thermionic Emission.

  electric field enhanced thermal emission of electrons from the traps state to the continuum of states formed by the conductive dislocations existing in the AlGaN barrier is responsible for PF emission [1.62]. Fig. 1.18 shows the classical conduction band diagram and the continuum states describing the physical mechanism of PF emission. The trap states are assumed to be located very close to the metal Fermi level and the continuum of states (Edis) formed due to the conductive dislocations in the AlGaN barrier, is at a height ɸt from the gate metal Fermi level. The increasing gate voltage (Vg) increases the electric field in the device and correspondingly, increases the current due to the reduction in barrier height for electron emission. Moreover, the increase in temperature results in increased current owing to the higher thermal energy acquired by the charge carriers to jump from trap state to the conductive dislocations in the AlGaN barrier. Therefore, the PF mechanism dominates the gate leakage current in the low to medium reverse-bias region.

Fig. 1 . 18 .

 118 Fig. 1.18. Gate leakage mechanism -Poole-Frenkel Emission.

Fig. 1 . 19 .

 119 Fig. 1.19. Gate leakage mechanism -Fowler Nordheim Tunneling.

Fig. 1 . 20 . 1 .

 1201 Fig. 1.20. Gate leakage mechanism -Trap-Assisted Tunneling.

3 )

 3 and ξxy is the strain in the x-y plane, a(0) and a(m) are the lattice constants, e31(m) and e33(m) are piezoelectric constants and c13(m) and c33(m) are elastic constants, respectively.The Al mole fraction dependent parameters of AlGaN material used for analytical model calculation are listed in Table2.1.

Fig. 2 . 1 .

 21 Fig. 2.1. Cross section of an AlGaN/GaN HEMT.

Fig. 2 .Fig. 2 . 3 .

 223 3 (a) shows the comparison of sheet density obtained from numerical solution and analytical model, indicates a good agreement over the complete operating range of gate-source voltage. Fig. 2.3 (b) shows the comparison of sheet density obtained for various Al mole fraction using analytical model and numerical solution. A good agreement between two results demonstrates that sheet density model is valid for various Al mole fraction. Comparison of numerical calculation and the analytical model: (a) sheet density vs. gate voltage (b) sheet density vs. Al mole fraction.

Fig. 2 .Fig. 2 . 4 .Fig. 2 . 5 .

 22425 Fig. 2.4 (a) and 2.4 (b) show the comparison of ID-VGS and ID-VDS characteristics of

Fig. 2 . 6 .

 26 Comparison of drain current characteristics for Al0.15Ga0.85N/GaN exttrinsic HEMT calculated using analytic model (Solid lines) and experimental data [2.13] (Points) for 1-µm device. (a) transfer characteristics (ID-VGS) and (b) output characteristics (ID-VDS).

Fig. 2 .Fig. 2 . 7 .

 227 Fig. 2.5 (a) shows the extrinsic ID-VGS characteristics of 2.1-µm Al0.26Ga0.74N/GaN HEMT device for the applied drain bias voltage of 6 V. Similarly, Fig. 2.5 (b) shows the ID-VDS characteristics obtained as a function of gate-source bias voltage. A good agreement is observed between the model and experimental data obtained from [2.15]. Fig. 2.6 (a) and 2.6 (b) show the comparison of ID-VGS and ID-VDS characteristics for 1-µm device obtained from our model with experimental data obtained from [2.13].

Fig. 2 . 8 .

 28 Fig. 2.8. TCAD Sentaurus physical simulation methodology.

2. 4 .

 4 Fig. 2.9. 2DEG Formation for the case of an ideal surface: (a) No 2DEG (d < dCR) (b) 2DEG is formed at the AlGaN/GaN interface (d > dCR) [2.29].

  e. the surface of the AlGaN region is expected to contain certain vacancies or other defects. The surface states thus formed constitute a net positive charge as shown in Fig.2.10 [2.30]. The energy level of this surface state is presumed to be constant during the growth of AlGaN region. It is also important to note that the Fermi level remains constant as the crystal is under equilibrium condition. The schematic of the conduction band diagram for a conventional AlGaN/GaN HEMT structure with its associated space charge component is shown in Fig.2.10. In the absence of any external electric-field, the sum of the various space charges induced is zero, in order to maintain the overall charge neutrality of the device[2.30]. Moreover, the polarization dipoles (± σpol) induced are of equal magnitude and opposite in sign and thus the net contribution of total polarization charges is exactly zero. The modulation doping in the AlGaN barrier ionizes some of the dopants (σAlGaN) and contributes to the formation of 2DEG (ns). Therefore, the charge balance equation under equilibrium conditions can be expressed by[2.30]: 63 states that the total number of electrons in the 2DEG region can be given by the sum of ionized dopants in the AlGaN barrier and the ionized surface donors (σsurface).

Fig. 2 . 10 .Fig. 2 . 11 .

 210211 Fig. 2.10. Band diagram of a conventional AlGaN/GaN HEMT illustrating various space charges [2.30].

Fig. 2 .Fig. 2 .Fig. 2 . 15 .Fig. 2 . 16 .

 22215216 Fig.2.13 (a). For barrier thicknesses less than 20 nm, no channel formation occurs. The corresponding electron and hole density as a function of AlGaN barrier thickness (d) under zero-bias conditions is shown in Fig.2.13 (b). It is clear that when the AlGaN barrier thickness is less than critical thickness (dCR =20 nm), the surface hole density is close to zero and hence, there is no 2DEG formed in the channel region. However, the increase in AlGaN barrier thickness after the critical thickness (d > dCR) causes the linear increase in 2DEG density and eventually it saturates for larger AlGaN barrier thickness (d » dCR). This confirms that for the ideal surface HEMT structure, the 2DEG density formed at the AlGaN/GaN hetero-junction interface is due to the accumulation of holes at the surface.

  (a). The polarization charges for various Al mole fraction (m) has been calculated based on Ambacher[2.6] method and are used in the simulations. The value of σ1 is calculated as 1.0× 10 13 cm -2 . The magnitude of interface charges defined at the Nitride/GaN cap interface, σ2 is -2.0× 10 12 cm -2 . Donor-like traps are introduced at the surface of the device with a concentration (NTD) of 1.0× 10 13 cm -2 and energy level of 0.2 eV below the conduction band.

Fig. 2 .Fig. 2 .Fig. 2 . 19 .

 22219 Fig. 2.17. (a) Polarization charges defined in the physical simulation (b) Simulated electron (2DEG) as a function of AlGaN barrier thickness (d) and for various m, under zero-bias conditions.

Fig. 2 . 20 . 2 . 5 .Fig. 2 .Fig. 2 . 21 . 2 . 6 .Fig. 2 . 22 .

 22025222126222 Fig. 2.20. Schematic of the conduction band diagram illustrating the influence of donors on the 2DEG density in Regions 2 and 3. If the trap energy level (ETD) lies well above EF, all donor traps are completely ionized and if ETD = EF, traps are partially ionized [2.31].

Fig 2 .Fig. 2 . 23 .

 2223 Fig 2.23 shows the simulated electron temperature inside the device for different drain bias conditions. The hydrodynamic model is more useful to study the variation of charge carrier temperature (electrons and holes) inside the device. It is evident from Fig. 2.23, at higher drain biases, the hot spot is clearly visible at the drain-side edge of the gate terminal and in the gatedrain region. The hydrodynamic simulation gives more accurate results, however the simulation time is very high and often faces the convergence issues. In this thesis, all the measurements are performed under deep class-AB operation mode, therefore, drift-diffusion simulation model is sufficient for all our analysis.

  traps and identifying the ways to minimize the influence of trapping effects on device performance is an active research area. There are various measurement techniques [3.11]-[3.18], such as deep level transient spectroscopy (DLTS), gate and drain lag transients, highvoltage transient CV, frequency dependent transconductance dispersion and low frequency noise (LFN) measurements are available to investigate the trapping behavior of the GaN HEMT devices.

8 )

 8 The process of capture and emission of these traps follows the Shockley-Read-Hall theory (SRH)[3.24]. The physical interactions between the free charge carriers and the generation/recombination mechanisms for the traps located at a particular energy level ET is shown in Fig.3.1. The four possible events that can occur for a single level traps located in the energy band of the device[3.23],[3.24]:(a) The capture of an electron by an empty trap from the conduction band with a capture probability coefficient cn and electron recombination rate Rn: The emission of an electron from the trap energy level to the conduction band with a emission generation rate Gn: The capture of hole by the occupied trap from the valence band with a hole capture probability coefficient cp and hole recombination rate Rp: The emission of a hole from the empty trap to the valence band with a hole emission probability coefficient ep and hole generation rate Gp:

Fig. 3 . 1 .

 31 Fig. 3.1. Electron and hole transition processes according to SRH theory.

Fig. 3 . 2 . 5 .Fig. 3 . 3 .Fig. 3 . 4 .

 3253334 Fig. 3.2. (a) Schematic of the pulsed I-V measurement set-up (b). Timing diagram illustrating pulsed I-V measurement principle.

3. 5 .Fig. 3 . 5 .

 535 Fig. 3.5. Schematic of the two-port LF S-parameters measurement setup using an Agilent E5061B network analyzer. Frequency range of 10 Hz to 10 MHz has been used for measurements.

Fig. 3 . 6 .

 36 Fig. 3.6. Small-signal HEMT equivalent circuit model including one trap parameters (gn, Cn).

4 eV and 1 .Fig. 3 . 7 .

 4137 Fig. 3.7. Imaginary part of the 8×75 µm device measured Y22-parameter vs. frequency for the Tchuck ranges between 25 o C and 100 o C. Bias conditions: VDS = 30 V and ID = 57 mA. (b)

Fig. 3 .

 3 Fig. 3.8 shows the variation of electron mobility and velocity as a function of electric field for

Fig. 3 . 8 .

 38 Fig. 3.8. Variation of electron mobility and velocity as a function of electric field using the

Fig. 3 . 9 .

 39 Fig. 3.9. (a) Schematic cross section of the GaN/AlGaN/GaN HEMT structure. (b) Polarization charges defined at each material interface in the TCAD simulation.

Fig. 3 .Fig. 3 . 10 .

 3310 Fig. 3.10 illustrates the influence of different calibration parameters on the 8×75 µm device simulated I-V characteristics and moreover at the end of this calibration process, the essential device parameters can be extracted. The calibration of each of the physical parameters are repeated several times in order to achieve the best match with the experimentally measured I-V characteristics.

Fig. 3 .Fig. 3 . 11 .Fig. 3 .

 33113 Fig. 3.11 (a) and 3.11 (b) show the comparison of the measured and simulated transfer and output characteristics of the 8×75 µm device at Tchuck = 25ºC.

Fig. 3 . 12 . 3 . 6 . 4 .Fig. 3 .

 3123643 Fig. 3.12. 6×75 µm device: Comparison of the simulated (solid lines) and measured (symbols) I-V characteristics. (a) Transfer characteristics at VDS = 5 V and Tchuck = 25 o C. (b) Output characteristics for varying VGS between 0 V and -4 V in steps of 0.5 V and at Tchuck = 25 o C.

Fig. 3 . 13 .

 313 Fig. 3.13. 8×75 µm device: Imaginary part of the simulated (lines) and measured (symbols) Y22-parameter vs. frequency for Tchuck = 25 o C and for different electron cross section parameters (σn). Bias conditions: VDS = 30 V and ID = 57 mA. Activation energy Ea = 0.4 eV, introduced in the simulation.

Fig. 3 .Fig. 3 . 14 .Fig. 3 . 15 . 3 . 6 . 5 .Fig. 3 . 16 .

 3314315365316 Fig. 3.14 (b) shows the Arrhenius plot extracted using the simulated Y22 parameter. The extracted trap energy level is 0.4 eV which corresponds to the acceptor trap energy level value introduced in the physical simulation. This study confirms that acceptor-like traps are present in the GaN buffer.

Fig. 3 . 17 .

 317 Fig. 3.17. Imaginary part of the simulated 8×75 µm device Y22-parameter vs. frequency for different Tchuck and with donor-like traps in the GaN buffer. Bias conditions: VGS = -1 V and VDS = 20 V. Donor-like traps in the device cause the peak amplitude increases as the device temperature increases.

Fig. 3 . 18 .

 318 Fig. 3.18. Imaginary part of the measured 4×50 µm AlN/GaN HEMT device Y22-parameter vs. frequency for different Tchuck, illustrating the existence of both acceptor and donor-like traps in the device.

  . Traps involved in GR noise are located mostly among energy states, between an energy band and a discrete trap energy level in the bandgap of the semiconductor material. Moreover, these traps are generated due to the presence of various defects or impurities in the semiconductor. The traps could either present either at the surface or interface or in the bulk of the material. A trapping-detrapping process results either in generation of excess charge carriers by 'generation' or reduction of charge carriers by 'recombination'. These process cause fluctuations in the number of charge carriers available for current transport. The trapping process also induce fluctuations in the mobility, barrier height and electric field of the semiconductor device.If there are 'N' number of charge carriers in the semiconductor device or material at equilibrium condition and if the GR process fluctuates the number of charge carriers (ΔN), the perturbation dΔN can be described by a differential equation[3.44],Where τ is the characteristic time constant (lifetime) of recombination of carriers and H(t) is the randomly generated noise source.

Fig. 3 . 19 .Fig. 3 . 20 .

 319320 Fig. 3.19. Noise Model of the transistor

Fig. 3 . 21 .

 321 Fig. 3.21. The complete setup for Noise Characterization [3.16].

Fig. 3 . 22 .Figure 3 . 22 .

 322322 Fig. 3.22. Equivalent circuit representation of LFN measurement [3.16].

Fig. 3 . 23 .

 323 Fig. 3.23. 6×75 µm device measured noise characteristics for various Tchuck ranging between 25ºC and 125ºC and under the biasing conditions of VDS = 10 V and ID = 65 mA: (a) output noise power spectral density vs. frequency and (b) output noise power spectral density multiplied by frequency.

Fig. 3 .

 3 24 shows the summary of the trap levels extracted using LF noise measurements along with the previously reported data[3.28],[3.33],[3.35]-[3.38],[3.48] by several research groups for the case of Fe-doped GaN buffer HEMT devices.The apparent activation energies of the trap levels determined are 0.57 (T1) and 0.51 (T2) eV, respectively. The corresponding cross sections determined are 4.96× 10 -15 and 2.13× 10 -16 cm 2 , respectively. The physical origin of these trap levels could be related to the Fe-doped GaN buffer. Moreover, the extracted activation energies of these trap levels are in excellent agreement with the already reported[3.33],[3.34],[3.36],[3.49] values of Fe-doped GaN HEMT devices.

Fig. 3 . 24 .

 324 Fig. 3.24. Summary of the trap levels extracted using LF drain noise measurements and previously reported literature data. Two trap levels are identified with an apparent activation energies of 0.51 and 0.57 eV, respectively.

Fig. 3 .Fig. 3 . 25 .

 3325 Fig. 3.15 (b), when the traps are uniformly distributed throughout the GaN buffer region, only the region close to the channel (approximately 0.45-µm thickness) is actively involved in trapping phenomenon. Therefore, in our noise simulations, the GaN buffer region is divided into three sections as shown in Fig. 3.25.

Fig. 3 . 26 .

 326 Fig. 3.26. Comparison of the simulated (red line) and measured (black line) LF drain noise power spectral density for different temperatures ranging between 25ºC and 100ºC. Two trap levels are introduced in the GaN buffer with an apparent activation energies of 0.51 and 0.57 eV, respectively.

Fig. 3 .

 3 Fig.3.26 shows the comparison of the simulated and measured output drain noise power spectral density (PSD) at different temperatures ranging between 25ºC and 100ºC. Good agreement has been achieved between TCAD physical simulation and measurement, confirms that these two traps are located in the GaN buffer (close to the GaN channel). This is the first time such a comparison between the simulated and measured drain noise spectral density has been reported for the GaN HEMT devices. Fig.3.27 shows the comparison of the simulated and measured output noise spectral density multiplied by frequency curve for different temperatures ranging between 25ºC and 100ºC.

Fig. 3 . 27 .

 327 Fig. 3.27. Comparison of the simulated (solid line) and measured (curvy line) LF drain noise PSD multiplied by frequency for different temperatures ranging between 25ºC and 100ºC.

Fig. 3 . 28 .

 328 Fig. 3.28. TCAD simulation results of G-R noise for various temperatures illustrating the existence of two traps in the device.

Fig. 3 .Fig. 3 . 3 . 8 . 3 . 8 . 1 .Fig. 3 .

 33383813 Fig.3.28 shows the simulated output generation-recombination noise for various temperatures, with and without involving the T1 in the simulation. It is evident from the simulation plot that T1 is visible only for temperatures greater than 50ºC whereas the second trap (T2) is noticeable at all temperatures. The T1 related dispersion in the noise characteristics occurs at very low frequencies and hence this trap is clearly observable only at higher temperatures. Fig.3.29 (a) shows the simulated output GR noise spectral density multiplied by frequency curve, considering two traps in the GaN buffer and for the temperature ranging between 25ºC and 100ºC. The Arrhenius plot for T2 is extracted using Fig.3.29 (a) and the corresponding plot is shown in Fig.3.29 (b). The extracted activation energy of T2 is 0.5 eV, corresponds to the trap energy level of 0.51 eV introduced in the GaN buffer. Therefore, this simulation study confirms that two acceptor-like traps are present in the GaN buffer. Traps with activation energy of 0.51 eV are located close to the GaN channel in the GaN buffer and the traps having an activation energy of 0.57 eV are just located below the 0.51 eV traps. Furthermore, this simulation study also demonstrates that low-frequency noise measurement is another effective tool similar to LF-admittance measurement for characterizing the traps existing in the GaN buffer.

Fig. 3 . 30 .

 330 Fig. 3.30. 6×75 µm Drain lag transient measurement using DCTS method.

Fig. 3 .Fig. 3 .

 33 Fig. 3.31. (a) Simulated dc-IV drain current characteristics of 6×75 µm device, by considering the different concentration of traps in the device structure (b) transient drain current characteristics by considering the different cases of traps. Blue line with round symbol indicates there are no traps in the device. Green line with triangle symbol shows the case of traps existing only in the AlGaN barrier. Black line with square symbol shows the transient characteristics with traps existing in both the AlGaN barrier and GaN buffer. Red line shows the case of traps only in the GaN buffer. Surface donors exist in all the aforementioned cases.

Fig 3 .Fig. 3 . 32 .

 3332 Fig. 3.32. Simulated dc (a) and transient (b) drain current characteristics of 6×75 µm device, with and without the surface donors. Buffer traps exist in both cases and it is confirmed that slow transient observed is due to GaN buffer traps.

Fig. 3 . 33 .

 333 Fig. 3.33. Simulated transient drain current characteristics of 6×75 µm device. Deeper the level of buffer traps, larger the time required to attain the steady state drain current.

Fig. 3 .Fig. 3 . 34 .Fig. 3 . 35 .

 3334335 Fig. 3.33 shows the transient simulation characteristics of the device by considering one trap level in the GaN buffer region and with two different energy levels. The trap concentration is assumed to be 5.0× 10 16 cm -3 , respectively. The simulation result demonstrates that buffer traps with an energy level of 0.4 eV has the smaller emission time constant compared to 0.5 eV. Therefore, deeper the trap energy level, more the possibility of ionization of acceptor traps, larger the time required to attain the steady state drain current.

Fig. 3 .Fig. 3 . 36 .Fig. 3 . 37 .

 3336337 Fig. 3.36. Schematic of the GaN/AlGaN/GaN HEMT used for transient gate lag simulations.

  author would like to thank Mr. Julien Couvidat, Ph.D student and Dr. Ahmad Al. Hajjar, Post-doctorate, XLIM Laboratory, University of Limoges, France for providing measurement results used in this chapter. Characterization of AlN/GaN/AlGaN HEMTs grown on Si and SiC Substrate through On-wafer Measurements and TCAD-based Physical Device Simulations 4.1. Systematic Study of Traps in AlN/GaN HEMTs using Numerical Simulation 4.1.1. Introduction

Fig. 4 . 1 .

 41 Fig. 4.1. (a) Cross section of an AlN/GaN/AlGaN HEMT used for simulation (b) Simulated energy band diagram under equilibrium condition.

  2 eV above the mid bandgap are introduced at the AlN/SiN interface. Electron (σn) and hole (σp) capture cross sections are assumed to be σn = σp = 1.0× 10 -15 cm 2 , respectively. For the simulation, constant mobility and field dependent mobility models are included for electrons and holes and Shockley-Read-Hall recombination model is used for carrier generation and recombination. The summary of the material parameters used in the simulations are listed in Table 4.1. The energy band diagram of the simulated structure under equilibrium condition is shown in Fig. 4.1 (b). In order to analyze the device characteristics, the simulation model needs to be properly calibrated to ensure that the simulated characteristics are in agreement with the experimentally measured characteristics. The calibration process initiates with fitting the pinch-off in simulation to experiment by adjusting the Schottky gate work function (4.25 eV). Then, by using the low field mobility and saturation velocity parameters of GaN material, the linear and saturation region drain current characteristics are calibrated. More details about the TCAD simulation model calibration process is given in Chapter 3 (section 3.6.1 -3.6.3). Fig. 4.2 (a) shows the comparison of the simulated and measured transfer and transconductance characteristics of the 2×100 µm device at drain-source bias voltage, VDS = 5 V and temperature, T = 25ºC. Fig. 4.2 (b) shows the simulated and experimental dc-output characteristics for gatesource bias voltage, VGS values varying from -2.5 V to 0.0 V in steps of 0.5 V. A good agreement between the simulation results and experimental data confirms the validity of the calibrated physical model. It is worthwhile to note that no traps are used in the device structure while performing the calibration of the simulation model. This will allow us to analyze the impact of different traps on device performances.

Fig. 4 . 2 .

 42 Fig. 4.2. Comparison of 2×100 µm AlN/GaN HEMT device measurement (symbols) and simulation (solid lines) results: transfer and transconductance characteristics at VDS = 5 V (a)

Fig. 4 . 3 .Fig. 4 . 4 .

 4344 Fig. 4.3. Impact of type of traps and its associated energy level in the energy band diagram.

Fig. 4 .Fig. 4 . 5 .

 445 Fig. 4.5 (a) and 4.5 (b) show the energy band diagram of the device with either acceptor or donor traps present in the GaN channel (a vertical cut is made in the gate-drain region, X = 1.35 µm, close to the gate end), whose trap energy level is 2.85 eV below the conduction band and the assumed trap concentration is 5.0× 10 17 cm -3 . The trap energy level (ET) lies well below EF for both cases under the biasing conditions of VDS = 5V and VGS = -1 V.

Fig 4 . 6

 46 shows the energy band diagram of the device with donor traps, having an energy level of 0.3 eV below the conduction band and for the biasing conditions of VDS = 5V and VGS = -4 V. It can be seen that ET lies above EF, causing ionization of donor traps introduced in the GaN channel of the device. Therefore, it can be concluded that donor traps will ionize only at high negative gate biases and only when the trap energy level is shallow inside the bandgap and thus, donor traps have no significant influence on the simulated dc-IV characteristics.

Fig. 4 . 6 .

 46 Fig. 4.6. Simulated energy band diagram of the device by considering donor traps in the GaN channel whose trap energy level is 0.3 eV below the conduction band. Biasing conditions: VDS = 5V and VGS = -4 V.

Fig. 4 .Fig. 4 . 7 .Fig. 4 . 8 .

 44748 Fig. 4.7 shows the probability of traps occupation as a function of device distance inside the GaN channel and for various ETA. It is evident that deeper the energy level of acceptor traps, larger the region of ionization of traps inside the GaN channel and thereby larger the reduction in drain current.

Fig. 4 .

 4 Fig. 4.8 (a) and 4.8 (b) show the electron density in the channel region as a function of horizontal (cut is made along the AlN/GaN interface) and vertical (cut is made in the gate-drain region, close to the gate end) device distance, for various acceptor traps energy level. As expected, deeper the trap energy level, larger the ionization of acceptors, larger the reduction of electrons in the channel.

Fig. 4 .

 4 Fig. 4.9 shows the electron density in the channel region as a function of horizontal (cut is made along the AlN/GaN interface) device distance and for various donor traps energy level. The donor traps remains unionized for the biasing conditions of VDS = 5V and VGS = -1 V and hence, the electron density in the channel remains the same, irrespective of the introduced donors.

Fig. 4 . 9 . 4 . 2 . 4 . 2 . 1 .

 4942421 Fig. 4.9. Simulated electron density in the channel as a function of horizontal device distance and for various donor traps energy level. Biasing conditions: VDS = 5V and VGS = -1 V.

[ 4 .

 4 19]-[4.24] for the temperature dependent characterization of AlGaN/GaN HEMT technology. However, as this AlN/GaN/AlGaN HEMT technology is relatively new, there has been little research on this device technology[4.25],[4.26]. The aim of this section of the chapter, is to contribute to the temperature dependent RON extraction[4.27] of AlN/GaN/AlGaN HEMT technology using on-wafer measurements and TCAD based device simulations.

  activated and contributes to dynamic RON. Therefore it is useful to analyze the impact of dynamic RON on device performance due to traps[4.15],[4.28],[4.29]. Moreover, the accurate modeling of trapping effects can significantly improve the performance of large signal model (LSM) and this is particularly important for designing high power RF amplifiers [4.30]-[4.32].4.2.2. DC MeasurementsOn-wafer DC-IV measurements are performed for different geometries of AlN/GaN/AlGaN HEMTs grown on SiC substrate. The measurements have been carried out at different chuck temperatures (Tchuck) between 0 o C and 150 o C using an Agilent B1500A semiconductor device parameter analyzer (SDA). Fig. 4.10 (a) and 4.10 (b) show the measured DC-IV output characteristics of the 2×100 µm device with LG =0.2 µm, LSG =0.4 µm and LGD = 2 µm. The output characteristics are shown for different VGS between 1.0 V and -1.0 V for a chuck temperature (Tchuck) of 25 o C and for various Tchuck between 0 o C and 150 o C at VGS =1.0 V, respectively. The derivatives are calculated from the measured ID-VDS curve at the point where the gate-source voltage, VGS equals drain-source voltage, VDS. The corresponding RON [= 1/ (dID/dVDS)] is extracted within the ohmic region of the measured IV characteristics.

  have been carried out using an Agilent E5061B network analyzer. The photograph of the device under test (DUT) and the LF measurement setup is shown in Fig. 4.11 (a).

Fig. 4 . 10 .Fig. 4 .

 4104 Fig. 4.10. Measured DC-IV output characteristics (ID-VDS): (a) for different VGS bias between 1.0 V and -1.0 V at Tchuck = 25 o C. (b) for different Tchuck between 0 o C and 150 o C at VGS = 1.0 V. Device dimensions: WG = 2×100 µm, LG =0.2 µm, LSG =0.4 µm, and LGD = 2 µm.

Fig. 4 .

 4 Fig. 4.11 (b) shows the measured real part of Z22 parameter of the 2×100 µm device for different Tchuck ranging between 0 o C and 150 o C at VGS =1.0 V, respectively. The corresponding RON is determined as a function of VGS and Tchuck, using the real part of the Z22 parameter.

Fig. 4 . 12 . 4 . 2 . 5 .Fig. 4 . 13 .

 412425413 Fig. 4.12. Comparison of the simulated (solid lines) and measured (symbols) DC-IV output characteristics: (a) for different VGS biases between 1.0 V and -1.0 V at Tchuck = 25 o C. (b) for different Tchuck between 0 o C and 150 o C at VGS = 1.0 V. Device dimensions: WG = 2×100 µm, LG =0.2 µm, LSG =0.4 µm, and LGD = 2 µm.

(4. 7 )Fig. 4 . 14 .

 7414 Fig. 4.14. Structure of the transistor showing the series contact resistance Rse (= Rs + Rd) and channel resistance Rch [4.38].

Fig. 4 . 15 .

 415 Fig. 4.15. Flowchart for extracting channel sheet resistance (Rsh) and series contact resistance (Rse).

4. 2 . 7 .Fig. 4 . 16 .

 27416 Fig. 4.16. LF S-parameters measurement at Tref = 0 o C and VGS = 1 V: extraction of dRON/dT [(a), (b) and (c)] for different gate-drain distance, LGD = 1, 2 and 3.0 µm, respectively, extraction of dRsh/dT (d) and Extraction of Rsh and Rse : at VGS = 1 V (e) and 0 V (f). Device dimensions: WG = 2×50 µm, LG =0.2 µm, LSG =0.4 µm, and LGD = 2 µm.

Fig. 4 . 17 .

 417 Fig. 4.17. Extracted (a) channel sheet resistance Rsh and (b) series contact resistance Rse as function of VGS and Tchuck using LF measurements. Device dimensions: WG = 2×50 µm, LG =0.2 µm, LSG =0.4 µm, and LGD = 2 µm.

Fig. 4 . 18 .

 418 Fig. 4.18. TCAD dc-IV simulation at Tref = 0 o C and VGS = 1 V: extraction of dRON/dT [(a), (b) and (c)] for different gate-drain distance, LGD = 1, 2 and 3.0 µm, respectively, extraction of dRsh/dT (d) and Extraction of Rsh and Rse : at VGS = 1 V (e) and 0 V (f). Device dimensions: WG = 2×50 µm, LG =0.2 µm, LSG =0.4 µm, and LGD = 2 µm.

4 . 3 .Fig. 4 . 19 .

 43419 Fig. 4.19. Extracted (a) channel sheet resistance Rsh and (b) series contact resistance Rse as function of VGS and Tchuck using TCAD simulations.

  numerical simulation results for the on-resistance extraction of 2×100 µm device. A good agreement is achieved between the simulated and extracted RON for the temperature range of 0 o C to 150 o C. Then, we have proposed a simplified methodology to extract the temperature dependence of series contact resistance and channel sheet resistance of GaN based HEMTs.The proposed methodology has been successfully applied on 2×50 µm AlN/GaN/AlGaN HEMT devices, for various gate-source bias voltages and the corresponding Rsh (T) and Rse (T) are extracted. Two-dimensional TCAD device simulations have been also carried out for the same device dimensions and the temperature dependency of channel and contact resistances are extracted.

Fig. 5 . 1 .

 51 Fig. 5.1. Pulsed I-V measurement setup: (a) calibration step and (b) measurement step.

Fig. 5 .Fig. 5 . 2 .Fig. 5 . 3 .Fig. 5 . 4 .Fig. 5 . 5 .

 552535455 Fig. 5.2 and Fig. 5.3 show the pulsed I -V measurement characteristics of the 2×25 µm HEMT device grown on Si and SiC substrates as a function of Pdiss and Tchuck. Similar measurements have been performed for 2×50 µm and 2×100 µm devices grown on Si substrate and the corresponding RON has been extracted.

Fig. 5 . 6 .

 56 Fig. 5.6. Extracted RTH as a function of device width for AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrate.

  has been consistently used for all our simulations. Therefore, thermal simulations presented in this chapter also utilizes TCAD Sentaurus tool. It provides an efficient way of analyzing the heat diffusion mechanism, as heat is generated self-consistently within the device. In general, the TCAD simulation model can solve self-consistently the basic Poisson's equation along with the lattice heat flow equation. In this work, instead of solving the Poisson's equation to generate the heat dissipation inside the device, we have assumed an external heat source across the channel region to generate the required heat dissipation. The current density (Jn,p) involving temperature gradient, electron and hole quasi-Fermi potential can be expressed as[5.14]: Jn,p = nqµn,p(n,p + Pn,pT). Here µn,p represent the electron and hole mobilities, Φn,p is the quasi-Fermi potential for electrons and holes respectively and Pn,p represent the absolute thermoelectric power. The second term appears due to the non-uniform distribution of temperature inside the device. This gives rise to the current flow owing to the temperature gradient. The temperature distribution due to the self-heating can be calculated by solving the following lattice heat flow equation[5.14]:

5. 6 .

 6 Thermal Resistance (RTH) Extraction Using TCAD Simulations 5.6.1. Device Structure The physical structure of the AlN/GaN/AlGaN HEMTs grown on Si,SiC or sapphire substrate is shown in Fig. 5.7. The enlarged view detailing the different regions of the device is shown in Fig. 5.8 (a). The device structure is symmetric with respect to X-axis and therefore half of the device structure is used for simulations. The device has been placed on a semi-infinite Si, SiC or sapphire block and the thickness of the Si/SiC/sapphire-block is assumed to be same as the wafer thickness. The device is composed of several layers as shown in Fig. 5.8 (b). The device has two fingers, with source length (LS) of 24 µm, gate-source separation (LSG) of 0.4 µm, gate length (LG) of 0.2 µm, gate-drain distance (LGD) of 2.0 µm and drain length (LD) of 13.36 µm respectively. The simulations are performed for three device widths, WG of 25, 50 and 100 µm, respectively. The heat source is placed at the interface between AlN barrier and GaN channel region, whose length (LHS) is assumed to be twice the gate length of the device.

Fig. 5 . 7 .Fig. 5 . 8 .

 5758 Fig. 5.7. Half of RF test structure of AlN/GaN/AlGaN HEMT grown on Si/SiC/Sapphire substrate.

Fig. 5 . 9 .

 59 Fig. 5.9. Mesh refinement in TCAD thermal simulation: (a) complete device structure (b) region around the heat source.

Fig. 5 . 10 .

 510 Fig. 5.10. Lattice (TLattice) and peak temperature variation for different LHS in Si substrate.

Fig. 5 . 11 .

 511 Fig. 5.11. Lattice temperature distribution at steady state condition for the applied DC power of 0.125 W per heat source of AlN/GaN/AlGaN HEMT on (a) Sapphire, (b) Si and (c) SiC substrate and with device width, WG = 2×25 µm.

Fig. 5 . 12 .

 512 Fig. 5.12. Lattice temperature variation along the transverse direction, X (a) and Y (b) through the middle of heat source in AlN/GaN/AlGaN HEMT on different substrates, with WG = 2×25 µm and for the applied dc power of 0.25 W).

Fig. 5 .

 5 Fig. 5.13. (a) Comparison of extracted RTH as a function of device width, WG between measurements and TCAD simulations for the AlN/GaN/AlGaN HEMT devices grown on different substrates (b) Extracted RTH as a function of gate length, LG and for various geometries of device.

Fig. 5 . 14 . 5 . 3 .

 51453 Fig. 5.14.Table 5.3. Analogy between thermal and electrical parameters.

Fig. 5 . 14 .

 514 Fig. 5.14. Electrical transmission line equivalent circuit for modeling thermal conduction.

Fig. 5 .

 5 Fig. 5.15. (a) A single pole electro-thermal network (b) Foster networkgeneralized thermal equivalent circuit.

Fig. 5 . 16 .

 516 Fig. 5.16. Electro-thermal Cauer network.

Fig. 5 . 17 . 5 . 7 . 3 .Fig. 5 . 17 .Fig. 5 . 18 .

 517573517518 Fig. 5.17. Modified recursive network.

Fig. 5 .Fig. 5 . 20 .

 5520 Fig. 5.20. 3D-TCAD thermal simulation and recursive thermal modeling of AlN/GaN/AlGaN HEMTs grown on SiC substrate. (a) 2×25µm (b) 2×50µm and (c) 2×100µm (d) Simulated

  due to the existence of defects/traps in the device which significantly degrade their performance. The presence of traps in the device causes different degradation mechanisms such as current collapse, transconductace dispersion, admittance dispersion, gate-lag, drain-lag, increased gate leakage and low frequency noise. The focus of this thesis work is to characterize the different aspects of GaN/AlGaN/GaN HEMT and AlN/GaN HEMT device technology using experimental characterization and TCAD-based physical device simulations. The research work presented in this thesis would benefit other members of the GaN HEMT community in order to completely understand the trapping mechanisms, particularly buffer related trapping effects, and also other important characteristics such as on-resistance (RON) and thermal-resistance (RTH) of these GaN HEMT devices. Moreover, this research study could also provide an efficient feedback for further improving the GaN HEMT device technology and its respective RF performance.Chapter 1 discussed the potential of GaN material in comparison with other semiconductor materials which makes them as an extremely powerful candidate for high power microwave and mm-wave applications. The brief history of evolution of GaN-based HEMT devices and the technological developments reported over the years, and the corresponding obtained improved device performances have been described in detail. Moreover, the performance of conventional AlGaN/GaN HEMT devices have been limited by the use of ultra-short gate lengths and ultra-thin AlGaN barrier. This give rise to AlN/GaN HEMT devices and also considered to be a suitable alternative to replace AlGaN/GaN HEMT devices. The polarization mechanisms and the theory of device operation, implementation of field-plates to improve the RF performance have been explained. Furthermore, the degradation mechanisms of GaN HEMTs such as current collapse, gate-lag, drain-lag, self-heating, and gate-edge degradation have been illustrated with the aid of theoretical diagrams. Although the scope of this thesis work is not to characterize the gate leakage mechanisms of GaN HEMT devices, it is however essential to understand the influence of gate leakage on device performance. The different tunneling mechanisms used to characterize the gate leakage have been described. Chapter 2 presented the physics based analytical modeling of current-voltage characteristics of AlGaN/GaN HEMT devices. The theoretical method used for estimating the Al-mole fraction (m) dependent polarization charges and the necessary analytical equations have been provided. A simple analytical model for estimating the sheet carrier density (ns) has been explained. The analytically calculated sheet carrier density as a function of gate voltage (VGS) and Al-mole fraction (m), are validated using our numerical simulation results. Then, a simple analytical model valid for calculating both intrinsic and extrinsic current-voltage characteristics of AlGaN HEMT device has been presented. The intrinsic HEMT model characteristics have been verified using TCAD simulation results, and an excellent agreement is achieved between analytical model and TCAD simulation. The extrinsic HEMT device characteristics have been validated using experimental results reported in the literature and in-house measured device characteristics. For long channel devices with different device dimensions, the proposed analytical model achieves a reasonable agreement with experimental characteristics. However for short channel device, the proposed model results show a large discrepancies with in-house measured characteristics. This is due to the proposed model does not consider short channel effects and channel length modulation which has large influence on the performance of submicron gate length devices. The second part of the chapter 2 describes the TCAD Sentaurus simulation methodology used in this thesis work. A brief overview of the TCAD Sentaurus simulation platform, with a brief description of the simulation tools utilized and different kinds of simulation models available has been provided. The basic theory of the formation of two dimensional electron gas (2DEG) sheet density in AlGaN/GaN heterostructure has been explained using theoretical diagrams and TCAD simulations. It is clear from the simulation results, for the case of ideal surface and when the AlGaN barrier thickness (d) is less than critical thickness (dCR), there is no 2DEG channel formation occurs at the AlGaN/GaN hetero-junction interface. However, the increase in AlGaN barrier thickness, d > dCR, causes the accumulation of electrons at the AlGaN/GaN interface and the corresponding holes are accumulated at the surface. This simulation study proves the theoretical fact that for the case of ideal surface, the 2DEG sheet density is formed only due to the accumulation of holes at the surface of the device. Furthermore, the influence of donor density and energy level in the formation of 2DEG sheet density have been studied. The three regions have been identified as the surface donor density and its associated energy level are varied. In Region 1, the surface donor density has negligible influence on the 2DEG sheet density whereas in Region 2, the 2DEG sheet density increases linearly with donor density and is independent of the energy level. However, in Region 3, the surface donor's energy level has a strong influence on 2DEG sheet density and the donor density has negligible influence. The comparison of different kinds of simulation model have been explained. Moreover, the driftdiffusion (DD) and hydrodynamic (HD) model achieves the same result at lower gate biases. This thesis work is primarily focused on characterizing the devices under class AB operation as this mode of operation is widely preferred for designing RF power amplifiers. Therefore, the simulation result suggested that DD model is sufficient for all our analysis and therefore, DD model is used for rest of the TCAD simulation results presented in this thesis. Chapter 3 investigates the trapping mechanisms of GaN/AlGaN/GaN HEMT transistors using experimental characterization and TCAD-based physical simulations. The different types of device characterization techniques such as pulsed I-V, LF-S parameters and LF noise bench have been described. The LF S-parameters measurement has been performed on 8×75µm device under deep class-AB operation mode and the measured S-parameters are converted into their equivalent Y-parameters. The traps existing in the GaN buffer cause the frequency dispersion in the output admittance Y22 parameter. Moreover, the emission time constant (τn)changes with measurement temperature and therefore, the emission time constant is calculated at each temperature and then by using Arrhenius law, the apparent activation energy (Ea) and apparent cross section of traps (σn) have been determined. The thermal resistance (RTH) of the device has been found to be 20.42 °C/W and used in the extraction of trap parameters. The extracted activation energy and cross section of the traps are 0.4 eV below the conduction band and 1.89× 10 -16 cm 2 , respectively. In order to understand the physical origin of this traps, a comprehensive analysis of the traps reported in the literature has been studied. This study suggested that the origin of this traps could be related to the iron doping present in the GaN buffer. However, in order to understand the physical location of traps, two-dimensional TCAD physical simulations have been used. In order to make physical simulations meaningful, it is essential to calibrate the TCAD simulation model in order to reproduce the measured data. The calibration process of TCAD simulation model has been explained. The simulation model has been calibrated for both 8×75 and 6×75-µm devices respectively, and are used for rest of the analysis presented in this chapter. Using the calibrated TCAD simulation model, LF admittance Y22 parameter simulation has been carried out using the same measurement biasing conditions.The junction temperature (Tj) has been estimated based on the known values of RTH, Tchuck and power dissipation (Pdiss), and are used in simulations. Moreover, the acceptor traps concentration (NTA) of 5.0× 10 16 cm 3 and σn value of 3.2× 10 -18 cm 2 has been used. A good agreement between the TCAD simulations and measurement Y22 parameter confirms the existence of acceptor-like traps in the GaN buffer. To the best of our knowledge, this is the first time that such a comparison between the physical simulation and measurement parameter has been reported for the GaN HEMT technology. Moreover, if the donor traps are existing in the GaN buffer, the simulated Y22 parameter does not show the frequency shift as the temperature increases, instead the peak amplitude increases with temperature. This type of behavior has been observed in our AlN/GaN HEMT devices. Therefore, we suggest that LF admittance measurement is an effective tool for characterizing the traps present in the GaN buffer. In case, if the traps are existing in the AlGaN barrier, this particular measurement technique could not be useful for detecting the traps and this has been validated using our TCAD simulations. Then, LF noise measurements has been carried out on 6×75µm device and the respective traps physical properties such as Ea and σn of the device have been extracted. Two traps have been identified and the apparent activation energies of the traps determined are 0.57 and 0.51 eV, respectively. The corresponding cross sections determined are 2.13× 10 -16 and 4.96× 10 -15 cm 2 , respectively. The extracted activation energies of these traps are in excellent agreement with the Fe-doped GaN HEMT devices. In order to physically confirm the location of these traps, TCAD simulations have been carried out by including these traps in the GaN buffer close to the GaN channel region. The total GaN buffer is divided into three regions and these two traps are introduced in the first two regions of GaN buffer. T2 with an activation energy of 0.51 eV are introduced in the first region and T1 having Ea of 0.57 eV are introduced in the second region of the GaN buffer, respectively. A good agreement has been achieved between TCAD simulation and measurement drain noise spectral density physically confirms that these two traps are located in the GaN buffer. This is the first time that such a comparison of noise characteristics has been reported for GaN HEMT devices. Moreover, it is concluded from the simulation results, T1 related dispersion in the noise characteristics occurs at very low frequencies and hence this trap is clearly visible only at higher operating temperatures.Furthermore, this study also suggest that low frequency noise measurement is another effective tool for characterizing the traps existing in the GaN buffer. The time-domain drain-lag characterization has been performed on 6×75µm device and the measured transient drain current characteristics shows a slow recovery of drain current with a relative long time constant, confirms the existence of traps in the device. The TCAD transient simulation result concludes that traps existing in the GaN buffer are responsible for the drain-lag phenomenon observed in measurement. Therefore, the simulation results presented in this chapter establish a correlation with measurements in order to identify the physical location of traps in the device and also very useful to validate the measurement methodology.The first part of the chapter 4 investigates the influence of GaN channel traps on the performance of AlN/GaN/AlGaN HEMT device through two-dimensional TCAD numerical simulations. The physical properties of the traps used in the study have been taken from the literature data. The TCAD simulation model is calibrated for 2×100µm device using the experimentally measured dc I-V characteristics. A good agreement has been achieved between the TCAD simulation and measured I-V characteristics confirms the validity of the calibrated physical model. The calibrated simulation model is used for analyzing the device characteristics by including different types of traps in the GaN channel. The simulation results demonstrate that acceptor-like traps whose energy level lies deep inside the conduction band causes a significant reduction of drain current and also the shift of pinch-off voltage of the device.

Table 1 . 1 .

 11 Typical comparison of physical properties of semiconductors for RF/microwave power applications [1.19]. ....................................................................................................

Table 1 . 2 .

 12 Summary of different substrate materials properties used for GaN devices. .........

Table 2 . 1 .

 21 Aluminum mole fraction dependent parameters of AlGaN for estimating polarization charge. ..................................................................................................................................

Table 2 . 2 .

 22 Constant parameters of Fermi level model at 298 K. ............................................

Table 3 . 1 .

 31 Summary of the deep levels (traps) reported in the literature for Fe-doped GaN devices. ..............................................................................................................................

Table 3 . 2 .

 32 Summary of the material parameters used in TCAD simulations........................

Table 4 . 1 .

 41 Summary of the material parameters used in TCAD simulations........................

Table 4 . 2 .

 42 Resistances and derivatives at different VGS using LF S-parameter measurements. ...........................................................................................................................................

Table 4 . 3 .

 43 Resistances and derivatives at different VGS using TCAD simulations. ...............

Table 1 . 1 .

 11 Typical comparison of physical properties of semiconductors for RF/microwave power applications[1.19].

	Parameter	Si	GaAs	4H-SiC GaN	Significance
	Band gap (eV)	1.1	1.42	3.26	3.39	High operating voltages; High temperature operation
	Electron Mobility (cm 2 /V.s)	1350 8500	700	1200	High DC gain; High operating frequency
	Dielectric Constant	11.8	13.1	10	9.0	Lower capacitance and it reduces the parasitic delay.
	Breakdown					Higher operating voltage; High
	Electric field	0.3	0.4	3.0	3.3	output impedance; Ease of
	(M.V/cm )					impedance matching
	Electron saturation velocity, Vsat (10 7 cm/s)	1.0	1.0	2.0	2.5	High output current density; High DC gain
	Thermal conductivity (W/cm.K)	1.5	0.43	3.3-4.5 1.3	Smaller die size; Efficient heat dissipation
						Smaller the difference in the
	Lattice constant (Å)	5.4	5.7	3.1	3.2	lattice constant between GaN and SiC (substrate) reduces the
						density of defect.
						Determines the power-
	JM	1	2.7	20	27.5	frequency limits of the
						material

  voltage of the device[1.39]. The break down voltage can be further increased by implementing the field plate structure for the gate region of the device[1.41]. A field plate is a metal plate, placed over the gate region and extended towards the drain region, in order to sustain the uniform electric field in the device structure, especially at the gate-drain edge and thereby

	reduces the degradation issues. The field plate also has a significant role in determining the
	large signal performance of the device.
	Two different types of field plate structure can be found in the literature namely the gate and
	the source connected field plates [1.19], [1.42], [1.43]. The cross section of gate and source
	connected field plate structure is shown in Figure 1.8. The gate field plate can be constructed
	either as a part of the gate (or) connected to the gate by an external means. The introduction of
	gate field plate improves the breakdown voltage of the device but it imposes the additional
	problem of increased gate-drain feedback capacitance (Cgd) and this causes the reduction of

small signal power gain and the maximum cut-off frequency of the device

[1.43]

. Whereas in case of source connected field plate structure, the field plate to channel capacitance contributes to the drain-source capacitance, which avoids the increase of Cgd and hence it provides improved small signal gain performance

[1.43]

.

Table 1 .2. Summary

 1 of different substrate materials properties used for GaN devices.

Thermal conductivity at 300 K (W/ cm. K) Lattice mismatch to GaN (%) Thermal expansion coefficient mismatch (%) Wafer cost

	Silicon Carbide (SiC)
	SiC is the most suitable substrate for GaN devices, since the lattice mismatch between GaN and
	SiC material is < 4%. It has the high thermal conductivity (4.55 W/cm. K) which is crucial for
	high power applications, and also relatively low thermal expansion coefficient (TEC)
	mismatch. The density of dislocations when the layer of GaN is grown over SiC substrate is
	under 10 8 cm -2 . SiC is generally considered to be the best material for producing powerful
	electronic devices and also the appealing choice of substrate for commercial GaN RF
	applications. Unfortunately, SiC substrate is expensive.
	GaN	1.3	0	0	Very expensive
	SiC	4.55	3.5	25	Expensive
	Sapphire	0.35	14 -23	34	Moderate
	Si	1.54	17	56	Less expensive

Table 2 . 1 .

 21 Aluminum mole fraction dependent parameters of AlGaN for estimating polarization charge [2.6].

Table 2 . 2 .

 22 14 , 2 × 10 15 and 2 × 10 16 atoms per m 2 at a constant room temperature of 298 K are given in Table 2.2. Constant parameters of Fermi level model at 298 K.

	Parameter	Value	Unit
	K1	-0.12562	eV
	K2	1.86342 × 10 -9	eV.m
	K3	1.0854 × 10 -18	eV.m 2

Table 3 . 1 .

 31 Summary of the deep levels (traps) reported in the literature for Fe-doped GaN devices.

	Reference	Activation	Cross	Trap	Growth	Analyzed samples	Measurement	Interpretation of
		Energy (eV)	Section	Concentration	technique		Technique	traps
			(cm 2 )	(cm -3 )
	Umano-	0.21	3.6 × 10 -17	3.1 × 10 13	MOCVD	n-GaN flims (lightly	DLTS	Also found in HVPE
	Membreno					Si doped GaN/Fe-		and RMBE GaN
	[3.31]					doped GaN buffer		layers
	Olena [3.32]	0.23	-	-	MBE	GaN sample	Cathodoluminescence	Fe-doped GaN
							(CL) measurements
	Heitz [3.29]	0.34	-	-	HVPE	GaN samples	Photoluminescence	Fe-doped GaN
							excitation (PLE)
	Olena [3.32]	0.36	-	-	MBE	AlGaN/GaN sample	Cathodoluminescence	Fe-doped AlGaN
						(Al =0.2)	(CL) measurements
	Chini [3.30]	0.37 -0.42	-	-	MOCVD	AlGaN/GaN/SiC	Drain current turn-on	GaN buffer
						HEMTs (Fe-doped)	transient measurement
	Umano-	0.535	2.0 × 10 -16	2.7 × 10 14	MOCVD	n-GaN flims (lightly	DLTS	Nitrogen antisite
	Membreno					Si doped GaN/Fe-		defect
	[3.31]					doped GaN buffer
	Axelsson [3.33] 0.54 -0.63	-	-	MOCVD	AlGaN/GaN HEMTs	Drain current	Traps located in the
						(Fe-doped GaN	Transient	GaN, whose physical
						Buffer)	Measurements (DCTS)	properties are
								influenced by Fe-
								doping

Table 3 . 2 .

 32 Summary of the material parameters used in TCAD simulations.

	Material Property	Units	GaN	AlGaN
	Electron Mobility	cm 2 /V s	1200	300
	Bandgap	eV	3.50	4.39
	Relative permittivity	-	8.9	8.8
	Electron affinity	eV	4.0	3.41
	Electron saturation velocity	cm/s	2.5× 10 7	1.1× 10 7
	Effective conduction band	cm -3	2.23× 10 18	2.71× 10 18
	density of states
	Effective valence band	cm -3	2.51× 10 19 2.06 × 10 19
	density of states

Table 4 . 1 .

 41 Summary of the material parameters used in TCAD simulations.

	Material Property	Units	GaN	AlN
	Electron Mobility	cm 2 /V s	1000	300
	Bandgap	eV	3.42	6.12
	Relative permittivity	-	9.5	8.5
	Electron affinity	eV	4.0	1.84
	Electron saturation	cm/s	9.0 × 10 6	1.5 × 10 7
	velocity
	Effective conduction	cm -3	2.24 × 10 18 4.1 × 10 18
	band density of states
	Effective valence band	cm -3	2.51 × 10 19 2.84 × 10 20
	density of states

Table 4 . 2 .

 42 Resistances and derivatives at different VGS using LF S-parameter measurements.

			Resistances at Tref = 0 o C and dR/dT
	VGS (V)
		Rsh (/□) dRsh/dT Rse (-mm)	dRse/dT
	-1.0	302	1.81	2.34	0.0060
	-0.5	300	1.82	2.25	0.0054
	0.0	298	1.80	2.21	0.0052
	0.5	297	1.77	2.20	0.0051
	1.0	296	1.75	2.19	0.0051

Table 4 . 3 .

 43 Resistances and derivatives at different VGS using TCAD simulations.

			Resistances at Tref = 0 o C and dR/dT
	VGS (V)
		Rsh (/□) dRsh/dT Rse (-mm)	dRse/dT
	-1.0	304	2.36	2.71	0.0067
	0.0	299	2.02	2.65	0.0056
	1.0	296	1.91	2.56	0.0052

  5-µm thick Al0.08Ga0.92N buffer layer, 150-nm thick GaN channel layer followed by a 6-nm ultrathin AlN barrier layer and 3-nm in-situ grown Si3N4 cap layer. Ni/Au Schottky gate contact and Ti/Al/Mo/Au metal stack for ohmic source and drain contacts were deposited directly on top of the AlN barrier layer by etching the in-situ Si3N4 layer. The devices with different gate widths, WG of 25 µm, 50 µm and 100 µm, each with two fingers (n=2) are

	fabricated on the same wafer. The gate length LG of the devices is 0.2 µm, source-gate
	separation (LSG) is fixed to 0.4 µm and gate-drain distances (LGD) is 2 µm, respectively.

Table 5 . 1 .

 51 Thermal conductivity and layer thickness of the materials used in thermal simulations.

		Thermal
	Material	Conductivity	Thickness [µm]
		[W/cm-K]
	AlN	2.85	0.006
	GaN	1.3	0.15
	AlGaN	0.4	2.5
	Si3N4	0.027	0.056
	Gold	3.15	0.256 (gate contact), 0.5 (GSG pad)
	Si	1.54	550
	SiC	4.55	550
	Sapphire	0.35

Table 5 . 2 .

 52 Ratio of thermal conductivity of different substrate materials and the associated lattice temperature obtained in thermal simulations.

Thermal conductivity ratio: Simulated lattice temperature ratio:

	K 	SiC Si		4.55 1.54		2.95	T 	Si SiC		330 300 310 300  		3
	K 	Si Sapphire		1.54 0.35		4.4	T 	Sapphire Si		422 300 330 300  		4.06
	K 	SiC Sapphire		4.55 0.35		13	T 	Sapphire SiC		422 300 310 300  		12.2

Conclusions and Scope of Future Works

List of Publications

Physics-Based TCAD Device Simulations and Measurements of GaN HEMT Technology for RF Power Amplifier Applications

Abstract: GaN High Electron Mobility Transistors (HEMTs) have demonstrated their capabilities to be an excellent candidate for high power microwave and mm-wave applications. However, the presence of traps in the device structure significantly degrades the device performance and also detriments the device reliability. Moreover, the origin of these traps and their physical location remains unclear till today. A part of the research work carried out in this thesis is focused on characterizing the traps existing in the GaN/AlGaN/GaN HEMT devices using LF S-parameter measurements, LF noise measurements and drain-lag characterization. Furthermore, we have used TCAD-based physical device simulations in order to identify the physically confirm the location of traps in the device. Moreover, our experimental characterization and simulation study suggest that LF measurements could be an effective tool for characterizing the traps existing in the GaN buffer whereas gate-lag characterization could be more useful to characterize the AlGaN barrier traps of GaN HEMT devices.

The second aspect of this research work is focused on characterizing the AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrate. We attempt to characterize the temperature-dependent on-resistance (RON) extraction of these devices using on-wafer measurements and TCAD-based physical simulations. Furthermore, we have proposed a simplified methodology to extract the temperature and bias-dependent channel sheet resistance (Rsh) and parasitic series contact resistance (Rse) of AlN/GaN HEMT devices. Further, we have made a comprehensive evaluation of thermal behavior of these devices using on-wafer measurements and TCAD-based three-dimensional (3D) thermal simulations. The thermal resistance (RTH) has been extracted for various geometries of the device using measurements and validated using TCAD-thermal simulations.