Dr Hassan Aboushady

Prof. Sayed Eid

Prof Ahmed Sultan

Dr Akram Malak

Hao Zou

Tamer Badran

Islam Eshra

Mohamed Bedir

Dr Alhassan Hadia

Keywords: smart power integrated circuits, substrate modeling, substrate noise, minority carriers, DC-DC buck converters Pragmatic substrate parasitic extraction framework 3.1 Conventional Substrate modeling components . . . . . . . . . . substrate parasitic extraction tool . . . . . . . . . . 3.4.1 AUTOMICS tool geometrical features extraction . . . . . AUTOMICS tool pre-processing stage . . . . . . . . . . . AUTOMICS tool extraction stage . . .

All praise be to God, the lord of the worlds, most Gracious, most merciful.

I would like to express my gratitude to my direct supervisor, Dr. Ramy Iskander, who selected me to pursue my PhD in LIP6. He allowed me to participate in an European project in which I got great knowledge as it comprises leading companies

Contents

Résumé Etendu en Français

Ce chapitre est un résumé étendu de la thèse, en français. Le lecteur intéressé par plus de détails pourra commencer directement par la lecture au chapitre suivant.

Introduction

De nos jours, les systèmes électroniques sont largement utilisés dans l'industrie automobile. Ces technologies sont déployées principalement pour offrir un environnement plus sûr et plus confortable au conducteur et à ses passagers. Les perspectives actuelles de l'électronique dans l'industrie automobile portent sur la connectivité des véhicules à l'internet comme une partie de l'internet des objets (IOT) et sur le contrôle des émission de CO 2 . Soulignons que la fiabilité et la durabilité des applications embarquées sont les principaux enjeux des systèmes électroniques automobiles. Les circuits intégrés de puissance intelligents sont utilisés dans l'industrie automobile, car ils intègrent sur le même substrat silicium des circuits fonctionnant sous haute tension (HT) avec ceux fonctionnant sous basse tension (BT). Ces procédés d'intégration permettent de miniaturiser les systèmes électroniques et de mettre en oeuvre plus de fonctionnalités dans les véhicules. Cependant, les phénomèmes de couplage par bruit de substrat dans les circuits intégrés de puissance intelligents est un problème important. Les concepteurs signalent des défaillances de fonctionnement dans les circuits dues au couplage par bruit de substrat au cours d'essais après fabrication. La plupart de ces échecs sont causés par la propagation des porteurs minoritaires dont le comportement n'est pas être pris en compte par les outils logiciels commerciaux actuels. Par conséquent, nous avons besoin d'étudier les techniques de modélisation de propagation de ces porteurs dans le substrat pour examiner leur aptitude à prédire un comportement aussi complexe.

La modélisation du substrat peut être divisée en deux catégories : 1) la modélisation du substrat dans les circuits comportant des signaux mixtes analogiquesnumériques et fonctionnent sous basse tension (AMS) et 2) la modélisation du substrat dans les circuits fonctionnent sous haute tension. Dans les circuits xxiii AMS, la principale source de bruit de substrat est le circuit de commutation numérique qui provoque l'injection de porteurs minoritaires et majoritaires dans le substrat. L'injection de porteurs peut perturber le fonctionnement des circuits analogiques sensibles aux variations de tension. Pour étudier ces phénomèmes, le substrat a été modélisé comme un réseau de résistances et capacités [START_REF] Stanisic | Addressing substrate coupling in mixedmode ICs: simulation and power distribution synthesis[END_REF]Van Heijningen02,[START_REF] Gharpurey | Substrate coupling: modeling, simulation and design perspectives[END_REF][START_REF] Birrer | Schematic-driven substrate noise coupling analysis in mixed-signal IC designs[END_REF][START_REF] Lan | Synthesized compact models and experimental verifications for substrate noise coupling in mixed-signal ICs[END_REF]. Etant donné que les charges de ces circuits sont principalement capacitives, les courants de substrat sont produits pendant les variations de tension et la composante de courant significative est due aux porteurs majoritaires.

Cependant, dans des circuits intégrés de puissance, les circuits sous haute tension (HT) ont des charges inductives. Ces charges inductives stimulent des composants parasites particuliers responsables de l'injection de porteurs minoritaires dans le substrat. Le bruit dû à l'injection de porteurs minoritaires dépend des tensions et des courants de fonctionnement. Ce bruit devient non négligeable et a un effet significatif lors des fonctionnements sous haute tension et forts courants. Par conséquent, de nouvelles techniques de modélisation ont été étudiées pour estimer l'impact de la propagation des porteurs minoritaires sur les phénomènes de couplage du substrat.

L'objectif principal de cette thèse est de proposer une méthodologie d'analyse et de vérification des effets de couplage des signaux, par le bruit de substrat, dans les applications fonctionnant sous haute tension. Cette méthodologie peut être utilisée pour fournir des règles de conception quantitatives pour les circuits intégrés de puissance intelligents. Elle peut également être utilisée pour analyser des pannes résultant du couplage par les porteurs minoritaires. Etant donné que cette approche permet de détecter les défaillances dans un environnement de simulation, elle peut être utilisée pour prévenir ces défaillances avant la fabrication. Par conséquent, c'est un facteur important de réduction du délai de commercialisation et de coût du produit final. Notre méthodologie repose sur l'extraction automatique des composants parasites du substrat. L'outil logiciel utilisé pour l'extraction et la création du réseau électrique équivalent au substrat est appelé AUTOMICS. Après ces étapes de vérification, vient la phase d'extraction des composants parasites de layout. Ces composants sont dus essentiellement aux fils de routage en métal et prennent en compte leur résistance et la capacités parasite avec le substrat, ainsi que les capacités de couplage entre les différentes couches de métaux. De tels composants sont susceptibles d'affecter les performances du circuit, par conséquent, les composants parasites extraits sont ajoutés au circuit d'origine pour valider l'ensemble par simulation. Les résultats de la simulation post-layout sont considérés comme le facteur décisif pour approuver la conception avant l'envoi en fabrication. Pour les circuits analogiques sensibles au bruit et fonctionnant à basse tension et pour les circuits intégrés de puissance intelligents, xxv on doit ajouter une phase supplémentaire d'extraction du substrat à ce flot classique, pour vérifier que le couplage du substrat n'affecte pas la fonctionnalité du circuit.

Méthodologie pour la vérification des circuits intégrés de puissance intelligents

Lors de chacune de ces différentes étapes, il est possible de modifier le circuit. Cependant, plus on s'avance dans le flot, plus la modification est coûteuse. La fabrication du circuit prend ensuite typiquement environ quatre mois. Lorsque la puce est revenue de fabrication, elle est prête pour des tests supplémentaires et des mesures en laboratoire pour valider sa fonctionnalité. Si la puce parvient à passer tous les tests, le cycle de conception est terminé et le produit est approuvé. Ce cycle de conception peut durer environ un an. Si le produit échoue à passer un test critique, alors il faut commencer une étape d'analyse de l'échec pour identifier la cause de l'échec et la solution pour l'éviter. L'analyse de l'échec dépend de mesures et d'analyses spécifiques, pour localiser la cause du problème qui n'a pas été détectée par le flot classique. L'expérience du concepteur joue alors un rôle majeur. Après avoir identifié le problème, un nouveau cycle de conception/modification commence. De telles défaillances peuvent allonger le cycle de conception et donc le temps de mise sur le marché et certainement augmenter le coût de conception. Dans la pratique, ce cycle de conception/modification peut être répété plusieurs fois pour un seul produit.

Les défaillances dues au substrat sont causées principalement par l'activation d'un transistor bipolaire NPN latéral parasite. La modélisation de ce transistor NPN n'existe pas dans les outils logiciels commerciaux actuels. La technique de modélisation à l'état de l'art de ce transistor repose sur des simulations TCAD. Les simulations TCAD donnent des résultats exacts, mais ne passent pas à l'échelle des circuits intégrés. Ces simulations ont été utilisées comme guide pour contrôler le courant de substrat [START_REF] Schenkel | Substrate current effects in smart power ICs[END_REF][START_REF] Gnani | Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits[END_REF]. En plus des simulations TCAD, des bancs de test sont utilisés pour caractériser ce transistor NPN latéral parasite et guider le concepteur pour diminuer l'impact du bruit de couplage à travers le substrat.

Puisque le bruit de substrat dû au transistor NPN latéral est la cause principale du dysfonctionnement du circuit, qui n'est pas modélisée actuellement par les outils logiciels commerciaux, nous proposons de reproduire les défaillances du circuit dues au transistor NPN dans un environnement de simulation, comme indiqué sur la figure 1. Si nous reproduisons, en simulation, les échecs du circuit, alors nous sommes en mesure de prévenir ces échecs avant la fabrication, comme indiqué dans la figure 2. Ainsi, en introduisant une nouvelle étape dans le flot classique de conception, associée à des paramètres technologiques adaptés, il sera possible de diminuer le nombre de cycles conception/modification et, par conséquent, le coût et le temps de mise sur le marché du système seront réduits. Soulignons que le modèle du substrat sur lequel nous nous appuyons, permet de réaliser les simulations dans un environnement de type SPICE, pour prendre en xxvi compte la simulation d'un circuit complet dans un temps raisonnable.

System level design Specifications

Layout design

Analyse de défaillance

Le principal objectif de cette étape consiste à reproduire, dans un environnement de simulation au niveau transistor, une défaillance survenue lors du test d'une puce, dans le cas où l'ingénieur de test diagnostique que le couplage de substrat pourrait être la cause de l'échec du test. Comme présenté à la figure 3, l'analyse classique des défaillances du substrat s'appuie sur un modèle du substrat construit comme une netlist de composantes parasites extraits à la main. Cette étape xxvii d'extraction est laborieuse et longue. Dans ce cas, la question principale est d'identifier la cause de l'échec, sans se próccuper de la précision de l'estimation qui n'est pas dterminante.

Substrate parasitic extraction using AUTOMICS

Failure occurs

Parasitic components hand extraction

Simulation and analysis

Hand-extraction Automated-extraction preliminary failure analysis

Simulation and analysis

Substrate parasitic extraction and reproduction of failure Dans ce cas, la précision de l'estimation n'est pas le principal problème, c'est le temps pour réaliser l'extraction qui nous importe. Avec la méthode d'extraction parasite automatisée, la cause de l'échec peut être identifié beaucoup plus rapidement. Cette nouvelle méthodologie peut donc accélérer l'analyse des défaillances et l'enrichir sur la base de simulations de couplage par le bruit de substrat. Il convient de noter que cette méthode s'appuie sur la décision de l'ingénieur de test que le défaut est dû au couplage par le substrat, par conséquent, notre approche d'analyse de défaillances n'est pas entièrement automatisée.

0.2.2

Extraction des parasites du substrat • La tension de sortie est captée et mise à l'échelle par un diviseur de tension. L'amplificateur amplifie la différence entre la sortie du diviseur (V divider ) et la tension de référence (V ref ) pour générer la tension de commande (V c ).

• La tension de commande (V c ) et la tension en dents de scie (V ramp ) sont converties en courants qui sont soustraits pour générer le courant de commande

(I comp ) [Erickson01].
• Le courant de commande polarise le transistor de détection (M sense ). La taille du transistor de détection est considérablement plus faible que celle de l'interrupteur HS ((W/L) HS = K × (W/L) sense ), où K est un facteur d'échelle. Par conséquent, la résistance du transistor de détection peut être exprimée comme (R sense = K × R HS ), où R HS est la résistance de l'interrupteur HS. Dans notre cas, le facteur K vaut 2000.

• Le comparateur compare la tension du noeud de commutation (V sw) et la tension du noeud de détection (V sense). La sortie du comparateur est élevée lorsque la tension de détection est supérieure à la tension du noeud de commutation (figure 6). Dans ce cas, le latch SR est remis à zéro, le commutateur HS est éteint et le cycle de charge est terminé. Le commutateur (LS) est activé après un certain temps mort jusqu'à la fin de la période de commutation.

• La condition pour éteindre le commutateur HS peut être exprimé sous la forme :

V sw < V Sense HV V in -I L × R HS < HV V in -I comp × R sense I L > K × I comp
Ainsi, le commutateur HS est désactivé une fois que le courant de l'inductance dépasse le courant K × I comp . Le facteur K permet d'utiliser le courant de commande (I comp ) de faible valeur et par conséquent, de réduire la consommation d'énergie.

• L'inductance et le condensateur moyennent la tension au noeud de commutation (V SW R) pour générer la tension de sortie. La variation de la tension d'entrée ou de la charge font varier le rapport cyclique de la tension du noeud de commutation pour maintenir la tension de sortie constante. Le courant dans la résistance de charge (RL) est le courant moyen de l'inductance.

xxxi

• Cas de test 2 : la source du transistor de commutation LS est déconnectée. Cela signifie que le courant injecté passe seulement à travers la diode de substrat.

Dans ces deux cas nous avons conservé le connecteur NWELL du transistor PMOS à une valeur de tension haute (15V ). La tension de seuil fonctionnelle pour la tension de référence est fixée à 1, 16V , ce qui représente un écart de 3 % par rapport à la tension de référence. En dessous de ce seuil, nous supposons que la tension de référence est perturbée.

Cas de test 1 : on considère les diodes de bulk et de substrat Les composants parasites du substrat sont extraits. ce sont principalement les transistors BJT latéraux entre les couches NWELL des transistors NMOS, PMOS et du bandgap. Dans la simulation, la netlist extraite est rétro-annotée au schéma initial des interrupteurs LS, SH et du circuit de bandgap. Le courant injecté va de 0, 01A à 0, 8A.

La figure 12 représente la tension de référence par rapport au courant injecté dans les simulations et les mesures. Les résultats de simulation suivent la même tendance que les points de mesure. La tension de référence n'a pas dépassé la tension de seuil fonctionnelle même lorsque le courant injecté est d'environ 0, 8A. Cas de test 2 : on considère seulement la diode de substrat Dans ce cas, nous avons déconnecté le contact de source du commutateur LS, par conséquent, le courant ne peut pas circuler dans la diode de bulk du transistor NMOS. La diode de substrat est responsable de l'injection du courant dans le substrat. Ce courant est divisé en un courant de substrat et le courant collecté par les couches NWELL.

La figure 13 montre les résultats de simulation et les mesures. Pour des valeurs de courant élevées, les données simulées sont plus impactées par le courant injecté. La raison principale de cette différence est que sur la puce, il existe de nombreuses autres zones NWELL qui peuvent servir à collecter les électrons, alors que dans la simulation, nous ne simulons qu'un point d'injection et deux autres points de collection DWELL. Dans la figure 13, la référence de tension ne parvient pas à se maintenir à un niveau acceptable, lorsque le courant injecté est supérieur à 300mA. Ce courant injecté abaisse la tension de référence en dessous du seuil de 3% de ce que nous avons fixé. Comme cela est représenté sur la figure 14, le circuit comprend un interrupteur côté haut et une diode de roue libre côté bas. La boucle de régulation se fait en contrôlant la tension sur la borne BPA en définissant le rapport cyclique du signal PWM par comparaison avec une tension de référence et ainsi en contrôlant le courant circulant dans le rotor. Afin de supporter les conditions de tension de polarisation inverse sur la batterie, un circuit de commande est utilisé pour éviter la conduction de la diode parasite en condition de polarisation inverse [START_REF] Fanucci | An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability[END_REF]. Dans l'état de polarisation inverse, lorsque la tension de la source du transistor PMOS est négative, afin d'éviter que la diode parasite D DB devienne conductrice, le commutateur est éteint et la protection de tension est activée [START_REF] Hao | A reverse-voltage protection circuit for MOSFET power switches[END_REF]. Pour réduire au minimum la dissipation de puissance, le commutateur présente une faible résistance à l'état ON.

Un test important est la connexion électrique et la déconnexion rapide de la batterie avec un fort dV/dt . Le circuit AUTOCHIP1 n'a pas réussi à passer le test de connexion rapide, et nous allons identifier la cause de ses défaillances dans la section suivante. L'origine de ce problème est que pendant la transition rapide de la batterie, le bulk du commutateur présente une résistance élevée qui active le transistor PNP vertical entre le bulk et la source du transistor PMOS et le substrat P, injectant un courant élevé dans le substrat. La tension de substrat augmente et active le transistor de commutation NPN latéral et la structure (SCR) est alors déclenchée.

Proposition d'identification du problème

Notre méthodologie peut être utilisée pour identifier un tel échec. A ce stade, le layout du circuit est disponible et peut être traité par l'extracteur AUTOMICS. La zone sélectionnée est le transistor PMOS et les anneaux de garde. Les quatre principaux terminaux sont le bulk du PMOS (W ELL), la source du PMOS (BP A), l'anneau de garde de type N (N guardring ) et le contact de substrat P (P SU B). Ces terminaux sont conservés dans l'extraction de parasites substrat.

Lorsque le circuit original est simulé seul, un pic de courant apparaît lors de la connexion d'alimentation, puis le courant revient à zéro en une fraction de microseconde comme le montre la figure 17 Nowadays, systems integration is one of the common trends in the electronics industry. The integration of different systems on one die improves the compatibility and reduces the size of the devices. In the low voltages electronics, the analogmixed integrated circuits are increasingly growing and integrate both analog and digital low voltage circuits on the same die. Similarly, in the high voltages, the smart power integrated circuits comprise high voltage and low voltage circuits on the same die. Since the automotive industry tends for enhancing the vehicle connectivity for the sake of internet-of-thing (IoT) technology and reducing the vehicle emissions, the smart power ICs technology emerges as a competitive solution.

However, this integration leads to undesirable substrate noise coupling. In the analog-mixed circuits, the coupling between the digital circuits, that are the aggressors due to their high switching frequencies, and the analog circuits, that are the victims as they are sensitive to voltage variations, were investigated [START_REF] Stanisic | Addressing substrate coupling in mixedmode ICs: simulation and power distribution synthesis[END_REF][START_REF] Donnay | Substrate noise coupling in mixed-signal ASICs[END_REF][START_REF] Gharpurey | Substrate coupling: modeling, simulation and design perspectives[END_REF]. The substrate modeling technique is based on resistive and capacitive network for the substrate. Hence, the carriers considered into the substrate noise are only the holes. In smart power ICs, the substrate noise coupling could be due to the injection of holes and electrons. Since the currents in HV circuits are considerably high currents, the substrate noise coupling due to the minority carriers in the P-substrate can not be neglected. Such injected minority carriers can be coupled to other n-wells disturbing the low voltage analog circuits or even triggering a latch-up structure that could lead to a destructive failure. Figure 1.1 shows the injection of electrons in the substrate due to below ground voltage state on the drain of HV DNMOS transistor. Such below ground state can be developed in many well known circuits such as the H-bridge and DC-DC buck converters. Many industrial reports stated that one This minority carriers propagation through the substrate is modeled by a lateral NPN BJT transistor. The modeling difficulty is that the lateral NPN BJT transistor parameters are layout dependent. Besides, the modeling of the BJT can not be obtained by the conventional diodes and resistors since the conventional diodes equations assume full recombination of minority carriers on its contacts [START_REF] Simon | Physics of semiconductor devices[END_REF].

In [Lo Conte11a], new models for the diodes and resistors were presented and the minority carriers propagation through the substrate was investigated.

The key feature of these models is the consideration of the minority carriers and preserving their concentration and gradient and consequently the bipolar transistor can be modeled using these enhanced components. However, these models did not consider the injection of high currents, known as high-injection phenomenon, and the substrate netlist was manually extracted, besides, only DC simulations were performed.

Contribution

In the context of the European project AUTOMICS, École polytechnique fédérale de Lausanne (EPFL) research team was responsible for developing the diode and resistor models to accelerate the model speed and accuracy especially for the high injection conditions. Along with this activity, in Université Pierre et Marie Curie (UPMC), the computer science laboratory (LIP6) research team was responsible for the development of a CAD tool performing the parasitic substrate extraction and developing a new design methodology for the smart power ICs.

This proposed design methodology aims at improving the design reliability. This improvement is achieved by simulating the effects of substrate minority carriers coupling between the high voltage and low voltage circuits integrated on the same die. Consequently, the coupling protection rings can be optimized and hence reducing the silicon area and the cost. Also, a methodology for analysis of failures due to the parasitic couplings is proposed.

The contributions of this thesis can be summarized in the following points:

• Proposal for a new smart power ICs design flow:

The conventional smart power ICs design flow considers the substrate as a network of resistors and capacitors hence it is not capable of modeling the lateral NPN transistors. We added a new step in the design flow in which we extract the substrate as a network of enhanced diode and resistor models that comprises the effect of minority carriers. Consequently, we are able to identify the coupling currents in the substrate and their effects.

We have also proposed a new technique to identify the root cause failures that are due to minority carriers coupling. The conventional failure analysis depends on the manual extraction of substrate parasitic components that is pretty tedious and time consuming. Our proposal is based on using the CAD tool AUTOMICS that is capable of extracting the substrate parasitic components automatically.

We conduct a study on an industrial test case that suffers from a failure due to the minority carriers coupling. We manage to identify the failure in transient simulations and analyze some techniques to prevent it.

• Proposal for a fully integrated PI compensation in DC-DC buck converter in low switching frequencies: Since the DC-DC converters are suffering from the substrate coupling due to the injection of minority carriers, we investigate this kind of circuits extensively in this work. In automotive applications, low frequencies may be used in order to reduce electromagnetic interference (EMI). In such low frequencies, the reactive components like the capacitors used in the compensation circuits in feedback loop have large values and can not be integrated.

In this context, we proposed a digital representation of the capacitor functionality that can be integrated on chip. Hence, the off-chip components count is reduced and the cost is reduced. The system level simulations show an acceptable performance for the proposed method and the conventional off-chip solution.

• Design of a DC-DC buck converter based on the proposed method-

Introduction ology:

The DC-DC buck converter system comprises high voltage blocks like switches and analog sensitive blocks like the bandgap circuit. The floorplan is an important step to guarantee that the mutual effect between these two blocks are minimum. We designed a full DC-DC buck converter system and verified the floorplan using the proposed methodology to guarantee that the substrate coupling is minimized. The chip is fabricated using AMS HVC-MOS 0.35 µm technology and the measurements and the post-simulation results using the tool AUTOMICS show an acceptable agreement.

Thesis outline

The outline of this thesis is as follows:

• Chapter 2 presents a survey of the state of the art of the substrate modeling techniques. It shows the main advantages and disadvantages of these modeling techniques. The different considerations when modeling the substrate in the low voltage analog-mixed signal and high voltage circuits are discussed.

• Chapter 3 focuses on the proposed substrate parasitic components extraction framework refered to as AUTOMICS. It starts with the explanation of the enhanced diode and resistor models developed in EPFL. A comparison between the conventional and enhanced components is presented. Also, it shows a circuit modeling for these enhanced models to facilitate the comprehension of the model from the circuit perspective. Finally, it shows the principles of the CAD tool used in the substrate parasitic components extraction.

• Chapter 4 presents the conventional smart power ICs design methodologies then introduces our proposed design methodology. The substrate parasitic coupling verification step is explained then the analysis step of failure due to substrate parasitic coupling is elaborated using the tool AUTOMICS. An industrial test case that has a failure due to the substrate coupling is investigated along with some protection techniques. Finally, the simulation results are presented.

• Chapter 5 establishes a background for the DC-DC buck converters. The small signal models of the buck converters are derived. The two common control methods which are the voltage mode control (VMC) and the current programmed mode (CPM) control are discussed. Lastly, the proposed analog-mixed PI controller in the low switching frequency is presented.

• Chapter 6 shows the circuit level of the DC-DC buck converter. The circuit of each block in the system is explained. Then, the floorplanning and the measurement of the system are discussed. Finally, the substrate simulation results are compared to measurements.

• Chapter 7 concludes the thesis and points out some future work.

Chapter 2

Substrate modeling state of the Art

Introduction

Automotive industry is a growing market for smart power integrated circuits (ICs). The smart power ICs incorporate the high voltage (HV) and low voltage (LV) circuits on the same die. This feature allows to miniaturize the electronic systems and implement more functionality in the vehicles.

A typical architecture for smart power IC in automotive applications is depicted in Figure 2.1. The analog front-end is the first stage that processes input signals from different transducers and sensors. These signals are then filtered, amplified and converted into digital domain using the Analog-to-Digital Converters (ADC). The logic unit is a processing unit that manipulates the inputs and communicates with the main central processing unit through the Controller Area Network (CAN) or Local Interconnected Network (LIN) buses. The CAN bus is used for mainstream power train communications with high bandwidth and high performance while the LIN bus is used for lower-cost and low bandwidth electronics. The HV stage is commonly used to drive HV loads such as motors. Consequently, its temperature becomes high and hence, raises the temperature of the chip.

Special dedicated silicon technologies have been developed to allow the integration of all these blocks, like Bipolar-CMOS-DMOS (BCD) or HV-CMOS technologies [START_REF] Murari | Smart power ICs: technologies and applications[END_REF]. On the one hand, the BCD technology is more concerned about the power part. It efficiently reduces the coupling between different blocks through the trench isolation techniques. However, this technology is complex and have a high processing cost. On the other hand, the HV-CMOS technology has lower performance on the power devices and isolation. However, it is much less If we would like to alternate between forward and reverse direction, we have to add a dead-time. In this dead-time period, all the switches are off to prevent the shoot-through current. The motor is considered as an inductive load. During the dead-time period, the current in the inductor does not change instantaneously, hence, the convenient current path is through the body diodes. Consequently, the voltage nodes across the inductor can be either above supply or below ground. show the below ground and above supply states effects. In the above supply state, the vertical PNP transistor is activated and starts to inject majority carriers in the substrate. This can raise the substrate potential and affect the system operation. In the below ground state, the minority carriers are injected in the substrate. The lateral NPN bipolar transistor is activated and the minority carriers are coupled to other N-wells. The main challenge in the NPN transistor is that it is a layout dependent and can not be extracted using conventional extraction tools.

M MP1 MP2 MN1 MN2 + - DN1 DN2 DP1 DP2 GP1 GP2 GN1 GN2 V supply OUT1 OUT2
Another common example of HV circuits is the DC-DC buck converter. The circuit is depicted in Figure 2.5. The switching node voltage (Vsw) is alternated between V in and ground using the high side (HS) and low side (LS) switches. An LC low pass filter is used to average the switching node voltage. In order to prevent the shoot-through current, the dead-time should be inserted and consequently, we get the below ground state as in the H-bridge. These coupling of minority carriers can cause failures, especially in the HV applications.

Since safety in the automotive industry is of critical concern, addressing electronics failures has a wide interest in order to guarantee more robust and reliable products. Currently, the design centers can prove by simulation the functional modes of electronic systems and validate them for reliability and aging issues. As a result, the number of the electronic failures are drastically reduced thanks to Design for Reliability (DfR) method [START_REF] Ognjanović | Design for reliability based methodology for automotive gearbox load capacity identification[END_REF][Sasun13] globally deployed in automotive design. Besides, the monolithic integration in ICs improves the reliability by manufacturing. However, failures due to the substrate noise cou- Through out the research done in the analog-mixed substrate coupling, the substrate had been modeled as a network of resistances and capacitances [START_REF] Stanisic | Addressing substrate coupling in mixedmode ICs: simulation and power distribution synthesis[END_REF]Van Heijningen02,[START_REF] Gharpurey | Substrate coupling: modeling, simulation and design perspectives[END_REF]. The common substrate modeling techniques are Finite Difference Method (FDM) [START_REF] Han | Accurate substrate analysis based on a novel finite difference method via synchronization method on layered and adaptive meshing[END_REF], Finite Element Method (FEM), Boundary Element Method (BEM) [START_REF] Li | An automated and efficient substrate noise analysis tool[END_REF], and macromodels [START_REF] Birrer | Schematic-driven substrate noise coupling analysis in mixed-signal IC designs[END_REF]. The main focus of these researches was to shorten the simulation time and improve the model accuracy.

Since the loads of these circuits are mainly capacitive, these works did not consider the injection of the minority carriers through the substrate as in this case the significant substrate noise contribution comes from the majority carriers. Therefore, new modeling techniques were investigated to study the substrate coupling due to the minority carriers propagation.

Substrate modeling in high voltage circuits

The injection of minority carriers in smart power ICs was addressed in [START_REF] Schenkel | Substrate current effects in smart power ICs[END_REF] using Technology Computer Aided Design (TCAD) simulation. TCAD simulation is based on Finite Element Method (FEM) technique. It divides the semiconductor into infinitesimal volume units and applies 3D equations describing the propagation of charges through this unit volume. This work investigated the majority and minority carriers injections in an H-bridge circuit by means of measurements and device simulations. It also proposed TCAD-guided design methodology for substrate current control. However, the TCAD simulation ac-curacy depends on the meshing size. Reducing the meshing size enhances the accuracy but increases the simulation time. Hence, the TCAD simulations can be used for designs with small number of components while addressing more complex structures would be impractical from the simulation time point-of-view. Also, the transient simulations are not possible in TCAD simulators.

In [Lo Conte10], a new modeling methodology for the PN junctions was introduced. The PN junction model was modified by additional terminal to take into account the minority-carrier concentrations and gradients at the boundaries. Such model is interesting since it can be used to model a bipolar junction transistor behavior. In Figure 2.7(a), the NPN transistor minority carrier concentration is shown. When connecting two back-to-back diodes as in Figure 2.7(b), the bipolar behavior can not be obtained since the conventional diode equation assumes full recombination of minority carriers at the contacts. Thus, the continuity of minority carriers concentration is not maintained. The proposed model has additional terminals that give an information about the minority carriers concentration and gradient as shown in Figure 2.7(c). Also, a compatible resistor with additional terminals was proposed to allow the propagation of minority carriers in the resistors. These models gave a different insight of substrate model as it can be viewed as a network of enhanced diodes and resistors instead of only conventional resistors. Besides, the lateral NPN transistors are inherently modeled using the enhanced diode. Consequently, the minority carriers propagation can be illustrated.

The key advantage of this modeling approach is its compatibility with circuit simulator. These enhanced diode and resistor models are developed in a way to express the minority carriers concentration as a voltage and the minority carrier concentration gradient as a current. Consequently, for the circuit simulator each additional terminal has two unknowns to be solved which are the voltage and the current. At the metal contacts, the excess minority carriers concentration is zero hence this would serve as a boundary condition to solve the substrate network.

In [START_REF] Fabrizio Lo Conte | A circuit-level substrate current model for smart-power ICs[END_REF], a double collector lateral NPN transistor was modeled using the proposed methodology and TCAD simulation. The results were in good agreement for low injected current values. A hand-crafted 3D substrate parasitic network for H-bridge circuit had been simulated in [Lo Conte11b]. A comparison between the TCAD, measurements, and the proposed modeling technique was presented. The proposed method shows consistent results and the simulation time was considerably less than TCAD simulations. However, in this work, low injected current levels were only considered and the substrate extraction was extracted manually that could be tedious for complex circuit analyses.

In this chapter, we illustrated the basic architecture of the smart power ICs and the technologies used in their fabrication. Two examples of HV circuits that are prone to the substrate noise due to the minority carriers propagation were illustrated. The substrate modeling in the HV circuits is discussed. These modeling techniques provide methods for the minority carriers propagation modeling. However, they failed to provide solutions for the long simulation times and the high current injection levels.

Chapter 3 AUTOMICS: Pragmatic substrate parasitic extraction framework

In smart power integrated circuits, the low and high voltage circuits are integrated on the same die. The substrate coupling is caused by majority and minority carriers. The high voltage circuits are frequently used to drive inductive loads. The presence of these loads stimulates the injection of minority and majority carriers in the substrate. These carriers can be coupled to low voltage analog sensitive circuits and perturb its operation or can cause a latch-up failure.

In this chapter, the conventional components used in modeling the substrate are explored to focus on the approximations that have been done. These approximations are mainly used to develop a closed formula to be used for the behavioral description of the component. Then, enhanced models developed in EPFL which are used to consider the minority carriers propagation in the substrate are elaborated. Finally, a computer aided design CAD tool (AUTOMICS) is introduced to extract the substrate parasitic components from the layout and construct a 3D substrate network. This substrate network can be back-annotated to the original circuit to estimate the substrate coupling between the noisy high voltage and other sensitive low voltage circuits.

Conventional Substrate modeling components

In this section, we are going to derive the conventional equations for the semiconductor resistance, diode, and capacitance. For each component, we show how the minority carriers are ignored to facilitate the derivation and obtain a closed form. Also, we show that the conventional diode equations are derived using the 3. Pragmatic substrate parasitic extraction in smart power ICs low injection condition.

Resistance in conventional substrate modeling

In semiconductors, there are two main types of currents: a) the drift current and b) the diffusion current. The drift current is due to the presence of an electric field and the diffusion current is due to the presence of gradient in the carriers concentration. The total current equation is expressed as follows [START_REF] Ben | Solid state electronic devices[END_REF]:

J total (t) = J p (x)+J n (x) = J p drif t (x)+J p dif f usion (x)+J n drif t (x)+J n dif f usion (x) (3.1)
where J p (x), J n (x) are the total holes and electrons current densities (A/m 2 ), respectively. J p,n drif t (x) are the drift current components of holes and electrons. J p,n dif f usion (x) are the diffusion current components of holes and electrons.

Assume a piece of p-type semiconductor, the total holes and electrons current densities can be expressed as a function of the doping concentration as follows:

J p (x) = qµ p E(x).(N a + δp) -qD p dδp dx (3.2)
J n (x) = qµ n E(x).(n o + δn) + qD n dδn dx (3.3)
where µ p,n are the holes and electrons mobility (cm 2 /(V.s)), D p,n are the holes and electrons diffusion coefficients (cm 2 /s), E(x) is the applied electric field intensity (V /cm), N a is the concentration of P-dopants (cm -3 ), n o is the equilibrium electron concentration in P-type region (cm -3 ) (n o = n 2 i /N a ) where n i is the intrinsic carrier concentration in semiconductor and δp and δn are the excess holes and electrons concentrations (cm -3 ).

Generally, in conventional substrate modeling, the injection of minority carriers is ignored and hence the excess minority carriers concentration is assumed to be zero (δp = δn = 0). The total current equation becomes:

J total (x) = q.E(x).(µ p N a + µ n n o ) (3.4)
From the equation 3.4, the total current is only the drift components and the conductivity of the semiconductor is evaluated as σ = q.(µ p N a +µ n n o ). Assuming a constant electric field, the resistance of a differential element (∆x) and crosssectional area (A) becomes

R s = V I = E(x)dx J(x)dA = 1 σ • ∆x A (3.5)
Such resistive model is used in substrate modeling for low voltage mixed signal and RF parasitic extraction [START_REF] Stanisic | Addressing substrate coupling in mixedmode ICs: simulation and power distribution synthesis[END_REF]. Such a model ignores the injection of minority carriers that can occur in the real devices.

PN junction in conventional substrate modeling

In substrate modeling, the PN junctions are formed in many regions due to the presence of N-well regions over the P-substrate. The physical equation of the PN junction can be derived as follows. At thermal equilibrium (TE), the electrons and holes concentrations can be expressed as follows [START_REF] Simon | Physics of semiconductor devices[END_REF]:

n o = n i • exp( E f -E i KT ) (3.6) p o = n i • exp( E i -E f KT ) (3.7)
Where E f is the Fermi-level energy (eV ), E i is the intrinsic level energy(eV ), K is the Boltzman constant (eV /K) and T is the temperature in Kelvins. From 3.6 and 3.7, the mass action law is obtained at equilibrium as follows:

p o × n o = n 2 i (3.8)
This relation holds at thermal equilibrium, however, if a voltage is applied to the junction, the Fermi-level is split into two quasi-Fermi levels and the electrons and holes concentration become:

n n = n i • exp( E F n -E i KT ) (3.9) p p = n i • exp( E i -E F p KT ) (3.10)
where n n and p p are the electrons and holes concentration on the n-and p-sides and E F n and E F p is the quasi-Fermi level energy on the n-and p-sides, respectively. In the depletion region, E F n and E F p remain relatively constant as the concentration of carriers inside the depletion region is very high and the depletion region width is typically shorter than the diffusion length [START_REF] Simon | Physics of semiconductor devices[END_REF]. Hence, the applied voltage can be described as a function of the quasi-Fermi levels as :

q • V = E F n -E F p (3.11)
where V is the applied voltage on the PN junction. From the equations 3.9, 3.10, and 3.11, equations describing the minority carriers concentrations in the p-and n-sides can be deduced as:

n p = n 2 i p p • exp( qV KT ) (3.12) p n = n 2 i n n • exp( qV KT ) (3.13)
where n p and p p are the electrons (minority) and holes (majority) concentrations on the p-type. Similarly, p n and n n are the holes (minority) and electrons (majority) concentrations on the n-type.

For low injection, the excess minority carriers are assumed to be much less than the majority carriers. Hence, the majority carriers can be assumed the same as the thermal equilibrium values.

p p = p po at TE + δp Excess injected carriers ≈ p po (3.14) n n = n no at TE + δn Excess injected carriers ≈ n no (3.15)
Thus, the equations 3.12 and 3.13 can be rewritten at the boundaries of the depletion region, as shown in Figure 3.1, as follows

n p (x = -W Dp ) = n po • exp( qV KT ) (3.16) p n (x = W Dn ) = p no • exp( qV KT ) (3.17)
Recall the charge neutrality which claims that the excess majority carriers concentrations should be equal to the excess minority carriers. For example, in the n-side the charge neutrality can be expressed as

p n -p no Excess holes = n n -n no Excess electrons (3.18)
Hence, the gradient of the holes and electrons concentrations are equal.

dp n dx = dn n dx (3.19)
Applying the continuity equation at the steady-state in the n-side of the junction, the electrons and holes continuity equations are shown as follows [START_REF] Simon | Physics of semiconductor devices[END_REF]:

-U + µ n n n dE dx + µ n E dn n dx + D n d 2 n n dx 2 = 0 (3.20)
total recombination of minority carriers at the contacts is assumed, hence, the boundary conditions become:

p n (x → ∞) = 0 p n (x = W Dn ) = p no + ∆p n (3.25)
Then, the solution of equation 3.24 based on the previous boundary conditions, gives the holes concentration in the n-type side as

p n (x) = (∆p n + p no )exp(- x -W Dn τ p D p ) (3.26)
Similarly, the electrons concentration in the p-side is given by

n p (x) = (∆n p + n po )exp( x + W Dp √ τ n D n ) (3.27)
The total current density of the junction can be obtained as the sum of the electrons current density at -W Dp and the holes current density at W Dn as follows

J total = qD n dn p (x) dx | x=W Dp -qD p dp n (x) dx | x=-W Dn = q( D p p no L p + D n n po L n )[exp( qV KT ) -1] (3.28)
This equation is the well-known equation for the diode modeling [START_REF] Simon | Physics of semiconductor devices[END_REF][START_REF] Ben | Solid state electronic devices[END_REF]. However, through the derivation we have made the following assumptions: 1) there is only low injection and 2) the minority carriers are fully recombined at the boundaries. The assumption of the full recombination is the main reason behind the lack of capability of modeling a bipolar junction transistor using the connection of two diodes as illustrated in Figure 3

Capacitance in conventional substrate modeling

The parasitic capacitance components that can be extracted from the substrate are mainly due to the PN junctions. The PN junction capacitances can be divided into two types:

1. Junction capacitance (depletion layer capacitance): it is formed by the fixed charges of donors and acceptors in the depletion region. This capacitance is dominant in the reverse bias operation.

2. Diffusion capacitance (charge storage capacitance): it arises from the injection of minority carriers and resulting in lagging between voltage and current to discharge this stored charges. This capacitance is the dominant in the forward bias operation.

In substrate modeling, the junction capacitance is well modeled and included in the current commercial substrate extraction tools. The junction capacitance equation can be expressed as follows [START_REF] Simon | Physics of semiconductor devices[END_REF]:

C j = | dQ d(V b -V ) | = ǫA W = ǫA[ q 2ǫ(V b -V ) N d N a N d + N a ] 1/2 (3.29)
where W is the width of the depletion region, V is the applied potential across the junction, and V b is the built-in barrier potential. However, the diffusion capacitance is more dependent on the minority carriers concentration. An expression for the diffusion capacitance is given based on the boundary conditions given in 3.25 as follows [START_REF] Simon | Physics of semiconductor devices[END_REF]:

C d = q 2 2KT (p no • L p + n po • L n )exp( qV b KT ) (3.30)
where L p is the holes diffusion length (cm) and is equal to 1/ D p τ p and L n is the electrons diffusion length and is equal to 1/ √ D n τ n . From the previous equation, the dependence of the diffusion capacitance on the injected minority carriers are clear. It is also proportional to the forward current. For instance in case of heavily doped n-region n + p, equation 3.30 can be reduced to

C d = q 2 2KT (n po • L n )exp( qV b KT ) = qL 2 n 2KT D n J F (3.31)
where J F is the forward bias current. Consequently, the diffusion capacitance lacks a proper model since it strongly depends on minority carriers concentration and the boundary conditions. Therefore, it is not considered in the substrate extraction tools.

Enhanced substrate modeling components

In this section, we elaborate enhanced models that account for the minority carriers propagation. These models were developed at EPFL during the AUTOMICS project and we use them in the extraction of the substrate equivalent network. For each model, we show the equations and construct an equivalent circuit for a small differential element. This differential element is going to be the basic building cell for the substrate network.

Enhanced resistance model

The enhanced semiconductor resistive model accounts for the minority carriers propagation and the high injection conditions [START_REF] Stefanucci | Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs[END_REF]. Assume a piece of p-type material, starting from equations 3.2 and 3.3 and considering the following conditions: 1) The neutrality conditions (δn = δp), 2) The electric field is constant. Then, the total current density can be written as

J(x) = qE[µ p .(N a + δn) + µ n .(n o + δn)] + q(D n -D p ) dδn dx (3.32)
The current in the previous equation can be separated as two parts:

1. The resistive part which is due to the applied voltage (E = ∆V /∆x), 2. The diffusion part which is due to the difference between the minority and majority diffusion current.

The conductivity (σ) can have three different approximated formulas:

1. The low injection conditions (δn << N a ), the conductivity can be expressed as (σ = q(µ p N a + µ n n o )).

2. Medium and high injection, no approximations can be done on the conductivity expression (σ = q[µ p .(N a + δn) + µ n .(n o + δn)]).

3. Very high injection (δn >> N a ), the conductivity can be simplified to

(σ = q(µ p + µ n )δn).
It is clear that the conductivity of a semiconductor in the medium and high injection is modulated by the excess minority carriers concentration. The equivalent circuit for the total current equation in a differential element of thickness ∆x and cross sectional area A (I tot = J tot * A) is shown in figure 3.3. The fixed conductance G o represents the fixed conductance which is present in all cases. The variable conductance G min which emulates the modulation of the conductance due to the minority carriers. The current I bulk is due to the minority carriers diffusion. In the equivalent circuit shown in Figure 3.3, there are two unknowns related to the minority carriers which are the excess minority carriers concentration (δn) Similarly,

G min = q A (µ p +µ n )/n / ûx G 0 = q A (µ p N a +µ n n o )/ ûx I bulk = q A (D n -D p )d/n/dx I tot V 1 V 2
J n (x i-1/2 ) = qµ n δn(x i-1/2 )E(x i-1/2 ) + qD n δn(x i ) -δn(x i-1 ) ∆x i-1 = qµ n δn(x i-1 ) + δn(x i ) 2 E(x i-1/2 ) + qD n δn(x i ) -δn(x i-1 ) ∆x i-1 (3.35)
where E(x i±1/2 ) is electric field intensity at the point i ± 1/2. Since the electric field is assumed to be constant, it can be expressed as the voltage gradient, i.e,E(x i+1/2 ) = (V (x i+1 ) -V (x i ))/∆x i . Using equations 3.34 and 3.35 in equation 3.33, the following expression can be deduced

µ n A qδn(x i ) + qδn(x i+1 ) 2 E(x i+1/2 ) -µ n A qδn(x i ) + qδn(x i-1 ) 2 E(x i-1/2 ) + D n A ∆x i (qδn(x i+1 ) -qδn(x i )) - D n A ∆x i-1 (qδn(x i-1 ) -qδn(x i-1 )) = ∆x i A 2τ n qδn(x i ) + ∆x i-1 A 2τ n qδn(x i ) (3.36)
If the physical quantity qδn(x i ) is assumed to be equivalent to a voltage V eq,i , the equation 3.36 can be viewed as a sum of currents to the node i and an equivalent circuit can be composed as shown in the Figure 3.5.

V eq,i-1 V eq,i G d i-1/2 V eq,i+1 . g mdi E i+1/2 i i+1 i-1 G d i+1/2 G c i G c i-1 . g mdi E i-1/2 ûx i-1 ûx i
I eq,i-1 I eq,i =I eq,i+1 The pi equivalent circuit is shown in Figure 3.6 [START_REF] Stefanucci | Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs[END_REF]. In the minority carriers equivalent circuit, there are three main components that are defined as follows:

1. The diffusance G d : it is the conductance that depends on the diffusion coefficient and emulates the diffusion current (G d = A.D n,p /∆x).

2. The combinance G c : it is the conductance that depends on the carrier life time and emulates the portion of minority carriers current that recombines (G c = A.∆x/(2τ n,p )).

3. The driftance g md : it is a transconductance that weights the effect of the electric field on the minority current diffusion (g md = A.µ n,p .[V eq,1 +V eq,2 ]/2).

Studying the continuity equation in transient results in additional two parallel branches representing the capacitance C d,i = ∆x i [START_REF] Stefanucci | Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs[END_REF]. Modeling such capacitance are very effective in modeling the junction and diffusion capacitance of the PN junction.

V eq,2 G d . g md E G c G c . g md E I eq
V eq,1 The combination of the total current circuit in Figure 3.3 and the minority carriers equivalent circuit in Figure 3.6 results in a four terminals component as shown in Figure 3.7. The voltages V 1 and V 2 represent the applied voltage to the differential element (∆x) and the voltages V eq,1 and V eq,2 represent the minority carriers concentration (V eq,i ≡ qδn(i)) and the current I tot represents the total current in the differential element including the contribution of the minority carriers while I eq,i represents the minority carriers gradient at (i) I eq,i ≡ qdδn/dx. This equivalent representation is useful for quantitative analyses and gives an insight to minority carriers propagation effects.

This model is implemented in VerilogA language and is used in the circuit simulator. The circuit simulator would be able to solve this coupled system based on boundary conditions applied at the contacts. For example, if the terminal 1 is the contact side (metal contacts), the minority carriers are totally recombined

V eq,2 G d . g md E G c G c . g md E I eq V eq,1 G min G 0 I bulk I tot V 1 V 2 C d C d Figure 3
.7: Enhanced model for semiconductor resistor known as EPFL resistor [START_REF] Stefanucci | Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs[END_REF] and hence, (V eq,1 ) is set to zero. Using KVL and KCL to the different blocks interconnected together, the overall distribution of current, voltages and minority carriers can be obtained with standard circuit simulators.

It should be noted that the enhanced model was obtained based on the finitedifference scheme hence, the substrate discretization affects the results. The effect of the substrate discretization or meshing has been studied in [START_REF] Stefanucci | Influence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs[END_REF]. The conclusion proves that the meshing affects the accuracy of the model and the accuracy can range from 4 -50% compared to a TCAD model with the same parameters. The meshing of the substrate thickness significantly affects the accuracy.

Enhanced PN junction model

The PN junction can be viewed as three main regions:

1. Quasi-neutral p-region, 2. Quasi-neutral n-region, 3. Depletion region.

The total current (I tot ) in the depletion region is the sum of the drift and diffusion currents of the holes and electrons [START_REF] Simon | Physics of semiconductor devices[END_REF]. Hence, it can be presented as a dependent current source which value depends on the minority carriers concentration gradient and voltage difference applied to the junction. In the low injection case, the dominant current component is the diffusion currents of electrons in the p-side and holes in the n-side.

In case of the high injection case, the dominant currents become the drift currents. Recall the boundary conditions in the equations 3.16 and 3.17 used in the conventional PN junction should be generalized to adapt to the high injection conditions. Hence, more accurate boundary conditions called Misawa boundary conditions are applied and the boundary conditions for the excess minority carriers become as shown below [START_REF] Stefanucci | Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs[END_REF]

δp n (x = W Dn ) ≃ N d 2   1 + 4n 2 i (exp( V j +Vr Vt ) -1) N 2 d -1   (3.37)
where δp n is the excess holes injected to the n-side at the edge of the depletion regions. Similarly, the excess electrons injected to the p-side is

δn p (x = -W Dp ) ≃ N a 2   1 + 4n 2 i (exp( V j +Vr Vt ) -1) N 2 a -1   (3.38)
In equations 3.37 and 3.38, V j corresponds to the voltage across the depletion region and V r is a correction factor since in high injection condition, the voltage drop across the junction saturates to the built-in potential V b , but the carrier injection continues. The main reason of this phenomenon is that the carriers injection depends on the separation between the quasi-Fermi levels which in terms corresponds to the junction voltage. However, in the high injection, this separation is not corresponding anymore to the voltage drop. The correction factor permits the increase of the excess minority carriers even if the junction voltage saturates to the built-in potential. The correction voltage is expressed in terms of the excess minority carriers concentration as shown in equation 3.39.

V r = V t ln N a + δn p (x = -W Dp ) N a + δn p (x = -W p ) p-side + V t ln N d + δp n (x = W Dn ) N d + δp n (x = W n ) n-side (3.39)
where W n and W p are the n-and p-type widths. The PN junction equivalent circuit is shown in Figure 3.8 . The advantages of this model are the consideration of the minority carriers propagation and the flexibility to adapt to low and high injection conditions.

V eq,2

g md E G c G c g md E I eq G min G 0 I bulk I tot V 2 G d g md E G c G c g md E I eq V eq,1 G min G 0 I bulk I tot V 1 + _ + _ V eq,n V eq,p V j P-type N-type Depletion Region + - W Dn W n W p W DP

Enhanced homojunction model

The homojunction is formed due to the implantation of heavily doped region (i.e, P+ or N+) over low doped material of the same type, such as junctions between P and P+ regions and N and N+ regions. Such junctions can be considered as a connection of two different resistances. The difference in the values of these resistances is extremely large, that can be considered as a resistance discontinuity and the voltage drop abruptly changes. These junctions can be modeled using the same technique used for modeling the PN junction. The total current of a PP+ or NN+ junction can be assumed to be constant. However, for the minority carriers there is an abrupt change in the excess minority carriers concentration.

To illustrate this phenomenon, assume a NN+ junction with a doping concentration of N d,1 >> N d,2 . At non-equilibrium conditions, the mass action law imposes that the product between minority and majority carriers concentration is the same and it is dependent on the quasi-Fermi levels splitting. Applying the quasi-neutrality condition and low injection case, a relation between the excess minority carriers on both sides can be obtained as in equation 3.40 [START_REF] Stefanucci | Impact of enhanced contact doping on minority carriers diffusion currents[END_REF].

n 1 p 1 = n 2 p 2 (N d,1 + δp 1 )(p o + δp 1 ) = (N d,2 + δp 2 )(p o + δp 2 ) N d,1 × δp 1 = N d,2 × δp 2
(3.40) Equation 3.40 shows that there is an abrupt change in the excess minority carriers concentration. If N d,1 is much greater than N d,2 then δp 1 is significantly less than δp 2 . This phenomenon is significant especially in the low injection conditions and it is referred as minority carriers mirrors in [START_REF] Stefanucci | Impact of enhanced contact doping on minority carriers diffusion currents[END_REF]. This change in excess minority carriers can be viewed as a dependent voltage source (∆V eq = q(δp 2 -δp 1 )) between two equivalent circuits for N and N+ as shown in figure 3.9.

V eq,2

g md E G c G c g md E I eq G min G 0 I bulk I tot V 2 G d g md E G c G c g md E I eq V eq,1 G min G 0 I bulk I tot V 1 + _ ûV eq N-type
N+-type

I tot

Conventional and enhanced substrate modeling

We are going to illustrate the difference in the extracted netlist using the conventional and the enhanced models.

Conventional substrate extraction

After finishing the layout of the design, parasitic components should be extracted. These parasitic components can be divided into two main categories:

1. Metal interconnects: The parasitic capacitances and resistances for the metal interconnects are extracted.

2. Substrate extraction: The substrate parasitic components are extracted.

The commercial extraction tools that are commonly used for the parasitic extraction are Star RCXT R provided by Synopsys , Quantus T M QRC provided by Cadence R , and Calibre xRC provided by Mentor Graphics R . These tools are used for the analysis of the parasitic noise coupling through the substrate based on modeling the substrate as RC network. The tool providers focus on improving the accuracy and reducing the simulation time. These coupling effects are critical for Mixed-Signal ASICs [START_REF] Donnay | Substrate noise coupling in mixed-signal ASICs[END_REF] and low voltage RF applications [START_REF] Bronckers | A methodology to predict the impact of substrate noise in analog/RF systems[END_REF]. However, the lateral parasitic coupling is not considered in the distributed RC model.

Assume a cross-section in HV-CMOS technology as shown in Figure 3.10. The figure shows isolated DNMOS and DPMOS transistors. An isolating guard ring is inserted in between to reduce the coupling between the two transistors and other wells. The solid line components represent the parasitic components that are included in the compact model of the transistors. The dashed line components represent a simple version of extracted netlist by the current commercial tools. On the one hand, we can observe that the vertical parasitic PNP transistor is modeled. On the other hand, the lateral NPN transistors between the three deep N-wells (i.e, DPMOS, DNMOS, and guard rings) are not modeled. The main impediment to model such parasitic components is its dependence on the layout and the circuit operation. For example, if the drain of the DNMOS goes below ground and the guard ring and the N-well of the DPMOS are connected to a high voltage, the resulting structure is a double collector BJT. This simple example can be extended to multi-collector parasitic components.

In high voltage applications, this lateral parasitic components can severely degrade the performance of low voltage circuits or even cause destructive failures due to latch-up. The extraction of these components relies on the hand extraction developed by the designer and some qualitative design rules [START_REF] Hastings | The art of analog layout[END_REF].

Enhanced substrate extraction

Since the enhanced components, previously presented, model the propagation of minority carriers, the lateral NPN can be seamlessly modeled. The substrate components could be resistance, diode, and homojunctions. The parasitic capacitance is inherently included in the enhanced diode model. The enhanced diode model compromises the diffusion capacitance model in case of forward biasing in addition to modeling the junction capacitance. Therefore, the lateral NPN transistor can be viewed as back-to-back diodes in the substrate network and This modeling scheme allows the designer to investigate the effect of the propagation of minority carriers and how it affects other low voltage circuits. Also, it will reduce the cost of the design by optimizing the area of the guard rings. Handling large integrated circuits manually would be a very exhaustive task, thus computer aided design (CAD) tool would be an added feature to this modeling scheme.

AUTOMICS: substrate parasitic extraction tool

Minority carriers propagation modeling in the substrate is the stronghold of the proposed modeling scheme, especially for high voltage and high temperature applications. As most of current tools are not considering the minority carriers propagation, the presence of a tool able to model the substrate including the minority carriers propagation would be helpful in the design. A CAD tool developed in LIP6 is able to extract the parasitic substrate components automatically from the layout of a design. This tool is referred as AUTOMICS tool. The extraction procedure has two basic steps:

A. Geometrical features extraction using AUTOMICS tool, B. Technological parameters calibration.

AUTOMICS tool geometrical features extraction

The main feature of the AUTOMICS tool is to extract the geometrical features of the parasitic components in the layout. The inputs and outputs of the tool is depicted in Figure 3.12. The main flow of the tool can be divided into three main steps [Zou15]:

1. pre-processing stage, 2. extraction stage, 3. post-processing stage.

AUTOMICS tool pre-processing stage

The layout is a two dimensional environment used by the designer to place different components of the design according to his experience to reduce the cross-talk between the different blocks. However, to consider the substrate parasitic components, we are missing the third dimension (z-axis or the depth) for each layer in the layout. The third dimension is a technology dependent parameter that can differ from one foundry to another. Thus, for extraction, the depths of the layers are given as an input to the tool, which is referred to as extraction rules Figure 3.12: Proposed substrate parasitic extraction flow [START_REF] Zou | Substrate noise modeling with dedicated CAD framework for smart power ICs[END_REF] file. This file is written in a standard Extensible Markup Language (XML) language. It contains the depths of the used layer and the depth of the substrate sub-layers used in the extraction. In addition to the depth, the doping profiles of the different layers are not available. The doping profiles are approximated to be constant for each layer to facilitate the extraction procedure. However, the doping concentrations are defined in a separate file called by the model of the enhanced components. The estimation of the doping concentration is based on some techniques that will be discussed in section 3.4.2.

A sample of the rules file is listed as follows: <Layers> <substrate depth= "(thickness of substrate)"/> <layer name= "N+" type="NPLUS"/> <layer name= "P+" type="PPLUS"/> <layer name= "DN" type="N" depth= "Depth of DN well"/> <layer name= "DP" type="P" depth= "Depth of DP well"/> </Layers> As shown in the rules file, we defined the thickness of the substrate and other layers. In the rules file, the layers that contribute to the substrate noise coupling are identified. Listing a layer in the rules file informs the extraction engine to consider the parasitic components related to this layer. Certain reduction rules are used to reduce the number of the extracted components. The extraction is limited to only homojunction and enhanced diode. The aim of studying the BCD structure was to evaluate the current passed beneath the trench and coupled to other wells.

homojunctions results from same type (P-or N-) mesh cells but different doping concentration values.

Assume that we have simple structure of deep N-well with a P-guard ring acting as substrate contact. A basic nonuniform rectilinear meshing is shown in Figure 3.16.The previous two rules are strictly applied. The grid size depends on the geometry of the layout which is normally very small in order of microns. Such small grid size would result in a good accuracy in applying the Finite Difference Method (FDM) used by the enhanced substrate parasitic components. Nevertheless, the number of the meshing points for such simple structure is significantly large which could develop unacceptable huge number of parasitic components for large scale circuits. As a result, the basic nonuniform meshing is adequate for small scale designs. The enhanced nonuniform rectilinear meshing relies on applying different meshing strategies on each shape independently. As illustrated in Figure 3.17, the inner DN well is meshed to consider the contact at the middle of mesh cells. Then, the interface between the DN and the P-substrate (the white area) is meshed independently. The deep P-well is meshed in the same way to satisfy the contacts rule. Finally, the interface between the DP and P-substrate is meshed. The nonuniform approach reduces the number of meshing points significantly. In this example, the number of mesh points in the uniform meshing is 81 and in nonuniform meshing is 33. The percentage of reduction relative to the uniform meshing is about 60%. This reduction in the meshing points is an indication to the reduction in the extracted number of components, which could facilitate the analysis of the large circuit. A trade-off between the accuracy and the number of the components exists in the enhanced nonuniform meshing. The enhanced nonuniform meshing is used by default in the extraction engine in addition to the basic nonuniform meshing as an option.

In conjunction with the extraction rules, 3D mesh elements for the substrate are constructed. The substrate is considered as a stack of sub-layers in the vertical direction. Each sub-layer contains multiple of wells and each well has a constant average doping. The meshing can be a basic nonuniform meshing as shown in Figure 3.18 or an enhanced nonuniform meshing as in Figure 3.19. The enhanced nonuniform rule can be summarized as that the mesh line stops at the interface of new layer. However, referring to [START_REF] Stefanucci | Influence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs[END_REF], the significant factors affecting the results of the substrate network are the meshing along the substrate and well depths and the meshing under the P-contact. Thus, uniform meshing in the vertical direction is preferred.

In the extraction phase, parasitic devices are extracted and classified based on the doping profiles and orientation. For instance, in Figure 3

AUTOMICS tool post-processing stage

In the post-processing stage, the extracted substrate netlist is ready for simulation alone to simulate the substrate parasitic components. For example, it can be used to estimate the coupling due to the activation of the lateral NPN transistor. In addition to the stand-alone simulation, the back-annotation of the original schematic netlist is possible to study the effect of the substrate coupling on the circuit performance. For example, it can be used to study the effect of the switching on sensitive low voltage analog circuits on the same substrate.

Model parameters calibration

Model calibration is a necessary step to estimate the doping concentration of the layers involved in the substrate parasitic components. These doping concentration values are stored in a parasitic model library for a certain process. The parasitic model library is called by the extracted substrate netlist to retrieve the concentration values and other model parameters such as the carrier life time and barrier potential for enhanced diode model.

In general, such a calibration process could be done through two methods:

1. Calibration using TCAD simulation:

The TCAD simulations need detailed input with respect to doping concentrations and doping profiles, which may not be provided by the foundries. The fitting between the TCAD and the actual process conditions would be onerous and time consuming task.

Industrial test benches:

Test structures implemented on the desired technology could serve as a reference for the calibration process. These test structures are measured to characterize and model the basic diode behavior as well as the interaction between different well implants due to minority carriers. They have different well shapes and distances. For one test structure, there could be many replicas placed on different positions of the wafer to consider the process variations. The calibration of the parameters are based on the measurement data.

The industrial test-benches calibration is adopted for the calibration of the parameters in AUTOMICS tool. Various test structures are fabricated for the HV-CMOS technology at ams and for the BCD technology at STMicroelectronics. Then, these test structures are extracted with AUTOMICS tool and parameters calibration is performed to fit the simulation results and measurements. This calibration procedure and parameters extraction were performed by AdMOS which is a specialized company in the field of CMOS modeling.

The calibration process principle is shown in Figure 3.20. Vertical devices need to be differentiated from the lateral ones to use different values for their model parameters reflecting the gradient of doping profile. The calibration process is controlled automatically to perform the simulations in the target circuit simulator with the same conditions that in the measurements of the test devices. The simulations are compared to measured data and an optimization algorithm is applied to tune the available model parameters to the measured curves [Moursy].

Conclusion

In this chapter, the substrate conventional components used in the commercial tools have been discussed. The propagation of the minority carriers is ignored in these components. However, in the high voltage technology, the propagation of the minority carriers is significant and should be considered. Hence, an enhanced model for diodes and resistors were explored by EPFL to consider the minority carriers propagation and the high injection conditions. A CAD tool referred to as AUTOMICS was developed to utilize these enhanced components to construct the substrate model automatically from the design layout. A model calibration is needed to estimate the doping profiles of different layers. This substrate modeling strategy could be used in the analysis of failures or as a verification step before fabrication.

Chapter 4 Proposed design flow for smart power ICs

In automotive applications, safety is a critical issue that should be insured. The smart power IC passes through many tests to emulate the harsh environment in the vehicles. However, with a good design that passes well all the post-layout simulations, it may fail during such kind of tests. The main cause of such failures reported is the parasitic lateral NPN transistors. These parasitic components are not modeled in the current commercial tools since they are layout-dependent. Besides, they can not be modeled with conventional components since multicollectors BJTs may exit.

In this chapter, the conventional design flow for the smart power ICs is discussed. Then, a proposed modification on the smart power IC design flow is presented. This modification depends on the extraction tool AUTOMICS and the enhanced components to model the substrate. An industrial test case named AUTOCHIP1 fabricated using HV-CMOS 0.35 µm technology is studied with the tool and the failure root cause is identified.

Conventional design flow for smart power ICs

The conventional principle stages in the power IC design flow is depicted in Figure 4.1. The design starts with a set of product specifications provided by a client with certain time frame. These specifications are used by the system level engineers to create a system level model for the product verifying that these specifications could be achieved. These top level simulations could serve as the initial block diagram of the system that achieve the required specifications. The system level engineer should be able to set the required specifications for each the circuit immunity to variations in process design technology, environmental conditions and electrical stresses.

In the smart power ICs technologies, the power transistor models have a safe operating area check (SOAC), where the transistors operating conditions are continuously checked during the simulations. Certain simulations are performed to ensure that the coupling between different circuits are reduced such as common mode rejection ratio (CMMR) and power supply rejection ratio (PSRR). After verifying the circuit specifications, the layout phase is started. In the layout design, many techniques are used for matching and reducing the coupling between different cells [START_REF] Hastings | The art of analog layout[END_REF]. Other checks are used to verify the proper functionality of the layout design such as layout versus schematic (LVS), design rule check (DRC), and electrical rule check (ERC). The DRC verification test is used to verify accordance of the layout to the foundry design rules which helps in preventing latch-up problems.

After these verification steps, the layout parasitic components are extracted. These components are mainly the routing metal layers parasitic resistors and capacitors and the coupling capacitors between different metal layers. Such components could affect the performance of the circuits, hence, the extracted parasitic components in conjunction with original circuit are simulated in the post-layout simulations. The post-layout simulation results are considered the decisive factor to approve the design to tape-out. In sensitive low voltage circuits and smart power ICs, the substrate should be extracted to ensure that the substrate coupling will not affect the circuit functionality.

The design modifications in these different steps are possible, however, each step down in the flow the modification becomes a burdensome task. After the design is approved, the fabrication of the chip starts in the tape-out step. This cycle could take about three to four months including the packaging and delivery.

Eventually, the chip is available and ready for further testing and measurements to validate and evaluate its functionality. On the one hand, if the chip manages to pass all these tests then the cycle of the design is done and the product is approved. The design cycle could last for approximately one year. On the other hand, if the product fails in one critical test then we have to start another step of failure analysis to identify the root cause of the failure and how to avoid it. The failure analysis depends on measurements and hand-analysis to locate the root cause that did not appear in the conventional simulation tools. The designer experience plays a major role in this step. After identifying the problem, the redesign cycle starts. Such failures would prolong the design cycle and increase the time-to-market and certainly increase the cost. In practice, this redesign cycle could be repeated several times for one product.

In the smart power ICs design, failures due to the substrate coupling are still reported in tests after fabrication. Such failures are induced owing to the automotive harsh environment and the electromagnetic interference (EMI). For example, when an electronic device receives negative voltage surge, latch-up can occur and may lead to a destructive failure or a freezing state, in the presence of current limiting techniques, that would require a disconnection of the battery to restart the circuit.

Failures due to the substrate are principally caused by the activation of the lateral parasitic NPN bipolar junction transistor. The modeling of this NPN transistor is not available in the current commercial tools. The conventional state-ofart modeling technique is based on TCAD simulations. TCAD simulations are accurate but not suitable for large scale designs. They can be used to develop a TCAD guidelines to control the substrate current [START_REF] Schenkel | Substrate current effects in smart power ICs[END_REF][START_REF] Gnani | Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits[END_REF]. The simulation of a complex system using the TCAD simulation takes relatively long time and is not suitable in practice. In addition to the TCAD simulations, fabricated test-benches are used to characterize the lateral NPN transistor and set guidelines used in design to decrease the substrate coupling noise.

Proposed design flow for smart power ICs

The proposed design flow is illustrated in Figure 4.2. Since the main substrate noise source under investigation is the lateral NPN transistor, the basic concept depends on the ability to reproduce failures due to this noise in the simulation environment as shown in Figure 4.2(a). If we successfully reproduce the failures then we are able to prevent these failures before the fabrication as in Figure 4.2(b). Consequently, using reliable tool and technology parameters, the number of redesigns due to such failures is reduced and hence the cost and time-to-market are reduced. Besides, all the simulations are done in SPICE-like simulator environment, hence, the simulation time is significantly shorter than TCAD simulations.

The proposed design flow has two additional stages in the design flow which are :

1. Failure analysis and reproduction, 2. Substrate parasitic extraction step.

Failure analysis and reproduction

The main objective of this stage is to reproduce a failure occurred in a test-chip in the simulation environment. The failure analysis engineer, after the preliminary failure diagnoses, predicts that the substrate coupling could be the cause of failure. Then, as shown in Figure 4.3, the conventional substrate failure analysis is based on the substrate parasitic components hand-extraction. Long time may be spent in the parasitic hand extraction. The accuracy in the failure analyses is not important since the most important thing is to identify the root cause of fail.

Substrate parasitic extraction using AUTOMICS

Failure occurs

Parasitic components hand extraction

Simulation and analysis

Hand-extraction Automated-extraction preliminary failure analysis

Simulation and analysis

Substrate parasitic extraction and reproduction of failure The proposed step is to replace this hand parasitic extraction with automated parasitic extraction using AUTOMICS. Since the accuracy is not an issue, the time would be the comparable factor. With fast parasitic extraction method, the failure root cause could be identified in short time. This proposed methodology could speed up the failure analysis and add comprehensive explanations based on the substrate noise coupling simulations that can be done. It should be noted that this methodology is based on the failure analysis engineer decision that the failure is due to the substrate coupling hence, it is not a full automated failure analysis tool. As the current returns back to zero this indicates that the circuit works properly. This is expected since the schematic with the conventional extract substrate parasitic components does not consider the layout aspects like the guard rings connections and voltages, as a result the lateral NPN transistor is not modeled. This proposed automated failure analysis saves the time required for the substrate parasitic extraction. Also, it could be used before the fabrication as a verification test for the design sensitivity to the latch-up structure. Obviously, using such tool would save long time for redesign and consequently lowering the cost and ameliorate the circuit design.

Proposed solutions for latch-up problems

In Figure 4.15 shows a simplified circuit for the extracted parasitic components of the PMOS transistor. The SCR structure is triggered as follows:

Vsupply R supply EXC_OUT R BD R GR R SUB C well Q 1 Q 2 Figure 4
.15: AUTOCHIP1 parasitic components equivalent circuit

• Initially, the voltage across the capacitor (C well ) is zero. The fast connection of the input source results in high current passing through the two resistors (R supply and R BD ) and the capacitor (C well ), assuming the voltage changes linearly with time, then the current can be described by the following equation:

I supply (t) = C well dV dt .(1 -exp(-t/τ 1 ) (4.1)
where C well is the parasitic capacitance between the well and ground and dV dt is the slew rate of the input voltage and the time constant τ 1 is equal to

C well • (R supply + R BD ).
• As the current is large the drop across the resistance R supply is large and voltage of the source and bulk nodes are low. The current follows the equation 4.1 till the drop across the resistor R BD is approximately 0.7V, Consequently the emitter-base junction of the PNP transistor is forward biased and the time constant τ 1 becomes approximately C well • (R supply ).

• Meanwhile, the Q1 PNP collector-base junction is still not sufficiently reversebiased since the PMOS bulk voltage is still low. When the supply voltage reaches the steady state (V 1 ), the current starts to decay exponentially according to the following equation

I supply (t) = V 1 R .(exp(- t (C well • R supply ) ) (4.2)
Hence, the voltages of the PMOS bulk and source start to increase and the collector-base junction of Q1 becomes more reverse collecting more current and passes through the substrate.

• The voltage across the substrate parasitic resistance could forward bias the guard ring and substrate junction. This junction corresponds to the emitter-base junction of the lateral NPN transistor (Q2) and it starts to conduct.

• The voltage across the resistance R sub is held to 0.7 V. According to Kirchhoff's current law, the current passing through the base of the Q2 lateral NPN transistor is equal to the current of the Q1 vertical PNP collector current minus the current passing through the substrate which is approximately equal to 0.7/R sub . If the current in the base of Q2 NPN transistor is sufficiently large and the loop gain of this SCR structure is greater than 1 (β N P N β P N P > 1), the latch-up occurs.

In order not to trigger the SCR structure at the fast connection test, we have to ensure that the vertical and lateral bipolar junction transistors are not sufficiently on to trigger the latch-up. Starting with the vertical PNP transistor, the switching on of this transistor depends on passing a large current through the R BD and the well capacitance. Since, the bulk driver circuit response is slow relative to the fast connection desired, the bulk driver switch resistance R BD is large. Consequently, the voltage across the resistance is large and switches on the vertical PNP transistor. Hence, the first proposed solution is to reduce the resistance of the bulk driver switch at the power up.

The second precaution is to modify the guard ring resistance. Adding a resistance in series with the guard ring requires an excess current through the substrate resistance to switch on the lateral NPN transistor. Thus, if the vertical transistor is turned on, the amount of current passing through the substrate resistance will not be sufficient to turn on the lateral NPN transistor and consequently the latch-up structure will not be triggered.

These precautions are done and the bulk driver resistance (R BD ) is lowered to 4 Ω and the guard ring resistance (R GR ) is risen to 5 KΩ. The simulation result of the substrate extracted network with the modified components were simulated and the simulation results are shown in Figure 4.16. The substrate voltage rises due to the injection of holes however the voltage across the guard ring resistor is also increased and the voltage difference between them is not sufficient to turn on the lateral NPN transistor. Hence, the latch-up is prevented. It should be noted that the shift in the substrate voltage is at and near the switch region and it decreases as the distance increases. Hence, the recommendation in layout design, to protect the low voltage circuits against such substrate voltage shifts, is to place them sufficiently far from the switch which can be quantitatively estimated using the proposed methodology.

Conclusion

In this chapter, we proposed a methodology for smart power ICs verification and failure analysis. This methodology is based on extracting substrate parasitic components using AUTOMICS extractor. The substrate is modeled as a network of enhanced diodes and resistors that is capable of implementing the lateral NPN transistor. The proposed methodology can be used as a verification step before fabrication to ensure that substrate coupling is tolerated by the system on chip. Apart from the verification step, it also can be used as an aid in the failure analysis if the chip fails. This failure analysis step is used to extract the substrate and highlight the reason of the failure in relatively short period compared to the handextraction. An industrial test chip designed by ams and verified by Valeo, which is referred to as AUTOCHIP1, was presented. A failure analysis was conducted in the conventional and proposed methodology. The latch-up has been simulated with the extracted netlist in transient simulation. A proposed solution to prevent latch-up with seamless changes in the design layout was discussed. The proposed methodology gives an insight of the substrate behavior and shorten the time to market and hence reduces the cost.

Chapter 5

DC-DC buck converter system level design

Nowadays, the electronic systems are extensively employed in the automotive industry. These emerging technologies are mainly deployed to offer more safe and comfortable environment for the automobile driver. The trend in the automotive technology is to enhance the vehicle connectivity to the internet as a part of internet of things (IoT) and to reduce the CO 2 emission. Consequently, the full electric vehicle (FEV) emerges as a competitive opponent to fulfill the needs of the automotive market. However, the reliability and durability are the main two features of the automotive electronic applications. Since the vehicle normally has only one supply which is the battery, this voltage has to be regulated to adapt to different electronic circuits applications.

In this chapter, we investigate the system level design of DC-DC buck converter. This system is considered as a complex test case for our investigation using AUTOMICS tool. This chapter starts with different power supplies used in the automotive industry. Then, one of the switching power converters which is the buck converter is selected for design. The system level design is explained along with the system simulation results are presented. Then, an analog-mixed signal controller is proposed to improve the capability of integration and reduce the circuit cost.

Power supplies in automotive industry

Several electronic applications are implemented in the vehicles to provide safety and comfort to the driver in addition to reducing the CO 2 emission and optimize the system efficiency. These electronic applications can be classified into three main categories [Fischer-Wolfarth13]:

Safety applications These applications are used to protect the driver in case of danger such as anti-lock breading system (ABS), air bag controller, and anti-collision radars.

Motion control applications These applications are used to control the engine, optimize the fuel consumption and assist in driving such as injection control, start-stop system, and parking assistant.

Entertainment applications These applications provide the driver with the in-car entertainment facilities such as radio, navigation system GPS, and internet connectivity.

Most of these applications need 1) an interface to the external world i.e. sensors, 2) control unit to process the data and make a decision, and 3) a power supply. Since the only power source in the vehicle is the battery which voltage is either 12V or 24V, regulators are needed to provide different voltage supplies.

Power supply classification

The power supplies can be classified into two main categories [START_REF] Kazimierczuk | Pulse-width modulated DC-DC power converters[END_REF] either linear regulators or switching regulators. Figure 5.1 illustrate this classification with some circuit examples. The advantages of linear regulators are the low noise levels and that they can be fully integrated in low voltage and low power applications. The disadvantages are their low power efficiency due to the high power dissipation and the large transistor sizes. On the other hand, the main switching regulators advantage is the high efficiency due to the low conduction losses. The disadvantages are the switching losses that can degrade the efficiency along with increasing the switching frequencies and their high noise.

Because of the periodic switching, spurs produced at the output could affect devices sensitive to such spurs like radio-frequency power amplifiers [START_REF] Tao | PWM control architecture with constant cycle frequency hopping and phase chopping for spur-free operation in buck regulators. Very Large Scale Integration[END_REF]. Also, the noise due to substrate coupling appears and becomes significant in the highvoltage applications . Recently, the switched capacitor DC-DC converters are growing rapidly in the market as a high efficiency solution for the low voltage and low power applications [START_REF] Loai | A footprintconstrained efficiency roadmap for on-chip switchedcapacitor DC-DC converters[END_REF][START_REF] Abdelfattah | A fully-integrated switched capacitor voltage regulator for near-threshold applications[END_REF][START_REF] Harjani | A unified framework for capacitive series-parallel DC-DC converter design[END_REF].

In this work, we focus on the pulse width modulator (PWM) regulators as it is widely used in the automotive industry. These PWM regulators can supply certain application or supply a linear regulator to further step down the voltage or reduce the switching harmonics. The PWM regulators can be divided into two topologies single-ended and multiple-switch PWM DC-DC converter. The multiple-switch PWM is out of the scope for this work. However, in this work we focus on the analysis and design of the DC-DC buck converter with spiral inductor.

Power supplies Linear regulators

Switching regulators PWM regulators

Resonant regulators

Switched cap regulators

Buck Boost

V i RL V o + - Buck-boost V i RL V o + - V i RL V o - + Dc-high-frequency-ac inverter V i RL V o + - Capacitive DC-DC buck V o V i L1 L1 L1 L2 L2 L2 L2 Series regulator - + R1 R2 RL V ref V i V o parallel regulator - + R1 R2 RL V ref V i Rs V o

DC-DC buck converter analysis

In this section, the principles used in the switching converter analysis are discussed. Then, the basic open loop equation describing the output voltage as a function of the input voltage is derived. Finally, the control methods used to maintain the output voltage constant is elaborated.

Switching converter analysis principles

In the analysis of DC-DC converters, three principles are used to facilitate the analysis and systematically derive the design equations for the converters [Erickson01].

Small ripples approximations

In the DC-DC converters, the voltages and currents contain some ripples due to the switching operation. Generally, the ripples should be minimized. Thus, the ripples of continuous signals can be ignored to simplify the analysis. This approximation can not be applied to the discontinuous signals such as switching node voltage. ripples ≈ 0 (

Inductor volt-second balance

The voltage across the inductor is defined as:

v L (t) = L. di L (t) dt (5.2)
If the current of inductor changes linearly over a period of T s due to switching the inductor voltage between two constant levels, then the equation 5.2 is integrated between t and t + T

s i L (t + T s ) -i L (t) = 1 L t+Ts t v L (t)dt (5.3)
In periodic steady state, the net change in the inductor current over one period is zero. Hence, the integration of the inductor voltage over one period is zero whenever the converter operates in the steady state. In transient analysis, it can not be considered as zero.

Therefore, in steady state, the average voltage across the inductor over one switching period is zero.

< v L (t) > Ts = 0 (5.4)

Capacitor charge balance

The current through the capacitor is defined as:

i c (t) = C. dv c (t) dt (5.5)
If the voltage across the capacitor is changing over a period T s , then the voltage across the capacitor can be expressed as:

v c (t + T s ) -v c (t) = 1 C t+Ts t i c (t)dt (5.6)
Therefore, in periodic steady state, the voltage across the capacitor is equal to zero. Hence, the total area (or charge) under the capacitor current is equal to zero in the steady state operation of the converter.

< i c (t) > Ts = 0 (5.7)

Derivation of large-signal equations Output voltage

Figure 5.2 shows the possible switching states assuming ideal components where the equivalent series resistance ESR is equal to zero. There are mainly two switches which are the high-side (HS) switch that connects the inductor to V in and the low-side (LS) switch that connects the inductor to the ground. The implementation of these switches could be either HS switch and diode, which is known as asynchronous converter, or HS and LS switches, which is known as synchronous converter. The asynchronous converters need only one control signal for the switch, while the synchronous converters need two control signals. The synchronous converter requires a dead-time generator to prevent short circuit.

Applying the small ripples and inductor volt-second principle, the output voltage can be expressed as follows:

V o = DV in (5.8)
where D is the duty cycle of the switching signal. Obviously, the output voltage can be controlled by changing the duty cycle of the switching signal.

In case of non-ideal components, the output voltage in the case of synchronous converter can be expressed as

V o = D.R L .V in D.R ON -HS + (1 -D).R ON -LS + DCR + R L (5.9) Vin L C ESR R L V o Switching node v L I o I L (a) HS switch is ON for DT s Vin L C ESR R L V o Switching node v L I o I L (b) LS switch is ON (1 -D)T s Figure 5.2:
The ideal switching states in buck converter where T s is the switching period and D is the duty cycle where D is the duty cycle of the switching control signal, R ON -HS and R ON -LS are the high side and low side switches on-resistances, DCR is the inductor series resistance, and R L is the load resistance.

Inductor current ripples

The inductor current slope is defined by the equation di/dt = v L /L. The inductor current ripples can be obtained by calculating the slope of the inductor current as shown in Figure 5.3.

∆i Lpp = (1 -D).V o f s .L (5.10)
where ∆i Lpp is the peak to peak inductor current ripples. It should be noted that the DC current component of the inductor current passes through the load resistor (R L ) while the AC current component is drained by the capacitor.

Based on the inductor current waveform definition, there are two modes of operation for the buck converters:

1. Continuous conduction mode (CCM): in this mode the minimum inductor current is greater than zero.

2. Discontinuous conduction mode (DCM): in the DCM, the inductor current can reach zero value. This mode is useful for light loads and relatively low input voltages reducing the silicon area and increasing the efficiency [START_REF] Fu | Switching and conduction loss analysis of buck converters operating in DCM-only scenarios[END_REF].

The boundary between the CCM and DCM can be defined by the peak current of the inductor ripples. If ∆i L = I L where I L is the average inductor current, The peak-to-peak ripple inductor current is commonly expressed as a percentage to the load current (I o ) and is known as LIR, where

LIR = ∆i Lpp I o = (1 -D).R L f s .L (5.
12)

It should be noted that the average load current is equal to the average inductor current. This equation is used for the inductor value selection. In most of the applications, LIR is suggested to be chosen between 0.1 to 0.3. Increasing the value of the inductor results in lower ripples, the time needed to charge and discharge the inductor increases which results in slower transient response. Thus, LIR represents the trade off between the inductor current ripples and transient response time.

Output voltage ripples

The current flowing through the capacitor is approximately the AC component of the inductor current. The output voltage ripples are composed of two components, one is the ripples across the capacitor and the second is the ripples across the equivalent series resistance (ESR).

Using the charge balance principle, the average capacitor current is equal to zero at steady state. Thus, over one switching period, the positive area under the current curve is equal to the negative area. Consequently, during the positive capacitor current, the voltage across the capacitor is changing from minimum to maximum voltage in time duration (T s /2). The charge stored in the capacitor during the positive current can be expressed as:

Q = t+Ts/2 t idt = C.(∆V rcpp ) = ∆i Lpp .T s 8 (5.13)
Hence, the peak-to-peak ripple voltage ∆V rcpp across the capacitor is expressed as

∆V rcpp = ∆i Lpp 8C.f s = (1 -D).V o 8 LC.f 2 s = π 2 2 .(1 -D).V o . f 2 o f 2 s (5.14)
where f o is the cut-off frequency of the LC low pass filter (f o = 1/(2π √ LC). The peak-to-peak voltage ripples across the equivalent series resistance (ESR) is expressed

∆V ESRpp = ∆i Lpp .ESR = (1 -D).V o .ESR L.f s (5.15)
Therefore, the maximum peak-to-peak output ripples voltage (∆V rpp (max)) is approximately the sum of the maximum peak-to-peak voltage ripples across the capacitor and the equivalent series resistance (ESR), as shown in equation 5.16.

∆V rpp (max) ≈ (1 -D min ).V o .ESR L.f s + (1 -D min ).V o 8 LC.f 2 s (5.16)
In addition to the output voltage ripple specifications, the output capacitor value should maintain the output voltage overshoot within the specified limits to satisfy the transient response specifications. Assume a transition in the inductor current equals to the maximum load current then the maximum voltage over shoot can be calculated using the conservation of energy principle. As the stored energy before the transition is equal to the energy after the transition.

1 2 CV 2 o + 1 2 LI 2 peak (max) = 1 2 C(V o + V ov ) 2 V ov ≈ L • (I o + ∆i L ) 2 (max) 2C • V o (5.17)
where I peak is the peak inductor current and V ov is the overshoot voltage at the output voltage.

Power Losses and efficiency of buck converter for CCM

The losses in the DC-DC buck converter is classified basically into two types:

1. Conduction losses: These losses are due to the non-idealities of the MOS switches and finite resistance of the inductor winding. To minimize the conduction losses, the on resistance of the MOSFET switches should be minimized resulting in large size transistors. These losses are proportional to the load current (I o ) and inversely proportional to the input voltage (V in ).

Switching losses:

These losses result from charging and discharging of the parasitic capacitance attached with the MOSFET transistors. At the switching node, this parasitic capacitance mainly comes from the drain-to-bulk capacitance of the high side and low-side switches and any routing capacitance due to layout at this node. At the gate of the MOSFET switches, the losses are due to the charging and discharging of the parasitic capacitance at the gate. These losses are independent of the load current (I o ) and proportional to the square of the input voltage (V in ).

The efficiency of the converter is the ratio between the input and output power and can be written as

η = P o P i = P o P o + P loss = 1 1 + P loss /P o (5.18)
where P o is the output power and P loss is the sum of the conduction and switching losses. The conduction losses (P cond ) and the switching losses (P switching ) versus the load current is shown in 5.4. At light load conditions, the efficiency drops due to the switching losses while in the high load conditions the efficiency drops due to the conduction losses.

Similarly, the losses and output power are plotted versus the input voltage in Figure 5.5. The efficiency drops at low input voltages due to the conduction losses while at high input voltages the efficiency drops due to the switching losses.

Systematic design procedure

The design procedure for the open loop buck converter components are illustrated in Figure 5.6. A GUI using MATLAB is developed to systematically solve the design equations and evaluate the components values. The GUI allows the iterations to calculate the ripples voltage and inductor current using the practical components values. The efficiency versus output current and input voltage are plotted.

Derivation of small-signal equations

The dynamics of the buck converter can be modeled through an AC equivalent circuit of the converter. These models are important in the design of the closed loop converter. In the closed loop converter, the control block is used to sustain the output voltage constant against load current and input voltage variations.

The loop stability is one vital aspects that is investigated using the smallsignal equations. To construct the AC equivalent model, the inductor volt-second balance and the capacitor charge balance are generalized for transient analysis not only steady state. The switching ripples in the inductor current and the output voltage are removed by averaging the voltage across the inductor and the current across the capacitor, respectively, in one switching period. Then, using the perturbation and linearization principles, one can deduce the AC equivalent model for the open loop buck converter [Erickson01].

The AC equivalent model for the buck converter is derived based on the inductor volt-second balance and capacitor charge balance principles.

• Inductor Volt-second balance

The voltage across the inductor is

v L = L di L dt = d.(v IN -v o ) + (1 -d).(-v o ) (5.19)
where d is the duty cycle, i L is the inductor current, v IN and v o are the input and output voltages. Averaging the equation 5.19 to remove the ripples effect

L d < i L > Ts dt = d.(< v IN > Ts -< v o > Ts ) -(1 -d).(< v o > Ts ) (5.20)
Each averaged quantity composed of DC and AC component. For instance, for a quantity x, the DC component notation is X and the AC component notation is x.

L d(I L + i L ) dt = (D + d).(V IN + v IN ) -(D + d).(V o + v o ) -(1 -D -d).(V o + v o )
(5.21) Ignoring the second order terms and equate the AC terms in both sides, results in the following equation

L d i L dt = d.V IN + D. v IN -v o (5.22)
• Capacitor charge balance The averaged current through the capacitor in transient is expressed as

C. d < v c > Ts dt =< i L > Ts - < v o > Ts R L (5.23)
given that v c = v o , hence the perturbed current in the capacitor is

C. d v o dt = i L - v o R L (5.24) • Input port modeling The input current (i IN ) is i IN = i L .d (5.25)
averaging and perturb the input current, the AC component of the input

current is i IN = D. i L + d.I L (5.26)
• load current perturbations modeling The load current is

< i o >= < v o > R L + r L (5.27)
where r L is the perturbation in the load resistance. The AC component of the output current is

i o = -I o . r L R + v o R L = I load + v o R L (5.28)
An equivalent AC model for the buck converter can be composed using the equations 5.22, 5.24, 5.26, and 5.28, along with considering the parasitic resistances ESR and DCR as zeros, as in figure 5.7.

The output voltage and the inductor current can be expressed as a function of the different perturbations as follows

v o (s) = G vd (s). d(s) + G v vin (s). v in (s) -Z o . I load (5.29)
where G vd (s) is the control-to-output voltage transfer function, G v vin (s) is the line-to-output transfer function, and Z o is the output impedance.

i L (s) = G id (s). d(s) + G i vin (s). v in (s) + A i . I load (5.30)
where G id (s) is the control-to-inductor current transfer function, G i vin (s) is the line-to-inductor current transfer function, and A i is the output current-to-inductor current transfer function.

From the figure 5.7, the transfer functions G vd (s), G v vin (s), and Z o can be obtained as follows

G vd (s) = v o d | v in =0, I load =0 = V in 1 + s ωo.Q + s 2
G vd (s) = V in (R L +DCR) R L .(1+SC.ESR) 1+ s ωo.Q + s 2 ω 2 o G id (s) = V in (R L +DCR) (1+SC.ESR) 1+ s ωo.Q + s 2 ω 2 o G v vin (s) = D•R L (R L +DCR) (1+SC.ESR) 1+ s ωo.Q + s 2 ω 2 o G i vin (s) = D R L +DCR 1+SC(R L +ESR) 1+ s ωo.Q + s 2 ω 2 o Z o = R L (R L +DCR) (1+SC.ESR).(SL+DCR) 1+ s ωo.Q + s 2 ω 2 o A i = R L (R L +DCR) 1+SCESR 1+ s ωo.Q + s 2 ω 2 o Q = √ (R+DCR).LC.(R L +ESR) C.ESR.R L +L+C.DCR.(R L +ESR) ω o = R L +DCR LC.(R L +ESR)
In order to maintain a constant output voltage disregarding the variations in the input voltage and/or the load current. A feedback loop should be added to control the duty cycle. Two quantities can be sensed and fed to the control loop, either the output voltage or the inductor current. When sensing the output voltage only, it is called voltage mode control, while sensing the inductor current and the output voltage is known as the current programmed mode control.

DC-DC buck converter system level design

In this section, we are going to show the system level design. The control loop, to sustain the output voltage constant, is either voltage mode control or current programmed mode control. We demonstrate the advantages and disadvantages of each control circuit.

Table 5.2 shows the DC-DC buck converter design specifications. The components values that are used to satisfy the above conditions are shown in Table 5.3. Using the practical values the peak-to-peak output voltage ripples is reduced to 0.13% and the inductor current ripples becomes 11.2 %. The efficiency is calculated at maximum input voltage and maximum load current.

Voltage mode control (VMC)

In this mode, the output voltage is sensed using a sensing circuit usually a voltage divider and compared to a reference voltage generated by a well controlled The design of the PID compensation circuit can be done to obtain certain crossover frequency and consequently estimate the converter response time, while achieving the required phase margin. The design steps to maintain certain phase margin (φ m ) at certain crossover frequency (f c ) can be listed as:

G L f L f z f p1 f p2 f c 0.1f L -90° 0
1. Calculate the gain and phase margin of the loop-gain without the compensator at the desired f c .

2. Determine the amount of phase shift (θ) required to achieve the required phase margin (φ m ).

3. The frequencies f z and f p1 can be obtained by the following expressions:

f z = f c . 1 -sin(θ) 1 + sin(θ) & f p1 = f c . 1 + sin(θ) 1 -sin(θ)
4. Find the G L to position the f c at 0dB.

G L = loop gain without compensator * f z f p 5.
The low frequency f L is chosen arbitrary less than f c /10, the high frequency f p2 represents the pole introduced by the practical opamp.

Practically, the f c is chosen to be 10 ∼ 20% of the switching frequency in order not to amplify the switching ripples.

V o = V ref + (R f /R i )(V ref -V i ) Since the DC component of V i is equal to V ref then output DC component is only equal to V ref .
The amplifier is modeled to have an infinite DC gain and limited bandwidth. To get a proportional compensation gain of 10, pure resistances are used of values R f = 100 kΩ and R i = 10 kΩ.

The gain block (Gv2c1) is used to represent the voltage to current conversion gain which is equal to 3.39 × 10 -4 . The repeating sequence block represents a sawtooth voltage signal with switching frequency (f s = 330 kHz) and changes from 0 V to 2.5 V. This sawtooth voltage signal is converted into current via the gain block (Gv2c2) which gain is 2.67 × 10 -5 . The slope compensation is performed by subtracting the ramp current (I ramp ) from the control current (I c ). A limiter is used to limit the maximum value of (I c ). The subtraction result is amplified by an additional gain (GCM) which is equal to 4.

The inductor current is scaled down using the gain block (AiL = 1/2000). The scaled inductor current (I ′ L ) is subtracted from the compensated control current (I comp ). If the output of subtraction is negative, the Reset is logic 0 otherwise it becomes logic 1 and the output of SR latch is 0. When the SR latch output is 0, this indicates that the HS switch is turned off and the LS switch is going to turn on after the dead-time. The set input of the SR latch is set to 1 periodically at the beginning of each switching period using short pulses. These short pulses are generated by comparing the sawtooth voltage signal to a small voltage V1. The duration of the short pulses (T sp ) can be expressed in terms of V1 as T sp = T s × V 1/V P where T s is the switching period and V P is the peak voltage of the sawtooth signal. Figure 5.25 shows the transient load regulation as the output voltage changes when the load resistance changes from 25 Ω to 5 Ω with a constant input voltage of 15 V. The maximum overshoot voltage is about 100 mV. Figure 5.26 shows the transient line regulation as the output voltage changes when the input voltage changes from 15 V to 5 V when the load current is at 0.1 A. The estimated system level efficiency versus the load current and the input voltage is shown in Figures 5.27 and 5.28. The simulation results of the system show that the output voltage has a static error which can be eliminated using a PI compensator as will be discussed in the next section. The transfer function of an ideal PI compensator is defined as follows:

G comp (s) = K p . s + K i /K p s (5.51)
where K p and K i are the proportional and integral gains of the PI compensator.

To design a PI compensator, the loopgain crossover frequency should be defined which is 40 kHz in our case. The low frequency zero (f z = 1/(2π×K i /K p )) should be located at least less than 1/10 of the crossover frequency in order not to affect the loopgain phase margin, i.e., f z = 4 kHz. However, circuit realization of such low frequency is difficult to be integrated. For instance, Figure 5.29 presents a simple transconductance PI compensator circuit. The PI transfer function is given as

A(s) = vc H divider . vo = g m R z s + 1/(C z R z ) s + 1/(C z R o )
, f orRo >> Rz (5.52)

From this transfer function, a proportional gain of g m R z is designed to get the desired loop gain crossover frequency. The low frequency zero is located at ω z = 1/(C z R z ). Hence, for f z = 4 kHz if R z = 10 kΩ, the capacitor needed C z is about 4 nF which is an off chip component that increases the cost of the converter.

gm The transfer function of the ideal system versus the transfer function of the circuit level assuming infinite output resistance is given by:

+ _ R o R z C z v ref V o . H divider v c
G comp (s) = g m .R z s + 1/(C z R z ) s = K p . s + K i /K p s (5.53)
From equation 5.53, the zero corner frequency depends on the value of the capacitor C z which is located in path 'B'. The proposed solution is to implement the proportional path 'A' in analog amplifier and to implement the integral path 'B' using a digital integrator. Figure 5.31 shows the integral path with a certain gain to have a response comparable to the analog integrator. Hence, the off chip capacitor C z will not be used.

The integral path consists of an ADC, a digital integrator and a DAC. First, the ADC is realized by a discrete-time single bit Σ∆ modulator. The single bit Σ∆ first order modulator is selected to simplify the design and reduce the silicon area. The Σ∆ system block diagram is shown in Figure 5.32. Since the signal-of-interest is the error signal v e (t) which is a low frequency signal, the Σ∆ sampling frequency can be minimized. However, increasing the sampling frequency results in reducing the integrator response time and consequently, the to vary from 300 Hz to 1.4 kHz when the load current changes from 0.05 to 0.6 A, respectively. Hence, the zero corner frequency of the PI compensator is selected to be 300 Hz.

A single bit Σ∆ modulator is used with a sampling frequency of 5.28 MHz. This sampling frequency is used to achieve a high resolution after decimation. The decimation ratio is 256 and the number of bits at the output is 8 bits. Hence, the integrator response time equals to 45µs which results in an acceptable transient response for the system.

Figure 5.36 shows the output voltage at minimum load current with only proportional amplifier and with PI compensator. The PI compensator eliminates the steady-state error voltage and keeps the error in output voltage within 3%. The proposed circuit shows idle pattern oscillation due to the presence of relatively low DC voltage at the input of the Σ∆ ADC. This pattern is limited to a very small value that can be tolerated by the system. For the proposed solution, the integrator gain (K i /K p T ) can be changed to control the settling time of the output voltage. In Figure 5.37, the output voltage response due to a pulse change in the load resistance from 50 Ω to 5 Ω for different integrator gains is shown. As the integrator gain reduces, the settling time increases.

In order to estimate the area of the proposed system, VHDL code for the digital part is generated directly from the Simulink using the HDL coder tool. Then, it is synthesized and laid out using 0.35 µm HV-CMOS technology. The estimated area is about 0.05 mm 2 and the reported number of gates used is 180 gates, with an estimated power consumption of 0.35 mW at a supply voltage of 5 V. An estimation for the area of the sigma-delta ADC is 0.017 mm 2 and the DAC area is about 0.034 mm 2 . Hence, the total estimated area is about 0.1 mm 2 . These metrics highlight the simplicity and the integration potential of the proposed control loop.

Conclusion

In this chapter, the basic principle and operation of the DC-DC buck converter were discussed. A systematic design procedure for the open loop components was developed. The pros and cons of the voltage mode control (VMC) and current programmed mode control (CPM) were discussed. Based on this discussion, the current programmed mode control was selected since it contains an inherent current limiting that protects the circuit against the overcurrent conditions especially the startup in-rush current. Also, it could have a simple compensation circuit either proportional or proportional-integral compensation circuit. A proposed system for an analog-mixed PI compensator was proposed. It attempted to alleviate the usage of an external capacitor in the pure analog compensation circuit along with relaxing clock speed constraints of the digital circuit in the fully digital PI solutions. Simulation results proved the functionality of the proposed system. The digital circuit occupied an area of 0.05 mm 2 in the system and its power consumption can be neglected relative to the rest of the system. The whole solution area is estimated to be approximately 0.1 mm 2 . The proposed solution can be easily mapped to different DC-DC buck converters specifications. The system level of CPM control buck DC-DC converter is going to be implemented on the circuit level. It will be used to simulate the substrate coupling effects on the sensitive bandgap circuit in the next chapter.

It should be noted that in the system level, we compared the currents directly. However, in the circuit level, we converted the current into voltage and compared the voltages.

DC-DC buck converter circuit building blocks

In Figure 6.1, the DC-DC buck converter circuit level block diagram is illustrated. For each block, the circuit level is going to be explained in coming sections. All the circuits are developed using the AMS 0.35 µm HV CMOS technology.

Switches and drivers circuits Switches

The switches are the main contributor in the conduction and switching power losses. To minimize the conduction losses the ON resistance should be as low as possible. However, there would be a trade-off between the conduction and switching losses.

As shown in Figure 6.3, the switching system comprises the HS switch (M HS ), Sense transistor (M sense ), and LS switch (M LS ) transistors. In order to sustain the high voltage, HV transistors were used that are able to handle upto 50 V across the drain-source junction. The HS and LS switches were sized to have an ON resistance of 0.5 Ω. The sense transistor is used to duplicate the resistance of HS switch but with a multiplication factor of 2000 (R sense : R HS = 2000 : 1).

The sense transistor drain voltage (V sense ) is used for the comparison between the inductor current (I L ) and compensation ramp current (I comp ). The LS switch is implemented using isolated DNMOS transistor which means that the DNMOS transistor is built in a deep N-well. This would reduce the HV perturbations on the rest of the circuits. The transistor resistance is extracted via biasing the transistor with a DC current of 0.6 A and measure the drop voltage. The transistor gate capacitance can be extracted via DC operating point parameter (C gg ). Also, from transient simulations, by biasing the gate with a pulse voltage source and a known resistance (R gate ) then measure the rise time (t r ), the gate capacitance can be estimated by (C gate ≈ t r /[2.2 × R gate ]). In the design, we consider the larger capacitance value as a worst case design. Tables 6.1 and 6.2 summarize the specifications of the switching system.

Pulse level shifter circuit

The pulse level shifter is the interface circuit between the low and high voltage signals. It is responsible for translating the input voltage levels of 0V and VDD into PVSS and HV Vin.

The pulse level shifter circuit used is shown in Figure 6.7. The transistors M N 1,2 are the input devices that acquire the low input pulses (0-5 V). These transistors are HV transistors and are able to sustain upto 50 V across their drain-source junctions. M P 1,2 are cascode HV transistors in which the gates are biased at PVSS. M N 3,4 and M P 3,4 are cross coupled inverters forming a latch that swings between PVSS and HV Vin. M N 5 and M P 5 form the output stage to deliver the required current to the next stage.

In case of the input voltage (NPULSE) is 0V and the output voltage (HS buffer in) is (HV Vin), then M N 1 is OFF and M N 2 is ON. M P 1 is OFF and M P 2 starts to conduct current moving from the deep triode region to linear region. V o1 starts to decrease from HV Vin towards PVSS. Once the V o1 crosses the threshold input voltage of the latch, the latch outputs V o1 and V o2 become PVSS and HV Vin. Consequently, the output voltage (HS buffer in) becomes PVSS. Finally, the M P 2 becomes in cut off region and M P 1 is in deep triode region.

Similarly, the same steps can be done for 5V input voltage. The advantage of this circuit is its acceptable response time since most of the transistors swings are limited to 5V.

Bandgap circuit

The bandgap circuit is designed to supply the reference voltage and the reference currents required in the system. The reference voltage is maintained at 1.2 V. A conventional voltage to current converter as in [START_REF] Qadeer | A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature[END_REF] is designed to supply a reference current of 10 µA.

A slew rate limiter is added at the reference bandgap output to ramp up the bandgap slowly to avoid any overshoots in the system. The ramp up time is designed to be about 350 µs. The circuit used in the bandgap will be shown later.

Oscillator circuit

The oscillator circuit is shown in Figure 6.10(a). It comprises three cascaded inverters. The first stage is a current starved cell as shown in Figure 6.10(b) While the other two stages are conventional inverters. The capacitors C2 and C3 are used to bound the voltage swing of V2 within the VDD and ground.

In Figure 6.10(b), M P 1 and M N 1 are used to supply a constant current for charging and discharging the capacitance C1 through the inverter transistors M P 2 and M N 2. M P 3 and M N 3 are used to provide an alternative path for the current source to maintain the voltages V1 and V2 constants and consequently, M P 1 and M N 1 are always in saturation region.

In case of equal charging and discharging currents (I), the oscillation frequency of this circuit is expressed as:

f = I 2 × C × ∆V (6.4)
Where C is the total capacitance at node V2 (C = C1 + C2 + C3) and ∆V is the change in voltage of node V2. If the second inverter has equal high and low threshold voltage then the voltage ∆V can be expressed as

∆V = V DD × C1 C1 + C2 + C3 (6.5)
In this design, the values of the capacitors are C1 = 900f F and C2 = C3 = 600 f F . The charging and discharging currents are the same with a value of 10 µA. Therefore, ∆V is approximately 2 V . Hence, the oscillation at the output is about 1.2 M Hz. This frequency is divided by 4 to maintain the required frequency.

Trimming current sources are used to fine tune the oscillation frequencies. These trimming bits are not shown in Figures.

is 15 V. The overshoot at the output voltage is limited to 0.2 V. Figure 6.15 also shows the results with PI compensator circuit which is formed by the implemented proportional amplifier in addition to an external analog integrator. Figure 6.16 shows the transient line regulation when the input voltage changes from 5 V to 15 V with a load current of 0.1 A.

Figure 6.17 shows the calculated efficiency from the circuit simulations. At low load currents, the simulated efficiency values are higher than the corresponding system values. As in the system level, we overestimate the parasitic capacitance values hence the switching losses in system level are more than the circuit level. It should be noted that the switching losses are the dominant losses in the low load current values.

Performance degradation analysis

The root cause of this performance degradation was identified as the PAD selection. The main issue is that the bandgap and the error amplifier outputs were connected to HV PADs.

In Figure 6.25, the parasitic components from the switching node to the bandgap or the error amplifier output are illustrated. For each change in the switching node, a parasitic current is coupled to the bandgap voltage and error amplifier outputs. Consequently, the voltages of the bandgap or the error amplifier are varied for each transition in the switching node. Figure 6.26 shows large variations in the error amplifier output, however, this voltage should not contain such variations and should be almost constant. Therefore, this coupling degrades the control loop response and the overall system performance.

In our design, we simplify the layout and use only the DNWELL of the PMOS and NMOS transistors and the Nwells of the BJTs in the bandgap as shown in Figure 6.30. The DNWELL of the PMOS represents the PMOS source and bulk terminals which are connected to the input high voltage while the DNWELL of the NMOS is the drain which is pulled down below ground.

To verify the proposed methodology with the DC measurements, we assumed two test cases:

• Test case 1: the LS switch NMOS transistor source terminal is connected to ground. This means that the injected current is divided into the body and substrate diodes.

• Test case 2: the source of the LS switch transistor is disconnected. This means that the injected current is passed only through the substrate diode.

Through these two test cases we kept the PMOS NWELL connected to high voltage of 15 V.

Test case 1: the body and substrate diodes are considered

The substrate parasitic components are extracted which are mainly the lateral BJTs between the NMOS DNTUB and PMOS DNTUB and bandgap NTUB. In the simulation test bench, the extracted substrate netlist is back-annotated to the original schematic of the LS and HS switches and the bandgap circuit. The injected current is swept from 0.01 A to 0.8 A. We are setting a functional threshold voltage for the bandgap voltage of 1.16 V which represents a 3% deviation from the reference voltage. Below this threshold we assume that the reference bandgap is perturbed. Hence, we assumed a maximum variation of 3 % in the bandgap voltage which is conventionally acceptable. Figure 6.31 shows the reference bandgap voltage versus the injected current in the simulations and measurements. The simulation results show a good agreement with the measurement points. The reference bandgap voltage did not pass the functional threshold voltage even when the injected current is about 0.8 A.

This can be explained in Figure 6.32 that shows the different current components of the injected current. Most of the injected current passes through the NMOS LS switch which can be divided into the body diode current and transistor leakage current. The remaining part of the injected current flows inside the substrate. Large portion of this remaining current is recombined and appears as a substrate contact current. The second part is coupled to the PMOS HS switch DNTUB since it has a high voltage and near the injecting point. This collection of minority carriers results in increasing the power consumption as it drains more current from the supply. The third part which is considerably small is coupled to the bandgap Nwells. In this test case, we disconnect the source contact of the LS switch, hence, prevent the current from flowing in the body diode. The substrate diode is injecting the current in the substrate. This current is divided into recombination substrate current and current collected by the HS switch DNTUB. Figure 6.33 shows simulated results and the measurements. For high current values, the simulated data shows greater effect of the injected current on the bandgap rather than the measurements. The main reason of this deviations is that in the chip many other N-wells can serve as a collecting points while in the simulation, we are only simulating the injecting point and two other collecting points which are the bandgap and the HS switch DNTUB. In Figure 6.33, the bandgap fails to sustain its reference voltage when the injected current becomes higher than 300 mA. This injected current lowers the bandgap voltage below the 3% threshold that we assumed. Figure 6.34 shows the injected current components in simulation results. Most of the injected minority carriers are recombined in the substrate that forms the substrate current. The second component is the HS switch DNTUB that forms a guard to limit the propagation of minority carriers. The rest of the current is coupled to the bandgap. where T switching is the switching period and I av (load) is the average load current. T d (total) is approximately 340 ns and the maximum load current is 0.6 A, hence, the maximum average dead-time current is 67 mA. In the normal operation, the source of the LS switch is connected to ground. Hence, from the test case 1, we can justify that the bandgap reference voltage will not be affected by the current injected in the dead-time.

Conclusion

In this chapter, we discuss the circuit implementation of the current programmed mode DC-DC buck converter. The circuit of each block used in the system was described. Circuit simulation results were shown in order to validate the performance. The chip was fabricated using 0.35 µm HV-CMOS technology. The measurement setup and results were elaborated. A verification step to estimate the effect of the injected minority carriers on the bandgap reference voltage was performed by the AUTOMICS tool. The DC measurements and the simulation results show a good agreement which validate the proposed methodology.

are not able to model the substrate coupling between different circuits. Hence, we proposed an extra verification step before fabrication. This step aims at extracting the substrate parasitic components and checking the mutual effects between the different circuits on the same die.

We designed a complete system for DC-DC buck converter as a case study for the tool. The DC-DC converter is current programmed mode control. On the system level, we have proposed a technique to integrate PI compensation circuit in low frequency applications used in automotive. The chip was fabricated on 0.35µm HV-CMOS technology. We analyzed the mutual coupling between the HV switches and the bandgap. The extracted substrate simulation results and the measurements showed a good agreement to each other.

Future work

In this thesis, we have investigated the minority carriers propagation from the design point of view as we have proposed an extra verification step and also from the failure analysis point of view. However, points for future work can be as follows:

1. High-level level modeling for the substrate noise: the main drawback of our proposed methodology is that it needs the layout of the design. This could be available in late stage of design and the proposed modifications may result in significant changes in the layout that could prolong the layout phase. Consequently, if the substrate coupling information could be estimated in the schematic, it would facilitate the layout phase. This would require several components to estimate the protection guard rings behavior in schematic environment.

2. Smart power ICs floorplanning: a complete automated floorplanning can be proposed based on the criteria of the substrate coupling. Since the placement of the components can be optimized to minimize the substrate coupling between each component. This would need a more developed CAD work to optimize the placement of the components based on simulation results.

3. Investigate pulse skipping techniques in DC-DC converters: pulse skipping techniques and other techniques should be investigated in order to improve the efficiency of the DC-DC converter at low load current range.

4. Investigate the substrate coupling in capacitive DC-DC converters: since the capacitive DC-DC converters are the recent trend in the ultra low power applications, the substrate coupling problem could be investigated.

High-side switch losses

Conduction losses:

The current through the high-side switch is expressed as

i HS =      0 , 0 ≤ t < t d i l , t d ≤ t ≤ DT s + t d 0 , DT s + t d < t ≤ T s
where i l is the inductor current and T s is the switching period. The conduction loss in the resistance R ON -HS is given by Thus, for designs with small LIR, the small ripples approximation is acceptable to facilitate the losses and efficiency calculations. Therefore, the conduction losses in the HS-switch is From equation 3, the maximum conduction loss in HS-switch occurs when the input voltage is minimum and the duty cycle is maximum at the maximum load current, i.e. R L is minimum.

switching losses:

Assume that at the switching node, there is a capacitance C sw which represents the equivalent capacitance of the drain-to-bulk capacitance of LS-and HS-switches. The switching losses occurs due to charging of C sw through the HS-switch from -V D to V in [START_REF] Fu | Switching and conduction loss analysis of buck converters operating in DCM-only scenarios[END_REF]. The switching losses can be estimated to be

P Lswitching (C sw ) = 1 2 .f s .C sw .(V in + V D ) 2 ∼ = 1 2 .f s .C sw .V 2 in = f s .C sw .R L 2.M 2 vDC .P o (4
) where M vDC is the output to input voltage ratio (V o /V in ).

Another source of switching losses is the gate capacitance of the MOSFET. The switching losses occurs due to charging and discharging of the gate capacitance C gs and C gd while turning on and off. Assume that the voltage of the gate changes from V in to the V in -V DD charging the c gs . while turning on a losses of 1 2 .c gs .V DD and the same amount is lost while turning off. Hence, the switching losses due to the gate capacitance is

P Lswitching (C cgs ) = f s .C gs .V 2 DD (5)
For the C gd , during the turn on of the HS-switch the gate voltage is saturated at miller plateau voltage (V GP ) and the the drain voltage changes from -V D to V in [START_REF] Brown | Power MOSFET basics: Understanding gate charge and using it to assess switching performance[END_REF]. After the drain voltage reaches its final value, the gate voltage continues to decrease to V in -V DD . Consequently, the voltage across C gd changes from V GP + V D to V GP -V in , hence, the voltage change across the capacitor is V in + V D . Similarly, when turning off the voltage change across the capacitor is the same.

The total switching loss due to c gd is

P Lswitching (C gd ) = f s .C gd .(V in + V D ) 2 ∼ = f s .C gd .V 2 in (6)
From the equations 3, 4, 5, and 6, then the total losses in the HS-switch transistor is where I o is the average inductor current or the load current and T s is the switching period. Then, the conduction losses in the LS-switch is

P HS-switch = D.
P Lcond (LS) = I 2 LSrms * R ON -LS = (1-D-2t d /T s ).I 2 o .R ON -LS = (1-D-2t d /T s ). R ON -LS R L (8)
2. switching losses Consider the capacitance C sw as a result of the drain-tobulk capacitance of LS-and HS-switches. The switching losses occur due to charging of C sw through the LS-switch from -V D to zero. The switching losses can be estimated to be

P Lswitching (C sw ) = f s .C sw .(V D ) 2 (9)
The losses due to the gate capacitance C gs , while turning on a losses of

Body-diode losses

The current through the body-diode is

i D =      I o , 0 ≤ t ≤ t d I o , DT s + t d ≤ t ≤ DT s + 2t d 0 , elsewhere
The rms current is

I Drms = I o . 2t d T s (13)
The power loss in the resistance associated with the body-diode R D is

P RD = I 2 Drms .R D = 2t d T s .I 2 o .R D = 2t d T s . R D R L .P o (14)
The power loss associated with the diode built-in potential voltage is

P V D = I D (average).V D = 2t d T s .I o .V D = 2t d T s . V D V o .P o (15)
From the equations 14 and 15, the total losses in the body diode P D is

P L Diode = 2t d T s . R D R L .P o + 2t d T s . V D V o .P o ( 16
)
Inductor power loss

The losses in the inductor is mainly due to the inductor winding resistance

Series resistance of capacitor power loss

The rms current of the capacitor current is

I crms = ∆i Lpp √ 12 = V o .(1 -D) √ 12.f s .L (18)
The power loss in the filter capacitor is

P LESR = ESR.I 2 crms = ESR. V 2

Résumé

L'industrie automobile est un marché en pleine croissance pour les circuits intégrés de puissance. Les circuits intégrés de puissance sont des systèmes électroniques miniatures qui apportent de nouvelles fonctionnalités aux véhicules. La robustesse et la fiabilité des produits électroniques embarqués dans les véhicules sont des enjeux majeurs. Il arrive pourtant que des défaillances dues au couplage par le bruit de substrat se produisent après la fabrication. L'origine de ce bruit de substrat vient de l'injection de porteurs majoritaires (trous) et minoritaires (électrons). Dans la première partie de cette thèse, nous étudions une nouvelle technique de modélisation proposée par un groupe de recherche à l'EPFL. Cette modélisation permet d'extraire les composants parasites du substrat en tenant compte des porteurs majoritaires et minoritaires. Un outil de CAO (AUTOMICS) a été développé par notre équipe à l'UPMC et est utilisé pour extraire le réseau des composants parasites de substrat s'appuyant sur les modèles de l'EPFL.

Dans la deuxième partie de ce travail, nous introduisons une nouvelle méthodologie pour la conception des circuits intégrés de puissance et l'analyse des défaillances avec l'outil AUTOMICS. Nous mettons en évidence les défaillances dues à un couplage par les porteurs minoritaires dans le substrat (électrons). La méthodologie proposée est validée sur un cas d'étude industriel. Ce cas d'étude a été conçu par l'entreprise ams et validé par l'entreprise Valeo. Ce cas d'étude a un problème latch-up. Ce problème n'a pas été identifié par des simulations électriques SPICE classiques. Grâce à notre méthode, nous sommes parvenus à reproduire le phénomène de latch-up dans l'environnement de simulation SPICE.

La troisième partie de ce travail présente le fonctionnement et la conception au niveau circuit d'un convertisseur de tension DC-DC. Le circuit a été fabriqué en utilisant la technologie HVCMOS 0.35µm. Nous avons modélisé l'effet du couplage par les courants de substrat entre l'agresseur et la victime et présentons des résultats de simulation cohérents avec les mesures.

4 vii

 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii 0.2 Méthodologie pour la vérification des circuits intégrés de puissance intelligents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv 0.2.1 Analyse de défaillance . . . . . . . . . . . . . . . . . . . . xxvii 0.2.2 Extraction des parasites du substrat . . . . . . . . . . . . xxviii 0.3 Convertisseur de tension DC-DC . . . . . . . . . . . . . . . . . . xxix 0.3.1 Fonctionnement du convertisseur DC-DC . . . . . . . . . . xxx 0.3.2 Effets du couplage de substrat sur la tension du bandgap . xxxiii 0.3.3 Mécanisme d'injection du courant dans le substrat . . . . . xxxiv Cas de test 1 : on considère les diodes de bulk et de substratxxxvi Cas de test 2 : on considère seulement la diode de substrat xxxvii 0.4 Etude de cas industriel : Autochip 1 . . . . . . . . . . . . . . . . xxxviii 0.4.1 Méthode classique d'identification du problème . . . . . . xxxix 0.4.2 Proposition d'identification du problème . . . . . . . . . . xl 0.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xli 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . .List of Figures

3. 1

 1 PN junction at forward biased and the minority carriers profiles . 3.2 Total recombination of minority carriers in two conventional PN junctions connected face-to-face . . . . . . . . . . . . . . . . . . . 3.3 Equivalent circuit of a differential P-type element considering minority carriers diffusion . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Diffusion of electrons through a piece of P-type with a cross section of A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Minority carriers propagation in circuit representation . . . . . . . 3.6 Minority carriers propagation in PI equivalent circuit representation 3.7 Enhanced model for semiconductor resistor considering minority and majority carriers . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Equivalent circuit for enhanced diode model . . . . . . . . . . . . 3.9 Equivalent circuit for enhanced Homojunction model . . . . . . . 3.10 Basic cross-section in HV-CMOS technology for isolated DNMOS and DPMOS conventional parasitic components . . . . . . . . . . 3.11 Basic cross-section in HV-CMOS technology for isolated DNMOS and DPMOS enhanced parasitic components . . . . . . . . . . . . 3.12 Proposed substrate parasitic extraction flow . . . . . . . . . . . . xi 3.13 HV-CMOS technology typical cross-section including wells containment relations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Hierarchical parasitic components in HV-CMOS technology . . . . 3.15 BCD technology typical cross-section For DPMOS and DNMOS . 3.16 Basic nonuiform rectilinear meshing in HV-CMOS technology . . 3.17 Enhanced nonuniform rectilinear meshing in HV-CMOS technology 3.18 Basic nonuniform rectilinear vertical layers meshing in HV-CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.19 Enhanced nonuniform rectilinear vertical layers meshing in HV-CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20 Technology parameters extraction flow . . . . . . . . . . . . . . . 4.1 Conventional smart power IC design flow . . . . . . . . . . . . . . 4.2 Proposed smart power IC design flow . . . . . . . . . . . . . . . . 4.3 Proposed failure analysis due to substrate coupling using AU-TOMICS tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Proposed substrate parasitic extraction using AUTOMICS tool ..4.5 AUTOCHIP1 regulation loop block diagram . . . . . . . . . . . . 4.6 AUTOCHIP1 Power stage circuit . . . . . . . . . . . . . . . . . . 4.7 AUTOCHIP1 high side switch reverse protection scheme . . . . . 4.8 AUTOCHIP1 damage after battery connection . . . . . . . . . . . 4.9 AUTOCHIP1 failure analysis using emission microscope EMMI . 4.10 AUTOCHIP1 parasitic hand extraction . . . . . . . . . . . . . . 4.11 AUTOCHIP1 parasitic extraction using AUTOMICS tool . . . . . 4.12 AUTOCHIP1 simulation testbench . . . . . . . . . . . . . . . . . 4.13 Simulation of AUTOCHIP1 schematic without the substrate network 4.14 AUTOCHIP1 Substrate network simulation. The latchup occurs and a current of 1A is drawn from the supply. . . . . . . . . . . . 4.15 AUTOCHIP1 parasitic components equivalent circuit . . . . . . . 4.16 Simulation of AUTOCHIP1 Substrate network with latch-up prevention techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Power supply classification . . . . . . . . . . . . . . . . . . . . . . 5.2 The ideal switching states in buck converter . . . . . . . . . . . . 5.3 Inductor current and voltage waveforms for one switching period in steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 A simple illustration of the output power and losses versus the load current in DC-DC buck converter . . . . . . . . . . . . . . . . . . 5.5 A simple illustration of the output power and losses versus the input voltage in DC-DC buck converter . . . . . . . . . . . . . . . 5.6 DC-DC buck converter open loop systematic design procedure. . . xii 5.7 Small signal equivalent circuit Buck converter. . . . . . . . . . . . 5.8 Voltage mode control closed-loop Buck converter block diagram. . 5.9 PID compensator tranfer function gain and phase. . . . . . . . . . 5.10 PWM basic block diagram . . . . . . . . . . . . . . . . . . . . . . 5.11 Block diagram of closed-loop Voltage mode control buck converter 5.12 loop gain magnitude and phase with and without compensation in VCM converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Simulink model for VCM buck converter . . . . . . . . . . . . . . 5.14 Inductor current in VCM with and without soft start technique . 5.15 PID compensation circuit and components values used in VMC buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Basic block diagram of the current programmed mode (CPM) control converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 Steady state and perturbed inductor currents without slope compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 Steady state and perturbed inductor current with compensation ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19 Deduction of the avergae inductor current used to derive the controlto-duty cycle transfer function in CPM control . . . . . . . . . . . 5.20 Block diagram of the current programmed mode (CPM) control converter modeling the duty cycle perturbation in terms of inductor current and input voltage variations . . . . . . . . . . . . . . . 5.21 Current programmed mode control (CPM) closed loop block diagram 5.22 The loopgain of the CPM control without compensation and with proportional compensation only . . . . . . . . . . . . . . . . . . . 5.23 CPM control closed loop transfer functions . . . . . . . . . . . . . 5.24 CPM large signal simulink model . . . . . . . . . . . . . . . . . . 5.25 CPM system level transient load regulation . . . . . . . . . . . . . 5.26 CPM system level transient line regulation . . . . . . . . . . . . . 5.27 Efficiency versus load current with different input voltages . . . . 5.28 Efficiency versus input voltage with different load current . . . . . 5.29 Continuous PI compensator using operational transconductance amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.30 PI compensator block diagram . . . . . . . . . . . . . . . . . . . . 5.31 Integral path proposed representation . . . . . . . . . . . . . . . . 5.32 Single bit Sigma-Delta system level as implemented on simulink . 5.33 Decimation block implementation using fixed point representation (DR = 256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.34 Integrator and PI compensator transfer functions . . . . . . . . . 5.35 Digital integrator and output DAC simulink blocks . . . . . . . . xiii 5.36 Steady-state output voltage at (I load = 0.05A) (a)Proportional amplifier only, (b) Analog PI compensation, (c) proposed analogmixed PI compensation . . . . . . . . . . . . . . . . . . . . . . . . 5.37 Load step response I load = 0.05 A to 0.5 A showing the effect of changing the digital integrator gain . . . . . . . . . . . . . . . . . 6.1 Basic circuit operation of the designed CPM buck converter. . . . 6.2 Essential transient signals in the CPM buck converter. . . . . . . 6.3 High side and low side switches with a sense transistor M sense . . 6.4 Transient currents through the driver resistances during the switching of HS switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Simulations to show the relation between the HS and LS gate voltages and the switching node voltage. . . . . . . . . . . . . . . . . 6.6 HS and LS drivers circuits . . . . . . . . . . . . . . . . . . . . . . 6.7 The pulse level shifter circuit. . . . . . . . . . . . . . . . . . . . . 6.8 High voltage comparator circuit. . . . . . . . . . . . . . . . . . . . 6.9 HV comparator biasing circuit . . . . . . . . . . . . . . . . . . . . 6.10 Clock generation circuits. . . . . . . . . . . . . . . . . . . . . . . . 6.11 Sawtooth voltage generation circuit . . . . . . . . . . . . . . . . . 6.12 Poportional compensator . . . . . . . . . . . . . . . . . . . . . . . 6.13 Voltage-to-current converter and current limiter circuit. . . . . . . 6.14 Asymmetric dead-time generator circuit with input and outputs wave forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 Transient load regulation in circuit simulation. . . . . . . . . . . . 6.16 Transient line regulation in circuit simulation. . . . . . . . . . . . 6.17 Buck converter efficiency versus the load current in the circuit level simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 DC-DC converter chip floorplan . . . . . . . . . . . . . . . . . . . 6.19 DC-DC converter chip die photo . . . . . . . . . . . . . . . . . . .6.20 The measurement setup for the DC-DC converter chip. The power supply display shows the output voltages and the maximum currents can be supplied by each channel. . . . . . . . . . . . . . . . 6.21 Transient measurement for the bandgap rise time. . . . . . . . . . 6.22 Transient measurement for the clock frequency. . . . . . . . . . . 6.23 The measured transient load regulation when load current changes between 0.25 A and 0.5 A. . . . . . . . . . . . . . . . . . . . . . . 6.24 The measured and simulated efficiency values at load current of 0.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 The parasitic components from the switching node to the bandgap output voltage node. M1 and M2 forms the HV PAD equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2 :

 2 Figure 2: Flot de conception proposé pour la conception et la vérification des circuits intégrés de puissance intégrant la prédiction des effets de couplage de substrat avant la fabrication.

Figure 3 :

 3 Figure 3: Proposition d'analyse de défaillance due à un couplage de substrat en utilisant l'outil AUTOMICS

Figure 12 :

 12 Figure 12: Tension de référence du bandgap en fonction du courant injecté, en simulations (ligne droite) et en mesures (cercles). La source du transistor PMOS est connectée à 15 V.

Figure 13 :

 13 Figure13: Tension de référence du bandgap en fonction du courant injecté, en simulations (ligne droite) et en mesures (cercles). On considère seulement la diode de substrat. La source du transistor PMOS est connectée à 15 V.

  Figure 16: AUTOCHIP1 EMMI

Figure 1 . 1 :

 11 Figure 1.1: Injection of electrons in the substrate due to below ground state on the drain of HV-DNMOS

Figure 2 . 2 :

 22 Figure 2.2: H-bridge circuit schematic.

Figure 2 . 3 : 2 .Figure 2 . 4 :

 23224 Figure 2.3: Substrate cross section for transistors MP1 and MN1 at the abovesupply state

Figure 2 . 6 :

 26 Figure 2.6: Substrate coupling in analog-mixed circuits.

Figure 3 . 2 :

 32 Figure 3.2: Total recombination of minority carriers in two conventional PN junctions connected face-to-face

Figure 3 . 3 :

 33 Figure 3.3: Equivalent circuit of differential P-type element of thickness ∆x and cross-sectional area A.

Figure 3 . 5 :

 35 Figure 3.5: Equivalent circuit to emulate the diffusion of minority carriers in a differential element.The parameter α is 1 for electrons (i.e, p-type) and -1 for holes (i.e, n-type)

Figure 3 . 6 :

 36 Figure 3.6: Steady state pi equivalent circuit to emulate the diffusion of minority crriers in a differential semiconductor element of thickness ∆x and cross-sectional area A.

Figure 3 . 8 :

 38 Figure 3.8: Equivalent circuit for enhanced diode model known as EPFL diode [Stefanucci15c]

Figure 3 . 9 :

 39 Figure 3.9: Equivalent circuit for enhanced Homojunction model known as EPFL Homojunction

Figure 3 . 10 :Figure 3 .

 3103 Figure 3.10: Basic cross-section in HV-CMOS technology for isolated DNMOS and DPMOS, the full line components are included in the compact model while the dashed components are extracted by the conventional substrate tools, and the orange lines represent the missing lateral parasitics

Figure 3 .

 3 Figure 3.14: Hierarchical parasitic components in HV-CMOS technology (a) All the possible combinations between different layers (b) The remaining parasitic components based on the reduction rules

Figure 3 .Figure 3 .Figure 3 .Figure 3 .

 3333 Figure 3.16: Basic nonuniform rectilinear example in HV-CMOS technology, the thick blue line represent the contacts of the PSUB and DNWELL

Figure 3 .

 3 Figure 3.20: Technology parameters extraction flow

Figure 4 . 3 :

 43 Figure 4.3: Proposed failure analysis due to substrate coupling using AUTOMICS tool

Figure 4 . 8 :

 48 Figure 4.8: AUTOCHIP1 damage after battery connection

Figure 4 . 9 :Figure 4 .

 494 Figure 4.9: AUTOCHIP1 failure analysis using emission microscope EMMI

Figure 4 .

 4 Figure 4.13: Simulation of AUTOCHIP1 schematic without the substrate network

Figure 4 .

 4 Figure 4.16: Simulation of AUTOCHIP1 Substrate network with latch-up prevention techniques

Figure 5 . 1 :

 51 Figure 5.1: Power supply classification

Figure 5 . 4 :Figure 5 . 5 :

 5455 Figure 5.4: A simple illustration of the output power and losses versus the load current in DC-DC buck converter

ω 2 o

 2 (5.31) equivalent series resistance (ESR) adds a zero to the transfer function of the control-to-output voltage.

Figure 5 . 9 :

 59 Figure 5.9: PID compensator tranfer function gain and phase.

  dB (at Inf kHz) , Pm = 83.8 deg (at 6.16 kHz) dB (at Inf kHz) , Pm = 41 deg (at 40.6 kHz) Compensated loop gain Frequency (kHz) (b) Compensated loopgain

Figure 5 .

 5 Figure 5.22: The loopgain of the CPM control without compensation and with proportional compensation of k p = 10 with a load current I o = 0.1A

Figure 5 .Figure 5 .Figure 5 .

 555 Figure 5.26: System level transient line regulation. The output voltage transient response when input voltage changes from 15 V to 5 V with load current I o = 0.1 A

Figure 5 . 2 .

 52 Figure 5.29: Continuous PI compensator using operational transconductance amplifier

Figure 5 .

 5 Figure 5.30: PI compensator block diagram

Figure 5 .Figure 5 .

 55 Figure 5.33: Decimation block implementation using fixed point representation (DR = 256)

Figure 5 .

 5 Figure 5.36: Steady-state output voltage at (I load = 0.05A) (a)Proportional amplifier only, (b) Analog PI compensation, (c) proposed analog-mixed PI compensation

Figure 5 .

 5 Figure 5.37: Load step response I load = 0.05 A to 0.5 A showing the effect of changing the digital integrator gain

Figure 6 .Figure 6 .

 66 Figure 6.16: Transient line regulation in circuit simulation. The output voltage transient response in case of proportional amplifier and PI compensator when the input voltage changes from 15V to 5V with load current I load = 0.1 A. The output voltage overshoot is less than the specified maximum overshoot (v ov (max) = 0.25 V )

Figure 6 .

 6 Figure 6.24: The measured and simulated efficiency values at load current of 0.25 A. The dashed red line is an estimated tend line for the measured data.

Figure 6 .Figure 6 .

 66 Figure 6.31: Bandgap reference voltage versus the injected current in simulations and measurements. The body diode is considered as a part of the simulation. The straight line is the simulation data and the circles represent the measurement points. The PMOS source is connected to 15 V power supply

Figure 6 .

 6 Figure 6.33: Bandgap reference voltage versus the injected current in simulations and measurements. The substrate diode is only considered. The straight line is the simulation data and the circles represent the measurement points. The PMOS source is connected to 15 V power supply

Figure 6 .

 6 Figure 6.34: Simulation results for injected current components when the PMOS source is connected to 15 V. The components are the substrate current, the collected current by the HS switch n-well, and the remaining current is collected by the bandgap

PFor LIR=0. 2 ,

 2 Lcond (HS) = I 2 HSrms * R ON -HS where the I HSrms is the root mean square current passing through the HSswitch. The rms value can be obtained by the following expression [Erickson01] max + I min .I max + I 2 min )(1)where I max and I min is the maximum and minimum current values in the HS-switch. The I max and I min can be expressed in terms of the average and ripples current as followI max = I o + ∆i L I min = I o -∆i LHence, the rms value of the current in the HS-switch isIHSrms = √ D.I o . the rms current is I HSrms = 1.00166 * D -t d /T .I o and for LIR = 0.5, the rms current becomes I HSrms = 1.01036 * D -t d /T .I o .

P

  Lcond (HS) = I 2 HSrms * R ON -HS = D.I 2 o .R ON -HS = D. R ON -HS R L .P o (3)

1 2 2 DD ( 10 )

 1210 .c gs .V DD and the same amount is lost while turning off. Hence, the switching losses can be obtained byP Lswitching (C cgs ) = f s .C gs .VFor the C gd , during the turn on of the LS-switch the voltage across C gd changes from -V D to V DD , hence, the voltage change across the capacitor is V DD -V D . Similarly, when turning off the voltage change across the capacitor is the same. Also, when the LS switch is OFF, the voltage across C gd is changed from -V D to V in when the HS switch turned ON and from V in to -V D when the HS switch turned off. The total switching loss due to c gd isP Lswitching (C cgd ) = f s .C gd .(V DD -V D ) 2 +f s .C gd .(V in +V D ) 2 = f s .C gd .(V 2 DD +V 2 in ) (11)from the equations 8, 9, 10, and 11, then the total losses in the LS-switch transistor isP LS-switch = (1-D-2t d /T s ). R ON-LS R L .P o +f s .C sw .(V D ) 2 +f s .C gs .V 2 DD +f s .C gd .(V 2 DD +V 2 in ) (12)

  . The inductor current is i L ∼ = I o and the rms current is I Lrms = I o . The power loss in the inductor is P LDCR = DCR.I 2 rms = DCR.I 2 o = DCR.

  .5 DC-DC buck converter open loop circuit schematic. . . . . . . . . 2.6 Substrate coupling in analog-mixed circuits. . . . . . . . . . . . . 2.7 The ideal switching states in buck converter . . . . . . . . . . . .

1.1 Injection of electrons in the substrate due to below ground state on the drain of HV-DNMOS . . . . . . . . . . . . . . . . . . . . . 2.1 Typical architecture of smart power IC chip. . . . . . . . . . . . . 2.2 H-bridge circuit schematic. . . . . . . . . . . . . . . . . . . . . . . 2.3 Substrate cross section for transistors MP1 and MN1 at the abovesupply state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Substrate cross section for transistors MP2 and MN2 at the belowground state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

  . . . . . xiv 6.26 Measured proportional error amplifier output. . . . . . . . . . . . 6.27 Bandgap circuit with start-up circuit. . . . . . . . . . . . . . . . . 6.28 Cross-sectional area for the low and high side switches and the PNP transistor used in the bandgap circuit . . . . . . . . . . . . . 6.29 Bandgap reference voltage versus the PNP base voltages . . . . . 6.30 Simplified layout used in the substrate extraction using the tool AUTOMICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31 Bandgap reference voltage versus the injected current in simulations and measurements in the presence of the body diode when the PMOS source is connected to 15 V. . . . . . . . . . . . . . . . 6.32 Simulation results for injected current components in the presence of the body diode when the PMOS source is connected to 15 V. . 6.33 Bandgap reference voltage versus the injected current in simulations and measurements in the absence of the body diode when the PMOS source is connected to 15 V. . . . . . . . . . . . . . . . 6.34 Simulation results for injected current components in the presence of the substrate diode only when the PMOS source is connected

	List of Abbreviations
	TCAD	Technology Computer Aided Design
	TE		Thermal Equilibrium
	VMC	Voltage Mode Control
	List Of Symbols
	ADC BCD Current density Analog-to-Digital Converter Bipolar-CMOS-DMOS technology A/cm 2 BJT Electron charge c Bipolar Junction Transistor CAD µ p Holes mobility J q cm 2 /(V.s) Computer Aided Design CAN µ n Electrons mobility cm 2 /(V.s) Controller Area Network CCM D p Holes diffusion coefficient cm 2 /s Continuous Conduction Mode CPM D n Electrons diffusion coefficient cm 2 /s Current Programmed Mode DCM E Electric field intensity V /cm Discontinuous Conduction Mode DfR n o Equilibrium electrons concentration cm -3 Design for Reliability DN p o Equilibrium holes concentration cm -3 Deep N-well DP n i intrinsic carriers concentration cm -3 Deep P-well DMOS σ Conductivity ℧.cm -1 Double-diffused MOS transistor DTI ρ Resistivity Ω.cm Deep Trench Isolation EMC K Boltzmann constant eV K 1 Electromagnetic Compatibility EMI T Absolute temperature K Electromagnetic Interference EMMI τ Carriers life time s Emission microscopy ESD W PN junction Depletion region width cm Electrostatic Discharge ESR N a Acceptor doping concentration cm -3 Equivalent Series Resistance HS N d Donor doping concentration cm -3 High Side HV V b Built-in barrier potential V High Voltage L p Holes diffusion length cm HV-CMOS High Voltage CMOS technology IC L n Electrons diffusion length cm Integrated Circuit IoT δn Excess electrons concentration cm -3 Internet of Things LIN δp Excess holes concentration cm -3 Local Interconnect Network LS ǫ Permittivity F/cm Low Side LV Low Voltage g m Mutual transconductance ℧
	PI	Proportional Integral
	PID	Proportional Integral Differential
	PWM	Pulse Width Modulation
	SCR	Silicon-Controlled Rectifier
	SOAC	Safe Operating Area Check
			xix xxi	xx

to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv List of Tables 4.1 power stage specifications . . . . . . . . . . . . . . . . . . . . . . 4.2 AUTOCHIP1 substrate extraction parameters . . . . . . . . . . . 4.3 Average doping of the extracted layers . . . . . . . . . . . . . . . 4.4 Substrate simulation parameters for Transient time = 8 µs . . . . 5.1 Summary of DC-DC buck converter transfer functions . . . . . . . 5.2 DC-DC buck converter specifications . . . . . . . . . . . . . . . . 5.3 DC-DC buck converter circuit components . . . . . . . . . . . . . 5.4 CPM control system parameters . . . . . . . . . . . . . . . . . . . 6.1 HS switch specifications . . . . . . . . . . . . . . . . . . . . . . . 6.2 LS switch specifications . . . . . . . . . . . . . . . . . . . . . . . . xvii List of Abbreviations

  De multiples simulations sont exécutées afin de vérifier la robustesse du circuit aux variations de la technologie et des conditions environnementales. Après avoir vérifié les caractéristiques du circuit, commence l'étape de dessin des masques. Dans cette étape, on utilise de nombreuses techniques pour réduire les interactions parasites entre différentes cellules[START_REF] Hastings | The art of analog layout[END_REF]. D'autres contrôles sont mis en oeuvre pour vérifier la qualité du layout, tels que l'extraction de la netlist et la comparaison au schéma initial, (layout versus schematic, LVS), le respect des règles de dessin (design rule check, DRC), et le respect de règles électriques (electrical rule check, ERC).

	System level design	Specifications
	Circuit level design	Circuit simulations
			Redesign
	Layout design	Layout Verification and Post-layout Simulation
	Tape-out
			Failure analysis
	Testing and Measurements	Evaluation and Validation	Substrate parasitic extraction using
			AUTOMICS
	Design Validated

Le flot de conception commence par un ensemble de spécifications, comme indiqué sur la figure

1

. Ces spécifications sont utilisées par les ingénieurs pour créer un modèle de simulation au niveau du système et évaluer la possibilité d'atteindre ces spécifications. Les spécifications peuvent être modifiées lors de la conception du fait de l'évolution de la technologie et / ou de contraintes de temps et de coût.

xxiv Dans l'étape suivante, chaque sous-système est réalisé au niveau du transistor. Failure

Figure 1: Flot de vérification proposé pour les circuits intégrés HT intégrant la phase d'analyse des défaillances par AUTOMICS.

  ). On considère seulement la diode de substrat. La source du transistor PMOS est connectée à 15 V.

		charge moyen. T d (total) est d'environ 340ns et le courant de charge maximal est
		de 0, 6A, par conséquent, la valeur moyenne maximale du courant I av (deadtime)
		est de 67mA. En fonctionnement normal, la source du commutateur LS est reliée
		à la masse. Par conséquent, en s'appuyant sur les résultats du scénario de test 1,
		nous pouvons affirmer que la tension de référence ne sera pas affectée par le
		courant injecté durant le temps mort.
		0.4 Etude de cas industriel : Autochip 1
		Le circuit AUTOCHIP1 est développé en technologie 0,35 µm HV-CMOS du
		fondeur ams. Il a été développé pour une application Valeo fonctionnant sous
		24V . Cette technologie est en mesure de supporter les surtensions jusqu'à 90V .
		La fonction principale de ce circuit est de contrôler les tensions entre 28V et 32V
		des alternateurs à courant maximal de 5A. Ce circuit intègre aussi différentes in-
		terfaces E / S, un bloc de gestion de l'alimentation et une petite partie numérique
		qui gère une communication série avec un noyau numérique externe, mis en oeuvre
		sur un FPGA [Fanucci10].
		Le rôle de l'alternateur est de recharger la batterie pendant la rotation du
		moteur. Il comporte deux parties : le rotor et le stator. Le courant dans le rotor
		induit un flux magnétique. Sa rotation produit un champ magnétique variable
		dans la bobine du stator. Par conséquent, le stator génère un courant qui est
		utilisé pour charger la batterie. La commande du courant du stator est réalisée
		en commandant le courant du rotor.
		Le courant moyen pendant la période de temps mort peut être exprimé comme
	:	I av (deadtime) =	T d (total) T switching	× I av (load)	(1)
		où T switching est la période de commutation et I av (load) est le courant de
		xxxvii

  .2.

			Base
	Emitter	P	N	N	P	Collector
	Minority			Total recombination at the
	carriers			contacts injected holes cannot be collected by the
	concentration		collector
	n pE		p nB		n pC
		Emitter-base	Base-collector
		depletion	depletion
		region		region

Table 4 . 2

 42

	: AUTOCHIP1 substrate extraction parameters
	Parameter	Value	Parameter	Value
	Active substrate depth	25 µm	Number of sub-layers	5
	Layer 1 depth	1.55 µm Layer 4 depth	15 µm
	Layer 2 depth	3.5 µm Layer 5 depth	25 µm
	Layer 3 depth	6.5 µm Total # of shapes processed 1900
	Extraction elapsed time (s)	232.6	Extraction CPU time (s)	199.45

Table 5 .

 5 1: Summary of DC-DC buck converter transfer functions

Table 5 .

 5

	2: DC-DC buck converter specifications
	Maximum input voltage (V imax )	15 V
	Output voltage (V o )	2.5 V
	Maximum load current	0.6 A
	Maximum output voltage ripples (V rpp /V o )	2 %
	Reference voltage (V ref )	1.2 V
	Inductor current ripples (LIR)	15 %
	Switching frequency (f s )	330 kHz
	Inductor winding resistance (DCR)	50 mΩ
	High-side switch resistance (R HS )	500 mΩ
	Low-side switch resistance (R LS )	500 mΩ
	Maximum overshoot (V ov )	250 mV
	Maximum settling time	250 µs

Table 5 .

 5

	3: DC-DC buck converter circuit components
	Circuit component	Calculated value Practical value
	Inductor value (L)	79.4 µH	100 µH
	Capacitor value (C)	35.4 µF	33 µF
	Max. equivalent series resistance (ESR)	0.546 Ω	0.035 Ω
	Load resistance (R load )	4.167 Ω	4.167
	Specifications
	LC cut-off frequency (f o )	2.839 kHz	2.775 kHz
	Estimated efficiency (η)	86 %	86.7 %

  R ON -HS R L .P o + f s .C sw .R L 2.M 2 vDC .P o + f s .C gs .V 2 DD + f s .C gd .V 2Using the small ripples approximation, the current through the low-side switch is expressed asi LS = 0 , 0 ≤ t < DT s + t d I o , DT s + t d ≤ t ≤ T s

	in	(7)
	Low-side switch losses
	1. Conduction losses:

  From the equations 7, 12, 16, 17, and 19, the overall power loss is given byP Loss = P HS-switch + P LS-switch + P L Diode + P LDCR + P LESR = D. R ON -HS R L .P o + f s .C sw .R L 2.M 2 vDC .P o + f s .C gs (HS).V 2 DD + f s .C gd (HS).V 2 in + (1 -D -2t d /T s ). R ON -LS R L .P o + f s .C sw .(V D ) 2 + f s .C gs (LS).V 2 DD + f s .C gd (LS).(V 2 DD + V 2The efficiency of the converter is the ratio between the input and output power and can be written as

		IN ) +	2t d T s	.	R D R L	.P o +	2t d T s	.	V D V o	.P o + DCR.	P o R L
	+ ESR.	R L .(1 -D) 2 12.f 2 s .L 2 .P o									(20)
		η =	P o P i	=	P o P o + P loss
		=	1 1 + P loss /P o				(21)
							o .(1 -D) 2 12.f 2 s .L 2 = ESR.	R L .(1 -D) 2 12.f 2 s .L 2 .P o	(19)

Acknowledgements

System level design Specifications

Layout design The control current to output voltage transfer function can be expressed as

To gain an insight into the main advantage of the CPM controller, we could assume that the simple converter function is to equate the control current (i c ) to the sensed inductor current (i L /A iL ) and since

→ 0 then F m tends to infinity in order to have a finite value for duty cycle. Thus, the control to output voltage transfer function becomes

This implies that the simple approximation of the control to output voltage transfer function comprises a single pole at 1/CR L . Consequently, the compensation circuit can be simplified in the feedback loop.

Closed loop system for CPM control

The closed loop CPM control system is shown in Figure 5.21. The control current is provided by an outer voltage loop in which the output voltage is scaled down by a voltage divider (H divider ) then compared to a reference voltage. The compensation circuit could be a proportional amplifier with a gain (k p ) to achieve the required loopgain crossover frequency or a proportional integral PI amplifier to achieve the required loopgain and eliminate the static error at the output. The compensated voltage is converted into the control current (i c ).

The output voltage can be expressed as follows

where the H vo-to-vref is the reference to output voltage transfer function, H vo-to-vin is the input voltage to output voltage transfer function, and H vo-to-iload is the load current to output voltage transfer function.

In the reference to output voltage transfer function, the loopgain can be expressed as follows:

A proportional compensation circuit was designed to maintain a crossover frequency of 40 kHz. The CPM system level was developed according to the design specifications stated in Tables 5.2 and 5.3.

Chapter 6 DC-DC buck converter circuit and measurements

In this chapter, we present the CPM control DC-DC buck converter circuit operation. Then, we illustrate the circuit representation of each block. The circuit and system simulations are compared. The floorplan of the chip is done and verified with AUTOMICS tool. This verification guarantees that the substrate coupling is not disturbing the bandgap operation. Finally, measurements are shown to verify the proper operation of the proposed flow.

DC-DC buck converter circuit operation

In this section, we explain the system operation on the circuit level deriving the basic circuit design equations. Figure 6.1 shows our chip basic building blocks on the circuit level. The inductor, capacitor, and load resistance are off-chip components. The chip has three input power supplies:

1. The high voltage supply (HV Vin), 2. the low bias voltage of the HS switch driver (PVSS),

the low voltage supply (VDD).

Since the gate-source of the HS switch can not sustain voltages higher than 5V, the HS buffer swing is limited to HV Vin and PVSS where P V SS = HV V in -5V .

Switches gate drivers

The HS-and LS-switches need gate buffers capable of driving large capacitive loads. The HS-switch buffer controls the rising and falling slew rate of the switching node voltage.

On the one hand, very fast transition at the buffer output results in a very large shoot-through current passing through the parasitic capacitor (c gd ) of the HS-and LS-switch resulting in high power dissipation. Also, in the presence of PAD parasitic inductance, during such fast transitions it can resonate with the MOSFET parasitic capacitance resulting in a very high frequency ringing at the switching node voltage which can take long time to decay. This high frequency ringing may produce electromagnetic interference (EMI) disturbing the operation of other circuits.

On the other hand, slow transition rate influences the efficiency as the switch spends longer time while its resistance is high and a very high current is passing through it and hence conduction loss increases [START_REF] Bhargava | DC-DC buck converter emi reduction using pcb layout modification. Electromagnetic Compatibility[END_REF]. Therefore, the buffer should be designed to reduce these losses.

In the following analysis, the inductor is simplified as constant current source as in [START_REF] Balogh | Design and application guide for high speed MOSFET gate drive circuits[END_REF]. Figure 6.4(a) shows the switching on of the HS-switch. Initially, the body diode is ON and the inductor current I L passes through the diode. The switching node voltage is -V D and the voltage across C GDP is V in + V D and across C SGP is zero. To turn the HS-switch on, the buffer pulls-down the HSswitch gate voltage to PVSS through the buffer pull-down resistance (R HS,LO ). The capacitance C SGP is charged till the voltage V SG reaches threshold voltage V T without changing V SD or I D . As V SG increases, the current through the transistor increases, reducing the current through the diode till the whole current passes through the transistor and the diode is turned off. The V SG at this point is called V SG,M iller or conventionally known as Miller plateau. At this voltage, a constant current passes through the transistor while |V SD | is greater than |V SG |-|V T |, hence the transistor operates in saturation region where

The capacitor C GDP is charged with a constant rate expressed as: Figure 6.22 shows the measured clock signal. The clock is provided by Dflip flop which has two outputs (Q and Q bar). The non-inverted output (Q) is connected in the internal system while the inverted output (Q bar) is connected to the external PAD for measurement. This explains the inversion in the wave form.

High voltage measurements

In this set of measurements, the PVSS source is connected and the system starts to operate. The transient load regulation when the load current changes between 0.25 A and 0.5 A is depicted in Figure 6.23.

Chapter 7

Summary and Future Work

Thesis summary

We have investigated a novel technique for substrate modeling. This technique depends on modeling the minority carriers propagation in the substrate using enhanced models for the diodes and resistors. These substrate enhanced models are capable of maintaining the minority carriers concentration and gradient using an additional terminal. A CAD tool referred to as AUTOMICS was developed in LIP6-UPMC to extract the substrate parasitic components. Then, it constructs an equivalent substrate network using the enhanced models.

In this work, we propose a modification in the smart power ICs design flow. This modification can be classified into two main points:

1. Failure analysis:

The failures due to the substrate can be identified by the several techniques like, EMMI microscopy. However, the failure analysis engineer has to reproduce the failure in simulations. This step is tedious and takes long time. Therefore, we proposed, using a substrate parasitic extraction tool (AU-TOMICS), an automated parasitic extraction procedure. This step would shorten the time of the failure analysis step. An industrial test case (AU-TOCHIP1) developed by ams and verified by Valeo has been used as test case for the proposed procedure. We manage to reproduce the failure in the simulations in shorter time compared to the conventional way.

Verification step:

Before the design tape-out, the parasitic components are extracted to verify that they are not affecting the system operation. However, these parasitic components are the parasitic resistance and capacitance components which

Appendix A. DC-DC buck converter Power losses

In this appendix, we derive the equations used in modeling the power losses in the buck converter. These equations were used in the system level simulations.

The losses in the dc-dc buck converter is classified basically into two types:

1. Conduction losses: These losses are due to the non-idealities of the MOS switches and finite resistance of the inductor winding. To minimize the conduction losses, the on resistance of the MOSFET switches should be minimized resulting in large size transistors.

Switching losses:

These losses result from charging and discharging of the parasitic capacitance attached with the MOSFET transistors. At the switching node, This parasitic capacitance mainly comes from the drain-to-bulk capacitance of the high side and low-side switches and any routing capacitance due to layout at this node. At the gate of the MOSFET switches, The losses is due to the charging and discharging of the parasitic capacitance at the gate.

In order to prevent the short circuit between the high-side and low-side switches, a dead time (t d ) is inserted at which the two transistors are off. During this deadtime, the inductor current passes through the body diode of the NMOS pulling the switching node below ground.