Abiel Aguilar-González

Madain Perez-Patricio

Miguel Arias-Estrada

Jorge-Luis Camas-Anzueto

Héctor-Ricardo Hernández-De León

Avisaí Sánchez-Alegría

Madaín Pérez-Patricio

An FPGA Correlation-Edge Distance approach for disparity map

Keywords: FPGA, Verilog, Disparity map

come   L'archive ouverte pluridisciplinaire

I. INTRODUCTION

Perception of depth values of points contained in a scene is one important task of computer vision systems. Recently depth perception has been used in diverse applications such as navigation systems for mobile robots, object recognition and 3D reconstruction [START_REF] Parrilla | Fuzzy control for obstacle detection in stereo video sequences[END_REF]- [START_REF] Delmerico | Building facade detection, segmentation, and parameter estimation for mobile robot stereo vision[END_REF]. Extracting information about the depth from images using a stereo configuration is the most used technique. In this technique the correspondence between images and the geometric configuration of the same allows to obtain depth images called disparity maps [START_REF] Faugeras | Three Dimensional Computer Vision: A Geometric Viewpoint[END_REF].

To define a disparity map it is necessary to measure the similarity of content points in the stereo image. Techniques to determine these similarities are divided into two categories: area-based algorithms [START_REF] Stefano | A fast area-based stereo matching algorithm[END_REF]- [START_REF] Jin | A fast and high quality stereo matching algorithm on fpga[END_REF], and feature-based algorithms [START_REF] Feiyangcheng | Stereo matching by usingthe global edge constraint[END_REF]- [START_REF] Jung | Stereo reconstruction using high-order likelihoods[END_REF]. In area-based algorithms the gray level of pixels round the interest pixel are used as similarity measure to produce dense disparity maps, i.e., the disparity is calculated for all the points in the scene. On the other hand, feature-based algorithms are based on specific points of interest. These points are selected in concordance with appropriate feature detectors. Feature-based algorithms are more stable against changes in lighting environment and contrast, because they represent the geometric properties of a scene. The main characteristic of using feature-based algorithms is that they do not generate dense disparity maps. Therefore, these algorithms must be applied in conjunction with other techniques and require an additional step for characteristics extraction, which increases the computational costs and runtime.

Due to benefits regarding to the management of large amounts of data at high speed of FPGAs devices, there is currently a wide variety of algorithms for estimating disparity maps implemented in FPGAs in the reported literature. In [START_REF] Faugeras | Real time correlation-based stereo: algorithm, implementations and applications[END_REF], an array of four FPGAs is used to estimate the Cross Correlation for 256×256 pixel resolution images at a rate of 7 frames per second. In [START_REF] Kanade | A stereo machine for videorate dense depth mapping and its new applications[END_REF], a hybrid system that uses digital signal processors with programmable logic devices PLD is presented. The authors of this paper generated disparity maps for 256×256 pixel resolution images at a rate of 30 frames per second. In [START_REF] Darabiha | Reconfigurable hardware implementation of a phase-correlation stereo algorithm[END_REF], is proposed a four Xilinx Virtex 2000E structure, on which is possible to obtain real-time dense disparity-maps for 256×360 pixel resolution images at a rate of 40 frames per second. In [START_REF] Diaz | Fpga based realtime opticalflow system[END_REF] the use of a single FPGA is proposed. The developed system processes images at 30 frames per second using 640×480 pixel resolution images. An adaptive window technique in conjunction with SAD is used in [START_REF] Roh | Symmetrical dense disparity estimation: algorithms and fpgas implementation[END_REF]. The presented method processes images up to 1024×1024 pixel resolution at a rate of 47 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 32 pixels. The architecture presented in [START_REF] Masrani | A real-time large disparity range stereosystem using fpgas[END_REF] uses four FPGAs to make a real time correction, in on the same paper a leftright consistency check is done to improve the quality of the disparity map produced. This method processes images up to 640×480 pixel resolution at a rate of 30 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 128 pixels. In [START_REF] Georgoulas | Fpga based disparity map computation with vergence control[END_REF] a module for calculating the real-time disparity map is proposed. The module was implemented in a single FPGA of Altera Stratix IV family. The autors of this paper processed images up to 640×480 pixel resolution at a rate of 320 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 80 pixels.

In this paper an FPGA module to calculate real-time dense disparity maps is presented. The novelty is the architecture design and FPGA implementation for the proposed method. The disparity maps are calculated at a rate of 75 frames/s for 1280×1024 pixel resolution images and generate 8-bit dense disparity maps within a range of disparities up to 63 pixels. The developed module allows simple and systematically scalability to different range of disparities, therefore the resulting hardware could be applied to a wide range of real-time stereovision applications such as high-speed tracking, tracking paths, high-speed objects recognition and mobile robot navigation.

II. THE PROPOSED METHOD

An overview of the proposed method can be seen in Fig. 1. This method consists in two steps. First, disparity maps for the input images and edge-distance images are computed, simultaneously an homogeneity parameter ψ is calculated for each point in the scene. Followed, based on the disparity maps previously generated and using the ψ parameter, a final disparity map is generated. A. Sum of absolute differences (SAD)

The Sum of Absolute Differences (SAD) is a correlationbased method mostly used due to its high computational efficiency. The general behavior can be described as following, given (x, y) coordinates of a pixel in left image and maximum value of expected disparity d max , an correlation index Crl(x, y, s) is calculated for each displacement S of the correlation window in right image. To calculate the correlation the following equation is used:

Crl(x, y, s) = u=w,v=w u=-w,v=-w |I l (x + u, y + v) -Ir(x + u + s, y + v)| (1)
as 2w+1 is the window size centered on the pixel with position (x, y). I l , I r are the gray values of the pixels in the left and right images respectively and S ranges from 0 to d max . The disparity d(x, y) is defined as S displacement that minimizes the correlation index:

d(x, y) = arg min s Crl(x, y, s) (2)
The main problem with this method is to select the correlation window size. High window size values allow to determine the true correlation values in areas with uniform texture, however this window size values imply a high computational demand and erroneous values at certain points due to the blurring edges and small features eliminated (see Fig. 3). On the other hand, small window size values imply low computational demand but the correlation coefficient measurement is very sensitive to noise and erroneous values at uniform texture regions are generated as seen in Fig. 4. Fig. 2 shows the true disparity map of a Tsukuba scene.

B. Edge distance

The euclidean distance between each pixel with I l (x, y), I r (x, y) coordinates, and the nearest left edge is calculated as following:

k(x, y) = |I δ (x, y) -I δ (x -1, y)| (3) distance(x, y) = l = 0, k(x, y) < β l = l + 1, k(x, y) > β ( 4
)
as β is the threshold value that defines an edge and δ is l or r for left or right images, respectively. Fig. 5 shows the nearest left edge distance for each point of the left image of Tsukuba scene. The darker values represent low value distances while light values represent high value distances. Fig. 6 shows the disparity map obtained using images of edge distance as input images for SAD. In this figure a significant improvement in regions with uniform texture is perceived, on the other hand, an increase of errors in regions with uneven texture is generated.

C. Homogeneity parameter

A ψ parameter corresponding to the homogeneity degree for each point of the left image of stereo pair is determined as following:

h(x, y) = u=w,v=w u=-w,v=-w l (x + u, y + v)| (5) ψ(x, y) = 0, h(x, y)/(w + 1) 2 < λ 1, h(x, y)/(w + 1) 2 > λ ( 6
)
as λ is threshold value that determines the homogeneity of a point with respect to its corresponding correlation window and 2w + 1 is the window size centered on the pixel with position (x, y). Fig. 7 shows ψ values for all points contained in the Tsukuba scene considering λ = 1.

D. Composition

Using the ψ parameter it is possible to determine a final disparity map by assigning the values obtained from the edge disparity map (Fig. 6) for points with uniform texture and the values obtained from the disparity map (Fig. 4) for points with uneven texture as following:

disparity(x, y) = distance(x, y), ψ(x, y) == 0, σ == 1 d(x, y), ψ(x, y) == 1 (7)
as σ is determined as following: σ : 0 < disparity(x, y) > d max .

Fig. 8 shown the disparity maps generated by the proposed method for the Tsukuba scene where w, β and λ parameters were configured with values equal to {1, 32, 1} respectively. In this figure a high improvement in regions of uniform texture and a low improvement in the points near the edges is obtained. The proposed method requires less computational load in contrast to various methods in the reported literature [START_REF] Jin | A fast and high quality stereo matching algorithm on fpga[END_REF]- [START_REF] Feiyangcheng | Stereo matching by usingthe global edge constraint[END_REF], [START_REF] Masrani | A real-time large disparity range stereosystem using fpgas[END_REF]- [START_REF] Georgoulas | Fpga based disparity map computation with vergence control[END_REF], however compute a disparity map for a stereo pair of 384×288 pixel resolution (Tsukuba scene resolution) implies a runtime close to 1 second. These runtime values are not acceptable for real-time applications. This was the main motivation to search efficient ways to implement the developed method, opted for an FPGA implementation. In Section III the detailed implementation in hardware is presented while in section IV the experimental results generated by this implementation are shown.

III. FPGA IMPLEMENTATION

The main advantages of using FPGA devices are: easiness to re-designed architectures based on specifications without incurring in non-recurring engineering and parallel processing ability, allowing real-time processing. Due to these advantages the proposed method was implement in a single Cyclone II EP2C35F672C6 FPGA assembled in an Altera DE2 breadboard. A 50 MHz clock frequency was used. In order to get input stereo pairs, TRDB DC2 plate connected in 1st expansion port of DE2 plate is used and provides stereo pairs to 1280×1024 pixel resolution in RGB scale. On the other hand, to determine the grayscale value of input stereo pairs the green channel value are used as grayscale value. The developed architecture is described in detail in the following sub-sections. A general diagram of the designed architecture can be seen in Fig. 9. In TABLE I a full description of the physical ports used by proposed architecture is shown.

A. Sum of absolute differences (SAD)

To calculate the disparity map by SAD it is necessary to have stored fragments of images to be processed. In order to manage the FPGA memory two vectors with capacity to store three rows of left image and three rows of right image respectively were used. The behavior of these vectors is similar to a shift register unit, however, due simplicity of these vectors hardware resources demand is reduced. In general terms, during time zero the pixel value (1, 1) is stored in index vector 0, a clock cycle later this value is crossed to index 1 and the pixel (1, 2) is stored in index 0. A similar process is repeated for all pixels making up the image.

To calculate the SAD, a 3×3 correlation window and maximum value of expected disparity d max = 63 is used. An architecture of pixel-parallel window-parallel was designed. The inputs are obtained from the vectors previously configured, using appropriate indexes is possible to process the image at video rate. SAD calculation starts after storing the first three rows of each image. This results in a (x -w)*(y -w) disparity map resolution, as x, y is the resolution values of input image and 2w +1 is the correlation window size. Fig. 10 shows the architecture for correlation calculation to a disparity value equal to zero. To calculate the correlation values for the remaining disparities similar architectures implemented in parallel were used.

To determine the appropriate disparity value, the min module is used (Fig. 11). First, this module uses the previously calculated correlation values and using an array of multiplexers activated by comparators as Sel : I1 > I2 determines the correlation value which minimizes the correlation window displacement. After, a CASE structure is used to assigned the corresponding correlation index Crl index , to determining the disparity value an equalizer is applied to Crl index as follows:

disparity = Crl index * (255/d max ) (8)

B. Edge distance

Fig. 12 shows the architecture for nearest left edge distance calculation. First, the storage vector module stores pixels with (x -1, y) and (x, y) coordinates for the left image and right images, then, applying equations 3 and 4 nearest left edge distance is calculated in edge distance module.

C. Homogeneity parameter

Fig. 13 shows the architecture for calculating the ψ parameter. The vector storage module stores three lines of the left image of the estero pair. Then, using the stored lines and applying equations 5 and 6, the homogenity computation module determines the correlation homogeneity window centered in the pixel of interest and assigns the corresponding ψ value.

D. Composition

The composition module operates on the principle of a conventional multiplexer assigning for each point (x, y) the value of one of its two inputs determined by the Sel parameter see (Fig. 14). Finally, generated disparity maps are shown on a 4.3" LCD screen of terasIC with 800×480 pixels resolution connected to the 2nd expansion port of the DE2 board.

IV. EXPERIMENTAL RESULTS

The architecture presented in Section III was implemented using a top-down approach. All modules were coded in Verilog and were simulated using ModelSim-Altera 6.6c to verify its functionality. Quartus II Web Edition SP1 version 10.1 was used for the synthesis and download in a Cyclone II EP2C35F672C6 FPGA assembled in Altera DE2 breadboard. Resource consumption of the developed architecture is shown in TABLE II. In order to evaluate the proposed method performance, the developed architecture was tested using different values for β and λ parameters. Tests were performed using the Tsukuba scene as test images. Whereas hardware implementation operates using binary strings and color depth equal to 8 bits, values with base 2 were tested. Fig. 15 shows the behavior of the error obtained in the final disparity map for β = {1, 8, 16, 32, 64, 128, 255} and λ = 1. Fig. 16 shows the behavior of the error obtained in the final disparity map for λ = {1, 8, 16, 32, 64, 128, 255} and β = 1. To determine the number of erroneous pixels, the generated disparity maps were evaluated using the Middlebury estereo vision system web site [21] Fig. 15: β parameter behavior.

In TABLE III, quantitative results for the proposed method with a 3x3 correlation window compared with other methods in the literature [START_REF] Brown | Advances in Computational Stereo[END_REF] are presented, occ is the error for points of occlusion in the input images, disc is the error for points with discontinuities and all is the error for total points in the scene. The shown values were obtained from the Middlebury estereo vision system evalaution [21] improvement is due to the left-edge distance that like featurebased methods represents the geometries of the input scene.

Due to mathematical simplicity of the proposed method, in the developed architecture a high processing speed is presented. Comparing the processing speed of the developed architecture with other FPGA implementations reported in the literature (TABLE IV) up to 32,768,000 pixels/s increase is observed.

Due to strategies such implementation of storage vectors and small correlation windows, the developed architecture has a low hardware resources demand (TABLE V). When comparing the consumption of logic elements and memory bits with other methods reported in the literature up to 76,694 and 60,259 reduction was observed.

V. CONCLUSIONS

In this paper a module for real-time disparity maps computation has been presented. The developed architecture shows a better performance in regions of uniform texture regarding to other methods mentioned in the literature. The principal advantage with the developed module it's a high processing speed and a low consumption of hardware resources, it allows to implement the proposed method in FPGA devices with relatively few resources which facilitates its application in realtime stereo vision applications.

Besides, one of the main characteristic of the developed architecture is its flexibility to be reconfigured or modified to work with different windows sizes and different maximum values of expected disparity.

Fig. 1 :

 1 Fig. 1: Block diagram of the proposed method.

Fig. 2 :

 2 Fig. 2: Tsukuba scene, true disparity map.

Fig. 3 :

 3 Fig. 3: Tsukuba scene, disparity map SAD w = 15.

Fig. 4 :

 4 Fig. 4: Tsukuba scene, disparity map SAD w = 1.

Fig. 5 :

 5 Fig. 5: Left image of Tsukuba scene, distance to nearest left edge.

Fig. 6 :

 6 Fig. 6: Tsukuba edge distance scene, edge disparity map SAD w = 1.

Fig. 7 :

 7 Fig. 7: Tsukuba scene, ψ parameter.

Fig. 8 :

 8 Fig. 8: Tsukuba scene, disparity map using the proposed method w = 1.

Fig. 9 :

 9 Fig. 9: General diagram of the developed architecture.

Fig. 10 :

 10 Fig. 10: Correlation computation module architecture, disparity=0.

Fig. 11 :Fig. 12 :

 1112 Fig. 11: min module architecture.

Fig. 13 :

 13 Fig. 13: ψ computation module architecture.

Fig. 14 :

 14 Fig. 14: Composition module architecture.

Fig. 16 :

 16 Fig. 16: λ parameter behavior.

  with following Image Settings: Tsukuba (384×288 resolution, d max = 15), Venus (434×383 resolution, d max = 19), Teddy (450×375 resolution, d max = 59) Cones (450×375 resolution, d max = 59) and performing re-designs in developed architecture to operate with d max values equal to {15, 31, 63, 63} respectively. For all test images w, β and λ parameters were configured values equal to {1, 32, 1} respectively, in Fig.

17

 17

  disparity maps generated by the proposed method for the same test scenes is shown. In

  Fig. 17: Disparity maps generated by the proposed method for different test images.

  Fig. 17: Disparity maps generated by the proposed method for different test images.

TABLE I :

 I PORTS DESCRIPTION OF THE DEVELOPED ARCHITECTURE

	Name	Type	Description
	Clk	Input	Pixel clock
	Left image	Input	Logical vector [7 : 0]
	Right image	Input	Logical vector [7 : 0]
	Disparity map	Output	Logical vector [7 : 0]

TABLE II :

 II DEVELOPED ARCHITECTURE SPECIFICATIONS

	Resource	Demand
	Logic elements (LEs)	16,240
	Memory bits (ALUTs)	33,080

  TABLE IV the speed of the developed architecture compared with other FPGAs implementations reported in the literature are presented. In TABLE V hardware resources demand compared with other FPGAs implementations reported in the literature are shown.

TABLE III :

 III QUANTITATIVE RESULTS OF THE PROPOSED METHOD COMPARED TO OTHER METHODS IN THE LITERATURE

	Method	Scene	occ	disc	all
		Tsukuba	21.8%	23.6%	36.9%
	Sum of Absolute	Venus	26.2%	26.8%	42.1%
	Differences (SAD)	Teddy	52.6%	54.0%	68.5%
		Cones	62.5%	63.3%	76.9%
		Tsukuba	21.3%	23.2%	36.5%
	Sum of Squared	Venus	25.0%	25.6%	41.8%
	Differences (SSD)	Teddy	56.2%	53.2%	67.8%
		Cones	60.9%	61.8%	75.8%
		Tsukuba	29.9%	31.1%	42.5%
	Normalized	Venus	30.6%	31.1%	44.1%
	Cross-Correlation (NCC)	Teddy	55.8%	57.5%	69.2%
		Cones	56.2%	58.2%	71.5%
		Tsukuba	34.9%	336.3%	46.5%
	Census	Venus Teddy	44.4% 69.7%	44.8% 70.2%	53.0% 69.2%
		Cones	77.5%	77.6%	84.7%
		Tsukuba	8.85%	34.0%	10.9%
	Proposed method	Venus Teddy	6.99% 30.2%	35.9% 47.8%	6.93% 34.1%
		Cones	43.4%	55.9%	46.5%

By analyzing TABLE III a significant improvement over other methods reported in the literature is observed. This

TABLE IV :

 IV PROCESSING SPEED COMPARED WITH OTHER FPGAs IMPLEMENTATIONS.

	Method	Resolution	Frames/s	Pixels/s
	[16]	1024X1024	102	106,954,752
	[18]	1280×1024	65	85,196,800
	[19]	640×480	230	70,656,000
	[20]	1280×1024	50	65,536,000
	Proposed*	1280×1024	75	98,304,000
	*Operating frequency = 50 MHz
	TABLE V: HARDWARE RESOURCE DEMAND COMPARED WITH OTHER
		FPGAs IMPLEMENTATIONS.
	Method	Logic elements (LEs)	Memory bits (ALUTs)
	[16]	86,252		62,669
	[18]	89,459		84,307
	[19]	53,616		60,598
	[20]	31,863		47,331
	Proposed	12,765		24,048


Abiel Aguilar-González

Miguel Arias-Estrada

Madaín Pérez-Patricio

J L Camas-Anzueto

An FPGA 2D-convolution unit based on the CAPH language

ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Introduction

Digital image processing involves procedures that are normally expressed in the form of algorithms. With the exception of image acquisition and representation, most functions of image processing can be implemented in software. The reason for using specialized hardware in image processing is due to need for higher speed processing in several applications such as, low-light microscopy, object recognition, computer vision, robotics and so on [START_REF] Rasnik | Electronic cameras for low, light microscopy[END_REF]2,13,[START_REF] Hofmann | Breaking the diffraction barrier in fluorescence microscopy at low light intensities by using reversibly photoswitchable proteins[END_REF]12,[START_REF] Zhou | Accelerating embedded image processing for real time: a case study[END_REF][START_REF] Acharya | A temporal superresolution method applied to low-light cardiac fluorescence microscopy[END_REF][START_REF] Barina | Adaptive real-time image processing exploiting two dimensional reconfigurable architecture[END_REF].

The bus architecture on most computers, except in a few high performance computers with embedded specialized image processing technology (for example CUDA technology or another GPU technology), do not allows to use the data-rate required for real-time applications. Due to high speed requirements most the current realtime image processing systems consist of a combination of computers, peripherals and specialized image processing hardware, such as FPGA devices or GPGPU devices. In most cases, the overall operation is controlled by software running on the host computer or embedded processor when the FPGA or GPGPU has one. [START_REF] Romero-Troncoso | Electrnica Digital y Lógica Programable[END_REF][START_REF] Romero-Troncoso | Sistemas digitales con VHDL[END_REF].

1.1 Spatial-domain convolution filters 2D-convolution is an important concept in several areas of math and engineering including computer vision, digital image processing for medical applications, statistics applications, object recognition and so on [START_REF] Asgher | Robust hybrid normalized convolution and forward error correction in image reconstruction[END_REF][START_REF] Fiack | Real-time embedded systems powered by fpga dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications[END_REF]8,[START_REF] Jiang | Novel multi-scale retinex with color restoration on graphics processing unit[END_REF]15,[START_REF] Reichenbach | Improved cubic convolution for two dimensional image reconstruction[END_REF][START_REF] Savarimuthu | Real-time medical video processing, enabled by hardware accelerated correlations[END_REF][START_REF] Shi | Image interpolation by twodimensional parametric cubic convolution[END_REF][START_REF] Mabrouk | A computationally efficient technique for real-time detection of particular-slope edges[END_REF]11,12,[START_REF] Zhou | Accelerating embedded image processing for real time: a case study[END_REF][START_REF] Acharya | A temporal superresolution method applied to low-light cardiac fluorescence microscopy[END_REF][START_REF] Barina | Adaptive real-time image processing exploiting two dimensional reconfigurable architecture[END_REF]. Convolution operates on two signals in 1D filtering operation or two images in 2D filtering operation. In case of 2D-convolution, one image is defined as the input signal or input image and the other, called kernel, is defined as a filter on the input image, producing an output image.

Due to 2D-convolution is the type of convolution used for digital image processing, we will concentrate on the discrete 2D-convolution. 2D-convolution between an image I and a convolution mask M of order n is defined as shown in the equation 1, where w = (n -1)/2 [START_REF] Romero-Troncoso | Electrnica Digital y Lógica Programable[END_REF][START_REF] Romero-Troncoso | Sistemas digitales con VHDL[END_REF]. By applying the equation 1, the convolution operation calculates the intensity value of an image pixel. The resulting pixel is computed considering the pixels from the vicinity and based on the weights of the elements of a spatial filter or kernel whose dimensions are equal to the vicinity of the image to be processed. Each of the elements of the kernel is multiplied with the corresponding value of the vicinity of the original image. Then, the sum of products correspond to the value of the pixel in the new image. Each of the pixels of the vicinity contributes, with its own value and a percentage to calculate the new pixel, Fig. 1 [START_REF] Romero-Troncoso | Electrnica Digital y Lógica Programable[END_REF][START_REF] Romero-Troncoso | Sistemas digitales con VHDL[END_REF]. Fig. 1: Convolution process for a 3×3 convolution kernel.

The CAPH language

CAPH [START_REF] Serot | Caph : A high-level actor-based language for programming fpgas[END_REF][START_REF] Serot | Caph: A domain specic language for implementing stream-processing applications on recongurable hard[END_REF][START_REF] Serot | Caph, un langage dé dié á la synthése; applications flot de données sur circuits fpga[END_REF]28] is a domain specific language suited to the description and implementation of streamprocessing applications on FPGAs. CAPH relies upon the actor/dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels. The behavior of each actor is defined as a set of transition rules using pattern matching. The CAPH suite of tools currently comprises a reference interpreter and a compiler producing both Systemic and synthesizable VHDL code. These tools allow to reduce the design time and enable high level programing compared with the conventional VHDL design.

Related works

In aeronautical and automotive applications, image processing systems with high speed processing are required.

In order to reduce cost, it is necessary to perform several pre-processing algorithms like 2D convolution in dedicated hardware such as FPGA devices. Therefore, several FPGA implementations for 2D-convolution have been reported in the literature. In [START_REF] Sangwine | Colour image edge detector based on quaternion convolution[END_REF] it is presented an FPGA edge filter based on an image convolution in which color images are convolved with a pair kernels with quaternion coefficients. When the developed filter is applied to a color image, the filter converts areas of smoothlyvarying color to shades of grey and generates colors in regions where edges occur in the image. An FPGA filter based on convolution with hypercomplex masks was introduced by authors of [START_REF] Sangwine | Colour image filters based on hypercomplex convolution[END_REF]. It was presented three color edge filters inspired by the Prewitt, Sobel and Kirsch filters. The presented filters produce an almost grayscale image with color edges when the original image present a sharp change of color.

Autors of [5] present a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the current requirements of image processing applications. The developed FPGA architecture allows adapting the processing elements as well as the communication infrastructure. The authors performed the convolution operation for a 384×286 pixel resolution images with a 1.69 ms runtime and a 5×5 convolution kernel. Finally, in [START_REF] Colodro-Conde | A practical evaluation of the performance of the impulse codeveloper hls tool for implementing large-kernel 2-d filters[END_REF] it is described the design of 2D convolution filters with large kernels, up to 50×50 coefficients, using the Impulse CoDeveloper TM high-level synthesis (HLS) tool. The authors provide a practical guide for designers willing to make the most of an HLS tool like Impulse CoDeveloper, and compare the results, in terms of area utilization, minimum clock period and power consumption, with implementations developed using lower-level design tools. The results show that RTL based implementations can achieve higher performance than CoDeveloper-based ones. However, CoDeveloper can meet the high performance requirements of the most demanding real-time applications, but with less effort and shorter design cycles.

Motivation

In practice, the convolution operation eq. 1 consists of a sum of products. However, when the algorithms are implemented in dedicated hardware such as FPGA devices, a high hardware resource consumption is required. In addition, due to elements of the convolution kernel ∈ R the computation of products with fixed point numbers is required, which increases the consumption of the hardware resources.

Even if the IEEE's optimized fixed point libraries are used, the product operation maintains a high hardware resource demand. Hence, it is possible to affirm that the problem resides in the product operation. The high hardware resource demand was our main motivation to search ways in which the product-operation is substituted by other operation which allows simple HDL implementation and enables to process the majority of the kernels using in industrial applications that involves convolution operations.

The rest of this paper is organized as follows: the section 2 presents the proposed algorithm for the real-time convolution operation. In the section 3, it is detailed the design via the CAPH language for the proposed algorithm's FPGA architecture. In addition, a review and analysis about the CAPH language are shown. Experimental results for different filters, a comparison regarding to different multiplication algorithms reported in the literature and a validation via MatLab is reported in the section 4. Finally, the section 5 concludes this article.

The proposed mhetod

Main objective is to demonstrate three contributions by investigating an FPGA architecture for a 2D-convolution filter described with the CAPH language. First, it is proposed a shift-based arithmetic which allows high flexibility regarding to the convolution operation and enables both reduction of the hardware resources consumption (up to 98%) and high speed processing, appropriate for real-time image processing systems. The filtered images are calculated at a rate of 103 frames per second for images up to 1200×720 pixel resolution. The novelty lies in the design of the FPGA architecture for the proposed method. By the use of strategies such as, the use of shiftsbased operators, and kernels coefficients defined as ± ν1 ν2 ; it is possible to manage large number of different convolution kernels and maintain low hardware resources consumption. Furthermore, to maintain high flexibility regarding to the input video, the developed hardware allows to configure the resolution of the input images with values of 3 × Y up to 1200 × Y ∀ Y ∈ N, allows to configure the kernel order with α values ∀ α ∈ N and allows scalability for different sizes of convolution kernel and input image resolution using a simple and systematic form. Finally, the proposed method performance enables the resulting hardware can be implemented to a wide range of real-time image processing applications.

Second, we study the advantages and disadvantages regarding to the CAPH language and its flexibility with respect to synthesizable VHDL source codes. Third, we provide a practical guide for developers willing to design and implement real-time image processing systems via the CAPH language.

The shift-based arithmetic

Considering a convolution kernel M of (n * 2) + 1 × (n * 2) + 1 ∀ n ∈ N, defined by coefficients in the form m i,j = ± ν1 ν2 ∀ ν ∈ 2 k for k ∈ N, max(k) = bits per pixel(bpp); all convolution kernel can be expressed as three matrices, A, B and C, as shown in equation 2.

m i,j = i=n,j=n i=1,j=1 2 k 2 k = A, B, C (2)
In the equation 3 one kernel and its ± ν1 ν2 representation is shown, while, in the equation 4 the corresponding A, B and C matrices for the selected kernel are shown. A is the sum of the k values of the numerator and denominator for the m i,j elements. B is the sign of the m i,j elements defined by equation 5 and C is defined as shown in equation 6.

 

-1 1 4 -1 1 4 8 1 4 -1 1 4 -1   =    -2 0 2 0 2 0 2 2 -2 0 2 0 2 0 2 2 2 3 2 0 2 0 2 2 -2 0 2 0 2 0 2 2 -2 0 2 0    (3)
original mask

± ν1 ν2 representation    -2 0 2 0 2 0 2 2 -2 0 2 0 2 0 2 2 2 3 2 0 2 0 2 2 -2 0 2 0 2 0 2 2 -2 0 2 0    =   0 2 0 2 3 2 0 2 0   ,   1 0 1 0 0 0 1 0 1   ,   0 1 0 1 0 1 0 1 0   (4) ± ν1 ν2 mask A B C b(i, j) = 1, m i,j < 0 0, m i,j ≥ 0 (5) c(i, j) = 1, m i,j < 1 0, m i,j ≥ 1 (6)
On the other hand, if G is an image with λ bits per pixel(bpp), his pixel values can be expressed by λ bit size registers and it is possible to define the H and T operators as shown in the equations 7 and 8. Where sll α and srl α corresponds to a left or right shift over a register and the magnitude of the shift is determined by α and complement represents the two's complement, applied over a λ bit size register.

H r,t,C i,j,A {G} = sll (ai,j ) (g r,t ), if c i,j = 0 srl (ai,j ) (g r,t ), if c i,j = 1 (7) T r,t i,j,B {g r,t } = (g r,t ), if b i,j = 0 complement(g r,t ), if b i,j = 1 (8)
By applying the H and T operators, the convolution operation between a G image and a M convolution kernel can be expressed by the C operator as shown in equation 9. Where g i,j represents the gray scale value of the (i, j) pixel of the G image, expressed by one λ bit register. n represents the order of the convolution kernel. b x,y are the elements of the B matrix for the M kernel. A, B and C are the A, B and C matrices for the M kernel, respectively. & applies a concatenation between registers, and x, y are defined by the equations 10 and 11. Finally, the convolution output image Q for a G input image with horizontal resolution equal to r 1 , vertical resolution equal to r 2 and a M convolution kernel of type ± ν1 ν2 can be computed as shown in the equation 12.

C{G} = u=n,v=n u=-n,v=-n b x,y & T u,v x,y,B {H u,v,C x,y,A {g i+u,j+v }} (9) x = n -1 2 + 1 + u (10) y = n -1 2 + 1 + v (11) q(i, j) = i=r1,j=r2 i=1,j=1 C{G} (12)

Performance and limitations

Before to applying the proposed method it is necessary to define some restrictions and limitations. First, the proposed method only is applicable if all the coefficients of the kernel can be expressed in the form ± ν1 ν2 . i.e., a kernel that includes the 0.173 coefficient cannot be expressed in the form ± ν1 ν2 , while a kernel with coefficients such as, 0.25, 0.50 or 0.125 are permissible. The use of kernel's coefficients defined by powers of two limits the scope of the proposed method. However, several applications such as gauss filtering, edge filtering, sharpened operation, pyramidal reduction and so on can be successfully applied by using the proposed method. On the other hand, some applications such as Gabor filtering or another directional filter cannot take advantages by applying the proposed method. Second, all the coefficients of the kernel have to be simplified, i.e., an coefficient equal to 2 4 must be treated as 1 2 , 4 12 as 1 3 , 2 16 as 1 8 and so on. Finally, a consideration for the zero value must be addressed. In all cases the zero value for any coefficient from the kernel will be defined as 2 0 2 bpp , where (bpp) is the bits per pixel in the input image.

On the other hand, the most important difference and advantage of the proposed method is to avoid the calculation of products and floating point operations, allowing to use large number of different convolution kernels with positive or negative coefficients for integers and fractional numbers. As a result, the proposed method can maintain a high flexibility regarding to the possible different input convolution kernels, near to 1 × 10 19 for kernels of order 3. In addition, the proposed method enables parallel implementation, suitable for FPGA devices.

FPGA architecture

An overview of the developed FPGA architecture are shown in Fig. 2. This architecture consist into three inputs. The values corresponding to the horizontal resolution of the video sequence, size of the convolution kernel and the coefficients of the kernel are sent via logical vectors to the FPGA architecture, settings input. The clk pixel input is defined as the pixel rate of the input image while the input pixel [7:0] input is defined as grayscale values of pixels from the input image. On the other hand, the filtered pixels are placed in a logical vector of 8 bits size, output pixel [7:0] output. The main difference between conventional HDL design and the CAPH design is the form by define behavior of the modules. In any HDL language such as VHDL or Verilog languages, behavior of the modules is defined via digital approach. Digital approach forces the user knowledge about digital electronics issues such as clock signals, control signals, state machines, RTL description and so on. In addition, in some cases time diagrams and propagation analysis must be applied. Requirements for electronic issues coupled with low level programing presented in the HDL design limits the scope. In most cases electronic, mechatronic or another similar specialists perform the HDL design process. In the Fig. 3 the general diagram for the developed FPGA architecture is shown. The developed CAPH design consist into two stages. In the first stage, the circular buffer stage, stores the necessary data to computing the convolution operation for the input settings. The resol [15:0] input is defined as the horizontal pixel resolution for the input frame while the pixel [7:0] input contain the grayscale value for one pixel from the input frame and the clk input defines the pixel rate. On the other hand, in the second stage, the reconfigurable convolution stage, the pixels and coefficients for the convolution kernel, pix• • • [7:0] and a(i,j)[3:0], b(i,j) and c(i,j), respectively are used to compute the convolution operation via the proposed method. Finally, the convolution result is placed in the output pixel 81×[16:0] output. In the following subsections the details about the developed design are presented.

The circular buffer stage

All 2D-convolution operation involves passing a 2D kernel over an image, and carrying out a calculation at each position of the kernel. In this way image memory must be accessed several times in order to complete a computation. For processing purposes, the conventional approach is to store the entire input image into a frame buffer, access the neighborhoods pixels and apply the convolution operation needed to produce the output image. If realtime processing is required, considering an n×n kernel, n×n pixel values are needed to perform the computations each time the kernel is moved and each pixel in the image is read up to n×n times. The memory bandwidth constraints make impossible to obtain all pixels stored in the memory in only one clock cycle, unless any kind of local caching is performed.

Conventional approaches are characterized by their abundant memory directly connected to each processing element. However, we proposed the use of a circular buffer schema, [START_REF] Saldaa | Compact fpga-based systolic array architecture suitable for vision systems[END_REF][START_REF] Saldaa | Customizable fpga-based architecture for video applications in real time[END_REF]. By using pointers of memory address it is possible to keep track of the elements being processed. Input data from the previous n rows can be stored using the memory buffers till the moment when the kernel is scanned along subsequent rows. To reuse hardware resources when new image data is processed, a shift mechanism between buffer rows is used. Data inside the buffer can be accessed in parallel and each input pixel is fed only once to the FPGA device. Buffer elements synchronize the supply of input pixel values to the processing elements. Furthermore, image buffers allow performing several window operators in parallel and enable the possibility to carry out computations with local data. Instead of sliding the kernel across the image, this implementation feeds the image through the kernel as shown in Fig. 4. In order to implement the circular buffer scheme in the CAPH language, the use of the ram driver and data actors is proposed, Fig. 3. Although the circular buffer schema allows to store n horizontal lines and the maximum kernel size could be set as n, design a reconfigurable FPGA architecture with a large maximum kernel size implies extensive source codes. Furthermore, the majority of the industrial applications use kernels sizes with values between 3×3 to 13×13. Hence, for practical purposes, in the developed FPGA architecture the maximum kernel size is set as 9×9, enabling to process kernels up to 9×9.

Considering the maximum kernel size as 9×9, the ram driver actor manages an array of 10 BRAM cores assigning to each one the corresponding address and the write-read value. The BRAM cores consists of a synchronous single-port block-ram unit. This cores were designed via MegaWizard Plug-In Manager -Quartus II. The design settings were assigned as: type = synchronous, width = 8, depth = 1200, operation type = single port and all others parameters were defined as default. These parameters allow to store the gray scale values for each pixel contained in a horizontal line from input images up to 1200 horizontal resolution with 8 bits per pixel (bpp). The use of an BRAM core array enables to read the grayscale values of the pixels contained in n horizontal lines from an image, see Table 1. The ram driver actor consist in one input, (resol) input, corresponding to the horizontal resolution of the input image and two outputs, re wr and direc. The re wr output consist on a logic vector with 10 bits of size, the write-read value of each of the BRAMs are determined by each one of the bits of the logic vector. The direc output consist on a logic vector with 11 bits of size that corresponds to the read/write address for all the BRAM cores. The maximum horizontal resolution for the input image is set as 1200 pixels. Hence, the maximum possible value for the direc output is 1199.

In the Fig. 5 the source code for the ram driver actor is presented. As can be seen, the CAPH programing possesses design sequence like structured programing. The CPAH design sequence could be divided into five stages. In the input/output declaration stage, the input/output definitions for a particular actor must be addressed. In the CAPH environment it is possible to define multiple actors in same source file. Hence, the input/output declaration stage and the second, and third stages must be performed for each actor defined in the file. The second stage addresses the variable declaration used into an actor. Then, in third stage the transition rules for an actor must be defined. After, in the fourth stage the input/output for the general CAPH design must be specified. Finally, in the fifth stage, the instantiation process between actors defined in the source code could be performing. The ram driver actor consists into two transition rules. The first, increments the initial value of the read/ write address for all the BRAM cores, and manages the re wr and direc outputs, Fig. 3. The second rule, assigns initial values for the variables used in the ram ram driver actor. Due to each BRAM core only provides the pixel value of one pixel of the horizontal line stored inside them, in order to access the others horizontal values necessary for the convolution operation, it is proposed the use of the data actor, Fig. 3. The data actor consists into one transition rule. Applying this, the values of one pixel for the nine lines are read in parallel at any time instant and placed in the outputs 1-9 of the data actor, then this values are placed in the outputs 10-18 and the new read data are placed in the outputs 1-9. This process are repeated until storage the 81 pixels for the 9×9 selected kernel size is completed.

The reconfigurable convolution stage

The reconfigurable convolution stage, Fig. 3, is comprised of three different actors. First, n × n shift actors performs the corresponding shifts regarding to each of pixels in the kernel, equation 7. The values of the A and C matrices serve as inputs of the shift actors, a(i,j)[3:0] and b(i,j), respectively. In order to perform the right shift over large grayscale values for the input pixels, all input pixel values are placed in registers of 16 bits of depth. shift actor consists into two rules, this rules represent the two possible solutions of the equation 7, sll or srl. Then, n × n two's complement actors perform the corresponding complements regarding to each pixels in the kernel, equation 8. The values of the B matrix and the outputs of the shift actors serve as inputs of the two's complement actors. The two's complement actor consists into two transition rules, the rules represent the two possible solutions of the equation 8. Considering the size of the input pixels as 16 bits, the equation 8 can be simplified as shown in equation 13. After, all values generated by the two's complement actors are concatenated with the coefficients of the B matrix. Finally, the adder actor performed the sum of all input pixels via one signed-sum unit defined in one transaction rule.

T r,t i,j,B {g r,t } = (g r,t ), if b i,j = 0 complement(g r,t ), if b i,j = 1 = (g r,t ), if b i,j = 0 65536 -(g r,t ), if b i,j = 1 (13)

Instantiation

CAPH environment performance regarding to instantiation is limited. In general, it is possible to instantiate between actors contained in the same source file. However, this process is complex in comparison with the design of the actors and considering the CAPH 2.3 version (released in July 2014) , the version used in this research, it is possible indicate that CAPH not allow instantiation for actors defined in different source files. In addition, when the source code of the actors is considerable, define multiple actors in the same source file is not practical.

Due to limitations regarding to instantiation process, it is proposed the use of a VHDL instantiation file. All actors were compiled via the CAPH compiler and it was obtained the following files: complement act.vhd, data act.vhd, ram driver act.vhd, shift act.vhd and adder act.vhd. Furthermore, MegaWizard Plug-In provides the bram.vhd file. All files have been instantiated in a VHDL file designed in Quartus II Web Edition 10.1SP1.

In order to assign lines in the outputs of the data actor in ascending form, i.e. line1 [7:0] = input image line number l, line2 [7:0] = input image line number l+1, • • •, line9 [7:0] = input image line number l+8, the outputs from the BRAM cores in read mode are assigned to the outputs of the data actor as seen in Table 2, the first column corresponds to the output w/r [n+1:0] of the ram driver actor, the second column corresponds to the numbers of the BRAM cores assigned to the outputs of the data actor while in Fig. 3, the instantiations between the BRAM cores and the data actor is shown. 4 Results and discussion

CAPH's performance and limitations

CAPH language possesses several advantages regarding to the conventional HDL design. First, the CAPH language takes advantages regarding to the conventional HDL languages due to the possibility to avoid digital approach which involves time requirements and control signals definitions. In addition CAPH allows a high level programing and enables to export to synthesizable VHDL code the source code. In addition, CAPH allows to use most of the synthesizable VHDL operators such as shifts, arithmetic operations and so on. Other advantage for to the CAPH language is the optimized operators for arithmetic operations. Several arithmetic operators such as +,-,*,/ and sqrt, produced VHDL optimized codes. It is useful when complex arithmetic operations such as products, quotients and radicals need to be implemented in FPGA devices.

CAPH performance regarding to instantiation is limited. In general, it is possible to instantiate between actors contained in the same source file. However, this process is complex in comparison with the design of the actors and considering the CAPH 2.3 version (released in July 2014), it is possible indicate that CAPH not allow instantiation for actors defined in different source files. In addition when the source code of the actors is considerable, define multiple actors in the same source file is not practical. Furthermore, although the majority of the CAPH instructions are exportable to VHDL, other limitation are operations between floating points and disability to low level programing operations such as, concatenation between registers and operations between bits of a register.

General performance of the developed FPGA architecture

The main characteristics and differences between the developed FPGA architecture and all the FPGA convolution architectures reported in the literature are two. First, the possibility to process different resolution regarding to input video stream without have to re-synthesize the developed hardware. Second, the possibility to applying different sizes or coefficients for the convolution kernel without have to re-synthesize the developed hardware. In the Fig. 6 the coefficients-distribution of the used convolution kernel is shown. As can be seen the central pixel corresponds to the 41 index. All the possible kernels must be centered in the central pixel, e.g., a 3×3 kernel must contain the pixels with the indexes equal to 31-33, 40-42 and 49-51, while a 5×5 kernel must contain the pixels with the indexes equal to 21-25, 30-34, 39-43, 48-52, and 57-61. In addition, to validate the functionality for each of the four tests presented in the Fig. 7, a convolution script that operates considering the equation 1 was designed in MatLab. The output images for the same convolution kernels are stored in a .jpj file. Then, the percentage of the number of erroneous pixels (φ) and the RMS error (σ) were computed by the equations 14 and 15; where I 1 is the output image generated for the conventional convolution method. I 2 is the output image generated for the proposed convolution method. x is the horizontal resolution of the input image. y is the vertical resolution of the input image. N is set as x * y and ∆ ψ is set as 0.01. In the Fig. 8 the results of this validation are shown. By analyzing the Fig. 8 it is possible to affirm the correct functionality of the FPGA architecture. The first test, Fig. 7 (a)-(c), involves anything operation due to the selected kernel is the identity kernel. In this case both errors σ and ψ must be zero as shown in Fig. 8, therefore it is possible to affirm the correct functionality of the developed FPGA architecture. On the other hand, due to decimal representation of the tests performed in Mat-Lab in contrast to the integer representation used in the ModelSim-Altera simulations, small error values for the second-fourth tests (Fig. 7 (d)-(l)) is expected. However, due the σ and ψ values obtained for these tests, close to zero, it is possible to ensure the correct functionality of all actors and cores in the FPGA architecture.

φ = 1 N * 100 i=x,j=y i=1,j=1 |I 1 (i, j) -I 2 (i, j)| > ∆ ψ (14) σ = 2 1 N i=x,j=y i=1,j=1 (I 1 (i, j) -I 2 (i, j)) 2 (15)
-1 0 -1 4 -1 0 -1 0 (f) convolution kernel (g) original image 200×200 (h) filtered image   -1 2 1 4 -1 2 1 4 2 1 4 -1 2 1 4 -1 2   (i) convolution kernel (j) original image 512×512 (k) filtered image           0 0 0 1 128 0 0 0 0 0 1
In order to evaluate the performance of the developed FPGA architecture, several comparisons between different approaches for the conventional convolution method are presented. For this purpose the developed FPGA architecture (Fig. 3) was modified as shown in Fig. 10. The modification consist in replace any shift actor and two's complement actor by one multiplication actor. The multiplication actor performs the multiplication operation between the pixels and coefficients in the convolution kernel, pix• • •[7:0] and k (x,y), respectively. Due to conventional multiplication stage and the proposed reconfigurable convolution stage do not require memory bits consumption, only comparisons between logic elements requirements were conducted, Fig. 9. IEEE approach consists into multiplication modules designed using the specialized fixed point libraries developed by IEEE. Sequential multiplication modules presented by Stevenson [31] are implemented in Sequential approach. Booth approach uses the multiplication module presented by Takagi et al [START_REF] Takagi | High-speed vlsi multiplication algorithm with a redundant binary addition tree[END_REF]. In CSA Wallace-Tree approach, the schema proposed by S.Wallace [START_REF] Swallace | A suggestion for fast multipliers[END_REF] is implemented. Finally, in Recursive approach, it is used the architecture proposed by Singh-Parihar and Reddy [START_REF] Singh-Parihar | Efficient Floating Point 32bit single Precision Multipliers Design using VHDL[END_REF] which consist in an optimized low level multiplication unit. 9 it is possible to affirm that even if the most efficient multiplication algorithms are used, the multiplication operation maintains a high hardware resources consumption. However Due to the proposed method consists into a shift-based arithmetic any FPGA device can take advantages by applying shift operations. Shift operations are low level operations which involves only one digital element in contrast with multiplication operations which involves several digital elements such as adders and logical elements (and or and so on), which increase the hardware resources consumption. As can be seen, if the proposed method is applied the hardware resources requirements can be reduced up to 98%. Reduction regarding to the hardware resources requirements is very useful in autonomous applications such as robotic applications, where the use of small FPGA devices that implies relatively few hardware resources is needed. On the other hand, any real-time application will take advantages if the hardware resources usage decreases.

Due to, in most of the image processing systems such as, low-light microscopy, object recognition, computer vision, and so on [START_REF] Asgher | Robust hybrid normalized convolution and forward error correction in image reconstruction[END_REF][START_REF] Fiack | Real-time embedded systems powered by fpga dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications[END_REF]8,[START_REF] Jiang | Novel multi-scale retinex with color restoration on graphics processing unit[END_REF]15]; a high speed processing is required, other parameter considered to evaluate performance is speed processing. In Table 4, processing speed comparisons between the same approaches presented in the Fig. 9 and the proposed method are presented. On the other hand, in Table 3 processing speed comparisons for the developed architecture regarding to different input image resolution are shown. As can be observed, the proposed reconfigurable convolution stage allows to maintain processing speed close or equal to the processing speed of all the compared multiplication methods. Furthermore, the developed FPGA architecture enables high speed processing for different resolutions of input video streams, Table 3. Hence, it is possible to affirm that the developed architecture is appropriate for realtime image processing applications. Finally, in Table 5 the full hardware resource consumption for the developed FPGA convolution unit is shown.

Implementation results

Post-synthesis implementation

The developed architecture was implemented in an FPGA Cyclone IIEP2C35F672C6 embedded in an Altera development board DE2. The maximum clock frequency was defined as 50 MHz. In order to validate the implementa- In this article a new method for the 2D-convolution operation in real-time has been presented. In this method, floating point operations are translated into low level operations between registers. Low level operations allow to reduce the hardware resources consumption, near to 98% compared to the conventional convolution implementations. In addition, the developed FPGA architecture was designed via the CAPH compiler. Due to high level programing and avoid to use electronic digital approach that involves time diagrams and propagation analysis, CAPH enables to reduce design time near to 75% compared to the plain VHDL design. The developed FPGA convolution unit allows to maintaining high flexibility regarding to the possible different input convolution kernels, near to 1 × 10 19 for kernels of order 3, 7 × 10 179 for kernels of order 9 and high speed processing. High speed processing and high flexibility regarding to the convolution kernel enable the developed convolution unit to be implemented to a wide range of real-time image processing applications. To validate functionality, post-synthesis simulations of the developed FPGA architecture has been performed. Furthermore, the architecture was implemented in an FPGA Cyclone II EP2C35F672C6 embedded in a development board DE2 of Altera. In all cases high accuracy level have been observed.

One purpose of this research was to explore the potential of the CAPH language for complex image processing tasks, in concordance, the FPGA architecture for the proposed method was performed in the CAPH environment which offers great advantages regarding to synthesizable VHDL design. Only one important limitation was detected in this research, flexibility for instantiation process. However, a VHDL instantiation file designed in the Altera VHDL tools or another VHDL design tool, easy solves this inconvenience.

Finally, an important characteristic of the presented architecture is scalability. All the actors, sub-actors and cores that integrate the FPGA architecture easily allow adaptation to work with convolution kernel of size major than the 9×9 kernel, and horizontal video resolution larger than the 1200 resolution which were the values used in the developed FPGA architecture. Consequently, it is possible to configure a wide variety of filters with appropriate values to the characteristics of the input video sequence and the user requirements.

C

  (x, y) = u=w,v=w u=-w,v=-w I(x+u, y+v)•M(x+u+w+1, y+v+w+1)(1)

Fig. 2 :

 2 Fig. 2: Black box diagram for the proposed FPGA convolution unit

Fig. 3 :

 3 Fig. 3: FPGA architecture for the developed convolution unit

Fig. 4 :

 4 Fig. 4: Structure for the circular buffer

Table 1 :

 1 Behavior of the used BRAM array w/r [9:0] Read lines by BRAM1,2,...,10 0000000001 -,-,-,-,-,-,-,-,-,-0000000010 -,-,-,-,-,-,-,-,,-,7,6,5,4,3,2,1 0100000000 -,-,8,7,6,5,4,3,2,1 1000000000 -,9,8,7,6,5,4,3,2,1 0000000001 10,9,8,7,6,5,4,3,2,-0000000010 10,9,8,7,6,5,4,3,-,11

Fig. 5 :

 5 Fig. 5: Source code for the ram driver actor

Fig. 6 : 4 . 3

 643 Fig. 6: Distribution of the coefficients for the convolution kernel

Fig. 7 :

 7 Fig. 7: Performance of the developed FPGA convolution unit

Fig. 9 :

 9 Fig. 9: Comparison of logic elements consumption

Fig. 10 :

 10 Fig. 10: FPGA architecture for the conventional convolution method

Fig. 11 .

 11 The frame generator module have stored in this one frame of 200×200 pixels resolution and provides grayscale values from the stored frame, pixel[7:0]. The settings module provides the horizontal resolution value for the input frame, settings [15:0] and the coefficients for the convolution kernel, kernel 81x[5:0]. The architecture that includes the frame generator and the settings modules was im-plemented in the IIEP2C35F672C6 FPGA device and was simulated via post-synthesis simulation performed in ModelSim-Altera 6.6c. The output image is stored in a text file. Then, the ψ and σ errors (equations 14 and 15) are computed in MatLab, considering the output image for the FPGA implementation and the output image for the same settings performed in MatLab. The obtained error values for the ψ and σ variables were 0 and 0, respectively. This values confirms the correct functionality of the implementation. In Fig.12the specifications for the FPGA implementation are shown.

Fig. 11 :

 11 Fig. 11: FPGA architecture for the post-synthesis implementation

Fig. 12 :

 12 Fig. 12: Specifications for the post-synthesis implementation

Fig. 13 :

 13 Fig. 13: FPGA architecture for the Real-time implementation

Table 2 :

 2 Input assignment for the data actor

	w/r [n+1:0]	Assignment lineK [7:0] for K=1,2, • • • , 9
	0000000001	2,3,4,5,6,7,8,9,10
	0000000010	3,4,5,6,7,8,9,10,1
	0000000100	4,5,6,7,8,9,10,1,2
	0000001000	5,6,7,8,9,10,1,2,3
	0000010000	6,7,8,9,10,1,2,3,4
	0000100000	7,8,9,10,1,2,3,4,5
	0001000000	8,9,10,1,2,3,4,5,6
	0010000000	9,10,1,2,3,4,5,6,7
	0100000000	10,1,2,3,4,5,6,7,8
	1000000000	1,2,3,4,5,6,7,8,9

Table 3 :

 3 Processing speed for different resolutions of input images

	Method	Resolution	Frames/s	Pixels/s
	IEEE	1200×720	103	135,005,160
	S.Wallace [32]	1200×720	103	135,005,160
	Singh-Parihar and Reddy [30]	1200×720	104	136,614,880
	Stevenson [31]	1200×720	104	136,614,880
	Takagi et al [33]	1200×720	104	136,614,880
	proposed*	1200×720	103	135,005,160
	proposed*	512×512	526	137,887,744
	proposed*	200×200	3500	140,000,000
	*Operating frequency = 100 MHz

Table 4 :

 4 Processing speed for different convolution methods

	Method	Required time	Clock specification
	IEEE	10.0 ns	100 MHz
	S.Wallace [32]	10.0 ns	100 MHz
	Singh-Parihar and Reddy [30]	9.61 ns	100 MHz
	Stevenson [31]	9.54 ns	100 MHz
	Takagi et al [33]	9.54 ns	100 MHz
	proposed	10.0 ns	100 MHz

Table 5 :

 5 Hardware resource consumption for the developed FPGA convolution unit

	Resource	Demand
	Total logic elements	8,573
	Total combinational functions	8,573
	Dedicated logic registers	3,351
	Total pins	523
	Total Memory Bits	163,840
	Embedded multiplier elements	0
	Total PLLs	0
	tion, the frame generator and the settings modules
	were designed,

Author Biographies

Abiel Aguilar-González received the B.Eng. degree of Mechatronics in June 2012, Universidad Politécnica de Chiapas, Tuxtla Gutiérrez, México. In June 2015 he received the M.Sc. degree of mechatronics engineering with highest honors, Instituto Tecnológico de Tuxtla Gutiérrez, Tuxtla Gutiérrez, México. He is currently pursuing his Ph.D. degree in Computer Science at the reconfigurable computing laboratory of the Instituto Nacional de Astrofísica Óptica y Electrónica, Cholula, México. His research interests are mainly real-time image processing, real-time FPGA-based system design, machine learning and fuzzy logic applications.