Stefan Holzer
email: stefan.holzer@ieee.org

Martin Wagner

Alireza Sheikholeslami

Markus Karner

Gerhard Span

Tibor Grasser

Siegfried Selberherr

An Extendable Multi-Purpose Simulation and Optimization Framework for Thermal Problems in TCAD Applications

HAL is

INTRODUCTION

State-of-the-art semiconductor process technology nodes require materials working near their limits to meet the proposed performance from the itrs (International Technology Roadmap for Semiconductor) [START_REF]International Technology Roadmap for Semiconductors -2005 Edition[END_REF]. In addition to the commonly known properties of the involved materials, parasitic effects have to be considered as well, since even small fluctuations of process parameters cause variations of device geometries. During operation, grain effects or reliability failures may occur, which change the device characteristics dramatically. Therefore, new models and methods have to be developed in order to describe the observed behavior with sufficient accuracy in tcad (technology computer-aided design) software. Today's semiconductor devices and interconnect structures have already reached a level of complexity, where the behavior of the included materials cannot be rigorously described by simple and basic equations because of limited knowledge of material parameters and material interactions. Different fundamental approaches have been proposed, e.g. ab-initio simulations, but their applicability to structures of industrial interest is still limited. Therefore, parameterized models are required as a sufficient description of the observed device characteristics within reasonable time for computation.

In the following we introduce our simulation and optimization framework, where we present its different operation modes: calibration, parameter extraction, and optimization. Furthermore, we demonstrate these optimization techniques for efficiency maximization of a thermoelectrical generator and model calibration of a thermochemical reaction for material deposition.

SIESTA

Highly sophisticated simulation and optimization environment frameworks [START_REF]TCAD Sentaurus Y-2006.06 User Manual[END_REF][START_REF] Heitzinger | An Extensible TCAD Optimization Framework Combining Gradient Based and Genetic Optimizers[END_REF] support a wide range of simulators, optimizers, and optimization strategies. Contrary to commercially available software [START_REF]TCAD Sentaurus Y-2006.06 User Manual[END_REF]4], our framework Siesta (Simulation Environment for Semiconductor Technology Analysis) [START_REF]SIESTA -The Simulation Environment for Semiconductor Technology Analysis[END_REF] provides an open architecture for numerous types of simulators and optimizers to be individually chosen for a particular problem. In order to achieve fast and accurate optimization results, this simulation environment offers modular and flexible interfaces by which external tools can be easily integrated [START_REF]SIESTA -The Simulation Environment for Semiconductor Technology Analysis[END_REF] and even combined with each other. other possible termination criterion is that the optimizer has found a local optimum which cannot be further improved with a gradient based optimizer [START_REF] Plasun | Optimization of VLSI Semiconductor Devices[END_REF]. For genetic or evolutionary approaches [START_REF] Heitzinger | An Extensible TCAD Optimization Framework Combining Gradient Based and Genetic Optimizers[END_REF], the loop also terminates, if the maximum number of evaluated genomes has been reached.

During start-up, Siesta generates an initial parameter set based on the user's initial guess within user-defined constraints for each simulation branch. After applying post processing tools, the simulation result is parsed in order to extract a representative quantity for comparing it with reference data. A score value is determined which indicates the quality how well these two data sets match. The optimizers use the computed score value to generate the parameter set to improve the score value that will be evaluated after each simulation run based on the currently generated parameter set. A typical example for reference data are measurements where also additional requirements can be specified to meet specific physical constraints under certain conditions.

Optimization Methods

Siesta supports different optimization modes which can be categorized into gradient-based [START_REF] Spellucci | Donlp2 Users Guide, NetLib Project[END_REF][START_REF] Marquardt | An Algorithm for the Estimation of Nonlinear Parameters[END_REF] techniques, genetic approaches [START_REF] Holland | Adaption in Natural and Artificial Systems[END_REF][START_REF] Wall | GAlib A C++ Library of Genetic Algorithm Components[END_REF], and heuristic approaches [START_REF] Ingber | Genetic Algorithms and Very Fast Simulated Re-Annealing: A Comparision[END_REF]. All these techniques have their own benefits and drawbacks and the user can decide which one to use for a particular problem. To provide the appropriate capabilities for problems related to thermal coupled systems, e.g. a calibration for a chemical vapor deposition (cvd) process model or an optimization to improve the efficiency of an electro-thermal generator, a simulated annealing optimization strategy has been chosen to provide a good combination of a fast local parameter search and the global search character due to its heuristic parts in the optimization algorithm [START_REF] Ingber | Genetic Algorithms and Very Fast Simulated Re-Annealing: A Comparision[END_REF].

All in Siesta available optimization techniques fit well for highly nonlinear optimization problems. For the examples shown in Section 3, some of the input parameters depend implicitly on other input parameters, and, e.g., therefore also constraints may change which can be seen for a special radiosity model [START_REF] Sheikholeslami | Simulation of Void Formation in Interconnect Lines[END_REF] that describes a temperature-driven chemical reaction for material deposition. To represent the physics, constraints are used to force the optimizer to use reasonable parameter sets. Due to implicit cross-dependencies between input parameters and boundary conditions, the constraints may also change with a new optimization state. A big challenge are optimizations with restrictions for the simulation, e.g., if the temperature reaches a certain value, where simulation is no longer able to predict the device behavior appropriately [START_REF] Holzer | Extraction of Material Parameters Based on Inverse Modeling of Three-Dimensional Interconnect Fusing Structures[END_REF] due to inadequate physical models, appropriate constraints have to be applied to ensure that the internal states of the simulation models as well as the its output parameter remain valid.

Most of the optimization algorithms used in Siesta support such restrictions only rudimentary. Therefore, only a limited number of optimizers can be used for these specific tasks. Thus, the user has to carefully design the specifications of a problem, otherwise the optimization can become instable and an interaction with the user is necessary, or the optimization process might not converge at all.

Siesta itself consists of several functional blocks which are shown in Fig. 2. The experiment and the configuration can be setup either with a graphical user interface (gui) or using text-based templates. Text-based configuration offers many more possibilities for tool combinations and is more flexible than the gui where only a limited number of problem classes based on predefined templates can be handled. Once the experiment has been setup, the experiment definition is submitted to the SeiLib (Siesta environment interaction library) which handles the interaction between the optimization software tools and the actual execution on different hosts in a heterogeneous network. Moreover, SeiLib provides a sophisticated host management which enables to use advanced load balancing on a heterogeneous network.

After the scheduled simulations have successfully been finished, the simulation results are submitted to the job database with the experiment definition. The quality of the simulation result is determined by using a userdefined score function to notify the optimizer to submit an updated parameter set for the next optimization loop according to the received quality criterion. The optimization results of Siesta can be tracked via visualization tools as well as by simple text files for data manipulation and logging purposes. Currently available optimization modes for Siesta [START_REF]SIESTA -The Simulation Environment for Semiconductor Technology Analysis[END_REF] are optimization, calibration, parameter extraction, and design of experiment (doe). Each of the optimizationrelated modes can be configured for minimization or maximization. The doe [START_REF] Lorenzen | Design of Experiments[END_REF] mode computes the score function for a whole parameter space with a certain userdefinable algorithm to cover all regions of interest. The output of a doe can be fed to a database for design engineers to improve their productivity by reducing waiting periods for simulation inquiries. In all these optimization modes, the score function which indicates the quality of the simulation result will be minimized or maximized, depending on the optimization goal. With this abstract modeling of the optimization procedure, the behavior can be tuned for particularly complex needs.

The default operation mode is optimization, which targets a specified scalar-valued quantity, for instance the power output of a simulated device, a leakage current of a transistor, or side effects like parasitic capacitances, or the on-resistances of transistors. Furthermore, power consumption, maximum temperature of a device, and the maximum value of the electric field can be optimized with an appropriate setup. In addition, combinations of different device parameters like the gain of amplifier devices, different sorts of yield, efficiencies, or the ratio of capacitance per area for memory cells can be optimized.

The calibration mode is commonly used for inverse modeling [START_REF]TCAD Sentaurus Y-2006.06 User Manual[END_REF][START_REF]SIESTA -The Simulation Environment for Semiconductor Technology Analysis[END_REF]. In this mode Siesta optimizes parameters in order to fit specific requirements consisting of output characteristics or constraint equations. The simulation results shown in Section 3.1, depict the outcome of the The operation of calibration and parameter extraction is quite similar. Calibration requires a good initial guess, whereby the initial parameter vector for the parameter extraction is not well known. Therefore, parameter extraction often requires a global optimization techniques due to the possibly large uncertainty of the given initial values.

Simulation Tool Flow

Since Siesta offers a text-based open application interface [START_REF] Holzer | Optimization and Inverse Modeling for TCAD Applications[END_REF], it is very easy to add additional simulation software tools to a particular simulation tool flow. Siesta provides several interfaces to commercial as well as to tailor-made simulation tools.

APPLICATIONS

TEOS Deposition

Material deposition processes can be accurately described by thermo-chemical reaction mechanisms [START_REF] Schumicki | Prozeßtechnologie[END_REF][START_REF] Raupp | Kinetics and Mechanism of Silicon Dioxide Deposition Through Thermal Pyrolysis of Tetraethoxysilane[END_REF]. However, the quantitative predictability of such fairly complex models is still limited for processes of industrial interest [START_REF] Coltrin | Chemical Kinetics in Chemical Vapor Deposition: Growth of Silicon Dioxide from Tetraethoxysilane (TEOS)[END_REF] in terms of time and in terms of accuracy due to fluctuations in the process conditions. Thus, simple calibrated process models applying sticking coefficients are a good alternative for process investigations [START_REF] Cale | Topography Simulation for the Virtual Wafer Fab[END_REF]. Especially for problems with high temperature variations, this approach reduces the computational effort drastically by orders of magnitude. Our attempt is to investigate whether it is possible to determine a valid parameter set for lpcvd (low pressure chemical vapor deposition) of teos at different temperatures and ambient pressures. The simulator Elsa (enhanced levelset applications) [START_REF] Sheikholeslami | Simulation of Void Formation in Interconnect Lines[END_REF][START_REF] Sheikholeslami | Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process[END_REF] has been calibrated by measurements from literature [START_REF] Heitzinger | Simulation and Inverse Modeling of TEOS Deposition Processes Using a Fast Level Set Method[END_REF] for typical trenches filled with silicon oxide from teos deposition as depicted in Fig. 3.

Stefan Holzer et al. An Extendable Multi-Purpose Simulation and Optimization Framework

As input parameters for the calibration process we provided the sticking coefficients for a lpcvd teos deposition model proposed in [START_REF] Sheikholeslami | Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process[END_REF] to describe the pyrolytic thermo-chemical reaction for deposition.

The calibration result for the first trench presented in Fig. 4 excellently agrees for the highly nonlinear equation system, and also other trenches for different temperatures and ambient pressures (cf. Fig. 5) show good agreement with measurements.

In addition, the identified parameter set is valid for a whole series of available test trenches, where the aspect ratio is in the range of 1.1 to 3.5. Typically, according to the depletion of the reactant at the bottom of the trench, the deposition model with sticking coefficients produces a larger error, if applied to trenches with larger aspect ratios.

Thermo-Electric Generator

Thermo-electric power generators made of SiGe alloys which exploit thermal gradients [START_REF] Span | Thermoelectric Power Generation Using Large Area pn-Junctions[END_REF] are interesting for future waste heat recovery applications because of their potentially high reliability.

Several device structures based on the Seebeck effect have been proposed to the conversion of heat to electrical power. As of yet, however, none of these approaches is for lpcvd teos deposition for a trench with a high aspect ratio at 0.5 Torr.

suitable for industrial application or economical use. We investigated and optimized a novel device structure for electro-thermal energy conversion with the goal to gain optimum power outputs as well as efficiencies for given thermal environments. A principle sketch of the device is depicted in Fig. 6. This presented thermo-electric generator consists of a large scale pn-junction with different thermal boundary conditions at each side of the junction. The heated side implies a zone where free electron-hole pairs are thermally generated and separated by the built-in potential of the pn-junction [START_REF] Span | Thermoelectric Power Generation Using Large Area Si/SiGe pn-Junctions With Varying Ge-Content[END_REF]. Electrical contacts are mounted at the cold side of the structure where an actively cooled heat sink forces the temperature at the cold side to room temperature.

Due to the strong temperature gradient along the pnjunction, the free carriers experience a driving force towards the cooled side. As a limiting factor, the thermal conductivity of the involved materials causes also a high heat flux from the heated to the cooled side. This in principle parasitic heat flux has to be minimized in order to obtain good efficiencies. Therefore, our goal is to obtain high power output through the introduction of graded material compositions Si x Ge 1-x as well as proper device geometries in order to achieve an appropriate temperature distribution for maximized carrier generation, optimum electrical transport conditions, and minimized heat flux.

For our investigations we used the three-dimensional device simulator Minimos-NT [START_REF]MINIMOS-NT 2.1 User's Guide[END_REF] and Siesta in the advanced two-loop optimization mode, where we extract the necessary load resistance for power match in the first optimization loop to obtain the best result for each single material composition. The thereby obtained intermediate result is provided for the calculation of the corresponding power output and for determining the device's power conversion efficiency. The efficiency has been taken as an objective target for the overall optimization process (second optimization loop).

As a result we achieved the position-dependent concentration of Ge and the predicted power output of the semiconductor device structure. The sensitivity of the power output to several parameters is tracked in order to remain within the manufacturing tolerances. Fig. 7 presents the optimization procedure in four major steps. As an initial guess, a Si-based device structure has been optimized by introducing a step-like Ge concentration profile as a first enhancement. As a second step and further improvement, the Ge content has been adapted to obtain a good local temperature distribution in order to maximize the total amount of generated carriers as well as the local Seebeck effect.

Moreover, a layout optimization further improved the efficiency by adapting the electrical transport conditions in a third optimization step. The global optimum for the power output was obtained by introducing certain doping profiles which maximizes the power output.

CONCLUSIONS

We have presented Siesta as a powerful and highly sophisticated optimization tool which can deal with thermal problems to perform optimizations on nonlinear electro-thermal semiconductor equations systems in Minimos-NT as well as on technology-related processes in Elsa including transient thermo-chemical simulation tasks. Moreover, these two applications have demonstrated the capability of this optimization tool to deal with a wide range applications due to its open application interface to other commercial and tailor-made tools, which enables to provide appropriate optimizations techniques for highly complex systems like thermally coupled electrical and chemical systems.

Fig. 1

 1 Fig.1depicts an abstracted data flow for a Siesta optimization. The presented optimization procedure consists of a loop which terminates when the result has reached the required accuracy determined, for instance, by the first derivative of the objective score function. An-

Figure 1 :

 1 Figure 1: Overview of the data flow during an optimization with Siesta.

StefanFigure 2 :

 2 Figure 2: Overview of the internal structure of Siesta showing various configurable modules.

Figure 3 :

 3 Figure 3: tem picture of a trench structure for identification of sticking coefficients of a lpcvd teos deposition model.

Figure 4 :

 4 Figure 4: Comparison of simulation and measurementsfor lpcvd teos deposition for a trench with a low aspect ratio at 0.6 Torr.

Figure 5 :

 5 Figure 5: Comparison of simulation and measurementsfor lpcvd teos deposition for a trench with a high aspect ratio at 0.5 Torr.

Figure 6 :

 6 Figure 6: Thermo-electrical power generator structure using a temperature gradient to exploit the Seebeck effect.

Figure 7 :

 7 Figure 7: Comparison of different optimization results after different stages of optimization.

ACKNOWLEDGMENTS

This work has been partly supported by FFG, the Austrian Research Promotion Agency ( Österreichische Forschungsförderungsgesellschaft) for projects 809975 and 810128 and the local government (Impulspaket Tirol).


Giovanni Buonaiuto

Andrea Irace

Giovanni Breglio

Paolo Spirito

THERMOS 3 , A TOOL FOR 3D ELECTROTHERMAL SIMULATION OF SMART POWER MOSFETS

In this work we present a novel 3D simulation tool capable of taking into account also particular driving strategies of the electron device as it may be the case of Smart Power MOSFETs where a control logic interacts with the power section and controls its dissipated power and temperature. As an example a thermal shutdown circuit, capable of reading the temperature on chip and switching the device off if the latter reaches dangerous values is usually embedded within Smart Power devices used in automotive applications to drive direction light or small motors/actuators.

INTRODUCTION

The simulation of power electron devices is a complex numerical problem and it has been faced in many different ways in the recent past as the issue of power dissipation together with the knowledge of electrothermal interactions in MOSFETs has become relevant. Being coupled, but on a different timescale with respect to the thermal problem, the electrical problem is usually reduced to few DC equation that are sufficient to model the temperature dependent static behavior of the single cell. The time-dependent heat equation is solved, numerically or analytically, in a way such as to take into account layout geometries, boundary conditions and heatsink influence. The THERMOS 3 simulator we propose, entirely written in MATLAB, is based on a forward iterative finite difference time domain scheme [START_REF] Breglio | Experimental detection of time dependent temperature maps in power bipolar transistors[END_REF] where the electrical equivalent of the thermal problem and the electrical quantities (drain current, source voltages) are solved selfconsistently at each discrete time step. Non linearity in the thermal conductivity together with voltage depolarization due to finite resistance of the source metallization is taken into account. The ID=f(VGS,VDS,T) behavior of the unit cell is modeled considering temperature dependence of the threshold voltage, mobility and MOSFET internal resistances.

Convection on the surface and sides and isothermal boundary condition at the heatsink have been used. As an exhaustive example of the capability of this new tool we present the simulation of a smart power device produced by STMicroeletronics (Fig. 1). This device is protected during permanent short circuit by a current feedback loop which keeps the dissipated power inside the SOA together with a thermal shutdown circuit which shuts the device of if temperature on chip exceeds a reference value. Dynamic temperature behaviour of this device has been fully characterized by fast transient infrared imaging [START_REF] Irace | Reliability enhancement with the aid of transient infrared thermal analysis of smart Power MOSFETs during short circuit operation[END_REF] therefore a quantitative comparison with the simulation is available for validation. One main issue is the optimization of timestepping since the overall behaviour of the device has to be observed in the 100ms (or longer) timescale while sensitive information such as fast temperature transients can be as short as 100µs. In our approach an adaptive timstepping strategy together with switching event prediction and detection has been implemented.

THE SIMULATOR

A multicellular power VDMOS can be treated as a number of equivalent single cells all of them sharing the same voltage on the drain and gate terminal and with the sources connected through a metal layer with a finite resistivity. Therefore both VDS and VGS are dependent not only on temperature (the resistivity of the metal layer is ) which are usually considered in power MOSFET models since we are interested in the behaviour of the device when it is driven in its triode or pinch-off region. Therefore for the generic cell we have:

0 0 0 0 ( ) 1 ( ) ( ) 2
( ) ϕ µ µ µ - = - - = ⎛ ⎞ = ⎜ ⎟ ⎝ ⎠ T T ox m V V T T W K T T C L T T T (1) ( ) ( ) 2 2 0 2 DS GS T D GS T DS GS T DS GS T GS T GS T DS GS T if V V I K V V V V if V V and V V V K V V if V V and V V V ⎧ ≤ ⎪ ⎪ ⎡ ⎤ = - - ≥ - ≤ ⎨ ⎣ ⎦ ⎪ - ≥ - ≥ ⎪ ⎩ (2)
Depolarization effects due to finite resistance of the source metal layer can be taken into account by solving the linear problem:

) ( ) ( T I V T Y E = ⋅ ( 3
)
where YE is the admittance matrix (where temperature dependence of the metal resistivity is taken into account) which defines the electrical network modelling the metal layer, V is the vector of the voltages at each node and I are the current flowing into each node (that is the drain current of the active MOSFET cells). Given the temperature field T(x,y) on the surface of our domain, both VDS and ID are known at each cell and therefore it is know the dissipated power at the particular location, that is the heat flux field Q(x,y) according to the equations:

( , ) ( , ) ( , )

DS D V x y I x y Q x y A = (4)
Since we discretize the domain in x and y directions the equation (4) reduces to its discrete form which gives us the discrete heat sources needed to solve the thermal problem , , , ,

i j i j i j i j V I Q A = (5)
The power device is treated as a surface heat source, being the heat flux equal to the power dissipated by joule heating within the device, while the solder and heat sink are modelled through simple RC networks. Convection/Radiation from the top and side surfaces are also taken into account. By writing heat balance at each node of the domain we can completely describe our problem by its matrix form

) ( ) ( T Q T T Y T = ⋅ (6)
where the admittance matrix YT is a sparsely populated matrix, T is the vector which defines temperatures at each node of the domain and Q is the vector which takes into account the heat flux injected into the domain as a consequence of the dissipated power by the power device.

The solution strategy we propose, entirely implemented in MATLAB, is based on a forward iterative finite difference time domain scheme [START_REF] Mills | Heat and mass transfer[END_REF] where the electrical equivalent of the thermal problem as described by eq.4 and the electrical quantities (drain current, source voltages) of eq.3 are solved iteratively at each discrete time step until a number desired convergence criteria is reached. Before entering the details of the simulation results few words regarding driving strategies of Smart Power Devices and consequent meshing and time stepping solutions have to be spent.

In our case the single unit cell is too small to be considered as a good elementary cell to discretize our domain. Therefore we decide to group a number of single devices and treat them as a macro cell with the current scaled by its area. We usually start with a 50µm x 50µm cell although, during the transient simulation, an adaptive remeshing strategy is used to refine the mesh where the temperature gradients are higher. In the case of the VND800PEP, which is about 2mm x 2mm the starting grid results in 40x40 elementary cells. During the transient solution the number of nodes is kept constant whereas their location is moved in the region where temperature gradients are higher.

Regarding time stepping strategy, the issue is slightly different. We have already described the driving strategy of this kind of devices and, in general, as we will deal with smart power devices, where dynamics can happen with very different dynamics and timescales, a fixed time step strategy can increase the computational time to non practicable solutions. We therefore choose an adaptive time stepping strategy where the time step shortens as temperature and voltage derivatives increase. This on its turn poses a problem when the control logic switches the power on and off being at this time instant the VGS derivative is theoretically infinite demanding for a time step which approaches to zero. We choose in this case an event-driven predictive algorithm in order to foresee the instant when the condition for commutation will be verified and adjust the time step accordingly. This is a quite new approach in the solution of electrical network with a high number of switches and it can be also implemented in this case where all the unit cells can be treated as a single switch.

THE FAST TRANSIENT INFRARED IMAGING

The detection of the temperature distribution across the area of the device in transient conditions has been made possible by the use of a custom developed radiometric 2D measurement system that allows acquiring the transient temperature maps of the device surface [START_REF] Irace | Reliability enhancement with the aid of transient infrared thermal analysis of smart Power MOSFETs during short circuit operation[END_REF]. We use a fast (actual time resolution is less than 2 µs) single cooled Cd-Mg sensor mounted in a microscope optical chain that has an equivalent spot size of about 10 µm with a working distance of 2.5 mm. In order to perform a 2D scanning of the surface to be mapped, we use an x-y step motor stage controlled via a motor control card installed in a PC which controls device biasing and data acquisition. In such way, the device under test is shifted with respect to the microscope spot, and it is possible to cover the entire surface under observation. The step by step acquisition of the radiometric waveforms coming from the sensor is performed by means of a 5MS/s 12bit A/D converter card that connected via the PCI bus into the PC converts and elaborates the output detected signal. The acquisition software also performs the pre-filtering of the detected signal by using an averaging procedure to increase the signal to noise ratio.

It is important to remember that radiometric systems are able to perform absolute thermal measurement only if the target emissivity coefficient is known. Unfortunately, the surface of power devices is often composed of different materials (i.e. aluminum, passivation, silicon oxide, etc.) that are characterized by different emissivity coefficients. Hence, in our thermal mapping procedure, a preliminary characterization step is also performed in order to determine the emissivity coefficients of the points that define the acquisition grid. The temperature map is reconstructed by acquiring the emissivity signals synchronized with the electrically switching and after that the numerical processing of the radiometric transient signals starts. First of all, the stored dynamic radiometric signals are properly corrected by using the emissivity coefficient of the corresponding grid point and converted into the true dynamic temperature signal. Then, the temperature array data manipulated to obtain the time frames of the temperature distribution on the DUT. By means of this equipment and following the previously described procedure we have obtained the thermal transient analyses used to optimize the performances of the devices described in this work.

THE VDN SMARTH POWER MOS AND ITS PROTECTION STRATEGY

Figure 1 shows a smart power MOSFET made with M0TM technology integrating a DMOS and its control part in a monolithic chip solution. To comply with automotive requirements this class of devices includes several protections that are described in fig. 2.

Short circuit protection

The more restricting rule driving the protection strategy of the Power actuator is to avoid false short circuit detections in the harsh and very noisy automotive environment. Beside a high level of electromagnetic susceptibility the devices should not turn off either for an inrush condition either for intermittent short circuit. The short circuit protection is implemented using only negative feedback method to ensure stability and to maintain the device in a predictable status in every condition.

A Current limitation combined with thermal shut down intervention protects the power device during short circuit operation. The integrated current feedback fixes the working point in the active area of the Power stage.

The resulting high power dissipated equal to battery voltage multiplied by Drain current leads to a fast increase of the thermal sensor temperature and to the intervention of thermal shut down block.

Logic

Current density versus technology evolution

The balance of power dissipation due to joule effect (P d = R on * I 2 ) and the ability to extract the heat (P d = R TH * (T J -T AMB )) establish the current rating of a Power device. In actual automotive junction boxes Smart Power are surface mounted and the heat is dissipated via G. Buonaiuto, A. Irace, G. Breglio the cupper traces of a PCB in FR4. With this boundary condition the die size reduction does not affect significantly the thermal resistance junction ambient so it is the on resistance of the device that manly sets the current rating. Scaled technology permitted a significant die size reduction and the R on *mm 2 has decreased by a factor 10 in the last 10 years. As a result the size of the silicon can be reduced significantly for the same targeted load.

On the other hand the short circuit current of the device cannot be reduced because this value needs to be higher than the inrush current of the targeted loads. The result is that also the power density generated in the device during short circuit increased also by a factor 10. The protection strategy is very simple (Fig. 3): as temperature at sensor location reaches a high threshold value (Tshutdown) drain current is switched off and the device is left to its free thermal evolution; when temperature then reaches a low threshold value (Treset) drain current is switched on again. In this way power is controlled, the device is kept well inside the SOA and failures are prevented (although reliability problems due to metal fatigue can occur [START_REF] Irace | Reliability enhancement with the aid of transient infrared thermal analysis of smart Power MOSFETs during short circuit operation[END_REF]). At this point the temperature is toggling between max temperature fixed and fixed temperature reset. The device returns automatically to nominal operation when the short circuit disappears so the device continues to operate properly.

Fig. 3 The sketched representation of the protection strategy of the device under short circuit conditions: Time plots in milliseconds scale of the whole dissipated power and temperature of the embedded thermal sensor.

RESULTS, COMPARISONS AND COMMENTS.

The device has been discretized in Nx × Ny × Nz unit cells each with its own thermal parameters and operated in short circuit to the usual battery voltage Vbat=12V.

Current feedback fixes the total current at Ilim=10A. In Fig. 4 we report a comparison between experimentally detected temperature distribution and the result of the simulation. As we can note a good quantitative agreement is obtained both in shape and in peak temperature value. To further investigate the features of the simulator we would like to underline that a well designed thermal shutdown strategy relies on the optimal position of the thermal sensor on the device surface. If this should not be the case, temperature difference between the sensor and the maximum temperature reached on chip can be observed and reliability of the device can be eventually impaired as temperature fatigue of the metals and soldering joint might increase the Ron of the device. In Fig. 5 we report a simulation where the temperature sensor has been deliberately placed far from the region where temperature reaches its maximum, we notice how, even if the sensor is correctly switching the device, the maximum temperature on chip reaches values higher than Tshutdown. From Fig. 5 and Fig. 6 the PWM modulation of the dissipated power and the timestepping strategy can also be observed. In particular (see Fig. 6) it is noticeable that as temperature at the sensor location reaches the shutdown threshold timestepping is reduced thanks to the predictive event detection algorithm and the same happens when temperature reaches the reset value with a negative slope. The value of such a tool in the design stage of a smart power device is straightforward as it can be used to optimize the whole design, influence of layout (i.e. position of temperature sensors, bond pads location etc.) and to investigate the performances of different protection strategies.

FURTHER IMPLEMENTATION

In our study on these kind of devices and in all the experienced acquired in the electro-thermal simulation of power devices, we have understood that not only the localization of the bond wires is important in simulations but also a proper electro-thermal description of these components must to be taken into account. Into the next new version of the THERMOS 3 simulation tool will be inserted also the possibility to well simulate and describe how the power bond wires, described in terms of position contact area with the device, thick and length, of power MOS can affect the electro-thermal behavior of the whole device.

Fig. 1

 1 Fig. 1 Optical picture of the two channels monolithic smart Power MOSFET implemented with M0 technology (VND830SP).

Fig. 4 :

 4 Fig.4: Temperature distribution on chip: experimental (up) and simulated (down)

  , A. Irace, G. Breglio, P. Spirito Thermos 3 , a Tool for 3D Electrothermal Simulations of Smart Power MOSFET ©TIMA Editions/THERMINIC 2006 -page-ISBN: 2-916187-04-9

Fig. 6 A

 6 Fig.5 Simulation of the permanent short circuit protection on a VND800PEP device

  G. Buonaiuto, A. Irace, G. Breglio, P. Spirito Thermos3 , a Tool for 3D Electrothermal Simulations of Smart Power MOSFET

	itself a function of temperature) but on the layout of the
	device and position of the source bond wires. The single
	cell is modelled by the following set of equations which
	are a version of the SPICE LEVEL 1 model modified to
	take explicitly into account temperature dependence of
	the threshold voltage and mobility. All the internal
	capacitances are neglected because the transient problem
	is observed on a different timescale, and also the other
	devices (drain-body diode etc.
	©TIMA Editions/THERMINIC 2006	-page-	ISBN: 2-916187-04-9

  G. Buonaiuto, A. Irace, G. Breglio, P. Spirito Thermos3 , a Tool for 3D Electrothermal Simulations of Smart Power MOSFET

©TIMA Editions/THERMINIC 2006

-page-ISBN: 2-916187-04-9

  , P. Spirito Thermos3 , a Tool for 3D Electrothermal Simulations of Smart Power MOSFET

©TIMA Editions/THERMINIC 2006

-page-ISBN: 2-916187-04-9


Michael Hertl --

Romain Fayolle -Diane

Weidmann -Jean-Claude Lecomte

THERMAL STRESS FAILURES: A NEW EXPERIMENTAL APPROACH FOR PREDICTION AND PREVENTION

A new experimental tool for analyzing the topography and deformation of electronics components under thermomechanical stress is presented. Application examples are shown for a great variety of components, for localizing and quantifying deformations of electronic assemblies.

Cooling and heating cycles following JEDEC type thermal profiles have been applied on different components, both before and after assembly. Simultaneously, real time topography and deformation measurements are obtained. These capabilities constitute a powerful tool for failure prediction, risk evaluation, and accelerated development.

The high resolution optical setup allows analysis of deformations in the micrometer range, even for very irregularly shaped surfaces.

INTRODUCTION

Decreasing the number of component failures like delaminations or BGA ball ruptures is a constant concern for electronics development engineers. Thermal stress induced by CTE mismatch between the multiple laminated materials or by increasing solder temperatures as consequence of the RoHS standard is the physical reason for a great number of damages. Additional damage risks are induced by hygroscopic stress, which is out of the scope of the present paper.

Failure analysis is often done by numerical modeling [START_REF] Suter | Proc. of the EuroSimE 2005 conf[END_REF]. However, the modeling of the thermomechanical behavior of electronic assemblies, whether soldered or not on a PCB, encounters many difficulties. These difficulties are mainly due to the rapid increase of the number of layers and the fact that the characteristics of the materials and the interfaces under thermal and mechanical stresses are partially unknown.

Reliable experimental tools are therefore required for detection of risks related to thermo-mechanical stress of the components [START_REF] Eurosime | Topography and Deformation Measurement under thermomechanical solicitations[END_REF]. Several conditions apply in order to obtain relevant results (Fig. 1):

The measurement has to be non destructive, in order to analyze real components without any obligation of cutting, drilling, or mechanically deforming them; The possibility to take measurements with a large field of view and to permit the simultaneous acquisition of all surfaces (S 1 , S 2 , S 3 in Fig. 1) of an electronic board has to be given; Measurements have to be done under thermal stresses like those encountered by the component during its assembly and product life time: reflow profiles, on/off cycles, external thermal solicitation, and others; Real time measurements simultaneously in plane (x, y) and out of plane (z) are necessary [START_REF]PC2A[END_REF]; Finally, the setup has to be flexible enough to allow analysis for a great number of different applications, like package development, CTE evaluation, in service stress evaluation, RoHS consequences analysis, reliability tests.

∆z1 ∆z2 ∆z3 ∆x1 -CTE 1 ∆x2 - CTE 2 Compression Tensile stress z1 z2 z3 0 S1 S2 S3 z1 + ∆ ∆ ∆ ∆z1 0 ∆x3 -CTE 3 z3 + ∆ ∆ ∆ ∆z3 Z2 + ∆ ∆ ∆ ∆z2
The scope of the present paper is to introduce TDM, a new tool developed for Topography and Deformation Measurement under thermo-mechanical stress. After a description of the experimental set-up, a large section is reserved for application examples in thermal management development in various fields of today's electronics.

SET-UP

The experimental setup is shown in Figure 2. The electronics assembly to be studied is illuminated by a light source, which projects a structured light field on the sample surface. The light's intensity pattern is more or less deformed by the sample's surface structure. The resulting image is captured by a CCD camera. Real thermal stress is available by top and bottom heating and cooling elements. The current sample temperature is monitored by several thermocouples. Thus JEDEC type temperature profiles with gradients up to +/-3°C/s may be imposed to the component, within a temperature range from -40 up to +300°C. This setup allows absolute and relative deformation measurements both in plane (xy) and out of plane (z). The in plane resolution is 5×10 -5 times the sample length, the out of plane resolution is 10 -4 times the sample length.

In comparison to Moiré interferometry [START_REF] Stellrecht | [END_REF], the present set-up features two main benefits. First, there is no need for a reference grating or any other movable part, simplifying noticeably the entire alignment and acquisition procedure. Second, the measurement procedure works independently for each voxel of the measurement volume. Therefore, large height variations (∆z steps) or even holes in the sample do not affect at all the measurement at the surrounding voxels.

RESULTS

Power device: Al 2 O 3 brazed on Cu plates

When alumina (Al 2 O 3) is deposited on copper (Fig. 3), for power components for example, the difference in the coefficients of thermal expansion between the two materials creates a deformation of the assembled parts and results in stress at the interface when the component returns to room temperature.

At the brazing temperature (400-600°C) both the alumina and the copper part are plane. During cooling, both materials will retract differently due to CTE mismatch, and strong deformation occurs. At room temperature the alumina part becomes convex, while the copper part is concave (Fig. 4). The space in between the two parts is filled with brazing alloy. However, the interface is subjected to strong stress, both in plane (shear stress) and out of plane (tensile stress). When submitted to thermal cycling this configuration contributes to premature aging and significantly increases the failure risk. Additional investigation [5] of the part by scanning acoustic microscopy (SAM) confirmed crack initiation in the four angles of the brazing area (Fig. 5).

Introducing TDM measurements in the development cycle of this product allowed to optimize the characteristics of the part (like the exact dimensions and the solder characteristics), in order to minimize the effect of opposite bending of the alumina and the copper part.

Lead free JEDEC thermal profile effect on BGA deformation and damage

New JEDEC type temperature profiles for soldering under lead free conditions attain sensibly higher peak temperatures than classical reflow profiles, with strong incidence on damage risks due to CTE mismatch or other stress induced deformations.

If such a high temperature profile is used for soldering a BGA, then both the BGA and the PCB will strongly bend during the soldering process. The final form of the balls will be fixed at more than 200°C, when the solder becomes solid. However, the final geometric form of BGA and PCB is determined only when the assembly is back at room temperature. Therefore, some balls will see compressive, others tensile stress (Fig. 1).

TDM allows following in detail the topography of the parts to be soldered during a JEDEC type reflow profile (Figures 6 and7).

The topography images show several incidents:

• The initial topography at room temperature is slightly concave. Up to 150°C, the BGA changes its topography only slightly, to become flat at this temperature. Between 150 and 200°C, the topography changes slowly, and the BGA becomes convex. • After cooling down to room temperature, some convex deformation remains. This hysteresis effect is the second characteristic observation when delamination occurred.

This kind of measurement has several direct benefits for the thermal management developer: The temperature where delamination occurs can be determined, and if possible the applied reflow profile adapted accordingly. The amplitude of deformation allows an estimation of the failure risk of the component in future applications, even if no direct delamination occurs. And successive measurements with the same temperature profile allow an evaluation of the componenet behavior under future cyclic load, like on/off cycles or for fatigue control.

Accuracy control on very small components

With increasing miniaturization, quality control on very small components becomes an issue in all fields of electronics. Parts manufactured by subcontractors needs to be controlled before being integrated in complex assemblies.

Figure 8 shows the photograph of a standard module for SIM cards in mobile phones. Critical dimensions are the height and the parallelism of those parts of the module which will be soldered onto the PCB. Figure 9 shows the topography of the bottom side of the component, measured with TDM. The height and the parallelism of the parts to be soldered are clearly identified, and may be compared to manufacturing specifications. Note that TDM is able to obtain high resolution topography even for components with very strongly structured surfaces, even in presence of multiple holes. A 3D representation of the component is given in Figure 10. This view, which is calculated on the basis of the 2D bottom view acquisition shown in Figure 9, allows detailed verification of the dimensions of further critical parts, like the springs in the centre of the module.

Overall, application of TDM measurements to this part allowed a big step forward towards total quality control of pieces delivered from subcontractors, manufactured following specifications defined in the order.

Quantitative deformation measurement on BGA after assembly on PCB

In this application, we compare, for the same component/PCB set, the assembly process with a Pb/Sn profile, Figure 11, and with a lead free profile, Figure 12. These Figures show diagonal warpage During the two different reflow profiles, the topography changes with temperature strongly differ. This situation induces different effects on the interface integrity, which might be seen afterwards using acoustic microscopy, and ball interfaces, which might be seen by X-ray tomography.

CONCLUSIONS

A new experimental tool, TDM, has been developed for topography and deformation measurement under thermo-mechanical stress. This tool enables high resolution absolute 3D imaging of warpage (z) and in plane (xy) deformation.

Four examples have been discussed for application of TDM in prediction and prevention of failures in electronics. In each example, analysis of the different components in an early stage of the development and production cycle allowed an early failure risk analysis, successive design changes, and thus shorter time to market as well as lower risk of customer returns.

In future, the results obtained by TDM will be coupled with modeling, which will allow easier definition of boundary conditions and validation of modeling results by experimental values.

Fig. 1 :

 1 Fig. 1: Schematic view of the variation of a BGA's topography with temperature. Top: BGA on PCB at room temperature. Bottom: Same assembly at 300°C.

Fig. 2 :

 2 Fig. 2: Sketch of TDM setup.

Fig. 3 :

 3 Fig. 3: Video Image of the Alumina part brazed on copper.

Fig. 4 :

 4 Fig. 4: Characterization of the alumina and the copper surface in one single measurement, at room temperature. A software zoom is possible on each surface, for a high resolution image of the surface topography.

Fig. 5 :

 5 Fig. 5: SAM analysis of the alumina -copper interface. Crack initiation is observed in all 4 angles of the brazing area.

Fig. 6 :Fig. 7 :

 67 Fig. 6: JEDEC type reflow profile generated and monitored by TDM. The arrows indicate temperatures where deformation measurements are automatically triggered. These temperatures may be defined by the user.

Fig. 8 :

 8 Fig. 8: Photography of a SIM card module. Dimensions of the component: 25 x 15 x 2 mm ( l × w × h).

Fig. 9 :

 9 Fig. 9: Height profile of the bottom side of the SIM module. The most prominent parts (green) are used for soldering the component onto the PCB.

Fig. 10 :

 10 Fig. 10: 3D view of the SIM module, calculated from the image given in Fig. 9. Note that one single 2D bottom side measurement of the component is sufficient for generating this view.

  profiles measured on the BGA while soldering on a PCB. In each Figure, the top diagram corresponds to the time interval where temperature increases, the lower diagram to the interval where temperature decreases.

Fig. 11 :

 11 Fig. 11: Diagonal warpage profile on a BGA during soldering on a PCB. Analysis for a Pb/Sn temperature profile (maximum temperature 230°C)

Fig. 12 :

 12 Fig. 12: Diagonal warpage profile on a BGA during soldering on a PCB. Analysis for a lead-free temperature profile (maximum temperature 255°C)

Fig. 13 :

 13 Fig. 13: SAM image of the BGA soldered on PCB using a lead-free reflow profile. White circles: crack initiation