Xueqing Li

Kaisheng Ma

Sumitha George

John Sampson
email: sampson@cse.psu.edu

Vijaykrishnan Narayanan

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures

Keywords: Internet-of-things, emerging devices, tunnel FET, negative capacitance FET, energy harvesting, nonvolatile memory, nonvolatile computing

In recent years, the concept of Internet-of-Things (IoT) has attracted significant interests. Required by the applications, the IoT power optimization has become the key concern, which relies on innovations from all levels of device, circuits, and architectures. Meanwhile, the energy efficiency of existing IoT implementations based on the CMOS technology is fundamentally limited by the device physics and also the circuits and systems built on it. This chapter focuses on a different dimension, exploring how emerging beyond-CMOS devices, such as tunnel field effect transistor (TFET) and negative capacitance FET (NCFET), and the circuits and architectures built upon them, could extend the low-power design space to enable IoT applications with beyond-CMOS features.

Introduction

Improved sensing, signal processing, and communication has significantly changed the connection between humans and the world with the rise of intelligent devices being developed for the Internet-of-things (IoT) [START_REF] Atzori | The Internet of Things: A survey[END_REF]. As designers seek to make these IoT systems smarter and more ubiquitous, high energy-efficiency has been the key to enhance both connectivity and IoT signal processing functionality. Crosslayer efforts in improving solid-state devices, and the circuits and systems built upon them, are the key to achieve the high energy efficiency demanded by an expanding future of IoT tasks.

Concurrently, the needs for portability and mobility, common in IoT applications, have driven devices toward battery and/or ambient energy harvesting power solutions [START_REF] Li | Rf-powered systems using steep-slope devices[END_REF]. In the past few decades, the power consumption of integrated circuits has been lowered significantly through the scaling of the CMOS technology together with signal processing techniques. Such achievement has made more and more IoT applications feasible while being powered with a modest battery capacity or ambient energy harvester (e.g. a solar cell). However, further power reduction has become more and more challenging for conventional CMOS technology (including FinFET innovations) and the computation and communication methodologies built upon it. The conventional means of power reduction alongside CMOS scaling of using a lower supply voltage to reduce the dynamic power consumption while simultaneously reducing threshold voltages to provide sufficient computing speed causes exponentially increasing leakage power, which can now approach magnitudes similar to dynamic power. This fundamentally limits the expansion of functionality via CMOS scaling alone, especially when IoT devices are powered by batteries or harvested energy.

Battery-less IoT systems face further challenges in obtaining sufficient energy from the low and intermittent power source in the ambient environment [START_REF] Kim | Ambient RF Energy-Harvesting Technologies for Self-Sustainable Standalone Wireless Sensor Platforms[END_REF]. Existing energy-harvesting circuits may encounter a low-input voltage that leads to a low power-conversion efficiency. Low harvested power not only limits the average amount of tasks being performed, but also increases the response latency, which is a key factor of quality-of-service (QoS). Meanwhile, distinct from conventional computing systems with a stable supply, the intermittency of harvested power also requires additional backup and restore operations, which consumes extra energy and time and carries the risk of losing computation progress if a backup operation is not carried out in time.

While these fundamental challenges have become a barrier when using CMOS technology, the advent of emerging technologies have brought new opportunities. These emerging technologies include emerging transistor devices, circuits, and architectures. The new opportunities can be seen, broadly, as advances in two key directions. Firstly, the Boolean switching behavior of some emerging transistors can replace the existing CMOS transistors in conventional computing approaches with substantially improved prospects for power scaling and low-voltage operation [START_REF] Nikonov | Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking[END_REF]. Secondly, certain emerging devices inherently support nonvolatile data storage and computing, enabling low-energy memory access and backup/restore operations.

There have been quite a few promising beyond-CMOS emerging devices, such as single-electron devices [START_REF] Lu | A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors[END_REF], spin-transfer-torque devices [START_REF] Roy | Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives[END_REF], the tunnel field effect transistor (TFET) [START_REF] Seabaugh | Low-Voltage Tunnel Transistors for Beyond CMOS Logic[END_REF], negative capacitance FET (NCFET, aka ferroelectric FET or FeFET) [START_REF] Khan | Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation[END_REF]. This chapter introduces two types of them, including TFET and NCFET. As promising beyond-CMOS candidates, these devices could work at a lower supply voltage to enable further power reduction in Boolean computation (without higher static leakage than CMOS). Meanwhile, the substantially novel features that they exhibit could also be captured to enable new computing architectures supporting nonvolatile data storage and computing.

The remainder of this chapter proceeds as follows. Section 2 investigates the challenges in designing energy-efficient IoT systems. Section 3 introduces the three types of emerging technologies, with more emphasis on their electrical characteristics. Section 4 describes how to make use of these emerging devices to design more energy-efficient IoT systems beyond those in CMOS. Section 5 discusses future research directions and Section 6 discusses key conclusions.

IoT Systems and Efficiency Bottlenecks

This section presents a model of a general IoT system, describes the functionality of each block, and analyzes the bottlenecks in each block considering existing optimization efforts. Fig. 1. A general battery-less IoT system powered by ambient-energy harvesting [START_REF] Swaminathan | Steep slope devices: Enabling new architectural paradigms[END_REF] While there has been a relatively long history of using solar cells to power devices, recently published battery-less IoT system designs have been demonstrated with an increasingly wide range of power sources. Devices powered by harvested radiofrequency (RF) energy have been shown to be successful for applications including a glucose level sensor on a contact lens, a highway RFID pass, bio-signal sensors on animals or insects, etc. [START_REF] Li | Rf-powered systems using steep-slope devices[END_REF]. Their system functionality varies from a simpler signal recorder to a more complex in situ signal processor, such as one with EEG signal processing, and wireless transmission. The system feature size, operating range, performed tasks, circuit design and architecture implementation, should be optimized based on the amount of obtainable energy and other quality-of-service (QoS) requirements in the applications.

A General IoT System

The system structure varies with the specific application requirements. A general battery-less IoT system could be built as shown in Fig. 1 using ambient-energyharvesting techniques [2][9]. While some blocks, such as sensors and interface, memory storage, and a digital signal processor and accelerators, can be similar to conventional designs with a stable power supply, there are extra and significantly different blocks when the system is battery-less and powered by ambient energyharvesting techniques.

In addition to the external power sources, the energy-harvesting IoT system consists of two major blocks: the block of energy harvesting and management, and the block of signal processing and data transceiving. The energy harvester differs with the ambient energy source, and a wake-up receiver may be used in scenarios when an external triggering signal is used to switch the system between different power or operation modes. A temporary energy storage medium in the form of a capacitor is usually used to smooth the supply glitch and cover a temporary power income loss.

As will be further discussed later, the power supply and management module, and the digital signal processing architecture for an energy-harvesting IoT system can be significantly different from conventional designs with a stable power supply. In fact, the overall system performance greatly relies on how these different blocks are built. The next sub-section (Section 2.2) will discuss more details of each block.

Bottlenecks and Existing Efforts

Energy sources and energy harvesting techniques. Solar, RF, piezoelectric and thermal gradients have been widely used ambient energy sources [START_REF] Tsai | Low-power high-speed current mode logic using Tunnel-FETs[END_REF]. When the energy source does not directly provide the required DC voltage output, voltage converters and regulators are needed. For example, a rectifier is required to convert AC signals from an RF signal antenna and piezoelectric films. DC-DC converters can be used to convert the DC supply voltage to be higher or lower. Despite of the differences between these ambient power sources, there are three major challenges in energy harvesting and storage. The first challenge is the relatively low and varying energy density, intermittency, dependency of the efficiency on the load condition, and the unpredictability of these factors. Therefore, circuit optimizations such as tracking and adaptive operations [START_REF] Brito | Evaluation of the Main MPPT Techniques for Photovoltaic Applications[END_REF] are usually required to mitigate these effects which significantly increases the design complexity. The second challenge is the low power-conversion efficiency (PCE) because of the weak power from the ambient environment. Such a weak power results in low-voltage operation and thus a high resistive energy loss with conventional CMOS technology [11][12]. The third challenge is the leakage of the energy storage capacitors, which makes the approach of "short-time-computing, long-time-harvesting" less applicable in ultra-low input power scenarios.

Sensing, interface, and communication. While this can be similar to IoT systems with a stable supply, the increasing amount of data being transferred by the IoT devices, the relatively much lower energy budget, and the unpredictable power outages make the interface challenging. There is not yet a mature protocol to deal with frequent supply failures in IoT. Some techniques, such as passive communications (e.g. backscatter in [0]), are useful to reduce the power, but limited in the operation range, speed, and overall energy-efficiency when considering the power transmitter.

Digital signal processing. There are two main challenges in the design of digital signal processors. The first challenge, as introduced in Section I, is that the slowing down of voltage scaling has become challenging because of increased leakage power. The question of how to build reliable and energy-efficient digital processing circuits under a lower voltage has become a hot topic in device, circuit, and architecture research. The second challenge, which is a result caused by intermittent supply failure, is that the frequent backup-restore operations consume significant amounts of energy, limiting the overall forward computing progress. There has been some initial research on the optimization of nonvolatile processors (NVPs) recently, as will be discussed later, showing great potential to mitigate the impact of power intermittency [START_REF] Ma | Architecture exploration for ambient energy harvesting nonvolatile processors[END_REF][START_REF] Ma | Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications[END_REF][START_REF] Ma | Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power[END_REF]. Nevertheless, the study of signal processing algorithms, computing architectures for IoT systems is still insufficient for digital signal processing under an intermittent power supply.

Data storage. For IoT systems, especially in sensing applications, memory elements are needed to store data before they are processed and transferred. Future IoT data storage will be using more memory as the task complexity increases. While the required data storage volume varies with the application, the major challenge in data storage for energy-harvesting IoT systems is the energy efficiency in read and write access due to a low energy budget. This challenge is particularly critical for on-chip nonvolatile memory (NVM) designs, as recent research has revealed the advantage of integrated on-chip NVM to reduce access energy and delay [START_REF] Ma | Architecture exploration for ambient energy harvesting nonvolatile processors[END_REF][START_REF] Ma | Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications[END_REF][START_REF] Ma | Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power[END_REF][17] [START_REF] George | Nonvolatile memory design based on ferroelectric FETs[END_REF]. It is likely that the co-design of data storage and signal processing architecture will be critical for overall energy efficiency, especially for some applications where memory access is the bottleneck due to frequent backup and restore operations [START_REF] Chi | PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory[END_REF].

Other issues. Other challenges, such as security and privacy [START_REF] Roman | Securing the Internet of Things[END_REF], reliability, yield, etc., which are not covered by this chapter, will also be critical in future IoT systems.

Emerging Beyond-CMOS Devices

In this section, TFET and NCFET, as emerging beyond-CMOS devices, will be introduced and compared with conventional CMOS. At the device level, there are a few widely-used performance metrics to evaluate a device:

ON-state current (ION): drain current when the transistor is in the ON state. ION is usually measured with both the gate-source voltage (VGS) and the drain-source voltage (VDS) set to be equal to the supply voltage. A higher ION is equivalent to smaller on-state resistance, and is thus preferred for higher speed.

OFF-state current (IOFF): drain current when the transistor is in the OFF state. IOFF is usually measured with VGS equal to zero and VDS equal to the supply voltage. A lower IOFF indicates larger off-state resistance, and is preferred for lower leakage current.

Subthreshold swing (SS): the required voltage change at the transistor gate to change the drain-source current by a decade in the subthreshold region. In conventional CMOS FETs, SS is limited by the thermionic emission of carriers, and is higher than 60mV/decade at the room temperature. A transistor with a smaller SS, could be operating at a lower supply voltage, while providing the same ION and IOFF. This capability reduces overall power consumption by reducing the dynamic power (as the voltage is lower). A smaller SS in analog and RF circuits is also preferred, because it also leads to higher gmID for higher gain and current efficiency:

(1)

Steep-slope devices: in this chapter, it is used to represent devices with SS lower than 60mV/decade of conventional CMOS FETs at the room temperature.

TFET

TFET is essentially a gated p-i-n diode with reverse biasing and asymmetric doping [START_REF] Seabaugh | Low-Voltage Tunnel Transistors for Beyond CMOS Logic[END_REF]. There have been many types of reported TFET devices [START_REF] Seabaugh | Low-Voltage Tunnel Transistors for Beyond CMOS Logic[END_REF]. The double gate GaSb-InAs heterojunction TFET (HTFET) device has shown good balance between a steep slope and high ION, as shown in Fig. 2(a) [START_REF] Liu | Tunnel FET RF Rectifier Design for Energy Harvesting Applications[END_REF]. When the gate bias voltage is low, the drain source current is small. This is because the wide energy barrier suppresses the probability of band-to-band tunneling (BTBT), as shown in Fig. 2

(b).

When the gate voltage is increased, the tunneling barrier is narrowed. As a result, the quantum-mechanical BTBT phenomenon creates an abrupt transition between the ON and OFF states as shown in Fig. 2(c), achieving a low SS at the room temperature as shown in Fig. 2(d).

In addition to the steep-slope switching characteristic, HTFET also exhibits some unique features shown in Fig. 2(e-f) [START_REF] Li | Rf-powered systems using steep-slope devices[END_REF][11][12] [START_REF] Kim | Enabling Power-Efficient Designs with III-V Tunnel FETs[END_REF]. The first feature is the unidirectional tunneling that makes TFET conducting current almost drain-to-source only in a moderate voltage range. This originates from the asymmetric structure in HTFET. The second feature is the negative differential resistance (NDR), which appears in the negative VDS range. The third feature is about the device capacitance.

HTFET has less capacitance than Si FinFET in the low voltage region, and more capacitance in the high voltage region. Table I summarizes some recent TFET experimental results. Device models for TFET are available for circuit SPICE simulations [START_REF] Liu | Tunnel FET RF Rectifier Design for Energy Harvesting Applications[END_REF][12] [START_REF] Liu | Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition[END_REF][START_REF] Tsai | Low-power high-speed current mode logic using Tunnel-FETs[END_REF][START_REF] Kim | A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter[END_REF][START_REF] Kim | Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs[END_REF].

GaSb-InAs HTFET

NCFET

A negative differential capacitor was predicted in 2008 to be stacked at the gate insulator in a MOSFET. By doing this, a small voltage change at the gate could create a larger change in the insulator surface potential, leading to a steeper switching behavior in the IDS versus VGS curves of the transistor [START_REF] Salahuddin | Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices[END_REF]. Fig. 3(a-b) shows the conceptual device structure and the equivalent gate capacitance network. Recently, there have been advances in both fundamental and experimental results [START_REF] Hu | 0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF. 2015 73rd Annual Device Research Conference (DRC)[END_REF][START_REF] Lee | Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics[END_REF][START_REF] Jo | Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices[END_REF][START_REF] Khan | Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor[END_REF][START_REF] Jo | Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching[END_REF][START_REF] Li | Sub-60mV-swing negative-capacitance FinFET without hysteresis[END_REF][START_REF] Lee | Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm[END_REF].

Table I shows some recent NCFET results. Due to the challenge of integrating the ferroelectric layer, some early devices were shown with an external ferroelectric capacitor. Recent reported devices are capable of integrating the ferroelectric capacitor around a fin-structure gate.

Many ferroelectric materials, including PbTiO, BaTiO, Pb(ZrTi)O, HfZrO, etc., could exhibit negative capacitance [START_REF] Khan | Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor[END_REF]. The matching of the ferroelectric negative capacitance and the internal MOSFET gate capacitance is the key towards the performance of an NCFET. Thus, a proper capacitance tuning through ferroelectric material layer thickness and area is critical to the success of an NCFET process [START_REF] Khan | Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor[END_REF]. Fig. 4 shows how the ferroelectric layer thickness affects the switching slope and hysteresis [18][36]. As the ferroelectric layer thickness increases, SS reduces, and a hysteresis window gradually appears and then finally covers both positive and negative VGS range. These characteristics of hysteresis, a steep slope, and their dependence on the ferroelectric material, have been explored in digital logic and memory circuit design [START_REF] George | Nonvolatile memory design based on ferroelectric FETs[END_REF][34] [START_REF] George | Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors[END_REF]. This section shows how the IoT system bottlenecks could be mitigated by the opportunities enabled by these emerging devices.

Energy Harvesters and Sensors with Higher Efficiency

It is intuitive that, by increasing harvested energy from the same ambient environment, the number of performed tasks and functionalities could be increased in an energy-harvesting IoT system. Existing research results have shown that, by making use of the steep switching characteristics, energy harvesters based on these emerging devices could operate better than CMOS transistors in the low-voltage scenarios. Fig. 5(a) is a conventional cross-coupled RF rectifier. Fig. 5(b) is a conventional DC-DC charge pump. Fig. 5(c) is an enhanced TFET DC-DC charge pump topology [11][12]. The power conversion efficiency (PCE) comparisons in Fig. 6 shows how III-V heterojunction TFET (HTFET) based designs outperform those based on the Si FinFET technology.

There are a few factors that lead to the improvement of power conversion efficiency when using HTFETs. The first factor is lower resistive power loss. When the input voltage is low, the resistive power loss limits the overall power conversion efficiency, and the designs in HTFET have less resistive power loss, leading to significant benefits. The second factor is lower capacitive power loss during charge redistribution when the input voltage is low. A combination of these two factors leads to a better transistor sizing strategy for the trade-off between the resistive power loss and switching capacitive loss. The third factor is the uni-directional tunneling conduction which leads to lower reverse power loss in a form of leakage current from the output to the input. The uni-directional tunneling feature of HTFETs also enables a new circuit topology towards even higher efficiency. For example, in the enhanced HTFET DC-DC converter in Fig. 5, the gate control of the output p-type transistor is now controlled directly by the input clock signal, which enables doubled gate driving voltage and less resistive power loss.

By providing higher power conversion efficiency, HTFET significantly extends the IoT operating applications to lower energy-income scenarios. It is also noted that, from another aspect, an energy harvester itself could be treated as a sensor that senses the input power level. A higher PCE provided by HTFET also improves the sensing sensitivity, such as motion or vibration sensors and radiation sensors. Similar rectifier and DC-DC charge pump designs based on NCFET and PhaseFET, although there is no result reported, a higher PCE will not be a surprise.

Analog Processing and Communication

For analog processing and transceiver designs, the lowest achievable power consumption is determined by the trade-off between various specifications, including gain, speed and bandwidth, linearity and spectral performance (such as spuriousfree dynamic range or SFDR, signal-to-noise+distortion ratio or SNDR, input-referred noise), etc. Fig. 7 shows the evaluation results of TFET based designs, including A/D converter, sense amplifier and D/A converter. Fig. 7(a) evaluates a 6-bit 10-MS/s successive-approximate-register (SAR) A/D converter, and Fig. 7(b) shows how HTFET is capable of lowering the energy beyond the limit of CMOS [START_REF] Kim | A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter[END_REF]. Such a gain stems from higher current efficiency for both digital logic (lower dynamic power) and the comparator (higher gm/ID). Fig. 7(c-d) shows the performance evaluation of a low-noise bio-signal sense amplifier (LNA) [START_REF] Liu | Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition[END_REF]. Here HTFET based design also has a higher gain because of higher gm/ID. A higher gain also leads to the input referred noise reduction as by definition, the input referred noise is the output noise divided by the gain of the amplifier. Fig. 7(d-e) shows the performance evaluation of a current-steering D/A converter [START_REF] Kim | Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs[END_REF]. HTFET shows a higher SFDR because of less transistor capacitance at the low voltage region, which leads to less coupled switching glitches and higher output impedance. TFET based typical RF circuit designs were reviewed in [START_REF] Swaminathan | An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs[END_REF], including RF LNA, mixer, frequency doubler, oscillators, etc. Substantial benefits are observed using HTFET in low-voltage high-frequency circuits, with higher preferred nonlinearity for mixers, and higher transconductance and gain at low power and low current levels.

Input Power (dBm) (a)

Analog Input

Reference

Considering that the above designs are widely used as a front-end and back-end block in IoT systems, as shown in Fig. 1, significant power saving could be achieved by adopting HTFET.

Energy-Efficient Volatile Digital Logic

There have been evaluations between TFET and conventional CMOS technologies on digital circuits, including combinational gates and adders, sequential gates like D flip-flops, and SRAM. TFET based designs are shown to outperform conventional CMOS in energy-delay especially with a low supply voltage, as shown in Fig.

8 [38][39]. It is also noted that, when using TFET for pass-transistor logic, the device feature of uni-directional tunneling conduction affects the functionality and is handled with by either adding another parallel pass transistor for the other opposite direction conduction, or re-designing the circuit topology. As the technology scales down to smaller dimensions, the parasitics and contact non-idealities play a more important role. Recently, an evaluation work considering parasitics indicates that, similar performance advantage by HTFET is still observed even with higher contact resistance due to a vertical structure [START_REF] Kim | Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells[END_REF]. Another work on processor design and evaluation shows that, with less energy per instruction (EPI), TFET based designs extends the design space when considering the thermal limit and the degree of parallelism, leading to higher performance [START_REF] Swaminathan | An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs[END_REF].

Similarly, for NCFET, lower energy-delay has been observed for digital logic in low-voltage scenarios when operating with a moderate-to-high capacitive wire load, as shown in Fig. 9(a) [START_REF] George | Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors[END_REF]. The hysteresis in the positive VGS region as shown in Fig. 5(c) could significantly improve the input noise margin by an amount of the hysteresis window width [START_REF] George | NCFET Based Logic for Energy Harvesting Systems[END_REF]. The theory of this could be understood as follows.

Considering an NCFET inverter with n-type NCFET transistor and p-type conventional transistor, the n-type NCFET transistor will not turn on until the input voltage increases beyond the rising hysteresis edge, nor will it turn off until the input signal reduces beyond the falling hysteresis edge. This is illustrated in Fig. 9(c). The improved input noise margin of NCFET logic could also be used to build SRAM cells with enhanced noise margin, as shown in Fig. 9(d) [START_REF] George | NCFET Based Logic for Energy Harvesting Systems[END_REF].

Energy-Efficient Nonvolatile Logic and Memory Circuits

For IoT energy-harvesting applications where the power supply is intermittent, it is critical to sustain inter-process data during power outages. Therefore, on-chip nonvolatile memory (NVM) becomes intriguing because of its non-volatility to avoid refreshing and its immunity to power failures. The possibility of on-chip memory access instead of out-of-chip access also reduces the energy consumption. Meanwhile, power-gating is very useful to further reduce the static leakage power of idle digital circuits, and NVM could be used to store the state of these idle circuits while turning off their power supply.

Furthermore, with on-chip NVM and associated sensing and control, a nonvolatile processor (NVP) could be built to back up the processor states and data, including memory, D flip-flops (DFF), registers, etc., into this NVM during power failures [42][49-56]. Such on-chip data backup and restore operations reduce the risk of losing computation progress. When compared with out-of-chip nonvolatile backup options, this on-chip backup solution has lower power, energy and interface overhead. Such an advantage enables more computational progress in power-supplyintermittent scenarios [START_REF] Ma | Architecture exploration for ambient energy harvesting nonvolatile processors[END_REF], as illustrated in Fig. 11.

NVP with on-chip NVM backup

Volatile With the tunable hysteresis in NCFETs, energy-efficient nonvolatile memory could be built. Fig. 10(a) shows an NCFET NVM design based on an NCFET hysteresis tuned around VGS=0V (see Fig. 3(d)) [START_REF] George | Nonvolatile memory design based on ferroelectric FETs[END_REF]. It is reported that this NCFET NVM exhibits improved access energy-delay. Different from existing nonvolatile memory devices such as ReRAM and STT-RAM, the NCFET itself is also a transistor. This provides opportunities of logic-in-memory process.

Attaching an NCFET nonvolatile bit storage to a conventional volatile DFF, a nonvolatile DFF with external backup and reset controls could also be built, as illustrated in Fig. 10(c) [START_REF] George | NCFET Based Logic for Energy Harvesting Systems[END_REF]. With a local nonvolatile memory cell, the backup and restore energy becomes lower than that of the clustered nonvolatile memory backup solution in which long-distance data transmission is time and energy consuming.

More aggressively, by exploring the embedded logic and non-volatility in NCFET, an external-control-free intrinsically nonvolatile DFF is possible. Such an intrinsically NV-DFF could be built by replacing the slave latch of a conventional volatile CMOS master-slave DFF with one NCFET nonvolatile latch shown in Fig. 12.

Making the NV-DFF intrinsically nonvolatile enables the removal of external controls, and makes fine-grained backup/restore operations in NVP and power-gating applications possible with more energy savings.

With the synergy of the low-voltage NCFET logic [START_REF] George | Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors[END_REF], NCFET nonvolatile memory array [START_REF] George | Nonvolatile memory design based on ferroelectric FETs[END_REF], and the NCFET NV-DFF, an energy-efficient NVP is designed, as shown in Fig. 13(b), in comparison with a conventional NVP in Fig. 13(a). As both logic and memory are intrinsically nonvolatile, there is no need for backup and restore controls for the NCFET storage. The baseline design uses conventional CMOS transistors for logic, a clustered FeRAM array as data and instruction memory, and NV-DFF using ferroelectric capacitor for state backup under external control [START_REF] Kimura | A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability[END_REF]. Giving the harvested RF power from TV stations, as shown in the power profile sampled per 0.2S in Fig. 14, the average input power is 8.7 µW, with the peak up to ~45 µW and frequent power failures with power lower than nW. The simulations are carried out in various test cases in MiBench [START_REF] Guthaus | MiBench: A free, commercially representative embedded benchmark suite[END_REF]. Fig. 15 shows the simulation results for these testbenches. Fig. 16 shows the comparison of computation progress versus time. The computation progress gain ranges between 1.5x to 2.8x, which confirms the benefit of using NCFET for NVP design.

When only TFET is used to replace CMOS in NVP design, improvement of computation progress is also observed, as shown in Fig. 17 [START_REF] Ma | Nonvolatile Processor Optimization for Ambient Energy Harvesting Scenarios[END_REF]. The improvement comes from the energy savings by low-power digital logic and less number of backup/restore operations.

Nonvolatile Computing Architectures

In this new NVP design regime, most existing guidance of low-power design techniques are still useful, but there has also been significant difference in the design and optimization methodology.

The first different rule is that "design for low power does not guarantee more computing progress" [START_REF] Ma | Architecture exploration for ambient energy harvesting nonvolatile processors[END_REF]. This is because, in a battery-less energy-harvesting IoT system, there is no ideal temporary energy storage, and the harvested energy will be wasted in the form of overflowing or leaking if it is not used efficiently in time. In other words, the computing forward progress (CFP) indicated by the number of executed instructions (NI) could be expressed as a function of computation energy (CE) and energy-per-instruction (EPI):

CFP = CE / EPI, (2)
where CE is a fraction of the total harvested energy, considering the energy loss from backup/restore operations, leakage and overflow in the energy storage capacitor, and leakage in the circuits.

And the fact is that the lowest EPI does not guarantee the highest CE because of the abovementioned energy harvesting and storage non-idealities. For example, an outof-order processor may contribute to more forward progress than a non-pipelined processor in scenarios when the harvested power is higher. As a result, the power of the processor should adapt to the harvester and energy storage status to find the best trade-off between the lowest EPI and the most CE.

There are various approaches to configuring the processor so as to fit the input power trace. One approach is to dynamically switch between different processing cores which are all embedded on the same chip based on level of harvested power and the store energy [START_REF] Ma | Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile[END_REF]. The second approach is to dynamically scale the operating frequency and voltage (DVFS) accordingly [START_REF] Ma | Dynamic power and energy management for energy harvesting nonvolatile processor systems[END_REF] [START_REF] Ma | Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors[END_REF]. The third approach is to dynamically re-allocate computing and storage resources for the processor which turns out to be a different degree of parallelism [START_REF] Ma | Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors[END_REF].

In addition to the trade-off between CE and EPI, there are other optimizations that have significant impact on the overall forward progress.

The first consideration is "what" and "when" to back up the computing states. There are various reasons that make this consideration important. First of all, less amount of backup states needs less backup energy but needs more energy to recover and recompute; Secondly, a backup operation which is carried out too early may be a complete waste of energy and time as it may not be necessary at all, while a too-late backup may lead to backup failure and progress rolling-backup. Also, there can be a risk to take, on how much energy that could be harvested in the future -which could also be counted into a certain amount of usable energy.

The second consideration is how to understand the feature of the harvested energy, and how to predict its trend. An accurate prediction of the input power will certainly help system configuration for more forward progress. For some energy sources such as ambient RF energy, the harvested power varies radically and is challenging to predict. Meanwhile, for some other energy sources, such as motion and solar energy sources, the harvested power has a certain pattern and could be predicted. Machine learning techniques have been proposed to predict the future energy to assist dynamic system configuration for more forward progress [51][56].

The third consideration is on-chip NVM optimization. There are a few key factors that must be considered. One factor is what types of on-chip memory to use for backup operations. Different NVM devices, such as ReRAM, FeRAM, STT-RAM, and the emerging NCFET NVM, etc., have different energy-delay performance for read and write operations. Another factor is to use centered (aka clustered) or distributed memory. Distributed memory uses a local nearby NVM bit storage close to each DFF with a copy of access interface circuit. Clustered memory is implemented with arrays of memory and could be dense in area due to shared elements such as sense amplifiers but may consume more energy and delay in access due to longer interconnection lines and limited degree of access parallelism.

Future Work for IoT Using Emerging Devices

While emerging devices have shown great potential for future energy-efficient IoT applications, there is still a large gap between what has been experimentally demonstrated and a complete system implementation and application mapping. Significant efforts from all the levels of device, circuits, system and applications are required to speed up the progress [START_REF] Li | Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures[END_REF].

Device understanding, characterization, and integrated fabrication: Continuous optimization of material and process is required for large-scale integration. It is a key to build accurate models of emerging devices that support more aspects of devices features, such as matching, noise, endurance, parasitics, etc., for circuit and higher level simulations;

Circuit and architecture optimizations: It is unlikely for emerging device features to be used as a drop-in replacement for all conventional CMOS techniques. Innovative circuit topology re-design and optimization are sometimes a must to obtain the desired circuit functionality and performance, which also brings additional tradeoffs to carry out. Circuit and architecture optimizations to make the most use of pros and mitigate cons of emerging devices are necessary [13-15][47]. Meanwhile, device features deviating from conventional CMOS behavior may actually be very useful in some applications, highlighting the necessity of device-circuit-application co-design.

Higher-level considerations: Quality-of-service (QoS) and task scheduling optimization, with support from software design are also an area of key interest [START_REF] Zhang | Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes[END_REF][53] [START_REF] Wang | Storage-Less and Converter-Less Photovoltaic Energy Harvesting with Maximum Power Point Tracking for Internet of Things[END_REF]. Security, privacy, and communication protocols are core concerns in any IoT deployment. The study of the interaction of quality and security metrics with design and power efficiency optimizations requires further investigations from device to architecture to software ecosystem.

The exploration of emerging devices, circuits, and architectures should be a joint effort. It is impossible to dig into all emerging devices for all different types of applications. Efforts spent for emerging device modeling and benchmarking may not be meaningful if the device finally turns out to be far from satisfactory. Moreover, research on modeling and higher-level design needs strong support from device developing groups and continuous interactions with them are crucial to ensure that each is aware of the newest findings and phenomena understandings in the other's domain.

Conclusion

This chapter has discussed new opportunities in Internet-of-Things enabled by emerging devices, circuits and architectures through enhanced and new features to the implementations. The future work for IoT based on emerging technologies is also discussed.

Fig. 2 .

 2 Fig. 2. HTFET: (a) Structure of an N-type HTFET; (b-c) Energy diagrams; (d, e) IDS-VGS comparison; (f) Capacitance [2][11][12][21]

Fig. 3 .Fig. 4 .

 34 Fig. 3. NCFET: (a) Device structure; (b) Capacitance model[START_REF] George | Nonvolatile memory design based on ferroelectric FETs[END_REF]

Fig. 5 .

 5 Fig. 5. Rectifier and DC-DC charge pumps: (a) Rectifier; (b) Conventional DC-DC charge pump; (c) Enhanced DC-DC charge pump in III-V HTFET [11][12]

Fig. 6 .

 6 Fig.6. PCE of rectifier in (a) and DC-DC charge pump in (b)[11][12]

Fig. 7 .

 7 Fig. 7. Comparisons between HTFET and Si FinFET circuits: (a-b) a 6-bit SAR A/D converter and performance; (c-d) bio-signal sensing OTA gain and input referred noise versus frequency; (e-f) Current-steering D/A converter and its SFDR [22][24][25]

Fig. 8 .Fig. 9 .

 89 Fig. 8. TFET design examples: (a) a 32-b adder; (b-c) SRAM[38][39]

Fig. 10 .

 10 Fig. 10. NCFET circuits [18][34]. (a) Two-transistor (2T) nonvolatile memory array; (b) Nonvolatile NCFET D flip-flop.

Fig. 11 .

 11 Fig. 11. Comparisons of computation progress between volatile processor with off-chip NVM and nonvolatile processor with on-chip NVM.

Fig. 12 .

 12 Fig. 12. NCFET nonvolatile latches (NCFET transistors are drawn with thick gates).

Fig. 13 NVPFig. 15 Fig. 17 TFET

 131517 Fig. 13 NVP design using NCFET logic and memory

TABLE I .

 I RECENT ADVANCES IN TFET, NCFET, AND PTD-BASED PHASEFET

	4 New Opportunities Enabled by Emerging Devices, Circuits,
	and Architectures
			NCFET			TFET
	Source	[32] IEDM'15	[29] EDL'16	[30] EDL'16	[46] IEDM'14	[45] EDL'15	[44] VLSI'15
	Structure	HfZrO FinFET	P(VDF-TrFE)	BiFeO3, FinFET	Si FinFET	III-V ver-tical	III-V vertical
	ION (A/m)	-	100	1e-4 -1e-6	-	8.4	275 N; 30 P
	IOFF	-	~5pA/m	1e-12-1e-14	ION/3e4 N; ION/2e6 P;	0.1nA/m	0.8nA/m N; 0.3nA/m P
	SSmin (mV/dec)	55-87	45-52 (2-4 w/ hystere-sis)	8.5-11 P; 16-50 N	56 N; 58 P;	64 N	55 N; 115 P;
	Hysteresis Depends	no	yes	no	no	no

Acknowledgements. This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet centers, sponsored by MARCO and DARPA, by NSF awards 1160483 (ASSIST), and NSF Expeditions in Computing Award-1317560.


Valentino Peluso

Roberto G Rizzo

Andrea Calimera
email: andrea.calimera@polito.it

Enrico Macii

Massimo Alioto

Beyond Ideal DVFS through Ultra-Fine Grain Vdd-Hopping

DVFS is the de-facto standard for low energy Multi-Processor SoCs. It is based on the simple, yet efficient principle of lowering the supply voltage (Vdd) to the minimum threshold that satisfies the frequency constraint (f clk ) required by the actual workload. An ideal-DVFS deals with the availability of on-chip high resolution voltage regulators that can deliver the supply voltage with a fine step resolution, a design option that is too costly. While previous research focused on alternative solutions that can achieve, or at least get close to, the efficiency of ideal-DVFS while using a discrete set of supply voltages, this work introduces Ultra-Fine Grain Vdd-Hopping (FINE-VH), a practical methodology that brings DVFS beyond its theoretical limit. FINE-VH leverages the working principle of Vdd-Hopping applied withinthe-core by means of a layout-assisted, level-shifter free, dynamic dual-Vdd control strategy in which leakage currents are minimized through an optimal timing-driven poly-bias assignment procedure. We propose a dedicated back-end flow that guarantees design convergence with minimum area/delay overhead for a cutting-edge industrial Fully-Depleted SOI (FDSOI) CMOS technology at 28 nm. Experimental results demonstrate FINE-VH allows substantial power savings w.r.t. coarse-grain (i) ideal-DVFS, (ii) Vdd-Hopping, (iii) Vdd-Dithering, when applied on the design of a RISC-V architecture. A quantitative analysis provides an accurate assessment of both savings and overheads while exploring different design options and different voltage settings.

Introduction

It is well known that power consumption is the most stringent constraint for the growth of digital System-on-Chips (SoCs) [START_REF] Venkatachalam | Power reduction techniques for microprocessor systems[END_REF]. As an answer to this issue, the multi-core/many-core design paradigm was introduced as the only possible way out. Indeed, when high performance need to meet a low energy budget, the availability of multiple processing units that can be turned-ON/OFF, or just slowed Fig. 1. Comparison between ideal-DVFS and dual-Vdd strategies down depending on the actual workload, represents an efficient solution. Within this context, Dynamic Voltage Frequency Scaling (DVFS) has been proven to be the most effective technique to get close to minimum energy consumption. DVFS is based on a straightforward working principle, that is, reduce the supply voltage (Vdd) down to the minimum threshold that satisfies the frequency constraint (f clk ) imposed by the workload.

Originally applied to "monolithic" SoCs [START_REF] Nowka | A 32-bit powerpc system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling[END_REF], the degree of freedom made available by multi-processor SoCs (MP-SoCs) architectures enabled a more efficient core-based, i.e., fine-grained, DVFS implementation [START_REF] Kolpe | Enabling improved power management in multicore processors through clustered dvfs[END_REF]. With a fine-grain DVFS, each core can be set working at a different operating point in the [f clk , Vdd] space; this allows to run multiple tasks asynchronously and bring down the minimum-energy point of the whole SoC. An example of fine-grain DVFS on massively parallel platforms is given in [START_REF] Truong | A 167-processor computational platform in 65 nm cmos[END_REF], where 167 processors are orchestrated over a wide frequency range achieving minimum power consumptions, from 1.07GHz -47.5mW at 1.2V to 66MHz -608µW at 0.675V. As an add-on feature, fine-grain DVFS is a perfect knob to compensate and/or mitigate variations due to Process, Voltage and Temperature (PVT) fluctuations that affect different cores after fabrication and during the lifetime of the circuit [START_REF] Dighe | Withindie variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core teraflops processor[END_REF].

A practical use of DVFS on MP-SoCs deals with the availability of programmable on-chip Vdd regulators that can deliver the supply voltage with fine resolution step and fast swing (Fig. 1-a). Unfortunately, the use of integrated DC/DC converters is made impractical due to high implementation costs. Indeed, on-chip DC/DC converters fabricated with today's technologies may occupy a huge silicon area due to the low integration density of the components they contain, e.g., capacitors and inductors [START_REF] Truong | A 167-processor computational platform in 65 nm cmos[END_REF]. The picture gets even more com-plicated if one considers that each single core should be equipped with a dedicated converter.

The challenge faced by previous works is to achieve, or at least get close to, the efficiency of high-resolution DVFS, ideal-DVFS hereafter, with a discrete set of supply voltages. In their more general embodiment, discrete DVFS strategies use two Vdd levels (VddL and VddH) generated off-chip through external voltage regulators and evenly distributed across the die (Fig. 1-b). The absolute values of VddL and VddH are shifted up/down depending on the workload, while each core is fed with the proper Vdd by means of dedicated power switches (PS). Even though this design option offers a practical solution with low impact on area and power, it comes with a speed penalty due to high voltage swing latency of the external voltage regulators [START_REF] Park | Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors[END_REF]. Nevertheless, this is an acceptable cost as the voltage scaling process typically applies at low rate.

The two most representative cases of discrete DVFS are the Vdd-Hopping [START_REF] Miermont | A power supply selector for energyand area-efficient local dynamic voltage scaling[END_REF] and the Vdd-Dithering [START_REF] Beigné | An asynchronous power aware and adaptive noc based circuit[END_REF]. The Vdd-Hopping is a basic scheme in which the supply voltage range is split into a discrete set of values, two ore more depending on the external voltage regulator; the proper Vdd is selected among the available values such that the frequency constraint is met. The Vdd-Dithering scheme is a more elaborated, yet precise scheme that implements a Vdd time-sharing strategy. Differently from Vdd-Hopping, the Vdd is made switching from low (VddL) to high (VddH), leading the core to an average frequency equals to the frequency constraint. As it will be shown later in the text, the power-frequency tradeoff obtained through Vdd-Dithering can be seen as a linear approximation of ideal-DVFS.

While the aforementioned techniques aim at pushing power consumption close to ideal-DVFS, this work proposes a solution that goes beyond that theoretical limit. Recalling the practical implementation described in [START_REF] Peluso | Ultra-fine grain vdd-hopping for energy-efficient multi-processor socs[END_REF], in this work we give a comprehensive parametric analysis of the main advantages brought by a Vdd-Hopping scheme applied at a ultra-fine granularity, i.e., within-the-core. Such a solution, called FINE-VH, represents a viable solution to achieve power consumption below ideal-DVFS by using a dual-Vdd scheme.

The implementation of a FINE-VH solution is not trivial nor even straightforward, especially when the goal is to devise a computer-aided design methodology and not a handcrafted design. Working with multiple voltages within the same functional block raises several concerns during the place&route stages, e.g., area overhead and timing closure due to layout fragmentation and standard cell displacement. Moreover, static power consumption increases due to leakage currents of logic gates driven by portions of the circuit powered at different Vdd. Considering a simple chain of two inverters, when the driven inverter is supplied at nominal Vdd, its static power increases up to 5.2x if the driver is powered at 90%Vdd, 22.1x at 80%Vdd. Notice that the use of voltage-level shifters is strictly forbidden at this level of granularity, as it would imply huge design overheads.

As an answer to these needs, we introduce a fully-integrated design flow that guarantees timing/power convergence through incremental re-synthesis stages.

In particular, an optimal poly-bias assignment strategy is used to reduce intradomain leakage power at zero area/delay penalties.

The core used as benchmark is the RI5CY, a RISC-V instruction set architecture embedded in the ultra-low power multi-processor platform PULP [START_REF] Rossi | A 60 gops/w, 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology[END_REF]. The RI5CY core has been mapped onto a cutting-edge Fully-Depleted SOI (FDSOI) technology at 28 nm. We give an accurate design space exploration which quantifies different figures of merit, like power, area and delay, at different granularity, i.e., using a layout partitioned into 9, 25 and 49 tiles, and different voltage set, i.e., multiple values of ∆Vdd=VddH-VddL . As will be shown later in the experimental section, FINE-VH gives substantial power savings w.r.t. state-of-the-art DVFS solutions: ideal-DVFS, Vdd-Hopping and Vdd-Dithering.

Previous Works

Approaching Ideal-DVFS

The need to get close to an ideal-DVFS implementation may suggest the use of programmable on-chip DC/DC converters that guarantee a fine Vdd regulation. Unfortunately this design option would imply large overheads, both in terms of area and power. As alternative solutions, Vdd-Hopping [START_REF] Miermont | A power supply selector for energyand area-efficient local dynamic voltage scaling[END_REF] and Vdd-Dithering [START_REF] Beigné | An asynchronous power aware and adaptive noc based circuit[END_REF] are a preferred option as they enable a good approximation of ideal-DVFS at reasonable implementation costs.

-Vdd-Hopping: differently from ideal-DVFS (dashed line in Fig. 2) where the supply voltage can be adjusted with a very high resolution, this method employs a discrete set of supply voltages to control the local Vdd of a functional core. Fig. 2-a gives a pictorial description of this principle. The whole supply voltage range is split into a specific set of intervals, three in the plots of Fig. 2; at a run-time, the proper supply voltage is selected in order to meet the target frequency (f clk ) imposed at the application level. Once f clk is identified, the core is supplied by the Vdd at the right edge of the interval in which f clk falls (Vdd 2 in Fig. 2-a). Within each interval, the Vdd is kept constant and the power consumptions decrease linearly with f clk . When f clk crosses a new interval, power scales accordingly with the new Vdd. Obviously, the power consumption obtained with Vdd-Hopping drifts from ideal-DVFS as f clk approaches the left side of each interval. -Vdd-Dithering: this scheme, graphically described in Fig. 2-b, implements a Vdd time-sharing scheme. Differently from Vdd-Hopping, the Vdd switches from low to high, i.e., from the left edge to the right edge of the reference interval (Vdd 1 and Vdd 2 in the example of Fig. 2-b). Given T high as the time spent at high Vdd, hence high frequency f high , and T low as the time spent at low Vdd, hence low frequency f low , the core operates at an average frequency (f avg ) which is proportional to the "switching ratio": Fixing the proper ratio between T high and T low allows the core to operate at an average frequency centered on the target frequency f clk . Apart from some overhead introduced by the non-ideality of power switches, experimental results in [START_REF] Beigné | An asynchronous power aware and adaptive noc based circuit[END_REF] have shown physical implementations of Vdd-Dithering well fit the trend line depicted in Fig. 2-b.

f avg ∝ (f low • T low ) + (f high • T high ) T low + T high . (1)

Within the core power management

The target of this work is to bring the Vdd-Hopping concept at a lower level of granularity, i.e., within the core. The basic concept behind this idea is not new as it follows the natural scaling other power-management strategies experienced in the last years, e.g., Multi-Vdd, Body-Biasing, Power-Gating [START_REF] Bolzani | Enabling concurrent clock and power gating in an industrial design flow[END_REF][START_REF] Calimera | Power-gating for leakage control and beyond[END_REF][START_REF] Tenace | Rowbased body-bias assignment for dynamic thermal clock-skew compensation[END_REF]. The taxonomy tree shown in Fig. 3 gives a compact classification of the many granularity options.

The low-power techniques were originally applied at the architectural level where the grain was a single functional block (Fig. 3-a). Examples of this functionalbased strategy are given in [START_REF] Liang | Revival: A variation-tolerant architecture using voltage interpolation and variable latency[END_REF][START_REF] Gupta | Tribeca: Design for pvt variations with local recovery and fine-grained adaptation[END_REF], where the power domains are defined as the boundaries of the micro-architectural units of a microprocessor. In [START_REF] Liang | Revival: A variation-tolerant architecture using voltage interpolation and variable latency[END_REF] authors introduce a voltage interpolation scheme inspired by Vdd-Dithering where the pipeline stages are dynamically fed by VddH and VddL in a time-shared manner; combined with a variable latency mechanism, this technique offers a viable solution to compensate process-variations while achieving minimum energy consumption. As an extension, the authors of [START_REF] Gupta | Tribeca: Design for pvt variations with local recovery and fine-grained adaptation[END_REF] improve the voltage interpolation mechanism by means of a dynamic local error detection&correction scheme for protection against timing violations.

While playing with functional blocks is an intuitive solution, the amount of power savings is limited by the coarse granularity at which the low-power knobs operate. It is well known that all the low-power techniques exploit a natural characteristic of digital circuits, that is, idleness; when a functional block is not used, or it can operate at a lower speed, its power can be reduced without affecting performance. This implies the identification of idle functional blocks and active ones. However, also within each single block large portion of the die are taken by non-critical components (e.g., standard cells belonging to fast logic paths) over which low-power knobs could effectively operate without inducing any performance penalty. Following this path, low-power techniques underwent a development process that brought them to work at a finer granularity, i.e., within-the-block.

R = Layout Row V DD1 (V BS1 ) V DD2 (V BS2 ) (b)
Unfortunately, working at a finer granularity is not a free lunch as strict rules imposed by semi-custom row-based layouts might prevent the physical implementation. This imposes a higher level of awareness of the layout constraints and it forces hard constraints on the geometrical size of the minimum grain. The most common layout-driven solutions are row-based and tile-based.

As shown in Fig. 3-b, in row-based strategies the atomic element is a single layout row. In [START_REF] Kakoee | Fine-grained power and body-bias control for nearthreshold deep sub-micron cmos circuits[END_REF], authors describe a row-based dual-Vdd technique for PV compensation. The core of this technique is a timing-driven clustering procedure where timing critical rows are assigned to high Vdd and the remaining rows to low Vdd. A customized placement algorithm groups critical cells on adjacent rows such that leakage currents at the row interfaces are minimized. The main limitation of this work is that Vdd assignment is done at design time, i.e., statically. Within the same category, [START_REF] Nakamura | 1/5 power reduction by global optimization based on fine-grained body biasing[END_REF] introduces a row-based scheme for ultra-fine grain body-biasing. Differently from [START_REF] Kakoee | Fine-grained power and body-bias control for nearthreshold deep sub-micron cmos circuits[END_REF], the layout is partitioned into equally sized bunches of rows. Such a structure is more flexible as it enables dynamic body-biasing scheduling for post-silicon process variation compensation.

In tile-based strategies, the atomic element consists of a regular section of the layout; Fig. 3-c reports a scheme where the layout of a logic circuit is arranged in 5x5 square mesh. Within this category, the most representative example is given in [START_REF] Muramatsu | 12% power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains[END_REF] where a PV-aware adaptive dual-Vdd strategy is applied on a DES core partitioned into 42 square tiles. The measurements obtained on a silicon testchip demonstrate power savings are limited to 12% (w.r.t. monolithic DVFS) due to static power overheads induced by intra-tile leakage currents. The same tile-based architecture is adopted in [START_REF] Yasufuku | 24% power reduction by post-fabrication dual supply voltage control of 64 voltage domains in vddmin limited ultra low voltage logic circuits[END_REF], yet with a different goal; it assigns a high Vdd to those tiles containing standard cells whose electrical behavior requires a minimum operating voltage (Vdd min ) larger than the majority of the other cells. This allows fault-free, low power operation even if the overall circuit is powered at Vdd< Vdd min .

3 Implementing FINE-VH

Design and Optimization

As highlighted in the introduction, the main contribution of this work is the implementation of a novel design strategy, FINE-VH, that reshapes the Vdd-Hopping principle at a ultra-fine granularity. For this purpose, we devised a computer-aided design methodology that implements FINE-VH strategy by means of ultra-fine dual-Vdd. Working with multiple voltages within the same functional unit raises several concerns during the place&route stages, e.g., area overhead and timing closure, due to layout fragmentation and standard cell displacement. Moreover, static power consumption increases due to leakage currents of logic gates driven by parts of the circuit powered at different Vdd.

This section firstly introduces the layout organization and the physical design stages that implement the FINE-VH; secondly it describes an optimal poly-bias assignment technique that compensates the intra-tile leakage at no delay penalty; finally it proposes a Simulation/Emulation procedure for optimal Vdd selection.

Physical Design

The proposed FINE-VH strategy resorts to a tile-based structured layout, abstract view given in Fig. 4. The core is regularly partitioned into NxN square tiles (N =3 in Fig. 4), each of them provided with dual-Vdd, i.e., low-Vdd (VddL) and high-Vdd (VddH), taken from around-the-core power-rings. The two power supply voltages are provided by external DC/DC converters and their value is fixed at the application level depending on the target frequency (referring to the example of Fig. 2, VddL=Vdd 1 and VddH=Vdd 2 ). Upper-metal horizontal/vertical stripes run over the core area forming five power-grids: VddH, VddL, Gnd, Vbn (n-bias), Vbp (p-bias). Notice that this scheme is compatible with adaptive back-biasing strategies (out of the scope of this work).

The layout rows are tied to the power-grids through p-type header power switches enclosed into dedicated cells, the Vdd-MUX cells. The power-management unit is in charge of driving those Vdd-MUXes by loading the Vdd configuration It is worth noticing that the layout partitioning follows a "no-look" style, that is, once the grain size is defined through the parameter N , the tile partitioning is done at the floorplanning stage without considering how and where the subfunctional blocks of the core will be placed. On the one hand, this might seem an overhead as functional blocks are split across multiple tiles. However, that's what allows commercial place&route tools digesting the ultra-fine granularity so as to achieve (i) a regular power planning and (ii) faster timing closure.

From a practical viewpoint, the FINE-VH flow encompasses six different stages fully integrated into a commercial design platform by Synopsys R by mean of dedicated TCL procedures:

1. Synthesis: logic synthesis using technology libraries characterized at the maximum Vdd, e.g., 1.0V for our 28 nm technology. 2. Floorplanning: estimation of the core area and creation of an empty layout; the latter is then automatically partitioned into NxN regular tiles using placement blockages. 3. PG-Synthesis: power-grids are synthesized following a regular mesh over the partitioned layout. 4. Placement: the Vdd-MUXes are placed at the boundaries of the tiles while standard cells are placed within the tiles so that timing constraints are satisfied.

VddL VddH

'0' '1' 5. Post-Placement leakage optimization: a re-synthesis stage performing optimal poly-bias assignment for those cells at the interface of the tiles (additional details in the next subsection). 6. Routing: a standard timing-driven routing for logic signals.

V g = VddL V s = VddH I leak ∝ e |Vg -Vs -Vth| VddL VddH '0' '1' V g = VddL V s = VddH PB VddL VddL -V tp V tn VddH VddH -V tp V tn Gnd VddL VddL -V tp V tn VddH VddH -V tp V tn Gnd V tn ⇑ V tp ⇑ { (b) (a)
Poly-Bias optimization In a FINE-VH design, static power consumption may increase due to larger leakage currents in the "interface-cells", i.e., cells driven by signals coming from other tiles. When an interface-cell is fed with an input signal having a voltage lower than its Vdd, its internal pull-up network is partially turned-ON and leakage currents increase. This scenario is depicted in Fig. 5-a.

This over-consumption effect can be mitigated increasing the p-MOS threshold voltage (V th ) of the interface-cells; the latter is typically done either through gate length modulation [START_REF] Saha | Row-based dual vdd assignment, for a level converter free csa design and its near-threshold operation[END_REF] or using high-V th transistors [START_REF] Diril | Level-shifter free design of low power dual supply voltage cmos circuits using dual threshold voltages[END_REF]. The FDSOI CMOS process, target of this work, is provided with multi-V th libraries obtained through the former technique, i.e., gate length modulation, also called poly-biasing (PB) and represented in Fig. 5-b. For each logic gate, four different versions are available: PB0 (the standard V th ), PB4, PB10 and PB16 (the highest V th ).

Since the Vdd assignment process is done at run-time, foreseeing those cells affected by intra-tile leakage is not feasible. At the same time, a conservative approach where all the interface-cells are swapped to high-V th would imply excessive delay overhead. As a compromise we introduce a timing-driven postplacement optimal poly-bias assignment which works as illustrated in Fig. 6. Starting from a placed netlist of standard V th cells, i.e., PB0, the interface-cells are first identified (a) and then virtually isolated in a separated netlist with back-annotated delay information (b). Using the optimization engine embedded into the physical synthesizer, a timing-driven multi-PB assignment is run (c). The netlist returned by the multi-PB assignment step has the minimum leakage configuration, i.e., the largest set of high-V th cells, that satisfies the delay Step (c) is where the actual leakage optimization takes places. Since the goal is zero-delay penalty, only those interface cells crossed by timing paths with a timing slack greater than a certain threshold are taken into consideration. Moreover, in order to maximize the usage of cells with the highest V th (PB16), we resorted to splitting the procedure into three incremental PB-assignment substages; at each substage, only a given class of PB cells is considered: at the first stage PB16, at the second stage PB10, at the third stage PB4. This procedure allows to eat the available slack first by PB16 cells (which guarantee the highest protection from intra-tile leakage), then by the PB10 cells, and finally by the PB4 cells (for which intra-tile leakage compensation is minimal).

The slack threshold used for the selection of the interface cells (i.e., those considered during PB assignment) may change depending on the actual substage, namely, depending on the class of PB cells. For instance, at the first substage (PB16 assignment), a larger slack threshold is needed as a replacement to PB16 would introduce a large delay penalty; at the third substage (PB4 assignment), the slack threshold can be relaxed. To this aim, a simple rule is followed. We first define a slow-down factor α sd for each class of PB cells; this parameter is empirically extracted from the plot of Fig. 7 which reports the delay overhead introduced by poly-biasing: 2.82x for PB4, 8.72x for PB10, 19.88x for PB16. Then, depending on the current substage, the slack-threshold S th is defined by (2):

where d avg represents the average delay of a cell belonging to the critical path, and α sd the slow-down factor reported in Fig. 7. This enables a slack threshold that is proportional to the type of PB used at each substage.

As final remark, it is important to note that the implemented multi-stage resynthesis is suited not only for the 28 nm FDSOI technology as it can be easily extended to all those technologies that offer multi-V th libraries.

Simulation and Emulation

Commercial CAD tools lack static-analysis engines that can process level-shifter free multi-Vdd designs. Moreover, since FINE-VH does apply at run-time, the Vdd-selection policy implemented by the power-management unit needs to be emulated at design-time. For what concerns the first point, we opted for a static approach that uses off-line characterizations, while regarding the second issue, we implemented a simple, yet effective timing-driven Vdd-assignment.

Intra-Tile Leakage Power Estimation. The key issue of static-analysis of multi-Vdd designs is to estimate the intra-tile leakage power avoiding heavy SPICE simulations of the whole core. We used a static methodology that adopts off-line characterizations. For each logic gate we compiled a look-up table containing the leakage power derating factors for all possible input patterns and all possible VddL/VddH voltage configurations. As for standard timing libraries, the LUTs are obtained under different operating conditions. Having those LUTs, the static power of a single cell is estimated using the same model implemented into commercial tools: where n is the number of input pins (the number of pins, for sequential cells), P i is the input pattern probability, L i is the nominal static power extracted from standard timing libraries, and k i is a derating factor picked from the LUT. Notice that k i =1 if the driver cell is placed in a tile having the same Vdd of the logic cell under analysis.

P leak = 2 n i=1 P i • L i • k i (3)
Vdd assignment. In order to emulate at design-time the Vdd-selection strategy we implemented a timing-driven Vdd-assignment whose pseudo-code is given in Algorithm 1. The algorithm applies a cell-based procedure during which tiles are sorted in terms of their timing criticality, that is, the tile containing the largest number of timing critical cells are assigned to VddH first. The procedure returns when all the cells show a positive slack.

The procedure starts by assigning all the tiles to VddL (line 1). For each tile a criticality score is initialized to zero (line 3). Once the most critical path is extracted, all the cells belonging to that path are stored in a dedicated list called Cell List (line 4). For each cell in Cell List, the propagation delay is extracted and added to the criticality score of the tile hosting the current cell (lines 5 to 8). Once all the cells in Cell List have been processed, those tiles that are still at VddL are sorted according to their score (line 10, 11). The tile with the highest score (line 12) is assigned to VddH (line 13). The procedure is run until the core presents a positive path slack, that is, when the required f clk is met (line 2).

Simulation Results

The RI5CY Benchmark

With no lack of generality, we validated the proposed FINE-VH flow on the RI5CY core, an open-source RISC-V instruction set architecture [START_REF]Pulp: An open parallel ultra-low-power processing-platform[END_REF] used in the low-power parallel-processing platform PULP [START_REF] Rossi | A 60 gops/w, 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology[END_REF]. The core consists of the following units: prefetch buffer, instruction decoder, a 31x32 bit register file, integer ALU, single-cycle 32x32 integer multiplier, a control status register, hardware loop unit, debug unit, load and store unit. Figure 8 shows a layout of the die after tile partitioning.

Experimental Set-Up

Static Timing and Power analysis are performed with the STA tool by Synopsys (PrimeTime). We used technology libraries provided by the silicon vendor characterized for Vdd ranging from V to 1.00 V (step of 50 mV) and worst-case corner (SS and 125 • C).

The four DVFS schemes used for the comparison have been set as follows.

-Ideal-DVFS: for each Vdd, the maximum frequency is extracted and set as the working frequency. The Vdd ranges from 0.60 V up to 1.00 V with a step of 25 mV, resulting in eight (f , Vdd) operating points; for those Vdd not available in the library set, we used a cross-library scaling feature embedded into the STA tool.

-Vdd-Hopping: the Vdd range [0.60 V-1.00 V] is split into a finite set of intervals having a fixed width: ∆Vdd=200 mV and ∆Vdd=100 mV; the resulting Vdd values are 0.60 V, 0.80 V, 1.00 V and 0.60 0.70 V, 0.80 V, 0.90 V, 1.00 V respectively. The Vdd is chosen depending on the target frequency (please refer to Fig. 2). -Vdd-Dithering: same Vdd ranges/intervals of the Vdd-Hopping scheme, but power consumption is a liner interpolation of points obtained through ideal-DVFS (please refer to Fig. 2). -FINE-VH: the technique proposed in this work. As for the previous schemes, the Vdd ranges is [0.60 V-1.00 V]; two ∆Vdd options are explored, i.e., 200 mV (Vdd range split into two intervals) and 100 mV (Vdd range split into four intervals).

For all the above design strategies the average power is extracted considering realistic switching activities of the primary inputs, i.e., annotating static probabilities and toggle rates extracted from functional simulations.

Results

Table 1 collects some key figures of the RI5CY core after FINE-VH is applied at different levels of granularity (#Tiles=1 implies no FINE-VH). Both the core area and the number of layout rows increase with granularity due to wrapper insertion around the tiles. Such a void space is used for de-cap cells insertion and intensive routing. The area overhead ranges from 2.42% for 9 tiles to 5.95% for 49 tiles. The most interesting note is that the active cell area and the nominal delay@1.00V (i.e., delay on the longest path when all the tiles are supplied at 1.00V) keep almost constant; this proves the convergence of the design flow, even at 49 tiles. As one can observe, the percentage of interface cells increases with the number of tiles, and so do the intra-tile interconnections. However, as will be shown later in the text, the intra-tile leakage overhead is controlled using the proposed poly-biasing optimization. Concerning the V th distribution, Fig. 9 shows that the PB assignment strategy makes extensive use of cells at the highest V th (PB16), above 57% in all the three configurations. This highlights how the leakage optimization engine Figure 10 shows the power vs. frequency tradeoff curves for a 49-tile FINE-VH configuration and the three state-of-the-art DVFS schemes. Numbers are normalized w.r.t. an ideal-DVFS implementation (dashed line in the plot) supplied at minimum Vdd. As expected, Vdd-Hopping and Vdd-Dithering do approximate the behavior of ideal-DVFS, even though in a different way. Within each Vdd interval the Vdd-Hopping gets worse at lower frequencies, while Vdd-Dithering always runs close to ideal-DVFS. FINE-VH outperforms the competitors for all the operating points, both for ∆Vdd=200 mV and ∆Vdd=100 mV. When ∆Vdd = 200 mV, average power reductions of 43.5% and 27.5% are obtained with respect to Vdd-Hopping and Vdd-Dithering respectively. Moreover, FINE-VH goes quite below ideal-DVFS achieving a 23.4% of power savings. The benefits of the proposed technique are even more empathized at ∆Vdd=100 mV, where the average power consumption is reduced to 35.3% w.r.t Vdd-Dithering and to 34.6% w.r.t. ideal-DVFS.

The power savings for each operating point are detailed through Fig. 11 (the plot does not show savings w.r.t. Vdd-Dithering as they are close to ideal-DVFS). For ∆Vdd=200 mV savings range from 8.5% to 30.6% w.r.t. ideal-DVFS and from 30.0% to 61.0% w.r.t. Vdd-Hopping. For ∆Vdd= 100 mV power savings range from 32.0% to 38.2% w.r.t. ideal-DVFS and from 33.6% to 49.7% w.r.t. Vdd-Hopping. When considering a direct comparison to Vdd-Hopping, larger savings are achieved at lower operating frequencies (left side of each Vdd interval), where a finer granularity allows to supply more portions of the layout at the low voltage. Vdd-Hopping, instead, forces the core running at a Vdd that is quite far from the optimal one. Working with ∆Vdd=100 mV brings larger average savings (w.r.t. ideal-DVFS) for two main reasons: (i) a finer voltage granularity allows a better selection of tiles that can be set at VddL, hence, it helps to get closer the global optimal; (ii) a smaller ∆Vdd guarantees better noise margins while mitigating the effects of intra-tile leakage. This would suggest that a smaller ∆Vdd is a better design option. That's true as long as power/delay overheads of external voltage regulators are neglected. Indeed, when the target frequency imposed at the application level is shifted outside the reference interval, VddL and VddH need to be set to different values (please refer to Fig. 2); this implies some extra power overheads and additional latencies due to off-chip DC/DC converters. Intuitively, a lower number of intervals, i.e., a larger ∆Vdd, may allow to cover Figure 12 shows the percentage of the cell area supplied at low Vdd when FINE-VH is applied at different granularity, i.e., 9, 25 and 49 tiles. The plot clearly shows that 49 tiles give the best savings. For both the two ∆Vdd options, working at higher frequencies decreases the amount of silicon area powered at low Vdd. For instance, at the maximum frequency, f clk = 2.59, with 9 tiles, the percentage of area at low Vdd drastically reduces to zero for ∆Vdd=200 mV, and to 2.4% for ∆Vdd=100 mV. A lower granularity implies larger tiles that, most probably, will contain at least one timing critical logic path that forces the selection of a high Vdd. This issue is progressively mitigated as the granularity gets finer. As one can observe, at the maximum frequency f clk = 2.59, with ∆Vdd=200 mV, the percentage of area powered at low Vdd increases to 11.3% at 25 tiles and 25.4% at 49 tiles. Savings are even larger when ∆Vdd=100 mV, 36.2% at 25 tiles and 58.7% for 49 tiles. The advantage of a finer granularity can be better appreciated considering the average over the whole frequency spectrum: for ∆Vdd=200 mV, the average percentage increases to 38.5% (9 tiles), 52.0% (25 tiles), 58.9% (49 tiles); for ∆Vdd=100 mV, the average percentage increases to 54.0% (9 tile), 60.7% (25 tiles), 69.2% (49 tiles). This confirms once again the rule of thumb: "the finer, the better".

Figure 13 shows the power savings (w.r.t. ideal-DVFS) achieved with the proposed PB optimization. For ∆Vdd=200 mV, do not using poly-biasing nullifies all the savings brought by FINE-VH, i.e., negative savings. On the contrary, the PB assignment helps recovering the overheads due to a level-shifter free strategy as multi-V th cells substantially reduce the intra-tile leakage and are intrinsically less leaky. Our PB strategy achieves average savings of 23.4%. For ∆Vdd=100 mV, though the overhead imposed by intra-tile leakage currents is smaller, our PB optimization allows larger savings, 34.6% (PB) against 10.8% (no PB), without any performance penalty. As additional piece of information, Fig. 14 reports the Vdd configuration obtained by running Algorithm 1 for the case ∆Vdd=100 mV. The plot shows the Vdd assignment for each tile and each operating frequency; for the sake of space we only show the 25 tiles configuration. When the frequency increases, the number of tiles supplied at low Vdd decreases. However, some tiles, like the #4 and the #5, are more critical than others as they are constantly fed by VddH; other tiles are less critical, like tile #3, #6, #16, and, even at higher frequencies, they still keep running at low Vdd. The most critical functional blocks are the arithmetic units, for which at least one tile is always supplied at high Vdd. The proof that the Vdd-assignment algorithm detects the most timing-critical tiles can be inferred by observing the regularity of the Vdd distribution within each individual voltage interval: once a critical tile is assigned to VddH it never swaps to VddL. This holds for tile #7, #8, #9, #10, #12.

Conclusions and Final Remarks

Ultra-Fine Grain Vdd-Hopping (FINE-VH) improves the efficiency of DVFS schemes in MP-SoCs. We implemented a fully automated layout-assisted, levelshifter free flow which enables tile-based Vdd-Hopping at ultra-fine granularity with minimum design overheads. The proposed technique includes a timingdriven incremental re-synthesis stage for optimal poly-biasing assignment addressing intra-tile leakage waste. The FINE-VH strategy was experimented on a RISC-V core for MP-SoC applications mapped onto a commercial 28 nm FD-SOI technology. In order to measure the benefits of the proposed technique, we devised an experimental framework capable of emulating the Vdd assignment at target clock frequency and estimating the intra-tile leakage power.

Experimental results shows that FINE-VH outperforms state-of-the-art dual-Vdd schemes and, most importantly, it goes beyond the theoretical limit imposed by ideal-DVFS. Indeed, when FINE-VH is compared with ideal-DVFS, average power savings range from 23.4% for ∆Vdd=200 mV up to 34.6% for ∆Vdd=100 mV.

An accurate parametric analysis clearly stated finer layout granularity enhances FINE-VH power efficiency; average layout area at low Vdd increases from 38.5% for 9 tiles, up to 58.9% for 49 tiles (when ∆Vdd =200 mV). Once again the rule of thumb "the finer, the better" is confirmed. Our quantitative analysis suggests FINE-VH can work for a wide range of ∆Vdd values, from 100 mV (10%Vdd) up to 200 mV (20%Vdd). This represents an important degree of freedom as a proper selection of ∆Vdd may depend on the characteristics of the off-chip voltage regulators and the actual design specifications.

Fig. 2 .

 2 Fig. 2. Frequency-Power tradeoff of existing DVFS strategies

Fig. 3 .

 3 Fig. 3. Taxonomy of low-power knobs granularity. From coarse-grained architectural level (a), up to finer granularity as row-based (b) and tile-based (c) layout organization

Fig. 4 .

 4 Fig. 4. Layout partitioning and tile organization bit-stream into a dedicated flip-flop chain. The Vdd-MUXes are uniformly distributed within each tile following a row-based insertion scheme [20, 21]. The power-grids are aligned with the Vdd-MUX columns, hence, VddL and VddH area easily brought to the Vdd-MUX cells using vertical vias.Tiles are isolated each other by a void-space wrapper that creates discontinuity in the lower-metal power rails. That's mandatory as adjacent tiles might have a different Vdd. The wrapper width is defined by the minimum metal-to-metal distance for the technology in use.It is worth noticing that the layout partitioning follows a "no-look" style, that is, once the grain size is defined through the parameter N , the tile partitioning is done at the floorplanning stage without considering how and where the subfunctional blocks of the core will be placed. On the one hand, this might seem an overhead as functional blocks are split across multiple tiles. However, that's what allows commercial place&route tools digesting the ultra-fine granularity so as to achieve (i) a regular power planning and (ii) faster timing closure.From a practical viewpoint, the FINE-VH flow encompasses six different stages fully integrated into a commercial design platform by Synopsys R by mean of dedicated TCL procedures:

Fig. 5 .

 5 Fig. 5. Intra-tile leakage (a) and its reduction via poly-biasing (b)

Fig. 6 .

 6 Fig. 6. PB assignment through local re-synthesis

Fig. 7 .

 7 Fig. 7. Normalized average delay overhead for the different poly-bias options

Algorithm 1 : 4 Cell List ← Cells ∈ Critical Path 5 foreach 9 end 10 Tile

 145910 Voltage Assignment Procedure Input: V ddL, V ddH, f clk Output: Vdd assignment 1 set VddL([All tiles]); 2 while Worst Slack < 0 do 3 zero(Tile Score[All tiles]); Cell ∈ Cell List do 6 Cell Delay ← propagation delay of Cell; 7 Tile ID ← tile hosting Cell; 8 Tile Score[Tile ID] += Cell Delay; Score ← Tile Score[Tiles@VddL]; 11 Tiles Score ← sort(Tile Score, decreasing); 12 Critical Tile ← Tile Score[0]; 13 set VddH(Critical Tile); 14 end

Fig. 8 .

 8 Fig. 8. A 49 tile RI5CY layout after standard-cell placement

Fig. 9 .

 9 Fig. 9. Poly-bias distribution across the interface-cells

Fig. 10 .

 10 Fig. 10. Comparison of four DVFS techniques: i) ideal-DVFS, ii) Vdd-Hopping, iii) Vdd-Dithering, iv) FINE-VH (49 tiles); ∆Vdd=200 mV (left), ∆Vdd=100 mV (right)

Fig. 12 .

 12 Fig. 12. Percentage of standard cell area @VddL for different number of tiles

Table 1 .

 1 Physical characteristics of the RI5CY with FINE-VH

	# Tiles	1	9	25	49
	Core Area µm 2 36229 37105 37626 38386
	# Rows	158	160	161	163
	Cell Area µm 2 25550 25397 25302 25698
	Delay@1.00V ns 3.00 2.95	2.99	3.00
	Interface Cells 0.0% 38.44% 56.89% 62.65%

  Power savings with respect to ideal-DVFS before and after PB optimization for ∆Vdd=100 mV and ∆Vdd=200 mV (49 tiles)

		Dual-Vdd w/o PB	Dual-Vdd w/ PB
	Power Savings w.r.t. ideal-DVFS	-20% -15% -10% -5% 0% 5% 10% 15% 20% 25% 30% 35% 40%	-20% -15% -10% -5% 0% 5% 10% 15% 20% 25% 30% 35% 40%
		1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6	1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
		Normalized Frequency	Normalized Frequency
	Fig. 13.

VddH VddL DC/DC Vdd Core DC/DC Vdd Core DC/DC Vdd Core DC/