Adaptive Test with Test Escape Estimation for Mixed-Signal ICs

Haralampos-G. Stratigopoulos, Member, IEEE, and Christian Streitwieser

Abstract-The standard approach in industry for postmanufacturing testing of mixed-signal circuits is to measure the performances that are included in the data sheet. Despite being accurate and straightforward, this approach involves a high test time since there are numerous performances that need to be measured sequentially by switching the circuit into different test configurations. Adaptive test is a new test paradigm that still adheres to the standard approach, but it adjusts it on-the-fly to the particularities of the circuit under test so as to better control test time and to achieve robust outlier detection. In this paper, we present an adaptive test flow for mixed-signal circuits that has comprehensive user-defined parameters to span the trade-off between test time savings and fault coverage so as to select an advantageous point on the curve based on test economics. The flow also provides robust test escape risk estimation so as to add confidence to the test process. The proposed idea is demonstrated on a sizable production dataset from a large mixed-signal circuit.

Index Terms-Mixed analog digital integrated circuit testing, adaptive testing, test metrics estimation, dynamic part average testing.

I. INTRODUCTION

The standard manufacturing test approach for mixed-signal circuits consists of measuring the performances promised in the data sheet and comparing them to the specifications to make a pass or fail decision. Some performances in the data sheet are measured directly, while others require a dedicated design-for-test on-chip infrastructure to be measured. This standard test approach is straightforward to put in place and results in high test quality, typically expressed in terms of test escapes (i.e. faulty circuits that are undetected) and yield loss (i.e. functional circuits that are inadvertently discarded). However, it incurs a very high test cost since it requires sophisticated automatic test equipment (ATE) and long test times. The test cost keeps increasing as technology nodes advance, as systems become more complex and heterogeneous and deliver more functionalities, as the frequency of operation increases, etc.

In recent years, there has been an intense effort to develop alternative test approaches that can replace effectively the standard test approach. Alternative test approaches include defect-oriented test that improves test quality and can replace the standard test approach in the case of robust designs that are very well centered and never fail due to process variations [START_REF] Mannath | Structural approach for built-in tests in RF devices[END_REF]- [START_REF] Coyette | Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis[END_REF], design-for-test and built-in self-test that aim to speedup the test by alleviating also the ATE requirements [START_REF] Stratigopoulos | Concurrent detection of erroneous responses in linear analog circuits[END_REF]- [START_REF] Barragan | A fully-digital BIST wrapper based on ternary test stimuli for the dynamic test of a 40nm CMOS 18-bit stereo audio Σ∆ ADC[END_REF], and H.-G. Stratigopoulos is with Sorbonne Universités, UPMC Univ. Paris 06, CNRS, LIP6, Paris, France (e-mail: haralampos.stratigopoulos@lip6.fr).

C. Streitwieser is with ams AG, Premstätten, Austria (e-mail: Christian.Streitwieser@ams.com). alternate test (or machine learning-based test) that aims to infer the performances implicitly based solely on low-cost measurements [START_REF] Variyam | Prediction of analog performance parameters using fast transient testing[END_REF]- [START_REF] Barragan | A procedure for alternate test feature design and selection[END_REF]. Such alternative test approaches have a high potential, yet they have not yet fully materialize either because they require design modifications which often finds designers very reluctant or because it is difficult to prove their equivalence to the standard test approach before a large volume of production data is collected for analysis [START_REF] Stratigopoulos | Fast Monte Carlo-based estimation of analog parametric test metrics[END_REF], [START_REF] Sequeira | Fault simulation for analog test coverage[END_REF]. In general, any approach that is less direct and conceptually different than the easily interpretable standard approach has been hardly convincing so far.

In the standard test approach, the test process is fixed and identical for every circuit and is only occasionally revised, typically every few months, when extensive test data have been collected and confident decisions can be made as to how the test process could be improved to lower the test cost.

A recently proposed alternative test paradigm is adaptive test which still adheres to the standard test approach, but dynamically adjusts it to the particularities of each wafer or die instead of having a fixed test process [START_REF] Maxwell | Adaptive testing: Dealing with process variability[END_REF]. In this way, significant test time savings and test quality improvements can be achieved. In the extreme, each wafer or die can be tested using a unique test process.

Adjusting the test process may involve adjusting: (a) The test limits so as to improve outlier detection and quality control; (b) The test content, i.e. given a test suite certain ineffective tests are dropped so as to save test time; and (c) The test order, i.e., assuming stop-at-first-fail and single-site testing, tests with higher fail rate are moved forward and applied first so as to save test time.

The dynamic adjustment is decided based on historical, near-time, and real-time data. Historical data include data from previously tested wafers or lots at various levels (i.e. e-tests, wafer-probe test, burn-in test, final package test, card/system test, etc.), as well as data on faulty devices that are customer returns. Near-time data include data of previously tested dies from the wafer that is currently under test or from wafers in the same lot that have been tested so far. Real-time data include data of previously performed tests on the die that is currently under test.

Despite the clear benefits of adaptive test, several challenges need to be addressed, including: (a) The development of decision-making algorithms to adjust the test process in realtime towards reducing the average test time per wafer or die. It is clear that any such real-time adjustment should either have no impact on test application time, i.e. it happens in the background in the idle time between testing two consecutive wafers or dies within the same wafer, or, if test application is delayed, then any such delay is counterbalanced and recompensed by an overall or average test time reduction per wafer or die; (b) The development of a test infrastructure that is flexible to simplify integration of new adaptive test techniques as they become available. The test infrastructure should support feedforward and feed-backward real-time data communication flow interfaces between the die that is under test, the ATE, and the memory where multiple large databases are stored, and should also be capable of tracing and linking stored data in realtime. In addition, it should offer test engineers a convenient means of obtaining deep visibility into the inner workings of an adaptive test system [START_REF] Kupp | Applying the model-view-controller paradigm to adaptive test[END_REF]; and (c) The real-time monitoring of the probability of test escapes which may inadvertently result from performing a reduced test suite.

In this work, we present a novel adaptive test algorithm for mixed-signal circuits. We consider wafer test, but the algorithm is directly extensible for final test as well. The algorithm starts with a pre-processing step where, based on a sample set of dies that is collected across the wafer, a first guess is made as to which tests can be skipped without sacrificing appreciably the fault coverage. The rest of the dies go through the adaptive test cycle where only the kept tests are applied. During the adaptive test cycle, optionally the test process can be tuned on a die-to-die basis. In particular: (a) Periodically a die can be sampled to be subjected to a full test for quality control purposes; (b) Dynamic part average testing (DPAT) can be embedded within the adaptive test cycle so as to apply tighter test limits and screen out outliers; and (c) If a test that was skipped initially in the pre-processing step is found to fail, then it can be switched on for the rest of the dies of the wafer that will go through the adaptive test cycle with the aim to reduce prospective test escape. In the final post-processing step, the test escape probability is estimated, thus monitoring in real-time the practical equivalence of the adaptive test approach with respect to the standard test approach and reporting any alarming situations. The proposed adaptive test algorithm considers multi-site testing and fully complies to the capabilities and restrictions of an existing adaptive test infrastructure implemented in ATE [START_REF] Streitwieser | Real-time test data acquisition and data processing enabling closed loop control systems for adaptive test[END_REF]. The algorithm is demonstrated on a sizable production dataset from a large mixed-signal circuit. It is shown that various trade-offs between test escape and test time savings can be achieved by varying comprehensive user-defined parameters.

The rest of the paper is structured as follows. In Section II, we provide a concise overview of previous works on adaptive test. In Section III, we present the proposed adaptive test algorithm in details. In Section IV, we discuss metrics to assess the adaptive test flow. In Section V, we present the case study and the available dataset. The results are presented in Section VI and the conclusions are drawn in Section VII.

II. PREVIOUS WORK ON ADAPTIVE TEST

There are several adaptive test ideas that have been explored to date. Approaches for purely digital and mixed-signal circuits present some conceptual similarities, but their practical implementation is different due to the different type of underlying data that are processed for making adaptive test decisions. In particular, in the case of purely digital circuits the underlying data are binary pass/fail data, whereas in the case of mixedsignal circuits the underlying data are continuous parametric measurements. The only approaches that are virtually applicable to both purely digital and mixed-signal circuits are those related to outlier detection since for this purpose it is typically required to extract parametric measurements from the digital circuit, i.e. IDDQ tests, minimum operating voltage, etc.

Ideas for purely digital circuits include: (a) Per-die test pattern re-ordering and elimination by scoring test patterns based on their fail rate probability which is updated on a die-to-die basis [START_REF] Gotkhindikar | Die-level adaptive test: Real-time test reordering and elimination[END_REF], i.e. test patterns with high fail rate are forwarded to the beginning of the list while test patterns that appear steadily in the end of the list are dropped. The scores of test patterns can be weighted based on test time, i.e. test patterns with lower test time are given a higher score, and based also on the position of the test pattern in the order, i.e. test patterns that appear late in the order are given a higher score because they are likely to uniquely detect defects [START_REF] Aslan | Aggressive test cost reductions through continuous test effectiveness assessment[END_REF]; (b) Per-wafer scoring of test patterns based on a control sample of dies collected across the wafer and subsequent application of only the highest score test patterns for the rest of the dies in the wafer, i.e. test patterns that uniquely detect a faulty die in the control sample are given the highest score considering that the majority of faulty dies are detected by a large number of test patterns [START_REF] Grady | Adaptive testing -cost reduction through test pattern sampling[END_REF]; (c) Per-wafer measurement of the global process parameters using on-chip sensors (i.e. ring oscillators) and selection of the corresponding test pattern set to be applied according to the process condition that is identified, where test pattern sets for different process conditions (i.e. fast-fast, typical, slow-slow, etc.) are generated in an offline step [START_REF] Shintani | A variability-aware adaptive test flow for test quality improvement[END_REF]; (d) Robust outlier detection by adapting the pass/fail threshold of IDDQ tests [START_REF] Daasch | Neighborhood selection for i DDQ outlier screening at wafer sort[END_REF]- [START_REF] Daasch | Variance reduction and outliers: statistical analysis of semiconductor test data[END_REF] or other parametric tests, such as the minimum operating voltage [START_REF] Daasch | Variance reduction and outliers: statistical analysis of semiconductor test data[END_REF] and the clock frequency at which the delay test patterns fail [START_REF] Wu | Statistical analysis and optimization of parametric delay test[END_REF]; (e) Periodical customization of the set of test patterns based on fault diagnosis results with the aim to minimize test escape for a given constraint on test costs, or alternatively, ensure that test escape does not exceed some predetermined threshold [START_REF] Yu | Diagnosis-assisted adaptive test[END_REF].

Ideas for mixed-signal circuits include: (a) Skipping tests on a wafer-by-wafer basis based on fail statistics of the wafer [START_REF] Streitwieser | Real-time test data acquisition and data processing enabling closed loop control systems for adaptive test[END_REF], [START_REF] Benner | Optimal production test times through adaptive test programming[END_REF]- [START_REF] Ahmadi | Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs[END_REF]; (b) Skipping tests that have a high pass probability on a die-to-die basis [START_REF] Yilmaz | Adaptive test elimination for Analog/RF circuits[END_REF]- [START_REF] Yilmaz | Per-device adaptive test for analog/rf circuits using entropy-based process monitoring[END_REF]; (c) Tightening onthe-fly test limits so as to improve quality control and outlier detection [START_REF] Fang | Cost effective outliers screening with moving limits and correlation testing for analogue ICs[END_REF]- [START_REF] Dobbelaere | Analog fault coverage improvement using final-test dynamic part average testing[END_REF]; (d) Changing the order of tests so as to move forward tests that have proven to achieve higher fault coverage [START_REF] Chen | Test cost minimization through adaptive test development[END_REF]; (e) Assessing on-the-fly the confidence of lowcost machine learning-based test solutions so as to perform a standard test if confidence is low [START_REF] Stratigopoulos | Error moderation in low-cost machine-learning-based Analog/RF testing[END_REF], [START_REF] Stratigopoulos | Adaptive alternate analog test[END_REF] or stop testing if the device is deemed functional with high confidence [START_REF] Léger | Combining adaptive alternate test and multi-site[END_REF]; and (f) Re-learning periodically the statistical mappings in low-cost machine learning-based tests so as to account for manufacturing process drifts [START_REF] Biswas | Maintaining accuracy of test compaction through adaptive re-learning[END_REF].

III. PROPOSED ADAPTIVE TEST FLOW

We consider multi-site testing with N sites sites, where in a single touchdown N sites dies are tested in parallel. Adaptive test flow and test content decisions can only be done per touchdown. This means that the test program execution is identical for all dies occupying the sites within one touchdown. Statistical analysis on tests takes into account site-to-site variations due to the different tester hardware and instruments per site.

We also consider that tests are arranged into test groups. A test group refers to the group of individual tests that are performed sequentially on the same test configuration. Since the switching time to a new test configuration is considerably higher than the test times of the individual tests that will be performed on this test configuration, it would make little sense to skip individual tests after having spent already the time to set up the test configuration. Furthermore, individual tests within a test configuration are often interdependent, that is, one test is needed for computing the value of another test. For these two reasons, it makes sense to skip or execute the whole group of tests corresponding to a test configuration.

The proposed adaptive test flow per wafer is shown in Fig. 1. It consists of a pre-processing step, the adaptive test cycle itself, and a post-processing step. These steps will be described next in more details.

A. Pre-processing step

In the pre-processing step, a control sample containing β% of dies of the wafer (or approximately β 100 N dies, where N is the total number of dies contained in the wafer) is selected randomly across the wafer. The dies in the control sample are fully tested and, based on the test results, the fail statistics are computed, in order to make a quick decision as to which test groups can be skipped without jeopardizing considerably the fault coverage. A test group is not skipped if any of the following conditions is met: Condition (d) considers the typical scenario where stopat-first-fail is employed. Stop-at-first-fail means that the test procedure terminates after all tests within the test group where the test that failed belongs to are executed. As a result, the values for the tests in the remaining dropped out test groups are missing from the data set. Stop-at-first-fail is not used to save test time, since in the context of multi-site testing it is unlikely that the dies on all sites will fail simultaneously, but to protect the ATE hardware. For example, after having detected a short on a high voltage pin, continuing testing is not wise as this may damage the ATE hardware. If stop-at-first-fail is not used and full test data from all failed dies are available, then we could potentially skip some test groups that present a nonzero failure rate on the control sample. For example, if two test groups always fail simultaneously, then the one incurring the largest test time could be skipped.

B. Adaptive test cycle step

In the adaptive test cycle, we go through the rest of the N -β 100 N dies of the wafer that are not included in the control sample. N sites dies are sampled each time and tested in the exact same way in a single touchdown.

In its simplest form, the adaptive test cycle consists of performing only the test groups that are kept based on the analysis in the pre-processing step and subsequently assigning pass or fail labels by comparing the recorded test values to the corresponding specifications. Several other options can be enabled during the adaptive test cycle so as to improve test quality at the expense, however, of increased test time. These options include applying periodical full test, applying DPAT, and restoring skipped tests and are discussed below. If none of the test groups is skipped, then the adaptive test cycle becomes equivalent to the standard test approach. In this case, all these options are meaningless and are automatically turned off. According to the conditions set above for skipping test groups, if there exist non-permanent test groups and finally none of such test groups is skipped, then it implies that the device under test likely has high failure probability and a low yield, thus performing adaptive test is too risky since it entails a high test escape probability.

The periodical full test option is used to generate useful data for (a) reevaluating the skipped tests and restoring those that could help minimizing test escape and for (b) estimating the test escape probability in the post-processing step. Specifically, in every sample rate-th touchdown the dies undergo a full test. For this purpose, a full test counter is maintained and is reset to 0 after sample rate touchdowns.

The DPAT option aims at applying tighter test limits so as to perform outlier screening [START_REF]Guidelines for Part Averaging Testing[END_REF]. In addition, it generates the same useful data as the periodical full test. DPAT is applied only to those dies in a touchdown that have been classified in the pass bin based on the kept test groups. First, the DPAT limits are computed for all kept tests. The computation is done per site so as to take into consideration site-to-site variations. The user can choose between two different DPAT approaches, namely static DPAT and moving DPAT. In the static DPAT approach, DPAT limits per site for a test are computed using the recorded values of the test on the dies in the control sample that occupied the corresponding site. Specifically, the DPAT limits are set to

[μ ± coef f DP AT σ], where μ = Q 2 , σ = Q3-Q1
1,35 , and Q 1 , Q 2 , Q 3 are the 25-th, 50-th, and 75-th percentile, respectively, of the ordered test values [START_REF]Guidelines for Part Averaging Testing[END_REF]. In the calculation of the mean and standard deviation we consider only the main part of the distribution between the 25-th and 75-th percentile, in order to make the calculation insensitive to outliers. The parameter coef f DP AT defines the sensitivity to outliers. Typically, coef f DP AT = 6 is used for robust outlier detection. Static DPAT limits need to be computed in fact only once before the adaptive test cycle starts and stay constant across all touchdowns. In the moving DPAT approach, DPAT limits are set using the above formula, but are recomputed and updated in each touchdown based on the last DP AT window size recorded values of the test from previous touchdowns. Potentially they can provide more robust outlier detection since they take into consideration the test equipment drift per site. In both approaches, DPAT limits for a test are defined only if at least 30 test values are available, otherwise they are set equal to the specification limits [START_REF]Guidelines for Part Averaging Testing[END_REF].

Once the DPAT limits are computed, they are applied to all kept tests. If one or more of the performed tests violates its DPAT limits, then the die is declared to be an outlier. An outlier die is not summarily discarded, but it is fully tested by switching-on and performing all the skipped tests, in order to assign it a pass or fail label with confidence. Inevitably, in this case, all other dies in the same touchdown are fully tested as well even if they are not outliers since the same test program applies to all dies in a touchdown.

Finally, if for any of the fully tested dies there is a test that was skipped and is found now to fail its specification limits, then the test group where this test belongs to could be optionally switched-on for all the following touchdowns so as to reduce test escape in future test insertions. Note that restoring skipped test groups requires full test data, thus this option requires that one or both other options, e.g. periodical full test and DPAT, are enabled.

C. Post-processing step

The post-processing step starts when all dies in the wafer have been tested. It consists of estimating the test escape risk for the dies that have gone through adaptive test and they have not been fully tested, that is, their pass or fail label has been assigned by comparing the values of the kept tests to their specifications. The test escape risk estimation is used to monitor the quality of the adaptive test program and guarantee its practical equivalence to a full test program. Essentially, whenever the test escape risk becomes prohibitively high beyond a specific threshold, then it triggers an alert signal that in the extreme could prompt a re-test of the whole wafer using the standard, non-adaptive, full test program. The test escape risk estimation method is detailed in Section IV-B.

D. Tuning the adaptive test flow

The proposed adaptive test flow offers several options (i.e. periodically performing full test, applying outlier screening based on DPAT, applying static or moving DPAT limits, restoring skipped tests) and several parameters (i.e. β, coef f DP AT , sample rate, DP AT window size). Each adaptive test flow and selection of corresponding parameters results, in general, in a different trade-off between fault coverage (or, equivalently, test escape) and test time savings. Selecting the most appropriate adaptive test flow and corresponding parameter depends on test economics, the target application, and the required outgoing quality levels.

In the most conservative scenario, the adaptive test flow and corresponding parameters are decided on a lot-to-lot basis by performing the standard test approach on one wafer in the lot. Thereafter, the selected adaptive test flow and corresponding parameters are employed for the rest of the wafers in the lot substituting the standard test approach. If the lot-to-lot variance due to equipment drift, operating procedures, etc., is insignificant, then this tuning could be done less regularly. In contrast, the control sample is selected on a wafer-by-wafer basis so as to capture individual wafer characteristics.

IV. ADAPTIVE TEST METRICS A. Test time savings

If the wafer comprises N dies, then these N dies can be tested into

N t = N N sites , (1)
touchdowns. If the control sample comprises β% of the N dies, then the dies in the control sample are tested into

N t-cs = β 100 N N sites , (2)
touchdowns. The rest N -β 100 N dies are forwarded to adaptive test and are tested into

N t-ada-test = N -β 100 N N sites , (3)
touchdowns. During adaptive test, the number of touchdowns that are periodically sampled to subject the dies into a full test is given by

N t-ps = N t-ada-test sample rate . ( 4
)
Regarding the rest of the touchdowns where the dies undergo a reduced test and outlier screening using DPAT limits, the number of touchdowns for which a full test will be performed because one or more dies within the touchdown is found to be an outlier is given by

N t-outliers = N t-ada-test i = 1 i = k • sample rate k ∈ Z + min(1, N (i) outliers ), (5)
where

N (i)
outliers is the number of dies that are screened out as outliers in the i-th touchdown.

Combining equations ( 2)-( 5), during the adaptive test cycle, the number of touchdowns for which dies undergo a full test is given by

N t-fulltest = N t-cs + N t-ps + N t-outliers . ( 6
)
and the number of touchdowns for which dies undergo a reduced test is given by N t-red-test = N t-ada-test

i = 1 i = k • sample rate k ∈ Z + 1 -min(1, N (i) outliers ) . ( 7
)
Since tests that were previously skipped can be switched on during the adaptive test cycle based on the full test results of outliers and every sample rate-th touchdown, the kept test groups may change from touchdown to touchdown. Let T denote the sum of test times of all test groups and let T (i) kept denote the sum of test times of kept test groups for the i-th touchdown.

The test time per wafer of the standard, non-adaptive test program is given by

T sta-test = N t • T. (8)
The test time of the adaptive test program is given by

T ada-test = N t-fulltest • T + N t-ada-test i = 1 i = k • sample rate k ∈ Z + 1 -min(1, N (i) outliers ) T (i) kept . ( 9
)
The test time savings per wafer can be expressed in % as

∆T = 100 1 - T ada-test T sta-test . (10)

B. Test escape

A test escape is the event where a die goes through the adaptive test cycle (i.e. it is not included in the control sample), ends up being tested using only the kept tests (i.e. if the full periodical full test option is used, then the die is not selected for full periodical test, and if DPAT is used, then the die is not screened out as an outlier), it passes all kept tests, but fails one or more tests that were skipped in the pre-processing step.

Let p j T E denote the probability of test escape for the j-th die that is candidate for test escape. Let also the j-th die be tested with a specific kept test suite, denoted by t j , and specific DPAT limits, denoted by j .

The set of n dies that are fully tested is used for the computation of probability of test escape for all dies that are candidate for test escape. This set includes the dies in the control sample, the dies in the touchdowns that are periodically sampled to be subjected to a full test, and the dies in the touchdowns that end up being subjected to a full test because one or more dies within the touchdown are screened out as outliers based on the DPAT limits.

Let us consider the i-die in this set and assume that it is tested with the kept test suite t j and DPAT limits j . We define the indicator function

I ij = 1 : i-th die is a test escape 0 : otherwise . ( 11
)
The indicator function I ij is a random variable which follows a Bernouli distribution with mean and variance

µ j = p j T E (12)
σ 2 j = p j T E (1 -p j T E ). ( 13
)
An estimate of the test escape probability p j T E is given by

pj T E = n i=1 I ij n . (14)
Using the central limit theorem, for n → ∞

n i=1 I ij -µ j n i=1 σ 2 j ∼ N (0, 1). (15)
Equivalently, substituting ( 12)-( 14) into [START_REF] Sequeira | Fault simulation for analog test coverage[END_REF] we have

pj T E -p j T E p j T E (1 -p j T E )/n ∼ N (0, 1). (16)
From ( 16) we have

Pr{-z α 2 ≤ pj T E -p j T E p j T E (1 -p j T E )/n ≤ z α 2 } = 1 -α, (17)
where z α 2 is the (1 -α 2 ) quantile of the standard normal distribution. Therefore, the 100 • (1 -α)% confidence interval for p j T E is given by

pj T E ± z α 2 p j T E (1 -p j T E ) n . ( 18
)
Replacing p j T E with pj T E into ( 18) we obtain

pj T E ± z α 2 pj T E (1 -pj T E ) n . (19)
To account for small n and extreme probabilities p j T E , we use the Wilson interval that implements a correction factor

1 1 + z 2 α 2 n   pj T E + z 2 α 2 2n ± z α 2 pj T E (1 -pj T E ) n + z 2 α 2 4n 2   , (20)
which can be rewritten as

    pj T E ± z α 2 pj T E (1-pj T E n + z 2 α 2 4n 2 1 + z 2 α 2 n     , (21)
where

pj T E = pj T E + z 2 α 2 2n 1 + z 2 α 2 n ( 22
)
is the corrected estimate of test escape probability p j T E . Since p j T E ≥ 0, the lower bound of the confidence interval is set at max

    pj T E - z α 2 pj T E (1-pj T E ) n + z 2 α 2 4n 2 1 + z 2 α 2 n , 0     . (23)
The absolute test escape per wafer, denoted by N T E , is defined as the number of dies per wafer that are given a pass label while they are faulty. Using [START_REF] Shintani | A variability-aware adaptive test flow for test quality improvement[END_REF], an estimate can be expressed as

NT E = j pj T E , (24)
where the summation is over all dies that go through the adaptive test cycle and are only tested with a reduced test suite. Using ( 21) and ( 23), the lower and upper bounds of the 100 • (1 -α)% confidence interval for N T E are given by

j max     pj T E - z α 2 pj T E (1-pj T E ) n + z 2 α 2 4n 2 1 + z 2 α 2 n , 0     (25)
and

j     pj T E + z α 2 pj T E (1-pj T E ) n + z 2 α 2 4n 2 1 + z 2 α 2 n     , (26)
respectively, where, again, the summation is over all dies that go through the adaptive test cycle and are only tested with a reduced test suite.

As test escape risk metric we can use either the absolute test escape per wafer estimate in [START_REF] Sabade | IC outlier identification using multiple test metrics[END_REF] or the upper bound of the confidence interval in [START_REF] Wu | Statistical analysis and optimization of parametric delay test[END_REF].

By definition, only faulty dies can be a test escape. Intuitively, DPAT may have tendency to screen out faulty dies and subject them to a full test. Thus, in the set that is used for the computation of test escape there are more dies candidate for test escapes compared to a random selection of dies and this may introduce some bias. The control sample, however, adds an opposite bias since it has zero dies candidate for test escapes. Indeed, given the conditions for skipping tests in Section III-A, the dies in the control sample do not fail any skipped test. Only the full periodical test option does a strictly random selection of dies.

C. Fault coverage

Let D l denote the defect level of the wafer, defined as the total number of faulty dies contained in the wafer. The fault coverage can be expressed in % as

F C = 100 1 - N T E D l . (27)
V. CASE STUDY Our case study is a mixed-signal application specific integrated circuit (ASIC) designed by ams AG. The ASIC is an inductive high speed off-axis motion sensor 1 We have at hand a data set that contains the test results from 2 lots. Each lot contains 25 wafers and each wafer contains about 4370 dies. For the first lot, the yield per wafer varies between 80.74% and 93.75% with an average value of 92.01% and the defect level per wafer varies between 273 and 843 with an average value of 349.44. For the second lot, the yield per wafer varies between 95.47% and 96.61% with an average value of 96.10% and the defect level per wafer varies between 143 and 191 with an average value of 164.28.

The multi-site test environment allows testing concurrently N sites = 4 dies and implements stop-at-first-fail.

VI. EXPERIMENTAL RESULTS

A. Adaptive test flows study and comparisons

We will study and compare three adaptive test flow scenarios, ranging from simplest to most elaborate, namely (a) The flow "no DPAT, no periodical full test" where during the adaptive test cycle no outlier screening and no periodical full test are allowed, that is, all dies are tested with a fixed reduced test suite defined based on the fail statistics from the control sample. In this scenario, the parameters coef f DP AT , sample rate, and DP AT window size are irrelevant; (b) The flow "static DPAT, periodical full test" where during the adaptive test cycle outlier screening based on static DPAT limits and periodical full test are enabled. This scenario is enabled by setting coef f DP AT = 6 and sample rate = 20, whereas the parameter DP AT window size is irrelevant; (c) The flow "moving DPAT, periodical full test" where during the adaptive test cycle outlier screening based on moving DPAT limits and periodical full test are enabled. This scenario is enabled by setting coef f DP AT = 6, sample rate = 20, and DP AT window size = 30. Restoring skipped tests is enabled in all flows, but for the flow "no DPAT, no periodical full test" this has no effect since no full test data are collected for reevaluating and eventually switching-on skipped tests if necessary.

In this experiment, we employ the first wafer from the first lot and we study the trade-off between fault coverage (or, equivalently, test escape) and test time savings for the three aforementioned adaptive test flows by varying the control sample size β. For a given value of β, the resultant trade-off depends on the particular subset of dies from the wafer that are included in the control sample. Therefore, to report trustworthy metrics, for each value of β we perform many trials, where in each trial we randomly populate the control sample from the available dies of the wafer. In the end, we report minimum, maximum, and average metrics values observed across the trials.

Fig. 4 shows the minimum, maximum, and average fault coverage and test time savings observed across 50 trials as a function of β for the three aforementioned adaptive test flows. The markers correspond to the average numbers, whereas the lower and upper ends of the intervals correspond to the minimum and maximum numbers, respectively. Fig. 5(a) plots the data in Fig. 4 from a different perspective. In particular, it shows using average values the trade-off between F C and ∆T that is achieved by each adaptive test flow scenario pointing also to the direction of change of β. In Fig. 5(b), the absolute test escape N T E is used instead of F C. The relationship between N T E and F C is given by [START_REF] Yu | Diagnosis-assisted adaptive test[END_REF] considering that for this particular wafer D l = 303.

We observe that every adaptive test flow has specific capabilities regarding the trade-offs F C -∆T and N T E -∆T that can be achieved. This is illustrated by the vertical and horizontal lines in Figs. 5(a) and 5(b). For a given adaptive test flow, as the control sample size β increases, the fault coverage F C increases since the fail statistics are computed on more dies and, thereby, they become more representative of the underlying failure modes. The improvement of F C, however, is at the expense of reduced test time savings ∆T since, as the control sample size β increases, more dies are fully tested and also the kept test suite is likely to be larger. For a given control sample size β, by enabling the periodical full test and DPAT options within the adaptive test cycle, we allow dies to be fully tested during the adaptive test cycle, which increases fault coverage at the expense of deceasing test time savings. In short, enabling the options within the adaptive test cycle, or keeping the options disabled and using a large control sample size β, results in a high F C-low ∆T or, N T E lies in the range [0.02, 1.82], and ∆T lies in the range [0.31%, 8.91%]. The flow "static DPAT, periodical full test" achieves similar range of values with the flow "moving DPAT, periodical full test". The difference is that for the flow "moving DPAT, periodical full test", in general, ∆T presents a much smaller variance across the different trials for a given β, as can be observed in Fig. 4. This points to a smaller variation in the number of outliers across the different trials, that is, a more robust outlier detection, and also reveals overall a smaller dependence on the composition of the control sample. In short, comparing the flows "static DPAT, periodical full test" and "moving DPAT, periodical full test", they achieve practically the same trade-offs F C -∆T and N T E -∆T , but it is recommended to use the flow "moving DPAT, periodical full test" since it offers test time savings with smaller variance.

For small β, many tests are expected to be skipped and this is likely to give rise to smaller fault coverage or, equivalently, higher test escape rate. Furthermore, as shown in Fig. 4, the variance of fault coverage is expected to be higher. This is due to the fact that as β decreases the defect level of the set of dies that go through adaptive test and end up being tested with a reduced test suite increases proportionally, thus increasing the upper bound of test escape across the trials. This elucidates that estimating the fault coverage or, equivalently, the test escape rate, is indispensable so as to monitor the test quality and identify alarming situations. For a given flow, as β increases, the number of dies that are fully tested increases and, thereby, the true test escape drops, as is also illustrated in Fig. 5(b). At the same time, as the number of dies that are fully tested increases, more data become available for estimating the test escape, resulting in more robust and accurate estimates and more confined confidence intervals. For a given value of β, the more reactive the adaptive test flow is in screening out dies for a full test, either periodically for quality control or because they are deemed to be outliers, the smaller the true test escape is and the more data are typically available for estimating it, resulting in more robust and accurate estimates and more confined confidence intervals.

For the flow "no DPAT, no periodical full test", only the control sample is used for estimating the test escape since there is no outlier detection or periodical quality control. By construction, all tests that fail for one or more dies contained in the control sample are kept and are carried out during the adaptive test cycle. In other words, in the control sample there is no die that passes the kept tests and fails a skipped test.

Returning to [START_REF] Shintani | A variability-aware adaptive test flow for test quality improvement[END_REF], this means that pj T E = 0 and pj where n = β 100 N . The 95% confidence interval becomes 0,

T E ≈ z 2 α 2 2n , 0
z 2 α 2
n . Therefore, for the flow "no DPAT, no periodical full test", the test escape estimate and the width of the confidence interval simply drop inversely proportional to β, as is also illustrated in 6(a). For the other two flows "static DPAT, periodical full test" and "moving DPAT, periodical full test", in general, pj T E = 0 and n > β 100 N . As it can be observed, for every flow and for every value of β, the average true test escape always lies within the 95% confidence interval. For the flow "no DPAT, no periodical full test", average test escape is largely overestimated for small values of β, but estimates improve as β increases. For the other two flows "static DPAT, periodical full test" and "moving DPAT, periodical full test", the average test escape estimates are very accurate even for low values of β and the 95% confidence interval is sufficiently narrow. In particular, for the flow "static DPAT, periodical full test", the maximum estimation error is 2.32 test escapes for β = 5% and drops below 0.5 test escapes for β = 50%. For the flow "moving DPAT, periodical full test", the maximum estimation error is 1.90 test escapes for β = 5% and drops below 1 test escape for β = 30%. Yet, similar to the flow "no DPAT, no periodical full test", we observe that for the two flows "static DPAT, periodical full test" and "moving DPAT, periodical full test" the test escape estimates are overestimated, but only slightly compared to the flow "no DPAT, no periodical full test".

B. In-depth analysis for a specific adaptive test flow

In this experiment, we consider without loss of generality the flow "moving DPAT, periodical full test" and we perform a more in-depth analysis. Similarly to Section VI-A, we employ the first wafer from the first lot. Fig. 7 shows the minimum, maximum, and average number of test groups that are skipped during the pre-processing step across 50 trials as a function of β. As it can observed, the average number of test groups that are skipped drops from around 34 to around 28 as β increases from 5% to 90%.

Fig. 8 shows the percentage of trials for which each test group is skipped for β=10%. As it can be observed, there are three categories of test groups. The two largest categories are those corresponding to test groups that are always skipped or never skipped. In total, there are 34 test groups that are never skipped and 27 test groups that are always skipped. The third smaller category contains 8 test groups that are skipped only in certain trials. Among these 8 test groups, the extreme cases are test group 47 which is skipped only 4% of the trials and test groups 37 and 58 which are skipped 96% of the trials. The height of the bars in Fig. 8 essentially point to the frequency with which a test group fails. A test group that is skipped for all 50 trials seems to never fail or, considering stop-onfirst-fail, whenever it fails, another test group earlier in the test group sequence fails at the same time and is not skipped.

A test group that is never skipped for any of the 50 trials is either a permanent test group or it fails very often, that is, any random control sample would contain a die that fails this test group. Fig. 9 shows the percentage of trials for which each test group is switched on during the adaptive test cycle for β=10%. As it can be observed, the skipped test groups that have a non-zero probability of being switched on are the same aforementioned 8 test groups shown in Fig. 8 that are skipped only in certain trials. In other words, a test group that is skipped for all 50 trials has a zero probability of being switched on during the adaptive test cycle. The aforementioned 8 test groups give rise to the intervals in Figs. 4 and7. For example, for β=10%, across the 50 trials, the number of test groups that are skipped varies from 31 to 35, while the corresponding test time savings vary from 2.36% to 14.78%. As it can be observed, although the number of test groups that are skipped varies very little, the test time savings can vary by more than 10%. This is due to the fact that these 8 test groups include test group 47 with test time 1.23s, which is by far the most time-consuming test group, as well as test groups 45, 48, and 58 with high test times 296.3ms, 310ms and 270.6ms, respectively. Fig. 10 shows the true and estimated absolute test escape, as well as the 95% confidence interval, across the 50 trials considering the two extreme values for β, i.e. 5% and 90%, which correspond to highest and lowest test escape risk, respectively. Fig. 10 sheds more light in the result in Fig. 6(c) showing the accuracy of test escape estimation across trials. As it can be observed, the true and estimated test escape values are close to each other, for all except one trial (e.g. trial 42 for β=90%) the true test escape value lies within the 95% confidence interval, and the 95% confidence interval is sufficiently narrow. In trial 42 for β=90% where the true test escape values lie outside the 95% confidence interval, the distance between the closest bound of the confidence interval and the true test escape is 1. Therefore, we conclude that test escape risk is well estimated, regardless whether it is high or low, providing large confidence in the adaptive test decisions. Finally, Fig. 11 shows for a specific test the moving DPAT limits per site as dies go through the adaptive test cycle. The moving DPAT limits are at any point in time tighter compared to the standard specifications, which are represented with the horizontal lines. As it can be observed, for this specific test there are tens of dies which do not violate the test specifications, but are clear outliers and are forwarded to a full test during the adaptive test cycle to investigate whether they fail one of the skipped tests.

C. Adaptive test in action

Since in our experiment adaptive test is applied during wafer test, any point in the curves in Fig. 5 is valid and potentially interesting from a test economics perspective. For example, if we are interested in performing a fast wafer test while discarding the majority of faulty dies but still affording packaging a non-negligible number of faulty dies, then using the simple flow "no DPAT, no periodical full test" and a low value for β is probably the best option. If, in contrast, we are very much concerned about saving the considerable cost of packaging faulty devices, then we may opt for the more elaborate flow "moving DPAT, periodical full test".

In this experiment, we consider without loss of generality the flows "moving DPAT, periodical full test" and "no DPAT, no periodical full test", and we apply them separately on all available wafers from the two lots imitating a real implementation scenario. For the flow "moving DPAT, periodical full test" we use β = 5%, while for the flow "no DPAT, no periodical full test" we use β = 30%.

Let us consider first the flow "moving DPAT, periodical full test". Fig. 12 shows the number of wafers in the first lot for which each test group is skipped during the pre-processing step. We observe three categories of test groups, namely test groups that are skipped for every wafer, test groups that are not skipped for any of the wafers, and test groups that are skipped only for a certain number of wafers. Comparing Fig. 12 to Fig. 8 that corresponds to a single wafer from the first lot, we observe that the same test groups that are kept for all trials for the single wafer are always kept for every other wafer too. These test groups are permanent and/or are very effective in detecting failures. In contrast, test groups that were skipped for all trials for the single wafer may be switched on for other wafers. This observation points to the fact that there are some defect types that do not manifest themselves on every wafer and are uniquely detected by specific test groups. Furthermore, in the set of test groups that are skipped only for a certain number of wafers, we observe that there are 7 test groups that are skipped for 24 wafers, that is, they are kept only for 1 wafer. These test groups seem to detect a rather rare fault that is not manifested in any of the other wafers. Fig. 13 shows the true and estimated test escape across all wafers in the first lot, as well as the 95% confidence interval for the estimated test escape. We recall that the defect level varies across wafers in the first lot between 273 and 842 with an average value of 349.44. As it can be seen, the true test escape varies between 0 and 3 and lies always within the 95% confidence interval. The mean estimation error is 1.24. Fig. 13 also shows the average true and estimated test escape, denoted by NT E and NT E , respectively, defined as the mean true and estimated test escape, respectively, computed over all wafers in the lot. The average true and estimated test escape values are 1 and 2.16, respectively, that is, the true value is overestimated by 1.16. We conclude that the test escape risk is very well estimated for all wafers providing confidence in the decisions. Fig. 14 shows the trade-off between yield, true and estimated fault coverage values, and test time savings across all wafers in the first lot. The plot also shows the 95% confidence interval for the estimated fault coverage. We recall that in the first lot the wafer yield varies between 80.74% and 93.75% with an average value of 92.01%. It is practically constant at around 92% across all wafers except for the second wafer that presents a much lower value of 80.74%. To estimate fault coverage from [START_REF] Yu | Diagnosis-assisted adaptive test[END_REF], an estimate of the defect level is derived from the dies in the control sample that are fully tested during the pre-processing step. The 95% confidence interval for the fault coverage is derived by using the 95% confidence interval for the absolute test escape. The true fault coverage varies between 99% and 100% with an average value of 99.70%. The estimated fault coverage is very accurate for all wafers in the lot with a mean estimation error of 0.42%, and the true fault coverage always lies within the 95% confidence interval which is very tight and hardly legible in the plot. The test time savings vary between 2.29% and 12.46% with an average value of 4.97%. We recall that this particular adaptive test flow targets a steadily high fault coverage, while achieving the maximum possible test time savings given this constraint. This flow is appropriate when the goal is to screen out all faulty dies at wafer-level so as to avoid packaging faulty dies, while still achieving some test time savings, which when projected to high volume are very significant. Figs. [START_REF] Sequeira | Fault simulation for analog test coverage[END_REF][START_REF] Maxwell | Adaptive testing: Dealing with process variability[END_REF][START_REF] Kupp | Applying the model-view-controller paradigm to adaptive test[END_REF] show the results for the flow "no DPAT, no periodical full test" using the wafers in the first lot. Comparing Fig. 15 to Fig. 12, we observe that on average test groups are skipped with a lower rate in the flow "no DPAT, no periodical full test" compared to the flow "moving DPAT, periodical full test". This is due to the fact that the value of β is higher for the flow "no DPAT, no periodical full test" than for the flow "moving DPAT, periodical full test". The true fault coverage varies between 94.60% and 99.40% with an average value of 97.87%, and the test time savings vary between 28.97% and 37.83% with an average value of 34.56%. Thus, the flow "no DPAT, no periodical full test" achieves on average about 2% less fault coverage and about 30% more test time savings than the flow "moving DPAT, periodical full test". This is expected since the flow "no DPAT, no periodical full test" is more appropriate when the goal is to maximize test time savings at wafer test, while detecting the vast majority of faulty dies and allowing a small percentage of faulty dies to be packaged. The estimates of the test escape and fault coverage are less accurate than in the flow "moving DPAT, periodical full test" and also pessimistic since, as explained in Section VI-A, in the absence of full test data during the adaptive cycle, they rely solely on the correction factor in the Wilson interval. Nevertheless, the estimates are deemed to be reasonable and always lie within the 95% confidence interval.

Finally, from Fig. 17 we observe that the lowest test time savings are observed for the wafers that incur the lowest yield. To shed more light into this observation, we repeat the experiment for the wafers in the second lot using the exact same parameter values as for the first lot. We recall that the average wafer yield for the first and second lot is 92.01% and 96.10%, respectively. Fig. 18, which shows the result of applying the flow "moving DPAT, periodical full test" for the wafers in the second lot. The test time savings end up being on average 10.33% across all wafers, while we recall that for the first lot the test time savings are on average 4.97% across all wafers, that is, an increase of more than 5%. When applying the flow "no DPAT, no periodical full test" the test time savings are on average 36.01%, while for the first lot the test time savings are on average 34.56%, that is, an increase of about 1.5%. This proves that there is a correlation between yield and test time savings for a target fault coverage, that is, the lower the yield is, the lower the test time savings are. This is expected since, in general, the lower the yield is, the smaller the number of test groups that is skipped in the preprocessing step is, and the larger the number of test groups that is switched on during the adaptive test cycle is. Moreover, in general, lower yield implies more outliers, thus the number of dies that end up being fully tested during the adaptive test cycle is higher.

VII. CONCLUSIONS

We presented an adaptive test algorithm for mixed-signal circuits. The algorithm is specifically designed for wafer test, but it can be extended for final test as well. It includes a number of comprehensive options and user-defined parameters such that it can be tuned to achieve the desired advantageous trade-off between test escapes and test time savings as dictated by the test economics of the target application. The algorithm considers the standard test suite and saves test time on average by judiciously selecting tests to skip. The set of tests that is skipped is adapted to the particularities of each wafer. It is selected based on automated criteria that include the fail statistics of a fraction of dies from the wafer that are fully tested and real-time outlier detection. In its last step, the algorithm quickly calculates an estimate of the test escape risk and a corresponding confidence interval, in order to add confidence to the adaptive test flow and report any alarming event. The algorithm is demonstrated using a sizable production test data set from a large mixed-signal circuit. It is shown that the algorithm can be tuned to achieve a large range of trade-offs between test escapes and test time savings and that test escapes can be estimated very accurately. It is also shown that the algorithm adapts to the wafer yield, resulting in significantly less test effort for wafers that present high yield.

Fig. 1 :

 1 Fig. 1: Adaptive test flow.

  (a) it contains permanent tests that are demanded by the end customer; (b) it contains tests with negligible test time and proven fault coverage, such as continuity and leakage tests; (c) it contains tests with low C pk values, where C pk = min USL-µ 3σ , µ-LSL 3σ , USL and LSL denote the upper and lower specification limits of the test, respectively, and µ and σ denote the mean and standard deviation of the test, respectively; (d) one or more dies in the control sample fail the test group, where, by definition, a test group fails when at least one test within this test group fails.

Figs. 6 5 :

 65 (a)-(c) show the average true and estimated test escape, denoted by NT E and NT E , respectively, computed across the 50 trials, as well as their difference, as a function of β for the three aforementioned adaptive test flows. Figs. 6(a)-(c) also show the average 95% confidence interval as a no periodical full test static DPAT, periodical full test moving DPAT, periodical full test -increases (a) Trade-off between fault coverage and test time savings achieved by different adaptive test flows. no DPAT, no periodical full test static DPAT, periodical full test moving DPAT, periodical full test increases (b) Trade-off between test escape and test time savings achieved by different adaptive test flows. Selecting adaptive test flow and relevant parameters based on test economics. function of β, which is computed by averaging the lower and upper bounds of the 95% confidence interval that are obtained across the 50 trials.

  -dence interval (a) No DPAT, no periodical full test.

  con-dence interval (b) Static DPAT limits, periodical full test.

  -dence interval (c) Moving DPAT limits, periodical full test.

Fig. 6 :

 6 Fig. 6: Average true and estimated test escape as a function of the control sample size β for different adaptive test flow scenarios showing also the average 95% confidence intervals.

Fig. 7 :

 7 Fig. 7: Number of test groups that are skipped across the 50 trials as a function of the control sample size.

Fig. 8 :Fig. 9 :

 89 Fig. 8: Percentage of trials for which each test group is skipped.

Fig. 10 :

 10 Fig. 10: True and estimated absolute test escape across the 50 trials for two "extreme" values of β, showing also the 95% confidence interval.

4 Fig. 11 :

 411 Fig. 11: Moving DPAT limits per site as dies go through the adaptive test cycle.

Fig. 12 :Fig. 13 :

 1213 Fig.12: Adaptive test flow "moving DPAT, periodical full test": number of wafers in the first lot for which each test group is skipped.

Fig. 14 :

 14 Fig. 14: Adaptive test flow "moving DPAT, periodical full test": trade-off between yield, true and estimated fault coverage values, and test time savings across wafers in the first lot, showing also the 95% confidence interval for fault coverage.

Fig. 15 :Fig. 16 :

 1516 Fig.15: Adaptive test flow "no DPAT, no periodical full test": number of wafers in the first lot for which each test group is skipped.

Fig. 17 :

 17 Fig. 17: Adaptive test flow "no DPAT, no periodical full test": trade-off between yield, true and estimated fault coverage values, and test time savings across wafers in the first lot, showing also the 95% confidence interval for fault coverage.

Fig. 18 :

 18 Fig. 18: Adaptive test flow "moving DPAT, periodical full test": trade-off between yield, true and estimated fault covvalues, and test time savings across wafers in the second lot, showing also the 95% confidence interval for fault coverage.

  . The standard test suite consists of 338 tests that are assorted into 69 different test groups each requiring a specific test configuration. As shown in Fig. 2, the number of tests per test group ranges from 1 to 40. The total test time is 7.8726s and is distributed per test group as shown in Fig. 3. The test group with the largest number of tests does not necessarily incur the largest test time. For example, test group 41 is the most populous

		40
		35
		30
		25
	tests	20
	#	15
		10
		5
		0
		0	20	40	60	80
				test group
		Fig. 2: Number of tests per test group.
	1400
	1200
	1000
	(in ms)	800
	time	600
	test	400
		200
		0
		0	20	40	60	80
				test group
			Fig. 3: Test time per test group.
	test group with 40 tests incurring 312.1ms, while test group
	47 is the most time-consuming test group with test time 1.233s
	including just 10 tests.

  Fault coverage and test savings as a function of the control sample size β for different adaptive test flow scenarios. equivalently, low N T E -low ∆T trade-off. Keeping the options disabled and using a low control sample size β results in a low F C-high ∆T or, equivalently, high N T E -high ∆T trade-off. Specifically, for the simplest flow "no DPAT, no periodical full test", F C lies in the range [93.62%, 99.78%], N T E lies in the range [0.66, 19.34], and ∆T lies in the range [4.27%, 56.01%]. For the most elaborate flow "moving DPAT, periodical full test", F C lies in the range [99.40%, 99.99%],

		no DPAT, no periodical full test
	FC	static DPAT, periodical full test moving DPAT, periodical full test
		"T
	Fig. 4:

More details regarding the ASIC may not be released due to a binding NDA.


Vincent Nabat
email: nabat@lirmm.fr

María De La O Rodriguez

Olivier Company

Sébastien Krut

François Pierrot
email: pierrot@lirmm.fr

Par4: very high speed parallel robot for pick-and-place

Keywords: Schonflies Motion, PKM, pick-and-place, Articulated traveling plate

This paper introduces a four-degree-of-freedom parallel manipulator dedicated to pick-and-place. It has been developed with the goal of reaching very high speed. This paper shows that its architecture is particularly well adapted to high dynamics. Indeed, it is an evolution of Delta, H4 and I4 robots architectures: it keeps the advantages of these existing robots, while overcoming their drawbacks. In addition, an optimization method based on velocity using Adept Motion has been developed and applied to this high speed parallel robot. All these considerations led to experimentations that proved we can reach high accelerations (13 G) and obtain a cycle time of 0.28 s.

I. INTRODUCTION

The first parallel mechanism is attributed to Gough with its well-known platform [START_REF] Gough | Contribution to discussion of papers on research in Automotive stability, control and tyre performance[END_REF] and Stewart [START_REF] Stewart | A platform with 6 degrees of freedom[END_REF] created the famous flight simulator few years later. Thanks to actuators located close to the frame, the dynamics of these mechanisms is high compared to serial robots. These machines have six degrees of freedom (dof) and the range of their angular motion is limited.

However, all robotized tasks do not need six dof. Brogardh proposed a classification [START_REF] Brogardh | PKM Research -important issues, as seen from a product development perspective at ABB robotics[END_REF] giving the necessary number of dof for different industrial tasks. Generally, pickand-place needs four dof: three translations and one rotation around a vertical axis. These motions are named Schoenflies motions [START_REF] Hervé | The lie group of rigid body displacements, a fundamental tool for mechanism design[END_REF] or SCARA motions. The main industrial applications for these mechanisms are packaging, including picking, packing and palletizing tasks.

Delta robot [START_REF] Clavel | Delta, a fast robot with parallel geometry[END_REF], developed by Clavel at EPFL at the end of 80s, generates Schonflies motion and is well adapted to pick-and-place tasks because of its high dynamics. Indeed, actuators of this robot are fixed on the frame which minimizes moving parts masses. However, the rotational motion of this robot is obtained using a central RUPUR chain (R: Revolute, U: Universal, P: Prismatic, bold representing the actuated joint) which could suffer from a lack of stiffness at workspace extremities. In addition, this telescopic arm has a short service life.

Other lower mobility parallel mechanisms able to realize SCARA motions have been developed. For example, Angeles [START_REF] Angeles | A novel manipulator architecture for the production of scara motions[END_REF] proposed a four-dof parallel mechanism. In addition, EPFL developed Kanuk and Manta robots [START_REF] Rolland | The manta and the kanuk: Novel 4-dof parallel mechanisms for industrial handling[END_REF], and the machine tool HITA STT which has been derived to pick-and place manipulator [START_REF] Thurneysen | A new parallel kinematics for high speed machine tools hita stt[END_REF]. At last, authors proposed H4 [START_REF] Pierrot | H4: a new family of 4-dof parallel Robots[END_REF], I4L [START_REF] Krut | I4: A new parallel mechanism for SCARA motions[END_REF] and I4R [START_REF] Krut | A high speed robot for scara motions[END_REF] introducing the articulated traveling plate concept (see Fig. 1).

This paper presents a new parallel manipulator based on H4 and I4 architectures: Par4. This mechanism has been developed with the aim of reaching very high speed and acceleration. Indeed, the second part of the paper presents the improvements of Par4 compared to I4 and H4. The third part exposes an optimization method dedicated to pick-and-place robots, applied to Par4. The last part presents experimental results showing that the prototype is able to reach accelerations up to 13 G.

II. DESCRIPTION OF PAR4

The particularity of Par4 compared to H4 and I4 is its articulated traveling plate. It is composed of four parts: two main parts (1,2) linked by two rods [START_REF] Brogardh | PKM Research -important issues, as seen from a product development perspective at ABB robotics[END_REF][START_REF] Hervé | The lie group of rigid body displacements, a fundamental tool for mechanism design[END_REF] thanks to revolute joints (see Fig. 2). The shape of this assembly is a planar parallelogram and the internal mobility of the traveling plate is a PI joint [START_REF] Hervé | Star, a new concept in robotics[END_REF] (circular translation) which produces the rotational motion about the vertical axis of the global robot. The range of this rotation is 4 . That's why, an amplification system has to be added in order to obtain a complete turn:

. The amplification system can be made of gears or belt/pulleys. The chosen mechanism for the prototype is belt/pulleys with an amplification ratio 4 (see Fig. 2b). The overall architecture is similar to H4 or I4R as described in [START_REF] Pierrot | H4: a new family of 4-dof parallel Robots[END_REF] and [START_REF] Krut | A high speed robot for scara motions[END_REF]. Arms and forearms, made of carbon fiber, are taken from ABB Flexpicker robot. Par4 is a Deltalike mechanism. The key difference with the Delta robot is the use of four kinematic chains instead of three. In addition, it uses the concept of articulated traveling plate in order to avoid the central telescopic leg. The key difference with H4 and I4 robots will be explained in the following.

Remark about models for kinematics solutions:

As mentioned previously, the articulated traveling plate of Par4 produces a rotational translation. From a modeling point of view, it can be assimilated to H4. Thus, models for kinematics solutions (position and velocity) can be found in [START_REF] Pierrot | H4: a new family of 4-dof parallel Robots[END_REF] and will not be presented here.

III. WHY PAR4 INSTEAD OF H4 AND I4

This new prototype has been developed in order to reach very high speed and acceleration, and to obtain a homogeneous behavior and a good stiffness in the whole workspace and for every direction. All these constraints can not be respected at the same time neither by H4 nor I4 for different reasons that are now explained.

A. From I4 to Par4

An advantage of this architecture is the good arrangement of actuators unlike H4 (see § III.B). In addition, models for kinematics solution of this mechanism are simple. However, the main weak point of I4 [10][11] is the use of prismatic joints in the articulated traveling plate. Indeed, used at high speed, commercial prismatic joints have a short service life, due to high acceleration and pressure exerted on balls. Thus, I4 is well suited for high force/ moderate acceleration application (machining for example).

For high speed robots, the use of revolute joints in the articulated traveling plate seems to be more adapted. That's why, Par4 has been developed with the constraint of using only revolute joints on its articulated traveling plate.

B. From H4 to Par4

H4 uses revolute joints, but a weak point of this robot is the arrangement of its actuators. This particularity is due to singularity configurations.

Singularities occur for particular poses of the mechanism and lead to a bad behavior of the end-effector. In [START_REF] Zlatanov | Identification and classification of the singular configurations of mechanisms[END_REF], a classification of singularities is proposed. They can be parted into three categories: under-mobilities [START_REF] Gosselin | Singularity Analysis of Closed-Loop Kinematic Chains[END_REF], over-mobilities [START_REF] Gosselin | Singularity Analysis of Closed-Loop Kinematic Chains[END_REF], and internal singularities [START_REF] Zlatanov | Constraint Singularities[END_REF]. These notions can be partly explained using linear kinematic equation [START_REF] Gosselin | Kinematic analysis optimization and programming of parallel robotic manipulators[END_REF]:

x q J x J q (1)
where x is the vector of operational velocities and q is the vector of actuated joints velocities.

In order to explain these categories of singularities, a simple two-dof parallel mechanism is proposed:

-On one hand, under-mobilities occur when J q is singular. In that case, a velocity q can be applied without producing any motion on the traveling plate (Fig. 3a), -On the other hand, over-mobilities occur when J x is singular. In that case, it is possible to have x 0 without moving the actuators (Fig. 3b).

x 0 At last, "internal" singularities can occur for some mechanisms. They cannot be enlightened thanks to J x or J q , and a more complete study has to be done. On Fig. 4, an internal singularity occurs when the parallelogram becomes flat. In that case, orientation of traveling plate cannot be guaranteed (this orientation does not belong to operaltional velocities).

1 0 q 2 0 q x 0 1 0 q 2 0 q (a)
x 0

1 0 q 2 0 q Fig.

Presentation of internal singularities

Placing actuators of H4 with a homogeneous repartition, i.e. placed at 90° one relatively to each other, leads to internal singularities. Thus, a particular arrangement has to be adopted. This particularity involves a non-homogeneous behavior of H4 in the workspace and a bad stiffness, as demonstrated in [START_REF] Company | A Method for Modeling Analytical Stiffness of a Lower Mability Parallel Manipulator[END_REF].

As said before, the study of classical matrices J x and J q presented in equation ( 1) is not enough to enlighten internal singularities.

That's why, a complete kinematic analysis has been done on Par4 in order to show that this architecture overcomes drawbacks of H4 and I4 while keeping all the advantages for high speed. The method of the analysis has been introduced in [START_REF] Krut | A high speed robot for scara motions[END_REF] and [START_REF] Krut | Contribution à l'Etude des Robots Parallèles Légers, 3T-1R et 3T-2R, à Forts Débattements Angulaires[END_REF] for I4 case. The analysis assumes that the mechanism is constituted of 2 sub-unit (actuators and traveling plate) linked by 8 rods having spherical joints. Each rod adds between those two sub-sets a pure geometrical length constraint.

This complete study can be done writing equiprojectivity of speeds for the 8 rods joining the actuators to the traveling plate. It leads to the following equation: Assuming that the PI joint in the traveling plate induces a constant parallelism of rods, it produces a coupling. Thus, velocities of revolute joints of traveling plate are equal and the following simplifications can be made: 14 13 (3)

tp 1 a c t J x J q (2) Aij Aij Bij Bij B11 B12 B22
21 22 ( 4
)
This coupling is the key difference with the complete kinematic modeling of H4.

Additionally, the following assumptions are made:

14 13 z v v e ( 5
)
21 22 z v v e ( 6
)
Note that x presented in (1) is the vector composed of operational velocities whereas 1

x in (2) is the vector composed of velocities of the complete articulated traveling plate, including internal velocities. Thus, 1

x is the following vector:

T x y z x y z 1 x (7)
where , , , z x y z are operational velocities.

It is now possible to write the 8 7 matrix J tp as described in (8). where and are respectively cross-product and dotproduct.

Matrix J tp expressed in (8) can be manipulated in order to enlighten blocks. It is then possible de rewrite expression [START_REF] Stewart | A platform with 6 degrees of freedom[END_REF]. It leads to the following equation: We recognize equation ( 1) with additional terms:

int q x x int int x J q J J v J 0 0 (10)
With this modeling, J int has the following expression: We can notice that the 4 3 matrix [START_REF] Krut | A high speed robot for scara motions[END_REF] shows that the mechanism is over-constrained (over-determined system). In addition, developing equation ( 10) leads to:

int x x int q int int J x J v J q J v 0 (13)
The second equation of system [START_REF] Zlatanov | Identification and classification of the singular configurations of mechanisms[END_REF] shows that additional terms v int will be null if J int is a full-rank matrix. It means that mechanism will not have "internal singularities": rank 3 int J [START_REF] Gosselin | Singularity Analysis of Closed-Loop Kinematic Chains[END_REF] Additionally, the usual kinematic relation (1) will be derived.

Considering that the four pairs of rods have a symmetric contribution on the mechanism, ( 14) leads to calculate one determinant D ijk (among the four possible ones), and to verify that:

, , 1, 2,3 , 1, 2, 4 , 1,3, 4 , 2, 3, 4 , 0

ijk i j k D ( 15
)
where,

ijk i i j j k k D f l f l f l (16)
This working condition remains always true while placing the motors at 90° one relatively to each other and scanning the whole workspace. This fact is a key issue for robot performance.

To summarize, Par4 has been developed with the aim of reaching high speed and acceleration. Thus, the adopted configuration is a good compromise between H4 and I4 robots: passive joints used in the articulated traveling plate are only revolute joints and motors are placed in homogenous arrangement.

IV. OPTIMIZATION OF PICK-AND-PLACE ROBOTS

Having the general configuration of the mechanism, it is necessary to optimize its geometrical parameters. The aim of this optimization is to satisfy some industrial constraints, while guaranteeing our final goal: to reach high speed and acceleration. Thus, an optimization method dedicated to pickand-place robots has been developed.

A. Principle of optimization method

The aim of this method is to determine the geometrical parameters in order to: i) obtain a robot with the smallest footprint,

ii) with the largest workspace, iii) while guaranteeing the possibility of performing a classical pickand-place cycle (named Adept Motion: see § III.B) in a given time, iv) and having a homogenous behavior in the workspace.

We decided to minimize the cost function :

L l D ( 17
)
where L is length of arms, l is length of forearms, and D is the diameter of workspace. Lengths are chosen equal for each kinematic chain.

This cost function was chosen in order to satisfy conditions i) and ii) at the same time.

The cost function is minimized under the following constraints:

-Verifying that maximum joint velocities of actuators are always lower than a given value while performing the Adept Motion (see §III.B) for a given time, -Verifying that conditioning number of the weighted jacobian matrix is always lower than a given value.

This first constraint characterizes condition iii) of optimization goals and the second one characterizes condition iv). The optimization process can be summarized as shown on Fig. 6.

Variation of parameters

Calculation of workspace

Under constraint of condition number For each set of parameters, the cost function is calculated using workspace and adept motion computations. If this cost is lower than a given value, the parameters are stored. This computation is done with other set of parameters until the end of the computation.

Calculation of max. articulated velocities

Adept Motion through several orientations

Calculation of cost function < max

Storage of parameters

Before presenting results obtained with this method applied to Par4, the following paragraph will present Adept Motion and the way to obtain it.

B. Adept Motion

This motion is well-known for commercial pick-andplace robots. It permits to evaluate performances of a robot for a pick-and-place task. It is defined by a length and an altitude. The indicator is the time made by the robot to complete a "round trip". Its shape is given at Fig. 7. As seen previously, we used the simulation of Adept Motion in order to determine maximum joint velocities.

Applying a time law, it is possible to determine absolute position and velocity function of time, x(t) and x(t) . By consequence q(t) and q(t) are obtained using models of robot.

Three options have been studied in order to realize Adept Motion: Bezier curves, clotoide, and half ellipses.

1) Bezier curves

Bezier curves are defined using controlled points. As proposed in [START_REF] Khalil | Modélisation, identification et commande des robots[END_REF], a time law can be applied on it using a 4 th degree polynomial interpolation [START_REF] Froissart | Génération adaptative de mouvement pour processus continus ; application au suivi de joint[END_REF]. However, this interpolation may cause velocity discontinuities.

2) Clotoide

The second option studied is clotoide equations in order to avoid discontinuity while connecting two lines [START_REF] Paul | Advanced industrial robot systems[END_REF]. Absolute coordinates are expressed using Fresnel integrals that do not have analytical solution and have to be resolved by Taylor's series.

3) Half-ellipse

A half-ellipse can be defined using three points: start, end, and transition points. Knowing these points, halfperimeter of ellipse can be approximated [START_REF] Spiegel | Formules et tables mathématiques[END_REF] by:

2 2 1 2 d A B ( 18
)
where A is the length of big half-axis of ellipse and B is length of little half-axis. As proposed in [START_REF] Codourey | Contribution à la commande des robots rapides et précis[END_REF], equation of ellipse can by easily approximated using projection of curvilinear abscissa of a circle on the ellipse. Applying a time law s(t), absolute positions can be expressed:

. [START_REF] Khalil | Modélisation, identification et commande des robots[END_REF] where C is the center of ellipse.

This simple solution has been kept in the optimization algorithm described at § III.A.

C. Optimization results

The described method has been applied to Par4 robot. Optimized parameters (see Fig. 8) were length of arms L, length of sub-arms l, position of actuators R (corresponding to a radius) and the altitude of workspace center Z 0 . In order to be in accordance with industrial requirements, diameter of workspace D has been fixed to 1 meter. For each L, a set of "optimum parameters" has been obtained (see Fig. 9). This compromise has been chosen in order to obtain a correct maximum actuated joint velocity while geometrical constraints L, l and R have reasonable values.

IV. EXPERIMENTAL RESULTS

Using optimal parameters presented in § III, and architecture developed with the aim of reaching very high speed in § II, a prototype (see Fig. 2) has been built.

All tests have been performed using Adept Motion (as described at III.B.3) with a length of 305 mm and an altitude of 25 mm. The control loop is P/PI applied on actuated variables.

The first experimentations have been done with the following characteristics: maximal velocity (v) = 2.5 m.s -1 , maximal acceleration (a) = 100 m.s -2 . Obtained cycle time (round trip) is: 0.45 s. Records of this experimentation are presented at Fig. 10. The second experimentations have been made applying high speed and accelerations: v = 3.8 m.s -1 , a = 130 m.s -2 .The obtained cycle time is: 0.28 s. (see Fig. 11). These experimentations show that we are able to have very good performances and to complete short cycle time. However, an overshoot is obtained as shown on Fig. 11. This restriction is partially due to torque limitation of actuators used on prototype.

IV. CONCLUSION

This paper introduces a new four-dof parallel manipulator dedicated to pick-and-place and developed to perform high speed and acceleration. It shows that this robot is an improvement of H4, I4 and Delta robots and its architecture has been developed to overcome drawbacks of these existing robots. The key point of this architecture is its symmetrical arrangement of actuators (involving homogenous behavior) and the use of articulated traveling plate made of revolute joints. This key point has been proved making a complete analysis of all singularities. In addition, the Adept Motion, a reference motion used by industrial people to evaluate pickand-place robots, has been used to run an optimization. The concrete result obtained is a prototype able to reach an acceleration of 13 G and a cycle time equal to 0.28s.

The future work we will make on this robot will be based on dynamic modeling and dynamic control in order to improve the behavior of the robot while reaching high acceleration.

A demonstration video of Par4 prototype can be consulted at: http://www.lirmm.fr/~nabat/par4.wmv

  Fig. 2 Par4 prototype

Fig. 3

 3 Fig. 3 Presentation of singularities

Fig. 5

 5 Fig. 5 Par4 parameters for complete singularity analysis As shown in Fig. 5, the following parameters are introduced: -i: number of kinematic chain. i = 1,4 -j: number of rod in each kinematic chain. j = 1,2 -k: number of half traveling plate. k = 1,2 -A ij : center of spherical joints on actuated side of forearms -B ij : center of spherical joints on traveling plate side of forearms -A i : geometrical point situated at the middle of A i1 and A i2 -B i : geometrical point situated at the middle of B i1 and B i2 -C ki : center of revolute joints of traveling plate -D: controlled point (located on one of the parts of traveling plate) -l i : vector between B i and A i f i : vector between B i1 and B i2 -v ki : unitary vector of collinear revolute joint axis ki d i : vector linking C ki and B i c k : vector linking C ki and D -e i = c k + d i ki :velocity of part k respectively to parallelogram rod (in revolute joint # ki oriented by v ki ) -, , x y z : internal angular velocities -( , , ) x y z e e e : reference frame axes, with z e describing the vertical axis

  Fig. 6 Optimization process

  Fig. 7 Adept Motion shape

Fig. 8

 8 Fig. 8 Optimized parameters

Fig. 9

 9 Fig. 9 Sets of optimal parameters Optimal parameters chosen are a compromise among the sets of parameters described on Fig. 9 : L = 0.825 m, l = 0.375 m, R = 0.275 m, Z 0 = -0.58 m It leads to the maximum articulated velocity: max Q = 21.9 rad.s -1This compromise has been chosen in order to obtain a correct maximum actuated joint velocity while geometrical constraints L, l and R have reasonable values.

Fig. 10

 10 Fig. 10 Evolution of position along x (v =2.5 m.s -1 , a = 100 m.s -2 )

Fig. 11

 11 Fig. 11 Evolution of position along x (v =3.8 m.s -1 , a = 130 m.s -2 )


J M Dutertre
email: dutertre@lirmm.fr

F M Roche
email: roche@lirmm.fr

G Cathebras
email: cathebra@lirmm.fr

Integration of Robustness in the Design of a Cell

When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impedance state switching. The design prevents perturbation to propagate inside the latch and saves an uncorrupted information source for recovery mechanisms. Post layout circuit simulations are used to verify the hardness assurance of this design; we also compare it to usual techniques and report significant improvements for its use in SoC.

Introduction

Integrated Circuits ( ICs ) are adversely affected by environment [START_REF] Ziegler | IBM experiments in soft fails in computer electronics (1978-1994)[END_REF]. Two main kinds of effects occur : the Total Ionizing Dose effects ( TID ) due to charge trapping in oxides which can cause threshold voltage shift and current leakage and the Single Event Effects ( SEE ) induced by a single ionized particle hitting on a sensitive area. Among these effects, the Single Event Latch-Up ( SEL ) and the Single Event Upset ( SEU ) are the most significant. The SEL is a destructive effect through the activation of a parasitic thyristor while the SEU results in a flipping of the information bits stored by latches. The SEL problem has now its solutions. We will here address on SEU effects. SEU originates many soft errors in ICs operating in space or high atmosphere as previously reported in [START_REF] Binder | Satellite Anomalies from Galactic Cosmic Rays[END_REF][START_REF]Analysis of Environmentally Induced Spacecraft Anomalies[END_REF][START_REF] O'neil | Single event upsets for space shuttle flights of new general purpose computer memories devices[END_REF], but also at ground level in terrestrial computer electronics as evidenced by IBM [START_REF] Ziegler | IBM experiments in soft fails in computer electronics (1978-1994)[END_REF] or Normand [START_REF] Normand | Single event upset at ground level[END_REF]. The consequences of this effect are enhanced by scaling and the emergence of blocks embedded in System-on-Chip (SoC), difficult to test. As a consequence the robustness of functional blocks is becoming a prior concern in integrated architectures, making of circuit hardening to the environmental constraints a new challenge.

Our approach puts aside special technological solutions. It consists in the implementation of rad-hard designs at the circuit level using available commercial technology. The process is unvaried but the design solutions are easily transferable.

In the following, we shall first examine the phenomenon originating the upset and its consequence on the data latch. Then the new tolerant structure is presented with the principles involved in hardening and its efficiency is evidenced. We conclude by a comparison using an equivalent redundant structure to analyze the performances as far as speed and area are concerned.

SEU effects on data latches

Upset phenomenon at transistor level

We will first briefly describe the Single Event Upset mechanisms and present the way to simulate its effects on CMOS. More details will be found in [START_REF] Peterson | Single Event Analysis and Prediction[END_REF][START_REF] Massengill | SEU Modeling and Prediction Techniques[END_REF][START_REF] Sexton | Measurement of Single-Event Phenomena in Devices and ICs[END_REF].

Three basic concepts explain SEU : energy loss, charge collection and transient upset. When an energetic ion passes through any material it loses energy through interaction with the semiconductor bound electrons. It creates a dense track of hole-electron pairs, which may recombine with no effect. But in the presence of electric fields, typically in reverse biased P-N junction, electrons and holes are drifted in opposite directions and collected at device junctions. The main consequence is a transient current pulse. Such an upset drives the drain voltage of PMOS or NMOS respectively to the high or low level. Thus, ICs performed with CMOS technology, have several sensitive areas localized under contact diffusions. It is necessary to check off all the SEU sensitive areas to predict SEU effects. Moreover the electric field dependence implies a variation of their location according to the logic state of the node. Summarizing, a voltage difference on a junction induces an electric field and so a sensitive area. In case of a hit on this area, contact voltage is driven to the corresponding substrate voltage ( high voltage for PMOS or low voltage for NMOS).

The physical evolution of this phenomenon is relatively complex, yet electrical simulations of the upset can be done in a simple way with a pulse current source located at the sensitive node giving a good representation of the SEU effects observed on ICs [START_REF] Massengill | SEU Modeling and Prediction Techniques[END_REF]. The current pulse is fixed at a 10 mA amplitude, 50 ps rise and fall times and a programmable duration to represent worst case conditions. Usually designers consider an upset duration between two or three hundred picoseconds.

Fortunately one another point is the random of the phenomenon joined to a low occurrence of the hits. So, we shall assume that just one upset (a single event upset) can happen at the time on the same sensitive area, excluding the case of multiple upsets.

These rules are used to identify and simulate the SEU sensitivity of a data latch in the next section.

Data latches and SEU

SEU effects on latches is a classical issue. The concern is the sensitivity of a standard data latch circuit to identify its level of vulnerability. This level is high.

If we consider a standard latch in static mode ( H=0, Hb=1 ), the Fig. 1 evidences the cell sensitive areas, state 1 corresponding to Q=G=1 and Qb=0 and state 0 to Q=G=0 and Qb=1. The sensitivity of the latch is characterized by logic state dependence. Sensitive area in state 0.

Figure 1. Latch design and its SEU sensitive areas

Simulations show, as expected, this high level of SEU sensitivity for the nodes Q, Qb and G. Figure 2 illustrates the results on node Qb with a 0.25 µm CMOS process and a post layout description, including parasitic capacitance extraction. The SEU simulations are achieved with a 50 ps current upset on node Qb and a latch in the logic state 1.

The current upset drives node Qb voltage to high level, turning the second inverter output Q and as a consequence G to low level. Thus, Qb is forced to high level through the first inverter, even after the current pulse has ceased. Feedback dynamics of data latches provoke a permanent bit flip in case of a transient upset.

Regarding the huge amount of data cells of the majority of ICs, designers in charge of radiation hardness have to cope with the SEU issue. We propose in the next section a way to improve the tolerance to the upset by revising the cell design.

The SEU hardened HZlatch

A few harden CMOS inverters and cells have been presented in the past few years [START_REF] Canaris | An SEU Immune Logic Family[END_REF][START_REF] Wiseman | Design and Testing of SEU/SEL Immune Memory and Logic Circuits in a Commercial CMOS Process[END_REF][START_REF] Velazco | Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits[END_REF][START_REF] Salager | Conception en vue du Durcissement des Circuits Intégrés numériques aux effets radiatifs[END_REF][START_REF] Monnier | Flip-flop Hardening for Space Applications[END_REF][START_REF] Roche | A design methodology to secure memories in Space environnement[END_REF]. Some are limited by their lack of robustness to the longest upsets, others present prohibitive areas. Our approach consists on providing SEU immunity by restructuring the data latch at the gate level.

The HZ inverter design

To attain SEU hardening assurance, we conceive a new inverter that we use to complete latches. This inverter is itself hardened against SEU through the use of two techniques: an information redundancy and a tristate double-output ( high impedance state gives the inverter name : HZ inverter ). Figure 3

Table 1. HZ inverter truth table

When the two inputs ( In1 and In2 ) are settled in the same logic state the circuit works like an inverter, with outputs at the same logical level ( Out1=Out2 ) a complementary one of the inputs, as the truth table shows. Now, if an error occurs above in the IC and inverts the logic state of one of the inputs, the outputs are tristating ; thus their logic states remain uncorrupted and the error propagation is stopped.

We take advantage of these properties in the new proposed SEU hardened HZlatch.

The HZlatch design

The way we design the HZlatch is similar to any basic data latch design comprising two cross-coupled inverters. Figure 4 shows how to put together the basic cells. Two HZ inverters are used in conjunction with pass gates to avoid feedback during write operation.

Redundancy and high impedance state provide both static and dynamic SEU hardening by cutting error propagation due to the feedback. A SEU is said to be static when it arises during hold state and dynamic during write operation.

Considering that the hardened latch of figure 4 is in hold state ( H=1 and Hb=0 ) and stores data so that nodes Q1 and Q2 exhibit a low state. As a consequence data nodes Q3 and Q4 are established in a high state, and data nodes Q11 and Q22 are low. For example if a hit occurs at one of node Q1 sensitive area, Q1 momentarily goes high. Then the outputs of the first HZ inverter, Q3 and Q4, are tristated. Thus a source of uncorrupted data remains because Q3 and Q4 are still high. These nodes drive the second HZ inverter, which assigns low state to its outputs Q11 and Q22. A recovery mechanism of node Q1 through the cell feedback is provided, thereby hardening the latch against single particle induced upsets. Similar dynamics are at work to harden the latch when an opposite data state is initially stored and when upset occurs at any of its sensitive nodes.

Dynamic hardening mechanism is similar. After the latch stored the right data, the design prevents any false information to be rewritten. For example any error on D1 has the same effect than any upset on Q1 ( respectively on D2 and Q2). The sole limitation is appearing at high clock frequencies. In this case an upset could last long enough to prevent a new state to be written, by tristating the first HZ inverter outputs during the whole write cycle.

Next section reports SPICE simulations for the purpose to confirm this approach.

HZlatch simulations

A layout of the HZlatch was completed using 0,25µm CMOS process ( see Fig. 5 ) and SPICE simulations were conducted after parasitic capacitance extraction. The upset is simulated on node Q1, using a current pulse of 10 mA amplitude with a duration up to 5000 ps. the purpose is to force its voltage to high level. The extreme case is illustrated in Figure 6 and confirms the intervention of hardness mechanisms (part 3.2.) Indeed node Q2 state is unchanged and due to high impedance effect nodes Q3 and Q4 hold on the high level; thus we verify that the low level of Q1 is restored as the upset current ceases, owing to recovery mechanism.

A simulation of the complementary upset on the same node Q1 ( see Fig. Exhaustive simulations were run on all the HZlatch nodes for a 10 mA amplitude and 5000 ps duration current; in all cases the cell was not flipped. These upsets are longer than upset durations generally reported in scientific literature ( 1000 ps for the longest ) showing that HZ latch is safe even in utmost conditions.

Comparison with usual designs

In order to evaluate the performances in terms of area and speed, the HZlatch must now be compared with an equivalent tolerant architecture based on a standard latch circuit. A general method to achieve an hardness efficiency of systems is the use of a Triple Modular Redundancy ( TMR ). Figure 8 presents the structure used : three standard latches are connected in parallel to the clock and data inputs while their outputs feed a voting gate. Any SEU arising in the latches will be corrected by the majority voting logic, implemented with a MUX structure as shown in Fig. 9.

A Vcc gnd B C V A B C V 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 A Vcc gnd B C V A B C V 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 A B C V 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

Figure 9. Majority vote module

Such a design is not totally SEU proof. Indeed an upset at the voter level is always possible, even if it will be corrected rapidly when the upset ceases. Another problem may appear if the latches are not continuously clocked; in that case errors can "accumulate" in the TMR triplet ruining its functionality. This eventuality is not coming in sight with the HZ latch which is continuously correcting any upset. Now we evaluate the worst delays to invert the data stored by the standard latch, the redundant circuit with propagation time through the voter and the HZ latch. These delays are estimated from mid-point of the inputs change to mid-point of the outputs voltage swing. The whole SPICE simulations are run with post layout extracted view of a 0.25 µm CMOS process. The simulation results are listed in Table 2 with the respective cell areas.

Table 2. Delay and area comparisons

This comparison shows that to achieve a similar SEU hardness, the HZ latch presents a delay improvement of 10% and an area reduced by more than half compared to an equivalent TMR design. Besides the HZ latch has an improved reliability.

Conclusion

We have proposed a new data latch circuit ( the HZlatch ) devoted to work in an harsh environment by restructuring the design at the transistor level. The hardening method stops error propagation inside the cell by using high impedance state and provides an "integrated redundancy" in the shape of a recovery mechanism. The HZlatch can be advantageously compared to the full traditional TMR structure; this make the HZlatch a good candidate for its use in embedded systems like SoC with specific reliability constraints.

Figure 2 .

 2 Figure 2. Upset on node Qb

Figure 3 .

 3 Figure 3. HZ inverter design

Figure 4 .

 4 Figure 4. HZlatch design

Figure 5 .Figure 6 .

 56 Figure 5. HZlatch layout We report here response curves during upset on node Q1. The results are similar for the other nodes.

Figure 7 .

 7 Figure 7. Upset ( 10 mA, 5000 ps ) on node Q1

Figure 8 .

 8 Figure 8. Tripple Modular Redundancy Structure

Delay

  details its design and Table 1 its truth table.