Keywords: WSN, régulateur de tension, émetteur courte portée WSN, LDO, Short-range transmitter, Data-rate

In the modern devices Ultra-low power consumption is the survival key for the energy-harvested sensor node. The reduction of the power budget can be achieved by mixing different low-power techniques at three levels of abstraction: transistor level, circuit level and system level. This thesis deals with the analysis and the design of Ultra-Low Power (ULP) circuits suitable for Energy-Harvesting Wireless Sensor Networks (EHWSN). In particular, voltage regulator and RF transmission circuits are examined. The former is the main block in power management unit; it interfaces the transducer circuit with the rest of the sensor node. The latter is the most energy hungry block and thus decreasing its power consumption can drastically increases the sensor on-time.

Titre : Conception des circuits à très faible consommation pour des applications Harvesting

Résumé : La très faible consommation dans les appareilles modernes est le facteur-clé pour les capteurs alimentée par une source d'énergie récupérée. La réduction du budget de puissance peut être atteinte grâce à différents techniques lié à trois niveaux d'abstraction : transistor, circuit et système. L'objet de cette thèse est l'analyse et la conception des circuits à très faible consommation pour des réseaux des capteurs sans fils. A' régulateur de tension et an émetteur RF ont été examiné. Le premier est le circuit principal pour la gestion de puissance ; il agit comme interface entre le transducteur et les autres circuits du capteur. L'metteur est le circuit que exiges le plus de puissance pour fonctionner, donc une réduction de sa puissance il permet une augmentation de la vie opérationnelle du capteur.

In chapter 4 the design ow of OOK modulation transmitter is addressed. The low targeted radiated power of -15 dBm poses a severe limitation for the global transmitter eciency. The rst part of the chapter is dedicated to the study of classical cascaded architectures where the oscillator (VCO) is directly connected to the input of the power driver. The trade-o between the supply voltage and the matching network is described highlighting the diculty to integrate the passive elements of matching network when the supply voltage for the power amplier is about 1 V and the peak to peak output voltage required over a 50 Ω is in the order of tens millivolts. To circumnavigate this problem a current reuse transmitter is proposed where the power driver and the VCO are stacked and the same bias current is used. With this architecture the supply voltage can be tuned between the two circuits to achieve the best trade-o between the power consumption and the performances of each circuit.

Résumé

La demande toujours croissante d'amélioration de la qualité de vie avec la création des environnements intelligents, a permis la diusion des reseaux des capteurs sans l. Les applications envisagées peuvent aller de la domotique à l'industrie, de la medicine à l'agriculture. Le probléme principal pour ces types des capteurs est le remplacement des batteries, étant donné que l'installation pourrait avoir lieu dans des environnement hostiles. Donc la recherche d' autres types des sources d'énergie qui peuvent remplacer les batteries a attiré l'attention de la Communauté scientique internationale. Nombreux sont les sources à partir des quelles il est possible obtenir de l'énergie électrique pour des systèmes miniaturisés. Néanmoins la faible énergie mise à disposition par des sources non-conventionnelles, pose un vrai dé pour les concepteurs s'ils veulent augmenter la durée de vie des systèmes. C'est seulement par l'utilisation des circuits à trés faible consommation que les capteures autonomes peuvent représenter un choix valable pour le marché. La réduction du besoin d'énergie peut être atteinte en mélegeant diérentes tecniques à trois diérent niveaux d'abstraction : transistor, circuit et système. L'objectif de la thése est la conception et l'analyse des circuits à trés faible consommation appropriés pour des applications d' Energy-Harvesting Wireless Sensor Networks (EHWSN). La première partie détaille le régulateur de tension, qui est le circuit fondamental du bloc dédiée à la gestion de la puissance. La deuxième partie est dédié à l'analyse et à la conception d'un emetteur RF, qui représente le circuit avec la consommation de puissance la plus haute présent dans le capteur. Par conséquent une reduction de la consommation de ce dernier circuit, baisse considérablement la démande d'énergie du systeme dans sa totalité. La thése est ainsi organisée : Le chapitre 1 décrit les sources de récupération d'énergie disponibles dans l'environnement, soulignant les avantages et les inconvénients quand elle sont appliquées à des circuits miniaturisés. La deuxième partie est dédiée à l'étude des techniques permettant la réduction de la consommation de puissance. Le chapitre 2 est dédié à l'étude des réseaux de capteurs sans l. Un cadre genéral de leur architecure est donné. L'équation pour calculer la puissance radiative nécessaire pour couvrir une certaine distance est donnée. En dernier lieu le rapport cyclic optimale est derivée à partir de l'énergie nécessaire, de la qualité du canal de communication et de la quantité des données à transmettre. Le chapitre 3 décrit la conception d'un régulateur Low-DropOut (LDO) à haute ecacité. L'attention est centrée pour obtenir une trés faible consommation de puissance sans sous-estimer la précision du réglage de tension. Pour obtenir un bonne réglage de tension, l'amplicateur d'erreurs doit avoir un slew-rate élevé, et la réponse en fréquence de la boucle, donc la vitesse de réglage du circuit, doit etre rapide. Les solutions adoptées pour surmonter le probléme sont un amplicateur d'erreur de classe-AB, avec un courant de polarisation qui s'adapte au courant de sortie du régulateur. L'ecacité est élevée pour toutes les conditions du courant de sortie avec moins d'impact sur la consommation de puissance globale du circuit. La stabilité de la boucle est assurée dans toutes les conditions par un buer de courant et une capacité Miller, meme pour un courant trés faible de stand-by en sortie. Le chapitre 4 décrit la conception d'un émetteur avec une modulation OOK. La faible puissance émise de -15 dBm limite l'ecacité globale du systém.

La premiére partie du chapitre est dédiée à l'étude d une structure classique en cascade, où la sortie du synthétiseur de fréquence (VCO) est directement connectée à l'entrée de l'amplicateur de puissance. Le chapitre continue présentant les compromis de conception pour le réseau d'adaptation quand la tension d'alimentation est élevée alors que la tension aux bor de la charge de 50 Ω est de quelques mV. Une architecture empilée est nalement proposée, où le VCO et le driver de puissance partagent le meme courant de polarisation, an de répartir la tension d'alimentation entre les deux circuits. The concept of making electronic devices electrically independent of expensive, not always available, and exhaustible sources is not new and it has wider applications that are very common. Nowadays it is easy to nd large surface solar panels or wind turbines especially in rural environment. In nature many are the sources from which it is possible to obtain electrical energy and several are the environments where harvesting process can nd use whether internal or external. Solar energy, thermal energy, vibrational energy and radio-frequency (RF) energy are the main sources exploited to replace the batteries in micro-scale or nano-scale electronic devices. Excluding solar and thermal energy, kinetic and RF source are not suitable for large-scale applications due to their low energy density. In the next section these energy sources will be briey introduced by describing the advantages and the drawbacks.

List of Figures

Solar Energy

The solar harvesting is based on the Photo-Voltaic (PV) eect where photon energy is used to excite an electron from its ground state to an excited state. Most of solar panels are made of by a semiconductor material; when the photon strikes the photo-cell an electron-hole pair is formed, therefore the semiconductor conductivity increases. To avoid the recombination of the two particles a PN junction is needed (N-type and P-type semiconductor overlapping). Basically a solar cell is an unbiased diode that is exposed to the light. If the N and P regions are connected by a load (see Fig. 1.1), power can be extracted from the device. To extract the maximum power from the PV cell the system has to be able to change the PV cell load, because an optimum value is needed for dierent illumination conditions. A DC-DC converter should be placed between the PV array and the load (see g. 1.2) for the Maximum Power Point Tracking (MPPT). One of the main problem with this type of source is the power density variability due to the incident solar luminosity. In outdoor condition high power density is achieved with 100 mW/cm 2 while in indoor environment the irradiated power decreases drastically to 0.5 mW/cm 2 [TTKS14] [START_REF] Wan | Review on energy harvesting and energy management for sustainable wireless sensor networks[END_REF]. Currently, the main eorts in PV harvesting sensor node

Thermal Energy

Thermo-electrical basics are used in modern devices to generate electrical or thermal energy depending if Seedback or Peltier eect are exploited as depicted in g. 1.3. The Seedback eect describes a phenomena that produces a voltage from a temperature gradient. Applying a temperature dierence ∆T = T C -T H across two metal or semiconductor junctions a voltage V is generated into the circuit

V = α SB ∆T (1.1)
where α SB is the Seedback coecient associated to the material properties. The Peltier eect produces the opposite phenomenon. The current generated by a voltage applied across two metal junctions causes the electron movement from one side to the other side. Consequently a heat absorption occurs at one junction and a heat dissipation at the other one. The amount of heat removed per time unit from one junction to the another one is given by

Q = Iπ P el (1.2)
where I is the circuit current, π P el is the Peltier coecient that has to be measured in isothermal condition for the two metals. It is clear that the material composition, the surface and geometry of contact between the two elements are the main parameters to achieve high conversion eciency. In [START_REF] Rozgi¢ | A miniaturized 0.78-mw/cm2 autonomous thermoelectric energy-harvesting platform for biomedical sensors[END_REF] a thermoelectric energy harvester demonstrates to be able to generate 0.78 mW/ cm 2 with 3.5 K of gradient temperature. With such of power it is possible to accomplish sensing task in 32x32 mm for body area network with comfort wearability. One of main drawbacks of thermal source is its power density variability due to a not constant temperature gradient. Moreover the small output voltage (≈ 40 mV) requires step-up circuit to get a usable voltage.

CHAPTER 1. LOW POWER TECHNIQUES FOR ENERGY HARVESTING SYSTEM 1.1.3 Kinetic Energy Kinetic harvesting sensor exploits the energy generated from movement, displacement or mechanical strain to produce electrical energy through electromagnetic, piezoelectric or electrostatic mechanisms.

Piezoelectric mechanism

Piezoelectric materials exhibit the capacity to generate electrical energy when subjected to a mechanical strain. The dipoles present inside a piezoelectric material becomes polarized when an external force is applied, and the polarization degree is proportional to the strain.

Electromagnetic mechanism

The conductor movement or the coil rotary in electromagnetic eld is used to generate a potential dierence which follow the Faraday's law. When an electric conductor is moved through a magnetic eld, an electromotive force is induced between the ends of the conductor. This voltage is proportional to the electromagnetic eld variations in the time.

Electrostatic mechanism

A variable capacitor is used to generate an electrical energy when a external vibration is applied. For a charge-constrained device, the plates movement causes an increasing or decreasing voltage across the capacitor, since the charge has to remain the same. In [MPW + 17] the breath movement is used to monitor the patient respiration. The frontend transducer is a piezoelectric material-based sensor. The harvested source is able to sustain a power consumption about 800 µW when the impulse radio ultra-wideband transmitter is active.

Radio-Frequency Energy

Probably nowadays the Radio-Frequency (RF) energy is the most easily available source: the mobile phone, Wi-Fi and Bluetooth connections. The RF harvesting devices are equipped with a antenna, picking-up the RF wave. The corresponding AC voltage is then transformed in a more suitable DC voltage for the electronic blocks by a rectier circuit. The conversion eciency and the voltage available at rectier output depend mainly on the channel communication qualities, on the antenna performances and on the rectier losses. As the energy available is small a storage element is mandatory to achieve sensing and transmission operations. The device dimensions are mainly tied to the antenna design, and the conversion eciency relates on the antenna gain and on power level of the incoming signal. The average energy density of RF source is about 1 µ W/cm 2 , but the RF-DC conversion circuit is able to generate voltage in the order of fews volts (1.4 V -3 V) with an output power of hundreds of micro-watts. The low energy available from the environment sources (Tab. 1.1) poses an hard challenge for the designers, to guarantee the required performances. Designing nano-watt or microwatt circuits surely can ensure long lifetime devices but at cost of poor performances. However there are several approaches to reduce the power consumption in radio and system circuits, which extend at dierent design level. In the next section the main techniques to design ultra-low power (ULP) system are introduced. The technology progress in CMOS fabrication has allowed the designers to develop several techniques in order to reduce power consumption in modern devices; not only at the transistor level but there are three dierent abstraction levels to address, in order to achieve low power consumption for the sensor node:

CHAPTER 1. LOW POWER TECHNIQUES FOR ENERGY HARVESTING SYSTEM

CMOS level: Scaling down, thick metal layer, ultra-low leakage MOSFET Circuit level: weak inversion, current reuse, multi-threshold CMOS (MTCMOS) System approach: wake-up protocol.

CMOS level

It is well-known that the transistor size scaling is described by the Moore's law: the number of transistors into an integrated-circuit chip is doubling approximately every two years without correspondingly increasing the chip costs. The reduced channel length (L channel ) in metal-oxide-semiconductor FET increases the cut-o frequency as the parasitic capacitances decrease proportionally to the L channel

C gate = ox o t ox L channel (1.3)
where C gate is the MOSFET gate capacitance, ox is the dielectric constant of silicon oxide, o is the permitivity of free space and t ox is the oxide thickness. Considering C gate as the most important parasitic capacitance inside the MOSFET the cut-o frequency f t can be written as:

f t = g m 2πC gate (1.4)
where g m is the MOSFET transconductance. The f t is the frequency at which the short circuit small-signal current gain is unitary; g. 1.4 plots f t versus the normalized drain source current density for ve technology nodes. RF circuits (Power amplier, Oscillator, Mixer,etc) take advantages from the MOSFET scaling because the transistor exhibits higher current gain for the same operation frequency. Therefore same performances can be achieved with less current and lower power consumption consequently. Also the threshold voltage decreases with the size downscaling, because the reduction in oxide thickness allows lower dierential potential needed to the MOSFET gate, in order to create the conduction channel. As consequence, it is possible to decreases the supply voltage needed to put the transistors in saturated region. The main benet when the circuit operates at lower power supply voltage is the reduction in active power dissipation P act for switched topology circuits. P act is proportional to the square of supply voltage V DD , to the capacitors involved in charge and discharge operations and to the switching frequency f switch :

P act = C switch V 2 DD f switch (1.5)
It seems clear from eq. 1.5, that with the possibility to operate at lower V DD the power consumption decreases. However as the distance between drain-source is reduced and the oxide is thinner, the probability that an electron moves in transistor o-state is higher and thus the leakage current increases degrading the power consumption performance in sleep mode; especially in ultra low duty-cycled system, where the circuit is o most of the time, the leakage current impacts the power budget; ultra-low leakage MOSFET can help with reducing the o-state current. Moreover the higher chip cost in deeply scaling technology has to be considered especially when low cost system is targeted.

Thick metal layer

Generally speaking the reduction of parasitic resistance allows to reduce the static power dissipation. This is the case for the drain source MOSFET resistance R DS in switching circuit and also for the inductor and capacitor parasitic resistance. In energetic circuit SYSTEM Figure 1.5 Combinations to achieve 8 nH inductance [START_REF] Vanukuru | High-Q inductors utilizing thick metals and densetapered spirals[END_REF] where W is the metal width and N is the numbers of turns.

(LC oscillator, tuned amplier, buck/bust voltage converter) the impact of lossy elements can be traduced through the quality factor Q [Raz]

Q = 2π EnergyStored EnergydissipatedperCycle (1.6)
High quality factor is preferable because the energy dissipated in lossy elements is low. A reduction in power consumption can be achieved by using high-Q elements and LC oscillator is a perfect example. In LC oscillator the oscillation is assured if the losses (the parasitic series resistances R s of Inductor and Capacitor) are counterbalanced by an active element as the MOSFET transconductance g m .

g m ≥ 1 R s (1.7)
In rst approximation the g m is proportional to the drain-source current. Therefore for small value of parasitic resistance (high-Q) the g m needed is lower and the drain-source current decreases proportionally. At low to medium frequency oscillation (from 400 MHz to 15 GHz) a customized inductor can helps in power consumption reduction with higher Q. In [START_REF] Vanukuru | High-Q inductors utilizing thick metals and densetapered spirals[END_REF] thick metal and dense tapered spiral inductor shows quality factor improvements for 10 GHz frequency oscillation. Fig. 1.5 depicts dierent geometries to get 8 nH inductance with the highest Q at the same generated frequency.

Circuit Level MOSFET operating region

Traditionally, the MOSFET is mostly used in strong inversion (SI) region with a drain-source current in the milli-Ampere range where the gate-source voltage V gs has to be greater than the threshold voltage V th

V gs >> V th (1.8) CHAPTER 1.

LOW POWER TECHNIQUES FOR ENERGY HARVESTING SYSTEM

In SI, for N-type Mosfet, I DS is proportional to the square of the eective gate-source voltage

I DS = 1 2 µ n C ox n W L (V gs -V th ) 2
(1.9)

Where µ is the carrier velocity, C ox is the oxide capacitance, n is a slope factor, W and L are the width and the length of conduction channel. Only from the second half of 90s [START_REF] Enz | Cmos low-power analog circuit design[END_REF], with the diusion of portable devices the weak inversion (WI) has been taken in consideration to address low power consumption in integrated circuit. In fact when V gs is lower than

V th V gs << V th (1.10)
the transistor operates in WI with an I DS in the range of micro-Ampere to the nano-Ampere. In this case the current is not more governed by a square law, but it follows an exponential behavior

I DS = 2nµC ox V 2 t W L exp V gs -V th nV t (1.11)
where V t is the thermal voltage. However the passage from SI to WI is not abrupt and the two regions are separated by the moderate inversion (MI), where V gs diers above or below V T H to a few tens of mV. Therefore the three regions represent three dierent degrees of MOS channel inversion. To give a coherent circuit design with the three level of channel inversion the Inversion Coecient (IC) has been introduced, which allows a continuous design ow from the WI to the SI. The IC [START_REF] Binkley | Tradeos and optimization in analog cmos design[END_REF] can be found by the drainsource current, divided by the product of the shape factor S = W L and the technology current

I o = 2nµC ox V 2 t IC = I DS I o S
(1.12)

The IC ranges from 0.01 in WI to 100 in SI and the center value is 1 at the middle of MI. Therefore every value of IC corresponds to a precise level of inversion with a well dened bias point. The transistor width is calculated from the choice of the channel length L, the drain-source current and the inversion coecient. Depending on the circuit performances, every operating region can accomplish a specic trade-o as shown in g. 1.6. Many works [START_REF] Enz | Nanoscale mosfet modeling for low-power rf design using the inversion coecient[END_REF] [TSM15] [START_REF] Shameli | Ultra-low power rc design using moderately inverted mosfets: an analytical/experimental study[END_REF] demonstrate that designing analog or radio-frequency circuits in MI ensures the best trade-o between power consumption, gm I ds eciency, low voltage design and AC response. Fig. 1.7 shows a cascoded single stage Operational Transconductance Amplier OTA where the transistors operate in saturation region. When the MOSFET are biased at the low side of SI (IC = 10) a V ds,sat = 0.24 V for each transistor can be assumed, while when the low side of MI (IC = 0.1) is considered the V ds,sat = 0.12 V. The only parameter analyzed is the minimum supply voltage needed to bias each transistor in saturation, and the reduction of V DD,min is quite evident. The main drawback when MOSFET operates in WI is the poor frequency response due to a large parasitic capacitance forced by the large MOSFET size. Moreover WI introduces a pronounce dependence en process and temperature variations.

Current Reuse

The static power consumption in electronic circuit is given by the supply voltage V DD and the bias current I bias owing from the supply voltage to the ground

P stat = V DD I bias (1.13)
If two cascaded circuits (A and B) are considered (Fig. 1.8) the total power consumption is equal to the sum of the single consumption: P stat,tot = P stat,A + P stat,B = V DD,A I bias,A + V DD,B I bias,B

(1.14)

The P stat,tot is reduced if the four variables are optimized. The main disadvantage is that the generation of two separate supply voltages increases the system complexity and power budget. In many case the chip size constraint and/or the energy available reduce space freedom degree in the design. Typically a single supply voltage is available for all circuit blocks. Therefore the optimization, from the supply voltage point of view, cannot be achieved completely and a lot of power is wasted. To overcome this problem and if an adequate supply voltage is available, stacked structure can allow power consumption reduction. In this case the bias current is recycled (reused) from the top circuit to the bottom one and the total power consumption is

P stat,stack = V DD,stack I bias,stack (1.15)
The condition to achieve lower power consumption in stacked topology is V DD,stack = V DD,A = V DD,B and I bias,stack = I bias,A = I bias,B . Moreover some precautions have to be taken against cross-talk phenomena, noise and high frequency loop. In [START_REF] Taris | Design of low power cmos rf building blocks[END_REF] a stacked LNA-VCO is presented, where each block achieves comparable performances with the state of the art of stand alone circuit; a LC lter is inserted between the two circuits to present high impedance at the frequency of interest avoiding cross-talk degradation. The reuse concept can be readapt to circuit level as in [?]. The RC relaxation oscillator used to generate the time reference to the system is reused to implement reading-out circuit for the measurement of the Relative Humidity. Therefore the oscillator accomplishes two tasks saving power consumption and area occupied.

Multi-threshold CMOS

The leakage power consumption has become a serious problem in below 100 nm technologies. In multi-threshold CMOS (MTCMOS) circuit, high-V T H transistors are used to block the leakage path because of their low leakage current [START_REF] Singhal | Analysis and comparison of leakage power reduction techniques in cmos circuits[END_REF]. Basically it shutsdown a part of the circuit, disconnecting the main blocks from the power supply. Fig. 1.9 illustrates a typical application where high threshold transistors cut-o the NAND logic circuit. However this technique implies an increase in cost process due to an extra mask for the two dierent threshold voltages. Moreover there is a trade-o between the size of high-V T H transistor and the performances degradation of the main circuit.

System level

Wake-up scheme and duty-cycled radio As it will be described in the next chapters the most hungry part in wireless sensor node is the transceiver circuit. A large number of papers suggest to keep the nodes transmitter part in low-power sleep mode for most of the time, allowing the node to operate at highest power consumption level only for a very short time. Wake-up scheme is a largely adopted technique to reduce the energy consumption extending the sensor node lifetime. Fig. 1.10 depicts the time-slot division for waked-up sensor node. The active time-slot includes:

start-up time where auxiliary circuits generate the wake-up signal for the transmission/reception part. After the radio-frequency circuits need a settling time to achieve proper operation (especially for the frequency synthesizer). transmission/reception time where the communication between the sensor node eectively takes place. To reduce the required overall energy both start-up and transmission slots have to be as short as possible for a lower power consumption. In [JLBS15] a 5.8 nW wake-up timer CHAPTER 1. LOW POWER TECHNIQUES FOR ENERGY HARVESTING SYSTEM Figure 1.10 Wake-up scheme timeline. is presented and it is suitable for EHWSN, whereas in [START_REF] Thirunarayanan | Reducing energy dissipation in ulp systems: Pll-free fbar-based fast startup transmitters[END_REF] the long start-up time phase-locked loop (PLL) frequency synthesizer is avoided using a fast lm-buck acoustic wave resonator with a time reduction of ≈1000X. However the system can be further optimized adopting duty-cycled operations during the transmission time. In this case the radio block is turned on/o with a rating that depends on the duty-cycle value:

DC = T on T on + T of f (1.16)
Aggressive DC in the range of (1-5)% can be adopted in burst communication mode, where a large amount of data is transmitted in short time with high data-rate.

CHAPTER 1. LOW POWER TECHNIQUES FOR ENERGY HARVESTING SYSTEM

Conclusion

In this chapter a description of the dierent energy harvesting sources usable for small scale applications has been presented. The low energy density available and the high variability pose a big challenge for the designers. Low-power design techniques are mandatory to extend the devices lifetime. The second part of chapter has described these techniques highlighting the advantages and the drawbacks. The three level of optimization, transistor, circuit and system, can be combined to achieve the best trade-o between the performances and the power consumption. In the next chapters a system overview and a design ow for very ecient voltage regulator and ultra-low power transmitter are presented.

Chapter 2

System Approach

The technology progress occurred in the last ten years in highly integrated microelectronic circuits, sensors, actuators, and wireless communications technology allowed the dissemination of wireless sensor network (WSN) in several domains:

Environmental Monitoring

WSN can be used for forest surveillance, weather forecasting. It is a natural candidate, because the variables to be monitored are usually distributed over a large area. In addition WSN can facilitate the measurement of a large variety of environmental data for a huge number of applications such as agriculture, meteorology, geology, zoology, etc.

Health monitoring

WSN could potentially provide better health-care delivery. They could improve the interaction between the patient and the medical sta. Several physiological parameters can be monitored, as (hearth condition, blood pressure, blood glucose, organ monitor, cancer detector). When the sensors are implanted for healthcare purpose, they are called Body Sensor Network (BSN).

Industrial Sensing

The industrial sector is one of the most involved player for the development of WSN. With the possibility to acquire information in real-time, unexpected failures can be avoided improving production quality and reducing costs. One of the main use is in the food industry to monitor the food supply chain.

Home Security Domestic represents another potential area for WSN. The "smart home" can regulate the room temperature, control air quality, adjusting lighting. Sensor networks can also improve the security of the house by sending an alarm message to the resident when it detects intruders, gas leakage, re occurrence or other safety risks. WSN can generally be described as a network of nodes that cooperatively sense and may control the environment enabling interaction between persons or computers and the surrounding environment. In spite of their versatility, the main constraint is the energy needed for the operation, specially when WSN are deployed in hostile environment or over a large area making the battery replacement very dicult, expensive or even impossible. For example, the study carried-out in [START_REF] Karli | Power consumption and battery life study of a two-node wireless sensor system[END_REF] shows the battery duration for WSNs with ZigBee/IEEE 802.l5.4 protocol. This standard has been developed by the Institute of Electronic and Electrical Engineer (IEEE) for low-power, low data-rate wireless personal sensor networks (WPSNs). The most adopted transmission frequency is 2.4 GHz with max data-rate of 250 kits/s and QPSK as transmission modulation. The IEEE 802.l5.4 standard is used as a base for developing ad-hoc standard as in the case of ZigBee. ZigBee protocol adds dierent enhancements as authentication valid nodes, encryption for security and data routing. Moreover ZigBee supports energy harvesting technology for no battery supply. Therefore one of the main problem of this standard, even if the low power consumption is one of the key point, remains the battery duration. In [START_REF] Karli | Power consumption and battery life study of a two-node wireless sensor system[END_REF] the study is based on the Peukert's law where the battery life is calculated as

L = C IH k (2.1)
where L is the time in hours for a given rate of discharge, H is the discharge time in hours, C the battery capacity in Amp.hours, I current in Amp and k Peukert exponent parameter which is a unique number for each battery. The experiment is conducted for three dierent batteries with dierent capacities. The communication distance is about 9 m and the data transmission is continuous. The results are summarized in Fig. 2.1 for I = 2.3 mA and k = 1.25. Fig. 2.1 shows that, for 10 years of operation a battery with 320 Ah capacity is needed. However such type of battery exhibits large sizes; it is therefore not suitable for high integrated applications. After a rst wave, WSNs have meet a stop in the popularity due to the size limitation. WSN have found a second youth with the technology progress in energy harvesting (EH) domain, where the circuits responsible of energy conversion have assumed sizes more and more tiny easily tting the request of smaller devices. Therefore, the possibility to have independent small sensor has open the future for new opportunities. The markets for WSNs invoices $ 552.4 millions in 2012 with a forecast of $ 14.6 billions in 2019. The Fig. 2.2 shows the trend of devices powered by EH system used in WSN. sectors exhibit an growth in the number of employed devices.

To make a sensor networks adaptable for a wide range of applications, the following requirements should be addressed:

Low Cost: The utility and scalability of a WSN highly depend on its density, which means large number of sensor nodes in the assignment area. To make the installation cost eective, the cost of individual sensor node should be extremely low.

Low Power: Nodes must be able to ensure a permanent connectivity and coverage for long periods, up to 10-20 years, without service interruption. Low power consumption represents one of the main challenge in modern devices, and it is of great importance when the sensor is supplied by low density energy source. Small Size: WSNs are desired to replace cables that are often impracticable. Therefore, the size of the sensor node must be small enough in order to allow the WSNs to monitor the environment in a discreet and transparent manner. However nowadays as introduced in the Chapter 1, the energy available from the harvesting transformation is not sucient to power the sensor node in continuous mode operation. For example the harvested power from vibration in industrial application can easily achieve 100 µW/cm 2 [RM10], but modern sensor node in transmission mode requires about 5 to 10 mW depending on the application. Fig. 2.4 shows that if one hand WSN requires less power thanks to development technological, on the other hand high ecient harvesting circuits allow to maximize the low energy available from the environmental sources.

However until now, technologies limitation (for example leakage current, process deviations) and performance constrains (noise, PVT variations) prevent the two curves to reach a intersection point. Actually a continuous autonomous operations can not be therefore assured. The sensing and data communication reliability can be assured only if sensor node operates for a fraction of total time. Therefore the two curves can approach, because micro-watt power availability is able to sustain operations in the range of mW. The building block diagram of an EH sensor node is shown in the Fig. 2.5 The electrical energy coming from the harvest transformation can be used to directly supply the sensor node or stored into a supercapacitor or a rechargeable battery. Although in some applications it is possible to bypass the energy storage, in most of the case the storage component acts as an energy buer for the system, with the main purpose of accumulating and preserving the energy. In order to manage the energy available from the storage element, the power management unit (PMU) has to be designed to extend the sensor lifetime. It controls the level of stored energy and at the demand of power depending on the adopted protocol, it supplies the sensor and/or the other circuits. The environmental information sensed is then transformed into digital information by the ADC and stored in the memory. In general the sensing and the data transmission are not accomplished at the same time, because the transmitter is the main power hungry block and the energy available is not enough to guarantee the two operations at the same time. Finally the data transmission can be validated internally by the PMU or externally on demand by the users.

Energy Management

The purpose of this work is to design low-power circuits for RF-energy harvesting WSN. In particular low drop-out voltage regulator and transmitter block have been designed. A framework at the system level can facilitate the circuit design. As briey introduced an energy buer (rechargeable battery or super-capacitor) is mandatory for duty-cycled power manager to stock the energy when the system is in idle mode and then make it available when requested. A simple PMU introduced in [PCFP14] is depicted in Fig. 2.6. To supply the regulated voltage to the RF front-end blocks, PMU uses dierent circuits to manage the stored energy. Voltage limiter is used to limit the maximum voltage with a safe margin. The voltage sensor veries that the voltage across the capacitor is between two dened bends V low and V high . When the voltage stored into the capacitor reaches V low , the PMU turns-o the voltage regulator and the system is in idle mode. During the idle mode the PMU draws a little bias current due to the monitoring circuits that are continuously on to ensure proper operation. When the voltage capacitor reaches V high , the PMU turns on the voltage regulator, the current ows from the capacitor to the voltage regulator output and the sensing operation and data transmission can take place. It seems clear that in the case of linear voltage regulator, where the regulated output voltage is obtained "loosing" a part of input voltage over a variable resistor, the stable PMU output voltage V reg has to respect the following condition

V reg < V low < V high (2.2)
where V reg depends on the application specications (transmission distance, quality and speed of transmission) and on the circuit architecture (stacked topologies, technology reliability), V low depends on the voltage regulator performances and on the minimum input voltage for which the regulation is ensured, V high can be obtained by the system energy analysis. Fig. 2.7 shows the energy prole (top gure) of harvesting sensor node where the CHAPTER 2. SYSTEM APPROACH Figure 2.6 Power management transistor level schematic implemented in [START_REF] Papotto | A 90-nm cmos 5-mbps crystal-less rf-powered transceiver for wireless sensor network nodes[END_REF] transmission time t on is less than the idle time t of f . In this case high power hungry circuits as frequency synthesizer and power amplier can be sustained by low power source as RF energy harvesting. The bottom graph in Fig. 2.7 shows the transient of voltage stored in the capacitor and the voltage at the regulator output. During t of f the sensor node is in harvesting mode and the capacitor is charging. The charging time depends on source signal quality. During this time interval the energy cost of monitor circuits has to be very low in such way to preserve the capacitor charge. The energy stored in the capacitor C is given by

E C = Q f Q i Q C dq = 1 2C (Q 2 f -Q 2 i ) (2.3)
where Q f is the charge stored at V high and Q i is the charge stored at V low . The energy stored in the capacitor can be rearranged as

E C = C 2 (V 2 high -V 2 low )
(2.4)

The energy needed for the data communication, assuming OOK modulation scheme for the transmission circuit (PA,VCO), and continuous operation during modulation for the other circuits to reduce start-up time can be written as

E transmission = E T X + E reg = (pP DC,T X + P DC,system )t on + (I load V drop )t on (2.5) CHAPTER 2. SYSTEM APPROACH
The above equation is obtained assuming the following hypothesis :

The transmitter block is responsible of the DC power consumed P DC,T X modulated by the probability p to transmitting a '0' or '1' data bit. P DC,system includes the DC power consumed by the control circuits As it will be explained in the next chapter, a linear voltage regulator has been chosen to transform the unregulated input voltage to the regulated output one.

The power dissipated by the voltage regulator is mainly due to the voltage dropped across the pass element V drop and to the load current I load that ows from the input to the output. As I load is quite high, due to the bias current drawn by the transmitter, the energy required by the regulator can not be neglected. Surely the energy required by the transmission block has to be equal to the energy stored in the capacitor

E transmission = E C (2.6)
therefore from the upper equation is possible to nd the storage voltage V high

V high = 2t on C (pP DC,T X + P DC,system + I load V drop ) + V 2 low (2.7)
Observing the above equation V high relies on dierent parameters: the size of the storage capacitor C, the power consumed by the transmitter, the type of modulation and also the amount of data to be transmitted. Indeed t on is obtained by the ratio between the data packet length and data-rate. It is interesting to note that V high value impacts the regulator energy eciency. Without entering into detail,because voltage regulator is the subject of the next chapter, the energy eciency can be writen as

η energy = V reg I load t on V in I load t on = V reg V in (2.8)
V in is not xed but decreases from V high to V low . The above equation states that the three voltage values V reg , V high and V low have to be as close as possible in order to not deteriorate the regulator eciency.

2.2

Link budget, data rate and duty cycle.

Required link Budget

Generally the power consumed by the power amplier (PA) to cover a given distance is the main contribution to the power dissipated by the transmitter block. Outdoor sensors are generally 100 m spaced-out and the communication is almost free of obstacles. On the other hand, in indoor network the transmission antenna has to cover a range about of 5-10 m and the signal quality could be degraded by walls. Dierent is the situation for BWNs where the distance does not exceed 1 m. The PA DC power is strictly dependent on the RF output power level needed for the applications. The rst step in the transmitter design concerns the estimation of the power radiated P rad at the PA output. At rst glance, the required P rad can be obtained as follow:

P rad = P RX -G antenna -P L = P RX -G antenna -20 log λ 4πD
(2.9) where P RX is the receiver sensitivity, G antenna is the antenna gain, λ is the wave length for the carrier frequency and D is the communication distance. The gain of a typical surface mount antenna can be estimated at 0 dB for a frequency carrier of 2.4 GHz while the path loss (PL) terms in free space can vary between -22dB to -30dB for a distance D between 1m to 10m. The last term in the right side of the eq. 2.9 P RX is almost dicult to calculate [START_REF] Bensky | Fundamentals of rf system design and application second edition[END_REF] because it relies on several variables:

P RX,dBm = N in + N F + 10 log(B) + (P redicted S N ) => P RX,linear = N in × N F × B × S N
(2.10) where N in represents the input noise density originated on the source resistance for example antenna equivalent resistor. N in = -174 dBm/Hz is considered for a perfect receiver at room temperature having a bandwidth of 1 Hz (no internal noise and ability to operate with a signal having the same power as the input noise). B is the bandwidth of the receiver signal and S N is the signal to noise ratio and can be specied to attain a given BER (bit error rate), depending on the adopted modulation scheme. The receiver noise gure NF is the dierence between the input S N and the output S N and it gives an information about the noise generated by the receiver circuit blocks.

To give an order of magnitude about the receiver sensitivity the Tab 2.1 shows the receiver State of the Art for ultra-low power application. Evaluating the data reported in the previous table an average value of -92 dBm can be considered for ULP receiver. Therefore the minimum P rad in the case of 2.4 GHz signal carrier, for an average communication distance D of 5 m has to be equal to -38 dBm. To cover a shorter distance of 1 m the P rad decreases to about -50 dBm. However these are optimistic values, because estimated with the transmission occurring under ideal conditions. To overcome sudden variations, 30 dB of path loss should be added for safe margin. An ULP transmitter with an average transmitter power of -15 dBm is considered. To give an idea about the power consumption of a transmitter, it is possible to assume that the PA is the most power hungry circuit. Therefore the DC power required for a given P rad in the case of class-A topology is: The energy required to transmit n-bit length data depends on the performances of the receiver. High sensitivity demands indeed high receiver power consumption but lower transmitter consumption.

P DC = 2V 2 DD R L (2.11) CHAPTER 2. SYSTEM APPROACH
A typical sensor node is equipped with a radio block for transmission and reception operation. For example, in mesh networks (g. 2.8) the message is propagated along a path by hopping from node to node until it reaches its destination. Optimizing both receiver and transmitter can represent an hard task in energy harvesting environment, because lowering the power radiated surely means lower power consumption for the transmitter circuits but, on the other side, the receiver needs high sensitivity to decrease error bit ratio and this increases its power consumption. The same trade-o occurs when lower sensitivity is accepted, because of the increased radiated power. To alleviate the sensor node complexity and to separate the trade-o between radiated power and receiver sensitivity, a centralized network (g. 2.9) can be adopted, where the data message passes from the sensor to the HUB in an unidirectional way. Therefore the sensor nodes are equipped only with the transmission block and they are powered by harvesting source. The HUB can perform both operation, transmission and reception, with high performances because it is equipped with a large capacity battery. The transmitter in sensor node can be optimized under a power consumption point of view, since the receiver can achieve high performances and complexity. In any case to extend the network lifetime the energy required by the transceiver to process the incoming signal has to be limited. A rendez-vous scheme based on pseudoasynchronous protocol is possible to adopt where the data transmission is accomplished on demand, using a periodic wakeup scheme. In [START_REF] Lin | Receiver initiated rendezvous schemes for sensor networks[END_REF] is demonstrated that Receiver-Initiated Cycled Receiver (RICeR) outperforms low power consumption when compared to Transmitter-Initiated Cycled Receiver (TICeR). In RICeR the destination node has the task to initiate the packet exchanges. Basically the data transmission is done as follow g.2.10: The destination node sends a wakeup signal (WS) to the adjacent nodes to communicate the willingness to receive the data packet. If there is no response, the node goes back to sleep. At the same time the source stays awake monitoring the channel. After the (WS), the communication takes place and the destination node ends the session with an acknowledgment sent to the source node.

CHAPTER 2. SYSTEM APPROACH 2.2.2 Data Rate and Duty Cycle Trade-o.

In transmission system, data-rate (DR) is the rate at which the data informations are transmitted. Considering the bandwidth allocation the Shannon's theorem gives the possibility to calculate the channel capacity C (the maximum rate at which the data can be transmitted over given communication path and under given condition )

C < B log 2 1 + S N
(2.12)

Where B is the channel bandwidth and S N is the signal to noise ratio specication. For short range devices the Electronic Communication Committee (ECC) has established the ERC recommendation [START_REF]ERC recommendations for short wireless devices[END_REF] for each frequency band and for dierent applications. For tracking, tracing and data acquisition in sensors and actuators applications, medical body area network system, wireless industrial application in the frequency band 2483.5-2500 MHz for 1 mW max output power radiated the maximum occupied bandwidth has to be less than 3 MHz. Therefore the channel capacity using the Eq. 2.12 is equal to 10 Mbps for 10 dB of signal noise ratio. As the DR states the TX payload, it is understandable that for a given number of bits N b higher DR means shorter transmission time. Therefore it is possible to express the energy needed to transmit a string of n bits as

E b = P BB + P rad η N b DR = P BB + P RX η × G antennna × P L N b DR (2.13)
where P BB is the power dissipated by the baseband circuits, η is power eciency which is equal to the ratio of P rad and the DC power dissipated by the TX circuits P DC,T X . The E b stated in the eq. 2.13 is low limited due to some trades-o between the variables involved in the equation.

The baseband power consumption is limited due to the noise performance and PVT (Process Variation Temperature) as the weak inversion region is exploited for the Mosfet transistors. High Power eciency requires high radiated power, but it is not the case in short distance communication where P rad ≈ 100 µW. As it will be demonstrated in chapter 4, designing a transmitter block with the same power consumption is a very hard task. At rst glance it seems that high data rate reduces the required energy [DvdZBK11] [ESY05]. This is true until the power consumption due to the higher frequency operations does not increase excessively. Moreover the noise bandwidth increases accordingly and better sensitivity is required for the same bit error rate.

By introducing the spectral eciency η DR-BW , as the ratio between DR and B

η DR-BW = DR B
(2.14)

Therefore expressing the P RX in linear value, the eq. 2.13 can be rearranged as

E b = P BB + N in × N F × DR × S N η × G antenna × P L × η DR-BW N b DR (2.15) CHAPTER 2. SYSTEM APPROACH
The results obtained is derived for continuously operation. However, intuitively and as largely reported in literature, the sensor node lifetime is extended when a duty-cycle protocol is adopted. Duty Cycle is the ratio between the slot-time when the sensor is on and the total time. This technique allows to preserve energy, because in o mode the node burns very low power in comparison with the on mode. Following the indication in [START_REF] Thirunarayanan | Reducing energy dissipation in ulp systems: Pll-free fbar-based fast startup transmitters[END_REF] the duty cycle DC can be calculated as

DC = DRA DR (2.16)
where DRA is the application data rate and DR is the data rate achievable by the system. By obtaining the DR in function of the DC and DRA, substituting it into eq. 2.15 and considering the carrier generation circuits start-up as in g. 2.10 the energy required to transmit n bit is equal to:

E b = P BB + N in × N F × DRA × η DR-BW × S N η × G antenna × P L × DC N b × DC DRA + t s
(2.17)

The above equations states that an aggressive DC, up to 5%, do not allows a reduction in the required energy per bit because it is present at the numerator and denominator in the right side of the equation. Moreover the choice of low or high value aects the power consumption in both receiver and transmitter part. In wake-up scheme both transmitter and receiver have to be turn-on and turn-o periodically, therefore to achieve low DC the two circuits the start-up time has to be reduced consequently. A quick response is obtained with an increase in the power consumption and observing the eq. 2.17 it is clear its no-monotonic trend with the duty-cycle. Generally speaking aggressive DC requires higher power consumption. Therefore it is possible from the eq. 2.17 to calculate the optimum DC for which the energy required is minimum.

δE b δDC = 0 => DC opt = N in × N F × η DR-BW × t s × DRA × S N η × G antenna × P L × P BB × N b (2.18)
The optimum duty-cycle relies on several parameters and there are some constraints which impose the boundaries for the choice of the duty-cycle. For the example G antenna increases with the sphere radius that completely contains the antenna and the small size demanded to the sensor node limits the maximum antenna gain consequently. Processing longer bit string increases the circuit complexity and it aects other system performances as signal-to-noise ratio, the noise gure and the bandwidth eciency.

CHAPTER 2. SYSTEM APPROACH

Conclusions

An overview has been given of WSN and physical layer node. Moreover the energy constraints have been shown and also the techniques and the circuit performances that have to be considered to extend the node lifetimes have been detailed. The relation between the maximum and minimum stored voltages into the capacitor and the regulated voltage have been introduced considering the voltage regulator energy eciency. As concern the transmit section, the indication about the link budget has been given and the trade-o between the receiver sensitivity and data rate has been explained. Duty-cycle operation shows that to be a powerful technique to reduce the energy cost for transmitted data. Optimum Duty-Cycle value permits to reduce as much as possible the required energy per bit. The results obtained in this chapter are used to properly design high about the performances for voltage regulator and transmitter.

Chapter 3 Voltage Regulator

In RF energy harvesting system, the DC voltage obtained from the AC-DC conversion of the incoming signal suers from the variability of the wireless power transfer itself. To smooth these uctuations a voltage regulator is mandatory to deliver a clean voltage for delicate circuit blocks as: ADC, VCO, etc. As explained in the previous chapter, the low energy available imposes dierent challenges in terms of performances for every involved circuit. This chapter describes the design methodology of ULP low drop-out (LDO) voltage regulator with good regulation performances while keeping high power eciency. The rst part of the chapter provides an overview on the main characteristics of the voltage regulator and the comparison between the two topologies of regulation: switching and linear. The reasons of choice are also illustrated. The chapter then ends by describing the design methodology of the LDO regulator with the simulation results.

Background

In modern devices, the energy management and the power delivery have assumed a crucial role. Optimizing the use of the energy contained in a battery or in other storage device, for example super-capacitor as in the case of harvesting source, allows to extend the autonomy of the device. The power management unit (PMU) Fig. 3.1 is responsible for a balanced distribution of energy according to the circuits consumption and the state of operations.

Figure 3.1 Power Management Unit

The eciency of harvesting systems strongly depends on the optimization of the power management unit. Due to the energy constraint, only by means of a depth understanding of the application it is possible to make the correct choices in terms of architecture and performances. For example in a body area network application (BAN), the sensor and the transmission block have to turn-on frequently to monitor the vital parameters for a short time period with very short distance (< 10 cm); while in wireless sensor application (WSN) where the distance is more important (> 1 m), the transmission time has to take a longer duration to prevent false data transmission due to channel interference. It is clear that the two applications are dierent in terms of data-rate, frequency modulation, duty-cycle and power consumption. For example in [MBT + 13] the PMU has to manage two dierent duty-cycled signals, in order to power supply or not the sensor and UWB transmitter, saving the power consumption. Typically the power management unit directly interfaces with the load through the voltage regulator. In most of case, the regulation performances dictate the design specications of the PMU (output voltage, max. supply current, transient response, etc). The following section describes the two dierent methodologies of regulation illustrating the advantages and the drawbacks for each of them.

Voltage Regulator

Voltage regulator is a circuit that converts an unregulated DC input voltage into a stable and clean DC output voltage. A stable and clean voltage at the output terminals is desired, in order to not deteriorate the performances of the load circuits. It is composed of two main parts as depicted in Fig. 3.2 1. the conversion stage transforms the unregulated input voltage to a regulated output one. 2. the control feedback monitors the output voltage and tunes the conversion stage condition in order to keep the output voltage at the nominal value Evaluating the static and dynamic characteristics, not only permits to compare the different topologies but also to understand the performances to improve which best match with the targeted application.

Static Characteristics

The static characteristics are evaluated under steady-state conditions when all the transient phenomena are clearly completed. They dier for the DC or AC nature.

Eciency

In energy harvesting system the eciency is one if not the most important design criterion to evaluate. It gives the power cost of the transformation, in other words the amount of power loss in the circuit. The eciency is expressed as the ratio between the delivered output P out and the input power P in :

η = P out P in (3.1)
An eciency of 100% means no power loss. But with real components the power is dissipated in resistive part or in other way as leakage phenomena.

Power Density

The power density puts in relation the eciency with the area occupied by the chip. It is expressed as P out normalized to the total area A:

P D = P out A (3.2)

Load Regulation

The load regulation describes the variations of the steady-state output voltage when output current I LOAD changes (Fig. 3.3) Figure 3.

Load Regulation

As the load regulation is not linear for the entire load range, it is measured for the minimum and maximum value CHAPTER 3. VOLTAGE REGULATOR

LoadRegulation = V out1 -V out2 I out1 -I out2 = R OL 1 + A ol β F B (3.3)

Line Regulation

The line regulation describes the variations of the steady-state output voltage for a variation of the input voltage V in (Fig. 3.4) Figure 3.4 Line Regulation It is measured for the minimum and maximum value of unregulated input voltage

LineRegulation = V out1 -V out2 V in1 -V in2 ≈ 1 1 + β F B A ol (3.4)
Where A ol is the open loop gain and β F B is the feedback factor. So line regulation is improved by high open-loop gain.

Noise

The noise is an AC characteristic and it quanties two aspects of the regulator: 1) the capability to suppress the interferences coming from the input signal; 2) the inherent noise produced by the regulator itself. The noise performances are evaluated with power supply rejection ratio PSR.

Dynamic Characteristics

The dynamic characteristics exhibits the capability of the regulator to restore the output voltage when a transient event appears. In the following section the description of two main conversion methodologies are given, switched and linear, illustrating the advantages and the weaknesses of each one and concluding with the analysis that demonstrates as linear regulator is the topology which best suits with the harvesting system.

Switching versus Linear

The reduction of the dimensions and the chip costs are the biggest challenges in modern electronic devices. Nowadays these problematics are managed with two types of integration: System on Chip (SoC) and System in Package (SiP). In the rst approach the electronic circuits are integrated on the same silicon die, while the second includes two or more dierent technology dies, usually with external passive components. With the aggressive technology scaling achieved in last 10 years and accompanied by the demand of devices ever smaller, SoC is the topology that best ts with these constraints. However, the main problem is the integration of passive components, inductors and capacitors, that suer from low quality factor. In SiP the possibility to use large passive components with better manufacturing quality, is counteracted by the large occupied area. Moreover, it requires advance packaging technologies (ne pitch ip chip, wire bonding, high density SMT) and complex electromagnetic interference shielding.

The Linear Regulator is well suited to be completely integrated on chip.The Fig. 3.5 depicts a classical representation of a linear regulator. The conversion is performed by changing the resistance of the pass element connected in series between the input and output voltage. The impossibility to be completely integrated occurs only when a large output o-chip capacitor (1 µF) is used to ensure the stability of the negative feedback loop 1 . Recent works have largely demonstrated that when compensation techniques are applied to the internal loop, a small integrable capacitor can be used at the output of the regulator. CHAPTER 3. VOLTAGE REGULATOR Figure 3.5 Linear Regulator For example, only 5 pF compensation capacitor with a cascode current compensation stage to achieve the stability is needed [LGZ + 15]. Q-reduction circuit proposed in [START_REF] Lau | A low-dropout regulator for soc with q -reduction[END_REF] permits to minimize on-chip capacitor (7 pF) and quiescent current. One of the main limits is that only down-conversion is possible, given that the output voltage is the dierence between the input voltage and the voltage drop over the pass element. Due to the continuous linear control and the fact that the conversion is performed dissipating the power on the pass element, the power eciency is not one of the strengths of this topology. Analyzing the eciency equation:

η = V out I Load (I Load + I q )V in (3.5)
where I q is the total drawn current to the ground, it is not preferable to have large conversion ratio Vout V in as anticipated in chapter two. If the quiescent current is negligible respects to the output current, it is clear that transforming 3 V into 1.5 V for example, the maximum eciency is only 50%. While the unregulated voltage is about 1.8 V the eciency increases to 83 %. For this reason linear regulator is preferable when the voltage conversion ratio is closely to 1. As can be easily understood, switching regulator (Fig. 3.6) performs the regulation activating one or more switches, in order to energize from the unregulated input voltage or de-energize into the load a storage element as capacitor or inductor. [ The use of energy storage elements and switches permits to transfer the energy from input to output with almost no loss. In theory this makes the switching regulator more ecient than the linear one. In reality the eciency is strongly dependent on the quality factor of the storage elements. As previously mentioned, integrating the passive elements particularly inductors in CMOS technology is a well-know challenge for the designer. The main reason is the poor quality factor due to the poor conductivity, high series resistance and thin metal layer. That translates in the increment in power loss on the parasitic resistance [START_REF] Lee | Evaluation of fully-integrated switching regulators for cmos process technologies[END_REF] (about 70% of power eciency).

HHY + 12] [FF14] [TSW + 15] [KBW12] V in (v) 1,6-5,5 1,2-2,5 1,8 1,66 2,4 V out (V) - 1 0,8-1,2 0,83 0,4-1,4 C L (
Switching regulators that achieve eciency above 85% normally requires inductor in the order of 1-100 µH, making the integration not feasible for SoC applications. In [START_REF] Wibben | A high-eciency dc-dc converter using 2 nh integrated inductors[END_REF], to attend high eciency 77,9 % and small passive component 2 nH, a stacked interleaved topology is used. In [START_REF] Rojas-González | Design of a fully-integrated buck voltage regulator using standard cmos technology[END_REF] the relationship between the frequency and the inductance is exploited to integrate the inductor (24 nH). But due to the increasing in switching loss with the frequency, the peak eciency is 60% only. The table 3.1 shows that only for switching frequency in the range of hundreds MHz the inductor can be integrated, while higher power eciency is achieved with o-chip inductor. CHAPTER 3. VOLTAGE REGULATOR Another aspect that has to be considered is the noise content at the output voltage. The large size of the power switch and the switching behavior are all factors that have a negative impact on this characteristic. The situation is worsen in the case of monolithic switching converter, where high switching frequency is required to integrate the passive elements. Linear regulator for its part presents a low noise contents at the output. It is not rare that linear regulator is positioned after a switching one, since it is able to suppress the ripple and to provide a cleaner voltage supply at its output.

As mentioned previously a good regulator needs a fast response to the load changes. The fast response of the linear topology, in the order of 0.1-1 µs, is due to the simplicity of the feedback loop. This means an advantage in terms of time-to-design and so in terms of cost. Conversely, switching regulator suers from a slow response. The ne control of the power switches normally requires clock generator, several digital blocks and other waveforms generator blocks depicted in Fig. 3

CHAPTER 3. VOLTAGE REGULATOR

There is no doubt that the most appropriate voltage regulator is linked to the application.

Starting from the power eciency, the on-o behavior of switching regulator permits to extend the lifetime of device with higher capability to transfer the energy from input to output. The power eciency represents a fundamental design criteria in such low energy system as in the case of RF harvesting source. But the needed of large inductor increases the chip cost. Since the local oscillator (LO) in transmission block is powered by the voltage regulator the noise content at the output of the regulator has to be as lowest as possible, in order to not degrade the phase noise. Linear regulator exhibits better results than switching one. This latter presents indeed a switching output voltage ripple.

Using on-o modulation and moderated duty-cycle to ensure data transmission with lower energy per bit, the recover time has to be as short as possible to not waste power. Switching on-o the VCO or PA means changing in the load current of the regulator. Since the maximum peak-to-peak voltage of the transmission signal, therefore the output power transmission, depends on the supply voltage it is clear that the fasten response of the linear regulator allows to reduce the time slots where the power transmitted is not at optimal value. Therefore linear regulator with fasten transient response than switching one, optimizes the global eciency of the whole system. In conclusion the previously argumentations provide good reasons that the linear regulation is the most appropriated regulator for harvesting applications.

Low Drop-Out Regulator

Drop-out voltage is the dierence between the unregulated input voltage and the regulated output one. As the power dissipated for the regulation is the product of the load current by the dropout voltage, it is mandatory to keep this value very low. As shown in Fig. 3.8 there are three dierent regions according to the input voltage value. In the linear region V out can be regulated within the allowable dropout voltage with a determinate loop gain. When V DO increases with decreasing V in the output voltage deviates from its nominal value due to the lower loop gain. The pass transistor acts as switch and the regulator enters in dropout region. The V DO is given by:

V DO = r on I D (3.6)
where r on is the on-resistance of the pass transistor used as pass element and I D its drainsource current. As V in decreases further the regulator enters in o region. The headroom in not sucient for the transistors to properly work and regulation property is lost. The Fig. 3.9 shows that the minimum drop voltage in the NMOS setup is the sum of the gate source voltage of the pass element V GS and the minimum saturation voltage of its driver transistor V SD . Depending on the technology node this value can exceed 0.7 V. In the case of PMOS setup the drop voltage is only the minimum overdrive voltage V SD of the transistor. In modern technologies 0.2 V is a common value. Therefore PMOS transistor is the candidate for the voltage regulator, because as pointed out previously, the power eciency is aected by the ratio between output and input voltage. However this statement remains valid as long as the output current is hundreds order of magnitude higher than the quiescent current. With very low dropout voltage achievable across the CHAPTER 3. VOLTAGE REGULATOR pass transistor, the current eciency

η c = I out I out + I q (3.7)
is a more interesting specication and one of main design criterion for modern ULP LDO voltage regulator. Since the load current can vary of several orders of magnitude and that standby condition and light 2 load mode occurs most of the time in harvesting systems, current eciency is an important factor to consider.

Basic LDO Architecture

To restore the output voltage when a variation of the load current appears at the output, the LDO topology requires a PMOS transistor M p that acts as conversion element. In the case of output voltage variation, due a load requested current, the pass transistor supplies such current to regulate the output voltage V out at the nominal value. Essentially the current that ows from input to output is modulated by a more or less conductive source-drain channel, by means of a lower or higher voltage applied to the gate of the PMOS. Therefore a control signal is needed to drive the gate of this transistor. In Voltage regulator is a dynamic system since it has to react to load current step, to limit the output voltage peaks and to bring it back to the nominal value in the shortest possible time. The Fig. 3.11 depicts the transient response when a load step appears at the output. When the load current changes from light condition to heavy condition, the pass device cannot immediately supply sucient load current because the loop inertia, requires time to respond to this large current variation. Therefore, the output voltage experiences a voltage drop. The recover time t 1 depends on the closed-loop bandwidth BW cl and the slew-rate of the error amplier. The response time can be approximated using eq. 3.8, where t sr is the slew-rate time needed to discharge the parasitic capacitance C par at the gate of PMOS pass transistor.

t 1 = 1 BW cl-1 + t sr (3.8)
The closed loop bandwidth BW cl is referred at light load. Similarly, in the case of a current change from heavy to light condition t 3 can be expressed by the eq. 3.9.

t 3 = 1 BW cl-3 + t sr (3.9)
Thus, in case of light-to-heavy and heavy-to-light changes t 1 and t 3 are dierent, because the bandwidths under light and heavy conditions vary and the pass transistor delivers current that is either too low or too high, respectively, to the output load. It seems clearly that the output capacitor C L acts as current buer to balance the energy dierence between input and output, as long as the pass transistor responds to the load change.

That is, C L delivers energy to the output before the V gs of pass transistor is adjusted to an adequate voltage as show in Fig. 3.12. In the opposite case, the output capacitor can Eq. 3.10 shows that a large capacitor limits the output voltage variations. The overshoot can be dissipated by the leakage current at the feedback divider resistor. However, the extra cost needed to provide a large area occupied for the output o-chip capacitor is not suited for the harvesting application. When a C-free 3 topology is applied, the way to compensate the degraded transient response is to reduce the recovering time t 1/3 . From the eq. 3.8 and eq. 3.9, it is clear that large bandwidth and high slew-rate performance of the error amplier are mandatory to overcome the absence of large output capacitor. However it implies higher quiescent current, therefore lower current eciency. In conclusion, a trade-o between speed and power consumption occurs, depending on the size of the output capacitor.

Frequency Response

As explained previously, the regulation is performed through a negative feedback loop. To properly process the signal, the loop has to remain stable for all load conditions. Figure 3.14 shows the linearized model of a LDO.

A ol (s) = G EA g m r o-pass (1 + s ω 0 )(1 + s ω 1 )
(3.11)

3. C-free or Capacitorless indicates a fully integrated topology. Normally for capacitor value in the range of 10-100 pF where G EA is the voltage gain of the error amplier, g mp and r o-pass the transconductance and the drain source resistance of the PMOS pass element respectively. The two frequencies ω 0 and ω 1 are expressed as follow:

ω 0 = 1 R 0-A C par ω 1 = 1 r o-pass C L (3.12)
The capacitance C par is formed by the output parasitic capacitances of the error amplier and the parasitic capacitance associated to the gate of the transistor M p . Paying attention to the Miller eect between gate-drain of the PMOS due to its voltage gain, C par is not constant but it varies with the output current. The amount is given by

C gdM =(1+g m r o-pass )C gd .
It is well known from signal theory that a negative feedback loop is stable when:

A cl = A ol 1 + βA ol |βA ol | = 1 P M (f 0dB ) > -180 • (3.13)
The basic approach to make the feedback loop stable is to ensure a dominant singlepole frequency response. This means that the closed loop gain A ol β reaches unity gain frequency with a slope of -20 dB/dec, for example pushing the main pole at very lower frequency. Obviously, the pole frequency position sets the system bandwidth and how quickly the system responds accordingly. Therefore, the frequency response should be designed carefully not only for stability, but also for transient response. In the LDO C-free topology the two main poles are identied from the eq. 3.12 : one at the LDO output and the other at the gate of the pass transistor. Observing the eq. 3.11, the loop compensation is a quite hard task due to the poles movement with the load condition. The pole ω 1 moves with the r o-pass variations therefore with the load current consequently.

The pole ω 0 moves with the g mp r 0-pass product therefore with the square roots of the load current.

ω 1 αI L ω 0 α I L (3.14)
As the load current can vary from several order of magnitude, the poles moves within of large frequency range. Moreover, the position of the two poles does not change proportionally. In conclusion the design of LDO voltage regulator demands several eorts to satisfy all specications. For the purpose of the applications three main aspects were considered for the design:

Current Eciency: this is the most important design criteria considered for the regulator. The greater eort was done to keep high current eciency especially for light load condition. As explained, the system spends most of time in stand-by or low power mode.

Transient Response: Adaptable is the concept introduced to improve the SR of error amplier and to extend the BW of the closed loop. Big load step current means higher quiescent current and vice-versa. Therefore, the bias current is adjusted dynamically with the load state.

Frequency Response: the compensation strategy has to ensure the stability also for ultra-low stand-by current.

CHAPTER 3. VOLTAGE REGULATOR

Design Implementation

From the previously done study it is evident that Capacitor-less LDO regulator is the best solution for our application. This section describes the techniques to improve the transient response. Moreover, the compensation strategy is also illustrated. The circuit is designed in a 130nm CMOS technology from STMicroelectronics

Output Target

To start the design of LDO regulator, it is needed to x the load current boundaries. In fact, its maximum value sets the size of the pass element. The aspect ratio of M p is fundamental, because the main performances of the regulator revolves around its characteristic. When the M p supplies the maximum current, the dropout voltage is kept at low value if the transistor has large aspect ratio S = W L (W and L are the width and the length of the PMOS channel respectively). Once the minimum drop-out V DO is chosen and thanks to the following equation

V DO < r o-pass I DS,triode (3.15)
where r o-pass and I DS,triode are the drain-source resistance and the drain current when the transistor is on ohmic region respectively, the aspect ratio can be calculated as

W L > 2I Dmax µ p C ox (V inmin -V th ) 2 V DO (3.16)
with µ p the mobility of the carriers, C ox the oxide capacitance , V th the voltage threshold and V inmin is the minimum unregulated input voltage assuming rail-to-rail voltage swing at the output of error amplier. With the size of M p it is possible to calculate the drainsource saturation voltage and therefore the input voltage boundary (V inB =V out +V sdsat ), when the pass transistor leaves the high gain region and starts to work in dropout region. From the well-known drain current equation of transistor in strong inversion:

I D = 1 2 µ p C ox W L (V SG -V th ) 2
(3.17) the saturation drain-source voltage is:

V sdsat = 2I Dmax µ p C ox W L (3.18)
Where I Dmax represents the max load current. From the Eq. 3.18 with xed drain current, the V SDsat = (V SG -V th ) decreases if the transistor has larger channel.

The rst step to design the regulator is to x the maximum load current. In the most published works the LDO regulator is characterized with a maximum current load in the range of 50-100 mA [START_REF] Guo | A 6µ w chip-area-ecient output-capacitorless ldo in 90-nm cmos technology[END_REF], [START_REF] Park | External capacitor-less low drop-out regulator with 25 db superior power supply rejection in the 0.4-4 Mhz range[END_REF], [ZM11], [START_REF] Ho | A capacitor-less cmos active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application[END_REF]. That is a prohibitive value in harvesting application.

Given the simplicity of the sensor node architecture, it is easy to nd that the transmission block is the hungriest part. In rst approximation, the maximum load current can be approximated as the sum of the current drawn by the transmitter and an adequate safety margin. This latter is due to the supply current for other regulator load circuits (ADC, sensor, digital circuit). Therefore, a preliminary study about the recent ULP transmitter is mandatory, to better address the design ow of regulator. In [VHH + 11b] a 2.4 GHz OOK transmitter with 0 dBm peak power and 10 Mbps data-rate draws 2.5 mA from 1V of V DD . With a more sophisticated and precise frequency generation [START_REF] Thirunarayanan | Reducing energy dissipation in ulp systems: Pll-free fbar-based fast startup transmitters[END_REF] to compensate the absence of PLL, the current consumption increases up to 6.8 mA. Ultra Wide Band impulse architecture approach [START_REF] Li | Power consumption trade-os in short-distance wireless transceivers for sensor nodes[END_REF] shows that for very short distance, the current consumption decreases drastically under 1 mA.

To help with the design, dierent OOK transmitters topology have been realized and simulated. The detailed characteristics, and the design ow are presented in the next chapter. For sake of clarity the table Tab. 3.2 shows only their current consumption. To obtain a 2.4 GHz carrier frequency with a peak output power of -15 dBm, the transmitter has to be supplied with an average current of 650 µA. Taking this value as the most important part of the load current and considering the extra current needed to the others circuits, the LDO is designed with a max load current of 1 mA.

However, some trade-o has to be considered before choosing the aspect ratio of Pass Element. In fact the parasitic gate capacitance of the PMOS increases with the size of the transistor. Larger gate capacitance demands better slew-rate performance. If the quiescent current of the error amplier is not increased to avoid lower current eciency, the regulator is aected by slower response. Therefore there is a trade-o between power consumption and speed.

With I LOAD = 1mA and V DO < 100mV, the width of PMOS channel has to be greater than 22 µm (eq. 3.16). This value is obtained with the minimum gate length size L = 0.13 µm. With the aspect ratio of pass element the minimum V SDsat is around 200mV, that gives a V inB =1.2 V, considering V out = 1V. To move the boundary towards values near V out , the size of transistor has to be increased. Figure 3.16 shows the simulated trends of the parasitic gate capacitance and the saturated drain-source voltage of pass transistor for dierent W, for minimum length gate size. A width of 200 µm is chosen to improve the robustness of the regulator versus the input voltage variation. In fact as explained previously, this signal suers from high uctuations due to the incertitude of RF source. Therefore, decreasing the V sdsat permits to extend the regulator linear region, where the pass element has the maximum gain. In addition also the eciency is improved as V DO decreases accordingly. But this results in larger parasitic gate capacitance and therefore in slower response.

Overcome current eciency-transient response trade-o

As pointed out the transient response depends on the slew-rate (SR) performance of the error amplier and on the bandwidth of the closed loop. In a simple amplier the slew rate is given by

SR = I biasEA C L (3.19)
where C L is the load capacitance seen at the output of the amplier and I biasEA is the bias current of the input dierential pair of the error amplier. Assuming the LDO regulator as a two stage amplier, and supposing a Miller capacitor C m to compensate the frequency response of the system, the gain-bandwidth product can be approximated as

ω GBW ≈ G mEA C m ∝ I biasEA (3.20)
where G mEA is the transconductance of the input dierential pair. Eq. 3.19 and 3.20 show that high bias current is needed to improve the SR and to have large GBW product. CHAPTER 3. VOLTAGE REGULATOR However, with a high and xed value of bias current the eciency is aected especially at light load condition. The problem can be circumnavigated if the regulator adapts its closed loop response with the variations of the load current. This translates in higher quiescent current when the LDO is a high load state and lower quiescent current when the output is at light load condition. In this way it is possible to reduce the impact of the regulator on the power budget. The two techniques implemented in this work to achieve this condition are: class AB Error Amplier and adaptively bias Error Amplier.

Slew-rate enhancement

Slew rate is the maximum voltage variation per time unit in a circuit node, due to the limited sink or source current. The SR of a circuit is limited by its slowest node: if the node is mostly made of a capacitance C, then the rate of voltage change across the capacitor is described by the well-known equation

dV dt = I C (3.21)
If the current is limited at I max , the maximum voltage change per time unit is

SR = max( dV dt ) = I max C (3.22)
The SR can be positive or negative depending if the node sources or sinks the current. For each internal node of the error amplier EA it is possible to associate capacitors. Clearly the large capacitance seen at the output of the EA limits its SR response and the speed of closed loop consequently. Eq. 3.22 indicates that the power consumption imposes a severe limit for the SR performance when the amplier is designed to work as a conventional class-A Fig. 3.17 The problem can be circumnavigated if a class-AB EA is used. In [CS90] a self-biasing dierential input pair that has a feedback loop allows to increase the quiescent current. Another way to enhance the SR performance is to add some extra circuit to improve the driving capability at the output of the amplier [START_REF] Grasso | Design methodology of subthreshold three-stage cmos otas suitable for ultra-low-power low-area and high driving capability[END_REF]. However these approaches exhibit several limits in terms of bandwidth and occupied area. The circuit proposed in this work [START_REF] Lopez-Martin | Low-voltage super class ab cmos ota cells with very high slew rate and power eciency[END_REF], uses a super class-AB OTA that breaks the trade-o between static power consumption and SR. The Fig. 3.18 depicts the class-AB amplier core. The input dierential pair M 1 and M 2 is cross coupled, at the source, with two ipped voltage follower (FVF) blocks that act as a dc voltage level shifters. At steady state when V dif f = V in + -V in -= 0 the circuit is biased at I bias by the current source. When the system is unbalanced, one of the two transistors M 1 or M 2 experiences higher gate-source voltage, therefore more drain-source current than the other one. For example, if V in + increases and V in -is kept constant, the transistor M 2 has larger V GS than the transistor M 1 . The consequence is that the current I D2 is greater than I D1 . The great advantage of this conguration is that at steady-state condition the circuit can be biased with very low quiescent current. Only when the differential input voltage V dif f = V in + -V in -is not zero, the amplier is able to supply more current at the output.

Class-AB Error Amplier

The adaptive biasing created by the two FVF cells has a positive impact on the SR performance of the amplier. The large signal time response is no more limited by the quiescent current but depends on the unbalanced high input signal. Therefore the same benets of class-AB amplier can be integrated in LDO voltage regulator, improving current eciency and transient response. In this case the negative input node of EA has a xed voltage V ref but the positive input senses the variation of the output voltage of the regulator. It is clear that, only in front of a load current step the EA responds with more current at its output, driving the pass transistor more quickly.

Figure 3.19 Class AB error amplier

A Current Mirror OTA depicted in Fig. 3.19 is used to implement the Error Amplier. The pairs of transistors M 5 -M 3 , M 4 -M 6 and M 7 -M 8 act as current mirrors. Depending on the ratio (K) between the aspect ratio (S) of the transistors, this topology can presents high transconductance, large BW and high SR, however at cost of higher output noise and higher power consumption.

To get a rst estimation of the total quiescent current of the EA, and its impact on the regulator performances, a minimum current eciency of 60% was estimated for the output current of 1µA. Considering the quiescent current of 200 nA in the feedback resistors Fig. 3.13, this leads to a global allowed quiescent current for the error amplier of around 200 nA. The amplier is designed with the nominal unregulated input voltage of 1.2 V and each transistor M b is designed to supply I b =30 nA. In order to bias the transistor M 1 -M 2 and M A1 -M A2 with the same current, it is needed to set S 1 /S A1 = S 2 /S A2 equal to 1. Therefore the total current consumption of the circuit is given by:

I qtotal = I b (4 + 2K) (3.23)
To achieve the total current consumption of 180 nA, K is set to 1. In this low bias condition, all transistors operate in sub-threshold region and currents4 drawing by M 1 and M 2 are given by

I D1 = I DO W L M 1 exp log I DA1 I DO W L M A1 -V dif f 1 V t n
(3.24a)

I D2 = I DO W L M 2 exp log I DA2 I DO W L M A2 + V dif f 1 V t n (3.24b)
where I DO is the technology current and it depends on the oxide capacitance, the substrate factor n and the carriers mobility µ 0 and V T is the thermal voltage about 25 mV at room temperature.

Figure 3.20 FVF cell with cascode Pmos transistor

The above equations state that the drain current increases exponentially with the large input dierential voltage. However to avoid large current process-voltage-temperature (PVT) variations due to the exponential characteristic in weak inversion, the aspect ratio of M b and the voltage V b are set in order to keep the transistor in strong inversion. It is worth noting that except M b , all other transistors have to be oversized, because they experience more drain current than the 30 nA of current bias not only when the system is unbalanced, but also because the circuit provides extra bias current for the error amplier proportional to the variations of the load current. Consequently transistors M 3 -M 4 are much larger than M b . Therefore the transistors M A1 -M A2 have lower V ds than M 1 -M 2 . As a result the drain current is not the same. In order to re-equalize the circuit a PMOS cascoding transistor M cas is inserted in the feedback loop of each FVF cell (Fig. 3.20). They provide a level shift proportional to the bias voltage V cas . Therefore the maximum voltage at the drain of M A1 -M A2 during idle mode is approximatively V cas +V sgcas . With a correct setting of V cas it is possible to re-balance the steady state drain current, however at the cost of extra power consumption.

The g (3.21a) depicts the voltage gain of the class-AB and class-A for a I b = 60nA. The simulation highlights that the DC gain and the unity-gain frequency in the case of class-AB are doubled compared to the class-A. The graph shows 46dB versus 40dB and 2.9 MHz versus 1.5 MHz. These results are explained by the fact that the dierential ac input signal is applied to both the gate and the source of M 1 and M 2 . Therefore the input signal sees a value of the transconductance double respect to the classical class-A topology. In the Fig. 3.21b the great advantage in term of Slew-Rate is more visible, due to the higher current delivered to the output thanks to the adaptively bias. The second design step concerns the implementation of the circuit to adapt the bias current of the error amplier with the regulator load current. As explained previously, high bandwidth can be achieved with high quiescent current as indicated in Eq. 3.20. It is clear that the system is over-sized in terms of bias current when the output is at light condition. Since high transconductance is needed only for high value of the output current, adapting the g m of the EA with the load current allows to reduce or to extend the bandwidth of the LDR regulator for the entire load range. Therefore a scaled version of the load current can be used for the I bias of the Error Amplier, through 3 current mirrors depicted in g. 3.22. The rst reduction is acted by the pair of transistors M p /M AB1 , then the small replica of the load current is mirrored through the pairs M AB2 /M AB3 and M AB4 /M AB . Therefore the bias current supplied by the transistor M AB is given by

Extended closed loop Bandwidth

I AB = I L mn (3.25)
where m is the scaled factor of the transistor M AB1 to the pass transistor M p and n is the aspect ratio between M AB4 and M AB . Considering that the transistors work in weak inversion for all load current range, the GBW product is proportional to

ω GBW ∝ I bias + I AB (3.26)
However the design of the adaptively biased LDO (AB-LDO) requires a careful study of the loop stability, therefore the two aspects have to be evaluated at the same time.

Compensation Strategy

As introduced in the section 3.4.1, to ensure the correct regulation the frequency response of the closed loop LDO has to respect the stability criteria. In literature are reported dierent techniques to accomplish this task. Q-reduction technique in [START_REF] Lau | A low-dropout regulator for soc with q -reduction[END_REF] is used to control the Q of the non dominant pole to compensate the regulator at light load. For a multistage LDO regulator [START_REF] Garimella | Reverse nested miller compensation using current buers in a three-stage ldo[END_REF] proposes a nested Miller Compensation with a current buer, to move left-half plane zero towards high frequency. However the main drawbacks of these topologies is that they require big compensation capacitor and the stability is ensured for a well dened minimum load current value.

The Miller compensation strategy with current buer [START_REF] Giustolisi | Robust miller compensation with current ampliers applied to ldo voltage regulators[END_REF] is used in this work to ensure the stability for the entire load range. Miller capacitor is one of the techniques widely used to assure stable frequency response in a two stages amplier. However, the well-known disadvantage of the LHP zero limits its strength, especially when a large capacitor is needed to achieve pole splitting eect. The purpose of current buer is to alleviate the inuence of the left-right plane (LHP) zero breaking the forward path created by the Miller capacitor. The frequency response of the voltage regulator can be associated with that of a two stages amplier. Therefore the same technique can be implemented to compensate the circuit. However the stability is more complicated to achieve due to the load current large span. Respect to other approaches (nulling resistor, Voltage buer, poe-zero cancellation), the current buer allows to reduce the compensation capacitor value and not degrade the time response of the circuit [START_REF] Grasso | Comparison of the frequency compensation techniques for cmos two-stage miller otas[END_REF]. The feedback resistance R f b1 -R f b2 are realized with a PMOS transistor to reduce the occupied area. The circuit is designed to supply 1 V with a maximum output current of 1mA. The unregulated input voltage range is (1.2-1.4)V. The voltage reference generated by an ultra low power sub-bandgap is 650 mV. The values of feedback resistors are 2.6 MΩ for R f b2 and 1.4 MΩ for R f b1 , which draw a ground current of 150 nA. One of the design trouble is that the large aspect ratio of the pass transistor imposes a minimum drain current to properly work. For example, if the load current is about 100 nA the transistor is in o-state and the regulation is lost. Therefore to provide the correct operation for the entire current load range the minimum drain current for M p is provided by the ground current of the resistive network.

If we look closely to the circuit three loops can be identied. The most evident is the main loop needed to perform the regulation. The second is constituted by the AB network to control the bias condition of the EA. The last loop is inside the main loop and is related to the Miller capacitor and the current buer. Therefore the LDO regulator has a stable response if the three loops respect the Phase Margin and Gain Margin criterion. The stability of the AB circuit can be assured if the loop gain is always less than 0 dB. Breaking the loop at the gate of the M AB (node at higher impedance), the loop gain is evaluated for the all load range current. The graphs in the Fig. 3.25 shows that the AB network is always stable at every load condition, since that the loop gain is well above 0 dB.

Figure 3.26 LDO small-signal feedback representation

Once the stability of AB circuit is veried, the study of the frequency response can be related merely to the LDO voltage regulator and the compensation circuit. As introduced in [GPS12] when a buer Miller compensation strategy is adopted the loop transfer function presents one dominant pole and a pair of complex and conjugate poles. The presence of the complex poles is due to the two nested loops. The open-loop transfer function is given by

T (s) = T (0) 1 -s Z LHP 1 -s Z RHP 1 -s p d 1 + s GBW I + s 2 GBW 2 I K IN (3.27)
where GBW I is the gain-bandwidth product of the internal loop and K IN is the separation factor of the internal loop. The DC gain T(0) is equal to

T (0) = G mEA R o-EA g mp R out (3.28a) R out = r o-pass ||(R f b1 + R f b2 ) (3.28b)
the two zeros are

Z LHP = -G M c2 C M B (3.29a) Z RHP = g mp C M + C gd-mp (3.29b)
where G M c2 is the transconductance of the current buer, while the dominant pole is equal to

p d = - 1 [g mp R o-EA (C M B + C F B + C L )] R out (3.30)
It is worth noting that the stability of the internal loop can be evaluated with the separation factor K

K ≈ tan(φ) ≈ |p 2 | GBW (3.31)
Where φ is the phase Margin and p 2 is the rst non-dominant pole of the generic transfer function. The separation factor K IN for the proposed voltage regulator is expressed by

K IN = |p 2IN | GBW I = C L (C F B + C gp )R o-EA + C M B G M c2 (C f b g mp R o-EA + C L ) 2 [g mp R o-EA (C M B + C F B ) + C L ] C L C M B (C F B + C gp ) R o-EA G M c2 (3.32)
where p 2IN is the rst non-dominant pole of the internal loop and C F B = C M + C gdp . With K IN =2 the PM = 65 • and the system is stable with a small damping factor. The minimum acceptable PM of 50 • is for K IN =1.2. The same stability criteria can be adopted for the external loop. The separation factor K EX in this case is related also to the gainbandwidth product of the external loop

K EX = GBW IN GBW EX (3.33a) K EX = [g mp (C F B + C M B )R o-EA + C L )] 2 C L (C f b + C gp )R o-EA + C CM G CA (C F B g mp R o-EA + C L ) G mEA R o-EA g mp (3.33b)
Where GBW EX is the gain-bandwidth product of the external loop. With a value greater than 1.5 for both separation factors the overall stability is achieved. Following the design methodology given in [START_REF] Giustolisi | Robust miller compensation with current ampliers applied to ldo voltage regulators[END_REF] the design equations for the compensation circuit are

C M = 2C gp n -1 -C gd (3.34) C M B = 4 -K IN BK IT 2C gp n -1 (3.35) G M c2 = 4-K IN BK IN 16 K EX K 2 I 1 G m-EA -n 2 -1 4 C L Cgp 1 g min mp (3.36) n < 64 K EX K 2 IN C gp C L g min mp G m-EA + 1
(3.37)

Where B = K 1 K from Fig 3.
24 and n is a scaling factor. Once the system is compensated the dominant pole and the second pole are expressed as

p D = - 1 g mp r o-pass (BC M B + C F B )R o-EA (3.38a) p 2 = - G mp (BC CM + C F B ) C L (C F B + C gp ) + C M B C F B gmp G CA (3.38b)
CHAPTER 3. VOLTAGE REGULATOR Some considerations have to be carried out about the two separation factors when an adaptively biasing topology is used. At rst glance, it is clear that K IN and K EX are not constant for the entire load range. In fact both terms depend on the transconductance of the pass transistor g mp and on the output resistance of the error amplier R o-EA . Moreover the impact of the transconductance of the EA G m-EA on the stability requires a further study. From (Eq. 3.38a-3.38b) it seems that it does not have any inuence on the frequency response of the regulator. However K EX is linked to G m-EA and this is included in the design equations (Eq. 3.36-3.37) for the compensation circuit. Given that G m-EA changes with the load current, it is important to understand which value has to be chosen in order to calculate n and G M c2 . Observing the equation of K EX , the minimum value occurs when the transconductance of the error amplier is at highest value. Therefore, assuming a Weak Inversion region for the entire load current range, the minimum of K EX is at heavy load condition. In conclusion G max m-EA has to be used to design the compensation circuit.

So the study of K IN and K EX can be related to g mp and R o-EA . Limiting the adaptively bias current of EA, its output resistance does not change substantially. Therefore for the rst approach, it is possible to consider that the stability depends largely on the pass transistor transconductance. To conrm this hypothesis, the (Fig.

Transistor Level Design

Once the design equations are established and with the constraints dictated by the application, the design steps of the proposed LDO regulator can be as follow achieve high current eciency (> 99%) from moderate to heavy load. Considering the 300 µA as the moderate load condition the total quiescent current of regulator has to be less than < 3µA. Being the EA the most power hungry block it is possible to estimate the maximum bias current. With the aim of Eq. 3.23 the I max AB is

I max AB = I q 6 -I b (3.39)
Assuming 60% of the total quiescent current, thus extending the eciency below the moderate load, I max AB ≈ 200nA. With Eq. 3.25 and with the above value, the scaling factors product mn is about 5000. Once all bias condition established, it is possible to calculate the compensation elements Eq. (3.34-3.37). Therefore, setting I min L = 300 nA and I max AB = 200nA, the related transconductances are g min mp = 8,78µS and G max mEA = 6µS. The minimum load current is stated to stand-by mode. K IN and K EX are both set equal to 1.8 to achieve a minimum phase margin of 60 • . The output capacitor is 20pF. The parasitic gate capacitance of the pass transistor is about 200 fF. The buer current gain is B = 1 in order to save the power consumption. The accepted trade-o is a larger occupied areas due to a higher value of the required compensation capacitors. The obtained values are C M = 2pF, C M B = 3.3 pF and G M c2 = 2.5 µS. The Fig. 3.29 shows the increasing of I AB with the I Load . The Fig. (3.30-3.31) show the benets of AB circuit, where the current eciency is kept above 99% when the load current is higher than 300 µA, while for low load current the system ensures a good value around 70%. At the same time, the GBW of the loop moves from 40 kHz when the output is under light condition, to around 360 kHz under heavy condition, improving the regulator transient response. Generally, depending on the fabrication technology, the output capacitor can be integrated for values up to 100 pF. As previously explained, higher value allows to respond more quickly to current demand in the case of low to high step, because it acts as charge supply. However the frequency response and the stability are largely aected by the value of this output capacitor. With the compensation topology adopted in this circuit there is a trade-o between the minimum Phase Margin achievable under stand-by condition and the value of output capacitor. Fig. 3.32 shows that the phase margin is inversely proportional to the value of C L . For example for the designed circuit the stand-by output current is 250 nA (dashed line) and the output capacitor value is 20 pF, thenthe PM achieved is about 70 • . Therefore if C L is replaced by a larger capacitor of 50 pF to reduce the output voltage spike, the minimum stand-by current has to be increased, to about 800 nA (dash-point line), to achieve the same PM of 70 • . Fig. 3.33 shows that heavy load condition the output capacitor has no impact on the phase margin. A minimum phase margin of 90 • (Fig. 3.34) is achieved in operating range assuring a stable regulation also with a light load. For the MOS technology used in this work, the technology current I 0 =0.63 µA for Nchannel transistor and I 0 =0.187 µA for P-channel transistor. The other two design parameters are the drain current and the channel length. Since the drain current is xed by the application, the size is related to the choice of the IC and the channel length to calculate the width of transistor. All transistors work at low side of the moderate inversion. This is an accepted trade-o between transconductance-current eciency and frequency response. Moreover in this region the transistor achieves high power eciency and low voltage bias. Therefore the range of IC considered for the design is between 0.1 and 0.5. Minimum channel length is avoided for all transistors in order to make the circuit more robust against V gs and V th mismatch. Moreover longer channel transistor operating at low side of Moderate Inversion exacerbates frequency response. Therefore a L = 0.7 µm for all transistors is chosen to limit the parasitic capacitance associated to the internal node of the circuit.

The bias transistor M b as previously introduced is the only device that operates in strong inversion. With a drain current of 30 nA this operation mode is possible because the gate voltage is externally driven. The channel width is 0.35 µm.

The input signal transistors M 1 -M 2 and M A1 -M A2 are sized with an IC = 0.3, to limit drain current mismatch due to threshold voltage variations. Assuming an higher drain current dictated by the class-AB operation (≈ 500nA) the resulting W is equal to 1.8 µm. The nal value is decreased to 1.4 µm to accomplish layout techniques as common centroid or interdigitized topologies. The two sink transistors M A3 -M A4 have to support twice the drain current than the input signal transistor. This leads to W = 2.8 µm.

For the PMOS current mirror transistors M 3 to M 6 the main trade-o is between the drain current mismatch and the DC gain of the Error Amplier. Therefore, with IC = 0.5 the W equals 3.5 µm.

The same design criteria is adopted for NMOS sink current mirror M 7 -M 8 . This leads to W = 1.4 µm.

The PMOS cascode transistor is designed to have a V sg = 200mV. With a drain current of only 2 nA, the transistor has to operate in deep Weak inversion. Therefore for IC = 0.01 W equals 0.7 µm Adaptively Bias Circuit The adaptively bias circuit is designed to transfer a scaled version of load current with a scaled factor of 5000. Moreover it is designed to be completely o at light load condition. In order to draw a low quiescent current the factor n ≈ 10000. Therefore the total quiescent current for the circuit at heavy load is about 140 nA, where each branch draws 70 nA. The aspect ratio of the transistors are: S M AB1 = ( 0.4 4 ), S M AB2 -M AB3 = ( 0.7 7 ) and S M AB4 = ( 2.8 0.7 ). Finally to achieve the desired scaling factor m = 1/2, the aspect ratio of S M AB equals ( 5.6 0.7 ).

Introduced in chapter one.

CHAPTER 3. VOLTAGE REGULATOR Current Buer The current buer is designed to present a transconductance of 2.5 µS to compensate the feedback loop. At weak inversion the equivalent current is about 80 nA. With a L = 0.7 µm and a IC = 0.1, the width of channel is W = 1.4 µm. The current mirror is designed to have B = 1, so the two transistors have the same aspect ratio of S M C1 -M C2 = ( 1.4 0.7 ).

Voltage Reference

Most of the time, nominal operation conditions of electronics devices can change due to extreme variation of environment property or to external interference. Especially temperature is one of the main factor, since that many of transistor parameters are temperaturedependent. The main goal of voltage reference is to generate a stable voltage independent to supply voltage and temperature. An independent supply voltage circuit means that once the equilibrium point is reached the bias condition does not change with the supply voltage. However to eliminate the thermal dependence, it is needed to create two quantities (voltage or current) exhibiting an opposite trend with the temperature. The three main aspects to be evaluated to quantify the robustness of a voltage reference are: temperature coecient, power supply rejection ratio PSRR and the minimum supply voltage.

Temperature Coecient

The temperature coecient quanties the output voltage variations respect to the temperature.

T C ef f = 1 V ref -nom V ref -max -V ref -min T max -T min (3.41)
where V ref -nom , V ref -max and V ref -min are the output reference voltages at room nominal maximum and minimum temperatures.

PSRR

It is a small-signal characteristic and indicates the capability of voltage reference to suppress the voltage ripple coming from the voltage supply

P SRR = 20log δV ref δV DD (3.42)
where δV ref is the ripple of the output voltage.

Minimum Supply Voltage

The minimum supply voltage is the value from which the output voltage reference is constant. Normally it is measured at room temperature. that acts as resistor being in triode region under Strong Inversion condition. As explained the voltage reference has to be supply independent; in this case the transistors M 1 -M 2 and M 8 with the two relative mirror current PMOS transistors generate the current in a self-bias way. This current is then mirrored in the other three branches. The output voltage reference is then equal to

V ref = V ds7 + V ds6 + V ds4 = V gs7 + V gs6 -V gs5 + V gs4 -V gs3 (3.43)
As the transistors work in WI, the Eq. 3.43 can be rearranged as

V ref = V gs4 + nV t ln S 5 S 3 S 6 S 7
(3.44) Eq. 3.44 shows that a V ref independent from the temperature can be obtained if the two temperature coecients of the two terms on right side of the equation are opposite. This circuit oers the advantage of eliminating resistors that for nanopower circuits assume high values and therefore large silicon area.

De Vita Voltage Reference To accomplish the main task of voltage reference, in [START_REF] Vita | A sub-1-v, 10 ppm/ circi c, nanopower voltage reference generator[END_REF] the temperature dependence of electrons mobility is eliminated.

The transistors M 1 and M 7 (Fig. 3.36) have gate oxide thicker than the others so higher threshold voltage. In this way the transistors M 1 -M 7 and M 2 -M 8 are biased in WI and SI respectively. The current I 0 generated in the load M 9 is proportional to the square of thermal voltage and the carrier mobility Since the load transistor is a diode connected in saturation region under SI conditions, the output voltage reference is given by

I 0 = µC ox S 8 2 S 8 S 2 -1 2 η 2 V t 2 ln 2 S 7 S 1 (
V ref = V th10 + ηV t S 8 S 2 -1 S 8 S 9 ln S 7 S 1 (3.46)
Adjusting the aspect ratio of transistor involved in the Eq. 3.46 the temperature dependence of the output voltage reference can be eliminated.

Bandgap Voltage Reference Normally the use of bipolar transistor as current reference in the circuit makes the output voltage equal to the bandgap voltage of the silicon (≈ 1.12 V). The output voltage reference generated by the circuit is given by

V ref = V BG + ψ V be ,T + 5 i=0 V t ln S 2i S 2i-1 (3.47)
where V be is the silicon bandgap voltage, ψ V be ,T is the temperature coecient of baseemitter voltage. Choosing a correct aspect ratio of the involved transistors, the second term in the right side of the equation can be reduced to zero.

In conclusion all the introduced circuits share dierent aspects: To eliminate the temperature dependence 2 quantities are needed: one that has a negative temperature coecient CTAT (complementary to absolute temperature), that can be generated by a voltage or a current. The other has to increase with the temperature (proportional to absolute temperature PTAT) and the weight of both has to be equal. All circuit are working with a quiescent current in the range of nano-ampere. To generate this low current, large resistors are required with a prohibitive occupied area. Therefore only transistor must be used.

The main problem in the design of a voltage reference is the process variations. The exponential trend of drain current in WI region strongly impacts the performances of the circuit, since the deviation from nominal value is more important than in SI. Moreover the change in the threshold voltage due to the process variation can aect the stability of the output voltage reference. These considerations have to be taken in account into the design ow. The voltage reference implemented in this work is based on [START_REF] Mattia | 2014 IEEE 5th Latin American Symposium on Circuits and Systems[END_REF]. In the left side of the Fig. 3.38 the CTAT voltage generator is made with the bipolar transistor Q and the MOS transistors M 1 -M 2 .In fact the voltage at the node X, simply the base-emitter voltage of Q, is equal to V gs1 +V gs2 . Therefore the gate-source voltage of M 1 can be expressed as

V gs1 = V eb 2 (3.48)
This relation is true if the two MOS transistors have the same width and length channel and if the bulk-source voltage is equal to zero. As the CMOS technology process addressed in the present work allows a triple n-well conguration it is possible to tie the bulk node to the source potential. The pair of transistors M 9 -M 2 acts as the rst PTAT voltage generator. With this conguration V ds2 = V gs2 -V gs9 and it can be expressed as:

V ds2 = nV t ln pS 9 S 2 (3.49)
where p is the number of times that the reference current I ref is replicated to generate the PTAT voltage. To create a self-biased circuit, the voltage at node X is generated by the feedback path through the current mirror M 11 -M 10 . In this way choosing the factor K and the aspect ratio of transistors M 1 a non zero equilibrium point can be achieved. With the Eq. 3.48 and knowing that I Q =I ref × K, V eb can be expressed as

V eb = V t 2mn 2n -m ln I D0 K I sat 4A W 1 L 1 + V th nV t (3.50)
where n is the slope factor of MOSFET transistor, m and A and I sat are the slope factor, the emitter surface and the saturation current of the bipolar transistor. At this point to counterbalance the CTAT voltage, the only PTAT cell created by transistor M 9 -M 2 is not enough. Thus, 3 cascaded source-coupled [START_REF] Vittoz | A low-voltage cmos bandgap reference[END_REF] cells are added to eliminate the temperature dependence. To ensure the correct function of every cell, the top transistor has to be in saturation region. Moreover the drain current has to be greater than the leakage current of MOSFET and lower than the value for which the transistor stops to work in WI. Every cell generates a PTAT voltage equal to the drain-source voltage of bottom transistor

V P T AT = V ds,bottom = ηV t ln I d,bottom S top I d,top S bottom (3.51)
The maximum generated voltage is around 100 -120 mV. Therefore the total PTAT voltage is given by:

V P T AT,tot = ηV t ln I 7 I 5 I 3 I 2 I 8 I 6 I 4 I 9 W 8 L 8 W 7 L 7 W 6 L 6 W 5 L 5 W 4 L 4 W 3 L 3 W 9 L 9 W 2 L 2 (3.52)
Finally the output voltage reference is expressed as

V ref = V gs1 + V P T AT,tot (3.53)
Setting the aspect ratio of transistors and the current multiplication factor given by the number of stages in cascade, it is possible to obtain the CTAT coecient temperature which cancels the thermal dependence of output voltage. Surely one of the main design criteria is the power consumption. But as explained previously the drain current has to be higher than the leakage current. Moreover the aspect ratio of transistors is an important parameter to be taken in account, since it impacts the PTAT coecient and has to simplify layout techniques as in the case of common centroid. Considering this limitation, it was chosen S 1 = S 2 = 4 and K = 4. The currents I ref = I 1 = I 2 = I 3 = 6.5 nA, thus the collector current of Q is equal to 26 nA. This leads to have V x = 0.584 V. The aspect ratio S 9 is 18. The remaining transistors exhibit a form factor S 4,6,8 /S 3,5,7 = 5. Therefore the nominal output voltage reference obtained at 27 • C is 650.4 mV. The total quiescent current is 52 nA, for a power consumption of 62.4 nW. (2/1) M 10 (8/1) M 9

(18/1)

M 2 M 1 (4/1) M 4 M 6 M 8 (10/1) M 3 M 5 M 7 (2/1) Q 1 (emitter area)
Sub-bandgap simulation results In fact the transient time decreases from 3.2 µs without the adaptively bias to 0.78 ns when the circuit is inserted. It is worth noting that the magnitude of voltage spike is the same for both circuits. This is because at rst time the error amplier counteracts the output voltage variation slewing the gate capacitance of pass transistor. Only when the voltage changes at the EA output, the adaptively bias circuit supplies more current to the amplier, therefore the bandwidth of closed loop extends accordingly. It is clear that the two circuits with the same EA at the same bias point present an identical voltage spike. The situation appears dierent when the output current moves from moderate condition to heavy condition as in Fig. 3.46. In this case, at the starting point the closed loop bandwidth of the LDO is larger for the adaptively bias topology and the spike reduction is about 15 mV. The Fig. 3.47 shows the simulation result in the case of an input voltage step at heavy load condition. Besides the improvement in speed response, the adaptively bias gives better results in term of noise suppression. In fact the PSR at very low frequency is inversely proportional to the closed loop gain. The Fig. 3.48 underlines that when the adaptively bias circuit is removed the power supply rejection is at very low value of -10 dB, while with adaptively bias circuit the improvement is of about 25 dB. Montecarlo simulations were performed for the phase margin (PM) (Fig. 3.49) and output voltage Fig. 3.50. In particular for the PM only worst cases were addressed. The results shows a mean of 92 • with a standard deviation of σ = 0.67 • for I load = 1µA and a mean of 65 • with a standard deviation of σ = 3.9 • for stand-by condition. For the output voltage the two extremes of the operating condition were addressed. In this case a mean of 1.029 V is obtained with a standard deviation of σ= 0.025 V for I load = 1µA. For I load = 1mA the regulator shows a mean of 1.004 V with a standard deviation of σ= 0.024 V.

Conclusion

An adaptively biased LDO regulator has been designed for harvesting applications. Class AB Error Amplier and adaptively bias circuit have been adopted to improve the transient response with high current eciency under all load condition. The stability of the feedback loop has been guaranteed by the Miller compensation capacitor with the aid of the current buer. The regulator exhibits a minimum PM about 65 • for a load current lower than the minimum value in operating range. In this way the stability has been ensured also under stand-by condition. When the adaptively bias is inserted, the time to recover the nominal output voltage is lesser than 1 µs consuming only 2,25 µW under heavy load condition. Also AC performances take advantage because the error amplier exploits higher voltage gain due to high quiescent current. The FOM = t r Iq I load,max is introduced to compare the dierent designs, lower value means better performances. Larger FOM respect to [START_REF] Keikhosravy | A 0.13µm cmos low-power capacitorless ldo regulator using bulk-modulation technique[END_REF], where the quiescent current is constant for all load range, is balanced by a better current eciency especially at light load condition. However, considering the strict requirements for the regulator, the designed LDO is well suited for harvesting applications. Table 3.4 Comparative switching regulator Chapter 4

[KM14] [ZG12] This Work V out (V) 1 - 1 V DO (V) - 0.

Ultra-Low power transmitter

Transmitter is one of the most hungry circuit in a communication system. Especially in long range transmission, where high output power level (> 20 dBm ) is required, the power amplier (PA) needs high quiescent current to assure high voltage gain. Moreover the system requires a stable frequency carrier and a clean spectrum to avoid adjacent channel interference. Clearly satisfying all those requirements means complex system and thus higher power consumption. To comply the necessity imposed by the energy constrains in harvesting system, the design approach of transmitter has to be revisited. At rst the communication distance is no more longer than 10 m and thus the transmission power level is in the range of tens-hundreds of µW (-20 dBm to 0 dBm). Therefore when the communication distances decrease, as in the case of the WSN, the PA weight in terms of power consumption is comparable with that of the local oscillator LO and matching network MN. For example adopting high performances receiver, with a frequency correction loop scheme, is possible to use simple and not very accurate local oscillator on the transmitter side. In this way it is possible to avoid high power PLL based frequency generator or high cost crystal reference based system. As reviewed in chapter 2, a non coherent modulation scheme (OOK or FSK) permits to reduce the power consumption and relax the power amplier linearity, and the low-complexity architecture is a favorable point for ULP transmitter. Unfortunately this conguration suers from a poor spectral eciency. In summary the paradigm "less is better" can represent a way to demolish the problematics of power consumption in ULP transmitter design. Clearly the performances achievable can not be comparable to the classical transmitter and depending on the application some aspects have to be sacriced. A classical two-step transmitter is depicted in Fig. 4.1. This topology is a modied version of direct-conversion architecture in order to avoid injection pulling phenomena [Raz99]. In fact one of the main problems is the high power signal at PA output, which can modify the frequency oscillation of the LO. With the two-step transmitter the PA spectrum is quite far from the frequency generated by the VCO, reducing the risk of frequency shift. However the number of blocks required to achieve high spectrum eciency and clean frequency are not negligible, unlikely this high power solution can represent a good approach for the target of this work. Since that in short distance communication the PA output power level is not high, the frequency pulling is less probable and a direct modulation scheme can be a optimum solution to implement very low-power transmitter. In fact only three blocks are needed to generate the RF signal, where the modulation is normally done in the frequency generation circuit Fig. 4.2. Both on-o keying (OOK) and frequency shift keying (FSK) can be implemented where the baseband signal directing modulates the signal transmission. Moreover non-linear high ecient power amplier can be adopted. It is clear that in direct modulation architecture every block has a more important impact on overall eciency respect to the high output power transmitter where the main design eorts are addressed to improve the PA ecient. Therefore the global transmitter eciency can be written as where P rad is the radiated power level, P DC,LO P DC,P A and P DC,mod are the DC powers dissipated by the local oscillator, the power amplier and the circuits which generate the modulation signal. It is worth noting that the maximum attainable PA eciency η P A not only depends on the PA operating class, but in short distance communication the matching network eciency has a crucial role in terms of power transmission capability. From the analysis in [START_REF] Han | Analysis and design of high eciency matching networks[END_REF] the eciency of a generic L-matching network can be expressed as

η M N = 1 - Q Q L - Q Q C ≈ 1 - R opti Rs -1 Q L (4.2)
where Q L and Q C are the quality factor of inductor and capacitor, Q is the total quality factor of matching network that depends on the transformation ratio between the optimum resistance R opti and the antenna resistance R s . The approximation is valid only up to 10 GHz, where the poor inductor quality factor dominates the overall eciency. Some considerations will be done further about the problematics of matching network design when the radiated power is in the range of tens of µW. Even if the transmission eciency (Eq. 4.1) gives us an instantaneous photography of the transmitter capability to save the available power, this does not highlight the energy cost to transmit a certain amount of data. Moreover, in WSN the transmitter is in stand-by mode for the most part of time.

An useful metrics used to evaluate the transmitter is the energy per bit (E bit ) needed to transmit a packet of information Where DR is the data-rate and P DC,tot and P DC,stand-by are the total powers burned by the transmitter in active and stand-by mode respectively, DC is the duty cycle. However this metric does not facilitate the comparison between dierent topologies. As rst it does not provide information about the radiated power, second to recover the information about the power dissipated in stand-by mode is not always possible. Therefore generally only E bit is used to compare dierent transmitters. To have a more complete framework, the FOM introduced in [TLHL14] [VHH + 11c] can be used to evaluate the performances of dierent topologies

F OM = E bit P rad (4.4)
The above equation relates the transmission eciency and the data rate highlighting the relation between the transmitter architecture and the application/standard. transmission of 400/500 MHz makes hard the passive integration. An extremely low complexity transmitter (dot 4 in the g.4.3) is presented in [MBL + 13]. The transmitter is composed by a direct-RF power oscillator, where the inductor acts as resonator and radiating element. The carrier frequency in this case is 2.4 GHz. The cross-coupled NMOS oscillator is tail-biased with ultra-low leakage transistor to reduce the stand-by leakage power. The transmitter is designed to support both FSK and OOK modulation. From the above analysis, ULP transmitters for short distance range prefer non conventional architecture to reduce the power consumption with low output power and medium/high data-rate. However good performances can be achieved with classical architecture. In the next section several classical direct modulation architectures are reviewed supported by a design guideline to achieve low power consumption. In classical direct modulation transmitter, optimizing not only PA but also LO and MN is possible to achieve low-power condition, especially with modern devices where the transition frequency easily exceeds 100 GHz for submicron technology. For example, the STMicroelectronics 130 nm CMOS technology oers MOS transistors with a peak f T of 120 GHz. In addition, the MOSFETs used in low power applications are generally small and therefore, their peak transition is higher than bigger transistors, even if the lower transconductance due the low bias current soothes this improvement. In any case, this high peak f T allows subthreshold operation, in order to reach higher transconductance eciency (g m /I d ). As a consequence, the same RF performances are achieved at lower power consumption. Another design key point is the choice of voltage supply. As the power consumption is directly proportional to V 2 dd , decreasing the supply voltage considerably enhances the circuit eciency. A lower V dd also reduces the electric elds in the device and improves its long term reliability. On the other hand, low V dd reduces the voltage headroom available for cascading transistors, invoking folded solutions. In the next section the design considerations and the techniques as well as the dierent circuit blocks of the transmitter are described.

Local Oscillator

The carrier frequency generation can be done through voltage control oscillator VCO. The VCO can be classied in two main architectures: ring oscillator and LC oscillator. Irrespective of the topology the equation for the instantaneous VCO frequency is The frequency oscillation of a ring oscillator is

f V CO = f o + K V CO V ctrl
f = 1 2N t d (4.6)
where N is the number of delay cell and t d is the delay time of each cells. As the oscillation frequency is inversely proportional to the delay time and which depends on the bias current I ref , V ctrl provides control for the oscillation frequency. In LC oscillator the frequency is generated through a lossy resonator. In order to sustain the oscillation a small-signal equivalent negative resistor has to be inserted to cancel out the losses, generated by the inductor and capacitor parasitic resistor. Fig. 4.7 shows a general representation of an LC oscillator, pointing out the negative resistor. The frequency oscillation is given by the resonant frequency of LC tank (Eq. 4.7). To set the desired frequency, the circuit is designed with a tunable voltage capacitor (VariCap).

f = ω o 2π = 1 2π √ LC (4.7)
One of the most important property of a VCO is its phase noise. In a noiseless VCO the output voltage is expressed as

V out (t) = A cos(ω o t + φ) (4.8)
where A is the output voltage amplitude and φ the phase. However in presence of a noisy source the amplitude and the phase are altered. In particular, as depicted in Fig. 4.8 if the noise is injected at the signal peak, the amplitude changes without phase shift, and it recovers its nominal value due to the limiting mechanisms in a real oscillator. While if the noise is injected during the transition Fig. 4.8, the signal phase is shifted and this uctuation persists innitely [START_REF] Hajimiri | Jitter and phase noise in ring oscillators[END_REF]. Therefore the Eq. 4.8 has to be rearranged as follows

V out (t) = A(t) cos(ω o t + φ(t))
(4.9) where A(t) and φ(t) are the output voltage amplitude and phase time-dependent. A denition of phase noise [START_REF] Mazzanti | Class-c harmonic cmos vcos, with a general result on phase noise[END_REF] is as follows

L(∆ω) = 10 log N L,i 2∆ω 2 C 2 A 2 (4.10)
where N L,i is the white noise source and ∆ω the oset frequency from the carrier at which the phase noise is measured. One of the unwanted eect of phase noise is the downconversion of adjacent channels in the band of the desired signal. Another important property of a VCO is the range that the oscillation frequency can be varied from its center frequency also named tuning range. For example a VCO with a center frequency of 2.4 GHz and a tuning range of 10% gives the possibility to vary the frequency between 2.16 GHz and 2.64 GHz. A large enough tuning range is important in order to address the frequency shift due to the process and temperature variations.

Ring versus LC Oscillator

In terms of phase noise the LC oscillator has better performances, because of the resonator quality factor Q. A common denition of Q is

Q = 2π
energy stored energy dissipated per cycle (4.11)

In a high Q resonator the energy is transfered between the capacitor and inductor with a little dissipation in parasitic series resistances. In this case, the LC oscillator exhibits therefore a low phase noise. In a ring oscillator the energy is stored in the parasitic capacitance of the next stage, that is charged and discharged every cycle. Therefore regarding the Eq. 4.11 LC oscillator has a Q higher than the RO one. Since phase noise is inversely proportional to the quality factor [START_REF] Lee | Oscillator phase noise: a tutorial[END_REF], clearly at the same power dissipated LC oscillator achieves better performances. Low frequency noise aspect that makes the RO more noisy is that its noise is high during the transition, which is the worst case scenario in terms of phase shift as previously explained. A high tuning range is often needed, whether to account for process variations. If a high tuning range is needed, a ring oscillator should be used. This because the parameter that can be varied to change the frequency of the ring oscillator can be varied over wide range. It is possible to reach a tuning range over 50%. In the case of LC oscillator the tuning range is more limited. In spite of limited tuning range, LC oscillator has been preferred due to better performance in terms of phase noise, and lower power consumption for the same phase noise value.

Designing Low Power LC Oscillator

As discussed previously, LC oscillator is formed by a tank resonator and an active part needed to sustain the oscillation and to assure the start-up condition. Once the oscillation is started, the energy conservation law states that the maximal energy stored in the inductor should match the maximal energy stored in the capacitor:

CA 2 peak 2 = LI 2 peak 2
(4.12)

A peak is the voltage peak across C, and Ipeak is the peak current amplitude through L and its parasitic series resistance R s . The eective losses in the tank can be calculated as

P loss = R s I 2 peak 2 = R s 2 C L A 2 peak (4.13)
Reminding that the oscillation frequency is ω o = 1 √ LC this expression can be rearranged as

P loss = R s 2 C 2 ω o 2 A 2 peak = R s 2L 2 ω o 2 A 2 peak (4.14)
one can remark that for a given oscillation the losses, therefore the power consumption, scale with R s and are inversely proportional to L 2 . The previous equations suggest that the tank design should maximize the L/C and/or the L/R s as well. The rst goal might be limited by the required tuning range while the second one by the given technology. Eventually, it is worth noticing that the losses quadratically scale with A peak . However, as Eq. 4.10 states a reduction in output voltage peak makes higher the phase noise. The inductor L is not only a indispensable player for the frequency generation, but it is an important design parameter to achieve low power consumption with good phase noise. At frequency of interest the parasitic resistance associated to the LC tank R p is due mainly to the inductor series resistance R s . Giving the inductor quality factor Q L it is possible to transform the lossy LC tank into a parallel RLC circuit: of the oscillator needed to satisfy the Barkhausen's criteria. The oscillation is sustained if an adequate loop gain is assumed:

Q = Q s = ωL s R s = Q p = R p ωL p
g m1,2 2 > 1 R p = R s (ωL) 2 (4.16)
where g m1,2 is the transconductance of M 1 and M 2 . R p is forced by the inductor parameters; Eq. 4.16 states that a critical transconductance g mcrit has to be assured. In general the active part is designed to have a g m three times higher than g m,crit . Depending on the transistor operation region, the g mcrit depends only on the drain current in WI and by the transistor size in SI. Eq. 4.16 suggests a high value of L is preferable in addition with high quality factor to achieve lower g mcrit . However the low quality factor of integrated inductor and the larger area occupied by high inductance limit the minimum power consumption achievable. If a sucient voltage headroom is available, a way to half the power consumption is to implement a CMOS LC oscillator as depicted in Fig. 4.11. Stacking PMOS and NMOS transistors, the transconductance presented to the LC tank is twice than the only NMOS topology. The g mcrit in this case is equal to:

g mcrit = g m1,2 + g m3,4 2
(4.17)

where g m3,4 is the transconductance of cross coupled PMOS transistor. Observing the Eq 4.17 the same NMOS cross coupled g mcrit can be achieved with the half of current bias. The VCOs depicted in Fig ( 4.10-4.11) exploit a current source to stabilize the bias point even if this comes with a higher phase noise. If the current source is omitted, larger signal swing, lower power dissipation and lower phase noise can be obtained even if the bias point will be more sensitive to temperature and bias voltage variations and electronics aging, as well.

Power Amplier

As introduced previously, the PA eciency is mainly set by its operating class. Classical topologies (A, B, and C class) use the transistor as an amplier and the operating class is set by the quiescent bias point and the amplitude of the input signal; PAs in Fig 4 .12 are indeed not small-signal ampliers, so the input signal is allowed to modify the transistor bias point.

For these classes the eciency should be a trade-o with distortion issue. It is also useful here to remind that over-voltages are present in class B and C PA, so that a maximum voltage of twice V DD is applied to the drain of the transistor. This might causes a trouble of long-term reliability. Theoretically, 100% eciency can be achieved by using switching topologies (D, E, and F class), where the transistors are used as switch and no more as amplier. The main idea is to avoid that current ows into a transistor when its drain-source voltage is not zero. So, current can ow but the drain-source should be zero (the transistor acts as closed switch) or the drain-source should be not zero but the transistor is o and so current cannot ow (the transistor acts as an open switch). In both cases the transistor is kept cold, because no dissipation takes place. Long term reliability troubles plague also the class E PA, where the maximum voltage applied to the drain can rise up to about 4 times V DD , while this is not the case for the class D and F, where the drain voltage does not exceed V DD .

Switching/non-switching PA?

Switched PA requires large transistors to achieve smaller on-resistance and these transistors should also be hard driven, as they should operate like switches. As pointed out by Chee [ea06], the resulting high drive requirement largely increases the power consumption. In addition, the matching networks for switched PA are complex and require several inductors, resulting in larger silicon area and higher losses, making this type of PA not suitable for low radiated power applications. On the other hand, non-switched PA requires less drive capability oering higher transmitter eciency for low radiated powers. For this reason, non-switched PA was adopted in the present work. In particular, class-C operation was used. It is here worth reminding that, as previously described, the OOK scheme does not pose constraint on the PA linearity and therefore a class C PA is well suited in spite of the distortion. As the conduction angle is well lower than π, the transmitter is not always active and low leakage transistors were preferred, in order to minimize the stand-by dissipated power even if their transition frequency In low power applications, matching network plays an important role, as it should guarantee that no power is wasted at the PA \antenna interface. However the MN eciency is deteriorated by the high transformation ratio required when the radiate power is in the range of tens of µW. The power delivered to the generic load resistance R L can be expressed as:

P 1 = R L I 2 1 = R L I 2 max 2π α -sin(α) 1 -cos( α 2 ) (4.18)
where P 1 is the power at the fundamental frequency, α the conduction angle, I 1 and I max are the fundamental and the peak current through R L . However, all PA topologies are most ecient when operating at their peak power, when the drain voltage experiences a full voltage swing of V DD . Therefore, observing the Eq. 4.19 for a very low output power either V DD has to be made very low, or R opti must be made very high:

P 1,max = V 2 DD 2R opti (4.19a) R opti = V 2 DD 2P 1,max (4.19b)
For example with P 1,max =-10 dBm, if the PA operates in class-B (α= π) and for a V DD = 1.2 V then R opti = 7.2 kΩ. At this point it is important to evaluate the impact of high R opti on the MN eciency. For sake of clarity the η M N equation is reported here:

η M N = 1 - Q Q L - Q Q C ≈ 1 - R opti Rs -1 Q L (4.20)
Once that the MN is inserted, if the network presents no-losses that means Q L close to innity, the ratio R opti Rs does not have any inuences on the eciency. However in real applications, as previously explained, the on-chip inductor exhibits a low quality factor and R opti value strongly aects the MN eciency. Expressing the power radiated from the antenna P rad as:

P rad = V 2 RF 2R s (4.21a) R s = V 2 RF 2P rad (4.21b)
where V RF is the voltage swing across R s , and equating the Eq. 4.18 and the Eq 4.21 the relation voltage-resistance is as follow

V DD 2 V RF 2 = R opti R s (4.22)
CHAPTER 4. ULTRA-LOW POWER TRANSMITTER According to the above equation the matching network eciency can be expressed as

η M N = 1 - Q Q L - Q Q C ≈ 1 - V 2 DD V 2 RF -1 Q L (4.23)
In the case of a standard value of 50 Ω for the antenna impedance, and for a PA operates in class-B, with P rad = -10 dBm the voltage across the antenna resistance V RF is about 0.3 V. Therefore, considering a supply voltage of 1.2 V and Q L = 10 the η M N = 62%. The Eq. 4.23 shows that to improve the global performances and to alleviate the matching network design a low supply voltage close to V RF represents a good solution.

Comparison of dierent low power direct modulation transmitters

All the considerations carried out in the previous sections on the single building blocks (VCO, PA, MN), have been addressed by designing several topologies of direct modulation transmitters in a bulk 130 nm CMOS technology. The goal is to transmit -15 dBm (about 32 µW) by keeping as low as possible the DC power consumption. As previously introduced the VCO pulling phenomena is less problematic when the output power is very low. One of the main interaction between the PA and the VCO frequencies, when are harmonically related, can happen via capacitive signal coupling. In general to avoid frequency drift due to the output load changes, a buer stage is interposed between the VCO output and the PA input to increase the isolation. As the power consumption increases consequently, and since the PA transistor provides sucient isolation for the targeted output power the use of buer stage can be avoided. Following the previous considerations the two direct modulation transmitters depicted in Fig. 4.13 have been designed with two dierent supply voltage for the PA stage to demonstrate the better eciency. Class-C PA and LC VCO are used for both the solutions.

Transmitter Design Steps

The rst designed block is the PA and a class-C operating mode has been chosen to achieve high power eciency. When operating in this mode the transistor is biased in sub-threshold region with a conduction angle (α) less than 180 • Fig 4 .14. Therefore the period where PA conducts is set by the DC voltage applied at the transistor gate and the overlapping sinusoidal gate voltage swing. It is clear that once all design aspects of the PA are established, the remain transmitter blocks (VCO) have to be designed in order to supply the required voltage amplitude at the PA input to proper set α and ensure the targeted output power.

Power Amplier

The PA design starts calculating the optimum output load resistor to ensure the maximum voltage swing admissible at the transistor drain V o,max . In this way the mini- mum fundamental RF current (I 1 ) value is achieved and its DC terms I DC consequently. Therefore the optimum load resistor can be founded from the Eq. 4.19. In this case a more general form is preferable:

R opti = V 2 o,max 2P 1,max (4.24)
The dierence in the two equations comes from the fact that in Eq. 4.19 a maximum voltage swing of V DD is supposed when the inductor works like a choke. The condition where the inductor carries only DC current and bypasses all the AC currents into the load is ωL choke R L with a ratio of about 10. For example:

For a full drain voltage swing of 0.8 V and considering the targeted output voltage of -15 dBm (∼ 32 µW) the R opti = 10 k Ω. Expressing the fundamental RF current as:

I 1 = V o,max R opti (4.25)
The peak drain current I max and the DC current are equals to:

I max = 2πI 1 1 -cos( α 2 ) α -sin(α) = 2π V o,max R opti 1 -cos( α 2 ) α -sin(α) (4.26a) I DC = I max 2π 2sin( α 2 ) -αcos( α 2 ) 1 -cos( α 2 ) (4.26b)
Taking a conduction angle of 150 • I max = 158 µA and the DC current is equal to 42.75 µA. However a voltage amplitude equal to V DD would require L choke of 6.5 µH which is impractical at 2.45 GHz even using o-chip components. However for the designed PA the supply voltage of 0.8 V limits the swing to 0.4 V, because of the 1.2 V voltage forced by the MOS technology. This limitation aects the DC and the RF current:

If V o,max = 0.4 V the R opti = 2.5 kΩ and for the same conduction angle of 150 • the peak RF current is I max = 353 µ A and I DC = 95.5 µ A The above considerations indicate that for the same output power, higher voltage swing at the output means higher load resistance but lower terms of RF current. Therefore the limit imposed by the MOS technology forces the transistor to work with higher drain current thus the PA does not operate at peak eciency condition. However the downside of high load resistance is represented by poor MN eciency when high conversion ratio is needed. In the case of R opti = 10 kΩ and considering the standard value of 50 Ω for the antenna impedance the Eq. 4.23 shows a negative value of η M N , because the maximum quality factor Q L achievable by the inductor is lower than the quantity R opti Rs -1. A practicable MN is possible when the R opti = 2.5 kΩ, but a poor η M N = 42% demonstrates the drawback of high transformation ratio that signicantly impacts the overall performances. All these considerations are based on the fact that the inductor does not work like a choke and a practical value is possible.

The following items are some points to note in this case:

The higher the ratio of impedance transformation the higher the Q of the transformation is. For a higher Q transformation, the intrinsic quality factor of the inductor in the network must be higher to minimize the losses in the network itself.

CHAPTER 4. ULTRA-LOW POWER TRANSMITTER When the transformation ratio is very high, it is sometimes better to do the transformation in multiple steps, but this also degrades eciency of the network, and leads to more area. A trade-o between the power consumption and the matching network design appears when the power radiated is in the range of tens of µW. Fig. 4.16 shows the trends of I peak and I DC for three dierent values of R L (2.5 kΩ, 1.25 kΩ, 0.60 kΩ) with the same output peak voltage of 0.4 V when the conduction angle moves from 10 • to 180 • . As illustrated, the peak currents increase when the load resistance decreases in order to keep constant the output voltage swing, and thus also the DC current increases consequently. Another important point is that the DC current decreases when the conduction angle decreases , while the peak current increases forcing the transistor to work in current capability limit.

The simple L-matching network in Fig. 4.15 demonstrates that a non-integrable onchip inductor is needed to transform higher impedance to 50 Ω. Since the application requires low power consumption the PA should be designed with the highest load resistance and low conduction angle to exploit the low range of DC RF current. However as the main limiting factor is the implementation of matching network, higher power consumption has to be accepted due to a lower load resistance. To increase the network matching eciency above 50% and to make feasible its implementation a load resistance of 1.25 kΩ is chosen. To present the correct impedance at the drain of MOS transistor and to lter the unwanted harmonics a π-matching network is used to transform 50 Ω to 1.25 kΩ. This MN performs a better integrability respect to a simple L-matching topology. As seen from the Fig. 4.17 the inductor value scales down from 17 nH to 11 nH and also the capacitor increases from 257 fF to 450 fF, making the MN less susceptible to the capacitive parasites. Since the targeted power is equal to -15 dBm (∼ 32 µ W) and with the constraint of R L the peak output voltage is equal to V o,max = √ 2R L P out = 0.282V . Once the load resistance is set, to perform a class-C power amplier a conduction angle less than 180 • has to be chosen. As explained previously the DC and the peak currents are aected when the conduction angle moves from 10 • to 180 • . To limit the peak current below 1 mA, it is possible to observe the trend of I RF and I DC from the Fig. 4.18 and α = 150 • (≈ 2.7 rad) is chosen that conducts to a I DC ≈ 132 µA. The transistor is sized taking in account the MOS eciency and the required voltage swing at the gate. In fact this latter relates

VCO implementation

The rst design step for the LC VCO in Fig. 4.13 starts with the denition of the inductance parameters. As explained previously the best inductor is the one with the highest parallel resistance, since it will lead to the lowest required transconductance and hence consumption. Moreover high R p value permits to increase the output voltage swing improving the phase noise performance. Therefore the dierential output voltage swing can be expressed as

V out,dif f = 4I bias R p π (4.28)
To nd the appropriate inductance value the quality factor and the parallel resistance have been simulated for dierent values of L. Fig. 4.19 shows the results when sweeping the inductance value from 6 nH to 15 nH at the frequency of interest of 2.4 GHz and for a constant outer diameter of 280 µ m. The simulations are related to a coil inductor width of 6.5 µ m and for a number of turns equal to 6. As expected from the Eq. 4.15 R p increases with L, while Q L exhibits a parabolic shape. In order to achieve the best ratio Q L L , the inductance value chosen is 10 nH that entails a R p of about 1.7 kΩ. Considering a tolerance margin factor of 3 to ensure start-up condition against PVT variations the g mcrit of the active part has to be greater than

g mcrit > 1.8mS (4.29)
However the main design criterion for the VCO is to ensure the voltage swing at its output which permits to drive properly the PA. The 535 mV of amplitude leads to a bias current of 240 µA. As the transistors exploit WI operation, the related transconductance can be found from the relation

g m = I D nV T (4.30)
With the slope factor n = 1.5, the thermal voltage V T = 26 mV and the drain current I D = 120 µA the transconductance is g m = 3.076 µS. This value is largely sucient to ensure the start-up condition. Each cross-coupled PMOS transistors have a size of 60 µm/0.13 CHAPTER 4. ULTRA-LOW POWER TRANSMITTER µm, while the NMOS pair has a size of 30 µm /0.13 µm. The tail transistor has a size of 120 µm/ 0.13 µm.

To tune the frequency of oscillation, two n-type accumulation mode MOS varactors are used. The variable capacitors are connected in parallel with the inductors. The tuning voltage V ctrl is applied at the drain/source terminals. Some aspects have to be investigated to reduce the gate resistance and the tank losses consequently. To increase the varactor quality factor, the channel length has to be kept at the minimum value, while an high number of gate ngers allows to decrease the gate resistance. However the width of each ngers is a compromise between the quality factor, the parasitics and the varactor size.

Transmitter Simulation Results

Two transmitters have been designed to demonstrate the high eciency when the PA is supplied with a low voltage. Therefore in the rst one the VCO and the PA share a single supply voltage equal to 0.8 V, while for the second one the PA is supplied with V DD = 0.4 V. For both transmitters only DC-blocking capacitor is used to interface the VCO output to the PA input. This is sized to provide minimal capacitance dividing at the fundamental frequency.

Single Supply Voltage In the transmitter supplied with a single V DD the PA dissipates about 212 µW for a 15% of eciency. Therefore the transmitter has global eciency of 8%.

Double Supply Voltage

Since that the PA is supplied with lower voltage some modications have been needed to achieve the best eciency. The MOS transistor has a larger width (60 µm) and the matching network was adapted consequently. The PA transmits the signal with the same conduction angle of 150 • that corresponds to a dc current of 301 µA. The power dissipated by the PA is now about 120.4 µW for a 26% of eciency. As consequence the transmitter presents a better global eciency about 10%. The Monte Carlo simulations Fig. (4.23-4.24) were performed for the output power. In the case of single supply voltage the transmitter shows a mean of 28µW with a standard deviation of σ=8 µW. While for the double supply voltage the mean value is 31 µW with a standard deviation of σ = 8.5 µW.

In this section two direct modulation transmitters have been designed for -15 dBm output power, both transmitters are made up by CMOS voltage control oscillator and a class-C power amplier. However the rst one adopts a single V DD = 0.8 V for both VCO and PA, while in the second one the PA is supplied with a low voltage V DD = 0.4 V to improve the global eciency. The trade-o between the optimum PA load resistance, the matching network and supply voltage is demonstrated. The simulation results prove that for the low output power a low V DD relaxes the constraints on the matching network and higher eciency can be achieved. However the main drawbacks when two voltages are required is the greater complexity in the Power Management Unit due to the necessity of another voltage regulator and the increasing power consumption consequently. In the next section a very ecient transmitter is presented that permits to overcome the inconvenient described above. In the previous section the issues about the supply voltage and the matching network at the PA output have been discussed. For very low output power a low V DD was preferred to alleviate the MN and to improve the overall eciency. However in this work the transmitter is supplied by the regulator described in the previous chapter, which presents an output voltage of 1 V. Surely this voltage does not match very well with the targeted output power of -15 dBm. Therefore to eliminate the necessity of a second regulator to supply an appropriate voltage for the power amplier a current reuse transmitter has been design. The idea is depicted in Fig. 4.25, where two possible topologies can be implemented depending if the VCO or the PA is stacked on the top or on the bottom. Two main features can be founded in stacked architecture. The rst one is related to the total bias current that is recycled from the top block to the bottom one saving power. The second one is related to the supply voltage, since it can be splitted in two optimized voltages for each block. Therefore this architecture can solve the constraints for the targeted output power, where the supply voltage ratio between the VCO and the PA can be adjusted to reduce the required optimum resistance at the PA output.

Current Reuse VCO

The LC VCO implemented to generate the frequency carrier is a current reuse topology [START_REF] Yun | A 1mw current-reuse cmos dierential lc-vco with low phase noise[END_REF]. Fig. 4.26 shows the transistors implementation and the two operating states. The circuit is derived from a classical NMOS cross coupled oscillator, where one of the two NMOS transistors is replaced by a PMOS. Respect to the NMOS topology, the two transistors are on at the same time in the rst half of oscillation period when the potential at V out 1 is high. Therefore a direct path is created from the supply voltage and the ground through the transistors and the energy is stocked in the inductor. In the second half period, when V out1 is at low level, the (N-and PMOS) transistors are o and current ows through the capacitors. It is interesting to highlight that in the rst half period the oscillator is in the voltage limited operation where the amplitude of the oscillation can extend up to V DD . In the second state no limitation is present and the peak oscillation can exceed the supply voltage.Another remarkable point is that the same feature of CMOS cross coupled VCO can be founded in the current reuse topology. Since the transistors switch on at the same time the transconductance presented is twice of that NMOS cross coupled topology for the same bias current. Moreover the absence of the common source node avoids noise addition from the second harmonic term and improve phase noise performance due to a low icker noise of the PMOS transistor. However without some modications, current reuse oscillator is not suitable for fully dierential applications since that the output voltage swing is not balanced. The reason comes from the two dierent operating modes, in the rst and in the second half period, and from the large drop in the dynamic current. To re-equalize the output a bias resistor can be added between the NMOS source and the ground, to force the VCO to operate in limited current mode in both periods. However to work properly and to ensure start-up condition over PVT variations, the stacked topology has to be supplied with a voltage greater than the sum of PMOS and NMOS threshold voltage. For the RF transistors available in the design kit, V DD should be higher than 0.85 V. At this point it seems clear that the 1 V of voltage supply for the transmitter architecture is not suitable to ensure sucient voltage headroom for the PA and the VCO at the same time. To allow start-up condition also for low supply voltage the NMOS transistor can be biased separately to provide minimum negative resistance to sustain the oscillation [START_REF] Taghivand | A low voltage sub 300 µw 2.5Ghz current reuse vco[END_REF]. The Fig. 4.27 depicts the modied current reuse VCO, where the NMOS gate transistor is AC-coupled via C dec to the node Y, and the R bias represents the bias resistance. An ac-ground capacitor C AC is needed to ground all high frequencies voltage bias components. However the ac-coupling capacitor and the bias resistor have to be properly sized to provide high enough start-up gain. From the analysis done in [START_REF] Taghivand | A low voltage sub 300 µw 2.5Ghz current reuse vco[END_REF] the impedance seen at the node Y is expressed as

Z Y = ( 1 R bias,Y + |A v |g mn + g mp -|A V |g mn g mp R p ) -1 (4.31)
where R bias,Y is the equivalent bias resistance seen at node Y to the ground, A v = V X V Y is the voltage divider ratio between the node X and Y, R p is the parasitic resistance of the tank. Since Z Y has to be negative and high enough to ensure start-up condition, A v has to be close to one. Considering the gate-source parasitic capacitance of NMOS transistor C gs,nmos the decoupling capacitor C dec should be larger than the parasitic capacitance to ensure high voltage divider ratio. If C dec C gs,nmos R bias,y ≈ R bias , therefore to not degrade the tank quality factor R bias has to be higher than R p . However high value can degrade the phase noise performance due to higher thermal noise. Fig. 4.29 conrms this hypothesis, high value of R bias corresponds to worst PN R bias = 4.5 kΩ can represent a good trade-o. Fig. 4.28 plots A V versus C dec . It is worth noting that the voltage divider ration does not change signicantly for C dec > 750 fF thus this value has been chosen. Also for the current reuse oscillator the frequency tuning is ensured by two NMOS varactors and a 9 nH inductor with a quality factor of 12 at the oscillation frequency. Fig. 4.30 shows the phase noise at 1 MHz from the carrier frequency when the supply voltage moves from 0.6 V to 1 V. Fig. 4.31 shows the FoM and the power dissipation on the same supply voltage range. In the next section the current reuse transmitter is presented, where the power amplier stage is stacked on top of the VCO.

Designed current Reuse transmitter

The analysis done previously has demonstrated that 0.6 V external bias voltage V DD ensures the start-up condition for CR-VCO . Therefore 1 V of supply voltage can be adopted for stacked topology since the PA for the targeted output power of -15 dBm achieves better eciency when its supply voltage is in the range of few hundreds of millivolts. The partition of the supply voltage depends on the bias voltage applied at the gate of the PA NMOS transistor. Taking as example the where V DD,V CO is the oscillator supply voltage, V bias is the voltage applied to the gate of the NMOS transistor and V gs,M n is its gate-source voltage. Depending on the V DD,V CO and the PA operating classes the V bias has to be chosen accordingly. From the study carried out on about the power amplier in classical transmitter topology and observing the trend of the CR-VCO FoM, the supply voltage about 0.65 V is chosen for the oscillator thus the remaining 0.35 V for the PA is an appropriate value for the M.N. trade-o. The complete transistor level schematic is depicted in Fig. 4.34 where the PA is stacked on top to have the possibility to explore all PA operating classes and a better control on the output power. To implement current reuse topology and to shunt all AC components avoiding possible high frequency loop and providing a virtual V DD to the VCO, a shunt capacitor of 20 pF is inserted at the PA and VCO common node. In the Fig. 4.33 the trend of the voltage at node P over the time is depicted, since the VCO and the PA are two large signal circuits V p achieves nal value when the oscillation is settled. In this chapter a design methodology for transmitter in short communication distance has been presented. The output power of -15 dBm entails that the approach should be dierent from the traditional approach adopted to design long distance transmitter. To achieve low power consumption a direct modulation scheme has been adopted to reduce the number of blocks needed for the transmission. In the rst part of the chapter two classical transmitters have been presented where the voltage control oscillator and the power amplier are cascaded. The discussion mainly focused on the diculty to transform the preferably high load resistance, when the power transmitted is about few tens of micro-watt, to the standard 50 Ω input antenna impedance. The trade-o between the supply voltage, the bias current and matching network eciency have been demonstrated. To show the advantages when the PA is supplied by a lower voltage two transmitters have been designed. In the rst one the VCO and the PA share the same supply voltage of 0.8 V, in the second one the VCO maintains the same voltage while the PA is supplied with a voltage of 0.4 V. However a double supply voltage requires another voltage regulator, that means more power dissipated and more complex system. To circumnavigate this problem, a current-reuse transmitter has been proposed where the VCO and the PA are stacked and the bias current is recycled from the top circuit to the bottom one. The possibility to distribute a single supply voltage in two optimized voltage one for each block oers several degree of freedom for targeted output power, phase noise and power consumption. Moreover for this topology only one voltage regulator is needed reducing the complexity of the system.

Chapter 5

Conclusions

This work investigates the design of ultra-low power circuits for Harvesting applications, in particular LDO voltage regulator and transmission part are involved in the study. To address the design, the rst part of dissertation presents the low-power techniques at three dierent levels: transistors level, circuit level and system level. In addition the main sources of energy Harvesting are presented outlining the energy available at their output and the level of integration. As the application targeted is the possibility to replace battery with EH source in wireless sensor networks in order to extend the operation lifetime, some system aspects are presented. From the networks architecture to the link budget, data-rate and energy management aspects. These lasts are fundamental aspects to take into account to give the circuit specications. Moreover the equation to estimate the optimum DC for the lowest energy consumption is given. Chapter 3 shows that to reduce the regulator power consumption even beyond to use the Mosfet transistors in Moderate Inversion, the better way to reduce the energy budget is to adapt the quiescent current to the load current of the LDO voltage regulator. With the class-AB Error Amplier and an adaptively bias approach also the transient response is improved. Therefore the LDO exhibits a quiescent current that spans from 560 nA to 1.8 µA when I load moves from 1 µA to 1mA. While the time response is halved. The regulator is designed to transform a variable input voltage of 1.2 V in a stable output voltage of 1 V. Two architectures for the transmission part are proposed in chapter 4: a classical cascaded topology VCO-PA and a current reuse transmitter. As the radiated power is in the range of some µW, there is a severe trade-o between the matching network eciency and the power amplier supply voltage. The achieve a global power eciency about 10% the oscillator and the amplier, in cascaded topology, are supplied with two dedicated voltages of 0.8 V and 0.4 V. To avoid two voltage regulators which increases system complexity, the current reuse permits to tune unique voltage supply between the VCO and the PA alleviating the design constraints for the matching network. Therefore a comparable eciency of 10.5% is obtained. Moreover Montecarlo simulations demonstrate that current reuse topology is more robust against PVT variations.

Perspective

To validate the obtained simulation results, the circuits realization and its measurements are the obvious steps to do consequently. More interesting would be the possibility

1. 1

 1 Section of Photovoltaic Cell . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Typical implementation of PV harvesting maximum power point tracking. 1.3 (a) Seedback eect, the generated voltage is proportional to the temperature gradient between the hot point T H and the cold point T C (b) Peltier eect the current generated by the applied voltage causes a thermal diusion from the heat dissipation to the heat absorption. . . . . . . . . . . . . 1.4 Cut-o Frequency trend in function of current density for dierent node technology [WKvL + 01] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Combinations to achieve 8 nH inductance [Van15] where W is the metal width and N is the numbers of turns. . . . . . . . . . . . . . . . . . . . . . 1.6 Inversion coecient line number with voltage and shape factor MOSFET properties [Bin07]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Minimum supply voltage required in classical cascode OTA when the transistors are biased in strong and in moderate inversion. . . . . . . . . . . . . 1.8 Cascaded circuit block with two separate supply voltage and independent bias currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Multi-threshold application in logic circuit. . . . . . . . . . . . . . . . . . 1.10 Wake-up scheme timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Plot obtained from the measurement results for I = 2.3 mA and k = 1.25.2.2 Market forecast for EH devices used in WSN applications. . . . . . . . . . 2.3 Energy Harvesting WSN market in 2012 (a) and prevision of market in 2017 (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Power comparison between WSN and Energy Harvested circuit. . . . . . . 2.5 Architecure of energy harvesting sensor node. . . . . . . . . . . . . . . . . 2.6 Power management transistor level schematic implemented in [PCFP14] . 2.7 The top graph depicts an example of energy prole in harvesting system. In the bottom graph the trend of voltage stored into the capacitor (red line) and the regulated voltage at the output of the PMU. . . . . . . . . . 2.8 Wireless sensor network mesh architecture . . . . . . . . . . . . . . . . . . 2.9 Wireless sensor network star architecture. . . . . . . . . . . . . . . . . . . . 2.10 RICER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 General block diagram of voltage regulator . . . . . . . . . . . . . . . . . . 3.3 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii LIST OF FIGURES 3.5 Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Block Diagram of Buck Converter [WTM10] . . . . . . . . . . . . . . . . . 3.8 Regulated output voltage versus input voltage. . . . . . . . . . . . . . . . . 3.9 N-type and P-type pass element . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Basic LDO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Typical transient Response of LDO regulator . . . . . . . . . . . . . . . . . 3.12 Energy balancing from light to heavy step . . . . . . . . . . . . . . . . . . 3.13 Energy balancing from heavy to light step . . . . . . . . . . . . . . . . . . 3.14 LDO negative feedback diagram . . . . . . . . . . . . . . . . . . . . . . . . 3.15 Poles movement with load current . . . . . . . . . . . . . . . . . . . . . . . 3.16 Parasitic gate capacitance C g (a) and saturation drain-source volatage V sd-sat (b) of the pass transistor for dierent width W . . . . . . . . . . . 3.17 Class-A bias topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 Class-AB bias topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.19 Class AB error amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20 FVF cell with cascode Pmos transistor . . . . . . . . . . . . . . . . . . . . 3.21 Gain Voltage (a) and SR (b) simulation for I b = 60 nA for Class-AB error amplier in solid line and class-A dot line. The simulations are performed with C L =350 fF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22 Adaptive biasing system. The rest of the circuit is omitted for simplication purposes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 Block Diagram of two stages amplier with current buer compensation technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24 Transistor level design of the LDO voltage regulator proposed in this work 3.25 AB loop gain for dierent load current . . . . . . . . . . . . . . . . . . . . 3.26 LDO small-signal feedback representation . . . . . . . . . . . . . . . . . . . 3.27 K EX for dierent values of R o-EA and g mp . The minimum value of separation factor is for light load condition. R o-EA has negligible impact. . . . . . 3.28 K IN for dierent values of R o-EA and g mp . The minimum value of separation factor is for light load condition.Also in this case R o-EA has negligible impact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.29 The trend of the bias current adaptability versus the load current. . . . . . 3.30 LDO quiescent current and current eciency versus load current. In this case the trend is shown only for operation mode (I Load = 1 µA-1 mA). For stand-by mode the current eciency is worsen by the minimum drain current needed to keep ON the pass transistor. . . . . . . . . . . . . . . . . 3.31 (a) Open loop gain for I Load = 1 µA (black line) and for I Load = 1 mA (blue line). It is evident the GBW product is increased at heavy load condition due to higher G mEA . GBW extends from 40 kHz to 360 kHz (b) Phase for the two load conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.32 Phase margin versus output capacitor value, for dierent stand-by output current values.From I stand-by L = 205 nA (dash line) to I operation-mode L = 1 µA (solid line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.33 Phase margin versus output capacitor value at heavy load condition . . . . 3.34 Phase margin versus output current for all operating regions. . . . . . . . . 3.35 Ueno voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LIST OF FIGURES 3.36 De Vita voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.37 Bandgap Voltage reference proposed in [HUKN10] . . . . . . . . . . . . . 3.38 Sub-bandgap voltage reference used in this work . . . . . . . . . . . . . . . 3.39 Output voltage reference versus the temperature . . . . . . . . . . . . . . . 3.40 The quiescent current (a) and the voltage reference (b) versus supply voltage 3.41 Monte Carlo simulations on the output voltage reference with 100 runs. . 3.42 Line regulation (orange line) of LDO when V IN moves from 0 V to 1.6 V. The simulation is performed at heavy load condition. . . . . . . . . . . . . 3.43 Output Voltage versus output current . . . . . . . . . . . . . . . . . . . . 3.44 Transient response for a load current step in operation mode. From 1 µA to 1 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.45 Transient response for a full load current step. From 300 nA to 1 mA. . . 3.46 Transient response for a load current step in moderate condition. From 300 µA to 1 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.47 Line transient at heavy load condition . . . . . . . . . . . . . . . . . . . . 3.48 PSR at heavy load condition . . . . . . . . . . . . . . . . . . . . . . . . . . 3.49 Monte Carlo simulations on the phase margin with 100 runs.a) for stand-by condition b) for minimum operating load condition . . . . . . . . . . . . . 3.50 Monte Carlo simulations on the regulator output voltage with 100 runs. a) for minimum operating load condition b) for maximum operating load condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Block diagram of two-step conversion transmitter . . . . . . . . . . . . . . 4.2 Block diagram of direct modulation transmitter. . . . . . . . . . . . . . . . 4.3 FOM versus data-rate for recent ULP transmitter. [KPL17] . . . . . . . . . 4.4 Block diagram of sub-harmonic injection locking transmitter [PO11]. . . . 4.5 Power VCO transmitter presented in [MBL + 13]. . . . . . . . . . . . . . . . 4.6 Current starved VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 LC resonator with negative resistor to compensate the losses due to parasitic resistor R P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Output voltage variation in presence of noisy source. At the left side the noise is injected at the peak voltage, at the right side the noise is injected at zero transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Transformation of series LC tank to parallel one. . . . . . . . . . . . . . . . 4.10 NMOS cross coupled LC oscillator. . . . . . . . . . . . . . . . . . . . . . . 4.11 CMOS LC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 General representation of power amplier. . . . . . . . . . . . . . . . . . . 4.13 Transistor level schematic of direct modulation transmitters. Single voltage supply for both VCO and PA (a), double voltage supply to optimize the PA eciency (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Bias point to perform class-C operation mode(a) typical voltage and current waveforms at the transistor drain(b) Biasing the transistor at voltage lower than the threshold voltage permits to reduce the voltage and current overlapping period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Implementation of L-matching network to transform 50 Ω to the optimum load resistance of 2.5 kΩ. The large value of inductor makes dicult the integration of the passive element. . . . . . . . . . . . . . . . . . . . . . . . v LIST OF FIGURES 4.16 DC RF current and Peak RF current depending on the conduction angle for three dierent output resistances and for a V o,max = 0.4 V. The period of conduction refers only to class-C operating mode for 10 • <α<180 • . . . . 4.17 Implementation of L-matching and π-matching networks to transform 50 Ω to the load resistance of 1.25 kΩ. A lower value of inductor is possible when a shunt capacitor is added to the network. . . . . . . . . . . . . . . . 4.18 DC RF load current and peak RF load current for R L = 1.25kΩ and V o,max = 0.282V depending on conduction angle . . . . . . . . . . . . . . . 4.19 Simulated quality factor Q L and relative parallel resistance for dierent inductance values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Varactor quality factor (a) and capacitance versus tuning voltage (b) . . . 4.21 Frequency range versus tunning voltage . . . . . . . . . . . . . . . . . . . . 4.22 Phase noise performance measured at 1 MHz from the carrier frequency. . 4.23 Monte Carlo simulation on the single supply voltage transmitter output power with 100 runs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 Monte Carlo simulation on the double supply voltage transmitter output power with 100 runs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 Block diagrams of current reuse transmitter. The two possible solutions are reported depending on the position of the VCO and the PA . . . . . . . . 4.26 LC current reuse oscillator schematic.The two operating states are also illustrated for the two dierent oscillation periods. . . . . . . . . . . . . . . 4.27 Modied current reuse VCO for low supply voltage. . . . . . . . . . . . . . 4.28 Voltage divider ratio versus the decoupling capacitor C dec . . . . . . . . . . 4.29 Phase noise performance measured at 1 MHz oset from the carrier frequency versus the bias resistance. . . . . . . . . . . . . . . . . . . . . . . . 4.30 Phase noise simulation at 1 MHz oset from the carrier frequency versus the supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 FoM and power consumption for dierent supply voltage. . . . . . . . . . 4.32 Supply voltage trend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 Trend of the voltage at the common node P. . . . . . . . . . . . . . . . . . 4.34 Transistor level schematic of Current Reuse transmitter. . . . . . . . . . . 4.35 Voltage and Current transient at the M P A drain. . . . . . . . . . . . . . . . 4.36 Phase noise simulated at 1 Mhz from the carrier frequency. . . . . . . . . . 4.37 MonteCarlo simulation performed over output power. . . . . . . . . . . . . A.1 FVF cell with cascode Pmos transistor . . . . . . . . . . . . . . . . . . . . vi List of Tables 1.1 Comparative energy sources . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Comparative ULP receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Comparative switching regulator . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Current consumption of designed examples . . . . . . . . . . . . . . . . . . 3.3 Transistors Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Comparative switching regulator . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Drain current terms of PA MOSFET for dierent channel width, for the same conduction angle and output power . . . . . . . . . . . . . . . . . . . 4.2 Devices size for the designed transmitter. . . . . . . . . . . . . . . . . . . .

Figure 1 . 1

 11 Figure 1.1 Section of Photovoltaic Cell

  Figure 1.4 Cut-o Frequency trend in function of current density for dierent node technology [WKvL + 01]

  Figure 1.6 Inversion coecient line number with voltage and shape factor MOSFET properties [Bin07].

  Figure 1.7 Minimum supply voltage required in classical cascode OTA when the transistors are biased in strong and in moderate inversion.

  Figure 1.8 Cascaded circuit block with two separate supply voltage and independent bias currents.

Figure 1 .

 1 Figure 1.9 Multi-threshold application in logic circuit.

Figure 2 . 1

 21 Figure 2.1 Plot obtained from the measurement results for I = 2.3 mA and k = 1.25.

Fig. 2 .

 2 3 shows the market movement of EHWSN applications from 2012 to 2017. All

Figure 2 . 2

 22 Figure 2.2 Market forecast for EH devices used in WSN applications.

Figure 2

 2 Figure 2.3 Energy Harvesting WSN market in 2012 (a) and prevision of market in 2017 (b)

Figure 2 . 5

 25 Figure 2.5 Architecure of energy harvesting sensor node.

Figure 2 . 7

 27 Figure 2.7 The top graph depicts an example of energy prole in harvesting system. In the bottom graph the trend of voltage stored into the capacitor (red line) and the regulated voltage at the output of the PMU.

Figure 2 . 8

 28 Figure 2.8 Wireless sensor network mesh architecture

Figure 2 . 9

 29 Figure 2.9 Wireless sensor network star architecture.

Figure 2 .

 2 Figure 2.10 RICER.

Figure 3

 3 Figure 3.2 General block diagram of voltage regulator

  where R OL is the open loop output resistance, A ol the open-loop gain and β F B the feedback factor of the regulator. V out1 and V out2 are the boundaries of output voltages considered and I out1 and I out2 the respective output currents. The load regulation is related to the open loop gain of the converter. So higher open-loop gain is preferred to assure a better regulation.

  CHAPTER 3. VOLTAGE REGULATOR Transient Response: Output overshoot and undershoot Overshoot and undershoot response are the deviation from the nominal output voltage due to a transient signal in load or control line. The feedback control has large impact on this parameter. A wide bandwidth of the control loop ensures a small voltage variation and a fast settling time at the output voltage when a load/line transient occurs. It should be specied under which circumstances and operating points the overshoot or undershoot occurs.

Figure

  Figure 3.6 Switching Regulator

  .7. For example a design rule is that the Gain Bandwidth product (GBW) of the feedback loop should be kept limited within 1/5 or 1/10 of the converter switching frequency, to ensure that the switching noise does not increase. But unfortunately limiting the GBW of the control loop means a reduction of the transient response. It is clear that in terms of speed, switching regulator suers from the complexity of the circuit and from the severals trade-o in terms of ripple/transient/stability/regulation.

Figure 3

 3 Figure 3.7 Block Diagram of Buck Converter [WTM10]

Figure 3 . 8

 38 Figure 3.8 Regulated output voltage versus input voltage.

Figure 3

 3 Figure 3.9 N-type and P-type pass element

  Fig 3.10 the classical representation of LDO regulator is depicted. The role of the error amplier is to generate an error control voltage V EA at its output, according to the dierence between the scaled version of the output voltage V F B and the reference voltage V REF . The resistance divider, R F 1 and R F 2 , generates the voltage at the positive input of the error amplier. Finally a capacitor C L is placed at the output as charge storage element, mainly to tackle the sudden changes in the output load current.

Figure 3 .

 3 Figure 3.10 Basic LDO Architecture

  Figure 3.12 Energy balancing from light to heavy step

Figure 3 .

 3 Figure 3.14 LDO negative feedback diagram

Figure 3 .

 3 Figure 3.15 Poles movement with load current

Figure 3 .

 3 Figure 3.16 Parasitic gate capacitance C g (a) and saturation drain-source volatage V sd-sat (b) of the pass transistor for dierent width W

Figure 3 .

 3 Figure 3.17 Class-A bias topology

Figure 3 .

 3 Figure 3.18 Class-AB bias topology

Figure 3 .

 3 Figure 3.21 Gain Voltage (a) and SR (b) simulation for I b = 60 nA for Class-AB error amplier in solid line and class-A dot line. The simulations are performed with C L =350 fF.

Figure 3 .

 3 Figure 3.22 Adaptive biasing system. The rest of the circuit is omitted for simplication purposes

Figure 3 .

 3 Figure 3.23 Block Diagram of two stages amplier with current buer compensation technique

  3.27 3.28) show the trends of K IN and K EX with the g mp and R o-EA .

Figure 3 .

 3 Figure 3.27 K EX for dierent values of R o-EA and g mp . The minimum value of separation factor is for light load condition. R o-EA has negligible impact.

Figure 3 .

 3 Figure 3.28 K IN for dierent values of R o-EA and g mp . The minimum value of separation factor is for light load condition.Also in this case R o-EA has negligible impact.

Figure 3 .

 3 Figure 3.29 The trend of the bias current adaptability versus the load current.

Figure 3 .

 3 Figure 3.30 LDO quiescent current and current eciency versus load current. In this case the trend is shown only for operation mode (I Load = 1 µA-1 mA). For stand-by mode the current eciency is worsen by the minimum drain current needed to keep ON the pass transistor.

Figure 3 .

 3 Figure 3.32 Phase margin versus output capacitor value, for dierent stand-by output current values. From I stand-by L

Figure 3 .

 3 Figure 3.33 Phase margin versus output capacitor value at heavy load condition

Figure 3 .

 3 Figure 3.34 Phase margin versus output current for all operating regions.

Figure 3 .

 3 Figure 3.35 Ueno voltage reference

  Figure 3.36 De Vita voltage reference

Figure 3 .

 3 Figure 3.37 Bandgap Voltage reference proposed in [HUKN10]

Figure 3 .

 3 Figure 3.38 Sub-bandgap voltage reference used in this work

Figure 3 .

 3 Figure 3.39 Output voltage reference versus the temperature

Figure 3 .

 3 Figure 3.41 Monte Carlo simulations on the output voltage reference with 100 runs.

Figure 3 .

 3 Figure 3.42 Line regulation (orange line) of LDO when V IN moves from 0 V to 1.6 V. The simulation is performed at heavy load condition.

Figure 3 .

 3 Figure 3.44 Transient response for a load current step in operation mode. From 1 µA to 1 mA.

Figure 3 .

 3 Figure 3.45 Transient response for a full load current step. From 300 nA to 1 mA.

Figure 3 .

 3 Figure 3.46 Transient response for a load current step in moderate condition. From 300 µA to 1 mA.

Figure 3 .

 3 Figure 3.47 Line transient at heavy load condition

Figure 3 .

 3 Figure 3.49 Monte Carlo simulations on the phase margin with 100 runs.a) for stand-by condition b) for minimum operating load condition

  Figure 4.1 Block diagram of two-step conversion transmitter

Figure 4 . 2

 42 Figure 4.2 Block diagram of direct modulation transmitter.

η

  T X = P rad P DC,P A + P DC,LO + P DC,mod = η P A 1 + η P A P DC,LO P rad + η P A P DC,mod P rad (4.1)

E

  bit,DC = E bit + P DC,stand-by DC × DR (4.3a) E bit = P DC,tot DR (4.3b)

Figure 4 . 5

 45 Figure 4.5 Power VCO transmitter presented in [MBL + 13].

  Figure 4.6 Current starved VCO

Figure 4

 4 Figure 4.7 LC resonator with negative resistor to compensate the losses due to parasitic resistor R P .

Figure 4 . 8

 48 Figure 4.8 Output voltage variation in presence of noisy source. At the left side the noise is injected at the peak voltage, at the right side the noise is injected at zero transition.

Figure 4 . 9

 49 Figure 4.9 Transformation of series LC tank to parallel one.

  (4.15) To understand how the inductor impacts on the power consumption a LC NMOS cross coupled oscillator is introduced in Fig. 4.10. The transistors M 1 and M 2 are the active part

Figure 4 .

 4 Figure 4.10 NMOS cross coupled LC oscillator.

Figure 4 .

 4 Figure 4.11 CMOS LC oscillator

Figure 4 .

 4 Figure 4.12 General representation of power amplier.

Figure 4 .

 4 Figure 4.13 Transistor level schematic of direct modulation transmitters. Single voltage supply for both VCO and PA (a), double voltage supply to optimize the PA eciency (b).

Figure 4 .

 4 Figure 4.14 Bias point to perform class-C operation mode(a) typical voltage and current waveforms at the transistor drain(b) Biasing the transistor at voltage lower than the threshold voltage permits to reduce the voltage and current overlapping period.

Figure 4 .

 4 Figure 4.15 Implementation of L-matching network to transform 50 Ω to the optimum load resistance of 2.5 kΩ. The large value of inductor makes dicult the integration of the passive element.

Figure 4

 4 Figure 4.16 DC RF current and Peak RF current depending on the conduction angle for three dierent output resistances and for a V o,max = 0.4 V. The period of conduction refers only to class-C operating mode for 10 • <α<180 • .

Figure 4 .

 4 Figure 4.18 DC RF load current and peak RF load current for R L = 1.25kΩ and V o,max = 0.282V depending on conduction angle .

Figure 4 .

 4 Figure 4.19 Simulated quality factor Q L and relative parallel resistance for dierent inductance values.

Figure 4 .

 4 Figure 4.20 Varactor quality factor (a) and capacitance versus tuning voltage (b)

Figure 4 .

 4 Figure 4.23 Monte Carlo simulation on the single supply voltage transmitter output power with 100 runs.

Figure 4 .

 4 Figure 4.24 Monte Carlo simulation on the double supply voltage transmitter output power with 100 runs.

Figure 4 .

 4 Figure 4.25 Block diagrams of current reuse transmitter. The two possible solutions are reported depending on the position of the VCO and the PA

Figure 4 .

 4 Figure 4.26 LC current reuse oscillator schematic.The two operating states are also illustrated for the two dierent oscillation periods.

Figure 4 .

 4 Figure 4.27 Modied current reuse VCO for low supply voltage.

Figure 4 .

 4 Figure 4.28 Voltage divider ratio versus the decoupling capacitor C dec

Figure 4 .

 4 Figure 4.29 Phase noise performance measured at 1 MHz oset from the carrier frequency versus the bias resistance.

Figure 4 .

 4 Figure 4.30 Phase noise simulation at 1 MHz oset from the carrier frequency versus the supply voltage.

Figure 4 .

 4 Figure 4.31 FoM and power consumption for dierent supply voltage.

  Fig 4.

  32 it is possible to writeV DD,V CO = V bias -V gs,M n (4.32)

Figure 4 .

 4 Figure 4.32 Supply voltage trend.

Figure 4 .

 4 Figure 4.33 Trend of the voltage at the common node P.

Figure 4 .

 4 Figure 4.34 Transistor level schematic of Current Reuse transmitter.

  Figure 4.35 Voltage and Current transient at the M P A drain.

Figure 4 .

 4 Figure 4.36 Phase noise simulated at 1 Mhz from the carrier frequency.

Figure 4 .

 4 Figure 4.37 MonteCarlo simulation performed over output power.

Table 1

 1

			.1 Comparative energy sources
			Energy Density	Advantages	Drawbacks
	Solar Energy	500 µW/ cm 2	-High energy den-sity	-Large area	occupied
				-Well	developed	-Indoor degradation
				technology.
	Thermal Energy	60 µW/ cm 2	-Always Available -Dicult to control -Low output volt-
						age
	Kinetic Energy	200 µW/ cm 3	-Several tions	applica-	-Low conversion ef-ciency.
				-Light weight
	RF Energy	1 µW/ cm 3	where -Available	every-	-Low energy density
				-Small surface	-Distance depen-
						dent
	1.2	Design techniques for ULP circuits

Table 2 .

 2

	Data-rate	5Mbps	2Mbps	1Mbps	250kbps	250Kbps
	Modulation OOK	HS-	GFSK	-	-
			OQPSK
	Topology	Super Reg. SIF-PDC	Hybrid	-	-
				Loop
	P diss (mW) 0.534	2.4	6	3.3	11.2
	P RX (dBm) -75	-92	-90	-94	-94.5

1 Comparative ULP receiver [VHH + 11a] [LBvdH + 14] [OST + 16] [LBW + 15] [PPA + 15]

Table 3 .

 3

1 Comparative switching regulator

[START_REF] Lefeuvre | Buck-boost converter for sensorless power optimization of piezoelectric energy harvester[END_REF]

Table 3

 3

		.2 Current consumption of designed examples
	Current	1 st	2 nd	3 th	4 th	5 th
		Architecture	Architecture	Architecture	Architecture	Architecture
	I DC (mA)	0.670	0.620	0.774	0.737	0.621

Table 3

 3

	.3 Transistors Size
	Transistor	Aspect Ratio
	M 11 M 12 M 13 M 14

  f t is low. Single-Ended/dierential PA? Most stand-alone PAs, as the one designed in the present work, are realized in a Single-Ended (SE) topology, since antenna is typically SE, and SE RF circuits are much simpler to test than their dierential counterparts. Even if a dierential PA would better use the VCO output, as they sense both the VCO output phases, for sake of simplicity, in the present work the PA was designed single-ended. No balun CHAPTER 4. ULTRA-LOW POWER TRANSMITTER was placed between the VCO/PA interface, in order to avoid extra losses. Matching Network

Table 4 .

 4 2 Devices size for the designed transmitter.

		Value
	L out	7 nH
	C out,s	450 fF
	C out,p	1 pF
	M P A	50 0,13	µm µm

  IEEE International Symposium on Circuits and Systems, pages 28732876, May 2012. [ZM11] C. Zheng and D. Ma. Design of monolithic cmos ldo regulator with d 2 coupling and adaptive transmission control for adaptive wireless powered bio-implants. IEEE Transactions on Circuits and Systems II: Regular Papers, 58(10):23772387, Oct 2011.

Two methods accomplish the closed loop stability: externally and internally compensated. In the rst topology the second order response of the loop is assured with the main pole at the output. In the second one the main pole is located inside the loop.

Drain current equations of transistors M 1 and M 2 is obtained in Appendix

In Fig. 4.3 representative ULP transmitters are classied based on the normalized FOM for respective data-rate. As can be seen most of them adopt a data-rate between 1 and 10 Mbps, proving that in general the information processed in WSN does not require high amount of data. For example the transmitter (dot 9 in the g.4.3) proposed in [START_REF] Kim | 500 mhz ook transmitter with 22 pj/bit, 38.4current combining[END_REF] is designed to have high bandwidth to support high data-rate, where the capsule endoscopy system uses high amount of data to generate high resolution image for accurate diagnosis. At the opposite side, for transmitter (dot 1 in the g.4.3) lower data-rate is chosen for peer-to-peer communication. The architecture is based on multiphase injection locking [START_REF] Pandey | A sub-100 µ w mics/ism band transmitter based on injection-locking and frequency multiplication[END_REF] where the frequency of injected signal is generated at 45 MHz through a stable crystal reference. Then the dierent phase-shifted signals from the injection locking ring oscillator ILRO are merged in a PA/EDGE-combiner EC

The Tab. 4.1 is made performing several simulation for dierent channel widths, at the same output power and at the same conduction angle. The matching network is adapted for each size. The results show that the best MOS current ratio between the DC current and the fundamental current is achieved for the smallest size of 20 µm. From the previously analysis the transistor channel width is 20 µm and it is biased at 290 mV with an signal amplitude of 178 mV. In this case the PA is in moderate Class-C operation, since that the threshold voltage is about 330 mV with a DC current of 267 µA. The higher I DC , about two times higher than the value obtained from the previously analysis, is due mainly to overcome the loss into the MN. Once all the PA characteristics are dened the design of the VCO is mainly focused to guarantee the optimum voltage swing at its output with good performances for current consumption and phase noise. CHAPTER 5. CONCLUSIONS to test the circuits in a more complex system, where the signal modulation incoming from the analog-to-digital convert. As the regulator presents important dependence PVT variations, an additional circuit to adjust the error amplier bias current could represent a solution to mitigate these eects. From the transmission side, to improve the spectrum eciency of the signal radiated a low-power FSK modulation could be easily implemented.

Appendix A Drain current calculation in class AB Error Amplier

The gate source voltage of M 1 and M 2 is equal to

From Eq. A1c and A1d the source voltages V sA1 and V sA2 are equal to

Substituting eq A3a and A3b in A2a and A2b, and then in the A1a and A1b the drain current of transistors M 1 and M 2 is equal

(A.4a)