Acknowledgment

I would like to express my honest appreciation to all the people who ever gave me help and support during my PhD study period. Particularly, I would like to thank my research advisor Prof. Thomas Zimmer for his continual instruction and encouragement. I have greatly benefited from his profound knowledge and charming personality. I would like to thank my co-advisor Dr.

Sebastien Fregonese for his guidance and valuable suggestions and always keeping his door open whenever I need help and advice. It has been always fruitful and joyful to discuss with him. I would also like to warmly thank Prof. Cristell Manuex for her continuous support and help during my Ph.D study period. Also I thank my committee members Prof. Mikael Östling from KTH, Royal Institute of Technology and Dr. Alain Chantre from STMicroelectronics for being on my thesis committee.

I would like to thank my former and present lab members, especially the Compact Modeling team members: Brice Grandchamp, Mario Weisz, Montassar Najari, Jad Bazzi, Gilles Kone, Si-Yu Liao, Arkaprava Bhattacharyya, Sudip Ghosh, Amit Kumar and my former colleague Johnny Goguet. Their help and support during these years was invaluable. It was fun to be part of this research group and share the time in the laboratory.

Finally, I wish to thank my mother, my brothers and sisters for their love, for supporting my decision to pursue my PhD far from them, and for providing invaluable assistance and encouragement. I am forever indebted to my family.

Abstract

The Impact of strain engineering technology applied on NPN-Si-BJT/NPN-SiGe-HBT devices on the electrical properties and frequency response has been investigated. Strain engineering technology can be used as an additional degree of freedom to enhance the carriers transport properties due to band structure changes and mobility enhancement. The mobility of charge carriers in bipolar devices can be enhanced by creating mechanical tensile strain in the direction of electrons flow to improve electron's mobility, and by creating mechanical compressive strain in the direction of holes flow to improve hole's mobility. Consequently, new devices concepts and novel device architectures that are based on strain engineering technology have been explored using TCAD modeling. The physical models and parameters used in TCAD simulations have been calibrated in collaboration with Bundeswehr University-Munich using Monte Carlo simulation. Specific models for SiGe bandgap, bandgap-narrowing, effective mass, energy relaxation, mobility for hydrodynamic and drift-diffusion simulations have been calculated and implemented in the house simulator using tabulated models compiled in C code. Two approaches have been used in this study to generate the proper mechanical strain inside the device. The first approach was through introducing strain engineering technology principle at the device's base region using SiGe extrinsic stress layer. The second approach was through introducing strain engineering technology principle at the device's collector region using strain layers. The study examined not only the transistor DC performance but also the RF performance through multiple optimizations for the explored vertical transistors. Simulation results showed that the strained silicon BJT/HBT devices exhibited better DC performance and high frequency characteristics in comparison with equivalent standard conventional BJT/HBT devices. An approximately 42% improvement in f T and 13% improvement in f MAX have been achieved for BJT device employing strain at the base region. As well, an enhancement of the collector current by nearly three times in strained silicon BJT device has been attained. The obtained results for applying the same technique on NPN-SiGe-HBT device have shown that applying strain on the base region of the HBT device is less efficient in comparison with the BJT device, as the SiGe base is already stressed due to the existence of Ge at the base. Moreover, utilizing a strain layer at the device's collector region will result in an approximately 9%-14% improvement in f T and 7%-12% improvement in f MAX in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BV CE0 value (1% 4%), the f T ×B VCE0 product enhancement is about 12% by means of strain engineering at the collector region.

Résumé

Dans le but d'améliorer les transistors bipolaires TBH SiGe, nous proposons d'étudier l'impact de la contrainte mécanique sur leurs performances. En effet, cette contrainte permet de libérer un degré de liberté supplémentaire pour améliorer les propriétés du transport grâce à un changement de la structure de bande d'énergie du semiconducteur. Ainsi, nous avons proposé de nouvelles architectures de composants basées sur l'ingénierie de la contrainte mécanique dans les semiconducteurs. Deux approches ont été utilisées dans cette étude pour générer la tension mécanique adéquate à l'intérieur du dispositif. La première approche consiste à appliquer une contrainte mécanique sur la base du transistor en utilisant une couche de SiGe extrinsèque. La seconde approche vise à appliquer une contrainte dans la région du collecteur en utilisant une couche contrainte. Les résultats obtenus montrent que cette méthode peut être une approche prometteuse pour améliorer les performances des TBH.

CHAPTER 1 Introduction & Background

Motivation

For the last two decades BiCMOS technology has been the dominant technology for analog RF high speed applications, due to the high linearity, high current drive capability, the lower 1/f noise, high output resistance, and voltage capability of the SiGe HBT. HBT has been a key device in this branch of semiconductor industry. However, due to the continuous demand for devices having higher frequency response, it becomes imperative to develop new bipolar architectures suitable for high frequency and power applications. Various techniques and efforts have been proposed to improve the performance of bipolar devices: introduction of a grading germanium into the base [1], introduction of carbon to improve 1D doping profile [2] and reduction of emitter width [3]. An additional way to improve the device performance is to enhance the carrier transport by changing the material properties. In advanced semiconductor devices strain can be used as an additional degree of freedom to enhance transport properties due to band structure changes [4]. Mobility of charge carriers in a bipolar device can be increased by creating mechanical tensile strain in the device in the direction of electrons flow to improve electron's mobility, and by creating mechanical compressive strain in the device in the direction of holes flow to improve hole's mobility [5].

The main motivation of this thesis is to clarify the impact of strain engineering technology on NPN-SiGe-HBT device's electrical properties and frequency response, through exploring new device concepts and proposing new device's architectures that are based on strain engineering technology, and investigating the feasibility of such concepts in an industrial environment. These new concepts have been studied using finite element simulation TCAD tools.

The work methodology consists of the following steps:

Virtually fabricate the device using process simulations.

Study the sensitivity of the device's different zones to strain.

Propose new methods to incorporate strain in the process and evaluate the strain level that can be obtained inside the device.

Define simulation parameters and physical models (the model parameters have been calibrated in collaboration with Universität der Bundeswehr München).

Perform numerical (device) simulations to analyze the device electrical performance.

Thesis Organization

The thesis is organized as follows: Chapter 2: Strain Technology; gives an overview of the elasticity theory of solids, physics behind strain, different strain types, and application techniques of strain.

Chapter 3: TCAD Simulation & Modeling; provides an overview of the Technology Computer

Aided Design (TCAD), process simulation, device simulation and the physical models used in this study.

Chapter 4; TCAD Simulation Results; gives a detailed discussion of the approaches used to create the desired mechanical strain inside the device, the devices architectures and the obtained results.

Principles of SiGe-HBT

The fundamental advantage of SiGe HBT over conventional Si BJT arises from the bandgap engineering technology principle. Bandgap engineering technology can be used to improve several key figure-of-merits for a bipolar transistor. The first step in understanding how a heterostructure device operates is to consider the energy band diagram. The energy band diagram for a forward biased ideal graded-base SiGe HBT with constant doping in the emitter, the base and the collector regions, and a comparable Si BJT are shown in Fig. 1. The Ge content is linearly graded from 0% near the metallurgical emitter-base (EB) junction to some maximum value of Ge content near the metallurgical collector-base (CB) junction, and then rapidly ramped back down to 0% Ge [6]. The effect of introducing a graded Ge profile into the base region is apparent in the band structure changes shown above, where E g,Ge (x = 0) and E g,Ge (x = W b ) represent the germanium-induced bandgap narrowing at the emitter end of the base (x = 0) and the germaniuminduced bandgap narrowing at the collector end of the base (x = W b ), respectively. As shown in the figure, a slight reduction in the base bandgap at the EB junction and a much larger reduction at the CB junction are observed with respect to the Si BJT device.

To illustrate the heterojunction action in a bipolar transistor, the operation of a conventional Si BJT will be considered first. When V BE is applied to forward bias the EB junction, electrons are injected from the electron-rich emitter into the base across the EB potential barrier. The injected electrons diffuse across the base, and are swept into the electric field of the CB junction, yielding a useful collector current. At the same time, the applied forward bias on the EB junction produces a back-injection of holes from the base into the emitter. If the emitter region is heavily doped with respect to the base, the density of back-injected holes will be small compared to the forward-injected electron density, and hence a finite current gain results.

The introduction of Ge into the base region will affect the dc and ac operations of the Si BJT device. The reduction of the potential barrier to injection of electrons from emitter into the base will yield exponentially more electron injection for the same applied V BE , translating into higher collector current, and hence higher current gain. In addition to that, the presence of a finite Ge content at the CB junction will positively influence the output conductance of the transistor, yielding higher Early voltage. For ac operation, the Ge-gradient-induced drift field across the neutral base will accelerate the injected minority electrons across the base, and thereby decreasing the base transit time. In what follows, the underlying physics of the NPN-SiGe-HBT, with particular emphasis on the fundamental differences between the operations of the SiGe HBT and the Si BJT will be introduced. For analysis purposes, a SiGe HBT and a Si BJT are taken to be of identical geometry, with identical emitter, base and collector-doping profiles, apart from the Ge in the base of the SiGe HBT. The Ge profile is assumed to be linearly graded from the EB to the CB junction as depicted in Fig. 1. This analysis assumes standard low injection conditions, negligible bulk and surface recombination and Boltzmann statistics.

Current Gain

Due to the introduction of Ge into the base region, the potential energy barrier in the conduction band at the EB junction is lowered allowing more electrons to be injected into the base and thereby leads to an increase in the collector current. Furthermore, hole back injection is also reduced by the large valence band discontinuity reducing the base current. Overall, this increase in the collector current dramatically improves the current gain. For a constant base doping profile, the collector current density (J C ) can be derived from the generalized Moll-Ross relation as J = q(e / 1) P (x)dx D (x)n (x) 1.1 where W b is the neutral base width for the applied bias V BE , P b (x) is the base doping, D nb is the minority electron diffusivity in the base and n ib is the intrinsic carrier density.

For SiGe HBT the intrinsic carrier density can be written as ( ) , ( ) /( ) e , ( )/ 1.2

n (x) = n e / e ,
Where E is the heavy-doping induced apparent bandgap narrowing in the base region, where, is the minority electron diffusivity ratio between SiGe and Si, and is given by

= D ( ) 1.5
The first term in Equation 1.4 corresponds to the Si BJT ,and the second term represents the modification of J C due to the introduction of Ge into the base region. As shown in the equation, J C in a SiGe HBT depends exponentially on the EB boundary value of the Ge-induced band offset, and is linearly proportional to the Ge-induced bandgap grading factor. Consequently,

The SiGe HBT exhibits higher collector current and approximately the same base current as the Si BJT. This increase in J C for the SiGe HBT will lead to an increase in current gain. For identically constructed devices, the ratio of the current gain ( ) between a linearly graded germanium profile SiGe HBT and a Si BJT is given by , , = , ( )/

, ( )/ 1 , ( )/

1.6

Equation 1.6 represents a ratio which is larger than unity for a finite Ge content, and indicates that the smaller base bandgap in a SiGe HBT exponentially increases the number of minority carriers injected into the base, causing an increase in the collector current for the same forward-bias, and hence higher current gain value.

Early Voltage

The most important physical effect which causes the collector current to increase with the collector-emitter voltage for a constant base current is the increase of collector current caused by a decreased neutral base width with base-collector reverse bias (V CB ). The output conductance is a measure of collector current variation with V CB . Therefore, low output conductance is desirable to achieve invariant output current in low-frequency analogue applications. The Early voltage (V A ) is a measure of the change in output conductance with changing V CB . For analogue circuit applications, a high value of the product of current gain and Early voltage is desirable, which is conventionally defined as the figure-of-merit for analog circuit design.

An additional benefit of using a graded-Ge profile in a SiGe HBT is the enhancement of the Early voltage. The enhancement of the Early voltage of a graded SiGe HBT can be expressed as

, , | exp , ( ) kT 1 , ( )/
, ( )/ 1.7

This ratio is larger than unity, and it indicates that for a finite grading across the quasineutral base, the exponential dominates the functional dependence on Ge content, yielding an improvement for a SiGe HBT compared to a Si BJT.

Transit Time

As a result of the quasi-electric field due to the grading of the Ge content in the base, the electrons injected from the emitter to the collector will be accelerated; thereby effectively reducing the base transit time. For bipolar transistors, the base transit time for a constant base doping is given by

For Si BJT, the base transit time is given by

, = W 2D 1.10
Hence, the enhancement of the base transit time due to the existence of a graded Ge profile into the base region is given by ratio of the base transit time for SiGe ( , ), and Si BJT ( , ) as

For a finite Ge grading, the ratio ( , , /

) will be less than unity, and therefore the SiGe HBT base transit time will be shorter than Si BJT.

Moreover, the forward bias in EB junction creates a back-injection of holes from the base to the emitter, and gives rise to emitter charge storage delay time ( ). The emitter charging time will be reduced due to the lower barrier which carriers must overcome before being injected into the base due to the existence of the graded Ge profile at the base region.

High Frequency Figures-of-Merit

The SiGe base gives new degrees of freedom for the design of SiGe HBTs and allows much higher values of the figures of merit; the cut-off frequency (f T ) and the maximum oscillation frequency (f MAX ), to be achieved in comparison with the conventional silicon BJTs.

The unity-gain cut-off frequency and the maximum oscillation frequency parameters are positively impacted by the Ge content in the base. As mentioned previously and decrease in SiGe HBT.

The unity-gain cutoff frequency (f T ) is given by the relation

= 1 2 q ( + ) + + + 2 + 1.12
Where I c is the collector current, C EB and C CB are the EB and CB depletion capacitances, W CB is the CB space-charge region width, v sat is the saturation velocity, and r c is the dynamic collector resistance. Therefore, improvements in and due to the presence of SiGe will directly translate into an enhanced f T of the transistor at fixed bias current. The maximum oscillation frequency (f MAX ) figure of merit is defined as

= 8 1.13
Where r B is the base resistance. Therefore, the increase in f T and the reduction in the base resistance aids in improving the f MAX of the SiGe HBT [7] [8].

State-of-the-Art

The design and study of a new semiconductor device structure hold promise at both the device level, where the transistor's electrical behavior may lead to novel effects, and the circuit level, where the device characteristics may be exploited to enhance functional performance. Since the revolutionary invention of the point-contact transistor at Bell Laboratories in 1947, the progress made in the field of semiconductor technology have a constant increase in performance according to Moore' law which states that the number of transistors per chip doubles every 18-24 months. However, as silicon BJTs reach their fundamental limits on speed because of the physical properties of the semiconductor material, advanced high-speed devices require heterojunction technology. The idea of varying the bandgap in a bipolar transistor structure to increase the emitter injection efficiency is almost as old as the bipolar junction transistor itself.

Shockley described the idea in his application for a patent on the junction bipolar transistor The rapid improvement in SiGe HBT performance is mainly due to careful tailoring of Ge and doping profiles, and also due to the continuing downscaling of device dimensions.

Material growth development is also an important factor for the success of SiGe technology and the most recent example is the incorporation of carbon in the SiGe epitaxial layers, which further improves performance. The developments of SiGe HBTs technology are summarized in Table .1 [7].

Historical Event Year

Ref.

First demonstration of transistor action [15] Basic HBT concept [9] First demonstration of a bipolar junction transistor [10] First demonstration of a silicon bipolar transistor [16] Drift-base HBT concept [17] Fundamental HBT theory [18][11] First epitaxial silicon transistors [19] First SiGe HBT [20] First ideal SiGe HBT grown by CVD [21] First SiGe HBT grown by UHV/CVD [22] First high-performance SiGe HBT [23][24] First self-aligned SiGe HBT [25] First SiGe HBT ECL ring oscillator [25] First pnp SiGe HBT [26] First operation of SiGe HBTs at cryogenic temperatures [27] First SiGe HBT BiCMOS technology [28] First LSI SiGe HBT integrated circuit [29] First SiGe HBT with peak f T above 100 GHz [30][31] First SiGe HBT technology in 200-mm manufacturing [32] First SiGe HBT technology optimized for 77K [33] First radiation tolerance investigation of SiGe HBTs [34] First report of low-frequency noise in SiGe HBTs [35] First SiGe:C HBT [36] First high-power SiGe HBTs [37][38] First sub-10psec SiGe HBT ECL circuits [START_REF] Washio | A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-Gate Delay[END_REF] First high-performance SiGe:C HBT technology [START_REF] Osten | Carbon doped SiGe heterojunction bipolar transistors for high frequency applications[END_REF] First SiGe HBT with peak f T above 200 GHz [START_REF] Jeng | A 210-GHz f T SiGe HBT with nonself-aligned structure[END_REF] First SiGe HBT with peak f T above 300 GHz [START_REF] Rieh | SiGe HBTs with cut-off frequency of 350 GHz[END_REF] First complementary (npn+pnp) SiGe HBT technology [START_REF] El-Kareh | A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits[END_REF] First C-SiGe technology with npn and pnp f T above 100 GHz [START_REF] Heinemann | A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs[END_REF] First vertical SiGe HBT on thin film (CMOS compatible) SOI [START_REF] Cai | Vertical SiGe-base bipolar transistors on CMOScompatible SOI substrate[END_REF] First SiGe HBT with both f T and f MAX above 300 GHz [START_REF] Rieh | SiGe HBTs for millimeterwave applications with simultaneously optimized f T and f MAX[END_REF] First Conventional Double-Polysilicon FSA-SEG Si/SiGe:C HBT with f MAX 423 GHz and f T 273 GHz [14] First Fully Self-Aligned SiGe:C HBT Architecture with f MAX 400 GHz [13] First SiGe HBT with f MAX 500 GHz (IHP: to be published in IEDM 2010)

Table 1: Milestones in the development of SiGe HBTs [7].

Strained SiGe HBT

Due to the continuous demand for devices having higher frequency response, it becomes imperative to develop new bipolar architectures suitable for high frequency and power applications. Therefore, various efforts and approaches have been proposed to improve the bipolar devices performance. In advanced semiconductor devices technology, strain engineering technology is considered as an additional degree of freedom to enhance transport properties due to band structure changes. Recent experimental and theoretical work point out uniaxially and biaxially stressed Si and SiGe substrates as a possible technique for the new generation HBT devices. Experimentally, two major methods have been used; wafer bending [START_REF] Wang | Effects of Mechanical Uniaxial Stress on SiGe HBT Characteristics[END_REF], and virtual substrates [START_REF] Persson | Fabrication and characterization of strained Si heterojunction bipolar transistors on virtual substrates[END_REF]. Wafer bending allows inducing uniaxial stress while virtual substrates create biaxial stress. Both methods induce a uniform stress over the device. In what follows, a brief description of the latest work done on strained SiGe HBTs using wafer bending and virtual substrate approaches is presented. Persson et al. [START_REF] Persson | Fabrication and characterization of strained Si heterojunction bipolar transistors on virtual substrates[END_REF] reported in their work (Fabrication and characterization of strained Si heterojunction bipolar transistors on virtual substrates), a strained Si HBT with a maximum current gain of 3700 using a relaxed Si 0.85 Ge 0.15 virtual substrate, Si 0.7 Ge 0.3 base and strained Si emitter. The schematic of the complete structure used in their study is shown in Fig. 5. Their he Si BJT/SiGe HBTs showed a consistent decrease in collector current and hence current gain after strain as illustrated in Fig. 8 and Fig. 9. This decrease in the collector current is attributed to the compressive strain in the orthogonal plane which degrades the electron transport [START_REF] Haugerud | The effects of mechanical planar biaxial strain in Si/SiGe HBT BiCMOS technology[END_REF].

Fig. 8: Forward Gummel characteristics of a first generation SiGe HBT for both pre-strain and post 0.123% biaxial strain. To the best of our knowledge, there haven't been any simulation or measurement results available in the literature to evaluate the effect of the stress layers in the above structures, thus we have analyzed the impact of strain engineering on SiGe-HBTs via modified ideas from the above patents using a specific structure provided by IMEC Microelectronic-Belgium as a reference device [START_REF] Decoutere | IMEC Microelectronics private communication[END_REF]. substrates as shown in Fig. 12. Using an approximate theoretical model, they found that the presence of a strained-Si/SiGe (relaxed) heterojunction barrier in the emitter can substantially improve the HBT's current gain as shown in Fig. 13. Furthermore, two-dimensional numerical simulations of a virtual substrate HBT with a realistic geometry demonstrate that, besides the current gain enhancement, a three times improvement in f T and f MAX were realized when a strained-Si/SiGe emitter is incorporated as shown in Fig. 14 and Fig. 15.

Moreover, Jankovic et al. presented a computational study by commercial TCAD of the potential electrical and thermal properties of n-p-n HBTs fabricated on relaxed Si 1-y Ge y virtual substrates. The dependences of dc, ac and self-heating characteristics of virtual substrate HBTs (VS HBTs) on alloy composition were investigated in details. It is found that symmetrical VS HBTs generally exhibit higher current drive capabilities compared with equivalent HBTs formed pseudomorphically on Si substrates, but at the expense of a lower f T and a decreased f MAX . In addition, simulated results show that self-heating effects become increasingly significant for VS HBTs, substantially degrading device electrical parameters such as the early voltage [54] [55]. The key element to achieve this, is that the emitter, base and collector regions are self-aligned to each other. This is accomplished by growing the collector/base and capping layer non-selectively, then etching the extrinsic device region away using a sacrificial emitter, and then using the sacrificial emitter to self-align a reconstructed external base to the emitter region. Initial results with this approach yielded marginal devices with poor performance. But the concept to fabricate such a device was demonstrated, and as the reasons for the poor performance and process marginalities were identified, IMEC continued to optimize this architecture in the frame of the DOTFIVE project. A schematic cross-section of the novel FSA IMEC device architecture is shown in Fig. 16. (L E ~5 µm).

However, IHP Microelectronics reached a SiGe HBT device with f T /f MAX of 300 GHz/500 GHz, their results will be published in IEDM 2010 proceedings. The speed-improvement compared to previous SiGe HBT technologies originates from the reduced specific collector-base capacitance and base resistance and scaling of the device dimensions.

DOTFIVE Project

THz technology is an emerging field which has demonstrated a wide-ranging potential.

Extensive research in the last years has identified many attractive application areas and has paved the technological path towards broadly usable THz systems. THz technology is currently in a pivotal phase and will soon be in a position to radically expand our analytic capabilities via its intrinsic benefits. In this context, DOTFIVE is planned to establish the basis for fully integrated cost efficient electronic THz solutions. An illustration of some exemplary applications of Terahertz radiation is shown in Fig. 24.

CHAPTER 2 Strain Technology

With the continuing reduction of silicon integrated circuits, new engineering solutions and innovative techniques are required to improve bipolar transistors performance, and to overcome the physical limitations of the device scaling. Therefore, strained-silicon technology has become a strong competitor in search for alternatives to transistor scaling and new materials for improved devices and circuits performances. Strained-Si technology enables improvements in electronic devices performance and functionality via replacement of the bulk crystalline-Si substrate with a strained-Si substrate. The improved performance comes from the properties of strained-Si itself through changing the nature of the wafer by stretching and/or compressing the placement of the atoms. This chapter gives an overview of the elasticity theory of solids, physics behind strain, different strain types and strain application techniques.

Theory of Elasticity

Elasticity is the ability of a solid body to recover its shape when the deforming forces are removed. The deformation of an elastic material obeys Hooke's law, which states that deformation is proportional to the applied stress up to a certain point. This point is called the elastic limit. Beyond this point additional stresses will cause permanent deformation [1]. The main law governing elasticity of materials is the theory of stress, strain, and their interdependence will be discussed.

The Stress Tensor

Stress is defined as the force per unit area. When a deforming force is applied to a body, the stress is defined as the ratio of the force to the area over which it is applied. There are two basic types of stress; if the force is perpendicular (normal) to the surface over which it is acting, then the stress is termed as normal stress, and if it is tangential to the surface, it is called a shear stress. Usually, the force is neither entirely normal nor tangential, but it is at some arbitrary intermediate angle. In this case it can be resolved into components which are both normal and tangential to the surface; so the stress is composed of both normal and shearing components. The sign convention is that tensional stresses are positive and compression stresses are negative.

Let's take an arbitrary solid body oriented in a Cartesian coordinate system, with a number of forces acting on it in different directions, such that the net force (the vector sum of the forces) on the body is zero. Conceptually, we slice the body on a plane normal to the Xdirection (parallel to the YZ-plane) as shown in Fig. 26. A small area on this plane can be defined as

= 2.1
The total force acting on this small area is given by

= + + 2.2
We can define three scalar quantities:

X y Z F 1 F 2 F 3 F = lim = lim = lim 2.3
The first subscript refers to the plane and the second refers to the force direction. Similarly considering slices orthogonal to the Y and Z -directions, we obtain

= lim F A = lim F A = lim F A 2.4 = lim F A = lim F A = lim F A 2.5
For static equilibrium, the shear stress components across the diagonal are identical ( = , = , and = ), resulting in six independent scalar quantities. These scalar quantities can be arranged in a matrix form to yield the stress tensor [2]:

= = 2.6

The Strain Tensor

Strain is defined as the change of the object length in a given direction divided by the object initial length in that direction. If a force is applied to a solid object, that may simultaneously translating, rotating, and deforming the object [3]. If we consider the two arbitrary neighboring points P and Q are marked at initial position x and + d respectively. After deformation these points move to position + u( ), and + d + u( + d ) respectively. The absolute squared distance between the deformed points can be written as

= [ + ( + ) ( )] 2.7
For small displacements , a Taylor expansion about the point x gives the absolute squared distance as

= + = + 2 + , , 2.8 ,
The squared distance between the original points can be written as = 2.9

The change in the squared distance can be written as

= 2 + , , , = + + , = + + , = 2 2.10
, Where are the strain tensor components, and are defined as

= 1 2 + + 2.11
For 1, the second term in equation (2.11) can be neglected, and the resultant tensor is

= 1 2 + 2.12
Therefore, the strain tensor is analogous to the stress tensor and can be written as

= 2.13
The diagonal terms are the normal strains in the directions X, Y, and Z respectively. While the off-diagonal terms are equal to one half of the engineering shear strain.

The strain components in three dimensions can be written as

= , = = 1 2 + = , = = 1 2 + = , = = 1 2 + 2.14
Where u, v and w are the displacements in the X, Y and Z directions, respectively [4].

Stress-Strain Relationship

Stress and strain are linked in elastic media by a stress-strain or constitutive relationship.

This relation between stress and strain was first identified by Robert Hook. For Hookean elastic solid, the stress tensor is linearly proportional to the strain tensor over a specific range of deformation. The most general linear relationship between the stress and strain tensors can be written as

= 2.15
Where is a fourth-order elastic stiffness tensor with 81 (3 ) elements.

However, due to the symmetries involved for the stress and strain tensors under equilibrium, is reduced to a tensor of 36 elements. To simplify the notations, the stress and strain tensors can be written as vectors using the contracted notations. First the off-diagonal strain terms are converted to engineering shear strains (The off-diagonal terms are equal to one-half of the engineering shear strain).

2 2 2 2 2 2 = 2.16
Where is the engineering shear strain.

The resulting matrix is no longer a tensor because it doesn't follow the coordinate-transformation rules. Then the elements are renumbered as the following

= = 2.17
The relationship between the stress vector and the strain vector can be written as

= 2.

18

The material property matrix with all of the elastic tensor constants (C's) is known as the stiffness matrix. The inverse of the stiffness matrix is called compliance matrix, S, where = [5]- [6].

The compliance matrix is written as

= 2.19
for linear elastic isotropic materials where the physical properties are independent of direction.

Therefore, Hooke's law takes on a simple form involving only two independent variables [7]. In stiffness form, Hooke's law for the isotropic medium is

= (1 + )(1 2 ) 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 2 2.20
where E is the Young's modulus. v is the Poisson's ratio, which is defined as the ratio of transverse to longitudinal strains of a loaded specimen.

For anisotropic materials such as cubic crystals (i.e. Si, and Ge crystals), in which their elastic properties are direction dependent. It is possible to simplify Hook's law by considerations of cubic symmetry. If the X, Y, and Z axes coincide with the [100], [010], and [001] directions in the cubic crystal, respectively, then Hooke's law in stiffness form can be written as = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2.21

For cubic crystals, the compliance-stiffness constants relationships are given by

= + ( )( + 2 ) 2.22 = ( )( + 2 ) 2.23 = 1 2.24 = + ( )( + 2 ) 2.25 = ( )( + 2 ) 2.26 = 1 2.27
The stiffness and compliance coefficients for Si and Ge are listed in Table 3.

C

Young's Modulus

Young's Modulus, E, is defined as the ratio of elastic stress to strain. It is a measure of the material's resistance to elastic deformation. The value of Young's modulus, E, depends on the direction of the applied force (anisotropic). For an arbitrary crystallographic direction, E can be written as:

= S 2 S S 1 2 S ( + + ) 2.28
where S are the elastic compliance constants. , , and are the direction cosines of the applied force with respect to the crystallographic axis [8].

The following are the measured values for the modulus E in silicon at room temperature for different directions of the applied force [9]- [10].

[ ] = 1 = 131 GPa 2.29 [ ] = 4 (2 + 2 + ) = 169 GPa 2.30 [ ] = 3 ( + 2 + ) = 187 GPa 2.31
Where, E [100] , E [110] , and E [111] are the Young's modulus that corresponds to the applied forces along the directions [100], [110] and [111], respectively.

Miller Indices (hkl)

The orientations and properties of the surface crystal planes are important. Since semiconductor devices are built on or near the semiconductor surface. A convenient method of defining the various planes in a crystal is to use Miller indices [11]. Miller indices are a symbolic vector representation in crystallography for the orientation of an atomic plane in a crystal lattice and are defined as the reciprocals of the fractional intercepts which the plane makes with the crystallographic axes, and denoted as h, k and l. The direction [hkl] defines a vector direction normal to surface of a particular plane or facet. Fig. 27 shows the Miller indices of three important planes in a cubic crystal [12].

Coordinate Transformation

It is often useful to know the stress tensor in the crystallographic coordinate system for a stress applied along a general direction with respect to the crystallographic coordinate system [13]. A stress applied in a generalized direction [ , , ] can be transformed to stress in the crystallographic coordinate system [ , , ] using the following transformation matrix, U

= 0 2.32
Where is the polar angle, and is the azimuthal angle of the applied stress direction relative to the crystallographic coordinate system as shown in Fig. 28.

The stress in the crystallographic coordinate system is given by = . .

2.33

Where is the stress applied in a generalized coordinate system.

Piezoresistivity

Piezoresistance is defined as the change in electrical resistance of a solid when subjected to stress. The piezoresistance coefficients ( ) that relate the piezoresistivity and stress are defined by

= / 2.34
Where R is the original resistance that is related to semiconductor sample dimension by = where is the resistivity l, w, and h are the length, the width, and the height of the sample respectively. is the applied mechanical stress.

The ratio x y z

'[x',y',z'] = + 2.35
The first three terms of equation ( 2 The resistivity change, , is connected to stress by a fourth-rank tensor , and is given by

= ,

2.36

In the vector form we can rewrite as , where i=1,2,…,6. Therefore, equation (2.36) can be written as

= 2.37
Where is a 6×6 matrix.

For a cubic crystals such as Si, has only three independent elements due to the cubic symmetry.

= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2.38

Where describes the piezoresistive effect for stress along the principal crystal axis (longitudinal piezoresistive effect). describes the piezoresistive effect for stress directed perpendicular to the principal crystal axis (transverse piezoresistive effect). describes the piezoresistive effect on an out-of-plane electric field by the change of the in-plane current induced by in-plane shear stress [14] [15].

Element of Bulk Si and Ge

Si and Ge are elements of group IV with four electrons in the outermost shell, and they

Energy Band Structure

Band structure is one of the most important concepts in solid state physics, it describes the variation of energy, E, with the wave vector, k. The band of filled or bonding states is called the Wave Vector K Wave Vector K

Calculation of Energy Bands

A wide range of techniques have been employed to calculate the energy band dispersion curves of semiconductor materials. The most frequently used methods are the orthogonalized plane-wave method (OPW), the pseudopotential method and the k.p method.

From quantum mechanics, Schrödinger equation can be solved by expanding the eigenfunction in terms of a complete basis function and developing a matrix eigenvalue equation.

A plane wave basis can be used to do so, but it has a difficulty because many plane waves are needed to describe the problem adequately. The OPW method has been proposed by Herring in 1940 [18]. It is an approach to avoid having to deal with a very large number of plane wave states. The basic idea is that the valence and conduction band states are orthogonal to the core states of the crystal, and this fact should be utilized in the selection of the plane wave, resulting in a reduced number of plane wave states used in solving the problem.

The pseudopotential method and the k.p method for calculating the band structure will be discussed in details in the following sections.

The Pseudopotential Method

The pseudopotential method is a technique to solve for band structures of semiconductors.

This method makes use of the information that the valence and conduction band states are orthogonal to the core states. In addition to that, this method uses empirical parameters known as pseudopotentials to solve the Schrödinger equation in the one-electron approximation [19]:

2 + ( ) ( ) = ( ) 2.39
Assuming that the electrons wave functions of the core states and their energies are given by and respectively. We then have

= [ + ( )] = | 2.40 Where = 2 2.41
The orthogonality condition is given by

= 0 2.42
this equation is called the orthogonalized plane wave.

The orthogonality condition is satisfied when we choose the wave function given by

, = , | 2.43
by substituting this equation into equation (2.39) we have

| | = | | 2.44
Then, the following relation is obtained

| + [ ]| = | 2.45
Equation (2.44) can be written as follows

[ + ( )]| = E | 2.46
Or

[ + ( ) + ( )]| = | 2.47
Where

( ) = [ ]| 2.48
There exists an inequality relation between the energies of the core states and the energies of the valence and conduction bands , which is given by > 2.49

Thus, > 0 2.50
Therefore equation (2.45) can be written as

[ + ( )]| = | 2.51 ( ) = ( ) + ( ) 2.52
Where ( ) is called the pseudopotential, which is periodic and can be expanded by Fourier series as follows (r) = e .

2.53

where are the Fourier coefficients, and they are given by = 1 ( ) .

2.54

maybe chosen so that the potential is expressed with a small number of the Fourier coefficients , and therefore, the small values of can be neglected.

By using the empirical pseudopotential method, the Fourier coefficients of ( ) are empirically chosen so that the shape of the critical points and their energies are in good agreement with experimental observation. The energy band calculations based on the empirical pseudopotential method takes into account as few pseudopotentials ( ) as possible, and use the Bloch functions of the free-electron bands for the wave functions | .

The energy bands are obtained by solving the equation:

2 + ( ) | ( ) = | ( ) 2

2.57

To obtain the eigenvalues and eigenfunctions of the above equation, we define the following

= + ( ) 2.58
Equation 2.54 becomes:

| + = | + 2.

59

Where

| + = e .

2.60

Then the solutions are obtained by solving the determinate

| + + , = 0 2.61

The k.p Method

The k.p method starts with the known form of the band structure problem at the edges, and using the perturbation theory to study wave functions according to the crystal symmetry, so that band structures away from the highly symmetry points in k space can be obtained.

Additionally, using this method one can obtain analytic expressions for band dispersion and effective masses around high-symmetry points [20] [21].

Assuming that the eigenvalues and Bloch functions are known for a semiconductor with a band edge at k 0 (k 0 is at position -point = [000] in the Brillouin zone). The Schrödinger equation for a one-electron system is given by

2 + ( ) , = , 2.62
Where ( ) is the potential energy with the lattice periodicity, , is the wave function, and is the total energy. The solution of equation (2.62) is given by the Bloch function , = , e .

2.63

Where k , r is a function of the lattice periodicity for band index n.

Substituting the Bloch function into equation (2.62), and using the following relations [22] , = , + e The k.p description of the non degenerate bands (i.e., conduction bandedge or the split-off band in the valence band for the case of large spin-orbit coupling) can be done using the perturbation theory to obtain the energy wave functions away from k 0 .

For k 0 =0, the Schrödinger equation for the perturbation Hamiltonian is given by

( + H + H ) = 2.
70

Where = P 2m + V( ) 2.71 = . 2.72 = k 2 2.73
And is the central part of the Bloch functions .

In the perturbation approach H 0 is a zero order term in , H 1 is a first order term in , and H 2 is a second order term in .

To zero order, we have

= 2.74 = (0) 2.75
To first order perturbation we have

= + . 0| | 0 (0) (0) 2.76 = (0) + . 0| | 0 2.77
For crystals with inversion symmetry such as Si and Ge, the states | 0 or will have inversion symmetry, therefore, the first order matrix elements vanish because P has an odd parity.

For the second order, the energy is given by

= (0) + k 2 + | n 0| | 0 | (0) (0) 2.78
Equation 2.78 can be expressed in terms of the effective mass as follows

= (0) + , , . 2.79
Where

, = + 2 0| | 0 0 0 (0) (0) 2.80
This equation is valid for conduction bandedge and the split-off bands. For the valence band, keeping only the valence bandedge bands in the summation, then the energy eigenvalue can be expressed as

= (0) + 2 2.81 With 1 = 1 + 2 1 3 2 + 1 + 2.82
Where is the energy gap at the zone center, and is the HH-SO (Split-Orbit) band separation.

For the Split-off band the energy eigenvalue is given by = 2 2.83

Where

1 = 1 + 2 3 ( + ) 2.84
The HH valence band structure is that of a free-electron, therefore, the effective mass is the same as free-electron mass, and is given by

= 2 2.85
and the light-hole band structure is given by = 2 2.86

Where

1 = 1 + 4 3
2.87

Impact of Strain

Crystal Symmetry

Due to the communication between symmetry operations and the crystal Hamiltonian, crystal symmetry determines the symmetry of the band structure. Therefore, straining the silicon lattice will reduce the crystal symmetry and change the inter-atomic spacing. The breaking of the crystal symmetry also causes band warping from symmetry restrictions. When the band structure of a material is changed, many material properties are altered including band gap, effective mass, carrier scattering, and mobility. Associated modifications in the electronic band structure and density of states contribute to changes in carrier mobility through modulated effective transport masses [23].

Band Structure and Band Alignment

The impact of biaxial strain on the band structure of a semiconductor can be discussed in two parts; hydrostatic strain (due to the fractional volume change), and uniaxial strain. Regarding the valence band, the biaxial tensile strain splits the top of the valence band, with the heavy hole (HH) moving down in energy and the light hole (LH) being raised in energy.

In contrast, biaxial compressive strain splits the top of the valence band, with the light hole (LH) The k.p method incorporated with Bir-Pikus strain Hamiltonian is used to calculate strain effect on band structures by introducing an additional perturbation term into the unstrained potential [24]. Therefore, the total Hamiltonian is given by

Compressive strained Tensile strained Unstrained

= . + 2.88

Mobility Enhancement

To understand the effect of strain on mobility, the simple qualitative Drude model of electrical conduction which explains the transport properties of electrons in materials dictates that =

2.96

Where is the carrier mobility, is the scattering time, and is the conductivity effective mass.

Therefore, the mobility improvement in strained silicon takes place mainly due to the reduction of the carrier conductivity effective mass, and the reduction in the intervalley phonon scattering rates.

The conduction band of unstrained bulk silicon has six equivalent valleys along the <100> direction of the Brilloun zone, and the constant energy surface is ellipsoidal with the transverse effective mass, m t = 0.19m 0 , and the longitudinal effective mass, m l = 0.916m 0 , where m 0 is the free electron mass [26]. If biaxial tensile strain is applied, the degeneracy between the four in-plane valleys ( 4 ) and the two out-of-plane valleys ( 2) is broken as shown in Fig. 31. As a consequence, the electrons prefer to populate the lower valleys, which are energetically favored.

This results in an increased electron's mobility via a reduced in-plane and increased out-of-plane electron conductivity mass. In addition to that, electron scattering is also reduced due to the conduction valleys splitting into two sets of energy levels, which lowers the rate of intervalley phonon scattering. Therefore, if the optimum strain is applied, both reductions in scattering rate and in effective mass will contribute to the electron mobility enhancement. The stress-induced electron mobility enhancement is given by

= 1 + 1 1 + 2 ( , ) ( ) 1 2.97
Where is electron mobility without the strain, and are the electron longitudinal and transverse masses in the subvalley, respectively, and , are the change in the energy of the unstrained and the strained carrier sub-valleys, is the quasi-Fermi level of electrons. The index i corresponds to a direction (for example, is the electron mobility in the direction of the x-axis of the crystal system and, therefore, , should correspond to the two-fold subvalley along the x-axis) [27].

For holes, the valence band structure of silicon is more complex than the conduction band.

For unstrained silicon at room temperature, holes occupy the top two bands: the heavy and light hole bands. Applying strain, the hole effective mass becomes highly anisotropic due to band warping, and the energy levels become mixtures of the pure heavy, light, and split-off bands.

Thus, the light and heavy hole bands lose their meaning, and holes increasingly occupy the top band at higher strain due to the energy splitting. To achieve high hole's mobility, a low in-plane conductivity mass for the top band is required, in addition to that, a high density of states in the top band and a sufficient band splitting to populate the top band are also required [25].

Strain Application Techniques

In the previous section it has been shown that the introduction of a compressive and/or tensile strain in the Si substrate can improve the mobility of both carrier types. Therefore, this provides a very important way to modify and enhance the electrical properties of Si through proper design, implementation, and control of strain in the active layers. Consequently, various methods and approaches have been proposed to induce the desired strain in electronic devices, such as "Global strain" through SiGe epitaxial processes [28] [29], "Local strain" using specially engineered high tensile films [29] and "Mechanical strain" by mechanically bending the wafer post fabrication [30] [31]. The different strain generation methods will be discussed in details.

Global Strain Approach

Global strain on wafer level is mostly induced by the epitaxial growth of Si 1-x Ge x and Si layers. Because the lattice parameter of Si 1-x Ge x (0 x 1) alloys varies between 0.5431 A 0 for Si (x=0) and 0.5657 A 0 for Ge (x=1), tensile strain is induced in a silicon layer epitaxially grown on top of the SiGe layer. And compressive strain is induced in the SiGe layer epitaxially grown on top of a Si layer as shown in Fig. 33. In this technology the degree of strain is controlled by changing the content of Ge in the Si 1 x Ge x layer, or by changing the thickness of the strained Si layer. In both cases the strain is in the plane of the layer ( = = || ), but this strain also produces a perpendicular strain, resulting in a tetragonal distortion of the lattice.

The strains are connected through the isotropic elasticity theory as

= 2 1 || 2.98
Where v is the Poisson's ratio.

The tetragonal distortion produced by the perpendicular strain results in a parallel lattice constant, and is given by

|| = 1 + 1 + 2.99
Where a is the Si lattice constant, f is the misfit between the two layers, h is the Si layer Under appropriate growth conditions, good quality layers of crystalline Si 1-x Ge x alloys on Si substrates can be grown. If the SiGe thickness remains below a critical thickness (h C ), which depends on the alloy composition and the growth temperature, a pseudomorphic Si 1-x Ge x film can be grown without the introduction of extended defects. If the Si 1-x Ge x thickness exceeds the critical thickness, or the substrate is exposed to sufficiently high temperatures for long period of time, at which the pseudomorphically grown layer is no longer thermodynamically stable, the lattice constant relaxes to its original value. This means that the strain in the Si 1-x Ge x layer will be relaxed and misfit dislocations will generate at the Si/ Si 1-x Ge x interface. Thus, the Si 1-x Ge x /Si strained heterostructures are limited in thickness and stability.

Various models have been developed to predict the critical thickness for which the epitaxial strain layer can be grown. Van der Merwe produced a thermodynamic equilibrium model by minimizing the total energy of a system with the generation of a periodic array of dislocations. In his model the critical thickness is when the strain energy equals the interface energy, and is given by

19 16 1 + 1 2.102
Where b is the magnitude of the Burger's vector. For a bulk Si substrate b=0.4 nm, and in general = / 2, where a is the lattice constant of the relaxed substrate.

Matthews and Blackeslee have proposed in their model that the critical thickness is when the misfit stress on an existing threading dislocation equals the line tension of the dislocation, or equivalently, when a dislocation half-loop is stable against the misfit stress. The critical thickness according to Matthews and Blackeslee model is given by

= 1 8 1 || 1 (1 + ) 4 2.103
Where is the angle between the dislocation line and the Burgers vector, is the angle between the Burgers vector and the direction in the interface normal to the dislocation line, v is the Poisson's ratio, and || is the in-plane strain.

However, it was verified that Van der Merwe model and Matthews and Blackeslee model calculations were not consistent with the experimental data of the critical thickness, and if epitaxy conditions are carefully controlled, then a Si 1-x Ge x layer with thickness above (h C ) could be grown. The simplicity of these models, as well, not taking in consideration the nucleation, propagation, and interaction of dislocations in their calculation were the reasons for the models failure. Afterwards, more accurate results were proposed by People and Bean. In their model they tried to explain the metastable critical thickness (h c,MS ) through a nonequilibrium approach.

According to their model, the metastable critical thickness is defined as the film thickness at which its strain energy density becomes greater than the self-energy of an isolated screw dislocation, and is given by

, = 16 2 1
|| 1 1 + , 2.104
In Fig. 34 the equilibrium (stable) and metastable values of critical thicknesses are plotted versus the Ge content, x, of a Si 1-x Ge x epitaxial layer grown on a Si substrate. As shown in the figure, increasing the Ge content will increase the strain in the SiGe layer, and thus the critical thickness decreases.

Even though the global strain approach described above has the advantage that it is waferlevel and the transistor fabrication process requires little or no change, it suffers from several process integration issues. The presence of Ge modifies dopants diffusion and changes thermal conductivity of the substrate. The relaxation of SiGe via misfit dislocation formation and thermal processing during the fabrication steps causes degradation of the device performance. Moreover, the growth of a thick SiGe strain-relaxed buffer can be costly [32].

Fig. 34 : The equilibrium and metastable critical thickness versus Ge content for pseudomorphic Si 1 x Gex layers grown on bulk silicon substrate.

Local Strain Approach

A second technique for introducing strain in semiconductor devices is the use of a tensile and/or compressive strain layer. In this approach, either uniaxial or biaxial strain is created through the device fabrication process using strain layers such as silicon dioxide (SiO 2 ), and silicon nitride (Si 3 N 4 ). In this technique, strain develops primarily during the deposition process and consists of two components: the intrinsic strain and the extrinsic strain. The intrinsic strain is the component of strain in the layer caused by the deposition process itself. Processing conditions such as temperature, thickness, pressure, deposition power, reactant and impurity concentrations, are important factors in determining the magnitude and strain type (i.e. compressive or tensile).

The extrinsic strain is the component of strain caused by a change in the external conditions on the wafer. The thermal expansion coefficient of materials like SiO 2 , and Si 3 N 4 layers are different from the silicon substrate thermal coefficient. Therefore, when the temperature changes, the layer and substrate try to expand or contract by different amounts.

Because the substrate and the stress layer are bound together, a stress will develop in both the layer and the substrate. Since layers are typically deposited above room temperature, the process of cooling after deposition will introduce a thermal component of strain. So, after deposition, the film tends to back to its initial state by shrinking if it was stretched earlier, thus creating compressive intrinsic stress, and similarly tensile intrinsic stress if it was compressed during deposition.

The thermal expansion coefficient, , is defined as the rate of change of strain with temperature, and is given by

= 2.105
Therefore, the thermal strain, , induced by a variation in temperature is given by

= T 2.106
The The local strain approach through using tensile and/or compressive strain nitride layer has been used to optimize NMOSFET and PMOSFET devices on the same wafer independently by applying different levels of strain as shown in Fig. 35 [35]. More than 2 GPa of tensile stress and more than 2.5 GPa of compressive stress have been developed through controlling the growth conditions of Si 3 N 4 layers [36]. As well, IBM, AMD and Fujitsu [37] [38] have reported a CMOS architecture in which longitudinal uniaxial tensile and compressive stress in the Si channel have been created. In this approach, the process flow consist of a uniform deposition of a highly tensile Si 3 N 4 liner post silicidation over the entire wafer, followed by patterning and etching the film over the p-channel transistors. Next, a highly compressive Si 3 N 4 layer is deposited, and this film is patterned and etched from n-channel regions. The advantages of this technique over the epitaxial SiGe technique, that the Dual Stress Liner (DSL) approach reduces the process complexity and integration issues. In addition, it simultaneously improves both n-and p-channel transistors. The local strain approach through using SiO 2 and Si 3 N 4 strain layers in the collector region will be presented in chapter 4.

Mechanical Strain Approach

The third technique of introducing strain into the transistors is through external mechanical stress post fabrication. In this approach, the strain is engendered into the Si either through direct mechanical bending of the Si wafer, or by bending a packaged substrate with a Si chip glued firmly onto its surface. One method used to apply external mechanical strain on the Si wafer is shown in Fig. 36 [30]- [31]. This technique is an extremely low-cost technique, and it allows the reversible application of either compressive or tensile strain. However, this technique is interesting for experimental study but cannot be used for practical applications.

Conclusion

Strained-Si technology enables improvements in electronic devices performance and functionality via replacement of the bulk crystalline-Si substrate with a strained-Si substrate.

Mechanical strain reduces the crystal symmetry and changes the inter-atomic spacing. In addition to that, mechanical strain causes band warping from symmetry restrictions, and induces a change in the band structure. When the band structure of a material is changed, many material properties are altered including band gap, effective mass, carrier scattering, and mobility. Strain can be generated as "global strain" on the wafer level by the growth of SiGe and Si layers, or as "local strain" on the transistor through the device fabrication process by using strain layers or as "mechanical strain" by mechanically bending the wafer post fabrication. Therefore, a profound knowledge and deep understanding of strain physics and strain application techniques are required to achieve the maximum benefit of applying strain technology on standard bipolar devices. This provides a useful way of studying the effects of process parameters on the device performance and both the device structure and the fabrication process can thus be optimized.

CHAPTER 3 TCAD Simulation & Modeling

However, TCAD process and device simulation tools play a critical role in advanced technology development by giving insight into the relationships between processing choices and nanoscale device performance that cannot be obtained from measurements tools alone. The TCAD process and device simulation tools support a broad range of applications such as CMOS, power, memory, image sensors, solar cells, bipolar, and analog/RF devices. A complete TCAD simulation involves the following steps:

• Virtual fabrication of the device using a process simulator or a device editor.

• Creation of a mesh suitable for device simulation.

• Device simulation that solves the equations describing the device behavior.

• Post processing i.e, generation of figures and plots.

The conventional role of TCAD simulation and modeling in integrated circuit devices processing is illustrated in Fig. 37 [1] [2]. In what follows, process simulation and device simulation will be discussed in more details.

Fig. 37: The conventional role of TCAD simulation and modeling in integrated circuit devices processing.

Process Simulation

The behavior and properties of all semiconductor devices are defined by their three geometrical dimensions and concentration profile of impurities. The main goal of process simulation is to model a virtual device with geometry and properties identical with the real structure. Sentaurus TCAD process is an advanced, complete, and highly flexible multi- The TCAD modeling input commands of individual steps make accessible all parameters which characterize the real fabrication processes. In this work TCAD process simulation tools have been used to build the device structures and to calculate the associated mechanical strain generated inside the device due to applying strain engineering technology (i.e. "Global" and "Local" strain techniques), using elastic anisotropic model. The major processing steps in the fabrication process of BJT/HBT devices used in this study will be described, namely deposition, etching, diffusion, oxidation, and mechanical stress computation.

Deposition

Deposition is the process of growing different layers (insulators, metals, poly Si). The deposition may be isotropic, anisotropic, polygonal (deposition according to a user-supplied polygon), and fill step (fill of the structure with a specific material up to a specific coordinate).

The thickness of a deposited layer is defined by the mask, the growth rate, and the deposition time. As the simulated region (volume) is changed, remeshing of the analyzed structure is required. The model parameters and local deposition rates can be specified to construct a geometry which is similar to the one observed in reality. In addition, fields such as stress, pressure, and dopants can be initialized in the deposited layers. With isotropic deposition process, it is possible to specify piecewise linear field values as a function of deposited depth.

Etching

Etching is the process of removing a material which is in contact with gas. The etching process may be isotropic, anisotropic, directional, Polygonal (Etch according to a user-supplied polygon), Fourier (Angle-dependent etching where etch rate is a cosine expansion of the etching angle), Crystallographic (Angle-dependent etching where etch rate is dependent on the crystallographic direction), and Chemical-mechanical planarization. In general, etching technology consists of both dry and wet etch methods. Dry etching methods include plasma etching, reactive ion etching, sputtering, ion beam etching, and reactive ion beam etching, while wet etching is liquid chemical etching. In Sentaurus TCAD simulator a set of geometry operations is provided which allows defining local etching rates that can be used to approximate the modifications of the structure. During the etching process the thickness of etched layer is defined by the mask, etching rate and etching time. Etch stop and selected material removal can be defined in TCAD simulator.

Sentaurus TCAD MGOALS library can be used to perform etching and deposition operations both in 2D and 3D. The MGOALS library operation can be summarized as follows:

Analyzing the starting structure for the interfaces that will be changed during the operation.

Performing the geometry-changing operations.

Remeshing the entire structure, so that nodes in the silicon region are retained as much as possible in their original locations to minimize the interpolation errors.

Diffusion

Dopant redistribution is caused by dopant and point defect diffusion as a result of chemical reactions at the interfaces and inside the layers, convective dopant transport due to internal electrical fields and material flow, and moving material interfaces when the substrate is under high temperature process. Diffusion is a high temperature process of diffusion of impurities due to the existing concentration gradient, which depends on temperature, time of diffusion, and boundary conditions characterizing the interface concentration of diffusion species at the Si substrate and gas interface. Sentaurus TCAD simulator includes various physical models with different levels of complexity depending on the type of impurity, point defects and electric field effects. For example, the simplest constant diffusion model neglects the interactions between the dopants and point defects. The pair diffusion model assumes that the gradient of dopant concentration and dopant-defect pairs with the electric field are the driving force of diffusion in active Si regions predefined by the mask. To control the dopant diffusion through various annealing cycles in the fabrication process, the temperature budget should be minimized to ensure very steep and shallow doping profiles for miniaturized structures and devices.

Oxidation

Oxidation is the process of growth of thermal silicon dioxide (SiO 2 ) at the silicon surface. This process depends on temperature, time, and oxidation ambient which characterize the diffusion of oxidants from the gas-oxide interface to Si-SiO 2 interface, and its reaction with Si.

The ramping up and down temperature cycles with slow temperature changes procedure are used to prevent structure damage due to the induced mechanical stresses and materials motion in the structure caused by the thermal oxidation process, as a result of the thermal expansion coefficients mismatch between SiO 2 layer and silicon substrate, and the growth of oxide on top of silicon substrate. The oxidation process has three steps: Diffusion of oxidants (H 2 O, O 2 ) from the gas-oxide interface through the existing oxide to the silicon-oxide interface.

Reaction of the oxidant with silicon to form new oxide.

Motion of materials due to the volume expansion, which is caused by the reaction between silicon and oxide.

Various oxidation models are implemented in TCAD simulator. They differ in complexity and coupling of the physical models involved. The oxidant diffusion equation is solved using the generic partial differential equation solver of Sentaurus Process. The model we use in this work is the default model which allows all materials to be simulated as nonlinear viscoelastics.

Mechanical Stress Computation

Mechanical stress plays an important role in the process simulation and modeling.

Mechanical stress modifies the bandgap energy, the carrier's mobility, and can affect the oxidation rates, which can alter the shapes of thermally grown oxide layers. Therefore, accurate computation of mechanical stress is important especially with the continuous trend towards designing process flows that produce the desired kinds of stress in the device to enhance the device performance. In Sentaurus TCAD simulator, stress computation simulations are performed in four distinct steps: Define the mechanics equations; the equations used in Sentaurus Process are equations that define force equilibrium in the quasistatic regime.

Define the boundary conditions for the mechanics equations. Define the material properties; in this part the relationship between stresses and strains is defined.

Define the mechanisms that drive the stresses; this is performed through intrinsic stresses, thermal mismatch, material growth and lattice mismatch, and densification.

Stress is solved in all materials, and the parameters describing materials behavior are included in the simulator's parameters database. In this work, the elastic anisotropy model has been used to calculate the associated mechanical stress with the fabrication process [3][4].

Device Simulation

Device simulation and modeling simulates numerically the electrical behavior of semiconductor structures by solving coupled, non-linear, partial differential equations that describe the physics of the device performance. The main purposes of the device simulation are to understand and to describe the physical processes in the interior of a device, and to make reliable predictions of the behavior of the next-generation devices. The electrical characterization includes static, time-dependent, large and small-signal frequency-dependent, electrical behavior, and parameter extraction of the studied structures. The quality of the physical models and the calibrated parameters used in the device simulation is very important for understanding the physical mechanisms in semiconductor devices, and for reliable prediction of the device characteristics. The input device structure typically comes from process simulation steps using Sentaurus process, or through TCAD operations and process emulation steps with the aid of tools like Sentaurus Structure Editor (SSE), or Mesh and Sentaurus Structure Editor. In device simulation, a real semiconductor device, such as a transistor, is approximated by a virtual device as a 2D or 3D structure whose physical properties are discretized onto a nonuniform mesh of nodes. The geometry (grid) of the device contains a description of the various regions, that is, boundaries, material types, the locations of any electrical contacts, and the locations of all the discrete nodes and their connectivity. The data fields contain the properties of the device, such as the doping profiles, in the form of data associated with the discrete nodes. By default, a device simulated in 2D is assumed to have a thickness in the third dimension of 1 m [5].

Sentaurus TCAD device simulation allows for arbitrary combinations of transport equations and physical models, which allows for the possibility to simulate all spectrums of semiconductor devices, from power devices to deep submicron devices and sophisticated heterostructures [1] [4]. In the following, the formulation of physical models and equations used in our structures device simulations will be described.

Basic Semiconductor Equations

The fundamental semiconductor equations that rule the semiconductor devices are Poisson's equation that solves the relationship between electrostatic potential and charge density, and charge carrier continuity equation that reflects the fact that sources and sinks of the conduction current are fully compensated by the time variation of the mobile charge [6] [7]. The Poisson equation is given by

. = 3.1
Where where is the electrical permittivity, is the electrostatic potential, and is the charge density.

The charge density is given by

= ( + ) 3.2
Where q is the elementary electronic charge, n and p are the electron and hole densities, is the concentration of ionized donors, and is the concentration of ionized acceptors.

Therefore, Poisson's equation can be written as

. = ( + ) 3.3
The general equations for describing electron and hole transport in a semiconductor under nonequilibrium conditions are the electron and hole continuity equations:

= R + 1 . 3.4 = R 1 .

3.5

Where J n and J p are the electron and hole current densities respectively, G n and G p are the electron and hole generation rates (m 3 s 1 ) due to external excitation, and R n and R p are the electron and hole recombination rates.

The current densities can be expressed in terms of quasi-Fermi levels and and as The total current density J at any point of the analyzed structure is then calculated as a sum of electron and hole currents = + 3.19

Transport Models

Drift-Diffusion Model (DD)

The drift-diffusion model is widely used as a starting point for simulating the carrier transport in semiconductors. For isothermal simulation the DD model incorporated in TCAD simulator numerically solves Poisson's equation, and the carrier continuity equation selfconsistently to get electron and hole concentrations, and the electrostatic potential at all points within the device structure (equations 3.14 and 3.15), assuming full impurity ionization, nondegenerate statistics, steady state, and constant temperature (the carrier temperatures are assumed to be in equilibrium with the lattice temperature). Even though the DD model is a simple model and not a very precise model for complex semiconductor devices simulation, it is still a good starting point for any device simulation due to the relative simplicity of the model, relative good convergence properties and its ability to provide an initial overview of the device operation in a short time [8].

Hydrodynamic Model (HD)

Due to its limitations, the conventional drift-diffusion model is not applicable for simulations in the submicron regime. As well, it is incapable to describe properly the internal and/or the external characteristics of state of the art semiconductor devices. Mainly, the DD approach cannot reproduce velocity overshoot and often overestimates the impact ionization

Generation-Recombination Models

Generation-Recombination are the processes by which mobile charge carriers are created and eliminated. The process by which both carriers annihilate each other is called recombination.

In this process the electrons fall in one or multiple steps into the empty state which is associated with the hole, both carriers eventually disappear in the process. The carrier generation is a process where electron-hole pairs are created by exciting an electron from the valence band of the semiconductor to the conduction band, thereby creating a hole in the valence band. The carrier generation-recombination models used in this study are the Shockley-Read-Hall (SRH) recombination model, and Auger recombination model.

SRH-Recombination Model

The SRH model describes the statistics of recombination of holes and electrons in semiconductors occurring through the mechanism of trapping. The net recombination rate for trap-assisted recombination is given by: = , ( + ) + ( + ) 3.25

The variables n 1 and p 1 are defined as

= , 3.26 = , 3.27
Where is the difference between the defect level and intrinsic level, and are the electron and hole lifetimes, and n i,eff is the effective intrinsic concentration.

The SRH recombination rate using Fermi statistics is given by Where N C and N V are the effective density-of-states, E C , E V are conduction and valence band edges, E F,n and E F,p are the quasi-Fermi energies for electrons and holes respectively.

The doping dependence of the SRH lifetimes is modeled through Scharfetter relation as

( ) = + + 1 +

3.31

This indicates that the solubility of a fundamental acceptor-type defect is strongly correlated to the doping density.

Auger Recombination Model

Auger recombination is typically important at high carrier densities such as in heavily doped regions or in cases of high injection. The rate of band-to-band Auger recombination is given by

= + ( + , ) 3.32
Where and are Auger coefficients.

The temperature-dependant Auger coefficients are given by ( ) = , + , + ,

Where T 0 =300K.

The default coefficients of Auger recombination model for Si are summarized in Table 5. For Ge and SiGe materials, same parameters have been used [5].

Coefficient [cm 6 s -1 ] [cm 6 s -1 ] [cm 6 s -1 ] H[1] N 0 [cm -

Mobility Models

Carrier mobility in semiconductors is determined by a variety of physical mechanisms.

Electrons and holes are scattered by thermal lattice variation, ionized and neutral impurities, dislocations, and electrons and holes themselves. Several models for carrier mobility in Si and strained Si have been implemented in TCAD simulator. In this study, Philips unified mobility model [9][10], high field saturation model [6], stress-induced electron mobility model [11], and piezoresistance mobility model have been used .

High Field Saturation Model

High-field behavior shows that carrier mobility decreases with electric field. With the increase of the applied electric field, carriers gain energies above the ambient thermal energy and are able to transfer energy to the lattice by optical phonon emission. Consequently, the mean drift velocity is no longer proportional to the electric field, but rises more slowly, and the mobility has to be reduced accordingly. Finally the velocity saturates to a finite velocity known as the saturation velocity (v sat ) which is principally a function of lattice temperature.

The high field mobility degradation due to carrier velocity saturation effects is introduced by the Canali model through the relation

( ) = ( + 1) 1 + ( + 1)

3.44

Where = , 300 ,

3.45

Where is the low field mobility, is the deriving field, is a temperature dependant model parameter.

Mobility Models Under Stress

Piezoresistance Mobility Model

This approach focuses on modeling of the variation of the carrier's mobility with the applied stress. The applied stress changes the electrical resistivity (conductivity) of the material, leading to mobility modification according to the relation

= 1 . 3.46
and the current density is given by = .

J

3.47

Where = , , is the second rank mobility tensor, is the isotropic mobility without stress, 1 is the identity tensor, is the stress tensor, is the tensor of piezoresistance coefficients that depend on the doping concentration and temperature distribution, J is the vector of the carrier current without the stress.

Taking in consideration the change in the effective masses and anisotropic scattering due to the applied stress, the piezoresistance coefficients become

= , + , ( , ) 3.48
The first term is an independent constant represents the change in the effective mass effect, while the second term represents the scattering effect. Where ( , ) is doping-dependent and temperature-dependent factor. Furthermore, the enhancement factors for both electron and hole mobilities due to the applied stress have been calculated using the piezoresistance mobility factor model [5] [12].

Stress-Induced Electron Mobility Model

This approach focuses on the modeling of the mobility changes due to the carrier redistribution between bands in silicon due to the applied stress. The origin of the electron mobility enhancement has been explained in chapter 2. The stress-induced electron mobility enhancement is given by

= 1 + 1 1 + 2 ( , ) ( ) 1 3.49
Where is electron mobility without the strain, and are the electron longitudinal and transverse masses in the subvalley, respectively, and , are the change in the energy of the unstrained and the strained carrier sub-valleys, is the quasi-Fermi level of electrons. The index i corresponds to a direction (i.e.

is the electron mobility in the direction of the x-axis of the crystal system and, therefore, , should correspond to the two-fold subvalley along the x-axis).

The general expression of the mobility along valley i, which includes the stress-induced carrier redistribution and change in the intervalley scattering, is given by = Where , , and are model fitting parameters, h i is the ratio between unstrained and strained relaxation times for intervalley scattering in valley i, and is the ratio between strained and unstrained total relaxation times for the valley i.

Band Structure Models

Bandgap Narrowing

Band-gap narrowing is observed in highly-doped semiconductors. At low impurity concentrations the interaction between electrons and holes and the Coulomb force acting between them doesn't play any role. Thus the impurities do not disturb the property of the crystal and the forbidden energy gap Eg is well defined by sharp band edges. On the other hand, at high impurity concentrations, there is Coulomb interaction between the ionized impurities, and thus overlapping of the wave functions associated with these impurities. This results in a splitting of the impurity energy level, and impurity band is formed. As a result the potential energy of these ionized impurities is reduced resulting in a narrowing of the bandgap.

The Bandgap narrowing for the Slotboom model is given by = + + 0.5

3.53

Where and are model parameters.

The bandgap narrowing effect has been modeled based on experimental measurements of in n-p-n transistor and for p-n-p transistor with different base doping concentrations and a 1D model for the collector current [13].

Intrinsic Density

In Sentaurus TCAD device simulation, the intrinsic carrier density for undoped semiconductors as a function of the effective density of states in the conduction and valence band, and the bandgap energy is given by the relation

( ) = ( ) ( ) ( ) 2 3.53
The effective intrinsic carrier density is given by

, = 2 3.54
Where is the doping-dependant bandgap narrowing [5].

Effective Density-of-States

Sentaurus Device computes the effective density-of-states as a function of carrier effective mass. The effective mass may be either independent of temperature or a function of the temperature-dependent band gap. For carriers in silicon the effective mass temperature-dependant is the most appropriate model for calculating the effective density-of-states.

The effective density of states in the conduction band N C is given by , , = 2.540933 × 10 300 3.55

Where m n is the effective mass of electrons.

The effective density of states in the valence band N V is given by , , = 2.540933 × 10 300 3.55

Where m p is the effective mass of holes [5][14].

TCAD Calibration

In order to calibrate and to study the accuracy of TCAD simulator, simulations have been performed in accordance with Monte Carlo (MC) simulation performed by Bundeswehr University-Munich [15]. The calibration process has been executed through three approaches; and the obtained results will be presented.

Mobility Models Calibration

A sample of Si 1-x Ge x substrate with different homogenous doping concentrations of Boron and Arsenic impurities (10 17 cm -3 to 1020 cm -3 ), and different Germanium content, x, (0% -0.28%) used in the calibration process of Sentaurus TCAD simulator is shown in Fig. 39. Table 6: Physical models used in the calibration process.

A comparison between TCAD and MC simulation results for electron velocity and hole velocity for both Boron and Arsenic doping impurities are shown in the following figures ( Fig. 40 to Fig. 44) (for Ge_content = 8%, 24%, at T=300K). The complete set of results are shown in the Appendix (i.e, Ge_content = 4%, 12%, 18%, 28%). In addition to that, the minority carriers mobility in Si 1-x Ge x substrate as a function of Germanium content, x, at low electric field values has been simulated using TCAD modeling (model (II)) . The TCAD simulation results have been compared with MC simulation results

reported by [16] as shown in Fig. 44. x Ge x substrate as a function of Ge content x using model (II).

MC TCAD (N A =10 18 cm -3 ) MC TCAD (N A =10 16 cm -3 ) MC TCAD (N A =10 14 cm -3 ) Ge_Content x [%]
As shown in the previous figures, good agreement has been achieved between MC and TCAD simulation results. Verifying the validity of the models used in TCAD simulator for mobility and velocity simulations.

Transport Models Calibration

In order to study the accuracy of TCAD default transport models, a reference NPN-SiGe-HBT device (f Tpeak =100 GHz) simulated by MC simulation reported by [17] has been used. The device structure and the doping profile are shown in Fig. 45. The reference structure has been simulated using TCAD. The simulations have been performed using the default transport models and parameter files. Simulation results are then compared with MC simulation results as shown in Fig. 46 and Fig. 47. The results indicate that the transport models need to be calibrated (specially the HD model).

To calibrate the HD transport model, TCAD simulations have been run using the default parameters reported by Stratton and Blotekjaer (Table 4). The simulation results are then compared with MC simulation results as shown in In addition to that, the electrostatic potential, electron and hole density, electron velocity, electron temperature, collector current, and transit frequency have been simulated using TCAD.

Due to the fact that TCAD simulator is not capable to simulate 1D bipolar transistor, different

IMEC Structure

After performing step one and step two in the calibration process, a real structure has been simulated using the data from IMEC HBT device structure (f Tpeak =240 GHz). Firstly, process simulation has been performed to build the device structure. The graded Ge profile and the doping profiles in the emitter, base, and collector regions of the device are identical to the ones from IMEC HBT device as shown in Fig.59 [19]. simulations have been calibrated in collaboration with Universität der Bundeswehr München using Monte Carlo simulations.

Conclusion

CHAPTER 4 TCAD Simulation Results

In advanced semiconductor devices technology, strain engineering technology can be used as an additional degree of freedom to enhance the carriers transport properties due to band In this work mainly two approaches have been used to create the desired mechanical strain inside the device. The first approach is through introducing strain engineering technology principle at the device base region using SiGe extrinsic stress layer. The second approach is through introducing strain engineering technology principle at the device collector region by means of local strain technique using strain layers. However, another approach to create strain inside the device is through using nitride liners, but this technique was not functional to create the desired strain inside the device, therefore no further work was done on it. In what follows, a detailed description of the main approaches used in this study and the obtained results are presented.

Strain Technology at the Base Region

NPN-Si-BJT Device with Extrinsic Stress Layer

The impact of introducing a SiGe stress layer formed over the extrinsic base layer, and adjacent to the intrinsic base of NPN-Si-BJT device on the electrical properties and frequency response has been investigated using TCAD modeling [1][2]. Process simulations are performed using Sentaurus TCAD software tools to build the device structure, and to calculate the associated mechanical stress due to the existence of the extrinsic stress layer using anisotropic elasticity model [3]. In what follows, the major processing flow steps are described. An oxide layer is then deposited to the same level of the emitter's mandrel nitride. The nitride of the emitter mandrel is then removed using selective etching technique, and using the underlying oxide layer as an etch-stop material resulting in an emitter opening. The opening extends downward to the oxide, and nitride spacers are formed on the sidewalls of the opening.

After that, the underlying oxide is etched also by selective etching technique to expose the base layer in the emitter opening as shown in Fig. 70. This is followed by the deposition of polysilicon and a hard mask of nitride. The nitride hard mask is etched and used to etch the polysilicon resulting in a T-shape emitter. Finally, the oxide is etched from all but under the overhanging portion of the emitter structure, and the contacts are formed using a proper technique as shown in Fig. 71. For simulation efficiency and saving of simulation resources, only half of the device is used for further device simulations as shown in Fig.72 [4]. The simulated effect of interposing the extrinsic stress layer at the device is shown in Fig. 73; the isocontour lines represent the stress values generated in the x-direction (S xx ) and y-direction (Syy) of the device due to the existence of the extrinsic SiGe stress layer.

Impact of Strain

Mechanical stress on semiconductors induces a change in the band structure and this in turn affects the carriers mobility. This effect can be explained by the deformation potential theory [5]. Strain changes the number of carrier sub-valleys and eventually a change in the actual band gap in the material [6]. The carrier redistribution that takes place between the various sub-valleys causes the change in mobility. The mobility enhancement is attributed to the increase in the occupancy of the conduction band valleys [7]. Consequently, incorporating an extrinsic SiGe stress layer at the bipolar device will create tensile strain in the direction of electrons flow to improve electrons mobility, and compressive strain in the direction of holes flow to improve holes mobility [8] . This process will decrease the intrinsic base resistance through the enhanced hole mobility, resulting in an improvement in the maximum oscillation frequency of the device according to the relation

= 8 4.1
Where f T is the cut-off frequency, R B is the base resistance, and C CB is the collector base capacitance.

On the other hand, the vertical tensile strain in the direction of electrons flow under the emitter will enhance the device electrons flow. Furthermore, reduces the electrons transit time through the enhanced electron mobility due to the applied strain, which will improve the cut off frequency according to the relations [9].

= = ( 1) + 1 + 1 4.2 = 1 2 4.3
Where is the base transit time, Q is the minority charge stored in the neutral base region, I is the time dependent quasi-static transfer current, is the base width, is the average electron minority mobility in the neutral base region, V is the thermal voltage, is the drift factor, f = exp ( ) is the drift function, is the electron velocity at the end of the neutral base region and is the total transit time.

Additionally, introducing an extrinsic stress layer at the device base region will decrease the bandgap energy through the reduction of the conduction band energy as shown in Fig. 74.

This in turn will improve electrons injection efficiency from emitter to collector, and enhance the device electrical performance. As well, the applied strain will induce a change in the band structure and this in turn affects the carrier mobility, resulting in an approximately 27% of mobility improvement in YY direction for electrons at the base region as shown in Fig. 75.

Electrical Simulation

Sentaurus TCAD software tools have been used to perform the two-dimensional device simulations using hydrodynamic transport model (HD), where the carrier temperature equation The results obviously show that bipolar device with extrinsic stress layer exhibit better high frequency characteristics in comparison with an equivalent standard conventional device. An approximately 42% of improvement in f T , and 13% of improvement in f MAX in NPN-Si-BJT with extrinsic stress layer have been achieved. These improvements are mainly due to the enhanced vertical electron mobility, which can be fully accounted to the impact of interposing the extrinsic stress layer in the device.

The impact of changing the Ge content at the extrinsic stress layer on the stress values generated inside the device (i.e, Sxx, Syy, and Szz), MAX , f MAX and f T has been studied, the obtained results are shown in Fig. 79 to Fig. 81. As shown in the figures, increasing the Ge content at the extrinsic stress layer will increase the stress values generated inside the device, which in turn improves the high frequency characteristics of the device and enhances the current gain. These improvements are related to the increase of the lattice constant difference between the silicon substrate and the SiGe stress layer, which will increase the stress values induced at the base, resulting in a decrease of the conduction band energy and hence the total bandgap energy.

This decrease in the bandgap energy will improve the electrons injection efficiency from emitter to collector, consequently enhancing the high frequency characteristics of the device.

Unfortunately, increasing the Ge content at the stress layer will also increase the misfit dislocations between the silicon substrate and the stress layer, which may cause a degradation of the device performance. Therefore, the Ge content at the stress layer must be controlled and chosen carefully to avoid such problems.

Moreover, the impact of changing the device's emitter width on the device performance has been studied. The result illustrates that increasing the emitter width will decrease the stress values induced at the base region of the device as shown in Fig. 82, causing a degradation of the device performance.

Conclusion

Simulation results demonstrate that Si bipolar devices with extrinsic stress layer exhibit better high frequency characteristics, and an enhancement of the maximum current gain in comparison with an equivalent standard conventional BJT device. An approximately 42%

Sxx Syy Szz

Emitter width [nm] improvement in f T and 13% improvement in f MAX have been achieved in NPN-Si-BJT with extrinsic stress layer at the base region. Furthermore, an enhancement of the collector current by almost three times, and an enhancement of the maximum current gain MAX in NPN-Si-BJT with extrinsic stress layer have been found. These improvements are related to the electron and hole mobility's enhancement, and to the decrease of the bangap energy. This in turn improves electron injection efficiency from emitter to collector, and improves the whole device electrical performance.

NPN-SiGe-HBT Device with Extrinsic Stress Layer

The higher gain, speed and frequency response of the SiGe-HBT make silicon-germanium devices more competitive in areas of technology where high speed and high frequency response are required. However, due to the continuous demand for such devices it becomes imperative to develop new bipolar device architectures suitable for high frequency and power applications.

Therefore, various techniques and efforts have been proposed to improve the performance of HBT devices through grading germanium profile at the base [11], introduction of carbon to improve 1D doping profile [12], and reduction of the emitter width [13]. An additional approach to improve the device performance is to enhance the carrier transport by changing the material transport properties by means of strain engineering technology. [14][15]. In what follows the impact of introducing a SiGe extrinsic stress layer formed above the extrinsic base layer, and adjacent to the intrinsic base of NPN-SiGe-HBT device on the electrical properties and frequency response will be presented.

Process simulations have been performed using Sentaurus TCAD software tools to build the device structure and to calculate the associated mechanical stress. The major processing steps of the NPN-SiGe-HBT device architecture are similar to those of NPN-Si-BJT device described previously except that we have a SiGe-base in this case. The complete HBT device structure with SiGe extrinsic stress layer is shown in Fig. 83. Likewise, for simulation efficiency and saving simulation resources, only half of the device is used for further device simulations as shown in Fig. 84. The graded Ge profile and the doping profiles at the emitter, the base and the collector regions have been taken from IMEC Microelectronics HBT device profile [4].

Impact of strain

Due to the addition of the extrinsic stress layer, stress is generated inside the device (i.e, Sxx) as shown in Fig. 85; these values are extracted at the middle of the base. An approximately 500 MPa of an additive compressive stress (Sxx) is generated at the base region, and 500 MPa of tensile stress (Sxx) is lessen at the collector region as shown in the figure . Chapter.2 provides a detailed discussion of the impact of strain on the bandgap energy and the carrier mobility.

Electrical Simulation

Sentaurus TCAD software tools have been used to perform the two-dimensional device simulations using HD transport model. The standard silicon models and parameter files included in TCAD software library cannot be used for the SiGe device with external stress. Therefore, specific parameter files and physical models have been calculated by Universität der Bundeswehr München (BU) using Monte Carlo simulations.

To acquire accurate simulation results, the HBT device has been divided into two regions;

The first one is the SiGe-base which is divided into two zones corresponding to different Ge content and doping concentration values as shown in Table 8 and Table 9. The second region is -0 .0 6 -0 .0 4 -0 .0 2 0 .0 0 0 .0 2 0 .0

Region (I)

For these regions, specific models for SiGe band-gap, bandgap-narrowing, effective mass, energy relaxation, mobility for hydrodynamic simulation and drift-diffusion simulation have been calculated by BU and implemented in our simulator using tabulated models compiled in C code.

Two methods have been used by BU to calculate the impact of stress on the bandgap energy: the first approach is based on Analytical Method, while the second approach uses the Empirical Pseudopotential Method (EPM). The results are summarized in Table 10 and Table 11. However, the results obtained using EPM are more reliable as they are based on a more realistic band structure. Therefore, the models and parameter files calculated using EPM approach are used in further device simulations. The cut-off frequency (f T ) and the maximum oscillation frequency (f MAX ) are plotted versus the collector current (Ic) using the physical models and parameters provided by Bundeswehr University. Simulation results show that introducing extrinsic stress layer on the HBT device structure will enhance the maximum oscillation frequency f MAX , and the cut-off frequency f T for both bandgap calculation approaches as shown in the following figures. An approximately 5% of improvement in f MAX , and 3% of improvement in f T have been achieved in comparison with the standard conventional HBT device (without extrinsic stress layer). Furthermore, the components of the transit time have been extracted for both HBT devices as a function of the collector current as shown in Fig. 91. Simulation results show that introducing the extrinsic stress layer on the device structure will decrease the total transit time, and hence improve the device performance. This reduction of the transit time is shown in Fig. 92 and Fig. 93 where the base transit time (t b ), and the collector transit time (t c ) have been plotted

versus the collector current separately for illustration. shown, increasing the Ge content at the extrinsic stress layer will increase the stress values generated inside the device. This is related to the increase of the lattice constant difference between the SiGe base layer and the SiGe stress layer, which will increase the stress values induced at the base. Nevertheless, increasing the Ge content at the stress layer will also increase the misfit dislocations between the two layers, which may cause a degradation of the device performance. Therefore, the Ge content at the stress layer must be controlled and chosen carefully to ensure device performance enhancement.

In addition, the impact of changing the device's emitter width on the device performance has been studied. The result shows that increasing the emitter width will decrease the stress values induced at the base of our device as shown in Fig. 95, causing degrade action of the device performance.

Conclusion

Simulation results show that introducing SiGe extrinsic stress layer on NPN-SiGe-HBT device will enhance the maximum oscillation frequency f MAX (~5%), the cut-off frequency f T (~3%) and the total transit time in comparison with a standard conventional HBT device (without extrinsic stress layer). However, applying strain engineering technology at the base region of NPN-SiGe-HBT device using the extrinsic SiGe strain layer is less efficient in comparison with the obtained results for the NPN-Si-BJT device. This is related to the high sensitivity of silicon Emitter width [nm] Sxx Szz material to strain in comparison with the SiGe base of NPN-SiGe-HBT device which is already stressed due to the existence of Ge content at the base.

Strain Technology at the Collector Region

Applying strain engineering technology at the base region of NPN-Si-BJT device by means of extrinsic SiGe strain layer can strongly enhance the device's performance due to the sensitivity of silicon material to strain. On the other hand, applying strain engineering technology at the base region of NPN-SiGe-HBT device through using SiGe strain layer is less efficient in comparison with the obtained results for the NPN-Si-BJT device, because the SiGe base is already stressed due to the existence of Ge at the base as presented previously. The intensive study of the transit time in the strained NPN-SiGe-HBT device shows that the main modification of the device's total transit time in comparison with the standard conventional NPN-SiGe-HBT device arises from the reduction of the collector transit time. Verifying that silicon material is more sensitive to strain than the SiGe base region, and the device's performance improvements are mainly due to the impact of the induced strain at the collector region.

Depending on the obtained results reported in [16], [17] and the sensitivity of silicon material to strain, new NPN-SiGe-HBT device's architecture employing strain engineering technology at the collector region will be presented. In this approach the desired strain is introduced during the device fabrication process through a specific device architecture employing silicon nitride (Si 3 N 4 ) and silicon oxide (SiO 2 ) strain layers at the collector region.

NPN-SiGe-HBT Device Employing Si3N4 Strain Layer

In this approach the desired strain is generated inside the device through introducing strain engineering technology principle using local strain technique by means of introducing silicon nitride (Si 3 N 4 ) strain layer at the collector region. Nitride films can induce stresses greater than 1GPa upon thermal treatment, which arises from two sources: Coefficient of thermal expansion mismatch between silicon and nitride film, and intrinsic film stress caused by film shrinkage. The origin of intrinsic stresses comes from the energy configuration of the deposited atoms or ions. Processing conditions such as temperature, pressure, deposition power, reactant and impurity concentrations are important factors in determining the magnitude and strain type (i.e. compressive or tensile) [18] [19].

In what follows the impact of employing a nitride strain layer at the collector region on the device's performance parameters will be presented.

Process Simulation and Device Structure

Process simulations are performed using Sentaurus TCAD software tools to build the device structure and to calculate the associated mechanical stress. In what follows, the major processing steps will be described. The process simulation starts by the deposition of a silicon layer as shown in Fig. 96. Then the silicon substrate is etched using selective etching technique as shown in 97. This is followed by deposition of a nitride layer as shown in Fig. 98. Next the nitride layer is etched using selective etching technique, and a silicon layer is deposited, this is followed by selective etching of this layer to form the device intrinsic base region as shown in Fig. 99. As shown in the previous figures; introducing Si 3 N 4 strain layer at the collector region will create compressive strain along the horizontal direction, and tensile strain along the vertical direction, which causes a reduction in the device's bandgap energy at the collector region. This is related to the reduction of the conduction band energy due to the applied strain. In addition, strain will induce a change in the band structure, and this in turn affects the carrier mobility, resulting in an approximately 20% of mobility improvement in YY direction for electrons in the neutral collector region.

Electrical Simulation

Sentaurus TCAD software tools have been used to perform the two dimensional device simulations using HD model without taking in consideration self heating effect [10]. The model parameters used in TCAD simulations have been calibrated by BU using Monte Carlo simulation.

The stress-induced mobility enhancement has been calculated using the Piezoresistivity model. A detailed description of the models used in the simulation is presented in chapter 3. V CB = -0.2

[Volt] These performance improvements are related to the enhanced carrier transport properties.

V CB = 0.0 [Volt] V CB =0.4 [Volt] V CB =0.6 [Volt] V CB =0.8 [Volt] V CB =1.0 [Volt] f T (
The carrier transport enhancement is mainly due to the enhanced carrier mobility by means of the induced tensile and compressive strains at the collector region. In addition to that, the induced strain at the collector region reduces the intrinsic collector resistance R C without altering the base-collector junction capacitance C BC as shown in Fig. 113, where the base-collector junction capacitance C BC is plotted versus the base-collector bias V CB .

The intrinsic collector resistance R C has a direct impact on the cut-off frequency f T value according to the relation: Where is the forward transit time, C BE is the base-emitter junction capacitance, and R E is the emitter resistance. Therefore, any reduction in the intrinsic collector resistance R C will result in a reduction of the R C ×C BC product, and consequently enhance the cut-off frequency f T value.

Furthermore, the breakdown voltage BV CEO has been extracted for both pre-and poststrain HBT devices for different collector doping levels (0.3Nc,0.4Nc, 0.5Nc, 0.65Nc, 0.75Nc, 0.8Nc, 0.9Nc, Nc, 1.5Nc, 2Nc, 3Nc, 4Nc), where Nc is the reference collector doping level taken from IMEC HBT device profile. The BV CEO values have been extracted from the plot of the absolute value of the base current as a function of V CE for both HBT devices for different collector doping level as shown in Fig. 114. The obtained results are summarized in Table 13. This reduction in the breakdown voltage value is related to the decrease of the collector band gap energy due to the induced strains at the collector region. However, despite of the very small decrease in the BV CEO value, the f T ×BV CEO product enhancement is about 6% by means of strain engineering (f T ×BV CEO (without-stress) =597.68 GHz.Volt, f T ×BV CEO (with-stress) =633.1

GHz.Volt ).

The maximum oscillation frequency f MAX , the relation between f MAX and f T is given by

f = f 8 R C 4. 5
Therefore, any enhancement in f T value will enhance the maximum oscillation frequency f MAX of the device.

Moreover, the f T , f MAX and BV CEO have been simulated for various collector doping levels. A typical BV CEO N C characteristic has been observed for which the BV CEO values decrease with increasing N C (high f T value). The peak breakdown voltage value is reached for the lowest collector doping for both devices as shown in Fig. 115. shown in Fig. 118 and Fig. 119. A trade-off between f T and f MAX values has been observed. This trade-off is illustrated in Fig. 120 where f T is plotted versus f MAX for different BV CEO values (i.e.

different N C ). As shown in Fig. 120, an improvement up to 43% in f T value can be achieved for a given f MAX , and up to 7% of improvement in f MAX value for a given f T can be achieved by means of strain engineering, as well by choosing the proper collector doping level. The dependence of f T , f MAX and BV CEO values of the investigated HBT devices on the selected doping distribution at the collector region can be explained by referring to Kirk effect phenomena in HBT devices [20]. Where the Kirk current density J K is given by

J = qv N N + 2 (V + V ) qW 4.6
Where V CB is the applied collector-base voltage, V BI is the base-collector built-in voltage, W C is the collector layer thickness and v sat is the electron saturation velocity of the collector layer.

The peak f T is limited by the onset of the Kirk effect or base push-out. Therefore using a high collector doping level suppresses the onset of the Kirk effect. Consequently, higher peak f T can be obtained, due to the reduced base widening at high current. On the other hand, increasing the collector doping level N C has two major disadvantages on the device's performance. Firstly, C BC will be increased, leading to a reduced power gain or f MAX . Secondly, the maximum electric field at the base-collector junction will be higher, leading to more impact ionization and thus

Conclusion

A new SiGe-HBT device's architecture employing nitride strain at the collector region has been presented. The device performance parameters have been investigated and compared with an equivalent standard conventional HBT device using TCAD modeling.

NPN-SiGe-HBT Device Employing SiO2 Strain layer

A second approach to improve the device performance is to introduce the desired strain inside the device through using a silicon oxide (SiO 2 ) stain layer at the collector region during the device fabrication process. Silicon has a high affinity for oxygen, and an amorphous native oxide film rapidly forms on Si upon exposure to an oxidizing ambient. During thermal processing SiO 2 layer expands and contracts at different rates compared to the silicon substrate according to their thermal expansion coefficients. Because of this thermal expansion coefficients mismatch, as well the growth of oxide on top of silicon substrate, a mechanical strain is induced. The magnitude and the type of the induced mechanical strain are determined by controlling the processing conditions such as temperature, pressure, deposition power, reactant and impurity concentrations [21] [22].

In this work, the oxide strain layer is formed so that the desired strain is induced at the collector region, i.e, a mechanical compressive strain is induced along the horizontal axis, and a mechanical tensile strain is induced along the vertical axis. This approach is different from the normal oxide shallow trenches isolation (STI) which is done with respect to the CMOS device fabrication process.

In what follows, a novel NPN-SiGe-HBT device architecture utilizing SiO 2 stressor at the collector region will be presented. Likewise the NPN-SiGe-HBT device employing nitride strain at the collector region, process simulations are performed using Sentaurus TCAD software tools to build the device structure and to calculate the associated mechanical stress. The major processing steps are described in the following figures.

Impact of Strain

The impact of introducing a SiO 2 strain layer in the HBT device's architecture on the bandgap energy, and the stress values generated inside the device (Sxx, Syy and Szz) are shown in the following figures (131 to Fig. 134). The mobility enhancement due to the applied stress has been calculated using the stress-induced electron mobility model. This model has been calibrated on mobility-strain enhancement results reported by [23] as shown in Fig. 135, taking into account the saturation improvement of mobility at high stress values. The impact of SiO 2 strain layer on the device electron mobility is shown in Fig. 136. As shown in the previous figures; introducing SiO 2 strain layer at the collector region will create compressive strain along the horizontal direction, and tensile strain along the vertical direction which causes a reduction in the device's bandgap energy at the collector region. This is related to the reduction of the conduction band energy due to the applied strain. In addition to that, strain will induce a change in the band structure. This in turn affects the carrier mobility, resulting in an approximately 42% of mobility improvement in Y-direction for electrons in the neutral collector region which is consistent with the obtained results reported by [23].

Electrical Simulation

TCAD Sentaurus software tools have been used to perform the 2D device simulations using hydrodynamic model (HD) without taking in consideration self heating effect and thermal behavior. However, the device's thermal behavior could be degraded by the formation of the oxide layer through affecting the device's thermal conductivity. The model parameters used in TCAD simulations have been calibrated by BU using Monte Carlo simulations. A detailed description of the models used is presented in chapter 3.

The same procedure carried out for investigating NPN-SiGe-HBT device with nitride strain at the collector region will be performed for NPN-SiGe-HBT device employing oxide Similarly, the base collector capacitance has been extracted as a function of collector base bias (V CB ) for both HBT devices as shown in Fig. 141. The induced tensile and compressive strains due to employing SiO 2 strain layer at the collector region will enhance the electron vertical mobility, which in turn reduces the collector resistance R C without altering the base collector junction capacitance. Consequently, the R C ×C BC product will decrease. As a result, f T will be enhanced due to the decrease of the R C ×C BC product according to the relation (4.4). V CB [volt] with_stress without_stress in the breakdown voltage BV CE0 value (~1%), the f T ×BV CE0 product enhancement is approximately 12% by means of strain engineering at the collector region (f T ×BV CE0 (without-stress) =424.6 GHz.Volt, f T ×BV CE0 (with-stress) =476.4 GHz.Volt ). and f MAX in HBT device utilizing SiO 2 strain layer at the collector region can be explained in the same manner as the trade-off between f T and f MAX in HBT device utilizing Si 3 N 4 strain layer at the collector region explained previously.

Conclusion

A novel NPN-SiGe-HBT device's architecture employing oxide strain layer at the collector region has been presented. The device performance parameters have been investigated

and compared with an equivalent standard conventional HBT device using TCAD modeling.

Simulation results show that the strained silicon HBT device exhibits better high frequency characteristics in comparison with an equivalent standard conventional HBT device. An approximately 14% of improvement in f T , and 9% of improvement in f MAX have been achieved

for the new device's architecture. The breakdown voltage BV CEO has been extracted for both devices for different collector doping level N C . The obtained results have shown a very small reduction in the BV CEO values for the strained silicon HBT device (~1%). In addition to that, a trade-off between f T and f MAX values has been observed from f MAX versus f T plot for different collector doping level N C . An improvement up to 47% in f T value can be achieved for a given f MAX , and up to 14% of improvement in f MAX value can be achieved for a given f T by means of strain engineering technology, as well choosing the proper collector doping level.

Summary & Conclusion

SiGe HBTs have proven their capability to support large bandwidth and high data rates for high-speed communication systems. Devices with impressive f T values have been demonstrated that only a couple of years ago would have been believed to be reserved for III-V technologies. SiGe HBT technologies that exhibit higher operating speed can be leveraged for advanced circuits and systems in different ways; they can open up new applications at very high frequencies (THz). Their speed can be traded for lower power dissipation, or they can be used to mitigate the impact of process, voltage and temperature variations at lower frequencies for higher yield and improved reliability (case of automotive radar application). Due to the continuous demand for devices in areas of technology where high speed and high frequency response are required, it becomes imperative to develop new bipolar device architectures suitable for high frequency and power applications. Among the various techniques and efforts proposed to improve the performance of HBT devices, strain engineering technology provides an additional degree of freedom to enhance the carriers transport properties due to band structure changes and mobility enhancement. The mobility of charge carriers in bipolar devices can be enhanced by creating mechanical tensile strain in the direction of electrons flow to improve electrons mobility, and by creating mechanical compressive strain in the direction of holes flow to improve holes mobility.

This work investigates the effects of introducing strain engineering technology principle on Silicon Bipolar Junction Transistor (BJT) and Silicon-Germanium Heterojunction Bipolar

Transistor (HBT) devices as a possible alternative to dimensional scaling. This thesis focuses on how strain affects Si BJT and SiGe HBTs, where compressive and tensile strains are applied during the devices fabrication process. The compressive and tensile strains are created through two approaches. The first approach is through introducing strain engineering technology principle at the device base region using SiGe extrinsic stress layer formed over the extrinsic base layer, nearly three times in strained silicon NPN-Si-BJT device has been attained. The obtained results

for applying the same technique on NPN-SiGe-HBT device have shown that applying strain on the base region of the HBT device is less efficient in comparison with the BJT device, as the SiGe base is already stressed due to the existence of Ge at the base. An approximately, 3% of improvement in f T , and 5% of improvement in f MAX have been achieved. In addition to that, a decrease in the device's total transit time has been observed. The intensive study of the transit time in the strained NPN-SiGe-HBT device shows that the major modification of the device's total transit time in comparison with the standard conventional NPN-SiGe-HBT device arises from the reduction of the collector transit time. Verifying that silicon material is more sensitive to strain than the SiGe base region, and the device's performance improvements are mainly due to the impact of the induced strain at the collector region.

Consequently, new NPN-SiGe-HBT device architectures utilizing strain layer at the collector region is proposed. Simulation results show that applying strain engineering concept at the collector region of the investigated devices will enhance the device's performance and frequency response characteristic. By using Si 3 N 4 as a strain layer, an approximately, 8% of improvement in f T , and 5% of improvement in f MAX have been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BV CE0 value (1% 4%), the f T ×B VCE0 product enhancement is about 12% by means of strain engineering at the collector region. Moreover, using SiO 2 as a strain layer at the device's collector region will result in 14% of improvement in f T , and 9% of improvement in f MAX and an enhancement of 12% of f T ×BV CE0 product in comparison with an equivalent standard conventional device.

The performance improvements in the strained BJT/HBT devices are related to the induced tensile and compressive strains inside the device, this in turn will enhance both electron and hole mobility's, and improves the devices electrical performance. The obtained results obviously show that strain engineering technology principle applied to BJT/HBT device can be a promising approach for further devices performance improvements.

However, the work done in this thesis opens new doors for further research and investigations in the field of strained BJT/HBT devices. In addition to that, it provides the suitable background and the calibrated simulator tools for future work on SiGe HBT compact modeling.

2. 3

 3 Conclusion .................................................................................................................125 Strain Technology at the Collector Region ..................................................................................126 3. NPN-SiGe-HBT Device Employing Si 3 N 4 Strain Layer ..................................................126 3.1 Process Simulation and Device Structure ..................................................................127 3.2 Impact of Strain..........................................................................................................131 3.3 Electrical Simulation..................................................................................................132 3.4 Conclusion .................................................................................................................140 4. NPN-SiGe-HBT Device Employing SiO 2 Strain layer .....................................................141 4.1 Impact of Strain..........................................................................................................145 4.2 Electrical Simulation..................................................................................................146 4.3 Conclusion .................................................................................................................152 References ................................................................................................................................153

Chapter 1 :

 1 Introduction & Background; provides a brief discussion of the SiGe HBT technology, theoretical background, state-of-the-art and the motivation for carrying out this research.

Fig. 1 :

 1 Fig.1: Energy band diagram for a graded-base SiGe HBT and a Si BJT.

E , ( 0 )

 0 is the Ge-induced band offset at x=0, E , (W ) is the Ge-induced band offset at x=W b , n io is the low-doping intrinsic carrier density for Si, and is the effective density-of-states ratio between SiGe and Si C N V ) SiGe represents the position-dependent Ge-induced changes associated with both the conduction and valence band effective density-of-states. The collector current density for SiGe HBT can be written as

  By substituting equation 1.2 into equation 1.8 and integrating, the SiGe HBT transit time becomes

[ 9 ]

 9 [10]. The inherent performance advantages of heterojunction bipolar transistors (HBTs) over conventional bipolar junction transistors have been recognized, and Kroemer first explained the underlying principle of the heterojunctions in 1957[11].The work by Kroemer on the heterojunction opened a new door for achieving higher speeds than anticipated with silicon bipolar transistors. Although the performance advantages of HBTs over BJTs were well understood, no fabrication technologies were available to produce high quality heterojunctions until the 1970s, where epitaxial growth of SiGe heterostructures demonstrated by Erich Kasper using molecular beam epitaxy (MBE)[12]. With the advent of heteroepitaxy, the concept of strained layers has been extended to include other elemental semiconductors. These developments set the stage for IBM's development of SiGe HBTs in 1987 using MBE. The successful demonstrations of SiGe HBT technology, in both high-performance digital and analogue circuit applications, are the results of over 15 years of steady research progress from initial material preparations in 1984, through device demonstrations from 1987-1992 to large scale circuit fabrication in 1994 and commercial products in 1998. Since then, the interest in SiGe HBTs from both academia and industry rose progressively through the years causing the figures of merit to increase and reach current state-of-the-art levels. Today's state-ofthe-art SiGe pre-production technologies have shown cut-off frequency close to 300 GHz, and maximum frequency of oscillation close to 400 GHz as reported recently by our partners of the European joint research project DOTFIVE[13] [14].

4 [

 4 Wang et al. investigated the impact of mechanical uniaxial stress on the characteristics ofSiGe heterojunction bipolar transistors uing a four-point bending apparatus to apply a uniaxial stress in the range of 200 MPa to + 200 MPa. The SiGe HBTs used in their study were fabricated using 0.18 µm self-aligned SiGe BiCMOS technology, with an emitter area of 0.2x10.16 µm 2 . Their results show that the performances of SiGe HBTs are varied with the stress level. The changes in the collector current, base current, current gain, and the breakdown voltage were found to be linearly dependent upon the mechanical uniaxial stress level, for the range of 200 MPa to + 200 MPa. The strain-polarity dependence of the collector current, base current, and current gain was positive under uniaxial compressive stress, whereas that of the breakdown voltage was negative[START_REF] Wang | Effects of Mechanical Uniaxial Stress on SiGe HBT Characteristics[END_REF].Yuan et al. in their work reported the performance of Si-SiGe HBT under the biaxial compressive and tensile mechanical stress with the comparison of BJTs. An externally uniform mechanical displacement at the center with the diameter of 13 mm on 100 mm wafers for both SiGe HBT and Si BJT devices has been applied as shown in Fig.2. The average biaxial strain used in this study is 0.028%. The current gain variations of the mechanically strained Si-SiGe heterojunction bipolar transistor (HBT) and Si bipolar junction transistor (BJT) devices were investigated. The current gain change for HBT is found to be 4.2% and 7.8% under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. The change for BJT is found to be 4.9% and 5.0% under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. Their results are shown in Fig.3. Moreover, their results show that the current gain changes show a good linear dependence on external biaxial mechanical stress as shown in Fig.49].

Fig. 2 :

 2 Fig.2 : Schematic diagram of the externally applied mechanical stress on the wafer.

Fig. 3 :

 3 Fig.3: Gummel plot of Si BJT and SiGe HBT devices without and with mechanical stress (V BC =0 V).

Fig. 4 :Fig. 6 :

 46 Fig.4: Current gain changes of SiGe HBT and Si BJT device as a function of stress level.

Fig. 7 :

 7 Fig.7: Current gain vs. base is increased by almost one order of magnitude in the strained Si HBT.

Fig. 9 :

 9 Fig.9: Output characteristics of a first generation SiGe HBT for both pre-strain and post 0.123% biaxial strain

Fig. 10 :Fig. 11 :

 1011 Fig.10: A cross-sectional view of a complete BJT device formed according to Chidambarrao et al.

Fig. 12 :

 12 Fig.12: 2D cross-section of the simulated virtual substrate HBT device with strained-Si/SiGe heterointerface emitter

Fig. 16 :

 16 Fig.16: Schematic cross-section of novel device architecture of IMEC.

  . The major deficiencies of the original structure have been alleviated, such as the marginal thickness of the external base connection, the marginal overlap of the polyemitter over the L-shaped spacer, the marginal L-shaped spacer formation, and the sloped profile of the pedestal etch. The resulting device has an effective emitter width of 80nm. This fully self-aligned SiGe:C HBT architecture featuring a single step epitaxial collector/base process, removal of the extrinsic part of the device using sacrificial emitter, external base reconstruction, L-shaped spacer formation after removal of the sacrificial emitter, and in-situ As doped polyemitter demonstrated 400 GHz f MAX . In addition, introducing carbon in the collector suppressed segregation of P in the collector to the Si/SiGe interface, which resulted in a strong increase of the f MAX because of the reduction of C BC . The resulting f T and f MAX curves are shown in Fig.18, and the base-collector reverse diode current is shown in Fig.19. The influence of the addition of 0.2% carbon to the undoped collector part is demonstrated. This improvement is the accumulated result of a further lateral scaling of the HBT device, a significant decrease of the base resistance and of the base-collector capacitance compared with the reference HBT device.

Fig. 17 :

 17 Fig.17:Cross-section SEM picture of the original (left) and improved (right) emitter/base structure.

Fig. 20 :

 20 Fig.20: Schematic cross-section of the IHP novel device architecture.

Fig. 21 :Fig. 22 :

 2122 Fig.21: Sketch of the FSA-SEG SiGe HBT architecture

Fig. 24 :

 24 Fig.24: Illustration of some exemplary applications of Terahertz radiation.

Fig. 25 :

 25 Fig.25: DOTFIVE project work packages

Fig. 26 :

 26 Fig.26: Arbitrary solid body under external forces (left) and a section of the solid body under external force (right).

Fig. 27 :

 27 Fig.27: Miller indices of three important planes in a cubic crystal.

Fig. 28 :

 28 Fig.28: Stress direction [x',y',z'] relative to the crystallographic coordinate system [x,y,z].

  .35) represent the geometrical change of the sample under stress, and the last term is the resistivity dependence on stress. For most semiconductors, the stress-induced resistivity change is much larger than the geometrical changeinduced resistance change, therefore, the resistivity change by stress is the determinant factor of the piezorestivity.

  have diamond lattice structure, where each atom is surrounded by four equidistant nearest neighbors which lie at the corners of a tetrahedron. The unit cell can be considered as two interpenetrating face-centered cubic (fcc) lattices separated by a/4 along each axis of the cell, where, a, is the lattice constant as shown in Fig.29. At 300K, the lattice constants of Si and Ge are 5.431 Å and 5.6575 Å, respectively [9]. The first Brillouin zone represents the central (Wigner-Seitz) cell of the reciprocal lattice. It contains all points nearest to the enclosed reciprocal lattice point. The first Brillouin zone for cubic semiconductors is a truncated octahedron. It has fourteen plane faces; six square faces along the <100> directions and eight hexagonal faces along the <111> directions. The coordinate axes of the Brillouin zone are the wave vectors of the plane waves corresponding to the Bloch states (electrons) or vibration modes (phonons). The points and directions of symmetry are conventionally denoted by Greek letters, as shown in Fig.29. The zone center is called the point (k=0), the directions <100>, <110>, and <111> are called, respectively, , , and directions and their intersections with the zone boundaries are called, X, K and L points respectively [12].

Fig. 29 :

 29 Fig.29 : Structure of the fcc crystal lattice (left), and the first Brillouin zone of the fcc lattice (right).

Fig. 30 :

 30 Fig.30 : Electronic band-structure of Si and Ge calculated by Pseudopotential method.

  The hydrostatic component leads to an energy band shift, and a change of the bandgap, while the uniaxial strain component splits the degeneracy of the conduction and valence bands but it has no effects on the average band energy. Under biaxial compressive strain, the six-fold degenerate Si conduction band energy ( 6 ) is splitted. The [001] conduction bands (two-fold degenerate 2 bands) move up in energy, while the [100] and [010] conduction bands (four-fold degenerate 4 bands) move down in energy. On the contrary, under biaxial tensile strain, the [001] conduction bands (two-fold degenerate 2 bands) move down in energy, while the [100] and [010] conduction bands (four-fold degenerate 4 bands) move up in energy. This splitting of degeneracy in the conduction band reduces the conductivity effective mass and suppresses intervalley scattering, hence enhancing the transport properties. The impact of compressive and tensile strains on the conduction band energy is illustrated in Fig.31.

Fig. 31 :

 31 Fig.31 : Schematic representation of the effects of hydrostatic and uniaxial stress on the conduction band energy in Si for tensile and compressive strains.

  energy and the heavy hole (HH) being raised in energy, thereby reducing both intersubband and intrasubband scattering. The impact of compressive and tensile strains on the valence band energy is illustrated in Fig.32.

Fig. 32 :

 32 Fig.32: Schematic representation of the effects of hydrostatic and uniaxial stress on the valence band energy in Si for tensile and compressive strains.

  and uniaxial deformation potentials at the Si conduction bandedge required for symmetry considerations, is the trace strain tensor, ( ) is the longitudinal (transverse) strain component (along [001], = , and = + ), and ( ) is the longitudinal (transverse) effective mass. of the strain-induced energy change in the energy of carrier bands in silicon is given by Where, a, b, and d are deformation potentials that correspond to the model, i corresponds to the carrier band number, and are the components of the strain tensor in the crystal coordinate system. The final value of the change in the energy band can be calculated by averaging the energy changes in all the sub-bands. The expression for the change in energy can be summarized as: number of subvalleys considered in the conduction and valence bands, respectively, and =300K [25].

  Fig.33: (a) A schematic diagram of the bulk lattice of a thin Si 1 x Ge x film to be grown on top of a thin bulk silicon layer with the top Si 1 x Ge x film being compressively strained. (b) A schematic diagram of the bulk lattice of Si film to be grown on top of a bulk Si 1 x Ge x film with the top Si film being tensile strained.

Fig. 35 :

 35 Fig.35: TEM micrographs of 45-nm n-type MOSFET with nitride-capping film with a large tensile stress[35].

Fig. 36 :

 36 Fig.36 : Schematic diagram of the externally applied mechanical stress on the Si (100) wafer.

1 .

 1 IntroductionTechnology Computer-Aided Design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices. TCAD simulation and modeling can be used to predict the device performance and expedite the device development/optimization process for new technology. As well, it greatly enhances the learning process through providing a remarkable physical insight into what real integrated circuits structures look like. The Sentaurus TCAD platform provides a comprehensive capability to simulate detailed and realistic process structures for subsequent electrical analysis by Sentaurus Device and it provides tools for interconnect modeling and extraction that supply critical parasitic information for optimizing chip performance[1]. TCAD modeling is used to design, analyze, and optimize semiconductor technologies and devices with fundamental and accurate models. The use of TCAD in semiconductor manufacturing and development of new technologies is two-fold: Process simulation and Device simulation. Process simulation models the complex flow of semiconductor fabrication steps and ends up with detailed information on geometric shape and doping profile distribution of a semiconductor device. The device simulation uses the information of the process simulation as the input file to calculate the characteristics of semiconductor devices and parameters extraction.

  dimensional process simulator for developing and optimizing silicon and compound semiconductor process technologies. It offers unique predictive capabilities for modern silicon and non-silicon technologies, when properly calibrated to a wide range of the latest experimental calibration methodology. It uses powerful numerical algorithms that simulate process steps like implantation, diffusion and dopant activation, etching, deposition, oxidation, and epitaxial growth in different semiconductor materials with efficient meshing for robust and stable simulation. The fabrication of integrated circuit devices requires a series of processing steps called a process flow. A process flow is simulated by issuing a sequence of commands that corresponds to the individual process steps. Also process conditions like the ambient chemical composition, temperature, pressure, etc. during individual fabrication steps can be controlled. In addition, several control commands allow selecting physical models and parameters, grid strategies, and graphical output preferences. The final output is a 2D or 3D device structure which can be used for device simulation. The major processing steps involved in the manufacturing of integrated circuit devices are shown in Fig.38. Each of these steps contain numerous possible variations in process controls, and may take several weeks to complete[1][3].

Fig. 38 :

 38 Fig.38: Major process steps involved in the manufacturing of integrated circuit devices.

  and hole mobilities.The quasi-Fermi levels are linked to the carrier concentrations and the potential throughBoltzmann approximations asWhere is the effective intrinsic concentration and is the lattice temperature.By substituting equations (3.8) and (3.9) into the current density expressions in equations (3The final term accounts for the gradient in the effective carrier concentration, which takes into account the band gap narrowing effect.The effective electric fields can be defined as conventional formulation of the current as the sum of a diffusion and drift term can be written asHere the diffusion current is proportional to the gradient of the carrier concentration, indicating that carriers flow from a region of high concentration to one of low concentration. The constants D n and D p are the diffusion coefficients or diffusivities, and are related to the mobilities n and p by Einstein's relations: = 3.17

Table 4 :

 4 generation rates. Consequently, the hydrodynamic model (or energy balance model) is preferred for determining the velocity overshoot and describing properly the characteristics of state of the art semiconductor devices, as it incorporates ballistic effects missing in the DD model. The HD model couples the basic set of semiconductor equations; Poisson equation and continuity equations, with energy balance equations for electrons, holes, and the lattice. The current densities in the HD case are defined as a sum of four contributions: masses of electrons and holes, and are the electron and hole carrier temperatures, and are parameters function of the material. The first term accounts for spatial variations of electrostatic potential, electron affinity, and the bandgap. The three remaining terms take into account the contributions due to the gradient of concentrations and carrier temperature, and the spatial variation of the effective masses, respectively. The energy fluxes for electrons, holes and the lattice are given by of the material, and is the lattice thermal conductivity. The default parameter values of Sentaurus Device are summarized in Table 4. These parameters are accessible in the parameter file of Sentaurus Device. Different values of these parameters can significantly influence the physical results, such as velocity distribution and possible spurious velocity peaks. By changing these parameters, Sentaurus Device can be tuned to a very wide set of hydrodynamic/energy balance models as described in the literature. HD model parameter values from Stratton and Blotekjaer In TCAD simulator, the electron, hole, and the lattice temperatures are solved by specifying the keywords in the command file; Electron Temperature, Hole Temperature, and Lattice Temperature, respectively. In spite of the time consuming and convergence problems associated with using the HD model in our study, it has the advantages of good accuracy and proper description of the characteristics of state of the art semiconductor devices [5] [8].

  donors concentrations respectively, ( ) and F( ) are analytic functions describing minority impurity and electron-hole scattering. , , , , and are model parameters.

( 1 )

 1 Mobility models calibration through simulating a sample of Si 1-x Ge x substrate parameterized with different Ge content (0% -28%), different doping concentrations for Arsenic and Boron impurities (10 17 cm -3 -10 20 cm -3 ), and different applied electric fields. (2) Transport models calibration through simulating a reference transistor (f Tpeak =100 GHz) and comparing the obtained results with Monte Carlo simulation results. (3) Simulating IMEC NPN-SiGe-HBT structure and comparing the obtained results with measurement. A description of each approach

Fig. 39 :

 39 Fig.39:The Si 1-x Ge x substrate used in TCAD simulator calibration process.

Fig. 40 :

 40 Fig.40: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) model (I) (b) model (II), (Ge_content = 8%, T=300K).

Fig. 41 :

 41 Fig.41: Comparison between MC and TCAD simulation results for eVelocity vs. Electric field using (a) model (I) (b) model (II), (Ge_content = 8%, T=300K).

Fig. 42 :

 42 Fig.42: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) model (I) (b) model (II), (Ge_content = 24%, T=300K).

Fig. 43 :

 43 Fig.43: Comparison between MC and TCAD simulation results using model (II) for (a) eVelocity vs.Electric field (b) hVelocity vs. Electric field, (Ge_content = 8%, T=300K).

Fig. 44 :

 44 Fig.44: Comparison between TCAD and MC simulation results for the minority carriers mobility in Si 1-

Fig. 45 :

 45 Fig.45: The reference transistor and the doping profile used in the calibration process.

Fig. 48 .Fig. 46 :Fig. 48 :Fig. 49 :Table 7 :Fig. 50 :Fig. 51 :Fig. 52 :

 484648497505152 Fig.46 : Ic comparison between TCAD and MC simulation results

Fig. 53 :Fig. 54 :Fig. 55 :Fig. 58 :

 53545558 Fig.53 : The reference transistor with different cross sections

Fig. 59 : 25 A

 5925 Fig.59 : IMEC HBT device, the graded Ge profile and the doping profiles in the emitter, base, and collector regions.

Fig. 61

 61 Fig.61 : f T comparison between measurements and TACD simulation results (V BC =0Volt).

  Fig.62 : C CB comparison between measurements and TACD simulation results.

  TCAD simulation tools are widely used throughout the semiconductor industry to speed up and cut the costs of developing new technologies and devices, since they make it possible to explore new technologies and concepts. TCAD simulations also provide information about the inner operation of devices, thus simplifying improvements on existing technologies. TCAD consists of two main branches: process simulation and device simulation. Process simulation models the complex flow of semiconductor fabrication steps and ends up with detailed information on geometrical shape and doping profile distribution of a semiconductor device. The device simulation uses the information of the process simulation as the input file to calculate the characteristics of semiconductor devices and parameters extraction. Different physical models have been used in our TCAD simulator, including; HD and DD models, carrier mobility models (Philips unified mobility model, and the high field saturation model). The stress-induced mobility enhancement has been calculated using the Piezoresistivity model, and the stress-induced electron mobility model. The carrier generation-recombination models used are the Shockley-Read-Hall recombination model, and Auger recombination model. As well, the doping induced bandgap narrowing model, the intrinsic density model, and the effective density of states model have been employed. The model parameters used in TCAD

  structure changes and mobility enhancement. The mobility of charge carriers in bipolar devices can be enhanced by creating mechanical tensile strain in the direction of electrons flow to improve electrons mobility, and by creating mechanical compressive strain in the direction of holes flow to improve holes mobility. The compressive and tensile strains are created through various methods and techniques such as Global Strain, Local Strain and Mechanical Strain. A detailed description of each technique is presented in chapter 2.

  Fig.65. This is followed by the deposition of a silicon layer to form the device base region as shown in Fig.66. Next, a thin layer of oxide and a layer of nitride are deposited as shown in Fig.67.

Fig. 64 :

 64 Fig.64: Process simulation: Fabrication of shallow and deep trenches isolation.

Fig. 65 :

 65 Fig.65: Process simulation: Deposition of etch-stop material and a thin layer of polysilicon.

Fig. 66 :

 66 Fig.66: Process simulation: Formation of the device base region.

Fig. 67 :

 67 Fig.67: Process simulation: Deposition of oxide and nitride layers.

Fig. 68 :

 68 Fig.68: Process simulation: Formation of the emitter mandrel and recesses.

Fig. 69 :

 69 Fig.69: Process simulation: Deposition of the SiGe extrinsic stress layer

Fig. 70 :

 70 Fig.70: Process simulation: Formation of the emitter opening and the sidewall spacers.

Fig. 71 :

 71 Fig.71: Process simulation: Formation of the Tshape emitter.

Fig. 72 :

 72 Fig.72: Cross-section of one half of the device (left), and the device doping profile (right) [4].

Fig. 73 :

 73 Fig.73 : Cross section of one half the device region of interest, the isocontour lines represent the stress Sxx (left) induced in the x-direction and Syy (right) induced in the y-direction of the structure.

Fig. 74 :

 74 Fig.74: Impact of strain on the bandgap energy. Fig.75: Electron mobility enhancement due to the applied strain.

  Fig.76shows the forward Gummel plots obtained by simulating both NPN-Si-BJT incorporating SiGe extrinsic stress layer at the base region, and a standard conventional NPN-Si-BJT device.

Fig. 76 :

 76 Fig.76: Comparison of forward Gummel plots for both conventional BJT, and BJT with stress layer (Ge=25%, W E =130 nm).

Fig. 77 :

 77 Fig.77: Cut-off frequency as a function of collector current for both devices (Ge=25%, W E =130 nm).

Fig. 78 :

 78 Fig.78: Maximum oscillation frequency as a function of collector current for both devices (Ge=25%, W E =130 nm).

Fig. 79 :

 79 Fig.79: Variation of the stress values generated inside the device with Ge content at the stress layer (W E =130 nm).

Fig. 80 :

 80 Fig.80: Variation of the maximum current gain with Ge content at the stress layer (W E =130 nm).

Fig. 81 :

 81 Fig.81:Variation of f T and f MAX with Ge content at the stress layer (W E =130 nm).

Fig. 82 :

 82 Fig.82: Variation of the stress values generated inside the device with the device's emitter width.

Fig. 83 :

 83 Fig.83: The complete structure of the NPN-SiGe-HBT device with extrinsic SiGe stress layer.

Fig. 84 :

 84 Fig.84: Cross-section of one half of the device (left), and the graded Ge profile, and the doping profile at the emitter, base and collector regions (right) [4].

Fig. 85 :

 85 Fig.85: Stress values (Sxx) generated inside the device due to the addition of the extrinsic stress layer.

  of the device without Ge content (the emitter and the collector regions). The different device regions and zones are shown in Fig.86.

Fig. 86 :

 86 Fig.86: Different regions and zones used for device simulations.

Fig. 87 :

 87 Fig.87: Improvement in f T due to the addition of the extrinsic stress layer (EPM).

Fig. 88

 88 Fig.88 Improvement in f MAX due to the addition of the extrinsic stress layer (EPM).

Fig. 89 :

 89 Fig.89: Improvement in f T due to the addition of the extrinsic stress layer (Analytical Method).

Fig. 90 :

 90 Fig.90: Improvement in f MAX due to the addition of the extrinsic stress layer (Analytical Method).

Fig. 91 :

 91 Fig.91:Transit time versus the collector current for HBT device with and without extrinsic stress layer.

Fig. 94 :

 94 Fig.94: Variation of the stress values generated inside the device with Ge content at the stress layer (W E =130 nm).

Fig. 95 :

 95 Fig.95: Variation of the stress values generated inside the device with the device emitter width.

Fig. 96 :

 96 Fig.96: Process simulation: Deposition of silicon substrate.

Fig. 97 :

 97 Fig.97: Process simulation: Etching of silicon substrate.

Fig. 98 :

 98 Fig.98: Process simulation: Deposition of nitride layer.

Fig. 99 :

 99 Fig.99: Process simulation: Nitride layer etching, and silicon substrate deposition.

Fig. 100 :

 100 Fig.100: Process simulation: Deposition of the SiGe base.

Fig. 101 :

 101 Fig.101: Process simulation: Deposition of oxide layer, formation of emitter opening, and deposition of polysilicon layer.

Fig. 102 :

 102 Fig.102: Process simulation: Etching of oxide and nitride layers, and formation of T-shape emitter.

Fig. 103 :

 103 Fig.103: Process simulation: Final device structure showing stress isocontour lines generated inside the device.

Fig. 104 :

 104 Fig.104: Isocontour lines representing the stress values generated inside the device; standard conventional NPN-SiGe-HBT device (left), and strained silicon NPN-SiGe-HBT (right).

3 . 2

 32 Impact of StrainThe impact of introducing Si 3 N 4 strain layer in the HBT device's architecture on the bandgap energy, and the stress values generated inside the device (Sxx, Syy, and Szz) are shown in Fig.105to Fig.108. Moreover, the impact of Si 3 N 4 strain layer on the carrier mobility is shown in Fig.109.

Fig. 107 :Fig. 105 :Fig. 109 :

 107105109 Fig.107: Impact of strain on Syy. Fig.108: Impact of strain on Szz.

A

  Fig.111. Simulation results illustrated in Fig.110 and Fig.111 show good agreement between measurement data and simulation results, verifying the validity of the physical models and parameters used in the TCAD simulations.

Fig. 110 :

 110 Fig.110: Forward Gummel plots comparison of measurement and simulation results.

Fig. 111 :

 111 Fig.111: f T comparison between measurement and simulation results (V BC =0Volt).

Fig. 113 :Fig. 114 :

 113114 Fig.113: C BC as a function of VCB for both HBT devices.

Fig. 115 :

 115 Fig.115: Variation of BV CEO with the collector doping level N C .

Fig. 116 :

 116 Fig.116: f T versus collector doping levels characteristics for both devices.

Fig. 117 :

 117 Fig.117: f MAX versus collector doping levels characteristics for both devices.

Fig. 118 :

 118 Fig.118: f T versus BV CEO characteristics for both devices.

Fig. 119 :

 119 Fig.119: f MAX versus BV CEO characteristics for both devices.

Fig. 120 :

 120 Fig.120: Trade-off between f T and f MAX for both HBT devices.

  lower BV CEO value. The dependence of f MAX on f T and the collector-base capacitance C CB is given by equation (4.5). As the results indicate, HBT devices with high f T tend to have a high C CB value. The C CB dominates and f MAX decreases despite the rise of f T value. And that can explain the trade-off between f T and f MAX illustrated in Fig.120. In the case of strained SiGe-HBT device, the tradeoff is modified through an enhancement of the collector conductivity without changing base-collector capacitance. transit time has been extracted for both HBT structures as a function of the collector current density Jc as shown in Fig.121. Simulation results show that the new SiGe-HBT device architecture employing nitride strain at the collector region exhibit lower transit time (t e , t b , and t c ) in comparison with an equivalent standard conventional HBT device. This enhancement on the device transit time is related to the reduction of the device bandgap energy and mobility enhancement by means of strain at the collector region.

Fig. 121 :

 121 Fig.121: The transit time as a function of the collector current density for both HBT devices.

Fig. 122 :

 122 Fig.122: Process simulation : Deposition of silicon substrate.

Fig. 123 :

 123 Fig.123: Process simulation: Silicon substrate etching.

Fig. 124 :

 124 Fig.124: Process simulation: Deposition of oxide, etching of oxide and deposition of polysilicon.

Fig. 125 :

 125 Fig.125: Process simulation: Deposition of silicon followed by etching of oxide and polysilicon layers.

Fig. 126 :

 126 Fig.126: Process simulation: Deposition of SiGe base.

Fig. 127 :

 127 Fig.127: Process simulation: Deposition of oxide layer, formation of emitter opening and deposition of polysilicon layer.

Fig. 128 :

 128 Fig.128: Process simulation: Etching of oxide and polysilicon layers to form the T-shape emitter.

Fig. 130 :

 130 Fig.130: Isocontour lines representing the stress values generated inside the device; standard conventional NPN-SiGe-HBT device (left), and strained silicon NPN-SiGe-HBT device (right).

Fig. 131 :

 131 Fig.131: Impact of strain on the bandgap energy. Fig.132: Impact of strain on Sxx.

Fig. 133 :Fig. 135 :

 133135 Fig.133: Impact of strain on Syy. Fig.134: Impact of strain on Szz.

Fig. 136 :

 136 Fig.136: eMobility enhancement due to the applied strain.

  Fig.138show good agreement between measurement and simulation results, verifying the validity of the physical models and parameters used in the TCAD device simulations.

Fig. 137 :

 137 Fig.137: Comparison of Gummel plots of IMEC measurements and the conventional HBT device simulations.

Fig. 141 :

 141 Fig.141: C BC as a function of V CB for both HBT devices.

Fig. 142 :Fig. 143 :

 142143 Fig.142: Absolute value of the base current as a function of V CE for both HBT devices.( W E =130 nm, V BE = 0.70 V).

Fig. 144 :

 144 Fig.144: f T versus collector doping level characteristics for both devices.

Fig. 145 :

 145 Fig.145: f MAX versus collector doping levels characteristics for both devices.

  Fig.146: f T versus BV CEO characteristics for both devices.

Fig. 147

 147 Fig.147: f MAX versus BV CEO characteristics for both devices.

Fig. 148 :

 148 Fig.148: Trade-off between f T and f MAX for both HBT devices.

Fig. 150 :

 150 Fig.150: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 4%, T=300K).

Fig. 151 :

 151 Fig.151: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 12%, T=300K).

Fig. 152 :

 152 Fig.152: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 18%, T=300K).

Fig. 153 :

 153 Fig.153: Comparison between MC and TCAD simulation results for hVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 28%, T=300K).

Fig. 154 :

 154 Fig.154: Comparison between MC and TCAD simulation results for eVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 4%, T=300K).

Fig. 155 :

 155 Fig.155: Comparison between MC and TCAD simulation results for eVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 12%, T=300K).

Fig. 156 :

 156 Fig.156: Comparison between MC and TCAD simulation results for eVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 18%, T=300K).

Fig. 157 :

 157 Fig.157: Comparison between MC and TCAD simulation results for eVelocity vs. Electric field using (a) Model (I), and (b) Model (II), (Ge_content = 28%, T=300K).

Fig. 158 :

 158 Fig.158: Comparison between MC and TCAD simulation results using Model (II) for (a) eVelocity vs. Electric field (b) hVelocity vs. Electric field, (Ge_content = 4%, T=300K).

Fig. 159 :

 159 Fig.159: Comparison between MC and TCAD simulation results using Model (II) for (a) eVelocity vs. Electric field (b) hVelocity vs. Electric field, (Ge_content = 12%, T=300K).

Fig. 160 :

 160 Fig.160: Comparison between MC and TCAD simulation results using Model (II) for (a) eVelocity vs. Electric field (b) hVelocity vs. Electric field, (Ge_content = 18%, T=300K).

Fig. 161 :

 161 Fig.161: Comparison between MC and TCAD simulation results using Model (II) for (a) eVelocity vs. Electric field (b) hVelocity vs. Electric field, (Ge_content = 28%, T=300K).

Fig. 162 :

 162 Fig.162 : The reference transistor with different cross sections used in the calibration process.

Fig. 163 :Fig. 165 :Fig. 169 :

 163165169 Fig.163: Hole density comparison between MC and HD model simulation results for the crosssection 50 nm

4.2 Current State-of-the-Art

	As mentioned previously, the European joint research project DOTFIVE partners have
	achieved SiGe:C HBTs with maximum frequency of oscillation (f MAX ) 400 GHz which are
	today's state-of-the-art SiGe:C HBTs. These partners achieve this milestone through completely
	different architectures. The first partners (IMEC & IHP Microelectronics) approache 400 GHz
	f MAX through fully self-aligned (FSA) SiGe:C architecture. While the second partner (ST
	Microelectronics) approaches 400 GHz f MAX through a conventional double-polysilicon FSA
	selective epitaxial growth (SEG) Si/SiGe:C HBT. In what follows a brief description of each
	approach is given.
	IMEC and IHP have developed two novel device architectures for half terahertz RF
	performance to reduce further the device parasitic elements compared to the reference quasi self-
	aligned (QSA) architecture (f T = 205 GHz, and f MAX = 275 GHz ). The first architecture named
	G1G architecture is the novel FSA IMEC architecture. The second architecture is the novel FSA
	IHP architecture. The novel device architecture that IMEC explores, attempts to reduce the
	device parasitics significantly.
	deice performance by means of strain engineering technology. As they are using an approximate
	theoretical model in their simulations, this approximate theoretical model might need to be
	calibrated and/or taking more effects in consideration to achieve more precise results.

Simulation results reported by Jankovic et al. show optimistic improvements of the HBT

Table 2 [

 2 14] [56].

	Parameter Measurements	BiCMOS9MW	B3T	B4T	Unit
		conditions
	f T	V CB =0.5 V	230	260	265	GHz
	f MAX	V CB =0.5 V	290	350	400	GHz
	W E	TEM	0.13	0.13	0.11	µm
	J C	Peak f T	15.0	11.8	13.0	mA/µm 2
		V BE =0.75V	950	1595	1750	-
	V AF		>200	>200	>200	V
	BV EBO		2.2	2.1	2.1	V
	BV CEO	V BE =0.7V	1.5	1.55	1.50	V
	BV CBO		5.5	6.0	6.0	V
	R Bi		2.7	2.5	2.5	k
	Table 2: HBT parameters comparison (wafer averages) FOR BICMOS9MW, B3T and B4T technologies

Table 3 :

 3 The elastic compliance coefficients Cij [GPa], and the elastic stiffness coefficients Sij [10 12 m 2 .N-1 ] values for Si and Ge.

		11	C 12	C 44	S 11	S 12	S 44
	Si	165.64	63.94	79.51	0.7691	-0.2142	1.2577
	Ge	128.7	47.7	66.7	0.9718	-0.2628	1.499

  .[START_REF] Jankovic | Performance evaluation of SiGe heterojunction bipolar transistors on virtual substrates[END_REF] Substituting equation (2.53) and equation (2.50) in equation (2.52), then the energy band structures are given by the following eigenvalue equation:

	2	+	e	.	e	. =	e	.
	Where
	|	= e	.					2.56

  intrinsic stress generated can be quantified by Stoney's equation by relating the stress to the

	substrate curvature as
	=	6(1	)	2.107
	where E Si	Si

are Young's modulus and Poisson's ratio of Silicon, h Si and h f are substrate and film thickness, and R is the radius of curvature of the substrate [33] [34].

Table 5 :

 5 Auger Recombination Coefficients of for Silicon.

Table 8 :

 8 The doping concentration and stress values generated inside Zone (I) (corresponds to Ge concentration = 7.6%, and x =0.364 um).

	Zone (II)	S xx [Pa]	S yy [Pa]	S zz [Pa]	Boron Active Con. [cm -3 ]
	With_Stress	-3.3417+9	-2.37776e+7	-3.34988e+9	2e+15 -5.2 e+19
	Without_Stress	-3.028e+9	2.32544e+6	-3.32093e+9	2e+15 -5.2 e+19

Table 9 :

 9

The doping concentration and stress values generated inside Zone (II) (corresponds to Ge concentration = 20.9%, and x =0.0265792 um).

Table 10 :

 10 Bandgap energy results obtained by BU for zone(I)

	Zone (I)	Eg_Analytical [eV]	Eg_EPM [eV]
	With_Stress	1.0251	0.988
	Without_Stress	1.0136	0.996
	Zone (II)	Eg_Analytical [eV]	Eg_EPM [eV]
	With_Stress	0.83	0.867
	Without_Stress	0.8189	0.8754

Table 11 :

 11 Bandgap energy results obtained by BU for zone(II)

Table 12 :

 12 Devices frequency characteristics results extracted for different V CB biases.

Table 13 :

 13 The extracted BV CEO values for both HBT devices.Simulation results show a very small reduction in the BV CEO value in the new HBT device's architecture in comparison with an equivalent standard conventional one (1% 4%).

	1 E -4
	1 E -5
	1 E -6
	1 E -7
	1 E -8
		dotted lines for H BT w ith stress solid lines for H BT w ithout stress		0.3N c 0.75Nc 1.5Nc	0.4N c 0.8Nc 2N c	0.5Nc 0.9N c 3Nc	0.65N c N c 4Nc
	1 E -9
	2 .0	2.1	2.2	2.3	2.4	2 .5	2 .6	2 .7	2 .8
					V CE [V olt]

  In addition to that, a trade-off between f T and f MAX values has been observed from f MAX versus f T plot for different collector doping level N C . An improvement up to 43% in f T value can be achieved for a given f MAX , and up to 7% of improvement in f MAX value for a given f T can be achieved by means of strain engineering, as well choosing the proper collector doping level

	HBT device.
	1 0	t e _ w ith o u t_ stress
		t e _ w ith _ stress
		t b _ w ith o u t_ stress
		t b _ w ith _ stress
	1	t c _ w ith o u t_ stress t c _ w ith _ stress
	0 .1
	Simulation results show that the strained silicon HBT device exhibits better high frequency characteristics in comparison with an equivalent standard conventional HBT device. An approximately, 8% of improvement in f T , and 5% of improvement in f MAX have been achieved for the new HBT architecture. The breakdown voltage BV CEO has been extracted for both devices for different collector doping 2 3 4 5 6 7 8 9 1 0 levels N 1 Jc [m A /cm 2 ]

C . The obtained results show a very small reduction in the BV CEO values for the strained

Fig.23: f T & f MAX vs. IC for BiCMOS9MW, B3T and B4T technologies at V CB = 0.5 V (L E ~5 m).

um Si 1-x Ge x Substrate

Philips Unified Mobility Model

The Philips unified mobility model proposed by Klaassen provides unified description of the majority and minority carrier bulk mobilities. In addition to describing the temperature dependence of the mobility, the model includes the effect of electron-hole scattering, screening of ionized impurities by charge carriers, and clustering of impurities. Because the carrier mobility is given as an analytical function of the donor, acceptor, electron and hole concentrations, and the temperature, this model is well suited for simulation purposes, and excellent agreement is obtained with published experimental data on Si.

The bulk carrier mobility for each carrier is given by Mathiessen's rule

3.35

The index i takes the values "e" for electrons and "h" for holes.

The first term in equation (3.35) represents phonon (lattice) scattering:

3.36

The second term in equation (3.35) accounts for all other bulk scattering mechanisms (due to free carriers, and ionized donors and acceptors): and adjacent to the intrinsic base of NPN-Si-BJT/NPN-SiGe-HBT device. The second approach is through introducing strain engineering technology principle at the device collector region by means of local strain technique using strain layers (Si 3 N 4 and SiO 2 strain layers).

The work methodology performed in this study consists of the following steps:

Virtually fabricate the device using process simulations.

Study the sensitivity of the device's different zones to strain.

Propose new methods to incorporate strain in the process and to evaluate the strain level that can be obtained inside the device.

Define simulation parameters and physical models (the model parameters have been calibrated in collaboration with Universität der Bundeswehr München).

Perform numerical (device) simulations to analyze the device electrical performance.

Process simulations were performed using Sentaurus TCAD software tools to virtually fabricate the device's structure, and to calculate the associated induced mechanical strain using anisotropic elasticity model. Sentaurus TCAD software tools were used to perform the two- Simulation results show that applying strain engineering concept at the base region of NPN-Si-BJT device using SiGe strain layer can strongly enhance the device's performance due to the sensitivity of silicon material to strain. An approximately 42% of improvement in f T , and 13% of improvement in f MAX have been achieved. As well, an enhancement of the collector current by

Future work

This work explores and investigates the impacts of mechanical strain engineering technology principle on Si bipolar and SiGe heterojunction bipolar devices using TCAD modeling (Process and device simulations). Although TCAD modeling gives a deep insight of the impact of mechanical strain on the devices performance, as well, provides the tool for designing and exploring new device concepts, it would be worth exploring the possibilities of fabricating new strained bipolar devices through a simplified device structure. This can be achieved by considering new device architectures that are based on less complicated fabrication process steps.

In addition to that, it would be beneficial to analyze the reliability issues for the proposed devices structures, such as self-heating effect and reliability issues associated with the materials used as stressors (oxide and nitride). Such a study could provide a complete set of information regarding the strained bipolar devices stability and the proper level of the applied strain.

Appendix

Mobility Models Calibration