Sophie Dupuy-Chessa

Yann Laurillau

Eric Céret

Considering Aesthetics and Usability Temporalities in a Model Based Development Process

Keywords: Utilisabilité, esthétique, conception, processus, modèle Usability, aesthetics, design, process, model ACM Classification H.5.m. Information interfaces and presentation (e.g., HCI): Miscellaneous. H5.2. User Interface: Graphical User Interfaces

L'ingénierie dirigée par les modèles offre des solutions pour créer interfaces utilisateurs, en particulier dans le cas d'interfaces complexes, comme celles adaptables à leur contexte d'usage. Cependant, ces interfaces souffrent d'une faible qualité. Cet article aborde ce problème en intégrant des étapes d'étude de l'esthétique et de l'utilisabilité dans un processus de développement basé sur les modèles, qui s'appuie sur le métamodèle M2FLex. M2Flex a été utilisé pour définir une version flexibilisée de la méthodologie UsiXML qui est dédiée à la conception et au développement d'interfaces adaptables. Des ajustements à la version flexibilisée de UsiXML sont proposés afin de prendre en compte les résultats d'une expérience qui montre que 1) l'esthétique perçue améliore l'évaluation des utilisateurs seulement lors de la phase d'exposition à l'interface ; 2) l'utilisabilité augmente les évaluations des utilisateurs après utilisation de l'interface.

INTRODUCTION

Model Driven Engineering (MDE) provides powerful solutions to tackle the design and the implementation of User Interfaces (UIs), opening possibilities such as more evolving and reusable systems [START_REF] Hamid | Designing Fault-Tolerant Component Based Applications with a Model Driven Approach[END_REF], greater quality, early detection of defects and inclusion of knowledge in executable models [START_REF] Mohagheghi | MDE Adoption in Industry: Challenges and Success Criteria[END_REF], and, carried to the extreme, dynamic adaptation to the context of use [START_REF] Calvary | A Unifying Reference Framework for the Development of Plastic User Interfaces[END_REF].

However, three main critiques are made to MDE. [START_REF] Resnick | Design Principles for Tools to Support Creative Thinking[END_REF] identifies a high threshold of use -the complexity to master models and transformations-, the lack of wide walls -the limited possibilities of exploring various solutions -and a low ceiling, which stands the poor quality of generated UIs. We focus here on this last issue. Model-based UIs are indeed known for offering low aesthetics and not considering enough usability questions.

If UI development processes integrate usability studies, they do not offer many elements dealing with aesthetics issues. However, the importance of aesthetics is recognized on the users' perceived ease of use [START_REF] Kurosu | Apparent usability vs. inherent usability: experimental analysis on the determinants of the apparent usability[END_REF][START_REF] Tractinsky | What is beautiful is usable[END_REF], on the overall impression [START_REF] Tractinsky | What is beautiful is usable[END_REF][START_REF] Schenkman | Aesthetics and preferences of web pages[END_REF] and on the appraisal of a system [START_REF] Mahlke | Studying antecedents of emotional experiences in interactive contexts[END_REF].

In this paper, we propose to consider altogether usability and aesthetics in a model-driven development process. We hypothesize that usability and aesthetics have a reciprocal [START_REF] Tractinsky | What is beautiful is usable[END_REF][START_REF] Angeli | Interaction, Usability and Aesthetics: What influences Users' Preferences[END_REF][START_REF] Sonderegger | The Influence of Aesthetics in Usability Testing: the Case of Dual-Domain Products[END_REF][START_REF] Tuch | Is beautiful really usable? Toward understanding the relation between usability, aesthetics, and affect in HCI[END_REF][START_REF] Hassenzahl | The inference of perceived usability from beauty[END_REF] and timely influence [START_REF] Bargas-Avila | Old wine in new bottles or novel challenges: a critical analysis of empirical studies of user experience[END_REF][START_REF] Hassenzahl | The interplay of beauty, goodness, and usability in interactive products[END_REF]. So to identify when studying each aspect, we conduct a large-scale experiment on the impact of each one on the user's experience. In this experiment, aesthetics and usability are treated as independent variables so as to make it possible to establish the chronology of their influence on the user independently of their reciprocal influence. Our main finding suggests starting UI designs by aesthetics before introducing usability aspects: it sheds a new light on the way to consider UI design processes. Thus, we draw first implications upon this finding to improve user experience at different steps of a UI design process.

The second section of the paper presents the state of the art about human-computer interaction design processes and aesthetics impact. The third and main section presents the development process, which will be extended with aesthetics and usability steps. Next we present and detail an experimental study to understand the impact of usability and aesthetics over time. Then we propose an extension of our process. Finally, the last section concludes and opens on perspectives.

STATE OF THE ART

User interface development processes are usually focused on usability aspect. They are based on iterative cycles, which allow designers to refine mock-ups or final UIs so as to obtain usable UIs [START_REF] Nielsen | Iterative User-Interface Design[END_REF][START_REF] Mayhew | The usability engineering lifecycle[END_REF]. These processes use techniques such as participatory design [START_REF] Muller | Participatory design: the third space in HCI. The human-computer interaction handbook[END_REF] or scenarios [START_REF] Hertzum | Making use of scenarios: a field study of conceptual design[END_REF] to consider the user's point of view. For instance, with the worth based design approach, [START_REF] Cockton | Value-centered HCI[END_REF] introduces design principles that are more general than usability. However, the authors recommend starting the development process by identifying the value that the system has to offer and ending it with value measurement. Their approach remains principle-based without direct recommendation for UI design. UI development processes don't offer many elements dealing with aesthetics issues, even if some of them offer large parts about usability. For instance, the Rational Unified Process RUP [START_REF] Kruchten | The Rational Unified Process: An Introduction[END_REF] only mentions that the software architect is "concerned with" aesthetics issue, whilst it insists several times on usability issues. The Diane+ method [START_REF] Tarby | The DIANE+ Method[END_REF] makes it explicit that usability relies on ergonomics elements but also doesn't mention aesthetics. Model-based approaches, such as MACAO [START_REF] Crampes | Méthode Orientée-objet intégrale MACAO : démarche participative pour l'analyse, la conception et la réalisation de logiciels[END_REF], Teallach [START_REF] Griffiths | Teallach: a model-based user interface development environment for object databases[END_REF] or UsiXML [START_REF]UsiXML Method Specification[END_REF] offer detailed processes for creating the needed models and developing or generating the UIs, but do not focus on usability and aesthetics issues even if MACAO refers to generic software quality criteria from [START_REF]Software Engineering -Product Quality -Part 1: Quality Model[END_REF], which includes for instance the ease of use.

In the field of industrial design (which relates to the design of objects not excusively of the UIs), [START_REF] Wagner | Method for Aesthetics Design Improvement[END_REF] focuses on improving aesthetics during design and states that it has a "relatively strong influence on the success of the product on the market". This paper presents an iterative approach for dealing with aesthetics issues. It recommends defining aesthetics criteria, assessing products against them and identifying new concepts from this evaluation. Authors exemplify their method with criteria such as "Harmony between subsystems", "Compactness", "Desired style", "Minimisation of the number of different forms". Even if this works relates to another domain and does not deal with usability issues, the recommendations show the relevance of aesthetics in a development process.

In guidance made of recommendations, several guides or approaches mentioned aesthetics. User-Centred Design [START_REF] Maguire | Methods to support humancentred design[END_REF][START_REF] Gulliksen | Key Principles for User-Centred Systems Design[END_REF] offers guidelines for designing UIs while including users in the process. They insist on increasing usability thanks to iterative, incremental development and user's evaluation, but they give no recommendation about aesthetics. Moreover, these works offer principles and techniques that are not included in a development process or more precisely, as [START_REF] Seffah | Avoiding the usability pitfalls involved in managing the software development life cycle[END_REF] says, are "decoupled from the software development lifecycle". In a more practical way, some guides such as [START_REF] Stone | User Interface Design and Evaluation (1rst Edition)[END_REF][START_REF] Galitz | The essential guide to user interface design: an introduction to GUI design principles and techniques[END_REF] mention visual aesthetics because of its impact on usability. But their recommendations are not included in a process. Some UI design guides, such as [START_REF] Lauesen | User interface design: a software engineering perspective[END_REF], exclude the question of aesthetics, considering this is not very important.

From the related works, we can note that 1) even if users are consulted during processes, the focus is on usability and aesthetics is only lightly discussed (at best); 2) some recommendations exist about aesthetics but none of them is integrated into a UI development process.

So our contribution is to propose steps to consider altogether aesthetics and usability during a model-based process. The next section describes the process that we will extend.

THE DEVELOPMENT PROCESS TO EXTEND

In [START_REF] Céret | M2Flex: a process metamodel for flexibility at runtime[END_REF], M2Flex is a metamodel for creating flexible process models, i.e. processes that can be adapted to the project's situation (goals, constraints, team competencies and knowledge…). This metamodel is used in [START_REF] Céret | Flexibilité des processus de développement à la conception et à l'exécution : application à la plasticité des Interfaces Homme-Machine[END_REF], to define a "flexibilized" version of the UsiXML methodology [START_REF]UsiXML Method Specification[END_REF], which is dedicated to the design and development of adaptable UIs. As recommended in the Cameleon reference framework [START_REF] Calvary | A Unifying Reference Framework for the Development of Plastic User Interfaces[END_REF], the process (Fig. 1) is based on four kinds of models: Tasks, Domain, Abstract User Interface (AUI), Concrete User Interface" (CUI). Different strategies are proposed allowing designers not to create all models.

Figure 1 shows this flexibilized process model, with various strategies (1) connecting goals (2) and reified into more or less detailed activities (3), with the used (4) and produced (5) artefacts. Despite its huge ability to adapt to its users and their project, this process model remains perfectible, as it offers only guidance for creating models and transforming them into other models. There is no mention about ergonomics, even if it is awaited to be taken into account in an UI development. We thus want to complete this process by including recommendations for increasing the quality of the generated UIs, particularly on aesthetics and usability.

The way users estimate aesthetics and usability differently -that will in turn influence the stages considering these questions in the development process -has already been stated by [START_REF] Diefenbach | The "Beauty Dilemma: beauty is valued but discounted in product choice[END_REF], which shows that if people appreciate beauty, they don't want it to increase the cost of the product nor reduce its usability. Aesthetics must then be a bonus on the top of a usable UI. From the designers' point of view, it is also a key factor of success [START_REF] Tractinsky | What is beautiful is usable[END_REF][START_REF] Steenkamp | How Country Characteristics Affect the Perceived Value of Web Sites[END_REF][START_REF] Chan | Usability for Mobile Commerce Across Multiple Form Factors[END_REF]. But for dealing with aesthetics and usability that might be opposite to each other without increasing drastically the cost, engineers need to be guided. To be able to guide them, we first need to understand when aesthetics and usability impact users' experience to know when each of them has to be studied during the process. So we start by realizing an experience, which hypotheses that the two aspects are not taken into account at the same time by users. The experiment we drove for verifying this hypothesis is presented in the following section.

EXPERIMENTAL STUDY

Goals and hypotheses

The experiment examines how the users' experience (pleasantness, playfulness, and perceived value) differs depending on usability and aesthetics and how it evolves. Several studies about the use of interactive products show that these three dependant variables (pleasantness, playfulness, and perceived value) are the most relevant. These works show that the use of technological products induces affective responses (e.g., [START_REF] Mick | Paradoxes of Technology: Consumer Cognizance, Emotions, and Coping Strategies[END_REF][START_REF] Wood | From Fear to Loathing? How Emotion Influences the Evaluation and Early Use of Innovations[END_REF]). The fun aspect of using user interfaces and its impact on UI's worth have been highlighted by several studies in different fields of research. For instance, about technological acceptance models, [START_REF] Venkatesh | Determinants of Perceived Ease of Use: Integrating Control, Intrinsic Motivation, and Emotion into the Technology Acceptance Model[END_REF] shows that playfulness positively impacts satisfaction while interacting. The positive aspect of such variable appears in several works such as modeling user experience on Internet (e.g., [START_REF] Novak | Measuring the Customer Experience in Online Environments: A Structural Modeling Approach[END_REF]) or using mobile phones [START_REF] Lee | Designing an electronic commerce interface: attention and product memory as elicited by web design[END_REF]. Similarly, works done in the information system research field (e.g. [START_REF] Sutanto | Addressing the Personalization-privacy Paradox: An Empirical Assessment from a Field Experiment on Smartphone Users[END_REF]), underline the importance of pleasantness while interacting with a system. Finally, perceived value is also a key aspect of user experience while using user interfaces: a broad range of works from HCI, information system and marketing research fields states it (e.g., [START_REF] Marbach | Who are you and what do you value? Investigating the role of personality traits and customerperceived value in online customer engagement[END_REF]).

In collaboration with marketing researchers, we conducted a large-scale experiment [START_REF] Jeannot | A Crossed Influence of Usability and Aesthetics on Interactive Device Evaluation: Studying Exposure versus Use Effects[END_REF]. We examine the users' evaluation of their experience over time at two consecutive stages:

• Exposure (first stage): interface experience based on three tasks based on visual inspection of the web sites, without user interaction;

• Use (second stage): interface experience based on three tasks implying user interaction with the web sites.

We suggest that the role of interface aesthetics and usability should vary depending on the users' experience stage.

So the hypotheses are:

• H1: After the exposure stage, high (vs. low) interface aesthetics imply a higher (vs. lower) (a) pleasantness, (b) playfulness, and (c) perceived value of the interactive device.

• H2: After the exposure stage, the interface usability has no impact on (a) pleasantness, (b) playfulness, and (c) perceived value of the interactive device. • H3: After the use stage, high (vs. low) interface aesthetics has no impact on the different scores of (a) pleasantness, (b) playfulness, and (c) perceived value of the experience.

• H4: After the use stage, high (vs. low) interface usability implies a higher (vs. lower) (a) pleasantness, (b) playfulness, and (c) perceived value of the interactive device.

Experimental Method

The two-stages study asked participants to evaluate a travel website thanks to a questionnaire. The first stage (exposure) consisted in asking participants to evaluate it based on a visual inspection of the web sites, without user interaction. During the second stage (use), participants had to evaluate the same travel website after having manipulated it through user interaction.

Versions of a same travel website were designed and developed according to two factors: high (vs. low) usability, and high (vs. low) aesthetics. So by combining these 2 values (low vs. high) for our two variables (aesthetics and usability), four versions of the website are created (Fig. 2).

Procedure and Tasks

In the first stage (exposure), in order to evaluate one assigned version of the four websites, the participants had to achieve three tasks, that just require to browse the website, related to three questions they had to answer to:

1. Which country does the travel agency promote?

2. What is the name of the first hotel that you can see on the travel agency's website?

3. What activity does the online travel agency offer?

We provided multiple choices answers for each question, with only one correct option.

In the second stage (use), the participants interacted with one website user interface and then answered questions. They were given three tasks to achieve. For instance, one of the tasks consists in searching for a 5stars hotel that offers a visit in the desert. While using the web-based user interface, they were asked to achieve four tasks related to the following questions:

1. How many 5-stars hotels offer a visit in the desert?

2. What is the name of the hotel that you found?

3. What city is this hotel located in? 65: in answer to the statement "I am familiar with travel websites"; from 1 "do not agree at all" to 7 "totally agree").

UI designs and apparatus

The study used mock travel agency's websites. The participants were asked to navigate one website to plan a hypothetical visit to Morocco, and they were then asked to evaluate the website. The participants were offered different options, such as various types of stay, hotels categories, cities, hotels comparison, activities, and types of package.

The four designs of the travel website were created by a website designer/developer (figure 2). To create these designs, basic functionalities and minimal user interaction were first specified through the generation of a task model and user interface mock-ups. As recommended by Tuch et al. [START_REF] Tuch | Is beautiful really usable? Toward understanding the relation between usability, aesthetics, and affect in HCI[END_REF], we manipulated-as independently as possible-the aesthetics and the usability of the website user interface. In order to verify the manipulations of aesthetics factors (high vs low) and usability factors (high vs low), a pretest has been driven with 58 students. Participants were exposed to the four UIs and evaluated their aesthetics and usability. Two scores for differences in average have been computed: one for low and one for high levels for aesthetics (M diff_aesth ) and for usability (M diff_usab ).

Results show a statistically significant difference in the averages of high and low aesthetics (t(57)=15. Thus, usability was first considered at the task level (i.e. interaction distance and workload) as well as in terms of concrete user interface. For the low usable version, the concrete user interface level was redesigned for increasing the workload, i.e. by using the navigational factors related to the ease of information access (interaction distance, additional unnecessary articulatory subtasks). For instance, as shown in figure 3, the list of hotels can be filtered using filtering criteria (left side of the user interface): the low usable version presents one criterion (vs. all criteria) at a time through a dynamic menu. Another example, some navigation elements were removed such as redundant hyperlinks.

To create a high vs. low interface-aesthetics, only the graphic factors were manipulated. As shown in figure 4, this included the background colour (bright vs. light), the framework shape (square vs. round), and the formatting (non-aligned vs. aligned) as studied in [START_REF] Minge | Dynamics of User Experience[END_REF].

The four designs were included in the online survey thanks to Qualtrics' online application. It allows completing the survey while navigating the travel web site within a single web page.

Study design: survey and measures

The experiment used a three-factor mixed design. The between-subject independent variables were the interface usability with two levels (low and high), and the interface aesthetics with two levels (low and high). The within-subject independent variable was the user experience that includes two stages (exposure and use).

During the first stage (exposure), participants answered questions related to the tasks to achieve as well their exposure experience (pleasantness, playfulness, and perceived value).

During the second stage (use), after completing the three tasks, the participants answered questions similar to stage one about their use experience (pleasantness, playfulness, and perceived value). The participants answered additional questions relating to the manipulation (usability and aesthetics), and answered some profile questions (age, gender, and familiarity with travel websites). Thus, the four different versions are designed to operationalise the independent variables.

For measuring the participants' experience, the survey included several seven-point scale-based questions (e.g. 1="strongly disagree" and 7="strongly agree"):

• Pleasantness: two items adapted from [START_REF] Venkatesh | Determinants of Perceived Ease of Use: Integrating Control, Intrinsic Motivation, and Emotion into the Technology Acceptance Model[END_REF]: "this website is pleasant to use"; and "this website is nice to use".

• Playfulness: three items adapted from [START_REF] Venkatesh | Determinants of Perceived Ease of Use: Integrating Control, Intrinsic Motivation, and Emotion into the Technology Acceptance Model[END_REF]: "this website is fun"; "this website is playful"; and "this website encourages a good mood".

• Perceived value: six items adapted from [START_REF] Steenkamp | How Country Characteristics Affect the Perceived Value of Web Sites[END_REF]: "overall, I think it is worth visiting this website"; "this website is useful"; "this website meets my expectations"; "visiting this website should be a good experience"; "this website one that I can trust"; and "I believed the information provided by this website".

To ascertain the reliability of these measures, correlation calculations (Pearson and Cronbach's alpha) were achieved after each stage for each measure: it shows a very high correlation (over 0.927 at least with p <0.001) between items. As the scale properties were satisfactory, we created an average index for the three dependent variables (pleasantness, playfulness, and perceived value) at both the exposure and use stages to test our hypotheses.

Therefore, to test the exposure effect, we focused on the means of the indices relating to the website evaluations.

To test the use effect, we compared the individual participants' website evaluations after the use stage with their evaluations at the exposure stage. We calculated a difference score for the use stage evaluations and for the exposure stage evaluations for the three dependent variables. This difference score estimates the improvement or the deterioration of the website evaluations (pleasantness, playfulness, and perceived value) due to the users' experience with the web site user interface.

To ascertain whether the high-(vs. low-) aesthetics/usability website led to higher (vs. lower) perceived aesthetics/usability, the participants assessed the perceived aesthetics and usability of the website. Therefore, to measure perceived usability and perceived aesthetics, we used respectively a four-item seven-point scale and a three-item seven-point scale, both adapted from [START_REF] Lee | Consumer responses to high-technology products: Product attributes, cognition, and emotions[END_REF]:

• Perceived usability: "this website allows information to be quickly found"; "this website does not need specific effort to find information"; "this website offers easy navigation"; and "this website offers a clear and understandable experience". Perceived aesthetics: "this website is visually attractive"; "this website is beautiful"; and "this website has an attractive design".

To ascertain the reliability of the measures, correlation calculations (Cronbach's alpha) were achieved after use stage for both measures: it shows a very high correlation (respectively 0.970 and 0.967 with p <0.001) between items.

As the reliability results were satisfactory, we computed two indices (average index) to test whether the perception of aesthetics and of usability respectively differ on the two factors: aesthetics (high vs. low) and usability (high vs. low).

Results

Perceived usability and aesthetics in line with the UI designs

The results confirm that UI usability impacts significantly and positively the perceived usability: ANOVA showed (F 1,201 =7.22 p=0.0078) that a website showing a high usability is perceived as easier to use than a website showing a low usability. Similarly, aesthetics impacts significantly and positively on the perceived aesthetics: ANOVA showed (F 1,201 =7.22 p=0.0078) that a website showing a high aesthetics is perceived as more appealing than a website showing a low aesthetics.

In the following, tables 1 and 2 show the results in tabular form and Figure 5 shows the results in graph form.

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IHM'16: Ingénierie de l'interaction homme-machine 25-28 oct. 2016, Fribourg, Suisse

Exposure stage: aesthetics comes first

The results emphasize that, after an exposure to the website display, a high aesthetic user interface provides a higher website evaluation than a low aesthetic user interface; however, user interface usability does not increase website evaluation at this stage.

Indeed, to test our hypotheses (H1 and H2), we computed two-sample t-tests (see Table 1, degrees of freedom=201) to test the impact of usability and aesthetics on the three dependent variables (pleasantness, playfulness, and perceived value).

As shown in Figure 5 (see Graph 1a), the pleasantness results show that aesthetics has a statistically significant positive impact on the perceived pleasantness of the website (p=0.046). However, usability has no significant impact (p=0.346). As shown in Figure 5 (see Graph 1b), the playfulness results similarly show that aesthetics has a statistically significant positive impact on the perceived playfulness of the website (p<0.001). However, usability has no significant impact (p=0.091).

As shown in Figure 5 (see Graph 1c), the perceived value results show that only aesthetics has a statistically significant positive impact on the perceived value of the website (p=0.007). However, usability has no significant impact (p=0.567).

Use stage: usability effect

The results emphasize that, comparing the exposure stage to the use stage, a high user interface usability improves website evaluation, whereas a low interface usability reduces website evaluation. The results show that the user interface aesthetics does not modify the website evaluation relating to use.

Indeed, to test our hypothesis (H3 and H4), we computed two-sample t-tests (see Table 2, degrees of freedom=201) to test the impact of usability and aesthetics on the three different scores (pleasantness, playfulness, and perceived value).

As shown in figure 5 (see Graph 2a), the pleasantness difference score (percentage) results show that aesthetics has no statistically significant impact on the website pleasantness difference score (p=0.433).

However, usability has a statistically significant and positive impact on the website pleasantness difference score (p=0.008).

As shown in figure 5 (see Graph 2b), the playfulness difference score (percentage) results similarly show that aesthetics has no statistically significant impact on the website playfulness difference score (p=0.336).

However, usability has a statistically significant and positive impact on the website playfulness difference score (p<0.001).

As shown in figure 5 (see Graph 2c), the perceived value difference score (percentage) result again shows that aesthetics has no statistically significant impact on the website perceived value difference score (p=0.223).

Only usability has a statistically significant and positive impact on the website perceived value difference score (p=0.041). Regarding UIs aesthetics, the results show that it only impacts the participants' evaluation at the exposure stage -when the users have to look for information through visual inspection of the web sites. In contrast, aesthetics do not influence the participants' evaluation at the use stage -when the users have to look for information based on their interaction with the website. Regarding user interface usability, the results show that usability does not influence the participants' evaluation when the users visually inspect the website (exposure stage). However, user interface usability improves the participants' evaluation when the users actually experience the website (use stage) through user interaction. In other words, user interface aesthetics only improves a user's evaluation of an interface after a mere exposure, whereas user interface usability only increases a user's evaluation after a use experience.

Thus, this experiment confirms that usability and aesthetics have a timely influence. Users are more impacted by aesthetics during the exposure stage, e.g. when they discover the application. This temporality can be taken into account by designers and developers. We therefore state a first recommendation that during a user interface design process, at early stage, designers should first study and propose the UIs aesthetics, and in a second phase focus on usability. Figure 6 shows the (end of the) resulting flexible process model after including the goals, strategies and activities corresponding to our experiment's results. Goals for exploring (1) aesthetics and evaluating it (2), as well as exploring usability (3) and evaluating it (4), have been added. The corresponding strategies have been included. As we need the process model to remain as flexible as possible, strategies [START_REF] Chan | Usability for Mobile Commerce Across Multiple Form Factors[END_REF][START_REF] Cockton | Value-centered HCI[END_REF] have also been redefined for making it possible to deliver the software without having to consider aesthetics and usability. For similar reasons, we also added a strategy for considering aesthetics but not usability [START_REF] Crampes | Méthode Orientée-objet intégrale MACAO : démarche participative pour l'analyse, la conception et la réalisation de logiciels[END_REF] or usability only [START_REF] Angeli | Interaction, Usability and Aesthetics: What influences Users' Preferences[END_REF]. As UI development is an iterative process, strategy (9) makes it possible to refine the aesthetics and usability elaboration by returning to the Concrete UI production, earlier stages being accessible from there. Dotted lines [START_REF] Chan | Usability for Mobile Commerce Across Multiple Form Factors[END_REF][START_REF] Cockton | Value-centered HCI[END_REF][START_REF] Crampes | Méthode Orientée-objet intégrale MACAO : démarche participative pour l'analyse, la conception et la réalisation de logiciels[END_REF] signify that, although these strategies exist and make it possible to avoid aesthetics and usability considerations, we do not recommend enacting them.

As a complement to the impact on process models, we also draw a recommendation that is, while conducting usability evaluations and testing phases, aesthetics has to be tackled first as it might have a bias effect on the results.

CONCLUSION AND PERSPECTIVES

This paper presents a step towards integrating aesthetics and usability in a model based UI development process. An experiment shows the temporal influence of aesthetics and usability: it advocates for considering aesthetics before usability in a UI development process. So we extend a model based process to include aesthetics and usability study steps. To strengthen these results, the experiment is currently extended with additional web sites. This will allow us to refine the aesthetics step. Moreover, other aspects of user experience can be studied, such as trust or perception of innovations. Their impact on the quality perceived by users must also be considered while designing a UI. Finally, we also will drive an experiment for evaluating if the proposed UI design process increases users' and designers' satisfaction.

Figure 1 -

 1 Figure 1 -UsiXML flexibilized process model according to the metamodel M2Flex

4 .Figure 2 :

 42 Figure 2: Four versions of a web site user interface: usability x aesthetics

Figure 3 :

 3 Figure 3: Filtering criterion: expanded list (left: high usability) vs. cumbersome dynamic menu (right: low usability).Figure 4: high (top) vs. low (bottom) interface-aesthetic.

Figure 4 :

 4 Figure 3: Filtering criterion: expanded list (left: high usability) vs. cumbersome dynamic menu (right: low usability).Figure 4: high (top) vs. low (bottom) interface-aesthetic.

GRAPH 1 :Figure 5 :

 15 Figure 5: Exposure effect results (GRAPH1: 1a, 1b, 1c) and use effect results (GRAPH2: 2a, 2b, 2c)

Figure 6 -

 6 Figure 6 -UsiXML flexibilized process model including aesthetics and usability considerations

Table 1 : Results of two sample t-tests after exposure stage

 1

			Mean	Std. dev.	t 201 (t-test)	p value
	Pleasantness	Low aesthetics High aesthetics Low usability High usability	4.18 4.55 4.46 4.49	1.41 1.17 1.23 1.37	2.00 0.944	0.046 0.346
	Playfulness	Low aesthetics High aesthetics Low usability High usability	4.52 5.09 4.95 4.67	1.33 0.97 0.98 1.35	3.482 1.695	< 0.001 0.091
	Perceived value	Low aesthetics High aesthetics Low usability High usability	4.52 4.93 4.77 4.68	1.23 0.93 0.95 1.23	2.700 0.567	0.007 0.567

Table 2 : Results of two sample t-tests after use stage

 2

			Mean	Std. dev.	t 201 (t-test)	p value
	Pleasantness	Low aesthetics High aesthetics Low usability High usability	-1.00% 10.35% -14.81% 23.39%	97.1% 109.0% 107.5% 95.8%	-0.784 2.667	0.433 0.008
	Playfulness	Low aesthetics High aesthetics Low usability High usability	1,49% -13.59% -33.84% 20.19%	98.4% 123.5% 125.2% 90.6%	-0.963 3.506	0.336 < 0.001
	Perceived value	Low aesthetics High aesthetics Low usability High usability	-3.55% -19.57% -25.41% 1.28%	88,5% 97.0% 103.6% 80.0%	-1.221 2.046	0.223 0.041

IHM'16: Ingénierie de l'interaction homme-machine 25-28 oct. 2016, Fribourg, Suisse

IHM'16: Ingénierie de l'interaction homme-machine

ACKNOWLEDGMENTS

Realised in collaboration with the CERAG laboratory, this work has been funded by the UPMF University and the INNOVACS research federation. Thanks are also due to our marketing colleagues: Maud Damperat, Florence Jeannot, Eline Jongmans and Alain Jolibert.


Touba
email: touba@ece.utexas.edu

Sreenivaas S Muthyala
email: sreenivaas@utexas.edu

Nur A Touba

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Keywords: 3D-IC, Testing, TSVs, Test Compression, Serialization

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Introduction

Three-dimensional Integrated Circuits (3D-ICs) are stacked devices with low latency interconnections between adjacent dies, resulting in reduced power consumption in interconnects and higher bandwidth for communication across layers [Hamdioui 11]. 3D-IC designs are suitable for fabricating chips containing heterogeneous components like analog, digital, mixed signal, flash, DRAM components, which is usually the case in System-on-Chip designs. The different layers in a 3D-IC are connected using through-silicon-vias (TSVs) which are vertical interconnects across layers. There are different ways of stacking the dies, wafer-to-wafer (W2W), die-to-wafer (D2W) or die-to-die (D2D), each having its own set of pros and cons, described in [Patti 06].

3D-IC testing is more challenging than 2D-IC testing, since the components of the system are distributed across different layers and, as mentioned earlier, can have nondigital components. In addition, the dies comprising the different layers can be synthesizable designs (soft cores), in which the design-for-test (DFT) architecture can be customized. The designs can also be layouts (hard cores) for which the DFT architecture is already fixed. It can also contain IP cores, in which it is possible to perform test pattern generation to obtain test patterns that are applied during test. Another challenge in 3D-IC testing is that the input tester channels from the automatic test equipment (ATE), i.e. the external tester, is fed only to the bottom layer in the 3D-IC, and to transfer the test data to the non-bottom layers, TSVs are used, like how the functional data is transferred. These TSVs used for testing purposes are also called test elevators [Marinissen 10]. This further constrains testing, the number of tester channels required for the non-bottom layers should be accommodated within the available number of TSVs, which is a challenge in hierarchical designs with numerous cores. Apart from these, it is also necessary to test the TSVs, since they are prone to defects such as insufficiently filled TSVs, development of micro-voids in the copper filling, and cracking, which is a result of having different coefficient of thermal expansion [Marinissen 09].

There are several stages in testing 3D-ICs; pre-bond testing is performed on each die individually, to ensure defective dies are not used in stacking and then post-bond testing is performed on the final stack, to ensure the 3D-IC as a whole is not defective. In some cases, testing is also done on partial stacks. In order to do pre-bond testing on the non-bottom layers, it is necessary to add probe pads for test purposes. This is because the TSV tips as well as the microbumps are too small to be probed and are very sensitive to scrub marks [Marinissen 09]. These probe pads are a test overhead that take up a lot of space and limit the locations where TSVs can be placed, which puts constraints on the design and floorplan of a die.

One important way to reduce test time is by test compression [Touba 06]. The conventional way of implementing test compression in core-based schemes is for each core to have its own local decompressor. This allows compressed test data to be brought over the Test Access Mechanism (TAM) lines to each decompressor in each core. In a 3D-IC, if a decompressor is shared across multiple cores that are in different layers, larger TAMs would be required, greatly increasing the routing complexity. In addition, this will also increase the number of test elevators required to transfer the uncompressed test data to the non-bottom layers, which is not desirable.

The existing methods for dynamically adjusting the number of free variables sent to each decompressor have the drawback that they increase the amount of routing (i.e. TAM width) required between the tester channels and the core decompressors. This is less suited for 3D-ICs because routing between layers requires additional test elevators (i.e., extra TSVs). This paper proposes a new architecture and methodology for test compression in core-based designs, which is better suited for 3D-ICs. It can be used to either provide greater compression for the same number of test elevators or reduce the number of test elevators while maintaining the same compression compared to existing methods.

This paper proposes a simple, elegant and scalable test compression architecture that reduces the required number of tester channels by sharing tester data amongst the different layers, which in turn, can be accommodated by using very few test elevators. In addition, further reduction in the number of test elevators can be obtained by using "Inter-layer serialization", a simple technique to send data serially across layers. Preliminary results were presented in [Muthyala 14].

Related Work

Testing a core based design typically involves designing wrappers around the cores, providing a test access mechanism, which transfers test data from the pins of the tester to the cores, and developing a test schedule, which decides the sequence in which the cores are tested, the set of cores that are tested concurrently and so on. There are several techniques to design wrappers, TAMs and test schedules, see [Xu 05] for a survey.

In the 3D-IC paradigm, an early work addressing the testability issues of 3D-ICs uses the concept of "scan island" for pre-bond testing [Lewis 09], which uses IEEE standards 1500 and 1149.1 to design wrappers for pre-bond testing. [Wu 07] proposes different optimization strategies for the number of scan chains and the length of TSV based interconnects for 3D-ICs. Heuristic methods for designing core wrappers is proposed in [Noia 09], however it does not involve the reuse of die level TAMs [Noia 10]. [Jiang 09] proposes using heuristics to reduce weighted test cost, while taking into account constraints on the widths of test pins for both pre-bond and post-bond testing. However, the above methods involve die-level optimization of TAMs. [Jiang 09] addresses TAM optimization for post bond testing by placing a constraint on the number of extra probe pads for pre-bond testing when compared to the post bond testing. [Lo 10] proposes reusing the test wrappers of individual cores embedded in the 3D-IC, for test optimization. Recently, the optimization procedures for minimizing test time under a constraint on the number of test elevators has been proposed in [Wu 08] and [Noia 10]. A feature of 3D-IC testing is that the number of probe pads on the non-bottom layers (which are added for test purposes, as explained in Sec. 1) is very limited, which results in limited bandwidth available from the tester for pre-bond testing. [ Jiang 12] proposes having separate TAMs for pre-bond testing and post-bond testing. [Lee 13] uses a single TAM with a bandwidth adapter to manage bandwidth for pre-bond and post-bond testing. However, all the above works target test time reduction by optimization of test architectures.

Some recent work has looked at ways to improve encoding efficiency by dynamically adjusting the number of free variables sent to the decompressor in each core on a per test cube basis to try to better match the number of free variables sent to the decompressor with the number of care bits. This can be done by dynamically allocating the number of tester channels used to feed each decompressor [Janicki 12] or by selectively loading decompressors in each clock cycle [Kinsman 10], [Muthyala 13]. [Larsson 08] presents selective encoding of test data for testing SOCs using codewords to represent the care bit profile of the test cubes. The conventional approach is to have independent decompressors for each core such that each of them has their own set of free variables so that the linear equations for each decompressor can be solved independently. This helps to reduce computational complexity. The drawback is that the unused free variables are wasted when the decompressor is reset be-tween test cubes. This happens in all of the existing methods except [Muthyala 13], which allows limited sharing of free variables between decompressors during a few cycles in such a way that the linear equations are mostly independent and can be solved with only a small increase in computational complexity.

In conventional testing, the scan shift frequency is typically much slower than the functional clock frequency and the maximum ATE (automatic test equipment) clock frequency, due to power dissipation limitations as well as the fact that the test clock may not be buffered and optimized for high speed operation. In [Khoche 02], the ATE shifts in test data n times faster than the scan shift. An n-bit serial-to-parallel converter is used to take in serial data at the fast ATE shift rate and convert it to n-bits in parallel at the slower scan shift frequency. This allows a single ATE channel to fill n scan chains in parallel. This idea was combined with a test compression scheme in [Wang 05], where faster ATE channels are sent to a time division demultiplexing (TDDM) circuit which feeds the inputs of a VirtualScan decompressor [Wang 04], and the compacted output response is fed through a time division multiplexing (TDM) circuit to go to the ATE. This paper proposes using a similar concept for test elevators when transferring test data from one layer to another layer in a 3D stack. The idea is to use a serializer in the layer sending the test data that accepts data in parallel at the scan shift frequency, and generates a serial output at the functional clock frequency which is sent over the test elevator to a deserializer on the receiving layer which converts the serial data coming in at the functional clock frequency into parallel outputs at the scan shift frequency. This approach is described in detail in Sec. 5.

Sequential Linear Decompression

Sequential linear decompressors are a major class of decompressors used for test compression, and are inherently attractive while encoding test cubes, i.e. test vectors with unassigned inputs represented as don't cares. The compressed test data, which is stored on the external tester (Automatic Test Equipment, ATE), is obtained using a two-step procedure as follows:

1. The test patterns applied to the scan cells are obtained from automatic test pattern generation (ATPG). 2. Since the decompressor architecture is known, the test patterns can be encoded to determine the compressed tester data.

Fig. 1 shows an example of how the tester data is obtained by encoding using a 4bit linear feedback shift register (LFSR) as the decompressor. To encode the test patterns, the tester data coming from the external tester are considered free variables and the dependence of scan cells on these free variables is obtained using symbolic simulation, which gives the linear equations for the free variable dependence of each scan cell. These equations are solved for each test pattern (Z in Fig. 2) by assigning values to the free variables, making them pivots (free variables that are not assigned any value are called non-pivots). These values of free variables (both pivots and non-pivots) constitute the tester data is stored on the tester to obtain the test pattern in the scan cells.

Fig. 1. Example of Symbolic Simulation of Sequential Linear Decompressor

More details about this procedure can be found in [Könemann 91], [Krishna 01] and [Wang 06], which is used in Mentor Graphics' TestKompress tool [Rajski 04]. An important thing to notice is that the LFSR that is fed by the free variables is reset to zero after decompressing each test cube, to keep the complexity of solving equations within manageable limits. This means that the non-pivot free variables, which are not required to have any value to solve the equations, are not used and simply thrown away. This source of inefficiency in compression has been dealt with in several previous works.

The amount of compression achieved with sequential linear decompressors depends on the encoding efficiency, defined as the ratio of the number of free variables (bits stored on the tester) versus the number of care bits in the test data. The encoding efficiency achieved using the conventional approach of having fixed size TAMs feeding multiple independent core decompressors is limited by the fact that the TAM bandwidth to each core decompressor needs to be large enough to bring enough free variables to encode the worst-case test cube with the largest number of care bits. To maximize encoding efficiency, a special ATPG procedure is used to generate test cubes in a way that limits the number of care bits in each test cube. This typically comes at the cost of more test cubes being generated. Moreover, there can still be a considerable amount of variance in the number of care bits per test cube (profiles for industrial circuits showing how the percentage of care bits varies can be found in [ Janicki 12]). The inherent drawback of the conventional approach is that the number of free variables brought in for decompressing each test cube is fixed by the worstcase test cube with the most care bits, and so, many free variables are wasted for test cubes with fewer care bits. Several improvements to the encoding procedure for sequential linear decompressors have been proposed, including reusing unused free variables [ Muthyala 12]. In addition, a test scheduling procedure for hierarchical SoC based designs was proposed in [Muthyala 13], which enables free variable reuse.

To implement test compression in a core-based 3D-IC, it is necessary to design Test Access Mechanisms (TAMs) for each core. The IEEE 1500 standard, which was introduced to address the challenges in SoC testing, would be a very suitable solution for 3D-IC testing. In addition, the provision of a test wrapper, which standardizes the test interface, further tilts the scales towards the IEEE 1500 standard for 3D-IC testing, since the same interface can be used for pre-bond and post-bond testing. However, the implementation of a test wrapper should also consider the fact that the number of test elevators used for testing should be minimized. There are several ways to design the connection between the test wrappers of each core, one of them, similar to the one shown in Fig. 3, is used in the test architecture proposed in this paper. Fig. 3. Test Architecture for a 3D-IC with Wrappers for Each Core However, it is not necessary to design wrappers in the way shown in Fig. 3; several other ways of designing core wrappers are possible, any design can be selected based on the need. Another application for wrappers is for bypassing cores that cannot be tested in tandem with other cores. For instance, if analog cores are present, the test wrapper for the analog core can be bypassed. These wrappers can be designed using the IEEE 1500 standard for testing SoCs, since the logic between the wrappers, namely the TSVs, are also required to be tested.

Proposed Architecture

The conventional approach for test compression in a core-based 3D-IC design, with each layer having several cores operating independently of other cores, is shown in Fig. 4. In this architecture, which uses static allocation of tester channels, the input test data bandwidth from the Automatic Test Equipment (ATE) is distributed to core decompressors using Test Access Mechanisms (TAMs) according to the free variable demand of each core. This distribution is done in a way to minimize the total time required to test the entire 3D-IC with no additional control information. However, the distribution of the tester channels among the decompressors is static and cannot be changed for every test cube. In addition, the tester channels allocated to each core should be large enough in number to ensure sufficient free variables are provided in symbolic simulation to encode the test cube that requires the largest number of free variables (in other words, the most difficult to encode test cube). However, there is a disadvantage if the decompressor is encoding a test cube that requires fewer free variables. Since the tester channels feed the same number of free variables for encoding all the test cubes, many free variables are wasted while encoding "easier-to-encode" test cubes, which results in increase in tester storage, as even the free variables not assigned any value (non-pivots) have to be stored on the tester. This extra tester storage, which is not used, is necessary to support the test architecture implemented in the 3D-IC.

Fig. 4. Test Architecture of 3D-ICs with Static Allocation of Tester Channels

To overcome this disadvantage, the tester channel allocation can be dynamic (i.e. changed for every test cube); however, to do so it is necessary to route the entire ATE bandwidth to all the layers, and control the number of channels allocated by providing additional control signals, which need more test elevators compared to static channel allocation. This presents a significant advantage that, because the number of channels allocated while decompressing every test cube can be changed, the number of wasted free variables from the tester can be reduced. In the context of 3D-ICs, the number of tester channels to each core also translates into the number of TSVs or test elevators required. Thus, dynamic allocation of tester channels requires lot more test elevators than static allocation, which may not be feasible for designs with large number of cores, as the number of TSVs available is limited.

The proposed architecture is shown in Fig. 5; with the decompressors of the cores daisy-chained together. This architecture uses the same number of test elevators as the static channel allocation, while providing an advantage almost equivalent to the dynamic channel allocation. In the architecture shown in Fig. 5, the decompressors of the cores are daisy-chained together, with a tapering bandwidth between successive higher layers of the 3D-IC. In other words, the number of channels between the highest layer and the middle layer is less than the number of channels between the bottom layer and the middle layer, which in turn is less than the input bandwidth to the decompressors in the bottom layer, i.e. total bandwidth from the ATE. Using this architecture, some free variables from the decompressor in the bottom layer is sent to the decompressor in the middle layer and so on. This provides some flexibility in encoding the test cubes. Free variables unused while encoding a core in a layer are available to encode other cores in the layers above with which they are shared, hence reducing free variable wastage and improving encoding efficiency.

Fig. 5. Proposed Architecture with Daisy-Chained Decompressors

The rationale behind such bandwidth allocation is that the bandwidth feeding each layer should be sufficient to supply enough free variables to encode the test cubes for the core in that layer and the test cubes for the layers above, as the decompressor in each layer is fed via taps from the decompressor of the layer below. Hence, the bandwidth supplied to the bottom layer should be big enough to supply free variables to encode test cubes of the cores in the bottom layer as well as cores in the middle layer and the top layer. Similarly, the bandwidth supplied to the middle layer should be big enough to supply free variables to encode test cubes of the cores in the middle layer and the top layer. In other words, the number of free variables supplied to decompressor in each layer decreases as we move from the bottom layer to the top layer. Hence, a tapering bandwidth is used, as shown in Fig. 5, proportional to the number of free variables required to be supplied to the decompressor in each layer. An example comparing the bandwidth allocation for the two architectures is shown in Fig. 6. It should be noted that the number of test elevators required to implement both the architectures is the same.

The proposed architecture provides flexibility in utilization of free variables; any free variable coming from the tester can be used in any of the layers, provided it is distributed across all the layers. Consider the decompressor in the top layer is encoding an easy-to-encode test cube with few specified bits, which needs less than average free variables, while the test cube being encoded in the middle layer is hard-to-encode with a larger number of specified bits, needing more free variables than average. In the proposed architecture, the free variables which are not required in the top layer can be used in the middle layer in help encode the hard-to-encode test cube. This reduces the number of free variables required to encode the entire test set for the 3D-IC, without additional hardware and control, with the same number of TSVs as used in the conventional architecture shown in Fig. 4. However, to accomplish this, the test cubes for the cores should be reordered and reorganized such that all the cores are not being tested by hard-toencode test cubes at the same time. In other words, the number of free variables required to encode test cubes that are decompressed together should be reduced as much as possible. This reduces the tester storage and thereby, the test time. This reordering can be accomplished heuristically by a test scheduling algorithm similar to the one explained in [Muthyala 13], with a few modifications to suit the 3D-IC testing paradigm. However, additional control data is not required, unlike [Muthyala 13], unless a subset of cores from those daisy-chained together have to be selected. To illustrate the encoding advantage of the proposed approach, consider a small example in which a 3D-IC has three layers with each layer having one core. Let the set of test cubes for the cores have care-bit profiles as shown in Table 1. Consider each care bit in a test cube needs one free variable to encode, as a first order approximation. To encode the entire 3D-IC using the conventional architecture shown in Fig. 1, core 1 would need a minimum of 13 free variables per test cube, core 2 would need 11 free variables and core 3 would need 12 free variables per test cube. Since there are 8 test cubes for each core, a total of (13 + 11 + 12) x 8 = 288 free variables are required to encode the 3D-IC.

Consider the same 3D-IC, now using the proposed architecture. In this case, encoding is done in groups of three test cubes, with one test cube from each core. Optimizing the test cubes in the group for minimizing the total number of care bits in the group, the test cubes are grouped as shown in Table 2. By encoding in groups according the above table, the maximum number of care bits in any group is 27, and hence, to encode the entire set of eight test cube groups, 27 x 8 = 216 free variables are required using the proposed architecture, which is less than the number of free variables required to encode using the conventional architecture shown in Fig. 4. Thus, it is seen that the proposed architecture gives better compression and hence reduces the tester storage requirements and test time.

The drawback in the proposed architecture is that the linear equations for scan cells driven by daisy-chained decompressors cannot be solved independently. In order to make sure the shared free variables are used in only one of the decompressors, the equations for all the scan cells fed by the connected decompressors have to be solved concurrently. Consider one test cube from each layer being encoded. The total number of free variables brought in from the tester has to be sufficiently large enough to encode all three test cubes. Hence, creating pivots for care bits in all the three test cubes involves a lot of computation. The total number of XOR operations required to create pivots is 9n 3 as compared to 3n 3 XOR operations required to encode using the conventional approach, where n is the number of free variables. Hence, this method is reasonable when the additional computation is a reasonable price to pay for the test time reduction achieved.

Optimizing Number of Test Elevators by Inter-layer Serialization of Test Data

In this section, an implementation is proposed using a serializer-deserializer structure to further reduce the number of test elevators required to implement the proposed architecture. The scan shift frequency is usually lower than the functional frequency, since the scan clock tree is generally not buffered up for high speeds. Another reason is that during scan shift, a large percentage of flip-flops toggle, and hence a large amount of power is drawn from the power grid of the chip. This causes a voltage drop in the power lines. To avoid these problems, scan shifting is generally considerably slower than functional frequency.

By using the proposed implementation, the difference between the slower scan shift frequency and the faster functional frequency can be exploited to further reduce the number of test elevators. The idea is to use a serializer at the layer sending test data to serialize the test data from the decompressor taps. The test elevators are driven in the sending layer by this serial test data. At the receiving layer, the data from the test elevators are restored in parallel and sent to the decompressor in the same format as sent by the LFSR in the sending layer. (Fig. 7). This is possible because the test elevators are optimized for the functional frequency. However, even if the transfer of data cannot be done at the functional frequency, it can be done at a frequency higher than the scan shift rate, as long as it is a multiple of the scan shift frequency. Consider a serializer driven by m taps from the LFSR in the sending layer. Let the functional clock be n times faster than the scan clock. Therefore, as explained previously, the number of test elevators required would be m/n. Let the number of test elevators required be represented as t, which, here, is equal to m/n. Inter-layer serialization would require an m x t serializer in the sending layer driving the test elevators between the layers and a t x m deserializer driving the LFSR in the receiving layer. The simplest way of implementing an m x t serializer in the sending layer is by using a m:t multiplexer controlled by a modulo m counter driven by the faster functional clock (Fig. 8). This ensures that the test data coming in at scan shift frequency from the LFSR is coupled to the test elevators at the faster functional clock frequency. Similarly, the deserializer can be implemented as an m bit shift register driven by the faster functional clock, whereas the data in the shift register is sampled at the slower scan clock rate (Fig. 9).

Alternatively, if the LFSRs can be operated at the functional frequency, or at any other faster frequency, the need for additional serializer and deserializer can be avoided. The LFSRs can just transfer the data at the faster frequency, while the scan chains shift in data at the scan frequency. However, this needs the time domains of the different cores to be synchronized or the frequency has to be reduced in such a way that the receiving LFSR can sample the data from the test elevators without any loss in data or introducing metastability concerns.

As discussed above, inter-layer serialization has a small area overhead; hence, it can be used in cases where the advantage of using it outweighs the additional cost of implementing the required architecture in the design.

Experimental Results

Experiments were conducted on six different 3D-IC designs and the results are presented in this section. These 3D-ICs have three layers, with each layer having one core. Three different test compression architectures were experimented using these test chips. In the first test architecture (arch1), each core has a 64-bit LFSR, acting as a decompressor. The input tester channels from the ATE are allocated to the decompressors statically as shown in Fig. 4. In this architecture, the output cone of the each decompressor is confined to the layer in which the decompressor is present, i.e. test elevators are required to transfer the compressed test data to the decompressors in the non-bottom layers. However, all scan cells driven by a decompressor are localized to the layer in which the decompressor is present. Hence, it is enough to have sufficient test elevators to transfer the compressed test data, which is generally less in number compared to using test elevators to transfer the uncompressed test data.

In the second architecture (arch2), the 64-bit LFSRs that were local to each layer in arch1, are interconnected and reconfigured to form a big primitive LFSR with number of flip-flops in this big LFSR being the sum of the number of flip-flops in the arch1 LFSRs in all the three layers. It should be noted that the LFSR in arch2 is distributed across the three layers, i.e. sections of LFSR are present in each of the three layers and these sections are interconnected using test elevators in such a way that a primitive LFSR is formed and this 192-bit LFSR drives scan chains in all three layers of 3D-IC. In this case also, the scan chains are confined within the layer, i.e. test elevators are required to transfer compressed test data to the sections of LFSR in the non-bottom layers.In addition, test elevators are also required to interconnect the sections of LFSR that are in different layers. Hence, more test elevators are required in arch2 compared to arch1. Using this architecture, the equations for the scan cells of the three layers are solved together and since the pivots for the test cubes are created in common, the free variables are used more efficiently and results in better compression and increased encoding efficiency.

The third architecture (arch3) is the proposed architecture using daisy-chained decompressors shown in Fig. 5. In this case, the decompressors used are similar to the ones used in arch1, a local 64-bit LFSR in each core acting as a decompressor for the core, with all the decompressors daisy-chained together. The tester channels are allocated to the decompressors as described in Sec. 4. This method combines the advantages of arch1 and arch2 at the cost of increased computational complexity of encoding the test cubes together. By using this architecture, some of the free variables are distributed to the decompressors in the other layers and the encoding of the test cubes of the three layers are done together, thereby the free variables are used more efficiently and results in better compression and increase in encoding efficiency similar to arch2. However, in this method, test elevators are required only to transfer the compressed test data to the non-bottom layers, similar to arch1, while providing an encoding advantage similar to arch2. In addition, reconfiguration of the local 64-bit LFSRs into a big LFSR for post bond testing of the 3D-IC is also not necessary when using arch3.

Experiments were run on six different designs of 3D-ICs, each containing three layers. The test cubes used provided 100% coverage of detectable faults. Static encoding was used to encode the test cubes. The compressed test data, i.e. tester storage required for the three architectures explained above and the number of test elevators (TSVs) required to implement the test architecture is presented in Table 3. As shown in Table 3, there is reduction in the amount of tester data while using arch2 when compared to arch1. As explained earlier, similar benefit is obtained by using arch3 as well. This is because both arch2 and arch3 provide flexible use of free variables across layers and the free variables that are not used in encoding test cube of one layer can be used to encode test cubes of other layers. In addition, by using daisy-chained decompressors (arch3), the number of test elevators required is less compared to arch2, since the decompressors are local to each layer.

Fig. 2 .

 2 Fig. 2. Gaussian Elimination to Obtain Tester Data for Example in Fig. 1

Fig. 6 .

 6 Fig. 6. Example for Comparing Channel Allocation between Conventional (left) and Proposed Architectures (right).

Fig. 7 .

 7 Fig. 7. Proposed Implementation of Inter-layer Serialization of Test Data

Fig. 8 .Fig. 9 .

 89 Fig. 8. Serializer Implementation for Functional Clock Operating n Times Faster than Scan Clock, Where Number of Test Elevators, t = m/n

Table 1 .

 1 Example -Care Bit Profile of Test Cubes for the Three Cores of the Example 3D-IC

	Test	# Care bits in Test cube
	Cube	Core 1	Core 2	Core 3
	1	13	11	12
	2	12	11	10
	3	10	10	9
	4	9	7	8
	5	8	6	7
	6	7	5	5
	7	7	5	4
	8	6	4	3

Table 2 .

 2 Care Bit Profile of Test Cube Groups for Encoding Using Proposed Architecture

	Test Cube Group	# Care bits in Test cube Core 1 Core 2 Core 3	Total Care Bits in Test Cube Group
	1	13	4	7	24
	2	12	5	8	25
	3	10	5	12	27
	4	9	6	10	25
	5	8	7	9	24
	6	7	10	5	22
	7	7	11	3	21
	8	6	11	4	21

Table 3 .

 3 Comparison of Tester Data for the Three Architectures

			Local Independent	Global		Proposed
	Test Vectors	Scan Cells	Decompressors (arch1) Tester Data (# of Bits) TSVs	Decompressor (arch2) Tester Data (# of Bits) TSVs	Daisy-chained Decompressors (arch3) Tester Data (# of Bits) TSVs	Percentage Reduction in Tester Data
	A 838 2578	8272	13	6016	21	6016	13	27.27%
	B 606 6747	18245	15	11070	21	11070	15	39.33%
	C 686 5662	9512	13	6560	21	6560	13	31.03%
	D 751 8724	13314	15	9193	21	9193	15	30.95%
	E 803 9432	13583	15	10144	21	10144	15	25.32%
	F 807 10538 17538	15	12046	21	12046	15	31.31%

Conclusion and Future Work

The proposed daisy-chain test architecture for 3D-ICs implements a free-variable sharing technique, which allows test patterns to be encoded more efficiently thereby reducing the amount of tester data that needs to be stored on the tester. Given the larger transistor count of 3D-ICs, reducing tester data is of a great importance. In addition, this architecture can use inter-layer serialization, where the number of test elevators required is reduced even further, by utilizing the faster functional frequency to transfer test data across layers. Experimental results are presented comparing the tester storage requirements of the conventional architecture and the proposed architecture, and it is shown that the proposed daisy-chain architecture presents a significant reduction in the amount of tester storage required, for the same set of test patterns.

This work opens up avenues of possible future work. The method proposed is an aggressive way of minimizing the number of test elevators at the cost of additional computation in the linear equation solver. One direction for reducing the amount of computation would be to develop intelligent partitioning methods for which cores are tested together that reduce the total amount of free variable sharing, but still retain most of the encoding flexibility where it is most needed. Another direction for further research would be to consider ways to reduce power dissipation during decompression by using the added encoding flexibility to reduce transitions in the decompressed scan vectors.