v 2.10 a) Optical photograph of the fabricated test devices included Ohmic con-

Introduction 1

1 Boron doped diamond semiconductor for unipolar power devices 3 1.9 Theoretical hole density as function of acceptor concentration and compensation at 300 and 500 K. The symbols are experimental data reported by: Barjon et al. [5], Volpe et al. [6], Gabrysch et al. [7], Werner et al. [8], and Tsukioka et al. [9]. Courtesy of Traore et al. [10] . . . . . . . . 23 Silvaco Atlas simulation the potential distribution at dierent gate bias a) V GS =-5 V ; b) V GS =0 V; c) V GS =6 V; and electric eld distribution at three dierent gate bias: a) V GS =-5 V ; b) V GS =0 V; c) V GS =6 V.

Simulation conguration were presented in Fig.

Introduction

Nowadays, global warming eect is becoming one of the most challenging issue for the human beings. In order to deal with this issue, many propositions were suggested. Most of them are dealing with the energy crisis, especially electricity. In fact, the amount of electricity needs to supply the demand of more than 6 billion people on earth is tremendous. The main electricity suppliers are coming from traditional energy sources like thermal power, nuclear power, hydroelectricity power, etc.. Most of the mentioned power sources are dangerous and/or potentially dangerous for nature and human beings.

Therefore, a greener energy is highly desired. Greener energy has two fold meanings:

on one hand, it uses renewable energy sources like solar power, wind power or geothermal energy instead of traditional energy sources, and on the other hand, using the electricity more eciently. A recent report has pointed out that the energy loss in US is about 10 %, more than the sum of all renewable energy generated in US. Therefore, an eective use of electricity and a limitation of the waste are critical.

Unfortunately, losses are endemic in semiconductor components, the central devices of all power conversion systems. Indeed, most of semiconductor components are fabricated on Silicon (Si), a semiconductor that has reached its physical limits. Even if the new architectures can push Si devices beyond their physical limits, this approach will not provide a long term solution. Therefore, the emergence of new semiconductors with superior physical properties is highly desired for next generation of power electronics.

Wide band-gap semiconductors such as silicon carbide (SiC), III-Nitride, gallium oxide (Ga 2 O 3 ) and diamond are promising materials to fabricate devices, exhibiting low loss in the on-state regime and high breakdown voltages in reverse regime. Among them, diamond is the ultimate semiconductor for power devices due to its superior physical properties. Recent progresses on diamond substrates that includes homoepitaxial growth, controlled doping and fabrication processing permits to consider diamond power devices, e.g. Metal Oxide Semiconductor Field Eect Transistors (MOSFET). However,up to now, most of diamond MOSFETs were realized by controlling the two dimensional hole gas (2DHG) on the hydrogen terminated diamond surface. Even though these devices are interesting, their working principle is based on uncertain quantities (trap states in the oxide) and bearing itself the demerits (see further discussion in the thesis).

In order to realize a diamond MOSFET by controlling diamond semiconductor, numerous issues must be overcome. Diamond is a wide bandgap semiconductor which does not have a native oxide layer, nd an appropriate candidate for the gate oxide on diamond MOSFET is challenging. The two most important criteria for the gate oxide choice are: i) barrier heights for electrons and/or holes at the diamond/oxide interface in order to ensure a low leakage current from the transistor channel to the gate metal, ii) low density of trapped charges at the diamond/oxide interface and/or in the oxide in order to obtain an ecient Fermi level control from the gate electrode bias. In this context, Chicot et al. [22] have introduced the O-diamond/Al 2 O 3 MOSCAP test devices. Marechal et al. [24] measured the type I band alignment at the O-diamond/Al 2 O 3 interface, which is favorable to realize both inversion and depletion MOSFETs. This PhD project is a continuation of the two previously mentioned thesis. It includes two main objectives: 1.

C o n d e n t i a l • In Chapter 1, we will discuss the losses of a semiconductor switch in power converter systems and the importance of wide bandgap semiconductors to reduce losses. The comparison between wide bandgap semiconductors by means of Figure-of-Merit (FOM) is followed to demonstrate the superiority of diamond. We will then present in details the important physical properties of diamond for power devices. State-ofthe-art of diamond devices will be reviewed. As an introduction for the MOSFET device, we will introduce the working principle of an ideal MOSCAP test device.

State-of-the-art of O-diamond MOSCAP test devices will be described. Finally, the chapter will conclude on the purpose of the thesis.

• Chapter 2 will be dedicated to the fundamental of understanding the O-diamond MOS capacitor test device. This chapter will include three parts:

Part 1: We will rstly address the methodology issues related to diamond growth, fabrication processing, electrical characterization and the reliable issue related to a correct C-V measurements. From correct C-V measurements, we will evaluate dierent crucial information of a O-Diamond MOS capacitor such as charges components, semiconductor surface potential and space charge region variation with gate potential. High frequency-capacitance method is applied to quantify the interface states density. Electrostatics model based on dierent charge components will be built. Electrostatics band diagram will be then introduced and the limit of this model will be addressed.

Part 2: We discuss the origin of leakage currents and capacitance-frequency dependent when O-diamond MOS capacitor is biased in negative potential. We will quantify the interface states density at the O-diamond/Al 2 O 3 interface using con- ductance method. With new interface states density, a complete electrostatics model for O-diamond/Al 2 O 3 MOSCAP will be proposed.

Part 3: We correlate the substrate imperfection versus the electrical characteristics of the O-diamond MOS capacitor. We will discuss the origin of leakage current and the capacitance-frequency dependence when the O-diamond MOS capacitor is biased in positive potential.

• Chapter 3 will introduce our rst approach to realize a depletion mode diamond MOSFET. We will rstly address dierent technical issues related to design, fabrication, measurements and simulation. Then, the combined electrical measurements, analysis and simulation on the diamond MOSFETs and test devices (TLM, MOS capacitor) fabricated on the same sample will be presented. Important parameters of the transistor such as contact resistance and carriers mobility will be quantied. The results on OFF state measurement, simulation and analysis will also be presented. The benchmarking of the device and the projection toward device improvement will be described. Finally, the thesis will be concluded.

C o n d e n t i a l

Chapter 1

Boron doped diamond semiconductor for unipolar power devices Nowadays, electricity is ubiquitous in our daily life. As shown in Fig. 1.1, human beings are now dealing with a wide range of energy, ranging from kW in some power suppliers to few GW in the grid energy transmission and distribution.

Basically, electricity exists in two forms: Direct Current (DC) and Alternating Current (AC). From the generation at power station to the transmission and delivery to home and electrical devices, electricity is necessary stepping up and stepping down as well as switching between two forms. Therefore, electrical conversion and amplication/attenuation are very important. Figure 1.2 represents the basics electrical circuit of a non isolated DC-DC boost converter (Fig. 1.2a) and a non isolated DC-DC buck converter (Fig. 1.2b). As shown in Fig. 1.2, power devices are the heart of the power converter systems (transistor and diode). Solid state switches like transistors, since being invented in 1947 [25], have replaced vacuum tube in every applications. These devices are critical in any power converter and power system.

In power electronics and power converters, power devices are used in switch mode, switching between two states and targeting the operating regimes with negligible losses:

ON-state and OFF-state. Ideally, in the ON-state, the device is working like a conductor and the resistance of the device is 0 (Ω). In the OFF-state, the device is completely isolated and the resistance of the device is innite.

C o n d e n t i a l 4 Chapter 1. Boron doped diamond semiconductor for unipolar power devices compared to other wide bandgap semiconductors. Even if novel designs push devices performance beyond its physical limits, Si will not provide a long term solution.

The emergence of new semiconductors is urgent. Wide bandgap semiconductor such as III-Nitride, Silicon Carbide (commercialized) and diamond are now considered as the solution for next generation power devices.

In order to evaluate the potential of semiconductors, Figure of Merits (FOMs) [26,27,1] are usually used as the mean. There are generally two kinds of FOMs: material FOMs to evaluate a material and device FOMs to evaluate the designs of the devices.

Unipolar device's Figure-of-Merit(FOM)

Considering the ideal switching waveforms of a power MOSFET (Fig. 1.4), losses of an unipolar switch without taking into account the circuit operation, can be expressed by using the following equation [1]: The rst term represents the DC conduction loss. The second term represents the switching loss, which is depending on the switching frequency. In conduction loss, the most important part is the ON-resistance R on (in case built-in potential is neglected). For an ideal uniformly doped drift region and abrupt junction in Non-Punch-Though (NPT) design (Figure 1.5), the ON-state resistance can be dened using the fundamental semiconductor equation:

P loss ≈ I 2 rms R on + V D I D (t r + t f ) f (1.1)
R on × S = W qµN A (1.2)
where S is the active surface of the device, W is the width of the drift region, q 1.6 × 10 -19 C is the elementary charge, µ the carrier mobility and W and N A are the thickness and doping concentration of the drift region, respectively. As a function of the breakdown voltage, the total ON-resistance can be splitted among dierent contributors other than drift region resistance (e.g. contact resistance, series resistance, heavily doped substrate, channel resistance, . . . ).

For a compromise between ON-state loss and OFF-state breakdown, the thickness and doping of the drift region must be optimized. Considering the OFF-state under reverse bias, a maximum voltage that can be supported by the drift region is estimated by the critical electric eld E c [27]. Once the maximum electric eld in the structure reached the critical electric eld of the material, devices will experience a breakdown due to avalanche eect.

Under breakdown conditions, depletion width is given by:

W = 2BV E c (1.3)
where BV is the breakdown voltage and E c is the critical electric eld.

The doping concentration in drift region required for a given breakdown voltage is:

C o n d e n t i a l

N A = ε sc E 2 c 2qBV (1.4)
where ε sc is the semiconductor dielectric constant. By combining the equations 1.2, 1.3 and 1.4, the ideal ON-resistance of the drift region is then expressed as:

R on = 4BV 2 ε sc µE 3 c (1.5)
The denominator is usually preferred as Baliga material FOM (BMFOM) [27], which has been derived by Baliga in 1983 as:

BM F OM = ε sc µE 3 c (1.6)
In principle, semiconductors with higher BMFOM are expected to have a lower conduction losses. Also, materials with higher critical electric eld are expected to have higher breakdown voltages than material with lower critical electric eld in a same device design (doping concentration, device structure, etc.). However, there are some issues with BMFOM. Firstly, BMFOM is not taking into account the incomplete ionization of wide bandgap semiconductors, e.g. diamond. Therefore, BMFOM underestimates the ONresistance of diamond devices at room temperature (RT). Second, the concept of using critical electric eld for the comparison is not necessary correct. As shown by Raynaud et al. [28] and Chicot et al. [23], critical electric eld is varying with doping concentration by integrating the impact ionization coecients into the avalanche calculation [29].

C o n d e n t i a l 8 Chapter 1. Boron doped diamond semiconductor for unipolar power devices

The application of the avalanche breakdown condition must be discussed, as some power devices will be limited by other phenomena and never reach the avalanche breakdown (leakage current limit, dielectric breakdown, . . . ). Finally, BMFOM is correct only for the devices operating at low frequency where conduction loss is dominant. When the operating frequency is high, switching losses becomes important and BMFOM is no longer appropriate.

In order to take into account the switching losses, current rising time (t r ) and voltage falling time (t f ) in Fig. 1.4 were considered by Huang et al. [1]. The author also assumed that during the switching period of high power devices, the charging and discharging of gate-to-drain charge Q gd dominate the switching loss, i.e. t f >> t r [1]. The general power losses of equation 1.1 is then approximated by:

P loss ≈ I 2 rms R on + V D I D t f f (1.7) with t f = Q gd ig,avg
where I g,avg is the gate current at the Miller Plateau and it can be controlled by the gate driver and gate resistors. Both ON-resistance and Q gd are related to the area of the device by their specic value. Equation 1.7 can be rewritten by considering the area factor of the device as:

P loss = I 2 rms R on,sp A + V D I D f Q gd,sp A i g,avg (1.8)
Where R on,sp and Q gd,sp are the specic ON-resistance and specic gate-to-drain charge, respectively. By increasing device area, the rst term decreases and the second term increases. Total power loss exhibits a minimum value at an area that:

dP dA = 0 (1.9) Therefore P loss,min = 2I rms V D I D f i g,av R on,sp Q gd,sp (1.10)
when the chip area is

A opt = I rms V D I D f ig,avg R on,sp Q gd,sp (1.11)
A. Huang claimed that the rst term of equation 1.10 is relating to circuit operating and the second term is relating to the device [1]. The second term is considered as the new device FOM named as Huang's device FOM (HDFOM) [1]:

HDF OM = R on Q gd (1.12)
where R on is identical to the expression in equation 1.5. Q gd is the gate-to-drain charge and usually known as Miller charge [1], and can be expressed as:

Q gd = kεE D = k V D V B εE c (1.13)
where V D is the converter bus voltage, and I D is the switch turn-on and turn-o current, E D is the peak electric eld when V=V D , k represents the area ratio of the gate- to-drain overlap area over the whole chip area [1]. The HDFOM is related to material C o n d e n t i a l properties by the multiplication R on in equation 1.5 and Q gd in equation 1.13. The minimum loss in equation 1.11 is then expressed as:

P loss,min = 4I rms (V B V D ) 3/4 kI D f ig,av E c √ µ (1.14)
The denominator is usually referred as Huang's material FOM (HMFOM) [1].

HM F OM = (E c √ µ) (1.15)
A material with higher HMFOM is expected to have a lower loss during operation compared to a material with lower HMFOM. Again, the concept of using critical electric eld E c for comparison is not necessary correct (E c depends on the doping concentration of the drift layer).

Until now, as far as author's knowledge, these two FOMs are the most common FOMs to evaluate the strength of semiconductors for unipolar high power conversion device applications. Table 1.1 represents the physical parameters of main semiconductors for power devices (Si, SiC, GaN and diamond) and the corresponding material FOM values calculated by its corresponding authors [27,1]. From these two FOMs, diamond is standing-out as the best semiconductor for unipolar power device applications.

The compromise between ON-resistance versus BV of dierent materials have also being calculated by Umezawa et al. [2], as shown in Fig. 1.6. This calculation shows that, for a given breakdown voltage at its best operating condition (250

• C), diamond
can provide the lowest specic ON-resistance (lowest loss). It's based on the fact that all critical physical properties of diamond are outstanding compared to other semiconductors.

In the following sections, we will discuss in details the critical physical properties of diamond for power devices application. It is ranging from critical physical properties for ON-state current: doping, carriers density and carriers mobility and critical physical properties for OFF-state breakdown voltage: maximum electric eld.

Diamond semiconductor for power devices

As shown in the previous section, the ON-resistance is the most important parameter which determines the loss of device. ON-resistance is basically including two parts: material resistance and contact resistance. Material resistance is specied by its resistivity, which is dened as:

ρ = 1 qpµ (1.16)
where p is the free carrier concentration and µ is the carrier mobility. In order to idealize material resistance, both p and µ must be optimized. Free carriers concentration is controlled by the doping, while mobility is depending on the nature of material and dierent scattering mechanism including doping eect.

Doping

Due to the wide bandgap nature (5.5 eV), diamond was considered as an insulator and had been used as a gate insulator for Field Eect Transistors (FET) [30]. To be considered as semiconductor, diamond must be doped. The concept of diamond doping can be categorized into two main directions: surface doping and bulk doping.

C o n d e n t i a l 1.2. Diamond semiconductor for power devices 11

Surface doping

Surface transfer doping is considered as a novel doping concept in some semiconductors [31]. This concept is widely used to interpret the surface conductivity of hydrogen terminated diamond (H-diamond) [3,32]. amond layer is terminated by hydrogen, the conduction band is above the vacuum level.

Chemical potential is also rigidly moved up. Consequently, H-diamond is a negative electron anity semiconductor with a relatively high chemical potential (Fig. 1.7b) [33]. In principle, any substance that has a lower chemical potential than diamond and located at diamond surface will attract the electrons from diamond [3,34]. Naturally, H-diamond surface exposed to the air will condensate a thin water layer (Fig. 1.7a). This thin layer of water has a lower chemical potential than H-diamond. Therefore, electron inside diamond layer will transfer to the diamond surface and the water layer to equilibrate the chemical potential dierence (Fig. 1.7c). The electron transfer leaves free hole with typical density of 10 13 cm -2 in the valence band to be accumulated at the diamond surface (Fig.

1.7d). Therefore, once diamond surface is hydrogen terminated and being exposed to the air, diamond surface becomes conductive [3,34]. This conductive surface will disappear when either the lower chemical potential substance disappear or the H-diamond surface disappear. As shown by Maier et al. [33] by changing diamond surface from H-diamond to oxygen terminated diamond (O-diamond), there are about 3 eV dierence in terms of diamond electron anity and the conductive diamond surface is disappeared.

The surface transfer doping is natural and somehow lack of controllability. Therefore, a more controllable doping method is required.

C o n d e n t i a l properties. This doping method is challenge because it is required one manage both crystal grow epitaxially as well as dopant incorporation. The pioneer works on incorporating dopants into homoepitaxy diamond were mainly done in Japan [35,36]. Since then, there are many eorts to investigate boron doped p-type diamond [36,37,38,39,40,41,42,43,44] and phosphorous (P) doped n-type diamond [35,45,[START_REF] Kato | n-type diamond growth by phosphorus doping on (0 0 1)-oriented surface[END_REF][START_REF] Kato | Low specic contact resistance of heavily phosphorus-doped diamond lm[END_REF][START_REF] Pinault | The n-type doping of diamond: present status and pending questions[END_REF][START_REF] Pinault-Thaury | n-type cvd diamond: Epitaxy and doping[END_REF]. One of the most challenging issue regarding diamond doping is the ionization energy of the dopant which is considerably deep. Since the dopant ionization of boron doped diamond is much lower compared to n-type diamond, the carriers ionization of p-type is also more eective than n-type diamond. In fact, the carrier activation also depends on doping concentration (N A ) as well as compen- sation concentration (N D ). As shown by Traore et al. [10], depending on compensation concentration, the ionization ratio of [B] dopant at RT can be ranging from 0.1% to 1%

. Therefore, there are a small portion of [B] dopant which can contribute to the free C o n d e n t i a l 1.2. Diamond semiconductor for power devices 13

hole density in the valence band at RT. The activation ratio is signicantly increased by raising the temperature to T = 500 K, as shown in Fig. 1.9b. Therefore, a proper diamond device is expected to have a negative temperature eect (ON-state performance is improved with the increasing of temperature) in a certain range of temperature. 17 (cm -3 ) to 0 eV for a doping concentration above 5×10 20 (cm -3 ) [43]. This behavior is excellently tted by the Pearson model [START_REF] Gk | Electrical properties of pure silicon and silicon alloys containing boron and phosphorus[END_REF] using the empirical law:

E a (eV ) = 0.38 -4.7877 × 10 -8 × N 1 3 A (1.17)
Where E a is the thermal ionization energy of boron acceptor and N A is the boron dop- ing concentration (cm -3 ). The metallic regime (N A = 5 × 10 20 cm -3 ) is useful to reduce the series resistance in the test device or improve the device performance in punch-through (PT) design. Therefore, mastering a wide concentration range of boron doped diamond is very important for device optimization toward low ON-state loss, high OFF-state breakdown diamond power devices.

Regarding the low ON-state loss, along with carrier density, carrier mobility is equivalently important to determine the resistivity, as shown in equation 1.16.

Carrier mobility and density

Diamond is considered as an ultimate semiconductor partly due to its superior carriers mobility compared to other wide bandgap semiconductors. Pernot et al. [11] have shown C o n d e n t i a l 14 Chapter 1. Boron doped diamond semiconductor for unipolar power devices that due to the low optical phonon population, carriers mobility in diamond is elevated at RT. In ideal case, carrier mobility is controlled by lattice scattering and dopant scattering.

As shown in Fig. 1.10, for a boron concentration around a few 10 17 cm -3 , the hole mobility is controlled by lattice scattering and an optimal hole mobility as around 2000 cm 2 /V.s can be obtained [11]. This hole mobility is higher than the electron mobility of other semiconductor like Si ( 1500 cm 2 /V.s), GaN ( 1250 cm 2 /V.s) and 4-SiC ( 1000 cm 2 /V.s). For a boron concentration larger than a few 10 17 cm -3 , scattering from neutral impurities becomes more important. At boron concentration above 3×10

18 (cm -3 ), the scattering from neutral impurity becomes dominant. Once the scattering from neutral impurity is involved, hole mobility is strongly degraded [11]. Similarly, a maximum electron mobility of 1000 cm 2 /V.s is determined for the low doped n-type diamond. [START_REF] Pernot | Electron mobility in phosphorous doped {111} homoepitaxial diamond[END_REF]. Free carriers density and carriers mobility at dierent doping concentration and temperatures can be calculated by using the model introduced in Volpe et al. [6] and Pernot et al. [11]. The free hole concentration is calculated by using the equation:

p = 1 2 (φ A + N D ) 1 + 4φ A (N A -N D ) (φ A + N D ) 2 1/2 -1 (1.18)
where

N v = 2 (2πm * k) 3/2 /h 3 and φ A = (g 1 /g 0 ) N v T 3/2 × exp -E A kT
, k is the Boltzman constant. The degeneracy factor of boron is assumed to be g 1 /g 0 = 1/4 and the average hole eective mass is 0.908m 0 . N A is the doping concentration and N D is the compensation concentration. More detailed parameters and approximations can be found in the corresponding references [6] [11].

C o n d e n t i a l 1.2. Diamond semiconductor for power devices 15

Hole mobility at dierent doping concentrations and temperatures, considering that only phonon scattering and dopant scattering can be calculated by [6][11]:

µ (T, N imp ) = µ (300, N imp ) T 300 -β(N imp ) (1.19)
with N imp = N A + N D . β (N imp ) and µ (300, N imp ) is evaluated individually by tting the experimental data. The function β (N imp ) is calculated as:

β (N imp ) = β min + β max -β min 1 + N imp N β γ β (1.20)
where β min = 0 for highly doped material, β max = 3.11 for pure material, N β = 4.1 × 10 18 cm -3 and γ β = 0.617 for boron doped diamond [6]. The µ (300, N imp ) function is calculated as:

µ (300, N imp ) = µ min + µ max -µ min 1 + N imp Nµ γµ (1.21)
where µ min = 0 (cm 2 /V.s) for the highly doped diamond in which hopping appears, µ max = 2016 (cm 2 /V.s) is the highest hole hall mobility, N µ = 3.25 × 10 17 cm -3 and γ µ = 0.73 [6].

Thanks to the above analysis, following conclusions can be drawn:

1. Boron doped p-type diamond is more favorable for diamond unipolar devices. This conclusion is based on the fact that boron doped diamond has a lower dopant ionization energy and a higher free carriers concentration compared to n-type diamond.

Furthermore, the hole mobility of p-type diamond is much higher compared to electron mobility in n-type diamond.

2. Regarding the compromise of boron concentration and hole mobility, a boron concentration of 10 17 (cm -3 ) is highly desired. Therefore, throughout this PhD thesis, a boron doped diamond epilayer of 10 17 (cm -3 ) is intentionally mastered.

3. The ideal ON-state device characteristic corresponding to a desired OFF-state breakdown voltage at a certain temperature can be projected by using the relationship between carrier density and carriers mobility with doping concentration and compensation concentration.

Dielectric breakdown eld

As mentioned above, OFF-state breakdown voltage of a power device is limited by the maximum electric eld of the material. Material with extreme critical electric eld is highly desired for power device to control signicant OFF-state voltage and consequently high power. As one can see from the dierent gure of merits, the higher the E c critical eld, the better the gure of merits. Therefore, wide bandgap devices reaching high critical electric eld can have a strong impact on power converters For diamond, Langstrass et al. [START_REF] Mi Landstrass | Device properties of homoepitaxially grown diamond[END_REF] has reported a paramount critical electric eld of 20 MV/cm. However, this value is relatively lacking reality. In the mentioned work, the Chapter 1. Boron doped diamond semiconductor for unipolar power devices test devices were fabricated on a thick epilayer (30 µm) and highly doped (10 18 cm -3 ).

Commonly, diamond theoretical critical electric eld is considered as around 10 MV/cm. From experimental reports, diamond breakdown electric eld is also very remarkable. P. N. Volpe et al. [12] reported a lateral oxygen terminated boron doped diamond Schottky diode on homoepitaxial boron doped ( 1016 cm -3 ) diamond with a breakdown voltage of 10 kV and a peak electric eld of 7.7 MV/cm at breakdown. The mentioned device structure and performance is shown in Fig. 1.11. Traore et al. also reported a similar breakdown electric eld by using pseudo-vertical punch-through design [13]. The experimental breakdown electric elds of diamond are already much higher compared to the theoretical critical electric eld of Si (0.3 MV/cm -doping and temperature dependent), 4H-SiC (3 MV/cm -doping and temperature dependent) and GaN (2 MV/cm -doping and temperature dependent, also devices structure dependent -GaN has a wider bandgap than SiC, but GaN devices are lateral where the peak electric eld is not achieved due to 3D eects). So far, we have shown that boron doped diamond is possibly the ultimate material for unipolar high power devices. It is thanks to an elevated hole mobility and a superior breakdown electric eld. The incomplete ionization problem can be solved by increasing the operation temperature. Therefore, diamond appeared to be an ideal candidate for unipolar high power and high temperature applications. In the next part, we will briey review the architectures and performances of state-of-the-art diamond unipolar devices.

C o n d e n t i a l 1.3. States-of-the-art of diamond unipolar power devices 17

States-of-the-art of diamond unipolar power devices

Thanks to the superior physical properties, diamond was seriously considered for power devices. After decades of investigation, epitaxial growth and doping control are well mastered [35][36, 40]. Dierent approaches to realize the diamond devices have been done. It can be categorized into two main directions: 1) two terminals devices such as p-n junction [START_REF] Makino | Diamond schottky-pn diode with high forward current density and fast switching operation[END_REF], p-i-n junction [START_REF] Makino | Electrical and light-emitting properties of homoepitaxial diamond pin junction[END_REF], Schottky diode [START_REF] Butler | Exceptionally high voltage schottky diamond diodes and low boron doping[END_REF][START_REF] Umezawa | 1 ω on-resistance diamond vertical-schottky barrier diode operated at 250 c[END_REF]12,13]; 2) three terminal devices such as bipolar transistor like BJT [START_REF] Kato | Diamond bipolar junction transistor device with phosphorus-doped diamond base layer[END_REF][58], JFET [START_REF] Iwasaki | Diamond junction eld-eect transistors with selectively grown n+-side gates[END_REF][START_REF] Iwasaki | High-temperature operation of diamond junction eld-eect transistors with lateral pn junctions[END_REF][START_REF] Iwasaki | 600 v diamond junction eld-eect transistors operated at 200[END_REF][START_REF] Suwa | Normally-o diamond junction eld-eect transistors with submicrometer channel[END_REF] and unipolar transistor like MOSFET, MESFET and delta doped FET. The works on bipolar junction transistor (BJT) [START_REF] Kato | Diamond bipolar junction transistor device with phosphorus-doped diamond base layer[END_REF][58] and junction eld eect transistor (JFET) [START_REF] Iwasaki | Diamond junction eld-eect transistors with selectively grown n+-side gates[END_REF][START_REF] Iwasaki | High-temperature operation of diamond junction eld-eect transistors with lateral pn junctions[END_REF][START_REF] Iwasaki | 600 v diamond junction eld-eect transistors operated at 200[END_REF][START_REF] Suwa | Normally-o diamond junction eld-eect transistors with submicrometer channel[END_REF] introduced numerous remarkable results on both the reliability at high voltage, high temperature and normally-o transistor. Also, delta doped eld eect transistors [START_REF] Gauthier Chicot | Hole transport in boron delta-doped diamond structures[END_REF][64] are very interesting to the physics point of view, although they did not show any mobility enhancement.

As we have mentioned, in frame of this PhD thesis, we will only focus on unipolar devices. As shown in Fig. 1.2, Schottky diode and transistor switches are the critical elements of a power converter system. Hereinafter, the recent achievements on unipolar diamond Schottky diodes and transistors will be summarized.

Diamond unipolar transistor

Basically, unipolar transistor can be categorized into either inversion mode transistor (Fig. In principle, as any insulator can be used as the gate insulator, the devices should be named as Metal Insulator Semiconductor Field Eect Transistor (MISFET). In this work, we only employed Al 2 O 3 oxide for gate insulator. Therefore, the devices will be named as Metal Oxide Semiconductor Field Eect Transistor (MOSFET) hereinafter. Thanks to the preservation of 2DHG, many H-diamond MOSFETs were realized [START_REF] Kawarada | Ch surface diamond eld eect transistors for high temperature (400 c) and high voltage (500 v) operation[END_REF]21]. A recent report demonstrated the H-diamond MOSFET with an ON-state current exceeding 100 mA/mm at V DS =-50 V and an OFF-state breakdown voltage of 1700

V for L GD =17µm, as shown in Fig. 1.16 [15]. Until the moment, this is among the best performance of a diamond transistor. This performance is also comparable with the lateral devices of other mature power devices like III-Nitride or SiC. Recently, the Kawarada's group also demonstrated the preservation of 2DHG for not only on the planar structure but also on the trench gate structure [15]. Thank to this particular interest, a vertical trench gate H-diamond MOSFET was recently realized [START_REF] Inaba | Hydrogen-terminated diamond vertical-type metal oxide semiconductor eld-eect transistors with a trench gate[END_REF]. Even if the performance of H-diamond MOSFET is very interesting, its working principle is actually based on an uncontrollability extrinsic factor i.e. trap states in the oxide (as shown in Fig. 1.15). For power electronic applications where the reliability of the device is crucial, this drawback is very undesired and necessary to be eliminated.

Also, this device has a positive temperature eect (ON-state resistance is increased by increasing the temperature) [15]. Usually, the surface conduction transistors are based on pseudo-intrinsic substrates, therefore there is no optimization of the doping concentration relatively to voltage breakdown mechanisms.

Bulk channel FET As shown in Fig. 1.13b, a depletion mode transistor can also be realized by controlling the SCR in bulk of epilayer. To realize an eective bulk controlled FET, one needs to rstly master the issues related to epitaxial growth, dopant incorporation and also high ionization energy of the dopant levels. However, since all of the superior physical properties of diamond that we discussed above are related to bulk diamond, a bulk controlled diamond FET is highly desired.

Umezawa et al. [16] realized a bulk controlled diamond MESFET by using oxygen terminated boron doped diamond. Top view structure and cross-section structure of this boron doped diamond MESFET are shown in Fig. 1.17.

Device electrical characteristic is shown in Fig. However, there are two problems with the boron doped bulk controlled diamond MES-FET. The rst problem is related to the versatility of gate bias. Since the gate is formed by a Schottky diode, there are generally a small threshold voltage in the forward regime.

Therefore, gate of the transistor is only able to be biased from around 0 V to positive bias (to prevent gate leakage current in the transistor to allow electrostatics controlled diamond epilayer). Therefore, the accumulation regime in semiconductor is not obtainable. This problem can be important in the moderate voltage application (around 1 kV) where channel length is approximate gate to drain distance. Another problem with MESFET is related to reverse current at the Schottky contact between metal gate and diamond. As discussed in Traore PhD thesis [START_REF] Traoré | High power diamond Schottky diode[END_REF], reverse current in diamond Schottky diode is controlled by thermionic-eld emission. By increasing diamond doping concentration, electric eld in reverse bias is being steeper. The typical thermionic emission current in an ideal Schottky diode will be enhanced by the tunneling current occurs at the thinner extension part of the potential barrier. Therefore, in order to prevent reverse leakage current, a low doped drift region of 10

Q A SC (Ψ s ) = ± 2ε sc qN A
kT q e -qΨs/kT -1 + Ψ s + kT q e q(Ψs-2Ψ b )/kT 1/2

(1.22) where Ψ s is the semiconductor surface potential, Ψ b is bulk potential which is dened as potential dierent between intrinsic Fermi Level and Fermi Level in the neutral part.

Semiconductor surface potential Ψ s is dened as the potential dierence between surface and neutral part of semiconductor. The (+) and (-) sign correspond to the positive charge of the hole in accumulation regime (Ψ s < 0) and negative charge of electron in inversion regime (Ψ s > 2Ψ b ), respectively. In an ideal p-type semiconductor system, by biasing gate metal from negative bias to positive bias, semiconductor surface potential and semiconductor charge are being driven into dierent regimes:

Insulator p-Semiconductor E v E f E c ψ s Q sc ∼ e -qψ s /kT E f V g <0 Accumulation p-Semiconductor ψ s < 0 E v E f E c Depletion Q sc ∼ ψ s E f V g >0 p-Semiconductor ψ s > 0 E v E f E c E f C s(FB) = ε s ε 0 λ p λ p = ε s ε 0 kT q 2 N A ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ 1/2 Flatband p-Semiconductor V g =V FB E v E f E c ψ s = 0 a)! b)! c)! d)! E fi! qψ b
1. Accumulation: When a negative gate bias is being applied, semiconductor surface band energy is bent upward. Majority carriers are being accumulated at semiconductoroxide interface, as shown in Fig. 1.20c. Semiconductor charge Q sc (equation 1.22) can be approximated as:

Q sc ∼ e -qΨs/
C s(F B) = ε sc ε 0 λ p (1.26)
With λ p is the semiconductor intrinsic Debye length and be calculated as: In 2015, Kovi and co-authors [20] at Uppsala University 5 also reported the results on oxygen terminated boron doped diamond MOS capacitor. They employed the identical structure and varied the epilayer doping concentration (from 10 17 cm -3 to 4×10 19 cm -3 ).

λ p = ε s ε 0 kT q 2 N A 1/
They obtained similar electrical characteristics than Chicot et al. [18]. Test devices exhibit a strong leakage current and strong capacitance-frequency dependent. The authors claimed they observed the minority carriers inversion on the fact that gate leakage currents were signicant [20] . This architecture allows Al 2 O 3 to be deposited at higher temperature (as high as desirable and within the limit of the apparatus). Gate leakage current and capacitance-frequency dependent were greatly reduced, but still existing.

By performing the X-ray Photoemission Spectroscopy (XPS) measurement, type-I band alignment between O-Diamond/Al 2 O 3 was determined [19] and shown in Fig. (c)! From the transistor point of view, a proper unipolar boron doped diamond MOSFET by controlling bulk diamond is still not accomplished at the beginning of this PhD study. Chapter 1. Boron doped diamond semiconductor for unipolar power devices

Conclusion

Diamond is a fascinating semiconductor with multiple superior physical properties for power electronics devices. However, a 2DHG surface channel diamond MOSFET is seemly not sucient to fulll all the potential. Controlling the bulk of diamond to realize a transistor is therefore crucial.

The objective of this thesis is the realization of a bulk controlled boron doped diamond MOSFET for power device applications. The scope of this thesis is ranging from the fundamental investigations the test device MOS capacitors structure and then realization a diamond MOSFET. This thesis is devoted to address the following issues:

i) The reliability of C-V measurements and eliminate the artifacts.

ii) How to access critical information on diamond semiconductor like surface potential, semiconductor charges, space charge width and its variation with gate bias?

iii) What is the origin of leakage current in both forward bias and reverse bias direction? What is the origin of capacitance-frequency dependent in both forward bias and reverse bias? Is it minority carriers inversion observed by Kovi et al [20]? iv) From the understanding of the MOS capacitor test devices, is it possible to realize a diamond MOSFET by controlling the bulk of diamond? How about the performance and the potential of this transistor?

This manuscript will answer to the mentioned questions by two main chapters: High frequency-capacitance method is being applied to quantify interface states density.

Electrostatics model based on dierent charge components is constructed. Electrostatics band diagram will be introduced and the limit of this model will be discussed.

Part 2: This part is devoted to elucidate the origin of leakage current of MOS capacitors under negative bias. The origin of capacitance-frequency dependent will be discussed. Interface states density will be re-evaluated by using the conductance method with DC current contribution being subtracted. With the interface states density from conductance method, a complete electrostatics simulation will be introduced and compared with experimental results by mean of semiconductor surface potential.

Part 3: This part is devoted to investigate the origin of gate leakage current when MOS capacitors are under positive bias. Device characteristics-substrates prole correlation will be mentioned. Relationship between leakage current and capacitancefrequency dependent when MOS capacitors are under positive bias will be elucidated.

Origin of the so-called inversion will be discussed.

Chapter 3: This chapter is devoted to introduce the proof of concept of a bulk controlled boron doped diamond MOSFET. We will introduce our approaches to realize a bulk controlled boron doped diamond MOSFET working in depletion mode. The performance of this device will be presented and demonstrated a complete electrostatic gate controlled boron doped diamond MOSFET. Along with the MOSFETs, dierent test devices such as MOS capacitors, TLMs were also fabricated and will be presented. The combination of MOSFETs with test devices and 2D nite element simulations allows us quantify the critical parameters of the MOSFET like contact resistance and carriers mobility. This device will be benchmark for the purpose of comparison with other diamond transistor and will be projected toward device optimization.

Finally, conclusions and perspectives of this work will be given.

C and experiment results by mean of semiconductor surface potential will be discussed.

Part 2: From the electrostatics band diagram, the origin of leakage currents when O-diamond MOS capacitors are under negative bias (forward current) will be elucidated in this part. A special attention will be paid to the relationship between forward current and interface states. We will also discuss dierent aspects related to the leakage current such as the limiting processes and the thermal activation processes. Equivalent circuit will be introduced and dierent approximations will be employed to simplify the model.

Conductance method by using the equivalent circuit and subtracting the DC current is employed to extract interface states density. The relationship between DC leakage current and a.c signal measurements will be claried. A complete electrostatics model will be presented.

Part 3: We discuss the leakage current when the MOS capacitor is under positive bias (reverse current). The relationship of reverse current with substrate imperfection will be claried by mean of combination electron beam microscope measurements. of diamond devices will be high. As shown in Fig. 2.1a, by using the lateral structure without a metallic p+ layer [18], a considerable series resistance in the MOS capacitor is expected since all the current is owing in the incomplete ionized semiconductor p-layer [22]. Another problem with lateral structure [18] is the limitation of ALD temperature.

Due to the photoresist layer on top of diamond substrate, temperature of ALD chamber have to be limited at around 100 • C (to prevent damaging the photoresist layer).

In order to solve the mentioned problems, we employed the pseudo-vertical structure [13] with a metallic diamond layer on the back side of the epilayer. With this metallic p+ layer, most of the additional ON-state resistance is localizing in metallic p+ layer, as shown in Fig. 2.1b. Comparing to the lateral structure in Fig. 2.1a, where most of the additional ON-state resistance is localizing in the p-layer, the pseudo-vertical structure is expected to have a much lower series resistance. The pseudo-vertical MOS capacitor is rstly presented in Marechal et al. [19] and his PhD thesis [24]. This structure will be used for all MOS capacitor test devices in this chapter. ) is inserted at the bottom of p-diamond epilayer (10 17 cm -3 ).

a)! b)!

Both layer were homoepitaxially grown on top of a diamond substrate.

Substrates and cleaning substrates

The 3×3 (mm×mm) High Temperature High Pressure (HTHP) Sumitomo (100) diamond substrate is used to grow the diamond epilayer. C o n d e n t i a l 2.1. Methodology 37 Prior to the growth, the substrate is cleaned by a standard cleaning process. In a rst step, the substrate is cleaned with solvent (acetone, ethanol, DI water) in ultrasonic to remove dust and surface contaminations. In a second step, the substrate is immersed into a mixture acid solution of HClO 4 :HNO 3 :H 2 SO 4 (1:4:3) at 250

• C during 30 minutes to remove carbon-phase and graphite on the diamond surface. Recipe parameters for the growth of p+ layer and p-layer are illustrated in Table 2.1.

During growth, the thin lm's parameters such as thickness and doping concentration are followed by the in-situ ellipsometry spectroscopy [START_REF] Bousquet | Spectroscopic ellipsometry of homoepitaxial diamond multilayers and delta-doped structures[END_REF]. More details on diamond epilayer growth and doping controlled can be found in the Fiori's PhD thesis [4]. The corresponding top view structure for each step is also given. Photoresist (S1805) is rstly coated on top of the substrate by using spin coating. A Heldelberg DWL66FS laser lithography instrument is employed to dene contact area, as shown in Fig. For the a.c measurements (impedance/admittance/capacitance), a small a.c signal with an amplitude voltage of V ac =20 mV is superimposed the DC signal (Fig. 2.12a).

Electrical measurements were performed thanks to the electrical characterization platform in our group, as shown in Fig. 2.11b.

Capacitance-frequency measurements

Small signal a.c measurements were performed by ModuLab XM MTS 2 . One of the most remarkable feature of this equipment is the concept of multisine/Fast Fourier Transform (FFT) impedance measurement in a wide frequency range (from µHz to MHz). Figure 2.12b represents the Solartron modulab and the accessories in our lab.

As shown in Fig. 2.12a, in order to measure the impedance of a system, a small sine wave a.c voltage is superimposed to the input in order to measure the a.c current at the output. To examine the response of a system against frequency, one usually performs dierent single measurements at dierent xed a.c frequencies (i.e. C-V at dierent

MOS fabrication using diamond semiconductor

The main problem to fabricate a MOS structure is to achieve the semiconductor oxide interface with a sufficiently low interface states density. In that case, the different regimes of the MOS can be controlled: accumulation of majority carriers, depletion, deep depletion or inversion of carriers. In most cases and contrary to the Si/Oxide interface, the too large density of interface states within the gap are charging under bias voltage, and the breakdown field of the oxide is reached before a)! b)! The multisine/FFT concept is based on generating and composing dierent sine waveforms into one measurement, as shown in Fig. 2.13. After that, by using the fast Fourier transform technique, the data on time domain (voltage and current samples collected over a period of time) are converted into the frequency domain (analyzing the frequency content of the signal and presenting impedance v.s frequency data). By using this concept, we are able to measure the response of a system against a wide frequency range, at dierent xed gate bias. This is the C-f measurements that we will present in the following parts. Since the a.c measurement is performed at xed gate bias, there is no DC degradation due to the biasing cycles. It is worth mentioning that this measurement in fact took a few seconds to be completed. Therefore, C-f measurement is appropriate to examine the response of a system against frequency. In our a.c measurements, we employed the frequency range from 1 Hz to 1 MHz. By further decreasing the frequency, the impedance of the system is increased rapidly while we did not observe further interesting phenomena.

Impedance measurement circuits

In principle, an impedance meter is measuring:

Z = Z + jZ (2.1)
where Z = Re(Z) the real part of impedance and Z = Im(Z) the imaginary part of impedance, j is the purely imaginary complex number (j 2 = -1).Then, depending on the conguration used in the software, the system is able to plot dierent parameters like C, L or R. However, the assumptions are needed to convert Z = Z + jZ to C, L and R. The most used circuit is the parallel circuit C p -R p , as shown in Fig. 2.14b. Admittance of this C p -R p circuit is:

Y = Y + jY = 1 R p + jωC p = G p + jωC p (2.2)
C o n d e n t i a l 2.1. Methodology 45

C1 ! 100 pF! C2 ! 10 nF! R! 100 kΩ! C s! R s! Cox Csc Rs ψ s R p! C p! C m! a)! b)! c)! d)!
C p -R p circuit; c) C s -R s circuit; d) C m circuit.
Which is equivalent to the inverse of measured impedance. This relationship can be expressed as:

1 Z = 1 Z + jZ = Y (2.3)
By conjugate multiplication, equation 2.3 is then equivalent to:

Y = Z -jZ Z 2 + Z 2 (2.4)
The parallel capacitance C p and the parallel conductance G p is then calculated as:

C p = Z Z 2 + Z 2 1 ω (2.5) G p = Z Z 2 + Z 2 (2.6)
By using the series C s -R s conguration (Fig. 2.14c), the series capacitance C s and series resistance R s can be directly evaluated as:

C s = 1 ωZ (2.7) R s = Z (2.8)
For C m conguration (Fig. 2.14d), the measured impedance is considered to be purely capacitive and C m can be calculated as:

C m = 1 |Z| 1 ω (2.9)
We employed the calibrated test circuit (Fig. 2.14a) provided by Ametek Scientic

Instruments to determine the measurement circuit used by Solartron Modulab.

The measured capacitance of the calibrated test circuit is compared with dierent measurement conguration, as shown in Fig. 2.15. This measurement illustrates that Solartron Modulab is using the C m conguration (Fig. 2.13d) to measure the capacitance.

The data can be converted to parallel circuit C p -R p or series circuit C s -R s by the above procedure (Fig. In the following sections, by dierent experimental approaches, we will gradually determine the parameters for an empirical electrostatics simulation. The simulation results will be compared to experiment results by mean of semiconductor surface potential Ψ s .

C-V characteristic of an ideal MOS capacitor

We rstly present the C-V characteristics of an ideal p-type Si/SiO 2 MOS capacitor. In C o n d e n t i a l

48 By sweeping the gate potential from negative bias of accumulation regime toward positive bias, semiconductor is driving toward depletion regime (Fig. 2.17). In depletion regime, semiconductor Space Charge Region (SCR) width and corresponding semiconductor capacitor C sc will be created. Capacitance of the MOS capacitor is equivalent to series oxide capacitor and semiconductor capacitor C M OS = CoxCsc Cox+Csc .

By further biasing in positive direction, semiconductor reaches inversion regime once Ψ s > 2Ψ b where Ψ b is the bulk potential. Capacitance of the MOS capacitor is now depending on applied frequency. At high frequency, C min value is obtained since the SCR extension is now negligible. Once the applied frequency is equivalent or lower than the minority carriers generation time constant (see the discussion below), inverted minority carriers will be able to participate to the dierential capacitance. Measured capacitance will increase with the decrease of frequency, as shown in the top inset of Fig. 2.17.

Once the applied frequency is suciently low, all minority carriers accumulate at the oxide/semiconductor interface. The surface of semiconductor is again like a metal with the inverted carriers. Capacitance of the MOS capacitor will be equivalent to the oxide capacitance C M OS = C ox .

In Si/SiO 2 MOS capacitor, the ideal C-V characteristics are obtained experimentally thanks to the low interface states density at Si/SiO 2 interface, i.e. the order of 10 10

(1/eV.cm 2 ). In any other MOS capacitor test devices, once the interface states density at oxide/semiconductor interface is high, numerous problems can be generated. Probably, the most serious problem is the lack of control of semiconductor population by gate bias.

Subsequently, MOSFET will not work or it will work in an uncontrolled manner. Interface states also aect the C-V measurements of MOS capacitor test devices at dierent frequencies (see the discussion below). Therefore, interpreting the measurements will be challenging and bearing some possible of misinterpretations.

Along with interface states, there are also dierent potential artifacts that can aects the MOS capacitor test devices measurements, i.e. oxide xed charges, oxide mobile charges, series resistance, gate leakage current, and even the combinations among them.

Therefore, distinguishing the artifacts and their origin, and accurately quantifying them are crucial for a comprehensively understanding as well as any further improvement. This is the ultimate methodology of this chapter, which is dedicated to the understanding of the O-diamond MOS capacitor test devices. We will rstly examine the general electrical behaviors, distinguish the contributions from artifacts and rene our examination windows. Then, we will gradually quantify the artifacts which could potentially aect our device. Finally, the empirical simulation will be performed to compare with experimental results.

Electrostatics of O-diamond MOS capacitor 2.2.1 I-V and C-V characteristics

Hereinafter, we will mostly present the results measured from MOS 12, sample #1 (Fig.

2.10

). Thanks to the systematic measurements that will be presented later, we show that these measurement results are general, scalable and reproducible. Forward current and reverse current are the DC current measured for forward bias and reverse bias, respectively. A similar specication is also applied to C-V measurement.

As shown in Fig. 2.18a, the forward current is clearly observed. This behavior is similar to the previous reports [18,20,19]. One noticeable improvement in this work compared to previous works [18,20] is the current density. The leakage current is about two orders of magnitude lower than previous reports [18,20]. We assign this improvement to the improved Al 2 O 3 being deposited at high temperature (250 • C). For this MOS capacitor, reverse current is under detection limit. However, this behavior is not general.

We will address the reverse current issues in the part 3 of this chapter.

E C m /C ox Gate Bias (V) a)! b)! V G : +8V to -8V! @RT! V G : +8V to -8V! f: 100 kHz! V ac = 20mV! @RT! C m /C ox! Figure 2.18: a) Typical I-V characteristics of O-diamond MOS capacitors for -8V≤ V G ≤ +8V ; b) C-V characteristics of O-diamond MOS capacitor measured by biasing V G : +8V to -8V at f =100 kHz and V ac =20 mV (MOS12 -Sample #1)
Figure 2.18b represents the C-V characteristic by applying the bias at same range as in I-V measurement. The superimposed a.c frequency is f = 100 kHz and the amplitude V ac =20 mV. We remind that the V ac = 20 mV is constantly used for all a.c measurements in this thesis. A maximum measured capacitance of C m = 0.135µF.cm -2 at V G = -8 V has been obtained. Measured capacitance has been normalized to the oxide capacitance C ox in Fig. 2.18b. C ox was measured from MIM capacitor test devices on the same substrate. Capacitance (µF/cm 2 )

Frequency (Hz) 2. The measured capacitance in reverse regime does not show the saturation of minimum capacitance C min . As long as a more positive bias is applied (up to +14 V, sample 1), the measured capacitance is further decreased. C o n d e n t i a l 52 4. By varying the frequency, measured capacitance of this MOS capacitor has shown dierent features. In the next section, we will discuss the capacitance-frequency characteristics of O-diamond MOS capacitor under negative bias.

-4 -3 -2 -1 0 1 2 3 4 2x10 -1 4x10 -1 6x10 -1 Capacitance (µF/cm 2 ) Gate Voltage (V) MIMCAP! V ac = 20 mV! V G =-3 V! @RT! MIMCAP! f = 100 kHz! V ac = 20 mV! @RT! a)! b)!

Capacitance-frequency characteristics

As dened in previous section, Cf measurement is performed by xing the gate bias and sweeping the frequency. By that method, we are able to examine the response of the system versus frequency. We will now consider the capacitance-frequency characteristics. A special interest is paid to capacitance-frequency dependent behavior. As it is well-known, series resistance and interface states are usually responsible for this eect [START_REF] Kevin | Mos capacitance measurements for high-leakage thin dielectrics[END_REF].

V G =-8V! V G =-4V! V G =-2V! V G =-8V! V G =-4V! V G =-2V! a)! b)! Capacitance C m (μF/cm 2 )" MOSCAP! MIMCAP! MOSCAP! V ac = 20mV! @RT! V ac = 20mV! @RT!

Series Resistance

Z (ω→∞) = R s + 1 jωCs R s and consequently, measured capacitance C m C m(ω→∞) = 1 ωZ = 1
ωRs is actually originated from series resistance.

From the C-f curves in Fig. 2.23a, we conclude that the series resistance eect at high frequency (1 MHz) is not important. Only a small capacitance variation is observed in this frequency range.

Series resistance can be quantied by using the impedance spectroscopy. As mentioned above, at high frequency, the capacitors are shorted and the real part of impedance Re(Z) is equivalent to series resistance Re(Z) = R s . From Nyquist plot Re(Z) vs. Im(Z) (Fig. 2.25a) and Re(Z) vs. f plot (Fig. 2.25b), a series resistance of R s = 702 Ω was extracted.

Another potential problem from series resistance in our MOS capacitor is the voltage drop in p-epilayer. For a highly resistive epilayer, the potential drop on epilayer could be elevated when the device is under high injection regime/high leakage. This potential drop could limit the gate bias possibility to modulate the semiconductor in high injection regime. Therefore, series resistance could be the origin of the C m << C ox eect we observed in the C-V curve (Fig. 2.18b). We conclude that the series resistance has no considerable eects on our pseudovertical O-diamond MOS capacitor test device. This is achieved thanks to the metallic diamond p++ layer, as demonstrated in Fig. 2.1b.

C ox C sc R s ψ s C ox C sc R s R ss C ss ψ s a)! b)! Cit! Rit!
R s × I DC 1 mV at V G = -8V ) is evaluated. V G =-8V! V ac = 20mV! @RT!

Interface State

Interface imperfections generally leads to localized states in the bandgap of semiconductor located at the interface between oxide/semiconductor interface. Interface states communicate with semiconductor conduction band (E C ) and/or valence band (E V ) by capture and/or emission of free carriers [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF]. In a MOS capacitor, interface states can have both a.c eects and DC eects.

For the sake of simplication, we rstly consider a single level interface state with density N it located at E it -E V in a p-type semiconductor. Electron occupancy function of the trap states is described by Fermi-Dirac function:

f = 1/ 1 + exp E -E F kT (2.10)
Where k is the Boltzmann constant, T the temperature and E F the Fermi level. Communication between trap states and band edges is represented by a characteristics time constant τ . Here, we will focus on communication process of majority carriers for sake of clarication. The charge transfer process between interface states and Valence band is either the interface states capture a hole from the Valence band (capture) or interface states emit a hole to the Valence band (emission).

The emission time constant is calculated as [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF].

τ = 1 σ p υ t N v X n exp E t -E v kT (2.11) C o n d e n t i a l 2.

Electrostatics of O-diamond MOS capacitor 55

Where σ p is the capture cross section of the trap states and υ t is the mean thermal velocity of majority carriers, X n is the entropy factor and N V is the density of states of valence band.

The capture time constant is described as [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF].

τ = [σ p υ t p s ] -1 (2.12)
where p s is the hole density at the semiconductor surface.

For the a.c eect, in an ideal MOS capacitor system, interface state is modeled by a series R it C it with a specic time constant dened as τ = 1 R it C it . An impedance equivalent circuit with the contribution from interface states is shown in Fig. 2.24b [85][86]. Once interface state time constant is close to the small a.c signal frequency f

1 2πτ
, [START_REF] Brammertz | Characteristic trapping lifetime and capacitancevoltage measurements of gaas metal-oxide-semiconductor structures[END_REF],

interface states start to contribute to the total measured impedance. The measured impedance and subsequently measured capacitance will be deviated by this contribution.

Depending on interface states density, by further decreasing the frequency, more interface states will be able to contribute to the total impedance. Hence, capacitance of the system will increase until all the interface states are able to respond to the a.c signal. This is the idea of high-low frequency method [START_REF] Cn Berglund | Surface states at steam-grown silicon-silicon dioxide interfaces[END_REF] to quantify the interface states density.

Therefore, interface states can be the origin of the capacitance-frequency dependence at low frequency.

Along with interface state, there are also dierent artifacts which could aect the capacitance measurement at low frequency range. For example, in III-V/high-k MOSCAP system, the capacitance frequency dependence is assigned to either border traps [89][90] or disorder induced gap states [91][92]. DC gate leakage current can also induce the capacitance-frequency dependence at low frequency [START_REF] Lu | Leakage current eects on cv plots of high-k metal-oxide-semiconductor capacitors[END_REF]. Subsequently, the C-V measurement using a low frequency may include many artifacts and will be strongly deviated from the ideal MOS capacitor conguration, i.e. C ox , C sc in series.

Along with a.c eects, interface states can also have DC eects. When Fermi level is crossing the interface state, the capture and emission are equivalent to the charge and discharge of interface states. Once interface states density is high, Fermi level needs to fully charge interface states before moving to the next energy level [94][95]. This process caused the Fermi Level Pinning Eect (FLPE) and it could be at the origin of insucient gate control semiconductor in accumulation region (C m << C ox in Fig. 2.18) .

Proper C-V measurement

From the discussions on capacitance-frequency dependence on a MOS capacitor, the following conclusions can be drawn:

1. Series resistance can aect the capacitance measurements at high frequency. However, in our pseudo-vertical MOS capacitor test devices, its contribution is minor.

Capacitance measurement at low frequency may include many artifacts and can

be strongly deviated from an ideal MOS capacitance conguration.

In fact, all of the above analysis can be seen from the Cf measurements in Fig. 2.23. At dierent gate bias (V G = -8V, -4V, -2V ), three regimes in the C-f curves can be observed: i) High frequency (about MHz): There is a minor eect from series resistance.

C o n d e n t i a l 56 ii) Low frequency (about 10 kHz to 1 Hz for V G = -8V ; about 3 kHz to 1 Hz for V G = -4V and almost negligible for V G = -2V ): Measured capacitance is strongly frequency dependent. Capacitance is increased one decade for one decade frequency.

In the previous reports on O-diamond MOS capacitor [18][20], capacitance frequency dependence of the low frequency range is huge. In Kovi et al. [20], the low frequency range is even observed up to few MHz.

iii) Proper frequency (the regime between high frequency and low frequency): the measured capacitance is constant with frequency. This frequency window is too low to be aected by series resistance and too high to be aected by interface states. In this frequency window, MOS capacitor is close to the proper MOS capacitor conguration, i.e. only includes oxide capacitor C ox and semiconductor capacitor C sc in series and the measured capacitor of the MOS capacitor is:

C M OS = CoxCsc Cox+Csc .
Therefore, in order to examine the response of semiconductor versus gate bias, capacitance measurements are necessary to be performed in this frequency window. In this work, we systematically perform the C-f measurements to predene frequency window for the proper C-V measurements, e.g. Fig.

C 2 vs. V G ). The term 1 C 2 m -1 C 2 ox
is used to eliminate the eect from oxide capacitance [START_REF] Pierre R Muret | Comprehensive characterization of interface and oxide states in metal/oxide/semiconductor capacitors by pulsed mode capacitance and dierential isothermal capacitance spectroscopy[END_REF]. The 1 C 2 -V G curve exhibits an almost perfect straight line for the gate voltage ranging from V G =-6V to V G =8V. From the slope of the curve, the doping concentration of semiconductor layer can be extracted by using the equation:

N A = -2 εε 0 A 2 1 dC 2 /dV (2.13) with ε = 5.7 is the diamond dielectric constant, ε o is the vacuum permittivity and A is the area of the diode. A doping concentration of N A = 3 × 10 17 cm -3 is extracted from the 1 C 2 -V G curve.
This value is almost identical with the target value expected from the diamond growth parameters.

Systematic measurements 5 demonstrated the homogeneous dopant incorporation in diamond epilayer. As shown in Fig. 2.27, by using the Schottky-Mott plot, the doping concentration N A on sample #3 has a very small variation (from 1.6×10 17 cm -3 to 1.9×10 17 cm -3 ) and very close to the target doping concentration (2×10 17 cm -3 ).

Oxide charges

Another feature can be seen from the C-V curve and 1 by the interface charges, the oxide charges and the work function dierence between metal and semiconductor. However, since our C-V measurements were performed at 100 kHz, we excluded the a.c contribution from the interface state charge. Also, the slope of 1

C 2 -V G curve
V FB N A = 3 × 1 0 1 7 c m -3 V FB! N A = 3 × 1 0 1 7 c m -3 ! V G : +8V to -8V! f: 100 kHz! V ac = 20mV! @RT!
C 2 -V G
in the range of examination has reliably reected diamond doping concentration. The DC contribution of interface states is also negligible. Therefore, we conclude that the shift of atband voltage V F B is the work function dierence between metal and semiconductor Φ M S and the net oxide charges Q ox .

Technically, V F B is evaluated from the linear tting of the 1/C

Q ox = C ox (φ M S -V F B ) qAt ox (2.14)
A net positive oxide charge density of Q ox = 6 × 10 18 (cm -3 ) is obtained.

Gate controlled diamond semiconductor

As mentioned in chapter

(V G = V F B ) and consequently semiconductor capacitance C sc (V G = V F B
) is a function of semiconductor intrinsic Debye length as:

C sc (V G = V F B ) = ε sc ε 0 λ p (2.15)
Where λ p is the intrinsic Debye length of semiconductor and it depends on doping concentration N A as λ p = εscε 0 kT q 2 N A 1/2 .

Since N A was extracted from the previous section, semiconductor atband capacitance C sc (V G = V F B ) can be calculated. Subsequently, atband capacitance of MOS capacitor C M OS (V G = V F B ) can be evaluated as:

1 C M OS (V G = V F B ) = 1 C ox + 1 C sc (V G = V F B ) (2.16)
From these relationships, a MOS capacitor atband capacitance of C M OS (V G = V F B ) = 0.279 µF.cm -2 had been evaluated for the MOS12-sample #1. In fact, the maximum measured capacitance of MOS capacitor at V G = -8V is lower than atband capacitance (C m (V G = -8V ) = 0.135 µF.cm -2 ). This is indicating that diamond is always in depletion regime even for high negative bias (V G = -8V ). This is an important conclusion which is opposite to the previous conclusions from Chicot's PhD thesis [22] and Kovi et al. [20].

Since diamond is always in depletion regime in the measured range, semiconductor SCR is proportional to the square root of surface potential Ψ s [17] in the whole voltage C o n d e n t i a l 2.2. Electrostatics of O-diamond MOS capacitor 59 range (+8V to -8V). Therefore, the semiconductor capacitance is also proportional to the square root of semiconductor surface potential as [START_REF] Edward H Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]:

C s = qN A ε o ε s 2Ψ s (2.17)
As measured capacitance C m and oxide capacitance C ox are known, semiconductor ca- pacitance C sc and semiconductor surface potential Ψ s can be calculated. By performing a simple mathematical derivation of equations 2.16 and 2.17, surface potential corresponding to a gate bias can be deduced by:

Ψ s (V G ) = q 2 N A ε o ε s Cox Cm -1 2 2C 2 ox (2.18)
In principle, by performing this calculation at dierent gate bias, we can establish the relationship between semiconductor surface potential against gate bias (Ψ s -V G ), and so evaluate the eciency of gate control semiconductor.

Gate Bias(V)

Insulator p-Diamond In fact, this is the reason why we were not able to observe the C min as in the ideal Si/SiO 2 MOS capacitor. Also, as we will shown in the part 3 of this chapter, by decreasing the frequency to lower than 10 Hz, no sign of minority inversion were observed. This is reasonable considering the fact that generation time constant of minority carriers between valence band to conduction band is very large in wide bandgap semiconductors. For diamond with the bandgap of E g =5.5 eV, the quickest characteristics generation time constant of minority carriers via a midgap state (E c -E t = Eg

ψ s E f E v E c Insulator p-Diamond ψ s E f E v E c a)! b)! V G : +8V to -8V! f: 100 kHz! V ac = 20mV! @RT!

2

) can be approximated as:

τ = 2 × 1 v th σ e N v e Ec-Ev 2k b T ≈ 10 37 (sec) ≈ 10 30 (years) (2.19)
With v th the mean thermal velocity of carriers, N v the equivalent density of states of valence band, σ e is the capture cross-section of a defects in midgap with typical magnitude of 10 -16 (cm -2 ).

Practically speaking, with this minority carrier generation time constant, minority carriers inversion is not reachable at thermal equilibrium. Therefore, a source of minority carriers [14] is needed to observe the inversion regime in a diamond MOS capacitor. This is an important dierence with respect to narrow bandgap semiconductors. Regarding silicon and other narrow bandgap semiconductors, generation time constant of minority carriers is of the order of seconds. As a consequence, the deep depletion regime in narrow band gap semiconductor will be very dicult to obtain. On the another hand, deep depletion is obtained in diamond semiconductor. The dierence between diamond and other narrower band gap semiconductor is that this deep depletion regime is permanent, and does not change with time. This concept will opens a new path to realize a bulk controlled diamond MOS transistor.

Depletion width vs. gate bias

From Ψ s -V G relationship, the SCR (W) width variation with V G can be calculated by:

W = 2ε sc ε 0 Ψ s qN A (2.20)
Figure 2.29 represents the SCR width of boron doped O-diamond versus V G . An eectively gate controlled diamond SCR width is obtained. This property will be very useful to realize a depletion mode diamond MOSFET (Chapter 3).

Interface states density extracted by Terman method

In this section, we will focus on the high negative gate bias part of the Ψ s -V G curve where the FLPE is remarkable. As we have discussed in previous part, FLPE is probably related to the interface states at semiconductor-oxide interface. Therefore, the relative movement of semiconductor Fermi level with gate bias could potentially represents the density of interface states in the gap [99][97]. This is the main idea of high frequencycapacitance method (Terman method) to extract the interface states density [START_REF] Lewis M Terman | An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[END_REF]. With By evaluating dΨs dV G , interface states capacitance can be calculated by:

C it (Ψ s ) = C ox dΨ s dV G -1 -1 -C s (Ψ s ) (2.21)
Subsequently, the interface states density can be evaluated by [START_REF] Edward H Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]:

C o n d e n t i a l 62

D it (Ψ s ) = C it (Ψ s ) q (2.22)
Figure 2.30 represents the interface states density at diamond/oxide interface evaluated by Terman method [START_REF] Lewis M Terman | An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[END_REF]. From Terman method [START_REF] Lewis M Terman | An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[END_REF], an interface states density of less than 10

12 1/eV.cm 2 is found in the midgap region and an abrupt increase up to 4 × 10 13 (1/eV.cm 2 ) for the interface states near the valence band (E t -E v ≈ 0.6 eV).

We will discuss in more details these results, but a rst quick evaluation of emission time constant (equ. 2.11) shows that interface states with E it -E v > 1 eV should not be observed for our DC voltage sweeping rate (100 mV/s)

Electrostatics simulation

As semiconductor charge qN A , oxide charge Q ox and interface states density D it have been experimentally determined, an empirical electrostatics simulation can be performed. We performed the electrostatics simulation by implementing the semiconductor charge qN A extracted from 1 The electrostatics simulation is relatively in agreement with experiment results for the gate bias range (-6V ≤ V G ≤ +2V ). However, when gate bias are out of that range, there is a discrepancy between experiment results and simulation results.

C 2 -V G curve, oxide charge Q ox extracted from shift of V F B
For the high positive bias, we understand that the simulation software performed in the ordinary manner where the inversion regime is assumed. As we have shown previously, this is irrelevant without a source of minority carriers.

For high negative bias, the discrepancy is most probably due to the inappropriate density of the input parameters. Figure 2.32 represents the semiconductor surface potential varying with gate bias obtained from experiments and nextnano simulation in negative bias region. As shown in Fig. 2.32, the semiconductor surface potential from simulation result is re-increased for decreasing V G (V G = -6 V to V G =-8 V). This region corresponds to the crossing of the Fermi level with the elevated interface states density region. Therefore, the discrepancy is highly suspected due to the overestimate interface states density. In fact, in Terman method, the DC leakage current and the non equi- Electric Field (MV/cm) Gate Bias (V) V to V G =-8 V -sample #1) toward a more complete electrostatic model. We will explore the origin of DC current and capacitance-frequency dependent in this bias regime. The eects from interface states will also to be discussed. A more appropriate method will be applied to evaluate the interface states density.

Position (nm) d)! V G = -4V! V G = -2V! V G = 0V! V G = 2V!

Conclusion

Introduction

In the Part 1 of this chapter, we introduced the typical electrical characteristics of a boron doped O-diamond MOS capacitor. We addressed dierent aspects ranging from diamond growth, fabrication processing and electrical characterization. From electrical measurements, a special attention was paid to obtain the crucial information of the MOS capacitor system. Leakage current and capacitance frequency dependent measurements were systematically observed when devices are biased toward negative direction (forward bias). We addressed the eects from serial resistance and interface states. We proposed a method to eliminate these parasitics thanks to the capacitance-frequency (C-f ) measurements. From the proper capacitance measurement, we evaluated the critical information of O-diamond MOS capacitor such as semiconductor doping concentration N A , semicon- ductor surface potential versus gate bias (Ψ s -V G ), semiconductor depletion width versus gate bias (W -V G ) and oxide charge density Q ox . Thanks to the V G -Ψ S relationship, we applied Terman's method [START_REF] Lewis M Terman | An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[END_REF] to extract the interface states density D it . Interface states density exhibit a low density in the midgap region and an elevated density up to 4 × 10 13 1/eV.cm 2 at E it -E v = 0.6 eV.

We implemented the semiconductor charges Q sc , oxide charges Q ox and interface states charges σ it (V G ) into the 1-dimensional nite element electrostatics Nextnano simulation.

A special attention was paid for the forward bias regime (negative bias). The simulation results are compared with experimental results by mean of semiconductor surface potential Ψ S . A quantitative agreement was obtained in the V G range where the gate leakage current is relatively low. Unfortunately, for the V G range where the gate current is high, the deviation between simulation and experiment is considerable.

Many issues are therefore raising. The rst issue is related to the accuracy of input charge densities, especially interface states density D it extracted from Terman method. Since Terman's method was applied without considering leakage current, deduced interface states density could be erroneous. The second issue concerns the origin of forward current and its relationship with electrostatics model. In another words, a method to quantify interface states density while subtracting any contribution from the leakage current is needed. Last but not least, the issue on capacitance-frequency dependence is also considerable. Elucidating the origin of capacitance-frequency dependence and its relationship with leakage current and interface states is necessary. Since interface states, leakage current and capacitance-frequency dependence are critical for the development of any MOS capacitor system toward a MOS transistor, a comprehensive understanding on their behaviors is prerequisite. This part is devoted to address and solve the above mentioned problems. In the rst section, we will re-introduce the general electrical characteristic of the O-diamond MOS capacitors to declare the problems. Then, we propose the forward current mechanism thanks to the electrostatics band diagram. From leakage current mechanism, we construct the physical equivalent circuit linearizing the small signal measurements. Approximated equivalent circuit based on dierent limiting processes will be discussed. Current limiting process is identied thank to dierent approaches. From approximated equivalent circuit, DC current is subtracted and conductance method is applied to quantify interface states density D it . As all parameters of the equivalent circuit have been extracted experimentally, measured capacitance-frequency dependence can be simulated by using C o n d e n t i a l 68 the equivalent circuit. Finite element electrostatics simulation is re-performed to reassess the accuracy of interface state density extracted from high frequency capacitance method and conductance method. In the end, this part will be concluded.

Results and Discussion

Typical electrical characteristics

Considering the ensemble of O-diamond MOS capacitors that have been previously fabricated by our group [18][19], the results published in literature [20] and the devices fabricated in the frame of this thesis, general electrical characteristics can be summarized in Fig. 2.33. The capacitance-frequency dependent phenomena was briey discussed in the Part 1 of this chapter. It can be summarized into three regimes: 1) High frequency: capacitance measurement is aected by series resistance; 2) Proper frequency: no capacitancefrequency dependence; 3) Low frequency: capacitance increased a decade with frequency decreasing a decade. The low frequency range is very dierent considering dierent Odiamond MOS capacitor system, ranging from few kHz in Marechal et al. [19] to few MHz in Kovi et al. [20]. In this part, we will elucidate the origin of the capacitance-frequency dependence in this low frequency regime.

Forward current mechanism

c)!

V ac =20mV! V DC +8V to -6V! @RT! Potentially, the ow at each step may includes dierent processes in parallel. In principle, the process with highest rate (slowest time constant) will dominate the ow at that step. On another hand, in order to complete a circulation, dierent steps in series may be involved. The step with the slowest rate (longest time constant) will limit the ow.

In the proposed current mechanism (Fig. 2 Therefore, the tunneling from gate metal into oxide trap states [START_REF] Seok | Tunneling-assisted poole-frenkel conduction mechanism in hfo2 thin lms[END_REF] is the most realistic process.

The tunneling current from metal to many oxide trap states can be approximately described by [START_REF] Yu | Conduction mechanism of tin/hfox/pt resistive switching memory: a trap-assisted-tunneling model[END_REF]:

I = N t qv (2.23)
where N t is the number of nearest traps that contribute to the conduction and v is the tunneling transmission rate. Tunneling transmission rate is calculated as v = v o .f.T C o n d e n t i a l 72 with v 0 ∼ 10 13 Hz is the attempt frequency which is representing the rate of escape of a particle from a conning structure by quantum tunneling through its outer barrier [START_REF] Peter | Attempt frequency in tunneling[END_REF].

f is the Fermi-Dirac function representing the occupancy probability of a trap state in the oxide. It can be expressed by:

I! II! III! IV! V! E b! V G =-5V ! V G =0V ! E c! E v! E F! E t! E A! E it!
f = 1/ 1 + exp E b -E t + F.t ox kT (2.24)
where E b is the electron barrier between metal electrode and oxide conduction band, E t is the depth of the traps in the oxide, F is electric eld in the oxide and t ox is the oxide thickness (Fig. 2.35). T is the Wentzel-Kramers-Brillouin (WKB) transmission coecient and can be written as:

T = exp - 4 3 qF √ 2m * E 3/2 t -(E t -F.t ox ) 3/2
v = v 0 exp - E c -E t kT (2.26)
where E t is the energy of the traps in the band gap of oxide [108] (Fig. 2.35). In case of Al 2 O 3 oxide deposited by Atomic Layer Deposition (ALD), trap states are usu- ally ascribed to non-stoichiometry of the oxide. Electron trap level which is nearest to conduction band is E c -E t = 1 eV [START_REF] Choi | Native point defects and dangling bonds in α-al2o3[END_REF]. First principle simulation assigned this trap to oxygen vacancies [START_REF] Choi | Native point defects and dangling bonds in α-al2o3[END_REF].

The trap to trap tunneling rate is calculated as [START_REF] Yu | Conduction mechanism of tin/hfox/pt resistive switching memory: a trap-assisted-tunneling model[END_REF] v

= v 0 exp - 2R ξ (2.27)
with ξ is the electron wave function localization length ξ 0.3 nm, R is distance between trap sites [START_REF] Yu | Conduction mechanism of tin/hfox/pt resistive switching memory: a trap-assisted-tunneling model[END_REF].

Distance between trap sites could be obtained by tting the DC non-linearity capacitancevoltage of MIM capacitor [START_REF] Khaldi | Dierences between direct current and alternating current capacitance nonlinearities in high-k dielectrics and their relation to hopping conduction[END_REF]. The DC non-linearity

C V G -C 0 C 0 = ∆C C 0 (variation of MIM
capacitance with gate bias) of MIM capacitor are tted by the equation:

∆C C 0 = a [exp (bV G ) -1] (2.28)
With C V G is the capacitance measurement corresponding to gate bias variation and C 0 is the capacitance corresponding to V G = 0 V. a and b are coecients and their expression will be detailed in next equation [START_REF] Khaldi | Dierences between direct current and alternating current capacitance nonlinearities in high-k dielectrics and their relation to hopping conduction[END_REF]. A complete expression of equation ( 6)

C o n d e n t i a l 74 is:

∆C C 0 = 2 (ε 0 ε) 2n t ox L D 1-2n 1 (2 + ρ) 2(1-n) 1 ω 2n σ 2n 0 × [exp (nqE ef f R/k B T ) -1] (2.29)
with n is an empirical parameters, t ox is the oxide thickness, L D is the Debye length, E ef f is the eective electric eld, ρ is the blocking parameters which measure charge exchange at the electrode 6 . Experimental DC non-linearity The time for carriers readjustment when they are trapped by interface states (Step III), as usual [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF] will be neglected because its thermalization process is very fast compare to other processes.

∆C C 0 versus V G is shown in

Charge transfer between interface states and semiconductor band edges

In the step IV, the trapped electrons at interface states will be emitted to the semiconductor valence band. Considering the single level interface states model with a density N it and a energy E it -E v from valence band, the occupation probability of a trap state by an electron is described by Fermi-Dirac function [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF]:

f = 1 1 + exp E-E F kT (2.30)
Equivalently, the occupation probability of a trap state by a hole is described as:

f p = 1 -f = f exp E -E F kT (2.31)
The hole capture rate is described as:

R p = N it σ p v th f p s (2.32)
and hole emission rate is described by:

G = N it σ p v th f p p 1 (2.33)
with σ p is the hole capture cross-section of the trap states, v th is the carriers mean thermal velocity, p s is the surface carriers density at thermal equilibrium and is described by: 6 see Khaldi et al. [START_REF] Khaldi | Dierences between direct current and alternating current capacitance nonlinearities in high-k dielectrics and their relation to hopping conduction[END_REF] for more details C o n d e n t i a l 2.4. Results and Discussion 75

p s = p b exp -eΨ s kT (2.34)
where p b is the bulk carriers density and can be calculated as:

p b = N v exp E v -E F kT (2.35)
where E F is the quasi-Fermi level and N v is the eective density of states in the valence band. p 1 represents the carrier density that established at the trap states when quasi-Fermi level equals the trap states level [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF] and can be calculated as:

p 1 = N v exp E v -E it kT (2.36)
The charge transfer rate of carriers trapped at interface states with semiconductor bands are described by net ow of carriers captured and emitted in Schockley-Read theory [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF].

U cp = N it σ p υ th (f p s -f p p 1 ) (2.37)
Recombination time constant of majority carriers with interface states is then calculated as:

τ R = 1 σ p v th p b exp(Ψ s ) (2.38)
Injected carriers from gate electrode to interface states and charge transfer of interface states with semiconductor band are described by the dierential equation for occupancy of interface states as [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF] N it df t dt = -U cp + j q .

(2.39)

Where j is the current injected from metal gate to interface state. The current in and out interface states discussed above is described by the interface states occupancy f ss [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF][102] which is approximated by:

f ss = (τ R f m + τ T f s ) / (τ R + τ T ) (2.40)
where f s and f m are the bulk semiconductor and metal occupancies, respectively [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF].

Drift in the diamond layer

The process of electron to be emitted to valence band is equivalent to the process of hole from valence band to be captured to interface states. To replace the evacuated hole, a hole from the back side (p+ layer) will move to diamond surface and be ready for a new capture event [START_REF] Muret | Hole injection contribution to transport mechanisms in metal/p-/p++ and metal/oxide/p-/p++ diamond structures[END_REF]. In reverse direction, electrons are transferring to back gate contact (p+) and complete the circulation.

C o n d e n t i a l In order to model the measured impedance and admittance of a MOS capacitor, linearized equivalent circuit is a well-known concept. Lehovec and Sloboskoy developed a comprehensive theory and derived a general equivalent circuit for the MOS capacitors [START_REF] Lehovec | Impedance of semiconductor-insulator-metal capacitors[END_REF]. Nicollian and Golzberger had paid their special attention to the conductance of interface states in thick oxide MOS capacitor [START_REF] Eh Nicollian | The si-sio2 interfaceâelectrical properties as determined by the metal-insulator-silicon conductance technique[END_REF]. The meaning of thick oxide is that the interface states are in equilibrium and close communication with semiconductor band edges. They also developed a model to evaluate the equivalent conductance G P /ω from C p and G p that consists only interface states density and its time constant [START_REF] Eh Nicollian | The si-sio2 interfaceâelectrical properties as determined by the metal-insulator-silicon conductance technique[END_REF].

For the special case where interface states communicate with both gate metal and semiconductor band edges, Freeman and Dahlke developed a theory as well as derived its corresponding equivalent circuits [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF]. Dierent possible limiting processes were also discussed. The approximations corresponding to each limited case were also done. Since then, there were dierent discussions about the possibilities and opportunities to employ gate tunneling into interface states to measure a wide range of interface states density [START_REF] Card | Conductance associated with interface states in mos tunnel structures[END_REF][102] [START_REF] Ma | Surface-state spectra from thick-oxide mos tunnel junctions[END_REF]. Kar and Dahlke performed the experiments on Si/SiO 2 MOS capacitor with a moderate oxide thickness and a non-degenerate Si semiconductor to investigate interface states thanks to gate carriers injected to interface states [START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF].

In the Part 1 of this chapter, we discussed the equivalent circuit of MOS capacitor in an ideal case where only the unavoidable series resistance were involved (Figure 2.34b) and in case of single level interface states in thick oxide MOS capacitor were taking into account (Figure 2.34c).

Corresponding to the current mechanism in Fig. 2.34a, we introduced the equivalent circuit for our O-diamond MOS capacitor (Fig. 2.34d). Non-perfect gate oxide with gate leakage current is modeled by an oxide conductance G ox and an oxide capacitance C ox in parallel. The ow of carriers from metal to semiconductor is injected to the mid point of the interface states recombination circuit, as proposed by Freeman et al. [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF].

Equivalent circuit approximation

In this section, the O-diamond MOS capacitor general equivalent circuit will be approximated corresponding to dierent limiting processes. We remind that the equivalent circuit in Fig. 2.34d is actually re-introduced in Fig. 2.37a. In the theoretical model of Freeman and Dahlke [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF] and in the experiments and analysis of Kar and Dahlke [START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF],

dierent limiting processes and their corresponding approximations were discussed. We will briey reintroduce these approximations here for the purpose of clarication .

As the drift in semiconductor (step 5) is expected much faster compared to two other processes, we will only consider the interface states recombination limited and the oxide tunneling limited.

Interface-states-recombination-limited The interface states recombination is limited when interface states recombination time constant is much longer than the oxide tunneling time constant (τ R >> τ T ). In other words, the oxide tunneling rate is much higher than the interface recombination rate. The interface states will therefore be in equi-C o n d e n t i a l 2.4. Results and Discussion 77 librium with metal. In this case, the interface states-recombination-limited was found to modify the Schottky barrier height due to the charge being accommodated at the interface states [START_REF] Jl Freeouf | Are interface states consistent with schottky barrier measurements?[END_REF][104] [START_REF] Muret | The inuence of interface states upon the admittance of metalsemiconductor diodes[END_REF]. Therefore, a self-consistent calculation is necessary to be performed in order to not violate the Gauss's law equations, as discussed by Werner et al. [START_REF] Werner | Interface-state measurements at schottky contacts: a new admittance technique[END_REF]. The rigorous self-consistence calculation was done by Muret et al. [START_REF] Muret | The inuence of interface states upon the admittance of metalsemiconductor diodes[END_REF] and also Wegner et al. [START_REF] Werner | Interface-state measurements at schottky contacts: a new admittance technique[END_REF] for Schottky diode with a thin oxide layer.

In case of a MOS capacitor system, the approximated equivalent circuit for the interface recombination limited was introduced by Freeman et al. [START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF] and Kar et al. [START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF]. The approximated equivalent circuit is shown in Fig. A major dierence between interface states recombination limited (Fig. Considering our O-diamond MOS capacitor, as presented in previous sections (Fig.

2.33c and Fig. 2.23), measured conductance is frequency dependent. Therefore, we conclude that the oxide tunneling process is the limiting process. The interface states recombination limited is possible in case of high injection MOS capacitors (e.g. current density ≥ 1 A/cm 2 ). In that case, the carriers injection from metal gate is sucient to preserve interface states in equilibrium with metal gate. The MOS #4 sample in Chicot et al. [18] and the 4 × 10 19 cm -3 doped sample in Kovi et al. [20] are most probably interface states recombination limited case.

Limiting process

As a consequence from the previous analyses, the oxide tunneling process was identied as the limiting process. However, since oxide tunneling is indeed a two step process, further approximation is needed. Bearing in mind that the limiting process for the transport in the oxide is basically either bulk oxide limited process (hopping between traps to traps)

or interface limited process (tunneling from gate metal into oxide trap states). The dierence is due to the nature of contact between metal and oxide, i.e. an ohmic contact or an unsaturated contact [START_REF] Robert | Two-carrier space-charge-limited current in a trap-free insulator[END_REF]. Transport in the oxide is usually bounded between the of Child law Space Charge Limited Current (SCLC) [START_REF] Rose | Space-charge-limited currents in solids[END_REF] is veried in high injection MOS capacitor. For the low injection MOS capacitor, I ∼ V 5 where interface-limited traps assisted tunneling [START_REF] Mahaveer | Thermionic trap-assisted tunneling model and its application to leakage current in nitrided oxides and algan/ gan high electron mobility transistors[END_REF] mechanism is probably governing these low injection MOS capacitor. In order to study the thermal activation process, I-V characteristics were measured at dierent temperatures (from 150K to 360K).

Cm! Gm! a) b) c) d) e) f) g) Cc! Rs! Gc! C c! Rs! Gdc! Gac!
For high injection MOS capacitor, the I-V characteristics at dierent temperatures are shown in Figure 2.39a. Figure 2.39b represents the current density measured at V G = -8 V versus temperature (J-T). The J-T curve is well tted by a e ( T 0

T ) 1/4 law,
which is characteristic of variable range hopping (VRH) [START_REF] Nevill | Electronic processes in non-crystalline materials[END_REF].

For low injection MOS capacitor, the I-V characteristics at dierent temperatures are shown in Fig. 2.40a.

Equivalent conductance G p /ω

Conductance of interface states ( 1 R it where R it is the one of Fig. 2.37) represents the energy loss due to carriers transfer between semiconductor band edge and interface states after a disturbance of a small a.c signal. In more details, it can be understood as the supplied small ac signal in both halves caused the disturbance and drive the equilibrium system between semiconductor band edge and interface states become non-equilibrium.

Therefore, there are carriers transferred between interface states and band edge. However, the carriers transfer is not immediate after the signal was supplied but lag behind and caused the loss. The loss is minimized or conductance is maximized when the applied signal is equivalent to the resonant frequency of the interface states. With the applied frequency lower than the resonant frequency, carriers are stored at the capacitance of the interface states but not transferred. Subsequently, conductance of the interface states is decreased. Therefore, conductance of interface states which is bearing the information of interface states should have a bell shape. For conductance method, the goal is to obtain the equivalent interface states conductance in Fig. 2.37d from measured conductance and measured capacitance in Fig. 2.37g.

In order to obtain the equivalent interface states conductance, measured parallel conductance and parallel capacitance are necessary to be corrected to eliminate the series resistance, the DC current and gate oxide capacitance. The circuit transformation is following the procedure introduced by Kar and Dahlke et al. [START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF] and in Vogel et al.

2.0x10

-11 From the measured conductance and capacitance, the corrected conductance and corrected capacitance with series resistance in Fig. 2.37f is given by:

V G =-8V V G =-7.5V V G =-7V V G =-6.5V V G =-6V V G =-5.5V V G =-5V V G =-4.5 V G =-4 Gp/omega (Cp) Omega (hz) G P /ω (S/sec) ω (1/sec) V ac =20mV! RT! MOS 12 -sample #1!
C c = C p (1 -G p R s ) 2 + ω 2 C 2 p R 2 s (2.41) G c = ω 2 C p C c R s -G p G p R s -1 (2.42)
Then, the G ac in Fig. 2.37e is obtained by subtracting the G c by oxide tunneling conductance G dc as:

G ac = G c -G dc (2.43)
where the conductance G dc is determined from derivation of DC current on DC voltage around the gate bias voltage dI DC dV DC V G .

Then, the ac conductance G ac must be corrected with gate oxide capacitance C ox to obtain the equivalent conductance G P /ω by using the equation:

G P ω = ωC 2 ox G ac G 2 c + ω 2 (C ox -C c ) 2 (2.44)
For the purpose of comparison the interface states density with Terman's method, we will present here the data measured on the MOS 12 on sample #1).

Interface states density

From equivalent conductance G P /ω, interface states density can be calculated as [START_REF] Eh Nicollian | The si-sio2 interfaceâelectrical properties as determined by the metal-insulator-silicon conductance technique[END_REF]:

N it = 2 G P ω max /q (2

D

it (1/eV.cm

2 )

E t -E v (eV)
V ac =20mV! @RT! MOS 12 -#1! The energy level of the trap states is calculated using the equation:

E it (V G ) -E v = Ψ s (V G ) + φ p (2.46)
where Ψ s (V G ) is extracted in the previous chapter and φ p kT q ln Nv N A which is around 0.37 eV in the case of moderate boron doped diamond.

C o n d e n t i a l

Results and Discussion 83

A notable dierence of the interface states density extracted from conductance method compared to the one of Terman's method is the interface states density near the valence band. While the Terman's method shows an elevated interface states density up to 4 × 10 13 (cm -2 ) at E it -E v = 0.6 eV, the results from conductance method are approximately one order of magnitude lower in the same energy range.

This discrepancy is actually due to the gate leakage current. In Terman's method [START_REF] Lewis M Terman | An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes[END_REF], the variation of semiconductor surface potential Ψ S with gate bias V G is completely attributed to the interface states at semiconductor-oxide interface. It is true when leakage current through the oxide is negligible. However, when the DC current is sucient, the potential drop on gate oxide is non-negligible. Therefore, in high injection regime, Terman's method highly overestimates the interface states density.

On conductance method, the contribution of DC current is actually excluded by equation 2.43. Final interface states density will therefore exclude the contribution from DC current. We conclude that the interface states density extracted from conductance method is more reliable than the Terman's method.

Interface states feature

By assuming interface states are single level states [START_REF] Eh Nicollian | The si-sio2 interfaceâelectrical properties as determined by the metal-insulator-silicon conductance technique[END_REF], i.e. Dirac energy distribution for the density of the trap, the equivalent conductance G P /ω is simulated by using the equation:

G P ω = C it ωτ 1 + ω 2 τ 2 (2.47)
where τ is the characteristics time constant of interface states and being determined at G P ω max

, where ωτ = 1. Interface states capacitance C it is determined from the peak of the equivalent conductance G P /ω as following: C it = 2 G P ω max . The simulation curves reproduced with a good agreement the experimental curves.

Similar results are obtained for dierent V G . Therefore, we conclude that single level in- terface state model is sucient to describe the interface states between O-diamond/Al 2 O 3 interface.

Capacitance-frequency dependence

With the latest interface states parameters evaluated, we have actually determined all parameters of the equivalent circuit (Figure 2.37c). Therefore, the capacitance-frequency characteristic of the system can be simulated to conrm the accurateness of the model. For the purpose of recall, we will summarize the parameters we have extracted and the corresponding extraction method.

Oxide capacitance C ox was measured by using the MIM capacitor. Semiconductor capacitance C sc was evaluated from MOS capacitor measured capacitance C m at proper frequency regime(f = 100 kHz), by using the relationship:

C sc = C ox .C m C ox -C m (2.48)
Series resistance R s is determined from real part of impedance measurements at high frequency regime f = 1 MHz. DC conductance is obtained from the statics I-V characteristics of the test device by using the derivation G DC = Capacitance (F)

Frequency (Hz) V G =-7V
LTSpice Simulation Capacitance (pF) Therefore, we are able to conclude that the measured capacitance-frequency dependence eect observed in O-diamond MOS capacitor is originated from the gate metal carriers injected to interface states and then recombined with diamond valence band.

Frequency (Hz) V G =-8V V G =-7V V G =-6V V G =-5V V G =-4V Simulation a)! b)! @RT! V ac =20mV! MOS 12 -sample #1! MOS 12 -sample #1! @RT! V ac =20mV!

Electrostatics simulation

Taking into account the new interface state density extracted by conductance method, the electrostatics simulation can be re-performed. We apply here the same 1D simulation model as introduced in the Part 1 of this chapter and replace the interface charges from Terman method by the one extracted from conductance method.

The simulation results are compared with the experiment results by mean of semiconductor surface potential Ψ s . As shown in Fig. 2.45, by using the interface states density extracted from capacitance method σ it (Capacitance), surface potential is rstly well matching with experimental results but then re-increased in the bias range where the test device is highly leaky. On another hand, by using the interface states density extracted by conductance method σ it (Conductance) where the potential drop on the oxide is excluded, electrostatics simulation is well-matching with the experiments. Fermi level pinning eect is reproduced and surface potential variation with gate bias is in good agreement. Therefore, we are able to conclude that this electrostatics model is adequate Terman method (blue curve) and conductance method (magenta curve).

Also, by identied the origin of FLPE (interface states and the carriers from gate metal injected into oxide and interface states), a new experimental recipe can be applied to eliminate the FLPE for a complete electrostatics gate controlled semiconductor. We will show in the perspective section our new recipe that allows us to eliminate FLPE in O-diamond MOS capacitor for a complete gate controlled boron doped diamond semiconductor.

Conclusion

In summary, this part was dedicated to elucidate the typical electrical characteristics However, on a MOS capacitors without reverse current, the so-called inversion is not present. For instance, it is clearly the case for the MOS C7 -sample #3 in Fig. dierent frequencies. When a reverse current is not observed, the so-called inversion is not present, even at a very low frequency (10 Hz).

- From the above observation, we conclude that the so-called inversion in O-diamond MOS capacitor is actually a capacitance-frequency dependence eect which is directly a consequence of reverse current in positive bias. Therefore, questions are raising on origin of reverse current and the relationship between DC reverse current and a.c measurements.

We are going to solve the mentioned questions in this work. After the motivation, we will introduce our approach to elucidate the origin of reverse current The measured capacitance-frequency curve is compared with the simulated results from the equivalent circuit. Finally, we will conclude our works.

Results and Discussion

As shown in Fig. 2.49, reverse current (under positive bias) is randomly observed even on the same substrate. Since reverse current is not universal, substrate imperfection is highly suspected as the origin. In fact, defects and dislocation on the substrates were found playing an important role in other diamond devices such as Schottky diode [START_REF] Ohmagari | Non-destructive detection of killer defects of diamond schottky barrier diodes[END_REF][122] or Metal-Semiconductor-Metal photodetector [START_REF] Lohstroh | Eect of dislocations on charge carrier mobilitylifetime product in synthetic single crystal diamond[END_REF].

Device characteristics-substrate prole correlation

We will rstly recall the plan view structure of our MOS capacitor test devices. Figure 2.50a represents the optical photograph of sample #1.

Combined FESEM and electrical measurement

Substrate region corresponding to the MOS A1 -sample #1 is then examined by Field Emission Scanning Electron Microscope (FESEM). Figure 2.52 represents the FESEM image of this grid region at dierent resolutions. A special notice has been paid to two defective spots: the hexagonal LS1 (Fig. 2.52b) and the rectangular LS2 (Fig. 2.52c).

By employing the FESEM system operated with the micromanipulator system [START_REF] Tchoulan | Direct imaging of pn junction in coreshell gan wires[END_REF],

we directly probed the defective spots and measured their electrical characteristic. Ohmic contact was grounded by one tip and the second tip with a radius curvature of 1 µm was mounted on the top of the defective spots. The I-V characteristics of the defective spot were then measured by using Keithley 2611 Electrometer. By applying the identical measurement conguration and probing the second tips outside the defective spots, current under detection limit is observed (Figure 2.53a, the open black circular). We concluded these defective spots are the killer defect directly related to the reverse current of the MOS capacitor.

Cathodoluminescence

We also performed cathodoluminescence (CL) measurements to correlate the localized A-band luminescence to the killer defects. In fact, there are number of discussions on correlating localized band-A-luminescence to killer defects on homoepitaxial diamond devices [121][122]. For the current study, we performed CL spectrum and CL mapping on dierent grid regions and correlate to electrical characteristics of MOS capacitors. As shown in Fig. 2.54, localized A-band at approximately 420 nm were found at dierent positions. However, there were no clear correlation between MOS capacitor reverse current and A-band CL. We also employed the micromanipulator system using the identical measurement conguration to measure the electrical characteristic of A-band defective spots. A systematic correlation between A-band defective sites and electrical leakage current was not obtained, as already noticed by Ohmagari et al. [START_REF] Ohmagari | Non-destructive detection of killer defects of diamond schottky barrier diodes[END_REF].

This could be related to the origin of A-band luminescence. The impurities aggregation and segregation at defect positions [START_REF] Lohstroh | Eect of dislocations on charge carrier mobilitylifetime product in synthetic single crystal diamond[END_REF][125] is claimed to be at the origin of A-band luminescence. However, since not all the defect sites are killer defects, A-band are not necessary revealed to killer defects. Therefore, it could be confusing to use CL to identify With d hkl = a √ h 2 +k 2 +l 2 where a=0.365 nm is the diamond lattice constant. A cosα = 0, 9487 which is equivalent with an angle between two crystallographic orientations of α =57.0743 o is determined. We conclude that the diamond-like non-homoepitaxially crystallite with bunch of dislocation inside is the feature of diamond killer defects. the diamond surface, only the region with defective leakage spots are allowed the carriers owing through. The MOS capacitor without leakage spots will be insulated and no reverse current will be observed.

Reverse current mechanism

V G >0! E C! E V! E C! E V! E F! V G >0! Ψ S!

Limiting process

To identify the limiting process, we reconsider the current-voltage power-law from the log-log plot in Fig. 2.51 and Fig. 2.53.

The I ∝ V 4 of MOS capacitor in Fig. 2.51b indicates that bulk oxide is not the limiting process [START_REF] Chiu | A review on conduction mechanisms in dielectric lms[END_REF][116] [START_REF] Rose | Space-charge-limited currents in solids[END_REF]. Carriers transport in defective leakage spots are followed ohmic law I ∝ V , as shown in Fig. 2.53b. Furthermore, the equivalent resistance of defective leakage spots is much lower than the resistance of MOS capacitors. We conclude that the transport through defective sites is not the limiting process. Therefore, for the gate bias range V G =-8V to V G =+8 V in current work, limiting process of reverse current is identied as the tunneling from metal to the oxide traps states [START_REF] Mahaveer | Thermionic trap-assisted tunneling model and its application to leakage current in nitrided oxides and algan/ gan high electron mobility transistors[END_REF].

Current-voltage were also measured at dierent temperatures to examine the thermal activation process, as shows in Fig. 2.59a. Current value for V G =7V at dierent tem- perature is plotted in Fig. 2.59b. By applying the Arrhenius plot, a thermal activation energy of E A 142 meV was evaluated. This thermal activation energy is assigned to the process at the barrier between metal and the Fermi-Dirac occupation function of the trap states in the oxide [START_REF] Mahaveer | Thermionic trap-assisted tunneling model and its application to leakage current in nitrided oxides and algan/ gan high electron mobility transistors[END_REF].

Capacitance-frequency dependence

As shown in Fig. 2.47 and Fig.

Equivalent circuit

In order to model the eect of reverse current on C mf measurements, we linearized the characteristics around a DC bias by an equivalent circuit. Oxide capacitance (C ox1 and C ox2 ) are corresponding to the eective area of the non- defective area and the defective area, respectively.

Impedance Simulation

Parameters Extraction The area of the defective leakage spots S crystallite are determined from FESEM measurement. The corresponding capacitance C ox2 can be evaluated C o n d e n t i a l 102 from the equation:

C ox2 = ε 0 ε ox S crystallite t ox (2.50)
Because C ox1 and C ox2 are two capacitances in parallel, the oxide capacitance C ox is equivalent with: C ox = C ox1 + C ox2 . The C ox1 is therefore evaluated by using:

C ox1 = C ox -C ox2 (2.51)
where C ox is the oxide capacitance measured from MIM capacitor.

Semiconductor capacitance C sc is evaluated from proper frequency capacitance mea- surements as discussed in the previous part. By using the equation:

C sc = C ox C m C ox -C m (2.52)
where C m is the MOS capacitor measured capacitance at high frequency range. R crystallite is the equivalent resistance of the defective leakage spots. The MOS A1 - sample #1 consists of two defective spots in parallel. Therefore, the equivalent R crystallite can be calculated as:

R crystallite = R 1 × R 2 R 1 + R 2 (2.53)
where R 1 and R 2 are corresponding to the resistance of the LS1 and LS2 defective leakage spots, which were determined from I-V measurement. The conductance of the crystallite is then evaluated by the inverse of R crystallite .

From DC I-V measurement of the MOS capacitor, the DC conductance G DC is evaluated by the derivation:

G DC = dI DC (M OS) dV DC (M OS) (2.54)
We considered that DC transport is a process of two serial processes: conduction in the oxide G ox and conduction in the crystallite G crystallite . By assuming G ox1 is not contributing to the DC transport, the G ox2 is evaluated as:

G ox2 = G DC × G crystallite G crystallite -G DC (2.55)
In summary, all the parameters in the proposed equivalent circuit can be experimentally determined for an empirical simulation. Table 2.4 represents the parameters we introduced for the impedance simulation. The corresponding extraction method are also indicated.

Measurement method MIMCAP FESEM C ox -C ox2

High frequency MOSCAP Impedance Simulation With all the parameters of the equivalent circuit experimentally determined, the C mf curve can be simulated.

I-V defect I-V defect 1/R crystallite IV MOSCAP V G (V) C ox (pF) C ox2 (pF) C ox1 (pF) C sc (pF) R LS1 (Ω) R LS2 (Ω) R cristallite (Ω) G crystallite (S) G DC (S) G ox2 (S) 7
R LS1 × R LS 2 R LS1 + R LS 2 parameters G DC × G crystallite G crystallite -G DC
The red line in Figure 2.61 represents the simulated capacitance-frequency curve by using the equivalent circuit in Figure 2.60 and the parameters in table 2.4. The simulation curve unambiguously reproduces the measured C mf curve. We conclude that the reverse current via defective leakage spots in the epilayer is responsible for the C mf dependent. Without reverse current, no C mf dependent is observed. We conclude that the conclusion on minority carrier inversion given by Kovi et al. [20] is most probably an eect from their enormous reverse current.

Conclusion

In this work, we investigated the origin of reverse current in O-diamond MOS capacitors.

The correlation between substrate prole with MOS capacitors electrical characteristics were done. Diamond-like defective leakage spots with bunch of dislocations inside were found to be responsible for the reverse current at positive bias

Deep depletion concept for diamond MOSFET

T.T. Pham, 1, 2, 3, a) C. Masante, 1, 2, 3 G. Chicot, 1, 3 F. Udrea, 4 P. Muret, 1, 2 D. Eon, 1, 2 E. Gheeraert, 1, 2 N. Rouger, 1, 3 and J. Pernot 1, 2, 5, b) Due to silicon physical limitations, wide band gap semiconductors are attracting a lot of interest for next generation power electronics device application. Among them, diamond is widely recognized as the best material 1 due to its superior physical properties like extreme breakdown field, high thermal conductivity and elevated carrier mobilities. After decades of investigation, diamond epitaxial growth and doping control are well mastered. It opens the path to realize diamond MOSFET which is one of two critical elements of a power converter system, along with Schottky diode.

Most of the diamond based MOSFET have been developed thanks to the surface transfer doping concept on H-terminated diamond 2 . Such MOSFETs, including an oxide layer between the metal and the carrier channel 3-5 , are promising devices able to combine low loss in onstate and high breakdown voltage in off-state with a stable behavior. Recently, diamond MOSFET based on O-terminated phosphorous doped diamond 6 working in inversion regime were also demonstrated. The on-state current of these two kind of MOSFETs is strongly dependent to the channel mobility at the interface between oxide and diamond. Indeed, the hole channel carrier mobility of these MOSFET is limited by interface phenomena (surface roughness scattering or interface states scattering) resulting in typical mobility of around 100 cm 2 .V -1 .s -1 for the best case. Thus, the full properties of diamond cannot be exploited in such MOSFET. Achieving a hole channel mobility having values comparable to bulk mobility 7 remains a challenge. On the other hand, bulk channel boron doped diamond can be used in MESFET as recently demonstrated 8 . In that case, bulk hole mobility can be achieved but the on-state current of this device is limited by the low doping level required (N A 10 16 cm -3 ) to preserve the Schottky contact at the gate without excessive leakage current. In this cona) thanh-toan.pham@neel.cnrs.fr b) julien.pernot@neel.cnrs.fr text and thanks to the oxide barrier, boron doped deep depletion mode MOSFETs are good alternative which will permit to use higher doping level combined with bulk mobility.

The boron doped deep depletion mode MOSFET principle relies on the large band gap of diamond. Generally, wide band gap materials are used because of their ability to sustain high breakdown field which permits to achieve devices having higher blocking voltage than Si. In the deep depletion FET concept, we propose to use the large band gap of diamond in another manner. The large band gap of diamond induces an infinitely long time for the generation of minority carrier. Also, when the deep depletion regime is achieved in diamond and at the opposite to Si, if no source of minority carrier is provided (drain or source in inversion MOSFET for example), the deep depletion regime is stable over time. Here, we demonstrate the interest of this property to fabricate a transistor in which the on-state is ensured thanks to a bulk channel conduction, boron doped diamond epilayer, and the offstate is ensured thanks to the thick depletion induced by the deep depletion regime. This report is dedicated to the description of the deep depletion concept and demonstration.

In a first part, the deep depletion concept will be detailed. Then, the sample fabrication and experimental details will be given. The electrical properties of diamond Metal Oxide Semiconductor Capacitors (MOSCAPs) will be analyzed in terms of deep depletion. The effectiveness of the space charge region modulation will be demonstrated. Finally, the transistor characteristics of two deep depletion diamond MOSFETs will be shown in order to illustrate the device concept.

Figure 1 describes the deep depletion concept. Figure 1a) shows a cross section of a deep depletion transistor. D and S are the drain and source electrodes having a circular and annular shape, respectively. G is the annular gate electrode composed of a stack of oxide and metal deposited on diamond surface. For sack of simplicity, we first consider that D and S are grounded and only the gate electrode can be biased with a voltage V G . For V G equals to the flat band voltage of the MOSCAP, no depletion of holes is expected below the gate electrode. The channel between the D and S is fully opened. A drain source voltage can create a channel current across the transistor. This is the on state of the deep depletion transistor. When a gate bias larger that the threshold voltage of the transistor is applied, the transistor is switching from the flat band regime to the depletion regime and then the deep depletion regime. The space charge region extends below the gate contact and could even reach the insulating substrate. The green areas of Fig. 1a) indicate the insulating area of the channel. This is the off state of the transistor. The electric charge below the gate can be quantified and even plot as function of the semiconductor surface potential Ψ s (Fig. 1b)). The different regimes can be observed. The vertical line at around Ψ s =4.8 eV represents the abrupt increase of the negative charges at the interface between the semiconductor and the oxide when the inversion regime is reached. Then, thanks to the method introduced by Vincent 9 , we can graphically identify the transistor regime by plotting simultaneously the straight line arising from the Gauss theorem in the oxide and in the semiconductor respectively. One example is shown in Fig. 1b) for a high positive gate voltage. The two intercepts of this example correspond to two different regimes: deep depletion and strong inversion. A diamond MOSCAP will switch from the deep depletion regime to the strong inversion regime with a typical time constant τ :

τ = 2 × 1 v th σ e N v e
Ec -Ev 2k b T ≈ 10 37 (sec) ≈ 10 30 (years)

(1) with v th the mean thermal velocity of carriers, N v the equivalent density of states of valence band, σ e is the capture cross-section of a defects in midgap with typical magnitude of 10 -16 cm -2 . E c and E v are the conduction and valence band energy respectively. This time constant characterizes the time needed for electron (here minority carrier) to be generated from the valence band to the conduction band and so, establish the inversion regime. An evaluation, using Si parameters for v th and N v , is shown in Fig. 1c) as a straight line. As observed, in the case of Si, this time constant is of the order of one second meaning that the deep depletion regime is not a stable state in silicon material. Silicon can not be used to fabricate deep depletion transistor. At the opposite, the time constant of larger bandgap like diamond is so large, 10 37 s at room temperature, that it can be considered as a stable state. In other words, Si MOSCAP switches from deep depletion to inversion in about one second and so, partially open the channel of the transistor destroying the off state of the transistor. At the opposite, diamond MOSCAP stays fully deeply depleted and so ensure the off state of the transistor. This particular property of wide bandgap material opens the route for the fabrication of high voltage high temperature devices. The possibility to use the deep depletion regime in MOSFET can be strongly beneficial in the design of the transistor since thick layer can be depleted with this concept. In order to demonstrate the validity of our concept, we fabricate and analyse diamond MOSCAP and transistors.

For the purpose of investigate the gate control diamond, the O-diamond MOSCAPs were fabricated using the lateral structure 10 , as shown in Fig. 2a). Monocristalline diamond layer with 500 nm thick and 5×10 16 cm -3 boron doped is homoepitaxially grown using a microwave plasma assisted chemical vapor deposition (MPCVD) NIRIM type reactor 11 on a 4 × 4 mm 2 Ib high pressure high temperature (HPHT) (001) diamond substrate. Oxygen termination of the semiconducting diamond top layer was done thank to a deep UV ozone treatment 12 . The ohmic contacts and gate contacts were defined by laser lithography (Heidelberg DWL66FS) and electron beam (e-beam) evaporation of Ti/Pt/Au (30/50/40 nm) followed by standard lift-off technique. 40 oTech. The precursor was Trimethylaluminium (TMA), and water as oxidant. The pulse and exposure duration were 15 ms and 30 s, respectively, with typical base pressure of 1.3× 10 -1 Torr. After the gate contact deposition, sample is annealed at 500 • C in vacuum condition during 30 mins. Optical top view structure of MOSCAP is shown in Fig. 2b). For MOSCAPs measurements, I(V) was measured by Keithley 2611 source-ammeter. Solartron Modulab with ac voltage V ac = 20mV was employed to measure C(V) and capacitance-frequency C(f).

For the purpose of proof-of-concept, two deep depletion diamond transistors name GD1 and GD2 have been fabricated. The MOSFETs structure is identical to the structure presented in Fig. 1a. On sample GD1, a 20nm Al 2 O 3 was deposited at 380 • C onto the top of diamond epilayer (2×10 17 cm -3 boron doped and 230 nm thick). On sample GD2, we deposited 40 nm Al 2 O 3 at 380 • C onto the top of diamond epilayer (5×10 16 cm -3 boron doped and 500 nm thick). Typical thermal annealing is employed for ohmic contact 13 of MOSCAPs and MOSFETs. For MOSFETs measurement, a two channel Keithley 2636 Source Meter Unit was used.

Figure 2c) represents the I(V) characteristic of the Odiamond MOSCAP. In this sample, leakage current are almost under detection limit for the bias range from -10V to +15V. The C(V) characteristic of O-diamond MOSCAP that were normalized to oxide capacitance C ox is shown in Fig. 2d). A complete p-type semiconductor MOSCAP operation (accumulation, flatband, depletion, deep depletion) is obtained. In this case, C ox is estimated using C ox = ε0εox tox with ε 0 vacuum permittivity, ε ox = 9 is the oxide dielectric constant and t ox is the oxide thickness. Prior to perform C(V) measurements, the a.c frequency is pre-determined by using C(f) measurements to eliminate the artifacts interfere C(V) measurements 14 .

The ideal I(V) and C(V) characteristic of this sample is obtained thanks to the improvements of oxide and oxide/diamond interface. The details of new process improved oxide and oxide/diamond interface can be found in 15 .

As mentioned above, the goal of this work is to demonstrate the deep depletion concept for boron doped diamond MOSFET. Therefore, the central role of the MOSCAP test devices is to examine the efficiency of gate control diamond semiconductor specialized on deep depletion regime.

As it is well-known, for depletion and deep depletion regime, semiconductor SCR is proportional to the square root of surface potential Ψ s 9 . Consequently, the semiconductor capacitance C sc and semiconductor surface potential can be evaluated from C(V) measurements 14,15 :

Ψ s (V G ) = q 2 N A ε o ε s Cox Cm -1 2 2C 2 ox (2)
The Ψ s -V G relationship in Fig. 2e demonstrates the efficiency of gate control diamond semiconductor in deep depletion regime. Minimum capacitance C min that generally observed in Si/SiO 2 MOSCAPs when Ψ s reaches the inversion condition (Ψ s > 2Ψ b ) 16 is not observed in diamond MOSCAPs. As illustrated in Fig. 1, this is the special characteristic of wide bandgap semiconductor due to the infinite minority carrier generation time constant.

From Ψ s -V G relationship, the SCR width (W) versus V G can be calculated by:

W = 2ε sc ε 0 Ψ s qN A (3)
Figure 2f) represents the SCR width of boron doped O-diamond versus V G . In the current configuration, 360 nm thick of diamond can be modulated. This analysis is critical to realize the deep depletion diamond MOSFET. The proof of deep depletion diamond MOSFETs concept is demonstrated in Fig 3 . We introduce here the transistor characteristic of two transistors. The transistor characteristic is measured by sweeping the source to drain voltage (V DS ) at different gate bias, ranging from negative to positive. As shown in Fig 3, current between source and drain is clearly controlled by the potential at gate electrode. The devices clearly exhibit transistor characteristics with ON-state and OFF-state. For both cases, gate leakage currents are under the apparatus detection limit (data not shown) demonstrated that the transistors are controlled electrostatically by the potential at metal gate.

C o n d e n t i a l

V DS (V)) a)! b)! T=295K! Step V G : 4V! T=295K! Step V G :1V! V G =-16V! V G =20V! V G =-5V! V G =10V! V DS (V)! V DS (V)!
As demonstrated, the deep depletion concept is working well for different epilayer thicknesses, doping concentrations, different oxide thicknesses and also envisage for different structures. This demonstration opens the concept of the vertical deep depletion MOSFET working like a Junction FET (JFET) 17 without the need of the n-type layer.

In summary, we demonstrated in this work the deep depletion concept which is unique of wide bandgap semiconductor. We fabricated O-terminated diamond MOSCAPs to investigate the effectiveness of gate control diamond semiconductor, specialized on deep depletion regime. We demonstrated the first ever a boron doped diamond MOSFET working by the deep depletion concept. This work opens the new perspectives to fully exploit the potential of diamond for MOSFET applications.

Comprehensive electrical analysis of metal/Al 2 O 3 /O-terminated diamond capacitance T.T. Pham, 1, 2, 3, a) A. Maréchal, 1, 2, 3 P. Muret, 1, 2 D. Eon, 1, 2 E. Gheeraert, 1, 2 N. Rouger, 4 and J. Pernot 1, 2, 5, b) 1) Univ. Grenoble Alpes, F-38042 Grenoble, France 2) CNRS, Inst. NEEL, F-38042 Grenoble, France 3) CNRS, G2Elab, F-38042 Grenoble, France Metal oxide semiconductor capacitors were fabricated using p-type oxygen-terminated (001) diamond and Al 2 O 3 deposited by atomic layer deposition at two different temperatures 250 • C and 380 • C. Current voltage I(V), capacitance voltage C(V) and capacitance frequency C(f) measurements were performed and analyzed for frequencies ranging from 1 Hz to 1 MHz and temperatures from 160 K to 360 K. A complete model for the MOSCAPs electrostatics, leakage current mechanisms through the oxide to the semiconductor and small a.c. signal equivalent circuit of the device is proposed and discussed. Interface states densities are then evaluated in the range of 10 12 eV -1 .cm -2 . The strong Fermi level pinning is demonstrated to be induced by the combined effects of the leakage current through the oxide and the presence of diamond/oxide interface states.

I. INTRODUCTION

Diamond has been widely recognized as an ideal semiconductor for power devices 1,2 due to its superior physical properties. Recent progresses on diamond substrate, homoepitaxial growth, doping control and fabrication processing permit to consider the diamond power devices, e.g. Metal Oxide Semiconductor Field Effect Transistors (MOSFET). Most of the diamond MOSFET 3-5 reported in the literature were realized thanks to the two dimensional hole gas (2DHG) at the hydrogen terminated diamond (H-diamond) surface due to surface doping concept 6 . Performances of H-diamond MOS-FETs are promising 4 and optimizations of the structures are still under investigations 5,7,8 . Recently, the first MOSFET transistor working in inversion regime has been reported 9 . In order to obtain such carrier inversion, n-type oxygen-terminated (O-terminated) [START_REF] Khaldi | Dierences between direct current and alternating current capacitance nonlinearities in high-k dielectrics and their relation to hopping conduction[END_REF] diamond epilayer has been used as substrate material in order to create a p-type channel MOSFET. These two MOSFETs architectures are opening the route for the fabrication of the next generation of diamond based MOSFETs for power electronics. However, a deep understanding of the oxide and interface properties of the gate transistor is still missing. In this work, we report an exhaustive analysis of metal oxide semiconductor capacitor (MOSCAP) fabricated on O-terminated diamond.

In order to examine the gate control boron doped diamond, Chicot et al. 10 This work is devoted to investigate the diamond/Al 2 O 3 interface and the origin of gate leakage current and capacitance-frequency dependence for O-diamond MOSCAP. In the first section, we briefly introduce the fabrication processes and the general electrical characteristic of the O-diamond MOSCAPs to illustrate the main issues. In the second section, we address the electrostatic properties of the O-diamond MOSCAPs, we introduce an approach to reliably perform the C(V) measurements and a method to quantify the semiconductor surface potential versus gate bias (Ψ S (V G )). Electric charges properties such as semiconductor doping concentration, oxide charges and interface states charges are then quantified from C(V) measurements. The electrostatic band diagrams are built by taking into account the charge components of the MOSCAP test device. Electrostatics simulations are compared with experimental results Ψ S (V G ). In the third section, we propose a model for the leakage current mechanism under negative bias thanks to the electrostatics band diagram. From leakage current mechanism, we build the physical equivalent circuit linearizing the small signal measurements. Approximated equivalent circuit based on different limiting processes is discussed. Current limiting process is identified thanks to different approaches. From the approximated equivalent C o n d e n t i a l 2 circuit, the conductance method is adapted to our specific MOSCAPs and applied to quantify interface states density D it . The impedance/admittance frequency dependence of the MOSCAP test device is empirically simulated by using the proposed equivalent circuit with all parameters extracted from experimental analysis. Finally, the paper is summarized.

II. MOSCAP FABRICATION AND TYPICAL ELECTRICAL CHARACTERISTICS

This section is dedicated to the description of the MOSCAPs fabrication process. Then, the typical I(V), C(V) and C(f ) measurements done on these MOSCAPs will be illustrated and discussed.

A. Experimental details

The test devices composed of a stack of a heavily (p+ layer) and a lightly (p-layer) boron-doped homoepitaxial mono-crystalline diamond layer grown by using a microwave plasma assisted chemical vapor deposition (MPCVD) NIRIM type reactor on a 3 × 3 mm 2 Ib high pressure high temperature (HPHT) (001) diamond substrate. The cross-section structure is shown in Fig. 1 a). The optical plan view structure of one fabricated test device is shown in Fig 1b . The moderately boron-doped diamond layer (N A 3 × 10 17 cm -3 ) is in contact with the gate oxide. The heavily boron doped (N A 5 × 10 20 cm -3 ) metallic diamond p+ layer acts as a low resistive ohmic contact electrode in order to reduce the series resistance. Vacuum ultraviolet (VUV) ozone treatment resulted in the Oxygen termination of the diamond surface 14 . The Al 2 O 3 gate oxide was deposited by atomic layer deposition (ALD) on the whole sample surface using a Savannah 100 deposition system from Cambridge Nan-oTech. The precursor was Trimethylaluminium (TMA), and water was used as the oxidant. The pulse and exposure duration were 15 ms and 30 s, respectively, with typical base pressure of 1.3× 10 -1 Torr. The ohmic contacts and gate contacts were defined by laser lithography (Heidelberg DWL66FS) and electron beam (ebeam) evaporation of Ti/Pt/Au (30/50/40 nm) followed by standard lift-off technique. The ohmic contact was deposited directly on p + layer prior to Al 2 O 3 deposition. This structure offers the advantage of having both MIMCAPs and MOSCAPs on the same sample, as shown in Fig. 1a). The details of two representative samples are presented in table I. These two samples are chosen as their electrical characteristics are mostly similar in term of leakage current density, capacitance-voltage and capacitancefrequency behaviors. The only difference is the shift of flatband voltage due to charge in the gate oxide, as it will be discussed in the following sections.

The DC Current-Voltage I(V) characteristic was measured by Keithley 2611 source-ammeter. Small-signal measurements (C(V), C(f ), impedance, admittance) were performed with a constant a.c voltage of V ac = 20 mV by Solartron Modulab impedance analyzer. Capacitance characteristics that will be introduced in the following section represent the measured capacitance of the equipment which is C m = 1 2πf Z . Where Z is the modulus of the measured impedance. To perform conductance method, the parallel capacitance-conductance circuit (C p -R p ) can be evaluated by using the real part and imaginary part of the measured impedance. Electrostatics simulation was performed using Nextnano 3 software. The band alignment for electrostatics simulation is employed from the XPS measurement introduced by Marechal et al.

B. Typical electrical characteristics

Typical electrical characteristics of O-diamond

MOSCAPs can be summarized in Fig. 2. These results are measured from MOSC7 test device on sample #2 and in agreement with O-diamond MOSCAPs that have been previously fabricated and reported by our group 11,13 and the results published in literature 12 .

Figure 2a) represents the I(V) characteristics. Under negative gate bias, leakage currents are systematically observed. Under positive bias, leakage currents are randomly observed among several test devices (in the current MOSCAP, leakage current under positive bias are under the apparatus detection limit). In the following sections, we will elaborate the origin of leakage currents and capacitance-frequency dependence for the Odiamond MOSCAPs under negative bias. The origin of leakage currents and capacitance frequency dependence for O-diamond MOSCAPs under positive bias will be discussed in another work.

Figure 2b) represents the C(V) characteristics at different frequencies, ranging from 1 kHz to 1 MHz on the same MOSCAP test device and the same bias range with I(V) measurement. A strong capacitance-frequency dependence is observed when the strong negative gate bias (-4 V ≤ V G ≤ -6 V ) is applied. For the high positive bias range, the capacitance-frequency dependence are not observed in this MOSCAP test device.

The capacitance-frequency dependence under negative bias can be further seen by C(f ) measurements, as shown in Fig. 2c). From the C(f ) curves, three different regimes can be distinguished: i) High frequency regime (between 500 kHz and 1 MHz): There is a minor effect from series resistance which induces a slightly capacitance increase versus f . However, in our pseudo-vertical MOSCAPs, series resistance contribution is almost negligible. ii) Low frequency regime (from 1 Hz to about 40 kHz for V G = -6 V ; from 1 Hz to 4 kHz at V G = -4 V ; from 1 Hz to 200 Hz at V G = -2 V ; and almost negligible in the whole frequency range for V G = 0 V ): the measured capacitance is strongly frequency dependent. Capacitance decreases with a slope of 20 dB/dec. Previous reports on O-diamond MOSCAPs 11,12 showed that the capacitance frequency dependence of the "low frequency range"is huge. In Kovi et al. 12 , the "low frequency range" is even observed for the frequencies up to few MHz. iii) Middle frequency regime (the regime between "high frequency"and "low frequency"): the measured capacitance is constant versus frequency. This frequency window is too low to be assigned to a series resistance effect and too high to be related to an interface states contribution. The C(V) measurement in this frequency window is considered as the proper C(V) characteristic of the MOSCAP. In another word, MOSCAP test device is in the ideal MOSCAP configuration i.e. oxide capacitor C ox and semiconductor capacitor C sc are in series. In this configuration, the measured capacitor of the MOSCAP writes: C M OS = CoxCsc Cox+Csc . In the following section, we will employ this proper C(V) measurement to evaluate the key informations of our O-diamond MOSCAP test devices.

III. ELECTROSTATICS: ELECTRIC CHARGES, ELECTRIC FIELD AND POTENTIAL DISTRIBUTION

This section is dedicated to quantify different electric charge components and to establish the electrostatic band diagram of the O-diamond MOSCAP.

A. Proper C(V) measurement

As shown in the typical C(f ) characteristics (Fig. 2c), capacitance measurement is affected by series resistance at high frequency regime and by other artifacts at low frequency regime. In our experiment, prior to perform C o n d e n t i a l C(V) measurements, the C(f ) measurements have been systematically employed to determine the "middle frequency" window which corresponds to each MOSCAP.

The open red circle curve in Fig. 3 represents the C(V) characteristics of MOS 12-sample #1 at f = 100 kHz, which is in the proper frequency window of this MOSCAP device. From the proper C(V) curve, notable behaviors can be noticed as: i) Under negative bias, for bias lower than the flatband voltage of the MOSCAP, the accumulation regime is expected corresponding to (C M OS = C ox ). In our case, the measured capacitance is much lower than the oxide capacitance C m << C ox even for V G = -8 V . Measured capacitance can be normalized to the oxide capacitance C ox = 0.4µF.cm -2 , measured from MIMCAP test devices on the same sample. A maximum measured capacitance of C m = 0.135µF.cm -2 at V G = -8 V is observed, corresponding to C m 0.35C ox . The systematic measurements demonstrated that this behavior is general for all measurable MOSCAPs on the same substrate 15 .

ii) The measured capacitance for positive bias does not show the saturation of minimum capacitance C min . Up to V G = +8 V , the measured capacitance monotonously decreases versus V G corresponding to the deep depletion regime.

iii) By sweeping the bias voltage from +8 V to -8 V and then from -8 V to +8 V , C(V) characteristics are almost identical. No sign of mobile oxide charges in this MOSCAPs test devices can be observed 15 .

In summary, from the proper C(V) measurement, three different charge components in the O-diamond MOSCAP can be envisaged: semiconductor charges, oxide charges and interface charges.

B. Semiconductor charges

From proper C(V) measurement, the semiconductor doping concentration is extracted using the Schottky-Mott plot. The open black circle curve in Fig. 3 represents the Schottky-Mott plot (reciprocal square capacitance versus gate bias plot 1 C 2 vs. V G ). The term

1 C 2 m -1 C 2
ox is used to eliminate the effect from oxide capacitance 16 . The 1 C 2 (V G ) curve exhibits an almost perfect straight line for the gate voltage ranging from V G =-6 V to V G = 8 V . From the slope of the curve, the doping concentration of the B-doped semiconducting diamond layer can be extracted by using the equation:

N A = -2 εε 0 A 2 1 dC 2 /dV (1)
with ε = 5.7 the diamond dielectric constant, ε o the vacuum permittivity and A the area of the diode. A doping concentration of N A = 3 × 10 17 cm -3 is extracted from the 1 measurements demonstrated the homogeneous and wellcontrolled dopant incorporation in B-doped diamond epilayer 15 .

C 2 m -1 C 2 ox versus V G curve

C. Oxide charges

One notable feature that can be seen from the C(V) curve and 1

C 2 m -1 C 2 ox
versus V G curve is the shift of the curves toward negative bias, compared to the ideal case. In fact, this shift is possibly induced by the interface charges, the oxide charges and the work function difference between metal and semiconductor. However, since our C(V) measurements were performed at 100 kHz, we can exclude the a.c contribution from the interface charges. As, the slope of 1

C 2 m -1 C 2 ox versus V G
in the range of examination has reliably reflected diamond doping concentration, the DC contribution of interface states is deduced to be negligible also for this gate voltage range. The experimental flatband voltage V F B , corresponding to the voltage at which the extrapolated

1 C 2 m -1 C 2 ox
straight line intercepts the horizontal axis, is equals to -7.3 V . This value is larger than the theoretical one, i.e. V F B = φ Mφ SC = -2.6 V where φ M = 4.3 eV is the work function of Ti metal and the semiconductor work function is φ SC E G + χ sc -E F = -6.9 eV with χ sc = 1.7 eV the electron affinity of O-diamond 17 , E G the diamond band gap and E F the Fermi level in the neutral region of the B-doped diamond referenced from the valence band (E V = 0). This experiment demonstrates that the measured flat band voltage includes a contribution of charges in the oxide Q ox . By applying the equation 18 :

C o n d e n t i a l

Q ox = C ox (φ M S -V F B ) qAt ox (2)
A net positive oxide charge density of Q ox = 6 × 10 18 cm -3 is deduced for sample #1. The shift of flatband voltage in sample #2 is about -5.4 V where the oxide charge is calculated as Q ox = 3.5 × 10 18 cm -3 .

D. Fermi level pinning effect due to a strong interfaces states density

MOSCAP is the suitable device to examine the efficiency of gate controlled semiconductor structure. As discussed by Vincent et al. 19 , semiconductor surface potential Ψ s is the critical quantity for this evaluation. Ψ s corresponds to the electrical potential variation between the neutral part of the semiconductor, where the Fermi level is flat, and the semiconductor surface, i.e. at the oxide interface. When Ψ s = 0 eV, the semiconductor is in the flatband regime. Therefore, flatband regime is the demarcation between accumulation regime and depletion regime. In the flatband regime, the semiconductor charge

Q sc (V G = V F B ) and consequently the semiconductor ca- pacitance C sc (V G = V F B
) is a function of the intrinsic semiconductor Debye length as:

C sc (V G = V F B ) = ε sc ε 0 λ p (3)
where λ p is the semiconductor intrinsic Debye length, which writes λ p = εscε0kT q 2 NA 1/2 . With N A extracted from the previous section, the semiconductor flatband capacitance C sc (V G = V F B ) can be evaluated. Subsequently, the flatband capacitance of the MOSCAP C M OS (V G = V F B ) is evaluated as:

1 C M OS (V G = V F B ) = 1 C ox + 1 C sc (V G = V F B ) (4)
From these relationships, a MOSCAP flatband capacitance of C M OS (V G = V F B ) = 0.279 µF.cm -2 is evaluated for MOS12 -sample #1. With the semiconductor doping concentration being homogeneous 15 , this value is typical of the MOSCAP measured on the whole sample. As shown in Fig. 3, the maximum measured capacitance of O-diamond MOSCAP at V G = -8 V (C m = 0.135 µF.cm -2 ) is lower than the flatband capacitance C F B . Therefore, it can be concluded that the diamond MOSCAP is always in depletion regime even for high negative bias (V G = -8 V ). In previous reports, Chicot et al. 10,11 and Kovi et al. 12 measured similar C(V) characteristics and deduced that their MOSCAP reached the accumulation regime. However, the present study shows that this assignment is erroneous and the misunderstanding is induced by the parasitic frequency dependence.

Since diamond is always in depletion regime, semiconductor Space Charge Region (SCR) is proportional to the square root of the surface potential Ψ s 19 in the whole voltage range (+8 V to -8 V ). Therefore, the semiconductor capacitance is also proportional to the square root of the semiconductor surface potential as 20 :

C s = qN A ε o ε s 2Ψ s (5)
As the measured capacitance C m and the oxide capacitance C ox are determined, the semiconductor capacitance C sc and the semiconductor surface potential Ψ s can be calculated. By performing a simple mathematical derivation of equations 4 and 5, the surface potential corresponding to a specific gate bias voltage can be written:

Ψ s (V G ) = q 2 N A ε o ε s Cox Cm -1 2 2C 2 ox ( 6
)
In principle, by performing this calculation at different gate bias, we can establish the relationship between semiconductor surface potential versus gate bias voltage (Ψ s -V G ), and so evaluate the efficiency of gate control semiconductor. For negative gate bias (V G : down to -8V), Ψ s stays positive showing that the Fermi Level Pinning Effect (FLPE) 21 is observed. The semiconductor regime at the interface approaches but never reaches the flatband voltage. This FLPE can be illustrated by the 1

C 2 m -1 C 2 ox
values, which are saturating and tending to a positive value for gate bias lower than -6V.

The strong FLPE observed here is assumed to be due to the presence of interface states in the semiconductor forbidden gap 20,22 . An evaluation of their density can be done thanks to the quantitative analysis of the capacitance stretching due to FLPE. This is the main idea of the high frequency-capacitance method developed by Terman 22 . With Ψ s -V G evaluated from eq.6, the interface states capacitance C it versus Ψ s is calculated by the high frequency capacitance method 20,22 :

C it (Ψ s ) = C ox dΨ s dV G -1 -1 -C s (Ψ s ) (7)
Subsequently, the interface states density D it can be evaluated by 20 :

D it (Ψ s ) = C it (Ψ s ) q (8)
An interface states density of less than 10 12 (eV -1 .cm -2 ) is found in the midgap region and an abrupt increase up to 4 × 10 13 (eV -1 .cm -2 ) for the interface states near the valence band edge (E t -E v ≈ 0.6 eV). We will see later that this method is not adapted to our case and overestimates the D it values. Indeed, the leakage current through the oxide is too high to consider the interface under equilibrium.

C o n d e n t a l 6 E. Electrostatics simulation

We performed the electrostatics simulation by implementing the semiconductor charges qN A extracted from the 1 C 2 -V G curve, oxide charges Q ox extracted from the shift of V F B and interface charges σ it (V G ) extracted from Terman method. Interface states charge is evaluated by integrating the interface states density over the energy band gap.

The electrostatics band diagrams of O-diamond MOSCAP for a gate bias of -5V is shown in Fig. 4 a). One remarkable issue from electrostatics simulation, which is not obvious from C-V measurement is the potential distribution within the oxide. This electrostatic band diagram is essential to identify the origin of leakage currents and capacitance-frequency dependence under negative bias.

IV. GATE OXIDE LEAKAGE CURRENT MECHANISM AND EQUIVALENT SMALL SIGNAL CIRCUIT

This section is dedicated to the analysis of the leakage current from metal to semiconductor and the corresponding equivalent small signal circuit.

A. Leakage current mechanism

In an ideal MOSCAP, the gate oxide prevents carrier transport between the gate metal and the semiconductor. Electrostatics gate control of carrier population at the oxide/semiconductor interface is crucial for semiconductor devices. However, in real situations, leakage currents are usually observed and perturb the carrier control.

In order to understand the origin of leakage currents, the source of transporting carriers must be determined. For a p-type MOSCAP under negative bias regime, currents are initiated from either the accumulated semiconductor majority carriers or gate metal carriers reservoir 23 . For O-diamond MOSCAPs, as evidenced from C -Vf analysis and electrostatics band diagram, we concluded that leakage current under negative bias is initiated from carriers reservoir of metal gate and not from accumulated hole of diamond semiconductor. This conclusion is based on the fact that FLPE preserved diamond in depletion regime, even at high negative bias (e.g V G = -8 V, MOS 12 -sample #1). No majority carriers (hole) are able to accumulate at the diamond-oxide interface. The transport due to accumulated majority carriers is therefore prohibited.

The next question to be addressed is, how do these carriers circulate in the MOSCAP system? Thanks to Nextnano electrostatics band diagram, we proposed a 5steps current mechanism, as shown in Fig. 4a). In step 1, carriers from gate metal are tunneling into the oxide trap states. Hopping between traps to traps through the oxide is taking place during step 2. In step 3, hopping carriers are captured by interface states. The charges transferring between interface states and valence band are taking place in step 4. Finally, these carriers drift through the diamond epilayer to the back gate contact (p + ) and complete the transfer process.

Potentially, the flow at each step may includes different processes in parallel. In principle, the process with highest rate (slowest time constant) dominates the flow at that step. On another hand, in order to complete a circulation, different steps in series could be involved. The step with the slowest rate (longest time constant) is the limiting process.

In the proposed current mechanism (Fig. 4a), interface states play a central role with a special interest. They are able to communicate with both the metal electrode and the semiconductor valence band. In principle, each charge transfer process is represented by its characteristic time constant τ . For the sake of simplicity and without losing the generality, we will firstly consider interface states as a single level state at energy E it -E v and density N it . In the following sections, we will discuss further the charge transfer between interface states with metal and semiconductor band edge.

Charge transfer between metal and interface states

The charge transfer between gate metal and interface states in a MOSCAP system was addressed by Dahlke and Sze 23 . The complementary theory was then developed by Freeman and Dahlke 24 . In their theory, interface states are modeled as a potential well and communicate with the gate metal by direct tunneling. The charge transfer is considered as an overlapping process of two wave functions. Kar and Dahlke experimentally studied the metal injection into interface states with a nondegenerate Si substrate and a moderate oxide thickness (20 -40 Å) MOS capacitor system 25 . A notable possible consequence of carriers injection from gate metal to interface states is that these carriers are possibly accommodating at interface states and therefore modulating Schottky barriers height at Metal-Semiconductor contact 26-28 .

In our case, the oxide is too thick to observe direct tunneling. Therefore, carriers injection from metal to interface states is suggested to be a process of two consecutive steps: the carriers tunneling from gate metal to oxide trap states (represented by tunneling time constant τ tun ) and then carrier hopping between trap sites happens in the oxide (represented by hopping time constant τ hop ). The two consecutive processes must happen in series and so the tunneling time constant τ T (from metal/oxide to oxide/semiconductor interface) writes:

τ T = τ tun + τ hop (9)
a. Tunneling from metal to oxide trap states As shown in Fig. 4 oxide layer. Even if there are many possible processes for a carrier from gate metal to be injected into the gate oxide 29 , most of them are practically not possible in our case. It is either direct tunneling, thermionic emission (Schottky injection) or tunneling into many trap states in the oxide. Considering the oxide thicknesses of 10 -40 nm that were systematically used for O-diamond MOS capacitors, direct tunneling by overlapping wave functions (theoretically less than 1 nm) 23 is not possible. Thermionic emission is a thermal activation process where carriers from the gate metal have to reach a sufficient energy to jump over the metal-oxide barrier height and being injected into the oxide layer. Regarding an approximate 3 eV barrier height between Ti and Al 2 O 3 , this process is not realistic. Also, the tunneling from the gate metal into oxide trap states 30 of the gate oxide is the most realistic process.

C o n d e n t i a l

Cox! Csc! Rs! Rit! Cit! Cox! Csc! Rs! R it! Gox! Cit! VG! Vox! Ψ s
Tunneling current from the gate metal to oxide trap states can be approximately described by 31 :

I = N t qν tun (10)
where N t is the density of nearest traps contributing to the conduction and ν tun is the tunneling transmission rate. The tunneling transmission rate is:

ν tun = 1 τ tun = v o f T T W KB (11)
with v 0 ∼ 10 13 Hz the attempt frequency which represents the rate of escape of a particle from a confining structure by quantum tunneling through its outer barrier. f T is the Fermi-Dirac function representing the occupancy probability of a trap state in the oxide. It can be expressed by:

f T = 1/ 1 + exp E a + F x kT (12)
where E a = E b -E t is the electron barrier between metal electrode and trap states, E b is the electron barrier between metal electrode and oxide conduction band, E t is the energy of the traps in the oxide, F is electric field in the oxide and x is the distance from the metal/oxide to the trap where the electron is tunneling (Fig. 4a)). T W KB is the Wentzel-Kramers-Brillouin (WKB) transmission coefficient and can be written as 32 :

T W KB = exp - 4 3hqF √ 2m * (E t + qF x) 3/2 -E 3/2 t ( 13
) with h is the reduced Planck constant and m * the effective mass of electron in the oxide 31 .

b. Hopping in the oxide Carriers transport in the oxide could be the sum of multiple parallel mechanisms 29,31 . One of two main mechanisms is the thermal activation from deep energy traps to oxide conduction band, which is generally called Poole-Frenkel emission. The second one is tunneling from traps to traps, also called hopping. In order to determine the dominant process, transfer rates of each process are necessary to be evaluated. The Poole-Frenkel emission rate is scaled versus T as v 0 exp -Ec-Et kT where E t is the energy of the traps in the oxide band gap 31 . In the case of Al 2 O 3 oxide deposited by ALD, trap states are usually ascribed to the non-stoichiometry of the oxide. From first principle simulation, the oxygen vacancy is found to be the electron trap level which is the nearest from the conduction band as E c -E t = 1 eV 33 .

C o n d e n t i a l

The trap to trap tunneling rate is calculated as 31

ν hop = 1 τ hop = v 0 exp - 2R ξ (14)
with ξ the electron wave function localization length ξ 0.3 nm, R distance between trap sites 31 . Distance between trap sites could be obtained by fitting the DC non-linearity capacitance-voltage of MIMCAPs 34 . The distance between trap sites in our ALD Al 2 O 3 is then estimated to be approximately 5 nm 15 .

A rough evaluation shows that the tunneling rate from trap to trap is almost 150 times faster than Poole-Frenkel thermal activation rate from traps level to conduction band at room temperature 15 . In case that an oxide trap level is deeper from oxide conduction band, which will be found below, the injection rate in step I will be even slower. It is therefore possible to conclude that tunneling from trap to trap is the main transport mechanism in the oxide.

Carrier readjustment

In step III, carrier readjustment is taking place. The readjustment process is a transfer from the energy levels of the oxide traps to the quasi-Fermi level of semiconductor at semiconductor/oxide interface. As depicted in Fig. 4 a), interface traps include two main parts: Acceptor-like levels close to the conduction band and donor-like levels close to the valence band, defining a Charge Neutrality Level (CNL). If the quasi-Fermi level is below the CNL (as shown in Fig. 4 a) donor-like levels will be positively charged between the quasi-Fermi level and the CNL. The other interface states will be neutral. In this case, the time for carriers readjustment, trapped by interface states (step III), will be neglected because its thermalization process is very fast compared to other processes 35 .

Charge transfer between interface states and semiconductor band edges

In step IV, the trapped electrons at interface states emit to the semiconductor valence band. We will firstly consider the single level interface states model with density N it and energy E it -E v from the valence band.

The serial charge transfers from gate electrode to interface states and from interface states to semiconductor valence band can be described by the differential equation 24 :

N it df t dt = -U cp + j q . ( 15
)
where j is the current injected from metal gate to interface states. U cp is the charge transfer rate of trapped carriers at interface states to semiconductor valence band and can be described by ? :

U cp = N it σ p υ th (f p s -f p p 1 ) (16)
with σ p is the hole capture cross-section of the trap states, v th is the carriers mean thermal velocity, f and f p are the occupation probabilities of a trap state by an electron and hole, respectively ? . p s = p b exp -eΨs kT is the surface carriers density at thermal equilibrium with p b the bulk carriers density. p 1 = N v exp Ev-Eit kT represents the carrier density that established at the trap states when the quasi-Fermi level equals the trap states level 24 . E F is the quasi-Fermi level and N v is the effective density of states of the valence band.

The current in and out interface states discussed above is then described by the interface states occupancy f ss 24,25 which is:

f ss = (τ R f m + τ T f s ) / (τ R + τ T ) (17)
where f s and f m are the bulk semiconductor and metal occupancies, respectively 24 . τ R is the recombination time constant of majority carriers with interface states and to be calculated:

τ R = 1 σ p v th p b exp(Ψ s ) (18)

Drift in the diamond layer

The process of electron being emitted to the valence band is equivalent to the process of holes from the valence band to be captured by interface states. To replace the evacuated hole, a hole from the back side (p+ layer) will move to the diamond surface and be ready for a new capture event 36 . In the reverse direction, electrons are transferring to the back gate contact (p + ) and complete the circulation.

B. Equivalent circuit and approximation 1. Equivalent circuit

In order to model the measured impedance and admittance of a MOS capacitor, linearized equivalent circuit is a well-known concept. Lehovec and Sloboskoy 37 developed a comprehensive theory and derived a general equivalent circuit for the MOS capacitors. Nicollian and Golzberger 38 paid special attention to the conductance of interface states in "thick oxide MOS capacitor" ˙. The meaning of "thick oxide" is that the interface states are in equilibrium and close communication with the semiconductor band edges. They also developed a model to evaluate the equivalent conductance G P /ω that consists C o n d e n t i a only interface states density and its time constant from the parallel capacitance-conductance (C p -R p ) circuit 38 .

For the special case where interface states communicate with both gate metal and semiconductor band edges, Freeman and Dahlke 24 developed the theory as well as the corresponding equivalent circuits. Different possible limiting processes were also discussed. The approximated equivalent circuits corresponding to each limiting case were also proposed. Since then, there were different discussions about the possibilities and opportunities to employ gate tunneling into interface states to measure a wide range of interface states density 25,39,40 . Kar and Dahlke 25 performed the experiments on Si/SiO 2 MOSCAPs with moderate oxide thickness and a nondegenerate Si semiconductor to investigate interface states thanks to gate carriers injected to interface states.

In an ideal case, where only the unavoidable series resistance of the drift layer is involved, the equivalent circuit of MOSCAP can be represented by Fig. 4b). In case of single level interface states involved in thick oxide MOSCAP (without leakage current), the equivalent circuit is represented as in Fig. 4c).

In our O-diamond MOSCAPs, corresponding to the current mechanism suggested in Fig. 4a), we introduce an equivalent circuit as in Fig. 4d). Non-perfect gate oxide with gate leakage currents is modeled by an oxide conductance G ox and an oxide capacitance C ox in parallel. The flow of carriers from metal to semiconductor is injected to the mid point of the interface states recombination circuit, as proposed by Freeman et al. 24 . This general equivalent circuit can be further simplified by the approximations corresponding to the leakage current limiting process.

Approximation

The O-diamond MOSCAP equivalent circuit will be simplified to the approximated equivalent circuits depending on the limiting transport processes of the leakage current. We remind that the equivalent circuit in the general case is shown in Fig. 4c. In the theoretical model of Freeman and Dahlke 24 and in the experiments and analysis of Kar and Dahlke 25 , different limiting processes and their corresponding approximations were discussed. We will briefly reintroduce these approximations here for the purpose of clarification.

As the carriers readjustment to interface states (step III) and drift in semiconductor (step V) are expected to be much faster compared to two other processes, we will only consider the interface states recombination limited and the oxide tunneling limited.

a. Interface states recombination limited The interface states recombination is limited when the interface states recombination time constant is much longer than the oxide tunneling time constant (τ R >> τ T ). In other words, the oxide tunneling rate is much higher than the interface recombination rate. The interface states will thus be in equilibrium with the gate metal. In this case, the interface states recombination limited was found to modify the Schottky barrier height due to the charge accumulated at the interface states 26-28 . Therefore, a selfconsistent calculation is necessary to be performed in order to not violate the Gauss's law equations, as discussed by Werner et al. 27 . The rigorous self-consistence calculation was done by Muret 28 and also Wegner et al. 27 for Schottky diodes with a thin oxide layer.

In case of a MOSCAP system, the approximated equivalent circuit for the interface recombination limited was introduced by Freeman and Dahlke 24 and Kar and Dahlke 25 . The approximated equivalent circuit is shown in Fig. 5a) where interface states recombination is in equilibrium with the gate metal and interface states are in the same potential as the oxide potential. In this circuit, G it is equal to 1 Rit . One important notice is that, in case interface states recombination limited, the measured conductance is frequency independent 24,25 .

b. Oxide tunneling limited When the oxide tunneling time constant is much longer compared to the interface states recombination time constant τ T >> τ R , the limiting process is the oxide tunneling. This means that interface states are considered to be in equilibrium with the semiconductor 24,25 and so, the injection from metal to interface states is approximated by an injection from the gate metal to the semiconductor. Interface states therefore will play a similar role as in the "nonleaky thick oxide" model where the interface states are in equilibrium and close communication with semiconductor band edges. In this circuit, G dc is approximated to G ox in Fig. 4b. The approximated equivalent circuit for oxide tunneling limited is shown in Fig. 5b).

A major difference between interface states recombination limited (Fig. 5 a) and oxide tunneling limited (Fig. 5b) is the measured conductance-frequency characteristics. For the purpose of comparison, the measured conductance circuit is the parallel conductance-capacitance C p -R p circuit in Fig. 5f). In case of oxide tunneling limited, the measured conductance is frequency dependent, as shown in Fig. 5b). For the case of interface states recombination limited (Fig. 5a), the measured conductance is frequency independent 25 .

Considering our O-diamond MOSCAP in this work, the measured conductance frequency dependent 15 indicates that the oxide tunneling process is the limiting process. The interface states recombination limited is possibly responsible in case of high injection MOSCAPs (e.g. current density ≥ 1 A/cm 2 at -8 V). In that case, the carriers injection from gate metal is sufficient to preserve interface states in equilibrium with the gate metal. The sample MOS #4 in Chicot et al. 10 and the sample 4 × 10 19 cm -3 boron doped diamond in Kovi et al. 12 are most probably interface states recombination limited.

As a consequence from the previous analyses, the oxide tunneling process was identified as the limiting process in our MOSCAP test devices. However, since oxide tunneling is indeed a two step process, a further approximation is needed. Bearing in mind that the limiting process for oxide tunneling is either bulk oxide limited (hopping between traps to traps) or interface limited (tunneling from gate metal to oxide trap states). The difference is due to the nature of the contact between metal and oxide, i.e. an ohmic contact or an unsaturated contact 41 . Ohmic contact indicates the strong injection of carrier from metal electrode to oxide layer. Unsaturated contact indicates the low injection of carrier from metal electrode to oxide layer. Depending on the nature of metal/oxide contact, I(V) characteristics will exhibit a specific power law of I = AV α . Therefore, in order to examine the power law of MOSCAPs and the contact nature at metal/oxide interface, we introduce the I(V) curves in the log-log plot. Figure 6 a) and Figure 6 c) represent the power law of two typical MOSCAPs: low injection MOSCAP (MOS50 -sample #1) and high injection MOSCAP (MOSA1sample #1), respectively.

C o n d e n t i a l

! Cac! Rs! G ac! Gdc! Cp! G p! Cc! Rs! Gc! C c! Rs! Gdc! Gac! Cox! Csc! Rs! R it! Gdc! C it! Cox! Csc! Rs! G it! C it! a) b) c) f) e) d)
For the low injection MOSCAP at RT (Fig. 6 a)), the I ∼ V 5 law indicates that the metal-oxide contact in this device is the unsaturated contact. The interfacelimited traps assisted tunneling 42 mechanism is probably governing this low injection MOSCAP at RT.

To study the thermal activation process, we measured the I(V) characteristic of the low injection MOSCAP at different temperatures, ranging from 160 K to 360 K. Figure 6b) represents the Arrhenius plot current density versus temperature of the low injection MOSCAP, measured at three different gate bias: V G = -8 V , -6 V and -4 V . From the slope, the thermal activation energy at different gate bias can be evaluated. The thermal activation energies are varying from E A = 260 meV at V G = -4V to E A = 208meV at V G = -4V . As suggested from the generalized thermionic trap assisted tunneling model 42 , this thermal activation energy is assigned to the barriers between metal and Fermi-Dirac occupancy function of the oxide trap states (Fig. 4a). This thermal activation energy variation with gate bias is in agreement with eq. 12.

For high injection MOSCAP (MOSA1 -sample #1), the I(V) characteristics at different temperatures from 160 K to 360 K are shown in Fig. 6c). At RT, the I ∼ V 2 of Child law Space Charge Limited Current (SCLC) 43 is identified (Fig. 6c). This power law indicates that the metal-oxide contact of this MOSCAP is an Ohmic contact at RT and the limiting process is the trap-totrap hopping process in the bulk of the gate oxide.

Figure 6d) represents the current density measured at V G = -8 V versus temperature of the high injection MOSCAP. The J-T curve is well fitted by a e ( T 0 T ) 1/4 law, which is characteristic of variable range hopping (VRH) 44 . This further confirms the trap-to-trap hopping space charge limited current in the high injection MOSCAPs.

In summary, this analysis demonstrates that one of the most important origin responsible for the leakage current of O-diamond MOSCAPs is the trap states in the gate oxide. To improve the gate control diamond semiconductor, the gate oxide leakage current must be minimized by introducing a new process that could limit both the metal/oxide interface injection and traps to traps hopping in the bulk of the oxide layer.

V. INTERFACE STATES OF AL2O3/O-TERMINATED DIAMOND

This section is dedicated to the investigation of interface states properties at Al 2 O 3 /O-terminated diamond interface. Thanks to the small signal equivalent circuit discussed above, we will be able to use a corrected conductance method in order to determine the interface traps density and their energy location within the diamond bandgap.

A. Equivalent conductance Gp/ω

The conductance of interface states (G it = 1 Rit where R it is the one of Fig. 4c represents the energy loss due to carrier transfer between semiconductor band edge and interface states after a disturbance of a small ac signal. In more details, it can be understood as the supplied small ac signal in both halves caused the disturbance and drive the system between semiconductor band edge and interface states become to be out of equilibrium. Therefore, there are carriers transferred between interface states and band edge. However, the carrier transfer is not instantaneous after the signal was supplied but lag behind and caused the loss. The losses are minimized or the conductance is maximized when the applied signal is equivalent to the resonant frequency of the interface states. With the applied frequency lower than the resonant frequency, carriers are stored at the capacitance of the interface states but not transferred. Subsequently, the conductance of the interface states is decreased. Therefore, the conductance of interface states which is bearing the information of interface states should have a bell shape. In the conductance method, the goal is to obtain the equivalent interface states conductance from measured conductance and capacitance (C p -R p ).

In order to obtain the equivalent interface states conductance, measured parallel conductance and parallel capacitance are necessary to be corrected in order to eliminate the series resistance, the DC current and gate oxide capacitance. In this work, the circuit transformation follows the procedures introduced by Kar and Dahlke et al. 25 and by Vogel et al. 45 .

From the measured conductance and capacitance, the corrected conductance with series resistance of Fig. 5f) is given by:

C c = C p (1 -G p R s ) 2 + ω 2 C 2 p R 2 s ( 19
)
and the corrected capacitance by:

G c = ω 2 C p C c R s -G p G p R s -1 (20)
Then, G ac in Fig. 5e) is obtained by:

G ac = G c -G dc (21)
where the conductance G dc is determined from the slope of the DC current versus DC voltage curve at a given gate bias voltage dI dc dV dc VG

. Then, the ac conductance G ac must be corrected with the gate oxide capacitance C ox to obtain the equivalent conductance G P /ω by using the equation:

G P ω = ωC 2 ox G ac G 2 c + ω 2 (C ox -C c ) 2 (22)
For the purpose of comparison the interface states density with Terman's method, we will present here the data measured on the MOS 12 on sample #1). The equivalent conductance at different gate bias are shown in Fig. 7a). The equivalent conductance shows the clear bell shape feature with a clear maximum GP ω max peak. As mentioned above, the frequency corresponding to the GP ω max is equivalent to the resonant frequency of interface states. By varying the gate bias from -8 V to -4 V (MOS 12 -sample #1), the GP ω max are gradually moving toward the lower frequency since the Fermi level is moving away from the valence band.

B. Interface states properties

From the equivalent conductance G P /ω, the interface states density can be calculated as 38 :

N it = 2 G P ω max /q (23)
C o n d e n t i a l 0 1 2 3 4 5 10 with GP ω max the maximum of the GP ω

-8 V -7.5 V -7 V -6.5 V -6 V -5.5 V -5V -4.5 V -4 V Simulation Omega (hz) G P /ω (S/sec) ω (1/sec) V ac =20mV! @RT! MOS 12 -#1! a)! V ac =20mV! @RT! MOS 12 -#1! b)! FIG.
curve. The open red circle curve in Fig. 7b) represents the interface states density extracted by conductance method versus the corresponding energy of the trap states in diamond band gap. The energy level of the trap states is then calculated by using the equation:

E it (V G ) -E v = Ψ s (V G ) + φ p (24)
where Ψ s (V G ) is extracted in the previous electrostatics section and φ p kT q ln Nv NA , which is assumed to be 0.37 eV in the case of moderate boron doped diamond.

A notable difference of the interface states density extracted from the conductance method compared to the interface density extracted from Terman's method (the open black circle curve in Fig. 7b)) appears near the valence band. While Terman's method gives an elevated interface states density up to 4 × 10 13 cm -2 at E it -E v = 0.6 eV, the results from the conductance method are approximately one order of magnitude lower in the same energy range.

This discrepancy is attributed to the gate leakage current and subsequently, the potential drop in the gate oxide. In Terman's method 22 , the variation of semiconductor surface potential Ψ S with gate bias V G is completely attributed to the interface states at the semiconductor/oxide interface. It is true when leakage current through the oxide is negligible. However, when the DC current is sufficient, the potential drop in the gate oxide is non-negligible. Therefore, in high injection regime, Terman's method highly overestimates the interface states density and cannot be used to evaluate the interface trap density.

In the conductance method, the contribution of DC current is actually excluded by equation 21. The final interface states density will therefore exclude the contribution from DC current. Electrostatic simulations using the interface states density extracted from Terman's method and from the conductance method have further demonstrated the accuracy of the conductance method 15 . We conclude that the interface states density extracted from the conductance method is more reliable than Terman's method. By assuming that the interface states are single level states 38 , i.e. Dirac energy distribution for the density of the trap, the equivalent conductance G P /ω can be simulated by using the equation:

Ψ S -V G MIM HF MOS Gp/ω τit DC I-V VG(V) Cox(pF) Csc(pF) Cit(pF) Rit(MΩ) G dc (
G P ω = C it ωτ 1 + ω 2 τ 2 (25)
where τ is the characteristic time constant of interface states and is determined at GP ω max , where ωτ = 1. The interface states capacitance C it can be determined from the peak of the equivalent conductance G P /ω as C it = 2 GP ω max . Knowing all parameters, the measured equivalent conductance can be simulated using equation 25 for the single level interface states model. The simulation curves by using single level interface state model and the parameters extracted from the conductance method are in agreement with the experimental curves for the bias range -4V ≤V G ≤ -8V 15 , as depicted in Fig. 7a). We conclude that the single level interface state model is sufficient to describe the interface states at the Odiamond/Al 2 O 3 interface. The similar results are also obtained for sample #2.

VI. CAPACITANCE-FREQUENCY DEPENDENCE

This section is dedicated to reproduce the capacitancefrequency characteristic of the O-diamond MOSCAPs by using the small-signal equivalent circuit introduced in the previous section (Figure 5b). The impedance simulation is performed with LTSPICE software.

One can note that all the parameters of the equivalent circuit have been experimentally extracted. The oxide capacitance C ox was measured by using the MIMCAP. The semiconductor capacitance C sc (V G ) was evaluated from MOSCAP capacitance measurements at "middle frequency regime"(f = 100 kHz), as described in section III. Series resistance R s can be determined from the "real part" of impedance measurements in the "high C o n d e n t i a l frequency regime" f = 1 MHz 15 . The DC conductance is obtained from the statics I-V characteristics of the test device by using G dc = dI dc dV dc . It must be noticed that G dc (ω) = G ox (ω) + 1 Rit is frequency dependent due to the hopping process which is represented by G ox (ω) . However, from MIMCAP measurements, a negligible frequency dependence was measured in this frequency range. The G ox variation from MIMCAP is lower than 10 nS for frequencies ranging from 1Hz to 1kHz 15 in Fig. 8 along with the capacitance-frequency dependent curves measured from MOS 12 -sample #1. The simulations using the proposed equivalent circuit and all extracted parameters reproduce the measured capacitancefrequency dependence of the O-diamond MOSCAP. We conclude that the capacitance-frequency dependence of the O-diamond MOSCAPs is originated from the complex charge transfer process from metal to oxide and recombine with diamond valence band at the interface states.

In summary, the comprehensive electrical characterization, analysis and simulations have demonstrated that the complex charge transfer process from gate metal to gate oxide, traps to traps hopping in bulk oxide and the interface/valence band recombination is the origin of the parasitic leakage currents, FLPE and capacitance-frequency dependence observed in the Odiamond MOSCAPs. Therefore, in order to eliminate these artifacts, it is very important to improve the oxide crystallinity, to increase the oxide thickness to decrease the hopping rate and to improve the interface of the O-diamond/Al 2 O 3 interface.

VII. CONCLUSION

In summary, the comprehensive electrical characterization, analysis and simulations have demonstrated that the complex charge transfer process from gate metal to gate oxide, traps to traps hopping in bulk oxide and the interface/valence band recombination is the origin of the parasitic leakage currents, FLPE and capacitance-frequency dependence observed in the Odiamond MOSCAPs. 1. When the O-diamond MOS capacitor is under negative bias, the FLPE was observed due to interface states and carriers injection from the gate metal. The accumulation of majority carriers (holes) was not obtained.

2. When the O-diamond MOS capacitor is under positive bias, an ecient control of the Space Charge Region (SCR) width in diamond was obtained. This special feature opens an opportunity to realize a depletion mode diamond MOSFET (D-transistor).

First, we will briey introduce about the general concept of a transistor. The rst transistor is realized in 1947 at Bell lab by Bardeen and Brattain [25]. with a Bulk/Substrate contact (B). In a proper transistor, when V DS is applied, the current owing between S and D (I DS ) is controlled by the voltage between G and S (V GS ). An enhancement mode MOSFET is usually a normally OFF transistor where the channel and/or Drain-Source regions have a high impedance for V GS = 0 V. A depletion mode MOSFET is usually a normally ON transistor where the channel has a reduced impedance when V GS = 0 V. Even if there are certain dierences between an enhancement MOSFET and a depletion MOSFET, their typical electrical characteristics are relatively similar. Typical electrical characteristic of a MOSFET is shown in Fig. 3.1b. For a small V DS , I DS increases linearly with V DS . This is the linear region where the transistor is working like a resistor. For a high V DS , I DS saturates with the increase of V DS . This is the saturation region where the transistor is working like a current source.

The magnitude of the saturation current is actually controlled by V GS . For V GS below the threshold voltage (V th ), only leakage current ow between electrodes -OFF state. In this state, the transistor is working like an open circuit. By increasing V DS , breakdown of the device will be observed. Subthreshold leakage current is readily increased due to breakdown event.

In fact, depletion mode transistors are the oldest members of the MOSFET family.

A depletion mode transistor is required in those applications that need a normally-ON switch. Inverter, voltage follower or switch are the obvious applications with a depletion mode transistor. However, most of the eorts in the past were pushed to the enhancement mode transistors. It is because that most of the transistors were realized on narrow band gap semiconductors like Si where the inversion is obtainable and deep depletion is unobtainable. Moreover and to the application point of view, normally OFF devices are preferred in power electronics to reduce the risk of power short circuit. The concept of depletion mode transistors is widely considering recently on dierent III-V or III-O materials, as example in N-type β-Ga 2 O 3 [START_REF] Pd Ye | Depletion-mode ingaas metal-oxide-semiconductor eld-eect transistor with oxide gate dielectric grown by atomic-layer deposition[END_REF][START_REF] Pd Ye | Gan metaloxide-semiconductor high-electron-mobility-transistor with atomic layer deposited al2o3 as gate dielectric[END_REF][START_REF] Higashiwaki | Depletion-mode ga2o3 metal-oxide-semiconductor eld-eect transistors on β-ga2o3 (010) substrates and temperature dependence of their device characteristics[END_REF].

Diamond FET devices

As discussed in Chapter 1, diamond is the ultimate material for power device applications.

Even if some others diamond MOSFETs were already realized, most of them are usually A particular feature of a H-diamond MOSFET is that most of the time the substrate is intrinsic or highly resistive. Therefore, the Breakdown Voltage (BV) is relatively xed by the distance between Drain and Gate (L GD ). The ON-state resistance is xed by the sheet carrier density, the carrier mobility in the 2DHG, the distance between Drain and Source (L DS ), the distance between Drain and Gate (L GD ) and the Gate Length (L G ). Even if there are remarkable results like ON-state current around 100 mA/mm at is another approach which can take benets of bulk diamond properties: by optimizing the drift region doping level (Drain-Gate, its doping and thickness), we can nd a better compromise in channel sheet carrier density versus BV. Indeed, using higher doping levels can increase the peak electric eld [23]. Moreover, boron doped channel resistance will exhibit a negative then positive temperature coecients, where as 2DHG based devices will have a positive coecient.

Bulk controlled diamond transistor

In bulk controlled MOSFET, the substrate doping concentration is optimized (BV vs. R on compromise). The BV is xed by the Non-punch though (NPT) design. The ON-state resistance is a consequence of the drift region design L GD , channel region L G and conduction region L GS . R on typically exhibits a negative then positive temperature coecient [23]. Courtesy of Umezawa et al. [16].

Diamond MESFETs that were introduced by Umezawa [16] are the rst properly bulk controlled boron doped diamond transistors. Figure 3.3 represents the cross-section structure and top view structure of the diamond MESFETs. High breakdown voltages (≥1500 V) were obtained [16]. ON-state currents were highly limited by contact resistance. The ON-state is suciently improved by increasing the temperature, with an improvement by a factor of 3 between RT and 300

• C. The demerit of this structure is the constraint in doping concentration (≤ 10 16 (cm -3 )) of the epilayer to limit the gate leakage current of the Schottky contact [START_REF] Traoré | High power diamond Schottky diode[END_REF]. As a consequence, the drift region can not be ideally optimized as in Chicot et al. [23], targeting higher doping levels where BV of the order of kV are desired. Also, in p-type MESFET device, only positive bias can be applied by gate metal because the Schottky contact between gate metal and diamond epilayer.

Therefore, accumulation regime in p-type semiconductor can not be obtained. In some moderate breakdown voltage device (about 1 kV), this limitation is undesired to improve C o n d e n t i a l

Methodology 129

ON-state current. The utilization of a gate insulator can circumvent these constraints, allowing one to increase the doping level of the epilayer as well as biasing the gate metal in negative bias voltage toward accumulation.

The aim of this chapter is to introduce the rst design and proof of concept to realize a depletion mode diamond MOSFET. After the introduction, we will present the design, the fabrication process, the electrical measurements and the 2D nite element simulations.

The electrical measurements on the test devices such as Transmission Line Model (TLM)

and MOS capacitors will be presented in the next part. The electrical characteristics, their analysis and the 2D simulation of the diamond transistor in both the ON-state and OFF-state are followed. Finally, the chapter will be concluded.

Methodology

Transistor design

We will rstly present in details the design of our transistors in the following sections.

Cross-section

The conceptual cross-section structure of the device is shown in Fig. The p-n junction is formed because 1b diamond substrates are highly Nitrogen (N) doped with the assumed N concentration of 3 × 10 19 cm -3 [22]. The expected depletion width in the epilayer at substrate-epilayer interface is calculated by the relationship:

W epi = 2 ε sc kT 2q 2 N D 1 1 + N A/ N D ln N A N D n 2 i (3.1)
where N D is the [N] donor concentration of the substrate, N A is the [B] acceptor concentration in the epilayer, n i is the intrinsic carriers concentration. Figure 3.5 represents the expected depletion width in p-type epilayer with dierent doping concentration [22].

N A <<N D! The details of the two sample parameters and processing conditions are presented in Regarding the dimensions of the device, the distance from Source to Gate (L GS ) is kept constant as L GS = 4 µm during this experiment. Two values of the gate width (L G ) are chosen as L G = 3 µm and L G = 4 µm. These values have been a consequence of sucient margin to the fabrication point of view, but both L GS and L G can be reduced: L GS must be designed to prevent gate to source breakdown (both in air and in diamond), where L G must be reduced as much as possible (lithography and gate technique limits).

We are then varying the distance from Gate to Drain as L GD = 2 µm, 3 µm, 5 µm, 10µm. The L GD = 10 µm is expected to obtain the highest V BD for the low doped sample (sample #2, with a dependence of BV on L GD ). For the highly doped sample, short L GD is expected to obtain a low R ON , where larger L GD must not modify the BV.

Top view

We intentionally introduced dierent device structures to target high voltage, high total current and bidirectional devices (double gated transistors), while investigating the eect of total active area and key parameters sweeping. The devices designed are the stripe structure (one short nger), the circular structure (optimized 3D electric eld distribution), the multiple-nger structure and double gate structure (bidirectional voltagecurrent transistors).

For this rst proof of concept, two lithography levels are considered: ohmic contact (drain and source metallization -in red color in Fig. 3.6 to Fig. 3.7) and gate metal (in yellow color in Fig. 3.6 to Fig. 3.7).

To target a high ON-current device, wide transistors are required. We employed then the stripe structure and nger structure, as shown in Fig. 3.6. For the stripe structure, three dierent channel widths (W = 30 µm, 100 µm, 150 µm) were designed.

As explained herein below, nger based transistors are designed for the purpose of ON state measurement.

A problem with the stripe and nger structures is the edge eects that could lead to premature voltage breakdown. In order to minimize the edge eects, we designed

Fabrication

Boron doped diamond epilayers were grown on a 4 × 4mm 2 Ib High Pressure High Temperature (HPHT) Nitrogen-doped substrate. Detailed conditions on diamond growth and doping controlled were addressed in chapter 2 and also previous PhD of the group [4,22,[START_REF] Traoré | High power diamond Schottky diode[END_REF]24].

For the device fabrication, dierent processes in series are needed. The detail owchart of devices fabrication processes are shown in Fig. 3.9.

After the growth of epilayers, dusts were removed by using conventional solvent in ultrasonic condition. Then, graphite and non-diamond phase were removed by using conventional cleaning recipe of a three acid mixture (H 2 SO 4 , HN O 3 and HClO 4 ) at 300 • C, as shown in step 1, Fig. 3.9.

For the fabrication process, positive photoresist S1805 was coated on top of epilayer by using conventional spin coating which produces a thickness approximately 5 µm, as shown in the step 2 -Fig. 3.9. Laser lithography (Heidelberg DWL66FS) was employed to dene the contact area. In order to obtain the expected device structure, two steps of lithography were performed (step 3 and step 7 -Fig. 3.9). After lithography process, the substrate is going through the develop and plasma etching to remove residual photoresist on the patterned region before metal deposition. Plassys ebeam evaporator was used in ior, an annealing at high temperature was required [START_REF] Chen | Ohmic contacts on p-type homoepitaxial diamond and their thermal stability[END_REF]. In order to form ohmic contact, the samples were annealed at high temperature (600 • C for sample #1 and 700

• C for sample #2) in vacuum environment with typical pressure of 10 -8 (mbar) in the step 5 -Fig. 3.9. The diamond surface were then oxygenated by using deep UV-ozone treatment [START_REF] Teraji | Low-leakage p-type diamond schottky diodes prepared using vacuum ultraviolet light/ozone treatment[END_REF]. Al 2 O 3 gate oxide were deposited at 380 • C by using Savannah 100 deposition system from Cambridge NanoTech in the step 6 -Fig. 3.9. The precursor was Trimethylaluminium (TMA) and oxidant was water. The pulse and exposure duration were 15 ms and 30 s, respectively. Typical chamber pressure was 1.3 × 10 -1 (Torr).

Measurements

Devices were probed by employing a homebuild micromanipulator system in the Field Emission Scanning Electron Microscope (FESEM) chamber [START_REF] Tchoulan | Direct imaging of pn junction in coreshell gan wires[END_REF]. For the MOSFET measurement, a two channel Keithley 2636 Source Meter Unit was used. For the test devices (i.e. MOS capacitors) a Solartron Modulab was used, with an AC voltage V ac = 20 mV and the frequency ranging from 1 Hz to 1 MHz.

Simulation

For device simulation, Silvaco 2D Atlas [START_REF]Inc. silvaco. atlas user's manual[END_REF] was employed. Simulation is performed in this work for a two fold purpose: Firstly, thanks to existing models that were developed previously in our group [23,[START_REF] Maréchal | Model implementation towards the prediction of j (v) characteristics in diamond bipolar device simulations[END_REF]24], a nite element analysis will be conducted on diamond MOSFET. The simulation results will be compared with experimental results.

Thanks to the simulations in 2D structure, visualization is easier and further support for the understanding. However, since the simulation models are not really completed (oxide charges, interface states and leakage current were not included), a further improvement will be required. In the second fold purpose, parameters that were extracted from the experimental results will be provided for an empirical model. This is an important step since diamond is a relatively new material. Many parameters are still unknown. Considering the fact that experiments for diamond power devices are costly and time consuming, an as completed as possible simulation model is highly desired.

Since the eorts to build a simulation model for diamond power devices were started previously and there are number reports in literature [START_REF] Maréchal | Model implementation towards the prediction of j (v) characteristics in diamond bipolar device simulations[END_REF]23,24], only brief details on the models will be provided in the frame of this thesis. Interested readers could nd more physical insights of the simulation models in the corresponding references [START_REF] Maréchal | Model implementation towards the prediction of j (v) characteristics in diamond bipolar device simulations[END_REF]23,24].

The 2D simulation conguration is shown in Fig. 3.11. We introduced the parameters that are identical with experiment for the purpose of reproducing the experimental structure. A diamond epilayer with the doping concentration of 2 × 10 17 cm -3 , compensation concentration of 10% and the thickness of 100 nm were introduced (i.e. sample #1).

This epilayer thickness is introduced by subtracting the p-n junction depletion width. In fact, in the simulation, the temperature can be swept to reproduce the experimental condition. Also, the impact ionization coecient [29][132] can be introduced [24] to predict or reproduce the breakdown voltage dependent on avalanche mechanism.

Structure dimension

Results and Discussion

Hereinafter, we will present the results of test devices and the diamond transistors obtained, with a special focus on sample #1. Due to the high resistance issue, the C-V measurement is not trivial. In order to perform a proper C-V measurement and eliminate series eect, an appropriate frequency is necessary. We performed Capacitance-frequency (C-f ) measurement with a xed gate bias (V G = -3 V ) to determine the appropriate frequency range. Figure 3.13c represents the C-V curve measured at three dierent frequencies (f = 300 Hz, 400 Hz, 500 Hz). The C-V behavior is almost identical with the C-V curve obtained from the MOS capacitor with the p+ layer. Fermi Level Pinning (FPE) eect is observed in negative bias regime at high leakage current. Capacitance-frequency dependent eect is also observed. In positive bias, the SCR extension is clearly obtained. It is remarkable that the capacitance value is signicantly decreasing for V G ≥ +4.3 V. Then, the capacitance is completely saturated at a very low value for V G ≥+7 V. This is an indication of the collapse of two SCRs where the eective area of the capacitor is greatly reduced. The transition is perhaps due to the non-homogenous charge distribution in the oxide region. Inverse square capacitance (1/C 2 ) is plotted against V G in Fig. 3.14 to extract the doping concentration from the relationship: The linear tting curve in Fig. 3.14 shows that there is an almost linear curve for the gate bias ranging from -3 V < V G < +4.3 V. A doping concentration of approximately 1.75 × 10 17 cm -3 is extracted by using the slope in this range. This extracted doping concentration is close to the boron-doping concentration targeted during the diamond growth.

N A -N D = -2 εε 0 A 2 1 dC 2 /dV
By employing the technique we have introduced in the Chapter 2, the expansion of the SCR with gate bias is also evaluated. First of all, we evaluate the variation of semiconductor surface potential Ψ S with gate bias V G , as shown in Fig. 3.15a. The corresponding SCR variation with gate bias is shown in Fig. 3.15b. Oxide capacitance is assumed to be C ox εoxε 0 tox with ε ox 9 oxide dielectric constant and t ox = 20 nm oxide thickness.

From Fig. 3.15b, a SCR width of approximately 190 nm at V G +4.5 V is deduced. From this SCR width, we can deduced that a sacriced epilayer thickness of h 40nm is initially depleted at the p-n junction of epilayer-substrate interface. The substrate is probably less N-doped than the assumed value (N D 3 × 10 19 cm -3 ). For an ecient transistor, along with the eectiveness SCR width modulation, ohmic contact is also very important. In order to evaluate the contact resistance, we introduced the Transmission Line Model (TLM) test device.

As in any semiconductor electronic devices, ohmic contact is very important to maximize ON-state current. TLM is fabricated to examine the ohmic behavior of the contacts and also the sheet resistance of epilayer.

Transmission Line Model (TLM)

First, we will briey discuss the working principle of TLM. TLM is an array of electrode pads that have an identical size with dierent spacing between the pads, while controlling the current spread between the contacts. The measured resistance between two electrode pads is the summation of two contact resistances and sheet resistance. R T can be calculated as:

R T = 2R C + R S L W (3.3)
where L is the distance between two electrodes, W is the width of the electrodes, R C is the contact resistance and R S is the semiconductor sheet resistance. Assuming the contact resistance and sheet resistance are homogeneous over the sample size, the measured resistance is then a function of L. For an accurate contact resistance measurement, mesa etching is required [START_REF] Chen | Ohmic contacts on p-type homoepitaxial diamond and their thermal stability[END_REF]. However, in the rst approach, we tuned the fabrication processes to quickly demonstrate a rst proof of concept for depletion mode diamond MOSFET. Therefore, for the sake of simplicity in the fabrication, mesa etching was not performed in the current study, as this step was not necessary for the rst designs of diamond transistors. The lack of mesa etching step played a relatively important role on TLM electrical characteristics. For instance and for the pads with a short spacing (L < 75 µm), the measured resistance is strongly deviated and the obtained value are usually unreasonable. This can be explained as current spreading is not evenly distributed (W >> L), and a signicant part of the current ow is not perpendicular to the LTM contacts. Fortunately, the pads with a long spacing (L ≥ 75 µm), the TLM is worth of interest. The measured resistance is consistent with the pads spacing. is important to refer to the comprehensive discussion by Tachibana et al. [START_REF] Tachibana | Correlation of the electrical properties of metal contacts on diamond lms with the chemical nature of the metaldiamond interface. ii. titanium contacts: A carbide-forming metal[END_REF]. The ohmic contact is actually formed thanks to a defective region at the interface between diamond and metal electrode, which is mediating the carriers tunneling between metal and diamond. Therefore, the non-ideal ohmic contact is likely indicating a good quality of diamond at the interface. Also, there is a barrier of approximately 0.5 eV between TiC/diamond [START_REF] Tachibana | Correlation of the electrical properties of metal contacts on diamond lms with the chemical nature of the metaldiamond interface. ii. titanium contacts: A carbide-forming metal[END_REF], which is possibly responsible for the non-ideal ohmic contact. The non-ideal ohmic contact will denitely aect the device performance, as we will show in the following parts. Therefore, it is very important to improve the ohmic contact in the upcoming approaches. From the interception of tting curve with y-axis, contacts resistance 2R c 11 (M Ω) has been determined for the TLM with the width W=150 µm. A normalized contact resistance 2R c .W = 175 kΩ.cm is obtained. This normalization has been employed since the 2D simulation has shown that all the carriers are being collected at the boundary of the contact pads toward the another one (will be shown in Fig. 3.23b).

Transistor Performance

ON-State

Transistor transfer characteristics I DS were measured by sweeping V DS from 0 V to -10 V at dierent xed V GS , ranging from -5 V to +10 V. since I DS = 0 at V GS = 0 V and V SD > 0 V. A maximum ON-state saturation current of around 1, 9 µA/mm is measured at RT. This ON-state saturation current at RT is comparable with the diamond MESFET reported by Umezawa [16]. However, this ON-state current is much lower than the reports from H-diamond MOSFET [START_REF] Kawarada | Ch surface diamond eld eect transistors for high temperature (400 c) and high voltage (500 v) operation[END_REF][21] and inversion diamond MOSFET [14]. One of the problems with this transistor is the non-ideal ohmic contact which is highly limiting the ON-state current. Also, since the FLPE prevents diamond from reaching the accumulation regime, the ON-state current is partially limited.

Last but not least is the contribution from incomplete ionization of boron doped acceptor at RT due to the deep ionization boron doped level. A projected ON-state current of few 10 times higher is expected for device working at the high temperature (500 K), assuming contact resistance is not changing by increasing the temperature.

Step V GS 1V! sweeping V DS from 0V to -10V at dierent xed gate biasV GS (V DS : -5V to 10 V, step V GS : 1V). The measurements have been performed at RT in the vacuum chamber of FESEM system.

The Gate to Source leakage current (I GS ) is under the detection limited for the whole V GS range of measurements in this device, as shown in Fig. 3.22b. This negligible gate leakage current demonstrates that this MOSFET is a complete electrostatics gate controlled transistor with an insulated gate.

In the OFF-state, the Drain leakage current is below the apparatus detection limit for a V GS ≥ 7 V. The channel is completely pinched o. This behavior is in agreement with the C-V characteristics of the test device MOS capacitor that we have shown in Fig. Hereinafter, we will present the electrostatics prole of the device with the simulation parameters introduced in Fig. 3.11. For the ON-state simulation, V SD is kept as low as possible (V SD = 1 V in this case) to minimize the potential perturbation under the gate region.

The potential distributions at three dierent gate bias (V GS = -5V, 0V, 6V ) are shown in Fig. 3.23a-c), respectively.

The corresponding electric eld distribution at three dierent corresponding gate bias (V GS = -5V, 0V, 6V ) are shown in Fig. 3.23 d-f ), respectively.

The corresponding hole distribution at three dierent gate bias (V GS = -5V, 0V, 6V )

are shown in Fig. 3.24 a-c), respectively.

V D = -1V! V GS =-5 V ; b) V GS =0 V; c) V GS =6 V; Cutline of the d) potential distribution; e) electric eld distribution; f ) hole distribution. Simulation conguration were presented in Fig. The simulation results are relatively coherent with the experimental results. At V GS =0 V, a part of the epilayer is depleted due to metal-semiconductor work function dierence. However, since the oxide charge was not included, the quantitative agreement was not reached. At high negative gate bias V GS =-5 V, the hole accumulation underneath the gate is observed. As shown from the analysis in Part One of the most interesting part in these simulations is the electrostatics distribution.

As we can see from Fig. 3.23, and Fig. 3.24, fully depletion is observed for a gate bias of V GS = +6 V . Also, the extension of SCR width is almost localized under the gate region. We believe this eect is originated from the low V SD value that were applied, together with a large L G value (larger than the lateral Drain-Gate SCR). In the following section, we assume this eect is still valid for a small V SD in the linear regime.

Transistor parameters

As we discussed in the rst part of this chapter, a transistor is working like a resistor in the linear regime. It is therefore important to distinguish the linear-regime and the saturation regime to extract the parameters of the transistor. In the linear regime, the channel charge density is presumably substantial distributed along the channel [START_REF] Homan | Zno-channel thin-lm transistors: Channel mobility[END_REF].

Therefore, the charge transport is dominated by the drift phenomenon. There is no diusion transport even at low V DS since there is no p-n junction at the contact like in an inversion mode MOSFET [START_REF] Homan | Zno-channel thin-lm transistors: Channel mobility[END_REF]. Figure 3.26 represents the I DS measurements with V GS at dierent xed V SD values. From Fig. 3.21 and Fig. 3.26, the linear regime is determined for a low V DS range of approximately V DS =-0.4 V to V DS =-2 V. by sweeping V GS from +14V to -5V at dierent xed V DS (V DS : -0.1V to -6V). The measurement have been performed at RT in the vacuum chamber of FESEM system.

The channel conductance in the linear region is dened as the slope of I DS -V DS in the Fig. 3.21 and can be evaluated by the derivation:

g D = dI DS dV DS (3.4)
Inverse channel conductance is equivalent with the sum resistance between source and drain.

Contact resistance of the diamond MOSFET

Figure 3.27 represents the descriptive device structure and the equivalent resistance between source and drain. We employed the hypothesis that the current owing between and non-negligible contact resistance.

From the equivalent resistance in Fig. 3.27b, the source to drain resistance can be expressed as:

1/g D = R SD = 2R C + R con + R channel + R drif t (3.5)
This expression is introduced since the gate to source leakage current (I GS -Fig. 3.22b) is negligible. The 2R C being the contact resistance of source and drain, which includes any contribution from the metal resistance and the metal-semiconductor interfaces. R con is the resistance in the conduction region between source and gate. Considering the crosssection structure of the device in Fig. 3.26 and the top view structure in Fig. 3.6, R con can be calculated by:

R con = ρ L GS W (d -h) (3.6)
With L GS is the gate to source distance. R drif t is the resistance in the drift region between gate and drain. The current spreading is assumed to ll completely the epilayer L GS >> epilayer thickness). For a low V SD voltage in the linear regime, the R drif t is calculated by:

R drif t = ρ L GD W (d -h) (3.7)
Where L GD is the distance from gate to drain. The channel region is dened as the region under gate. The corresponding channel resistance is calculated as (hole distribution is neglected and carrier distribution is supposed constant within w):

R channel = ρ L G W (d -w -h) (3.8)
By using the resistivity that was extracted from TLM test device at RT, the R con and R drif t can be calculated. Equation 3.5 can be then rearranged as: Channel thickness (nm)

R SD -R con -R drif t = 2R C + R channel (3.9)
4 3 2 1 0 -1 -2 -3 -4 Gate Bias V GS (V)
Stripe transistor! Sample #1! @ RT! 2RC+Rchannel (MΩ)" As the parameters in the left side of the equation (R SD , R con , R drif t ) were determined, the unknown parameters in the right side of the equation (R C and R channel ) can be determined. By replacing R channel in equation 3.8 into equation 3.9, equation 3.9 can be rewritten as: where d, w, h are the thickness of epilayer, the SCR width at diamond/oxide interface and the SCR width at epilayer/substrate p-n junction, respectively. x = (dwh) is the neutral region width between the 2 SCRs (see Fig. 3

2RC!

R SD -R con -R drif t = 2R C + ρ L G W 1 (d -w -h) = 2R C + ρ L G W 1 x (3.

.26).

As one can see in equation 3.10, the right side of the equation is a function of 1 x and is limited by the 2R C . Therefore, in principle, the value of 2R C can be found by plotting R SD -R GS -R GD against 1

x . With x is the value measured by MOS capacitor test device, assuming the extension of SCR in the MOSFET is similar to the MOS capacitors. In fact, the correlation between transistor electrical characteristics and MOS capacitor behavior as well as 2D Silvaco Simulation have demonstrated this assumption is reasonable for the linear regime. Therefore, the variation of drain conductance in linear regime versus gate bias (I DS vs. V G -linear region, Fig. 3.21 ) is similar to a TLM test device. In this case,

x (equation 3.10) is equivalent to L (equation 3.3). This value is in agreement with the contact resistance evaluated by the TLM technique.

This contact resistance is very high and highly hinders the carriers collection between source and drain. It is therefore very important to improve the contact resistance in the next fabrication run.

Mobility

The carriers mobility between source and drain can be evaluated after eliminating the contribution from contacts resistance 2RC. The intrinsic semiconductor resistance is obtained after eliminating the contribution of the contact resistance as:

R Semi = R SD -2R C (3.11)
With R semi is as dened as in Fig. 3.27, it can be calculated as:

R Semi = ρ L GS + L GD t + L G t -x (3.12)
The carrier mobility under low eld in semiconductor region can be evaluated as:

µ = 1 qpR Semi W L GS + L GD t + L G t -x (3.13)
Considering the hole concentrations that we have projected from TLM measurement, the hole mobility of our device could ranging from µ h 300 cm 2 /V.s for the lowly compensated sample to 1700 cm 2 /V.s for the highly compensated sample. These value of hole mobility is typical for the bulk conduction of boron doped diamond at doping concentration of 2×10 17 cm -3 [11]. This mobility is around the highest reported mobility in a diamond MOSFET, compared to inversion diamond MOSFET (µ h = 8 cm 2 /V.s) [14] and H-diamond MOSFET (30-100 cm 2 /V.s, this mobility has been measured by Hall eect measurement) [START_REF] Kawarada | Ch surface diamond eld eect transistors for high temperature (400 c) and high voltage (500 v) operation[END_REF]. Even this mobility could bearing some source of errors (since contact resistance were too high and compensation concentration has not been systematically quantied), this value highlights the clear benets of a depletion mode diamond

OFF-State

One of the most unique feature of wide bandgap semiconductors is the endurability against a high electric eld in the OFF-state regime. In our device, breakdown voltage is measured by applying a positive gate bias (V GS = +12 V ) to ensure the pinch-o of the channel. Then, V DS is swept in the negative direction from 0 V to -200 V (limit of the apparatus). The current compliance is set as low as 25% ON-states current to limit the destructive high power passing through the device. The measurements have been done

in the FESEM chamber under vacuum.

- abs(I) (A/mm) 3.20b (I D vs. V DS and I G vs. V DS ). Subthreshold leakage current is less than 10 -10 (A).

V DS (V) I D I G V GS =12 V! @ RT! Sample #1! abs (I) (A/mm)! a)! Circular MOSFET! Sample #1! @RT ! I D! I G! abs (I) (A/mm)! b)! V GS =12 V! @ RT! Sample #1! Circular MOSFET! Sample #1! @RT ! I D! I G!
Subthreshold drain leakage current is found rstly decrease when V DS is biasing from 0V to -40V and then increase for V DS from -40V to -200V. This drain leakage current could be related to the potential gradient between Source and Gate as well as Drain and Gate. Since subthreshold leakage current is an important factor could initiate the premature breakdown of the MOSFET devices, a systematic investigation of the subthreshold leakage current mechanism is highly suggested. The device is able to withstand an OFF state voltage up to -200 V without any catastrophic voltage breakdown (sudden increase of subthreshold leakage current). By using the linear electric eld approximation between gate and drain, a lower bound electric eld is evaluated at less than 1 MV/cm for a bias of -200 V. However, since the drift layer is moderately doped (1.75 × 10 17 cm -3 ), this approximation is highly underestimating the peak electric eld of the drift region.

In order to evaluate the breakdown electric eld of the device, we performed a Silvaco

Benchmarks

In order to compare to other diamond transistors [16] cient. This dierence is due to the increase of free carriers with higher temperatures in MESFET, whereas a higher temperature reduces the carrier mobility in 2DHG without positive eects compensating this mobility reduction.

The D-mode MOSFET in this work is represented by the blue circle (measured at RT) and the blue cross (this spot is expected). As we have discussed in the previous section, the ON-state current of this device is highly limited by the contact resistance. In fact, the contact resistance represents more than 90% of the total resistance of the device.

An improvement of the contact resistance will strongly improve the ON-state current of this device. As shown by Chen et al. [START_REF] Chen | Ohmic contacts on p-type homoepitaxial diamond and their thermal stability[END_REF], using a proper post treatment or regrowth a highly doped p+ layer for ohmic contact, the specic contact resistance can potentially be reduced to less than 10 -5 Ω.cm 2 . Taking into account the improved contact resistance, the FOM of our MOSFET at RT is expected to move to the open red circle in Fig. 3.32.

The ON-state current is therefore potentially comparable with the ON-state current of the H-diamond MOSFET [21], albeit with a smaller BV.

Regarding the OFF-state breakdown voltage, as we have shown in the previous part, a spike electric eld at the drain side of gate contact could potentially caused the premature breakdown. In order to reduce the peak electric eld, a eld plate technology is critical in such lateral high voltage devices. It has been demonstrated that by using the eld plate, breakdown voltage is highly improved in the lateral design [START_REF] Hoi Wong | Field-plated ga 2 o 3 mosfets with a breakdown voltage of over[END_REF]. Therefore, the implementation of eld plate(s) is required in the transistor design to allow the ) is expected at approximately 1000 V in the Non Punch Through condition [23].

In the optimized structure for typical high voltage power devices, the ON-resistance is generally mainly due to the resistance of the drift region, which is the smallest total resistance possible for a BV value. Any other source of series resistance must be further eliminated. If one can achieve both the reduction on series resistance along with eld plate structure to maximize the breakdown eld, the FOM of our MOSFET can be improved as the green spots in the Fig. 3.32. Further reductions on the RonS for the same BV can be achieved, but it would require a thicker drift region, where the channel would consequently be more dicult to fully deplete.

The critical challenges with our device architecture is to achieve a high electric eld, and to combine a thick drift region, with a channel exhibiting distinctive ON and OFF states. Nonetheless, new lateral architectures can be further optimized, and the theoretical minimum RonS FOM at RT is plotted in Fig. 3.32 (this is the limit of the vertical devices). The theoretical breakdown voltage vs. specic ON-resistance has been determined by considering the ideal mobility where the scattering mechanisms are purely phonon and doping dependent [11][6].

As far as breakdown voltage is concerned, Chicot et al. [23] introduced an optimization calculation breakdown voltage based on avalanche eect with the up to date ionization coecients [132][29]. As shown in Fig. 3.33, for dierent breakdown voltage 1 kV, 3 kV, 6.5 kV, 10 kV, the optimized doping concentration and drift region is 1.8×10

17 (cm -3 ),

1.9×10

16 (cm -3 ), 5.5×10 15 (cm -3 ), 2.5×10 15 (cm -3 ) and 1.9 µm, 10 µm, 27 µm, 48 µm, Since our MOSFET architecture is based on free carriers from boron doped diamond, the ON resistance can be reduced at higher temperatures. However, the increase of free carrier is compensated by the decrease of carrier mobility, as presented in chapter 1. For each targeted voltage breakdown (i.e. doping level and length of the drift region), it exists therefore an optimal temperature where the Ron is minimized. Such points are presented in Fig. 35 (the black crosses). The key challenges will be now to push the FOM towards those theoretical values, with outstanding performances relatively to other semiconductors devices.

Conclusion

In summary, by using the oxygen terminated boron doped diamond and an optimized C o n d e n t i a l

General Conclusion and Perspective 161

This transistor is normally ON and is working in depletion mode. A clear transistor action with both ON and OFF states was achieved. By fabricating and analyzing the test devices like TLM, MOS capacitors and the combination of 2D simulation and electrical models, the physical parameters of the transistors are evaluated. The high contact resistance is currently limiting the ON-state current, which was expected. The simplied process was selected for the sake of reducing the fabrication time, albeit with large contact resistances. After excluding the contribution from the contact resistance, the hole mobility is quantied. A high hole mobility (from 300 cm 2 /V.s to 1700 cm 2 /V.s) has been evaluated. It is among the highest carriers mobility in a diamond transistor.

A breakdown voltage higher than 200 V is measured. The 2D simulation illustrates a corresponding critical electric eld of 4 MV/cm at the gate edge. The device performance is benchmarked with other diamond transistors, highlight further optimizations. There

is still an open road to improve the performances of lateral and vertical transistors based on CVD diamond.

Perspective

To realize the higher OFF-state breakdown voltage (few kVs), drift region doping concentration are necessary to be reduced and oxide thickness are necessary to be increased (like transistor sample #2). As shown in Fig. 3.34, the transistor of our sample #2 exhibits the clear electrostatics gate modulates source-drain current eects. However, since the epilayer has not been optimized, the OFF-state regime of this device can not be obtained (since reverse leakage current start to appear at high positive gate bias). Therefore, the thickness of epilayer have to be further optimized to ensure that both the ON-state and OFF-state regime of the transistor can be obtained. Investigate the accumulated hole gas will be important to improve the depleted mode boron doped diamond MOSFET, especially in the ON-state. Therefore, fabricate the Hall bar test devices on the same sample to investigate the accumulated hole gas is needed in near future. This Hall bar test device is also required to investigate the compensation of the boron doped diamond epilayer. It will allow us to be more quantitative on transistor analysis.

Regarding ON-state current, as we have demonstrated, the ON-state current of this device is highly limited by the contact resistance. An improvement of the contact resistance is critical. Therefore, optimizing the ohmic contact annealing temperature or performing the selective etching and then regrowth the p+ diamond for ohmic contact is highly desired. Also, optimized transistor structure to eliminate parasitics resistance toward a smallest total resistance possible for a given BV value is highly desired to improve the device performance.

Regarding the OFF-state breakdown voltage, as we have shown in the previous part, a spike electric eld at the drain side of gate contact could potentially caused the premature breakdown. A eld plate technology is critical in such lateral high voltage devices.

C o n d e n t i a l

General Conclusion and Perspective 163

Therefore, the implementation of eld plate(s) is required in the transistor design to allow the diamond reaching its theoretical avalanche breakdown voltage. Identifying the subthreshold leakage current is also equivalently important. Since subthreshold leakage current can be the origin of premature breakdown voltage. Therefore, additional electrical measurements to identify the subthreshold leakage current is critical to understand the premature breakdown voltage and further improve the OFF-state performance.

In the end, thanks to the mastering diamond/oxide interface, the rst proper bulk controlled boron doped diamond power MOSFET has been realized. This will open the new path to realize the other bulk controlled diamond MOSFETs for power devices.

1

Deep-depletion mode boron doped monocrystalline diamond metal oxide semiconductor field effect transistor Thanh-Toan Pham, Julien Pernot, David Eon, Etienne Gheeraert and Nicolas Rouger Abstract-A p-type deep-depletion mode monocrystalline diamond MOSFET is demonstrated for the first time, with a 190nm-thick controllable channel. Such a device offers new opportunities for a better optimization of the bulk doping versus designed breakdown voltage and the resulting figure of merit. Diamond MOSFETs with Boron doping of 1.75 × 10 17 cm -3 and using 20nm ALD deposited Al2O3 as the gate oxide show promising IV characteristics, with a clear ON and OFF state operation. The MOSFETs have a normally-ON operation with typical threshold voltages of VT H = +7V and a ON-state drain current of ISD = 1.9µA/mm at VSD = 10V and VGS = -5V , at room temperature. A high hole mobility from 300cm 2 /V.s to 1700cm 2 /V.s has been extracted both for channel and bulk regions. Just before the experimental voltage breakdown at 200V , the gate leakage is still below 0.6nA/mm at room temperature and the peak electric field in diamond at the gate edge is simulated at 4M V /cm. Beyond this first experimental proof of concept, these combined values show the high potential of deepdepletion mode Boron doped diamond MOSFETs.

Index Terms-Diamond transistor, Boron doped monocrystalline diamond, depletion mode diamond MOSFET.

I. INTRODUCTION

Diamond has unique properties such as a wide bandgap of 5.5eV, a high thermal conductivity of 20W/cm.K, high free carrier mobility and hopping conduction mechanisms. The classical doping techniques of diamond rely on incorporation during growth of impurities with high activation energies (ptype Boron 0.38eV and n-type Phosphorous 0.57eV), with consequently p-type doping as the main approach. These properties can have a high impact in electronics and power electronics applications, where diamond (power) devices can have better performances at high temperatures (400K-700K), with outstanding figures of merit (lower specific ON state resistance R ON S, higher breakdown voltages BV ). Several diamond transistor architectures have been proposed in the litterature, with a special focus on two dimensional hole gas (2DHG) based Field Effect Transistors (FET) [1], [2], Junction FETs [3], [4] and MEtal Semiconductor FETs [5], [6]. Diamond 2DHG FETs require a Hydrogen (H) terminated diamond surface and a specific control of H-terminated surface and adsorbed ions during the fabrication. The ON of 10 -8 (mbar). The diamond surface was then oxygenated by using deep UV-ozone treatment [17]. A 20nm thick Al 2 O 3 gate oxide was deposited at 380 • C by using Savannah 100 deposition system from Cambridge NanoTech. The precursor was Trimethylaluminium (TMA) and oxidant was water. The pulse and exposure duration were 15 ms and 30 s, respectively. Typical chamber pressure was 1.3 × 10 -1 (Torr). As shown in figure 2 and table I, both MOSFET fingers and cylindrical Corbino structures have been fabricated, respectively for better ON state characterization and electric field management in OFF state. The dimensions have been targeted as a first proof of concept, with a limited stress on lithography and fabrication steps.

III. RESULTS AND DISCUSSION

Key parameters have been extracted with test structures on the same sample (MOS capacitors): the boron doping is 1.75× 10 17 cm -3 and the SCR extension in the CVD p-type diamond towards the n-type substrate is 40nm (C-V). The consequent sheet resistance and resistivity of the p-type neutral region is estimated at R sheet = 4M Ω/ , ρ epi = 75Ω.cm (room temperature, doping compensation).

A. ON-State and OFF-State

Figure 3 shows the clear ON-state and OFF-state operations of the depletion mode diamond transistor (#1), with a normally-ON behavior: the maximum drain saturation current is I DS = -1.91µA/mm at V DS = -10V and V GS = -5V , a threshold voltage V T H = +7V and a gate leakage below detection limit over the swept biasing conditions. In the linear regime, the measured specific ON resistance is 162 C o n d e n t a l Ω • cm 2 (active region, without contact areas). Due to the FESEM setup, it was not possible to measure the temperature effects on the transistors. A R ON S of 8 Ω • cm 2 is expected at higher temperatures. As evidenced by Conductance-Biasfrequency analyses, Fermi Level Pinning Effect (FLPE) due to interface states prevents however to achieve the accumulation regime in ON state ([1REF]). The breakdown and OFF-state characterization of the Corbino #2 transistor is presented in figure 4: the maximum breakdown voltage is close to 200V , with a low leakage current close to the breakdown (10 -10 A or 0.6nA/mm). Figure 4c) shows the simulated electric at 200V , with the gate biased in deep depletion regime. The simulated peak electric field in diamond is 4MV/cm, with a SCR width towards drain of 2.5µm. These values show great opportunities for further improvements, with already attractive performances.

B. Carrier mobility

Assumptions: constant doping profile + no carrier gradient + no 2D/3D current spreading. The carriers mobility between source and drain can be evaluated after eliminating the contribution from contacts resistance 2RC R Semi = R SD -2R C , whereas R semi is as defined as in Fig. 1, it can be calculated as: The carrier mobility under low field in semiconductor region can be evaluated as:

µ = 1 qpR Semi W L GS + L GD d -h + L G d -h -l (1)
Considering the hole concentrations that we have extracted from TLM measurement, the hole mobility of our device extracted at different gate biases is ranging from µ h 300 cm 2 /V.s for the lowly compensated sample to 1700 cm 2 /V.s for the highly compensated sample. These values of hole mobility are typical for the bulk conduction of boron doped diamond at doping concentration of 2×10 17 cm -3 [18]. This mobility is around the highest reported mobility in a diamond MOSFET. Even if this mobility could bearing some source of errors (since contact resistance were too high and compensation concentration has not been systematically quantified), this value highlights the clear benefits of a depletion mode diamond FET with an insulated gate. An improved contact resistance as well as the fabrication of the Hall bar test devices on the same substrate for the systematic investigation the compensation of the sample are critical in the next fabrication run.

C. Benchmark

In order to compare to other diamond transistors [6]

IV. CONCLUSION

In summary, by using the oxygen terminated boron doped diamond and an optimized MOS capacitor technology, we have demonstrated a lateral diamond MOSFET. This transistor is normally ON and is working in the deep depletion mode. A clear transistor action with both ON and OFF states was achieved. A simplified fabrication process was selected for the sake of reducing the fabrication time, albeit with large contact resistances. After excluding the contribution from the C o n d e n t i a l contact resistance, the hole mobility is quantified. A high hole mobility (from 300 cm 2 /V.s to 1700 cm 2 /V.s has been evaluated. It is among the highest carriers mobility in a diamond transistor. A breakdown voltage higher than 200V is measured. The 2D simulation illustrates a corresponding critical electric field of 4 MV/cm at the gate edge. The device performance is benchmarked with other diamond transistors, highlighting further optimizations. There is still an open road to improve the performances of lateral and vertical transistors based on CVD diamond. Such improvements will focus on the reduction of series resistance and interface state density, annealing at high temperature to improve the gate oxide crystallinity, reaching the accumulation regime, adding an efficient field plate and optimizing transistor dimensions.

  diamond. The experimental boron ionization energies are taken from the literature[START_REF] Okano | Characterization of boron-doped diamond lm[END_REF][START_REF] Fujimori | Properties of boron-doped epitaxial diamond lms[END_REF][START_REF] Visser | Electrical conduction in homoepitaxial, boron-doped diamond lms[END_REF], Windheim 1993, Borst 1995, Deguchi 1996, Lagrange 1999, Klein 2007, Gajewski 2009, Volpe 2009] and the solid curve is drawn after Pearson and Bardeen law [Pearson 1949]. Phosphorus ionization energies are taken from the literature [Koizumi 1997, Kato 2005, Kato 2007, Pinault 2007, Kato 2008, Pinault-Thaury 2011, Stenger 2013]. Its value is assumed to be constant over the entire doping range. Courtesy of Fiori's PhD thesis [4] . . . . . . . . . . 12

13 1. 10

 1310 The dependence of hole mobility to boron concentration at a) 300 K; b) 500 K. Courtesy of Pernot et al. [11]. . . . . . . . . . . . . . . . . . . . . 14 1.11 O-diamond Schottky diode on homoepitaxial boron doped diamond with a breakdown voltage of 10 kV and a breakdown electric eld of 7.7 MV/cm. Courtesy of Volpe et al. [12]. . . . . . . . . . . . . . . . . . . . . . . . . 16 1.12 Pseudo-vertical diamond Schottky diode and its electrical characteristics, Courtesy of Traore et al. [13]. . . . . . . . . . . . . . . . . . . . . . . . . 18 1.13 Cross-section structure of a) Lightly doped drain inversion MISFET; b) depletion MISFET; c) building block MISCAP. . . . . . . . . . . . . . . 18 1.14 Inversion mode of pMOS phosphorous doped oxygen terminated diamond MOSFET: a) cross-section structure; b) top view structure; c) electrical characteristics. Courtesy of Matsumoto et al. [14]. . . . . . . . . . . . . . iv List of Figures

23 1 .

 1 20 Schematics description of dierent regimes of a MOS capacitor: a) denition of semiconductor surface potential Ψ S ; b) accumulation regime under negative bias; c) depletion and deep depletion regime under positive bias; d) Flatband regime where there are no energy dierent between surface and neutral part of semiconductor. . . . . . . . . . . . . . . . . . . . . . 24 1.21 First propositional structure of a O-diamond MOS capacitor. Courtesy of Chicot et al. [18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.22 Typical J-V and C-V characteristics of some rst O-diamond MOS capacitor. Leakage current in both forward bias and reverse bias is observed. Capacitance are strongly frequency dependent. Courtesy of Chicot et al. [18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.23 a) Pseudo-vertical structure O-diamond MOS capacitor; b) Band alignment between O-diamond and Al 2 O 3 deposited at 250 • C. Courtesy of Marechal et al. [19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.24 Electrical characteristics of the pseudo-vertical O-diamond MOS capacitor, a) C-V characteristic; b) J-V characteristic. Courtesy of Marechal et al. [19] 28 2.1 Illustration of the conduction path in MOS structures; a) without a buried p++ layer; b) with a buried p++ layer. . . . . . . . . . . . . . . . . . . . 35 2.2 a) Conceptual cross-section structure of test devices included Ohmic contact, MIM Capacitors and MOS Capacitors; b) Corresponding plan view of test device structure where MIM capacitors and MOS capacitors are fabricated with dierent shapes and sizes. . . . . . . . . . . . . . . . . . 36 2.3 a) Typical feature of a 1b HTHP diamond substrate; b) Optical prolemeter photograph of the substrate. . . . . . . . . . . . . . . . . . . . . . 36 2.4 MPCVD reactor at Institut NEEL. . . . . . . . . . . . . . . . . . . . . . 37 2.5 Schematics representing the structure and the working principle of the reactor. Courtesy to Fiori's PhD thesis [4] . . . . . . . . . . . . . . . . . 38 2.6 Diamond surface topography after growth measured by a) Optical prolemeter; b) AFM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7 Schematics describing the process for diamond etching and ohmic contact fabrication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 a) Optical prole-meter of the etched mesa structure. . . . . . . . . . . . 40 2.9 Schematic describing MOS capacitors and MIM capacitors fabrication steps. 41 sample #3; b) Conductance-Voltage characteristics of MOS C7 measured at dierent frequencies; b) Capacitance-Voltage characteristics of MOS C7 measured at dierent frequencies; d) Capacitance-frequency of MOS C7 measured at V G = -5V . . . . . . . . . . . . . . . . . . . . . . . . . . .

69 2 . 1 T 4

 214 34 (a) Proposed current path mechanism including ve steps: I. Electron tunneling from metal gate electrode to oxide gate, II. Hopping from traps to traps in the oxide, III. Recombination to surface traps state, IV. Electron from surface states emit to valence band or hole from valence band captured to interface states, V. Carriers drift in diamond epilayer to the back gate contact. (b) Equivalent circuit of a MOS capacitor without interface states and leakage current; (c) Equivalent circuit including interface states and an ideal gate oxide without leakage current (d) Equivalent circuit where the injected carriers from metal to interface states and the charges transfer between interface states and valence band are taken into account. 70 2.35 Proposed current mechanism of dierent processes and its corresponding energy level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.36 DC Capacitance-Voltage non-linearity of MIM capacitors and the tting to extract hopping distance. . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.37 Equivalent circuit for O-diamond MOS capacitor: a) general circuit with gate carriers injected to single level interface states; b) approximated equivalent circuit for interface states recombination limited; c) approximated equivalent circuit for oxide tunneling limited; d)-g) step by step circuit transform to achieve measurement circuit; d) Circuit transformed from circuit c); e) circuit transformed from circuit d); f ) Circuit transformed from circuit e); g) the parallel circuit for measured capacitance and measured conductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.38 a) Semi-log plot Current-Voltage characteristics of high injection MOS capacitor and low injection MOS capacitor; b) the log-log plot to identify the current-voltage power law from linear tting (MOS 1 and MOS 50 -Sample #1) @RT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.39 a) Current-Voltage characteristics of high injection diode measured at different temperatures ; b) Temperature dependence of gate leakage current versus measured at V G = -8V in MOS 1 -sample #1. The logJ versus 1 T 4 dependence well tted by the straight line indicates a variable range hopping in the oxide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures 2.56 a) TEM image of the defective leakage spot; b) Selected Area Electron Diraction SEAD pattern obtained at position A of Figure 2.56a (sample #1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.57 Selected Area Electron Diraction pattern obtained at a) Substrate; b) center of defective leakage spot (sample #1). . . . . . . . . . . . . . . . . 99 2.58 Proposed current mechanism and its corresponding electrostatic band diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.59 a) Current-Voltage of MOS capacitor measured at dierent temperatures, ranging from 150K to 370K; b) Arrhenius plot of current measured at dierent temperatures when gate are biased at V G =7V (MOS A1 -sample #1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.60 Proposed equivalent circuit which is corresponding to the current mechanism for simulating the a.c measurement. . . . . . . . . . . . . . . . . . . 102 2.61 Capacitance-frequency dependent in the reverse regime from a.c measurement (closed black circular) and simulation (red line). . . . . . . . . . . . 104 3.1 a) Typical structure of an enhancement transistor; b) Typical electrical characteristics of a Transistor . . . . . . . . . . . . . . . . . . . . . . . . 127 3.2 Structure of a transistor on H-diamond. a) Cross-section structure; b) Plan view structure. Courtesy of Kawarada et al. [21] . . . . . . . . . . 127 3.3 Structure of the p-type diamond MESFET a) top view; b) cross-section. Courtesy of Umezawa et al. [16]. . . . . . . . . . . . . . . . . . . . . . . 128 3.4 Cross-section structural concept of depletion mode oxygen-terminated boron doped diamond MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.5 Expected depletion region width between substrate and epilayer with different doping concentration. Considering the 1b substrate is highly nitrogen doped (N D = 3 × 10 19 cm -3 ). Courtesy of Chicot's PhD thesis [22]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.6 Transistor structure target high ON-states current a) Stripe structure; b) Fingers structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 3.7 Circular structure transistor target high OFF-state breakdown voltage. . 132 3.8 a) A complete structure of a reticule included dierent device structures and test device; b) The full mask structure includes 3 × 3 reticules and the TLM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.9 The ow chart fabrication process of depletion mode O-diamond MOSFET.134 3.10 Top view FESEM photograph of the completed boron doped diamond MOSFET and test devices (sample #1). . . . . . . . . . . . . . . . . . . 134 3.11 Silvaco simulation conguration with diamond epilayer thickness of 100 nm and doping concentration of 2×10 17 cm -3 , oxide thickness of 20 nm, L GS = 4µm, L G = 4µm, L GD = 3µm, L D = 1µm, L S = 1µm. Substrate were considered as an insulator to minimize the simulation time constant. 136 3.12 Top view of MOS capacitor structures captured by optical microscope. . 137 3.13 Electrical characteristics of MOS capacitor test devices on the diamond transistor sample: a) Current-Voltage characteristic; b) Capacitance-frequency characteristic at V G = -3 V ; Capacitance-Voltage characteristics measured at dierent frequency. (Sample #1 -@RT). . . . . . . . . . . . . . List of Figures ix 3.14 Reciprocal square capacitance plotted with gate bias to extract eective doping concentration (sample #1 at RT). . . . . . . . . . . . . . . . . . . 139 3.15 a) Surface potential variation with metal gate bias; b) Corresponding depletion width variation with gate bias. . . . . . . . . . . . . . . . . . . . 140 3.16 Conceptual description of the TLM test device. . . . . . . . . . . . . . . 141 3.17 a) Typical IV characteristics of the Ohmic contact after annealing at 600 • C; b) Measured resistance as function of electrode spacing with linear tting to extract sheet resistance and contact resistance . . . . . . . . . . . . . 142 3.18 The relationship between compensation concentration N D and resistivity of boron doped diamond at dierent dopant concentration N A . Courtesy to Traore et al. [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.19 The relationship between compensation concentration N D and hole con- centration of boron doped diamond at dierent dopant concentration N A . Courtesy to Traore et al. [10] . . . . . . . . . . . . . . . . . . . . . . . . 143 3.20 FESEM image of the boron doped diamond MOSFET. a) Stripe structure MOSFET target high ON-state current; b) Circular structure target high OFF-state breakdown voltage. Device dimension parameters were taken from mask design. Measurements have been performed at RT in the vacuum chamber of FESEM system. . . . . . . . . . . . . . . . . . . . . 144 3.21 Transfer characteristics of the stripe transistor -sample #1 measured by sweeping V DS from 0V to -10V at dierent xed gate biasV GS (V DS : -5V to 10 V, step V GS : 1V). The measurements have been performed at RT in the vacuum chamber of FESEM system. . . . . . . . . . . . . . . . . 145 3.22 a) Transfer characteristics of the stripe transistor -sample #1 measured by sweeping V GS from +10V to -5V at a xed V DS (V DS =-10V) ; b) Gate leakage current I GS measured instantaneously with transfer I D . The mea- surement have been performed at RT in the vacuum chamber of FESEM system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.

  3.11 and temperature is assumed at RT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 3.24 Silvaco Atlas simulation of the hole distribution at dierent gate bias a) V GS =-5 V ; b) V GS =0 V; c) V GS =6 V; Cutline of the d) potential dis- tribution; e) electric eld distribution; f ) hole distribution. Simulation conguration were presented in Fig. 3.11 and temperature is assumed at RT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.25 Silvaco simulation of drain current (I D ) for V DS = -1V at dierent gate bias (V GS : -5V to +6V) in a) linear scale; b) semilog scale. Simulation conguration is identical with the Fig. 3.11 and temperature is kept at RT. 149 3.26 a) Transfer characteristics of the stripe transistor -sample #1 measured by sweeping V GS from +14V to -5V at dierent xed V DS (V DS : -0.1V to - 6V). The measurement have been performed at RT in the vacuum chamber of FESEM system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C o n d e n t i a l x List of Figures 3.27 a) Descriptive cross-section of the depletion mode diamond MOSFET; b) Equivalent Source to Drain resistance of the MOSFET corresponding to the cross-section and non-negligible contact resistance. . . . . . . . . . . 151 3.28 2RC+Rchannel versus channel thickness (the width of neutral region under gate) at dierent V GS (top x-axis). . . . . . . . . . . . . . . . . . . . . . 152 3.29 Breakdown voltage measured with V GS =-12 V and drain voltage sweeping in negative bias voltage to V DS = -200 V (limit of the apparatus): a) rst cycle breakdown measurement; b) 5th cycle breakdown measurement. . 154 3.30 Silvaco Atlas simulation critical electric eld for V DS =-200 V without im- pact ionization a) in linear scale; b) logarithm scale . . . . . . . . . . . . 155 3.31 Cut line of Silvaco Atlas simulation critical electric eld for V DS =-200V without impact ionization a) In diamond epilayer; b) In oxide layer . . . 156 3.32 Specic ON-resistance versus breakdown voltage of dierent diamond transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.33 Specic ON-resistance vs. dierent breakdown voltage of NPT boron doped diamond devices. Courtesy to Chicot et al. [23] . . . . . . . . . . 159 3.34 Electrostatics gate controlled the current between Source and Drain at dierent gate bias. Transistor sample #2. . . . . . . . . . . . . . . . . . . 161 3.35 a) DC leakage current and b) Capacitance-voltage characteristic measured at 100 Hz of MOS 100um, sample #2. . . . . . . . . . . . . . . . . . . .

Contents 1 . 1

 11 Unipolar device's Figure-of-Merit(FOM) . . . . . . . . . . . . . . 5 1.2 Diamond semiconductor for power devices . . . . . . . . . . . . . 10

1. 4

 4 Metal Oxide Semiconductor Field Eect Transistors (MOSFET) 23 1.4.1 MOS capacitor working principle . . . . . . . . . . . . . . . . . . . 23 1.4.2 O-diamond MOS capacitor . . . . . . . . . . . . . . . . . . . . . . 25 1.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 1 . 1 :Figure 1 . 2 :Figure 1 . 3 :

 111213 Figure 1.1: Power range requirements of various applications (chart is based on Yole Development report).

Figure 1 . 4 :

 14 Figure 1.4: Switching waveforms of a generic unipolar power device. Courtesy of Huang et al. [1].

1. 1 .Figure 1 . 5 :

 115 Figure 1.5: Ideal drift region in Non-Punch-Through (NPT) design that considering the compromise between ON-state loss and OFF-state breakdown, considering breakdown is due to avalanche eect when maximum electric eld in the structure reached material critical electric eld.

Figure 1 . 6 :

 16 Figure 1.6: ON-resistance and breakdown voltage of dierent semiconductor at RT and at 250 • C, courtesy of Umezawa et al.[2].

Figure 1 .Figure 1 . 7 :

 117 Figure 1.7: Schematic description of surface doping model in H-diamond. Courtesy of Maier et al. [3].

Figure 1 .Figure 1 . 8 :

 118 Figure 1.8: Ionization energy of dopants as a function of the impurity concentration in diamond. The experimental boron ionization energies are taken from the literature [Okano 1989, Fujimori 1990, Visser 1992, Windheim 1993, Borst 1995, Deguchi 1996, Lagrange 1999, Klein 2007, Gajewski 2009, Volpe 2009] and the solid curve is drawn after Pearson and Bardeen law [Pearson 1949]. Phosphorus ionization energies are taken from the literature [Koizumi 1997, Kato 2005, Kato 2007, Pinault 2007, Kato 2008, Pinault-Thaury 2011, Stenger 2013]. Its value is assumed to be constant over the entire doping range. Courtesy of Fiori's PhD thesis[4]

Figure 1 . 9 :

 19 Figure 1.9: Theoretical hole density as function of acceptor concentration and compensation at 300 and 500 K. The symbols are experimental data reported by: Barjon et al. [5], Volpe et al. [6], Gabrysch et al. [7], Werner et al. [8], and Tsukioka et al. [9]. Courtesy of Traore et al. [10]

Figure 1 . 10 :

 110 Figure 1.10: The dependence of hole mobility to boron concentration at a) 300 K; b) 500 K. Courtesy of Pernot et al. [11].

Figure 1 .

 1 Figure 1.11: O-diamond Schottky diode on homoepitaxial boron doped diamond with a breakdown voltage of 10 kV and a breakdown electric eld of 7.7 MV/cm. Courtesy of Volpe et al. [12].

1 .

 1 13a) or depletion mode transistor (Fig. 1.13b). Both inversion mode and depletion mode transistor diamond were realized.

Figure 1 . 12 :Figure 1 . 13 :Figure 1 . 14 :

 112113114 Figure 1.12: Pseudo-vertical diamond Schottky diode and its electrical characteristics, Courtesy of Traore et al. [13].

Figure 1 . 15 :

 115 Figure 1.15: The proposed model for the 2DHG at H-diamond/oxide interface. Courtesy of Kawarada et al. [15].

Figure 1 . 16 :

 116 Figure 1.16: Electrical characteristics and breakdown voltage at dierent gate to drain distances of H-diamond MOSFET. Courtesy of Kawarada et al. [15].

Figure 1 . 17 :Figure 1 . 18 :

 117118 Figure 1.17: Top view structure and cross-section structure of the oxygen terminated boron doped diamond MESFET. Courtesy of Umezawa et al. [16].

Figure 1 . 19 :

 119 Figure 1.19: Relationship between semiconductor charge Q SC and semiconductor surface potential Ψ S . Courtesy of Vincent et al. [17].

Figure 1 . 20 :

 120 Figure 1.20: Schematics description of dierent regimes of a MOS capacitor: a) denition of semiconductor surface potential Ψ S ; b) accumulation regime under negative bias; c) depletion and deep depletion regime under positive bias; d) Flatband regime where there are no energy dierent between surface and neutral part of semiconductor.

Figure 1 . 21 :

 121 Figure 1.21: First propositional structure of a O-diamond MOS capacitor. Courtesy of Chicot et al.[18]

Figure 1 . 22 :

 122 Figure 1.22: Typical J-V and C-V characteristics of some rst O-diamond MOS capacitor.Leakage current in both forward bias and reverse bias is observed. Capacitance are strongly frequency dependent. Courtesy of Chicot et al.[18]

Figure 1 .

 1 Figure 1.23: a) Pseudo-vertical structure O-diamond MOS capacitor; b) Band alignment between O-diamond and Al 2 O 3 deposited at 250 • C. Courtesy of Marechal et al. [19]

Figure 1 . 24 :

 124 Figure 1.24: Electrical characteristics of the pseudo-vertical O-diamond MOS capacitor, a) C-V characteristic; b) J-V characteristic. Courtesy of Marechal et al.[19]

Figure 2 . 1 :

 21 Figure 2.1: Illustration of the conduction path in MOS structures; a) without a buried p++ layer; b) with a buried p++ layer.

Figure 2 .

 2 Figure 2.2a represents the conceptual cross-section structure of the O-diamond MOS capacitor test devices used in this work. In this structure, a 300 nm metallic diamond p+layer (5×10 20 cm -3) is inserted at the bottom of p-diamond epilayer (10 17 cm -3 ).

Figure 2 .Figure 2

 22 Figure 2.3: a) Typical feature of a 1b HTHP diamond substrate; b) Optical prole-meter photograph of the substrate.

2. 1 . 3

 13 Diamond growth Diamond epilayers were grown by Microwave Plasma-enhanced Chemical Vapor Deposition (MPCVD) NIRIM reactor [4]. This is a modied version of the Japanese reactor created at NIRIM (National Institute of Research in Inorganic Materials) by Kamo et al. [80]. Figure 2.4b represents the photograph of the MPCVD reactor at Institut NEEL 1 when the plasma ball is activated.

Figure 2 . 4 :

 24 Figure 2.4: MPCVD reactor at Institut NEEL.

Figure 2 .

 2 Figure 2.5 represents the working principle of the reactor. The reactor working principle is based on a plasma discharge ball at the intersection between silica tube and microwave guide. A microwave guide (generator operating at 2.45 GHz) can be tuned by adjusting the impedance in order to minimize the reected power and maximize the energy at the plasma discharge ball. Gas sources like methane, oxygen, hydrogen and diborane are used for diamond growth and boron doping control.

Figure 2 . 6 :

 26 Figure 2.6: Diamond surface topography after growth measured by a) Optical prolemeter; b) AFM.

Figure 2 .

 2 Figure 2.7 represents the fabrication processes for etching p-layer and ohmic contact deposition.

Figure 2 . 7 :Figure 2 . 8 :

 2728 Figure 2.7: Schematics describing the process for diamond etching and ohmic contact fabrication.

Figure 2 .Figure 2 .

 22 Figure 2.10 represents the optical photograph of sample #1. MOS capacitors, MIM

  2 http://www.ameteksi.com/products/materials-testing-systems/modulab-xm-mts C o n d e n t i a measurements. Frequency dependent capacitance measurements have been performed with a.c. signal frequency ranging from 100 Hz to 2 MHz and typical amplitude of 50 mV. A Solartron Modulab-MTS system was also used for advanced C(V ) for very low frequency (down to 1 Hz).

Figure 4 . 13 :

 413 Figure 4.13: Picture of the experimental set-up used for C(V) and I(V) measurements. The sample is put into the metallic box (vacuum and T-controled). Using the binocular, probe tips (inset) can be placed accurately on the sample.

Figure 2 .Figure 2 .

 22 Figure 2.11: a) General electrical measurement conguration; b) Electrical measurement platform at Wide bandgap Semiconductor Group (SC2G)-Institut NEEL

Figure 2 . 13 :

 213 Figure 2.13: Multisine waveforms concept of Solartron Modulab

Figure 2 .

 2 Figure 2.14: a) The calibrated test circuit provided by Ametek Scientic Instruments; b)

  2.15).

Figure 2 . 15 :

 215 Figure 2.15: Capacitance-frequency characteristic of the calibrated test circuit by using dierent measurement congurations

Figure 2 . 16 :

 216 Figure 2.16: Band alignment input conguration for nextnano electrostatics simulation [19].

  3 http://www.nextnano.com/index.php C o n d e n t i a l 2.1. Methodology 47 In order to have the simulations as accurate as possible, the empirical input parameters are highly desired. One important parameter for electrostatics simulation is the O-diamond/oxide band alignment. As mentioned in the rst chapter, this parameter has been determined by Marechal et al. [19]. Figure 2.16 represents the type I band alignment between O-diamond and Al 2 O 3 that we have implemented into our simulations.

Figure 2 . 17 :

 217 Figure 2.17: Typical Capacitance-Voltage characteristics of an ideal MOS capacitor

Figure 2 .C o n d e n t i a l 2 . 2 .

 222 Figure 2.18a represents the DC I-V characteristics when the gate is biasing from +8V to -8V. We dene the biasing in negative direction (0V to -8V) is the forward bias and

Figure 2 .

 2 Figure 2.19 represents the measured capacitance of MIM capacitor at a xed gate bias (V G = -3 V) versus frequency (1 Hz to 1 MHz) (Fig. 2.19a) and at a xed frequency(f =100 kHz) versus gate bias (+4 V to -4 V) (Fig.2.19b). For an oxide thickness of t ox = 20 nm, measured oxide capacitance is about 0.4 µF/cm 2 . Oxide dielectric constant of ε ox 9 was evaluated. This dielectric constant is approximately the value reported in literature for the ALD Al 2 O 3[82].

Figure 2 . 19 :Figure 2 . 20 : 1 .Figure 2 . 21 :

 2192201221 Figure 2.19: Measured capacitance of MIM capacitor by a) Capacitance-Frequency at V G = -3V ; b) Capacitance-Voltage at f =100 kHz.

3 .

 3 By switching the bias direction, from (+8V to -8V) to (-8V to +8V), the C-V characteristics are almost identical, as shown Fig.2.22. We conclude the contributions from mobile oxide charges in this MOS capacitor are negligible.

Figure 2 . 22 :

 222 Figure 2.22: The hysteresis C-V characteristics of sample 1 measured by switching the bias direction, from (+8V to -8V) to (-8V to +8V) to estimate the mobile oxide charge (MOS45-Sample #1).

Figure 2 .

 2 23 represents the measured C mf characteristics at V G = -8V, -4V, -2V , respectively. Figure 2.23b represents the corresponding conductance-frequency G pf characteristics from the same measurement, with G p = 1 Rp from Fig. 2.14 b.

Figure 2 .

 2 Figure 2.23: a) Capacitance-frequency characteristics at V G =-8V, -4V, -2V; b) Conductance-frequency (G pf ) characteristics obtained from the same measurement (MOS12-sample #1).

Figure 2 .

 2 Figure 2.23 demonstrates that both measured capacitance C m and measured conductance G p are frequency dependent.

Figure 2 . 24 :

 224 Figure 2.24: Equivalent circuit of a MOS capacitor system in case of a) high frequency regime; b) taking into account the contribution from interface states

Figure 2 .

 2 Figure 2.25: a) Nyquist plot (Re(Z) versus Im(Z))of impedance measurements; b) Real part impedance Re(Z) versus frequency (MOS12-sample #1).

Figure 2 . 26 :Figure 2 . 27 :

 226227 Figure 2.26: Inverse square capacitance-voltage characteristics of O-diamond MOSCAP for extracting doping concentration (MOS12 -sample #1)

Figure 2 .

 2 Figure 2.28b represents the Ψ s -V G relationship by using the above mentioned technique.

Figure 2 .

 2 Figure 2.28: a) Diamond surface potential variation with gate bias (MOS12 -sample #1); b) description corresponding to diamond Fermi level moving against gate bias in Figure 2.7a. Fermi level pinning eect is suggested due to interface states (Magenta part in Fig. 2.7 b is the descriptive interface states density)

C o n d e n t i a l 2 . 2 .- 8 Figure 2 . 29 :Figure 2 . 30 :

 228229230 Figure 2.29: Depletion region variation with gate bias (MOS12 -sample #1).

  and interface states charge σ it (V G ) extracted from Terman method. Interface states charge is evaluated by integrating interface states density over the energy band gap. Simulation results are shown in Fig. 2.31. Electrostatics band diagrams of MOS capacitor at dierent gate bias are shown in Fig. 2.31 a-c). Without gate bias (V G = 0 V), due to high density positive charge in the oxide, holes from the p-type diamond are attracted to the oxide. A strong built-in potential around 5 eV was created. Also, an approximately 80 nm width close to the oxide/diamond interface is depleted, as shown in Fig. 2.31 b). For a positive bias (Fig. 2.31 c), the SCR is further modulated by gate bias. Deep depletion regime is obtained with a depletion thickness of 130 nm at V G = 2V. Finally, Figure 2.31 a) represents the band diagram for a relatively small negative bias V G = -4V. One remarkable issue from electrostatics simulation, which is not seen trivially from C-V measurement is the potential distribution within the oxide. This electrostatic band diagram is essential to identify the origin of forward current and capacitance-frequency dependence measurement. The electric eld distribution of O-Diamond MOS capacitor at dierent bias regime is shown in Fig. 2.31 d.

  C o n d e n t i a l 2.2. Electrostatics of O-diamond MOS capacitor 63

Figure 2 . 31 :

 231 Figure 2.31: Electrostatics band diagram of O-diamond MOS capacitor calculated by Nextnano 3 at dierent metal gate potentials a) When device is biased positively toward deep depletion; b) When device is under zero bias condition; c) When device is negatively biased toward accumulation; d) Electric eld distribution at dierent bias condition.

Figure 2 . 32 :

 232 Figure 2.32: Nextnano simulation result compared with experiment by mean of surface potential (MOS12-sample #1).

Figure 2 .

 2 Figure 2.33a represents the typical DC current-voltage (I-V) characteristics of dierent MOS capacitors for V G : +8V to -6V. Here we present MOS C7, MOS C17 and MOS B12 of sample #3. This sample has been annealed and oxide charge were reduced. Under forward bias, forward currents are systematically observed with dierent magnitudes.Under positive bias, reverse currents are relatively random. The magnitude of forward current does not show a strong relationship with the reverse current. We will devote Part 3 of this chapter to investigate the origin of reverse current and its possible consequence.

Figure 2 .

 2 Figure 2.33b represents the typical measured Conductance-Voltage (G p -V G ) at different frequencies of MOS C7 -sample #3 for V G : 0V to -6V . Measured conductance are frequency dependent at high frequency range. At a given low frequency range (≤ 1 kHz), the measured conductance is frequency independent and it is almost identical to the statics conductance (DC I-V).

Figure 2 .

 2 Figure 2.33c represents the typical measured Capacitance -Voltage (C m -V G ) at dierent frequencies of MOS C7 -sample #3 for V G : +8V to -6V. Figure 2.33d represents the Capacitance-Frequency (C mf ) at V G = -5V. In fact, this C mf curve is equivalent to the cut line at V G = -5V in Fig. 2.33c. Both measured capacitance and measured conductance are frequency dependent as identical with the C mf and G pf in the part 1. Measured conductance behaves in a complementary manner with

Figure 2 .

 2 Figure 2.33c represents the typical measured Capacitance -Voltage (C m -V G ) at dierent frequencies of MOS C7 -sample #3 for V G : +8V to -6V.Figure 2.33d represents the Capacitance-Frequency (C mf ) at V G = -5V. In fact, this C mf curve is equivalent to the cut line at V G = -5V in Fig. 2.33c. Both measured capacitance and measured conductance are frequency dependent as identical with the C mf and G pf in the part 1. Measured conductance behaves in a complementary manner with measured capacitance. (The terms measured capacitance and measured conductance are used here to discriminate with corrected capacitance, corrected conductance and equivalent conductance further dened in the following sections).

Figure 2 .Figure 2 .

 22 Figure 2.33: a) Current-Voltage characteristics of three MOSCAP: B12, C7 and C17 of sample #3; b) Conductance-Voltage characteristics of MOS C7 measured at dierent frequencies; b) Capacitance-Voltage characteristics of MOS C7 measured at dierent frequencies; d) Capacitance-frequency of MOS C7 measured at V G = -5V .

Figure 2 . 35 :

 235 Figure 2.35: Proposed current mechanism of dierent processes and its corresponding energy level.

Figure 2 . 36 :

 236 Figure 2.36: DC Capacitance-Voltage non-linearity of MIM capacitors and the tting to extract hopping distance.

Fig. 2 .

 2 Fig.2.38 with the tting curve using equation(6). From tting curve, b value is evaluated as 0.094. The distance between trap sites in our ALD Al 2 O 3 is then estimated of approximately 5 nm.A rough calculation shows that the tunneling rate from trap to trap is almost 150times faster than Poole-Frenkel thermal activation rate from traps level to conduction band at room temperature. In case an oxide trap level is closer to oxide conduction band, the injection rate in the step 1 will be mostly dismissed. It is therefore possible to conclude that tunneling from trap to trap is the main carriers transport mechanism in the oxide.

76 2. 4 . 3

 7643 Equivalent circuit and conductance method 2.4.3.1 Equivalent circuit

  2.37 b) and oxide tunneling limited (Fig. 2.37c) is the measured conductance-frequency characteristics. For the purpose of comparison, measured conductance circuit is the parallel circuit C p -R p in Fig. 2.37g. In case oxide tunneling limited, measured conductance is frequency dependent, as shown in Fig. 2.37c. For interface states recombination limited (Fig. 2.37 b), measured conductance is frequency independent.

Figure 2 . 37 :

 237 Figure 2.37: Equivalent circuit for O-diamond MOS capacitor: a) general circuit with gate carriers injected to single level interface states; b) approximated equivalent circuit for interface states recombination limited; c) approximated equivalent circuit for oxide tunneling limited; d)-g) step by step circuit transform to achieve measurement circuit; d) Circuit transformed from circuit c); e) circuit transformed from circuit d); f ) Circuit transformed from circuit e); g) the parallel circuit for measured capacitance and measured conductance.

Figure 2 .

 2 40b represents the Arrhenius plot of current density measured at V G = -8 V versus temperature. From the slope, a thermal activation energy of E A = 215 meV was evaluated. As suggested from generalized thermionic trap assisted tunneling model[START_REF] Mahaveer | Thermionic trap-assisted tunneling model and its application to leakage current in nitrided oxides and algan/ gan high electron mobility transistors[END_REF], this thermal activation energy is assigned to the barriers between C o n d e n t i a

Figure 2 .Figure 2 .Figure 2 .

 222 Figure 2.38: a) Semi-log plot Current-Voltage characteristics of high injection MOS capacitor and low injection MOS capacitor; b) the log-log plot to identify the current-voltage power law from linear tting (MOS 1 and MOS 50 -Sample #1) @RT.

Figure 2 . 41 :

 241 Figure 2.41: Equivalent conductance G p /ω at dierent gate bias measured at RT (MOS 12 -Sample #1).

Figure 2 . 42 :

 242 Figure 2.42: Comparison of the interface states density extracted from conductance method and Terman method. MOS12 -sample #1

Figure 2 . 43 :

 243 Figure 2.43: Representative equivalent conductance G P /ω and the simulation by using single level interface state model at V G = -7.5V and V G = -4.5V . (MOS 12 -Sample #1).

Figure 2 .

 2 Figure 2.43 represents the experimental equivalent conductance G P ω at representative gate biases (V G = -7.5 V and V G = -4.5 V) and the simulation curves by using single

Figure 2 . 44 :

 244 Figure 2.44: Capacitance-frequency dependence of the MOS capacitor test device by comparing the measurements and LTspice simulation a) V G = -7V ; b) At dierent V G (MOS 12 -sample #1).

C o n d e n t i a l 86 forFigure 2 . 45 :

 86245 Figure 2.45: Semiconductor surface potential variation with gate bias determined from experiment and from nextnano simulation by using interface states density extracted from

C o n d e n t i a l 2 Figure 2 . 46 :at 100 •

 2246100 Figure 2.46: Current-Voltage and Capacitance-Voltage characteristic at dierent frequencies of O-diamond MOS capacitor presented by Kovi et al. [20].

2. 49 .Figure 2 .

 492 Figure 2.47: a) Current-Voltage and b) Capacitance-Voltage characteristics at dierent frequencies of the MOS B12 (sample #3).

Figure 2 .Figure 2 . 49 :

 2249 Figure 2.48: a) Current-Voltage and b) Capacitance-Voltage characteristics at dierent frequency of the MOS C7 (sample #3).

Figure 2 .

 2 Figure 2.50: a) Optical photograph of the completed test devices (sample #1) including ohmic contact, MIM capacitor and MOS capacitor; b) the FESEM image of substrate in Figure 2.49a after removing gate metal, gate oxide and redeposited ohmic contact on p+ region and grids on p-region for device electrical characteristics-substrate prole correlation.

Figure 2 .Figure 2 .

 22 Figure 2.51a represents the semilog I-V characteristics of the MOS A1 -sample #1 where reverse current was observed.Figure 2.51b represents the reverse I-V characteristics in log-log scale. Linear tting indicates the current-voltage power law of I∼V 4 in reverse regime.

Figure 2 .Figure 2 .

 22 Figure 2.53a represents the semilog I-V characteristics of the defective sites under positive bias. The corresponding log-log plot is shown in Fig. 2.53b. A current-voltage ohmic

C o n d e n t i a l 2

 2

Figure 2 .

 2 Figure 2.53: a) Current-Voltage characteristics of defective spots under positive bias in semilog plot; b) Current-Voltage characteristics of defective spots under positive bias in log-log plot (Sample #1).

Figure 2 .C o n d e n t i a l 98 2. 7 . 1 . 3 FIBFigure 2 . 55 :Figure 2 .C o n d e n t i a l 2 . 7 .Figure 2 . 57 :

 298713255227257 Figure 2.54: a) CL spectrum of diamond substrate; b) CL mapping of diamond substrate recorded at A-band luminescence (sample #1).

2. 7 . 2 . 1

 721 Current mechanismAs we have shown, reverse currents are related to defective leakage spots in the substrate. Figure2.58 represents our proposed reverse current mechanism. Two sections are included: The section surrounded by blue dash represents the area without defective leakage spots. Since positive voltage is applied, SCR width of diamond epilayer is expanding.

C o n d e n t i a l 100 Carriers

 100 are not allowed to ow through this region. The corresponding electrostatic band diagram is represented in the left hand side of Fig.2.58.

Figure 2 . 58 :

 258 Figure 2.58: Proposed current mechanism and its corresponding electrostatic band diagrams.

C o n d e n t i a l 2 Figure 2 .

 22 Figure 2.59: a) Current-Voltage of MOS capacitor measured at dierent temperatures, ranging from 150K to 370K; b) Arrhenius plot of current measured at dierent temperatures when gate are biased at V G =7V (MOS A1 -sample #1).

Figure 2 .

 2 58b represents the proposed equivalent circuit which is based on the current mechanism (Figure 2.58). The area surrounded by a blue dash is corresponding to an ideal MOS capacitor in deep depletion regime. The semiconductor SCR is in series with oxide capacitance C ox1 and oxide conductance G ox1 . The area surrounded by a red dash represents the equivalent circuit corresponding to the defective leakage spots area. Resistance of defective leakage spots R crystallite are in series with oxide capacitance C ox2 and oxide conductance G ox2 .

Figure 2 . 60 :C o n d e n t i a l 2 . 7 .

 26027 Figure 2.60: Proposed equivalent circuit which is corresponding to the current mechanism for simulating the a.c measurement.

Figure 2 . 61 :

 261 Figure 2.61: Capacitance-frequency dependent in the reverse regime from a.c measurement (closed black circular) and simulation (red line).

FIG. 1

 1 FIG. 1. a) Schematics represent the concept of deep depletion MOSFET for wide bandgap semiconductor. The three different regimes are drawn: flatband regime, deep depletion regime and inversion regime. b) Graphical solution of semiconductor charge per unit area as a function of gate voltage VG for an ideal MOS structure with NA = 1.75 × 10 17 cm -3 acceptor doping level. The thickness and relative dielectric constant of Al2O3 are 40 nm and 9, respectively. The transition from the initial deep depletion regime to the inversion regime is characterized by the characteristic time constant τ . c) Minority carrier generation tine constant as function of material bandgap at room temperature using Si parameters for v th and NC,V . τ can be considered as infinite for diamond.

FIG. 2

 2 FIG. 2. a) Cross-section structure of the lateral O-diamond MOSCAP. b) Optical top view structure of the fabricated Odiamond MOSCAP. c) I(V) characteristics of the O-diamond MOSCAP for +15V≤VG ≤ -10V indicates the negligible leakage current. d) C(V) characteristic of the O-diamond MOSCAP indicates the complete electrostatics gate control diamond into accumulation, flatband, depletion and deep deletion regime. e) Semiconductor surface potential variation with gate bias for the gate bias from flatband voltage to deep depletion regime. f) the variation of semiconductor space charge region versus gate bias.

FIG. 3 .

 3 FIG. 3. Transistor characteristics measured by sweeping VDS at different fixed VGS.a) transistor characteristics of sample GD1; b) transistor characteristics of sample GD2.

4 ) 5 )

 45 Universit de Toulouse ; LAPLACE ; CNRS ; INPT ; UPS, F-31071 Toulouse, France Institut Universitaire de France, 103 boulevard Saint Michel, 75005 Paris, France (Dated: June 2017)

  introduced the O-diamond/Al 2 O 3 MOSCAPs test device. Strong leakage currents 10 and capacitance frequency dependence 11 were observed through a) thanh-toan.pham@neel.cnrs.fr b) julien.pernot@neel.cnrs.fr the O-diamond MOSCAPs for Al 2 O 3 deposited by ALD at 100 • C. Kovi et al. 12 employed an identical structure using Al 2 O 3 deposited by ALD at 250 • C and reported similar electrical characteristics. Marechal et al. 13 employed the XPS measurements and determined the type I band alignment at O-diamond/Al 2 O 3 interface with Al 2 O 3 deposited by ALD at 250 • C. However, in all mentioned reports, a complete understanding on the electrical characteristics of boron doped O-diamond/Al 2 O 3 MOSCAPs is still lacking.

13

 13

FIG. 1 .

 1 FIG. 1.Structure of the test device that include Ohmic contact, MIMCAPs and MOSCAP a) Cross-section; b) Top view.

FIG. 2 .

 2 Figure 2

FIG. 3 .

 3 FIG. 3. Proper C(V) measurement indicates that diamond are in depletion regime even for VG = -8V . Doping concentration of diamond epilayer is extracted from 1 C 2 (VG) curve (MOS12 -sample #1).

  a), electrons from gate metal are suggested to initiate the flow by tunneling into Al 2 O 3 gate

FIG. 4 .

 4 Figure 3

FIG. 5 .

 5 FIG. 5. Equivalent circuit for the O-diamond MOSCAP corresponding to the approximation: (a) approximate equivalent circuit for the interface states recombination limited case (τR >> τT ) where Git = 1 R it ; (b) approximated equivalent circuit for the oxide tunneling limited case (τT >> τR) where G dc ≈Gox.; (c) Circuit (b) transformed to include a continuum of interface states.; (d) Circuit (c) transformed to show capacitance corrected for series resistance (Cc) and the a.c. conductance (Gac); (e) Circuit (d) transformed to show Cc and conductance corrected for series resistance (Gc): (f) Circuit (e) transformed to show measured capacitance (Cp) and measured conductance (Gp):

FIG. 6 .

 6 FIG. 6. (a) Experimental log-log plot I(V) characteristics of the low injection MOSCAP (MOS 50 -Sample #1). (b) Arrhenius plot current density versus Temperature at different gate bias: VG=-8V, -6V and -4V, indicates the thermal activation energy of the low injection MOSCAP. (c) Log-log plot I(V) characteristics of high injection MOSCAP (MOS1-sample #1); (d) Current density at VG = -8V versus versus 1 T 4 indicates the variable range hopping in the high injection MOSCAP.

C o n d e n t i a l 3 Figure 3

 33 Figure 3.1: a) Typical structure of an enhancement transistor; b) Typical electrical characteristics of a Transistor

Figure 3 . 2 :

 32 Figure 3.2: Structure of a transistor on H-diamond. a) Cross-section structure; b) Plan view structure. Courtesy of Kawarada et al. [21]

Figure 3 . 3 :

 33 Figure 3.3: Structure of the p-type diamond MESFET a) top view; b) cross-section.

3

 3

Figure 3 . 4 :

 34 Figure 3.4: Cross-section structural concept of depletion mode oxygen-terminated boron doped diamond MOSFET.

Figure 3 . 5 :- 3

 353 Figure 3.5: Expected depletion region width between substrate and epilayer with dierent doping concentration. Considering the 1b substrate is highly nitrogen doped (N D = 3 × 10 19 cm -3 ). Courtesy of Chicot's PhD thesis [22]. In the rst approach, we fabricated two samples with multiple diamond transistors and test devices on a same substrate. In sample #1, a p-type diamond epilayer with the target boron doping concentration of 2×10 17 cm -3 and a Al 2 O 3 gate oxide with a 20 nm thickness were employed. Sample #2 is fabricated to target higher breakdown voltages device. Therefore, the epilayer doping concentration is decreased (target 5×10 16 cm -3 ) and the oxide thickness is increased (40 nm). Consequently, sacriced SCRs width of 100 nm and 230 nm are expected for sample #1 and sample #2, respectively (Fig. 3.5).

C o n d e n t i a l 132 Chapter 3 .Figure 3 . 6 :Figure 3 . 7 :Figure 3 . 8 :

 1323363738 Figure 3.6: Transistor structure target high ON-states current a) Stripe structure; b) Fingers structure.

C o n d e n t i a l 134 Chapter 3 .Figure 3 . 9 :Figure 3 . 10 :

 134339310 Figure 3.9: The ow chart fabrication process of depletion mode O-diamond MOSFET.

Figure 3 .

 3 Figure 3.10 represents FESEM image of the completed devices after the fabrication.

Figure 3 . 11 :

 311 Figure 3.11: Silvaco simulation conguration with diamond epilayer thickness of 100 nm and doping concentration of 2×10 17 cm -3 , oxide thickness of 20 nm, L GS = 4µm, L G = 4µm, L GD = 3µm, L D = 1µm, L S = 1µm. Substrate were considered as an insulator to minimize the simulation time constant.

3. 3 . 1 C o n d e n t i a l 3 . 3 .Figure 3 . 12 :

 3133312 Figure 3.12: Top view of MOS capacitor structures captured by optical microscope.

  Figure 3.13b represents the C-f curve of a MOS capacitor test device. From the C-f curve, we can see that the artifacts like leakage current (Fig. 3.13a), interface states and series resistance strongly aect the capacitance measurement, as discussed in chapter 2. The C-f curve also indicate that C-V measurements are necessary to be measured at the frequency range of few hundreds hertz.

Figure 3 . 13 :C o n d e n t i a l 3 . 3 .

 31333 Figure 3.13: Electrical characteristics of MOS capacitor test devices on the diamond transistor sample: a) Current-Voltage characteristic; b) Capacitance-frequency characteristic at V G = -3 V ; Capacitance-Voltage characteristics measured at dierent frequency.(Sample #1 -@RT).

is the slope from linear tting of 1 C 2 -Figure 3 . 14 :

 12314 Figure 3.14: Reciprocal square capacitance plotted with gate bias to extract eective doping concentration (sample #1 at RT).

C o n d e n t i a l 140 Chapter 3 .Figure 3 .

 33 Figure 3.15: a) Surface potential variation with metal gate bias; b) Corresponding depletion width variation with gate bias.

Figure 3 .Figure 3 . 16 :

 3316 Figure 3.16 represents a typical conceptual structure of the TLM. In the current work, TLM are the multiple electrode pads of Ti/Pt/Au with width of W=150 µm and spacing between pads L of 10 µm, 25 µm, 50 µm, 75 µm, 100 µm and 150 µm.

Figure 3 .

 3 Figure 3.17a represents the I-V characteristics at RT of three TLM at dierent spacings: L = 75 µm, 100 µm and 150 µm, respectively. The ohmic contact behavior of the contacts was not obtained. Regarding the origin of non-ideal ohmic behavior, it

C o n d e n t i a l 142 Chapter 3 .Figure 3 .

 33 Figure 3.17: a) Typical IV characteristics of the Ohmic contact after annealing at 600 • C; b) Measured resistance as function of electrode spacing with linear tting to extract sheet resistance and contact resistance

Figure 3 .Figure 3 . 18 :

 3318 Figure 3.17b) represents the measured total resistance with three pads spacing of L=75 µm, 100 µm and 150 µm, respectively. The linear tting of the total resistance as a function of the gaps gave a straight line with the slope of 26.4 kΩ/µm and an intercept with y-axis at 11.7 MΩ. A corresponding sheet resistance of approximately R Sheet

[ 10 ]Figure 3 . 19 :

 10319 Figure 3.19: The relationship between compensation concentration N D and hole concen- tration of boron doped diamond at dierent dopant concentration N A . Courtesy to Traore et al.[10]

Figure 3 .

 3 Figure 3.20 represents the FESEM image of the fabricated transistors under measurement conguration. Figure 3.20a represents the stripe structure transistor. The ON-state current that will be presented below is measured from this device. The specic dimensions of this transistor are: W=34µm, L DS =10µm, L G =3µm, L GS =4µm and L GD =3µm.

Figure 3 .Figure 3 . 20 :

 3320 Figure 3.20b represents the FESEM image of the circular transistor, from which the OFF-state performance will be presented. The specic dimensions of this transistor are:L G =4µm, L GS =4µm and L GD =10µm. From both transistors, the dimensions are the designed values (mask), and do not take into account possible misalignments and process variations.

Figure 3 .C o n d e n t i a l 3 . 3 .

 333 Figure 3.21 represents the transfer characteristic of the stripe structure transistor. The transfer characteristic clearly shows three typical regimes of a proper transistor: linear

Figure 3 . 21 :

 321 Figure 3.21: Transfer characteristics of the stripe transistor -sample #1 measured by

C o n d e n t i a l 146 Chapter 3 .Fig. 3 .

 33 Fig. 3.22a, acknowledging an OFF state leakage current below detection limit (reduced W of the transistor).

Figure 3 .

 3 Figure 3.22: a) Transfer characteristics of the stripe transistor -sample #1 measured by sweeping V GS from +10V to -5V at a xed V DS (V DS =-10V) ; b) Gate leakage current I GS measured instantaneously with transfer I D . The measurement have been performed at RT in the vacuum chamber of FESEM system.

Figure 3 . 24 :

 324 Figure 3.24: Silvaco Atlas simulation of the hole distribution at dierent gate bias a)

3 .C o n d e n t i a l 3 . 3 .Figure 3 .

 3333 Figure 3.24d represents the cutline potential distribution, which is corresponding to the potential distribution in Fig.3.23a-c). Figure3.24e represents the cutline electric eld distribution, which is corresponding to the electric eld distribution in Fig.3.23d-f ).

Figure 3 .

 3 Figure 3.24e represents the cutline hole distribution, which is corresponding to the hole distribution in Fig. 3.24a-c).

Figure 3 . 25 :

 325 Figure 3.25: Silvaco simulation of drain current (I D ) for V DS = -1V at dierent gate bias (V GS : -5V to +6V) in a) linear scale; b) semilog scale. Simulation conguration is identical with the Fig. 3.11 and temperature is kept at RT.

C o n d e n t i a l 150 Chapter 3 .

 3 Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond 3.3.2.

Figure 3 .

 3 Figure 3.26: a) Transfer characteristics of the stripe transistor -sample #1 measured

C o n d e n t i a l 152 Chapter 3 .

 3 Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond in the Gate to Source region (as suggested by the simulation from Fig. 23b), since

Figure 3 .

 3 Figure 3.28: 2RC+Rchannel versus channel thickness (the width of neutral region under gate) at dierent V GS (top x-axis).

10 )C o n d e n t i a l 3 . 3 .

 1033 Results and Discussion 153

Figure 3 .

 3 28 represents the R SD -R GS -R GD plotted versus channel thickness (the width of neutral region under gate). By using equation 3.10 for tting Fig. 3.28, contact resistance of 2R C 31 MΩ is determined. A normalized 2R C W 110 kΩ.cm is obtained.

FET

  with an insulated gate. An improved contact resistance as well as the fabrication of the Hall bar test devices on the same substrate for the systematic investigation the compensation of the sample are critical in the next fabrication run. C o n d e n t i a l 154 Chapter 3. Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond

Figure 3 . 29 :

 329 Figure 3.29: Breakdown voltage measured with V GS =-12 V and drain voltage sweeping in negative bias voltage to V DS = -200 V (limit of the apparatus): a) rst cycle breakdown measurement; b) 5th cycle breakdown measurement.

Figure 3 .

 3 Figure 3.29 represents the measured breakdown of the circular device in Fig.

C o n d e n t i a l 3 . 3 .Figure 3 . 30 :Figure 3 .Figure 3 . 31 :

 333303331 Figure 3.30: Silvaco Atlas simulation critical electric eld for V DS =-200 V without impact ionization a) in linear scale; b) logarithm scale

Figure 3 . 32 :

 332 Figure 3.32: Specic ON-resistance versus breakdown voltage of dierent diamond transistors.

C o n d e n t i a l 158 Chapter 3 .

 3 Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond diamond reaching its theoretical avalanche breakdown voltage. Assuming that the breakdown is only due to the avalanche eects (impact ionization), a maximum breakdown voltage using the same epilayer doping concentration (1.75 × 10 17 cm -3

  respectively, in a NPT conguration. The question of avalanche breakdown in diamond devices remains however open, since most observed breakdown mechanism are destructive and non-reproducible, or based on excessive leakage current.

Figure 3 . 33 :

 333 Figure 3.33: Specic ON-resistance vs. dierent breakdown voltage of NPT boron doped diamond devices. Courtesy to Chicot et al.[23]

Figure 3 . 34 :FigFigure 3 .

 3343 Figure 3.34: Electrostatics gate controlled the current between Source and Drain at dierent gate bias. Transistor sample #2.

Fig. 1 . 2 StepFig. 3 .

 123 Fig. 1. Conceptual cross-section structure of the depletion mode oxygenterminated boron doped diamond MOSFET.

Fig. 2 .

 2 Fig. 2. Top view of the fabricated boron doped diamond MOSFET and test devices: left, zoom under optical microscope and right, SEM image of the whole diamond sample.

Fig. 4 .

 4 Fig. 4. Breakdown voltage measured with V GS =-12 V and drain voltage sweeping in negative bias voltage to V DS = -200 V (limit of the apparatus): a) first cycle breakdown measurement; b) 5th cycle breakdown measurement. c) 2D simulation at V DS = -200 V and V GS >V T H

  [19], the Figure of Merit (RonS vs. BV) of this work is benchmarked in figure5, highlighting measured performances and foreseen improvements (circles and crosses are respectively performances at RT and high temperatures). Combining these attractive figures of merit with extremely low leakage current and high temperature operation capability, depletion mode diamond transistors are demonstrated for the first time as realistic solutions.

Fig. 5 .

 5 Fig. 5. Specific ON-resistance vs breakdown voltage.

  Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.2 Carrier mobility and density . . . . . . . . . . . . . . . . . . . . . 13 1.2.3 Dielectric breakdown eld . . . . . . . . . . . . . . . . . . . . . . 15 1.3 States-of-the-art of diamond unipolar power devices . . . . . . . . . . . . Switching waveforms of a generic unipolar power device. Courtesy of Huang et al. [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

	List of Figures
	1.1 1.2 2 Oxygen terminated boron doped diamond metal oxide semiconductor Unipolar device's Figure-of-Merit(FOM) . . . . . . . . . . . . . . . . . . Diamond semiconductor for power devices . . . . . . . . . . . . . . . . . 1.2.1 capacitor I Electrostatics 2.1 Methodology . . . 161 5 10 28 31 33 Bibliography 169 1.1 Power range requirements of various applications (chart is based on Yole Development report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Electrical circuit of the power converter a) DC-DC boost converter; b) DC-DC buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Typical electrical characteristic of simple power device (diode) where the loss in the ON-state and breakdown in the OFF-state are unavoidable. . 5 1.4 6 C o n d e n t i a l 1.5 Ideal drift region in Non-Punch-Through (NPT) design that considering

17 1.3.1 Diamond Schottky diode . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.2 Diamond unipolar transistor . . . . . . . . . . . . . . . . . . . . . 17 1.4 Metal Oxide Semiconductor Field Eect Transistors (MOSFET) . . . . . 23 1.4.1 MOS capacitor working principle . . . . . . . . . . . . . . . . . . 23 1.4.2 O-diamond MOS capacitor . . . . . . . . . . . . . . . . . . . . . . 25 1.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1.1 MOS Capacitor test device structure . . . . . . . . . . . . . . . . 35 3 Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond 125 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.1.1 Transistor electrical characteristics . . . . . . . . . . . . . . . . . 125 3.1.2 Diamond FET devices . . . . . . . . . . . . . . . . . . . . . . . . 126 3.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.2.1 Transistor design . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.2.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.2.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.2.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.3.1 Test devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.3.2 Transistor Performance . . . . . . . . . . . . . . . . . . . . . . . . 144 3.3.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 3.3.4 OFF-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4 Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.6 General Conclusion and Perspective . . . . . . . . . . . . . . . . . . . . . 160 3.6.1 General Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.6.2 Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . the compromise between ON-state loss and OFF-state breakdown, considering breakdown is due to avalanche eect when maximum electric eld in the structure reached material critical electric eld. . . . . . . . . . . . . 7 1.6 ON-resistance and breakdown voltage of dierent semiconductor at RT and at 250 • C, courtesy of Umezawa et al.[2]. . . . . . . . . . . . . . . . 10 1.7 Schematic description of surface doping model in H-diamond. Courtesy of Maier et al. [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 Ionization energy of dopants as a function of the impurity concentration in

  1.15 The proposed model for the 2DHG at H-diamond/oxide interface. Courtesy of Kawarada et al. [15]. . . . . . . . . . . . . . . . . . . . . . . . . 20 1.16 Electrical characteristics and breakdown voltage at dierent gate to drain distances of H-diamond MOSFET. Courtesy of Kawarada et al. [15]. . . 21 1.17 Top view structure and cross-section structure of the oxygen terminated boron doped diamond MESFET. Courtesy of Umezawa et al. [16]. . . . 22 1.18 MESFET electrical characteristics and breakdown voltage at dierent gate to length distance. Courtesy of Umezawa et al. [16]. . . . . . . . . . . . 22 1.19 Relationship between semiconductor charge Q SC and semiconductor sur- face potential Ψ S . Courtesy of Vincent et al. [17]. . . . . . . . . . . . .

2

  List of Figures fundamental investigations dedicated to the electrical characteristics of an O-diamondMOS capacitor test device; 2. From understanding MOSCAP test devices to realize an unipolar diamond MOSFET by controlling the diamond semiconductor epilayer. The thesis will include three chapters:

Table 1 .

 1

1: Physical properties and FOMs value of main semiconductors for power device applications.

  kT -1

	1.4. Metal Oxide Semiconductor Field Eect Transistors (MOSFET)	25
	Q sc ∼	√ e q(Ψs-2Ψ b )/kT	(1.25)
	4. Flatband: Flatband regime is the position where there are no energy dierence
	(1.23) 2. Depletion and deep depletion: When a positive bias is being applied, the p-type semiconductor band energy is bent downward, as shown in Fig. 1.20b. Semiconductor is being converted to depletion and deep depletion regime. The semiconductor charge Q SC is proportional to square root of surface potential. Equation 1.22 is approximated by: Q sc ∼ Ψ s (1.24) 3. Inversion: Semiconductor reach the inversion regime when Ψ s > 2Ψ b (Fig. 1.19). With Ψ b is semiconductor bulk potential, as dened in Fig. 1.20a. Semiconductor charge at the surface is being inverted by minority carriers. Semiconductor charge is being exponentially proportioned to Ψ s -2Ψ b . Equation 1.22 can be approximated as: between the surface and the neutral part of semiconductor. In another words, semicon-ductor surface potential is equal to 0 eV, as schematically shown in Fig. 1.20d. Therefore, atband voltage and atband capacitance are a demarcation between accumulation and depletion. At atband voltage, semiconductor charge and consequently semiconductor C o n d e n t i a l capacitance is a function of semiconductor intrinsic Debye length as:

  Capacitance-frequency dependence . . . . . . . . . . . . . . . . . . 100 2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.9 Conclusion of Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . 105

	32	Chapter 2. Oxygen terminated boron doped diamond metal oxide semiconductor capacitor
	o n d e n t i a l C o n d e n t i a l Chapter 2 Oxygen terminated boron doped diamond metal oxide semiconductor capacitor Contents 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.1 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . 68 2.4.2 Forward current mechanism . . . . . . . . . . . . . . . . . . . . . . 68 2.4.3 Equivalent circuit and conductance method . . . . . . . . . . . . . 76 2.4.4 Capacitance-frequency dependence . . . . . . . . . . . . . . . . . . 84 2.4.5 Electrostatics simulation . . . . . . . . . . . . . . . . . . . . . . . . 85 2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.6 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.7 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.7.1 Device characteristics-substrate prole correlation . . . . . . . . . . 94 2.7.2 Reverse current mechanism . . . . . . . . . . . . . . . . . . . . . . 99 2.7.3 As introduced in the rst chapter, the MOS capacitor stack is the building block of a MOSFET. In order to realize a diamond MOSFET, it is necessary to comprehensively control the diamond/oxide interface. Therefore, a complete understanding of the MOS capacitor is required. In this chapter, we will focus on dierent fundamental aspects of the boron doped O-diamond MOS capacitor test device toward a bulk controlled diamond MOSFET. This chapter will include three parts: Part 1: We address several technical issues related to a MOS capacitor test device such as: the needs of new structures to reduce series resistance, the diamond growth and device fabrication processes, the electrical measurements and the nite element electrostatics simulation. Then, we examine the artifact eects on the capacitance measurement and we introduce a method to perform a proper capacitance measurement. From the proper capacitance measurement, the methodologies to quantify the crucial information of the MOS capacitor such as semiconductor charge, oxide charge and the variation of semi-conductor surface potential versus gate bias will be presented. Interface states density is also extracted from the high frequency-capacitance method. Finite element electrostat-ics simulation will be employed to simulate the electric eld, potential distribution and C o n d e n t i a l electrostatics band diagram of the system. The discrepancy between simulation results

lithography cess d) Ti, Pt, Au deposition and lift-off -layer -layer iamond substrate ght + ozone 2 O * O 2 O 3 O * O 2 O 3 O * p-layer p + -layer Ib HPHT diamond substrate TMA + H 2 O -layer -layer iamond substrate p + -layer Ib HPHT diamond substrate p-layer MIM MOS Top view b)! Cross-Section Al 2 O 3! HPHT 1b (100)! p-! p+! a)! Ohmic ! Contact! MIMCAPs! MOSCAPs! MIMCAPs! MOSCAPs! Ohmic Contact!

	Figure 2.2: a) Conceptual cross-section structure of test devices included Ohmic contact,
	MIM Capacitors and MOS Capacitors; b) Corresponding plan view of test device struc-
	ture where MIM capacitors and MOS capacitors are fabricated with dierent shapes and
	sizes.
	The p-layer was
	then selectively etched to create a mesa structure. Ohmic contact and Metal-Insulator-
	Metal (MIM) capacitor test devices are allowed to be deposited directly on top of p+
	layer. Metal-Oxide-Semiconductor (MOS) capacitor test devices are formed on top of
	the semiconducting p-layer. Test devices (MIM capacitors and MOS capacitors) were
	intentionally fabricated with dierent shapes and sizes. The corresponding plan view
	structure is shown in Fig. 2.2b.

Schematics representing the structure and the working principle of the reactor. Courtesy to Fiori's PhD thesis [4]

	38
	After growth, diamond surface topography is characterized by dierent methods. Fig-ure 2.6a represents the surface topography measured by optical prole-meter. Figure 2.6b 1 http://neel.cnrs.fr Figure 2.5: layer Pres (Torr) Temp (°C) Power (W) B/C (ppm) CH 4 (sccm) H 2 (sccm) O 2 (sccm) [B] (cm -3 ) p + 33 830 240 1200 7.6 200 0 5x10 20 C o n d e n t i a l p -33 870 270 600 1 100 0.25 2x10 17

Table 2

 2 the features of defective structures and their correlation with electrical characteristics of test devices will be addressed in the part 3 of this chapter.

	.1: Conditions for growth of metallic diamond (p+) and moderate boron doped
	diamond (p-).
	represents the surface topography measured by Atomic Force Microscope (AFM). From
	both measurements, the surface Root Mean Square (RMS) are generally found less than 1
	nm. On the top of diamond surface, there are remarkable defect structures. More details

on

layer Ib HPHT diamond substrate Resist p-layer p + -layer Ib HPHT diamond substrate a) Laser lithography process b) Nickel mask deposition p-layer p + -layer Ib HPHT diamond substrate c) ICP etching d) Laser lithography process e) Ti, Pt, Au deposition and lift-off Top view p-layer p + -layer Ib HPHT diamond substrate p-layer p + -layer Ib HPHT diamond substrate p-layer p + -layer Ib HPHT diamond substrate

	40
	2.7a. MF26 developer is used to develop the photoresist. A plasma etching of 30 s is subsequently employed to eliminate the residual photoresist. Plassys ebeam evaporator is employed to deposit a 150 nm Nickel (Ni) mask layer on the dened region, as shown in Fig. 2.7b. The Plassys Reactive Ion Etching (RIE) with a manual process (average etching rate of 40 nm/min) is used for etching p-layer, as shown in Fig.2.7c. After etching, the Ni mask is removed by immerse into aqua-regia solution at 250 • C during 30 min. The etched thickness is conrmed by optical prole-meter and mechanical scanning Dektak, as shown in Fig.2.8. Figure 2.9 represents the test devices (MOS capacitors and MIM capacitors) fab-rication processes. In order to replace the hydrogen terminated layer by the oxygen terminated layer, we employed the Deep Ultra Violet (DUV) ozone technique [79]. The DUV ozone treatment is illustrated in Fig. 2.9a. Al 2 O 3 gate oxide was then deposited on top of the O-diamond by Atomic Layer Deposition (ALD) method by using a Savannah 100 ALD system from Cambridge Nanotech, as shown in Fig. 2.9b. This deposition method consists in sequential exposure of diamond surface to precursor Trimethylalu-minium (TMA) and oxidant water. The pulse and exposure duration were 15 ms and 30 s, respectively. Chamber pressure is typically set as 1.3 × 10 -1 (torr). Since there is no photoresist involved during the ALD deposition, the chamber temperature can be increased as high as desirable, in the limit of the equipment. During this thesis, two depo-sition temperatures were used: 250 • C and 380 • C (limit of our ALD equipment). After the p-layer C o n d e n t i a l p + -

VUV light + ozone O 2 O 3 O * O 2 O 3 O * O 2 O 3 O * O 2 O 3 O * p-layer p + -layer Ib HPHT diamond substrate TMA + H 2 O p-layer p + -layer Ib HPHT diamond substrate p + -layer Ib HPHT diamond substrate p-layer MIM MOS

	Figure 2.9: Schematic describing MOS capacitors and MIM capacitors fabrication steps.
	diamond MOS capacitor. Table 2.2 summarizes the processing details of the fabricated
	samples studied in this work.
	Sample	p-thickness (nm)	Oxide thickness t ox (nm)	Surface treatment	ALD temperature (°C)	Metal electrode	Annealing
	#1	600	20	DUV	250	Ti/Pt/Au	NA
	#2	300	10	DUV	250	Ni	NA
	#3	300	20	DUV	380	Ti/Pt/Au	500°C-VC
	#4	400	40	Chemical treatment	380	Ti/Pt/Au	NA
	#5	400	40	DUV	250	Ti/Pt/Au	NA
	#6	400	20	F-termination	250	Ti/Pt/Au	NA
	#7	400	20	DUV	380	Pt/Au	FGA 450°C

Table 2 .

 2

2: Processing conditions for fabricating test devices during this thesis. DUV indicates deep UV ozone treatment. F-termination indicates the uorine termination.

FGA indicates Forming Gas Annealing.

  As discussed in Chapter 1, a remarkable problem with diamond is the depth of dopant levels and the consequently incomplete ionization. Diamond with a moderate doping C o n d e n t i a l 2.2. Electrostatics of O-diamond MOS capacitor 53 concentration at RT will have low free carrier density. Subsequently, the epilayer is highly resistive. Once series resistance is considerable, equivalent circuit of the MOS capacitor is shown Fig. 2.24a. This equivalent circuit is equivalent to the series circuit C s -R s in Fig. 2.14c if we convert series capacitors C ox and C sc to C S . At high frequency, impedance of the capacitors is decreasing (Z C = 1

	jωC	). As a result, measured impedance

  As shown in Fig.2.26, a at band voltage of V F B =-7.3V is deduced. This value is larger than the theoretical one. Theoretically, V F B = φ M S = φ Mφ SC = -2.6 V where φ M = 4.3 eV is the work function of Ti metal and semiconductor work function is φ SC E G + χ sc -E A . With χ sc = 1.7 eV is the electron anity of O-diamond[33]. The discrepancy indicates the presence of net positive oxide charges.

	58
	2 slope and its inter-C o n d e n t i a l ception with gate bias axis. By applying the equation:

  In an ideal MOS capacitor, carriers transport between gate metal and semiconductor are necessary being blocked by a gate oxide. Electrostatics gate control of carrier population

	2.4. Results and Discussion	69
	1
	-6 -6 C o n d e n t i a l -4 -2 0 2 4 6 8 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 -1 B12 10 C17 C7 Current (A/cm 2 ) Voltage(V) -4 -2 0 2 4 6 8 10 -11 10 -9 Gate Bias (V) 1 MHz 500 kHz 100 kHz 50 kHz 10 -10 10 kHz 5 kHz Capacitance (pF) 1 kHz

  .34a), interface states play a central role C o n d e n t i a l 2.4. Results and Discussion 71with a special interest. They are able to communicate with both the metal electrode and the semiconductor valence band. In principle, each charge transfer process is represented by its characteristic time constant τ . For the sake of simplicity and without losing the generality, we will rstly consider interface states as a single level state at E it -E v and density of N it . In the following section, we will further discuss the charge transfer of interface states with metal and semiconductor band edge.2.4.2.1 Charge transfer between interface states and metalThe charge transfer between interface states and gate metal in a MOS capacitor system was addressed by Dahlke and Sze[START_REF] We Dahlke | Tunneling in metal-oxide-silicon structures[END_REF]. The complementary theory was then developed by Freeman and Dahlke[START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF]. In their theory, interface states are modeled as a potential well and communicate with the gate metal by direct tunneling. The charge transfer is considered as an overlapping process of two wave functions. Kar and Dahlke had

experimentally studied the metal injection into interface states with a non-degenerate Si substrate and a moderate oxide thickness (20 -40 Å) MOS capacitor system

[START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF]

.

A notable possible consequence of metal's carriers injection to interface states is that these carriers are possibly accommodating at interface states and therefore modulating Schottky barriers height at Metal-Semiconductor contact

[START_REF] Jl Freeouf | Are interface states consistent with schottky barrier measurements?[END_REF]

[104]

[START_REF] Muret | The inuence of interface states upon the admittance of metalsemiconductor diodes[END_REF]

.

In our case, the oxide is too thick to observe direct tunneling. Therefore, carriers injection from metal to interface states is suggested to be a process of two consecutive steps: the carriers tunneling from gate metal to oxide trap states (represented by tunneling time constant τ tun ) and then carrier hopping between trap sites happens in the oxide (represented by hopping time constant τ hop ). We considered that the global characteristic time constant for the charge transfer between metal to interface states τ T is approximately the time constant of the slower process in two mentioned processes.

Tunneling from metal to many oxide trap states As shown in Fig.

2

.34 a), electron from metal gate is suggested to initiate the ow by tunneling into Al 2 O 3 oxide layer. Even if there are many possible processes for a carrier from metal gate to be injected into the oxide

[START_REF] Chiu | A review on conduction mechanisms in dielectric lms[END_REF]

, most of them are practically not possible in our case. It's either direct tunneling, thermionic emission (Schottky injection) or tunneling into many trap states in the oxide. Considering the oxide thicknesses of 10 -40 nm that were systematically used for O-diamond MOS capacitors, direct tunneling by overlapping wave functions (theoretically less than 1 nm)

[START_REF] We Dahlke | Tunneling in metal-oxide-silicon structures[END_REF]

is not possible. Thermionic emission is a thermal activation process where carriers from metal have to reach a sucient energy to jump over the metal-oxide barrier height and being injected into oxide layer. Regarding an approximate 3 eV barrier height between Ti and Al 2 O 3 , this process is not realistic.

  2.37b where interface states recombination is in equilibrium with metal and interface states are in the same potential with oxide potential. One important notice is that, in case interface states recombination limited, the measured conductance is frequency independent[START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF][START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF].

Oxide-tunneling-limited When the oxide tunneling time constant is much longer with respect to interface states recombination time constant τ T >> τ R , the limiting process is the oxide tunneling. This is approximatively equivalent to interface states are in equilibrium with semiconductor

[START_REF] Lb Freeman | Theory of tunneling into interface states[END_REF]

[START_REF] Kar | Interface states in mos structures with 2040 å thick sio2 lms on nondegenerate si[END_REF]

. Since interface states are in equilibrium with semiconductor, the injection from metal to interface states is approximated as injection from metal to semiconductor. Interface states therefore will play a similar role with interface states in thick oxide model where it is in equilibrium and closed communication with semiconductor band edges. The approximated equivalent circuit for oxide tunneling limited is shown in Fig.

2

.37c.

Table 2 . 3

 23

	This simulation is performed by LTspice software	7 .
	Measurement method	MIMCAP	High frequency MOSCAP	Conductance G P /ω	Characteristic G P /ω frequency	Static I-V
	V G (V)	Parameters	C ox (pF)	C sc (pF)		C it (pF)	R it (MΩ)	G DC (μS)
		-8	70.8	35.8		24.2	2.6	0.64
		-7	70.8	31.2		15.7	5.07	0.50
		-6	70.8	26		20.9	4.8	0.33
		-5	70.8	18.2		23.5	10.7	0.153
		-4	70.8	13.36		32.2	19.68	0.05

: Input parameters for the LTSPICE simulation and the corresponding extraction method (MOS 12 -sample #1).

  Interface states resistance is evaluated by using the resonance frequency τ R =

	dI DC dV DC	. Finally,
	interface states capacitance C it and interface states resistance R it were evaluated from
	the equivalent interface states conductance 2 G P ω max . 1 C it R it of the trap states where G P ω show maxima. G P . With interface states capacitance C it = ω

The detailed parameters at dierent gate biases and the corresponding extraction method are represented in table 2.3. 7 http://www.linear.com/solutions/ltspice C o n d e n t i a l 2.4. Results and Discussion 85

  role of substrate on the electrical characteristics of the test device. The reverse current eects on small a.c signal measurements is modeled by an electrical equivalent circuit.

. A special attention is paid to correlate substrates prole with MOS capacitor's electrical characteristics. The combination of dierent electron beam microscopy techniques is used to elucidate the 8 done by D. Valenducq, a master 1 internship from University Grenoble Alpes at SC2G, Institut NEEL C o n d e n t i a l 94

  .7. Results and Discussion 95 also re-deposited onto p+ layer. Figure2.50b represents the Field Emission Scanning Electron Microscopy (FESEM) photograph of the substrate after the test devices were removed, grid region and ohmic contact were re-deposited. By comparing the plan view structure of test devices with grid region, we were able to determine the substrate region corresponding to each specic MOS capacitors.

order to correlate substrate prole with MOS capacitor electrical characteristic, we eliminate gate electrode and gate oxide of the sample after all electrical measurements have been done. The chemical etching by the aqua-regia solution is employed. Then, the substrate is immersed in KOH solution.

After that, we employed a new lithography process to dene a 8 × 8 grids into the pregion of the substrate (the region previously with MOS capacitors). Ohmic contacts were C o n d e n t i a l 2

Table 2 . 4

 24

: Input parameters for the a.c impedance/capacitance simulation and its corresponding extraction method.

  Deep depletion regime is demonstrated in metal oxide semiconductor capacitors using p-type oxygenterminated (100) diamond as semiconductor and Al 2 O 3 deposited by Atomic Layer Deposition (ALD) at 380 • C. Current voltage I(V) and capacitance voltage C(V) measurements were performed to study the effectiveness gate control diamond semiconductor. An effective modulation of the Space Charge Region (SCR) in deep depletion regime is obtained for positive gate bias. The deep depletion metal oxide semiconductor field effect transistor (MOSFET) using boron doped diamond are demonstrated.

	1) Univ. Grenoble Alpes, F-38042 Grenoble, France 2) CNRS, Inst. NEEL, F-38042 Grenoble, France 3) CNRS, G2Elab, F-38042 Grenoble, France 4) Department of Engineering, The University of Cambridge, CB2 1PZ Cambridge,
	United Kingdom 5) Institut Universitaire de France, 103 boulevard Saint Michel, 75005 Paris,
	France

TABLE I .

 I Sample t p -t p + tox O-termination T dep of ALD T annealing Sample structures details: thickness of moderately doped layer t p -, heavily doped layer t p + , oxide layer deposited by ALD tox, treatment for oxygen termination (VUV ozone treatment is defined as VUV), ALD deposition temperature T dep and annealing temperature T annealing .

		(nm) (nm) (nm)		( • C)	( • C)
	#1	600 300 20	VUV	250	NA
	#2	300 300 20	VUV	380	500

  7. (a) Equivalent conductance Gp/ω at different gate bias ranging from -4V≤ VG ≤ -8V of the MOS 12 -Sample #1, measured at RT. The single level interface state model is employed to simulate the equivalent conductance and demonstrate a good agreement. ; (b) Interface states density at Odiamond/Al2O3 interface measured by conductance method (open red circle curve) and by Terman method (open black circle curve).

  . Finally, interface states capacitance C it and interface states resistance R it were evaluated by conductance method GP ω with C it = 2 GP ω max and R it = τR Cit where τ R is extracted at GP ω max . Table II summarizes the parameters extracted by various methods at different gate bias for the impedance simulation. The LTSPICE simulation results are plotted

	10 -7	-8V MOS 12 -sample #1!
	10 -10 10 -9 10 -8 Capacitance (F)! Capacitance (F)	-7V -6V -5V -4V Simulation @RT! V ac =20mV!
	10 -11
		1 10 10 2 10 3 10 4 10 5 10 6
		Frequency (Hz) Frequency (Hz)!
	FIG. 8. Measured Capacitance-frequency dependence of the
	MOSCAP test device is reproduced by LTspice simulation
	with all the parameters extracted experimentally.

  Thanks to this comprehensive understanding, we established a new method that allows the complete electrostatics gate controlled O-diamond MOSCAP. This will open a new route toward gate controlled diamond MOS devices for power electronic applications. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.1.1 Transistor electrical characteristics . . . . . . . . . . . . . . . . . . 125 3.1.2 Diamond FET devices . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.2.1 Transistor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.2.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.2.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.2.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.3.1 Test devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.3.2 Transistor Performance . . . . . . . . . . . . . . . . . . . . . . . . 144 3.3.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 3.3.4 OFF-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4 Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 3.6 General Conclusion and Perspective . . . . . . . . . . . . . . . . . 160 3.6.1 General Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.6.2 Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

	126	Chapter 3. Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond
	Chapter 3 a.c small signal analyses, the prominent electrical characteristics can be summarized as
	follows:	Depletion-mode Metal Oxide
	C o n d e n t i a l C o n d e n t i a l C o n d e n t i a l Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond Contents 3.1 3.1 Introduction 3.1.1 Transistor electrical characteristics In Chapter 2, the comprehensive studies on boron doped O-diamond MOS capacitor test device were detailed. Based on electrostatics model, current transport mechanism and C o n d e n t i a l

V

  DS = -50 V and OFF-State breakdown voltage up to 1700 V [76][21], there are certain C o n d e n t i a l 128 Chapter 3. Depletion-mode Metal Oxide Semiconductor Field Eect Transistor (MOSFET) on Oxygen Terminated boron doped Diamond demerits in this kind of devices. As we pointed out in Chapter 1, its working mechanism is based on an uncontrolled parameters (negative charges in the oxide). Moreover, temperature eects typically increase the ON state resistance, similar to GaN HEMTs and other transistors at typical temperatures. Since 2DHG and BV are not related, there

table 3 . 1 .

 31 In principle, the channel is OFF when the two SCRs are collapsed and the whole thickness of epilayer under the gate is depleted. The channel is ON when the neutral region under the gate is existing. As we have mentioned, in some moderate breakdown

	voltage applications (around 1 kV), the channel conductance can be improved by the

Table 3 .

 3 1: Details of substrate parameters and processing conditions of two sample. free hole gas under the gate when the MOS structure are under accumulation regime.Furthermore, if the accumulation regime can be obtained, one can design a normally-OFF D-mode diamond transistor. However, as we have identied the FLPE of O-diamond MOS capacitor toward accumulation in the Chapter 2, we designed here a Normally-ON transistor, taking sucient margins to guarantee that both a ON state and a OFF state will be possible.

  1, Chapter 2 as well as the C-V measurement on the MOS capacitor test device on this sample, this accumulation is not obtained in experiment due to FLPE. In this simulation, interface states and gate oxide leakage current were not implemented. Therefore, in order to have a better agreement between simulation results and experiment results, it is important to either eliminate interface states and/or leakage current in the experiments or include interface states and gate oxide leakage into the simulation models.

  T.T. Pham, J. Pernot, D. Eon and E. Gheeraert are with Institut Néel , Université Grenoble Alpes, CNRS, Grenoble 38031, France. N. Rouger is with LAPLACE, INP Toulouse, CNRS, Toulouse 31071, France. nicolas.rouger@laplace.univ-tlse.fr thanh-toan.pham@neel.cnrs.fr state resistance in such transistors depends on surface conduction (sheet free carrier concentration and hole mobility in 2DHG, typical resistivity with a positive temperature coefficient) whereas the OFF state voltage breakdown is governed by typically unintentional doped diamond. In other p-type diamond transistors as MESFETs, the drift region is designed accordingly to the R ON S versus BV optimization (typical resistivity with a negative temperature coefficient), but with limitations due to excessive gate leakage for higher doping levels. Typical hole mobilities in previous diamond transistors were 8cm 2 /V.s [7] and 30 -100cm 2 /V.s [8] (hall effect measurement), showing room for improvements. On the other hand, several efforts on the MOS gate stack on Oxygen (O) terminated monocrystalline diamond have been done in [9], [10], offering new opportunities for diamond MOSFETs on O-terminated surfaces and better FET channel control. Novel MOSFET architectures have been also demonstrated in other wide bandgap materials, as with n-type β-Ga 2 O 3 depletion mode MOSFETs [11]-[14]. In this work, we design and develop a deep depletion mode diamond p-type MOSFET with a MOS gate on O-terminated diamond -figure 1. This normally-ON MOSFET will be grown on a nitrogen doped (ntype) monocrystalline diamond substrate. This depletion mode MOSFET offers new opportunities for a reliable fabrication and better R ON S versus BV compromises over a wide range of breakdown voltage and temperatures (in comparison with 2DHG FETs), and with a strongly reduced gate leakage (in comparison with MESFETs).

TABLE I PARAMETERS

 I OF SELECTED TRANSISTORS -MASK DIMENSIONS.

	Type, Device #	Lgs	Lg	Lgd	W
		µm µm	µm	µm
	Finger, #1 Corbino #2	4 4	3 4	3 10	34 176

Baliga, B Jayant, J. Appl. Phys. 53 1759 (1982).