Timothée Levi
email: timothee.levi@ims-bordeaux.fr

Member IEEE Noëlle Lewis
email: noelle.lewis@ims-bordeaux.fr

Jean Tomas
email: jean.tomas@ims-bordeaux.fr

Member IEEE Sylvie Renaud
email: sylvie.renaud@ims-bordeaux.fr

T Lévi

Application of IP-based Analog Platforms in the design of Neuromimetic Integrated Circuits

Keywords: Analog_circuits, CAD, Design Re-use, Neuromimetic Circuits and Systems, Behavioral and multidomain simulation

Re-use methodologies are now widely used to design digital circuits. They are based on the concept of Intellectual Property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design re-use for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on re-use, focusing on those three key questions: the formal content of the IP block, the design of a re-usable analog IP and finally the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. The method is inspired from platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of re-usable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage for future design projects.

I. RE-USE METHODOLOGY FOR CIRCUIT AND SYSTEM DESIGN

HANKS to the growing improvements in semi-conductor manufacturing processes nowadays, VLSI circuits can reach a high level of complexity. The design methodologies have also considerably evolved to allow System-on-Chip (SoC) integration. The SoC design flow is mainly based on reusable components, called Intellectual Property (IP) blocks or cores, which are now well defined and widely used in the digital domain [START_REF] Saleh | System-on-Chip: Reuse and Integration[END_REF]. They are classified from Soft to Hard IP; Soft IP refers to synthesizable HDL (Hardware Description Language) description and a Hard IP is a layout level design. The Firm IP corresponds to an intermediate level, and refers to a pre-synthesized block, using generic components, with a remaining degree of optimization respecting the technology specifications [START_REF] Keating | Reuse methodology manual[END_REF]. The advantages of Soft IPs are flexibility and portability, but their real behavior depends on the physical implementation; at the opposite, Hard IPs are optimized for a specific application, on a target technology, consequently they have a predictable behavior.

Moreover, digital design flow is much more automated than the analog one. Digital design profits from standardized tools and methods which allow automatic synthesis. While the trend over the past years has been to integrate both digital and analog circuits on the same chip, the analog part is always the most costly in terms of design effort.

Fig. 1 was extracted from a report on Design topic of International Technology Roadmap for Semiconductors (ITRS) [START_REF]International Technology Roadmap for Semiconductors (ITRS), Design[END_REF]. It illustrates the traditional V-cycle of system design, from specification to layout, with intermediate abstraction levels called behavioral and circuit levels. The topdown way is known as synthesis flow and the bottom-up way as verification flow. This compact picture summarizes the maturity difference between digital and analog design flows and emphasizes future requirements for Electronic Design Automation (EDA). For digital circuits there is a lack of methods and tools at the highest level of the hierarchy, (executable specifications and whole system verification procedures for example); for analog circuits, complete solutions are rarely found at all level of abstractions. Automation of the analog design process is still an open challenge, and re-use methodology is a predominant recommendation.

Important conceptual advances have been proposed in the last twenty years, with precursor works of [START_REF] Harjani | OASYS: A framework for analog circuit synthesis[END_REF] and [START_REF] Chang | A Top-Down, constraint-Driven Design Methodology for Analog Integrated Circuits[END_REF], resulting in effective software solutions. Our work was guided by these concepts and developments, and also took into account the specificities of neuromimetics circuits and systems. Our background material results from a 20 years experience in our research group in this field of neuromorphic engineering [START_REF] Tomas | Design of a modular and mixed neuromimetic ASIC[END_REF] [START_REF] Levi | Neuromimetic Integrated Circuits[END_REF]. It consists in particular in a library of analog computation blocks used to design analog ASICs (Application Specific Integrated Circuit) that mimic the dynamics of biological neurons electrical activity [START_REF] Saighi | A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable Real-Time Silicon Neurons[END_REF]. Those blocks were initially described by their electrical schematic and physical layout; we name it the "initial Hard IP." Starting from this background material, we intended to build a dedicated design platform, to automate the design of future neuromimetic ASICs. As demonstrated later, this context is very favorable to the development of a library of Firm IPs, and finally the implementation of an IP-based design flow.

T

The paper is organized as follows: in section II, a state-ofthe-art review describes the main concepts and solutions regarding analog design synthesis, and points out issues related to IP re-use in the analog domain. Preliminary tasks for the implementation of the design flow are discussed in section III. Then, we define our methodology in 3 points: the IP-package content (section IV), the design of a re-usable IP block (section V) and the integration of an IP in the system design flow (section VI). Concrete application of the methodology is given in section VII, through examples of design projects [START_REF] Tomas | Design of a modular and mixed neuromimetic ASIC[END_REF].

II. STATE-OF-THE-ART REVIEW : BACKGROUND CONCEPTS AND ISSUES FOR ANALOG IP RE-USE

A. Background concepts for analog design flow automation

Before addressing the specifications of an analog IP-based design framework, let us overview the possible approaches to improve the analog design flow for VLSI and reach the automatic analog synthesis.

First, directly inspired from the success story of digital design using FPGAs, we would like to mention the FPAA (Field Programmable Analog Array) technology [START_REF] Basu | A Floating-Gate-Based Field-Programmable Analog Array[END_REF]. Its principle is very efficient for the rapid prototyping of state-of-the-art analog functions; it can't be yet applied to our application domain, which requires very specific functional blocks.

Then, concerning analog ASIC design automation, the main problem is the optimization of one architecture or topology for a set of specifications. Two ways are then possible for this optimization: simulation-based [START_REF] Koh | OPASYN: a compiler for CMOS operational amplifiers[END_REF], [START_REF] Phelps | Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search[END_REF] or knowledge-based. The first one sizes a given schematic by a closed-loop process with an optimizer, an analog simulator and standard transistor models. The drawbacks are intensive simulations, CPU time and the selection of the design parameters among a huge list. Analog designers are generally more interested in knowledgebased optimization, to keep control over the choice of parameters. This was also our choice. A review of knowledgebased synthesis tools can be found in [START_REF] Iskander | Knowledge-aware synthesis for analog integrated circuit design and reuse[END_REF]. In such an approach, the designer must identify (i) a useful subset of design parameters in relation to the targeted performances, (ii) the circuit equations, and (iii) the sizing procedure.

The circuit equations are supposed to relate the performance parameters to the design parameters. This point is a non-trivial issue, which involves simplification algorithms and more or less insights in the circuit operation [START_REF] Martens | High-level modeling and synthesis of analog integrated systems[END_REF], [START_REF] Harjani | OASYS: A framework for analog circuit synthesis[END_REF], [START_REF] Rutenbar | Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs[END_REF]. As explained in section IV, our approach leads to multi-level modeling, starting from the ideal functional equation (given by neuroscientists in our case), with gradual refinement to behavioral equations. We use mainly the technique of userdefined equations and sometimes a simulation-based technique coupled with regression.

The circuit sizing process generally happens after topology selection. It starts from an un-sized schematic and follows the designer's steps to set a sized schematic, responding to the specifications. Layout generation, as the final design step, is often a separate task and rarely included in the sizing procedure [START_REF] Tuong | Définition et implantation d'un langage de conception de composants analogiques réutilisables[END_REF].

For complex integrated circuit, up to the system level, a hierarchy of abstraction levels must be defined and the topdown/bottom-up design flows may be combined in different ways. One can propagate the constraints down starting from top-level to the schematic and layout [START_REF] Chang | A Top-Down, constraint-Driven Design Methodology for Analog Integrated Circuits[END_REF], [START_REF] Gielen | Computer-aided design of analog and mixed-signal integrated circuits[END_REF], [START_REF] Castro-Lopez | Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits[END_REF]. Another solution is to merge top-down and bottom-up flows in a meetin-the-middle approach, which is the principle of platformbased design [START_REF] Bernardinis | Robust System Level Design with Analog Platforms[END_REF], [START_REF] Sun | Contract-Based System-Level Composition of Analog Circuits[END_REF]. This method relies on a library of components, well characterized and abstracted in a set of models, used for a bottom-up phase. Then the top-down phase consists in selecting the optimal component, according to some cost function, that satisfies all constraints.

Two main reasons justified our choice to build such a design platform. The first one is related to our specific application field of neuromimetic ASICs. Such devices require the use of non-traditional analog functional blocks, different from OTAs or OPAMPs. In addition, to ensure stability throughout longterm projects in this field, we could start from functional modules already identified and sized for previous projects [START_REF] Saighi | A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable Real-Time Silicon Neurons[END_REF]. So we did not question the sizing procedure from the beginning but rather decided to characterize the ability to reuse these blocks; in other words, the question was how to transform a library of Hard IPs (schematic and layout) in a library of Firm IPs and how to implement an automated flow for further design projects.

B. What kind of IP for an analog block?

The notion of analog IP for automation of analog design flow was the subject of numerous debates [START_REF] Ohr | PANEL : analog intellectual property : now ? or never ?[END_REF], [START_REF] Koch | Analog IP -stairway to SoC heaven ?[END_REF], [START_REF] Singh | Analog IP re-use: concerns for "digitally-oriented" SoC designers[END_REF], [START_REF] Goering | True Circuits rolls out 65-nm analog IP[END_REF] and [START_REF] Li | A Study on Analog IP Blocks for Mixed-Signal SoC[END_REF].

Ideally, the analog design flow should be identical to the digital one, but this is not the case yet. Of course, the initial context is different and the rules based on analog design are more difficult than Boole algebra. The designer has to challenge non-linear functional relationships, technological parameters and various second order sensitivities [START_REF] Dessouky | Analog Design for Reuse -Case Study : Very Low-voltage ∆Σ Modulator[END_REF], [START_REF] Gilbert | Design for manufacture, Trade-offs in analog circuit design. The designer's companion[END_REF] (temperature, noise, mismatch, etc.). Analog signal processing is more performing in terms of speed and power consumption but its design is more difficult, closely linked to designer's knowledge. An analog block is designed for a specific application. Consequently there is no consensus on the analog design processes and the primitive functions could be very different depending on cases: current or voltage design mode, bipolar or CMOS design, strong or weak inversion mode for CMOS transistors, etc.

A clear definition of what should contain an analog IP is therefore the starting point for a productive, capable reusebased design framework for analog ICs. The 3 classes of digital IPs have been exposed in the introduction. Let us see hereafter, the pertinence of this classification for the analog case.

1) Hard IP?

Among the typical operators in analog design, we can find operational amplifiers, ADC and DAC convertors, PLLs, filters, voltage references and RF modules. These blocks are usually optimized in consumption and area for one specific application: the natural trend in analog design is then Hard IP. This type of IP had been chosen in the guide of design and documentation steps by VSIA consortium in 2001 [START_REF] Vsia | Analog/Mixed-Signal VSI Extension Specification Version 2.2[END_REF].

In this case, technology migrations are solved by re-design instead of re-use.

2) Soft IP?

What could be a Soft-IP in analog design? We can describe in HDL design language one analog block with the selected functionality. The issue is that there is currently no universal synthesis process which delivers a sized electrical schematic for one application. Furthermore, we first have to select a design mode (current mode, voltage mode), choose primitive functional blocks and select one topology for each. One helping tool capable of enabling the designer to choose one topology among different possibilities would be a great step for the analog synthesis. Promising work about analog circuit sizing method using interval analysis could solve this issue [START_REF] Michel | Analogue circuit sizing method using interval analysis[END_REF] and allow selecting or deleting some topologies. Nevertheless, before creating this selection tool, a database should be build, with adequate documentation for each topology.

3) Firm IP?

Between the Soft and the Hard-IP, we find the Firm-IP which seems to be the best choice for analog design. It is a compromise between a fixed layout and a purely HDL description. It proposes a design based on electrical schematic, with enough tunable characteristics to be re-usable for several applications.

C. State-of-the-art review

Questions arising from the development of an IP-based analog design flow can be illustrated by Fig. 2. The IP Library is the central point; it is filled by the Analog IP Design Flow and it interacts with the System Design Flow. Then, the first task is to define [START_REF] Saleh | System-on-Chip: Reuse and Integration[END_REF] what kind of information should be embedded in the IP and in which format. After that, it is important to emphasize (2) the design methodology of a reusable IP, because it differs from the design methodology of a "one-shot" circuit. And the last point is (3) the re-use of an IP in the system design flow. First, we propose to review how these three points have been addressed by the main contributions that could be found in the literature.

1) IP-package content

This point deals with the IP general information, including characteristic parameters, design knowledge, models, description formats adapted to every step of the design flow (architecture simulation, sizing, verification, and layout).

O'Connor et al. [START_REF] O'connor | UML/XMLbased approach to hierarchical AMS synthesis[END_REF], [START_REF] Connor | CNTFET Modeling and Reconfigurable Logic-Circuit Design[END_REF], [START_REF] Connor | Automated synthesis of current-memory cells[END_REF] have defined as analog IP content:

-Set of descriptive views: input/output ports, functional model, structural model -Set of parameters: for electrical performances, electrical and physical design -Set of relationships and calculation methods between these parameters.

Evaluation methodology allows the translation from physical to performance parameters. Extraction methodology allows the translation from simulations to performance parameters. Synthesis methodology allows the translation from performance to design parameters. Constraint distribution methodology formalizes the translation from IP to under-block specifications.

These relationships are built from the designer knowledge and the main challenge is to express it. This knowledge could be written in an analytical form with an approach based on experiences, or in a procedural form with an approach based on extensive simulations and optimization. This analog IP definition has been applied to amplifier circuits included in a chain of CMOS photo-reception and used to demonstrate the possibility of an automated hierarchical synthesis, in the field of interconnection optical systems.

Secondly, Castro-Lopez et al. [START_REF] Castro-Lopez | Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits[END_REF], [START_REF] Castro-Lopez | An Integrated Layout-Synthesis Approach for Analog ICs[END_REF] have defined an analog IP that contains a behavioral model, a sized schematic and a layout. As this IP is developed for a specific technology, this definition is close to what we consider as Hard IP.

Third, Hamour et al. [START_REF] Hamour | Analog IP design flow for SoC applications[END_REF] have proposed an IP definition including similar views: sized schematic, behavioral model, test bench model, but no layout.

Pimentel et al. [START_REF] Pimentel | A Methodology for Describing Analog/Mixed-Signal Blocks as IP[END_REF] describe the content of analog and mixed signal IPs: one IP could be divided into three parts: models (functional, behavioral and structural), documents (basic information, user, creation and test guides, physical implementation and models) and circuit schematics.

2) The design of one IP

This point is important for guiding the designer in the different development steps of a re-usable block [START_REF] Binkley | A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design[END_REF]. Analyzing the experience design to make it re-usable is a complex task. In particular, formalizing the sizing process is a critical step.

Louërat et al. have developed a tool named CAIRO+, which is a platform of analog IP re-use [START_REF] Iskander | Design Space Exploration for Analog IPs using CAIRO+[END_REF], [START_REF] Iskander | Automatic DC Operating Point Computation and Design Plan Generation for Analog IPs[END_REF]. First, the designer has to describe his circuit into an electrical schematic, a set of sizing parameters and a floor plan layout. CAIRO+ tool can make an automatic sizing and layout, depending on technological parameters, if the procedural sizing steps have been described beforehand. This task is assisted by a synthesis methodology developed in the dissertation of R. Iskander [START_REF] Iskander | Knowledge-aware synthesis for analog integrated circuit design and reuse[END_REF].

3) Integration of an IP in the system design flow

What are the main issues related to this point? First, from the architecture exploration to the verification step, it is mandatory to manage different abstraction levels of the IP. Another point is the storage of IPs into a data base which could be queried according to an adequate exploration method.

Besides these questions, interesting approaches of Firm IP hardening flow have been developed, by two previously cited teams. With Louërat et al., the IP description in CAIRO+ is parametric and described into equations then the Hard IP is automated and needn't optimization. Some examples are in the Nguyen-Tuong dissertation [START_REF] Tuong | Définition et implantation d'un langage de conception de composants analogiques réutilisables[END_REF]. With O'Connor et al., the synthesis process is described with UML language and it is included into the design platform (RUNE II) which contains simulation and optimization tools [START_REF] Tissafi-Drissi | RUNE: Platform for automated design of integrated multi-domain systems. Application to high-speed CMOS photoreceiver front-ends[END_REF].

Note that, despite the general trend is to design a library of Firm IPs, a specific adjustable functional component, the answers to the previous three main questions depend on the initial IP point of view. The method used to reach the desired Firm IP differs in two ways: in some cases the notion of Firm IP is progressively derived from a Soft IP view, while in other cases it is derived from an initial Hard-IPs library. Our approach belongs to this second case. Indeed our background material was a library of blocks listing 3 views: symbol, schematic and layout. As explained in section I, the issue here was to transform a library of Hard IPs in a library of Firm IPs. The critical points in the proposed process are: multi-level modeling, characterization of validity range to fit requested performances. Finally we implemented a system design flow, based on the automated exploration of an IP database. We are now going to detail step by step the process methodology.

III. PRELIMINARY TASKS TO ESTABLISH THE DESIGN FLOW

Preparatory tasks are required to structure and finally establish an IP-based design flow. The first one is to define the system hierarchy and the primitive blocks, which are associated to each level of this hierarchy. The second one is to define a set of typical specifications that constrains the circuit performances. This part will describe these preliminary issues, with examples taken from our application context of neuromorphic engineering.

A. The specific context of neuromorphic engineering

The originality of that work relies on this particular application domain: the design of analog ASICs that are involved in neuromorphic systems. The goal of neuromorphic engineering is to develop integrated circuits and systems that emulate the electrical activity of biological neural networks. From the microelectronic point of view, one solution is to design analog ASICs for real-time computation of neurons' activity and to digitally control the connectivity between these neurons. We focus here on a series of analog ASICs that implement an electro-physiological neuron model, inspired from the Hodgkin-Huxley (HH) formalism [START_REF] Hodgkin | A quantitative description of membrane current and its application to conduction and excitation in nerve[END_REF]. They are typically used as hardware simulators in computational neurosciences, in order to explore information coding and adaptation principles in the brain [START_REF] Renaud | PAX: A mixed hardware/software simulation platform for spiking neural networks[END_REF].

This domain has appeared to be a favorable background to the development of a design flow based on IP-reuse. The main reason is that the bases of system hierarchy and design primitives have been clearly established, along successive design projects [START_REF] Levi | Neuromimetic Integrated Circuits[END_REF]. This point is finally similar to the reality of digital design and it should be the first requirement of the methodology: what is the system hierarchy and what are the primitives at each hierarchical level?

B. Design primitives and system hierarchy

The principle of the modular design of the neuromimetic ASICs has been already exposed in [START_REF] Saighi | A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable Real-Time Silicon Neurons[END_REF]. The architecture of one ASIC is based on the repetition of a small number of computation primitives, namely sigmoid, kinetic, power, output (see Fig. 3). One can consider them as a first version of the IP blocks, on the form of Hard IPs, that were realized on AMS BiCMOS 0.35 m process. Each of these elementary cells is an analog operator involved in the equations of the Hodgkin-Huxley formalism. These analog operators are then assembled to produce a so-called neuromimetic ASIC, capable of emulating, in real-time, the dynamics of a small neuron's network. Fig. 3 shows the correspondence between the mathematical function of the HH model and the analog cells that are used for its realization. Note the choice of a current mode design. V mem is the membrane potential of the neuron, while V offset and V slope are input voltages used to tune the neuron model parameters. τ is the kinetic of the activation/inactivation of ionic current. g max is the maximum conductance, and m and h represent the activation and inactivation terms, respectively. Dynamic functions describe the permeability of membrane channels to its specific ion. V equi is the ion-specific reverse potential and p and q are integers. m relaxes back toward its associated steadystate value m  , which is a sigmoid function of V mem .

Starting from the previous basic operators, it is possible to construct the hierarchy of an integrated circuit that emulates a biologically realistic neural network: this hierarchy is described on Fig. 4. The IP level corresponds to the recurrent computation blocks of Fig. 3 and the higher hierarchical levels of rank N+1 are simply structural descriptions using the primitive blocks of level N.

C. System specifications and IP-block performances

The specifications of such a system are slightly non-typical, regarding the traditional analog design field. The neuroscientists interested in those systems want to fix:

-the number of neurons defining the network: N (defined at System Level) -the number and type of ionic channels considered for each neuron: Na conductance (Sodium channel), K conductance (Potassium channel), Leak conductance (Leak channel) and Slow conductance (additive channel for calcium dependence) (defined at Macro-block level) -the number of synapses Ns for each neuron and their electrophysiological parameters: τ, V equi and g max .

(defined at Macro-block level) -the electrophysiological parameters of each ionic channel:

V offset , V slope , τ, V equi and g max .

(defined at Block Level and propagated to Cell Level).

Let us note that for the Na conductance and Slow conductance, the parameters V offset , V slope and τ, are duplicated because of two concurrent processes in the neurophysiology, named activation and inactivation. A typical specifications set is given on Table I. It corresponds to a small circuit of two neurons: Neuron 1 has 3 ionic channels (Na, K, Leak) and Neuron 2 has one additive channel for calcium dependence (Slow conductance). Furthermore, the implemented neuron models must emulate a variety of biological neuron behaviors, thus the IP-blocks must be designed to guaranty a certain tuning range for the electrophysiological parameters. This constraint imposes that the IP-block functionality must be preserved while varying the electrophysiological parameters in the so-called validity ranges. Hence, the performances of the IP-blocks are quite non typical and are given in terms of these validity ranges. For example, typical performances for sigmoid IP are given in Table II

0.5 V 4.5 V Voffset 1.5 V 3.3 V Kslope 1.7 V 4.7 V
After this introduction, required to efficiently prepare the implementation of an IP-based design flow, we will now consider in details the three main points of the methodology.

IV. ANALOG IP PACKAGE

As explained in part II, our approach is to build Firm IPs starting from Hard IPs (only symbol, schematic and layout) that have previously been designed and optimized for a given project. So the question is: how can we transform a Hard IP to a Firm IP? Based on our experience, combined with the proposed studies in the literature, it appears that the main properties required for a re-usable IP are:

-ease of simulation at each level of abstraction of the system, -description of the design process and -ability to resize the IP to deal with a technology migration or a change in specifications. In our methodology, each Firm IP we created has 7 informative views that are described in Table III. The views Symbol, Schematic and Layout were already present in the Hard IPs library. The new Firm IP package contains additive description views that correspond to hierarchical abstraction models (Connectical, Functional and Behavioral). These models are developed by the designer, in a standard design language. In our case, we use the Verilog-A language [START_REF]Verilog-A, Language Reference Manual[END_REF]. In order to have a fluent design flow, all these views have the same terminals and the same symbol as the schematic. These views are useful for multilevel simulations especially in the verification phase of the design process. The Functional view describes the ideal equations of the function to be implemented. The Behavioral view is more detailed and contains refined equations that fit the circuit non-ideal behavior [START_REF] Shi | VHDL-A design objectives and rationale[END_REF], [START_REF] Pêcheux | VHDL-AMS and Verilog-AMS as Alternative Hardware Description Languages for Efficient Modeling of Multidiscipline Systems[END_REF]. The Connectical view is an empty model used to verify that blocks are well connected, without any functional equations. It is used for the ultimate verifications, when the overall ASIC needs to be simulated. To emphasize the re-usability of one IP, we also add a last file, namely the Documentation view. This file finally collects the design expertise and contains data such as:

-the performance and design parameters -the design procedure and sizing algorithm (or how to link the performance parameters to the design parameters) -the characterization of the block with the objective of reuse (what are the performances, how to measure them, and how far the circuit functionality is stable regarding operational changes) -information that concerns the already designed layout view (technology, supply voltage, area and cost).

V. DESIGN OF A RE-USABLE IP

Design for re-use is not limited to the design and sizing of a "one-shot" circuit (Hard IP case). An additional effort is required to obtain a Firm-IP; in our case it is to express the design procedure, to develop hierarchical models, to characterize the circuit and to write the documentation file. This methodology is presented here using the example block sigmoid.

A. Design procedure of one IP

The expression of design expertise is essential to make an IP re-usable. The topology of the circuit being given, we must begin by identifying the performance parameters of the block (the parameters that are constrained by specifications) and the design parameters (those that can be adjusted in the design procedure); then explain how the design parameters are linked to the performance parameters. Let develop this point on the sigmoid block.

As mentioned in Fig. 3, the mathematical function of the HH formalism to imitate is the following:

Vslope Voffset Vmem mem e V m ) ( 1 1 ) (      (1)
In practice, one chooses to represent the variable m ∞ with a normalized current 2I 0 . The electrical functional equation becomes:

Vslope Voffset Vmem m e I I ) ( 0 1 2      (2)
The topology chosen to emulate this function is based on a differential pair which takes direct input voltages V mem and V offset . The slope control parameter V slope of the model is generated through a current-voltage converter, controlled by the K slope voltage [START_REF] Levi | Neuromimetic Integrated Circuits[END_REF]. The Schematic view is given below by Fig. 5: Thus the tuning of the V slope parameter is made using the following equation where U T is the thermal voltage (≈25 mV at 25 °C):

slope slope T slope R K Vcc I r U R V   0 (5)
We can extract the parameters needed for this design procedure. The performance parameters are V mem , V offset , V slope (or K slope which is linearly related to V slope ). The design parameters are: R slope , R, r and I 0 . The previous equations are used to connect those two sets of parameters using a method based on knowledge.

B. Multi-level modeling of one IP

As explained previously, models are considered at 3 levels of abstraction and are written in Verilog-AMS. Using the example of the sigmoid block, the Functional model reproduces the functional equations of the preceding paragraph (3), ( 4), [START_REF] Levi | Neuromimetic Integrated Circuits[END_REF]. For the Behavioral model, the input and output impedances are included as well as non-ideal effects. For instance, in this sigmoid block, we add the non-ideal gain of the op-amp in the voltage-current converter, the unbalanced differential pairs and the copy factor errors of current mirrors. All that non-ideals characteristics are extracted from electrical simulations of Schematic view.

The Connectical view is at a higher abstraction level; it is a virtually empty block, simply being responsible for detecting defaults of connection between blocks. The principle consists in verifying that the voltages and currents applied to the block lie within a plausible range, and if so, the output is set to a nominal value, if not it is set to zero.

Simulations with multiple levels of abstraction are then very interesting to optimize the simulation time: some critical IPs can then be represented by their Behavioral or even Schematic view, while standard IPs may be represented by their Functional or Connectical view.

C. Characterization procedure of an IP

The IP characterization is useful to define the performances of the cell. In the context of re-use, the question is also: under what conditions the unit may undergo a change in specifications?

We have previously seen that the performance parameters of the sigmoid block are V mem , V offset and K slope input voltages. The IP has been sized once to ensure proper operation for precise values of these voltages. To what extend can the IP keeps its functionality for a different set of values? To determine this, a systematic analysis was performed to extract the validity ranges of the performance parameters, i.e. the intervals of V mem , V offset and K slope where the sigmoidal function is preserved. This study is conducted by performing a series of simulations (AC, DC, transient and Monte Carlo) with the initial Hard IP, already sized for a given set of specifications. The validity ranges of input voltages of sigmoid block have been previously given on Table II.

This simply means that the IP sigmoid can be re-used without modification in its design, provided that the specifications for V mem , V offset and K slope are included in these intervals.

The Documentation file includes the description of the characterization procedure as well as the results of all simulations. To illustrate this, Fig. 7 shows the responses of the circuit (I sig ) to a DC voltage sweep of V mem for several values of V offset . The validity range for V offset is then determined so that this error does not exceed 5x10 -7 . Fig. 8 shows that bars 20 and 21 are outside the range (20, 21 corresponds respectively to V offset =3.4 V and V offset =3.5 V); thus the validity range for V offset is [1.5 , 3.3] V, as mentioned in Table II.

To complete the IP characterization procedure, we evaluate the robustness of this validity range versus the technological fluctuations. We performed 3 Monte-Carlo simulations using as input values, respectively the middle, the upper bound, the lower bound of the parameters intervals (Table II). In that case, MonteCarlo simulation results show that 0% of I sig simulated values are out of the tolerance interval; thus we don't modify the preliminary validity range (defined in Table II).

VI. IMPLEMENTATION OF AN IP-BASED ASIC DESIGN FLOW

The recurrent IP blocks have been now designed, modeled and characterized using the approach described in the previous paragraph. Now the arising question is the organization of the IPs in a database that can be the hub of the design flow of an ASIC. In this part, the IP database implementation and exploration are addressed.

A. General organization of the flow

A typical flow chart is given in Fig. 10. Once the ASIC specifications are known (see typical specifications of Table I), functional models present in the database can be used to validate a first architecture by highlevel simulations. The database is then queried to see if the IPs can be re-used. If so, the different views contained in the IP package are retrieved for the final stages of the design. If not, we will see how characterization information can be used to re-adjust an existing IP.

B. Database structure

IPs are gathered in a SQL database hosted on an Apache server [START_REF] Bowen | Apache server[END_REF]. Ten tables were needed to describe this database:

-Definition of each IP: 1 table -Link father-son between functions (hierarchical link between level N and level N-1): 1 table, describing the hierarchy of the system -Link father-son between IPs: 3 tables, one for each hierarchical level (Cell, Block, Macro-block) -Number of IPs for a given function: 1 table -Performance parameters' values of each IP: 3 tables, one for each hierarchical level (Cell, Block, Macro-block) -Connection between different Macro-blocks which define the whole system: 1 table This covers all information for one IP, including characterization and hierarchical data, to be able to implement an automatic top-down exploration. This database is included in an operating platform that transforms the specification (captured on a remote computer by the 'client') in requests (sent to the server machine designer). This required the use of PHP [START_REF] Rigaux | Pratique de MySql et Php[END_REF], SQL [START_REF] Dubois | Sams Developer's Library[END_REF], HTML and XML [START_REF] Abiteboul | Data on the web from relations to semistructured data and XML[END_REF].

Once the specifications have been entered in a web form, a PHP script extracts data from it, arrange them in a text file and produce a report for the client. For the designer's point of view, the specification data are transformed into SQL requests which explore the database and a report is created.

C. Database exploration method

The most important criteria for the exploration of the database are: (i) the targeted technology and (ii) the desired specifications, in the form of parameter values P spec , such as those of Table I: V offset , K slope , τ, V equi , g max . As explained previously, re-usability of each of the IP is characterized by validity domains [P min , P max ] for the performance parameters V offset , K slope , V equi , g max . For the kinetics parameter, τ, it depends on an external capacitance value, connected to the kinetic block.

The exploration method is a Top-Down one, from the Macro-Block Level to the Cell Level; an IP is selected if its performance validity domains can cover the targeted specifications, i.e. if : P min < P spec < P max [START_REF] Saighi | A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable Real-Time Silicon Neurons[END_REF] The database exploration algorithm is based on the principle illustrated by the chart of Fig. 11. If we have different corresponding IPs, we take the closest to the specifications: we calculate, for each parameter, the distance between the specification and the middle of the validity range, named d:

2 min max P P P d spec    (7)
Then we accumulate the total distance by adding the contribution of each parameter. It is logical to take the IP corresponding to the minimum total distance.

D. Results of the exploration

As illustrated on Fig. 11, when looking for one IP corresponding to given specifications, the answer can be:

-a) one IP exists in the database -b) no IP could be immediately found but there is one IP whose performances are close to the specifications -c) one IP corresponds to the specifications but it was designed in another technology process.

In case a), the IP package is recovered by the designer. In cases b) and c), an aid for re-design is given. Case b) will be illustrated in an example in the next part. In the case (c)) the issue results from the technology or the supply voltage, some guidelines we developed for a resizing methodology can help to fix the problem, [START_REF] Levi | A CMOS Resizing Methodology for Analog Circuits: linear and non-linear applications[END_REF] but that will not be detailed here.

At the final step, a diagnosis is returned and quantifies the possibility of re-using IPs for a new ASIC project. This is illustrated in Fig. 12. In practice, this step is performed thanks to an XML file that summarizes the results of the exploration and allows generating an HTML page (not shown) of the diagnosis. In case of a successful exploration (previous case a)), this page also indicates, the result of the automatic calculation of external capacitances (needed to obtain the desired  values) and details the IP content with related links to access more information.

Figure 12. Screen snapshot of HTML diagnosis of re-use for a given ASIC design project ; a green boxt means "the IP has been found with the desired specfications", a red box means "no IP has been found" and a white box reports on a case not applicable. This diagnosis describes firstly the connection status to the database, the number of requested neurons, the chosen technology and associated supply voltage. Secondly, it describes the result of the top-down database exploration. We see in the example that the macro-block FS neuron didn't match all the specifications. Tests to identify the problem source showed that the Sodium current blocks didn't match and more specifically the Sigmoid Cells. The problematic parameter is then Vslope_inactivation, as the exploration algorithm cannot find a corresponding IP. A table summarizes the results: green marks when the IP is identified, red mark otherwise.

VII. EXAMPLES OF USE

The database automatic exploration process has been tested on many plausible specifications' sets. Here we propose two examples of the implemented design flow, each one corresponding to realistic design projects.

A. Design project 1

For this first application, the objective is to design one neuromorphic ASIC, which is composed of five neurons: three are regular spiking neurons (RS neuron), one is a fast spiking neuron (FS neuron) and one is a slow conductance neuron (5c neuron) [START_REF] Renaud | Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks[END_REF]. The initial specifications, defined in agreement with our biologist partners, are partially given on Table I of part III. This Table summarizes the specifications of 2 of the 5 neurons.

As biological specifications are filled in, designer chooses conversion factors (voltage and capacitance factors) as well as the targeted technology to transform biological specifications to electrical specifications.

In this favourable case of use, the diagnosis of re-use indicates a total success, i.e. all needed IPs have been found in the database. The exploration program takes less than one minute to give the result, in the form of 5 diagnosis tables. Then, the designer can quickly retrieve the system netlist, as well as all IP-packages. At this step, the designer is able to perform different verifications through multi-level simulations of the entire ASIC. To illustrate this, Fig. 13 shows a multi-level simulation of the full ASIC. We test the RS neuron 3 and 5c neuron with transistor level descriptions (Schematic view) while the other blocks use Behavioral views. The validation criterion is the presence of oscillations with neuromimetic spikes on the membrane voltage of each neuron, what appears clearly on the transient response. The Behavioral view realizes a compromise between accuracy and computation time. The simulation of one FS neuron at transistor level takes 14 min 56 s for a simulation stop time of 60 ms; this duration decreases to 3 min 17 s using the Behavioral view. Furthermore, this simulation time increases exponentially versus the number of neurons (around 10 hours for a simulation of 5 neurons at transistor level). This design project 1 was complete and was sent to the foundry. This new ASIC named Galway is currently working.

B. Design project 2

For this second application, the objective is to design one ASIC composed of two neurons. The initial specifications are slightly different from those of Table I; the specification for V slope_inact for Na conductance is now -23 mV instead of -7.3 mV (both values are biologically realistic). Fig. 12 represents the diagnosis of re-use for this new set of specifications. It indicates that the specifications of the inactivation sigmoid IP of Sodium current of a Neuron 1 could not be met during the exploration (presence of the red rectangle in the table). At this step, the designer has localized the issue and our tool includes an aid for re-design. The idea is to create a new IP block by resing an existing one.

First of all, the database is re-explored for finding the sigmoid IP that is the closest to the required specifications. This can be performed simply and automatically by minimizing the distance defined by equation ( 6).

In the current example, the problem comes from the specification of the V slope parameter. The sizing relation between V slope and the design parameters, which has been expressed previously in equation ( 5), can be found in the Documentation file of the sigmoid IP.

To adequately re-size the IP, we just have to change the value of one design parameter, R. In our case, we changed the value from 30 kΩ to 35 kΩ, which had the consequence to shift the V slope validity domain to include the specification value. The layout view has to be redesigned from the original one. Usually it just consists in enlarging or reducing the size of resistances or capacitors. Nevertheless, in some case, it could be more complex and require the use of automatic layout resizing techniques [START_REF] Dessouky | Analog Design for Reuse -Case Study : Very Low-voltage ∆Σ Modulator[END_REF], [START_REF] Youssef | A Pythonbased layout-aware analog design methodology for nanometric technologies[END_REF]. This new IP can now be added to the database. Its design time is almost negligible compared to the first-time design of one IP. Thanks to the documentation view, that expresses the relationships between the design parameters and the performance parameters, re-sizing just consists in modifying the design parameters.

VIII. CONCLUSION

Globally, automation of the analog design process is still an open challenge, and re-use methodology is a predominant recommendation of the ITRS. This paper has proposed a synthesis of an experience in analog IC design, centered on the notion of IP. Following the presentation of the issue and review of contributions found in the literature, a methodology is explained in details, with a tutorial intention.

In order to develop an analog design flow based on re-use, some preliminary work is necessary: it includes a clear definition of the system hierarchy, and the identification of the the computation primitives, or IP blocks, at each level of the hierarchy. IP blocks of the lowest level include several transistors and each one is associated with a function. We applied our methodology to the case of neuromimetic ASICs, which design needs can be addressed by our design flow. Furthermore, these devices offer a clear definition of design primitives and system hierarchy.

The starting point of the methodology was an existing library of Hard IP blocks and the first question addressed here is: what information must be added to a Hard IP to transform it into a Firm IP? The proposed answer is (i) to develop a set of models, adapted to multiple abstraction levels, (ii) to formulate the sizing relationships between performance parameters and design parameters and (iii) to characterize to what extent the IP can keep its functionality, when varying the values of performances parameters.

The next point is the implementation of an ASIC design flow centered on a database gathering these IPs. A SQL database, including IP packages and hierarchical links between blocks, has been built that allows the implementation of an automatic top-down exploration. We explained the algorithm used to found an IP corresponding to the desired specifications. Finally, the resulting automatic design flow has been tested for two plausible ASIC design projects. These examples show how our web-based platform can assist the designer: it globally accelerates the system design cycle, the designer can quickly see a diagnosis of re-use for his targeted ASIC. In case of total success, the IP packages are immediately retrieved and the designer can perform multi-level simulations of the entire ASIC in a verification phase; in case of partial success, our tool proposes an aid to re-design an IP that matches the specifications.

Figure 2 .

 2 Figure 2. First-preview of an analog IP-based design flow

Figure 3 .

 3 Figure 3. Correspondence between mathematical function and electrical implementation, for each type of Cell Level IP. All the voltages (Vmem, Voffset, Vequi, Vslope) are in Volt in biological expression and are multiplied by 5 for electronic correspondence. The time constant (τ) is the same in electronical and biological fields. The conductance (gmax) is in Siemens in biological expression and multiplied by 10 in its electronic counterpart. m is a probability (unitless) in biological model and it is a current (Ampere) in electronic. p and q are integers in both electronic and biological expressions.

Figure 4 .

 4 Figure 4. ASIC hierarchy and related neuronal computation blocks

Figure 5 .

 5 Figure 5. Schematic view of sigmoid Cell level IPThe first and second sub-blocks are finally described by the following functional equations:

Figure 6 .

 6 Figure 6. Modelling views

Figure 7 .

 7 Figure 7. DC current response of Sigmoid cell parametered by Voffset These responses are compared to the ideal response of the sigmoidal function (simulation with Functional view) by measuring the mean square error.

Figure 8 .

 8 Figure 8. Mean square error of Sigmoid block (schematic view compared to ideal fonctional view) output current, depending on Voffset; numbers 1 to 20 correspond to incremented values of Voffset from 1.5V to 3.5V.

Fig. 9

 9 gives an illustration of the Monte-Carlo simulation (100 samples) of the response of Sigmoid IP (I sig ), for V offset = 1.5 V, lower bound of the preliminary validity range. If the distribution of I sig values results in more than 5% out of the interval [0.95*Targeted value , 1.05*Targeted value], we reduce the validity range of the used parameter (in this Fig. 9, V offset ).

Figure 9 .

 9 Figure 9. MonteCarlo simulation of the current output Sigmoid IP with parameter Voffset = 1.5 V (100 samples). Targeted value is 20,40µA (theoritical value), standard deviation is 304,34nA, and all values are inside the tolerance interval [0,95*20,40µA ; 1,05*20,40µA].

Figure 10 .

 10 Figure 10. Principle of an IP-based design flow

Figure 11 .

 11 Figure 11. Exploration algorithm used to look for an IP in the database

Figure 13 .

 13 Figure 13. Multi-level abstraction simulation results of one ASIC setting with 5 neurons

  Application of IP-based Analog Platforms in the design of Neuromimetic Integrated Circuits Timothée Levi, Noëlle Lewis Member IEEE, Jean Tomas, and Sylvie Renaud Member IEEE

TABLE I TYPICAL

 I SPECIFICATIONS OF AN ASIC WITH A SMALL NETWORK OF 2 NEURONS

		Voffset_act	Vslope_act	Voffset_inact	Vslope_inact	τ _act	τ _inact	Vequi	gmax
	Sodium	-39 mV	8,55 mV	-47 mV	-7.3 mV	0.03 ms	0.25 ms	40 mV	0.7 µS
	Potassium	-27 mV	12,6 mV			3 ms		-80 mV	1.4 µS
	Leak							50 mV	0.5 µS
	Synapse					4 ms		60 mV	0.3 µS
	Synapse					5 ms		50 mV	0.2 µS
		Voffset_act	Vslope_act	Voffset_inact	Vslope_inact	τ _act	τ _inact	Vequi	gmax
	Sodium	-39 mV	8.55 mV	-47 mV	-6,6 mV	0.03 ms	0.25 ms	40 mV	0.7 µS
	Potassium	-27 mV	12.6 mV			3 ms		-80 mV	1.4 µS
	Slow conductance	-55 mV	10.4 mV	-38 mV	-20 mV	6 ms	6 ms	-100 mV	0.1 µS
	Leak							50 mV	0.33 µS
	Synapse					6 ms		10 mV	0.1 µS

  , for kinetic IP the time constant range have to be [τ, 50 τ] and for output IP the transconductance range [g max , 50 g max ].

His research interests include design of analog and mixed signal circuits and systems dedicated to neuromorphic applications. He has also authored and co-authored more than 50 peer-review publications.

Currently, he is Associate Professor at Université Bordeaux 1 in IMS Laboratory (UMR 5218 CNRS / Université de Bordeaux).

Pr. Sylvie Renaud graduated in electronic engineering (MSc) in Supelec (Paris-France) in 1986. She received her PhD in Physics at the University of Bordeaux (France) in 1990, and her HDR (Research Habilitation) in 2001. After a post-doctoral stay at Brandeis University (MA, USA) in 1991_1992, she was appointed as an Assistant-Professor, then Professor in ENSEIRB Bordeaux (National Engineering School) where she was recently appointed as Research Board Director in the Institut Polytechnique de Bordeaux.

She created in 1994 the « Engineering of Neuromorphic Systems » group in IMS-Labs (Univ. Bordeaux, CNRS, ENSEIRB), and now heads the BioElectronics group with 12 permanent researchers. Her research interests are: analog and mixed neuromorphic VLSI; real-time hardware simulation platforms of spiking neural networks; hybrid systems interfacing living and artificial neurons; analog ASICs for biological signal conditioning and events detection; active VLSI implants for neurodegenerative diseases and diabetes; closed-loop living-artificial systems. She authored and co-authored more than 50 reviewed international articles and communications.

Prof Renaud is an expert for the EU commission on FET and ICT calls, and for NS-NIH on CRCNS calls. She is a reviewer for IEEE journals and conferences since 1997 and organizes special Sessions, Tutorials and workshops in IEEE conferences on a regular basis.


P Leblay

J.-F F Henry
email: jf.henry@univ-reims.fr

D Caron

Denis Leducq

André Bontemps
email: andre.bontemps@cea.fr

L Fournaison

IR THERMOGRAPHY MEASUREMENT OF CONVECTIVE HEAT TRANSFER COEFFICIENTS WITH PERIODIC EXCITATION BY JOULE EFFECT APPLIED TO THE ESTIMATION OF COMPACT HEAT EXCHANGER EFFICIENCY

come

IR Thermography measurement of convective heat transfer coefficients with periodic excitation by Joule

effect applied to the estimation of compact heat exchanger efficiency

INTRODUCTION

Brazed aluminium heat exchangers are composed of flat tubes on the refrigerant side and louver fins on the air side. The flat tubes are grouped within a header, to use the heat exchanger in a parallel flow configuration. These exchangers have some advantages compared to the heat exchangers with round tubes, such as charge reduction and higher heat transfer efficiency. But a reduced diameter implies a great number of parallel circuits [START_REF] Hrnjak | Microchannel heat exchangers as a design option for charge reduction in NH3 and HC systems[END_REF]. Conventional distributors are thus not suitable to small-channel heat exchangers. Increasing the number of tubes and reducing the hydraulic diameter implies a refrigerant distribution much more penalizing for these exchangers than for round tube heat exchangers. Indeed, according to [START_REF] Kulkarni | Header design tradeoffs in microchannel evaporators[END_REF], an uneven distribution may result in a performance reduction up to 20 %. The major influence of geometrical parameters on distribution [START_REF] Webb | Two-phase flow distribution to tubes of parallel flow air-cooled heat exchangers[END_REF] implies disposing of a non intrusive measurement method respecting the heat exchanger geometry. Indeed, investigating twophase distribution in a small-channel heat exchanger requires an appropriate measurement technique. Typically, distribution between channels is studied in terms of flow rate of each phase in every tube. [START_REF] Bernoux | Etude de la distribution d'un mélange liquide-vapeur à l'entrée des échangeurs de chaleur[END_REF] and later [START_REF] Ahmad | General characteristics of two-phase flow distribution in a compact heat exchanger[END_REF] have thus equipped every tube with its own flowmeter and condenser to measure the distribution of two-phase R-113 and HFE-7100 in the whole exchanger. This protocol has also been used by [START_REF] Poggi | Experimental and numerical study of the distribution of a single-phase flow in a small channel heat exchanger[END_REF] for two-phase HFE-7100. [START_REF] Watanabe | General characteristics of twophase flow distribution in a multipass tube[END_REF] and later Cho andCho (2006, 2004) used a variant of this system, with separators of liquid and gas followed by liquid and gas flowmeters. Such a system, even if reliable, can't be easily translated to a typical heat exchanger configuration. Indeed, the influence of the outlet header isn't taken into account in this case. Moreover, this method is reasonably adapted for exchanger with only a few channels, considering the need to dispose of one or two flowmeters per channel.

2

Investigations of Kim and Lee (2006) stand on the same principle. The heat exchanger was separated at its middle to include a derivation system. With this modification, distribution of two-phase fluid can be estimated by measuring flow rate and quality at each channel outlet successively. [START_REF] Hwang | Refrigerant distribution in minichannel evaporator manifolds[END_REF] used a similar system to measure the distribution of two-phase R-410a. This protocol takes into account the effect generated by the outlet header. However, this system requires a pressure drop measurement to avoid the influence of sampling on distribution. For liquid distribution, O'halloran et al. (2004) used PIV (Particle Image Velocimetry) to study the distribution. This method provides good results but was not suitable for two-phase measurement. Distribution was also estimated by measuring the evaporator air temperature contours. Shi et al. (2011) studied the influence of geometry on the distribution. Evaporator air temperature contours was measured with thermocouples and authors relied on these data to support their observations. IR 1 thermography was used by Sa et al. (2003) to provide information on two-phase distribution. Transient measurements were performed with various exchanger configurations. Knowledge of transient temperature distribution, together with quantitative data such as heat transfer rate and pressure drop, were used to select the best configuration. The present paper focuses on the development of a method designed to measure the efficiency of heat exchanger. The measurement of heat transfer coefficient allows qualifying the efficiency of the distribution. The method is based on an infrared thermography measurement of the flat tubes surface temperature under a periodic heat flux by Joule effect, and a mathematical model to deduce the heat transfer coefficient.

MEASUREMENT PRINCIPLE

The objective of the measurement performed in the GRESPI laboratory is to estimate heat transfer coefficients between the flowing water and the inlet wall of a pipe. The studied exchanger was composed of seven multiport flat tubes. Each tube was heated by Joule effect with a periodic excitation. The heat flux was measured with an ammeter and voltmeters, and the oscillation of the outside surface temperature of the tubes with an IR camera. Heat flux and temperature amplitude were used as entry variables in a model to finally estimate the heat transfer coefficients. Tubes were electrically heated by a sinusoidal wave DC generator which output voltage was modulated at low frequency (f = 0.05 Hz in this study). Since the tube acts as a pure resistance, the current is itself at the same frequency as the voltage and in phase with it. Their expression is given in eq. (1).

) cos( t U U U a m ω + = ) cos( t I I I a m ω + = (1)
The power dissipated by Joule effect in the tubes is equal to the product I U and therefore has three components: a continuous one, one at the excitation frequency f and one at a frequency twice that of the source. The model takes into account these components.

MODEL DEVELOPPED

The model developed assimilates the flat tube to a wall, as presented in Figure 1. Thanks to the symmetry condition induced by the geometry, only half the flat tube was considered. The relation between the periodic heating energy and the temperature oscillations of the outside wall is composed of the heat conduction equation inside the wall and of the boundary conditions. These conditions are a convective heat flux imposed on the inner surface of the tube by the fluid flow and a condition of adiabaticity on the outer surface. Indeed, heat losses by external convection and radiation are negligible compared to the heat flux transferred to the fluid and will be neglected here. To take into account the influence of the fins formed by small-channel separations, two different surfaces were added to the model. Surfaces 1 s and 2 s were considered respectively for conduction and for convection. Considering the low heat flux provided by the power supply, oscillating from 5 W to 35 W, a second assumption is a constant fluid temperature. The third hypothesis concerns the independence of the thermodynamic properties of the material and of the convection coefficient to the temperature. The fourth and last hypothesis is a 1-D temperature variation. Heat transfers in any other direction than the x axis are then neglected.

The system to solve, composed of the energy equation and boundary conditions, is given in eq. ( 2).

( ) ( ) ( ) ( ) ( ) ( )            = ∂ ∂ - = - = ∂ ∂ - = - = ∂ ∂ - ∂ ∂ = = 0 x T k 0 x T T s h x T s k e x k q t T a 1 x T 0 x t , x w in , f t , e w 2 e x t , x w 1 ) t ( t , x w 2 t , x w 2 & (2)
Temperature, like power, has three components: a continuous one, one at the excitation frequency, and one at a frequency twice the excitation frequency. By defining eq. ( 3), ( )

in , f ) t , x ( w ) t , x ( T T - = θ (3)
and assuming a periodic established state, we obtain eq. ( 4)

( ) ( ) ( ) ( ) ϕ ω θ ϕ ω θ θ θ ω ω + + + + = t 2 j exp t j exp ) x ( 2 ) x ( ) x ( c ) t , x ( (4) and (5) ( ) ( ) t 2 j exp q t j exp q q q 2 c ) t ( ω ω ω ω & & & & + + = (5)
where ϕ is the phase shift between the temperature and the heat source. The resolution of the system provides the expression of ( )

ϕ θ ω j exp ) x ( , w
, given in eq. ( 6) and [START_REF] Watanabe | General characteristics of twophase flow distribution in a multipass tube[END_REF].

( ) ( ) ( ) ( )               +         - - = e m ch e m sh s s h m k x m ch c m V k m 1 1 k m q j exp 2 1 f , p f 2 2 ) x ( , w ω ω ω ω ω ω ω ω ϕ θ & & (6) with a j m ω ω = (7)
The same resolution was applied to the system at twice the excitation frequency to obtain the expression of ( ) 2. Knowing eq. ( 8),

ϕ θ ω j exp ) r (
h s 2 s 1 x 0 e ) (t q & p c ρ k 4 ( ) ( ) ϕ θ ϕ θ θ ω ω j exp j exp ) x ( 2 ) x ( ) x ( + = (8)
an evaluation of the h value is finally obtained by minimizing ε such as given in eq. ( 9).

EXPERIMENTAL FACILITY

The exchanger in which the heat transfer coefficient measurements were carried out was composed of two headers and seven multiport flat tubes. Both headers were acrylic round tubes of 2.1 cm diameter. They were transparent to allow flow pattern visualization. The tubes were made of aluminium and their geometry is presented in Figure 2. The tubes were connected to the headers with a pitch of 1 cm and with an intrusion depth of 1 cm. The exchanger itself is positioned to be supplied in a vertically downward way. The two main devices needed to estimate heat transfer coefficients were a power supply to generate periodic excitation by Joule effect and a scanning device to monitor and measure the surface temperature. A length of 30 cm was thus heated by Joule effect at a frequency of 0.05 Hz. This effect was located between electrodes connected to the power supply with copper cables. To supply the complete exchanger, tubes were connected in series with copper electrodes, as presented in Figure 3. A clamp ammeter and voltmeters were connected to a data logger to measure respectively electric current in the exchanger and voltage in each tube. points in 200 seconds and thus 10 periods. The tube external surface was painted in black in order to increase and homogenize their emissivity. The area observed by the camera was about 20 cm long and was located in the middle of the area heated by Joule effect. The area considered for calculation, presented in Figure 4, is a part of each tube that is about 1.2 cm wide and 2.4 cm high. To measure the temperature evolution of the complete exchanger, the thermographic camera was inclined with an angle of 45 °. The hydraulic circuit is presented in Figure 5. Air and water were used as working fluid. The two fluids were mixed through a static mixer to have an homogeneous mixture. Water and air flow rate were controlled by valves. Both fluid flow rates were measured by a corresponding flowmeter. Total inlet mass flux and quality of air-water ranged from 29 kg.m -2 .s -1 to 116 kg.m -2 .s -1 and 10 % to 70 %, respectively. A thermocouple, located at the outlet of the exchanger, measured the water temperature during experiments in order to check that the water temperature remained constant during the test. The tank temperature was controlled using a thermocouple connected to the data logger.

Corresponding author: P. Leblay Phone: + 33 (0)1 40 96 65 78 E-mail address: Patrick.leblay@irstea.fr 6

EXPERIMENTAL RESULTS

In studies focused on the measurement of liquid and gas distribution, the flow rate in each channel is evaluated in terms of liquid and gas flow ratio in each channel. The flow ratio * i m & is the ratio of the flow rate of the phase considered i m & inside the tube number i over the mean flow rate of this phase. It is given in eq. ( 10.

N m m m N 1 j j i * i ∑ = = & & & (10)
Similarly, to compare the distribution of heat transfer coefficients obtained for various flow rates and quality, results are presented here in terms of Nusselt ratio. The Nusselt ratio * i Nu of the tube number i is the ratio of the Nusselt number measured i Nu on the tube i over the mean Nusselt number calculated for all the tubes, given by eq. ( 11.

N Nu Nu Nu N 1 j j i * i ∑ = = (11)
We thus have a relative comparison of the heat transfer obtained along the header, with a value of 1 indicating a homogeneous distribution. The effect of mass flux on heat transfer distribution for a vertical downward header is presented in Figure 6. It appears that, whatever the mass flux, the last channels are characterized by greater heat transfer. Heat transfers are almost evenly distributed for the tubes one to five. The effect of quality on distribution of heat transfer is presented in Figure 8. It appears that, for a low quality (x = 0.10%), the latest tubes are oversupplied at the expense of the tubes 2 to 5. For an intermediate quality, the distribution of heat exchange is homogeneous for the five first tubes and sharply increases for the last two. Finally, for a high quality (x = 0.70), the distribution of heat exchange is homogeneous for the four first tubes, falling for the fifth and increasing for the last two. Results obtained by [START_REF] Poggi | Experimental and numerical study of the distribution of a single-phase flow in a small channel heat exchanger[END_REF] on the influence of quality on distribution are presented in Figure 9. More pronounced effect is observed in this study. Indeed, increasing quality makes the liquid supplying of all the tubes reduced in favour of the last ones. For a lower quality, the height of liquid accumulated at the bottom of the header is more important. Gas distribution, while relatively homogeneous, improves with the increase of the quality. The difference between the two results regarding the influence of this parameter may be related to the fluid used. Indeed, the density ratio between phases is much smaller in the case of an air-water mixture than in the case of HFE-7100 (0.0012 and 0.0070 respectively). Air velocity is much higher than water velocity. Some liquid particles are carried away by the air passing through the first tubes. In the case of HFE-7100, this phenomenon is less important. Moreover, the heat exchanger used by [START_REF] Poggi | Experimental and numerical study of the distribution of a single-phase flow in a small channel heat exchanger[END_REF] did not include outlet header. Thus, the dragged effect is increased in our case, the outlet header generating a suction phenomenon.

CONCLUSION

A method has been developed to measure the convective heat transfer coefficient in a tube. This method is based on a modulated heat flux generated by Joule effect. In this way, the measurement of the amplitude of the tube outside wall temperature with an IR thermographic camera allows to determine internal heat transfer coefficients through a simple analytical model or by using commercial software. The simplicity of the model allows appliance to more complex shaped tubes. This flexibility makes it a perfect tool for controlling series of elements with a similar shape. This method has several advantages. First, it is a non-intrusive measurement method. It enables heat transfer differences to be estimated without requiring knowledge of the flow rate, temperature or properties of the fluid. Moreover, it does not require a high heat flux, thus avoiding strong perturbation of the fluid properties. The use of infrared thermography allowed us measuring heat transfer on several tubes connected in parallel. In this way, the heat transfer distribution over the entire surface of a heat exchanger could be analyzed. Among insights, lock-in thermography could be an additional tool. In this way, the thermograms could be treated using a synchronous detection algorithm to obtain complete maps of amplitude and phase. These can then be correlated with exchange coefficient maps.

ACKNOWLEDGEMENTS

This work has been supported by the Cetim foundation as part of the research project "Two Phase Flow Distribution in a Compact Heat Exchanger".

3 Figure 1 :

 31 Figure 1: Representation of the multiport flat tube and related quantities

  amplitude of the temperature oscillations. So, the knowledge of the properties of the tube material p c , k , ρ , the excitation frequency f , the power densities ω q & and ω 2 determine the convective heat transfer coefficient h .

Figure 2 :

 2 Figure 2: Cross-sectional view of the multiport flat tube (unit: mm)

Figure 3 :

 3 Figure 3: Electrical assembly

5

 5

Figure 4 :

 4 Figure 4 : Area considered

Figure 5 :

 5 Figure 5: Hydraulic circuit

Figure 6 :Figure 7 :

 67 Figure 6: Effect of mass flux on Nusselt number distribution along the header for air-water

Figure 8 :

 8 Figure 8: Effect of quality on Nusselt number distribution along the header for air-water

9 :

 9 Effect of quality on flow distribution of liquid (a) and gas (b) along the header

2 =

 2 (rad.s -1 )

CemOA : archive ouverte d'Irstea / Cemagref


P Leblay

J.-F Henry
email: jf.henry@univ-reims.fr

D Caron

D Leducq

A Bontemps
email: andre.bontemps@cea.fr

L Fournaison

Infrared Thermography applied to measurement of Heat transfer coefficient of water in a pipe heated by Joule effect

Keywords: InfraRed Thermography, Naples, ITA, 11-14 june 2012

A methodology has been developed based on periodic excitation by Joule effect and infrared thermography measurement. It has been applied to measure heat transfer coefficients of water flowing in a round tube and in a multiport-flat tube. Models were developed to deduce heat transfer coefficient from wall temperature amplitude and heat flux measurement. For the round tube and for the multiport flat tubes, Reynolds number investigated ranges respectively from 2000 to 14000 and from 800 to 10000 and heat flux from 5 W to 29 W and from 10 W to 70 W. The good agreement between experimental and theoretical results has demonstrated the reliability of the methodology. This methodology also present the advantage to require a low heat flux, is not intrusive and fluid independant.

twice the excitation angular frequency

Brazed aluminium heat exchangers are composed of flat tubes on the refrigerant side and louver fins on the air side. The flat tubes are grouped within a header, to use the heat exchanger in a parallel flow configuration. These exchangers have some advantages compared to the heat exchangers with round tube, such as charge reduction and higher heat transfer coefficient.

But, according to Hrnjak [START_REF] Hrnjak | Microchannel heat exchangers as a design option for charge reduction in NH3 and HC systems[END_REF], reduced diameter implies a great number of parallel circuits. Conventional distributors are thus not suitable to small-channel heat exchangers. As a consequence, the refrigerant distribution is much more penalizing for these exchangers than for round tube heat exchangers. Indeed, according to Kulkarni et al. [START_REF] Kulkarni | Header design tradeoffs in microchannel evaporators[END_REF], an uneven distribution may result in a performance reduction up to 20 %.

Efficiency of heat transfer distribution is a direct consequence of refrigerant distribution at header inlet. Measurement of heat transfer coefficients would thus allow estimating the quality of this distribution. Infrared (IR) thermography is a reliable and non-intrusive technique for such measurements.

IR measurement of convective heat transfer usually involves steady state heating and the measurement of external temperatures used as boundary conditions to solve an inverse heat conduction problem. Transient techniques (single blow, impulse or periodic) are also efficient experimental methods to measure convective heat flux in transient conditions. The subject of the present study is the IR thermography methodology based on periodic temperature fluctuations to evaluate convective heat transfer coefficients.

Hausen [START_REF] Hausen | Wärmeübertragung im Gegenstrom, Gleichstrom und Kreuzstrom[END_REF] first developed this method, based on the measurement of phase shift and temperature amplitude. He applied this method to evaluate heat transfer coefficients on a regenerator.

Later, Roetzel et al. [START_REF] Roetzel | Measurement of the heat transfer coefficient in plate heat exchangers using a temperature oscillation technique[END_REF] applied a similar method, developed in Roetzel et al. [START_REF] Roetzel | Measurement of heat transfer coefficient and axial dispersion coefficient using temperature oscillations[END_REF], to characterize the transfer coefficients and dispersion in plate heat exchangers. Water was used as working fluid. A steady state method, already proven, was also applied for the sole purpose of comparison for the heat transfer measurement. Temperature oscillation was measured at the inlet and the outlet of the exchanger. The phase shift between these two temperatures and the ratio of the amplitude were used. A mathematical model relates the amplitude and the phase shift to the distribution of residence time in the exchanger and the heat transfer such that:

0 ) , ( 0 ) , ( exp exp =
- = - ϕ ϕ θ θ NTU Pe NTU Pe th th (1)
The results showed a good agreement between the two methods for low Reynolds numbers. However, for higher Reynolds numbers, the results obtained with the transient technique appeared to be higher than those obtained with the steady-state method. Two possible explanations for this difference were proposed. Firstly, for a high Reynolds number, the period used for the transient method was comparable with the time delay of pneumatic valves and the flow fluctuation effect. Secondly, the steady state method did not take dispersion into account.

Recently, Freund and Kabelac [START_REF] Freund | Measurement of local convective heat transfer coefficients with temperature oscillation IR Thermography and radiant heating[END_REF] developed a three-dimensional model which allows a rapid assessment of the distribution of heat transfer coefficients. The heat transfer coefficients are deduced from the phase shift between the heat source, usually a laser, and the temperature response of the wall. Freund et al. [START_REF] Freund | Local heat transfer coefficients in spray cooling systems measured with temperature oscillation IR thermography[END_REF] and Freund and Kabelac [START_REF] Freund | Investigation of local heat transfer coefficients in plate heat exchangers with temperature oscillation IR thermography and CFD[END_REF] then applied this method to measure the distribution of convection coefficients on a plate cooled by jet impingement of air and on the surface of a plate heat exchanger. They obtained encouraging results, but specified that their model could not be transposed to more complex shapes than cylinders and plates.

As noted by Freund [START_REF] Freund | Local Heat Transfer Coefficients Measured with Temperature Oscillation IR Thermography[END_REF], heat transfer estimation requires an accurate measurement of the phase shift between heat flux and temperature response. This implies using hardware that enables the time gap between heat flux and temperature measurement to be precisely determined. Without such equipment and to avoid errors due to synchronisation of the device, temperature oscillation measurement is not sufficient to determine the heat transfer coefficient.

The present study focuses on the IR measurement of convective heat transfer coefficients in a horizontal pipe by temperature oscillations. The heating was generated here by Joule effect to maximize the accuracy of the measurement. The parameter considered for the estimation of the heat transfer coefficient was the temperature amplitude measured on the outside wall by infrared thermography.

The method was first applied to a round tube. A heat transfer model of the system was developed to correlate the heat transfer coefficient and the temperature amplitude. Considering the efficiency of the method for a round tube, it was then applied to a multiport flat tube. An analytical model was developed, and the results were compared to a resolution with the commercial software COMSOL and to theoretical values.

Measurement principle

The objective of measurement, performed in the GRESPI laboratory of Reims, was to estimate heat transfer coefficients between the flowing water and the inlet wall of a pipe. The two geometries have been studied, the round tube and the multiport flat tube. In both cases, the pipe was heated by Joule effect with a periodic excitation. The heat flux was measured with an ammeter and a voltmeter, and the oscillation of the outside surface temperature of the tube with an IR camera. Heat flux and temperature amplitude were used as entry variables in models to estimate heat transfer coefficients for a round tube and for a multiport flat tube.

Considering the temperature, the peak to peak amplitude of the oscillations varied from a few tenths of a degree to more than one degree of magnitude depending on the experimental conditions. For example, for the round tube, a power oscillating from 1.3 W to 11.0 W and a Reynolds number of 9200 induced a temperature amplitude of 0.35 °C. A temperature amplitude of 1.17 °C was reached with a power oscillating from 6.8 W to 18.0 W and a Reynolds number of 2500.

The tube was electrically heated by a sinusoidal wave DC generator which output voltage was modulated at low frequency (f = 0.05 Hz in this study). Since the tube acts as a pure resistance, the current is itself at the same frequency as the voltage and in phase with it.

) cos( t U U U a m ω + = ) cos( t I I I a m ω + = (2)
The power dissipated by Joule effect in the tube is equal to the product I U and therefore has three components: a continuous one, one at the excitation frequency ω and one at a frequency twice that of the source. The model takes into account these components and is described for the two geometries, the flat tube and the round tube.

Model developed for the round tube

The relation between the periodic heating energy and the temperature oscillations for a round tube, as presented in Fig. 1, is composed of the heat conduction equation inside the tube wall and the boundary conditions. These conditions are in this case a convective heat flux imposed on the inner surface of the tube by the fluid flow and a condition of adiabaticity on the outer surface. Heat losses by external convection and radiation are negligible compared to the heat flux transferred to the fluid and will therefore be neglected. Considering the low power provided by the power supply, a second assumption is a constant fluid temperature. The third hypothesis concerns the independence of the thermodynamic properties of the material and of the convection coefficient with respect to the temperature. The fourth and last hypothesis is a 1 D temperature variation. Angular and axial heat transfers are then neglected.

Fig. 1. Representation of the tube and related quantities

The following system of equations has to be solved twice, at the excitation frequency and at twice the excitation frequency. We will not solve the continuous system of equations which does not provide more information except for purposes of comparison. It includes the equation of energy conservation and the boundary conditions:

( )            = ∂ ∂ - = - = ∂ ∂ - = - = ∂ ∂ - ∂ ∂ + ∂ ∂ = = 0 r T k R r T T h r T k R r k q t T a 1 r T r 1 r T o i i R r ) t , r ( w o ) t , R ( w in , f R r ) t , r ( w i ) t ( ) t , r ( w ) t , r ( w 2 ) t , r ( w 2 & (3)
Temperature, like power, has three components: a continuous one, one at the excitation frequency, and one at a frequency twice the excitation frequency. By defining:

( ) in , f ) t , r ( w ) t , r ( T T - = θ (4)
And assuming a periodic established state, we have:

) (t q & f T r o R i R ) t ,
( ) ( ) t 2 j exp q t j exp q q q 2 c ) t ( ω ω + + = (6)
Where ϕ is the phase shift between the temperature and the heat source. The resolution of the system provides the expression of ( )

ϕ θ ω j exp ) r ( : ( ) ( ) ( ) ( ) ( ) [ ] ( ) ( ) ( ) ( ) ( ) ( )               - +       - - + + = i 0 i 1 o 1 i 0 i 1 o 1 0 o 1 0 o 1 2 3 2 ) r ( R m I k m h R m I R m K R m K k m h R m K R m I r m K R m I r m I R m K k m q h k m q j exp ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ϕ θ & & (7) with: a j m ω ω = (8)
In these equations I0, I1, and K0, K1 are the modified Bessel functions of the first and second kind respectively, of order zero and one. The same resolution was applied to the system at twice the excitation frequency to obtain 2. Knowing that:

( ) ϕ θ ω j exp ) r (
( ) ( ) ϕ θ ϕ θ θ ω ω j exp j exp ) r ( 2 ) r ( ) r ( + = (9)
an evaluation of the h value is finally obtained by minimizing ε such that:

) ( exp ) ( o o R R θ θ ε - = (

Models developed for the multiport flat tube

Two models were developed for the multiport flat tube. An analytical 1-D model was first developed to allow sensitivity analysis. This first model was then compared to a 2-D resolution with the commercial software COMSOL.

Assumption 1: Assimilation of the flat tube to a wall

The first model developed considers the flat tube as a wall, as presented in Fig. 2. Thanks to the symmetry condition induced by the geometry, only half the flat tube was considered. The relation between the periodic heating energy and the temperature oscillations of the outside wall, as presented in Fig. 2, is composed of the heat conduction equation inside the wall and the boundary conditions. These conditions are a convective heat flux imposed on the inner surface of the tube by the fluid flow and a condition of adiabaticity on the outer surface. Indeed, heat losses by external convection and radiation are negligible compared to the heat flux transferred to the fluid and will be neglected. To take into account the influence of the fins formed by small-channel separations, two different surfaces were added to the model. Surfaces 1 s and 2 s were considered respectively for conduction and for convection.

Fig. 2. Representation of the multiport flat tube and related quantities

As the heat flux provided is greater than the one delivered for the round tube, water temperature can't be considered constant. Indeed, as presented in Fig. 3, water temperature amplitude was not negligible compared to wall temperature amplitude. Water temperature was thus obtained through a power balance. Considering the low excitation frequency, the hypothesis was done that water phase shift was equal to tube phase shift. The third hypothesis concerns the independence of the thermodynamic properties of the material and of the convection coefficient to the temperature. The fourth and last hypothesis is a 1-D temperature variation. Heat transfers in any other direction than that of the x axis are then neglected. The system to solve, composed of the energy equation and boundary conditions, is thus as follows:

( ) ( ) ( ) ( ) ( ) ( )            = ∂ ∂ - = - = ∂ ∂ - = - = ∂ ∂ - ∂ ∂ = = 0 x T k 0 x T T s h x T s k e x k q t T a 1 x T 0 x t , x w ) t ( f t , e w 2 e x t , x w 1 ) t ( t , x w 2 t , x w 2 & (11)
As for the tube, two systems must be resolved, one at the excitation frequency and the last at a frequency twice the excitation frequency. Considering Eq. ( 4) to [START_REF] Freund | Measurement of local convective heat transfer coefficients with temperature oscillation IR Thermography and radiant heating[END_REF], and with: [START_REF] Edwards | Transfer Processes[END_REF] the power balance for water provides:

( ) ( ) in , f ) t ( f t , x f T T - = θ (12) and ( ) ( ) ( ) ( ) ( ) ϕ ω θ ϕ ω θ θ θ ω ω + + + + = t 2 j exp t j exp 2 , f , f c , f t , x f
f , p f , f c m V q j exp & & ω ω ϕ θ = (14) the expression of ( ) ϕ θ ω j exp ) r ( , w is: ( ) ( ) ( ) ( )               +         - - = e m ch e m sh s s h m k x m ch c m V k m 1 1 k m q j exp 2 1 f , p f 2 2 ) x ( , w ω ω ω ω ω ω ω ω ϕ θ & & (15) with a j m ω ω = (16)
The same resolution was applied to the system at twice the excitation frequency to obtain

( ) ϕ θ ω j exp ) r ( 2 , w
. The resolution is then identical to the case of the cylinder.

Assumption 2: COMSOL

The problem was also solved with COMSOL. The geometry used for 2-D model is presented in Fig. 4, with 536 elements in the mesh. The boundaries noted 2 and 6 are considered insulated due to symmetry conditions. The boundary noted 1 is also considered insulated for the same reasons as previously, i.e. heat losses by external convection and radiation are negligible compared to the heat flux transferred to the fluid. An internal flux is also considered. The thermodynamic properties of the material and of the convection coefficient are considered independent with respect to the temperature.

Fig. 4. Part of the multiport-flat tube considered for the COMSOL resolution

The following system of equations has to be solved, which includes the equation of energy conservation and the boundary conditions: The expression of the internal heat flux and the water temperature are as follow:

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )            = ∇ - = = ∇ - = - = ∇ = - = ∇ - = = ∇ - = = ∇ - = - = ∂ ∂ - ∇ ⋅ ∇ 0 T k H y 0 T k W x ) T T ( h T k h y ) T T ( h T k w x 0 T k 0 y 0 T k 0 x k q t T a 1 T t ,
( ) ( ) ( ) ( ) V t cos I I t cos U U q a m a m ) t ( ω ω + + = & (18) f , p f ) t ( in , f ) t ( f c m V q T T & & ω + = (19)
The theoretical temperature amplitude is then calculated from temperature evolution provided by COMSOL. This value is then compared to the experimental value as for the second and third model up to obtain the value of the heat transfer coefficient.

Experimental facility

The tube in which the heat transfer coefficient measurements were carried out was connected to a hydraulic loop shown in Fig. 6. It was composed of a circulation pump and a water tank with a capacity of 100 l. Both tubes were arranged horizontally. The inner and outer diameters of the copper tube used were 6 mm and 8 mm respectively. The flat tube geometry is presented in Fig. 5. The water flow rate was controlled by a valve and provided Reynolds numbers ranging from 2000 to 14000 for the round tube, from 800 to 10000 for the flat tube. A thermocouple, located at the outlet of the tube, measured the water temperature during experiments in order to check that the water temperature remained constant during the test. The tank temperature was controlled using a thermocouple connected to the data logger.

Fig. 5. Cross-sectional view of the multiport-flat tube (unit: mm)

To generate the periodic heat source and to monitor and measure the temperature oscillations, the experimental facility consisted in a power supply that delivers a periodic Joule effect heating and an infrared scanning device to monitor and measure the temperature of the tube surface, as shown on Fig. 6.

Fig. 6. Hydraulic circuit

In the test section for the round tube the studied area was located one meter from the flow entrance so that the requirement L / D > 40, required to avoid entrance effect, is confirmed (L / D = 200). For the flat tube, which test section is presented in Fig. 7(a), the length of the tube did not allow satisfying this condition. Indeed, the total length of the flat tube, including the transition from flat to round tube, is of 65 cm. The flow pattern was not established at the measurement point.

For both cases, length of 30 cm was heated by Joule effect at a frequency of 0.05 Hz. This effect was located between two electrodes connected to the power supply with copper cables. A clamp ammeter and a voltmeter were connected to the data logger to measure electric current in the tube and voltage between the two electrodes over time. The thermographic camera (Titanium Cedip) measured the temperature on the external surface of the tube at a frequency of 2 Hz. This allowed the capture of 400 points in 200 seconds and thus 10 periods. The external surface of the two tubes was painted in black in order to increase and homogenize their emissivity. The area observed by the camera was about 10 cm long and was located in the middle of the area heated by Joule effect. The area considered for calculation, presented in Fig. 7(b), is a part of the tube that is about 0.5 cm wide and 1 cm high.

Experimental results

The experiments were conducted for a large range of water flow rates. The results obtained experimentally were compared with values obtained from three empirical correlations. For each one, thermodynamic properties were considered at mean temperature, such that:

( ) 2 T T T out in m + = (20)
The correlation of Gnielinski [START_REF] Gnielinski | New Equations for Heat and Mass-Transfer in Turbulent Pipe and Channel Flow[END_REF], adapted to transitional and turbulent flows is given by: ( ) ( ) with L the length of establishment of the flow in the tube before the measurement point, w Pr the value of the Prandtl number at wall temperature and Λ the Darcy friction factor defined by: [START_REF] Kakac | Handbook of Single-Phase Convective Heat Transfer[END_REF]), also used for comparison and valid for transitional and turbulent flows, is defined by: ( ) This correlation was developed for developing laminar flow in the entrance region with constant surface temperature. The results obtained for the round tube are presented in Fig. 8. These results show good agreement between experimental and theoretical results. Results are close to those obtained with the Gnielinski [START_REF] Gnielinski | New Equations for Heat and Mass-Transfer in Turbulent Pipe and Channel Flow[END_REF] correlation for a Reynolds number lower than 10000. Despite the fact that the correlation of Gnielinski is available for a wide range of values, it appears that experimental results are more consistent with the values obtained with the Colburn [START_REF] Colburn | A method of correlating forced convection heat transfer data and a comparison with fluid friction[END_REF] correlation for greater values of number. The correlation of Gnielinski [START_REF] Gnielinski | New Equations for Heat and Mass-Transfer in Turbulent Pipe and Channel Flow[END_REF] is indeed proposed with 20 % of error.

( ) ( ) ] L / D 1 [ ) T ( / ) T (

Fig. 8. Comparison of Nusselt numbers obtained experimentally and from correlations as a function of the Reynolds number for the round tube

These results highlight the efficiency of the method for a configuration widely studied in the literature. Considering multiport flat tube, results are presented in Fig. 9. First of all, the two models provide similar results. Concerning the shape, it appears that flow patterns observed are consistent with theory. Transition between laminar and turbulent begins for a Reynolds number of almost 2000, as predicted by literature. Finally, the two curves, theoretical and experimental, have the same trends. Values obtained experimentally appear lower than those obtained with correlations. This difference can be linked to the geometry. Indeed, correlations were established for round tubes, whereas small-channels are rectangular. Moreover, discrepancies observed for high Reynolds numbers highlight the necessity of increasing heat flux to obtain a better precision for high heat transfer coefficients.

Conclusion

A method has been developed to measure the convective heat transfer coefficient in a tube. This method is based on a modulated heat flux generated by Joule effect. In this way, the measurement of the amplitude of the tube outside wall temperature with an infrared thermographic camera allows internal heat transfer coefficients to be determined through a simple analytical model or by using commercial software. The simplicity of the model allows appliance to more complex shaped tubes. This flexibility makes it a perfect tool for controlling series of elements with a similar shape.

This method has the advantage of being non intrusive. It enables heat transfer differences to be estimated without requiring knowledge of the flow rate, temperature or properties of the fluid. Moreover, it does not require a high heat flux, thus avoiding strong perturbation of the fluid properties.

The use of infrared thermography will allow us measuring heat transfer simultaneously on several tubes connected in parallel. Another insight is to apply lock-in thermography. By this mean, we will have two series of data, phase map and amplitude map, to deduce heat transfer coefficient map.

2 q

 2 amplitude of the temperature oscillations. So, the knowledge of the properties of the tube material p c , k , ρ , the excitation frequency f , the power densities ω q & and ω & and the amplitude of the measured temperature exp ) ( o R θ allow us to determine the convective heat transfer coefficient h .

Fig. 3 .

 3 Fig. 3. Time evolution of wall and fluid temperature

  Quantitative InfraRed Thermography, Naples, ITA, 11-14 june 2012 CemOA : archive ouverte d'Irstea / Cemagref ( )

  Quantitative InfraRed Thermography, Naples, ITA, 11-14 june 2012 CemOA : archive ouverte d'Irstea / Cemagref

  Quantitative InfraRed Thermography, Naples, ITA, 11-14 june 2012

Fig. 7 .

 7 Fig. 7. Test section (a) and area considered (b)

  Hausen (Kakac et al.

Fig. 9 .

 9 Fig. 9. Comparison of Nusselt numbers obtained experimentally and from correlations as a function of the Reynolds number for the multiport flat tube

Table 1 .

 1 Nomenclature

& & & &

QIRT-11th Quantitative InfraRed Thermography, Naples, ITA, 11-14 june 2012 CemOA : archive ouverte d'Irstea / Cemagref

Acknowledgements

This work has been supported by the Cetim foundation as part of the research project "Two Phase Flow Distribution in a Compact Heat Exchanger".