Frank Sill Torres

Rodrigo Possamai Bastos
email: bastos@lirmm.fr

Robust Modular Bulk Built-In Current Sensors for Detection of Transient Faults

Keywords: Built-in current sensors, concurrent detection, fault tolerance, reliability, security, soft errors, transient faults I

Soft error resilience is an increasingly important requirement of integrated circuits realized in CMOS nanometer technologies. Among the several approaches, Bulk Built-in Current Sensors (BBICS) offer a promising solution as they are able to detect particle strikes immediately after its occurrence. Based on this idea we demonstrate a novel modular BBICS (mBBICS) that tackles the main problems of these integrated sensors -area, leakage, and robustness. Simulations based on a predictive nanometer technology indicate competitive response times for high performance applications at the cost of 25 % area overhead and very low power penalty. Thereby, all simulated particle strikes that lead to transient faults could be detected. Additionally reliability analysis proved the robustness of the proposed mBBICS against wide variations of temperature and process parameters.

INTRODUCTION

CMOS is furthermore the most widespread technology for integrated designs as no feasible alternative is in sight to date and in the near future. Driving forces of this leadership are the high miniaturization capability and the reliability of CMOS. Against the background of nanotechnology though, reliability concerns are arising with an alarming pace. The shrinking of technology sizes result in circuits that are susceptible to several errors sources like oxide breakdown [START_REF] Srinivasan | The impact of technology scaling on lifetime reliability[END_REF], parameter variations [START_REF] Unsal | Impact of parameter variations on circuits and microarchitecture[END_REF] or radiation [START_REF] Karnik | Characterization of soft errors caused by single event upsets in cmos processes[END_REF]. In case of the latter, energetic particle can inject electrical charge into sensitive regions of the semiconductor devices and, thus, lead to soft errors. Until the early 2000's, researches on this kind of errors focused mostly on memories and application oriented on avionics and aerospace environment. In current nanometer technologies though, soft error resilience is also required for ground level applications and the combinational parts of the circuits. In recent years, several concurrent error detection and/or correction techniques have been proposed to mitigate the effects of soft errors. This includes the use of debug resources from the scan path [START_REF] Mitra | Robust system design with built-in soft-error resilience[END_REF], the combination of error detecting codes with carry-save arithmetic [START_REF] Wenjing | Fault tolerant arithmetic with applications in nanotechnology based systems[END_REF], and selective redundancy [START_REF] Ruano | A methodology for automatic insertion of selective tmr in digital circuits affected by seus[END_REF]. In contrast to the before mentioned approaches which focus on gate and system level, Bulk Built-In Current Sensors (BBICS) offer a promising solution on transistor level to detect particle strikes immediately after its occurrence [START_REF] Neto | Using bulk built-in current sensors to detect soft errors[END_REF]. The advantages of this technique are zero delay penalty and fast error detection.

On the downside, existing BBICS are prone to temperature and parameter variations and/or require a considerable amount of area [START_REF] Neto | Tbulk-bics: A built-in current sensor robust to process and temperature variations for soft error detection[END_REF]. Further, several known BBICS implementations increase the leakage power dissipation of the monitored circuits.

The aim of this work is to present a new modular BBICS (mBBICS) which operates reliably under wide temperature and process variations, has reasonable area requirements, and has low impact on power dissipation.

The rest of the paper is organized as follows: section 2 gives basic information about the content of this work. Section 3 describes the concept of the proposed sensor while section 4 is related to simulation results and discusses the findings. Finally, section 5 draws the conclusion.

II. FUNDAMENTALS

This section presents preliminary information regarding soft errors, Bulk Built-In Current Sensors (BBICS) and leakage currents in nanometer technologies.

A. Transient Faults in Integrated Circuits

Transient voltage variations during the lifetime of combinational or sequential circuits are defined as transient faults. The first harmful effects of transient faults are soft errors by inverting stored results of system operations (i.e. bit-flips).

Due to the transistor shrinking and the growing communication of confidential data, soft errors can happen today even at ground level by means of perturbation events arisen from environmental or intentional sources. Examples of environment events are alpha particles released by radioactive impurities and more importantly neutrons from cosmic rays [START_REF] Neto | Using bulk built-in current sensors to detect soft errors[END_REF]. On the other hand, intentional perturbation events are usually produced by optical sources such as flashlights or laser beams [START_REF] Neto | Tbulk-bics: A built-in current sensor robust to process and temperature variations for soft error detection[END_REF] that can maliciously induce transient effects on secure circuits like smartcards to retrieve their secret information.

Soft errors and transient faults are also known respectively as single event upsets (SEU) and single event transients (SET) in fault-tolerance-related fields or even as consequences of attacks based on fault injection in security applications.

A transient fault in CMOS circuits is modeled by injecting a double exponential current pulse I fault at the sensitive node. Thereby, the shape of the pulse can be approximated by following equation [START_REF] Srinivasan | Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation[END_REF]:

       f r t t f t t fault f r Q I e e t t (1)
with Q f is the charge collected due to the particle strike, t f means the decay time of the current pulse, and t r labels the time constant for initially establishing the ion track.

B. BICS Detecting Transient Faults

Built-in current sensors (BICS) were initially proposed as a mechanism for detecting large increases in the current I DDQ consumed by a CMOS circuit during its quiescent state, i.e. when the circuit is not switching. The mechanism allows thus testing CMOS circuits against permanent faults [START_REF] Athan | A novel built-in current sensor for iddq testing of deep submicron cmos ics[END_REF]. Further, BICS were also adapted for detecting transient faults in memory cells (i.e. bit-flips) [START_REF] Vargas | Seu-tolerant sram design based on current monitoring[END_REF][START_REF] Gill | An efficient bics design for seus detection and correction in semiconductor memories[END_REF][START_REF] Ndai | A soft error monitor using switching current detection[END_REF]. Recently, efforts were made for monitoring transient faults in combinational logic as well [START_REF] Narsale | Variation-tolerant hierarchical voltage monitoring circuit for soft error detection[END_REF]. All these techniques connect BICS to the power lines (VDD and GND) of the monitored circuit in order to distinguish anomalous transient currents from normal currents. The today's problem is that the amplitude of transient currents induced by radiation effects or fault attacks can have the same order of currents normally generated by switching activities in combinational logic circuits.

Hence, schemes monitoring power lines are very limited for detecting just small range of transient faults.

On the other hand, BICS connected to the bulks of the monitored circuit's transistors are able to detect a wide range of transient faults [START_REF] Neto | Using bulk built-in current sensors to detect soft errors[END_REF][START_REF] Neto | Tbulk-bics: A built-in current sensor robust to process and temperature variations for soft error detection[END_REF]. As Fig. 1(a) and (b) illustrate, Bulk-BICS (BBICS) identify anomalous transient currents I A flowing through the junction between a bulk and a reversely-biased drain of a perturbed transistor (MOSFETs "off" in Fig. 1). BBICS indeed take advantage of two facts: (1) in fault-free scenarios (i.e. I A = 0) the bulk-to-drain (or drain-to-bulk) current I B is negligible even if the MOSFET is switching in function of new input stimuli; and (2) during transient-fault scenarios I A is much higher than the leakage current flowing through the junction. The range of detectable transient faults is easily adjustable by calibrating the size of the transistors that constitute the BBICS. Hence, schemes based on BBICS can be designed to latch a flag of fault indication for abnormal currents within a defined range that represents a risk of resulting in soft errors.

Fig. 1 (c) summarizes the strategy for protecting system's blocks against transient faults in pull-down network by using BBICS. Equivalent strategy must be taken for detecting transient faults in pull-up network as well. Note that in such a strategy the connection between the monitored circuit (e.g. system's block 1) and the BBICS's circuitry (e.g. NMOS-BBICS 1) is done via metal -from the body-ties of each monitored transistor (e.g. T11, T12, and T13) up to the input of the BBICS's circuitry. Thereby, the peak of the anomalous transient current (i.e. the transient fault) is almost not attenuated, ensuring thus an efficient detection. In fact, this very small attenuation is a function of the local distance between the struck zone of the monitored transistor and its body-tie.

C. Leakage

Ideally, CMOS cells draw no current or rather dissipate no power when idle. Unfortunately, this is not true for real cells realized in nanometer technologies. A major impact originates from sub-threshold leakage current I sub which is the current between source and drain when the transistor is in theory cut off. A commonly used approximation of I sub is [START_REF] Hu | Berkeley short channel igfet model[END_REF]:

1             gs th B q V v nk T sub W I a e L (2)
with a 1 is a technology factor, W means the gate width, L labels the gate length, q corresponds to the charge of an electron, n means the sub-threshold swing coefficient, k B is Boltzmann's constant, T labels the operating temperature, V gs is the gate-source voltage, and v th labels the threshold voltage. Further, the threshold voltage can be modeled with [START_REF] Hu | Berkeley short channel igfet model[END_REF]: with v th0 is the zero-bias threshold voltage, γ is the bodybias coefficient, a 2 and a 3 label technology constants, η corresponds to the is Drain Induced Barrier Lowering (DIBL) coefficient, V sb labels the source-bulk voltage, and V ds is the drain-source voltage.

2 3      th th 0 sb ds v v aV aV (3)

III. MODULAR BBICS

In this section, the underlying assumptions as well as the proposed sensor structure is presented.

A. Origination of the approach

Existing BBICS are capable of detecting smallest bulk currents with low response times. Moreover, the approach is much more efficient for dealing with transient faults of long duration and multiple faults without impact on the system's operating frequency. However, common problems are high area effort as well as strong susceptibility to parameter and temperature variations. Further, most available BBICS create an offset on the bulk voltage and, thus, decreases V sb [START_REF] Neto | Tbulk-bics: A built-in current sensor robust to process and temperature variations for soft error detection[END_REF][START_REF] Zhichao | A new bulk built-in current sensing circuit for single-event transient detection[END_REF]. Following from eq. 3, this results in lower threshold voltage and, consequently, in considerably higher sub-threshold leakage (see eq. 2).

Based on these observations, we investigated on solutions for reducing the sensor area, increasing the sensor robustness, and avoiding any voltage offset on the bulk at normal operation (i.e. in fault-free scenarios). Thereby, we identified sharing of functionality between different BBICS as possible solution to reduce the required area overhead. Further, we decided to connect the bulk via a high ohmic transistor in on-state with VDD or GND, respectively, as proposed in [START_REF] Wirth | Bulk built in current sensors for single event transient detection in deep-submicron technologies[END_REF]. Last but not least, we searched a positive feedback structure to increase stability and decrease the sensor response time.

Next, the basic structure and the mode of operation of the proposed modular BBICS, in the following named as mBBICS, is presented. The considerations are related to the sensor for the NMOS bulk. The PMOS version, whose behavior is complementary, is omitted for the sake of simplicity.

B. Basic Structure

Figure 2 depicts the basic structure of the proposed mBBICS which can be divided in two kinds of components: head and tail. Thereby, several heads which are connected to separate bulks share one tail.

A head connects via transistor Nh1 the bulk of the Block Under Test (BUT) with GND. The transistor which has a small W/L ratio is on-state. The bulk is also connected with the gate input of transistor Nh2 whose drain connects to the common signal head NMOS of several heads.

A tail which is similar to an asynchronous latch consists of an inverter realized via the transistors Pt1 and Nt1 whose input is connected with head NMOS . Its output inv out feeds the gates of the devices Pt2 and Nt2, as well as the input of the inverter INV3. The output of the latter is the error signal error NMOS . Further, the output of the inverter formed by Pt2 and Nt2 connects to head NMOS which is also connected to VDD via transistor Pt3 whose gate is controlled by the signal reset.

C. Mode of Operation

In normal operation, i.e. no particle strike occurs, the bulk is at GND level (at  in Figure 3). Further, the net head NMOS has VDD potential and the devices Nh2 in the head modules are in off-state. In case of a particle strike within the BUT, a current flows through transistor Nh1 in the related head module. This results in a voltage drop over Nh1 based on its channel resistance. Consequently, the bulk level increases (at  in Figure 3) and Nh2 starts to conduct leading to a reduction of the head NMOS voltage level (at  in Figure 3).

In the tail block, the decrease of the level of head NMOS activates the inverter formed by Pt1 and Nt1, whereby the state of signal inv out starts to change from GND to VDD (at  in Figure 3). As consequence, transistor Pt2 changes from on-state to off-state, and Nt2 vice versa, which in turn decreases the level of head NMOS and, thus, forces the change of inv out to VDD level. This positive feedback stops when inv out reaches VDD level while head NMOS is at GND level. At the same time, the error signal error NMOS changes to VDD level (at  in Figure 3), which can be processed by higher instances as a flag indicating the occurrence of a transient fault. Consequently, the mBBICS has to be reset after such a process by changing Pt3 shortly into on-state (at  in Figure 3) and, thus, setting the level of head NMOS back to VDD level. It has to be observed that when a flag of fault is latched and during the reset of the mBBICS no new transient fault can be detected. It should be observed that based on the described positive feedback and adequate sizing, which will be explained in the next subsection, it is not required that the head circuit reduces the signal head NMOS below VDD/2. Thus, variations of the head circuit characteristics have lower impact on the functionality of the mBBICS.

D. Sizing

The devices Nh1in the head modules must have a low W/L ratio (i.e. L is longer than W) to guarantee sufficient onresistance. In contrast, the devices Nh2 must be sized with a great W/L ratio to assure that already minor changes of its gatesource voltage V gs_Nh2 result in considerably drain-source current I ds_Nh2 that changes the level of head NMOS . As long as Nh2 is in its sub-threshold region, i.e. V gs_Nh2 is smaller than the threshold voltage of Nh2, I ds_Nh2 is equal to the sub-threshold leakage (see eq. 2). Hereby, the sensor profits from the high sub-threshold leakage of integrated circuits realized in nanometer technologies.

The devices Nt1 and Pt1 in the head module must be sized to support a GND-to-VDD change of the net inv out . Hence, Pt1 should have a high W/L ratio and Nt1 a small one. In a first guess, the transistors Pt2 and Nt2 of the following inverter should be sized to support a VDD-to-GND transition of the signal head NMOS . This is true for Pt2. However, during our analysis of the mBBICS behavior in nanometer technologies we could observe that the leakage through Nt2 is critical as it is discharging the node head NMOS . Therefore, Nt2 should be minimum sized, or even with a greater gate length which considerably reduces the leakage (see also eq. 1). Device Pt3 as well as the inverter can be minimum sized.

IV. RESULTS AND DISCUSSION

This section presents the attained findings and discusses its implications.

A. Simulation Environment

All simulations are based on predictive 16 nm technology models using a VDD of 0.7 V [START_REF] Balijepalli | Compact modeling of carbon nanotube transistor for early stage process-design exploration[END_REF] [START_REF]Predictive Technology Model (PTM)[END_REF]. Each Block Under Test (BUT) consists of six chains of ten inverters, whereas each inverter is sized with a driving strength of two. The bulk of all NMOS devices of a BUT is connected to one head circuit. In contrast, the bulk of the PMOS devices of each BUT is monitored by two head circuits whereas each head is connected to the bulk of the half of the PMOS transistors. This configuration assures equal capacitive load of the monitored PMOS and NMOS bulk. The transistor sizes of the modules of each mBBICS type are listed in Table I.

A particle strike was simulated by a current pulse based on eq. 1 at the output node of the 5 th inverter of the first chain, in the following named sensitive node. All simulation were executed with a rise time t r of 1 ps.

B. Nominal Case

At first, we determined the susceptibility of the BUT to particle strikes. Therefore, we varied the collected charge Q f and the decay time t f (see also eq. 1). Then, we measured the voltage peaks at the sensitive node and the output of the inverter chain. We defined a transient fault TF when the voltage at the sensitive node as well as at the output of the inverter chain crossed VDD/2.

Next, we estimated the ability of the proposed mBBICS sensor to detect TF if the parameters of the applied technology have its nominal values. Based on initial robustness approximations we chose an mBBICS configuration with 6 heads and one tail circuit for the PMOS and NMOS version as reference implementation. The simulations were executed for the same Q f and t f values as in previous susceptibility analysis. The results, including the response time t resp , are shown in Table II whereas  -marks that no TF and no detection occurred, marks that no TF but a detection occurred,  marks that a TF but no detection occurred, and  -marks that a TF and a detection occurred. It can be seen that all transient faults could be detected by the mBBICS. However, for the highest charge a false detection happened for the NMOS as well the PMOS mBBICS. This case is unfavorable though, its impact on the design performance is bearable as it results only a small amount of additional clock cycles. Further follows that the maximum response time is 452 ps for the PMOS mBBICS and 430 ps for the NMOS version.

In the following step we analyzed the response time of the NMOS and PMOS mBBICS in function of the number of heads. Thereby, the simulations were executed for the case Q f = 2 fC, t f = 5 ps which was determined as lower border for the occurrence of a transient fault. The results as well as the area overhead are depicted in Figure 4. The response time varies for the NMOS mBBICS between 157 ps and 598 ps while t resp of the PMOS version is between 240 ps for and 734 ps. Thereby, the response increases with rising number of heads which is based on the increasing capacitive load of the nets head NMOS and head PMOS . Further follows that the maximum supported number of head circuits is 20 for the NMOS mBBICS and 22 for the PMOS version. A higher number leads to false detection without any particle strike. The reason for these false detections is the sub-threshold leakage of the Nh2 transistors in the head circuits.

The area overhead starts with 49 % for mBBICS with only one head circuit and settles at around 21 % for the maximum supported number of heads. Thereby, for mBBICS with six heads the area overhead reduced already to 25 %.

In the last step, we determined the impact on delay and power dissipation in normal operation, i.e. no particle strikes. We estimated the maximum delay of the inverter chains with and without connected mBBICS and could observe no differences. Next, we measured the dynamic power dissipation of the inverter chains for an input signal frequency of 2 GHz. For our reference implementation with 6 heads we could determine a power increase of 0.25 %. Thereby, the average bulk voltage varied only in the range of µV. Hence, it can be concluded that the power increase is solely based on the leakage power dissipation of the mBBICS. Finally, we compared the power dissipation in standby mode and estimated an increase of 3.5 % which is also only based on the leakage of the mBBICS.

C. Robustness Analysis

Robustness is a critical requirement for integrated sensor as variations of all kinds are continuously increasing. Thereby, the main impact on the sensor performance comes from temperature and process variations.

For the first robustness analysis we analyzed the response time as well as the functionality of the mBBICS in function of the temperature. All simulation were executed for the reference configuration with 6 heads, a collected charge of Q f = 2 fC and a decay time of t f = 5 ps. The results are depicted in Figure 5. We could observe that for temperatures below -15 ºC (PMOS mBBICS) and 0 ºC (NMOS mBBICS), respectively, the transient fault could not be detected. Further, the simulations showed that for temperatures above 45 ºC (PMOS mBBICS) and 60 ºC (NMOS mBBICS), respectively, false detection occur. Hence, both mBBICS versions work in a range of 60 ºC. The response time in that range varies for the PMOS mBBICS between 994 ps to 368 ps, and for the NMOS mBBICS between 659 ps and 171 ps. The response time decreases with rising temperature as higher temperatures lead to higher subthreshold leakage I sub [START_REF] Sill | Design of mixed gates for leakage reduction[END_REF]. Hence, the nodes head NMOS and head PMOS can change faster its voltage level. This increase of I sub explains also the false detections at high temperatures.

In the second robustness analysis we executed MonteCarlo simulations utilizing a normal distribution for the varied technology parameters. The expected values µ and the standard deviations  for the modified BSIMv4 parameters are depicted in Table III [START_REF] Hu | Berkeley short channel igfet model[END_REF]. For each configuration we executed 50 MonteCarlo simulations which is recommended amount [START_REF] Synopsys | Hspice® user guide: Simulation and analysis[END_REF].

At first, we determined the functionality and maximum response time in dependence of the collected charge for the reference mBBICS configuration of 6 heads. The results are depicted in Figure 6 and indicate a maximum response time of 1091 ps (PMOS mBBICS) and 778 ps (NMOS mBBICS) each for collected charge of 2 fC. Further, we could observe that all in all simulation all transient faults could be detected and that in no case a false detection occurred if the no particle strike happened. For a collected charge of Q f = 1 fC the NMOS mBBICS showed no false detection while the PMOS mBBICS had 6.

Finally, we determined the functionality and maximum response time for greater amount of chains. Thereby, we could observed that up to 8 heads both mBICCS types never suffered under false detections if no particle strike occurred. The maximum response time increased to 1418 ps (PMOS) and 1384 ps (NMOS).

V. CONCLUSIONS Bulk Built-In Current Sensors (BBICS) offer a promising solution to cope with soft error problems in current nanometer technologies. However, this kind of sensors suffers under its susceptibility to temperature and parameter variations, as well as area and power increase. The proposed modular BBICS applies functional block sharing and positive feedback to mitigate these problems. Simulations with a predictive 16 nm technology indicated that the proposed sensor could detect all injected transition faults with response times below 500 ps for the nominal case, and 1 ns under wide process and temperature variations. This could be achieved with a reasonable area offset of 25 % and very low increase in power dissipation.

Figure 1 .

 1 Figure 1. The two cases of transient faults in a CMOS inverter perturbed by an anomalous current "IA" in (a) and (b), and "K" blocks of a system protected by "K" BBICS in (c)

Figure 2 :

 2 Figure 2: Structure of the proposed mBBICS (version for NMOS bulk)

Figure 3 :

 3 Figure 3: Voltage curves of a mBBICS (NMOS version) detecting a transient fault

Figure 5 :

 5 Figure 5: Response time in function of temperature (6 heads, Q f = 2fC, tf = 5 ps)

TABLE I .

 I TRANSISTOR SIZES IN NM FOR THE APPLIED MBBICS WHEREAS THE 1 ST NUMBER INDICATES THE WIDTH AND THE 2 ND THE LENGTH (THE OMITTED INVERTER INV3 IS MINIMUM SIZED)

		5
	reset	VDD		5
	3 error NMOS 4 GND		4	Name	NMOS	Size	name	PMOS	Size
	inv out		3	Nh1		16 / 160	Ph1	16 / 176
		2			Nh2		160 / 18	Ph2	224 / 18
	1 head NMOS		2	Pt1		64 / 16	Pt1	16 / 160
	0 bulk NMOS	0	1	Nt1 Pt2		16 / 64 16 / 160	Nt1 Pt2	160 / 16 16 / 32
			1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 me →	Nt2		16 / 32	Nt2	16 / 320
					Pt3		16 / 16	Nt3	16 / 16
	lirmm-00715122, version 1 -6 Jul 2012

TABLE II .

 II DETECTION CAPABILITY OF PROPOSED MBBICS (6 HEADS,  -NO TF, NO DETECTION;  -NO TF, DETECTION,  -TF, DETECTION)

			AND RESPONSE TIME T RESP
			PMOS			NMOS
	Q f	t f		t resp		t resp
	1 fC	5 ps		-		-
	2 fC	5 ps		452 ps		430 ps
	3 fC	5 ps		136 ps		76 ps
	4 fC	5 ps		89 ps		50 ps
	1 fC	10 ps		-		-
	2 fC	10 ps		270 ps		210 ps
	3 fC	10 ps		78 ps		62 ps
	4 fC	10 ps		55 ps		43 ps
	1 fC	20 ps		-		-
	2 fC	20 ps		210 ps		175 ps
	3 fC	20 ps		81 ps		70 ps
	4 fC	20 ps		55 ps		50 ps
	Figure 4: Response time and area offset for NMOS and PMOS mBBICS in
		function of the number of heads

TABLE III .

 III EXPECTED VALUES (µ) AND THE STANDARD DEVIATIONS () OF NORMALLY DISTRIBUTED PROCESS PARAMETERS FOR MONTECARLO SIMULATIONS Figure 6: Maximum response time in function of collected charge Q f (6 heads, tf = 5 ps, 50 MonteCarlo simulations)

	Parameter	µ	NMOS		µ	PMOS	
	L int (nm)	1.45		0.0483	1.45	0.0483
		Vth0 (V)	0.47965	1.6E-2	-0.43121	-1.4E-2
		K1	0.4		0.013	0.4	0.013
	µ0 (m²V -1 s -1 )	0.03			1E-3	0.006	2E-4
	NDEP (cm -3 )	7.0E18		2.3E19	5.5E18	1.8E19
		xj (m)	5.0E-9		2.5E-10	5.0E-9	2.5E-10
			MonteCarlo
	Maximum response time	0 ps 200 ps 400 ps 600 ps 800 ps 1000 ps 1200 ps
		1 fC	2 fC		3 fC	4 fC
			Collected Charge Q f
				PMOS	NMOS

This work was sponsored by PRPq/UFMG, FAPEMIG, CAPES, and CNPq.


R Possamai Bastos
email: bastos@lirmm.fr

G Di Natale
email: dinatale@lirmm.fr

M L Flottes
email: flottes@lirmm.fr

B Rouzeyre
email: rouzeyre@lirmm.fr

Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults

Keywords: built-in current sensors, transient faults, soft errors, fault attacks, concurrent error dectection schemes I

This work presents a novel circuit for detecting transient faults in combinational and sequential logic. The detection mechanism features a built-in current sensor connected to the bulks of the monitored logic. The proposed circuit was optimized in terms of power consumption and enhanced with low-power sleep-mode. In addition, a calibration method for bulk built-in current sensors is presented. Overhead results indicate an increase of only 15% in power consumption which represents an improvement of almost factor 6 compared to similar existing sensor.

INTRODUCTION

Higher error resilience is expected from an increasing number of integrated systems while, at the same time, ultradeep submicron technologies make these systems more and more sensitive to natural aging processes or environment sources like radiations from cosmic origin or every day material [START_REF] Karnik | Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes[END_REF]. In addition to these natural phenomena, malicious fault-based attacks can be used to bypass security mechanisms of secure systems and extracting information on confidential data [START_REF] Leveugle | Early Analysis of Fault-Based Attack Effects in Secure Circuits[END_REF]. Both these natural or malicious phenomena on integrated circuits can induce transient effects that provoke bitflips of stored results during the system lifetime.

Until the early 2000's, researches on transient faults focused essentially on memory elements, which were considered the system's most vulnerable circuits. Many concurrent error detection and/or correction mechanisms were proposed to mitigate soft errors induced by transient faults in memory cells. In the last decade, however, more sensitive deep-submicron technologies as well as the increasing demand in terms of digital security have also pushed for the development of countermeasures against transient faults in combinational parts of the circuits. These faults indeed can propagate up to storage elements and thus cause soft errors as well. On the other hand, if the transient fault does not induce any error due to an electrical, logical or latching-window masking effect, its detection is crucial all the same in secure applications since the fault itself reveals an attempt of attack.

Coping with transient faults by using mitigation techniques at different abstraction levels of the design is today the trend in order to efficiently protect integrated systems [3][4]. The idea behind is the avoidance of costly fault-tolerance mechanisms like tripe modular redundancy, taking advantage of cheaper mitigation techniques that ensure satisfactory soft-error coverage for the system's most recurrent operations. This modern strategy is exemplified through system's recovery schemes fired in function of the indication of concurrent error detection (CED) circuitries.

CED mechanisms designed at transistor or gate level guarantee an early detection, as soon as the faults happens, preventing more critical failure scenarios such as the induction and propagation of multiple errors to other clock cycles, stages, or parts of the system. In case of misbehavior, the generated error flag is able to activate, for instance, recovery machines already implemented in modern systems for dealing with branch misprediction [3][4]. Thereby, faulty operation can be repeated in fault-free conditions, adapting the system to perform again its normal computational sequence.

This paper proposes a new low-cost CED scheme that efficiently identifies transient faults. The proposed circuit monitors transistors' bulks of system's blocks such as similar existing bulk built-in current sensor (BBICS) [START_REF] Neto | Using Bulk Built-in Current Sensors to Detect Soft Errors[END_REF] [START_REF] Neto | Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection[END_REF]. Our solution, though, is optimized to satisfy today's need for lowpower transient-fault robust systems. More precisely, to the best of our knowledge, the innovative contributions of this paper are: (1) an optimization of the original BBICS's circuitry [START_REF] Neto | Using Bulk Built-in Current Sensors to Detect Soft Errors[END_REF][6] to achieve reasonable overheads in power consumption;

(2) the introduction of the sleep-mode for BBICS that allows additionally energy savings when the system is on standby; (3) a calibration method defined at design time for BBICS detecting a minimum profile of transient fault.

II. BUILT-IN CURRENT SENSORS DETECTING TRANSIENT

FAULTS

Built-in current sensors (BICS) were initially proposed as a mechanism for detecting large increases in the current I DDQ consumed by a CMOS circuit during its quiescent state, i.e. when the circuit is not switching. The mechanism allows thus testing CMOS circuits against permanent faults [START_REF] Athan | A Novel Built-in Current Sensor for I DDQ Testing of Deep Submicron CMOS ICs[END_REF]. Further, BICS were also adapted for detecting transient faults in memory cells (i.e. bit-flips) [START_REF] Lo | Design of Static CMOS Self-checking Circuits using Built-In Current Sensing[END_REF][9][10] [START_REF] Ndai | A Soft Error Monitor Using Switching Current Detection[END_REF]. Recently, efforts were made for monitoring transient faults in combinational logic as well [START_REF] Narsale | Variation-tolerant hierarchical voltage monitoring circuit for soft error detection[END_REF]. All these techniques connect BICS to the power lines (V DD and GND) of the monitored circuit in order to distinguish anomalous transient currents from normal currents. The today's problem is that the amplitude of transient currents induced by radiation effects or fault attacks can have the same order of currents normally generated by switching activities in combinational logic circuits. Hence, schemes monitoring power lines are very limited for detecting just small range of transient faults.

On the other hand, BICS connected to the bulks of the flowing through the junction between a bulk and a reverselybiased drain of a perturbed transistor (MOSFETs "off" in Fig. 1). BBICS indeed take advantage of two facts:

(1) In fault-free scenarios (i.e. I A = 0) the bulk-to-drain (or drain-to-bulk) current I B is negligible even if the MOSFET is switching in function of new input stimuli; and

(2) During transient-fault scenarios, I A is much higher than the leakage current flowing through the junction.

The range of detectable transient faults is easily adjustable by calibrating the size of the transistors that constitute the BBICS. Hence, schemes based on BBICS can be designed to latch a flag of fault indication for abnormal currents within a defined range that represents a risk of resulting in soft errors.

Fig. 1 (c) summarizes the strategy for protecting system's blocks against transient faults in pull-down network by using BBICS. Equivalent strategy must be taken for detecting transient faults in pull-up network as well. Note that in such a strategy the connection between the monitored circuit (e.g. system's block 1) and the BBICS's circuitry (e.g. NMOS-BBICS 1) is done via metalfrom the body-ties of each monitored transistor (e.g. T11, T12, and T13) up to the input of the BBICS's circuitry. Thereby, the peak of the anomalous transient current (i.e. the transient fault) is almost not attenuated, ensuring thus an efficient detection [START_REF] Wirth | Bulk built in current sensors for single event transient detection in deep-submicron technologies[END_REF]. In fact, this very small attenuation is a function of the local distance between the struck zone of the monitored transistor and its body-tie.

The work in [START_REF] Lisboa | Using Built-in Sensors to Cope with Long Duration Transient Faults in Future Technologies[END_REF] show that area overheads imposed by BBICS's mechanisms for protecting adder circuits can be up to 13.4 % without impact on the system's operating frequency. The costs therefore are considerably smaller than the ones due to classic CED schemes [START_REF] Bastos | How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?[END_REF]. Moreover, BBICS approach is much more efficient for dealing with transient faults of long duration and multiple faults. Nevertheless, the negative issue of existing BBICS is the elevated power consumption to provide high detection sensitivity in ultra-deep submicron technologies [START_REF] Neto | Using Bulk Built-in Current Sensors to Detect Soft Errors[END_REF][6] [START_REF] Zhang | A new bulk bult-in current sensing circuit for single-event transient detection[END_REF].

III. THE PROPOSED BBICS CIRCUIT

The circuit of our sleep-mode improved bulk built-in current sensor is presented in Fig. 2 (a). If the mode of operation is identical to the original BBICS's circuit [START_REF] Neto | Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection[END_REF] shown in Fig. 2 (b), our structure is optimized in such a way that the power consumption could be largely reduced. The NMOS-BBICS's basic structure in Fig. 2 is composed of a latch (transistors 5, 6, 7, and 8) that is responsible for amplifying the anomalous transient currents coming from the bulk "NMOS_Bulk" of the monitored block (e.g. "virtual_ gnd_1" of system's block 1 in Fig. 1 (c)). Higher gain of amplification is obtained by increasing design factors X and Y, hence higher BBICS's sensitivity in detecting transient faults is also determined in terms of these design factors.

BBICS's latch has, moreover, the function of memorizing a flag in case of a transient fault within a defined current rangei.e. "Flag_N" in Fig. 2 keeping V DD level. On the other hand, as

(a) (b) (b) (c) (a)
soon as the flag of fault is processed by higher instances of the system, BBICS's latch must be reset (through the input "Reset" in Fig. 2) in order to detect other transient faults.

Our solution for reducing the static power consumption is introducing transistor 9 such as illustrated in Fig. 2 (a). It allows the utilization of a sleep-mode when the system is left on standby. Transistor 9 is, in this case, set "on", making a less resistive path between the node "NMOS_bulk" and GND. Consequently, the gate-source voltages of transistors 6 and 8 approach to zero, the sub-threshold leakage currents becomes much lower, and thus the static power consumption is drastically reduced. Furthermore, based on simulation experiments, we identified that the costly transistors 9, 10, and 11 from original BBICS in Fig. 2 (b) are not necessary to efficiently and quickly detect short and long duration transient faults in a 32-nm CMOS technology [START_REF]Predictive Technology Model (PTM) Web site[END_REF].

IV. METHOD FOR CALIBRATING BBICS

Previous section defines the two factors named X and Y in Fig. 2 that allows calibrating the amplification of the anomalous transient current, and thus, adjusting the BBICS's sensitivity in detecting transient faults. This section defines a calibration method that searches, at design time and in function of X, for the smallest and the largest Y able to detect a minimum transient-fault profile.

In order to discover these factors Y max and Y min , several electrical-level simulations under a single-transient fault injection are performed. After the set of simulations, if the sensor is designed with a Y lesser than Y min , a flag is not able to be latched, and then a transient fault cannot be detected. Otherwise, if the sensor is designed with a Y greater than Y max , a flag is always latched, and thus a transient fault or any other event is not capable to be identified. This calibration method, therefore, allows finding, for any technology, the optimal BBICS's design factors within a range between Y max and Y min .

V.

RESULTS AND CONCLUSIONS

Transistor-level simulations were performed for comparing our Sleep-mode Improved BBICS named "sibbics_esref2012" with the previous BBICS labelled as "bbics_tns2008". The circuit versions were designed with VDD of 0.9V and in nominal conditions of a 32-nm CMOS technology based on the Predictive Technology Model (PTM) [START_REF]Predictive Technology Model (PTM) Web site[END_REF].

Fig. 3 shows the increase in power consumption of a casestudy circuit (10 chains of 10 inverters) in which all its transistors are monitored by BBICS. The 200 transistors of the chains were designed with minimum size to analyze the technology's smallest capacitances, which represent the most sensitive nodes. Thus, this case-study circuit allows inducing the smallest profiles of transient fault as well as evaluating the minimum sensitivities of the BBICS. We can conclude from Fig. 3 that "bbics_tns2008" versions present large power consumption overhead for any value of X. On the contrary, the proposed "sibbics_esref2012" versions have very lower power consumption, which is additionally reduced during sleep-mode. Note that the results allow defining the minimum and maximum increases since our calibration method searches for the smallest and the largest possible Y.

Figure 1 .

 1 Figure 1. The two cases of transient faults in a CMOS inverter perturbed by an anomalous current "IA" in (a) and (b), and "K" blocks of a system protected by "K" BBICS in (c) monitored circuit's transistors are able to detect a wide range of transient faults [5][6][13]. As Fig. 1 (a) and (b) illustrate, Bulk-BICS (BBICS) identify anomalous transient currents I Aflowing through the junction between a bulk and a reverselybiased drain of a perturbed transistor (MOSFETs "off" in Fig.1). BBICS indeed take advantage of two facts:(1) In fault-free scenarios (i.e. I A = 0) the bulk-to-drain (or drain-to-bulk) current I B is negligible even if the MOSFET is switching in function of new input stimuli; and(2) During transient-fault scenarios, I A is much higher than the leakage current flowing through the junction.The range of detectable transient faults is easily adjustable by calibrating the size of the transistors that constitute the BBICS. Hence, schemes based on BBICS can be designed to latch a flag of fault indication for abnormal currents within a defined range that represents a risk of resulting in soft errors.Fig.1(c) summarizes the strategy for protecting system's blocks against transient faults in pull-down network by using BBICS. Equivalent strategy must be taken for detecting transient faults in pull-up network as well. Note that in such a strategy the connection between the monitored circuit (e.g. system's block 1) and the BBICS's circuitry (e.g. NMOS-BBICS 1) is done via metalfrom the body-ties of each monitored transistor (e.g. T11, T12, and T13) up to the input of the BBICS's circuitry. Thereby, the peak of the anomalous transient current (i.e. the transient fault) is almost not attenuated, ensuring thus an efficient detection[START_REF] Wirth | Bulk built in current sensors for single event transient detection in deep-submicron technologies[END_REF]. In fact, this very small attenuation is a function of the local distance between the struck zone of the monitored transistor and its body-tie.The work in[START_REF] Lisboa | Using Built-in Sensors to Cope with Long Duration Transient Faults in Future Technologies[END_REF] show that area overheads imposed by BBICS's mechanisms for protecting adder circuits can be up to 13.4 % without impact on the system's operating frequency. The costs therefore are considerably smaller than the ones due to classic CED schemes[START_REF] Bastos | How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?[END_REF]. Moreover, BBICS approach is much more efficient for dealing with transient faults of long duration and multiple faults. Nevertheless, the negative issue of existing BBICS is the elevated power consumption to provide high detection sensitivity in ultra-deep submicron technologies[START_REF] Neto | Using Bulk Built-in Current Sensors to Detect Soft Errors[END_REF][6][START_REF] Zhang | A new bulk bult-in current sensing circuit for single-event transient detection[END_REF].

Figure 2 .

 2 Figure 2. The proposed NMOS sleep-mode improved BBICS's circuit "sibbics_esref2012" in (a) and the original NMOS-BBICS version "bbics_tns2008" [6] in (b)

Figure 3 .

 3 Figure 3. Increase in power consumption due to the implementation of NMOS-BICS and PMOS-BICS versions for monitoring a case-study circuit composed of 100 NMOS and 100 PMOS