S Turgis

N Azemard

D Auvergne

Design and Selection of Buffers for Minimum Power-Delay Product

Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives.

Introduction

Driving buffers have been extensively used to control delays on combinatorial paths. Values of tapering factors were determined depending on the performance modeling level and on the physical representation of the cells involved with a common objective: minimizing the delay of paths. In an initial simple theory Lin and Linholm [START_REF] Lin | An optimized output stage for Mos integrated circuits[END_REF] introduced the fixed tapered buffer where the minimum propagation delay time is achieved when the output current drive to output capacitance ratio, in each buffer stage remains constant. Jeager [START_REF] Jaeger | Comments on 'An optimized output stage for MOS integrated circuits[END_REF] showed that the optimum tapering factor was a constant e = 2.72. This result has been then highlighted in the popular books of Mead and Conway [START_REF] Mead | Introduction to VLSI systems[END_REF] and Weste and Eshragian [START_REF] Weste | Principles of CMOS VLSI design[END_REF]. Improvements to this simple model were obtained by including inertial delay of gates [START_REF] Hedenstierna | CMOS circuit speed and buffer optimization[END_REF][START_REF] Li | CMOS tapered buffer[END_REF][START_REF] Prunty | optimum tapered buffer[END_REF] in the so called split capacitor model. Sakurai [START_REF] Sakurai | A unified theory for mixed CMOS/BiCMOS buffer optimization[END_REF] also extended the model using standard cell characterization laws, to define optimal tapering factors. First consideration on power minimization for buffer design have been given by Veendricks [START_REF] Veendrick | short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits[END_REF] in his widely recognized attempt to model the influence of input rise and fall time on short circuit power dissipation. Vemuru [START_REF] Vemuru | Variable Taper CMOS buffer[END_REF] introduced then a variable tapered approach to save area (and dynamic power). Using calibrated analytical equation of delays [START_REF] Deschacht | Explicit formulation of delays on CMOS data path[END_REF] Sha Ma [START_REF] Ma | Energy control and accurate delay estimation in the design of CMOS buffers[END_REF] obtained 20-30% energy saving in designing multistage variable tapered buffers from multivariable Kuhn-Tucker optimization. CAD tools have been proposed to size gates [START_REF] Fishburn | TILOS: A polynomial programming approach to transistor sizing[END_REF][START_REF] Al-Khalili | A module generator for optimized CMOS buffers[END_REF][START_REF] Chen | iCOACH: a circuit optimization aid for CMOS high performance circuits[END_REF], moreover they use numerical programming techniques which are far to be intuitive for designers. An exception is offered in [START_REF] Auvergne | Formal sizing rules of CMOS circuits[END_REF] where a local optimization has been used to define explicit sizing equations for equal rise and fall times on individual gates, resulting in a variable taper implementation with smaller area than that obtained with global methods. The last published work to date addresses the problem of buffer design with local interconnect capacitance [START_REF] Cherkauer | design of tapered buffers with local interconnect capacitance[END_REF] by conserving a constant load capacitance to current drive tapering ratio. A complete treatment of buffers must use an accurate explicit modeling of delay and power, showing clearly up design and process parameters in order to useful in full custom design approach as well as with standard cell methodology.. In the work presented here, we address this important problem of designing tapered buffers, with low power-delay product, using analytical means. This paper is organized as follows. The delay modeling is described in section 2. In section 3 we specify the power component to be considered in the objective function. Using the results obtained in section 2 it is then possible to define a general sizing strategy for buffers, this is given in section 4. Section 5 introduces the concept of load limit for buffer insertion. Design conditions for a minimum power delay product are examined in section 6 and applied to standard cell library in section 7. In section 8, we draw a conclusion and discuss a speed up strategy based on template selection and fanout limit evaluation. The main contributions of this paper include: the general formulation of buffer sizing rule, the definition of buffer insertion limits and the application to the buffer design to satisfy minimum power delay product constraints.

-Delay Modeling

An accurate delay analysis must take into account real cell parameters such as technology, structural complexity, cell environment including total output load and input slope effects. To obtain a better accuracy than the RC model [START_REF] Rubinstein | Signal delay in RC tree networks[END_REF],we used an explicit formulation based on the physical modeling of the switching operations of individual transistors [START_REF] Deschacht | Explicit formulation of delays on CMOS data path[END_REF][START_REF] Auvergne | Input waveform slope effects in CMOS delays[END_REF]. It allows a real delay evaluation of inverters as a linear combination of the step responses of the driving (i-1) and the controled (i) cell (Fig. 1) as follows:

t HL, LH (i) = A . t LHS, HLS (i -1) + t HLS, LHS (i) 1 + α . A t LHS, HLS (i -1) t HLS, LHS (i) ⋅ (1)
where A specifies the voltage range to be considered in evaluating input slope effect (A=1-2.V T /V DD ), α is a slow input ramp correcting factors [START_REF] Auvergne | Input waveform slope effects in CMOS delays[END_REF] and t HLS ,t LHS are the fall and rise step responses of inverters, evaluated for a variation of the output voltage from the output static level to half supply voltage (V DD /2).

INV1 INV2 LOAD (i-1) C load (i) (i+1)
Figure 1: General configuration for a real delay evaluation. These responses can be directly obtained from the mean charge transfer evaluated across the node under consideration and produced by the imbalance current developed in the cell under evaluation, as follows:

t HLS i ( ) = τ ST ⋅ C load 2C N i ( ) ⋅⋅⋅⋅⋅⋅t LHS i ( ) = τ ST ⋅ µ N µ P ⋅ C load 2C P i
( ) (2) for an inverter made up of N (C N ) and P (C P ) transistors, loaded by a capacitance C load , where:

τ st = 2CoxW N L min 2 µ N Cox V cc -V tN ( ) . 8V cc V cc -V tN ( ) 7V cc 2 + 4V tN 2 -12V cc V tN (3)
is the elementary fall time characteristic of the technology, which can easily be found to be the fall time of a sequence of ideal inverters (W N =W P and no parasitic capacitance) with minimum length transistors, loaded by an identical one. The ratios C load /C N , C load /C P can be understood as the ratio of load capacitance to the current drive of each switching structure. Note that τ ST and µ N /µ P (eq. 2), represent speed characteristic parameters of the considered process, and are defined through average values of mobilities and transistor lengths across the full voltage excursion. Their values can be extracted directly from the characterization of specific oscillators or calibrated from simulation of inverters [START_REF] Coll | Process characterization with dynamic test structures[END_REF].

-Power Dissipation in CMOS Buffers

The main component of power to be considered arises during the input signal transition, and consists of two parts, a dynamic dissipation (P d = C load V DD 2 .f) and short circuit one (P SC = I average .V DD ). The dynamic power is the power dissipated to modify the charge content of the capacitive load, it is proportional to the switching frequency and to the load capacitance, and thus depends on the area of the buffers. The short circuit power dissipation is produced by the simultaneous conduction of P and N transistors during the transition of the input signal. As shown in [START_REF] Veendrick | short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits[END_REF][START_REF] Turgis | Explicit evaluation of short circuit power dissipation for CMOS logic structures[END_REF] the ratio of input to output transition times is a good indicator of short circuit power dissipation. For ratio values comparable or lower than unity, which is the objective of buffer design, the short circuit power dissipation can be neglected. Buffer design with fixed or variable tapering factors have been obtained [START_REF] Vemuru | Variable Taper CMOS buffer[END_REF] with short circuit power content lower than 10% of the total power dissipation. As a result, in the definition of our optimizing objectives, we will just consider the dynamic component:

P = f ⋅ V DD 2 ⋅ C REF ⋅ C tot C REF (4)
where C tot is the total value of the load capacitances involved in the design, it includes layout parasitic (diffusion and interconnect) and active loads (C IN (i)= CN(i) + C P (i)) and C REF is the minimum capacitance considered in the design methodology or in the library under consideration.

-Buffer Design

An interesting analyzis of the power dissipation of buffers has been published recently [START_REF] Choi | design of CMOS tapered buffer for minimum power delay product[END_REF]. A comparison of uniform and nonuniform tapered buffers for minimum switching energy, using simple RC model, is given. For an ideal array constituted of N stages, design rules can be summarized as follows:

T N = C load C IN ⋅⋅⋅⋅⋅⋅⋅ N = ln C load C IN ln T (5)
where C load is the load capacitance, C IN the minimum input capacitance and Τ the tapering factor between stages. The output ratio of PMOS to NMOS transistors is assumed to be the same for all stages, and no consideration is given on the symmetry of the responses.

As expected for ideal array, the minimum delay time is obtained for Τ = 2.72 while the minimum power delay product is reached for higher values (Τ =4.25). Considering real structures with layout parasitic capacitances these factors are significantly increased depending on the relative parasitic content. A non uniform tapering factor can only be considered for minimizing the power delay product and results in only few per cent of improvement [START_REF] Choi | design of CMOS tapered buffer for minimum power delay product[END_REF] with respect to uniform implementations. Minimization of the power-delay product can then be resumed (for regular structures, but this can be solved at the layout level) to the search for a minimum of the product active area-delay. Due to the tapering factor values involved in real buffer arrays it appears reasonable to limit the study to a maximum of N=3 stages. In order to take into accouns input controlling ramp [START_REF] Auvergne | Input waveform slope effects in CMOS delays[END_REF], the minimum structure to be considered for design optimization must be constituted of two inverters and this guarantees convexity of delays.

Let us now consider a real two stage bufferconstituted of inverters with identical internal configuration ratios (k=C Pi /C Ni ), the delay expressions become:

θ HL = µ N µ P ⋅ 1 k 1 + k ( )C N 2 + C par 1 C N 1         + (1 + k )C N 3 + C par 2 C N 2         (6)
with equivalent expression for the rising edge. In this equation the delay is expressed in reduced units (θ=2t/(1+A)τ ST ), and the subscrits (1,2,3) specify the rank of the buffer, from the input of the array to the output, respectively, C par ( i ) represents the parasitic output capacitance of each inverter.

As deduced from the posynomial variation of delay equations, constraint on equality of delays between falling and rising edges results in the equality of loading factors (load to drive ratio):

(1 + k )C N 2 + C par 1 C N 1 = (1 + k )C N 3 + C par 2
C N 2 [START_REF] Prunty | optimum tapered buffer[END_REF] which gives:

C N 2 = C par 1 2(1+ k ) -1 + 1 + 4(1 + k )C N 1 n(1 + k )C N 1 + C par 2 [ ] C par 1 2           ( 8
)
where it is assumed that C N 3 is a tapered value of C N1 .Cancellation of the derivative of θ with respect to C Ν 2 cannot be obtained in closed form. Replacing, in eq.6, C N2 by the value given in eq.8, we plot on figure 2 the variation of t HL = t LH for different values of node capacitive load versus the value of the internal configuration ratio. As shown, the minimum delay occurs for the above defined k values belonging to the interval 1.5-3.8, for pure active or parasitic load conditions, as it can directly be obtained from the cancellation of the derivative of θ for these special configurations.

Figure.2: Evolution of the delay of two stage inverters with the content of thecapacitive load versus the internal configuration ratio value (k) .

For the total range of considered loads, sizing with k=1 results in delay degradation ranging from 36% for purely parasitic load to 5% for purely active one. However for buffer array where the parasitic content is not higher than the gate capacitance value of the corresponding transistors [START_REF] Mellah | Standard cell performance modeling[END_REF], the degradation of performance obtained, by selecting identical N and P type transistors to size the inverters, is not much higher than 20% of the minimum available value for a 75% reduction of the transistor area (dynamic power) .

-Buffer Insertion Limit

Next point of interest is to characterize the performance of inverters in terms of load and design parameters, and to define the limit of loads at which any cell can be speed up by insertion of wider inverters. This corresponds to the buffer insertion limit definition for each cell . As previously discussed the general performance equation for inverters can be written as:

Delay = t 0 + K ⋅ C L C IN (9)
where the signification of the different terms can be found from equ. 2. t 0 corresponds to the delay introduced by the inverter layout parasitic capacitance (usually specified as inertial delay), K is characteristic of the gate strength and is defined (equ.8-14) by the sizing strategy of each inverter. Figure 3 illustrates the load limit of an inverter, defined as the fanout limit, at which buffer insertion improves the speed of the cell. Using equ.6 (fig. 4) , we have to satisfy the condition: t(a) > t(b). This results in the straight condition :

t 01 + K 1 . C load C IN 1 > t 01 + K 1 . C IN 2 C IN 1 + t 02 + K 2 . C load C IN 2
C IN 2 = K 2 K 1 C load • C IN 1 ( 11
)
This equation defines the best template satisfying the preceding inequality with an optimal buffer insertion, it defines also the maximum load to be used for a given selection of templates. Solving inequality 10 with 11 gives a direct evaluation of the INV1 load limit for which buffer insertion will speed up the corresponding path. This is obtained from:

T lim it -2 K 2 K 1 • T lim it - t 02 K 1 ≥ 0 ( 12
)
where T l i m i t is more conveniently defined as : T = C load /C IN1 , K 2 and K 1 represent the derating coefficients of equ. 9, characteristics of the gate structure.This value of T limit is absolutely general and can be defined for inverters as well as for gates, as long as performance characterization laws are available. For real inverters, with identical configuration ratios (K 1 = K 2 ), the solution of equation [START_REF] Ma | Energy control and accurate delay estimation in the design of CMOS buffers[END_REF] is:

T lim it = 1 + 1 + t 02 K 1         2 ( 13
)
For real structures, evaluated on full custom cells, t 02 /K 1 can be easily evaluated from equ.14 as: [START_REF] Al-Khalili | A module generator for optimized CMOS buffers[END_REF] showing clearly up design parameters. The buffer insertion condition is then obtained from:

t 02 K 1 = C par 2 C IN 2 = C par 2 C IN 1 1 T lim it
T lim it -2 T lim it - C par 2 C IN 1 • 1 T lim it ≥ 0 (15)
Note that considering average value of delays, this result stands for individual inverters with internal configuration ratios balancing or not fall and rise delay times. From layout modeling considerations it can be easily shown that the ratio C par2 /C IN1 is nearly constant, for transistor widths greater than approximatively 10 times the minimum available length [START_REF] Moraes | Flexible macrocell layout generator[END_REF][START_REF] Mellah | Standard cell performance modeling[END_REF]. Table 1 As shown, T limit value varies from 4 (which corresponds to the result previously obtained by Mead [START_REF] Mead | Introduction to VLSI systems[END_REF]), for an ideal structure or with negligible parasitic content, to 10 for a poorly designed inverter. C par2 /C IN1 = 4 is a typical value of 1µm standard cell library. This limit for buffer insertion, that we defined here, corresponds to the maximum acceptable load on an inverter implementing the lowest delay configuration. This structure appears then as the best candidate to be selected for a minimum power-delay product implementation.

-Design for Minimum Power Delay Product

In this part we define an explicit expression for the powerdelay product of inverters and compare design solutions, for the minimum of this product, to the alternatives investigated in the preceding parts. We show that delays in CMOS structures depend on the ratio of the total load to the drive capacitance of each cell, and that this ratio could be expressed (θ) as a fractional part of a reference capacitance, (C REF ) used as a measure unit for the load. In the same way, we expressed in equ. 4, the total dynamic power as the product of a reference power, P REF = f.V DD 2 .C REF , by the total load capacitance normalized with respect to the reference capacitance C REF , as:

P Dyn = P REF ⋅ C Tot C REF (16)
For an array of 2 inverters this results in:

P Dyn P REF = C load + C par 2 C REF + (1 + k )C N 2 + C par 1 C REF + (1 + k )C N 1 C REF       (17)
The power-delay product can then be obtained as:

θ ∑ • P Dyn P REF = 1 + k [ ] 2 (1 + µ N µ P ⋅ 1 k ) ⋅ ( C IN 2 + C par 1 C IN 1 + C load + C par 2 C IN 2 )         • C Load + C par 2 + C par 1 C IN 1 + ( C IN 2 C IN 1 + 1)         (18)
where C IN1 =(1+k)C N1 defines the reference capacitance. Derivative of this expression with respect to C IN2 gives the optimum tapering factor minimizing the power-delay product. However for this equation no closed form solution is available. and the configuration ratio k=1. As shown, depending on the parasitic content of the array implementation, tapering factors for minimum power delay implementations exhibit a small variation with respect to the parasitic load. Alternatives, with explicit solutions, allow interesting trade offs between speed and power with a few penalty on the power delay product. As shown, an explicit sizing at Tlimit constitutes a good solution for low power implementations.

-Application to Standard Cells

From the previously shown results it appears that if the inverter is the most efficient gate in terms of load derating factor and fanout limit, the cost of each gate selection can be evaluated, on line, in terms of transistor size and fanout factor compared to its limit value (T/T limit ). RISE (ns) FALL (ns) T limit C limit (pF)

C IN (pF) INV1 0.29+ 2.95C L 0.29+ 2.68C L 5.9 0.34 0.06 INV2 0.22+ 1.44C L 0.20+ 1.21C L 5.9 0.65 0.11 INV3 0.25+ 0.95C L 0.22+ 0.76C L 5.9 0.96 0.16 INV4 0.21+ 0.74C L 0.19+ 0.63C L 5.9 1.20 0.2 INV5 0.22+ 0.59C L 0.21+ 0.50C L 5.9 1.50 0.25 Table 3: Performance equations of a 1µm standard cell library. We applied these results to the different inverter cells of an industrial 1µm library, which performance equations are given in Table 3 together with the values of T limit, the maximum load allowed and the input capacitance of each template. These values constitute the first determination, at the cell level, of real buffer insertion limits allowing, by a direct inspection of loading factors on the output nodes, the definition of speed up or reconfiguration strategies as discussed later. In Table 4 we

( 10 )Figure 3 :Figure 4 :

 1034 Figure 3 : Illustration of buffer insertion limits: t 1 , (t 1,4 ) represents the variation of the delay with the load, for one inverter (INV1) or an array of two inverters( INV1,INV4), respectively.

Table 1 :

 1 summarizes the values of Tlimit deduced, from equ.14, for different parasitic content values. Buffer insertion limit of single inverter for different output parasitic capacitance content.

	C par2 /C IN1	0	1	2	4	10
	T limit	4	4.9	5.6	6.8	9.4

Table 2 :

 2 Comparison of the power delay product minima obtained for a two stage array, to the values obtained by sizing the 2nd stage for θmin or at Tlimit. For illustration we represent in Table 2 the variation, with C IN2, of the power-delay product (equ.18) for a configuration of 2 real inverters. The load has been imposed equal to 10 C IN1

	C par1 =C par2	0	1	2	4	6
	C IN2 min P.θ	2.6	2.7	2.8	3	3.2
	Τ= Cload/C ΙΝ2	3.8	3.7	3.6	3.3	3.1
	θ	45	54	63	82	99
	P	27	31	37	44	52
	P.θ	1.2	1.5	2.3	3.6	5.2
	C IN2 min θ	3.2	2.7	2.5	1.9	1.2
	Τ= Cload/C ΙΝ2	3.2	3.7	3.9	5.3	8.5
	θ	44	53	62	80	98
	P	2 8	3 2	3 7	456	5 4
	P.θ	1.3	1.5	2.3	3.9	7
	C IN2 T limit	2.5	2	1.8	1.5	1.3
	Τ= Cload/C ΙΝ2	4	5	5.6	6.8	7.7
	θ	46	60	74	105 137
	P	27	30	34	41	49
	P.θ	1.2	1.6	2.5	4.3	6.7

compare delay, power and power-delay product values for different selection of inverters necessary to feed different loads. Different selection of design choices are investigated: implementation with the optimal number of stages (equ.5), minimum number of stages defined at the minimum delay with the condition T<T limit , with regular tapering factor values, and selection of templates at T limit resulting in irregular tapering factor values. As shown in the Table the last condition results always in minimum power-delay product with very low penalty in delay. Sizing loaded stage at Tlimit always results in non uniform tapering factors with a lower Pθ product. Note that due to the limited choice in the library (discrete variation of the drive capabilities of the cell), some alternatives are equivalent for particular loading conditions. Load (pF)

-Conclusion

Design and sizing of tapered buffers has been considered for minimizing the power-delay product. Rules for buffer insertion have been defined as a function of physical design parameters.

They have been shown to constitute a good alternative for efficient use of inverter templates as well as for searching heavily loaded nodes to apply speed up alternatives. From a general definition of the power-delay product it has been shown that sizing at the buffer insertion limit constitutes an efficient solution for buffer implementation with a minimum power-delay product. Moreover this allows closed form solutions of this problem, which can be completely determined from the performance characterization laws of library cells. Application to a 1µm standard cell library has been given. Comparisons of implementations realized for an optimum buffer stage number, a minimum delay and a selection of templates at T limit , gives evidence of the benefit of this last solution for low power design.