Shahzad Muzaffar
email: shahzad.muzaffar@ku.ac.ae

M Elfadel

Pulsed Decimal Encoding for IoT Single-channel Dynamic Signaling

Keywords: Dynamic Signaling, Single-Channel, Low-Power Communication, Clock and Data Recovery, Internet of Things, Automatic Protocol Configuration, Pulsed-Decimal Communication, Pulsed-Index Communication

Pulsed-Index Communication (PIC) is a recent technique for single-channel communication that is based on the principle of transmitting the indices of only the ON bits as a series of pulse streams. In this paper, a modified version of PIC, called Pulsed Decimal Communication (PDC), is presented that uses the same underlying principle but with key improvements in data rate and reliability. Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It consists of a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step to achieve higher data rates. The segmentation step splits the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step further splits the segments into smaller sub-segments. The complete process significantly reduces the total number of pulses required for transmitting binary data, thus improving the data rate by about 78% . A theoretical model of the PDC protocol is exploited to estimate its data rate and derive the optimum segmentation. Furthermore, PDC is shown to be more reliable than PIC as it eliminates the variations in the number of symbols to be transmitted. The FPGA and ASIC (65nm technology) implementations of PDC show that the low-power operation and small footprint of PIC are preserved. PDC consumes around 25µW of power at a clock frequency of 25M Hz with a gate count of approximately 2150 gates.

Introduction

The basic structure of an Internet of Things (IoT) application is that of a twotier architecture in which the first tier acts as a gateway to the Internet of People (IoP) and has privileged cloud access [START_REF] Muzaffar | A versatile hardware platform for the development and characterization of IoT sensor networks[END_REF] while the second tier is made of the remaining sensing and instrumented devices that are connected to the gateways using simple, low-power physical links and protocols. An example of such twotier architecture can be found in smart homes where a range of electronic devices pertaining to lighting, air-conditioning, security, fire protection, as well as several other common electronic household items, need to be controlled remotely by a smartphone or computer. Some of these devices can be selected as gateways while others remain on the edge to communicate with the gateways. Single-channel protocols are very promising to achieve the connectivity between the first and second tiers as they provide easy and scalable networking options. The main requirements of such protocols are low-power for long battery life, high data rates for reliable transmission during bursts of activity and small form factor for lowering silicon implementation costs. Unfortunately, the existing protocols fail to meet these requirements simultaneously. Protocols providing high data rates, such as WiFi, WLAN, TCP/IP, USB, etc. [START_REF] Shi Dayu | A GEO-Related IoT Applications Platform Based on Google Map[END_REF][START_REF] Byun | Lilliput: Ontology-Based Platform for IoT Social Networks[END_REF][START_REF] Jenq | A Sensor Information Gateway Based on Thing Interaction in IoT-IMS Communication Platform[END_REF], are power-hungry and involve complex controllers to handle two-way communications. On the other hand, low-power protocols such as 1-Wire [START_REF] Maxim | OneWireViewer User's Guide[END_REF], UART [START_REF] Dos Reis Filho | Monolithic data circuit-terminating unit (DCU) for a one-wire vehicle network[END_REF], etc. have low data rates.

To fill up the gap, a new single-channel communication technique, called Pulsed-Index Communication (PIC) has recently been introduced ([6, 7, 10]). Its fundamental novelty lies in the replacement of the transmission of data bits with the transmission of ON bit indices in the packet stream. PIC achieves very low power consumption as it does not require any clock and data recovery (CDR). It also achieves high data rates due to a novel encoding scheme that guarantees error-free decoding even in the presence of clock discrepancies between transmitter and receiver. Additionally, PIC offers a flexible and scalable single-channel networking option for the connectivity of devices in a variety of IoT use cases [START_REF] Muzaffar | A versatile hardware platform for the development and characterization of IoT sensor networks[END_REF]. Though PIC has shown very competitive figures of merit, it does have few disadvantages. One of them is that PIC is prone to complete packet failure, especially when there is a corruption in either the ON bit index number or in the number of ON bit indices. At the root of this packet failure is the fact that two adjacent data words can have vastly different numbers of ON bits or significant differences in the locations of the ON bits.

The objective of this paper is therefore to present a modified PIC protocol that significantly improves packet transmission reliability while maintaining its core idea of transmitting information in the form of pulse streams instead of transmitting data bits. The novel protocol, called Pulsed Decimal Communication (PDC), is based on transmitting a number of pulses which is equal in count to the decimal number represented by the data. For long data words, it is intuitive that such transmission will need a large number of pulses. To reduce the represented decimal number, and hence the pulse count, PDC uses a three-level data segmentation and encoding algorithm with the twofold goals of reducing the decimal value of the bit stream and controlling the number of pulses per data segment. The three levels of the algorithm are:

1. First-level segmentation: This is similar to PIC and is meant to break the data word into smaller data segments to split a number into smaller decimal numbers.

2.

Encoding: This is applied to each segment and is meant to further reduce the number by relocating the ON bits to the least-significant part of the segment. 3. Second-level segmentation or sub-segmentation: This step is applied to each of the encoded segments. Each sub-segment is made of 4 bits. This step is meant to equalise the number of pulses in each first-level segment and thus improve transmission reliability.

Like PIC, PDC is dynamic in that it can accommodate several data rates in the range of 4.87 -12.9 Mb/s with an average of 7.33 Mb/s using a 25-MHz clock.

The main advantage of PDC is that it generates a fixed number of symbols per data word, which results in a simpler and more reliable transmission with respect to packet failures. Other important side advantages of PDC with respect to PIC include a simpler packet header, a more compact decoding, and an improvement of about 78% in data rate. Furthermore, ASIC synthesis of the PDC protocol, using GLOBALFOUNDROES 65nm process, has shown that it is well within the power and area envelopes of PIC. This chapter is a significantly expanded version of [START_REF] Muzaffar | A pulsed decimal technique for single-channel, dynamic signaling for IoT applications[END_REF] with the following important additions:

1. We have introduced a new example to better explain the PDC protocol. See Subsection 3.6] 2. We have added a detailed PDC performance analysis and derived the PDC optimum segment size. See Subsection 4.3. 3. We have added a new treatment of the PDC tolerance to clock jitter and its robustness with respect to clock rate discrepancies between transmitter and receiver. See Subsection 4.5. 4. We have clarified the power management aspects of PDC and commented on the additional power savings that can be achieved through pulse width control. See Subsection 4.7. 5. We have added a discussion on automatic PDC parameter setting at the power-on phase in a realistic master-slave network context. See Subsection 4.6. 6. We have expanded Section 5 on Experimental Results and added several benchmarking charts and tables.

Review of PIC

Pulsed-Index Communication (PIC) [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF] is a recent single-channel protocol that does not require any circuitry for clock and data recovery (CDR). The protocol is based on the concept of a pulsed index where instead of transmitting the bits themselves, only the indices of the ON bits in a data word of length B bits are transmitted. These indices are encoded as pulse counts. The core of the protocol is to encode these indices so as to minimize the number of ON bits, and move them to the Least Significant Bit (LSB) end of the packet. The encoding process includes a segmentation step where the data is broken into N independent segments of size l bits each (i.e., N = B/l). To maximize data rate, PIC uses, on each segment, an encoding combination of bit inversion and/or segment reversion/flipping. This combination is meant to reduce the number of ON bits and decrease their index values so as to lower the number of pulses required to transmit the data bits. To facilitate decoding, flag pulses representing the type of encoding performed (i.e., inversion (1 pulse), reversal (2 pulses), both (3 pulses), or none (4 pulses)) are added to each segment. All the pieces of information including flags, number of indices, and the indices themselves are transmitted in the form of pulse streams. The pulse is characterized by its width which is the number of clock cycles during which it remains high. Within a given packet, segment pulse streams are separated by an inter-symbol delay, α, as shown in Fig. 1. The receiver counts the number of pulses for each pulse stream and applies the decoding according to the flags received. The data rate depends on the number of clock cycles required to transmit a packet. Beside the elimination of CDR, the implementation of PIC is very area-efficient, low-power and highly tolerant of clocking differences between transmitter and receiver. As empirically found in [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF], PIC is dynamic and provides data rates in the range of 3.1 -8.5 M b/s with an average of 4.1 M b/s operating at a clock rate of 25M Hz and transmitting data words of 16-bits each. For an ASIC implementation using 65nm technology, PIC can reduce area by more than 80% and power by more than 70% in comparison with a CDR-based serial bit transfer protocol.

Pulsed Decimal Communication

Like PIC, the core concept of PDC is to break the data packet into smaller segments, and to transfer these segments as series of pulses. The number of transferred pulses of a given segment is equal in count to the decimal number represented by the segment bits. Hence the name of this technique: Pulsed Decimal Communication (PDC). High-data rates are achieved by a three-step

First Step: L1 Segmentation

The decimal number represented by the data word increases exponentially with the number of bits. The count of pulses to represent a number becomes large and it becomes infeasible to transfer this count in pulses. Therefore, segmentation is required to break a data word into several independent segments with lower number of bits, hence representing smaller numbers. It is mentioned in [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF] that a segment size of 8 bits optimizes the number of delays for PIC to increase the data rate. For PDC, 8 bits is not an optimum segment size and the segments need to be cut down further before the pulses can be transferred. On the other hand, increasing the number of segments before encoding would decrease the data rate. This is because each time a segment is encoded, flags are generated to represent the type of encoding applied. The process of encoding will be explained in the following subsection. The encoding flags are also transmitted in the form of a separate pulse stream, and an increase in the number of segments increases the number of flag streams to be transferred, which would of course reduce the data rate. Additionally, there is an increased area and power overhead associated with the encoding of each of the segments. Therefore, it is not feasible to break the data word into a large number of segments before the encoding is applied.

To address this, we have introduced two levels of segmentation, pre-and postencoding as shown in Fig. 3. In the first segmentation level, data is broken into segments called Data Segments (DS) each of which is 8 bits long. One could think of applying encoding on a 16-bit data word instead of performing the first level of segmentation, but it has been experimentally observed that encoding 8 bits is far better than encoding 16 bits in order to reduce the decimal number represented by the segment bits.

Second Step: Encoding

The PDC encoding is similar to that of PIC [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF]. Reducing the number of ON bits, within each segment, and mapping these bits to the locations with smallest This can be achieved using bit-wise inversion and segment-wise reversal. Bit-wise inversion is a conditional one's complement operation on the segment bits, the condition being that more than half of the length of the segment is occupied by ON bits. Reversal is a conditional right-left flipping operation, the condition being that the decimal value of the segment bits after flipping is less than its decimal value before flipping. Fig. 4 illustrates the application of inversion and reversal on a 8-bit data segment. In particular, it shows that inversion and reversal alone cannot minimize the number of pulses. On the other hand, combining inversion and reversal results in the smallest decimal number, namely 7, for that particular example. One's complement and flipping on short data words are not only very easy to implement in hardware but also very energy-efficient. Each of the four types of encoding is represented by a flag number as shown in Fig. 5.

Third Step: L2 Segmentation

As mentioned earlier, PDC needs to have a second level of segmentation postencoding to further reduce the number of pulses per segment. This second level of segmentation, shown in Fig. 3, breaks each data segment (DS) into Sub-segments (SS), each of which is 4 bits long. The 4-bit length is the optimum segment size for PDC as will be explained in Section 4. The complete three-step process is shown in Fig. 6(a). EDS0 and EDS1 represent the two 8-bit encoded first-level data segments.

Serialization

The serializer collects the encoded data from the encoder and transmits it serially according to the format shown in Fig. 7. Unlike PIC, each segment is transmitted independently without any header to indicate the encoding flags. The body of the message includes the pulses of the L2 sub-segments (SS) only. The flag information is transmitted along with the start pulse prior to the transmission of SS's. As mentioned earlier, each flag is a 2-bit code representing one of the 4 encoding cases (Fig. 5) for each DS of the L1 segments. The PDC serializer combines all DS flag codes to generate one flag code that is 4 bits long, called the CFlags, as shown in Fig. 7. It must be remembered that in the absence of any encoding PIC used the flag code 4 instead of 0 because it needed at least one pulse to represent the absence of data pulses which is already assigned as another flag code. On the other hand, PDC replaces the flag code of 4 with 0 as the "CFlags" pulses are transmitted along with the start pulse, which helps in recognizing 0 without any additional pulse. "SSn" (SS0 to SS3) represents the number of pulses being transmitted for a particular L2 SS. Each of these parts is sent in the form of a pulse stream (one pulse is equal to 1 clock cycle), and each stream is followed by an inter-symbol delay, α, made of 4 clock cycles.

Transmission is initiated with a start pulse followed by all the message pulses. It ends with two stop pulses. There is inter-symbol delay, α, of 4 clock cycles after the "Start+CFlags" and "Stop" pulses. The waveforms for PDC transmission are shown in Fig. 8.

PDC Example

An example of PDC data transmission is shown in Fig. 9. If we transmit the decimal number represented by data without any segmentation and encoding, we need numerous pulses (i.e. 65055). The data rate would be decreased drastically.

In the L1 segmentation step, if we break data into two independent segments then we will reduce the decimal number to two smaller numbers, 31 and 254. Though the numbers of pulses are reduced significantly, still these are large enough to deteriorate data rate considerably. Segment 1 has higher number of ON bits as compared to half of the segment size and, therefore, need encoding where all the bits are complemented resulting in fewer number of ON bits. The resulting segment number is increased to 224 instead of decreasing because the ON bits are now located at higher index numbers. This needs the second step of encoding that is to flip the segment bit-wise which results in a smaller number that is 7. The flag for segment 1 is set to {1, 1} = 3 to indicate that both steps of encoding are applied. On the other hand, Segment 2 only need inversion of bits as it results in fewer ON bits which are located at lower index numbers. The resulting number in segment 2 is 1. The flag for Segment 2 is set to {1, 0} = 2 to indicate that bits are inverted only. In L2 segmentation step, if we break data into four independent sub-segments then the number of pulses needed for each sub-segment would reduce further. Both flags are combined to generate one 4bit CFlags. In serialization or transmission process, we have one start pulse, one CFlags with pulse count of 14, four sub-segments with pulse counts of 8, 1, 2, and 1, and two stop pulses. All of these pulse streams are then transmitted in a packet format as shown in Fig. 7, 8, and 9.

PDC Protocol Analysis and Optimization

Preliminary Equations

Let b n i denote the i-th bit in the n-th sub-segment and f d i denote the i-th bit of the flags code for d-th encoded data segment. We assume the number of bits per segment and the number of sub-segments in the data stream to be both 4. Then the total number of pulses C is given by

C = 3 + 6α + Φ C + 3 n=0 P n (1)
P n = 1 + 3 i=0 2 i b n i (2)
Φ C = 1 + 1 d=0 4 d F d with F d = f d 0 + 2f d 1 (3) R = B T C ( 4
)
where α is the inter-symbol delay, P n is the number of pulses required for the n-th sub-segment SS n , F d is the flag pulse count for the d-th encoded data segment DS d , and Φ C is the combined CF lags flag pulse count. The expression of C in (1) results from a summation over all segments in a data stream of length B = 16 bits, which results in the data rate R in (4).

General Case

A data word length of 16 bits is recommended to guarantee best results and, therefore, the PDC discussion so far and the equations above have considered 16 bits of data to transmit. However, the PDC system can be generalized if data words of more than 16 bits are transmitted. To achieve high data rates, one needs to make sure that the data size is a multiple of 16. If the data words are not multiple of 16, we append 0's at the MSB end of the data. In general, the total number of L1 data segments would be D = B/8, the total number of L2 sub-segments would be N = D × 2, and the total number of CFlags would be M = D/2. A data word size greater than 16 bits results in multiple CFlags.

One of these CFlags is transmitted along with the start pulse, as mentioned in Section 3, and the remaining CFlags are transmitted as separate pulse streams. Each of these pulse streams is comprised of CF lags + 1 pulses followed by an α delay, and is transmitted prior to the transmission of the corresponding data segments. With this notation, we have the following general expression for the total pulse count

C = 2 + M + (M + N + 1)α + M -1 m=0 Φ Cm + N -1 n=0 P n ( 5
)
where l is the size of the L2 sub-segment, which is 4 in our implementation of PDC. Recall that each of the Φ Cm represents the encoding flags of two adjacent data segments. For example, if B = 32 bits, the number of CFlags would be M = 2. Φ C0 would represent the 16 LSBs (i.e., two data segments, DS0 and DS1). Similarly, Φ C1 would represent the 16 MSBs (i.e., the two next data segments, DS2 and DS3). The generalized transmission packet format is shown in Fig. 10.

Optimum Sub-Segment Size

The L2 sub-segment (SS) size is chosen to maximize data rate. For a short SS, α delays inserted between pulse streams to separate symbols increase linearly and reduce the data rate. Similarly, for longer SS, segments have large decimal number representations and, therefore, require a large number of pulses to transmit.

The number of pulses increase exponentially with the size of SS, which in turn reduces the data rate rapidly. It is therefore intuitive that there is a segment size for which the data rate is maximum. For PDC, our experimental results have shown that the data rate is maximized when the number of bits per L2 SS is 4.

To find the optimum L2 sub-segment length, we will minimize the number of clock cycles needed to transmit the PDC packet. We know from the previous section that the number of segments is N = B/l. Because there is one CFlags for two consecutive segments, the number of CFlags would then be M = N/2 = B/2l. For a length l, the number of pulses P n of (2) becomes

P n = 1 + l-1 i=0 2 i b n i (6)
Assuming that bits 0 and 1 are equally likely, the expected value of P n is

E[P n ] = 2 l + 1 2 (7)
Similarly, using

E[F d ] = E[f d 0 ] + 2E[f d 1 ] = 1 2 + 2 × 1 2 = 3 2 (8)
the expected value of Φ Cm as expressed in ( 3) is given by

E[Φ Cm ] = 1 + E[F 0 ] + 4E[F 1 ] = 1 + 3 2 + 4 × 3 2 = 17 2 (9)
Using N = B/l and M = B/2l, the expected value of the total number of clock cycles C as given in ( 5) becomes

E[C] = 2 + M + (M + N + 1)α + M E[Φ Cm ] + N E[P n ] (10) E[C] = 2 + M (α + 1) + N α + α + 17M 2 + N 2 l + 1 2 (11) E[C] = 2 + B 4l (α + 1) + B l α + α + 17B 8l + B(2 l + 1) 2l ( 12
)
Taking the derivative with respect to l and equating it with zero, we get

∂E[C] ∂l = - B 4l 2 (α + 1) - B l 2 α - 17B 8l 2 + B 2 l ln(2) 2l - B 2 l 2 l 2 - B 2l 2 = 0 ( 13
) -2(α + 1) -8α -17 + 4l 2 l ln(2) -4 2 l -4 = 0 (14) 2 l (l ln(2) -1) = 1 4 (23 + 10α) ( 15
)
which gives the following expression of α as function of l

α = 2 5 2 l (l ln(2) -1) - 23 4 ( 16
)
This function is plotted in Fig. 11 and can be used to obtain the optimum sub- An alternative graphical method to find l opt for a given α is to plot the left-and right-hand sides of

l ln(2) -1 = 1 4 (23 + 10α)2 -l (17)
as function of l. The optimal segment size l is at the intersection of these two curves. Such plot is shown in Fig. 12 for α = 4, which corresponds to

l ln(2) -1 = 63 4 2 -l (18)
Again, the optimum value of the L2 sub-segment length is found to be

l opt = 3.5 ≈ 4 ( 19
)
If the sub-segment length is increased or decreased from this optimum value, the data rate declines rapidly. To achieve maximum data rate at a given cock frequency, one must therefore operate the PDC signaling with an L2 sub-segment length of 4 bits.

Data Rate

PDC is dynamic in that the actual data rate of the protocol is dictated by the pulse C count which is very much data dependent as is clear from (1) and ( 5). We have analyzed the statistical distribution of PDC data rates using exhaustive sampling of 16-bit data words (2 16 -1 PRBS), each segmented into four 4-bit sub-segments. For data rate calculations, we use a 25MHz clock. The analysis has shown that the three-step encoding process (L1 Segmentation + Encoding + L2 Segmentation) is generally needed not only to maximize the (average) data rate but also to tighten the distribution of dynamic rates around the average data rate. The effect is shown in Table 1. Note that after full three-step encoding, there is a significant improvement in the average data rate and a tightening of the data rate distributions around the average. The histogram of data rate is shown in Fig. 13.

Tolerance with Respect to Clock Variations

Even if similar clock generators are used at the transmitter and receiver end, there would be a slight difference between their clock frequencies due to the various sources of variability. Considering the slow speed end as a reference and keeping the inter-symbol delay α the same for both ends, the rate of the fast clock should not exceed a limit above which decoding errors start to occur [START_REF] Muzaffar | Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications[END_REF]. In Fig. 14(a), we plot the maximum limit on the clock speed of the fast clock, f F max , for a range of α while the slow clock, f S , is at 25MHz.

Automatic Protocol Configuration

While PDC is tolerant towards clock discrepancies, its per-device parameters have to be adapted in order to support high level of clocking differences. The device parameter setting may be done manually or at the factory in a way similar to existing low-power, single wire solutions. Not only does manual or factory setting method limits the scalability of IoT network to an arbitrary number of devices, but also it prevent the devices from communicating at the highest data rate allowed by the protocol. To overcome this limitation an algorithm for automatically detecting and setting the PDC protocol parameters at the poweron phase can be used that to help remove the restriction on the IoT devices in the PIC network to communicate at a pre-specified baud rate and allows the devices with different capabilities to communicate reliably. At power-on, based on clockrate differences the master device configures all the slave devices connected to a single-channel network prior to the start of any device-to-device communication. Pulse count differences between the pulse trains at the transmitter and receiver are used in closed-form formulas to find a suitable inter-symbol delay coefficient so as to eliminate the need to know the exact clock rates at both ends of the link. An example flow of the configuration process is shown in Fig. 15 where the master device broadcasts a clock pulse stream and then contacts the slave devices one-by-one to receive their responses. Each of the slave devices receives the incoming clock stream and compares with its local clock speed. At master device request, if the device is at higher clock speed as compared to master, five pulses are transmitted back and the slave device updates it's α accordingly. If the device is at lower clock speed as compared to master, three pulses followed by 255 pulses are transmitted back at local clock rate. Depending on the response format, the master updates a table of α entries for the slave devices. Later, the master device picks up the corresponding α from the look-up table and starts communicating with a slave device.

Power Management

Although PDC [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF] itself is power-efficient, the PDC physical layer can be the source of significant power consumption. A PDC power management policy can be used to improve further its ultra-low power characteristics without impacting data rates. This policy shows that an additional 22% power saving at the PIC PHY layer can be achieved using the duty cycle of the pulse as a power control parameter, as shown in Fig. 16. A mathematical model helps in selecting the physical design parameters related to PDC PHY power management. For an input duty cycle of 20ns, the implementation of this policy in 45nm CMOS technology shows that the smallest duty cycle of 0.39% can be generated to achieve 22% of extra power saving.

Reliability

In this subsection, we analyze PDC in terms of its robustness and reliability in comparison with PIC. We use packet failure rates as a comparison metric.

Considering the PIC transmission format for 16 bits of data, there exist several locations in the packet which, if corrupted, may be the source of complete packet failure. For instance, there are 8 to 16 locations of α delays, and each can be a source of packet failure if it gets corrupted. This corruption makes it difficult for the receiver to detect α and sample the subsequent pulse streams at the expected instants of transmission. Similarly, if the information on the number of indices (NOI, one for each packet) is not received successfully, there is no way for the receiver to know about the number of incoming index pulse streams. Additionally, the corruption of two sync pulses can also misalign the pulse streams during PIC decoding. when 0 ≤ N OI ≤ 4. Analyzing the PDC transmission stream, we know there would always be a fixed number of pulse streams that directly eliminates the threat of packet failure due to the NOI and sync pulses, as these are not included in the packet at all. In terms of α delays, there are only 6 locations (P E P DC = 6) for all the possible 16 bit data words. This makes PDC simpler and more reliable even when compared with the best PIC case, P E P IC = 10 in (21).

Experimental Results

A full experimental setup, similar to that of PIC [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF], is implemented in Verilog on the Xilinx Virtex-7 FPGA platform. The prototype platform is used to verify PDC functionality and performance. Extensive simulations and real time hardware verification are performed in order to verify the results. To make a fair comparison with PIC, we have used 16-bit data words and a clock rate of 25 MHz as in the PIC testing system [START_REF] Muzaffar | A pulsed-index technique for single-channel, low-power, dynamic signaling[END_REF]. The same experimental flow is adopted in which the PDC transmitter sends the 16-bit data starting at 0 with an increment of 1 at each transmission. The receiver resends the same data back. The returned and original data words are compared to verify the complete round-trip chain.

To get the most realistic comparison with PIC in terms of power and area, we have synthesized the PDC system using GLOBALFOUNDRIES 65nm technology and found that PDC consumes around 25µW with a gate count of around 2150, while offering dynamic data rates in the range of 4.87 -12.9 Mb/s (7.33 Mb/s average) with a 25-MHz clock. As compared to PIC, the PDC increases average data rate by 78%, makes the transmission more reliable with respect to packet failure rates, and still remains well within the power and area budget of PIC. Table 2 shows a comparison between PIC and PDC. In Fig. 17, an overall comparison of PIC and PDC is presented. Along with the increased data rate, the gate count, power consumption and energy per bit in PDC are also reduced as compared to PIC. The reliability in terms of vulnerable locations is also reduced by 40% as compared to the best reliability case in PIC transmission. Table 3 presents a comparison of PDC with CDR based simple serial transfer technique. The ASIC synthesis results show that PDC can reduce power consumption by more than 72% and area by more than 89% as compared to the best cases of CDR based serial transfer techniques available to-date.

Conclusions

Pulsed Decimal Communication (PDC) is an improved version of Pulsed Index Communication (PIC). It is a novel, simple yet robust method of signaling over single-channels that fulfils the requirements for high-data rate, ultra-low power protocols for IoT sensors. The concept of transmitting the indices of ON bits is replaced with the transmission of reduced decimal numbers. The PDC segmentation and encoding process reduces the overall number of transmission pulses by reducing decimal numbers, hence improving the data rate by 78% with respect to PIC. The average data rate is 7.33 Mb/s with a 25-MHz clock consuming a power of 25uW with a gate count of 2150 in 65nm technology. Unlike PIC, there are fewer inter-symbol delays α in the PDC packet. Moreover, a fixed number of pulse streams is used for transmission, thus providing a simpler and more reliable communication technique that results in a significant decrease in packet failures, especially for low-end devices and sensors. The elimination of variations in the number of pulse streams makes the use of error detection and correction schemes easier. Like PIC, the PDC reduces silicon area and power consumption significantly by eliminating the need for a CDR. It is also robust with respect to skews, jitters, and clock variations as its decoding is based on counting the rising edges of the transmitted pulses. Additionally, all the presented PIC-related work for robustness analysis [START_REF] Muzaffar | Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications[END_REF], auto detection of communication parameters [START_REF] Muzaffar | Automatic protocol configuration in single-channel low-power dynamic signaling for IoT devices[END_REF], and power management [START_REF] Muzaffar | Power management of pulsedindex communication protocols[END_REF] are valid for PDC without any change.

Fig. 1 .

 1 Fig. 1. PIC Packet Format

Fig. 2 .

 2 Fig. 2. Conceptual Block Diagram of PDC

Fig. 3 .

 3 Fig. 3. PDC Three-Step Encoding Process

Fig. 4 .

 4 Fig. 4. PDC Encoding: (a) No Reversal or Inversion (b) Reversal (c) Inversion (d) Inversion and Reversal

Fig. 5 .Fig. 6 .

 56 Fig. 5. PDC Flags

Fig. 7 .

 7 Fig. 7. PDC Transmission Format

Fig. 9 .

 9 Fig. 9. PDC Example

Fig. 10 .

 10 Fig. 10. Generalized PDC Transmission Format

Fig. 11 .

 11 Fig. 11. α vs. L2 Sub-segment Length

Fig. 12 .

 12 Fig. 12. Optimal Segment Length for α = 4

Fig. 13 .

 13 Fig. 13. Data Rate Analysis

Fig. 14 .

 14 Fig. 14. (a) α vs Inaccuracy Limit (b) Regions of Operation (fS = 25M Hz) [7]

Fig. 6 (

 6 b) identifies different regions of operation. Beyond the safe region of operation, there is a region of uncertainty in which errors start occurring randomly. At a certain level of clock discrepancy, total failure occurs due to the failure in detecting even a single inter-symbol delay. The recommended region of operation is of course the one delimited by f F max .

Fig. 15 .

 15 Fig. 15. An Example of Automatic Parameter Detection [9]

Fig. 16 .

 16 Fig.[START_REF] Urano | A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL[END_REF]. Proposed PIC PHY Layer[START_REF] Muzaffar | Power management of pulsedindex communication protocols[END_REF]

Table 1 .

 1 PDC Data Rate Comparisons

	Encoding Process Steps
	L1 Segmentation Only	19	1.81	0.75
	L1 Segmentation + Encoding	19	3.92	0.97
	L1 Seg. + Encoding + L2 Seg. 12.9	7.33	4.87

*Max. *Avg. *Min. *All data rate entries are in Mb/s.

  The number of locations, P E P IC , whose corruption in a PIC stream of 16 bits results in a complete packet failure during transmission has been found in the range 8 + 2N OI min + 2 ≤ P E P IC ≤ 8 + 2N OI max + 2

		(20)
	10 ≤ P E P IC ≤ 18	(21)

Table 2 .

 2 Synthesis Results Data Rate (M b/s) Power (µW ) Avg. E b (pJ/bit) Area (gate count) PDC 4.87-12.9 (7.33 Avg.) ≈25 3.41 ≈2150 PIC 3.1-8.5 (4.1 Avg.) ≈ 26.6 6.49 ≈2356 Fig. 17. PDC vs. PIC

Table 3 .

 3 PDC Comparison With Simple-Serial Power (µW ) Area (gate count) SRL a CDR Total d (PI) e SRL CDR c Total d (PI) e Serializer b. Normal Serial Transfer c. Estimated calculation d. SRL+CDR e. %Increase as compared to PDC

	PDC 25 N/A	25	2150 N/A	2150	65nm
		70 102.1 (75.5%)		15600 16927 (87.3%) 90nm [12]
		62.5 94.6 (73.6%)		60000 61327 (96.5%) 90nm [14]
	NST b 32.1	90 122.1 (79.5%)	1327	N/A	N/A	90nm [15]
		57.5 89.6 (72.1%)		19800 21127 (89.8%) 65nm [16]
		60.6 92.7 (73%)		N/A	N/A	28nm [13]

a.

Acknowledgments

This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi-SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Investment Company, Abu Dhabi, UAE.


Vivek Nautiyal
email: vivek.nautyial@arm.com

Lalit Gupta

Gaurav Singla

Jitendra Dasani

Sagar Dwivedi

Martin Kinkade

Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications

Keywords: Power-on Reset (POR), sub-threshold, 16nm, FinFET, Self Timed, Internet of Things (IoT)

des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

INTRODUCTION

At the time of power-up, the POR signal generator senses a minimum threshold voltage, and generates a POR signal as shown in Figure 1. This POR signal is used to preset/reset the flip-flops, latches, and registers to a known state. The supply voltage for the POR circuit is the same as the SOC supply voltage. This presents a challenge because the POR circuit needs to operate while the supply is ramping up. Conven-tionally, higher-voltage applications use a band-gap reference voltage to compare with supply voltage to generate the reset signal. As low-power devices continue to use supply voltages below the band-gap voltage, conventional POR circuit design becomes difficult. More specifically, the challenges occur as the supply voltage of lowpower applications like IoT devices approaches the threshold voltage. Multiple factors increase the complexity of the POR circuit. Slow ramping supply voltage may not generate a POR signal with sufficient voltage level and pulse width to reset the logic circuit. Sharp supply rise times can extend the pulse width of the POR signal, even when supply has fully ramped up because of the longer reaction time of the circuit and the coupling capacitance with supply voltage. The circuit presented in this paper uses a self-timed circuit, to ensure that the reset signal pulse-width varies according to the time needed to reset the latch. The proposed circuit is designed to operate without any reference voltage, thus eliminating these limitations.

The supply voltage requirement of the SOC is based on the maximum supply requirement of all the components. The amount of on-chip decoupling capacitance is also designed based on regular circuit activity. However, at the time of power-up, unpredictable activity of the components causes the supply ramp-up rate to be nonlinear. With technology scaling, process variation increases as device dimensions, threshold voltages, and supply voltages have decreased. Device simulation models fit to silicon behavior in limited voltage range, for example nominal voltage, with some tolerance. It is possible that a fully functional POR pulse generator operating in a simulation fails in silicon. To avoid such a situation, the POR signal generator must be simple, and must be thoroughly analyzed. To verify our design, we performed exhaustive simulations involving Monte Carlo tests on different PVT corners with a post-layout netlist. After that, we performed digital testing on silicon.

Fig. 1. General POR circuit waveform

This work is an extension of the POR circuit presented in [START_REF] Nautiyal | Robust, self-timed power-on reset circuit for low-voltage applications[END_REF]. We propose 2 circuits to set/reset latch at power up correctly. 1. Self-Timed POR circuit [START_REF] Nautiyal | Robust, self-timed power-on reset circuit for low-voltage applications[END_REF] 2. Latch based self-feedback POR circuit [START_REF] Gupta | Power-On-Reset Circuit[END_REF] First the self-timed circuit is explained. Although it resolves the issue, it comprises of some limitations in terms of its implementation in all scenarios. The latch based selffeedback circuit resolves these issues based self-feedback circuit.

In summary, the major contributions of the proposed circuit are as follows:

• Removing the requirement for a reference voltage. This is useful for low-voltage applications • Implementation of a self-timed circuit, to ensure that the reset signal pulse-width varies according to the time needed to reset the latch. • Use of NAND latch in POR Circuit: -NAND gate resets with 0 voltage level which is the case for all the nodes at power up, making it easier to ensure reset at lower voltage level. Reset of the NAND latch is further used to reset all other latches in the design. • Latch based self-feedback circuit: To resolve limitations of self-timed circuit.

The paper is organized as follows. Related Work is presented Section 2. Requirement of POR circuit in SRAM memories in explained in Section 3.1. Overview of the first proposed self-timed circuit is mentioned in Section 3.2. Detailed working of the selftimed circuit is provided in Section 4. Verification of the proposed circuits is presented in Section 5. Section 6 comprises of limitations of self-timed circuit and working of the self-feedback latch-based circuit to avoid these issues. Finally test-chip results and silicon validation are provided in Section 7, followed by conclusion in Section 8.

RELATED WORK

Researchers have been studying and developing POR circuits for a long-time because of their need in analog and digital integrated circuits (ICs). It began with traditional RC circuits, and then researchers explored the use of diodes, BJTs, and MOSFETs as circuit complexity increased [START_REF] Shen | Power-on reset pulse generator[END_REF][START_REF] Hanke | CMOS power-on reset circuit[END_REF]. POR circuits are now used in various applications such as automotive and RFID tags [START_REF] Guo | Power-on-reset circuit with power-off auto-discharging path for passive RFID tag ICs[END_REF][START_REF] Giuffredi | A programmable power-on-reset circuit for automotive applications[END_REF]. Further research in this field led to the development of circuits focused on low-voltage and low-power applications [START_REF] Yasuda | A power-on reset pulse generator for low voltage applications[END_REF][START_REF] Chhabra | Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM[END_REF][START_REF] Prakash | Zero quiescent current delay adjustable power-on-reset circuit[END_REF].

A current-source-based POR is also proposed in [START_REF] Katyal | A self-biased current source based power-on reset circuit for on-chip applications[END_REF] for on-chip applications.

The circuits have been designed and enhanced to support multiple I/O power supplies [START_REF] Burdia | Power-on reset circuit for SoC with multiple I/O power supplies[END_REF]. Temperature, ramp-up rate, and threshold voltage variation affect the reliability of a POR circuit. Designs have been proposed in [START_REF] Zhang | Design of a novel power-on-reset circuit based on power supply detector[END_REF][START_REF] Wen-Cheng | A precision CMOS power-on-reset circuit with power noise immunity for low-voltage technology[END_REF] to overcome these variations and offer robust circuits.

Discrete ICs for POR functionality is available. However, designing on-chip POR offers an area reduction advantage. In this study, we propose an on-chip, self-timed, low-voltage POR circuit that is functional at a minimum of 400mV on 16nm FinFET technology. The technique uses multiple delay stages and uses a combination of coupling capacitances and resistor divider circuits to generate a reset signal. The area overhead of the POR circuit is minimal, the circuit uses no dynamic power during normal SOC operation, and the pulse width of the reset signal is self-timed.

OVERVIEW OF SELF-TIMED POR CIRCUIT

Problem Statement

Conventional SRAM architectures have latches to latch data, address and other input signals. These latches are provided CLK input such that it resets the latch as desired for expected functionality. Hence POR circuit is not usually needed in such designs.

In latch-based pseudo dual port SRAM memories [START_REF] Nautiyal | An ultra high-density pseudo dual-port SRAM in 16nm FINFET process for graphics processors[END_REF], latches are used for portA but using latch for portB creates the need of POR circuit as will be explained in this section. To resolve this issue flip-flops can be used but at the cost of significant impact on area. Thus, latches were used instead of flip-flop for portB inputs to save area. Figure 2 shows NOR based SR latch that was used in dual/two port memories, to optimize the portB hold time and area. For dual port memories, CLK signal generates 2 internal clocks known as global timing pulse (gtp). Initially data for portA is passed through the mux by selecting the mux_sel signal accordingly. Until then data for portB is latched. At power-up, it is essential that signal qi, which further generates clk_latb and iclk for the latch operation is set to the desired state.

Figure 3 shows both cases where signal qi can be set to different values. When set to low level, data for portB is latched as expected because clk_latb is low. When qi is set to high level, data for portB is not latched correctly. This will result in write failure for the first cycle. Since NOR latch needs a high pulse to reset it, conventional method of resetting it through delaying the supply at the input of NOR latch was showing failures in Monte Carlo simulations.

To resolve this issue, well-known solutions can be implemented but such conventional POR circuit has its own limitations and penalties. To have a high pulse which is enough to latch correctly, amount of required RC is huge. Hence RC and stage delaybased POR circuit costs a lot of area. Stage delay suffers from variability and need big area to provide a reasonable big delay at slow supply ramp. Voltage divider-based POR circuit suffers from significant DC current requirement and are analog in nature. These kind of Power-On-Reset circuits needs silicon validation and are not needed for memory circuits which are supposed to be simple in nature. Based on the mentioned analysis, we propose the following self-timed POR circuit which resolves the SR NOR latch problem and its use is not limited to this scenario. Figure 5 shows the detailed transistor-level diagram of the POR circuit. PCTRL is delayed as compared to the ramping supply. The feedback circuit also generates NCTRL, which prevents any DC current through the POR circuit. This enables the POR circuit to be used in low-power applications. When the supply is ramping up, capacitors C0, C1 and C2 couples with VDD and turns PCTRL and NCTRL signals low causing the latch to reset. After reset output NQ follows the supply, while Q stops following the supply voltage. NQ generates a feedback signal when the reset is complete. The feedback output switches PCTRL and NCTRL signals such that it makes NOR output independent of NQ. The circuit is self-timed, which means that the reset signal turns off depending on the delay of the circuit and the ramp-up time of the power supply. This will help in providing sufficient pulse width for the reset signal. Generation of delayed VDD is shown in Figure 6. The output of this circuit, VDD_DLY_LVL1, is used to generate a supply-delayed PCTRL signal. Before the power-up operation, all nodes in the circuit are at ground (VSS) level. When powerup begins, the supply starts ramping up, the LO node is coupled because of the Miller capacitance of P0 and P1. This delays the ramping of HI node which in turn helps LOW node to remain at high state. The Vds of the PMOS transistor P0 causes a slight delay in the HI node. The HI node voltage is much lower than the threshold voltage of the NMOS transistor when the ramp-up is slow delaying P1 conduction. The LO node falls with a delay, thus delaying VDD_DLY_LVL1 output supply. N2 acts as a clamping node in case the LO node is coupled higher than Vt as this would turn off the PMOS transistor.

PCTRL generation

Figure 7 shows that the VDD_DLY_LVL1 from Figure 6 and feedback circuit output FEED/BFEED from Figure 9 generate the PCTRL signal. This signal is also delayed with respect to the VDD supply. Initially at ramp up BFEED = '0', and FEED is ramping up. PCTRL is a delayed VDD signal because of coupling of capacitors C0 and C1 with VDD. When BFEED = '1', PCTRL follows VDD. PCTRL is delayed VDD because of three mechanisms. First, VDD_DLY_LVL1 is used as a source bias for the PMOS transistor P3, whose drain generates the PCTRL signal. The gate of the transistor P3 is connected to coupling capacitance C0. The other node of the coupling capacitor C0 is connected to the supply. As the supply rises, the coupling capacitor makes the gate of the PMOS rise, thereby turning it off. The FEED node at the gate of the NMOS N4 of the PCTRL generator is coupled HIGH through the coupling cap C1. This causes some charge of the PCTRL to leak through the NMOS transistor.

POR and the feedback circuit

The POR circuit is shown in Figure 10 which corresponds to Section 3d in Figure 5. PCTRL and NCTRL are the inputs to this circuit and the output is a reset signal for the SR latch. PORB and NQ signals are inputs to the feedback circuit shown in Figure 9.

Since PCTRL is delayed with respect to the ramping supply, the POR signal which follows VDD is also delayed. After POR goes HIGH, then the SR latch RESET goes HIGH. When the SR latch is reset, the corresponding output Q becomes LOW and after the latching operation, output NQ starts following supply. As shown in Figure 9, logic NOR of NQ and the PORB signal generate a feedback signal. When reset is executed, the NQ signal goes HIGH making FEED go LOW and BFEED go HIGH.

The FEED and BFEED signals will switch the PCTRL signal HIGH, turning off the PMOS transistor P3 in Figure 7. Similarly, BFEED turns on the N7 transistor in Figure 8, making NCTRL go HIGH. Now, PCTRL, which is HIGH, and NCTRL, which is also HIGH, turn off the reset signal as per the circuit in Figure 10. The PORB signal in the feedback circuit also turns HIGH.

When PORB turns HIGH, the state of reset, FEED, BFEED, and all other signals stay the same and becomes independent of NQ, making normal operation of SR latch independent of RESET signal. Based on process variation, the forward path, or feedback path, of the SR latch will make one of the nodes go HIGH and other go LOW. This state of the SR latch is probabilistic. If the state of the SR latch is as desired, an initial RESET pulse will be generated, which will do nothing to latch as it is already in the desired state. After some time, when NQ disables the RESET pulse operation, the SR latch will become independent of the POR circuit. If the state of the SR latch is not as desired, the initial HIGH pulse on the SR latch will make sure that the latch flips to the desired state, and afterwards the RESET pulse will be disabled. Since this is a simple feedback mechanism it doesn't need any reference voltage generation; hence it operates very well at low voltages. In proposed circuit, a feedback circuit is used. In case there are multiple flip-flops and latches that need to be reset, it is not possible to take feedback from all the latches. The circuit can be used in such cases as well. Instead of taking feedback from all the latch outputs, feedback will be still taken from a single latch. However, the output NQ of that latch will act as RESET signal for all the other latches. the feedback with a single latch will not be enough for timing if a reset signal is propagated through a buffer tree. This is resolved by considering worst RC distance for the POR latch. Additionally, the latch is skewed to account for variation and a buffer is inserted in the feedback path.

SPICE VERIFICATION FOR SELF-TIMED POR CIRCUIT

Figure 11 shows timing waveform from self-timed POR circuit simulation. All the internal signals along with the reset signal can be seen in the figure. The VDD signal is ramping up which generates the reset signal and turns PORB high. As mentioned earlier, factors such as temperature and process variation, device models, supply ramp-up rate, and supply noise increase complexity of the POR circuit. To make sure, that our proposed POR circuit functions correctly, we exhaustively verified it. For global variation, we took different global process corners and for local variation, we ran 5000 Monte Carlo simulations for each of the global corner with the criteria shown in Table 1.

Monte Carlo Simulations 5000

On-chip or on-board supply and ground are not always ideal. They are susceptible to different kinds of variations and noises. For simulating noise at power up, we superimposed 50mV sinusoidal noise on VSS and 10% of instant supply sinusoidal noise on the supply for the POR block. As shown in Figure 12, when RESET or BFEED signals are at VSS level, 50mV noise is present. Also, the supply ramping up shows 10% instant supply value as noise in the VDD. As shown in Figure 11, when the BFEED signal switches from HIGH to LOW, after some delay. The reset signal also switches from HIGH to LOW. Before that, the RESET signal has been following supply because of the POR circuit. 5000 Monte Carlo simulations returned zero defects. Different voltages, temperatures, and supply ramp-up slopes, supply and ground noise for different process split verify the working of the circuit.

LATCH BASED SELF-FEEDBACK POR CIRCUIT

To address dual/two port latch wrong initialization issue, if we use flip-flop for portB, we don't need power on reset circuit. That will not be area efficient for dual port ultra-high-density design where area is most important.

Although the self-timed circuit resolves the latch issue discussed in Section 3.1, it comes with some limitations. The proposed self-timed circuit is completely based on capacitive coupling. Since it was implemented on 16nm technology where advanced technology helped with the coupling, older technology nodes comparatively have lesser coupling capacitance. In some cases, at lower voltages, coupling might not be as desired for functional operation of the circuit. These issues can lead to limitation of the circuit to be used for older nodes. Here latch based self-feedback circuit is proposed which overcomes these limitations of the self-timed circuit.

Figure 13 shows the block diagram of self-feedback circuit. The idea is to receive feedback from the NOR SR latch, and provide a reset signal to the NOR latch using the NAND SR latch. As shown in the figure, the NAND SR latch uses delayed VDD. Figure 14 shows the detailed diagram for self-feedback POR circuit. Vdd is delayed using RC circuit and logic gates. A NAND SR latch is used after delayed supply Vdd. Since i/p of NAND latch, 'Vdd_delay' starts with 0v, o/p 'pwreset' will follow Vdd, assuming when latch is in wrong state, nqia=low, feed will follow Vdd. NAND latch will fast latch the pwreset signal. Latched pwreset from NAND latch makes latching of NOR latch independent of logic delay in vdd_delay. Figure 15 shows the simulated waveform for self-feedback circuit shown in Figure 14. As shown in the figure, initially nqia is low, once it goes high, feed signal turns low making nqib high. Once nqib turns high, the NAND gate i1 turns pwrreset low. Pwrreset signal stays low thus making nqia stay high. Our assumption is when latch is in wrong state, nqia=low, feed will follow Vdd but this assumption is not always correct. Nqia can initially follow Vdd before finally setting to wrong low state, and so feed is not following Vdd. In this case we do not get benefit of NAND latch.

Figure 16 shows a case where Vdd_delay is not enough with circuit shown in Figure 14. This can lead to pwreset signal turning low earlier, further leading to make nqia signal stay low. If nqia signal stays low, portB data will not be latched as explained in Section 3A. To delay pwrreset signal and make sure the circuit is functional, we increase the delay of Vdd_delay going high. We do this by using Vdd_delay as a supply to NAND i2 as shown in Figure 17. When feed is not following Vdd (is less than Vdd) and pwreset is also going high there is a current through resistive divider and vdd_delay rising is delayed thus getting benefit of NAND

TEST CHIP AND SILICON TEST RESULTS

To do silicon validation of designed POR circuit and to get statistical yield data we designed and fabricated a POR validation IP. This IP consists of 16 samples of POR; it has two different latch structures which need to be reset. Figure 20 is the block diagram of POR validation IP. 16 latches, each associated with one POR circuit can be written parallel with the help of D and CLK pin. This is used to initialize the latch with a value opposite to the reset value. Output of 16 latches can be read serially through output Q of a 16:1 mux. The POR validation IP has two supplies: VDDD for digital latches and isolated supply VDDA for POR block. For testing purpose, it is important to initialize the latches. Since supply is ramping up for the POR circuit, we need to have 2 supplies, one of which VDDD is used to initialize, while VDDA is used to generate POR pulse. We tested multiple samples per process split. For each process split we had 20 packaged chips, each packaged chip contains 16 POR circuits. In total, we tested 320 samples per process split. The process split included "SS, TT, FF, SF, and FS". Based on the number of silicon samples tested on different process splits, we observed the self-timed POR circuit is fully functional at a minimum voltage of 400mv. Low voltage operation makes the POR circuit an attractive choice for low power applications like IoT. Also, the 400mv limitation is because of the SR latch. If sub-threshold flipflops/latches are used, the circuit can be used even below 400mv. Figure 21 shows the timing diagram followed for testing of the POR circuit.

First, VDD is supplied and DIN and CLK is used to write a predetermined data into the latches. Then the data is read out serially by the Q pin. Figure 22, shows chip layout of POR validation IP fabricated in 16nm FinFET process.

Once that is done, power VDDA is provided with different ramp-up times and a reset signal is generated. POR circuit should overwrite previously written data in the latches. Once again, the data is read out of the latch to validate the working of the POR circuit. If the output Q of the MUX changes from are used to select data from a single latch amongst the 16 latches present. The self-feedback circuit was tested and validated under stress conditions like self-timed POR circuit.

CONCLUSION

To initialize flops and latches, a POR circuit is needed. The circuit must work with different temperatures, process corners, process variation, supply ramp-up time, and supply noise. For low-power circuits such as IoT devices, the circuit must be functional at low voltages. A robust POR circuit is designed and exhaustive verification with SPICE models for several global corners and 5000 Monte Carlo simulations for local variations was done. In these simulations, the supply ramp-up time was varied from 100ns to 10ms, and supply and ground noise was introduced. The proposed POR circuit operates at low voltage and has no DC power consumption after the supply has ramped up. The self-timed pulse width of the reset signal varies with the time needed to reset the latch. In 16nm FinFET process, we fabricated a validation testchip and performed pass/fail testing of the POR circuit. We found 100% yield for samples of the POR circuit across different process splits, temperatures, and voltages. The circuit has minimal area overhead of 21.3µm2. Silicon validation, demonstrates that the proposed POR circuit works at a minimum supply voltage of 400mV.

Fig. 2 .Fig. 3 .Figure 4

 234 Fig. 2. POR requirement in latch-based pseudo dual port SRAM

Fig. 4 .Fig. 5 .

 45 Fig. 4. Block Diagram of Self-Timed POR circuit components

Fig. 6 .

 6 Fig. 6. Circuit for delayed VDD generation

Fig. 7 .Figure 8

 78 Fig. 7. Circuit for PCTRL generation

Fig. 8 .Fig. 9 .

 89 Fig. 8. Circuit for NCTRL generation

Fig. 10 .

 10 Fig. 10. Self-Timed POR circuit

Fig. 11 .

 11 Fig. 11. Simulated waveform for self-timed POR circuit

Fig. 12 .

 12 Fig. 12. MC simulations of POR with 10ms supply slope

Fig. 13 .Fig. 14 .

 1314 Fig. 13. Block Diagram for Self-feedback POR circuit

Fig. 15 .

 15 Fig. 15. Simulated waveform for self-feedback POR circuit

Figure 18

 18 Figure 18 and figure 19 shows monte carlo simulation results for the self-feedback results at 10mnsec and 100nsec slope of pwreset signal respectively. Both figures show that all the 5000 monte carlo simulations passed with the circuit show in figure 17.

Fig. 18 .Fig. 19 .

 1819 Fig. 18. Monte Carlo simulation at 10msec slope of pwreset signal

Fig. 20 .

 20 Fig. 20. POR validation IP block diagram

Fig. 22 .

 22 Fig. 22. 16nm chip layout

Table 1 .

 1 Simulation Criteria

	Simulation type	Post layout full chip extraction
	Supply ramp up time	100ns, 1us, 1ms, 10ms
	Temperature	-40c, 85c, 125c
	Supply Voltage	0.4v, 0.51v, 1.2v
	Parasitic Extraction-RC ex-traction for metals	-40c and 125c for worst R and worst C
	VSS noise	50mV sinusoidal wave
	Supply noise	Sinusoidal wave of 10% of instant supply value
	Process Corners	SS, TT, SF, FF, FS