Rémy Caillaud

Cyril Buttay

Roberto Mrad

Johan Le Leslé

Florent Morel

Nicolas Degrenne

Stefan Mollov

Thermal Considerations of a Power Converter with Components Embedded in Printed Circuit Boards

Printed-Circuit-Board (PCB) technology is attractive for power electronic systems as it offers a low manufacturing cost for mass production. Integration technologies such as device embedding have been developed to take advantage of the interlayer space in multi-layer PCBs and to increase the performances (Electrical, Thermal). However, the PCB technology offers limited power dissipation due to the low thermal conductivity (≈0.3 W/(m•K)) of its composite substrate.

In this paper, we consider PCB embedding for a 3.3 kW AC/DC bidirectional converter. We describe the integration of not only the power dies, but also the gate drive circuits and the power inductor, with a special focus on the thermal management. The manufacturing processes of the boards are presented. Two thermal models based on finite elements (FE) of this converter stage are introduced. The accuracy of these models is validated against experiments. The results show that a simplified FE model offers satisfying accuracy and fast simulation, even considering the relatively complex structure and layout of the PCBs.

I. INTRODUCTION

O VER THE LAST DECADES, evolution in power elec- tronics has mainly been driven by improvements in the switching components. Since 2001, semiconductor devices made out of wide band-gap materials have been commercially introduced: first Silicon Carbide (SiC) and more recently Gallium Nitride (GaN) [START_REF] Millán | A Survey of Wide Bandgap Power Semiconductor Devices[END_REF]. However, their performances are currently limited by their packaging. Nowadays, the next driver for progress is considered to be better integration and packaging technologies [START_REF] Wyk | On a Future for Power Electronics[END_REF][START_REF] Kolar | What are the "Big CHALLENGES" in Power Electronics ?[END_REF]. In particular, future packaging technologies should offer better electrical and thermal performances and low cost.

Among the possible integration technologies, Printed-Circuit Board (PCB) is especially attractive: because it is a mature technology, many advanced design tools are available, as well as a complete supply chain. It allows a high density of interconnects, and uses relatively inexpensive materials. Many manufacturing steps of a PCB rely on batch processes, allowing a large number of interconnects to be processed at once. Its main limitation is the low thermal conductivity of its base material (most commonly a glass-epoxy composite). Even the best materials have thermal conductivities lower than 10 W/(m•K) [START_REF] Randoll | Characteristics and aging of PCB embedded power electronics[END_REF], a fraction of that achieved by the ceramic materials used in power electronics (e.g. 150 W/(m•K) for AlN). As a consequence, multilayer PCBs are mainly used for low-power converters (<100 W). For higher power levels,

VS IS EMI Filter dc filter L1 Load Q11 Q31 Q21 Q41 N • 1 N • 2 N • 3 N • 4
Figure 1: Circuit diagram of the converter. The topology includes an EMI filter, a Power Factor Corrector (PFC) and a dc filtering stage. The PFC uses 4 interleaved cells [START_REF] Le Leslé | Optimisation of an integrated bidirectional interleaved single-phase power factor corrector[END_REF][START_REF]Optimum Design of a Single-Phase Power Pulsating Buffer (PPB) with PCB-integrated Inductor Technologies[END_REF].

Insulated Metal Substrates (a single-layer, thin PCB bonded onto a thick metal plate) or ceramic substrates are preferred. With the ever increasing need for more compact electronic systems, integration technologies have been developed to take advantage of the inter-layer space in multi-layer PCBs by embedding components in the substrate [START_REF] Buttay | Application of the PCB-Embedding Technology in Power Electronics -State of the Art and Proposed Development[END_REF]. Embedding the devices in the PCB allows to overcome some of the thermal limitations (by reducing the thickness of low-conductivity composite between the components and the thermal management system). Some signal electronic systems were produced with almost all components embedded in PCB [START_REF] Ostmann | Evolution and future of embedding technology[END_REF], but for power electronics, the research has mainly been focused on embedding the active devices only [START_REF] At&s | Embedded Device Packaging Ramping Up Next Generation SiP[END_REF][START_REF] Kearney | PCB Embedded Power Electronics for Low Voltage Applications[END_REF]. The embedding of passives has also been investigated for low power converter (1-100 W) with the embedding of Surface Mount Technology (SMT) components (Resistors, Capacitors, ICs) [START_REF] Alderman | 3-D Embedded Packaging Technology[END_REF], of magnetic cores [START_REF] Ali | Design of a hybrid integrated EMC filter for a DC-DC power converter[END_REF][START_REF] Perrin | 2 MHz highdensity integrated power supply for gate driver in high-temperature applications[END_REF], or of formed components using capacitive or resistive layers [START_REF] Waffenschmidt | Design method and material technologies for passives in printed circuit board embedded circuits[END_REF]. It is worth noting that aside from the scale, this vertical stacking of flat structures (also called "2.5D") is very close to the "chip stacking" concept. Chip stacking is commonly used in microelectronics, and the thermal modeling of such structures have been explored in papers such as [START_REF] Codecasa | Compact dynamic modeling for fast simulation of nonlinear heat conduction in ultra-thin chip stacking technology[END_REF] or [START_REF] Ziabari | Fast thermal simulations of vertically integrated circuits (3d ics) including thermal vias[END_REF]. However, these advanced models require a considerable implementation effort.

In this paper, we investigate the embedding of all components of an AC/DC converter (semiconductor power devices, corresponding gate driver, and inductor), rated at 3.3 kW, with a special focus on thermal aspects. In section II, some details are given regarding the components to be embedded and the chosen physical implementation. The manufacturing process is described in section III. Then, in section IV, two thermal models are presented, while the acquisition of experimental temperature data is presented in section V. Finally, the results are compared and discussed in section VI.

II. DESIGN OF A PFC CELL

The converter topology to be implemented is presented in Fig. 1. It includes an EMI filter, several interleaved Power Factor Corrector (PFC) cells and dc filtering stage. The components of this circuit have been selected using an optimization procedure to achieve the best power density/efficiency ratio [START_REF] Le Leslé | Optimisation of an integrated bidirectional interleaved single-phase power factor corrector[END_REF][START_REF]Optimum Design of a Single-Phase Power Pulsating Buffer (PPB) with PCB-integrated Inductor Technologies[END_REF]. The optimized circuit is composed of 4 PFC cells (each handling a power of 825 W, for a total of 3.3 kW). In the remaining of the paper, we will focus on a single PFC cell, for which the input (ac) voltage is 240 V, 50 Hz, the output (dc) is 400 V and the input current 4 A RMS.

A PFC cell is composed of 4 SiC MOSFETs (CPM2-1200-0080, Wolfspeed) in a full bridge configuration, driven by 2 half-bridge gate drive circuits (based on an IRS21864 IC, Infineon, with their peripheral components -resistors, capacitor, diodes in SMT package -) and an inductor (34.7 µH). The inductor uses an "Embedded Toroidal" structure which corresponds to an embedded annular magnetic core with a winding formed around by PCB tracks and vias (Fig. 2) [START_REF] Caillaud | Design , manufacturing and characterization of printed circuit board embedded inductors for power applications[END_REF]. Note that both half-bridge operate at different frequencies: in Fig. 1, Q1 and Q3 control the current in L1, and switch at high frequency (180 kHz), while Q2 and Q4 are only turned-on or off with respect to the polarity on the mains (i.e. at 50 Hz).

These 3 sets of elements (power semiconductor devices, gate drive circuit and inductor) are embedded in different PCBs which are stacked on top of a heatsink to form a compact assembly. Each PCB is separated by a layer of Thermal Interface Material (TIM). The TIM chosen is a thin (200 microm), electrically insulating (breakdown voltage 3000 V) elastomeric material which is soft enough to conform to the PCB patterns (Bergquist Sil-Pad 1500ST). The boardto-board interconnections are done with wires soldered in metallized through holes. A schematic view of the assembly is given in Fig. 3, and a photograph of the exploded PFC cell is visible in Fig. 4.

With the chosen approach, the empty space created around each component is filled with resin, as compared to air in a standard converter. The replacement of air by resin allows a better conduction of the heat from the components to the heatsink [START_REF] Diaz | Heat Dissipation Challenge in Automotive High-Power Integrated Magnetics[END_REF] and allows easier interconnection. However, the thermal conductivity of the FR-4 (Epoxy resin -fiberglass composite) which composes the substrate of the PCB remains low (0.3 W/(m•K)). With the thick structure presented in Fig. 3 (more than 1 cm), investigations are required to ensure no component will exceed its maximum operating temperature.

III. MANUFACTURING OF THE BOARDS

As depicted in Figs. 3 and4, 3 boards are used to form the PFC cell. While two of them have similar structure ("inductor board" and "driver board", both 4.5 mm-thick), this is not the case for the "Dies board", which is much thinner (0.7 mm). From a manufacturing point-of-view, this requires the production of two different panels, each with a different manufacturing process. For the "Dies board", a "thin panel" is processed, while the "inductor" and "driver" PCBs correspond to a "thick panel". Both of these panels have 4 copper layers (numbered 1 to 4, top to bottom).

1) Thin Panel: Only bare SiC dies are embedded in the "Thin PCB" panel, between both inner layers. The process is presented in figure 5. It starts with a 35 µm plain copper sheet (Fig. 5a) on which the dies are accurately positioned and bonded with non-conductive glue. Some dies are mounted "bottom up" (flip-chip, Fig. 5b) so that interconnects with fast voltage transient (i.e. the middle points of the full-bridge structure) are away from the heatsink, thus reducing commonmode noise. On the contrary, dc voltage potentials (the drain of Q1 and Q2, or the source of Q3 and Q4 in Fig. 1) are routed on large planes close to the heatsink to foster capacitive coupling to ground while providing an electrostatic screen between fast switching potentials and the heatsink.

Sheets of glass-fiber pre-impregnated with resin (so-called "prepregs") are then stacked to compensate for the die thickness (Fig. 5c) and to isolate the dies from the copper layer above. This stack is laminated (Fig. 5d) to form a solid part.

The dies interconnections ("track to dies" vias) are drilled on both sides using a laser ("microvias", Fig. 5e). The laser power is calibrated using sacrificial dies, so that the vias extend all the way through the insulating material (25 µm for the bottom glue layer and 50 µm for the top laminated sheet) and stop when reaching the pads of the dies (finished with 8 µm copper, a value recommended by the PCB manufacturer). Copper is then electro-plated to fill the vias (Fig. 5f). After the copper electro-deposition, the thickness of the copper layers is 70 µm. They are then etched to form the PCB tracks (Fig. 5g). The X-ray image of an embedded die is visible in Fig. 6. The via positioning accuracy with respect to the dies is theoretically estimated at 100 µm (practically, it was found to be 33 µm in the worst case), thanks to accurate manufacturing equipment and monitoring of board deformation.

Finally, the external layers (layers 1 and 4) are added, using similar steps (Figs. 5h to 5k). These two layers are required so that the final panel is rigid enough for handling, has a symmetrical structure (to prevent bowing), and for routing the interconnects.

2) Thick Panel: For this panel, components are no longer glued. Soldering is used instead, as it is compatible with standard SMT packages. This requires to pattern the copper layer 3 before populating it with components. The process begins with a double-sided laminate with 70 µm thick copper (Fig. 7a). Through-all vias are mechanically drilled (Fig. 7b) and electro-plated. The copper is then etched to form the circuit on both sides (Fig 7c). Some solder paste is deposited on the board by stencil-printing, with a pattern matching the footprint of the components. The components are placed on the paste and soldered using a reflow oven (Fig. 7d).

Two prepreg layers are then placed, with cut windows matching the components location and size (Fig. 7e). The aim of these prepreg layers is to provide adhesion for additional layers and to isolate the magnetic cores from copper layer 3. A spacer, composed of several PCB cores and prepregs layers is placed on top (Fig. 7f).

Finally (figs 7g and h) , two more prepreg layers are placed on top to isolate the magnetic core from copper layer 2 and to bond the laminate forming the layers 1 and 2 (which was manufactured similarly to figs. 7a to c). Through-all vias are then manufactured to interconnect all four layers.

IV. THERMAL MODELS

With the complex structure depicted in Fig. 3, it is important to ensure that all embedded components operate below their maximum temperature. Here, we present the thermal models which are used to compute the temperature distribution in the cell. First, a simple model is presented for the convective heat transfer from the heatsink. In a second time, two models are proposed for the heat conduction in PCB stack, and are compared regarding their complexity and computation time.

A. Heatsink Model

While the heatsink used here is fairly simple (a piece of extruded aluminium with straight fins), its Finite Element Model (FEM) is relatively complex: not only does it require many elements to mesh the heatsink itself, but the surrounding air must also be meshed so Computational Fluid Dynamics (CFD) can be applied. This is very important as the air movement (convection) dictates the heat exchange between the heatsink (i.e. the heat flux between the converter) and its environment. To keep the thermal simulations of the converter simple, a two-step approach is used: first, a detailed heatsink model is built, and simulated in a variety of conditions; then a simple equation is fitted to the results of these simulations. For converter simulations, which are performed with a different FE simulator for practical reasons, this equation is used as a boundary condition, in place of the FE heatsink model. The detailed heatsink geometry is drawn in 3D using the Icepack software (Ansys). The heatsink is placed inside a "cabinet", which represents a large volume of air around the heatsink. The cabinet dimensions need to be larger (twice, in our case) than the heatsink dimensions so its boundaries do not disturb the airflow. Air flow is only allowed to cross the top and bottom boundaries of the cabinet. Gravity is taken into account. In addition to convection phenomena, the simulator also calculates the heat exchanged by radiation. The ambient air temperature is 60 • C (maximum ambient temperature specified in our application).

A uniform power dissipation is applied on top of the heatsink baseplate. The temperature of the heatsink (considered uniform) is the result of the simulation. Several simulations are run for power dissipation levels ranging from 1 W to 50 W. The heatsink temperature is extracted for each simulation. It then becomes possible to calculate an equivalent heat transfer coefficient h at baseplate-level such as:

h = P A base • ∆T (1)
with P the power dissipation, A base the top surface area of the baseplate and ∆T the temperature difference between the heatsink and the ambient air. The heat transfer coefficient as a function of the heatsink temperature is presented in Fig. 8.

Finally, an equation of the form h = α(∆T ) β is fitted to the data from Fig. 8. This equation is used in the PCB-stack model as a boundary condition for the converter area which is in contact with the heatsink. This way, CFD is no longer necessary in the thermal simulations of the converter. This approach, however, can only apply to steady-state conditions (it does not consider the "thermal mass" of the heatsink), and is only valid over the power/temperature domain for which it was identified.

B. PCB-Stack Models

To some extent, a model of the PCB-stack described in Fig. 3 is simple to build: the stack has flat external surfaces; the side surfaces can be considered adiabatic, heat only being exchanged through the bottom (heatsink) and top surfaces. In this way, only heat conduction has to be considered, with heat exchange coefficients as boundary conditions on the top and bottom surfaces. Here, the complexity comes from the internal structure, which is an intricate pattern of parts with different heat conductivities and thicknesses. Overall, there are 12 copper layers in the stack, many copper vias through the substrate layers, and large parts of ferrite material. The complete FEM model of such a structure would require a very fine mesh (with many elements measuring only a few microns). Two approaches are proposed below to generate models: the first only uses a coarse approximation of the copper layout, with the objective to offer acceptable results with a low computation time, while the second considers the actual copper layout (albeit with the finer features removed). Both models are built and simulated using COMSOL.

1) Approximated layout model: Here, each layer of the PCB stack is represented by a unique prismatic block, with an in-plane thermal conductivity set depending on the layout of that layer. Two cases are considered here: either a layer mainly comprises large copper planes, or it mainly contains thin tracks. Indeed, heat is going to spread much more over a plain copper layer (in this case, in-plane conductivity is considered to be that of copper, 400 W/(m K)) than in the case of a copper layer with thin PCB tracks covering only a small part of the surface (in-plane conductivity set at 0.3 W/(m K), that of the substrate). For the substrate layer, an area with a high concentration of copper vias will increase the thermal conductivity in the z-axis. This model has a relatively low number of elements (300 000).

The thermal conductivity of the substrate layer is 0.3 W/(m•K). For a substrate layer with a high concentration of vias, the z-axis thermal conductivity is increased to 50 W/(m•K) [START_REF] Regnat | Silicon carbide power chip on chip module based on embedded die technology with paralleled dies[END_REF], while the thermal conductivities in the x-axis and y-axis remain the same. The thermal conductivity of the copper is 400 W/(m•K) in all directions for a plain layer. For a layer with only thin PCB tracks, the in-plane conductivities are considered to be those of the substrate layer (0.3 W/(m•K)). The heatsink is only represented by its aluminium baseplate (4 mm-thick with λ= 237 W/(m•K)). These anisotropic thermal conductivities are summarized in table I.

The boundary conditions are: a constant heat exchange coefficient on the top (h=12 W/(m 2 K), calculated as the sum of natural air convection on a horizontal plane and heat radiation, for a 7×7 cm surface at 125 • C [START_REF] Annaratone | Engineering heat transfer[END_REF]); the heat exchange coefficient from Fig. 8 on the bottom; adiabatic condition on the sides; an ambient temperature of 60 • C. Heat is dissipated in the high and low frequency SiC dies and in the inductor. The power dissipated in each element is given in Tab. II (the calculation of these values is presented in [START_REF] Le Leslé | Optimisation of an integrated bidirectional interleaved single-phase power factor corrector[END_REF]).

The structure of the model is presented in Fig. 9. Some results are presented in Fig. 10.

2) Detailed layout model : For this model, we directly import the detailed layout description (ODB++ file format generated from the PCB design software -Altium Designer) to build a 3D model in COMSOL. In order to simplify the model, the tracks and corresponding vias associated with the driver board are removed (the thermal vias of this board are kept). This model has 1 500 000 elements. The copper areas for the power and ground net are represented with their real layout. In this model, all thermal conductivities are isotropic.

As for the approximated layout mode, the baseplate of the heatsink and the different TIM layers are added to the model. All other simulation parameters (boundary conditions, material properties, etc.) are identical. Some results are given in Fig. 11.

C. Simulation Results

The results are listed in Tab. III. Both models predict that the junction temperature of the high frequency dies is close to 129 • C, while that of the low frequency dies is close to 115 • C (in this converter topology, half of the semiconductor dies are switching at 180 kHz while the second half only switches at the mains frequency, i.e. 50 Hz). For the inductor, the detailed

V. THERMAL EXPERIMENT

The objective of the thermal tests presented here is to assess the accuracy of the thermal models. In these tests, a set amount of power is dissipated by the SiC dies and the inductor, and the corresponding temperature inside the PCB stack is monitored using Resistance Temperature Detectors (RTDs) embedded in the PCBs. The experiment is performed in two stages: first a calibration step allows to set the dissipated power level for the inductor, for which it is difficult to directly measure the dissipated power. In a second stage, a complete PFC cell is submitted to the same power dissipation, and its internal temperature is recorded using the RTDs.

A. Calibration of the Dissipated Power

The test circuit diagram used to dissipate power in the dies and inductor is presented in figure 12. Wires are soldered to the drain, source and gate of each die. The gate and the drain of each transistor are shorted together, so they can be considered as dipoles. This configuration allows to easily control the power dissipation in a transistor with a single power supply (in our case, two Source and Measure Units -references 2636 and 2602 -from Keithley, each having two independent channels as well as precision ammeters and voltmeters). Furthermore, as the transistors have a threshold voltage of around 3 V, a realistic power dissipation can be achieved with with the moderate current level the sources can supply (3 A), which also has the advantage of limiting joule heating in the interconnects.

For the inductor, because (active) power dissipation is very small compared to the (mostly reactive) power involved, direct measurement of the dissipated electrical power would not be accurate. Instead, and indirect approach is chosen: calorimetry. Calorimetry is a simple and accurate way to measure losses. For that, the inductor is placed in a calorimeter (Figs. 14a and14b) and supplied using an amplifier (AE Techron 7226) with a 70 kHz sinewave. This frequency is chosen to obtain the highest possible power dissipation, considering the limitations of the amplifier. The calorimeter is composed of an enclosure which ideally should be adiabatic (in our case a Dewar jar with a plastic lid). A calibration resistor, the Device Under Test (DUT) and a RTD (connected to a Keithley 2700 precision multimeter) are placed in the enclosure, and immersed in a dielectric liquid (Novec 7500, 3M). This fluid is chosen because of its relatively low toxicity, its high boiling point (128 • C), its chemical and electrical compatibility with power electronics, and because it does not leave any residue after drying. A stirrer ensures a homogeneous temperature distribution of the bath.

The principle of this measurement setup is first to estimate the total heat capacity (m i • C i ) of the liquid bath and all the elements it contains by dissipating a set amount of energy using the calibration resistor and measuring the corresponding temperature rise of the bath. After this calibration phase, the DUT is operated for a set amount of time, and the corresponding temperature increase of the bath is measured again, this time to calculate the losses P . Figure 13 presents an example of the bath temperature during the losses measurement step. For both steps (calibration and measurement), eq (2) is used.

P = (m i • C i ) • ∆T t (2)
The measurement error with this setup is estimated at 4.49 %, and mainly comes from the manual control of the heating time (±1 s). This is considered sufficient in our case. In addition, note that calorimetric measurements are performed at a bath temperature of ≈ 30 • C, and that inductor losses will increase with temperature for a constant excitation signal. This effect, however, is not taken into account here.

B. Measurement of the Internal temperature

For the thermal test, a PFC cell is assembled and raised a few centimeters above the work surface to allow air flow in the heatsink placed on the bottom. The ambient temperature is 30 • C. The Board-to-Board interconnects are replaced with thin wires to connect the dies and inductor according to

C. Experimental Results

The losses generated in each element are presented in Tab. IV. These values are lower than those estimated during the circuit design stage (Tab. II) due to limitations with the amplifier and the SMUs.

The temperatures inside a PFC cell are measured with 6 RTDs (PT1000 in this case). 4 RTDs are placed in the driver board, directly above the MOSFET dies. The 2 remaining RTDs are placed in the inductor PCB, one in the center and the other at the exterior of the inductor. The measured ∆T (temperature difference with the ambient temperature, measured at 30 • C) are presented in Tab. V, along with the values calculated in the same conditions (same power dissipation, same ambient temperature) using the thermal models described above.

VI. DISCUSSION

Overall, the results given in Tab. V show a very good agreement between experiment and simulation. In particular, the ∆T for the RTDs above the dies (LF and HF) falls inbetween the values predicted by both models. The maximum error for both models is 1.8 • C, which can be considered small in comparison with ∆T (>30 • C).

For the RTDs located around the inductor, there is more difference between measured and simulated values (up to 4.9 • C). Furthermore, simulation results tend to systematically overestimate the temperature. This is particularly true for the "Approximated layout" model. This model does not consider the vias which form the inductor winding (Fig. 2). This may explain the higher temperature predictions. Also, for both models, a constant heat exchange coefficient value is considered on top of the PCB stack. This coefficient, however, is highly dependent on the temperature difference with the ambient.

The "Detailed layout" model tends to give results which are closer to the experiments, despite the simplifications which were performed to obtain an automated mesh. The computation time is 30 min. An advantage of this model is the ease to describe the geometry of the board, as it is directly imported from Altium Designer. However, a manual alteration of the layout is still required to remove the finest tracks and some vias to make it compatible with automated meshing. The "Approximated layout" model tends to result in slightly larger errors, which remain acceptable for the dies. Its computation time is smaller (2 min). An advantage of this model is that its generation can be automated (by calculating the copper fraction of each layer and the density of vias from the layout files).

In conclusion, both models generate satisfying results. The "Approximated layout" model is especially attractive. Indeed, it makes it possible to compute the accurate temperature distribution of a complex PCB stack in a few minutes. A possible refinement of this model is to consider subdivisions of each layers (for example 1 cm 2 areas), each with their own thermal conductivities (to better match the layout of the boards). This would not require more elements in the mesh (for this model, the element size is dictated by the layer thickness, so that the element form factor remains acceptable), and would therefore not take longer to simulate.

Regarding the simulations presented in section IV-C (i.e. with the power dissipation level predicted by the circuit simulation and a worst case ambient temperature of 60 • C), the thermal models predict that all components remain at acceptable temperatures. The high frequency dies, which are the hottest points in the structure, are far from their quoted maximum junction temperature (175 • C). The gate driver IC, which has a maximum temperature of 125 • C, runs closer to its limits, with a calculated temperature of 123.8 • C. Running so close to the limit might be an issue, as it removes any safety margin for overload operation. A design iteration could be performed, based on the FEM simulations, to move the gate drivers to a milder place on the same PCB. In our case, in the absence of specifications regarding overload or other extreme operation cases, we consider that the current design meets the specifications. VII. CONCLUSION A 3.3 kW AC/DC bidirectional converter stage has been implemented using 3 different boards: one for the semiconductor dies, one for the gate drive circuits, and one for the inductor. The manufacturing process has been described. To form a converter, all three boards were stacked on top of a heatsink.

Two modeling approaches were proposed for the stack: one is based on a simple approximation of each layer of the board, while the second considers a more accurate description of the board layout. Both models have been compared to experimental results, and show a good accuracy, especially for the dies). Regarding the inductor, the error is larger (up to 4.9 • C difference between simulation and experiment).

Applying these models to the expected operating conditions of the converter show that the components temperatures should remain within specification. This is true despite the poor conductivity of the PCB substrate material and the thickness (≈ 1 cm) of the PCB stack. This demonstrates that with careful implementation, PCB embedding technology may be used for medium-power converters.

Figure 2 :

 2 Figure 2: Drawing of an "Embedded Toroidal" inductor. The dielectric layers are not show.

Figure 3 :

 3 Figure 3: Cross section of a PFC cell. The PCBs thicknesses are exaggerated with regard to the heatsink thickness and of the width of the boards. The components and layout in the drawing are only illustrative..

Figure 4 :

 4 Figure 4: Exploded view of a PFC cell.

Figure 5 :

 5 Figure 5: Manufacturing step for the panel with embedded dies: "Thin PCB". Dark orange denotes copper; light orange denotes prepreg, i.e. un-cured glassepoxy layers which are cured during the lamination process; green denotes cured glass-epoxy layers.

Figure 6 :

 6 Figure 6: X-ray image of an embedded SiC die (white outline of the die and pads added for clarity), showing the microvias drilled on both sides.

Figure 7 :

 7 Figure 7: Manufacturing step for the panel with both embedded SMT components and magnetic cores: "Thick PCB".

Figure 8 :

 8 Figure 8: Simulation results of heat transfer coefficient as a function of the temperature of the heatsink, considering convection and radiation effects, for an ambient temperature of 60 • C.

Figure 9 :

 9 Figure 9: Stack-up used in the "Approximated layout" model.

Figure 10 :

 10 Figure 10: (a) Geometry of the "Approximated layout" model. A symmetry is used to reduce the computation time. Temperature plots over planes cutting through (b) the HF die and the center of the PCB, (c) the LF die and the center of the PCB and (d) the diagonal of the PCB.

Figure 11 :

 11 Figure 11: (a) Geometry of the "Detailed layout" model. Temperature plots over planes cutting through (c) the top HF die and the bottom LF die, (c) the bottom HF die and the top LF die and (c) a diagonal of the PCB.

Figure 12 :

 12 Figure 12: Circuit diagram of the thermal experiment.

Figure 13 :Figure 14 :

 1314 Figure 13: Bath temperature as a function of the time for the losses measurement step. The temperature difference between the two dashed lines corresponds to the temperature increase due to the operation of the DUT; the downward slope of the dashed lines is caused by heat leaks of the "adiabatic" enclosure.

Fig. 12 .

 12 Fig.12. The power sources (in particular the AC amplifier) are set as for the calibration phase. The RTDs are monitored using a Keithley 2700 multimeter, and the temperature values are recorded after a 30 min delay.

Table I :

 I Thermal conductivities of the different layers for the "Approximated Stack-up" thermal model.

	Layer Name	Thermal Conductivity (x,y,z) (W/(m•K))
	Copper Layer : Plane Copper Layer : PCB Traces Substrate layer : Standard Substrate layer : Vias TIM (Sil-Pad 1500 ST, Bergquist) Baseplate Ferrite	λ = (400, 400, 400) λ = (0.3, 0.3, 400) λ = (0.3, 0.3, 0.3) λ = (0.3, 0.3, 50) λ = (1.8, 1.8, 1.8) λ = (237, 237, 237) λ = (5, 5, 5)

Table II :

 II Losses in each power element of a PFC cell for the converter at nominal power (as estimated during the circuit design stage[START_REF] Le Leslé | Optimisation of an integrated bidirectional interleaved single-phase power factor corrector[END_REF]).

	Dissipating element	Losses (W)
	High Frequency Die (Per die, 2 dies per cell) Low Frequency Die (Per die, 2 dies per cell) Inductor (One inductor per cell)	5.83 W 0.81 W 8.25 W

Table III :

 III Temperature comparison for both models.

			Standard Substrate Copper Plane Copper PCB Tracks Substrate With Vias TIM Aluminium	h=12 W/(m².K) h=17.29 (ΔT) 0.308 (Fig. 7)	} } } }	Heatsink Baseplate Dies PCB (0.7 mm-thick) Driver PCB (4.5 mm-thick) Inductor PCB (4.5 mm-thick) TIM (0.2 mm-thick) TIM (0.2 mm-thick) TIM
	Name	Approximated Layout	Detailed Layout
	HF Die LF Die Magnetic Core	129.1 • C 115.8 • C 121.4 • C	128.2 • C 115.6 • C 125.5 • C

Table IV :

 IV Losses generated in each power element of a PFC cell for the thermal tests.

	Dissipating element	Losses (W)
	High Frequency Die (per die) Low Frequency Die (per die) Inductor	4.00 W 0.81 W 2.00 W

Table V :

 V Comparison of the temperature difference (∆T ) between the RTDs and the ambient obtained by experiment and simulation.

	RTD location	Experiment	Approximated Layout	Imported Layout
	HF Die RTD	36.8 • C 35.3 • C	35.2 • C	37.6 • C 37.1 • C
	LF Die RTD	33.8 • C 33.3 • C	33.6 • C	34.1 • C 34 • C
	Outer Ind. RTD Inner Ind. RTD	27.3 • C 30.2 • C	32.2 • C 32.8 • C	30.9 • C 31.2 • C

From 2000, he was a Lecturer with the University of Birmingham, where his research activities focused on power electronics applications in the field of autonomous systems, aerospace electrical systems, and renewable energy sources and storage. In 2005, he joined ADETEL Group, France, as a Power Electronics Expert, working on transportation applications. In 2009, he joined THALES Avionics as a Power Supply Expert. Since 2013, he has been the Head of the Power Electronic Systems Division, Mitsubishi Electric R&D Centre Europe, Rennes, France. His current interests lay in physics of failure, health and condition monitoring and highly integrated converters.


C Buttay

C Martin

C Joubert

H Morel

B Allard

P Bevilacqua

M Cabrera

P Lombard

O Avino-Salvado

T Wickramasinghe

R Caillaud

M Beye

Benefits of GaN transistors and embedding in PCB laminates

Keywords: high temperature power conversion, wide-band-gap semiconductors, magnetic devices, dielectric devices, polymer substrate, embedding

More electrical vehicles, either automotive or aeronautics, should benefit of the electrical performances of GaN power transistors. High-speed switching opens the possibility for higher switching frequency and the consequential benefit on the size of passive components. Efficiency and power density should be improved by overcoming some strong challenges. Reducing the parasitic components within the switching cell is a prime concern. Embedding transistors has been experimented, with a special care given to the issue of thermal management. Multiple chips per switch may be necessary to address medium power applications but paralleling GaN transistors is not straightforward. A multi-phase converter architecture may circumvent the latter problem, as PCB technology is especially suited to managing complex interconnnects. Embedding not only the active devices, but also the passive components may introduce additional degrees of freedom. If a proper design approach is considered and some limitations are reasonably taken into account, combining the advantages of GaN transistors and their embedding technologies is promising solution. The paper proposes a review of the state of art and discusses some specific results to support the pros and cons of mixing GaN transistors and embedding in printed circuit board.

Introduction

Electrical vehicles (EV or HEV), including aircraft and ships, are the grounds for advanced developments in terms of electrical network. Advances are comparable in diversity, constraints and objectives as those related to smart grids. An electrical network is an assembly of software and hardware components (Fig. 1,[1]). Different schematics may be appreciated depending on the issues to highlight. In Fig. 2, the network aspect is more obvious with the exchanges of information and energy between components. Buried in many places inside such a network are power electronic converters, either DC/DC or AC/DC, or any combinations. There is a considerable momentum towards more efficient converters within a lower volume or lighter technologies with a target of cost and easiness of design. Figure 2: Example of brake-by-wire network point-ofview [START_REF] Ramesh | Brake by wire[END_REF].

Gallium-Nitride transistors are supplanting Silicon-Carbide transistors in automotive applications as an acceptable cost of these devices is foreseen. Further, multiple manufacturers are pushing for better performances to circumvent possible limitations like a questionable ruggedness or smaller lifetime than their silicon counterparts. GaN transistors enable a higher frequency of operation with a benefit on the size of passive devices. A GaN High Electron Mobility Transistor (HEMT) is capable of very fast switching. This capability comes with now well-known issues. The switching cell configuration must exhibit the lowest possible parasitic components, mainly the inductive stray inductance, the effect of magnetic coupling or the common-mode capacitances. When stimulated, these parasitic components create over-current and over-voltage stresses along with high dI/dt and dV/dt. Electro-Magnetic Interferences are exacerbated and filters must be implemented, increasing the cost of the power density and weight. The paper summarizes several activities performed at Ampere-lab about GaN-based power conversion. Section 2 introduces a simple example to show the benefits of GaN HEMTS but also inherent limitations. Section 3 introduces the issues related to paralleling of GaN transistors. Embedding of active devices and passive devices appear then as a possible degree of freedom to alleviate critical limitations. Section 4 describes what can be achieved when using embedding of interconnects and devices. To save cost and be compliant with conventional fabrication tools, a specific design approach is necessary that is introduced in Section 6.

A textbook example

A test vehicle is presented to highlight the interest of GaN HEMTs compared to their silicon counterparts [START_REF] Sarrafin-Ardebili | Quad Driver for GaN transistors based Dual Active Bridge with capacitive coupling[END_REF][START_REF] Sarrafin-Ardebili | New structures for multicellular conversion based on GaN transistors[END_REF]. The vehicle explores a standard dual-activebridge (DAB) for a low voltage application (Table 1)

Table 1: Main specification for the vehicle in Fig. 6.

A N-MOSFET implementation is shown in Fig. 3. A conventional transformer is selected but it is not the limiting component regarding losses. Transistors are subject to large switching losses at 500 kHz and a maximum efficiency of 92.2% could not be exceeded, regardless of the optimization effort. A GaN HEMT version is characterized with no particular layout strategy, except a sufficient convection area underneath each transistor (i.e. a thermal-option limited design) (Fig. 4). Schottky diodes are inserted and reverse conduction of transistors is avoided. Efficiency is thus improved even at 1 MHz, a frequency only limited by the magnetic material and transformer design (Fig. 4, Table 2).

Reverse conduction of GaN HEMT may be introduced. Schottky diodes are removed at the expense of some additional losses (Table 3). At low voltage a diode-less converter may be safely considered.

If a galvanic insulation is not mandatory in the application, the magnetic transformer may be replaced by a series resonant impedance (Fig. 5). Table 3: Performance indicators of the converter in Fig. 4 without Schottky diodes.

Table 4: Performance indicators of the capacitivecoupling converter in Fig. 5 without Schottky diodes. Table 4 lists the performance indicators and both the power density and efficiency are improved. At this stage a possible optimization is to reduce the footprint of the bridges using a quad driver instead of two phase-leg drivers. When pre-designing the quad driver, an electrothermal simulation indicates a limitation due to the convection approach to cool the HEMTs: the driver is directly in the thermal flow. An alternative layout must be considered or a hightemperature quad driver.

One other major limitation has not been mentioned so far: the fast switching of GaN HEMT (50 V/ns) introduces a lot of EMI issues that disturb the drivers and finally limit the operating frequency [START_REF] Sarrafin-Ardebili | Analysis of Gate-Driver Circuit requirements for H-Bridge Based Converters with GaN HFETs[END_REF]. Parasitic components along the power switching loop (switching cell) is a well-known issue. The distance between devices causes stray inductances, which in turn are stimulated by the electromagnetic energy they capture. The minimal loop area is quickly obtained in a planar configuration (Fig. 8a) [START_REF] Letellier | Power conversion based on wide bandgap devices[END_REF]. The concept of orthogonal loop is the other strategy to reduce the loop area, i.e. the electromagnetic energy stored in the loop during operation. Options in Fig. 8b and 8c have been explored in [START_REF] Letellier | Power conversion based on wide bandgap devices[END_REF]. The thickness of the polymer substrate is the limitation in Fig. 8b, while an application specific polymer substrate may be considered in Fig. 8c. Embedding of active devices is in fact exploring the same idea but with more degree of freedom, as layers of interconnection are managed underneath and above the active devices. The HEMT gate loop is affected by the same limitation as illustrated in Fig. 9. The energy is exchanged between the decoupling capacitor of the driver, the driver and the gate-source path. The area of this loop must be minimized as well. Some options of interconnection are illustrated in Section 4. The next section discusses the issue with respect to paralleling GaN HEMT, i.e. the antagonism between a reduction of switching loop area and multi-chips per switch for a higher current rating. Figure 9: Schematic of the HEMT control loop (dashed blue).

Paralleling GaN HEMTs

The main concerns related to paralleling GaN transistors are based on the package and board level design. Layout arrangement of many parallel devices can affect the current distribution among them. A simple H-bridge circuit (as the schematic diagram in Fig. 10) is implemented to investigate the parallelization of four GaN HEMTs in a single switch.

The layout is designed to take advantage of the footprint of the GaN transistor packages. The package used here (GS66516T, GaN Systems) is suited to a line configuration. However, current distribution among GaN devices is subject to parasitic components in each power trace. In a line configuration as shown in Fig. 11, the distance to drain input of the far-end GaN device from a singlepoint power supply is noticeably longer than for the devices in the middle. If all transistors use the same gate signal for their operation, devices may not handle the same level of stress. At turn-on, the device with low impedance in the path handles more stress than the rest. And at turn-off the device with high impedance remains active a longer time, hence carrying more current stress.

As observed in the thermography of Case 1 (see Fig. 12), a quite fair distribution of temperature is observed but some discrepancy is installed with higher input voltage and higher output current.

A more symmetrical layout may be considered where the GaN HEMTs are arranged on both sides of the PCB as illustrated in Fig. 13. This arrangement is possible as the thermal pads of GS66516T devices are on the top side of the package.

The power path can be optimized further by a more compact layout of the components. Though the thermal distribution among the components in the circuit is fairly equal, the parasitic components in the gate control path seems to trigger high frequency oscillations in the current and voltage waveforms. The switch transient current of each device at high frequency operation could be measured using high bandwidth coaxial shunts. However, the approach adds more parasitic elements to the power path and degrade the quality of the final results. A detailed analysis of the optimizing board level parasitic components can be found in [9].

So far the results tend to demonstrate that a standard planar substrate is somewhere a limitation in power device arrangement. This is the reason why embedding in the polymer substrate has received a large attention.

Embedding in polymer substrate

Fig. 15 gives a tentative schematic for a half-bridge configuration (650 V, 25 A) with a fair power density.

Looking at the various functions, it appears that the auxiliary power supply (i.e. the power supply of the gate drivers) becomes a limiting factor. A resonant flyback configuration with an active clamp has been explored in [START_REF] Perrin | Characterization and Design of High-Switching speed Capability of GaN Power Devices in a 3-Phase Inverter[END_REF] with high temperature capability. One practical solution to meet the footprint specification has been to limit the operating frequency of the flyback converter but to embed the coupling inductances in the polymer substrate, including the magnetic material. A zoom on a cross section of the magnetic core is pictured in Fig. 16, with the substrate obtained from laminated pre-preg from Panasonic, dedicated for continuous operation at +200°C.

Embedding gives a degree of freedom in terms of geometry and the coupling inductors were designed for a minimal capacitive coupling (0.85 pF @ 1.2 MHz) to enable a dynamic isolation up to 75 kV/µs at the driver level [START_REF] Perrin | 2 MHz high-density integrated power supply for gate driver in high-temperature applications[END_REF]. Such immunity to fast voltage transients is required to take full advantage of the GaN power transistors. Two flavors of the converter have been characterized: one is using low-voltage GaN HEMT (Fig. 17a) and the other one encompasses a silicon power ASIC (Fig. 17b). The silicon counterpart is limited in frequency but the efficiency is somewhat higher at the expense of a larger footprint. The GaN HEMT based converter could be optimized for a similar targeted efficiency without losing on the footprint area.

A tentative design approach

While embedding is a very attractive solution to increase power density, reduce circuit parasitics and provide suitable thermal management to PCBmounted power electronics, it is currently complex to implement. Despite the research efforts invested in modelling and simulation, the design of a power electronics converter still pretty much relies on trialand-error on hardware prototypes.

The reason for this may be found in the heterogeneity of power electronics, which are an assembly of custom, semi-custom and off-the shelf components supplied from many vendors, most often assembled together using a variety of technologies (PCB, busbars, loose wires…). This is depicted in Fig. 18. As a consequence, there is no unified software description of the converter (complete virtual prototype). In many cases, not all models are compatibles, and only a small subset of the converter can be simulated at a time. This is quite different from the situation in microelectronics, where monolithic integration is standards, and electronic design automation (EDA) software allows advanced simulations and design verification prior to manufacturing. PCB embedding may help to improve the situation (Fig. 19): this is a unified manufacturing technology which can provide satisfying thermal performance (at least up to a few tens of kilowatts [START_REF] Boettcher | 3D Modular Power Electronic Systems, based on Embedded Components[END_REF]), can manage complex interconnects (multilayer circuits, high density interconnects technologies), and which builds upon an existing base of advanced design software tools and a mature PCB industry. Therefore, it becomes possible to build a performant converter using a single technology, and the entire converter can be described and modelled from the data available in the PCB layout software. There is still a long way to go, but PCB embedding may offer the first opportunity to demonstrate a full "virtual prototype" in power electronics. This will become a necessity, because embedding tends to make prototyping more complex (it is a new technology, so a lot of preparation work is required prior to manufacturing) and its high level of integration makes measurements and debugging more difficult (and this is not to mention circuit repair or modifications which are near to impossible).

Figure 19: Rationalized manufacturing flow, where all the assembly is taken care of using PCB embedding (as well as standard PCB assembly) [START_REF] Buttay | Application of the PCB-Embedding Technology in Power Electronics --State of the Art and Proposed Development" 3D Power Electronics Integration and Manufacturing (3D-PEIM)[END_REF].

Conclusion

GaN HEMTs open a degree of freedom to the power electronic engineer but with large constraints. Other degrees of freedom must be considered to solve issues regarding interconnects to and from the power transistors and to and from the passive devices.

Embedding in polymer substrate is one candidate technology to take full advantage of the performances of GaN devices.

Figure 1 :

 1 Figure 1: Possible schematic of the electrical network in an electrical vehicle [1].

Figure 3 :

 3 Figure 3: N-MOSFET DAB on a two-layer FR4 board.

Figure 4 :

 4 Figure 4: GaN HEMT DAB with Schottky freewheeling diodes on a two-layer FR4 board

Figure 5 :

 5 Figure 5: Diode-less, GaN HEMT DAB without a magnetic transformer.

Figure 6 :

 6 Figure 6: Schematic of a quad driver for synchronous operation of the GaN HEMTs.

Figure 7 :

 7 Figure 7: Electro-thermal simulation of the quad driver environment.

Figure 8 :

 8 Power loop in a half-bridge configuration: planar (a), orthogonal (b) and (c)[START_REF] Letellier | Power conversion based on wide bandgap devices[END_REF].

Figure 10 :

 10 Figure 10: Schematic diagram of the test prototype.

Figure 11 :

 11 Figure 11: Case 1: four GaN HEMTs in parallel configuration. HEMTs are laid in a line.

Figure 12 :

 12 Figure 12: Thermography of the Case 1. Input voltage 80 V, load current about 27 A, switching frequency 200 kHz.

Figure 13 :

 13 Figure 13: Case 2: four GaN HEMTs in parallel configuration. Two HEMTs are laid on each side (i.e. top and bottom).

Figure 14 :

 14 Figure 14: Thermography of the Case 2: (left) top side and (right) bottom side of the PCB. Input voltage 80 V, load 27A.

Figure 15 :

 15 Figure 15: Footprint of the gate driver power supply inside a tentative half-bridge configuration.

Figure 16 :

 16 Figure 16: Cross section of the embedded flyback transformer, showing the magnetic core and the copper windings.

Figure 17 :

 17 Figure 17: Resonant flyback with an embedded magnetic device and performance indicators.


Rémy Caillaud

Johan Le Lesl É †

Cyril Buttay
email: cyril.buttay@insa-lyon.fr

Florent Morel

Roberto Mrad

Nicolas Degrenne

Stefan Mollov

Evaluation of the PCB-embedding technology for a 3.3 kW converter

This paper presents a converter fully made using PCB embedding technology (including the semiconductor devices, but also their gate driver circuits as well as the passive components). This converter is rated at a high-power (3.3 kW) considering the PCB technology. Here, the focus is given to the experimental validation of the embedding process, with the characterization of many of the embedded devices (SiC MOS-FETs, diodes, capacitors). These results show that most of the components were unaffected by the process, with the noticeable exception of the large inductors which exhibit variations in the inductance values as well as a large ac resistance. Finally, the converter is successfully assembled an tested at low power.

I. INTRODUCTION

This article presents the implementation of a 3.3 kW, bidirectional, ac/dc converter which could be used, for example, as part of an on-board battery charger in an electric vehicle (in this case, the bidirectional energy transfer capability could be used for vehicle-to-grid [START_REF] Tomić | Using fleets of electric-drive vehicles for grid support[END_REF]). The circuit design of this converter is presented in [START_REF] Le Lesle | Optimisation of an Integrated Bidirectional Interleaved Single-Phase Power Factor Corrector[END_REF]. Here, we focus on the integration technology used to actually build the converter: PCB embedding.

Embedding components within a Printed Circuit Board (PCB) is a relatively recent technology [START_REF] Ostmann | Evolution and future of embedding technology[END_REF]. It is particularly attractive for power applications, as it allows to reduce the inductance of the interconnects or to provide better cooling. Detailed reviews of this technology are given in [START_REF] Alderman | 3-D Embedded Packaging Technology[END_REF], [START_REF] Buttay | Application of the PCB-Embedding Technology in Power Electronics -State of the Art and Proposed Development[END_REF]. It consists in inserting components in the material stack used to form multi-layer PCBs, prior to the lamination process. Afterwards, connections are formed with the embedded components using microvias (laser-drilled holes filled with electroplated copper).

Semiconductor chips are especially good candidates for embedding, because they experience the fastest current changes and the highest power density in a converter. In [START_REF] Boettcher | 3D modular power electronic systems, based on embedded components[END_REF], the authors present the embedding of SiC power dies. Thermal performance is increased through the use of ceramic or thick copper layers. Regarding circuit parasitics, a very low value of loop inductance (0.43 nH) is achieved to connect GaN transistors in [START_REF] Savulak | Three-phase inverter employing PCB embedded GaN FETs[END_REF], thanks to PCB embedding. Many other publications on this topic are listed in [START_REF] Buttay | Application of the PCB-Embedding Technology in Power Electronics -State of the Art and Proposed Development[END_REF].

Beyond power semiconductors, it may be interesting to embed other components. In particular, magnetic components can be made by embedding a solid ferrite core [START_REF] Ali | Design of a hybrid integrated EMC filter for a DC-DC power converter[END_REF], some ferrite powder [START_REF] Caillaud | High power PCB-embedded inductors based on ferrite powder[END_REF] or thin sheets of amorphous magnetic materials [START_REF] Marxgut | Multiobjective optimization of ultraflat magnetic components with PCB-integrated core[END_REF]. Windings are then formed by patterning the copper layers of the PCB and drilling vias. In some cases, sheets of polymer loaded with magnetic particles can directly be laminated as part of a multilayer PCB [START_REF] Waffenschmidt | Design Method and Material Technologies for Passives in Printed Circuit Board Embedded Circuits[END_REF] instead of discrete magnetic cores. A similar approach can be used for capacitors, by stacking thin dielectric layers with high permittivity [START_REF] Andresakis | Embedded Capacitors[END_REF], but the capacitance density or voltage breakdown of such capacitors tend not to be suitable for power electronics [START_REF] Buttay | Application of the PCB-Embedding Technology in Power Electronics -State of the Art and Proposed Development[END_REF].

Finally, it is also possible to embed standard Surface-Mount Devices (SMDs) [START_REF] Alderman | 3-D Embedded Packaging Technology[END_REF], providing they are thin enough. This approach gives access to a very large catalog of components. In particular few integrated circuits are available in a bare die form that is compatible with direct embedding (which requires thick -10 µm-copper pads, with a relatively coarse pitch). Embedding packaged devices (or using an interposer between the chip and the PCB [START_REF] Kugler | Chip Embedding in Laminates[END_REF]) solves these problems, at the expense of a larger footprint. Multi-Layer Ceramic Capacitors (MLCCs) are another example of components which can be embedded, as they offer the capacitance values required in power electronics applications (micro-farads at several hundred volts).

The manufacturing technologies selected for our PFC converter are presented in the next section. Components were embedded in tests coupons, and then characterized to evaluate the consequences of the embedding process. The results are presented in section III. Finally, some test results of the complete converter are given in section IV and discussed in section V.

II. DESIGN AND MANUFACTURING PROCESS

The converter topology was chosen and optimized thanks to the procedures described in [START_REF] Le Lesle | Multi-objective optimisation of a bidirectional single-phase grid connected AC/DC converter (PFC) with two different modulation principles[END_REF], [START_REF] Caillaud | Comparison of planar and toroidal PCB integrated inductors for a multi-cellular 3.3 kW PFC[END_REF]. This resulted in a PFC converter with 4 interleaved cells, each switching at 180 kHz, rated at 825 W, and based on SiC MOSFETs (CPM2-1200-0080B, Wolfspeed). The circuit diagram of this converter is presented in Fig. 1.

The actual implementation of the PFC stage in a structure based on PCB embedding is shown in Fig. 2. It is comprised of 3 separate boards, stacked together and separated with layers of Thermal Interface Material (TIM) (Sil-Pad 1500 ST, Bergquist). Because of their power density, and because they are directly connected using microvias, the semiconductor dies are embedded in a dedicated, thin PCB located close to a heatsink. The other (packaged) components are soldered The embedding of the chips starts by gluing them onto a plain sheet of copper. Then, sheets of glass fiber impregnated with un-cured resin (prepregs) are stacked around the dies, followed by a second layer of copper. Vacuum lamination is then performed so that the resin flows to fill the voids and cures. Microvias are then drilled with a laser, and filled with copper to connect the drain, source and gate terminals of the MOSFETs. The copper layers are patterned using chemical etching to form the circuit layout. The microsection of an embedded SiC MOSFET is given in Fig. 3. A second lamination cycle is performed to bond two additional copper layers and form a 4-layer PCB. This is required to route all the signals, but also for mechanical strength (a thin, 2-layer board would be too weak for proper handling) and thermal management (more copper layers improve heat spreading).

The thicker boards ("Driver" and "Inductor", in Fig. 2) are made simultaneously on the same panel, as they share the same stack-up configuration. The manufacturing starts with a thin, two-layer PCB (MCL-E-679, Hitachi), which is patterned according to the desired layout. A contour of solder resist is printed where components are to be mounted. Components are then assembled using a standard soldering process (stencil printing/automated positioning/solder reflow). A set of prepregs and cured glass-epoxy sheets are then machined and stacked to make-up for the thickness of the components and of the ferrite cores; a second two-layer board is placed on top (to form a symmetrical structure and prevent warpage); the stack is then laminated under vacuum and through-all vias are formed to interconnect the 4 copper layers.

III. CHARACTERIZATION OF THE TEST COUPONS

Several test coupons were made for each part used in the converter (all PCBs presented here were manufactured by Cimulec, France). This includes relatively large ceramic capacitors, diodes, or SiC MOSFETs. The characterization of these test coupons, along with that of some components of the converter which could also be tested individually (for example, the SiC dies, for which all three terminals can be accessed), is presented below.

A. SiC MOSFETs

An X-ray image of an embedded SiC MOSFET is given in Fig. 4. In this image, the microvias appear as darker dots. The outline of the die is highlighted with black lines for clarity sake. It shows satisfying alignment of the vias, especially on the gate contact (500×800 µm 2 ).

The static characteristic of the MOSFET coupons was measured using an IWATSU CS-5400 curve tracer in 4-wire configuration. An example is given in Fig. 5. Overall, all 8 test coupons were characterized and showed similar characteristics. The main parameter, the on-state resistance (R DSon ) of the coupons is presented in Fig. 6a. The values are consistent with the R DSon quoted in the datasheet of the devices (80 mW,

I d s (A) V GS = 15 V V GS = 5 V V GS = 17 V
V GS = 10 V Fig. 5. Direct static characteristic of one of the SiC MOSFET coupons [START_REF] Wolfspeed | CPM2-1200-0080B Silicon Carbide Power MOSFET[END_REF]). Their slightly higher value can be associated with the interconnect resistance of the coupons (Fig. 6b), as the 4wire measurement configuration is not maintained up to the SiC MOSFET. In the off state, the drain leakage current of the MOSFETs remains well below the limits specified by the manufacturer [START_REF] Wolfspeed | CPM2-1200-0080B Silicon Carbide Power MOSFET[END_REF] (1 µA at 1200 V typical, 100 µA max.), as shown in Fig. 7.

Other measurements were performed (using a Keithley 2636A SMU), on the 8 MOSFET coupons as well as on the 9 PFC boards (each containing 4 SiC chips), for a total of 44 MOSFETs. Gate leakage current measurements were all found to be in the range of tens of pico-amperes, except for one device which has a gate leakage current of 250 nA at 20 V. The distribution of the threshold voltages (defined as the V GS value required to reach a drain current of 5 mA under a V DS of 5 V) is presented in Fig. 8, and is consistent with the datasheet of the devices.

Overall, no degradation of the MOSFETs was found after embedding, except possibly for one of the chips, which exhibited a higher (but still acceptable) leakage current.

B. SMD diodes

Three kind of SMD diodes are used in our gate driver circuit: two zener diodes (4.7 V and 15 V, On Semiconductor MMSZ52 series) for the regulation of the output voltage (-5/15 V), and one 600 V fast rectifier for the bootstrap power supply (VS-1EFU06HM3, Vishay Semiconductors). This latter diode has the biggest package (a SMF case, roughly 2.9×1.9×1.1 mm 3 ), while the two zener diodes are slightly smaller (SOD 123 case, 2.7×1.6×1.2 mm 3 ).

Forward and reverse characterization results for 4 coupons of each diode reference are presented in Fig. 9. They show consistent characteristics, which match the manufacturer's specifications. One 600 V diode failed during the characterization, but no conclusion was reached regarding the possible causes of failure.

C. Ceramic capacitors

Ceramic capacitors were selected for embedding, as they can sustain the high temperatures associated with the PCB lamination process (above 180 • C for 1-2 h). However, ceramic capacitors are brittle, and may crack when submitted to the lamination pressure. Cracks would then result in an increase in the leakage current in the capacitor. An example of the leakage currents measured on the capacitor coupons is presented in Tab. I (using a Keithley 2410 SMU, after 15 min biasing). The 500 V, 330 nF X7R capacitors (C1812W334KCRACTU, Kemet, 1812-size case) are used for decoupling of the dc bus, while the C0G 56 pF capacitors (C1206C560JCGACTU, Kemet, 1206-size case) are connected in parallel with the output capacitance of the SiC MOSFETs for soft-switching operation. Other lower-voltage capacitors were also investigated (such as those used in the bootstrap power supply of the gate driver), but they are not presented here as they offer similar results.

Compared to the reference (an identical capacitor not connected or mounted to any board), there is no noticeable increase in leakage current for any embedded capacitor.

D. Inductors

Inductors are the bulkiest component in our converter, as the magnetic cores alone are 50 or 63 mm in diameter (for the EMI filter and the PFC inductor respectively, both with a thickness of 3 mm). X-Ray images of two inductors are shown in Fig. 10. While most of the cores were found to be in good condition, such as that presented in Fig. 10a, some were found to be broken (Fig. 10b), possibly because of the pressure experienced during the lamination process.

However, broken cores might only partially explain the characterization results presented in Fig. 11: a large discrepancy is found among the inductance values (from 10 to almost 100 µH) and ac resistances exceed 10 W at the switching frequency of the PFC (180 kHz). This is an unacceptably high value for a converter cell rated at 825 W.

Several phenomenon seem to be involved in these disappointing results: the fringing magnetic field around the large airgap (Fig. 10a) induces strong eddy currents in the nearby copper windings [START_REF] Caillaud | Design, manufacturing and characterization of printed circuit board embedded inductors for power applications[END_REF]; broken and/or misaligned cores cause variations in the inductor behaviour; finally, current investigations seem to indicate that the inductor structure, with large, flat copper windings parallel to the core surface may intrinsically offer poor frequency performances.

IV. CHARACTERIZATION OF A PFC CELL

A photograph of a PFC cell is shown in Fig. 12. It corresponds to the structure shown in Fig. 2, with 3 stacked PCBs on top of a heatsink. 4 such cells are then assembled to form the interleaved PFC, as shown in Fig. 13a (in this case, electrolytic capacitors were used for testing instead of the PPB stage described in Fig. 1). Finally, the input EMI filter is presented in Fig. 13b.

As described in Section III, all components were found to operate satisfyingly after embedding, with the exception of the inductors. Therefore, it was possible to operate the converter, albeit at a limited power level. The current in the AC link of each PFC cell is shown in Fig. 14. While they exhibit satisfying sinus shapes, their amplitudes are noticeably different. This is because of the differences in inductor values described in section III-D. Replacing the embedded inductors with more standard planar inductors yielded a much better current balance, and allowed us to reach higher power levels. This is, however, beyond the scope of the present paper.

V. DISCUSSION AND CONCLUSION

Component embedding showed a very satisfying yield for a prototype run, with 43 SiC diodes out of 44 exhibiting good, consistent performances. The same conclusions were drawn for all the components, in particular regarding the gate drive board, which contains a few dozen components (a gate drive IC, a bootstrap power supply, some resistors and capacitors, as well as temperature sensors).

The main issue is related to the inductors, which are the largest component in the system. Even without considering the few of them that broke during the embedding (this should easily be solved in future manufacturing the performance of these components is not yet satisfying. In particular, they exhibit a very large ac resistance at 180 kHz. It is not sure whether this can be reduced down to acceptable levels, even by removing the copper windings close to the air gap.

Another issue with the embedded inductors is their very flat form factor, which results in a flat EMI filter (Fig. 13b). While such a form factor might be desirable in a few cases (for example, in [START_REF] Marxgut | Multiobjective optimization of ultraflat magnetic components with PCB-integrated core[END_REF], the authors presented a flat flyback converter intended for supplying flat displays), it is not the case of most applications, where a more compact outline is preferred. Stacking PCBs is possible, as demonstrated with the PFC cells, but it requires extra care regarding thermal management. Also, embedding all components does not really save space (in our case, the volume of the PFC cells is 0.69 L and that of the EMI filter 0.16 L), as the thickness of the entire board is dictated by the thickest component. A more compact option probably includes embedding some components, while some other are mounted on the surface, in a more traditional manner.

Fig. 1 .Fig. 2 .Fig. 3 .

 123 Fig. 1. Circuit diagram of the converter. Gray parts denote sections of the circuit which are duplicated: there are actually 3 common mode (CM) and differential mode (DM) stages for the EMI filter, and 4 PFC cells, each comprised of 4 MOSFET and inductor L P F C . The Power Pulsating Buffer (PPB) stage intended for DC filtering is not addressed in this article.

Fig. 4 .

 4 Fig. 4. X-Ray image of one of the embedded dies, showing the microvias used to contact the gate, drain and source terminals. Die size: 3.36×3.1 mm 2 .

Fig. 6 .

 6 Fig. 6. (a) R DSon of the MOSFETs coupons. (b) photograph of one of the SiC MOSFET coupons.

Fig. 7 .Fig. 8 .

 78 Fig. 7. Drain current in the off state (V GS = 0 V through one of the embedded SiC MOSFETs, as a function of V DS .

Fig. 9 .

 9 Fig.9. Electrical characterization of the diodes used in the bootstrap power supply circuit for the gate driver. The forward and reverse characteristics of all tested diodes are in agreement with their datasheet.

Fig. 10 .

 10 Fig. 10. X-ray images of two PFC inductors: (a) one in good condition and (b) one which cracked during lamination. Both magnetic cores are 63 mm in diameter, 3 mm-thick.

Fig. 11 .

 11 Fig. 11. Evolution of the inductance and of the resistance of the PFC inductors as a function of frequency, showing a dramatic increase in resistance and the discrepancy between supposedly identical inductors.

Fig. 12 .Fig. 13 .Fig. 14 .

 121314 Fig. 12. Photograph of one PFC cell (size 7×7×3.5 cm 3 ).


M Elmquist

A Gawer

P Le Masson
email: pascal.le_masson@mines-paristech.fr

Innovation Theory and the (Re-)foundation of Management: Facing the Unknown

Innovation Theory and the (Re-)foundation of Management:

Facing the Unknown

Setting the stage for this special issue

Within the management research community, the last few years have revealed a growing desire to focus explicitly on new discoveries and to challenge the very foundations of our discipline. This special issue addresses how innovation-management theories might enrich management science, helping to discover new phenomena and formulate research hypotheses with relevance for the entire discipline.

Contemporary managers face many challenges when shaping new industrial ecosystems, engaging with disruptive technologies, inventing new business models, or even re-inventing their own organizations. An interesting recurring theme in all these contexts is that they involve not just uncertainty, but facing the unknown. While uncertainty refers to events that are known, and whose probability of occurrence can be estimated (as inherited from statistical decision theory), the unknown denotes events that can be expressed conceptually, but can hardly be imagined, and therefore cannot be described. For example, tomorrow's weather is uncertain, but forms of extraterrestrial life are unknown. While uncertainty can be reduced (e.g. by statistical sampling), the unknown must be explored through an effort of imagination.

In innovation management, the way innovators relate to the future is closer to exploring the unknown. They don't regard the future as "uncertain," but as a matter that has to be shaped, transformed, named, and generally invented in a proactive way. This perspective could also be useful to general management.

Some innovation management concepts have already enriched mainstream management literature. "Organizational ambidexterity" [START_REF] Duncan | The ambidextrous organization: designing dual structures for innovation[END_REF][START_REF] Tushman | Ambidextrous Organizations: Managing Evolutionary and Revolutionary Change[END_REF][START_REF] Tushman | Organizational designs and innovation streams[END_REF][START_REF] Gibson | The Antecedents, Consequences, and Mediating Role of Organizational Ambidexterity[END_REF], which was initially proposed as a way of organizing for innovation, has more recently been acknowledged as a fundamental notion in organization studies [START_REF] Birkinshaw | Clarifying the Distinctive Contribution of Ambidexterity to the Field of Organization Studies[END_REF]. The concept of "absorptive capacity" has enjoyed a similar crossover. But despite these individual examples, innovation management has largely remained a "specialization," as illustrated by journal rankings in many countries, preventing it from taking root in management science. The purpose of this special Issue is to bring insights from innovation management to the very heart our discipline.

We now summarize the six papers included, before discussing how they contribute to (re-)visiting and (re-)founding management science with innovation theory.

Six contributions linking innovation management and management foundations

In "Understanding the invention phase of management innovation: a design theory perspective," Albert David examines the invention process of a single famous management innovation: Drucker's "Management by Objectives" (MBO) concept.

In "A century old and still visionary: Fayol's innovative theory of management," Armand Hatchuel and Blanche Segrestin revisit Fayol's legacy and argue that, contrary to previous analysis, Fayol positioned innovation at the very core of management science.

In "Contracting for the unknown and the logic of innovation," Anna Grandori and Marco Furlotti identify specific types of contracts for managing innovation, which they term "constitutional contracts."

In "The design logic of new business models: unveiling cognitive foundations of managerial reasoning," Dirk Schneckenberg and Vivek Velamuri uncover the cognitive processes used in creating innovative business models.

In "Experimenting in the unknown: Lessons from the Manhattan Project," Sylvain Lenfle and Thomas Gillier show that Thomke's model of experimentation was actually built for experimentation in uncertainty, and extend it to the unknown.

Finally, in "Designing decisions in the unknown: towards a generative decision model for management science," Pascal Le Masson, Armand Hatchuel, Mario Le Glatin, and Benoit Weil address the issue of designing decisions in the unknown.

(Re-)visiting and (re-)founding management science with innovation management

It is a privilege to be able to include, in just one issue, papers addressing the work of groundbreaking founders of management science such as Fayol [START_REF] Hatchuel | A century old and still visionary: Fayol's innovative theory of management[END_REF], Wald (Le [START_REF] Masson | Designing decisions in the unknown: towards a generative decision model for management science[END_REF], Drucker [START_REF] David | Understanding the invention phase of management innovation: a design theory perspective[END_REF], and Simon [START_REF] Grandori | Contracting for the unknown and the logic of innovation[END_REF]. These new papers will encourage our readers to reengage with the legacy that these great authors left to management science. The papers also provide a panorama of the management science discipline, from its historical roots (Fayol) to the most recent trends (business-model innovation), while revisiting key inflection points (e.g., Drucker). Last but not least, the papers adopt a trans-disciplinary perspective: even as they work towards the (re-)foundation of management science, they articulate its position in relation to other disciplines such as economics and sociology [START_REF] Hatchuel | A century old and still visionary: Fayol's innovative theory of management[END_REF]; re-examine its roots in statistics (Le [START_REF] Masson | Designing decisions in the unknown: towards a generative decision model for management science[END_REF][START_REF] Lenfle | Experimenting in the Unknown: Lessons from The Manhattan Project[END_REF]; and make use of cognitive science approaches [START_REF] Schneckenberg | The design logic of new business models: unveiling cognitive foundations of managerial reasoning[END_REF][START_REF] Masson | Designing decisions in the unknown: towards a generative decision model for management science[END_REF], legal concepts [START_REF] Grandori | Contracting for the unknown and the logic of innovation[END_REF], and design theory [START_REF] David | Understanding the invention phase of management innovation: a design theory perspective[END_REF][START_REF] Grandori | Contracting for the unknown and the logic of innovation[END_REF][START_REF] Masson | Designing decisions in the unknown: towards a generative decision model for management science[END_REF].

Beyond this rich panorama, there are three ways in which the six papers, taken together, contribute to the (re-)foundation of management science using specific concepts from innovation management.

1) Revisiting the classics First, the papers exhort us to revisit some classic notions of the management discipline. It is inspiring to see how each paper, taking the perspective of innovation management, uncovers new limitations of established theories and pushes research to go beyond the "common sense" of management. David discusses "Management by Objectives," often taken to be a self-evident notion. Hatchuel and Segrestin revisit Fayol's administrative theory, which is usually seen as the application of scientific rationality to administration. Grandori and Furlotti revisit a commonly admitted assumption-namely, that contracting in the unknown necessarily leads to an "incomplete contract." Schneckenberg and Velamuri explain that business models can no longer be considered a reference frame for how to meaningfully interpret information in contexts that include high levels of both complexity and novelty. Lenfle and Gillier revisit the notion of experimentation, which is usually considered a good way to reduce uncertainty. Finally, Le Masson et al. show that decision-making is not the only way to behave rationally. In so doing, they re-examine not only rational decision-making, but also its inherent dark side: the assumption that creativity is necessarily irrational.

2) New methods inspired by innovation-management research

A second contribution is that the papers propose a set of new methods, stemming from innovation management, to extend the classics. David and Le Masson et al. apply design theory to management classics: the invention of managerial notions (David) and the decision (Le Masson et al.). Meanwhile, the papers by David and Hatchuel and Segrestin rely on historical method and a genealogical approach to understand the evolution and dynamics of meanings.

3) New notions to extend the classics and (re-)found management science The third contribution may be the most important: by revisiting the classics, the papers don't just raise criticisms-they also propose new notions to extend classic ones.

For instance, David analyzes the unknown in management techniques-the paper shows how the design perspective uncovers the internal coherence of a managerial technique, beyond its multiple facets such as process, practice, instrument, organization principle, mindset, and performance logic. The author considers management as a design process and management innovations as the managerial artifacts that result from such design effort.

After discussing the limitations of contracts, which imply known outcomes and clear problems to be solved, Grandori and Furlotti propose a new notion. "Constitutional contracting" is adapted for facing "the unknown," and situations where "means are in search of uses." This new contractual type is procedural rather than substantive, constitutional rather than operational, and democratic rather than hierarchical.

Gillier and Lenfle propose new principles to extend the logic of experimentation in the unknown, based on the capacities to identify the unknown (not just the uncertain), to design new descriptors (and the formal models and theories attached to them), and to design the instruments to characterize these new descriptors.

Le Masson et al. propose a formal model to systematically map the design paths leading to the design of new decision options. The authors show that contemporary design theory can help us plot a systematic, rational path to design decisions in the unknown.

Finally, Hatchuel and Segrestin, revisiting Fayol's legacy, reveal that, for Fayol, management science is inseparable from innovation. Following Fayol, who put the logic of innovation at the heart of managerial action, management is necessarily a theory of creative/political rationality where collective action is structured by coping with the unknown. This suggests that management should be the science of "creative, scientific, economics and social advancements."

Management science as a science of the design of collective action

Of course, these six papers are but a small sample of all the efforts to link innovation theory and management science. Nonetheless, they invite us to develop this collective endeavor more systematically. They also remind us that modern management was created by innovators such as Taylor, Fayol, and Parker Follett (O'Connor 2000)-famous founders who did not just conceptualize and characterize new forms of collective actions, but even invented them. These works remind us that innovation was historically at the heart of management science-and that without innovation, management science would be locked into a spiral of imitation and reproduction.

Moreover, the work in this issue illustrates that innovation management today pushes us to revise and challenge the basic notions of management science. Previous discussions in management science have elaborated theory by building polarities, often corresponding to "theory" vs. "practice" or "optimal rationality" vs. collective heuristics and biases. But managing in the unknown obliges us to go beyond such polarities. We need a new rationality:

the design of new forms of collective action. These six papers help unfold this new paradigm of management science.

If management is about designing collective action, management science can be considered the science of inventing new organizational logics, new rationality, and new values. It is management science that discovers these things; conceptualizes them; perhaps even proposes them and helps experiment with them. This new paradigm is coherent with the essence of management science (see [START_REF] Hatchuel | Towards an epistemology of collective action. Management research as a responsive and actionable discipline[END_REF], which is neither a fixed repertoire of forms (and hence different from an "applied sociology") nor the direct consequence of rational optimization (and hence different from an "applied economics"). This new paradigm of management science also has a promising future, because it constitutes a "post-decisional" paradigm-one adapted to contemporary unknowns and the invention of new societies, new industries, new skills, new knowledge, and new dreams of the future.

We hope you will enjoy these six papers as much as we do, and that your insights and inspiration will repay the efforts of all the authors, reviewers, and editors who have worked so hard to produce this special issue. We owe them all a great debt of gratitude.