Magnus Rimskog

Tomas Bauer

M.Sc Mr Magnus Rimskog

Tomas Mr

M.Sc Bauer

High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 µm pitch for through wafer connections in up to 600 µm thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" -features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.

INTRODUCTION AND BACKGROUND

This presented via technology was developed in an environment consisting of a fully equipped 1000 m² state-ofthe-art 6" wafer fab. With regards to manufacturability, cost efficiency and simplified back-end, the via technology has great benefits. Packaging for example is often considered a limiting factor when quickly taking a product from design concepts to working prototypes and the following volume manufacturing. Following the general trend, there is a need to continuously work on developing proprietary MEMS foundry processes, leveraging on intellectual property and know-how to complement the standard manufacturing capability. The via technology is an excellent example of such MEMS process enabling true wafer level packaging and MEMS designs with significantly reduced form factor. The technology has already been applied to a diverse range of products, and while not offering any own products to the market, a MEMS foundry is in a unique position to promote the benefit of the technology to a wide range of applications. The via technology as presented here is applied to a number of different types of products from low volume applications to high volume consumer electronic markets.

TECHNOLOGY

In response to demand for through silicon interconnect functionality a novel idea to isolate a section of a low resistivity silicon wafer laterally by incorporating a trench filled with an isolating material [START_REF] Kälvesten | Elektriska anslutningar i substrat / Electrical connections in substrates[END_REF] was invented. This means that the actual via plug is there from beginning and the difficulties with homogenous fill of a wide plug area is avoided. The isolating trench can have various shapes however most often it is shaped as a circle to minimize any stress. The trench can also take other shapes if necessary as long as it constitutes a closed loop in order to avoid shorting to the base substrate. The process uses a DRIE process in order to make a trench. This DRIE process has been developed in order to achieve the necessary high aspect ratio features in up to 600 µm thick substrates but more important it has been optimized in order to provide a fast etch time. The trench width is varied depending on actual design criteria with typical width in the order of 10 to 15 µm. In order to keep the via plug in place, the trench etch stops short of reaching all the way through the wafer. Following this etch, the wafer is subject to a filling process, which fills up the trenches with a dielectric material providing necessary isolation from the remaining bulk. In several customer applications the via has been proven to be able to hold a good vacuum level and cross section analysis shows that with the qualified via fill process voids can be avoided. As a final step, a CMP process is applied to the backside of the wafer, removing the material that keeps the "via plugs" connected to the bulk, thereby isolating the via plugs from the bulk of the wafer. In some sense the via technology could be compared with the Silicon on Insulator (SOI) technology, noting the 90° difference in the orientation of the buried insulator versus the plane of the wafer. It is also possible to integrate the via technology into SOI material hence enabling further interesting option with regards to continued processing.

Typical Design Flow

Detailed design rules can unfortunately not be detailed in this paper, but some general guidelines can be given with respect to integrating via technology on wafer level. The typical procedure begins with the outline of the requested position of the through wafer connections on the wafer. For smallest possible pitch between vias, down to 50 µm or less, it is necessary to have neighboring vias share the same isolating trench. Since actually a whole wafer without any processing can be considered as a through wafer connection there is no upper limit in terms of the size of the isolated area. As the designer can choose the trench layout freely, assuming a uniform trench width is used over the entire wafer, and the resistance is proportional to the cross section of the connecting silicon, shapes can be chosen that efficiently utilize the available space. Shapes are in many cases optimized towards providing a sensing or an actuating function towards the device silicon in the design. Often there is a requirement for a tight pitch in only one axis of the two-dimensional space and less of a limitation in the other axis. One example of this is the contact pads surrounding a CMOS chip. In such case, a larger total cross section area of the via connection, and thereby lower resistance, can be achieved by outlining the vias in rectangular shape. By using the available chip area to a maximum, while maintaining a small pitch along the other axis resistance can be minimized. Following customer input on the design layout, engineers performs a cross check against design rules, taking into consideration wafer thickness and structural stability versus possible post processing requirements.

Process Implementation

From a technological standpoint, the described via process is primarily a "via-first" process as it needs a high temperature step during filling. From a MEMS processing perspective, the "via-first" approach is in most cases very suitable as in most often there is a desire to minimize additional wafer level post processing and handling of for example released MEMS structures since these can be rather delicate. As mentioned, the completed via substrate wafer resembles the SOI wafer as it allows more or less unlimited processing of the substrate, even at temperatures exceeding 1000°C. This means the via substrate wafer will be able to enter the MEMS device manufacturing flow as part of the starting material.

Integrating the via technology with traditional SOI technology enables combining the technology with applications requiring a high resistivity device layer. The original via process requires a low resistivity bulk part to create a low loss electrical connection, but by integrating the via process into an SOI wafer with a low resistivity handle and high resistivity device layer this can still be achieved. Depending on the post processing requirements, the contacting to the via sections in the handle part of the substrate is made by one of the existing conductive layers or alternatively by incorporating shallow plugs of doped polysilicon into the design. Lately a variation of the via technology involving localized doping allows also for low resistance connections through bulk material with higher resistivity. This, as well as the combination with SOI material as described above increases the possibility for integration to a wider amount of designs and applications.

IMPLEMENTATION

When debating pros and cons of MEMS technology, not rarely has the argument brought forth that the main hurdles relating to commercial implementation is packaging and interconnect. With the increasing maturity of the MEMS industry a number of special solutions has been brought forward and are also starting to turn into standard solutions.

ISBN: 978-2-35500-006-5

With the successful integration of the via technology described herein to more than 10 various products over a large area of application fields the via technology offered provides one such standard. In short a well qualified via process virtually takes care of one of the inherent, most significant problems associated with MEMS by providing true wafer level packaging of MEMS. Depending on the designs in question the components can either be mounted directly onto PCB or combined with ceramic packaging technology.

Cost Factor

The via substrate manufacturing flow, containing a through wafer DRIE process and the following filling and CMP, does add on manufacturing cost. In volume production this cost is comparable to an overall cost similar to that of an SOI wafer. The reduced form factor and wafer level packaging of the MEMS die, enabled by the technology, makes the implementation beneficial for most applications and is especially effective with small die sizes where bond pad area takes up a significant part of the die size. It also in several cases constitutes an enabling technology which leads to new market opportunities with regards to component development.

Implementation Examples

To date, the via process has been offered to a number of foundry customers as an added value building block for integration in customer specific designs. One of the most unmistakable examples of via process implementation is wafer level packaging of MEMS devices. Metal routing and contact pad area in many cases consumes a large portion of many MEMS die layouts. Adding a standard ceramic package, the final component will in many cases be ten times larger in area than the active die itself. Incorporating via technology for interconnect and wafer level packaging significantly reduces the form factor while getting simplifying a large share of the traditional "back-end" process.

Since the via substrate allows for high temperature processing fusion bond can in many examples be used for the capping process. This enables seal ring size to be reduced adding further to the increase in number of dies per wafer. Also the technology solves any issues with exposing bond pads through elaborate two step dicing methods. The dies can be singulated with a single cut by a dicing saw and are surface mountable straight of the dicing line. Another area of interest for implementation is the integration of MEMS and CMOS. Via technology provides new possibilities for such integration although yield factors for particular designs needs to be carefully considered when integration method (wafer level or die level) is chosen.

Figure 6: Single element MEMS micromirror with integrated

Vias.

For many sensing devices such as flow-and pressure sensors the via technology simplifies packaging and connection to the chip. The connection to the sensing chip can be made at the chip side facing away from the media while having the sensing part of the die in direct contact with the measured media.

In cases of dies made up of large arrays of "facets" extensive metal routing in the plane of the active area is often required. By using through wafer via technology, real estate can be saved while improving fill factor. Metal routing and flip chip mounting is accommodated on the back side of the die beneficial for example in imaging applications.

Using via technology in micro-fluidic devices enables creation of electrodes in the channels, and at the same time it allows the integration of more additional MEMS features such as fluidic filters, high aspect ratio structured channels and silicon to glass bonding.

The via technology is also applicable when using the System in Package (SiP) approach, integrating a number of integrated circuits in a single module. The SiP can perform many of the functions of an electronic device, such as a mobile phone. This feature is particularly valuable in space constrained environments like mobile phones as it reduces the form factor and complexity of the PCB and overall design. There is also a continued drive for advanced small scale packaging, which can benefit from use of other materials than ceramics to achieve the accuracy and reduction in footprint requested. Traditional packaging based on low temperature or high temperature co-fired ceramics (LTCC or HTCC) are reaching limitations when using existing manufacturing methods. These technologies have difficulties achieving the small pitch for the electrical feedthroughs (<100 µm) and tight tolerances are required when moving closer to "micro scale". In that respect, silicon provides a good candidate with its long term reliability and high precision micromachining capabilities. In this respect, via technology and MEMS processing technology can be implemented as an alternative to realize customized silicon based wafer level packaging solutions.

TECHNOLOGY LIMITATIONS

Current limitations when implementing silicon via technology are typically found in the domain of RF applications. When gold signal lines are not good enough as in many high frequency circuits and solutions are sought in copper, the silicon via will not do the job. Typical resistance in a standard via connection of 100 µm diameter in a 400 µm thick substrate is in the order of 1 Ohm and such resistance will in most RF designs constitute a loss higher than acceptable. There is extensive work in many places striving to enable a hermetic via solution with lower resistance but that is rather a subject for separate articles. No doubt such a technology proven in volume will enable even further development of MEMS and IC technologies while having limitations with regards to post processing allowed. A void free metal interconnect technology will for sure complement the Silicon via technology when further reduction of interconnect resistance is necessary.

COMPETING TECHNOLOGIES

via technologies is not a new concept in the MEMS or in the IC community and are seeing increased success in terms of commercial viability. However, the various approaches are still to a large extent struggling with inherent technological difficulties tightly linked to the chosen technology. Typical issues with metal based Vias have been the thermal mismatch with silicon causing micro cracks and reliability issues. Furthermore, a metal via must be incorporated towards the end of a MEMS process as the thermal budget of would not allow too much of high temperature post processing.

TECHNOLOGY LICENSING

With several foundry customers using the process today and an extraordinary line-up of potential users, it is of great interest to facilitate making this process a standard in the MEMS industry. In this context, the via technology is offered through licensing agreements and technology transfer programs to selected customers and partners who would favor to incorporate the technology in their manufacturing lines [START_REF] Kälvesten | Elektriska anslutningar i substrat / Electrical connections in substrates[END_REF].

CONCLUSIONS

This paper has detailed information on a commercially available through wafer via process that provides a viable solution to some inherent problems associated with MEMS (packaging and interconnect). It has also provided examples of some of the many features made possible through this new technology. The via process has now been in production since 2005 for applications ranging from advanced medical devices to mobile phones, and since mid 2006, the process is offered as a standard MEMS foundry process.

To conclude this paper, key features characterizing this through silicon via process are listed below:

• High density via technology (pitch <50 µm)

• "No metal" starting material with unrestricted MEMS or CMOS post processing capability • Enables true wafer level packaging of MEMS devices with vacuum sealing • Low cost solution due to minimized component form factor and "all silicon package" for SMD assembly • First through wafer via technology in volume production

Figure 1 :

 1 Figure 1: Schematic cross-section of through wafer interconnects.

Figure 2 :

 2 Figure 2: SEM picture of through wafer via "plug", formed using DRIE.

Figure 3 :

 3 Figure 3: Schematic cross section of via substrate features.

Figure 4 :

 4 Figure 4: Integration of via process in SOI wafer with high resistivity device layer.

Figure 5 :

 5 Figure 5: Example of wafer level packaging of MEMS device with 3D interconnect by Silex silicon Vias.

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 11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5

Figure 7 :

 7 Figure 7: Interposer solution for system in package (SiP).

Figure 8 :

 8 Figure 8: Wafer level micro scale packaging enabled by Silex via technology.


M Puech

Jean-Marc M Thevenoud

J M Gruffat

N Launay

N Arnal

P Godinat

Fabrication of 3D Packaging TSV using DRIE

Keywords: TSV, Via first, Via last, Packaging, DRIE, Silicon etching, Bosch process, Tapered profile, Oxide etching, PECVD

ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

INTRODUCTION

The ever storage capacity demanding products as MP3, mobile phones, digital still camera,.. are asking for smaller size packages and higher memory density.In response to the performance and density requirements, the semiconductor industry has definitively moved from 2D to 3D style packages with shorter electrical connections. Through silicon vias (TSV) and related techniques are enabling technologies clearly identified. The fabrication of TSV includes three major steps: silicon via etching, via insulation and via metallization. Depending upon the positioning of the TSV sequence within the overall wafer manufacturing, there are many different process flows. In addition to the "Via First" approach, developed within the Emc3d consortium [START_REF]Emc3d consortium[END_REF], we review the other "Via First before FEOL" and "Via Last after BEOL" alternative solutions.

DRIE PROCESS

Developed more than 10 years ago for the MEMS emerging products, the DRIE tools are based on ICP source because of their high degree of gas dissociation, Fig. 1. The most common used DRIE process is known as the "Bosch" process [START_REF] Laermer | Method of Anisotropically Etching Si[END_REF]. This process alternates short step of SF 6 plasma for the fast but isotropic removal of silicon, with short C 4 F 8 plasma deposition step for the sidewalls protection; the polymer layer will be removed at the bottom of the feature during the first part of the next etching step with SF6. Thanks to the "F" based chemistry, this process has the potential to deliver very high and selective etching rate.

"VIA FIRST prior to FEOL" TSV

The "via first prior to FEOL" strategy is the strategy where the vias are done on the blank Si wafer prior to any CMOS process (Fig. 2). Due to the step position in the wafer fabrication process, it can be realized by the CMOS manufacturer, or even the wafer supplier, but not by the packaging company. Due to all the further CMOS manufacturing steps, the refilling material has to be resistant to all the thermal processes, usually at higher than 1000 degrees. That's why the mostly used refilling material is polysilicon. As the poly-silicon refilling process can be achieved only in narrow features, the etched features have a width lower than 5µm. One advantage of such process is that it doesn't require any seed layer, and the isolation layer can be easily done using a traditional oxidation process.

As the wafer will be thinned down at the latest stage to a thickness around 150µm, the less than 5µm wide features have to be etched down to at least 150µm, that means a more than 30 aspect ratio (Fig. 3). The Aspect Ratio (A.R.) of a given feature, like a trench, is defined as the ratio between the depth of the trench and the width. The use of un-pulsed processes, such as a mixture of SF6 and O2, is not possible to reach such high aspect ratio, and the selectivity is also too low. A "Bosch" process, or even better, a "S.H.A.R.P." (Super High Aspect Ratio Process) process [START_REF] Puech | A novel plasma release process and super high aspect ratio process using ICP etching for MEMS[END_REF] can be used to achieve the best etch performances. This Alcatel patented process allows an increase of the aspect ratio in comparison with the "basic" Bosch process". When applying the innovative "S.H.A.R.P." process to deep etching of very small features, it was demonstrated that an Aspect Ratio as high as 110 was achievable as shown in Fig. 4.

The D.R.I.E. is the only technology available that can etch features of 5µm wide to a depth higher than 100µm in Silicon, and Alcatel Micro Machining Systems is the only company that can provide the S.H.A.R.P. process. For a manufacturing point of view, the "via prior to FEOL" strategy has the big advantage to be easily integrated to the actual fabrication process, as there is only the D.R.I.E. equipment to be added to the current fabrication. All the other steps are achievable using the current tools used in a semiconductor fab. And so, the integration is very easy and not at all costly.

"VIA FIRST after BEOL":

In this approach, the TSV will be realized once the CMOS device will be completed and before the grinding process for wafer thinning (Fig. 5). The advantage of this strategy is that the CMOS structure is already finished and passivated. At this stage, since the wafer will no longer be exposed to high temperature cycles, the use of via copper refilling material with much better electrical and thermal properties compared to polysilicon is allowed.

Typical features size for those "Vias first after BEOL" are diameters ranging from 10 to 40µm etched at depth of 70-120µm. After etching and before refilling the via with copper, a dielectric layer and later a barrier and a seed layer have to be applied using CVD and PVD techniques (Fig. 6). For a better coverage of the metal layer, a typical 83° to 85° tapered profile is usually required. As this step is quite costly and time consuming, an alternative "Open Mouth" profile has been successfully developed.

This new approach consists in making a facet at the top part of the hole, enlarging the entrance of the via hole. Starting with the same mask design previously used, the proposed process consists in a first step during which a highly tapered profile is applied through the use of mixed SF 6 + C 4 F 8 plasma chemistry and then to apply a pure anisotropic process as shown on the Fig. 7. We evaluate this method targeting a facet angle of 70° on the first 30 µm of depth. When the desired depth is achieved, the process recipe is switched to an anisotropic process. Because the anisotropic process is ion enhanced, the transition between tapered and vertical profile occurs exactly underneath the mask opening, keeping a good CD control. Fig. 8, shows the result of such a combined process: the average etch rate is still high at more than 12 µm/min with a very good uniformity (+/-2.5%), the profile angle is 70° at the top 30 µm then 88,8° down to 180 µm depth. Because of the further thinning operation, the etched depth is limited to less than 100µm resulting in relatively low aspect ratios not exceeding 5 to 10, which are very favorable to high etching rate regimes required for high throughput manufacturing.

The fluorine radicals produced in the ICP plasma are transported within the gas phase to the silicon surface where they react with the silicon to produce volatile SiF 4 molecules evacuated by the pumping system according to:

Si(s) + 4F(g) → SiF 4 (g) + ∆G 0 (eq.1)

A given plasma parameters setting, as flow rate, pressure, ICP power.., will produce a given "F" partial pressure available for the removal of silicon. As the Si etch rate is directly proportional to the fluorine radicals reaching the substrate (Fig. 9) and thanks to its 20 years knowledge in plasma technology, Alcatel Micro Machining Systems has developed the hardware as well as specific processes to produce higher quantity of fluorine radicals.

Fig. 9: Fluor radical flux rates versus Si etch rate

A high Si etch rate step combined with the most efficient passivation or deposition step, has allowed us to achieve anisotropic profiles, with very high etch rates of 50µm/min. or more.

As the etch rate increases, the capability to control the wafer temperature becomes crucial to obtain a uniform etch across the wafer whatever the wafer diameter.

In order to evacuate all this heat and achieve the best uniformity of temperature, Alcatel has designed a "P" type electrostatic chuck (ESC) with an innovative design, allowing to adjust the temperature regarding the wafer patterns. For a given process, the "P" type ESC, gives a uniform temperature of ±0.15 degree across the wafer, with an excellent thermal conductivity.

"VIA LAST after BEOL":

Similarly to the wafer level packaging of the CMOS Image Sensors (CIS), in the "Via last" approach, the device wafer is grinded and thinned to its final thickness prior to the Via formation (Fig. 10). For that operation, the device wafer is temporary bonded onto a wafer carrier, usually made of glass. It will remain attached to this carrier until the stacking of the wafer onto another wafer, or until the transfer of the wafer onto a dicing frame, depending upon the attachment technique: wafer to wafer or die to wafer. Because the wafer carrier is little bit larger than the silicon wafer for a robust wafer, the overall handling system has to accept wafer substrates with diameter 2 mm larger than the standard wafers. Another major difference is on the capability of the wafer chuck to be able to electro statically clamp Silicon on Glass (SOG) substrates.

From a process perspective, the fact that the wafer is temporary bonded with adhesive onto a wafer carrier, implies that all the further process steps have to be limited at temperatures between 180 °C to 200 °C. The DRIE "Via last" etching is very similar to the "Via First", after BEOL approach in term of via dimensions and profiles. However, we have to keep in mind that the wafer temperature limitation, discussed above, will be a major limiting factor in the high etching rate regime. In order to minimize the impact of the glass carrier onto the wafer surface temperature, we developed specific low thermal resistance ESC's.

DRIE of high aspect ratio oxide:

The major difference of the "Via Last" approach compared to the "Via First" is that in this technique, the backside via metallization has to come in contact with the metal pad contact. Therefore, after the DRIE of the via, the stacked insulating oxide layers have to be dry etch removed down to the metal pad; then a conformal dielectric layer has to be deposited (at low temperature) and finally, this dielectric layer has to be cleared from the bottom via such to allow the deposition of the barrier and seed layers to be in contact with the metal pad. If the via profile is almost vertical, the two steps of dielectric etching can be done quite easily without any additional photolithography steps. If the via profile is quite tapered (for and easy PVD deposition of the barrier and seed layers), then the etching of the dielectric layers will necessitate a specific photolithography step to remove the dielectric layers from the bottom of the Via while keeping a thick sidewall layer for a good electrical isolation. In the packaging of the CIS, we already demonstrated that is was possible to remove the insulating layers underneath the metal pads using our high density plasma dielectric etcher. However in the packaging of CIS application, the via diameter is much larger than the one targeted for the die stacking (70µm to 80µm) and the taper angle is much pronounced ( 65° to 75°) allowing for easier photo-resist coating and developing. In order to demonstrate that we could extend our technology to higher aspect ratio features as the ones involved in the die stacking, we evaluated the etching of a buried oxide layer just after the DRIE of Si. The buried oxide layer was removed at 500 nm/mn with a 10:1 selectivity compared to the P.R. mask used to define the Via (Fig. 11).

Low Temperature PECVD of dielectrics:

As for the other process steps, the deposition of a conformal insulating layer has to be done while keeping the substrate temperature at around +180°C. Taking benefit of our experience in the deposition of silicon nitride passivation layers for the manufacturing of III-V compounds, we developed specific LT-PECVD of oxide layers adapted at larger wafer diameter.

Based on the AMMS high density plasma source, we developed a Silane/Oxygen PECVD process focusing on step coverage deposition rate and uniformity while keeping the breakdown voltage at high values.

Deposition of 2µm thick oxide layers at deposition rate in excess of 500 nm/mn +/-5% on 8" wafers has been performed (Fig. 12). An in-depth analysis showed insulating oxide layers with a step coverage higher than 50% for aspect ratio higher than 1:1 with breakdown voltage in excess of 7.5 MV/cm.

CONCLUSION

A complete range of etching processes has been developed to address not only the "Via First" challenges but also to comply with the Via First before FEOL and Via Last after BEOL requirements. The available process range has been extended to the etching of buried oxide and to the deposition of conformal insulation layers at low temperature. The issues related to the handling of non SEMI Standard wafers has been addressed and successfully implemented onto the latest AMMS products.

Fig. 1 :

 1 Fig. 1: AMMS de-coupled ICP process chamber

Fig. 2 :

 2 Fig. 2 : "Via first prior to FEOL" From left to right: D.R.I.E., Oxidation, Poly-Si refilling

Fig. 3 :

 3 Fig. 3: Typical "Via first prior to FEOL" etch Courtesy: ST Microelectronics

Fig. 4 :

 4 Fig. 4: The "SHARP" Process for submicron features. (Courtesy:ESIEE)

Fig. 5 :

 5 Fig. 5: "Via first after BEOL" From left to right: D.R.I.E., Oxidation, Copper refilling

Fig. 6 :

 6 Fig. 6: Left "Via first after BEOL" after D.R.I.E., Right: "Via first after BEOL" after refilling step.

Fig. 7 :

 7 Fig. 7 : "Ideal" profile (top), Tapered etching step (left bottom), followed by vertical etching step (right bottom).

Fig. 8 :

 8 Fig. 8: 60x180 µm Via Hole; Profile angle:70° at top 30 µm then 88.8° down to 180 µm.

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 11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5

Fig. 10 :

 10 Fig. 10: "Via last after BEOL" From left to right: D.R.I.E., Oxidation, Copper refilling. A temporary wafer carrier is used from the via formation until the complete refilling of the via.

Fig. 11 :

 11 Fig. 11: Etching profile of a buried oxide layer underneath a Silicon layer.

Fig. 12 :

 12 Fig. 12: Top & Bottom corner via with a highly conformal LT-PECVD oxide layer.


Won-Kyu Jingli Yuan

Chang-Hyun Jeung

Seung-Wook Lim

Young-Do Park

Sung Kweon

Yi

A Low-cost Through Via Interconnection for ISM WLP

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A Low-cost Through Via Interconnection for ISM WLP Jingli Yuan, Won-Kyu Jeung, Chang-Hyun Lim, Seung-Wook Park, Young-Do Kweon, Sung Yi PKG Team, Corporate R&D Institute, Samsung Electro-Mechanics Co., LTD.

314, Maetan3-Dong, Yeongtong-Gu, Suwon, Gyunggi-Do, Korea

Abstract-WLP (Wafer level packaging) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to establish electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and TSV (Through Silicon Via). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Key fabrication processes include glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is needed for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.

I. INTRODUCTION

With rapid development of information technology, ISM (Image Sensor Module) becomes more and more widely adopted in all kinds of mobile digital devices, especially cellular phones. Market of built-in image sensor module has also kept growing for many years. However, with the trend of miniaturization, multifunctionality, and increasing competition in market, new generation mobile devices have higher requirements for ISM, such as high performance, small form factor and low cost. Conventional ISM package, such as COB (Chip On Board) and COF (Chip On Flexible), will have difficulties to meet all those requirements due to their limitations in packaging methods. WLP (Wafer Level Packaging) Technology becomes very promising and has been studied for years for image sensor packaging [START_REF] Viswanadam | Novel wafer level package technology studies for image sensor devices[END_REF].

WLP (Wafer level packaging) for image sensor devices has the advantage of small size, high performance and low cost. In order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed such as T-contact and TSV (Through Silicon Via) [2][3]. T-contact type image sensor WLP has very complicated fabrication process, and it needs large pad pitch and scribe line width. However, the pad pitch and scribe line width of CMOS image sensor device wafer will continue to decrease with the development of IC technology and motivation of cost reduction. TSV type image sensor packaging is obtaining more advantages in fabrication process and cost reduction.

In this paper, a wafer level package of image sensor with novel TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and to increase yield of image sensor packaging. Compared to large opening area of tapered via on the backside of CIS wafer, only small opening area is needed for making the via interconnection that is presented in this paper. Vertical via etching and DFR (Dry Film Resist) lamination process can achieve lower cost and lower process difficulty than tapered via etching, spray coating and deep photolithography processes. The via bottom notch problem caused by over etch and wafer thickness non-uniformity can also be overcome by remaining a fillet structure at the bottom of vias, instead of over etch. The fillet structure can give better insulation layer and seed layer deposition yield inside the vias, without influence to bottom insulation layer opening process.

II. FABRICATION PROCESS OVERVIEW

Structure of the image sensor packaging with TSV interconnection is shown in fig. 1. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, solder ball formation, and dicing, as shown in fig. 2. All the process steps are performed at temperature lower than 200 Celsius degree, because low-temperature processes are preferred for the protection of the sensor device and micro-lens.

The image sensor WLP is composed of a 4-inch CIS (CMOS Image Sensor) wafer, a polymer bonding layer and a 4-inch glass cap wafer with thickness of 250um. The CIS Then via holes are filled by Cu electroplating, and backside redistribution layers and solder balls are formed.

III. Through Via Interconnection Formation

TSV (Through Silicon Via) formation process presented in this paper includes process steps of via etch by DRIE, SiO insulation layer by low-temperature PECVD, DFR (Dry Film Resist) lamination and photolithography, Al pad opening by laser drilling, metal seed layer sputtering, and via filling by Cu electroplating, as shown in fig. 2. Key processes are explained below in detail.

Through via etch

A 6um-thick photoresist layer is coated and patterned on backside of the device wafer as etching mask for through via formation after bonding process of glass cap wafer. DRIE process is used to form vertical vias from the wafer backside surface to the insulation layer at the bottom of Al pads. Via diameter is 50um and aspect ratio is optimized as 2.0 for an optimum balance of process capability requirement between via etch process and passivation layer deposition process, as shown in fig. 3.

Through via with vertical sidewall is adopted in this design for reducing via etch process difficulty and increasing process 7. passivation layer etch for pad opening. 8. Seed layer deposition. 9. via filling by electroplating. 10. Solder ball formation ISBN: 978-2-35500-006-5 yield. When the insulation layer under Al pad is exposed with enough area (diameter>30um in this design) during via etch, a fillet structure with various size remains at the bottom corner of the via holes, as shown in fig. 4. This fillet structure can help to prevent notch problem when etching the bottom of via holes, so that coverage of insulation layer and metal seed layer at the bottom of via holes can also be improved with this structure.

With DRIE process for via etching, scallop on via sidewall can seriously affect insulation layer deposition result on the sidewall, and cause current leakage with deficient insulation layer coverage inside via holes. Process parameters are optimized to minimize the scallop to an acceptable size good for sequent passivation process. Notch-free process for via etch is also tested in this research as an alternative for the process with fillet structure at the bottom of via. Both HF (high frequency) and LF (low frequency) processes are used in the via etch step to get benefit of both good etch rate and notch-free process. Optimized scallop (<200nm) and notch (<1um) are achieved, as shown in fig. 5.

Backside passivation layer deposition

A SiO passivation layer is deposited on wafer backside and inside via holes by low-temperature PEVCD process at 100 Celsius degree. The process is optimized for good step coverage, sufficient passivation thickness and acceptable deposition rate. A 1um-thick passivation layer at via bottom and sidewall is achieved to provide sufficient passivation effect for sequent via filling process. Multi-step deposition process is used for film stress compensation and wafer warpage control. Fig. 6 shows the passivation layer after deposition process.

Al pad opening (Via bottom insulation layer etch)

The composite insulation layer under Al pads of image sensor device includes multiple layers of SiO and SiN. At the bottom of the via holes, this layer needs to be etched to expose Al pads for formation of electrical interconnection to backside of the device wafer. Etching process must be carefully optimized to provide sufficient etching depth to ensure a clear opening area under Al pad, also without damage of Al pad and passivation layer on via sidewall and fillet structure at the bottom corner of the via.

Two etching processes, dielectric dry etch and laser drilling, are tested in this research. For dry etch process, a DFR layer is laminated and patterned on the backside of image sensor device wafer as etching mask. Opening with 30um diameter is formed above each via hole. Since via hole diameter is 50um, the etching mask with 30um-diameter opening can help to etch the via bottom insulation layer in the center of via bottom surface, without damaging the passivation layer on the fillet structure. However it is difficult

Fig. 1 .

 1 Fig. 1. Structure of ISM WLP with TSV interconnection.

Fig. 4 .Fig. 3 .Fig. 2 .

 432 Fig. 4. Cross-sectional view of via hole with fillet structure at bottom corner

Fig. 5 .

 5 Fig. 5. Via bottom etch result with optimization of scallop and notch.

  Fig. 6. SiO passivation layer deposition result.

Fig. 7 .

 7 Fig. 7. Bottom of via hole after dry etch of Al pad opening.

Fig. 10

 10 Fig. 10(a). Resolution test for image sensor package.

Fig. 9

 9 Fig. 9(a). CMOS Image sensor wafer after WLP (Backside)

9-11 April 2008

©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5 to control dielectric dry etch process to stop at a proper end point because the Al pad layer is very thin and easily damaged. So yield of the dielectric dry etch process for pad opening is very low. The process result is shown in fig. 7. Laser drilling process is also tested to make openings in the insulation layer under Al pads. Etching selectivity between SiO/SiN layer and Al pad layer is very important to prevent damage of Al pad. Excimer laser shows good selectivity with carefully selected wave length and energy. Fig. 8 shows the pad opening result after laser drilling.

After seed layer deposition and Cu electroplating, electrical interconnection is established from Al pad of image sensor device to the backside of the wafer. GND-to-GND resistance of 2.5ohm is achieved by this TSV interconnection.

IV. WAFER FABRICATION RESULT

The CIS wafer after wafer level packaging with the TSV interconnection is diced and tested, as shown in fig. 9. Final package size is 3.67mm X 3.42mm X 0.39mm, which is the same size as the image sensor chip. Resolution and color test result is shown in fig. 10. High-quality photo images are also obtained during test. The through via interconnection adopted in this image sensor package shows good electrical connection performance. The fillet structure helps to reduce process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation, including vertical via DRIE, SiO PECVD, DFR lamination, laser drilling, and so on.

V. CONCLUSION

A low-cost through via interconnection is developed for CMOS image sensor WLP. The process steps used for fabrication are based on the consideration of low cost and good processablity. Image sensor package using this through via interconnection shows good electrical performance and it can gives good working result. This research demonstrates the performance and fabrication validity of the low-cost through via interconnection with fillet structure and laser drilling process for Al pad opening, and shows that this technology is suitable for the application of ISM wafer level packaging.


Rozalia Beica

Charles Sharbono

Tom Ritzdorf

Copper Electrodeposition for 3D Integration

published or not. The documents may come

INTRODUCTION

Two-dimensional approaches have been traditionally applied for IC integration. Continuous pressure for new IC packages that can address the ever-expanding consumer electronics market demands for increased functionality and performance while reducing the size and cost, has driven the semiconductor industry to develop more innovative packaging, using vertical, 3D integration [START_REF] Lassig | Manufacturing Integration Consideration of Through-Silicon Via Etching[END_REF][START_REF] Jang | Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)[END_REF][START_REF]3D IC&TSV Report[END_REF][START_REF] Schmauch | 3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments[END_REF].

3D packaging has been extensively studied in recent years, in particular for advanced mobile devices. 3D stack packages were initially developed using wire bonding for memory packages and SDRAM of cellular phones [START_REF] Jang | Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)[END_REF].

General advantages of 3D packaging technologies include form factor miniaturization (size and weight), integration of heterogeneous technologies in a single package, replacement of long 2D interconnects with short vertical interconnects, and the reduction of parasitics and power consumption.

Therefore, 3D packaging can offer significant advantages in performance functionality and form factor for future technologies.

Based on the stacking method, there are different type of 3D packages, which include on-chip 3D integration based on layer-by-layer build-up of functional layers within a chip; 3D stacking with die-to-die stacking or package-to-package stacking (package-on-package POP or package-in-package PIP); and 3D ICs (3D integration of ICs), which have die-todie interconnection with through-silicon vias.

The typical trend in technology development continues to move from 2D configuration to 3D stacking (with wire, bumps and micro vias), and then to 3D ICs with TSV interconnects in order to reduce form factor, increase silicon efficiency, and have shorter interconnects [START_REF] Kim | EMC-3D Consortium Targets Cost-Effective TSV Interconnects[END_REF].

Wire bonding today, even if it has the advantage of being a mature, well-known and characterized technology, is limited when it comes to 3D chip stacking in terms of density and performance. To accommodate wire bonds both vertically and horizontally, higher density packages are needed; therefore miniaturization of the devices is more difficult to achieve. The I/O density is also reduced, and the connections are long and limited to the periphery of the device.

Conventional flip-chip connections have their size limitations as well, which is why this technology cannot be broadly adopted for chip stacking.

By providing shorter connections with TSV, the distance of information flow on a chip will be significantly reduced (by up to 1000x). TSV connections also allow the addition of increased number of channels or pathways (up to 100x more than 2D chips), necessary for the information to flow. TSV can replace less-efficient wire bonds for transferring signals off the chip, increase speed while reducing power consumption and enables uniform power delivery to all parts of the device [START_REF]IBM tips TSV 3D chip stacking technique[END_REF]; it makes possible the formation of higher density and higher aspect ratio connections, allowing the integration of multi-chip systems entirely within the silicon with a better packing density than traditional 3D packaging methods. Because of its advantages over traditional technologies, the TSV approach, although still expensive and difficult to implement in high volume for most applications, continues to have a growing interest, being one of the hottest topics of the semiconductor industry today, not only for 3D packaging purposes, but also for the raw benefits offered in a single device, such as higher frequency [START_REF] Schmauch | 3D Packaging -How to Build 3D Packages from Design through Materials & Equipment[END_REF]. PROCESS FLOW FOR TSV CHIP STACKING Depending on the application, there are two approaches adopted for TSV chip stacking: blind-via filling before wafer thinning and through-via filling after wafer thinning [START_REF] Edelstein | Technical Digest, IEEE International Electron Devices Meeting[END_REF][START_REF] Venkatesan | Technical Digest, IEEE International Electron Devices Meeting[END_REF][START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF].

The vias in the first approach (as presented in Figure 1) are filled with copper from the front side of the silicon wafers, very similar to the typical interconnect applications. After the vias are filled and overburden is removed, the wafer is thinned at the backside of the wafer/vias until the TSV electrodes are exposed. The second approach (as presented in Figure 2) is to fill vias through via holes after wafer thinning. In this case the seed layer is deposited on one side of the wafer. Due to the difficulties in handling and plating thinned wafers, the first approach has gained more popularity becoming the most preferred TSV stacking method in the industry today.

III. MATERIALS AND PROCESSES FOR TSV ELECTRODES

There are different materials and methods that have been proposed and tested for TSV applications. Feature dimensions, final deposit characteristics and process reliability, along with cost considerations are the main limiting factors of applicability of these materials and methods.

The most common material used for via filling and formation of TSV electrodes is copper, due to its properties and compatibility to conventional multilayer interconnection in FEOL and back-end-of-line (BEOL) processes [START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF]. Alternative conductive materials include chemical vapor deposited (CVD) tungsten and doped polysilicon. Both of these materials provide a better match of the coefficient of thermal expansion (CTE) with silicon, very important especially for larger features, however, at the expense of lower electrical and thermal conductivity than copper. Although announce-ments of using all these materials have already been made, which one is going to gain more market acceptance remains to be seen [START_REF] Schmauch | 3D Packaging -How to Build 3D Packages from Design through Materials & Equipment[END_REF][START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF][START_REF] Niklaus | Wafer Level 3D Integration Technology Platform for ICs and MEMS[END_REF][START_REF] Vardaman | 3-D Through-Silicon Vias Become a Reality[END_REF].

Copper can be applied through CVD, plasma vapor deposition (PVD) and most commonly through electrodeposition. The CVD method, although a well-known technology from the front-end-of-line (FEOL) contact via applications, is more suitable for smaller features (up to 2µm in diameter). Electrodeposition processes are typically performed at room temperature and pressure, so the equipment is less complex and expensive than vacuum deposition equipment. Because of the high costs involved with CVD applications and the use of unstable and hazardous organo-metallics, which result in deposits that have lower purity and higher resistivity, as well as the advantages that come with electrodeposition processes, such as faster speed, higher stability, ease of control and maintainability, most TSV developments have been focusing on using electrodeposition as the preferred application method [START_REF] Schmauch | 3D Packaging -How to Build 3D Packages from Design through Materials & Equipment[END_REF].

The formation of TSV electrodes using copper deposition, following the via first stacking approach described in Figure 1, starts with via etching in the silicon (deep reactive ion etch or laser technologies), followed by a deposition through plasma enhanced chemical vapor deposition (PECVD) of an insulator (SiN x or SiO 2 ). The insulator is then covered with barrier layers such as TiN or TaN using metal organic chemical vapor deposition (MOCVD) or PVD technology and subsequently with a conductive Cu seed layer, either through CVD or PVD, depending on the features shape and aspect ratio. Once the seed layer is present inside the features it provides the necessary conductive layer required for electrodepositing the TSV structures [START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF].

Depending on via sizes and applications, there are typically three types of deep via copper (as presented in Figure 3): lining and full filling with and without stud [START_REF] Schmauch | 3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments[END_REF][START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF]. If via lining is more practical for larger features, more commonly found in MEMS and sensor applications, full filling is applied over a wider range of via dimensions, ranging from near damascene applications to larger vias used for sensor applications. Photoresist patterns can also be added to enable formation of a stud or additional connections, such as redistribution lines (RDL), for solder bonding. After electrodeposition, the wafer is thinned and additional processing steps are applied to form the final 3D package.

IV. FACTORS AFFECTING VIA FILLING PROCESS PERFORMANCE

Copper electrodeposition has been already applied for many years in the semiconductor and electronics industry, therefore the transfer of this technology, from applications such as copper damascene as well as printed wiring boards (PWB), to TSV applications, was believed to be easily done. That was not the case. Many of the conventional copper chemistries have been tried; however the results were not satisfactory. Defects such as seams, voids and inclusions of the electrolyte, which could have a negative impact on reliability by disrupting the ability to carry the electrical signal, occurred. There was need for better performing chemistries and processes able to address the limitations seen with the conventional materials and methods.

Copper, due to enhanced transport at the top of the via and a higher field at the small curvature -highly accessible areas) is going to build up faster, pinching-off and creating a voided deposit [START_REF] Landau | Copper Metallization of Semiconductor Interconnectsissues and prospects[END_REF]. In order to achieve void-free filling, the deposition at the top needs to be significantly suppressed while the deposition at the bottom accelerated, to achieve a so-called "bottom-up" deposition. The composition of the copper electrolyte was found to have a significant effect on the process performance, with respect to quality of the deposit and maximum applicable deposition rates. Depending on bath composition and process parameters, different filling profiles can be obtained, as shown in Figure 4 By selection of the right organics, optimization of the chemistry in combination with the process parameters and reactor design, reliable TSV structures through copper electrodeposition can be achieved. Today's commercially available chemistries consist of three organic components designed as accelerator (or brightener), suppressor (or carrier) and leveler, in addition to the inorganic components of metallic ions, acid (either sulfuric or methanesulfonic based) and halide ions (chloride being the most commonly used). Additionally, very important characteristics of the electrolytes necessary for achieving void-free filling are good wettability (especially for high aspect ratio features) and stability (for larger features that require longer processing times).

Besides the need for advanced, high performing chemicals, wafer design (via profile and smoothness), seed layer continuity and high performance equipment are equally critical factors needed in order to successfully process TSV structures.

V.

EXPERIMENTAL Experiments were performed using whole wafers (150-200mm) and wafer coupons (2x2cm 2 ). The test vehicles used varied substantially with respect to via profile, sizes and aspect ratios, with features ranging from 3-150µm in diameter and 10-250µm in depth, and aspect ratios of 2:1 to more aggressive ones, such as 10:1. All the wafers were plated using Semitool fountain type plating equipment. All the electrodeposition tests performed were done prior to wafer thinning (via first approach). The flow rate of the solution was kept constant at 5 gallons per minute (gpm) and the bath temperature was fixed at 25°C. The effects of the critical factors mentioned in the previous section, as well as of the various process parameters such as wafer rotation speed, current density, and waveform on process performance were studied. For process performance characterization, a focused ion beam (FIB, FEI dual beam 820) was used.

VI. RESULTS AND DISCUSSIONS

A. The effect of via profile

Via profile, as mentioned in the previous section, was found to impact successful deposition in TSV structures. Depending on the process used to etch vias into the silicon, the different profiles, such the ones illustrated in Figure 5, can be obtained. These types of profiles could be tapered (usually with a profile angle between 85-90°), straight (with a profile angle of 90°) and re-entrant (smaller width at the top of the via compared to the center and bottom of the via). Tapered vias, compared with straight and re-entrant vias, ensure adequate sidewall seed coverage and ease via filling [START_REF] Black | 3D A Revolution in Design[END_REF]. The larger the opening of vias, the easier it is to fill. In comparison, the re-entrant profiles were found to be the most difficult ones to work with, due to higher probability of nonuniform seed layer coverage, especially at the bottom of the feature, and the need of higher performing chemistries that have the ability to provide an increased suppression at the via Tapered profiles also ensure growth minimization in silicon die size and minimize the impact of wafer thinning on device performance and reliability [START_REF] Lassig | Manufacturing Integration Consideration of Through-Silicon Via Etching[END_REF][START_REF] Black | 3D A Revolution in Design[END_REF].

B.

The effect of insulator/barrier/seed layer coverage

The deposition quality (sufficient thickness, uniform coverage and good interlayer adhesion) is very important. Depending on the method used for depositing these layers, as well as via profile and aspect ratio of the features, the characteristics of these layers could vary. While PECVD used for depositing oxide can be conformal, PVD processes for barrier and seed layers have the difficulty of forming continuous layers, especially for small vias with high aspect ratios [START_REF] Lassig | Manufacturing Integration Consideration of Through-Silicon Via Etching[END_REF]. Figure 6 shows a bottom void obtained during via filling, due to non-coverage with seed layer of the via bottom. Seed layer enhancement or wet chemical deposition of seed layer, originally designed for damascene interconnect [START_REF] Schmauch | 3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments[END_REF][START_REF] Haumesser | ECD Seed Copper Layer for Seed Ehancement in Advanced Interconnects[END_REF][START_REF] Chen | ECD Seed Layer for inlaid copper metallization[END_REF] has been demonstrated to be effective for deep 3D vias in overcoming the problems caused by insufficient coverage of seed layers [START_REF] Schmauch | 3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments[END_REF].

C. Wettability of the features

Wetting and ability to super-conformally fill vias of various sizes and aspect ratios, at faster speeds, are the main characteristics required with respect to the chemistries used for electrodeposition.

Chemistries with poor wetting capabilities will result in bottom voids, as shown in Figure 7a, especially for smaller vias with higher aspect ratios. Besides chemistry, oxides present on the surface of the seed layer could also cause poor wettability of the features (Figure 7b). Elimination of the wetting problems can be achieved by more aggressive pretreatments (impingement spray of liquid as prewet process), addition of a surfactant with high wetting capabilities either in the prewet step or in the deposition chemistries. The wetting agent needs to be chosen in such a way that it will not negatively affect via filling deposition.

In case the wetting defects are due to oxidized seed layer, an etching step with diluted acid solution can be applied.

D.

The effect of process parameters Most process parameters were found to influence the deposit and filling mechanism within via to some extent. In our study, current density, waveform and bath composition were the parameters that had the most significant effect on the process performance.

With respect to current density, the probability of void formation becomes larger with increasing the current density, as shown in Figure 8. This is believed to be caused by increased current crowding at the via bottom and more significant mass transport limitations towards the bottom of via, when plating at higher current densities. Improvement to the deposition process can be achieved by applying the proper waveform parameters. Pulse reverse deposition involves application of a forward current followed by a short, high-energy reverse pulse periodically interposed. It is believed that using pulse plating, the mass transport conditions are improved inside the features, due to adsorbtion/desorption phenomena which otherwise are not possible [START_REF] Schlesinger | Modern Electroplating, Fourth Edition[END_REF], resulting in improved fill performance, as shown in Figure 9. To determine the effect of bath composition, two different electrolytes as well as variations of each of these electrolytes were tested. The results showed that bath composition as well as stability of the bath could have a significant effect of fill performance.

VII. CONCLUSIONS

Feasibility of the copper electroplating process of forming TSV electrodes has been proven. Although the via sizes for TSV applications can vary significantly, by proper optimization of chemistries in combination with reactor design and process parameters, successful via filling can be achieved in a wide range of feature sizes and aspect ratios, as shown in Figure 10.

Via diameter (µm) Fig. 10. Void-free electrodeposition of various TSV structures Due to the complexity of this process and the large number of variables that could affect the final process performance, the plating mechanism is still not fully understood and continues to be investigated. In order to throughput and reduce the costs associated with this process, continuous efforts to develop faster and more stable processes are in progress.

Fig. 1 .

 1 Fig. 1. Blind-via filling before wafer thinning [10]: (a) Via formation, insulator/barrier/seed deposition; (b) Via filling; (c) Metal removal, wafer thinning

Fig. 2 .

 2 Fig. 2. Through-via filling after wafer thinning [10]: (a) Thinning / via formation/seed deposition; (b) Via filling; (c) Seed removal

Fig. 3 .

 3 Types of deep-via deposition: (a) lining; (b) full-filling, and (c) full-filling with stud formation

9- 11

 11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5

  [START_REF] Schmauch | 3D Packaging Enabled with Electrochemical Deposition Techniques from Varied Electronic Industry Segments[END_REF][START_REF] Kim | High Aspect Ratio Via Filling with Copper for 3D Integration[END_REF].

Fig. 4 .

 4 Fig. 4. Filling profiles: (a) sub-conformal profile, with void at the bottom; (b) conformal profile, with seam void; (c) conformal profile, void-free, bottom-up filling

Fig. 5 .

 5 Fig. 5. Via profiles: (a) tapered; (b) straight; (c) re-entrant (Source: Alcatel Micro Machining Systems)

9- 11

 11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5 top and, at the same time, highly accelerated deposition at the bottom.

Fig. 6 .

 6 Fig. 6. Bottom via due to insufficient seed layer coverage

Fig. 7 .

 7 Poor deep-via electrodeposition due to: (a) poor wetting; (b) oxides present on the seed layer (or inconsistent seed layer coverage)

Fig. 8 .

 8 Fig. 8. The effect of average current density on fill performance: (a) full filling (12µm diameter/100µm depth); (b) partial filling (40µm diameter/100µm deep vias)

Fig. 9 .

 9 Effect of waveform on via filling: (a) direct current (DC); (b) pulse current (PC); (c) and (d) pulse reverse (PR) with different reverse currents 9-11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5

ACKNOWLEDGMENT

The authors would like to thank James Burnham, Paul Kusler and Ross Kulzer for their continuous help with development and FIB/SEM analysis and acknowledge the contribution of Bioh Kim (EVG Group) who initiated this work while employed at Semitool.


Chi-Jia Tong

Ming-Tzer Lin

Process nano scale mechanical properties measurement of thin metal films using a novel paddle cantilever test structure

Process nano scale mechanical properties measurement of thin metal films using a novel paddle cantilever test structure

Chi-Jia Tong, Ming-Tzer Lin

INTRODUCTION

Microelectromechanical systems (MEMS) technologies are developing rapidly with increasing study of the design, fabrication and commercialization of microscale systems and devices. The roadmap for MEMS plans for developing the complexity and packing density of devices into the future allowing ever smaller in the range of nanometer scale and more densely packed structures to be fabricated. Continued growth of Microsystems technologies requires still further miniaturization, with a corresponding need to understand how length scales affect mechanical behavior of all the components. Accurate knowledge on the mechanical behaviors of thin film materials used for MEMS is important for successful design and development of MEMS.

Although many previous studies had performed on the characterization of mechanical behavior on thin films, the results obtained from different measurement techniques were vary widely for nominally identical samples due to the difficulty with the techniques. Example such as the nanoindentation experiment on thin film is stronger correlated its substrate. Therefore, the ISO (International Standard Organization)-14577 had defined the proper measurement range of using Nano Indentation test that the contact depth has to be <200nm & h<t/10, where t is film thickness. As a result, it limited the ability to do extensive study of thin film.

Here a new technique was developed for studying the mechanical behavior of Nano-scale thin metal films on substrate. The test structure was designed on a novel "paddle" cantilever beam specimens with dimensions as few hundred nanometers to less than 10 nanometers. This beam is in triangle shape in order to provide uniform plane strain distribution. The experiment is designed to be operated by using the electrostatic deflection on the "paddle" uniform distributed stress cantilever beam and then measure the deposited thin metal film materials on top of it. Thus allow us to explore mechanical function mechanisms in thin films and film of the thickness on nanoscale regime.

II. DESIGN & DEVELOPMENT PROCEDURES

In traditional microbeam bending, cantilevered beams of the film of interest are fabricated by micromachining. The end of the beam is deflected using an indentation apparatus which senses vertical displacement. Elastic properties of the thin film material can be determined from the measured load-displacement characteristics [START_REF] Weihs | Mechanical deflection of cantilever microbeams: a new technique for testing the mechanical properties of thin films[END_REF][2][START_REF] Schweitz | Mechanical characterization of thin films by micromechanical Techniques[END_REF]. If a thin film is deposited on a thicker free-standing cantilever, (e.g. silicon) plastic properties of the thin film can be probed as well [START_REF] Schweitz | Mechanical characterization of thin films by micromechanical Techniques[END_REF].

However, the primary drawbacks in common beam bending, due to the non-uniform distribution of stresses, only a small portion of the sample (at the root of the beam) is exposed to the maximum load. One would thus expect to see higher values for yield strength from beam bending experiments compared to techniques which sample larger volumes. In addition, using indentation apparatus providing vertical displacement for the beam will generate localized effects in the vicinity of the loading point due to its destructive force and complicated analysis processes.

The "paddle" cantilever beam approaches here was to design a "constant stress" cantilever beam that eliminate the non-uniform distribution of stresses along the cantilever. In a cantilever beam with a single localized load at the free end, the bending moment varies linearly from zero at the point of load application to a maximum at the built in end. Thus for a parallel sided beam, as in the preceding sketch Fig. 1, the axial stress on the beam surface is proportional to the bending moment; and, is expressed by: ISBN: 978-2-35500-006-5

Where: σ (x) = bending stress on the beam surface at a distance X from the point of load application, psi (N/m 2 ) M(x) = bending moment at distance X, in-lbs. (mN) c = t/2 = distance from neutral axis to beam surface, in(m) I = bt 3 /12 = Moment of inertial of beam cross-section, in 4 (m 4 ) Z = bt 2 /6 = Section modulus of beam, in 3 (m 3 ) b = beam width , in (m) t = beam thickness, in (m) Thus, through the design of a cantilever section which modulus can be made proportional to X by making the width proportional to X, and holding the thickness constant, thus stress is constant from one end of the beam to the other. This constant-stress "paddle" cantilever beam is shown in Figure 1 and was primary discussed in various studies in bulk structure [4].

Figure 1: A constant-stress cantilever beam [4] In addition, the electrostatic deflection force on the designated plate to drag "paddle" cantilever beam can be used instead of using indentation apparatus to provide vertical displacement for the beam. Thus can reduce localized effects in the vicinity of the loading point.

A. Sample design and fabrication

The single test chip is designed (Figure 2) to fit in an apparatus where one side of the paddle plate is pulled by an electrostatic field. The measured strain was converted through the capacitance measurement for the deflection of the cantilever.

The sample is shown as the structure of a 20mm╳20mm chip with paddle as shown above in plane view and cross section. The thin silicon beam (40 um thick) has a triangular shape in plane view to provide uniform strain in a metallic film on its surface when the beam is bent with force on the paddle. Figure 2 shows the front side and backside view of the sample. frontside backside The sample fabrication procedure is using standard clean room processing for MEMS structures. We utilize these techniques and develop one of the simplest sample fabrication processes to conduct an experiment that can maintain consistent sample preparation and excellent yield procedures. The sample is fabricated on a standard 4 inches diameter double polished silicon wafer. Each wafer consists of 7 test chips after standard clean room fabrication. Fabrication can be carried out either with crystallographic etching in KOH or deep Si plasma etching. The detail of the fabrication process sequence is outlined:

A 220 um thick doubly polished Si wafer with 75 mm in diameter is coated by LPCVD SiN x on both sides. The two SiN x surface are patterned with masks as shown above. The wafer is then etched from both sides in hot KOH. After 110um of the silicon has been etched from each side, the paddle is free from the surrounding frame expect at the left-hand end. Etching is continued until the beam section has desired (40um) thickness after which the wafer is rinsed and dried. The paddle has the full thickness of the wafer. Cleavage streets 75 um deep (defined by the width of the patterned line on one mask) are etched from one side. The individual chips may be cleaved from the wafer at this point as the test chip carrier. Then either individually blanket metallized thin film, or the whole wafer may be blanket metallized can be deposited with desired thickness and film materials for the following tests of interested.

The structure can be metallized from both sides. No processing is required after the metal has been deposited. If desired, the SiN x may be removed by reactive ion etching (RIE) before metal deposition. Later, a metallic conducting surface is required on both sides of paddle for stable deflection and capacitance measurements to be made. Figure 3 shows the KOH process schematic. the full thickness of the wafer. Etching from the back creates the desired beam thickness. It may be desirable to the process with slightly non-vertical sidewalls to facilitate producing continuously conducting surfaces on both sides of a chip when it is metallized on tested thin film. Figure 4 shows the deep RIE process schematic. The finish paddle sample is shown in Figure 5 and 6. The figure 5 is the whole sample view; the white zone is after KOH etching and the Figure 6 shows just paddle plate. The Figure 7 is the wafer just finish KOH etching.

B. Testing System

The apparatus is custom design and the system set-up is design to measure beam deflection by capacitance. It consists of the guard-ringed capacitor electrode, the metal spacer, the calibration sample and the deflection electrode. Figure 8 shows the schematic of the measuring system. The sample chip is mounted together with a guard-ringed capacitor electrode as shown below. A spacing of 25 to 125um to the window frame chip surface around the paddle structure is defined by a metallic spacer. Where A is the capacitor plate area, d is the spacer thickness and ε 0 is dielectric constant. Thus we can have linear correlation between deflection space and the accurate capacitance value.

A second electrode is mounted below the paddle plate. This electrode is used for electrostatic deflection of paddle. The whole chip is at DC ground but driven at 100 kHz with amplitude of a few volts. That provides a displacement current to central electrode of the capacitor plate which is proportional to the capacitance, and hence inversely proportional to the gap. Depending on the spacing selected, the capacitance is between 2 and 4 pF. The measurement of the capacitance can be made to a precision of approximately 0.1 fF so that paddle spacing changes of 50 nm are readily determined. The paddle can be pulled up with a DC voltage on the guard-ringed electrode or pulled down with a DC voltage on the lower electrode. The

C. Measurements of specimen bending and strain

For the electronic setup of the capacity measurement, a sine-wave generator at 100 kHz is applied to the film simultaneously measuring capacity of the paddle capacitor while a second generator drives at the same frequency for a test capacitor which has a known capacity. The two units are coupled (one master, one slave) and have a phase shift of 180 0 . Figure 9 shows the circuits. The 180 0 out of phase currents from the two generator-capacity pairs are summed at input of change sensitive preamplifier. The amplified sum is measured with lock-in amplifier with the reference signal from one of the frequency generators.

When the current flowing through the two capacitors is approximately equal, the lock-in will show a value close to zero. In this case the ratio of the capacities is inversely-proportional to the ratio of the amplitudes of the driving:

C V Z V Z V C V 2 2 2 2 1 1 1 1 ~⋅ = ⋅
If now the capacitance of the paddle capacitor is changed by a change in y p , the 180 0 out of phase currents are unbalanced and the lock-in amplifier will measure the difference. The measurement is controlled by PC through National Instrument LabVIEW program. The control electronics include a controller, amplifier and waveform generator. Monitored signals are conditioned and then fed into an A/D board which is located in a PC. Data acquisition is performed with LabVIEW software. During sample testing, it is placed inside the chamber, and the samples are monitored with an optical microscope. After the sample is being locked inside the system, then wait until the system is reaching the thermal equilibrium and the capacitor read out is clear, the test can be perform.

D. System Calibration

The calibration of the testing system is done to see if a linearity of capacitor value respect to the space between the paddle face and top electrode panel can be obtained. After the system is built, we can set up spacer of different thickness between 25 and 125um to hold the metal film on the sample at a fixed distance from metallic film on the Pyrex plate. Together with the metal film on the sample this plate forms a capacitor. A guard ring connected to ground surrounds the capacitor, shields it from stray signals and minimized fringe capacitance. The outermost region of the pattern metal film provides electrical connection to the sample. With different spacer we can calculate respected capacitance value at the same time we can also measuring the capacitance with different spacer and check the linear correlation between the capacitance value and the spacer thickness. Figure 10 shows an example of calculated capacitance value versus 1/d which can be used as the calibration reference line of the system.

III. CALCULATION RESULTS & DISCUSSIONS

The mathematical studies of system performance were done to verify the performance of the systems. For all the measurement, the overall performance on the capacitance, electrostatic electrode and the paddle cantilever as shown in Figure 11 is essential. As we can observe in this plot when the force is equal to zero imply the system is in its equilibration position with no electrostatic force.

IV. CONCLUSION

A novel "paddle" cantilever beam specimens with dimensions as few hundred nanometers to less than 10 nanometers is designed and fabricated. The experiment can be operated by using the electrostatic deflection on the "paddle" uniform distributed stress cantilever beam and then measure the deposited thin metal film materials on top of it. Capacitance techniques were used to measurement on the other side of the deflected plate to measure its deflection with respect to the force. The measured strain was converted through the capacitance measurement for the deflection of the cantilever. System performance on the residual stress measurement of thin films are calculated with three different forces on the "paddle" cantilever beam, including the force due to the film, compliance force and electrostatic force. The calculation helps to predict system performances including capacity versus bending high, driving voltage versus electrostatic force, maximum deflection and the free end of cantilever beam position in different residual stress. They also provided proof of the testing approach as well as potential use for the design and development of MEMS

Figure 2 :

 2 Figure 2: Schematics view of sample

Figure 3

 3 Figure 3 KOH etching process for an example of thin metal sample Tapered sidewalls are naturally produced with KOH etching. The alternative is to use deep RIE. It produces the vertical sidewalls and the processes are clean and easy. Processing with deep Si etching is also a two-mask process. Etching from the front can define the paddle geometry through

Figure 4 :

 4 Figure 4: RIE etching process for an example of thin metal sample

Figure 5 :

 5 Figure 5: A finished paddle sample

Figure 8 :

 8 Figure 8: System schematicDuring the experiment, we apply an electrostatic force to the specimen and measure the capacitance change. The deflection of the paddle beam can be measured from the capacitance value which is described by

  be made with a time resolution of ± 10 msec.

Figure 9 :

 9 Figure 9: Electronic setup for the capacity measurement

Figure 10

 10 Figure 10 Calculated Capacitance versus 1/spacer thickness

Figure 11 ε

 11 Figure 11 Schematic arrangements of capacitance, electrostatic electrode and the paddle cantilever Whenever the cantilever is bent, the capacitance of the paddle cantilever structure is ( )

Figure 12

 12 Figure 12 Schematic view of electrostatic force deflection. In this case y(X) = d c -y b -slope‧x and the slope of the paddle plane is 2y b /l b . This yields

Figure 13 :ε

 13 Figure 13: Capacitance versus y p position for d c = 100um; l p = 5mm; l b = 3mm.The electrostatic force on the paddle is given by ( )∫ ⋅ + + = l X slope

Figure 14 :ε

 14 Figure 14: Electrostatic force versus y p position for l p =5mm; l b =3mm; d e =100umFor these dimensions the maximum value of y p is 61.53um because at that point the end of the paddle touches the capacitance plate. The minimum value is -61.53um because the paddle then touches the deflection electrode.The total force on the paddle isF F F F e P

Figure 15 :

 15 Figure 15: Film and beam force together versus y p position for initial stress in the film is 100, 200 and 300MPa

ACKNOWLEDGMENT

The authors are grateful to Prof. Walter Brown of Lehigh University for valuable discussions. This work was supported by Taiwan National Science Council; grant number NSC96-2221-E-005-082.


Y.-H Wang

Tzu-Han Hsueh

Rong-Hua Ma

Chia-Yen Lee

Lung-Ming Fu

P.-Ch Chou

Chien-Hsiung Tsai

Yu-Hsiang Wang

Ming Fu

Po-Cheng Chou

A Microcantilever-based Gas Flow Sensor

published or not. The documents may come

INTRODUCTION

Flow measurement is a necessary task in such diverse fields as medical instrumentation, process control, environmental monitoring, and so forth. Many previous studies have demonstrated the successful applications of MEMS techniques to the fabrication of a variety of flow sensors capable of detecting both the flow rate and the flow direction [START_REF] Adamec | MEMS wind direction detection: from design to operation[END_REF][START_REF] Kim | Measurement of flow direction and velocity using a micromachined flow sensor[END_REF][START_REF] Makinwa | Constant power operation of a two-dimensional flow sensor using thermal sigma-delta modulation techniques[END_REF][START_REF] Ozaki | An air flow sensor modeled on wind receptor hairs of insects[END_REF]. Broadly speaking, MEMS-based gas flow sensors can be categorized as either thermal or non-thermal, depending upon their mode of operation.

Many thermally-actuated gas flow sensors apply some forms of resistors to evaluate local temperature changes [START_REF] Adamec | MEMS wind direction detection: from design to operation[END_REF][START_REF] Kim | Measurement of flow direction and velocity using a micromachined flow sensor[END_REF][START_REF] Makinwa | Constant power operation of a two-dimensional flow sensor using thermal sigma-delta modulation techniques[END_REF]. In such sensors, the temperature difference between the sensing resistors varies as the gas flow passes through the sensor, and the comparison of the resistance variations among each resistors enables the gas flow direction to be determined. Adamec et al. [START_REF] Adamec | MEMS wind direction detection: from design to operation[END_REF] fabricated a multi-axis hotwire anemometer with four thermoresistor to evaluate flow direction with a power consumption of 25 mW. Kim et al. [START_REF] Kim | Measurement of flow direction and velocity using a micromachined flow sensor[END_REF] presented a circular-type thermal flow sensor consists of a heater and circular-type temperature sensors to detect flow direction and velocity. However, the power consumption of this device exceeded 80 mW. Recently, non-thermal gas flow meters have been developed. These devices typically have the advantages of lower power consumption and an improved potential for integration with other sensors. Ozaki [START_REF] Ozaki | An air flow sensor modeled on wind receptor hairs of insects[END_REF] fabricated an air flow sensor modeled on windreceptor hairs of insects which can detect low velocity of air flow, but the maximum measurable flow rate was just 2 ms -1 . The practicality of the device for flow rate sensing applications was severely limited. Wang et al. [START_REF] Wang | A MEMS-based Air Flow Sensor with a Free-standing Microcantilever Structure[END_REF][START_REF] Ma | Micromachined Silicon Cantilever Paddle for High-Flow-Rate Sensing[END_REF][START_REF] Ma | Microcantilever-based weather station for temperature, humidity and flow rate measurement[END_REF] fabricated an air flow sensor with a free-standing microcantilever structure which has a high sensitivity (0.0284 Ω/ms -1 ) and a high velocity measurement limit (45 ms -1 ). In the current study, four cantilever beams are formed and the measured values of four piezoresistors on them are compared to determined the airflow direction. The flow rate can also be measured by calculating the total resistance variations on the four cantilevers.

II. DESIGN AND FABRICATION

A. Shape Design

As shown in Fig. 1, the electrodes used to connect the piezoresistor to the external LCR meter are fabricated from gold since gold has a lower resistivity than platinum, and hence the resistance effect of the leads is reduced. The resistance R of the piezoresistor is given by cross-sectional area, w is the width and t is thickness. The derivative of (1) is

wt l A l R R R ρ ρ = = (1)
t dt w dw l dl d R dR R R - - + = ρ ρ (2)
where defines

R R l l dl = ε , l dl ∆ = , w dw ∆ = and t dt ∆ = , then it could be rearranged to ) 2 1 ( v R dR l + ≈ ε (3)
As shown in Fig. 2, when air flows over the cantilever structure, the beams are deflected that causing a change in the cross-sectional area, and hence the resistance of the platinum resistor changes. The corresponding airflow velocity and direction can then be evaluated and determined simply by measuring the resistance change using an external LCR meter.

B. Shape Design

Fig. 3 indicates the configuration and dimensions of the cantilever beams and platinum resistors considered in this study. In Fig. 3(a), the periphery of the black line indicates the cantilever beams. In Fig. 3(b) the black netted area corresponds to the platinum resistors. All units are µm. As shown in the figures, the gas flow sensor is assembled with four cantilever beams that perpendicular to each other and manufactured with piezoresistors on each micro-cantilever.

C. Fabrication

Fig. 4 presents an overview of the fabrication process used for the current micromachined gas flow sensor. Initially, a low-stress nitride layer of thickness 1.0 µm was deposited on either side of a 500 µm thick double-side-polished silicon wafer. A thin layer of Cr (0.03 µm) was then deposited on the upper surface of the wafer to form an adhesion layer for the subsequent deposition of the platinum resistors. The platinum resistors (0.1µm thickness) were deposited using an electron -beam evaporation process. The same technique was then used to deposit a layer of Au (0.1µm thickness) on the resistors to serve as an electrode and to provide electrical leads. To form the micro-cantilever beams, the cantilever structure and a back-etching nitride mask were patterned in SF 6 RIE plasma. In the etching process, the cantilever structure was released in a KOH etchant (40 wt %, 85 o C, supplied by J. T. Baker). Following the etching process, the total micro-cantilever beam thickness was 20 µm (nitride: 1µm / silicon: 19 µm) and the cantilever beams exhibited an upward bending effect as a result of the stress relaxation caused by the thermal stress induced in the heating and cooling steps performed before etching. This phenomenon causes an initial beam deformation position which assists the flow rate sensing function. To increase the reliability of the micro-cantilever, a small thickness of silicon was retained to act as an understructure. Fig. 5 presents a scanning electron microscope (SEM) image of a typical freestanding structure fabricated in this study.

III. RESULTS AND DISCUSSION

A systematic investigation was conducted into the performance of the fabricated micro gas flow sensors. The characterization of the sensors was carried out with a rotary table (LC-PR60, TanLian E-O Co., Ltd., Taiwan) in a wind tunnel, and the relative position between the air flow direction and the sensor is shown in Fig. 6. The variation in the sensor resistance as the airflow passed over the cantilever was measured using an LCR meter (WK4230, Wayne Kerr Electronics Ltd., Taiwan). For reference purposes, a Pitot tube flow meter was also used to measure the velocity of the airflow.

A. Flow Rate

For the of measurement of the flow rate in the wind tunnel, the relationship between the sum of the absolute value of resistance variation in all the four piezoresistors on the beams and flow rate is shown in Fig. 7. It shows that as the airflow direction was at 180 o or 135 o direction, the sum of the absolute values of the resistance variation was equal and it just depended on the flow rate.

B. Flow Direction

For the measurement of the flow direction, a strong dependence of the measurement was found on the geometrical setup of the sensor axes. It is necessary to assure the cantilevers precise location with the angle 90 o . As the airflow pass through the gas flow sensor from 180 o , the largest resistance variation was caused by the downwind cantilever deformation, and the least resistance variation was caused by upwind cantilever deformation. The resistance variation of cantilever beams that perpendicular to the airflow direction are almost equal to zero. The measured values at different flow rate, 30, 25, 20 and 15 m/s, are shown in Fig. 8.

IV. CONCLUSIONS

The current study develops a MEMS-based gas flow sensor featuring a free-standing micro-cantilever structure. In the sensing operation, the air flow velocity is detected by measuring the change in resistance of the piezoelectric resistors deposited on the cantilever beams as the beam deforms under the effect of the passing airflow and the airflow direction can be obtained by comparing the resistance variation difference between the upstream and downstream cantilever beams to evaluate the airflow angle.

Figure 1

 1 Figure 1 Schematic illustration of gas flow sensor.where l R is the resistor length, ρ is the resistivity, A is the

Figure 2 Figure 3

 23 Figure 2 Diagram of gas flow sensor during sensing operation.

Figure 4 Figure 5

 45 Figure 4 Overview of fabrication process employed for proposed flow sensor.

Figure 6

 6 Figure 6 The relative position between the initial air flow direction and the sensor.

Figure 7

 7 Figure 7 The relationship between the airflow velocity and the total resistance variation when airflow direction was 135 o , and 180 o .

Figure 8

 8 Figure 8 The relationship between the airflow angle and the resistance variation when airflow velocity was (a)15 ms -1 [○], (b)20 ms -1 [∆], (c)25 ms -1 [□] and (d) 30 ms -1 [◊ ].

ACKNOWLEDGMENT

9-11 April 2008 ©EDA Publishing/DTIP 2008 ISBN: 978-2-35500-006-5 The authors would like to thank the financial support provided by the National Science Council in Taiwan (NSC 96-2221-E-212-037 and NSC 95-2218-E-006-022).


Haifa El-Sadi

Nabil Esmail

Simulation of Coating -Visco-Elastic liquid in the Mico-Nip of Metering Size Press

for a set of operating conditions and coating color formulations, undesirable phenomena like color spitting and coating ribs may be triggered in the Micro-nip during the coating process. Therefore, our interest in this work focus on another parameter affect on the undesirable phenomena as the vortices in the Micro-nip. The problem deals with the flow through the Micro-nip of metering size press. The flow enters and exits at a tangential velocity of 20 m/s between two rollers with diameter 80 cm and 60 m apart. In the upper and bottom part of the domain the angular velocity is 314 rad /s. It has one sub-domain. Previous studies focus on the Micro-nip without considering the inertia and the viscoelasticity of the material. Roll coating is a technique commonly used in the coating industry to meter a thin fluid film on a moving substrate. During the film formation, the fluid is subjected to very high shear and extensional rates over a very short period of time. The fluid domain changes as a function of the hydrodynamic pressure within the nip as a result of the deformable cover usually used on one of the rolls. The free surface also adds more complexity to the flow due to the force equilibrium in the fluid gas interface. Last of all, the rheological behavior of the coating fluid is usually non-Newtonian, so the metering flow hydrodynamics is finally very difficult to describe. It is concluded that the normal forces of micro-nip increases with increasing the inhibitors. Therefore, it affects on the smoothness and creates defects. On the other hand, it can be concluded that the creation of big vortex in the middle of micro-nip affects on the coating liquid behavior.

INTRODUCTION

Last few years, researchers have used the lubrication theory as well as Navier Stokes equations (CFD models) to investigate reverse roll coating flows [START_REF] Greener | Reverse Roll Coating of Purely Viscous Liquids[END_REF][START_REF] Kang | Minimum Film Thickness for Reverse Roll Coating[END_REF][START_REF] Coyle | The Fluid Dynamics of Reverse Roll Coating[END_REF][START_REF] Coyle | A Simple Model of Reverse Roll Coating[END_REF][START_REF] Coyle | Reverse Roll Coating of non-Newtonian Liquids[END_REF][START_REF] Fourcade | Finite Element Analysis of Fluid-Solid Interaction in the Metering Nip of a metering size Press[END_REF][START_REF] Poranen | Experimental and Theoretical Study for Metering Size Press[END_REF]. For the lubrication theory, the main hypothesis is that inertia effects are minimal and therefore neglected. The flow can be represented by dP/dx = µ ( 2 x/ y2) [START_REF] Greener | Reverse Roll Coating of Purely Viscous Liquids[END_REF].

Greener and Middleman [START_REF] Greener | Reverse Roll Coating of Purely Viscous Liquids[END_REF], using both vanishing pressure and pressure gradient as boundary conditions, predicted the coating thickness on the transfer roll for a relatively narrow range of metering rod to transfer roll speed, although the flow rate deviated from the predictions of the model due to some recirculation upstream from the nip.

Coyle et al. [START_REF] Coyle | The Fluid Dynamics of Reverse Roll Coating[END_REF] showed that the metered nip flow deviates from the lubrication theory predictions at high speed ratios and capillary numbers. The dynamic wetting line moves towards the nip center, the nip length shrinks, and the film thickness passes through a minimum.

Most of previous studies of forward roll coating focused on the simple case of two rigid rolls separated by a narrow gap [START_REF] Pitts | The Flow of Thin Liquid Films Between Rollers[END_REF][START_REF] Savage | Mathematical Models for Coating Processes[END_REF][START_REF] Coyle | The Fluid Mechanics of Roll Coating:Steady Flows, Stability, and Rheology[END_REF]. In many cases, one of the rolls is rubber covered, and both rolls are pressed against each other by an external load W. The coating thickness is thus governed by the operating parameters (speeds and loading), mechanical properties of the solids and the mechanical properties of the fluid. The general features of roll coating operations involving a deformable roll have been described by Coyle [115]. together with various types of boundary conditions. As part of the same package, (a preprocessor) Gambit is used to draw the geometry and generate the required grid for the solver. An unstructured grid with triangle elements is used as shown in Figure 1. The upper and lower walls were divided into non-uniformly spaced elements using pave meshing scheme with a ratio 0.1. The steady shear viscosity for coating colors depends on the concentration of added inhibitors. The viscous and elastic moduli of coating colors increase with increasing concentration of inhibitors, which is related to strong interaction between the particles.

Since the viscosity is increasing with increasing the yellowing inhibitor, the viscosity of the coating liquid with 1% inhibitor was 0.7 pa.s, the viscosity of coating liquid with 0.6% inhibitor was 0.3 pa.s and the viscosity of coating liquid without inhibitor was 0.15 pa.s. the relaxation time was 0.01.

B. Mathematical Equations

The KBKZ model provides additional accuracy by including a damping function in its constitutive equations.the KBKZ model can calculate the extra stress tensor (T) which is = T1 +T2.

Where T1 is computed from:

(

and T2 is computed from Equation:

(

) 2
where D is the rate-of-deformation tensor and 2 is the viscosity factor for the Newtonian (i.e., purely-viscous) component of the extra-stress tensor. The viscosity ratio r is defined as 2 / . The relationship of 1 and 2 to is expressed by: (4) and ( 5)

In Equation ( 1), i is the index of the relaxation mode and θ θ θ θ is a scalar parameter that controls the ratio of the normalstress differences: [START_REF] Fourcade | Finite Element Analysis of Fluid-Solid Interaction in the Metering Nip of a metering size Press[END_REF] and H is the damping function.

The

Papanastasiou-Scriven-Macosko (PSM) model computes H from [START_REF] Poranen | Experimental and Theoretical Study for Metering Size Press[END_REF] where α α α α is a material parameter that primarily influences the shear-thinning behavior. The default value for α α α α is 1, which may be unrealistic for many fluids, due to the large possible range of this parameter. The Papanastasiou-Scriven-Macosko (PSM) has a reversible and an irreversible function type. The irreversible PSM model allows H only to decrease.

C. Results and Discussion

Figure 2 shows the contour of velocity distribution. It shows the formation of big vortex. . Therefore, it affects on the smoothness and creates defects. On the other hand, it can be concluded that the creation of big vortex in the middle of 9-11 April 2008 micro-nip affects on the coating liquid behavior

Fig. 2 .

 2 Fig. 2. the velocity contour in the micro-nip II.

  is a material parameter that influences only the elongational behavior of the material. Table F reveals the material properties of different coating colors. It can be noticed the effect of inhibitors on the properties of coating color.