First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits

Chapter 1: Introduction AI (Artificial intelligence) is a very fresh and hot topic application area that can benefit from the 3D IC. Google AlphaGo and IBM Watson's Jeopardy defeat the best human Shogi player, but they all ran on server clusters, which are too difficult for widespread use. Today automatic driving technique uses more specialized processors, but the automobiles are not safe enough. The safety need will require more sophisticated control systems that are likely to increase computational requirements.

As we know from "von Neumann bottleneck", data moves between the separate MPU (microprocessor unit) and memory. In this case, latency is unavoidable. These years, processor speeds have increased significantly to about 4.2 GHz. But the memory improves mostly in the density, that's to say that the memory can store more data in a fixed space, rather than in the augmentation of transfer rates. As MPU working frequency has increased, the processor has spent an increasing amount of waiting time, in order to write and read from memory. So no matter how fast the MPU can work, it is limited by the memory transfer rate. [1], [2] Figure 1 Performance (speed) gap between MPU and memory increasing with time [3] (Performance's unit is number of transistors per unit cm 2 )

So the next generation of AI architectures is emerging the need for more densely integrated memory and processor. For example, the memory occupies a very big space in the IBM's TrueNorth neural network chip, Google TensorFlow and the new generation of GPUs used in automatic driving cars have huge memories.

1.1) From Two-Dimension (2D) IC to Three-Dimension (3D) IC

As Figure 2a illustrates, a traditional von Neumann computer system is the heterogeneous integration of logic cells (yellow), memory chips (orange), and the interconnections (gray). For example, here Data A saves the data from RF electronics, Data B saves data from camera sensors, First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 9

the dynamic random-access memory (DRAM) process has a 10× higher memory density than the same generation's logic cell. So the cache in the MPU is too small for the implementation of memory, and the data must inevitably be moved through the high-energy loss route between logic and memory, twice per communication (as shown in the green line).

Figure 2b shows the equivalent data-transmission route for one merge stage of a bitonic sort. The light yellow logic layer on top (with black points) shows the merging of four stages of bitonic sort. When applying the structure in Figure 2b, the comparisons and exchange can be placed on the logic layer. Data to be calculated (Data A) and a place of storage (Data B) are located in the bottom orange memory and connected through short wires crossing the large 2D plane, rather than a border. For the 3D structure in Figure 2b, data can be read all at once from memory, and then compared and exchanged in hardware. A traditional computer will need to transport all the data from memory to the processor sequentially, so, the memory bottleneck becomes a principal issue when processing a huge amount of data and other low-level kernels in artificial intelligence (AI). So the 3D circuits has a better advantage. Moore's Law seems to be showing down. Because of the physics limits, the technical challenges of continuously miniaturization are difficult to overcome, which is increasing the cost and slowing the pace of scaling. In addition, the benefits of scaling are decreased because of the mismatch between the scaling and the former performance advantages. So the future semiconductor industry focuses on two technical issues. Functional diversification is the first direction. It is the main driving force of System-In-Package (SiP) architecture. The second one is 3D IC, as shown in the Figure 3. This can gain the functionalities of one given node and also First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 10 increases performance and reduces power supply. There are several driving factors for 3D integration. The benefits include better performance, reduced power supply, reduced latency, lower cost and smaller size compared to 2.5D and 2D plane packaging. Some of the basic driving factors for 3D integration are presented in the Figure 4 below. [4] Figure 3 Elements incorporated into complex SiP packages through heterogeneous integration Figure 4 Driving forces for 3D Integration [START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF], [START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF] 3D IC leads to a revolution of potential new scale-up. The interconnections between logic and memory has restricted systems for decades. Solving this bottleneck could continue improving system performance and advancing semiconductor industry. However, in order to get the advances, it needs some more time to work through the engineering processes (as shown in Figure 4 and Figure 5). But every little breakthrough in the engineering processes will reduce the von Neumann First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 11 bottleneck's impact. For applications that could benefit from denser integration, this could offer continuous performance increases as linewidth scaling.

1.2) Roadmap of 3D Integrated Circuits

Computing performance can be substantially improved by monolithically integrating several new heterogeneous memory layers on top of logic layers powered by a combination of CMOS and "new switch" transistors. This new phase, called 3D power scaling, will continue to support an increase in transistor count at Moore The 2D integration will reach the point where no more 2D scaling will be possible, the death of Moore's law is spoken out everywhere, but the development of vertical integration of transistors and integration of layers of vertical transistors is on the way to continue increasing the transistors' density per cm 2 at a same or faster velocity than Moore's law in the future.

The 2017 IRDS (International Roadmap for Device and System) road map projects the development of integrated-circuit technology for the next 15 years. Figure 5 offers a preview [2]. As we can see, 2D planar scaling in accordance with Moore's law is predicted to end until the mid-2020s, after which further advances will come mainly from the stack of layers. This miniaturization will reduce die purchase fee, energy costs and operational benefits [START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF]. This evolution demonstrates that 3D VLSI offers the possibility to stack devices and enable high-density interconnects at device level (100 million "via" per mm 2 ), as Table 1 shows. 3D packaging has been available for decades in large scale, with interconnections, performance, and energy efficiency. Fully integrated 3D (3D Monolithic) is supposed to be available in less than one decade.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 12 In the 1970s, two fundamental laws became the footstones for the whole industry: Moore's and Dennard's scaling laws. Dennard's scaling law presented how to improve transistor performance by means of geometrical scaling. At the beginning of the previous decade, physical scaling (the gate oxide thickness limit) came to a halt, and the advent of new transistor by reducing the horizontal dimensions and introducing new materials and new physical effects continues the Dennard's law. The new era is name equivalent scaling. And the vertical structures begin replace planar transistor. The predictive revolution date is 2021. At that moment, device built via 2D scaling will reach a fundamental manufacturing 2D physics limit, the transition to complete vertical device structures, heterogeneous integration in conjunction with reduced power consumption become the technology drivers. [2], [3] Figure 6 The different ages of scaling

The IRDS projects also five steps of functional transition from 2D to 3D VLSI: (here include the functional heterogeneous devices as sensors, new storage devices, alternative logic and memory devices or circuits)  Two stacked layers with large scale components such as analog, I/O, and power management, MEMS in one layer and high-performance logic and memory in the other.  Monolithic integration of two layers, where each layer contains one of the two fundamental transistor types in logic, NMOS and PMOS (n-channel and p-channel MOS), stacked on top of each other in order to increase logic density.  Two layers: logic and memory.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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 Analog, I/O, and RF connectivity as an extra layer, giving more freedom to include special devices in the design.  3D VLSI with fine-pitch logic-on-logic as well as special functional layers exploiting new architectures

1.3) Development of 3D IC

Today, memory producers, they are facing similar problems because they have no space in 2D, and the cost of producing memory circuits of small dimensions keeps rising while the number of stored electrons in the floating gate keeps decreasing. To solve these problems, memory producers have already worked out and announced several new architectures that stack multiple layers of memory on top of each other in a single IC. As many as 48 and 96 layers of flash memory have been reported. Table 2 shows the prediction of flash memory devices for more than 100 layers. So heat removal and reduction of power will be the two main issues in the 3D power scaling. Maximum number of bits per cell for 3D NAND 3 3 3 3 3 3 3

Figure 7 Example 3D architecture of future monolithic integrated circuits [3] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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Beyond 2020, the future ICs architecture will change to a type of structure similar to the one in Figure 7. This new method of scaling, which is capable of stacking multi-layers in a 3D devices level, can substantially accelerate Moore's law. Research on new switches began in 2005. By 2010, the tunnel FET (TFET) seems a potential replacer of MOS as shown in the figure 8, because of its lower operating power. [START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF] Negative capacitance FET (NC FET) has also shown as another lower operating power devise than MOS. [START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF], [START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF] CNTs (Carbon nanotube) have become the most viable switch later in the next decade, because of its energy saving and performance improvement. [START_REF] Shulaker | Carbon nanotube computer[END_REF] The number of transistors that can be integrated on a cm 2 of silicon will continue to increase at Moore's law pace for the next 10 or more years by means of 3D integration. Till now, transistor speed has continued to increase during this decade, and the operation frequency of transistor has already arrived at 100 GHz if power dissipation wasn't a bottleneck, but because of the power dissipation limits of ICs, today's MPU's operating frequency has been limited to a few GHz (CPU intel Core i9 4.2 GHz). So in the next decade, the goal of IC design has shifted from high frequency design to low power and better heat dissipation design.

Figure 8 Switching energy vs. delay of a 32-bit adder [START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF] Three Dimensional (3D) Integration and Packaging has been successful in mainstream devices to increase logic density and to reduce data movement distances. It solves the fundamental limits of scaling e.g. increasing delay in interconnections [START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF], development costs and variability [START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF]. Most memory devices shipped today have some form of chip-stacking involved. 3D integration have different technologies, with the development, they are wire bonding and flip chip for SiP (Silicon in Package), through silicon via (TSV) in bulk, TSV in SOI (Silicon on insulator), 3D parallel, 3D sequential (MIV monolithic inter via).

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 15 In the bulk level design (>2um), there have two stacked dies types, the interconnection via substrate, and direct connection between dice. The typical interconnection via substrate technology is wire-bonding stack. The wire bonding stack, as shown in the Figure 10(a), has a low density, low bandwidth, high latency and high power dissipation characteristic (the exact numbers can be found in the previous table 1). And TSV in bulk is the typical one of the direct connection between dice, which is the main stream of 3D interconnection because that they don't need substantial change to the existing fabrication flow, as shown in the Figure 10(b). The size in CMOS image sensors using "via last" approach has a diameter of about 50um. [START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF]- [START_REF] Charbonnier | Wafer Level Packaging Technology Development for CMOS Image Sensors Using Through Silicon Vias M1 pad on front side[END_REF]. And it has smaller size for 3D stacked memory (NAND, DRAM …) and logic circuits (MPUs with cache memory). Stacking involves drilling holes through silicon chips to provide electrical connections between layers of stacked silicon chips. Chip stacks up to 40 layers deep are available that have lower engineering costs than adding layers lithographically or epitaxial deposition. TSV offers lower bandwidth and less efficient connectivity between chip layers than adding layers with photolithography processes, but far higher bandwidth and efficiency than using conventional chip packaging. It has an advantage of 10X more links in the circuit and better bandwidth, better latency, lower power supply [START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF], [START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF]- [START_REF] Yook | High D ensity and Low-cost Silicon Interposer using Thin-film and Organic Lamination Processes[END_REF]. However, the keep-out zone (KOZ) [START_REF] Wang | An effective approach of reducing the keep-out-zone induced by coaxial through-silicon-via[END_REF]- [START_REF] Yang | Combination of electrical and thermomechanical impacts of through-silicon via (TSV) on transistor[END_REF] required for through-silicon via (TSVs) and limitations on the die alignment precision generate limits on the device integration density that can be designed using TSV-based 3D stacking [2], [START_REF] Kannan | Device performance analysis on 20nm technology thin wafers in a 3D package[END_REF].

Figure 9 Alignment capability versus 3D contact width in parallel and sequential integration schemes [START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF] Below 1um, in this field, the 3D technology's interest stays at the transistor scale design. As observed in the Figure 9, which shows the alignment accuracy between the stacked transistor layers with regards to the 3D contact width (pitch), the 3D parallel integration [START_REF] Topol | Enabling SOIbased assembly technology for three-dimensional (3d) integrated circuits (ICs)[END_REF], [START_REF] Philip | Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits[END_REF] as shown in the Figure 10(c), enables the continuously reduction after 3D TSV, the pitch reduction has been reduced to 1um. But even though some 3D SOI (silicon on insulator) architectures can reduce the First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 16 3D contact size, the 3D contact pitch remains however limited by the alignment performance, which is limited to about 1um, to guarantee a correct throughput.

3D sequential integration is the next generation of 3D integration technologies, it's also named Monolithic 3D (M3D) [1]- [4], [START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF], [START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF], [START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF], [START_REF] Chang | Design Automation and Testing of Monolithic 3D ICs : Opportunities , Challenges , and Solutions[END_REF], [START_REF] Koneru | Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits[END_REF], [START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF], [START_REF] An | Electrical Modeling and Analysis of 3D Neuromorphic IC with Monolithic Inter-tier Vias[END_REF]- [START_REF] Arabi | 3D VLSI: A scalable integration beyond 2D[END_REF]. It has been demonstrated that 3D interconnections and planar contact pitches are matching even for advanced nodes [START_REF] Topol | Enabling SOIbased assembly technology for three-dimensional (3d) integrated circuits (ICs)[END_REF] and it has the potential to achieve nano-scale device integration compared to TSV-based 3D stacking [START_REF] Arabi | 3D VLSI: A scalable integration beyond 2D[END_REF], and for the 3D parallel integration, one via has a connection of a few thousand transistors blocks [START_REF] Philip | Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits[END_REF], as shown in the table 3. That's too coarse-grained compared with monolithic inter-tier vias (MIVs) [START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF]. So that's why the 3D sequential integration is the only possibility to fully exploit the potential of the third dimension, especially at the transistor scale. There are three categories of M3D integration depending on the pitch of tier partitioning; transistor-level, gate-level and blocklevel M3D integration. In transistor-level M3D, P-channel transistors are placed on one tier and Nchannel transistors on another tier, and connection between them is established by MIVs. In gatelevel M3D, standard cells are split across multiple tiers, and inter-cell connections which cross tiers utilize MIVs. Block-level M3D design, which is the coarsest-grained design style, partitions functional blocks, and inter-block MIVs are deployed to deliver signals between functional modules in different tiers. Unfortunately, nowadays the commercial EDA tools to support 3D integration are temporally not available. So, various studies have been reported on M3D IC design using 3D commercial tools. M3D has also the disadvantage of device and interconnect performance mismatch between tiers, testing challenges, cost, etc. Table 3 Ratio between 3D via and planar contact pitch in sequential and parallel case [START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF] Implementation of a 3D structure including CNFETs, resistive RAM (RRAM), and spintransfer torque magnetic RAM (STT-MRAM) has already been proposed and analyzed by using N3XT (Nano-Engineered Computing Systems Technology) proposed by University of Stanford and University of California Berkeley. [START_REF] Aly | Energy-efficient abundant-data computing: The N3XT 1,000[END_REF] The structure is shown in the Figure 11. The N3XT model has been demonstrated to have a 23X speedup and 37X energy reduction, that's to say, it will have a total energy-delay product benefit of 851. [START_REF] Aly | Energy-efficient abundant-data computing: The N3XT 1,000[END_REF] Figure 11 monolithically integrated 3D system enabled by Nano-Engineered Computing Systems Technology (N3XT). On the right are the five key N3XT components. On the left are images of experimental technology demonstrations: (a) transmission electron microscopy (TEM) of a 3D resistive RAM (RRAM) for massive storage, (b) scanning electron microscopy (SEM) of nanostructured materials for efficient heat removal (left: microscale capillary advection; right: copper nano-mesh with phase-change thermal storage), and (c) SEM of a monolithic 3D chip for high-performance and energy-efficient computation. CNTs: carbon nanotubes, FETs: field-effect transistors, and STT-MRAM: spin-transfer torque magnetic RAM. [START_REF] Aly | Energy-efficient abundant-data computing: The N3XT 1,000[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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1.4) Background and outline

This new architecture shows that computing performance can still be improved in the next decade, and the main power will rely on 3D heterogeneous integration. So the future of semiconductor industry is quite bright, and future discoveries will continue to bring progress and bring new breakthrough. This thesis is embedded in a very vast project, driven by ST Microelectronics crolles and CEA LETI in Grenoble, and in cooperation with 3IT (Interdisciplinary Institute for Technological Innovation) and University of Sherbrooke. This project has the goal to design and produce a 3D CMOS image sensor [START_REF] Coudrain | 3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies[END_REF], and the design of cooling system of this equipment is very important; the heat dissipation issues in the 3D CMOS image sensor can be crippling. Another demonstrator is on the way. This demonstrator (Figure 12) applies the nuclear magnetic resonance (NMR) / magnetic resonance imaging technology in the micro/nano scale. In recent years, NMR/MRI portable devices have drawn attention of numerous researcher teams. They are used for variety of applications, especially for medical diagnosis. The 3D schematic of the micro/nano MNR chip is shown in the Figure 12. This project is driven by numerous hospitals, here include hospitals in Lyon and New York [START_REF] Trejo Rosllo | Contribution à l'amélioration de la Sensibilité d'un Microrécepteur RMN Implantable[END_REF]. As we know, the coil receiver can be easily affected by the environmental noises; moreover, its self-noise is expressed as 4kRT; R is for instance, the resistance of the coil. So, reducing the coil self-noise means to reduce this resistance. And, in the same time, the quality factor Q of the coil, defined as Q = 𝜔𝜔𝜔𝜔 𝑅𝑅 ⁄ , will be increased. The SNR (signal noise ratio) in the coil design can be a crippling evaluator during the miniaturization of MNR/MRI. First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 19 So the purpose of the thesis is to provide a global design method for the 3D integrated circuit in electrical, thermal, electro-thermal and also noise field. Due to the high density design of 3D IC, the passive heat management method is another important work of this thesis. Hereafter will be included simulation methods for substrate and also relative connectivity (TSV, RDL, Micro strip and circuits embedded into the substrate), thermal and electro-thermal modeling method, and also keep-out of zone calculation methods.

The chapter 2 presents some background knowledge on electrical parasitic effects of TSVs. Based on the parasitic effects, we programmed and generated in Matlab a substrate impedance extractor and a 3D TLE (3D transmission line extractor), which can automatically extract the impedance from any contacts with arbitrary shape and arbitrary material. The extractors are 100% compatible with SPICE core simulator, like ADS (Advanced design system) and can be used in the S parameters extraction and transient study in ADS. The extracted data is verified with measurement results and finite element method (FEM) simulation results. Based on the parasitic effects of TSV, a 26 GHz frequency and 2 GHz bandwidth RF filter is proposed in this work.

The chapter 3 presents the thermal and electro-thermal modeling method. So the chapter 3 implements an analytical solution for multi-layers substrate nonstationary temperature distribution. In the 3D circuits, the thermal issues are crippling issues in the 3D IC design, especially when we scale down to nanoscale. The electrical resistance increase with temperature, likewise the substrate resistance. Most of thermal simulation works are based on the steady regimes; few people work on the non-stationary case. Non-stationary effects are crippling, like hot spots, which can be enhanced by voltage ramps. We propose also a multi-layers 3D IC's 3D heat dissipation calculation method. This method is suitable for any 3D IC. A 4 core CPU heat dissipation case is studied in this chapter. The later part of this chapter presents how the electro-thermal simulation works. The electrothermal simulator can be 100% compatible with SPICE (-like) simulator, and the electrical part is verified with ADS. This work constructs the framework of 3D IC electro-thermal analysis.

The chapter 4 presents the passive thermal dissipation method. As a solution to the local heat dissipation, the passive heat dissipation component, flat heat pipe (FHP) is proposed as a prospective component in the chapter 4. This chapter presents the FEM simulation approach of the FHP, and also the analytical modeling. The two results have good match, and an extensive study of the working performance's limiting condition has also been presented in this thesis.

The chapter 5 presents the noise issues of 3D IC. We firstly propose the analytical solution for the substrates noise distribution and present noise analysis methods. And this chapter investigates also the keep-out-of-zone (KOZ) of TSV to transistor. The investigation methods of electrical noise impact and thermal-mechanical noise impact are shown in this part.

Finally, the chapter 6 summarizes the contributions of these dissertation works, drawing conclusions of the manuscript.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 20 First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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Chapter 2: Electrical modeling of TSV

Integrating multiple functional layer in a single device is a major trend in the electronics field. Therefore, requiring a higher integration degree of equipment becomes more important today. 3D-IC technology based on vertical through silicon via (TSV), has been proposed as a prospective solution to the current 3D interconnection problem. Reduction of parasitic effects, higher interconnection density, faster inter-chip communication speed and less energy consumption are the main advantages of TSV interconnection [START_REF] Knickerbocker | 3D silicon integration[END_REF]. In this way, the 3D-TSV technology is considered to be the main design object of 3D highly integrated technology. In the next few years, TSV structure can flourish in the field of chips. In addition, more chips will be integrated in the 3D-IC to meet the requirements for higher bandwidth, more I / O interfaces and smaller sizes. The multi-layer TSV will be the only technology to realize this structure [START_REF] Cadix | Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits[END_REF]. Therefore, there is an urgent need for multi-layer TSV electrical characteristics and coupling problems in some researches.

For 3D stacked DRAM modules, some signals can be exchanged with other different chip signals (assuming the same layout of the chip), including the read control, address bus, data bus, write control, power supply [START_REF] Zhu | Development and characterization of a through-multilayer TSV integrated SRAM module[END_REF]. Some structures have been completed by experimental tests [START_REF] Kim | A 1.2V 12.8GB/s 2Gb mobile wide-I/O DRAM with 4x128 I/Os using TSV-based stacking[END_REF]. Although the manufacturing process gets more attention, it should also emphasize more simulation analysis. Many research work has been completed, mainly focused on the study of different electrical characteristics of TSV and calculation of TSV electrical parasitic parameters formula [START_REF] Yoon | Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer[END_REF]- [START_REF] Xu | Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture[END_REF]. However, the pre-layout study of electromagnetic modeling and analysis of TSV in multilayer substrates is critical before it enters production. The crosstalk becomes a key problem in reducing the TSV performance due to the fact that the silicon substrate with conductive properties, has parasitic capacitance effects on the insulating oxide (SiO2, isolation material surrounded by the TSV) and the isolation layer formed by the TSV metallization, especially in the TSV array. Many studies have focused on TSV crosstalk problems.

2.1) Single TSV analytical approach 2.1.1) Cylindrical TSV parasitic parameters

Cylindrical TSV is the most common TSV structure, as shown below. We can use copper, tungsten, polycrystalline silicon and so on, as the filling material, which depends on the adequate resistivity we need. Due to the simple structure, it's the easiest one to be simulated, so the research to this model has outdistanced the other TSV structures. And the thermal-mechanical and highfrequency characteristics are the main two emerging problems of TSV [START_REF] Khan | Through-Silicon Via(TSV)-induced Noise Characterization and Noise Mitigation using Coaxial TSV[END_REF], [START_REF] Rousseau | Through-silicon via based 3D IC technology : Electrostatic simulations for design methodology[END_REF]. And in following part, we will precisely introduce cylindrical TSV. In low frequency, cylindrical TSV resistance can be calculated by using the traditional wire resistance equation. When the current pass through the wire, the wire's resistance is inverse proportional to the cross-sectional area (A), and proportional to the wire's length, the resistance can be expressed by the following equation [START_REF] Jhong | Scalable Modeling and Measurement of TSV Applied for Efficiency Improvement of a RF PA[END_REF], [START_REF] Interconnects | 2.5D interposer, 3DIC and TSV Interconnects[END_REF], [START_REF] Coudrain | 3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies[END_REF], [START_REF] Pak | Electrical Characterization of Trough Silicon Via ( TSV ) depending on Structural and Material Parameters based on 3D Full Wave Simulation[END_REF]- [START_REF] Yu | Electrical Characte rization of RF TSV for 3D Multi-Core a nd Heterogeneous ICs[END_REF] 𝑅𝑅 = 𝜌𝜌𝜌𝜌 𝐴𝐴 And 𝜌𝜌 is the resistivity of the wire, 𝑙𝑙 is the wire's length, 𝐴𝐴 is the wire's cross section area. In the integrated circuit, we use normally the copper and aluminum as the interconnection material. In 3D IC design, interconnection delay has been the major influence factor of the circuit performance, so we usually use the copper (resistivity 1.68 × 10 -8 Ω • 𝑚𝑚) instead of the aluminum (resistivity 2.83 × 10 -8 Ω • 𝑚𝑚) to reduce the interconnection delay of via. For TSV radius 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 , cross sectional area π𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 2 's cylindrical TSV, it's resistance can be expressed as [START_REF] An | Electrical Modeling and Analysis of 3D Synaptic Array using Vertical RRAM Structure[END_REF] 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐷𝐷𝐷𝐷 =

𝜌𝜌𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 π𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 2 (2-2)
With the augmentation of the signal's frequency, the skin effects should be taken into consideration, that's to say, with the increase of the signal frequency in the metal, the current that passes through the via will tend to the conductor's surface. The skin effect will increase the effective resistance of the conductor and the skin effect will be more obvious as the frequency gets higher. And here we should introduce skin depth δ. It means that when the current density in the conductor gets down to the 1 e (e: Euler's number) times of the conductor's surface current density, the expression equation is [START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF] δ = � 𝜌𝜌 𝜋𝜋𝜋𝜋𝜇𝜇 0 𝜇𝜇 𝑚𝑚 (2)(3) Here, 𝑓𝑓 is signal's frequency of the wire, 𝜇𝜇 0 is the free space permeability (the value is 4π × 10 -7 H/𝑚𝑚), 𝜇𝜇 𝑚𝑚 is the metal's permeability. And through this equation, we can deduce the corner frequency if the skin effect, [START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits (2-4) So when the frequency 𝑓𝑓 is smaller than the 𝑓𝑓 𝛿𝛿 , the skin depth 𝛿𝛿 will be bigger than the TSV radius 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 of metal part, and at this case, the skin effect is negligible. So the resistance of TSV can be defined as a DC resistance, which can be expressed as shown in the R TSV_DC = ρl TSV πr TSV 2 (2-2); when the frequency 𝑓𝑓 is bigger than the 𝑓𝑓 𝛿𝛿 , the skin depth 𝛿𝛿 will be smaller than the TSV radius 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 , and at this case, the AC resistance introduced by the skin effect can be shown as following [START_REF] Hall | High speed digital system design: a handbook of interconnect theory and design practices[END_REF] 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐴𝐴𝐷𝐷 =

𝜌𝜌𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋[𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 2 -(𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 -𝛿𝛿) 2 ]
(2-5)

As we can see here, the TSV parasitic resistance is composed of a DC resistance and a AC resistance, and can be expressed as following [START_REF] Hall | High speed digital system design: a handbook of interconnect theory and design practices[END_REF]

𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 = � 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐷𝐷𝐷𝐷 2 + 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐴𝐴𝐷𝐷 2 (2-6)
For a TSV with 60𝜇𝜇𝑚𝑚 diameter and 100𝑛𝑛𝑚𝑚 oxide layer thickness, the corner frequency can be 4.7 MHz, and for a TSV with 5𝜇𝜇𝑚𝑚 diameter and 100𝑛𝑛𝑚𝑚 oxide layer thickness, the corner frequency can be 681 MHz. So here means, if we don't want to see the skin effect, either use a conductive material with a higher conductivity or reduce the via's diameter.

2.1.1.2) Cylindrical TSV Capacitance:

The capacitance of TSV is defined as the capacitance between the metal conductor and silicon substrate, because the TSV insulation layer's thickness is usually less than 1µm, so this parasitic capacitance has a great influence to the transmission, in the study of 3D IC signal integrity and power dissipation, TSV's capacitance need more accurate simulation and analysis. Because of the insulation layer (𝑇𝑇𝑆𝑆𝑆𝑆 2 ), which is used to insulate the TSV signal and the outside silicon substrate, the TSV structure forms a metal-oxide-semiconductor structure, which is MOS structure. We can get the analytical solution by solving the 1D poison equation in the cylindrical coordinate system. The TSV equivalent capacitance is composed of two parts, they are respectively oxide capacitance 𝐷𝐷 𝑜𝑜𝑜𝑜 and capacitance of depletion 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 .

𝐷𝐷 𝑜𝑜𝑜𝑜 is expressed as [START_REF] Xu Ca | Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3D-ICs[END_REF]

𝐷𝐷 𝑜𝑜𝑜𝑜 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) (2-7)
Here, 𝑡𝑡 𝑜𝑜𝑜𝑜 is the thickness of the oxide layer, 𝜀𝜀 𝑜𝑜𝑜𝑜 is the dielectric constant of 𝑇𝑇𝑆𝑆𝑆𝑆 2 (the value is 3.9), 𝜀𝜀 0 is the free space absolute dielectric constant (the value is 8.854 × 10 -12 F/𝑚𝑚)

The depletion capacitance is noted as 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 which is shown as [START_REF] Xu Ca | Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3D-ICs[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 24

𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 ) (2-8)
And the depletion width 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 can be calculated by the following relationship. [START_REF] Savidis | Closed-form expressions of 3-D via resistance, inductance, and capacitance[END_REF] 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 = � 4𝜀𝜀 0 𝜀𝜀 𝑠𝑠𝑆𝑆 𝑇𝑇 𝑡𝑡ℎ ln (

𝑁𝑁 𝐴𝐴 𝑛𝑛 𝑆𝑆 ) 𝑞𝑞𝑁𝑁 𝐴𝐴 (2-9)
Here, 𝑁𝑁 𝐴𝐴 is the doping density, 𝑛𝑛 𝑖𝑖 is the intrinsic silicon carrier concentration (the value is 1.5 × 10 16 𝑚𝑚 -3 ), 𝑇𝑇 𝑡𝑡ℎ is the thermal voltage, which can be expressed by the following equation [START_REF] Savidis | Closed-form expressions of 3-D via resistance, inductance, and capacitance[END_REF] 𝑇𝑇 𝑡𝑡ℎ = 𝑘𝑘𝑇𝑇 𝑞𝑞

(2-10)

When T=300K, 𝑇𝑇 𝑡𝑡ℎ 's value is 25.9mV, the 𝑘𝑘 is the Boltzmann constant (the value is 1.38 × 10 -23 𝐽𝐽/𝐾𝐾), 𝑞𝑞 is the unit electron charge constant (the value is 1.6 × 10 -19 𝐷𝐷).

When the metal voltage and silicon substrate voltage are different, there will be MOS effect. In the analysis of the MOS effect, we should define the bias voltage, threshold voltage and flat band voltage. When the TSV is working, the voltage applied in the metal is called bias voltage of TSV (𝑇𝑇 𝐵𝐵 ); the threshold voltage (𝑇𝑇 𝑇𝑇𝑇𝑇 ) is the voltage applied in the metal when the voltage in the 𝑇𝑇𝑆𝑆/𝑇𝑇𝑆𝑆𝑆𝑆 2 interface equals to 2ln (𝑁𝑁 𝐴𝐴 /𝑛𝑛 𝑖𝑖 ); And the flat band voltage (𝑇𝑇 𝐹𝐹𝐵𝐵 ) is the voltage applied in the metal when the 𝑇𝑇𝑆𝑆/𝑇𝑇𝑆𝑆𝑆𝑆 2 turns to the flat band state, and the 𝑇𝑇 𝐹𝐹𝐵𝐵 can be expressed in the following expression [START_REF] Savidis | Closed-form expressions of 3-D via resistance, inductance, and capacitance[END_REF]

𝑇𝑇 𝐹𝐹𝐹𝐹 = Φ 𝑚𝑚 -Φ 𝑠𝑠𝑆𝑆 - 𝑟𝑟 𝑜𝑜𝑜𝑜 𝑞𝑞Q 𝑓𝑓 𝜀𝜀 𝑜𝑜𝑜𝑜 𝜀𝜀 0 ln ( 𝑑𝑑 𝑜𝑜𝑜𝑜 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) (2-11)
Here, Φ 𝑚𝑚 is the work function of TSV's metal conductor, Φ 𝑠𝑠𝑖𝑖 is the work function of the outside silicon substrate, Q 𝜋𝜋 is the surface charge of the 𝑇𝑇𝑆𝑆/𝑇𝑇𝑆𝑆𝑆𝑆 2 interface.

If the silicon substrate is P type substrate, when the metal's voltage is different from the silicon substrate, a lot of cavities will leave 𝑇𝑇𝑆𝑆/𝑇𝑇𝑆𝑆𝑆𝑆 2 interface, and then the carrier depletion appears. The following Figure 14 is the MOS structure, 𝑟𝑟 𝑑𝑑𝑑𝑑𝑑𝑑 is the depletion radius, 𝑟𝑟 𝑜𝑜𝑜𝑜 is the oxide radius, 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 is the metal's radius. When 𝑇𝑇 𝐵𝐵 < 𝑇𝑇 𝐹𝐹𝐵𝐵 , there will be depletion layer, and at this case, 𝑟𝑟 𝑑𝑑𝑑𝑑𝑑𝑑 equals to the 𝑟𝑟 𝑜𝑜𝑜𝑜 . And this area is named accumulation region, and the equivalent capacitance is 𝐷𝐷 𝑜𝑜𝑜𝑜 .The expression is the same like (2)(3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF].

𝐷𝐷 𝑜𝑜𝑜𝑜 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) (2-12)
When 𝑇𝑇 𝐹𝐹𝐵𝐵 ≤ 𝑇𝑇 𝐵𝐵 < 𝑇𝑇 𝑇𝑇ℎ , the depletion layer appears, with the increase of 𝑇𝑇 𝐵𝐵 , the 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 increases, but 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 decreases (see equation (2)(3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF] and (2)(3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF]). And this area is named depletion region, and the total capacitance is defined as following [START_REF] Savidis | Closed-form expressions of 3-D via resistance, inductance, and capacitance[END_REF]

𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑠𝑠𝑆𝑆 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +2𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 ) (2-13) 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 = � 4𝜀𝜀 𝑠𝑠𝑆𝑆 𝑇𝑇 𝐹𝐹 ln ( 𝑁𝑁 𝐴𝐴 𝑛𝑛 𝑆𝑆 ) 𝑞𝑞𝑁𝑁 𝐴𝐴
(2-14)

𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 = ( 1 𝐷𝐷 𝑜𝑜𝑜𝑜 + 1 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 ) -1 = 𝐷𝐷 𝑜𝑜𝑜𝑜 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 𝐷𝐷 𝑜𝑜𝑜𝑜 +𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 (2-15)
When 𝑇𝑇 𝐵𝐵 ≥ 𝑇𝑇 𝑇𝑇ℎ , the depletion width 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 gets to its maximum, and it will not continue to increase with 𝑇𝑇 𝐵𝐵 , and this area is named inversion region, and at this moment, 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 gets to its minimum, so the same as the 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 . [START_REF] Savidis | Closed-form expressions of 3-D via resistance, inductance, and capacitance[END_REF]

𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑠𝑠𝑆𝑆 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +2𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 ) (2-16) 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 = � 4𝜀𝜀 𝑠𝑠𝑆𝑆 𝑇𝑇 𝑡𝑡ℎ ln ( 𝑁𝑁 𝐴𝐴 𝑛𝑛 𝑆𝑆 ) 𝑞𝑞𝑁𝑁 𝐴𝐴 = � 4𝜀𝜀 𝑠𝑠𝑆𝑆 𝑘𝑘𝑇𝑇ln ( 𝑁𝑁 𝐴𝐴 𝑛𝑛 𝑆𝑆 ) 𝑞𝑞 2 𝑁𝑁 𝐴𝐴 (2-17) 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇𝑚𝑚𝑆𝑆𝑛𝑛 = ( 1 𝐷𝐷 𝑜𝑜𝑜𝑜 + 1 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 ) -1 = 𝐷𝐷 𝑜𝑜𝑜𝑜 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 𝐷𝐷 𝑜𝑜𝑜𝑜 +𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 (2-18) 𝑇𝑇 𝑇𝑇ℎ = 𝑇𝑇 𝐹𝐹𝐹𝐹 + 2𝑇𝑇 𝑇𝑇 ln � 𝑁𝑁 𝑎𝑎 𝑛𝑛 𝑆𝑆 � + 𝑞𝑞𝑁𝑁 𝑎𝑎 𝜋𝜋(� 𝑑𝑑 𝑡𝑡𝑠𝑠𝑡𝑡 2 +𝑡𝑡 𝑜𝑜𝑜𝑜 +𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 � 2 -( 𝑑𝑑 𝑡𝑡𝑠𝑠𝑡𝑡 2 +𝑡𝑡 𝑜𝑜𝑜𝑜 ) 2 )𝑠𝑠𝑆𝑆𝑛𝑛𝑠𝑠 2𝜋𝜋𝜀𝜀 𝑜𝑜𝑜𝑜 ln ( 𝑑𝑑 𝑡𝑡𝑠𝑠𝑡𝑡 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +𝑙𝑙 𝑡𝑡𝑠𝑠𝑡𝑡 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 𝑑𝑑 𝑡𝑡𝑠𝑠𝑡𝑡 +𝑙𝑙 𝑡𝑡𝑠𝑠𝑡𝑡 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-19)
Based on the TSV RC parasitic parameters' extraction model, the paper [START_REF] -T. Qian | Through-slicon-via-aware interconnect prediction model for 3D integrated circuit[END_REF] gives a TSV RC parameters' extraction and Q3D simulation result in the 45nm CMOS background, as shown in the table below. The comparison shows that the average error between these parasitic parameters and Q3D simulation is about 5%, and the formulas can be used in TSV parasitic extractions.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits The TSV's inductance is composed of self-inductance and mutual-inductance, here we use some simplifications, and assume that the current back path is in the infinite, so the inductance of TSV is, (𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 is the TSV's metal diameter), this formulae comes from publication [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF] by taking taper angle to 0.

𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝜔𝜔 𝑆𝑆𝑛𝑛𝑛𝑛𝑑𝑑𝑟𝑟 + 𝜔𝜔 𝑑𝑑𝑜𝑜𝑡𝑡 = 𝜇𝜇 0 𝜇𝜇 𝑚𝑚 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 8𝜋𝜋 + 𝜇𝜇 0 𝜇𝜇 𝑚𝑚 2𝜋𝜋 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 [ln � 2𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 + � 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 2 +4𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 � + (𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 - � 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 2 + 4𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 )] (2-20)
Normally the inner inductance is far smaller than the exterior inductance, so the inductance of TSV can be expressed as [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF] Due to the longer and longer interconnection delay, it will decide the limit between system clock frequency and interconnection transmission. In order to reduce the interconnection RC delay, paper [START_REF] -T. Qian | Through-slicon-via-aware interconnect prediction model for 3D integrated circuit[END_REF] propose a buffer inserted design. Figure 15 shows the interconnection model after inserting buffer, in the Figure 15, r and c are respectively the interconnection resistance and capacitance per unit length. The equivalent buffer resistance can be expressed as 𝑅𝑅 𝑑𝑑 /𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 , and equivalent capacitance can be expressed as 𝐷𝐷 0 * 𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 , 𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 and 𝜔𝜔 𝑜𝑜𝑑𝑑𝑡𝑡 are the buffer's best size and distance, 𝑅𝑅 𝑑𝑑 and 𝐷𝐷 0 are respectively the buffer's output resistance and input capacitance. And the longest interconnection delay 𝐷𝐷 𝑟𝑟𝑑𝑑𝑑𝑑 can be expressed as following [START_REF] Banerjee | Analysis of on-chip inductance effects for distributed RLC interconnects[END_REF]

𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝜇𝜇 0 𝜇𝜇 𝑚𝑚 2𝜋𝜋 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 [ln � 2𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 +�𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 2 +4𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 2 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 � + (𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 -�𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 2 + 4𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 )] (2-21)
𝐷𝐷 𝑟𝑟𝑑𝑑𝑑𝑑 = 2.37𝜔𝜔 𝑙𝑙𝑜𝑜𝑛𝑛𝑙𝑙𝑑𝑑𝑠𝑠𝑡𝑡 �𝑅𝑅 𝑑𝑑 𝐷𝐷 0 𝑟𝑟𝑐𝑐 (2-22)
And 𝜔𝜔 𝜌𝜌𝑜𝑜𝑙𝑙𝑙𝑙𝑑𝑑𝑠𝑠𝑡𝑡 is the overall longest interconnection line, and it can be expressed by the Davis random distribution model. [START_REF] Banerjee | Analysis of on-chip inductance effects for distributed RLC interconnects[END_REF] 𝜔𝜔 𝑙𝑙𝑜𝑜𝑛𝑛𝑙𝑙𝑑𝑑𝑠𝑠𝑡𝑡 = 2

𝐷𝐷 3𝐷𝐷 = 𝐷𝐷 𝑟𝑟𝑑𝑑𝑑𝑑 + 𝑁𝑁 𝑇𝑇𝑇𝑇𝑇𝑇 * 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 (2-24)
And here 𝑁𝑁 𝑇𝑇𝑇𝑇𝑇𝑇 is the chip's TSV numbers along the interconnection line. And the buffer's TSV intrinsic delay is [START_REF] Banerjee | Analysis of on-chip inductance effects for distributed RLC interconnects[END_REF]

𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝑅𝑅 𝑑𝑑 𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 ⋅ 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 2 + ( 𝑅𝑅 𝑑𝑑 𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 + 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 ) × ( 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 2 + 𝑠𝑠 𝑜𝑜𝑑𝑑𝑡𝑡 𝐷𝐷 0 )
(2-25)

2.1.1.5) Power dissipation during interconnection

In the 3D system, the power dissipation is composed with the following parts. [START_REF] Qian | Three-dimensional global interconnect based on a design window[END_REF], [START_REF] Sekar | IntSim: A CAD tool for optimization of multilevel interconnect networks[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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𝑃𝑃 𝑡𝑡𝑜𝑜𝑡𝑡𝑎𝑎𝑙𝑙 = 𝑃𝑃 𝑆𝑆𝑛𝑛𝑡𝑡 + 𝑃𝑃 𝑙𝑙𝑜𝑜𝑙𝑙𝑆𝑆𝑐𝑐 + 𝑃𝑃 𝑟𝑟𝑑𝑑𝑑𝑑 + 𝑃𝑃 𝑇𝑇𝑇𝑇𝑇𝑇 (2-26)
Here 𝑃𝑃 𝑖𝑖𝑙𝑙𝑡𝑡 is the interconnection line dissipation, 𝑃𝑃 𝜌𝜌𝑜𝑜𝑙𝑙𝑖𝑖𝑙𝑙 is the logic gate dissipation, 𝑃𝑃 𝑟𝑟𝑑𝑑𝑑𝑑 is the inserted buffer dissipation, 𝑃𝑃 𝑇𝑇𝑇𝑇𝑇𝑇 is the TSV dissipation.

𝑃𝑃 𝑆𝑆𝑛𝑛𝑡𝑡 = 𝑠𝑠 2 𝐷𝐷 𝑆𝑆𝑛𝑛𝑡𝑡 𝜔𝜔 𝑡𝑡𝑜𝑜𝑡𝑡 𝑇𝑇 𝑑𝑑𝑑𝑑 2 𝑓𝑓 (2-27)
Here, 𝑇𝑇 𝑑𝑑𝑑𝑑 is the supply voltage, 𝑠𝑠 is the average gate active factor, 𝑓𝑓 is the working frequency, 𝐷𝐷 𝑖𝑖𝑙𝑙𝑡𝑡 is the interconnection capacitance per unit length, 𝜔𝜔 𝑡𝑡𝑜𝑜𝑡𝑡 is the total length of interconnection line, it's supposed to follow the random distribution model. [START_REF] Qian | Three-dimensional global interconnect based on a design window[END_REF], [START_REF] Sekar | IntSim: A CAD tool for optimization of multilevel interconnect networks[END_REF]

𝜔𝜔 𝑡𝑡𝑜𝑜𝑡𝑡 = ∫ 𝑙𝑙 • 𝑆𝑆(𝑙𝑙)𝑑𝑑𝑙𝑙 2�𝑁𝑁 𝑡𝑡 1 (2-28)
𝑆𝑆(𝑙𝑙) is the interconnection density function.

Logic gate and inserted buffer have the same dissipation model, they can be expressed as [START_REF] Qian | Three-dimensional global interconnect based on a design window[END_REF], [START_REF] Sekar | IntSim: A CAD tool for optimization of multilevel interconnect networks[END_REF]

𝑃𝑃 𝑙𝑙𝑜𝑜𝑙𝑙𝑆𝑆𝑐𝑐 = 𝑁𝑁 𝑡𝑡 𝑠𝑠 2 𝐷𝐷 𝑙𝑙𝑜𝑜𝑙𝑙𝑆𝑆𝑐𝑐 𝑇𝑇 𝑑𝑑𝑑𝑑 2 𝑓𝑓 (2-29) 𝑃𝑃 𝑟𝑟𝑑𝑑𝑑𝑑 = 𝑛𝑛 𝑟𝑟𝑑𝑑𝑑𝑑 𝑠𝑠 2 𝐷𝐷 𝑟𝑟𝑑𝑑𝑑𝑑 𝑇𝑇 𝑑𝑑𝑑𝑑 2 𝑓𝑓 (2-30)
𝐷𝐷 𝜌𝜌𝑜𝑜𝑙𝑙𝑖𝑖𝑙𝑙 and 𝐷𝐷 𝑟𝑟𝑑𝑑𝑑𝑑 are respectively the gate and buffer's equivalent capacitance, 𝑛𝑛 𝑟𝑟𝑑𝑑𝑑𝑑 is the inserted buffer's number and 𝑁𝑁 𝑡𝑡 is the chip's total logic gate number.

And the TSV's RC model depends on the via's number. [START_REF] Qian | Three-dimensional global interconnect based on a design window[END_REF], [START_REF] Sekar | IntSim: A CAD tool for optimization of multilevel interconnect networks[END_REF]

𝑃𝑃 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝑁𝑁 𝑇𝑇𝑇𝑇𝑇𝑇 𝑠𝑠 2 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 𝑇𝑇 𝑑𝑑𝑑𝑑 2 𝑓𝑓 (2-31)

2.1.2) Taper TSV parasitic parameters

Taper TSV is proposed by MIT's Lincoln's laboratory [START_REF] Yarema | Development of 3D Integrated Circuits for HEP[END_REF], its structure is shown as Figure 16. Taper TSV is an inevitable manufacturing byproduct, due to the non-ideal Dry Reactive Ion Etching [START_REF] Lu | Detailed electrical and reliability study of tapered TSVs[END_REF]. Paper[92] proposed a precisely controlled taper TSV fabrication process. But in compare with the cylindrical TSV, taper TSV has a higher parasitic resistance. And if it has a very high inclination, it's easy to generate a 'V' form TSV (which will be an error). [START_REF] Banerjee | Analysis of on-chip inductance effects for distributed RLC interconnects[END_REF]- [START_REF] Todri | A Study of 3-D Power Delivery Networks With Multiple Clock Domains[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Taper TSV resistance is also composed with a DC part and AC part [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF].

𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐷𝐷𝐷𝐷 = 𝜌𝜌𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋𝑎𝑎(𝑎𝑎+𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝛽𝛽) [1 + 1 2 𝛽𝛽 2 ] (2-32) δ = � 𝜌𝜌 𝜋𝜋𝜋𝜋𝜇𝜇 0 𝜇𝜇 𝑚𝑚 (2-33) 𝑓𝑓 𝛿𝛿 = 𝜌𝜌 𝜋𝜋𝜇𝜇 0 𝜇𝜇 𝑚𝑚 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 2 (2-34) 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐴𝐴𝐷𝐷 = 𝜌𝜌(2+𝛽𝛽 2 ) 4𝜋𝜋𝛽𝛽δ log (1 + 2𝛽𝛽𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2𝑎𝑎-δ ) (2-35)
𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 = � 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐷𝐷𝐷𝐷 2 + 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇_𝐴𝐴𝐷𝐷 2 (2-36)
Where 𝛽𝛽 = (𝑏𝑏 -𝑎𝑎)/𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 , 𝑏𝑏 and a are respectively top surface and bottom surface radius. When 𝛽𝛽 = 0, the model will change to cylindrical TSV model.

2.1.2.2) Taper TSV Capacitance:

When we change from cylindrical TSV to taper TSV 𝐷𝐷𝑜𝑜𝑜𝑜 will change to [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF]

𝐷𝐷 𝑜𝑜𝑜𝑜 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 sinαln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜+𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-37)
When 𝑠𝑠 = 90°, taper TSV will turn to a cylindrical TSV, and the formula will change back to the cylindrical TSV formulas

The depletion capacitance 𝐷𝐷𝑑𝑑𝑑𝑑𝑑𝑑 will change to [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 sinαln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +2𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-38)
And the depletion width 𝑊𝑊𝑑𝑑𝑑𝑑𝑑𝑑 can be calculated by poisson's equation, but it's too complicated.

𝑇𝑇 𝐹𝐹𝐵𝐵 is the flat band voltage, which is the voltage applied at the via when the system stay in the flat band state. It can be expressed as [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF]

𝑇𝑇 𝐹𝐹𝐹𝐹 = Φ 𝑚𝑚 -Φ 𝑇𝑇𝑆𝑆 = Φ 𝑚𝑚 -Χ - 𝐸𝐸 𝑙𝑙 2𝑞𝑞 -V 𝑇𝑇 log ( 𝑁𝑁 𝑎𝑎 𝑛𝑛𝑆𝑆 ) (2-39)
Where Φ𝑚𝑚 is the metal's work function, for copper, Φ𝑚𝑚 = 4.65𝑇𝑇, Φ 𝑇𝑇𝑖𝑖 is the silicon substrate work function, Χ = 4.05V is the electronic affinity for silicon substrate, the intrinsic carrier concentration 𝑛𝑛𝑆𝑆 = 1.18𝑑𝑑10 𝑐𝑐𝑚𝑚 -3 , band gap 𝐸𝐸 𝑙𝑙 = 1.12𝑑𝑑𝑇𝑇, the unit charge 𝑞𝑞 = 1.6022𝑑𝑑 -19 𝐷𝐷, in the room temperature, the thermal voltage 𝑇𝑇 𝑇𝑇 = 𝑘𝑘𝑇𝑇 𝑞𝑞 = 0.026𝑇𝑇, 𝑁𝑁 𝑎𝑎 = 1.25𝑑𝑑15𝑐𝑐𝑚𝑚 -3 is the ionized acceptor concentration, 𝑄𝑄 𝑓𝑓 = 5𝑑𝑑14 * 𝑞𝑞 C/𝑚𝑚 2 is the Si/SiO2 surface charge density.

And for the 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 , we have the following relationship. [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF]

𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇 = V 𝐹𝐹𝐹𝐹 + Ψ(𝑅𝑅 𝑜𝑜𝑜𝑜 ) + 𝑈𝑈 𝑜𝑜𝑜𝑜 (2-40) 𝑈𝑈 𝑜𝑜𝑜𝑜 = 𝑄𝑄 𝑚𝑚 𝐷𝐷 𝑜𝑜𝑜𝑜 = 𝑞𝑞𝑁𝑁 𝑎𝑎 𝜋𝜋(𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑 2 -𝑅𝑅 𝑜𝑜𝑜𝑜 2 )𝑠𝑠𝑆𝑆𝑛𝑛𝑠𝑠 2𝜋𝜋𝜀𝜀 𝑜𝑜𝑜𝑜 log ( 2𝑅𝑅 𝑜𝑜𝑜𝑜 +𝑙𝑙𝑡𝑡𝑠𝑠𝑡𝑡𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 2𝑅𝑅 𝑚𝑚 +𝑙𝑙𝑡𝑡𝑠𝑠𝑡𝑡𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-41) Ψ(𝑅𝑅 𝑜𝑜𝑜𝑜 ) = 𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑜𝑜𝑜𝑜 2 4𝜀𝜀 𝑠𝑠𝑠𝑠 - 𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑 2 2𝜀𝜀 𝑠𝑠𝑠𝑠 log(𝑅𝑅 𝑜𝑜𝑜𝑜 ) + 𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑 2 4𝜀𝜀 𝑠𝑠𝑠𝑠 �2 log�𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑 � -1� (2-42)
And we can get the 𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 by the following relationship

𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑜𝑜𝑜𝑜 2 4𝜀𝜀 𝑠𝑠𝑆𝑆 - 𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 2 2𝜀𝜀 𝑠𝑠𝑆𝑆 log(𝑅𝑅 𝑜𝑜𝑜𝑜 ) + 𝑞𝑞𝑁𝑁 𝑎𝑎 𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 2 4𝜀𝜀 𝑠𝑠𝑆𝑆 �2 log�𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 � -1� = 2𝑇𝑇 𝑇𝑇 log ( 𝑁𝑁 𝑎𝑎 𝑛𝑛𝑆𝑆 ) (2-43)
And the threshold for the minimum capacitance region is

𝑇𝑇 𝑡𝑡ℎ = 𝑇𝑇 𝐹𝐹𝐹𝐹 + 2𝑇𝑇 𝑇𝑇 log � 𝑁𝑁 𝑎𝑎 𝑛𝑛𝑆𝑆 � + 𝑞𝑞𝑁𝑁 𝑎𝑎 𝜋𝜋(𝑅𝑅 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 2 -𝑅𝑅 𝑜𝑜𝑜𝑜 2 )𝑠𝑠𝑆𝑆𝑛𝑛𝑠𝑠 2𝜋𝜋𝜀𝜀 𝑜𝑜𝑜𝑜 log ( 2𝑅𝑅 𝑜𝑜𝑜𝑜 +𝑙𝑙𝑡𝑡𝑠𝑠𝑡𝑡𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 2𝑅𝑅 𝑚𝑚 +𝑙𝑙𝑡𝑡𝑠𝑠𝑡𝑡𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-44)
When 𝑇𝑇 𝐹𝐹 < 𝑇𝑇 𝐹𝐹𝐹𝐹 accumulation region, there will not be depletion layer, and at this case, 𝑟𝑟 𝑑𝑑𝑑𝑑𝑑𝑑 equals to the 𝑟𝑟 𝑜𝑜𝑜𝑜 . And this area is named accumulation region, and the equivalent capacitance is 𝐷𝐷 𝑜𝑜𝑜𝑜 .The expression is the same like .

𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝐷𝐷 𝑜𝑜𝑜𝑜 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 sinαln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜+𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 𝑐𝑐𝑜𝑜𝑡𝑡𝑠𝑠 ) (2-45)
When 𝑇𝑇 𝐹𝐹𝐹𝐹 ≤ 𝑇𝑇 𝐹𝐹 < 𝑇𝑇 𝑇𝑇ℎ depletion region, the depletion layer appears, with the increase of 𝑇𝑇 𝐹𝐹 , the 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 increases, but 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 decreases (see equation (2)(3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF] and (2)(3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF]). And this area is named depletion region, and the total capacitance is defined as following First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits

𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 = ( 1 𝐷𝐷 𝑜𝑜𝑜𝑜 + 1 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 ) -1 = 𝐷𝐷 𝑜𝑜𝑜𝑜 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 𝐷𝐷 𝑜𝑜𝑜𝑜 +𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 (2-47)
When 𝑇𝑇 𝐹𝐹 ≥ 𝑇𝑇 𝑇𝑇ℎ minimum capacitance region, the depletion width 𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑 gets to its maximum, and it will not continue to increase with 𝑇𝑇 𝐹𝐹 , and this area is named inversion region, and at this moment, 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 gets to its minimum, so the same as the 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇 .

𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 0 𝜀𝜀 𝑠𝑠𝑆𝑆 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 sinαln ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 +2𝑊𝑊 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑎𝑎𝑜𝑜 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 +2𝑡𝑡 𝑜𝑜𝑜𝑜 ) (2-48) 𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇𝑚𝑚𝑆𝑆𝑛𝑛 = ( 1 𝐷𝐷 𝑜𝑜𝑜𝑜 + 1 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 ) -1 = 𝐷𝐷 𝑜𝑜𝑜𝑜 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 𝐷𝐷 𝑜𝑜𝑜𝑜 +𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑𝑚𝑚𝑆𝑆𝑛𝑛 (2-49)
As we can see, the taper TSV model has some similarities with cylindrical TSV, so it can be simplified.

𝐷𝐷 𝑜𝑜𝑜𝑜_𝐷𝐷 = sinα𝐷𝐷 𝑜𝑜𝑜𝑜_𝑇𝑇 (2-50) 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑_𝐷𝐷 = sinα𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑_𝑇𝑇 (2-51)
So, the cylindrical and taper TSV's parasite capacitance have the following relationship

𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇_𝐷𝐷 = sinα𝐷𝐷 𝑇𝑇𝑇𝑇𝑇𝑇_𝑇𝑇 (2-52)
So if we use error to present the relative error, when 1 -sinα < 𝑑𝑑𝑟𝑟𝑟𝑟𝑜𝑜𝑟𝑟, that's when α > 𝑎𝑎𝑟𝑟𝑐𝑐𝑠𝑠𝑆𝑆𝑛𝑛 (1 -𝑑𝑑𝑟𝑟𝑟𝑟𝑜𝑜𝑟𝑟), the Taper TSV can use the cylindrical TSV's model. If error = 5%, we can get the limit inclination is 73 degree. So that means if the inclination of the taper TSV is less than 15 degree, we can use the cylindrical TSV model.

2.1.2.3) Taper TSV Inductance

When the taper TSV's inclination is less than 15 degree, the parasitic inductance can be expressed as, [START_REF] Liang | Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[END_REF]

𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝜇𝜇 0 𝜇𝜇 𝑚𝑚 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 8𝜋𝜋 + 𝜇𝜇 0 𝜇𝜇 𝑚𝑚 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2𝜋𝜋 [ln � 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 + � 𝑎𝑎 2 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 𝑎𝑎 � + �2𝑎𝑎 -2 � 𝑎𝑎 2 + 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 � + 4𝛽𝛽𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 (𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 -(𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 +𝑎𝑎)( � 𝑎𝑎 2 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 -𝑎𝑎)) ( � 𝑎𝑎 2 +𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 2 -𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 )(4𝑎𝑎+𝛽𝛽𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 ) ] (2-53)

2.1.3) Single Tapper TSV analytical result

In order to verify the taper TSV model, we use a standard TSV geometry, TSV metal radius 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 = 2.5𝜇𝜇𝑚𝑚, height 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 = 10𝜇𝜇𝑚𝑚, oxide layer thickness 𝑡𝑡 𝑜𝑜𝑜𝑜 = 0.1𝜇𝜇𝑚𝑚. And here we study the different inclination angle's influences by considering tapper TSV skin effect. As we can see from the Figure 17, from 1MHz to 10MHz, this region is constant, this is the DC region. Beyond 1GHz, First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 32 the total resistance increases monotonically with frequency. The region between 10MHz and 1GHz is quite complicated. For the taper TSV, due to the different top radius and bottom radius, we can always find out 2 skin frequency (equation 2-33), they match well with the two pics in the figure 17. The left pic match always with the skin frequency of the bigger radius, and right pic match with the skin frequency of smaller radius. When the inclination angle gets close to 90 degree, the two pics approach, when it equals to 90 degree, the two pics turn to one big pic. This comes back to the skin frequency of cylindrical TSV case. But the equations and are not valid outside of the skin effect boundary conditions. We found a more accurate model:

𝑓𝑓𝑜𝑜𝑟𝑟 δ > b and b > a, 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐷𝐷𝐷𝐷 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋𝜋𝜋𝜋𝜋 (2-54) 𝑓𝑓𝑜𝑜𝑟𝑟 δ < a and b > a, 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐴𝐴𝐷𝐷 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 2𝜋𝜋(𝜋𝜋-𝜋𝜋)δ log ( 2b-δ 2a-δ ) (2-55) 𝑓𝑓𝑜𝑜𝑟𝑟 𝑎𝑎 < δ < b and b > a, 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐷𝐷𝐷𝐷𝐴𝐴𝐷𝐷 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 (δ-a) 𝜋𝜋𝜋𝜋δ(𝜋𝜋-𝜋𝜋) + 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 2𝜋𝜋(b-a)δ log ( 2b-δ δ ) (2-56)
For the straight wire:

r = √𝑎𝑎𝑏𝑏 [107] 𝑓𝑓𝑜𝑜𝑟𝑟 δ > r, 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐷𝐷𝐷𝐷 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋𝑟𝑟 2
(2-57)

𝑓𝑓𝑜𝑜𝑟𝑟 δ < r, 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐴𝐴𝐷𝐷 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋(2𝑟𝑟-δ)δ (2-58)
And the broadband model for cylindrical wires:

𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 𝐵𝐵𝐵𝐵 = 𝜌𝜌𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋δ(2𝑟𝑟-δ(1-𝑑𝑑 -𝑟𝑟/δ ))(1-𝑑𝑑 -𝑟𝑟/δ ) (2-59)
We see some different results from Figure 17 that's because that the bigger inclination angle will cause smaller capacitance contact surface.

When the bias voltage is bigger than the flat band voltage, the depletion capacitance has a great influence to the TSV's final parasitic capacitance, especially when it arrives at the C region. If we neglect the influence of depletion region, it will cause big calculation error.

Figure 19 Taper TSV Error without MOS effect Figure 19 gives the error when we don't take into account the MOS effect, with the increase of the bias voltage, the error increases. In the C region, all the 4 cases reach an error of more than 200%, so the depletion region's capacitance is non-negligible. Figure 20 shows that the inclination angle's influence to the TSV inductance, for a TSV of 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 = 2.5𝜇𝜇𝑚𝑚 𝑎𝑎𝑛𝑛𝑑𝑑 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 = 10𝜇𝜇𝑚𝑚 , is almost null.

2.2) Substrate modeling and verification by using coplanar wave model

2.2.1) CPW parasitic extraction

We used a CAD-based space mapping method to describe the fabricated CPW (coplanar wave model) lines. So, the dielectric constants of silicon are characterized in literature and hence were set as their standard value as 11.7. A simulation was done by using the value to compare with measurement. CPW lines were set on an epitaxial layer and silicon substrate, the oxide isolation was then designed underneath.

Figure 21 CPW model geometry BEOL coplanar waveguides are copper made, with a thickness of 0.8μm, and ground planes width is equal to 80μm. Depending on the test structure, the signal line width is either 90μm with a slot of 15μm (CPW_W1) or 60μm with a slot of 30μm (CPW_W2). There are 3 different lines variation lengths: 60μm, 240μm and 540μm. The coplanar waveguides are realized in a highly conductive silicon substrate (rho=9mΩ.cm for low resistive, rho=62Ω.cm for high resistive, εr=11.7) with a thickness of 120μm. A thin epitaxial layer (thickness: 4.5μm, resistivity: 10Ω.cm, permittivity: 11.7) is deposited on the substrate. Lines are isolated from the substrate by an oxide layer (thickness: 0.9μm, permittivity: 5.2). [START_REF] Lorival | An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration[END_REF] Coplanar lines resistance, self and mutual inductances are calculated from experimental formulas. Resistance is calculated for a DC value, without taking into account the skin effect. And inductances (self and mutual) are calculated depending on the inductance analytical expressions [START_REF] Rosa | The self and mutual-inductances of linear conductors[END_REF].

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits (2-61)

𝑀𝑀 = 𝜇𝜇 0 𝜇𝜇 𝑟𝑟 𝐿𝐿 2𝜋𝜋 [ln � 2𝐿𝐿 𝑑𝑑 � -1 + 𝑑𝑑 𝐿𝐿 ] (2-62)
where ρ is the metal resistivity (copper: 1.72e-8 Ω.m), μ0 and μr the vacuum and the copper permeabilities, W, L, T and p respectively the line width, length, thickness and the pitch between two lines.

The interline/coupling capacitance Cinter between lines is calculated according to the equations defined by Nurmi in [START_REF] Osborn | All-Copper Chip-To-Substrate Interconnects for High Performance Integrated Circuit Devices[END_REF] from the concerned lines surfaces and the fringe capacitances Cf and Cf' taken at the boundaries and the middle of the coupled-lines. Cp is the coupling capacitance between the ground plane and the concerned line surface, which is also treated in the literature as the line's self-capacitance [ (2-66)

Where εox and ε0 are the silicon oxide and the vacuum permittivity and S the lines gap. An average value of the width W is considered because signal and ground lines are geometrically different in width. Yue MA 2018 37

In the case of the CPW, when the substrate is highly conductive, like in our test structures, Eddy currents can be neglected in low and medium frequency. The substrate can then be modelled as a very low resistance or a simple node. Vertical current in the epitaxial layer for each coplanar line is modelled by a resistance (Repi) in parallel with a capacitance (Cepi). The capacitances of the oxide layer (Cox) isolating the lines from the substrate are also included in the environment modelling. (2-67)

𝐷𝐷 𝑑𝑑𝑑𝑑𝑖𝑖 = 𝜀𝜀 0 𝜀𝜀 𝑑𝑑𝑑𝑑𝑠𝑠 •𝐿𝐿•𝑊𝑊 𝑇𝑇 𝑑𝑑𝑑𝑑𝑠𝑠 (2-68) 𝐷𝐷 𝑜𝑜𝑜𝑜 = 𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 •𝐿𝐿•𝑊𝑊 𝑇𝑇 𝑜𝑜𝑜𝑜 (2-69)
The coplanar waveguide model is shown in Figure 24 with all the lines connected in the substrate through a node SUB. Depending on the system physical and material data, the induction between the two ground lines can be neglected or not.

The assumption of modelling the conductive substrate as a simple node is only viable for low and medium frequencies. Substrate coupling effects require to be added in the system electrical modelling by describing the substrate as a {RLCG} network to evaluate precisely the IC's losses in high frequency.

From this perspective, an extraction demo is proposed relying on the Transmission Line Method for multi-layered substrate extraction. Basically, a current is applied on one contact pad which can be placed at the substrate surface or placed anywhere in the substrate. A voltage is then collected at another contact placed atop or within the substrate too, permitting to deduce a transfer impedance matrix [ZT] which relies on the number of contacts. Substrate coupling effect between two contacts is generally modelled by a resistance in parallel with a capacitance. To extract the values of the overall resistances and capacitances constituting the substrate network from the elements of ZT, the matrix is inverted to obtain a conductance matrix GT and nodal analysis using Kirchhoff's Current Law (KCL) is applied. The method can be used for both high resistive or high First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 38 conductive substrates being uniform (same resistivity and permittivity in all the considered volume) or not, explaining why a multi-layered approach has been considered. Moreover, values of the substrate electrical network can be given in DC or evolving in function of the frequency. The detailed method can be found in [START_REF] Valorge | Analytical and Numerical Model Confrontation for Transfer Impedance Extraction in Three-Dimensional Radio Frequency Circuits[END_REF] in which it was validated for two contacts. Currently, the method is expanded on TSVs.

The method was applied in the example case of coplanar waveguides at the top of a high resistive substrate without epitaxial layer. Coplanar lines can hence be assimilated to three contacts. Material and technological data considered for the lines and oxide layers are the ones of the CPW test structure. Substrate height and permittivity are also kept and resistivity is fixed to 60Ω.cm. The following figure illustrates the corresponding substrate network. Values of the resistances and the capacitances are derived from the transfer conductance matrix such that: with g12 = (R12 // C12), g13 = (R13 // C13), g23 = (R23// C23)

𝐺𝐺 𝑇𝑇 = �

2.2.2) Experimental de-embedding process for CPW

The first step is to extract the contribution of coplanar access to the measurement of the total test structure by using a vector network analyzer, as shown in Figure 26. A new method has been performed to rigorously extract access line effects. This method is presented with details in a recent publication [START_REF] Nguyen | Through Silicon Via Interconnections for High Reliability Applications[END_REF].

Figure 26 Measurements with a Vector Network Analyzer (VNA) for a frequency sweep [START_REF] Fengyuan | Analyse et Caractérisation des Couplages Substrat et de la Connectique dans les Circuits 3D: vers des Modèles Compacts[END_REF] Using this method we make first a measurement of a "Thru" test structure. This structure connects directly right and left coplanar access lines. Measurements of the ABCD matrix of this "Thru" structure give the ABCD matrix of the coplanar access line, named ABCDtest fixture. Next, we de-embedded the contribution of two test fixtures on the measurement of the total test structure using formula . ABCDDUT and ABCDcoplanar are respectively the ABCD matrix of the "total test structure" and the part "CPW" (2-72)

�
The propagation constant of the line and its characteristic impedance are derived from ABCDcoplanar matrix according to the following equation (ANNEX 1).

𝐴𝐴𝐹𝐹𝐷𝐷𝐷𝐷 𝑙𝑙𝑜𝑜𝑑𝑑𝜌𝜌𝜋𝜋𝑙𝑙𝜋𝜋𝑟𝑟 = � cosh (𝛾𝛾 0 ∆𝜔𝜔) 𝑍𝑍 𝑙𝑙0 sinh (𝛾𝛾 0 ∆𝜔𝜔) sinh(𝛾𝛾 0 ∆𝜔𝜔) /𝑍𝑍 𝑙𝑙0 cosh (𝛾𝛾 0 ∆𝜔𝜔) � (2-73)
Once the ABCD-parameters of de-embedded CPW are known, its propagation characteristics can also be determined through the formulas in ANNEX 1.

Real part of the characteristic impedance and imaginary part of the propagation constant are presented in Figure 27 as an example. As we can see from figure 26, the measured data have a quite stable transmission characteristics between 5GHz and 20GHz. Because of the test bench's limit in (very) high frequency, the measured data is correct below 20GHz.

2.2.3) ADS Parameter extraction and model fitting on experimental data

The EDA software ADS can replace the value of one component (resistance or capacitance) by a variable. So we can predefine one variable arbitrarily by <Var> block, as shown in Figure 29. We can define the constraint of the variable, for example, we can restrict the variable in the interval We replace the substrate and the epitaxial layer by a RC model. The complete circuit can be simulated in ADS as following. Here we define all the variables and give them an initial value in the block <Var>. The original parameters, optimized parameters and 3D-TLE extracted parameters The extracted layers parameters: The result can be seen like following As we can see, if we change only the substrate conductivity, it will not match with the measurement. So we can see that the substrate conductivity has a great influence to the high frequency transmission. The higher is the substrate conductivity, the more obvious gets the signal attenuation.

Resistive substrate

2.2.5) High resistive substrate study

2.2.6) Transient study -Eye diagram

The eye diagram can be used to evaluate the extracted interconnection transmission's quality (3D-TLM). In order to simplify the simulation, we input a numeral signal and measure the output signal. And the output signal is more or less deformed according to the interconnection, which can be seen through a bigger or smaller eye diagram.[92]- [START_REF] Todri | A Study of 3-D Power Delivery Networks With Multiple Clock Domains[END_REF] We can get the eye diagram by using ADS's <Eye Probe> and <Simulation-Transient> study. We put a bit sequential voltage source at the input by accompanying a 50 ohm resistance at its output. We attach the under test numeral component in the circuit and add a 100 fF capacitance at the output. We can get the three different setting.

2.3) TSV models' parasitic extraction 2.3.1) Characterization and parameter extraction of two TSV model

Here, we present our own analytical expressions for the medium-density TSV compact model resistance and oxide capacitance. The expressions of TSV are deduced from the formula of a perfect cylindrical conductor, it depends on the conductor length, the thickness and radius. [START_REF] Lorival | An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration[END_REF]

𝑀𝑀 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝜇𝜇 0 𝜇𝜇 𝑟𝑟 𝑇𝑇 2𝜋𝜋 [𝑠𝑠𝑆𝑆𝑛𝑛ℎ -1 � 𝑇𝑇 𝑑𝑑 � + 𝑑𝑑 𝑇𝑇 -�( 𝑑𝑑 𝑇𝑇 ) 2 + 1] (2-79)
Where: Rmt and Tmt are the copper layer radius and thickness of the TSV top surface;

Rot and Tot the oxide layer radius and thickness of the TSV top surface;

Rmd and Tmd the copper layer radius and thickness of the TSV bottom surface;

Rod and Tod the oxide layer radius and thickness of the TSV bottom surface.

p is the pitch between two nearby TSVs and Ra the TSV average radius TSV filing material does not significantly affect its RF behavior. Besides, the influences of the copper layer thickness and the TSV radius are very low. So, the self-and mutual-inductances can still use the analytical expressions of a filled cylindrical conductor.

Since the substrate is highly conductive for the studied CPWs model, it can be modelled as a simple node. For each CPW line, the vertical current transmission path in the thin epitaxial layer has been treated as a parallelepiped shape and so it can be modelled by a resistance (Repi) in parallel with a capacitance (Cepi). The isolating lines from the epitaxial layer can be modelled by an oxide layer capacitances (Cox). [START_REF] Lorival | An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits (2-82)

The electrical parameter values must be adjusted based on the distributed elementary cell length, width and height. For the TSV chain, the currents passes vertically by the epitaxial and the oxide layers and reach finally the BEOL level ground planes. The epitaxial and oxide layers electrical parameters (Repi(TSV), Cepi(TSV) and Cox(GND)) can be calculated by using the same expression as the coplanar waveguide. The substrate and TSVs couplings are considered with the geometrical capacitance Cox(TSV). The coupling effects of TSVs are considered. The TSV chain electrical model of the BEOL ground lines is divided into serial blocks on the overall surface. These surface parts have a length of the TSVs contact pads length Lpad. The epitaxial layer parameters (Repi(TSV), Cepi(TSV)) and the oxide capacitance (Cox(GND)) which model the current propagation to the ground line through the TSV, should then be calculated with L = Lpad. The width and the thickness are the same as the other line parts. The surface cells of ground lines included in the current paths can be simply modelled by a RL networks; otherwise they are modelled as shown in the following figures. As an illustration, the above figures show how the two top BEOL ground lines are changed into serial blocks for a 2xTSV U-chain. The interline current paths should also be considered, they have mainly two kinds, MI and MII. The total wire length, Lground, is equal to 2Lpad, plus the BRDL line length, Lspace. Lspace represents to the gap between two contact pads. The BRDL line connecting the two TSVs, the substrate coupling of which can be expressed by an oxide capacitance between the SUB node and BRDL, which is located in the contact pads gap (MII).

The 2xTSV has a form of "U". So for nxTSVs chains, there will be n/2 "U-shaped" structures connected at the BEOL surface by contact pads and 60μm access BEOL lines.

The following figure shows the structure of a 4xTSV chain; the coupling effects between the four TSVs are also represented. The BEOL ground line total length then equals: [START_REF] Lorival | An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration[END_REF]

𝜔𝜔 𝐵𝐵𝐵𝐵𝐵𝐵𝐿𝐿 = 𝑛𝑛𝜔𝜔 𝑑𝑑𝜋𝜋𝑑𝑑𝑠𝑠 + 𝑙𝑙 2 𝜔𝜔 𝑠𝑠𝑑𝑑𝜋𝜋𝑙𝑙𝑑𝑑 + ( 𝑙𝑙 2 -1)𝜔𝜔 𝜋𝜋𝑙𝑙𝑙𝑙𝑑𝑑𝑠𝑠𝑠𝑠 (2-83)
It illustrates the ground lines total transmission line length (related to the transmission loss) for nxTSV chain.

2.3.2) Simulation and optimization of 2 TSVs U-model

We use the same simulation process. Firstly, we try to simulate the S parameters by using the netlist generated by the 3D-TLE extractor. And we compare it with the de-embedded experimental result (by using the test bench Figure 26). Through the pub [START_REF] Kim | Highfrequency scalable modeling and analysis of a differential signal through-silicon via[END_REF], the substrate parasitic parameters can be expressed by a parallel of capacitance and conductance. And their expressions are shown as follow

𝐷𝐷 𝑇𝑇𝑆𝑆_𝑠𝑠𝑠𝑠𝑏𝑏 = 𝜋𝜋×𝜀𝜀 0 𝜀𝜀 𝑟𝑟,𝑠𝑠𝑆𝑆 𝑐𝑐𝑜𝑜𝑠𝑠ℎ -1 ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) × ℎ 𝑇𝑇𝑇𝑇𝑇𝑇 [𝐹𝐹]
(2-84)

𝐺𝐺 𝑇𝑇𝑆𝑆_𝑠𝑠𝑠𝑠𝑏𝑏 = 𝜋𝜋×𝜎𝜎 𝑠𝑠𝑆𝑆 𝑐𝑐𝑜𝑜𝑠𝑠ℎ -1 ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) × ℎ 𝑇𝑇𝑇𝑇𝑇𝑇 [𝑇𝑇] (2-85)
And here, when we extract the measurements, we must apply the de-embedding method, the following two figures show the difference between with and without de-embedding.

Measurements S21 result without deembedding(blue line)

Measurements S21 result with deembedding(blue line) As we can see from the two figures, the result with de-embedding is more close to our simulated circuits. As shown in (a), (b), when Cox3=2e-12F, the curve is much closer to measurements. And it corresponds to epsr_ox=3.28 (we use 5.8 originally at the 3D-TLE), and when Cox2=7e-13F, the curve is much closer to measurements. And it corresponds to a epsr_ox=10.98 (we use 5.8 originally at the 3D-TLE, Cox2=3.7e-13 originally), it has a very big influence to the final S parameter approximation. Repi2 has a big influence to the result. When Repi2=38ohms, the result is close to the measurements. And the 3D-TLE value is 50.5 ohms with a resistivity of 9.09e-2 ohm*m, now, with a Repi2=38ohms, the resistivity changes to 6.84e-2 ohm*m. The MOS depletion effect doesn't have a big influence to the S21 parameters, but at very high frequency, it has a slightly influence. Here the Cdep vary from 0.5e-13 F to 8e-12 F.

As we can see, after 10GHz, the substrate has a big influence to the S21 parameter. The best fit Rsub value is about 100 ohms, at this resistance, the substrate has a resistivity of about 0. So in all, the final influence factors are the substrate resistivity, oxide layer's permittivity, tsv isolation permittivity, and epitaxial layer resistivity.

So after the optimization of the only 4 parameters, we can get the final S21 parameter As we can see, the TSV oxide permittivity has changed from 5.8 to 6.5, that's close, so there may be some measurement's error, So is the resistivity of epitaxial layer. The oxide layer permittivity has doubled to 11.6, and the substrate is no more non resistive, its resistivity changes to 0.2154.

In order to verify our 3D-TLE extractor, a finite-element simulation (COMSOL Multiphysics) is realized. The simulation results are shown as following. They have a really good fit between 3D-TLE extractor, COMSOL simulation and measurement. Since the TSV electrical model has been verified in low and medium frequency, timing analyses are studied by using Eye Diagrams to check the signal integrity in the case of a 3x3 medium-density TSVs matrix [START_REF] Motoyoshi | 3D-LSI technology for image sensor[END_REF], [START_REF] Kang | 8 Gb 3-D DDR3 DRAM using through-silicon-via technology[END_REF], [START_REF] Arabi | 3D VLSI: A scalable integration beyond 2D[END_REF], [START_REF] Morot | 3D Interconnect Optimization for Single Channel 100-GBps Transmission in a Photonic Interposer[END_REF], [START_REF] Buitrago | Functionalized 3D 7×20-array of vertically stacked SiNW FET for streptavidin sensing[END_REF]. We have modeled it using TSVs having the same dimensions used in their W1 configuration. The distance between the TSVs equals to 120 μm. Figure 51 shows this modelling consideration for a 2x2 TSVs matrix. The coupling effects among all the TSVs (inductive couplings) are once more evaluated in these studies. The Eye Diagrams are generated by Advanced Design System (ADS) by assuming a symmetrical test setting with 50 Ω input and output equivalent resistances Z0. The TSVs are attached with a 100fF load capacitances (Figure 52). Three configurations are studied and illustrated in Figure 53. The first configuration, all the TSVs are connected to ground except for the central TSV. The second configuration is a shielded arrangement for which only the matrix's inner TSV has data transmission; the others are grounded. For the third one, all the TSVs are signal TSVs. The generated Eye Diagrams are presented in Figure 55. When signals are transmitted in a "Source" TSV, crosstalk voltages can be observed on the neighboring "victim" TSV which is at a logic state (configuration A or B). A transmission delay can also be observed if the victim TSV is a signal TSV. The larger the distance between two TSVs, the more the coupling effects can be neglected. The interference due to the inductive coupling effects can be observed clearly in the configuration C. The rise time and propagation delay increase with the increase of the neighbouring signal TSVs number. As a consequence, the eye width is shortened. Compared with configuration A, the rise time in configuration C is 38 % longer. Besides, the voltage crosstalk changes respectively from 65 mV up to 250 mV in the configurations B and C. As the noise margins decrease with technological evolution, signal integrity in TSV matrices must be more fully quantified for cases in which signals propagate in the same direction, as in the presented analyses, or in opposite First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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directions. The compact model between the substrate and the TSVs should also be considered in the TSVs matrices' electrical models, in order to evaluate the impact of coupling effect to the signal integrity.

The previous results show that the 3D-TLE extractor can be easily integrated with a common EDA software and provide compact models for analyzing the performance of TSVs matrix for high speed data transmission.

2.4) A 26GHz TSV based 3D filter

Portable devices such as cellphones, PCs and so on, are required to be compact, high-speed, and multifunctional; moreover, they can work with a variety of communication standards such as GSM, WCDMA, LTE, GPS, WLAN, Bluetooth, and NFC. In order to solve such communication demands, advanced packaging technique, such as, system-in-package (SiP) and system-on-chip (SoC) technologies are fast developed, because they can miniaturize the communication systems. During the past few years, heterogeneous 3-D IC technique has been rapidly developed and commercialized, in order to simultaneously improve the performance and minimize the whole system size, this advanced packaging technology makes chips design not only in horizontal direction but also in vertical direction by adopting TSVs and interposers. Thanks to heterogeneous 3D IC technology, the packages are getting small and smaller.

However, traditional radio-frequency (RF) passive components, such as, filters, couplers, and antennas, are very difficult to be integrated into packages. The sizes of RF passive components are usually proportional to several square wavelengths of working frequencies. As a consequence, RF passive components must be put outside packages and designed on PCB; but, as a disadvantage, a lot of PCB areas are taken.

To solve this problem, many researchers have invented advanced RF components by using passive fabrication processes. For example, miniaturized RF filters were designed by using integrated passive device (IPD), low-temperature co-fired ceramics (LTCC), liquid crystal polymer (LCP) processes, and so on [START_REF] Vyas | Liquid Crystal Polymer (LCP): The ultimate solution for low-cost RF flexible electronics and antennas[END_REF], [START_REF] Yang | Super compact low-temperature co-fired ceramic bandpass filters using the hybrid resonator[END_REF]- [START_REF] Hoft | Design of symmetric trisection filters for compact lowtemperature Co-fired ceramic realization[END_REF]. These techniques can continue minimize the sizes of RF filters, and give better quality factors in comparison to CMOS processes. Once the RF filters can be designed small enough and put into the packages, a huge area can be saved from PCB.

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Besides, some RF filters are fabricated by using interposer technology such as silicon interposer and glass interposer [START_REF] Yook | High D ensity and Low-cost Silicon Interposer using Thin-film and Organic Lamination Processes[END_REF], [START_REF] Mori | Development of a new interposer including embedded thin film passive elements[END_REF]- [START_REF] Wu | Miniaturized UWB Bandpass Filters Yue MA 2018 236 Integrated with Notch Filters Using a Silicon-based Integrated Passive Device Technology[END_REF], these filters can be easily integrated into heterogeneous 3-D IC circuit as shown in Figure 56. For these filter designs, they can fully profit the 3-D IC technique.

In the following part, a wideband filter based on TSVs is designed. The filter design procedure, simulated results, and discussions are given in this part. Such TSV-based mini-bandpass filters demonstrate the advantages of 3D IC packaging technique.

Traditional coupled-resonator filter is a prospective option in the 3D RF filter design. The proposed filter is based on lumped elements: lumped inductors formed by TSVs' self-inductance and parallel-plate capacitors (TSVs' coupling capacitance). Thanks to the advanced silicon interposer process, the high-density TSV array can have a narrow wire pitch (200 um in our design). By properly designing the TSV in the silicon substrate, we don't need to put 2 capacitances and 2 inductances in the 2D plane and the size of filters can be largely miniaturized. In this part, a TSVbased bandpass filters are generated as examples using TSV parasitic effect. Figure 57 shows the lumped circuit topology of the proposed RF filter by using a single interposer. Here the π-type filter cell is used, the resonant frequency and bandwidth can be expressed as: [START_REF] Tseng | Compact TSV-based wideband bandpass filters on 3-D IC[END_REF]

𝑓𝑓 𝑙𝑙 = 1 2𝜋𝜋�2𝐿𝐿 1 𝐶𝐶 1 (2-86) Bandwidth = 1 2𝜋𝜋𝑅𝑅 𝑟𝑟𝑑𝑑𝑓𝑓 𝐶𝐶 1 = 4𝜋𝜋𝐿𝐿 1 𝜋𝜋 0 2 𝑅𝑅 𝑟𝑟𝑑𝑑𝑓𝑓 (2-87)
The first step, we define the filter specifications, the coupled capacitances C1/2 can be easily determined. But, in order to achieve wideband bandwidth (>20%), large-value capacitances of input/output are needed but that's not practical. To tackle this problem, we use a directly input/output setting as shown in Figure 57.

Once lumped values are chosen, the next step is to transform them to physical layouts. The layout of the proposed RF filter is shown in Figure 58. Inductors of resonators L1 are the intrinsic inductance of TSV, which can be changed for meeting the design demands by adjusting the TSV's radius. And, the shunt-to-ground capacitor (Cbump) is generated by the parallel-cylindrical capacitance, which can be seen from Figure 58. By utilizing the 3D IC technology, we don't need to design the filter in 2D plane and the filter shows very good potential in circuit miniaturization and performance improvement. In all, the proposed TSV based filter can be easily embedded into the interposers, which can be linked to First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 65 other components in the 3-D IC packaging technique. So in the future, new RF passive components on 3-D IC, such as compact couplers and antennas, would be an interesting and valuable topic.

2.5) Conclusion

This chapter gives the cylindrical TSV, tapering TSV's electrical analytical model, qualitatively analyzes the taper TSV's parasitic parameters model by considering MOS capacitance effect, eddy current and substrate parasitic effect. Based on MATLAB GUI and according to the parasitic model, a 3D-TLE extractor is generated, which is designed for 3D ICs; the output of this extractor is saved in a SPICE netlist, which is compatible with every SPICE core simulator (ADS). The 3D-TLE extractor is verified by the common Micro-stripe model and 2 TSVs chain model of 3D ICs. For the CPW with substrate model, the 3D-TLE extractor fits well with the measured data, which need a de-embedding process. Reducing the substrate conductivity (reducing the doping concentration), can largely increase the substrate's resistivity, thus highly reduce the attenuation of S12 parameter in high frequency, and improve the transmission performance. For the 2xTSVs chain model, after the comparison with measurements, FEM (COMSOL Multiphysics [START_REF] Multiphysics | COMSOL multiphysics[END_REF]) verification, we find a good fit beyond 10 GHz. By using this model, we analyze the influence of TSV's parasitic parameters and generate the characteristic curves of five key factors: TSV oxide layer capacitance, depletion capacitance of MOS effect, substrate parasitic resistance, epitaxial layer's resistance, insolation layer's capacitance, and get the five key factor's influence to the high frequency transmission performance. But this study doesn't take backside passivation layer's positive charges into consideration [START_REF] Stucchi | Anomalous C-V Inversion in TSVs: The Problem and Its Cure[END_REF]. We also study the transmission performance of TSV matrix in difference transmission mode. Based on the TSV and substrate's parasitic effect, we propose a 26 GHz filter. This chapter provides an important theoretical basis for improving the reliability and flexibility of the 3D ICs. Further work will be developed, that will encompass accurate M3D (monolithic 3D) model and the co-design of transistors and M3D in nanoscale. The electro-thermal and thermo-mechanical modeling will be the key problem in the future M3D design. And the M3D analytical model should also be integrated in our simulator 3D-TLE. In order to get close to the future neuromorphic chip design, a CMOS based or new analogical/mixed signal M3D transistor should be designed.

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Chapter 3: Electro-thermal modeling of 3D circuits

3.1) Introduction

In the past years, a lot of electro-thermal (ET) co-analysis methods have been proposed for IC design. In order to solve the temperature distribution, the heat equation is solved in 2D and 3D. Then, the electrical resistivity of the circuit will change with temperature, and the electrical solution is updated. Such process will be the starting point for updating the heat sources for the thermal issues. The iteration stops when the convergence reaches the fixed accuracy.

The current techniques are normally based on two major systems, depending on how the thermal problem is solved. The first method consists in solving the heat conduction equation, by using FEM, FVM or FDM methods, as shown in the standard multi-physics simulators. It can accurately simulate 3D geometries and/or add also other phenomena like micro-heat pipe cooling effects [START_REF] Xie | Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and joule heating effects[END_REF], with a very high computational cost. For the second one, the thermal problem is solved by using an equivalent circuit model, so both the thermal circuits can be simulated by using the electrical solver, like the SPICE-like ones (ADS). This method can largely reduce the computational cost, and handle strongly coupled high speed electro-thermal problems. Many of the ET methods have focused on the chip or PCB study using PDN analysis, but less on the device level design. [START_REF] Todri-Sanial | Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains[END_REF], [START_REF] Khan | Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies[END_REF], [START_REF] Todri-Sanial | Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains[END_REF], [START_REF] Todri | A Study of 3-D Power Delivery Networks With Multiple Clock Domains[END_REF], [START_REF] Magnani | Electrothermal analysis Yue MA 2018 233 of carbon nanotubes power delivery networks for nanoscale integrated circuits[END_REF], [START_REF] Xie | Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and joule heating effects[END_REF]- [START_REF] Zheng | Full-Chip Power Supply Noise Time-Domain Numerical Modeling and Analysis for Single and Stacked ICs[END_REF]. PDNs should be analyzed by considering different parts such as CPW, vias, C4 bumps, etc. Consequently, even though each simple models can be simplified as a single node, but the size of the total equivalent network for PDNs can easily overpass several millions nodes [START_REF] Kim | High-frequency scalable electrical model and analysis of a through silicon via (TSV)[END_REF]- [START_REF] Bazigos | Analytical Compact Model in Verilog-A for Electrostatically Actuated Ohmic Switches[END_REF]. Hence, the major challenge to ET simulations of PDNs is how to reduce the computational cost. The traditional model reduction technique are more suitable for systems with a large number of poles, however, a PDN is usually composed of a huge number of nodes, which have a low number of poles. Therefore, the model reduction for PDN is not so obvious [START_REF] Wünsche | Electro-thermal circuit simulation using simulator coupling[END_REF]. Recently, new reduction methods have been studied only for electrical networks, based on the concept of node reduction [START_REF] Magnani | A node clustering reduction scheme for power grids electrothermal analysis[END_REF][157] [START_REF] Zhong | Fast Algorithms for IR Drop Analysis in Large Power Grid[END_REF]. Once the reduction methods are suitable for the electrical and thermal study, the reduction strategies can be directly used, with a predefined accuracy, and reduce the network size [START_REF] Mori | Development of a new interposer including embedded thin film passive elements[END_REF]- [START_REF] Wu | Miniaturized UWB Bandpass Filters Yue MA 2018 236 Integrated with Notch Filters Using a Silicon-based Integrated Passive Device Technology[END_REF]. This chapter will emphatically introduce the electro-thermal modeling method for substrate, 3D circuits and multi-cores system. In order to give a brief introduction to these phenomena, some simple models are presented here. we use the solving method in TSV level simulation (Modified Nodal Analysis method). The power distribution network will be a very interesting topic in future studies, but here in the thesis, we just use the simulation method. We interest only in the low voltage study.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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3.2) Electro-thermal modeling of substrate

Substrate noise coupling in integrated circuits becomes a significant consideration in the circuit design. Nowadays, micro (nano) technology and the development of semiconductor technology enable designers to integrate multiple systems into a single chip, not only in 2-D (planar) but also in 3-D (in the bulk). This design technology reduces cost, while improving performance, and makes the possibility of a system to be on chip [START_REF] Cioccio | 3D at CEA LETI MINATEC[END_REF][163] [13][164].

3-D Si integration seems to be the right way to go and compete with Moore's law (more than Moore versus more Moore). However, it is still a long way to go. In 2010, the question was why 3-D. Today, the questions are when and how is 3-D used. The 3-D chip stacking is well known to overcome conventional 2-D IC issues, using in-depth contacts or some through silicon for signal transmission.

The kind of silicon substrate in which 3-D interconnections are processed is an important parameter and has a strong impact on 3-D interconnection electrical behavior [START_REF] Leduc | Enabling technologies for 3D chip stacking[END_REF]. Electrical modeling methods are dependent on the substrate type of the application. Two different kinds of p silicon substrates are typically used in CMOS/BiCMOS processes: uniform lightly doped substrate (>1 Ω・cm) and heavily doped substrate (<1 Ω・cm) with lightly thinned doped (>1 Ω ・cm) epitaxial layer. Other semiconductor substrates are used in micro/nanotechnologies and could embed 3-D interconnections (silicon on insulator technologies, microelectromechanical systems technologies, sensor technologies, etc.). Indeed, we attempt to propose an analysis of dynamic electro-thermal phenomenon studies in 3-D layered circuits.

First of all, we solve Poisson's equation, using Green kernels [START_REF] Utsuno | Transfer function method for measuring characteristic impedance and propagation constant of porous materials[END_REF][166] [167][168][169] [START_REF] Gontrand | 3D substrate modeling; From a first order electrical analysis, towards some possible signal fluctuations consideration, for radio frequency circuits[END_REF].

Here we show that this mathematical method is an analog to the transmission line matrix (TLM), based on reflection transmission of voltage and current through the layers, when adopting it to embedded contacts of any shape. Then, we work on the resolution of the unsteady 3-D heat equation that has been shown; during this, we use the algorithms developed for the electrical modeling, particularly when using the spreading impedance concept. Finally, we show that these electrical and thermal spreading impedances can be considered entangled. This approach drives us to start an attempt to model the more general problem of noise in 3-D ICs, using again, a transfer impedance paradigm.

3.2.1) Brief introduction of mathematical tools

In this part, Green functions are applied to homogeneous stacked layers for substrate circuit model extraction, as opposed to numerical methods; the resolution speed of the former method is much faster. Some basic recalls and concepts are first introduced. The use of discrete cosine transforms (DCTs), applying twice as fast a Fourier transform (FFT) in this model, will accelerate First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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and compute the speed. Then, an improved model, which can be applied on substrate with in-depth contacts (or via), is shown; it can treat the case of contacts lying in different layers. For verification, a finite element method is compared (FEM) [START_REF] Software | User-Driven COMSOL Software Updates Now Available in Version 5.2a[END_REF].

3.2.1.1) Green Kernels

The high density integration and high system frequency make substrate noise coupling become one of the most significant considerations in the design due to its great impact on the performance of ICs. The aim of this 3D substrate analysis is, first of all, to efficiently extract the Z impedance parameters between any contacts (electrode and via) that are located on or into the silicon substrate.

An efficient impedance extraction tool, for any two contacts, could help the designer to accelerate the design and optimize the final layout. Like in planar technologies, 3D interconnects can be built as a resistance, inductance, capacitance, and conductance (RLCG) equivalent electrical model, with a Π or a T network. Generally, a simple compact model is constructed by modeling the substrate as a simple node. However, this assumption is only viable when substrate is highly conductive, in low and medium frequency domains, and is not suitable for the multilayer substrates. That is the reason why, in this thesis, we propose a substrate extraction method relying on TLM method over multilayered substrate and/or Green functions to model these effects, in the bulk [START_REF] Ahmed | Discrete Cosine Transform[END_REF][167] [START_REF] Verghese | Rapid simulation of substrate coupling effects in mixed-mode ICs[END_REF][169].

3.2.1.2) Substrate Analysis

The most well-known pioneering paper came from ref [START_REF] Gharpurey | Transform Domain Techniques for Efficient Extraction of Substrate Parasitics 2 : Theory : The Substrate Green Function[END_REF]: a layered 3-D substrate, with two surface contacts.

We present hereafter a 3-D substrate study with top or embedded contacts. The originality as we consider and apply here is to do all the calculations in the reciprocal domain, from the very beginning of the calculations to the end, to extract voltage or temperature.

In general, the Z parameters could be defined as [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑍𝑍 𝑚𝑚𝑙𝑙 = 𝑇𝑇 𝑚𝑚 𝐼𝐼 𝑛𝑛 |𝐼𝐼 𝑘𝑘≠𝑙𝑙 (3-1)
In practical operation, by injecting a unitary current as an excitation source, I at the n th point, and a unitary current excitation source, -I (equivalent to a sink current I) at an m th point and calculating the resulting voltage at the probe point, we can get the direct impedance Zmn between the m and n contacts.

If we can get the resulting potential distribution in the substrate caused by the unitary current, we could easily get the Z parameters by .Under quasi-static conditions, the potential over the substrate satisfies Laplace's equation:

∇ 2 𝜑𝜑(𝑜𝑜, 𝑦𝑦, 𝑧𝑧) = 0 (3-2)
It can also be written as:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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� 𝜕𝜕 2 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝜕𝜕𝜕𝜕 2 + 𝜕𝜕 2 𝜕𝜕𝜕𝜕 2 � 𝜑𝜑(𝑜𝑜, 𝑦𝑦, 𝑧𝑧) = 0 (3-3)
Hereafter, for Poisson or heat diffusion equations, the analytical method is, first of all, based on the algorithm of variable separation, leading to solve an Eigen problem.

When assuming that φ=X(x, x')・Y (y, y')・Z(z, z'); can be rewritten by defining [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

Z(z, z ′ ) = Z ′ (z, z ′ ) • cos � m•π•x′ a � • cos � n•π•y ′ b � (3-4)
And we get, for a potential due to a point charge, a simple equation [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] ab

4 • � d 2 Z dz 2 -γ mn 2 • Z� = - δ(z-z ′ ) ε N with γ mn = � � 𝑚𝑚•𝜋𝜋 𝜋𝜋 � 2 + � 𝑙𝑙•𝜋𝜋 𝜋𝜋 � 2 (3-5)
For z ≠ z', δ(z-z') = 0. The above equation, has a well-known general solution:

𝑍𝑍 ′ = 𝐴𝐴 • 𝑑𝑑 -𝛾𝛾 𝑚𝑚𝑛𝑛 •(𝑑𝑑+𝜕𝜕) + 𝐹𝐹 • 𝑑𝑑 𝛾𝛾 𝑚𝑚𝑛𝑛 •(𝑑𝑑+𝜕𝜕) (3-6)
This equation also invokes a transmitted wave and a reflected one.

For instance, for the case that both the point charge and the point of observation are in the same dielectric layer, on the surface with z = z' = 0, the Green function then changes to [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

∅(x, y; x ′ , y ′ ) z=z ′ =0 (G 0 ) z=z ′ =0 = �∑ ∑ f mn C mn cos � mπx a � cos � mπx ′ a � cos � nπy b � cos � nπy ′ b � ∞ n=0 ∞ m=0 � (3-7)
Where Cmn= 0 for (m=n=0), Cmn=2 for m=0 or n=0 but m ≠ n and Cmn= 4 for all other m and n (m>0 and n>0).

The function fmn is given by: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑓𝑓 𝑚𝑚𝑙𝑙 = 1 𝜋𝜋𝜋𝜋𝛾𝛾𝜀𝜀 𝑁𝑁 𝛽𝛽 𝑁𝑁 𝑡𝑡𝜋𝜋𝑙𝑙ℎ(𝛾𝛾 𝑚𝑚𝑛𝑛 𝑑𝑑)+𝛤𝛤 𝑁𝑁 𝛽𝛽 𝑁𝑁 +𝛤𝛤 𝑁𝑁 𝑡𝑡𝜋𝜋𝑙𝑙ℎ(𝛾𝛾 𝑚𝑚𝑛𝑛 𝑑𝑑) (3-8)
βN and ΓN can be computed recursively from: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

� β k Γ k � = 1 2 • � 1 + ε k-1 ε k (1 - ε k-1 ε k )e 2θ k (1 - ε k-1 ε k )e -2θ k 1 + ε k-1 ε k � × � β k-1 Γ k-1 � (3-9)
Where

𝜃𝜃 𝑘𝑘 = 𝛾𝛾 𝑚𝑚𝑙𝑙 (𝑑𝑑 -𝑑𝑑 𝑘𝑘 ), 𝛽𝛽 0 = 1, 𝛤𝛤 0 = 1 (3-10)
Then, after the derivation of some formal mathematical solutions from Poisson's equation, with boundary conditions, we will depict hereafter a more physical (and graspable) approach of the problem, using a TLM method, with some brief recalls. Note that, in our whole algorithm, from its beginning, we work on the reciprocal space. More precisely, for instance, it means that we also take the Fourier transform of the injected currents on the discretized contacts.

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In practice, then, we can choose any shape for these embedded contacts, whereas, in all the few others works, to the best of our knowledge, all the contacts are rectangular, the integration over them being done in the real space. This last point seems to be crucial to us, and we should work with through silicon vias (TSVs) (cylindrical, tronconic, etc.) in our 3-D circuits.

After a bi-dimensional spatial Fourier transform in the x and y directions, (3-3) should be

𝜕𝜕 2 Φ 𝜕𝜕𝜕𝜕 2 -𝑘𝑘 𝑜𝑜 2 Φ -𝑘𝑘 𝜕𝜕 2 Φ = 0 (3-11)
Where Φ is the spatial-frequency domain potential and kx, ky are the spatial-frequency variables (m -1 ).

Since the current density

* Z Z J E σ = (σ* is the complex conductivity) and Z E z ϕ ∂ = - ∂
, we can write

𝐽𝐽 𝜕𝜕 = -𝜎𝜎 * 𝜕𝜕𝜕𝜕 𝜕𝜕𝜕𝜕 (3-12)
In the spatial frequency domain, it changes to [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] 𝐽𝐽

𝜕𝜕 (𝑘𝑘 𝑜𝑜 , 𝑘𝑘 𝜕𝜕 , 𝑧𝑧) = -(𝜎𝜎 + 𝑗𝑗𝜔𝜔𝜀𝜀) 𝜕𝜕𝜕𝜕(𝑘𝑘 𝑜𝑜 ,𝑘𝑘 𝑦𝑦 ,𝜕𝜕) 𝜕𝜕𝜕𝜕 (3-13)
After derivative calculations of the above equation, we obtain [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

� 𝜕𝜕𝜕𝜕 𝜕𝜕𝜕𝜕 = - 𝐽𝐽 𝑧𝑧 (𝜋𝜋+𝑗𝑗𝑗𝑗𝜀𝜀) 𝜕𝜕𝐽𝐽 𝑧𝑧 𝜕𝜕𝜕𝜕 = -(𝜎𝜎 + 𝑗𝑗𝜔𝜔𝜀𝜀)(𝑘𝑘 𝑜𝑜 2 + 𝑘𝑘 𝜕𝜕 2 )Φ (3-14)
These equations indicate the relationship between current density in the z-direction and the potential distribution in the spatial frequency domain.

3.2.1.3) Transmission Line Analogy for Multilayered Media

In its simplest form, a transmission line is a pair of conductors linking together two electrical systems (source and load, for instance), with forward and return paths; for cases where the return path is floating, a third conductor (or more) is introduced as the grounding shield. For microwaves, they are waveguides. In our case, the propagation of EM waves and their interferences, through the silicon substrate, is among the most serious obstacles in the steady trend toward integration of the present day microelectronics. In fact, the TLM method has been established in some cases concerning substrate surfaces; TLM can be seen as a more physical interpretation of the mathematical developments presented above.

The principal strength of this method seems to be well dedicated to embedded contacts, irrespective of their number and shape.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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Let us consider a plane wave through a multilayered medium, its plane of incidence being parallel to the <x, y> plane, providing the same boundary conditions as mentioned above.

Then, we consider the general case in which the line's impedance is not the same as that of the load. A wave-front A hits the load ZL: a part of energy is absorbed by ZL, and the remaining energy is reflected; in this case, voltage and current wave-fronts are not in phase. This reflected wave can meet another incident wave-front B.

The direction of the current flow depends on the polarity of the waveform at the time of observation; if two positive directed waveforms (one forward and one reflected) meet, the current waveforms subtract, but the voltage waveforms add. Likewise, if a positive directed waveform meets a negative directed waveform, the current will add and the voltage will subtract.

The expression for the apparent impedance is given as follows: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑍𝑍 = 𝑇𝑇 𝑚𝑚𝑜𝑜𝑚𝑚𝑎𝑎𝑡𝑡 𝑖𝑖 𝑚𝑚 𝑜𝑜𝑚𝑚𝑎𝑎𝑡𝑡 = 𝑇𝑇 𝐹𝐹 ±𝑇𝑇 𝑅𝑅 𝑖𝑖 𝐹𝐹 ∓𝑖𝑖 𝑅𝑅 (3-15)
Then, the general solution for voltage and current is [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑇𝑇(𝑧𝑧) = 𝑇𝑇 𝜋𝜋 𝑑𝑑 𝛾𝛾𝜕𝜕 + 𝑇𝑇 𝑟𝑟 𝑑𝑑 -𝛾𝛾𝜕𝜕 (3-16) 𝐼𝐼(𝑧𝑧) = 𝑌𝑌 𝑙𝑙 (𝑇𝑇 𝐹𝐹 𝑑𝑑 -𝛾𝛾𝜕𝜕 -𝑇𝑇 𝑟𝑟 𝑑𝑑 𝛾𝛾𝜕𝜕 ) (3-16)
Where the propagation coefficient γ is the square root of the product Z by Y, the linear impedance and admittance, respectively, γ = α + jβ; α: attenuation, β = 360°/𝜆𝜆 𝑠𝑠𝑖𝑖 Directly deriving from the chain matrix [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

� 𝑇𝑇 1 𝐼𝐼 1 � = � 𝑐𝑐𝑜𝑜𝑠𝑠ℎ 𝛾𝛾𝜔𝜔 𝑍𝑍 𝑙𝑙 𝑠𝑠𝑆𝑆𝑛𝑛ℎ 𝛾𝛾𝜔𝜔 𝑌𝑌 𝑙𝑙 𝑠𝑠𝑆𝑆𝑛𝑛ℎ 𝛾𝛾𝜔𝜔 𝑐𝑐𝑜𝑜𝑠𝑠ℎ 𝛾𝛾𝜔𝜔 � � 𝑇𝑇 2 -𝐼𝐼 2 � (3-17)
And from the output branch V2 = -ZLI2, we get:

� 𝑇𝑇 1 𝐼𝐼 1 � = -𝐼𝐼 2 � 𝑍𝑍 𝐿𝐿 𝑐𝑐𝑜𝑜𝑠𝑠ℎ 𝛾𝛾𝜔𝜔 𝑍𝑍 𝑙𝑙 𝑠𝑠𝑆𝑆𝑛𝑛ℎ 𝛾𝛾𝜔𝜔 𝑍𝑍 𝐿𝐿 𝑌𝑌 𝑙𝑙 𝑠𝑠𝑆𝑆𝑛𝑛ℎ 𝛾𝛾𝜔𝜔 𝑐𝑐𝑜𝑜𝑠𝑠ℎ 𝛾𝛾𝜔𝜔 � � 1 1 � (3-17)
Where Zc = 1/Yc (square root of Z and Y ratio) is the characteristic impedance (electric and magnetic fields' modulus ratio), ZL is the charge impedance, and L is the distance from the load. We can extract an input impedance, Zl (=V1/I1), function of the load impedance Zl+1 (l: layer number), as [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] 𝑍𝑍 𝜌𝜌 = 𝑍𝑍 𝑙𝑙 𝑍𝑍 𝑡𝑡+1 +𝑍𝑍 𝑐𝑐 𝑡𝑡𝜋𝜋𝑙𝑙ℎ 𝛾𝛾𝐿𝐿 𝑍𝑍 𝑐𝑐 +𝑍𝑍 𝑡𝑡+1 𝑡𝑡𝜋𝜋𝑙𝑙ℎ 𝛾𝛾𝐿𝐿 (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF][START_REF] Limansyah | 3D image sensor SiP with TSV silicon interposer[END_REF][START_REF] Motoyoshi | 3D-LSI technology for image sensor[END_REF] This well-known (TLM) equation Zl is directly related to (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF], where Zc = βN and ZL = ΓN [START_REF] Utsuno | Transfer function method for measuring characteristic impedance and propagation constant of porous materials[END_REF].

In fact, restarting from (3-7) and taking into account the limit or boundary conditionscontinuity of potential and discontinuity of the electric field if there is a surface charge at the considered layer interface-it is easy to program this iterative solution against substrate depth, or the layers of (3-7). In fact, these calculations are made only one time, at each frequency. In our simulator, using MATLAB [START_REF]Matlab[END_REF], we use a matric formalism, extending the impedance (Z) and the current (T) transmission from a layer l to its adjacent one [see (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF] or (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF][START_REF] Limansyah | 3D image sensor SiP with TSV silicon interposer[END_REF]], starting from a k layer

� 𝑍𝑍 𝑘𝑘,𝜌𝜌+1 𝑇𝑇 𝑘𝑘,𝜌𝜌+1 � = � 𝐴𝐴 𝑘𝑘 -𝐹𝐹 𝑘𝑘 𝐷𝐷 𝑘𝑘 -𝐷𝐷 𝑘𝑘 � � 𝑍𝑍 𝑘𝑘,𝜌𝜌 𝑇𝑇 𝑘𝑘,,𝜌𝜌 � (3-19)
Where T addresses the derivation of the current (between two parallel regions).

Based on the transmission line method, a substrate extractor is programmed, shown in the following Figure 61. The ABCD parameters are variously known as chain, cascade, or transmission line parameters. This cascade connection model is very suitable.

As mentioned earlier, all the calculations are done in the reciprocal space. For instance, the potential is derived from the (Kronecker) product of (sub) matrix Z, by a DCT of the matrix of the injected current, accomplished using two consecutive FFTs. In our algorithm, the contact voltage is the mean value of the voltage of the discrete contact elements, calculated via Millman's theorem, as [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

v = ∑ 𝑗𝑗𝑗𝑗𝑙𝑙𝜕𝜕 𝑛𝑛 𝑁𝑁 𝑛𝑛=1 ∑ 𝑗𝑗𝑗𝑗𝑙𝑙 𝑁𝑁 𝑛𝑛=1 = 1 𝑁𝑁 ∑ 𝜑𝜑 𝑙𝑙 𝑁𝑁 𝑙𝑙=1 (3-20)
Where n ϕ the substrate voltage at a node and N is the number of contact sub-areas. Therefore, in our modified algorithm, the contact voltage is then calculated by taking the average <Va> of the potentials of the substrate region, under the injecting contact.

3.2.2) Simulation Results by using Green/TLM

In this work, as a check, a typical process flow compatible Bi-CMOS 0.35µm technology is first considered. In Figure 60(a), a specific region (p+/p) of this process is presented. [170][80] We approximate the actual profile by stacked layers of given thicknesses uniformly doped as shown in Figure 60(b).

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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First of all, we did some numerical experiences (not presented here) using COMSOL [START_REF] Software | User-Driven COMSOL Software Updates Now Available in Version 5.2a[END_REF], a well-known Multiphysics (electrical, thermal, and mechanical couplings) simulator, for testing its robustness and accuracy. It is also a dedicated tool for full-wave electromagnetic analysis. It essentially uses Galerkin-like algorithms; typically, a 3-D simulation can use a few ten of minutes or more than 1h. Figure 62 shows the general algorithm of substrate impedance extraction. Figure 63 shows the extracted voltage and impedance.

3.2.2.1) Contacts Embedded

Considering the general case where the contacts (previous works exist for surface contacts [START_REF] Gharpurey | Transform Domain Techniques for Efficient Extraction of Substrate Parasitics 2 : Theory : The Substrate Green Function[END_REF]), real or virtual, are totally embedded in Figure 60. Then, the substrate can be seen as an First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 75 actual parallel connection of two separated parts (current derivation). The current is injected on a contact of an i th layer, so the substrate is divided in two parts, from this layer.

We write a synoptic model algorithm, all developed in the reciprocal spaces in Figure 62. Now, it seems to be easy to calculate any transfer impedance by TLM. Possibly embedded in the substrate, contacts can be introduced into any layer; they can be real (e.g., metal like) or virtual, of any shape.

The surface die is typically 30 µm Χ 30 µm, with M = N = 300; surface contact: 20 by 20 points (the calculation points, M Χ N, are equidistributed). From the above results, one can find that the comparison between TLM/Green and COMSOL is quite good. The proposal method's calculated results agree well with the COMSOL simulation ones, while our method uses comparatively less time (roughly 1/50-1/100).

Regarding the top surface potential distribution of the two-contact model in Figure 64, one can find that the potential on the contact surface is not uniform (high-voltage region). The non-uniform potential is caused by an injection of uniform current density instead of a uniform voltage. This non-uniform potential feature makes 3D-TLE very profitable when one calculates the impedance of two resistive regions rather than two metal contacts, for example, the oxide-insulated conductive regions (e.g., pads and coplanar waveguide) and junction insulated well regions (e.g., n-well regions over a p-type substrate). In these cases, the substrate plates could not be considered as an equipotential plate.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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The simulation results obtained with Green/TLM implemented in MATLAB and compared with COMSOL are found to be practically equal. Indeed, we choose, in MATLAB, layers as perfect parallelepipeds (uniform thickness layers).

We are quite aware that the quasi-electrostatic modeling framework cannot work so perfectly up to 10 THz (versus experiments), which implies a wavelength of roughly tens of micrometers in Si. This wavelength is of the ten orders small compared to the contact-to-contact distance (3μm) used; in this work we use quasi-static assumption, not the full wave Maxwell equations.

Figure 60 shows the frequency to 10 THz, because we want to find out how to simulate parasitic effects at very high frequency, the typical RC model still works for substrate in our case with validation of FEM results, but which are no longer valid in a physical point of view; we should use a full wave method for the very high frequency (>10GHz). But it's still a way to compare FEM method (COMSOL) and our calculations. Moreover, for TSV cases, we should be more careful, we want to establish a valid compact model for frequency >10GHz, so that's why we do the optimization for TSV compact model, because at high frequency (>10GHz), if we keep the same RLCG model, by adjusting their values, we can still fit with the measurement data (c.f 2.3.2), up to 10GHz. Currently, we did not explicitly take into account the permeability; it is not realistic to go beyond 20 GHz in this analysis (that is not so bad); but we think that it was interesting to compare the FEM in order to test the robustness of our algorithm.

3.2.2.2) Alteration of the Contacts' Shape and Their Number

Unlike the pioneered method, based on Green's functions [START_REF] Gharpurey | Transform Domain Techniques for Efficient Extraction of Substrate Parasitics 2 : Theory : The Substrate Green Function[END_REF] that calculates only for rectangular contacts, our method can be used for any contact shape: circle, concentric circles, rectangle, loop, T-shape, etc. Figure 65 shows some examples from our 3-D TLE simulator. We test it by comparing with the results from COMSOL.

First, we apply our model, with three different contacts in Figure 65(a).

All the three contacts are on the top surface of the substrate. The square contact is contact 1, the T-shape contact is contact 2, and the circle one is contact 3.

The impedance modules between these three contacts, calculated from 3D-TLE and COMSOL, are shown together in Figure 65 (b), in which Z12 at the top is the impedance between contacts 1 and 2, the rest being of a similar manner.

We can see that these results, from the proposed methods, agree very well with the results calculated from COMSOL.

3.2.3) Heat equation

A problem commonly encountered in the thermal analysis of electronic packages, or in 3-D ICs, is that of thermal spreading resistance. Thermal spreading resistance occurs as heat flows by conduction between a source and a sink with different cross-sectional areas. One example is that of a multilayer chip. Another one is that of a module package with a thermal grease path between a chip and the module cap. In either case, heat flows from the chip across a given area into the substrate or cap and spreads out to leave across another area. We are, here, in the case of (un)steady temperature due to one or multiple heat sources, using in this last case the principle of superposition. A thermal spreading resistance (still in the reciprocal domain) can be extracted from discrete heat source. Typical applications are cooling of device areas, at the package and at die level. [START_REF] Yue Ma | Electro-Thermal Considerations Dedicated to 3-D Integration; Noise Coupling[END_REF], [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF] We consider 3-D transient heat conduction in a non-homogenous finite medium [START_REF] Tamene | Thermal behaviour of a multilayer media in transient regime[END_REF] [START_REF] Ndip | Analytical, numerical, and measurement-based methods for extracting the electrical parameters of through silicon vias (TSVs)[END_REF] [176] [START_REF] Ferraiuolo | Heat transfer in a multi-layered thermal protection system under aerodynamic heating[END_REF].

We can write the heat equation as follows: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑑𝑑 2 𝑇𝑇 𝑑𝑑𝑜𝑜 2 + 𝑑𝑑 2 𝑇𝑇 𝑑𝑑𝜕𝜕 2 + 𝑑𝑑 2 𝑇𝑇 𝑑𝑑𝜕𝜕 2 - 1 𝛼𝛼 𝑑𝑑𝑇𝑇 𝑑𝑑𝑡𝑡 = 0 (3-21)
Where 𝑠𝑠 = 𝑘𝑘/ρc is the thermal diffusivity, k is is the effective isotropic thermal conductivity, and c is the isobar mass heat. For the steady state, the heat equation is resumed to the Laplace equation, similar to Poisson's equation when no electric charge is present.

As it can be seen, we get analogies with (3-2)-(3-8).

In the same way that for Poisson's equation, we extract an associated Green kernel, i.e., if we assume T = X(x, x')・Y (y, y')・Z(z, z')τ (t, t'), we can extend (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF][START_REF] Limansyah | 3D image sensor SiP with TSV silicon interposer[END_REF][START_REF] Motoyoshi | 3D-LSI technology for image sensor[END_REF][START_REF] Charbonnier | Wafer Level Packaging Technology Development for CMOS Image Sensors Using Through Silicon Vias M1 pad on front side[END_REF][START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF][START_REF] Katti | Through-silicon-via capacitance reduction technique to benefit 3-D IC performance[END_REF], thus resulting in First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 78

1 𝑋𝑋 • 𝑑𝑑 2 𝑋𝑋 𝑑𝑑𝑜𝑜 2 + 1 𝑌𝑌 • 𝑑𝑑 2 𝑌𝑌 𝑑𝑑𝜕𝜕 2 + 1 𝑍𝑍 • 𝑑𝑑 2 𝑍𝑍 𝑑𝑑𝜕𝜕 2 = -𝐴𝐴 2 𝛿𝛿(𝑜𝑜-𝑜𝑜′)•𝛿𝛿(𝜕𝜕-𝜕𝜕′)•𝛿𝛿(𝜕𝜕-𝜕𝜕′)•𝛿𝛿(𝑡𝑡-𝑡𝑡′) 𝛼𝛼 (3-22)
Then [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]]

𝑑𝑑 2 𝑋𝑋 𝑑𝑑𝑜𝑜 2 + λ 2 𝑋𝑋 = 𝑑𝑑 2 𝑌𝑌 𝑑𝑑𝜕𝜕 2 + µ 2 𝑌𝑌 = 𝑑𝑑 2 𝑍𝑍 𝑑𝑑𝜕𝜕 2 -γ 2 𝑍𝑍 = 𝑑𝑑τ 𝑑𝑑𝑡𝑡 -𝑠𝑠(λ 2 + µ 2 -γ 2 ) τ = 0 (3-23)
Where λ, µ, and γ are the eigenvalues associated with the Green kernel of this heat equation with [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

λ 2 + µ 2 -γ 2 + 𝐴𝐴 2 𝛼𝛼 = 0 (3-24)
The last equation in has an evanescent solution versus time; for an i th layer, we can write

𝜏𝜏 𝑖𝑖 = 𝜏𝜏 𝑖𝑖0 • exp (-(λ 𝑖𝑖𝑜𝑜 2 + µ 𝑖𝑖𝜕𝜕 2 -γ 𝑖𝑖𝜕𝜕 2 ) • 𝑠𝑠 • 𝑡𝑡 (3-25)
Staying static in the reciprocal domain (so, we can also take advantage of the data compression, inherent to the DCT), equation (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF][START_REF] Limansyah | 3D image sensor SiP with TSV silicon interposer[END_REF][START_REF] Motoyoshi | 3D-LSI technology for image sensor[END_REF][START_REF] Charbonnier | Wafer Level Packaging Technology Development for CMOS Image Sensors Using Through Silicon Vias M1 pad on front side[END_REF][START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF][START_REF] Katti | Through-silicon-via capacitance reduction technique to benefit 3-D IC performance[END_REF] becomes [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑑𝑑 2 𝑋𝑋 𝑑𝑑𝑜𝑜 2 + 𝑑𝑑 2 𝑌𝑌 𝑑𝑑𝜕𝜕 2 + 𝑑𝑑 2 𝑍𝑍 𝑑𝑑𝜕𝜕 2 - 1 τ . 𝑑𝑑τ 𝑑𝑑𝑡𝑡 = -λ 2 𝑋𝑋 -µ 2 𝑌𝑌 + γ 2 𝑍𝑍 -� j α � ωτ = 0 (𝑗𝑗 2 = -1) (3-26)
We can define a Fourier coefficients' spreading (transcendental) impedance function as the following ratio: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] 𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇𝑖𝑖 = 𝐴𝐴 𝑖𝑖 /𝐹𝐹 𝑖𝑖 Where Ai and Bi are the Fourier coefficients of the general i th solution for the temperature, in the z-direction perpendicular to the stacked layers

𝐹𝐹𝐷𝐷𝑇𝑇 𝑖𝑖 = 𝐴𝐴 𝑖𝑖 • cosh(𝛾𝛾𝑧𝑧) + 𝐹𝐹 𝑖𝑖 • sinh(𝛾𝛾𝑧𝑧) (3-28)

Boundary Conditions

The continuity of the thermal conductivity at interface layers leads to

𝑘𝑘 𝑖𝑖 𝑑𝑑𝑇𝑇 𝑠𝑠 𝑑𝑑𝜕𝜕 𝑠𝑠 = 𝑘𝑘 𝑖𝑖+1 𝑑𝑑𝑇𝑇 𝑠𝑠+1 𝑑𝑑𝜕𝜕 𝑠𝑠+1 (𝑁𝑁𝑑𝑑𝑠𝑠𝑚𝑚𝑎𝑎𝑛𝑛𝑛𝑛 𝑐𝑐𝑜𝑜𝑛𝑛𝑑𝑑𝑆𝑆𝑡𝑡𝑆𝑆𝑜𝑜𝑛𝑛) (3-29)
We have also at interface

𝑋𝑋 𝑖𝑖 (𝑡𝑡) = 𝑋𝑋 𝑖𝑖+1 (𝑡𝑡), 𝑌𝑌 𝑖𝑖 (𝑡𝑡) = 𝑌𝑌 𝑖𝑖+1 (𝑡𝑡) (𝐷𝐷𝑆𝑆𝑟𝑟𝑆𝑆𝑐𝑐ℎ𝑙𝑙𝑑𝑑𝑡𝑡 𝑐𝑐𝑜𝑜𝑛𝑛𝑑𝑑𝑆𝑆𝑡𝑡𝑆𝑆𝑜𝑜𝑛𝑛) (3-30) 𝑘𝑘 𝑖𝑖 𝑇𝑇 𝑠𝑠,𝑧𝑧 𝑇𝑇 𝑠𝑠+1,𝑧𝑧 = 𝑘𝑘 𝑖𝑖+1 𝑅𝑅 𝐹𝐹𝐷𝐷𝐷𝐷𝑇𝑇 𝑠𝑠,𝑧𝑧 𝑅𝑅 𝐹𝐹𝐷𝐷𝐷𝐷𝑇𝑇 𝑠𝑠+1,𝑧𝑧 (3-31)
See the analogy with the induction vector; at an interface without charge, we have

𝜀𝜀 𝑖𝑖 𝐸𝐸 𝑖𝑖 = 𝜀𝜀 𝑖𝑖+1 𝐸𝐸 𝑖𝑖+1 (𝐸𝐸: 𝐸𝐸𝑙𝑙𝑑𝑑𝑐𝑐𝑡𝑡𝑟𝑟𝑆𝑆𝑐𝑐𝑎𝑎𝑙𝑙 𝑓𝑓𝑆𝑆𝑑𝑑𝑙𝑙𝑑𝑑) (3-32)
If and are verified, it follows: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 79

𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇 𝑖𝑖,𝜕𝜕 • 𝑌𝑌 𝑖𝑖(𝜕𝜕) • 𝑑𝑑 -(-γ 𝑠𝑠,𝑧𝑧 2 + µ 𝑠𝑠,𝑦𝑦 2 + λ 𝑠𝑠,𝑜𝑜 2 )𝑡𝑡 = -𝐹𝐹 𝑖𝑖,𝜕𝜕 • 𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇 𝑖𝑖+1,𝜕𝜕 • 𝑌𝑌 𝑖𝑖+1(𝜕𝜕) • 𝑑𝑑 -(-γ 𝑠𝑠+1,𝑧𝑧 2 + µ 𝑠𝑠+1,𝑦𝑦 2 + λ 𝑠𝑠+1,𝑜𝑜 2 )𝑡𝑡 (3-33) 𝑘𝑘 𝑖𝑖,𝜕𝜕 • 𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇 𝑖𝑖,𝜕𝜕 • 𝑌𝑌 𝑖𝑖(𝜕𝜕) • 𝑑𝑑 -(-γ 𝑠𝑠,𝑧𝑧 2 + µ 𝑠𝑠,𝑦𝑦 2 + λ 𝑠𝑠,𝑜𝑜 2 )𝑡𝑡 = -𝑘𝑘 𝑖𝑖+1,𝜕𝜕 • 𝐹𝐹 𝑖𝑖+1,𝜕𝜕 • γλ𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇 𝑖𝑖+1,𝜕𝜕 • 𝑌𝑌 𝑖𝑖+1(𝜕𝜕) • 𝑑𝑑 -(-γ 𝑠𝑠+1,𝑧𝑧 2 + µ 𝑠𝑠+1,𝑦𝑦 2 + λ 𝑠𝑠+1,𝑜𝑜 2
)𝑡𝑡 We have the same set and , replacing Y by X. Moreover, and (3-34) are verified if [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] Note that for different thermal diffusivities or conductivities, in each layer, but with kx,i = ky,i (see isotropy) [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

γ 𝑖𝑖+1,𝜕𝜕 = � α i α i+1 . γ 𝑖𝑖,𝜕𝜕 2 + � α i α i+1 -1� . ( λ 𝑖𝑖,𝑜𝑜 2 + µ 𝑖𝑖,𝜕𝜕 2 )� 1 2
(3-37)

We obtain [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝐴𝐴 𝑖𝑖𝜕𝜕 = 𝐹𝐹 𝑖𝑖𝜕𝜕 • 𝑅𝑅 𝐹𝐹𝐶𝐶𝐷𝐷𝑇𝑇 𝑖𝑖,𝜕𝜕 . (γ 𝑖𝑖,𝜕𝜕 ) (3-38) 𝑅𝑅 𝐹𝐹𝐶𝐶𝑇𝑇 𝑖𝑖,𝜕𝜕 (γ 𝑙𝑙 ) = 𝑘𝑘 𝑠𝑠+1 𝑅𝑅 𝐹𝐹𝐷𝐷𝑇𝑇 𝑠𝑠+1,𝑧𝑧 (γ 𝑛𝑛 )+𝑘𝑘 𝑠𝑠 •𝑡𝑡𝜋𝜋𝑙𝑙ℎ(γ 𝑠𝑠,𝑧𝑧 •𝑡𝑡 𝑠𝑠 ) 𝑘𝑘 𝑠𝑠 .𝑅𝑅 𝐹𝐹𝐷𝐷𝑇𝑇 𝑠𝑠+1,𝑧𝑧 (γ 𝑛𝑛 )•𝑡𝑡𝜋𝜋𝑙𝑙ℎ(γ 𝑠𝑠,𝑧𝑧 •𝑡𝑡 𝑠𝑠 ) (3-39)
Here, γ 𝑙𝑙 refers to the eigenvalue in ; ti is the thickness of the i th layer.

The above development seems to be important because it does not have the classic form of previous works, especially in this thermal area. Furthermore, we get a shape analogous to the thermal impedance and the recursive electrical impedance specific to the TLM method [see First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 80 (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF][START_REF] Limansyah | 3D image sensor SiP with TSV silicon interposer[END_REF][START_REF] Motoyoshi | 3D-LSI technology for image sensor[END_REF]] also produced by Green kernels [see (3)(4)[START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF]]. Moreover, to the best of our knowledge, this triple analogy, working in the reciprocal field, is innovative.

The impedance associated with the Fourier coefficient ratio of temperature solution is presented in Figure 65. Using this low-pass filter, tuning a maximum frequency should permit us, for instance, to scrutinize the thermal flow behavior across each interface layer, for a frequency range domain. In addition, taking inverse Fourier transforms, we could compare the direct calculation of time-dependent heat profile (see FEM).

Finally, in general, the real solution of (3-21) takes the following expression:

∆𝑇𝑇 (𝑜𝑜, 𝑦𝑦, 𝑜𝑜 ′ , 𝑦𝑦 ′ , 𝑧𝑧, 𝑧𝑧 ′ ) = 𝑇𝑇 -𝑇𝑇 ∞ = 𝑇𝑇 0 • 𝑑𝑑𝑜𝑜𝑑𝑑�-� λ 𝑖𝑖,𝑜𝑜 2 + µ 𝑖𝑖,𝜕𝜕 2 -γ 𝑖𝑖,𝜕𝜕 2 � • 𝑠𝑠 • 𝑡𝑡� • ∑ ∑ � 2�𝐴𝐴 𝑁𝑁 𝑑𝑑 -γ 𝑚𝑚𝑛𝑛 �𝑑𝑑+𝑍𝑍 𝑡𝑡 � +𝐵𝐵 𝑁𝑁 𝑑𝑑 γ 𝑚𝑚𝑛𝑛 �𝑑𝑑+𝑍𝑍 𝑡𝑡 � ��𝑑𝑑 -γ 𝑚𝑚𝑛𝑛 𝑍𝑍 ℎ +𝑑𝑑 γ 𝑚𝑚𝑛𝑛 𝑍𝑍 ℎ � 𝜋𝜋𝜋𝜋 𝑁𝑁 γ 𝑚𝑚𝑛𝑛 �𝐵𝐵 𝑁𝑁 𝑑𝑑 𝑑𝑑 -𝐴𝐴 𝑁𝑁 𝑑𝑑 -𝑑𝑑 � � 𝑐𝑐𝑜𝑜𝑠𝑠 � 𝑚𝑚𝑜𝑜 𝜋𝜋 � 𝑐𝑐𝑜𝑜𝑠𝑠 � 𝑙𝑙𝜕𝜕 𝜋𝜋 � ∞ 𝑙𝑙=1 ∞ 𝑚𝑚=1 (3-40)
Where 𝑇𝑇 ∞ is the stationary temperature.

We built our simulator in order to make an efficient use of the analogies between, first of all, electrical and thermal models. In particular, if all the relevant variables' calculation (voltages/temperature, current density/thermal flow, noise power/current fluctuations) made in the reciprocal domains of space and frequency is done in the main program, we do develop a single special subroutine to calculate the impedance (electrical or thermal, or transfer impedances) [see hereafter] for noise extraction (between any two points into the bulk). Typically, we take 300 points Χ 300 points, and 12 layers [see the rectangle in Figure 61 and Figure 62: Zin(k) by TLM]. The first results are presented for temperature coming both from FEM algorithm and from our method, where the temperature source profile, applied to one or both the contacts, is depicted in Figure 66(a) and the temperature map in Figure 66(b) (FEM results (left) and Green's results (right)). We will go further, particularly with numerical experiences, to consolidate our algorithms.

We think these modellings can be efficient for the concerned industry, for instance, with 3-D electrical simulations. We can also seek hot points, involving drastic transient regimes, by the thermal approach. We should work on the placement routine of coolers, via investigations on the heat spreading, in three dimensions. A minimum, the electro thermal coupling can be done by the linear simple formula as [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF]

𝑅𝑅 = 𝑅𝑅 0 (1 + 𝑠𝑠 0 ∆𝑇𝑇) (3-41)
Finally, we will begin to study noise phenomena, fundamental for the nanoscale, for instance, the thermal noise, 4kRT, coupling still electrical and thermal fields, or the generationrecombination (GR)-like one, as well as their coupling.

We present here a first modeling of second-order electrical phenomena for 3-D circuits.

3.3) Thermal connection modeling

After a thermal substrate analysis, we inspect the thermal behavior of TSVs, the key elements of connections embedded in the substrate. 3D IC integration can effectively increase the system's integrity, but as a side effect, the following increase of system power density can cause serious heat dissipation problem [START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF] [START_REF] Li | Real-time constrained task scheduling in 3D chip multiprocessor to reduce peak temperature[END_REF]. It has become a bottleneck for the 3D IC. In this case, how to remove heat from the IC circuits and realize an effective heat management, becomes the key of the 3D IC technology. In order to solve the heat dissipation problem, researchers from all over the world have proposed some heat management solutions, such as conducting TSV, micro-pumps, using the new carbon nano-tube and graphene (which have a better heat conductivity than silicon) as the material. But all these technologies are based on the analysis of the heat transfer. The following part of this chapter will firstly give an accurate heat transfer analytical model of cylindrical TSVs, and study the temperature characters. And then, a study of a 4 cores single chip model is settled, in order to calculate multi-cores 3D-IC temperature characteristics.

[178][179][180][181][182][183][184]
Here, we did not consider the temperature-dependent material characteristics' change or we can also say that the temperature is fixed low, so the change of the material's characteristics is weak. Here, we just give a solution for each uniform layer and low temperature design.

In our study, we adopt linear model; we mean that the global effects of substrate and connections can be split. But, if the connections become very important, we cannot dissociate substrate with TSV, RDL, etc. Intercorrelation terms do intervene; the system can be approached by non-linear models.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 83

3.3.1) 3D IC heat analysis

3.3.1.1) 3D IC heat transfer compact model without TSVs

As shown in the following, Figure 68(a), 3D-IC is composed of n dies, and the bottom die is connected to a heat sink. Each die is connected by an adhesive coating layer, Si substrate and an oxide layer; the heat is generated by the heat source attached at each die, and the n th die's power dissipation is supposed here as 𝑄𝑄 𝑙𝑙 .

Because of the weak heat conductivity between oxide layer and coating layer, the heat conduction between dies becomes very hard, and compared with the dies' temperature change, the temperature exchange between dies can be neglected. Therefore, we can use one average temperature to define the temperature of each layer, and 3D chip is composed of n layers' 2D chips with different temperatures. According to the Fourier heat flow analysis, using the heat flow as an analogy of the current, temperature as an analogy of the voltage, heat resistance as an analogy of the resistance, we can get the j th layer's temperature. [START_REF] Im | Full chip thermal analysis of planar(2-D)and vertically integrated(3-D)high performance ICs[END_REF]

𝑇𝑇 𝑗𝑗 = ∑ [𝑅𝑅 𝑖𝑖 (∑ 𝑄𝑄 𝑚𝑚 𝑙𝑙 𝑚𝑚=𝑖𝑖 )] 𝑗𝑗 𝑖𝑖=1 (3-42)
Here, n is the total layer number, 𝑅𝑅 𝑚𝑚 and 𝑄𝑄 𝑚𝑚 are respectively the m th layer's heat resistance and power dissipation. [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF]- [START_REF]Matlab[END_REF] Assuming that the each layer's power dissipation is the same, all Q, the first layer's thermal resistance is 𝑅𝑅 1 , and the rest layers' thermal resistances are the same R, so for the n layers 3D IC, the top layer' temperature can be expressed as [START_REF] Im | Full chip thermal analysis of planar(2-D)and vertically integrated(3-D)high performance ICs[END_REF], From Figure 68(b), we can see that, the first die's thermal resistance 𝑅𝑅 1 include the thermal resistance of 𝑇𝑇 𝑖𝑖_1 substrate, package and heat sink; the other dies' thermal resistance R include the thermal resistance of 𝑇𝑇 𝑖𝑖 substrate, coating layer and oxide layer. The thermal resistance is defined as 𝑅𝑅 = 𝑙𝑙/(𝑘𝑘𝑇𝑇), 𝑙𝑙 is the heat flow length, k is the heat conductivity, 𝑇𝑇 is the cross-section surface of heat flow; 𝑄𝑄 represents the power dissipation, so 𝑅𝑅 1 and 𝑅𝑅 represent respectively [START_REF] Im | Full chip thermal analysis of planar(2-D)and vertically integrated(3-D)high performance ICs[END_REF]

𝑇𝑇 𝑙𝑙 = 𝑄𝑄 � 𝑅𝑅 2 𝑛𝑛 2 + (𝑅𝑅 1 -
𝑅𝑅 1 = 𝑅𝑅 𝑠𝑠𝑖𝑖 + 𝑅𝑅 𝑑𝑑𝑘𝑘 + 𝑅𝑅 ℎ𝑠𝑠 = 𝜌𝜌 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑠𝑠𝑠𝑠 𝑇𝑇 + 𝑅𝑅 𝑑𝑑𝑘𝑘 + 𝑅𝑅 ℎ𝑠𝑠 (3-44) 𝑅𝑅 = 𝑅𝑅 𝑠𝑠𝑖𝑖 + 𝑅𝑅 𝑙𝑙𝜌𝜌𝑡𝑡𝑑𝑑 + 𝑅𝑅 𝑖𝑖𝑙𝑙𝑠𝑠 = 𝜌𝜌 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑠𝑠𝑠𝑠 𝑇𝑇 + 𝜌𝜌 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 𝑘𝑘 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 𝑇𝑇 + 𝜌𝜌 𝑠𝑠𝑛𝑛𝑠𝑠 𝑘𝑘 𝑠𝑠𝑛𝑛𝑠𝑠 𝑇𝑇 (3-45)
where 𝑅𝑅 𝑠𝑠𝑖𝑖 , 𝑅𝑅 𝑑𝑑𝑘𝑘 , 𝑅𝑅 ℎ𝑠𝑠 , 𝑅𝑅 𝑙𝑙𝜌𝜌𝑡𝑡𝑑𝑑 , 𝑅𝑅 𝑖𝑖𝑙𝑙𝑠𝑠 represent respectively, thermal resistance of each dies' silicon substrate, package , heat sink, coating layer and insulation layer, 𝑙𝑙 𝑠𝑠𝑖𝑖 , 𝑙𝑙 𝑙𝑙𝜌𝜌𝑡𝑡𝑑𝑑 , 𝑙𝑙 𝑖𝑖𝑙𝑙𝑠𝑠 represent respectively the thickness of silicon substrate, coating layer and insulation layer, 𝑘𝑘 𝑠𝑠𝑖𝑖 , 𝑘𝑘 𝑙𝑙𝜌𝜌𝑡𝑡𝑑𝑑 , 𝑘𝑘 𝑖𝑖𝑙𝑙𝑠𝑠 represent the thermal conductivity of silicon substrate, coating layer and insulation layer, S is the chip's surface.

3.3.1.2) 3D IC top layer chip temperature analysis model by considering TSVs

In the 3D IC, TSV generally is filled with copper, because of its high thermal conductivity and strong heat dissipation power. If we neglect TSVs in the heat transfer model, it will lead to an overestimation of the chip temperature, so it's necessary to consider TSV parasitic when analyzing 3D IC heat characteristics. And here we adopt a 3D IC top layer analytical model by considering TSVs.

After adding TSVs in the 3D IC, the structure will change to the following Figure 69 Assuming that the total surface of each layer in the IC is 𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇 , the total chip surface is S, and TSV surface ratio is r, defined as:

𝑟𝑟 = 𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇 𝑇𝑇 (3-46)
When considering TSVs, the layer's thermal resistance will change to the parallel of TSV thermal resistance and the original thermal resistance, as shown in Figure 69(b). Assuming chip's surface stays unchanged, by adding TSV, the other parts' surface of the layer will be reduced, and that will be (1 -𝑟𝑟)𝑇𝑇. So, the first layer's thermal resistance will change from 𝑅𝑅 1 to 𝑅𝑅

𝑇𝑇 𝑙𝑙 = 𝑄𝑄[ (� 𝑡𝑡 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑠𝑠𝑠𝑠 + 𝑡𝑡 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 𝑘𝑘 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 + 𝑡𝑡 𝑠𝑠𝑛𝑛𝑠𝑠 𝑘𝑘 𝑠𝑠𝑛𝑛𝑠𝑠 � 1 (1-𝑟𝑟)𝑇𝑇 || 𝑡𝑡 𝑠𝑠𝑠𝑠 +𝑡𝑡 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 +𝑡𝑡 𝑠𝑠𝑛𝑛𝑠𝑠 𝑘𝑘 𝑇𝑇𝑇𝑇𝑇𝑇 𝑟𝑟𝑇𝑇 ) 2 𝑛𝑛 2 + (( 𝜌𝜌 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑠𝑠𝑠𝑠 (1-𝑟𝑟)𝑇𝑇 || 𝜌𝜌 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑇𝑇𝑇𝑇𝑇𝑇 𝑟𝑟𝑇𝑇 + 𝑅𝑅 𝑑𝑑𝑘𝑘 + 𝑅𝑅 ℎ𝑠𝑠 ) - ( � 𝑡𝑡 𝑠𝑠𝑠𝑠 𝑘𝑘 𝑠𝑠𝑠𝑠 + 𝑡𝑡 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 𝑘𝑘 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 + 𝑡𝑡 𝑠𝑠𝑛𝑛𝑠𝑠 𝑘𝑘 𝑠𝑠𝑛𝑛𝑠𝑠 � 1 (1-𝑟𝑟)𝑇𝑇 || 𝑡𝑡 𝑠𝑠𝑠𝑠 +𝑡𝑡 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑 +𝑡𝑡 𝑠𝑠𝑛𝑛𝑠𝑠 𝑘𝑘 𝑇𝑇𝑇𝑇𝑇𝑇 𝑟𝑟𝑇𝑇 2 ))𝑛𝑛]
(3-49)

3.3.1.3) 3D IC Thermal modeling result

Here, we use an 8 dies 3D IC model, and we choose MATLAB to do the simulation. The following table gives the model parameters. Through the Matlab simulation, we can get the TSV top layer's temperature's change with the IC layer numbers, as shown in the following figure 10. We can see that, with the increase of number of layers, the chip top surface temperature increases linearly, the three colored lines represent r equals to 0.0001, 0.001, 0.01 and the black dotted line represents the dies without TSV. For the case without TSV, the top surface temperature can reach 427K, but after considering TSVs, the decrease of temperature is more obvious. The greater the r is, the lower the temperature is. So for a 8 layers 3D-IC, when r equals to 0.0001, the temperature of top layer decreases from 427K to 421K, when r=0.001, it decreases to 392K, when r=0.01, it's 360K, and this is because of the heat dissipation effect of TSV. As shown in Figure 71, the 3D IC top layer's temperature change with TSV surface ratio r and dies' number n. For the same r, with the increase of dies' number n, r has more and more obvious influence to temperature. For a very high n, when we decrease r, at the beginning, the chip's temperature doesn't change, when r arrives enough small, the temperature T increases heavily. The following Figure 72 shows the temperature changes when n=8. When r equals to 0.0001, 3D IC top surface's temperature is 421K, with the increase of r, the temperature decreases. When r equals to 0.005, the temperature decreases to 366K, the decrease can reach 55K, about 13%; when r equals to 0.01, to compare with r equals to 0.005, the decrease is 6K, about 1.6%. When r equals to 0.015, the temperature is 357K, compared with r = 0.01, the decrease has only 3K, about 0.8%, and with the augmentation of r, the temperature doesn't have a significant change. Thus, in the 3D-IC design, for n=8, the best surface ratio of TSVs is 0.5%~1%. It can be adjusted with different demands. If the chip doesn't need so many interconnection signal line, the other TSVs can be First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 87 changed to thermal via and get a better heat transfer. 3D IC designer can read directly from the above Figure 71, the r value according to their temperature demand. When n equals to other value, r can also be calculated by this way.

Figure 72 Temperature change with surface ratio r (n=8)

But if we want to get every point's temperature of the 3D IC, another 2D heat transfer solver should be used to generate accurately the temperature 2D distribution. Here, we adopt a finite volume method (FVM). The heat diffusion equation is in general used to describe the heat conduction in a chip and calculate the temperature profile:

ρ𝑐𝑐 𝑑𝑑 𝜕𝜕𝑇𝑇(𝑟𝑟 ⃗,𝑡𝑡) 𝜕𝜕𝑡𝑡 = ∇ • [𝑘𝑘(𝑟𝑟 ⃗, 𝑇𝑇)∇𝑇𝑇(𝑟𝑟 ⃗, 𝑡𝑡)] + 𝑙𝑙(𝑟𝑟 ⃗, 𝑡𝑡) (3-50)
Which is subject to the general thermal conduction boundary condition.

𝑘𝑘(𝑟𝑟 ⃗, 𝑇𝑇)

𝜕𝜕𝑇𝑇(𝑟𝑟 ⃗,𝑡𝑡)

𝜕𝜕𝑙𝑙 𝑠𝑠 = ℎ 𝑖𝑖 (𝑇𝑇 𝜋𝜋 -𝑇𝑇(𝑟𝑟 ⃗, 𝑡𝑡)) (3-51)
In the above equations, T is the temperature (K), k is the thermal conductivity [W/m/K], ρ is the density of the material (kg/m 3 ), 𝑐𝑐 𝑑𝑑 is the specific heat [J/kg/K], g is the power density of the heat sources (W/m 3 ), and ℎ 𝑖𝑖 is the heat transfer coefficient in the direction of heat flow 𝚤𝚤 ⃗ on the boundary surface of the chip [W/m 2 /K].

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 88 Figure 73 shows our total 3D Thermal simulation work flow. In our case, we firstly get the surface ratio r, and calculate the r-dependent thermal resistance, such as 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 , 𝑅𝑅 𝑇𝑇𝑖𝑖 , 𝑅𝑅 𝑙𝑙𝜌𝜌𝑡𝑡𝑑𝑑 , 𝑅𝑅 𝑖𝑖𝑙𝑙𝑠𝑠 . By using the analytical vertical model, the temperature vertical distribution can be obtained. With the temperature difference, which is similar (analog) to the electrical potential, and we can also directly calculate the heat which passes by the substrate and also heat which passes by TSVs, which can be calculated by the following equation:

𝑞𝑞 𝑇𝑇𝑇𝑇𝑇𝑇_𝑙𝑙 = (𝑇𝑇 𝑛𝑛 -𝑇𝑇 𝑛𝑛-1 ) 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 (3-52) 𝑞𝑞 𝑠𝑠𝑡𝑡𝜋𝜋_𝑙𝑙 = (𝑇𝑇 𝑛𝑛 -𝑇𝑇 𝑛𝑛-1 )
𝑅𝑅 𝑠𝑠𝑠𝑠_𝑛𝑛 +𝑅𝑅 𝑔𝑔𝑡𝑡𝑔𝑔𝑑𝑑_𝑛𝑛 +𝑅𝑅 𝑠𝑠𝑛𝑛𝑠𝑠_𝑛𝑛 And finally, we come back to 2D thermal conduction with 2 different kinds of heat source, 𝑞𝑞 𝑇𝑇𝑇𝑇𝑇𝑇_𝑙𝑙 and 𝑞𝑞 𝑠𝑠𝑡𝑡𝜋𝜋_𝑙𝑙 .Here, we adopt the finite volume method (FVM) to solve the problem. And then, a 2D thermal distribution is generated. The following figures show the bottom layer's and top layer's thermal temperature distribution in the substrate of an 8 dies model with r=0.01 and 4 TSVs. The bottom layer's TSV temperature is 344K and top layer's TSV temperature is 359.88K.

3.3.2) CMP (Chip multiprocessor) heat transfer

With the development of micro-processors, the traditional superscalar technology has slightly improved the CPU performance. Power dissipation issues have greatly restricted the gain of CPU clock frequency. Because of all these things, it needs a change of computer structure arrangement, and it needs a smaller distribution design of micro-processor, and a partially better cell structure. In this background, researchers proposed Chip multiprocessor technology (CMP) [START_REF] Xie | Fast electrical-thermal co-simulation using multigrid method for 3D integration[END_REF][189][152]- [START_REF] Gharpurey | Transform Domain Techniques for Efficient Extraction of Substrate Parasitics 2 : Theory : The Substrate Green Function[END_REF]. CMP means to integrate 2 or more CPU cores in one chip, in which every core can do a multi-thread calculation simultaneously. The main purpose of CMP is to gain the integrity and increase performance. Nevertheless, with the augmentation of integration level and First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 90 the reduction of feature size, chip internal interconnection line ratio increases continuously, especially when the chip feature size is reduced below 0.18μm, the interconnection delay has surpassed gate delay; this brings a serious challenge for the CMP's performance. By adopting 3D technologies, the different cores can be connected vertically, and it can solve effectively a lot of 2D CMP problems. However, due to the 3D CMP layers multi-heat source, CMP 3D IC faces a more serious heat dissipation issues than the other 3D IC. So the thermal study of the CMP 3D IC is very important.

For 3D CMP temperature characteristics, thermal resistance matrix is a very important parameter. It represents unit power dissipation's influence to temperature, once the thermal resistance matrix is obtained. Moreover we can get whichever core's power dissipation influence to the other core. This chapter gives the thermal resistance matrix expression. Based on the thermal resistance matrix, we study precisely the 3D CMP temperature characteristics, and analyze the heat capacitor, thermal resistance and power dissipation's influence on the temperature.

Multiple cores 3D CMP structure involves connecting the cores vertically. Thus, for 2 layers 3D CMP, the chip's internal heat transfer model can be shown as follows, assuming that, each layer has 2 cores. They can be expressed as A,B and C, D, ginter, gintra and ghs are the interlayer heat conductance, inner layer heat conductance and heat sink conductance, respectively. CH, CI, CJ and CK are the cores heat capacitors, respectively. PH, PI, PJ and PK are cores' power dissipation. Tamb is the environment temperature. According to current Fourier heat analysis theory, the heat flow as an analogy of the current, temperature as an analogy of the voltage, heat resistance as an analogy of the resistance, heat capacitor as an analogy of capacitance, and the CMP 2 layers model can be described as the following equation: [START_REF] Santos | Thermal performance of 3D ICs: Analysis and alternatives[END_REF], [START_REF] Zhang | Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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𝐷𝐷 𝑑𝑑𝑇𝑇(𝑡𝑡) 𝑑𝑑𝑡𝑡 + 𝐴𝐴𝑇𝑇(𝑡𝑡) = 𝑃𝑃𝑠𝑠(𝑡𝑡) (3-54)
Here, C is a 4X4 diagonal matrix, and every diagonal element is the core's heat capacitor. T(t) is a 4-dimensional vector, which represents the four cores temperature at time t. A is a 4X4 thermal conductance matrix. P is a 4 dimensional power vector. u(t) is a step function.

3.3.2.1) Thermal resistance matrix

For the stationary case, we neglect the heat capacitor matrix C's influence, and the heat conduction equation can be simplified to

𝑇𝑇 = 𝐴𝐴 -1 𝑃𝑃 (3-55)
Here, 𝐴𝐴 -1 is the thermal resistance matrix. It describes unit power dissipation's influence to the temperature, so it can be called thermal influence matrix. [START_REF] Santos | Thermal performance of 3D ICs: Analysis and alternatives[END_REF], [START_REF] Zhang | Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation[END_REF] By using the nodal analysis, we use 𝑅𝑅 𝑖𝑖𝑗𝑗 to represent the core i's influence resistance to core j, and the thermal resistance matrix can be expressed as

𝐴𝐴 -1 = � 𝑅𝑅 𝐴𝐴𝐴𝐴 𝑅𝑅 𝐴𝐴𝐵𝐵 𝑅𝑅 𝐴𝐴𝐶𝐶 𝑅𝑅 𝐴𝐴𝐷𝐷 𝑅𝑅 𝐵𝐵𝐴𝐴 𝑅𝑅 𝐵𝐵𝐵𝐵 𝑅𝑅 𝐵𝐵𝐶𝐶 𝑅𝑅 𝐵𝐵𝐷𝐷 𝑅𝑅 𝐶𝐶𝐴𝐴 𝑅𝑅 𝐷𝐷𝐴𝐴 𝑅𝑅 𝐶𝐶𝐵𝐵 𝑅𝑅 𝐷𝐷𝐵𝐵 𝑅𝑅 𝐶𝐶𝐶𝐶 𝑅𝑅 𝐶𝐶𝐷𝐷 𝑅𝑅 𝐷𝐷𝐶𝐶 𝑅𝑅 𝐷𝐷𝐷𝐷 � (3-56)
Because core A and core D do not have a direct thermal connection, the thermal influence between them can be neglected, so as the B, C. Then:

𝑅𝑅 𝐴𝐴𝐷𝐷 = 𝑅𝑅 𝐷𝐷𝐴𝐴 = 𝑅𝑅 𝐵𝐵𝐶𝐶 = 𝑅𝑅 𝐶𝐶𝐵𝐵 = 0 (3-57)
By using the nodal analysis, the thermal resistance matrix can be expressed as [START_REF] Santos | Thermal performance of 3D ICs: Analysis and alternatives[END_REF], [START_REF] Zhang | Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation[END_REF]

𝐴𝐴 = � 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 + 𝑙𝑙 ℎ𝑠𝑠 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 + 𝑙𝑙 ℎ𝑠𝑠 � (3-58)

3.3.2.2) CMP Thermal modeling result

After getting the thermal resistance matrix, we can get the 3D CMP temperature characteristic equations [START_REF] Santos | Thermal performance of 3D ICs: Analysis and alternatives[END_REF], [START_REF] Zhang | Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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� 𝐷𝐷 𝐴𝐴 0 0 0 0 𝐷𝐷 𝐵𝐵 0 0 0 0 0 0 𝐷𝐷 𝐶𝐶 0 0 𝐷𝐷 𝐷𝐷 � ⎝ ⎜ ⎜ ⎜ ⎛ 𝑑𝑑𝑇𝑇 𝐴𝐴 (𝑡𝑡) 𝑑𝑑𝑡𝑡 𝑑𝑑𝑇𝑇 𝐵𝐵 (𝑡𝑡) 𝑑𝑑𝑡𝑡 𝑑𝑑𝑇𝑇 𝐷𝐷 (𝑡𝑡) 𝑑𝑑𝑡𝑡 𝑑𝑑𝑇𝑇 𝐷𝐷 (𝑡𝑡) 𝑑𝑑𝑡𝑡 ⎠ ⎟ ⎟ ⎟ ⎞ + � 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 0 0 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 + 𝑙𝑙 ℎ𝑠𝑠 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 -𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑟𝑟𝜋𝜋 + 𝑙𝑙 𝑖𝑖𝑙𝑙𝑡𝑡𝑑𝑑𝑟𝑟 + 𝑙𝑙 ℎ𝑠𝑠 � � 𝑇𝑇 𝐴𝐴 (𝑡𝑡) 𝑇𝑇 𝐵𝐵 (𝑡𝑡) 𝑇𝑇 𝐶𝐶 (𝑡𝑡) 𝑇𝑇 𝐷𝐷 (𝑡𝑡) � = � 𝑃𝑃 𝐴𝐴 𝑃𝑃 𝐵𝐵 𝑃𝑃 𝐶𝐶 𝑃𝑃 𝐷𝐷 � 𝑠𝑠(𝑡𝑡) (3-59)
Assuming that every core has the same heat capacitor C, and their power dissipations are all P. By using Matlab differential equation solver, we can get 3D CMP temperature characteristics. When t=0, input a step heat source, 3D CMP temperature temporary character can be found below. Because core A and B stay in the same condition, so their temperature characteristics are the same. We can see that from the following Figure 76 and so is core C and D. From this figure, the change of the heat flow will increase the cores temperature at first. Then, the temperature will get to stationary. Core A and B's temperature is about 5K higher than that of core C and D, that's due to core C and D are a bit far away from the heat sink. Moreover, heat is not easy to be dissipated. For different heat capacities, the temperature characteristics of core A, B and core C, D are shown in the former Figure 77. The higher C is, the longer time the cores will need to attend the stationary temperature. However, it will not change the maximum temperature, thus we cannot change the CMP temperature by changing heat capacity.

Nevertheless, when the heat dissipation changes, core A&B, and core C&D's temperature character can be found in the former Figure 77. The three lines represent the heat dissipation of 20W, 25W and 30W. Once the heat dissipation increases 5W, core A&B and core C&D gain separately about 13.17K and 12.9K. The power dissipation has more influence on the core A&B, that's due to the longer distance to the heat sink comparing with the core C&D. The core's stationary temperature change linearly with power dissipation, so designers can adopt different low power technique to reduce core's power dissipation and then reduce the temperature. As we can see from the Figure 77 (e)(f), when the thermal resistance increase 50% of the standard value, the core A&B's temperature increase about 32.2K, and core C&D's temperature increase about 30.3K. So the stationary temperature increases linearly with the thermal resistance. Then, we can choose a higher thermal conductivity material or use more thermal via in the dies, in order to reduce the chip's thermal resistance, and control the chip's temperature.

3.3.2.3) CMP conclusion

Firstly, this part introduces some basic thermal analysis leading to a 3D IC top layer's temperature model, by introducing surface ratio r, correlate the 3D IC temperature analytical model. Based on the correlated temperature model, study the influence of TSV's surface ratio r to the temperature, finally give the best r factor's range of 8 dies 3D IC model. Based on the thermal resistance, we study the 3D CMP temperature characteristics, and analyze the heat capacity, thermal resistance and heat dissipation's influence on chip temperature. As shown above, thermal resistance and power dissipation can affect 3D CMP's stationary temperature, so we can adopt different low power design to reduce chip's power dissipation, and we can also choose a higher heat conductivity material to reduce the thermal resistance to control the chip temperature. The higher heat capacity is, the longer time 3D CMP will need to get to the stationary temperature. However, the change of heat capacity will not change the final stationary temperature. Furthermore, this part gives a very important basis for the 3D CMP heat management.

In fact, this part gives a simple total very prime view of 3D IC problems and a simple solution. We don't take so complicated case into consideration, but for the further study, we will consider electro-thermal effect of caches' and cores' interconnections.

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3.4) Electro-thermal (ET) modeling of VLS circuits

As indicated in the roadmap for integrated circuits (ICs), the increasing power density needs the decreasing power supply voltage, which results in the need of larger current supply by the power delivery networks (PDNs) [4], [START_REF] Devised | ITRS for semiconductor 2015[END_REF]. Consequently, Joule heating and power switching [START_REF] Zheng | Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits[END_REF] rise a lot the circuit temperature, which heavily influences the electrical performances, because of the heavily changed electrical temperature dependent resistivity [START_REF] Pedram | Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods[END_REF]. So an efficient ET cosimulation PDN software is needed, for now, to calculate the effective IR drop, which is strongly related to the electrical resistivity. Moreover, ET co-simulations are inevitable in 3D IC design [START_REF] Todri | A study of tapered 3-D TSVs for power and thermal integrity[END_REF] [START_REF] Xie | Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and joule heating effects[END_REF].

We use a standard structure for ground and power networks as shown in the following Figure 78. The ground and power networks are separated by an insulation layer, and connected respectively with VDD and GND pins, through a series of impedance Zsupply .

The electrical and thermal issues should be solved together in the static and dynamic analysis. A device level thermal and electrical modeling method will be provided and justified, dedicated to CPW and TSVs. The main heat sources are the logic gates switching, as well as the Joule heating in the PDN interconnects. The thermal transport and electrical transport are very similar, the heat flow corresponding to the electrical current and the temperature difference plays the role of the electrical voltage [START_REF] Chang | Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs[END_REF]. By this way, the electro-thermal co-simulation can be exploited within the same circuit solver. [START_REF] Duong | A Battery-Assisted Passive EPC Gen-2 RFID Sensor Tag IC with Efficient Battery Power Management and RF Energy Harvesting[END_REF]- [START_REF] Pares | Image sensor evolution and enabling 3D technologies[END_REF] Figure 78 Structure for ground and power networks

3.4.1) Electrical modeling of VLS (Very Large Scale) circuits

The DC problem is modeled by two regular resistive grids and one internal node; the temperature-dependent resistors R(T) connect neighboring nodes of the same layer. The power and ground layer are interconnected by a current source I0. The solution of the electrical problem can be expressed as the voltage drop at the node i:

𝑇𝑇 𝑑𝑑 (𝑆𝑆) = 𝑇𝑇 𝐷𝐷𝐷𝐷 -(𝑇𝑇 𝑙𝑙 (𝑆𝑆) -𝑇𝑇 𝑙𝑙 (𝑆𝑆)) (3-60)
Where 𝑇𝑇 𝑙𝑙 (𝑆𝑆) and 𝑇𝑇 𝑙𝑙 (𝑆𝑆) are the node potentials of power and ground planes, respectively.

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A dynamic electrical model can also be carried out when parasitic dynamic circuit has been defined for this structure. We use the standard first order model for each physical cell, by considering the parasitic inductive effect L between adjacent nodes, and a parallel capacitive C between neighboring nodes on the VDD and GND grids. By this way, we draw a dynamic elementary cell schema as shown in Figure 79. The segments' resistance is 3.5 ohm, inductance is 1.2e-3 H, the capacitance is 7.3e-6 F, and the added capacitance at the probe side is 10e-6 F. The voltage source is a sine signal, with an amplitude of 3V, and working frequency 200Hz. Here we use the modified nodal analysis method (MNA) and generalized conjugate residual (GCR) solver and also sparse matrix technic to solve and accelerate the calculation of large scale differential matrix. The precise method description can be found in the annex. In order to verify the method's robustness, the same simulation is done with ADS (advanced design system by Keysight Technologies [207]). The signal is shown in the figure (a), the output signal comparison with ADS is shown in the Figure 82(b). And Figure 82(c) shows the relative error of the MNA+GCR method and ADS. As we can see from the Figure 82(c), our MNA+GCR method has a very good accuracy in compare with the ADS, the maximum error is about 4%. The model describe a coplanar wave model. The electrical circuit is shown in Figure 84.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 99 We define two kinds of lines, one signal line, one ground line, and each line is treated as a T model. We define a Cinter between any two lines and each line is isolated from the substrate by an oxide layer. The voltage source is a pulse signal, with an amplitude of 1V, rise and down time of 0.05ns, duty cycle of 60%, and working frequency 2GHz. Here we also use the modified nodal analysis method (MNA) and generalized conjugate residual (GCR) solve. In order to verify the method's robustness, the same simulation is done in ADS. The signal is shown in the Figure 85(a The model describes a coplanar wave model. The electrical circuit is shown in Figure 87. In Figure 88, we can find out that the MNA+GCR method have the save accuracy with ADS simulator, and it can be integrated with 3D-TLE extractor without any difficulties. The general design process is shown in Figure 89.

This part gives a simple thermal modeling solution for 3D IC. This study method is viable for one CPW model, it can also be used for 20, 100 and more CPWs cases. A difficulty lies on that we could not consider a great number of CPWs, as simple sum of CPWs; we do consider non-linear models, which needs more physical studies.

3.4.3) Thermal modeling of VLS circuits

Due to the negligible heat diffusion in the dielectric, the thermal model can be assumed steady. So the temperature distribution T(x) of metal interconnects can be solved by the 1-D heat diffusion equation: [START_REF] Magnani | Electrothermal analysis Yue MA 2018 233 of carbon nanotubes power delivery networks for nanoscale integrated circuits[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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𝑑𝑑 2 𝑇𝑇(𝑜𝑜) 𝑑𝑑𝑜𝑜 2 = - 𝑙𝑙(𝑜𝑜,𝑇𝑇) 𝑘𝑘 𝑚𝑚 (3-61)
Where 𝑘𝑘 𝑚𝑚 is the thermal conductivity of the metal [W/mK] and 𝑙𝑙(𝑜𝑜, 𝑇𝑇) is the heat sources term [W/m3].

Once the defined grid lengths are smaller than the heat characteristic length, the grid can be used to solve both electrical and thermal dissipation [START_REF] Magnani | A node clustering reduction scheme for power grids electrothermal analysis[END_REF]. Figure 90 is a typical node of thermal network. It is composed of thermal resistances between neighboring nodes, and another thermal resistance linked to the heat-sink. The VDD layers and GND layers are connected by adding the heat sources 𝑃𝑃 𝑠𝑠 and 𝑃𝑃 𝐽𝐽 , 𝑃𝑃 𝑠𝑠 is the switching power, defined as 𝑃𝑃 𝑠𝑠 (𝑆𝑆) = 𝐼𝐼 0 𝑇𝑇 𝑑𝑑 (𝑆𝑆), related to the voltage drop at node "i" calculated by electrical equation and 𝑃𝑃 𝐽𝐽 is the Joule heating term coming from the power dissipation in the PDN: [START_REF] Magnani | Electrothermal analysis Yue MA 2018 233 of carbon nanotubes power delivery networks for nanoscale integrated circuits[END_REF] 𝑃𝑃 𝐽𝐽 (𝑆𝑆) = The electro-thermal coupling problem is solved in a classical approach: firstly solving the thermal network in room temperature, secondly calculating the temperature dependent electrical resistances R(T), thirdly solving the electrical network, and then getting the voltage. After calculating the thermal heat sources, we can repeat the first 3 steps, and so on. The final temperature and voltage distributions can be obtained when the relative error gets smaller than the predefined error value.

Further investigation of the dynamic analysis can be carried out from the previous static ET analysis by adding the following two steps. The first step is calculating the dynamic elements (capacitors, inductors, etc.…) related voltage drop. The second step is checking if the new thermal distribution is still compatible with the static electro-thermal equilibrium. Thus, with a predefined impedances circuit, a frequency analysis can be then carried out by using the dynamic analysis workflow.

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3.4.4) Electro-thermal modeling of VLS circuits

3D integration gives a way to higher performance, increased functionality and heterogeneous implementation. Nevertheless, compared to 2D integration, due to the parasitic, large switching current and longer power delivery path, the power and thermal integrity issues are always the concerns for 3D integration. In this part, we provide an in-depth study of power and thermal issues of 3D integration, especially for the Through Silicon Vias (TSVs). Our study is based on a three layer's system using TSV based technologies. Based on the heat dissipation models, we present a power and thermal integrity analysis of 3-D ICs, especially TSV. key challenge of this analysis is to calculate simultaneously electrical and thermal analysis. Therefore, the temperature dependent resistivity is used in this analysis.

𝜌𝜌 = 𝜌𝜌 0 [1 + 𝛽𝛽(𝑇𝑇 𝑑𝑑𝑚𝑚𝑑𝑑𝑑𝑑𝑟𝑟𝜋𝜋𝑡𝑡𝑡𝑡𝑟𝑟𝑑𝑑 -𝑇𝑇 0 )] (3-64)
Where 𝜌𝜌 0 (1.53265e-8 Ω m) is the electrical resistivity at 𝑇𝑇 0 which is 300K and 𝛽𝛽 (0.0067) is the temperature coefficient for electrical resistivity [START_REF] Multiphysics | COMSOL multiphysics[END_REF]. The electrical resistivity of conductors goes up while temperature increases, and the power supply will be greatly influenced. Besides, the voltage drop and flowing current on the transmission line will cause Joule heating. After a sufficiently long time, the difference of temperature distribution will lead to electron-migration (EM) issues. By this method, electrical and thermal issues are coupled together.

To perform the 3-D multi-layers system for electrical analysis, we adopt Kirchhoff's law to solve the linear equations. These linear equations can be transformed together to one matrix. The matrix formulation follows the rules of modified nodal analysis (MNA) method which is often used for power grid analysis [START_REF] Magnani | Electrothermal analysis Yue MA 2018 233 of carbon nanotubes power delivery networks for nanoscale integrated circuits[END_REF] [START_REF] Todri | A study of tapered 3-D TSVs for power and thermal integrity[END_REF]. These matrices can be expressed as Laplace transform:

[𝐺𝐺 + 𝑠𝑠𝐷𝐷]𝑜𝑜(𝑠𝑠) = 𝐼𝐼(𝑠𝑠) (3-65)
Where 𝐺𝐺 is the n-by-n conductance matrix, 𝐷𝐷 is the n-by-n capacitance and inductance matrix, and 𝐼𝐼 is the n-by-1 vector of current sources and voltage sources. 𝑜𝑜(𝑠𝑠) is the n-by-1 vector that represents nodes' voltage and current. To get nodes' voltage drop and current distributions, we solve the electrical power network by inversing this matrix[𝐺𝐺 + 𝑠𝑠𝐷𝐷]. For large system analysis, we use sparse matrix and generalize conjugate residual (GCR) method [209] to ease matrix computations.

As a heat conductor from one layer to another, TSVs can sometimes be very beneficial for dissipating heat away from a hot layer but sometimes they can be harmful to neighboring layers or components. In this work, by following the principle of electrical-thermal duality [START_REF] Todri | A study of tapered 3-D TSVs for power and thermal integrity[END_REF], the heat flow passing through a thermal resistor is equivalent to the current passing through the electrical resistance and temperature difference is equivalent to voltage difference.

Heat is normally generated from the upper layers, and transferred through TSVs and other layers (for example, isolation layers) to the silicon substrate. Isolation layers have much lower thermal conductivities than that of silicon, so they act as thermal barriers. The voltage changes in the switching circuits will contribute to the heat generation. TSVs, redistribution layers, coplanar lines and heat sink are modeled as thermal resistances in order to conduct the vertical and lateral heat flows in the 3D system. Due to the difference between TSVs' vertical thermal resistances and other material layers' thermal resistances, heat dissipates at different rates. The equivalent thermal resistances are represented as the parallel connection of TSVs' resistances and other layers' thermal resistances. The temperature of heat sink is assumed to be the ambient temperature. Thanks to the principle of electrical-thermal duality, the thermal network can also be solved by using MNA method. The nodes' thermal linear equations can be merge to the following equation: Where 𝐺𝐺 𝑡𝑡ℎ is the thermal resistance matrix of size m-by-m and m is the number of nodes on the 3D system. 𝑇𝑇 𝑑𝑑𝑚𝑚𝑑𝑑 is the m-by-1 vector of temperature nodes and Q is the m-by-1 vector for heat sources.

We develop an electrical and thermal analysis flow to calculate the electro-thermal coupling effect of a 3D system. The proposed method is an iterative process and Figure 92 shows the electrical and thermal analysis flow. Electrical analysis is a transient analysis, the voltage drop on the metal tracks will result in an elevation of temperatures. The increase in temperature is then treated as a thermal source and applied to the thermal analysis step. Thermal analysis provides temperature distribution for the different layers and TSVs, where altered temperatures will change conductors' resistivity and then influence electrical analysis. The iterative calculation of resistivity and temperature will converge when there are no more changes on voltage drop and temperature distribution. Here, the thermal analysis is a steady state analysis which captures the temperature distribution from a given electrical network. This method is limited to capture the dynamic thermal distribution. However, as fast and accurate capturing of temperature distribution is always our purpose. The 1D static thermal analysis is a viable approach. We adopt the modified nodal analysis as described in the previous to perform efficient electrical and thermal networks analysis. package and outside the package, a heatsink is used. The chip's size is 10mmΧ10mm, the silicon layer's thickness is 50μm, the coating layer and insulation layer have respectively a thickness of 2µm and 8.8µm. TSV's surface ratio r is fixed to 0.01.

The electrical circuit and thermal circuit are shown in Figure 93(a) (c). We input a pulse signal (defined as previous part), and parallel a 50 ohm's resistance at the input and output, and a 150fF capacitance at output in order to see the output signal. Here, the resistance of TSV is about 0.0052e-4 ohm, so in compare with 50 ohm, the TSV resistance is too small. So the parallel circuit's effective resistance depends on the TSV resistance (frequency dependent straight wire formula (2-57) and (2-58)), and the parallel connection of 50ohm resistance will not change the output signal. The current will change to heat when passing by the resistance of TSV. And the generated heat is dissipated in the 3D geometry. The thermal path is composed of TSV conduction and the other 3 layers' serial heat conduction, the heat pass separately by the series of 3 layers and also by the TSV (because of the copper's nice heat conductivity). And then the heat is collected in the package level, and conducted through the package to the heatsink. The package and heatsink have also their own effective heat conductivities, especially for the heatsink, it has a very high heat conductivity and so a very low thermal resistance. And the ambient temperature is about 300K. As shown is the following Figure 94, the S parameter is calculated by using ADS simulator. Figure 95 shows the 2.5GHz's signal transmisison effects. Figure 95 (a) shows the comparison of input and output signal. Figure 95 (b) shows respectively the top of coating layer, the bottom of TSV and the bottom side of packaging's temperature. Figure 95 (c) shows the voltage transmission change when considering electro-thermal coupling effects between ADS (without Electro-thermal consideration), MNA method (with Electro-thermal consideration) and MNA (without Electrothermal consideration). Figure 95 (d) is the output voltage error without considering electrothermal effect. As we can see from the result of 2.5GHz study, the output signal has almost the same waveform than the input signal, the temperature change in the circuit is 0K. The ADS simulated result has a good fit with our simulator, and after considering the electro-thermal effect, the maximum output change is 0.2%, which can be neglected.

The output voltage error Err can be defined as From the above results, the one TSV model does not have electro-thermal effect at very low working frequency. For some period of frequencies, the output frequency increase linearly, and it will generate a lot of heat and increase the via's temperature. Therefore, we find out that the electrothermal effect has a relationship with the trend of S parameters. The S parameters stay stable at low frequency and very high frequency, but for a band of frequency, it changes dramatically. We can superpose the S parameters with the error curves and maximum temperature curve. The As we imagined, the S parameters have really a good tendency with the electro-thermal effects. Strong electro-thermal effects appear while S parameters change. The only difference between this model and previous model is the substrate. In the previous model, the substrate is treated directly as a ground node. But in this model, the substrate is highly doped. It is treated as a conductor with a very low resistivity (1e-4 ohm•m). The substrate is expressed as a RC parallel model. The substrate resistance and capacitance can be expressed by the following equations [START_REF] Kim | Highfrequency scalable modeling and analysis of a differential signal through-silicon via[END_REF]

𝐷𝐷 𝑇𝑇𝑖𝑖_𝑠𝑠𝑡𝑡𝜋𝜋 = 𝜋𝜋×𝜀𝜀 0 𝜀𝜀 𝑟𝑟,𝑠𝑠𝑠𝑠 𝑙𝑙𝑜𝑜𝑠𝑠ℎ -1 ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) × ℎ 𝑇𝑇𝑇𝑇𝑇𝑇 [𝐹𝐹]
(3-68)

𝐺𝐺 𝑇𝑇𝑖𝑖_𝑠𝑠𝑡𝑡𝜋𝜋 = 𝜋𝜋×𝜋𝜋 𝑠𝑠𝑠𝑠 𝑙𝑙𝑜𝑜𝑠𝑠ℎ -1 ( 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 𝑑𝑑 𝑇𝑇𝑇𝑇𝑇𝑇 ) × ℎ 𝑇𝑇𝑇𝑇𝑇𝑇 [𝑇𝑇] (3-69)
Figure 98 shows the results. These two figures show that by adding a highly doped substrate, we can reduce the electro-thermal effect, especially in the band of frequency where S parameters change heavily. And the maximum temperature has been reduced to 5e-4K, which is about 3 times less than the one TSV model, and maximum error has been reduced to a half, about 1.5e-5%. Thus, by adding a highly doped substrate, the electro-thermal heating effect can be effectively reduced. From the above Figure 99, we can see that, the error curve and maximum temperature curve have always the same tendency. They keep stable at low frequency. Once the S parameters change, the two curves change dramatically. Even though we have studies the electro-thermal modeling until 10THz, due to the non-linear system, from 20GHz to 10THz, we should use full wave models for electrical study. But at least, it works for the frequencies less than 15GHz, sufficient for our industrial collaborator, for the next generation of mobile sample, for instance. Here, we will not speak on quantic interference of temperature, for nano devices. And this analysis method will be useful in analyze of thermo-mechanical effect, which will be introduced in the chapter 5.

3.5) Conclusion

In this work, 3D IC analytical models and electrical-thermal analysis technique, for substrate, thermal connections (3D via) and system level 3D PDN, are introduced and used to explore power and thermal integrity issues in 3D integration. The 3D IC analytical models consider also the electro-thermal effects of TSV parasitic. We provide an extensive study of power and thermal dissipation issues in 3D integration considering several aspects such as:

• Single and multi-layer auto-heating effects on 3D power and thermal dissipation; First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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• TSVs and substrate impact on power and thermal integrity and their design implications;

• Heat sink's thermal conductivity's influence to the electro-thermal effects.

We combine switching frequency and electro-thermal effects together. And by comparing with S parameters, we found out that the electro-thermal effects appear only when S parameters change, and the reduction of thermal resistance and the increase of doping concentration of substrate will restrain the electro-thermal signal integrity problem.

In fact, we can use more layers, then with lower thicknesses. Here, we did not consider the temperature-dependent material characteristics' change or we can also say that the temperature is fixed low, so the change of the material's characteristics is weak. Here, we just give a solution for each uniform layer and low temperature design.

In our study, we adopt linear model; we mean that the global effects of substrate and connections can be split. But, if the connections become very important, we cannot dissociate substrate with TSV, RDL, etc. Intercorrelation terms do intervene; the system can be approached by non-linear models. Moreover, our extractor (3D-TLE) is now efficient, although some models are, by now, roughly simple. But, the industry wants simple compact models, and then, we should keep the simplicity, by considering, as well as possible, the in-depth physics.

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Chapter 4: Heat pipe Simulation

Advances in the computational performance of electronic devices have created an urgent need for improved methods of passive thermal management, particularly in 3D systems. This has led to renewed interest in the use of vapor chambers as heat spreaders in applications ranging from mobile devices to high-performance-computing and power electronics systems. While detailed numerical models of vapor chamber operation have been developed, an easy modeling with low computational cost method has also been implemented for parametric study and quick assessment of vapor chamber performance in system-level models. [START_REF] Van Olmen | 3D stacked IC demonstration using a through silicon via first approach[END_REF], [START_REF] Pedram | Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods[END_REF], [START_REF] Zheng | Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits[END_REF], [207]- [START_REF] Lacroix | Caracterisation du transport fluidique et thermique dans les mousses metalliques capillaires en cuivre Characterization of fluid and thermal transport in copper metal foam wicks[END_REF], [START_REF] Longtin | A One-Dimensional Model of a Micro Heat Pipe During Steady-State Operation[END_REF]- [START_REF] Yadavalli | Flat heat pipe performance thresholds at ultra-thin form factors[END_REF], [START_REF] Yadavalli | Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-thin Form Factors[END_REF]- [START_REF] Faghri | Review and Advances in Heat Pipe Science and Technology[END_REF]

4.1) Introduction

Micro/nano flat heat pipes (FHP) are an effective passive heat transfer technology for high heat flux electronic devices, especially CPU, MPU. Because of the high thermal conductivity, reliability and low weight penalty, they are treated as a very proficient high power cooling system. A FHP is an enclosed vapor chamber whose inner and outer surface is covered respectively with porous medium and thermal conductive materials. Heat sources and heat sinks are located on the outer surface of FHP, with the rest parts thermally insulated. The fluid in the wick is evaporated by the heat sources, the generated vapor increases locally the pressure, and the pressure difference pushes vapor from the evaporator to the condenser, where the vapor is condensed and changes to fluid in the wick. Once again, the condensed liquid increases the local pressure in the wick, and the pressure difference in the wick pumps the liquid back to the evaporation side. This phase-change circulation of FHP will continue until the heat sources disappear or capillary pressure cannot be offered by liquid [START_REF] Faghri | Heat Pipe Science and Technology[END_REF]. For the working fluid, water, acetone, ethanol or methanol are more commonly used in the electronic devices. [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF], [START_REF] Yadavalli | Flat heat pipe performance thresholds at ultra-thin form factors[END_REF], [START_REF] Zuo | A network thermodynamic analysis of the heat pipe[END_REF], [START_REF] Faghri | Review and Advances in Heat Pipe Science and Technology[END_REF], [START_REF] Luo | A novel flat micro heat pipe with a patterned glass cover[END_REF], [START_REF] Faghri | Heat Pipe Science and Technology[END_REF], [START_REF] Hopkins | Flat Miniature Heat Pipes With Micro Capillary Grooves[END_REF], [START_REF] Lin | High performance miniature heat pipe[END_REF], [START_REF] Carey | Liquid-vapor phase-change phenomena[END_REF], [START_REF] Soni | Performance analysis of bulk driven MOSFET and CNFET for low voltage applications[END_REF] Researches on FHP have been conducted to characterize the cooling performances of micro heat pipes. For pre-study the thermal performance of heat pipes, many researchers have suggested simplified 1D theoretical models [START_REF] Van Olmen | 3D stacked IC demonstration using a through silicon via first approach[END_REF], [START_REF] Shiraz | Analytical and Numerical Modeling of Flat Heat Pipes[END_REF], [START_REF] Luo | A novel flat micro heat pipe with a patterned glass cover[END_REF], [START_REF] Marek | Analysis of the evaporation coefficient and the condensation coefficient of water[END_REF], [START_REF] Oh | TSVs embedded in a microfluidic heat sink: High-frequency characterization and thermal modeling[END_REF], however, the simplified 1D model is no longer accurate for the extra-thin FHP.

In the current work, a computational low-cost FHP model is developed, targeting the geometries and operating conditions. The model considers mass flow, momentum changes, and energy transport in the vapor chamber, wall, and wick, as well as phase change at the wick-vapor interface. [START_REF] Patankar | A Time-Stepping Analytical Model for 3D Transient Vapor Chamber Transport[END_REF] The studied configurations of flat heat pipes are shown in Figure 100. Figure 100 a,b,c presents respectively the configurations of flat heat pipes with a single heat source, multiple heat sources, and a heat source on one side and a heat sink on the other side. All the studies are based on the

4.2) Configuration I & II 2D simulation 4.2.1) 2D heat pipe Analytical solution

• Thermal Conduction in wall [START_REF] Lips | A general analytical model for the design of conventional heat pipes[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits The dimensionless 2D steady-state heat conduction equation in the wall can be written as:

𝜕𝜕 2 𝜃𝜃 𝜕𝜕𝑋𝑋 2 + 1 𝑇𝑇 𝑤𝑤 2 𝜕𝜕 2 𝜃𝜃 𝜕𝜕𝑌𝑌 2 = 0 (4-3)
The boundary condition at the boundary (X=0 and X=1) are

𝜕𝜕𝜃𝜃 𝜕𝜕𝑋𝑋 = 0 (4-4)
At the wick/wall interface (Y=0), the thermal boundary condition can be determined by assuming linear temperature profile and constant saturation temperature at the liquid-vapor interface. The boundary condition can be written as

𝜕𝜕𝜃𝜃 𝜕𝜕𝑌𝑌 = 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 𝑇𝑇 𝑤𝑤 𝑘𝑘 𝑤𝑤 𝑇𝑇 𝑡𝑡 𝜃𝜃 (4-5)
The boundary condition at the outer wall (Y=0) are constant heat fluxes in the evaporators and the condenser, which can be located at different locations on the heat pipe, and a heat flux equal to zero in the adiabatic sections (the rest of the surface). This is shown as:

𝜕𝜕𝜃𝜃 𝜕𝜕𝑌𝑌 = � 1 𝑑𝑑𝑡𝑡𝑎𝑎𝑑𝑑𝑜𝑜𝑟𝑟𝑎𝑎𝑡𝑡𝑜𝑜𝑟𝑟 0 𝑎𝑎𝑑𝑑𝑆𝑆𝑎𝑎𝑏𝑏𝑎𝑎𝑡𝑡𝑆𝑆𝑐𝑐 -𝛾𝛾 𝑐𝑐𝑜𝑜𝑛𝑛𝑑𝑑𝑑𝑑𝑛𝑛𝑠𝑠𝑑𝑑𝑟𝑟 (4-6)
The non-dimensional temperature for configurations I and II can be expressed by an infinite Fourier series as:

𝜃𝜃(𝑋𝑋, 𝑌𝑌) = ∑ 𝐴𝐴 𝑚𝑚 (𝑌𝑌)cos (𝑚𝑚𝜋𝜋𝑋𝑋) ∞ 𝑚𝑚=1 (4-7)
The non-dimensional input heat flux depends on the location of heat sources and sinks, and can be written as follows:

𝜕𝜕𝜃𝜃 𝜕𝜕𝑌𝑌 = ∑ 𝐹𝐹 𝑚𝑚 cos (𝑚𝑚𝜋𝜋𝑋𝑋) ∞ 𝑚𝑚=1 (4-8)
where

𝐹𝐹 𝑚𝑚 = 2 𝑚𝑚𝜋𝜋 {sin(𝑚𝑚𝜋𝜋𝜔𝜔 2𝑑𝑑 ) -sin(𝑚𝑚𝜋𝜋𝜔𝜔 1𝑑𝑑 ) + sin(𝑚𝑚𝜋𝜋𝜔𝜔 4𝑑𝑑 ) -sin(𝑚𝑚𝜋𝜋𝜔𝜔 3𝑑𝑑 ) + sin(𝑚𝑚𝜋𝜋𝜔𝜔 6𝑑𝑑 ) - sin(𝑚𝑚𝜋𝜋𝜔𝜔 5𝑑𝑑 ) + sin(𝑚𝑚𝜋𝜋𝜔𝜔 8𝑑𝑑 ) -sin(𝑚𝑚𝜋𝜋𝜔𝜔 7𝑑𝑑 ) -𝛾𝛾[sin(𝑚𝑚𝜋𝜋𝜔𝜔 2𝑙𝑙 ) -sin (𝑚𝑚𝜋𝜋𝜔𝜔 1𝑙𝑙 )]} (4-9)
In which 𝜔𝜔 1𝑑𝑑 , 𝜔𝜔 2𝑑𝑑 , 𝜔𝜔 3𝑑𝑑 , 𝜔𝜔 4𝑑𝑑 , 𝜔𝜔 5𝑑𝑑 , 𝜔𝜔 6𝑑𝑑 , 𝜔𝜔 7𝑑𝑑 , 𝜔𝜔 8𝑑𝑑 , 𝜔𝜔 1𝑙𝑙 𝑎𝑎𝑛𝑛𝑑𝑑 𝜔𝜔 2𝑙𝑙 express the locations of the heat sources and heat sink. • Vapor flow [START_REF] Lips | A general analytical model for the design of conventional heat pipes[END_REF] A parabolic velocity profile is used for vapor flow within the heat pipe. The vapor velocity The velocity distribution is represented by a product in the x and y directions:

𝑠𝑠 𝑣𝑣 (𝑜𝑜, 𝑦𝑦) = -6𝑈𝑈 𝑣𝑣 (𝑜𝑜)[� ℎ 𝑡𝑡 ℎ 𝑣𝑣 � 2 + ℎ 𝑡𝑡 ℎ 𝑣𝑣 + �1 + 2 ℎ 𝑡𝑡 ℎ 𝑣𝑣 � � 𝜕𝜕 ℎ 𝑣𝑣 � + ( 𝜕𝜕 ℎ 𝑣𝑣 ) 2 ] (4-11)
Where 𝑈𝑈 𝑣𝑣 (𝑜𝑜) is the local mean velocity along the x direction.

The continuity equation for the two-dimensional incompressible vapor flow can be integrated with respect to y to determine 𝑈𝑈 𝑣𝑣 (𝑜𝑜)

∫ ( 𝜕𝜕𝑡𝑡 𝑣𝑣 𝜕𝜕𝑜𝑜 + 𝜕𝜕𝑣𝑣 𝑣𝑣 𝜕𝜕𝜕𝜕 )𝑑𝑑𝑦𝑦 -ℎ 𝑡𝑡 -(ℎ 𝑡𝑡 +ℎ 𝑣𝑣 ) = ∫ 𝜕𝜕𝑡𝑡 𝑣𝑣 𝜕𝜕𝑜𝑜 𝑑𝑑𝑦𝑦 -ℎ 𝑡𝑡 -(ℎ 𝑡𝑡 +ℎ 𝑣𝑣 ) + 𝑡𝑡 𝑣𝑣,𝐼𝐼 (-ℎ 𝜌𝜌 ) -𝑡𝑡 𝑣𝑣 (-(ℎ 𝜌𝜌 + ℎ 𝑣𝑣 )) (4-12)
Where 𝑡𝑡 𝑣𝑣,𝐼𝐼 represents the vapor interfacial velocity. The heat flux normal to the liquid-vapor interface, 𝑞𝑞 𝐼𝐼 can be calculated from the conduction model with the assumption of linear temperature profile across the wick: Integrating (4-14) with respect to x and using the boundary condition at the beginning of the evaporator 𝑠𝑠 𝑣𝑣 = 0, will result in an expression for 𝑈𝑈 𝑣𝑣 (𝑜𝑜):

𝑈𝑈 𝑣𝑣 (𝑜𝑜) = 𝑞𝑞 𝑑𝑑 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑣𝑣 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 ℎ 𝑡𝑡 ∑ ( 𝜌𝜌 𝑚𝑚𝜋𝜋 )𝐴𝐴 𝑚𝑚 (0)sin ( 𝑚𝑚𝜋𝜋𝑜𝑜 𝜌𝜌 ) ∞ 𝑚𝑚=1 (4-15)
Therefore, the quasi-two-dimensional velocity profile is:

𝑠𝑠 𝑣𝑣 (𝑜𝑜, 𝑦𝑦) = -6𝑞𝑞 𝑑𝑑 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑣𝑣 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 ℎ 𝑡𝑡 ∑ � 𝜌𝜌 𝑚𝑚𝜋𝜋 � 𝐴𝐴 𝑚𝑚 (0) sin � 𝑚𝑚𝜋𝜋𝑜𝑜 𝜌𝜌 � ∞ 𝑚𝑚=1 × [� ℎ 𝑡𝑡 ℎ 𝑣𝑣 � 2 + ℎ 𝑡𝑡 ℎ 𝑣𝑣 + �1 + 2 ℎ 𝑡𝑡 ℎ 𝑣𝑣 � � 𝜕𝜕 ℎ 𝑣𝑣 � + � 𝜕𝜕 ℎ 𝑣𝑣 � 2 ] (4-16)
The boundary layer form of the x direction momentum equation for steady-state incompressible laminar vapor flow can be integrated to obtain the vapor pressure distribution:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Assuming the constant vapor pressure at each cross-section, and utilizing the boundary conditions at the beginning of the evaporator, 𝑠𝑠 𝑣𝑣 = 0 and 𝑑𝑑 𝑣𝑣 = 𝑑𝑑 𝑟𝑟𝑑𝑑𝜋𝜋 yields

𝑑𝑑 𝑣𝑣 = 𝑑𝑑 𝑟𝑟𝑑𝑑𝜋𝜋 + 𝑞𝑞 𝑑𝑑 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑣𝑣 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 ℎ 𝑡𝑡 ℎ 𝑣𝑣 3 ∑ 𝐴𝐴 𝑚𝑚 (0) �cos � 𝑚𝑚𝜋𝜋𝑜𝑜 𝜌𝜌 � -1� + 18𝜌𝜌 𝑣𝑣 𝑈𝑈 𝑣𝑣 2 [ 1 5 � ℎ 𝑡𝑡 ℎ 𝑣𝑣 � 5 + 1 30 ] ∞ 𝑚𝑚=1 (4-18)
Where 𝑈𝑈 𝑣𝑣 is obtained from (4-15).

The temperature drop in the vapor can be related to the pressure drop in the vapor region by applying the Clausius-Clapeyron equation and using the ideal gas law:

𝑇𝑇 𝑣𝑣 = 1 1 𝑇𝑇 𝑟𝑟𝑑𝑑𝑓𝑓 - 𝑅𝑅 ℎ 𝑓𝑓𝑔𝑔 log ( 𝑑𝑑 𝑣𝑣 𝑑𝑑 𝑟𝑟𝑑𝑑𝑓𝑓 ) (4-19)
Where R is the ideal gas constant, ℎ 𝜋𝜋𝑙𝑙 is the latent heat, and 𝑑𝑑 𝑣𝑣 is the pressure drop obtained from (4-18).

• Liquid flow [START_REF] Lips | A general analytical model for the design of conventional heat pipes[END_REF] The continuity equation for the incompressible liquid flow can be integrated with respect to y to obtain the liquid axial velocity 𝑠𝑠 𝜌𝜌 (𝑜𝑜):

∫ ( 𝜕𝜕𝑡𝑡 𝑣𝑣 𝜕𝜕𝑜𝑜 + 𝜕𝜕𝑣𝑣 𝑣𝑣 𝜕𝜕𝜕𝜕 )𝑑𝑑𝑦𝑦 0 -ℎ 𝑡𝑡 = -𝑡𝑡 𝜌𝜌,𝐼𝐼 (-ℎ 𝜌𝜌 ) -ℎ 𝜌𝜌 𝑑𝑑𝑡𝑡 𝑡𝑡 𝑑𝑑𝑜𝑜 (4-20)
where 𝑡𝑡 𝜌𝜌,𝐼𝐼 represents the interfacial velocity (normal to the liquid vapor interface) for the liquid and is related to the vapor interfacial velocity by:

𝜌𝜌 𝜌𝜌 𝑡𝑡 𝜌𝜌,𝐼𝐼 = 𝜌𝜌 𝑣𝑣 𝑡𝑡 𝑣𝑣,𝐼𝐼 (4-21)
The axial liquid velocity can be calculated by integrating (4-20) with respect to x using the velocity boundary condition at the beginning of the evaporator (x = 0), 𝑠𝑠 𝜌𝜌 = 0:

𝑠𝑠 𝜌𝜌 (𝑜𝑜) = 𝑞𝑞 𝑑𝑑 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑣𝑣 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 ℎ 𝑡𝑡 2 ∑ � 𝜌𝜌 𝑚𝑚𝜋𝜋 � 𝐴𝐴 𝑚𝑚 (0) sin � 𝑚𝑚𝜋𝜋𝑜𝑜 𝜌𝜌 � ∞ 𝑚𝑚=1 (4-22)
The one-dimensional steady-state conservation of momentum for incompressible liquid flow in the wick can be expressed by Darcy's law, assuming negligible inertial effects in comparison to viscous losses, as:

𝑑𝑑𝑑𝑑 𝑡𝑡 𝑑𝑑𝑜𝑜 = - 𝜇𝜇 𝑡𝑡 𝑡𝑡 𝑡𝑡 𝐾𝐾 (4-23)
In which the permeability K is calculated for a mesh screen as: The liquid pressure is obtained by integrating (4-24) and utilizing the pressure boundary condition at the end of the condenser (x=l), 𝑑𝑑 𝜌𝜌 = 𝑑𝑑 𝑣𝑣 :

𝑑𝑑 𝜌𝜌 = 𝑞𝑞 𝑑𝑑 𝜇𝜇 𝑡𝑡 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑡𝑡 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 𝐾𝐾ℎ 𝑡𝑡 2 ∑ ( 𝜌𝜌 𝑚𝑚𝜋𝜋 ) 2 𝐴𝐴 𝑚𝑚 (0) �cos � 𝑚𝑚𝜋𝜋𝑜𝑜 𝜌𝜌 � -cos (𝑚𝑚𝜋𝜋)� + 𝑑𝑑 𝑟𝑟𝑑𝑑𝜋𝜋 + ∞ 𝑚𝑚=1 𝑞𝑞 𝑑𝑑 12𝜇𝜇 𝑣𝑣 𝑘𝑘 𝑑𝑑𝑓𝑓𝑓𝑓 ℎ 𝑤𝑤 𝜌𝜌 𝑣𝑣 ℎ 𝑓𝑓𝑔𝑔 𝑘𝑘 𝑤𝑤 ℎ 𝑣𝑣 3 ℎ 𝑡𝑡 ∑ ( 𝜌𝜌 𝑚𝑚𝜋𝜋 ) 2 𝐴𝐴 𝑚𝑚 (0)[cos(𝑚𝑚𝜋𝜋) -1] ∞ 𝑚𝑚=1
(4-26)

• Capillary pressure [START_REF] Lips | A general analytical model for the design of conventional heat pipes[END_REF] 𝑑𝑑 𝑙𝑙𝜋𝜋𝑑𝑑 = 𝑑𝑑 𝑣𝑣 -𝑑𝑑 𝜌𝜌 (4-27)

4.2.2) FEM simulation[141]

The numerical model employed here is adopted from [START_REF] Vadakkan | Transient Analysis of Flat Heat Pipes[END_REF]. In summary, the continuity, momentum, and energy equations are solved in the wall, wick, and vapor regions of the FHP. Evaporation and condensation at the interface follow a kinetic theory-based formulation that depends on the interface temperature calculated from a local energy balance. The vapor density is calculated from the vapor pressure and local temperature using the ideal gas law; the liquid mass is adjusted to conserve mass. All other properties are fixed to be constant. [START_REF] Cnrs | COMSOL simulation of heat pipe[END_REF] The liquid and vapor flow are considered to be laminar and incompressible. The continuity equation is as follows:

φ 𝜕𝜕𝜌𝜌 𝜕𝜕𝑡𝑡 + 𝜌𝜌∇ • �𝑇𝑇 �⃗ � = 0(𝑆𝑆𝑛𝑛 𝑠𝑠𝑡𝑡𝑎𝑎𝑡𝑡𝑆𝑆𝑜𝑜𝑛𝑛𝑎𝑎𝑟𝑟𝑦𝑦, 𝑛𝑛𝑜𝑜 𝑡𝑡𝑆𝑆𝑚𝑚𝑑𝑑 𝑡𝑡𝑑𝑑𝑟𝑟𝑚𝑚) (4-28)
The term ∂ρ/ ∂t accounts for the increase or reduction of mass in the fluid. The momentum equations with a Brinkman-Forchheimer extended Darcy model for fluid flow in the wick region and the vapor core are: In the vapor core, permeability k = ∞ and porosity φ = 1.

1 𝜀𝜀 𝑑𝑑 𝜌𝜌 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝑡𝑡 + 1 𝜀𝜀 𝑑𝑑 ρ�𝑇𝑇 �⃗ • ∇�𝑇𝑇 �⃗ 1 𝜀𝜀 𝑑𝑑 = ∇ • �-𝑑𝑑𝐼𝐼 + 𝜇𝜇 1 𝜀𝜀 𝑑𝑑 �∇𝑇𝑇 �⃗ + �∇𝑇𝑇 �⃗ � 𝑇𝑇 �� -�𝜇𝜇𝑘𝑘 -1 + 𝛽𝛽 𝐹𝐹 �𝑇𝑇 �⃗ �� • 𝑇𝑇 ����⃗ (4-
The energy equation in the wall, wick and vapor core is The mass flux rate due to phase change at the wick/vapor interface is evaluated using the difference between the local interface temperature and the local vapor-core saturation temperature [START_REF] Vadakkan | Transient Analysis of Flat Heat Pipes[END_REF] as:

𝑚𝑚̇′ ′ = 2𝜋𝜋 2-𝜋𝜋 ℎ 𝑓𝑓𝑔𝑔 𝜌𝜌 𝑣𝑣 𝑇𝑇 𝑣𝑣 1.5 � 𝑀𝑀𝑙𝑙 2𝜋𝜋𝑅𝑅 𝑐𝑐𝑜𝑜𝑛𝑛𝑠𝑠𝑚𝑚 � 0.5 (𝑇𝑇 𝑖𝑖𝑙𝑙𝑡𝑡 -𝑇𝑇 𝑠𝑠𝜋𝜋𝑡𝑡 ) (4-32)
𝑚𝑚̇′ ′ > 0 for the evaporation part and contrary for the condenser part.

A positive value indicates evaporation, while a negative value indicates condensation. The value of 𝜎𝜎 is chosen to be 0.03 [START_REF] Marek | Analysis of the evaporation coefficient and the condensation coefficient of water[END_REF]. The saturation temperature in the vapor core is computed using the Clausius-Clapeyron equation. The boundary conditions for the vapor core specify that there is no slip in velocity at the thermally insulated lateral sidewalls.

𝑎𝑎𝑡𝑡 𝑜𝑜 = 0, 𝑠𝑠 = 𝑡𝑡 = 0; At the lateral and bottom face of the wall, a thermal insulation is set.

𝑠𝑠 = 𝑡𝑡 = 0; 𝜕𝜕𝑇𝑇 𝜕𝜕𝑜𝑜 = 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 = 0 (4-39)
At wick-vapor interface

𝑠𝑠 = 𝑡𝑡 = 0; 𝑞𝑞 𝑑𝑑𝑣𝑣𝜋𝜋𝑑𝑑 = 𝑚𝑚̇′ ′ • ℎ 𝜋𝜋𝑙𝑙 (4-40) (𝜌𝜌𝐷𝐷 𝑑𝑑 V � �⃗ ) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 • ∇𝑇𝑇 + ∇ • (𝑘𝑘 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 ∇𝑇𝑇) = -𝑞𝑞 𝑑𝑑𝑣𝑣𝜋𝜋𝑑𝑑 + 𝑄𝑄 𝑣𝑣𝑑𝑑 (4-41) (𝜌𝜌𝐷𝐷 𝑑𝑑 V � �⃗ ) 𝑣𝑣 • ∇𝑇𝑇 + ∇ • (𝑘𝑘 𝑣𝑣 ∇𝑇𝑇) = 𝑞𝑞 𝑑𝑑𝑣𝑣𝜋𝜋𝑑𝑑 + 𝑄𝑄 𝑣𝑣𝑑𝑑 (4-42)
At the upper wall: The evaporator section has a constant heat flux condition The thermal setting can be shown as Figure 102.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 124 At the lateral face of the vapor core, a symmetry is set

u = v = 0; K � �⃗ -�K � �⃗ • n �⃗� • n �⃗ = 0, K � �⃗ = [𝜇𝜇(∇u �⃗ + (∇u �⃗) 𝑇𝑇 )]n �⃗ (4-47)
The phase change at the wick and vapor interface is connected at the boundary at x and y limits by adding the following boundary conditions.

𝑎𝑎𝑡𝑡 𝑜𝑜 = 𝜔𝜔 𝑜𝑜 -𝑑𝑑_𝑤𝑤𝑎𝑎𝑙𝑙𝑙𝑙; 𝑃𝑃 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 = 𝑃𝑃 𝑣𝑣 (4-48)
And the vapor is always treated as an ideal gas, so we have the following relationship:

𝜌𝜌 𝑣𝑣 = 𝑃𝑃 𝑜𝑜𝑑𝑑 •𝑀𝑀 𝑛𝑛 𝑅𝑅_𝑙𝑙𝑜𝑜𝑙𝑙𝑠𝑠𝑡𝑡•𝑇𝑇 (4-49)
To improve the stability of the model, and account for the coupling of interface mass flow with temperature, the mass flow rate is linearized with respect to temperature. To prevent round-off errors in the computation of pressure gradients from pressure differences that are small compared with the absolute pressure, the pressure is split into two components: 1) a system operating pressure and 2) a hydrodynamic component. These implementation details are discussed further in [START_REF] Vadakkan | Transient Analysis of Flat Heat Pipes[END_REF] and [START_REF] Vadakkan | Transport in Flat Heat Pipes at High Heat Fluxes From Multiple Discrete Sources[END_REF].

The governing equations are discretized using the finite-element method and solved with the commercial solver COMSOL [START_REF] Software | User-Driven COMSOL Software Updates Now Available in Version 5.2a[END_REF]. The maximum element mesh size of the wick is set to d_wick/16, and the vapor core is set to d_vapor/16, and the maximum and minimum mesh size of the rest of the model is set to 1.48mm and 5um. In this case, steady state is considered to be achieved when the heat transfer rate in the condenser section reaches within 0.1% of the value at the evaporator section. The solution at each time step is considered converged when the residuals are less than 0.0001 times of the equation's normal value for the continuity, momentum equations and energy equation. And the maximum number of iterations is set to 150.

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4.2.3) Results and discussion

The schematic diagram of the simulated geometries is shown in the Figure 100.

The properties of the working fluid, copper and porous wick materials used in the vapor core chamber simulations are shown in the following Table 14. Vapor properties are shown at temperature of 40degC. The temperature fields predicted by the modeling approaches are shown in Figure 103. Figure 103(a) shows the temperature profile comparison along the x direction of 50W heat source between FEM model (COMSOL Multiphysics) and publication of Maziar Agnvami [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF] and the error between them, while Figure 103 (b) shows the COMSOL simulated temperature profile with 30W, 40W and 50W heat source. The temperature profile has a maximum temperature at the evaporation side in the top surface and a minimum temperature at the condenser side. The plots reveal a highaccuracy match between COMSOL and theoretical solution. The maximum error is about 6% for configuration I and 0.075% for configuration II. From Figure 103 (b) &(d) we can see that by increasing 10W at the heat source, the temperature gains about 3K for configuration I, and 4K for configuration II. As we can see in the Figure 104, the vapor has a maximum velocity at the vapor core center and reduce to 0 when it attaches the wall. And for the COMSOL model, the maximum velocity is about 7 m/s, that's almost the same like the velocities of paper [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF]. For configuration I, there is about 20% difference between analytical solution and COMSOL one, especially for the analytical solution, the velocity of configuration I has a non-symmetry form. But for configuration II, the difference in velocity is less than 4%. And by increasing 10W of the heat source, the velocity gains about 1.5 m/s for configuration I and 6 m/s for configuration II.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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And finally, the most important part of the heat pipe is the capillary pressure in the vapor/wick interface. Figure 105 shows the capillary pressure at the wick/vapor interface. At the evaporation side, the water is evaporated and the vapor has a maximum pressure gain at this side, but at the condenser side, the water is condensed and causes the water liquid's flow in the wick, so we can see a contrary process in the wick flow, the wick has a mass flow in at the condensation side, and has a mass flow out at the evaporation side, so the water flow from the condensation side to the evaporation side, but with a velocity much slower than the vapor core. And from Figure 105, we can see that the capillary pressures of configuration I of FEM simulation and publication [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF] have at maximum 20% difference. But for configuration II, the capillary pressures are almost the same. And the error is less than 0.5%. A stationary model for vapor chamber operation was developed that allows for multiple, arbitrarily shaped, heat inputs on the evaporator-side face; the model predicts 2D fields of temperature, pressure, and velocity in the vapor chamber, subject to assumptions regarding the vapor chamber size, liquid and vapor flow, and the material properties. The governing mass, momentum, and energy equations in the wall, wick, and vapor core domains were established. The model is compared with a numerical model [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF].

4.3) Configuration III 3D simulation 4.3.1) Effective thermal resistances for 3D flat heat pipes

The purpose of the simulation of heat pipe is to get the total effective thermal conductivity. Before study the configuration III, a first homogeneous 3D heat pipe should be studied. The studied flat heat pipe is heated on one side and cooled on the other side. The geometry of the model is shown as following. The properties of the working fluid, copper and porous wick materials used in the vapor core chamber simulations are shown in the upper table. Vapor properties are shown at temperature of 300K. The heat pipe is heated at the whole bottom face, and cooled at the whole top face. The heating power is set to 1W.

We simulate respectively the 1D, 2D and 3D heat transfer process in COMSOL, and compare the results with the first order heat thermal resistance method. Due to the symmetry in the x and y directions of the flat heat pipe, the thermal path can be expressed along the Z direction. The heat flow from the wall to wick, and the heat is evaporated at the wick/vapor interface, the evaporated heat is equal to qevap, and then at the other side of vapor chamber, the vapor is condensed and the heat is transferred from vapor to wick, and finally the heat flow to the wall and condensed by the air convection. As we can see from Figure 107, R1 to R6 are the relative thermal resistance during the heat flow process.

𝑅𝑅 1 = 𝑅𝑅 6 = 𝑑𝑑 𝑤𝑤𝑎𝑎𝑡𝑡𝑡𝑡 𝑘𝑘 𝑐𝑐𝑜𝑜𝑑𝑑𝑑𝑑𝑑𝑑𝑟𝑟 (4-50) 𝑅𝑅 2 = 𝑅𝑅 5 = 𝑑𝑑 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘 𝑘𝑘 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘 (4-51) 𝑅𝑅 3 = 𝑅𝑅 4 = 𝑑𝑑𝑑𝑑𝜌𝜌𝑡𝑡𝜋𝜋𝑇𝑇 𝑞𝑞 𝑑𝑑𝑣𝑣𝑎𝑎𝑑𝑑 = 1 ℎ 𝑓𝑓𝑔𝑔 * 2𝜎𝜎 2-𝜎𝜎 ℎ 𝑓𝑓𝑔𝑔 𝜌𝜌 𝑣𝑣 𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 1.5 � 𝑀𝑀𝑛𝑛 2𝜋𝜋𝑅𝑅 𝑐𝑐𝑜𝑜𝑛𝑛𝑠𝑠𝑚𝑚 � 0.5 (4-52)
By using these thermal resistances, we can get the 1D analytical heat pipe model.

We also simulate a 1D, 2D and 3D model in FEM commercial software, the geometries are shown as following. Figure 109 shows a comparison of the temperature variations of the 1D, 2D, 3D COMSOL model and the 1D analytical model. At the wall and wick, the thermal resistances are the same for the COMSOL and analytical one, but at the vapor chamber, they have a slightly difference. We can see from Table 16, the variation of the thermal resistances between COMSOL 1D model and Matlab analytical one is about 3.7%. So we can say that COMSOL matches better with the 1D thermal resistance method. And Figure 109 shows also that the 3D model is more close to the When we increase the Qin to 10W, the difference between COMSOL 3D and thermal resistance model turns more obvious. Even if we have already set the thermal conductivity to zero in the X and Y direction, guess: the convective term in the energy equation no zero and have a very high influence to the result. By using the 3D COMSOL model, we can also find the 3D temperature map, 3D pressure map of the heat pipe model. wall, wick and the vapor-core have dimensions of Lx and Ly, respectively, in the x and y directions. The vapor chamber is subjected to multiple arbitrarily shaped and time-varying heat inputs on one of its faces (z = 0), while the other face (z =hwall,1 + hwick,1 + hvap + hwick,2 + hwall,2) is subjected to a uniform convective boundary condition. The lateral walls are insulated. The thickness of the walls and wick along the sides at x = 0, x = Lx, y = 0 and y = Ly is assumed to be negligible. [START_REF] Patankar | A Time-Stepping Analytical Model for 3D Transient Vapor Chamber Transport[END_REF] The governing equations solved for the vapor chamber are described below. The wick is assumed to be a homogeneous porous medium with saturated liquid. Flow in the wick and vapor core is assumed to be laminar and incompressible. The governing equations for mass, momentum and energy transport are Mass conservation equation:

4.3.2) Analytical solution for 3D heat pipe (configuration III)

∂u 𝜕𝜕𝑜𝑜 + ∂v 𝜕𝜕𝑜𝑜 + ∂w 𝜕𝜕𝑜𝑜 = 0 (4-53)
Momentum equation:

𝜌𝜌 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝑡𝑡 + 1 𝜀𝜀 𝑑𝑑 ρ �𝑠𝑠 • 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝑜𝑜 + 𝑡𝑡 • 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝜕𝜕 + 𝑤𝑤 • 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝜕𝜕 � = -∇(𝜀𝜀 𝑑𝑑 𝑃𝑃) + 𝜇𝜇( 𝜕𝜕 2 𝑇𝑇 � �⃗ 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝑇𝑇 � �⃗ 𝜕𝜕𝜕𝜕 2 + 𝜕𝜕 2 𝑇𝑇 � �⃗ 𝜕𝜕𝜕𝜕 2 ) -𝜇𝜇𝐾𝐾 -1 𝑇𝑇 �⃗ (4-54)
Energy equation:

(𝜌𝜌𝐶𝐶 𝑑𝑑 ) 𝑑𝑑𝑓𝑓𝑓𝑓 𝜕𝜕𝑇𝑇 𝜕𝜕𝑡𝑡 + �𝜌𝜌𝐷𝐷 𝑑𝑑 � 𝜌𝜌 (𝑠𝑠 • 𝜕𝜕𝑇𝑇 𝜕𝜕𝑜𝑜 + 𝑡𝑡 • 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 + 𝑤𝑤 • 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) = 𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 ( 𝜕𝜕 2 T 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝑇𝑇 𝜕𝜕𝜕𝜕 2 + 𝜕𝜕 2 𝑇𝑇 𝜕𝜕𝜕𝜕 2 ) (4-55)
For wick,

(𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝑑𝑑𝜋𝜋𝜋𝜋 = 𝜀𝜀 𝑑𝑑 (𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝜌𝜌 + (1 -𝜀𝜀 𝑑𝑑 ) (𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝑠𝑠 (4-56)
For the wall,

(𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝑑𝑑𝜋𝜋𝜋𝜋 = (𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 (4-57)
For the vapor core,

(𝜌𝜌𝐷𝐷 𝑑𝑑 ) 𝑑𝑑𝜋𝜋𝜋𝜋 = (𝜌𝜌𝐷𝐷 𝑑𝑑 ) v𝜋𝜋𝑑𝑑 (4-58)
Mass flux rate [START_REF] Carey | Liquid-vapor phase-change phenomena[END_REF],

𝑚𝑚̇′ ′ = 2𝜋𝜋 2-𝜋𝜋 ℎ 𝑓𝑓𝑔𝑔 𝜌𝜌 𝑣𝑣𝑎𝑎𝑑𝑑 𝑇𝑇 𝑣𝑣𝑎𝑎𝑑𝑑 1.5 � 𝑀𝑀𝑙𝑙 2𝜋𝜋𝑅𝑅 𝑐𝑐𝑜𝑜𝑛𝑛𝑠𝑠𝑚𝑚 � 0.5 (𝑇𝑇 𝑖𝑖𝑙𝑙𝑡𝑡 -𝑇𝑇 𝑠𝑠𝜋𝜋𝑡𝑡 ) (4-59)
The saturation temperature in the vapor core is computed using the Clausius-Clapeyron equation: Assumption:

𝑑𝑑𝑃𝑃 𝑠𝑠𝑎𝑎𝑚𝑚 𝑑𝑑𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 = ℎ 𝑓𝑓𝑔𝑔 𝑃𝑃 𝑠𝑠𝑎𝑎𝑚𝑚 𝑅𝑅𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 2 (4-60)

Boundary conditions

(-𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 -𝑚𝑚̇2 ′′ ℎ 𝜋𝜋𝑙𝑙 = (-𝑘𝑘 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑣𝑣𝜋𝜋𝑑𝑑 (4-67) At z = ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,2 𝑠𝑠 = 𝑡𝑡 = 𝑤𝑤 = 0 (4-68) (-𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 = (-𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 (4-69) At z = ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,2 + ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,2 𝑠𝑠 = 𝑡𝑡 = 𝑤𝑤 = 0 (4-70) (-𝑘𝑘 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 = ℎ(𝑇𝑇 -𝑇𝑇 ∞ ) (4-
𝑇𝑇 � 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 = 𝑇𝑇 � 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 = 𝑇𝑇 � 1 (4-78) 𝑇𝑇 � 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,2 = 𝑇𝑇 � 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,2 = 𝑇𝑇 � 2 (4-79) 𝑇𝑇 = 𝑎𝑎�𝑧𝑧 -ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 -ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 � 2 + 𝑏𝑏�𝑧𝑧 -ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 -ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 � + 𝑐𝑐 (4-80) 𝑎𝑎 = 3(𝑇𝑇 � 1 +𝑇𝑇 � 2 -2𝑇𝑇 � 𝑣𝑣𝑎𝑎𝑑𝑑 ) ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 2 , 𝑎𝑎 = 6𝑇𝑇 � 𝑣𝑣𝑎𝑎𝑑𝑑 -4𝑇𝑇 � 1 -2𝑇𝑇 � 2 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 , c = 𝑇𝑇 � 1 (4-81)
At wick, we have

𝜇𝜇 𝜕𝜕 2 𝜕𝜕𝜕𝜕 2 , 𝜌𝜌 𝜕𝜕 𝜕𝜕𝑡𝑡 ≪ 𝜇𝜇𝜀𝜀 𝑑𝑑 𝐾𝐾 (4-82) So ∇(𝜀𝜀 𝑑𝑑 𝑃𝑃) = -𝜇𝜇𝐾𝐾 -1 𝑇𝑇 �⃗ (4-83) (ρ𝐷𝐷 𝑑𝑑 ) 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕𝑇𝑇 𝜕𝜕𝑡𝑡 = 𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕 2 𝑇𝑇 𝜕𝜕𝜕𝜕 2 (4-84)
By combining all the above equations, and replace T by θ,

𝜃𝜃 = � 𝑇𝑇 � 1 𝑇𝑇 � 𝑣𝑣𝜋𝜋𝑑𝑑 𝑇𝑇 � 2 � (4-85) 𝜕𝜕𝜃𝜃 𝜕𝜕𝑡𝑡 = 𝐴𝐴 � 𝜕𝜕 2 𝜃𝜃 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝜃𝜃 𝜕𝜕𝜕𝜕 2 � + 𝐹𝐹𝜃𝜃 + 𝐷𝐷 (4-86) 𝐷𝐷 = ⎣ ⎢ ⎢ ⎢ ⎡ 𝑞𝑞 𝑠𝑠𝑛𝑛 ′′ -𝑚𝑚̇1 ′′ ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 1 0 ℎ𝑇𝑇 ∞ -𝑚𝑚̇2 ′′ ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎥ ⎤ (4-87) 𝛽𝛽 1 = �𝜌𝜌𝐷𝐷 𝑑𝑑 � 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + �𝜌𝜌𝐷𝐷 𝑑𝑑 � 𝑑𝑑𝜋𝜋𝜋𝜋,𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 (4-88) 𝛽𝛽 2 = �𝜌𝜌𝐷𝐷 𝑑𝑑 � 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,2 ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,2 + �𝜌𝜌𝐷𝐷 𝑑𝑑 � 𝑑𝑑𝜋𝜋𝜋𝜋,𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,2 ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,2 (4-89) 𝐴𝐴 = ⎣ ⎢ ⎢ ⎡ 𝑘𝑘 𝑤𝑤𝑎𝑎𝑡𝑡𝑡𝑡,1 ℎ 𝑤𝑤𝑎𝑎𝑡𝑡𝑡𝑡,1 𝛽𝛽 1 0 0 0 0 0 0 0 𝑘𝑘 𝑤𝑤𝑎𝑎𝑡𝑡𝑡𝑡,2 ℎ 𝑤𝑤𝑎𝑎𝑡𝑡𝑡𝑡,2 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎤ (4-90) 𝐹𝐹 = ⎣ ⎢ ⎢ ⎢ ⎢ ⎡ -𝑘𝑘 𝑣𝑣𝑎𝑎𝑑𝑑 𝛽𝛽 1 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 0 0 0 6𝑘𝑘 𝑣𝑣𝑎𝑎𝑑𝑑 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 2 �𝜌𝜌𝐶𝐶 𝑑𝑑 � 𝑣𝑣𝑎𝑎𝑑𝑑 0 0 0 -𝑘𝑘 𝑣𝑣𝑎𝑎𝑑𝑑 𝛽𝛽 2 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑⎦ ⎥ ⎥ ⎥ ⎥ ⎤ × � 4 -6 2 1 -2 1 2 -6 4 + ℎ * ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 𝑘𝑘 𝑣𝑣𝑎𝑎𝑑𝑑 � (4-91)
First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 137

For the vapor core, another assumption

ρ 𝜕𝜕𝑇𝑇 � �⃗ 𝜕𝜕𝑡𝑡 = 0 (4-92) ∇𝑃𝑃 = 𝜇𝜇 𝜕𝜕 2 𝑇𝑇 � �⃗ 𝜕𝜕𝜕𝜕 2 (4-93)
So along with the boundary conditions, we have

u = 1 2𝜇𝜇 𝜕𝜕𝑃𝑃 𝜕𝜕𝑜𝑜 (𝑧𝑧 2 -�2ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + 2ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 �𝑧𝑧 + (ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 )(ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 )) (4-94) v = 1 2𝜇𝜇 𝜕𝜕𝑃𝑃 𝜕𝜕𝜕𝜕 (𝑧𝑧 2 -�2ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + 2ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 �𝑧𝑧 + (ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 )(ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 )) (4-95)
So the mass conservation equation of the vapor core change to:

𝜕𝜕 2 𝑃𝑃 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝑃𝑃 𝜕𝜕𝜕𝜕 2 = - 12𝜇𝜇 𝜌𝜌ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 3 (𝑚𝑚̇1 ′′ + 𝑚𝑚̇2 ′′ ) (4-96)
With clausius-clapeyron equation

𝜕𝜕𝑃𝑃 𝜕𝜕𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 = 𝜆𝜆 = ℎ 𝑓𝑓𝑔𝑔 𝑃𝑃 𝑟𝑟𝑑𝑑𝑓𝑓 𝑅𝑅(𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 2 ) 𝑚𝑚𝑑𝑑𝑎𝑎𝑛𝑛 (4-97) 𝜆𝜆 � 𝜕𝜕 2 𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝑇𝑇 𝑠𝑠𝑎𝑎𝑚𝑚 𝜕𝜕𝜕𝜕 2 � = - 12𝜇𝜇 𝑣𝑣𝑎𝑎𝑑𝑑 𝜌𝜌 𝑣𝑣𝑎𝑎𝑑𝑑 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 3 𝜀𝜀 𝑑𝑑 (𝑇𝑇 � 1 + 𝑇𝑇 � 2 -2𝑇𝑇 𝑠𝑠𝜋𝜋𝑡𝑡 ) (4-98)
Solution to the combined energy equation

𝜃𝜃 = � 𝑇𝑇 � 1 𝑇𝑇 � 𝑣𝑣𝜋𝜋𝑑𝑑 𝑇𝑇 � 2 � = ∑ ∑ �𝑎𝑎 𝜌𝜌𝑘𝑘 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜 � cos � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦 �� , 𝑤𝑤ℎ𝑑𝑑𝑟𝑟𝑑𝑑 𝑎𝑎 𝜌𝜌𝑘𝑘 = � 𝑎𝑎 1 𝑎𝑎 𝑣𝑣𝜋𝜋𝑑𝑑 𝑎𝑎 2 � 𝜌𝜌𝑘𝑘 ∞ 𝑘𝑘=0 ∞ 𝜌𝜌-0 (4-99) 𝑇𝑇 𝑠𝑠𝜋𝜋𝑡𝑡 = ∑ ∑ �𝑐𝑐 𝜌𝜌𝑘𝑘 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜 � cos � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦 �� ∞ 𝑘𝑘=0 ∞ 𝜌𝜌-0 (4-100) 𝑐𝑐 𝜌𝜌𝑘𝑘 = [1 0 1]𝜋𝜋 𝑡𝑡𝑘𝑘 ( 𝜆𝜆𝜌𝜌 𝑣𝑣𝑎𝑎𝑑𝑑 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 3 12𝜇𝜇 𝑣𝑣𝑎𝑎𝑑𝑑 𝜀𝜀 𝑑𝑑 𝜋𝜋 2 ( 𝑡𝑡 2 𝐿𝐿 𝑜𝑜 2 + 𝑘𝑘 2 𝐿𝐿 𝑦𝑦 2 )+2) (4-101) ∑ ∑ �𝑏𝑏 𝜌𝜌𝑘𝑘 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜 � cos � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦 �� = ⎣ ⎢ ⎢ ⎡ 𝑞𝑞 𝑠𝑠𝑛𝑛 ′′ 𝛽𝛽 1 0 ℎ𝑇𝑇 ∞ 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎤ ∞ 𝑘𝑘=0 ∞ 𝜌𝜌-0
G = A𝜋𝜋 2 � 𝜌𝜌 2 𝐿𝐿 𝑜𝑜 2 + 𝑘𝑘 2 𝐿𝐿 𝑦𝑦 2 � -𝐹𝐹 - ⎣ ⎢ ⎢ ⎡ -𝜀𝜀 𝑃𝑃 ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 1 0 0 0 0 0 0 0 -𝜀𝜀 𝑃𝑃 ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎤ - ⎣ ⎢ ⎢ ⎡ 𝜀𝜀 𝑃𝑃 ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 1 0 𝜀𝜀 𝑃𝑃 ℎ 𝑓𝑓𝑔𝑔 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎤ [1 0 1]𝜋𝜋 𝑡𝑡𝑘𝑘 ( 𝜆𝜆𝜌𝜌 𝑣𝑣𝑎𝑎𝑑𝑑 ℎ 𝑣𝑣𝑎𝑎𝑑𝑑 3 12𝜇𝜇 𝑣𝑣𝑎𝑎𝑑𝑑 𝜀𝜀 𝑑𝑑 𝜋𝜋 2 ( 𝑡𝑡 2 𝐿𝐿 𝑜𝑜 2 + 𝑘𝑘 2 𝐿𝐿 𝑦𝑦 2 )+2) (4-104) 𝑏𝑏 𝜌𝜌𝑘𝑘 = 𝛿𝛿 𝑡𝑡𝑘𝑘 𝐿𝐿 𝑜𝑜 𝐿𝐿 𝑦𝑦 ∫ ∫ ⎣ ⎢ ⎢ ⎡ 𝑞𝑞 𝑠𝑠𝑛𝑛 ′′ 𝛽𝛽 1 0 ℎ𝑇𝑇 ∞ 𝛽𝛽 2 ⎦ ⎥ ⎥ ⎤ 𝐿𝐿 𝑦𝑦 0 𝐿𝐿 𝑜𝑜 0 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜 � cos � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦 � 𝑑𝑑𝑜𝑜𝑑𝑑𝑦𝑦 (4-105) 𝛿𝛿 𝜌𝜌𝑘𝑘 = 4 𝑓𝑓𝑜𝑜𝑟𝑟 𝑙𝑙 > 0 𝑎𝑎𝑛𝑛𝑑𝑑 𝑘𝑘 > 0 𝛿𝛿 𝜌𝜌𝑘𝑘 = 2 𝑓𝑓𝑜𝑜𝑟𝑟 𝑙𝑙 = 0 𝑎𝑎𝑛𝑛𝑑𝑑 𝑘𝑘 > 0 𝑜𝑜𝑟𝑟 𝑙𝑙 > 0 𝑎𝑎𝑛𝑛𝑑𝑑 𝑘𝑘 = 0 𝛿𝛿 𝜌𝜌𝑘𝑘 = 1 𝑓𝑓𝑜𝑜𝑟𝑟 𝑙𝑙 = 0 𝑎𝑎𝑛𝑛𝑑𝑑 𝑘𝑘 = 0 𝑎𝑎 𝜌𝜌𝑘𝑘 0 = 𝛿𝛿 𝑡𝑡𝑘𝑘 𝐿𝐿 𝑜𝑜 𝐿𝐿 𝑦𝑦 ∫ ∫ � 𝑇𝑇 � 1 0 𝑇𝑇 � 𝑣𝑣𝜋𝜋𝑑𝑑 0 𝑇𝑇 � 2 0 � 𝐿𝐿 𝑦𝑦 0 𝐿𝐿 𝑜𝑜 0 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜 � cos � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦 � 𝑑𝑑𝑜𝑜𝑑𝑑𝑦𝑦 (4-106) 𝑎𝑎 𝜌𝜌𝑘𝑘 𝑙𝑙+1 = (𝐼𝐼 3 + ∆𝑡𝑡𝐺𝐺) -1 (∆𝑡𝑡𝑏𝑏 𝜌𝜌𝑘𝑘 𝑙𝑙+1 + 𝑎𝑎 𝜌𝜌𝑘𝑘 𝑙𝑙 ) (4-107)
For the wick As we can see, here, we have a good fit in the mass flow between COMSOL and analytical model, the difference between FEM and the analytical model comes very probably from that the COMSOL calculates temperature map and pressure field iteratively, but the analytical model replace the mass flow by a temperature dependent formula, and the temperature is calculated only by temperature field. And the pressure field in the analytical model is dominated by temperature. So that's to say, by using FEM model, we can more accurately restore the temperature value, because the analytical model make an assumption that the evaporated mass depends only on the temperature. This will decrease the calculation accuracy. But, in all, the analytical model has also a good fit with FEM model which has a difference of about 2.5%. If the temperature gets higher, the difference will be more negligible. Besides, with FEM model, the velocity field and pressure field of wick and vapor chamber can be extracted, shown in the Figure 114 and Figure 115. From Figure 115, we can see the exact velocity of water and vapor, the water is evaporated at the heater part and turns to vapor, and then the vapor flows to the other side of the heat-pipe and then condensed, turns back to water. From Figure 114, we can extract also the capillary pressure at the wick/vapor interface. Here, in this case, the marge of capillary pressure is about 200 Pa.

𝜕𝜕 2 𝑃𝑃 𝑠𝑠𝑔𝑔𝑚𝑚 𝜕𝜕𝑜𝑜 2 + 𝜕𝜕 2 𝑃𝑃 𝑠𝑠𝑔𝑔𝑚𝑚 𝜕𝜕𝜕𝜕 2 = 𝑚𝑚̇1 ′′ 𝜇𝜇 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 + 𝑚𝑚̇2 ′′ 𝜇𝜇 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 (4
As a conclusion, the analytical model is accurate in the estimation of the mass flow, but for the calculation of temperature, it needs some little improvement. And the FEM model is very accurate; it considers the pressure field in the calculation, and especially it can extract the capillary pressure from the model, which will be very useful in the future study of wick layer's capillary effects. The temperature drop due to the thermal transfer mechanisms the flat heat pipe can be calculated using the above simplified effective thermal resistance network, as shown in Figure 116. The thermal resistances due to the vertical conduction along the thickness of the wall in the evaporation (𝑅𝑅 𝑤𝑤𝜌𝜌,𝑑𝑑 ) and condensation sides (𝑅𝑅 𝑤𝑤𝜌𝜌,𝑙𝑙 ) are negligible (because of the thin thickness of wall), which is viable only for ultrathin heat pipes with high conductive materials. Lateral conduction along the wall is represented as 𝑅𝑅 𝑤𝑤𝜌𝜌,𝜌𝜌𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟𝜋𝜋𝜌𝜌1 and 𝑅𝑅 𝑤𝑤𝜌𝜌,𝜌𝜌𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟𝜋𝜋𝜌𝜌2 ; the effective thermal resistances can be obtained using an effective length 𝜔𝜔 𝑑𝑑𝜋𝜋𝜋𝜋 that considers the different heat load along the length of the evaporator and condenser, and is written as [START_REF] Yadavalli | Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-thin Form Factors[END_REF] 𝜔𝜔 𝑑𝑑𝜋𝜋𝜋𝜋 = 𝜔𝜔 𝜋𝜋 +

4.4) Performance-limiting Conditions

𝐿𝐿 𝑑𝑑 +𝐿𝐿 𝑐𝑐 2 (4-119)
Resistances vertically across the wick in the evaporation side (𝑅𝑅 𝑤𝑤,𝑑𝑑 ), condensation side (𝑅𝑅 𝑤𝑤,𝑙𝑙 ), and along the wick ( 𝑅𝑅 𝑤𝑤,𝜌𝜌𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟𝜋𝜋𝜌𝜌 ) are supposed to be conductive. The solid and fluid thermal convection in the wick is neglected, due to the low liquid flow velocities. Here, we use an effective saturated wick thermal conductivity to simplify the calculation of thermal conduction resistances. Lateral heat flow through the wick is neglected, because of the high thermal resistance that results from the low thermal conductivity and high aspect ratio of wick geometry. To simplify the simulation, heat loss due to surroundings' convection is neglected.

The wick/vapor phase-change thermal resistances are expressed by 𝑅𝑅 𝑖𝑖,𝑑𝑑 and 𝑅𝑅 𝑖𝑖,𝑙𝑙 , respectively. They are normally small [START_REF] Reay | Heat Pipes: Theory, Design, and Applications[END_REF], so, neglected. The effective thermal resistance of the vapor core 𝑅𝑅 𝑣𝑣 , is calculated from an effective thermal conductivity of vapor [START_REF] Prasher | A Simplified Conduction Based Modeling Scheme for Design Sensitivity Study of Thermal Solution Utilizing Heat Pipe and Vapor Chamber Technology[END_REF], which is calculated by assuming that the vapor flow is laminar, incompressible, fully developed flow between parallel plates, and governed by continuum equation along the effective length of vapor core. The effective conductivity of vapor is shown as follow.

𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋,𝑣𝑣 = ℎ 𝑓𝑓𝑔𝑔 2 𝑃𝑃 𝑣𝑣 𝜌𝜌 𝑣𝑣 𝑡𝑡 𝑣𝑣 2 12𝑅𝑅𝜇𝜇 𝑣𝑣 𝑇𝑇 𝑣𝑣 2 (4-120)
where the thermos-physical properties are those of ideal gas and the effective thermal conductivity depends on the local vapor temperature along the effective length of vapor core. To calculate temperature-dependent vapor thermal conductivity, the vapor effective thermal resistance is discretized along the flowing direction. This approach does not consider the vapor convection effects.

So the effective thermal resistance of the FHP configuration I can be expressed as

𝑅𝑅 𝑇𝑇𝑃𝑃 = 1 1 𝑅𝑅 𝑤𝑤𝑡𝑡,𝑡𝑡𝑎𝑎𝑚𝑚𝑑𝑑𝑟𝑟𝑎𝑎𝑡𝑡1 + 1 𝑅𝑅 𝑤𝑤𝑡𝑡,𝑡𝑡𝑎𝑎𝑚𝑚𝑑𝑑𝑟𝑟𝑎𝑎𝑡𝑡2 + 1 (𝑅𝑅 𝑣𝑣 +𝑅𝑅 𝑤𝑤,𝑑𝑑 +𝑅𝑅 𝑤𝑤,𝑐𝑐 ) (4-121)
By generating the performance map through different input heat fluxes and for a range of geometries, it is possible to identify the advantageous region of small thickness and low input power FHP. Figure 117 shows a color map of the ratio between the heat pipe and copper heat spreader thermal resistances with the length and total thickness being varied. The colored region Figure 117 (a) show the advantageous region for the FHP with a lower input heat flux of 0.2 W/cm 2 . When the input heat fluxes stay low, the fluid velocities induced capillary pressure is sufficiently small, and the capillary limit moves to lower thicknesses and higher working lengths.

Figure 117(b) show the advantageous region for the FHP with a higher input heat flux of 2 W/cm 2 . From the figure we can see, as the thickness is reduced to certain length, the minimum thickness for which RHP/RHS remains greater than 1 is governed by the capillary limit. That means that when the thicknesses reduce to a relatively small value and heat fluxes increase to a relatively high value, the pressure drop at the wick/vapor interface due to the higher mass flow gets higher than the maximum capillary pressure which is related to the liquid surface tension at the wick surface. The performance advantage of FHP comes from the small thermal resistances brought by liquid/vapor phase change between the evaporation and the condensation when heat is applied to the wick structure. However, this advantage will not exist while the FHP gets shorter and thicker, where the solid heat sinks with the same geometry can provide a more direct and higher conductivity than the FHP.

Except for the thickness-to-length ratio limit and the capillary limit, there is another limit, which is called vapor-resistance threshold. By calculating the equivalent thermal resistance of Figure 116, utilizing the assumption that RHP/RHS equals to 1, and representing the thicknesses of the vapor core, wick, and walls as fractions of the total thickness, i.e., tv = rvt, tw = rwt, and twl = rwlt, the new limit can be denoted as [START_REF] Yadavalli | Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-thin Form Factors[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits The equation have two positive roots representing the thickness limits where the RHP/RHS equals to 1. The minimum thickness limit governed by this equation is

𝑡𝑡 𝜌𝜌𝑖𝑖𝑚𝑚𝑖𝑖𝑡𝑡 = ⎝ ⎜ ⎛ 𝐿𝐿 𝑑𝑑𝑓𝑓𝑓𝑓 𝑘𝑘 𝑠𝑠 𝜋𝜋-�� 𝐿𝐿 𝑑𝑑𝑓𝑓𝑓𝑓 𝑘𝑘 𝑠𝑠 � 2 -4 𝑟𝑟 𝑤𝑤 𝑘𝑘 𝑤𝑤 � 1 𝐿𝐿 𝑑𝑑 + 1 𝐿𝐿 𝑐𝑐 �� 𝐿𝐿 𝑑𝑑𝑓𝑓𝑓𝑓 𝑀𝑀 𝑣𝑣 𝑟𝑟 𝑣𝑣 3 � 2 𝑟𝑟 𝑤𝑤 𝑘𝑘 𝑤𝑤 � 1 𝐿𝐿 𝑑𝑑 + 1 𝐿𝐿 𝑐𝑐 � ⎠ ⎟ ⎞ 1 2 (4-123)
where a = 1/(1 -rwl) and Mv is the vapor properties related constant. The above limit depends only on the FHP geometry and material properties, it's independent of the heat input. Besides, this limit appears at the lower side of the thickness, so it should be considered in conjunction with the capillary limit, which depends on the heat inputs. For the FHP of low heat inputs, this limit depends on the single factor Mv, and it's also called vapor-resistance limit. The key factor Mv can be expressed by the following equation: [START_REF] Yadavalli | Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-thin Form Factors[END_REF]

𝑀𝑀 𝑣𝑣 = ℎ 𝑓𝑓𝑔𝑔 2 𝜌𝜌 𝑣𝑣 𝑃𝑃 𝑣𝑣 𝑅𝑅𝜇𝜇 𝑣𝑣 𝑇𝑇 𝑣𝑣 2 (4-124)
which is independent of geometric parameters.

4.5) Conclusion

As a conclusion, the FEM based model (COMSOL Multiphysics) is very accurate in the 2D and 3D simulations of thin flat heat pipe. Precise boundary conditions can be found in the previous part; it considers the pressure field in the calculation, and especially it can extract the capillary pressure directly from the model, which will be very useful in the future study of wick layer's capillary effects.

As future work, the simplification for the evaporated mass should be changed to a temperature dependent parameters and a quantitative analysis of the model error, due to the employed simplifying assumptions, will be performed over a range of operating conditions. This model will be changed to a 3D model and then used to simulate the behavior of a vapor chamber subjected to multiple heat input boundary conditions to demonstrate the capability of the model in solving the 3D thermal real-applications. Before coming to the real-applications, some transfer mechanisms should be included in the model, for instance, the effects of external boundary conditions on the wick/vapor interfacial mass flux, the influence of inner vapor convections, and smearing effect of the interfacial mass flux into the heat insulation region by lateral thermal conduction. However, these effects should be considered only for detailed numerical models for the application-oriented design and optimization of ultrathin FHP.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

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Chapter 5: Noise in 3D circuits

The last chapter is interested in the noise in a much generalized way. Noise is a highly prominent and stochastic phenomenon, but from the other side of view, parasitic effects can be determinist effects in the 3D IC design. This chapter gives more possibilities on the domain of the noise, rather subtle which becomes prohibitive because of the miniaturization and the passage to the 2D through 3D, where reside strong conceptual problems. Noise is a universal phenomenon. Generally, micro-electronics and, of course, nano-electronics are domains where although autonomous noise sources can be dependent on each other due to their proximity, for example. Here, we will introduce concepts such as correlation of random variables, and noise spectral density. We will recall briefly the concept of transfer impedance; calculations at the unidimensional level have already been developed, but there are few in 2D and nothing considerable in 3D. Velocity fluctuations or generation-recombination, which can help quantifying certain noises by using master equations like the Boltzmann ones, can be taken into account in statistical methods like Monte Carlo ones.

5.1) Introduction

Laboratories work in the domain of background noise in semiconductors and devices, thus on fluctuation of physical or electrical quantities and ad hoc mathematical tools, thereby building a comprehensive and cooperative program via dialogue between researchers, students, postgraduates, devices and information. This covers fundamental studies as well as their application in modern submicronic devices (submicronic (SiGeC) silicon transistors, ultimate CMOS, high-speed III-V devices (HEMT: High Electron Mobility Transistor, Heterojunction Bipolar Transistor), and optoelectronic devices (lasers, photodiodes). [START_REF] Yue Ma | 3-D Interconnects with IC's Stack Global Electrical Context Consideration[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] In electronic chips, semiconductor devices are immersed in a more or less noisy environment. From a microscopic point of view, fluctuations of physical and electronic quantities can be apprehended, for instance, using the Boltzmann equation, numerically or via Monte Carlo methods, and by calculating, for example, the speed fluctuation correlation function and its Fourier transform, which will give the noise spectral density. It was Shockley [START_REF] Shockley | Quantum Theory of Atoms, Molecules and Solid State[END_REF], inventor of the bipolar transistor (1948), who initiated these studies. Van der Ziel [START_REF] Van Der Ziel | Noise in solid state devices and circuits[END_REF], [242] and Van Vliet [START_REF] Picinbono | Introduction à l'étude des signaux et phénomènes aléatoires[END_REF], as well as other eminent researchers contributed to these studies [START_REF] Beyne | Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration[END_REF][245].

Currently, related numerical methods, such as the very promising transfer impedance method, can lead to some results, but most of the time, it will lead to 1D.

• Random functions

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 147

A random variable is a real or complex number, the value of which depends on chance, (that is, a priori, unpredictable) meaning that it depends on a "proof". A random function is one for which the value is constantly dependent on chance. A simple random function depends on one or more random variables. To know the value of the function at a specific moment t, then, there is a random variable x (f) that can be described by its probability density p (x, t) or, briefer still, by certain moments: <X 1 (t)>, <X 2 (t)>, etc. (average values are also called expectations and marked E; thus: E{X (t)}, E{X 2 (t)} …) It will also be interesting to look at properties at two given instants: a moment that plays a specifically important role is covariance or correlation: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] Γ�X(𝑡𝑡 1 , 𝑡𝑡 2 )� =< X(𝑡𝑡 1 )X * (𝑡𝑡 2 ) >

(5-1)

X * (𝑡𝑡 2 ) is the complex conjugate of X(𝑡𝑡 2 )
• Second order stationary random functions:

In numerous cases, we deal with at least second order random functions. These functions have the following properties: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] a) They are first-order stationary:

< X(t) >= 𝑚𝑚 (5-2)
b) Let us use second order stationarity

Γ�X(τ)� =< X(t)X * (t -τ) > (5-3)
For 𝜏𝜏 = 0, Γ�X(0

)� =< |X(t)| 2 >
From the stationarity, we directly get:

Γ�X(𝜏𝜏)� = Γ�X * (-𝜏𝜏)� (5-4)
• Wiener-Khinchin theorem

If the signal can be written as a Fourier-Stieltjes transform, complex exponentials on elementary growth dx(ν) :

X(t) = ∫ e 2iπνt ∞ -∞ dx(ν) (5-5)
Taking (5-2) and (5-5) into consideration, the average, which is constant, can be written as:

m = ∫ e 2iπνt ∞ -∞ < 𝑑𝑑𝑜𝑜(ν) > (5-6)
From which we get First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 148

< 𝑑𝑑𝑜𝑜(𝜈𝜈) > = 𝑚𝑚𝛿𝛿(𝜈𝜈)𝑑𝑑𝜈𝜈 (5-7)
Thus, < 𝑑𝑑𝑜𝑜(ν) > is independent of ν and non-zero only when ν = 0. Now, if we take second order stationarity into account, that is, if we substituted X(t) and X * (t -τ) with their values:

Γ X (τ) = < ∫ e 2iл𝜈𝜈𝑡𝑡 dx(ν) +∞ -∞ • ∫ e -2iл(𝑡𝑡-𝜏𝜏) dx * (ν ′ ) +∞ -∞ > (5-8) Γ X (τ) = ∫ ∫ < dx(ν)dx * (ν ′ ) > 𝑑𝑑 2iл(𝜈𝜈′)τ e 2iл(𝜈𝜈-𝜈𝜈′)τ +∞ -∞ +∞ -∞ (5-9)
Γ X (τ) must be independent of t, and so all ν ≠ν terms are zero. The integral (IV.18) must be zero. Thus, we can write:

< dx(ν) dx * (ν ′ ) > = 𝛿𝛿(ν -ν ′ )γ X (ν)dνdν′
(5-10)

Thus, there is no correlation between different frequencies for second order stationary functions. The γ X (ν) quantity is called spectral density of fluctuation of X. It is observed on the whole frequency spectrum, positive and negative. In general, we only take positive frequencies, and the measurable physical quantity SX (f) is defined by: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

S X (f) = S X (𝑓𝑓) = γ X (ν = 𝑓𝑓) + γ X (ν = -𝑓𝑓) (5-11) Γ X (τ) = ∫ ∫ 𝛿𝛿(𝜈𝜈 -𝜈𝜈′)γ X (ν)e 2iлν′τ +∞ -∞ e 2iл(𝜈𝜈-𝜈𝜈′)τ dν dν′ +∞ -∞ (5-12)
After integrating on 𝜈𝜈′, [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

Γ X (τ) = ∫ e 2iлντ +∞ -∞ γ X (ν) dν
(5-13) Γ X (τ) is the Fourier transform of the spectral density: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] γ

X (ν) = ∫ e -2iлντ +∞ -∞ Γ X (τ) dτ (5-14)
Equations (5-3) and [START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF] relate to the Wiener-Khinchin theorem.

• Properties of spectral density of fluctuation.

a) Complex conjugate of equation (5-14):

By taking (5-14) into consideration and adding θ = t -τ, we get: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

γ X * (ν′) = -∫ Γ X * (-θ)e -2iлνθ +∞ -∞ dθ = ∫ Γ 𝑜𝑜 (θ)e -2iлνθ +∞ -∞ dθ = γ X (ν) (5-15)
Hence, γ X * (ν) is a real quantity. It is positive.

b) White noise: the noise is said to be white if γ X (ν) is constant, irrespective of ν, equation (5-13) will be First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 152

S 𝑇𝑇 (f) = |Z| 2 S 𝐼𝐼 (𝑓𝑓) (5-40) S I (f) = S V (f) R 2 +L 2 ω 2
(5-40)

Now, let us consider the microscopic aspect and calculate < 𝑆𝑆 2 >. The average energy stored inside the coil is:

1 2 𝜔𝜔𝑆𝑆 2
(5-41)

In 1D, we can write: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

1 2 𝜔𝜔𝑆𝑆 2 = 1 2 𝑘𝑘𝑇𝑇 (5-41)
Yet:

< 𝑆𝑆 2 >= ∫ S i (f) ∞ 0 d𝑓𝑓 = ∫ df R 2 +4π 2 L 2 f 2 ∞ 0 = S V 4RL (5-42)
So:

S V = 4kRT(Nyquist theorem) (5-43) S I = 4kT R R 2 +L 2 ω 2
(5-44)

• Forms of Langevin Equations Langevin equations often involve several coupled equations for 𝑋𝑋 1 (𝑡𝑡), 𝑋𝑋 2 (𝑡𝑡) variables, the average value of which satisfy the relationship of the form: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] 𝜕𝜕<𝑜𝑜 𝑠𝑠 (𝑡𝑡)> 𝑐𝑐𝑜𝑜𝑛𝑛𝑑𝑑 𝜕𝜕𝑡𝑡 + ∑ 𝑀𝑀 𝑖𝑖𝑗𝑗 𝑖𝑖 < 𝑜𝑜 𝑖𝑖 (𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 = 0

(5-45)

< 𝑜𝑜 𝑖𝑖 (𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 is a conditional mean respecting the given initial conditions. This is the case, for example, with electric circuits where initial conditions must be set; these equations are valid around the polarization point for all nonlinear systems. If derivatives of an order higher than 1 appear, the order of the system is to be reduced; for example, for a second order system, we construct a new random variable, first derivative of the initial variable It can be shown that these phenomenological equations are equivalent to a Langevin description, which is the set of unconditional regression equations

The related Langevin description is: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

𝜕𝜕<𝑜𝑜 𝑠𝑠 (𝑡𝑡)> 𝜕𝜕𝑡𝑡 + ∑ 𝑀𝑀 𝑖𝑖𝑗𝑗 𝑗𝑗 < 𝑜𝑜 𝑗𝑗 (𝑡𝑡) > = ϛ(𝑡𝑡) (5-46)
Given that the source terms are mean zero and have white noise.

• Example: Electron injection in p area of a PN junction.

In an ohmic regime, the transport equation without generation-recombination: -𝜕𝜕𝑛𝑛/𝜕𝜕t), is written as: And also: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] < ∆𝑗𝑗 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 = -𝑑𝑑 𝜇𝜇 𝑙𝑙 < ∆𝑛𝑛(𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 𝐸𝐸 �⃗ + 𝑑𝑑 𝐷𝐷 𝑙𝑙 < ∆𝑛𝑛(𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 (5-48)

𝜕𝜕∆𝑙𝑙(𝑟𝑟 ⃗,𝑡𝑡) 𝜕𝜕𝑡𝑡 = - ∆𝑙𝑙(𝑟𝑟 ⃗,𝑡𝑡) 𝜏𝜏 + 1 𝑑𝑑 𝛻𝛻 �⃗ . ∆𝚥𝚥⃗ 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) + ϛ 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) (5-49) ∆𝑗𝑗 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) = -𝑑𝑑 𝜇𝜇 𝑙𝑙 ∆𝑛𝑛(𝑟𝑟 ⃗, 𝑡𝑡)𝐸𝐸 �⃗ + 𝑑𝑑𝐷𝐷 𝑙𝑙 < ∆𝑛𝑛(𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 𝜂𝜂 ⃗ 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) (5-50)
Analogously, for holes: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] 𝜕𝜕∆𝑑𝑑(𝑟𝑟 ⃗,𝑡𝑡)

𝜕𝜕𝑡𝑡 = - ∆𝑑𝑑(𝑟𝑟 ⃗,𝑡𝑡) 𝜏𝜏 - 1 𝑑𝑑 𝛻𝛻 �⃗ . ∆𝚥𝚥⃗ 𝑙𝑙𝑑𝑑 (𝑟𝑟 ⃗, 𝑡𝑡) + ϛ 𝑑𝑑 (𝑟𝑟 ⃗, 𝑡𝑡) (5-51) ∆𝑗𝑗 𝑑𝑑 (𝑟𝑟 ⃗, 𝑡𝑡) = + 𝑑𝑑 𝜇𝜇 𝑑𝑑 ∆𝑑𝑑(𝑟𝑟 ⃗, 𝑡𝑡)𝐸𝐸 �⃗ -𝑑𝑑 𝐷𝐷 𝑑𝑑 𝛻𝛻 �⃗ . ∆𝑛𝑛(𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑 + 𝑑𝑑𝜂𝜂 ⃗ 𝑑𝑑 (𝑟𝑟 ⃗, 𝑡𝑡) (5-52)
ϛ 𝑙𝑙 𝑎𝑎𝑛𝑛𝑑𝑑 ϛ 𝑑𝑑 are noise sources.

5.3) Noise calculation using the impedance field method

• Principle of the method [START_REF] Nougier | IV-V Microelectronics[END_REF], [START_REF] Van Vliet | Noise in single injection diodes. I. A survey of methods[END_REF] The impedance field method was introduced by W. Shockley et al. [250]. This method differs from the Langevin method in the way it links the macroscopic quantity to elementary microscopic fluctuations. The spectral density of voltage fluctuations can be brought down to two basic calculations: that of the spectral density of voltage fluctuation and that of elementary fluctuations.

• Impedance fields:

Let us consider a polarized specimen between electrode N and the grounding. If we inject a little current ∆𝐼𝐼, flowing out of N, at a coordinate point 𝑟𝑟 ��⃗ in the volume the potential of N varies by ∆𝑇𝑇(𝑁𝑁, 𝑟𝑟 ��⃗).

Each noise course at the coordinate point 𝑟𝑟 ��⃗ in the substrate (and also in the devices) produces a noise in another point of the volume and the surface (and electrodes).

The noise induced depends on its sources and its way of propagation via the impedance field. In order to study the noise between two contacts on the surface or in the substrate, we inject a little current (noise) that is complex, ∆𝐼𝐼 , at frequency f, at a coordinate point 𝑟𝑟 ��⃗(+/-𝑑𝑑𝑟𝑟 ����⃗ ) in the substrate, superimposed on a continuous current between the contacts. This little current produces a potential V(f) in another contact. Thus, we can write: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] ∆𝑇𝑇(𝑟𝑟 + 𝑑𝑑𝑟𝑟) = 𝑍𝑍(𝑟𝑟 + 𝑑𝑑𝑟𝑟)𝛿𝛿𝐼𝐼

(5-53) Z(r,f) is an impedance.

The resulting difference in voltage is:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 155

S v (f) = ∫ ∇ � �⃗ 𝑍𝑍(r, f) • K(r, f) • 𝛻𝛻 �⃗ Z * (r′, f) (5-66)
• Calculation of impedance field

Calculating the impedance field is easy in the case of homogenous samples. But in the casa of non-homogenous samples, in space charge regime, for instance, some precautions must be taken. a) We determine the working regime that is the polarization point, by: -Solving local equations (Poisson's equation, electric neutrality, phenomenological expression of current density, etc.) -Taking boundary conditions into account, that is, for electrodes, to determine integration constants in the preceding differential equations. Thus, we get the local mean field E 0 (𝑟𝑟) based in the average current density 𝑗𝑗 0 .

The average voltage at junctions in the sample is: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

𝑇𝑇 0 = -∫ 𝐸𝐸 �⃗ 0 𝑁𝑁 𝑁𝑁 0 ( 𝑟𝑟 ⃡). 𝑑𝑑𝑟𝑟 ⃡ (5-67)
Where 𝑁𝑁 0 and N are the electrodes. The average current is:

𝐼𝐼 0 = ∬ 𝚥𝚥 0 � ��⃗. 𝐷𝐷 𝑇𝑇 ����⃗ (5-68)
Where S is a slice of the sample, for instance, the surface of an electrode.

b) We calculate the fluctuations of the electric field resulting from introducing current ∆𝐼𝐼 at coordinate point r ⃗. This ∆E � �⃗ (r ⃗ , r ⃗') field is obtained as follow: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

E � �⃗ (r ⃗ ′) = E 0 ����⃗ ( r ⃗ ′) + ∆E � �⃗ (r ⃗ , r ⃗ ') and ȷ ⃗(r ⃗ ′) = ȷ 0 ��⃗( r ⃗ ′) + ∆ȷ ⃗ (r ⃗ , r ⃗ ') (5-69)
The ∆ being considered as disturbances with regard to E 0 and 𝐼𝐼 0 , these zero order terms give the equations for mean values, while the first order terms in ∆𝐸𝐸 and ∆𝐼𝐼 give linear equations. Local Langevin equations thus obtained are solved and the integration constants are determined by imposing the same boundary conditions on ∆E � �⃗ as those applied on E 0 ����⃗ . For ∆E �����⃗ , these conditions are at the level of electrode N and the r̅ point, and at N and No for E 0 ����⃗ . Thus, we get ∆E � �⃗ (r ⃗ , r ⃗ ').

c) We then deduce the impedance gradient

• Example application: noise in ohmic space charge regime (simple injection)

The sample is assumed to be a parallelepiped; we are dealing with a longitudinal unidimensional case. The space charge is not negligible and can make the device's characteristics nonlinear.

We distinguish between the two different regimes:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 156 a) when the space charge of the injected carriers is very weak to significantly affect the volume's conductivity, we get the ohmic regime, where the mean current is proportional to the voltage at the junctions of the sample: 𝐼𝐼 0 ∝ 𝑇𝑇 0 . [172], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

𝑗𝑗 = -qµnE + ε ∂E ∂t (5-70) ∂E ∂x = -q ε ( n -N D )
(5-71)

𝑗𝑗 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) = 𝑑𝑑 𝜇𝜇 𝑙𝑙 𝐸𝐸 �N D+ ε e ∂E ∂t � + ε ∂E ∂t
(5-72) (q = -e, >0)

As for fluctuations: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

E = 𝐸𝐸 0 + ∆𝐸𝐸𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡 (5-73) n = 𝑛𝑛 0 + ∆𝑛𝑛𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡
(5-74) j = 𝑗𝑗 0 + ∆𝐽𝐽𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡

(5-75)

∆𝑗𝑗 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) = 𝑑𝑑. N D 𝜇𝜇∆𝐸𝐸 + εµE 0 ∂∆E ∂x + εµΔE ∂E 0 ∂x + iε𝜔𝜔∆E (5-76)
Hence:

εµE 0 ∂∆E ∂x + ( 𝑑𝑑 µN D + εµ ∂E 0 ∂x + iε𝜔𝜔)∆E = ∆𝑗𝑗 𝑙𝑙 (5-77)
If n=ND

εµE 0 ∂∆E ∂x + (-𝑑𝑑 𝜇𝜇 𝑙𝑙 + iε𝜔𝜔)∆E = ∆𝑗𝑗 𝑙𝑙 (5-78) εµE 0 ∂∆E(x,x′) ∂x + ( 𝑑𝑑𝜇𝜇N D + iε𝜔𝜔)∆E ′ x, x′) = ∆𝑗𝑗 𝑙𝑙 (5-79)
The solution is:

∆E(x, x ′ ) = ∆𝑗𝑗 𝑛𝑛 -𝑑𝑑 𝜇𝜇 𝑛𝑛 + iε𝑗𝑗 + K(x)e - 𝑑𝑑 𝜇𝜇 𝑛𝑛 N D + iε𝜔𝜔 ϵµ 0 E 0 x ′ (5-80) ∆E(x, x′) = ∆𝑗𝑗 𝑛𝑛 𝑑𝑑 𝜇𝜇 𝑛𝑛 + iεµ𝑗𝑗 + ( 1 -e 𝑑𝑑 𝜇𝜇N D + iεµ𝜔𝜔 ϵµ 0 E 0 (x -x ′ )) (5-81)
The impedance gradient is defined by:

𝜕𝜕𝑍𝑍(𝑁𝑁,𝑜𝑜) 𝜕𝜕𝑜𝑜 = - 1 ∆I ∫ 𝜕𝜕∆E(𝑜𝑜,𝑜𝑜")) 𝜕𝜕𝑜𝑜 𝐿𝐿 𝑜𝑜

𝑑𝑑𝑜𝑜′

(5-82)

Then if the diffusion length is much smaller than that of the sample, we can write:

𝜕𝜕𝑍𝑍(𝑁𝑁,𝑜𝑜) 𝜕𝜕𝑜𝑜 = ∆𝑗𝑗 𝑛𝑛 𝑇𝑇( iε𝑗𝑗° 𝑑𝑑 𝜇𝜇 𝑛𝑛 ) . ( 1 -e 𝑑𝑑 𝜇𝜇N D + iε𝑗𝑗 ϵµ 0 E 0 (x-L) ) (5-83)
As for the noise, calculating internal noise spectra that comes from these fluctuations. This method, generalizing the original impedance field method of Shockley et al., was widely used in recent decades to calculate noise and is only efficient in 1D. The important role of this method was, and still is, to calculate the entire range of voltage fluctuations between the device's junctions. Currently, the problem remains unsolved in 3D (even in 2D), not because of the numerical difficulties, but in a physical point of view.

• PRINCIPLE

A current generator induces a voltage variation in every dx slice. The result is that two distinct slices can be correlated. Thus, we cannot write that the spectral density (d.s.) of voltage at junctions of the whole set is the sum of d.s. of voltage of each separate slice (cf. Salami method).

The ∆v(x), ∆v(x′) cross terms must be added. More specifically, let us consider two slices, numbered as α and β. Microscopic noise sources, each sheltered by a noise current generator marked 𝑇𝑇𝑆𝑆 𝛼𝛼 and 𝑇𝑇𝑆𝑆 𝛽𝛽 , are untiled, but not the voltage fluctuations induced by these noise sources. Voltage induced at junctions of slice β by current 𝑆𝑆 𝛼𝛼 is 𝑍𝑍 𝛽𝛽𝛼𝛼 (𝑤𝑤)𝑆𝑆 𝛼𝛼 where 𝑍𝑍 𝛽𝛽𝛼𝛼 is the transfer impedance between slices α and β. As a consequence, the total voltage induced at the junctions of β for all the current generators of different slices is: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

ΔV β = ∑ z βα i α α (5-91)
𝑆𝑆 𝛼𝛼 𝑎𝑎𝑛𝑛𝑑𝑑 𝑆𝑆 𝛽𝛽 are untiled, we get: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

S v Δf = � �i α 2 �z βα z αγ * ∞ αγ (5-92) E � �⃗ (r) ���⃗ = E 0 ����⃗ (r) ���⃗ + δE � �⃗ (r � �⃗, ω)e iωt (5-93) ȷ ⃗(r) ���⃗ = ȷ 0 ��⃗(r) ���⃗ + δȷ ⃗(r � �⃗, ω)e iωt (5-94)
The first order terms are linked via an operator L � : [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] L � δE � �⃗ (r � �⃗, ω) = δȷ ⃗(r � �⃗, ω) (

We can then introduce Green's functions of the operator L �

L ⏞ Z ⇒ �r � �⃗, r′ ���⃗ , ω� = I ⇒ . δ �r � �⃗ -r′ ���⃗ � (5-96)
Where I ⇒ : unit matrix

δE � �⃗ (r � �⃗, ω) = ∭ Z ⇒ �r � �⃗, r ′ ��⃗ , ω� δȷ ⃗(r′ ���⃗ , ω)d 3 r′ (5-97)
The ddp at junctions of a "dr" on an inter-electrode line can be written as:

δV 2 = -∫ dr T ∭ Z ⇒ �r � �⃗, r ′ ��⃗ , ω� δȷ ⃗(r′ ���⃗ , ω)d 3 r′ L 0
(5-98)

And so, between 2 electrodes:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 159

δV = -∫ dr T L 0 ∭ Z ⇒ �r � �⃗, r ′ ��⃗ , ω� δȷ ⃗(r � �⃗, ω)d 3 r′ (5-99)
Finally, for a material of L length, after some simple calculation that may be a little "heavy", we get: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

S v Δf(ω) = ∫ ∫ ∭ d 3 r′′ ∭ d 3 r′′′dr T Z ⇒ �r � �⃗, r ′′ ����⃗ , ω� ȷ N ���⃗�r ′′ ����⃗ , ω�. ȷ N ���⃗′(r ′′′ �����⃗ , ω) L 0 L 0 z T ⇒ �r′ ���⃗ , r ′′′ �����⃗ , ω� dr ′ (5-100)
We also have the spectral density of current fluctuation:

ȷ N ���⃗�r ′′ ����⃗ , ω�. ȷ N ���⃗ ′ �r ′′′ �����⃗ , ω�=K�r ′′ ����⃗ , ω�. δ �r′′ ����⃗ -r′′′ ������⃗ � Δf (5-101)
K is the noise source.

If we want to get "ddps" or impedance of the whole sample, curvilinear integrals must be calculated. Currently, some calculations can be carried out only in 1D, and this is a huge hurdle. Equation (5-100) is written as: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

S v (ω) = ∬ ∇ � �⃗ Z(r, ω) • Sj(r, ω)∇Z T dr 3 (5-102)
To be compared with ((5-78) -cf. impedance field).

Note: S v (ω) is zero if the Z gradient is zero. Hence, we can create a (straight) strongly and uniformly doped slice between the noise source and a target to be protected.

• One-dimensional structures: Noise of a bar in ohmic regime in high frequencies.

E = 𝐸𝐸 0 + ∆𝐸𝐸𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡
(5-103) n = 𝑛𝑛 0 + ∆𝑛𝑛𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡 (5-104) j = 𝑗𝑗 0 + ∆𝐽𝐽𝑑𝑑 𝑗𝑗𝑤𝑤𝑡𝑡 (5-105)

𝑗𝑗 = -qµnE + ε ∂E ∂t (5-106) ∂E ∂x = -q ε (n -N d ) (5-107)
In high frequencies, we can write: Where A is a square section.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 161

Note: The approach for calculating the impedance field, in practice, can be to force the AC sources at each mesh node of the device and evaluate the response at the device's electrodes.

A method derived from the system principle is simpler to implement; we calculate the transimpedance Zij, where i is any node and j is an electrode. As a consequence, Zij = Zji; it can be checked by applying an AC source at a terminal and calculating the internal potentials at each node.

5.5) Substrate noise: towards 3D

The generation-recombination noise (G-R) represents a noise source that is typical and fundamental of a noise in semiconductor materials and related devices, where the carrier concentration can change the order of magnitude a lot. For electron density, fluctuations can happen between two levels: conduction band and donor impurity, or due to defects. Conductivity, associated with GR noise, can be written by relating it to an average carrier lifespan τ:

σ GR = σ 0 1+jωτ
(5-120)

A typical compatible BiCMOS 0,35um process is considered. A specific region (P+/P) is represented. The real profile is modelled by a stack of layers of uniform thickness and uniformly doped.

Let us consider two places where we see this G-R. Modulations of impedance resulting in these GR noises are represented in Figure 119 (a) and (b). Our first results are qualitative, but also seem quantitatively realistic. For instance, we clearly see that in both cases, the influence of the additional GR current, reducing the resistance to low frequencies, before a cutoff frequency of 𝑓𝑓 𝑙𝑙 = 1/(2𝜋𝜋𝜏𝜏). The impedance, for a lifespan of 𝜏𝜏 of 1ns, can be reduced by 5% if its reference value, sans GR. Finally, Figure 120 presents the noise spectral densities of previous two GR cases. For this, we use the impedance transfer paradigm, applied to the multilayer substrate (cf. Figure 60 (b)), using equations like equation .

It should be possible to study current noise, induced by temperature fluctuations in the volume, with these methods.

5.6) Electrical and thermo-mechanical noise impacts of through-silicon via (TSV) on transistor

From the point of view of electrical aspect, TSV-induced substrate noises that threaten the performance of neighboring transistors due to the parasitic path between TSV and transistor [START_REF] Yin | Effectiveness of p+ Layer in Mitigating Substrate Noise Induced by Through-Silicon Via for Microwave Applications[END_REF]. From the point of thermo-mechanical aspect, owing to the inherent mismatch in coefficient of thermal expansion (CTE) between metal and silicon, thermo-mechanical stress will emerge in the vicinity of TSV, when the system cools down from the possible localized high temperature to the room temperature [START_REF] Wang | Study on thermal stress and keep-out zone induced by Cu and SiO2 filled coaxial-annular through-silicon via[END_REF]. The carrier mobility of neighboring transistors would be influenced by the TSVs-inducing thermomechanical stress due to piezo-resistive effect [START_REF] Guo | Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology[END_REF], [START_REF] Guo | Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime[END_REF], [START_REF] Wang | Effects of coaxial through-silicon via on carrier mobility along [100] and [110] crystal directions of (100) silicon[END_REF]. There are some papers focusing on the electrical impact and thermo-mechanical impact of TSV on transistor [START_REF] Yin | Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone[END_REF], [START_REF] Wang | Thermo-mechanical performance of Cu and SiO2 filled coaxial through-silicon-via (TSV)[END_REF], [START_REF] Lin | 3-D transient analysis of TSV-induced substrate noise: Improved noise reduction in 3-D-ICs with incorporation of guarding structures[END_REF], [START_REF] Kim | Effectiveness of a guard ring utilizing an inversion layer surrounding a through silicon via[END_REF]. In fact, the transistors in the vicinity of TSV are affected simultaneously by both the coupling noises and thermo-mechanical stress. There has been some reports on the crossing effect of the two aspects. We implement the combination effect of electrical and thermo-mechanical impacts of TSV on the saturation current of transistor by taking NMOSFET for instance [START_REF] Pares | Image sensor evolution and enabling 3D technologies[END_REF]- [START_REF] Zheng | Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits[END_REF]. The study method is also appropriate for PMOSFET. Models of NMOSFET and PMOSFET are calculated from predictive technology model of the site [START_REF]Nanoscale Integration and Modeling (NIMO) Group[END_REF].

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 163

5.6.1) Investigation method of electrical noise

The saturation current can be impacted by the noise induced by TSV through the body effect. The saturation current 𝐼𝐼 𝑑𝑑𝑠𝑠𝜋𝜋𝑡𝑡 of NMOSFET can be calculated by

𝐼𝐼 𝑑𝑑𝑠𝑠𝜋𝜋𝑡𝑡 = 1 2 𝜇𝜇 𝑙𝑙 𝐷𝐷 𝑜𝑜𝑜𝑜 𝑊𝑊 𝐿𝐿 (𝑇𝑇 𝐺𝐺𝑇𝑇 -𝑇𝑇 𝑡𝑡ℎ ) 2
(5-121)

where 𝑇𝑇 𝐺𝐺𝑇𝑇 represents the voltage difference between gate and source of the NMOSFET; W and L are the width and length of gate, respectively; Cox is the capacitance between gate and carrier channel; 𝜇𝜇 𝑙𝑙 is electron mobility; the threshold voltage 𝑇𝑇 𝑡𝑡ℎ can be related to the body voltage 𝑇𝑇 𝐵𝐵 [START_REF] Xu | Compact modeling and analysis of through-Si-Viainduced electrical noise coupling in three-dimensional ICs[END_REF]

𝑇𝑇 𝑡𝑡ℎ = 𝑇𝑇 𝑡𝑡ℎ0 + 𝛾𝛾��2Φ 𝐹𝐹 -𝑇𝑇 𝐵𝐵𝑇𝑇 + �2Φ 𝐹𝐹 � ≈ 𝑇𝑇 𝑡𝑡ℎ0 - 𝛾𝛾 2�2Φ 𝐹𝐹 𝑇𝑇 𝐵𝐵𝑇𝑇 (5-122)
Where 𝑇𝑇 𝑡𝑡ℎ0 is the threshold voltage at zero body voltage; 𝛾𝛾 represents the body-effect parameter; and 2Φ 𝐹𝐹 represents the surface-potential parameter. 𝑇𝑇 𝐵𝐵𝑇𝑇 is the body voltage. �2Φ 𝐹𝐹 (𝑇𝑇 𝐺𝐺𝑇𝑇 -𝑇𝑇 𝑚𝑚ℎ ) 2 𝑇𝑇 𝐵𝐵𝑇𝑇 Without the coupling voltage noise, the body voltage would be zero. Therefore, the noise can result in the variation of saturation current.

In order to get the noise body voltage 𝑇𝑇 𝐵𝐵𝑇𝑇 , MNA (modeified nodal analysis) is employed using the equivalent circuit model shown in the previous figure. As said in the second chapter, the TSV resistance Rtsv is calculated by

𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 = �( 𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 ℎ 𝜋𝜋𝑅𝑅 𝑚𝑚 2 ) 2 + ( ℎ 𝜋𝜋𝜋𝜋 𝑇𝑇𝑇𝑇𝑇𝑇 𝛿𝛿(2𝑅𝑅 𝑚𝑚 -𝛿𝛿)
) 2 (5-125)

Where

𝛿𝛿 = � 𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋𝜇𝜇 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋
(5-126)

𝛿𝛿 is the skin depth; f is the frequency; 𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 , h, 𝑅𝑅 𝑚𝑚 and 𝜎𝜎 𝑇𝑇𝑇𝑇𝑇𝑇 are the resistance, height, radius and conductance of TSV; TSV inductance 𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 is expressed as

𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝜇𝜇 0 ℎ 2𝜋𝜋 [ln � ℎ+�ℎ 2 +𝑅𝑅 𝑚𝑚 2 𝑅𝑅 𝑚𝑚 � + 𝑅𝑅 𝑚𝑚 -�ℎ 2 + 𝑅𝑅 𝑚𝑚 2 ]
(

The oxide liner capacitance Cox, and MOS effect induced depletion capacitance Cdep are calculated by

𝐷𝐷 𝑜𝑜𝑜𝑜 = 2𝜋𝜋𝜀𝜀 𝑜𝑜𝑜𝑜 ℎ ln ( 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜 𝑅𝑅 𝑚𝑚 ) (5-128)
𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 𝑠𝑠𝑠𝑠 ℎ ln ( 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜 +𝑤𝑤 𝑑𝑑𝑑𝑑𝑑𝑑 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜 ) (5-129)
𝑤𝑤 𝑑𝑑𝑑𝑑𝑑𝑑 = � 4𝜀𝜀 𝑠𝑠𝑠𝑠 𝑘𝑘𝑇𝑇 𝑞𝑞 2 𝑁𝑁 𝑎𝑎 ln ( 𝑁𝑁 𝑎𝑎 𝑙𝑙 𝑠𝑠 ) (5-130)
Where 𝑡𝑡 𝑜𝑜𝑜𝑜 and 𝜀𝜀 𝑜𝑜𝑜𝑜 are respectively the thickness and permittivity of oxide liner; 𝑤𝑤 𝑑𝑑𝑑𝑑𝑑𝑑 is the thickness of the depletion layer [START_REF] Engin | Modeling of crosstalk in through silicon vias[END_REF]; k is the Boltzmann's constant; T is the absolute temperature; q is the electronic charge; 𝑁𝑁 𝜋𝜋 is the doping concentration of silicon; 𝑛𝑛 𝑖𝑖 is the intrinsic carrier concentration.

The silicon substrate capacitance Csub and conductance Gsub can be calculated by [START_REF] Engin | Modeling of crosstalk in through silicon vias[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits ) 2 -1)

(5-131)

𝐺𝐺 𝑠𝑠𝑡𝑡𝜋𝜋 = 𝜋𝜋 𝑠𝑠𝑠𝑠 𝜀𝜀 𝑠𝑠𝑠𝑠 𝐷𝐷 𝑠𝑠𝑡𝑡𝜋𝜋 (5-132)
Where 𝜎𝜎 𝑠𝑠𝑖𝑖 and 𝜀𝜀 𝑠𝑠𝑖𝑖 are the conductivity and permittivity of silicon respectively; 𝑑𝑑𝑆𝑆𝑡𝑡𝑐𝑐ℎ is the distance between TSV and transistor.

The time-domain simulation setup method is also given in Figure 121. Here, OP, the observing point, represents the body of transistor. Vin is the input pulse signal of 1 V and 1 Gb/s with rise time of 100 ps. Another end of TSV is terminated by a 50 ohms resistor. The load at OP is a resistance R of 225 ohms representing the on-resistance of an NMOS device in parallel with a capacitance C of 9.6 fF emulating the total capacitance including p-n junction, wire, and gate capacitances [START_REF] Gu | Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology[END_REF].

5.6.2) Investigations method of thermo-mechanical noise impact

TSV induced thermo-mechanical stress appears in surrounding silicon substrate due to the mismatch of CTE between TSV metal and silicon, when the structure is subjected to a thermal ramp in the process flow. The saturation current of transistors can be adversely affected by the TSV-induced thermomechanical stress, since the carrier mobility is modified due to piezo-resistive effect.

The work [START_REF] Yin | Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone[END_REF] [99] has studied the impacts of thermo-mechanical stress induced by TSV on carrier mobility. Here, we describe simple but enough updated information for the method of estimating thermomechanical impact of TSV. The saturation current change ∆𝐼𝐼 𝑠𝑠𝜋𝜋𝑡𝑡 𝐼𝐼 𝑠𝑠𝜋𝜋𝑡𝑡 ⁄ can be estimated by [START_REF] Athikulwongse | Impact of mechanical stress on Yue MA 2018 240 the full chip timing for through-silicon-via-based 3-D ICs[END_REF] [245] [START_REF] Yin | Effectiveness of p+ Layer in Mitigating Substrate Noise Induced by Through-Silicon Via for Microwave Applications[END_REF] [254]

∆𝐼𝐼 𝑠𝑠𝑎𝑎𝑚𝑚 𝐼𝐼 𝑠𝑠𝑎𝑎𝑚𝑚 ≈ ∆𝜇𝜇 𝜇𝜇 (𝑟𝑟, 𝜃𝜃) = Π × 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑠𝑠𝑖𝑖 (𝑟𝑟) × 𝛽𝛽(𝜃𝜃) (5-133)
where 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑠𝑠𝑖𝑖 is the TSV-induced radial stress; 𝜇𝜇 is the mobility of substrate. 𝛽𝛽(𝜃𝜃) represents orientation factor; 𝜃𝜃 is the angle between transistor channel and radial stress induced by TSV. 𝜃𝜃 = 0° and 90° mean the transistor Drain and Source channels are parallel and perpendicular to TSVinduced radial stress respectively [START_REF] Yin | Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone[END_REF]; Π is the piezo-resistive coefficient at 𝜃𝜃 = 0°, which works as longitudinal stress. For nMOS, Π = -31 × 10 -11 𝑃𝑃𝑎𝑎 -1 , 𝛽𝛽(0°) = 1 , 𝛽𝛽(90°) = 0.5 , for pMOS, Π = 71.8 × 10 -11 𝑃𝑃𝑎𝑎 -1 , 𝛽𝛽(0°) = 1, 𝛽𝛽(90°) = -0.6. [START_REF] Wang | An effective approach of reducing the keep-out-zone induced by coaxial through-silicon-via[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 166 The considered linear elastic body in this model consists of TSV filler (Cu, labeled as M), an insulating layer (SiO2, labeled as I), and a wafer (Si, labeled as W). The Cu filler is in 0 < r < R1, SiO2 is in R1 < r < R2, and Si is in R2 < r < Rsi. Due to the cylindrical form of TSV, we use the cylindrical coordinates (r, ϕ, z) in the analysis. The related parameters such as the shear modulus μ, Poisson's ratio ν, and the CTE (constant of thermal expansion) α are listed in the Figure 122.

The following notations are used: 𝑠𝑠 𝑖𝑖 𝑃𝑃 is the displacement vector; 𝑑𝑑 𝑖𝑖𝑗𝑗 𝑃𝑃 is the elastic strain tensor; 𝜎𝜎 𝑖𝑖𝑗𝑗 𝑃𝑃 is the stress tensor; P = M, I or W; i, j = r, φ, z. Due to the symmetry, the displacement vector 𝑠𝑠 𝑖𝑖 𝑃𝑃 can be written as follows [START_REF] Berto | Three-dimensional linear elastic distributions of stress and strain energy density ahead of V-shaped notches in plates of arbitrary thickness[END_REF] 𝑠𝑠 𝑟𝑟 𝑃𝑃 (𝑟𝑟) = 𝑠𝑠 𝑃𝑃 (𝑟𝑟) +∝ 𝑃𝑃 (𝑇𝑇 2 -𝑇𝑇 1 )𝑟𝑟 (5-134)

𝑠𝑠 𝜕𝜕 𝑃𝑃 (𝑟𝑟, 𝑧𝑧) = 𝜕𝜕 ℎ 𝑤𝑤 𝑃𝑃 (𝑟𝑟) +∝ 𝑃𝑃 (𝑇𝑇 2 -𝑇𝑇 1 )𝑧𝑧 (5-135) 𝑠𝑠 𝜕𝜕 𝑃𝑃 (𝑟𝑟) = 0 (5-136)
where 𝑟𝑟 = 0.5 * D (D is the wafer thickness), and 𝑠𝑠 𝑃𝑃 (𝑟𝑟) and 𝑤𝑤 𝑃𝑃 (𝑟𝑟) are functions to be solved. The nonzero components of the elastic strain tensor 𝑑𝑑 𝑖𝑖𝑗𝑗 𝑃𝑃 are determined as follows:

𝑑𝑑 𝑟𝑟𝑟𝑟 𝑃𝑃 = 𝑑𝑑𝑡𝑡 𝑃𝑃 𝑑𝑑𝑟𝑟 , 𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 = 𝑡𝑡 𝑃𝑃 𝑟𝑟 , 𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 = 𝑤𝑤 𝑃𝑃 ℎ , 𝑑𝑑 𝑟𝑟𝜕𝜕 𝑃𝑃 = 𝜕𝜕 2ℎ 𝑑𝑑𝑤𝑤 𝑃𝑃

𝑑𝑑𝑟𝑟

(5-137)

The stresses 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑃𝑃 are related with the elastic strains 𝑑𝑑 𝑖𝑖𝑗𝑗 𝑃𝑃 by Hooke's law First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits

5.7) Results and discussion

Based on the study method in the previous two sections, the relative changes of saturation current caused by the coupling noise, thermo-mechanical stress, and combination of the two aspects can be obtained, as shown in following Figure 123(a). According to the current technology, the parameters used in this simulation are selected as follows. The height and radius of TSV are 50um and 2.5um, respectively; the thickness of oxide liner around TSV is 0.1um; the conductivity of TSV is 5.8e7 S/m. The oxide liner and silicon have relative permittivity 3.9 and 11.9, respectively. The conductivity and doping concentration of the p-type silicon substrate is 10 S/m and 1.25e15 cm -3 , respectively. Here a 22nm nMOS is used. According to the predictive technology model First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 168 [START_REF]Nanoscale Integration and modeling (NIMO) Group[END_REF], the body doping concentration at the depletion region boundary between the channel and the body in a 22-nm technology node is 5.5e18 cm -3 , the thickness of gate oxide is 1.1nm, the environment temperature is fixed to 300K. The body effect γ and surface potential 2𝜙𝜙 𝐹𝐹 can be expressed by: [START_REF]Nanoscale Integration and modeling (NIMO) Group[END_REF] 𝛾𝛾 = 𝑡𝑡𝑜𝑜𝑜𝑜_𝑙𝑙𝑚𝑚𝑜𝑜𝑠𝑠 𝜀𝜀 𝑜𝑜𝑜𝑜 �2𝑞𝑞𝜀𝜀 𝑠𝑠𝑖𝑖 𝑁𝑁𝑠𝑠𝑠𝑠𝑏𝑏 (5-145)

2𝜙𝜙 𝐹𝐹 = 2𝑘𝑘𝑇𝑇 0 𝑞𝑞 𝑙𝑙𝑜𝑜𝑙𝑙( 𝑁𝑁𝑠𝑠𝑡𝑡𝜋𝜋 𝑙𝑙𝑖𝑖 ) (5-146)
Because the piezo-resistive coefficient is negative for NMOS, the thermo-mechanical stress leads to a decrease of the saturation current. While the coupling noise has an opposite impact on the variation of saturation current. Therefore, the two aspects are counteracted each other to a certain extent. In order to compare the two impacts clearly, Figure 123(a) gives the absolute value of the thermo-mechanical impact on saturation current. It is shown in Figure 123(a) that, as the distance between TSV edge and transistor is smaller than 5um, the thermo-mechanical stress plays a major role in the variation of saturation current. As the distance is larger than 5um, the electrical coupling noise is major. The Keep-out zone (KOZ) [START_REF] Guo | Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology[END_REF], [START_REF] Guo | Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime[END_REF], [START_REF] Wolf | Expected Failures in 3-D Technology and Related Failure Analysis Challenges[END_REF] is defined as the region with a change of saturation current over 5% [START_REF] Wang | Thermo-mechanical performance of Cu and SiO2 filled coaxial through-silicon-via (TSV)[END_REF], [START_REF] Ayala | Thermal modeling and analysis of 3D multiprocessor chips[END_REF], [START_REF] Wang | Design and realize of 3D integration of a pressure sensor system with through silicon via (TSV) approach[END_REF], [START_REF] Pedram | Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods[END_REF]- [START_REF] Tewari | Electro-Thermal Design of a Heat Pipe Based High Power Voltage Source Converter Using Emitter Turn-Off Thyristor[END_REF], meaning the region where devices cannot be made, since transistor performance is adversely affect. The KOZ results are summarized in Figure 123(b). It is shown that, KOZ is 25um and 1um for individual electrical impact and thermo-mechanical impact, respectively. Nevertheless, KOZ should be 21um considering the combination impact of the two aspects. The error reaches more than 50% if only individual electrical impact or thermo-mechanical impact is considered. Therefore, it is necessary to take both electrical and thermo-mechanical impacts into consideration for KOZ evaluation.

In this section, the research method is used for the typical situation, and it can also be applied to other conditions, such as, PMOSFET (and then CMOS imagers [START_REF] Arabi | 3D VLSI: A scalable integration beyond 2D[END_REF], [START_REF] Casu | Design and Fabrication of High-K Filled Sub-IOO nm Gap Resonators with Embedded Dielectric Field Effect Transistor for Ultra High Frequency Applications[END_REF], [START_REF] Zhang | A block-diagonal structured model reduction scheme for power grid networks[END_REF]), FinFETs, other parameters of NMOS, TSV and even CNFET (Carbon Nanotube FET, University Stanford [START_REF]Stanford Virtual-Source Carbon Nanotube Field-effect Transistors Model[END_REF]). But in compare with the CMOS components, TSV has slightly influence to CNFET.

A representative CNFET structure is shown in Figure 124(a): a cylindrical gate-all-around structure with heavily doped source/drain extensions. Throughout this part, Vgs(i) and Vds(i) denote the voltages across the gate to the (internal) source and the (internal) drain, respectively, as shown in the corresponding transistor schematic in Figure 124 As shown in Figure 125, Id increases as Vgs becomes small due to the increase in inter-band direct source-to-drain tunneling current.

The KOZ noise consideration method can also be taken into account in the vs-CNFET model, but because that the CNTs sit on a thick insulator (e.g. SiO2), so the body terminal is assumed to have no effects. So the TSV electrical parasitic has no influence to the Idsat of vs-CNFET, and the piezo-resistive effect has a great influence to the carrier mobility μ, as shown in the electromechanical part, which is directly related with the thermo-mechanical noise.

In order to have the same relationship: As we can see here, when the 𝜇𝜇 is below 200𝑐𝑐𝑚𝑚 2 /𝑇𝑇𝑠𝑠, the Idsat change linearly with 𝜇𝜇, but when 𝜇𝜇 gets higher, it has nearly no influence to Idsat. So that's to say, when the carrier mobility is below 200𝑐𝑐𝑚𝑚 2 /𝑇𝑇𝑠𝑠, we will have the relationship of equation But the carrier is found in the CNTs, which are isolated from substrate by a layer of oxide. So one more time, the CNFET is isolated from the thermo-mechanical noise. That's to say that, even we put TSV very close to CNFET, it has no electrical and thermos-mechanical noises to the saturation current.

TSV has two aspects of impact on the saturation current of transistor. On one hand, TSV induces coupling noise to surrounding transistors due to current pathway composed by the parasitic parameters of the structure. On the other hand, TSV induces thermo-mechanical stress owing to the thermal ramp in the process flow. We don't limit to the CNFET, in this later part, we deal with a simple NMOS example, which is part of the CMOS imager of the final demonstrator, by taking NMOSFET for instance, the electrical impact of TSV on the saturation current of transistor is studied based on the equivalent circuit model, and the thermo-mechanical impact is analyzed based on the piezo-resistive effect. Then the combinative impact of the two aspects is investigated. It is shown that, the coupling noise and thermo-mechanical stress have opposite impacts on the variation of saturation current. KOZ has an error of more than 50% if only one aspect is considered. The study method is also appropriate for PMOSFET and other situations.

5.8) Conclusion

Modeling in 3D noise, even 2D, is, for the most part, a failure due to physical modeling problems: for example, discerning the hole and electron contribution to noise in devices. Master equations, like the Boltzmann equation, associated with second order instances, should be developed more for theoretical study of noise.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 173

For submicronic devices, new effects, like non-stationary electro-thermal phenomena, crop up. By reducing the length of a device to some mean free paths, each carrier undergoes very few collisions on its path from one electrode to another. Another example is correlation of noise sources in space, which, are not independent, even though autonomous. Moreover, intensities of noise can increase during voltage ramp applied to a circuit. Other investigations must be made, in the case of the following points:

• Quantum phenomena: duration of carrier collisions versus energy exchange with phonons.

• Proposing rigorous techniques or methods of noise reduction, although it is subtler than it seems in this ambiguous domain.

The program, to be developed in the future, could focus on the following main areas:

• Continuing basic studies on microscopic behavior of noise sources up to 3D, with theories and experiments, in order to have a better understanding of phenomena.

In this configuration, connecters (especially TSVs), substrate and devices are deeply entangled. Study submicronic, nano-metric transistors, used for high speed logic in information technology. The objective is to study, for instance, the 1/f noise and the RTS (Random Telegraphic Signal) noise, in order to better understand ultimate (Bi-)CMOS, and develop compact electric models of device noise to correctly and fully simulate the behavior of these devices and the related circuits.

High speed III-V transistors (HEMT and HBT), as important elements of future high-frequency broadband telecommunication systems. Low frequency analyses (1/f and RTS noise) and high frequency noise (G-R) will be conducted on semiconductor devices and material (bulk, epitaxial layers, and flexible electronics).

Noise in photoelectric detectors and lasers, particularly in multi-quantum well structures, for high speed, optoelectronics and gigabit communications.

Sensors, in particular those using magnetic effects.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 175

We combine switching frequency and electro-thermal effects together. And, by comparing with S parameters, we found out that the electro-thermal effects appear only when S parameters change dramatically, and the reduction of thermal resistance and the increase of doping concentration of substrate will restrain the electro-thermal signal integrity problem.

The chapter 4 presents the flat heat pipe simulation. As a solution to the local heat dissipation, the passive heat dissipation component, flat heat pipe (FHP) is proposed as a prospective component in the chapter 4. The FEM based model (COMSOL Multiphysics) is very accurate in the 2D and 3D simulation of heat pipe. Precise boundary conditions can be found in this chapter; it considers the pressure field in the calculation, and especially it can extract the capillary pressure directly from the model, which will be very useful in the future study of wick layer's capillary effects. And an extensive study of the working performance limiting condition has been presented in this part.

The chapter 5 firstly proposes the analytical solution for the substrates non-stationary noise distribution and presents some noise analysis methods. And this chapter investigates also the keepout-of-zone (KOZ) of TSV to transistor, like nMOS and CNFET. The investigation methods of electrical noise impact and thermo-mechanical noise impact show large influence to nMOS like device (pMOS, pFET and nFET). But for CNFET, due to the highly isolation between carbon nanotube and substrate, the parasitic effect of TSV has no influence to it.

To conclude, this work can, in addition to realizing the electrical, thermal and electro-thermal modeling of single TSV, TSV matrix and multi-layers 3D IC, clarify the features constrains and coupling noise processes involved in multi-layers substrate, and also give the EDA design tools. But much remains to be done, a complex real case should be studied. (cf. CMOS imager, NMR system, etc.) Extension of this work will concern a M3D (3D Monolithic) electro-thermal modeling, which can directly realize nanoscale device level design (a CMOS inverter can be obtained in nanoscale by connection of a pMOS and nMOS with a M3D). And more RF devices can be generated by using TSV or M3D technology in micro and nano scale; for example, micro RF antenna with TSV, TSVs based thermal coupler, TSV or M3D based logic cell, and other 3D sensors.

Recently the research of 3D IC has extended to optic-electrical design. So one of the future research interest will be the EDA co-design of optic-electronic. But this will be kind of useless, because that in the optical application, the substrate and transmission medium are always glasses, and in this case, the parasitic effects are always negligible, in micro scale. But due to the high speed transmission signal, the optical circuits can be easily overheated. So the optic-electrical-thermal co-design will be one important and interesting work in the future.

One of the hot subject in the research is the neuromorphic chip. Brain-inspired, spike-based computation in electronic systems is being investigated for developing alternative, nonconventional computing technologies. The AI (Artificial Intelligence) chip, which is the best way First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 176 to integrate learning algorithm with hardware design. The Neural Engineering Framework provides a method for programming these devices to implement computation. [START_REF] Corradi | Mapping arbitrary mathematical functions and dynamical systems to neuromorphic VLSI circuits for spike-based neural computation[END_REF] The most interesting part for 3D IC design is that, if we can implement a mixed signal analog/digital neuromorphic multi-neuron VLSI chip into a 3D chip and imitate the brain structure, we will have a better understanding of human's learning system.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits

C CPW C l Z l A B ABCD l Z l C D γ γ γ γ     = =        
Where l is the length of CPW

The characteristic impedance is:

C B Z C =
The propagation constant is:

B.2) De 2D IC à 3D IC

Comme l'illustre la Figure B2 a, un système informatique traditionnel de von Neumann est en fait l'intégration hétérogène de puces logiques MPU (jaune), de puces de mémoire (orange) et d'interconnexions de puce à puce (grise). Par exemple, ici, la donnée A enregistre les données de l'électronique RF, la donnée B enregistre les données des capteurs de la caméra, le processus DRAM a une densité de mémoire 10 fois plus élevé que le processus logique de la même génération. Le cache dans l'unité MPU est donc trop petit pour l'implémentation de la mémoire, et les données doivent inévitablement être déplacées à travers l'interface à haute énergie entre la logique et la mémoire, deux fois par répétition (comme le montre la ligne verte).

B.3) Feuille de route pour les circuits intégré3D

Le problème aujourd'hui est que on continue à augmenter la densité de transistors par cm 2 à la même vitesse ou à un rythme plus rapide que la loi de Moore. Les dimensions horizontales atteindront un point où aucune réduction horizontale ne sera possible, et le développement des transistors verticaux et l'intégration des couches de transistors verticaux apparaissent.

La feuille de route IRDS 2017 (Feuille de route internationale pour le développement et le système) prévoit la technologie des circuits intégrés de pointe pour chaque année ou pour les 15 prochaines années. La Figure B5 en offre un aperçu [2]. Comme vous pouvez le voir, une échelle de densité 2D efficace selon la loi de Moore est prédite jusqu'au milieu des années 2020, après quoi les avancées viendront de la densité 2D multipliée par le nombre de couches ou la projection de la densité 3D sur une surface 2D. Cette mise à l'échelle réduira les coûts d'achat et de consommation d'énergie et fournira des avantages au niveau du système. [START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF] Cette évolution démontre que le point ultime de la mise à l'échelle est le 3D VLSI qui offre la possibilité d'empiler des dispositifs permettant des contacts à haute densité au niveau de VLSI du système (jusqu'à 100 millions de vias First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits  3D VLSI avec logique-sur-logique à pas fin ainsi que des couches de fonctions spéciales exploitant de nouvelles architectures

B.4) Développement des circuits intégrés 3D

Aujourd'hui, les producteurs de mémoire flash font face à un problème similaire parce qu'ils manquent d'espace horizontal, et le coût de production de circuits mémoire intégrés de petites dimensions ne cesse d'augmenter tandis que le nombre d'électrons stockés dans la porte flottante ne cesse de diminuer. Pour éliminer ces problèmes, les producteurs de mémoire flash ont déjà démontré et annoncé plusieurs nouveaux produits qui empilent plusieurs couches de mémoire les unes sur les autres dans un seul CI. Jusqu'à 32 et 48 couches de mémoire flash ont été signalées.

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 186

Le Table 2 montre que les dispositifs de mémoire flash avec plus de 100 couches ont été prédits. L'élimination de la chaleur et la réduction de la puissance seront donc les deux principaux défis de la mise à l'échelle 3D. Au-delà de 2020, l'architecture des futurs IC changera en un type de structure similaire à celui de la Figure B7. Cette nouvelle phase de mise à l'échelle, capable d'ajouter des couches multiples au niveau des dispositifs 3D, peut considérablement accélérer la loi de Moore. La recherche sur de nouveaux commutateurs a débuté en 2005. En 2010, le tunnel FET (TFET) semble être un substitut potentiel au MOS, comme le montre la Figure B8, en raison de sa faible puissance de fonctionnement. [START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF] La capacité négative FET (NC FET) est également consideré comme un autre concept qui a une performance de puissance mieux que MOS. Les nanotubes de carbone (nanotubes de carbone) [START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF], [START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF] sont devenus l'interrupteur le plus viable au cours de la prochaine décennie, en raison de ses performances et ses économies d'énergie [START_REF] Shulaker | Carbon nanotube computer[END_REF]. Le nombre de transistors pouvant être intégrés sur une surface de 1 cm 2 de silicium continuera de croître au rythme de la loi de Moore pour les 10 prochaines années et au delà grâce à l'intégration 3D. Jusqu'à présent, la vitesse du First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 187 transistor a continué d'augmenter pendant cette décennie, et sa fréquence de fonctionnement aurait atteint 100 GHz si la dissipation de puissance n'était pas un problème. En raison des limites de dissipation de puissance des circuits intégrés, la fréquence de fonctionnement est limitée à quelques GHz (Intel Core i9 4.2 GHz). Ainsi, au cours de la prochaine décennie, l'objectif de la conception de circuits intégrés est changé de la conception de haute fréquence à une conception faible puissance avec une meilleure conception de la dissipation thermique. L'intégration et l'encapsulation tridimensionnels (3D) ont été couronnés de succès dans les dispositifs traditionnels pour augmenter la densité logique et réduire les distances de transmission des données. Cela résout les limites fondamentales de la mise à l'échelle, par ex. retard croissant dans les interconnexions [START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF], coûts de développement et variabilité [START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF]. La plupart des périphériques de mémoire livrés aujourd'hui comportent une forme 3D. L'intégration 3D utilise différentes technologies, ils sont wire-bonding et flip-chip pour SiP (Silicon in Package), TSV(Through Silicium Via) en substrat, TSV en SOI (Silicium sur isolant), 3D parallèle, 3D séquentiel (MIV inter-monolithique).

Dans la conception de niveau micro (> 2um), il existe deux types de méthode d'interconnection, wire-bonding et flip-chip. La typique technologie de l'interconnection est le wire-bonding. Le wirebonding, comme représenté sur la Figure B10(a), a une faible densité, une faible bande passante, une latence élevée et une haute dissipation de puissance (les nombres exacts peuvent être trouvés dans le tableau 1 précédent). Le TSV est le via vertibal qui peut traverser le substrate directement. TSV en substrate est la technologie d'interconnection directe entre les puces, qui est la technologie principale dans l'industrie, car ils n'ont pas besoins de changement substantiel au flux de fabrication existant, comme le montre la Figure B10 En dessous de 1um, dans ce domaine, l'intérêt de la technologie 3D reste à la conception de l'échelle des transistors. La Figure B9 montre la précision d'alignement entre les couches de transistors empilés en ce qui concerne la largeur de contact 3D (pitch). L'intégration parallèle 3D [START_REF] Topol | Enabling SOIbased assembly technology for three-dimensional (3d) integrated circuits (ICs)[END_REF], [START_REF] Philip | Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits[END_REF] (Figure B10(c)) permet la réduction continue après 3D TSV, la réduction de la hauteur a été réduite à 1µm. Mais même si certaines architectures 3D SOI (silicium sur isolant) peuvent réduire la taille de contact 3D, le pas de contact 3D reste toutefois limité par la performance d'alignement, limitée à environ 1µm, pour garantir un débit correct.

L'intégration séquentielle 3D est la prochaine génération de technologies d'intégration 3D, elle est aussi appelée 3D monolithique (M3D) [1]- [4], [START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF], [START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF], [START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF], [START_REF] Chang | Design Automation and Testing of Monolithic 3D ICs : Opportunities , Challenges , and Solutions[END_REF], [START_REF] Koneru | Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits[END_REF], [START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF], [START_REF] An | Electrical Modeling and Analysis of 3D Neuromorphic IC with Monolithic Inter-tier Vias[END_REF]- [START_REF] Arabi | 3D VLSI: A scalable integration beyond 2D[END_REF]. Il a été démontré que les interconnexions 3D et les pas de contact planaires correspondent même pour

B.5) Contexte

Cette nouvelle architecture montre que les performances de calcul peuvent encore être améliorées dans la prochaine décennie, et la puissance principale dépendra de l'intégration hétérogène 3D. L'avenir de l'industrie des semi-conducteurs est donc prometteur, et les découvertes futures continueront à apporter des progrès et à apporter de nouvelles avancées.

Cette thèse s'inscrit dans un très vaste projet mené par ST Microelectronics crolles et le CEA LETI de Grenoble, en collaboration avec 3IT (Institut Interdisciplinaire d'Innovation Technologique) et l'Université de Sherbrooke. Ce projet a pour but de concevoir et de produire un capteur d'image CMOS 3D [START_REF] Coudrain | 3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies[END_REF], et la conception du système de refroidissement de cet équipement est très importante; les problèmes de dissipation thermique dans le capteur d'image CMOS 3D peuvent être bloquants. Un autre démonstrateur (Figure B12) est en route. Ce démonstrateur applique la technologie de résonance magnétique nucléaire (RMN) / imagerie par résonance magnétique à l'échelle micro / nanométrique. Ces dernières années, les appareils portables RMN / IRM ont attiré l'attention de nombreuses équipes de chercheurs. Ils sont utilisés pour une variété d'applications, en particulier pour le diagnostic médical. Le schéma 3D de la puce micro / nano MNR est montré dans la Figure B12. Ce projet est piloté par une équipe de l'université de Lyon et la medical school New York [START_REF] Trejo Rosllo | Contribution à l'amélioration de la Sensibilité d'un Microrécepteur RMN Implantable[END_REF]. Comme nous le savons, la bobine réceptrice peut être facilement affecté par les bruits environnementaux; de plus, son bruit propre est exprimé en 4kRT; R est la résistance de la bobine. Donc, réduire le self-noise de la bobine signifie réduire cette résistance, par conséquences, augmenter le facteur de qualité Q, défini comme Q = ωL/R. Le SNR (rapport de signal / bruit) est un critère déterminant dans la miniaturisation de MNR / MRI des capteurs RMN. Le but de la thèse est donc de fournir une méthode de conception globale pour les circuits intégrés 3D : électrique, thermique, électrothermique aussi le bruit. Ci-après seront incluses des méthodes de simulation pour le substrat et également la connectivité relative (TSV, RDL(ligne de redistribution), Micro strip et circuits intégrés dans le substrat).

Le chapitre 2 présente quelques connaissances de base sur les effets parasitaires électriques des TSV. Basé sur des effets parasites, nous avons programmé sous Matlab un extracteur de substrat qui s'appele 3D-TLE (extracteur de ligne de transmission 3D), qui peut extraire automatiquement de tous les contacts; impédance, de forme arbitraire et de matériaux arbitraires. Cet extracteur est 100% compatible avec les simulateurs de noyau SPICE, comme ADS (Advanced design system). Les données extraites sont vérifiées avec des mesures et un résultat de simulation par la méthode des éléments finis (FEM). Basé sur des effets parasites du TSV, un RF filtre de fréquence 26 GHz et bande passante de 2 GHz est proposé dans ce travail.

Ainsi, le chapitre 3 propose une solution analytique pour la distribution de température non stationnaire du substrat multi-couches. Les problèmes thermiques sont de réels défis dans la conception de circuits intégrés 3D, en particulier lorsque nous réduisons à l'échelle nanométrique. La résistance électrique augmente avec la température, de même que la résistance du substrat. La plupart des travaux de simulation thermique sont basés sur les régimes stables; Peu de gens travaillent sur le cas non stationnaire. Les effets non stationnaires sont couplexes, comme les points chauds, qui peuvent être améliorés par des rampes de tension. Il propose également une méthode de calcul de dissipation thermique tridimensionnelle multi-couches 3D IC. Cette méthode est adaptée à tout circuit intégré 3D. Un cas de dissipation de chaleur CPU à 4 coeurs est étudié dans ce chapitre. La dernière partie de ce chapitre présente le fonctionnement de la simulation électrothermique. Le simulateur électrothermique peut être 100% compatible avec le simulateur SPICE (similaire), et la partie électrique est vérifiée avec ADS. Ce travail construit le cadre de l'analyse électrothermique 3D IC.

En tant que solution à la dissipation thermique locale, le composant dissipation de chaleur passive, caloduc plat (FHP) est proposé comme une composante prospective dans le chapitre 4. Ce chapitre présente l'approche de simulation FEM du FHP, ainsi que la modélisation analytique. Les deux résultats sont en bonne correspondance.

Le chapitre 5 propose tout d'abord la solution analytique pour la distribution du bruit non stationnaire des substrats et présente des méthodes d'analyse du bruit. Et ce chapitre étudie aussi le keep-out-of-zone (KOZ) de TSV au transistor. Les méthodes d'investigation de l'impact du bruit électrique et de l'impact du bruit thermo-mécanique sont présentées dans cette partie.

Enfin, le chapitre 6 résume les contributions de ces travaux de thèse, tirant des conclusions du manuscrit. A titre d'illustration, les figures ci-dessus montrent comment les deux lignes de masse sont décomposées en blocs sériels pour une chaîne 2xTSV. Les parties des lignes concernées par le trajet actuel sont modélisées en MI et les surfaces restantes en MII. La longueur totale du câble, Lground, est égale à 2Lpad, plus la longueur de la ligne BRDL, Lspace. Notez que Lspace correspond également à l'écart entre les deux plages de contact. La ligne BRDL délimitant les deux TSV est décrite par une capacité d'oxyde atteignant le noeud de substrat SUB où se trouvent les surfaces de la ligne de masse BEOL, correspondant à l'entrefer des plots de contact (MII).

En fonction de la manière dont les TSV sont connectés, la chaîne 2xTSV peut être vue comme une structure en "U". Pour les chaînes nxTSVs, n / 2 structures en "U" sont connectées au niveau BEOL par des plages de contact et des lignes d'accès de longueur 60μm quelle que soit la configuration.

La figure suivante montre la vue de profil d'une chaîne 4xTSV; les effets de proximité entre les quatre TSV sont également représentés. La longueur totale de la ligne de masse BEOL est donc égale à:

𝜔𝜔 𝐵𝐵𝐵𝐵𝐵𝐵𝐿𝐿 = 𝑛𝑛𝜔𝜔 𝑑𝑑𝜋𝜋𝑑𝑑𝑠𝑠 + 𝑙𝑙 2 𝜔𝜔 𝑠𝑠𝑑𝑑𝜋𝜋𝑙𝑙𝑑𝑑 + ( 𝑙𝑙 2 -1)𝜔𝜔 𝜋𝜋𝑙𝑙𝑙𝑙𝑑𝑑𝑠𝑠𝑠𝑠 (B-10).
Il illustre la décomposition des lignes de base en blocs de série dans le cas de la chaîne 4xTSV. La décomposition peut être étendue pour les chaînes comprenant un plus grand nombre de TSV.

B.7) Electro-thermal (ET) modeling of VLS circuits

Le cahier des charges pour les circuits intégrés (CI) impose une densité de puissance croissante et une tension d'alimentation décroissante, ce qui oblige les réseaux de distribution d'énergie (PDN) à fournir des courants plus importants [4], [START_REF] Devised | ITRS for semiconductor 2015[END_REF]. En conséquence, l'auto-échauffement dû à l'effet Joule et à l'activité de commutation de puissance [START_REF] Zheng | Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits[END_REF] est responsable d'une élévation de température de plus en plus importante qui affecte largement les performances électriques, en raison de la dépendance de la température de résistivité électrique [START_REF] Pedram | Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods[END_REF]. Par conséquent, une cosimulation électro-thermique (ET) efficace des grands PDN sur puce est aujourd'hui nécessaire, par exemple, pour donner une estimation correcte de la chute IR, fortement liée à la résistivité électrique. De plus, les co-simulations ET sont inévitables si l'intégration verticale 3D est envisagée, étant donné les courants croissants dans ces systèmes comparés aux 2D et la densité de flux thermique croissante due à l'empilement vertical [START_REF] Xie | Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and joule heating effects[END_REF] [START_REF] Todri | A study of tapered 3-D TSVs for power and thermal integrity[END_REF].

Dans ce travail, nous présentons des techniques de réduction pour la co-simulation ET de grands PDN, sur la base du concept de clustering de noeuds. La stratégie de réduction est ensuite mise en oeuvre en définissant des ''macro-noeuds'', à partir d'un critère selon lequel les interactions locales entre deux noeuds du modèle original pourraient être négligées. Après avoir choisi une définition correcte des niveaux de quantification pour les plages de température et de chute de tension, les noeuds sont classés en sous-ensembles. Ensuite, les sous-ensembles sont réduits à des ''macro-noeuds'', et les éléments de connexion entre eux sont calculés en conséquence. Une telle First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 200 procédure permet une réduction drastique de l'ordre du système, tout en assurant une bonne précision.

Nous considérons une structure standard pour les réseaux de masse et de puissance comme représenté sur la Figure B21. Les deux réseaux conducteurs sont séparés par une couche d'isolation, et connectés aux broches d'alimentation VDD et GND, respectivement, par une impédance série Zsupply aux quatre coins de l'élément de base (cachet) des noeuds nxn sur la grille. La puce entière est obtenue en tant que répliques mxm d'un tel tampon. La puce est connectée d'un côté à un dissipateur thermique, à des fins de dissipation thermique.

Les problèmes électriques et thermiques doivent être résolus conjointement dans l'analyse statique (et éventuellement dynamique). Une modélisation adéquate de la puce, du point de vue thermique et électrique, sera fournie et justifiée, en référence à toutes les possibilités technologiques envisagées tout au long de ce travail de thèse. Les principales sources de chaleur dans la structure sont associées à l'activité du circuit (commutation des portes logiques), ainsi qu'aux effets Joule dans les interconnexions PDN. Il existe une dualité bien connue entre les modèles thermique et électrique, où le flux de chaleur joue le rôle d'un courant électrique et la différence de température correspond à la tension électrique. De cette manière, l'équivalence électrothermique classique peut être exploitée de manière appropriée pour une co-simulation conjointe du problème physique, dans le même solveur de circuit. [START_REF] Duong | A Battery-Assisted Passive EPC Gen-2 RFID Sensor Tag IC with Efficient Battery Power Management and RF Energy Harvesting[END_REF]- [START_REF] Pares | Image sensor evolution and enabling 3D technologies[END_REF] Une analyse dynamique est ensuite effectuée (à température donnée par la solution du modèle électrothermique statique précédent) pour étudier plus en détail: (i) les effets de la chute de tension supplémentaire due aux éléments dynamiques; (ii) si le niveau de puissance thermique supplémentaire dans la structure est toujours compatible avec l'équilibre thermique statique supposé. Il est réalisé via une approche classique d'analyse de domaine fréquentiel, en considérant le circuit d'impédances correspondant à une fréquence donnée.

Cette approche est basée sur deux faits fondamentaux: (i) en raison de la linéarité du (sous-) modèle électrique, la superposition s'applique aux tensions et aux courants évalués à différentes fréquences (y compris DC); (ii) les puissances moyennes électriques calculées à différentes fréquences peuvent être additionnées, en raison de leur "orthogonalité". En réglant correctement la gamme de fréquences d'intérêt pour le cas considéré, une analyse de fréquence exhaustive est facilement réalisée, à un temps de calcul abordable.

Enfin, on peut noter qu'une analyse dynamique électrothermique totalement cohérente, si nécessaire, peut être poursuivie dans les mêmes hypothèses de modélisation, en exploitant la linéarité de chaque (sous-) modèle, dans un nouveau cycle de relaxation, où le DC et La contribution AC à la puissance thermique moyenne est prise en compte en même temps. Les changements de résistivité et de température se traduisent par un processus itératif, qui converge lorsqu'il n'y a plus de changement de tension et de distribution de température. Vous notez que l'analyse thermique est basée sur une analyse en régime permanent pour déterminer la distribution de température sur chaque niveau pour un profil de puissance donné. Il est limité à la caractérisation de la distribution thermique dynamique à des profils de puissance variables. Cependant, comme nous visons à déterminer rapidement et avec précision la distribution de température sur chaque niveau pour un profil de puissance donné, l'analyse thermique 1-D est une approche viable. Nous utilisons des modèles mathématiques tels que décrits dans la partie précédente et des méthodes avancées de traitement numérique pour réaliser des analyses efficaces de réseaux puissance / masse et thermique.

B.8) Simulation de micro-caloduc

Les caloducs plats micro / nano sont une technologie de transfert de chaleur passive efficace dans le refroidissement du flux thermique élevé dans les appareils électroniques tels que les puces informatiques, en raison de leur conductivité thermique élevée, de leur fiabilité et de leur faible poids. Un caloduc plat est une chambre fermée dont la surface interne est recouverte d'une structure de mèche capillaire, le volume restant contenant la vapeur. Les sources de chaleur et les puits de chaleur sont situés sur la chambre, les autres parties étant isolées thermiquement. Le fluide de travail est vaporisé par la source de chaleur au niveau de l'évaporateur, et la différence de pression générée conduit la vapeur de l'évaporateur au condenseur, où elle se condense et pénètre dans les structures de mèche. La pression capillaire dans la mèche refoule le liquide condensé vers l'évaporateur où il est vaporisé. Cette circulation de changement de phase interne continuera tant que le passage d'écoulement n'est pas bloqué et qu'une pression capillaire suffisante est maintenue [START_REF] Faghri | Heat Pipe Science and Technology[END_REF]. Pour le refroidissement des appareils électroniques, les fluides de travail les plus couramment utilisés sont l'eau, l'acétone, l'éthanol ou le méthanol [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF], [START_REF] Yadavalli | Flat heat pipe performance thresholds at ultra-thin form factors[END_REF], [START_REF] Zuo | A network thermodynamic analysis of the heat pipe[END_REF], [START_REF] Faghri | Review and Advances in Heat Pipe Science and Technology[END_REF], [START_REF] Luo | A novel flat micro heat pipe with a patterned glass cover[END_REF], [START_REF] Faghri | Heat Pipe Science and Technology[END_REF], [START_REF] Hopkins | Flat Miniature Heat Pipes With Micro Capillary Grooves[END_REF], [START_REF] Lin | High performance miniature heat pipe[END_REF], [START_REF] Carey | Liquid-vapor phase-change phenomena[END_REF], [START_REF] Soni | Performance analysis of bulk driven MOSFET and CNFET for low voltage applications[END_REF] Des investigations sur les caloducs plats ont été menées pour caractériser les performances thermiques et hydrodynamiques des micro-caloducs utilisés pour le refroidissement de l'électronique. Pour prédire les caractéristiques thermiques des caloducs, de nombreux chercheurs ont proposé des modèles théoriques simplifiés unidimensionnels [START_REF] Kim | Analytical and experimental investigation on the operational characteristics and the thermal optimization of a miniature heat pipe with a grooved wick structure[END_REF], [START_REF] Longtin | A One-Dimensional Model of a Micro Heat Pipe During Steady-State Operation[END_REF], [START_REF] Hopkins | Flat Miniature Heat Pipes With Micro Capillary Grooves[END_REF], [START_REF] Babin | Steady-State Modeling and Testing of a Micro Heat Pipe[END_REF], [START_REF] Lin | High performance miniature heat pipe[END_REF].

Dans le travail actuel, un modèle de chambre à vapeur à faible coût est développé, ciblant les géométries et les conditions de fonctionnement typiques des applications de gestion thermique. Le modèle prend en compte le transport de masse, de quantité de mouvement et d'énergie dans la paroi de la chambre de vapeur, la mèche et le noyau de vapeur, ainsi que le changement de phase à l'interface vapeur-vapeur. [START_REF] Patankar | A Time-Stepping Analytical Model for 3D Transient Vapor Chamber Transport[END_REF] Les configurations proposées des caloducs plats, constitués de la paroi, des mèches poreuses saturées de fluide de travail et de l'espace vapeur, sont illustrées à la Figure B34. La Figure B34a, b, c présente les quatre configurations de caloducs plats avec une seule source de chaleur, plusieurs Les propriétés du fluide de travail, du cuivre et des matériaux de mèche poreuse utilisés dans les simulations de la chambre à noyau de vapeur sont présentées dans le tableau 14 suivant. Les propriétés de la vapeur sont obtenues à une température de 40 °C. Les niveaux de température prédits par les approches de modélisation sont présentés à la Figure B35. La Figure B35 (a) montre la comparaison du profil de température le long de la direction x de la source de chaleur 50W entre les résultats obtenues par COMSOL et ceux de la publication Maziar Agnvami [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF]. Et enfin, la partie la plus importante du caloduc est la pression capillaire dans l'interface vapeur / mèche. La Figure B37 montre la pression capillaire à l'interface mèche / vapeur. Du côté de l'évaporation, l'eau est évaporée et la vapeur présente un gain de pression maximal de ce côté, mais du côté du condenseur, l'eau se condense et provoque l'écoulement de l'eau dans la mèche, ce qui nous permet de voir un processus contraire. La mèche présente un débit massique du côté de la condensation et une masse s'écoule du côté de l'évaporation, de sorte que l'eau s'écoule du côté de la condensation vers le côté d'évaporation, mais avec une vitesse beaucoup plus lente que le noyau de vapeur. À partir de la Figure B37, nous pouvons voir que les pressions capillaires de la configuration I de la simulation et de la publication COMSOL [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF] ont une différence maximale de 20%. Mais pour la configuration II, les pressions capillaires sont presque les mêmes. Et l'erreur est inférieure à 0,5% Un modèle pour le fonctionnement de la chambre à vapeur a été développé qui permet de multiples entrées de chaleur de forme arbitraire sur la face de l'évaporateur; le modèle prédit les champs 2D de la température, de la pression et de la vitesse dans la chambre à vapeur, sous réserve d'hypothèses concernant la taille de la chambre à vapeur, le débit de liquide et de vapeur et les propriétés du matériau. Les équations régissant la masse, le momentum et l'énergie dans les domaines de la paroi, de la mèche et de la vapeur ont été établies. Le modèle a été comparé à un modèle numérique [START_REF] Aghvami | Analysis of flat heat pipes with various heating and cooling configurations[END_REF].

B.9) Imfluences des bruits électriques et thermo-méchanic du through-silicon via (TSV) sur transistor

Du point de vue de l'aspect électrique, on s'intéresse aux bruits de substrat induits par les TSVs qui menacent la performance des transistors voisins en raison des connections parasites entre TSV et transistor [START_REF] Yin | Effectiveness of p+ Layer in Mitigating Substrate Noise Induced by Through-Silicon Via for Microwave Applications[END_REF]. Du point de vue thermomécanique, en raison de l'inadéquation inhérente du coefficient de dilatation thermique (CTE) entre le métal et le silicium, des contraintes thermomécaniques apparaîtront au voisinage de TSV, lorsque le système est refroidit de la température maximale localisée possible à la température ambiante [START_REF] Wang | Study on thermal stress and keep-out zone induced by Cu and SiO2 filled coaxial-annular through-silicon via[END_REF]. La mobilité des porteurs des transistors voisins serait influencée par la contrainte thermomécanique induite par les TSV due à l'effet piézorésistif [START_REF] Wang | Effects of coaxial through-silicon via on carrier mobility along [100] and [110] crystal directions of (100) silicon[END_REF]. Certains articles portent sur l'impact électrique et l'impact thermomécanique du TSV sur le transistor [START_REF] Yin | Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone[END_REF], [START_REF] Wang | Thermo-mechanical performance of Cu and SiO2 filled coaxial through-silicon-via (TSV)[END_REF], [START_REF] Lin | 3-D transient analysis of TSV-induced substrate noise: Improved noise reduction in 3-D-ICs with incorporation of guarding structures[END_REF], [START_REF] Kim | Effectiveness of a guard ring utilizing an inversion layer surrounding a through silicon via[END_REF]. En effet, les transistors au voisinage de TSV sont simultanément affectés à la fois par les bruits de couplage et par les contraintes thermomécaniques. Il n'y a pas eu de rapport sur l'effet de croisement de ces deux aspects. Nous étudions la combinaison des impacts électriques et thermo-mécaniques de TSV sur le courant de saturation du transistor en prenant un NMOSFET, par exemple [START_REF] Pares | Image sensor evolution and enabling 3D technologies[END_REF]- [START_REF] Zheng | Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits[END_REF]. La méthode d'étude est également appropriée pour le PMOSFET.

B.9.1) Method d'investigation du bruit électric

Le courant de saturation peut être affecté par le bruit induit par TSV à travers l'effet du bulk. Le courant de saturation 𝐼𝐼 𝑑𝑑𝑠𝑠𝜋𝜋𝑡𝑡 de NMOSFET peut être calculé par Où 𝑇𝑇 𝐺𝐺𝑇𝑇 représente la différence de tension entre la porte et la source du NMOSFET; W et L sont la largeur et la longueur de la porte, respectivement; Cox est la capacité entre la porte et le canal porteur; 𝜇𝜇 𝑙𝑙 est la mobilité des électrons; la tension de seuil 𝑇𝑇 𝑡𝑡ℎ peut être liée à la tension du bulk 𝑇𝑇 𝐵𝐵 [START_REF] Xu | Compact modeling and analysis of through-Si-Viainduced electrical noise coupling in three-dimensional ICs[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits La contrainte thermomécanique induite par le TSV apparaît dans le substrat de silicium environnant en raison du décalage de CTE entre le métal de TSV et le silicium, lorsque la structure est soumise à une rampe thermique dans le flux de processus. Le courant de saturation des transistors peut être affecté négativement par la contrainte thermomécanique induite par le TSV, puisque la mobilité du porteur est modifiée en raison de l'effet piézorésistif.

𝐼𝐼 𝑑𝑑𝑠𝑠𝜋𝜋𝑡𝑡 =
Le travail [START_REF] Wang | Thermo-mechanical performance of Cu and SiO2 filled coaxial through-silicon-via (TSV)[END_REF][24] a étudié les impacts du stress thermo-mécanique induit par le TSV sur la mobilité des porteurs. Ici, nous décrivons des informations simples mais suffisamment à jour pour la méthode d'estimation de l'impact thermomécanique de TSV. Le changement de courant de saturation ∆𝐼𝐼 𝑠𝑠𝜋𝜋𝑡𝑡 𝐼𝐼 𝑠𝑠𝜋𝜋𝑡𝑡 ⁄ peut être estimé par [START_REF] Athikulwongse | Impact of mechanical stress on Yue MA 2018 240 the full chip timing for through-silicon-via-based 3-D ICs[END_REF] ∆𝐼𝐼 La zone Keep-out (KOZ) est définie comme la région avec un changement de saturation de plus de 5% [START_REF] Ayala | Thermal modeling and analysis of 3D multiprocessor chips[END_REF], [START_REF] Wang | Thermo-mechanical performance of Cu and SiO2 filled coaxial through-silicon-via (TSV)[END_REF], [START_REF] Wang | Design and realize of 3D integration of a pressure sensor system with through silicon via (TSV) approach[END_REF], [START_REF] Pedram | Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods[END_REF]- [START_REF] Tewari | Electro-Thermal Design of a Heat Pipe Based High Power Voltage Source Converter Using Emitter Turn-Off Thyristor[END_REF], ce qui signifie la région où les périphériques ne peuvent pas être , puisque la performance du transistor est affectée. Les résultats de KOZ sont résumés dans la Figure B40 (b). Il est montré que KOZ est 25um et 1um pour l'impact électrique individuel et l'impact thermo-mécanique, respectivement. Néanmoins, KOZ devrait considérer l'impact combiné de ces deux aspects. L'erreur atteint plus de 50% si seul un choc électrique individuel ou un impact thermo-mécanique est pris en compte. Par conséquent, il est nécessaire de tenir compte des impacts électriques et thermomécaniques pour l'évaluation de KOZ.

B.10) Conclusion générale

Dans ce travail de thèse, nous avons développé une méthode de conception globale de circuits intégrés 3D dans le domaine électrique, thermique, électrothermique et aussi le bruit. Ci-après seront incluses des méthodes de simulation pour un seul TSV, une matrice TSV, un substrat multicouche, des multi-processeurs et une conception de dissipation thermique.

Nous présentons d'abord quelques connaissances de base sur les effets parasites électriques (effet MOS et effet de peaux) du TSV. Basé sur des effets parasites, nous avons programmé dans Matlab un extracteur de substrat qui s'appele 3D-TLE (extracteur de ligne de transmission 3D), qui peut extraire automatiquement de tous les contacts; impédance, de forme arbitraire et de matériaux arbitraires. Cet extracteur est 100% compatible avec les simulateurs de noyau SPICE, comme ADS (Advanced Design System). Les données extraites sont validées par des mesures et des résultats de simulation par la méthode des éléments finis (FEM). Basé sur des effets parasites du TSV, un RF filtre de fréquence 26 GHz et bande passante de 2 GHz est proposé dans ce travail.

Le chapitre 3 propose une solution thermique analytique pour la distribution de température non stationnaire du substrat multi-couches. Dans la conception 3D IC, les problèmes thermiques sont des problèmes bloquants, en particulier à l'échelle nanométrique. La résistance électrique augmente avec la température, de même que la résistance du substrat. La plupart des travaux de simulation thermique sont basés sur les régimes stables; Peu de gens travaillent sur le cas non stationnaire. Les effets non stationnaires sont couplexes, comme les points chauds, qui peuvent être améliorés par des rampes de tension. Nous combinons le modèle compact thermique 1D en utilisant MNA (analyse nodale modifiée) et la méthode de volume fini 2D (FVM) pour résoudre le calcul de température IC multicouche 3D, qui, en comparaison avec la simulation 3D FEM, réduit considérablement les complexités de calcul. Cette méthode est adaptée à tout circuit intégré 3D. En outre, un cas de dissipation de la chaleur des processeurs à 4 noyaux est étudié dans ce chapitre. La dernière partie de ce chapitre présente le fonctionnement de la simulation électrothermique. Le simulateur électrothermique peut être 100% compatible avec le simulateur SPICE (similaire), et la partie électrique est vérifiée avec ADS. La méthode MNA est normalement utilisée pour la conception de 3D PDN VLSI, mais ici, nous l'appliquons dans la simulation au niveau de l'appareil, à notre connaissance, ce point est unique et original. Ce travail fournit un cadre d'analyse First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 223 électrothermique pour le substrat, les connexions thermiques (via 3D) et le PDN 3D au niveau du système. Nous fournissons une étude approfondie des problèmes de puissance et de dissipation thermique dans l'intégration 3D en considérant plusieurs aspects tels que:

• effets de commutation à un ou plusieurs niveaux (auto-échauffement) sur la puissance 3D et la dissipation thermique;

• l'impact des TSV et du substrat sur la puissance et l'intégrité thermique et leurs implications en termes de conception;

• Influence de la conductivité thermique du dissipateur de chaleur sur les effets électrothermiques.

plus de dispositifs RF peuvent être générés en utilisant la technologie TSV ou M3D à l'échelle micro et nanométrique, par exemple, antenne micro RF avec TSV, coupleur thermique à base de TSV, cellule logique basée sur TSV ou M3D et autres capteurs 3D.

Récemment, la recherche de 3D IC s'est étendue à la conception optique-électronique. L'un des voie de recherche à l'avenir sera le co-design EDA de l'optique-électronique. Cependant dans le cs de l'application optique, le substrat et le milieu de transmission sont toujours du verre, et dans ce cas, les effets parasites électriques sont toujours négligeables, à l'échelle microscopique. Mais en vue de la haute fréquence, les circutis optiques ont beaucoup de problèmes thermiques. Donc les effects opto-electrique-thermiques doivent être considéré ensemble.

L'un des sujets brûlants dans la recherche est la puce neuromorphique. Le calcul basé sur le cerveau et basé sur les pointes dans les systèmes électroniques est étudié pour le développement de technologies informatiques alternatives non conventionnelles. La puce AI, c'est la meilleure façon d'intégrer l'algorithme d'apprentissage avec la conception matérielle. Le cadre d'ingénierie neurale fournit une méthode de programmation de ces dispositifs pour mettre en oeuvre le calcul. [START_REF] Corradi | Mapping arbitrary mathematical functions and dynamical systems to neuromorphic VLSI circuits for spike-based neural computation[END_REF] La partie la plus intéressante pour la conception 3D IC est de pouvoir implémenter une puce VLSI multi-neurones neuromorphique analogique / numérique à signaux mixtes dans une puce 3D et imiter la structure cérébrale, nous aurons une meilleure compréhension du système d'apprentissage humain. [92] P. Dixit, H. Viljanen, J. Salonen, T. Suni, J. Molarius, and P. Monnoyer, "Fabrication, electrical characterization and reliability study of partially electroplated tapered copper through-silicon vias," Proc. Tech. Pap. -Int. Microsystems, Packag. Assem. Circuits Technol. Conf. IMPACT, pp. 190-193, 2013.

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 7 List of personal publications ............................................................................................ 225

Figure 2

 2 Figure 2 Advantage of 3D for interconnections. (a) 2D systems comprise logic and memory chips, with the green curve illustrating a mixed logic-memory calculation that's inefficient precisely because of this logic and memory partitioning. (b) 3D systems with tight coupling between logic and memory avoid high latency paths, bandwidth bottlenecks, and conversion of signals to high energy levels for off-chip interconnects. The blue curve shows a representative data-movement step in sorting.

Figure 5

 5 Figure 5 Preview of the 2017 International Roadmap for Devices and Systems' predictions for future 3D structures. D: drain; FDSOI: fully depleted silicon on insulator; G: gate; LGAA: lateral gate-all-around; S: source; TBOX: thin buried oxide; VGAA: vertical gate-all-around[2]

  's law pace well into the next decade. --Computing in science & engineering March/ April 2017, vol.19, No.2.

Figure 10

 10 Figure 10 Different 3D interconnection technologies (a) Wire-bonding (b) Through silicon via (high density TSV & Medium density TSV) (c) 3D parallel integration (d) 3D Sequential integration

Figure 12

 12 Figure 12 Connectivity relationship of MNR chip (TSV, RDL: Redistribution layer and circuits embedded into the substrate)

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 22

Figure 13

 13 Figure 13 Cylindrical TSV

Figure 14

 14 Figure 14 Cylindrical TSV top view (with depletion layer)

Figure 15

 15 Figure 15 Interconnection model after inserting buffer

Figure 16

 16 Figure 16 Taper TSV

Figure 17

 17 Figure 17 Taper TSV resistance with different inclination angle (a) original formula (b) new formula (c) 75 o TSV resistances TSV metal radius 𝑟𝑟 𝑇𝑇𝑇𝑇𝑇𝑇 = 2.5𝜇𝜇𝑚𝑚, height 𝑙𝑙 𝑇𝑇𝑇𝑇𝑇𝑇 = 10𝜇𝜇𝑚𝑚, oxide layer thickness 𝑡𝑡 𝑜𝑜𝑜𝑜 = 0.1𝜇𝜇𝑚𝑚. And here we study the different inclination angle's influences by considering Cdep.

Figure 18

 18 Figure 18 Taper TSV MOS effect with different inclination angleFigure18shows the taper TSV's parasitic capacitance's change with the bias voltage, and different colors mean different inclination angle. When the bias voltage is less than the flat band voltage, TSV stay in the accumulation region, the parasitic capacitance is Cox (A region), with the increase of the voltage, TSV parasitic capacitance reduces due to the expansion of the depletion layer, this region is depletion region (B region). When the bias voltage arrives at the threshold voltage, the depletion width reaches the maximum and the capacitance will turn to the minimum and stay unchanged. From the Figure18, we can see that the bigger angle the smaller capacitance,

Figure 20 Taper

 20 Figure 20 Taper TSV inductance with different inclination angle

Figure 22

 22 Figure 22 CPW line structure 𝑅𝑅 = 𝜌𝜌 𝐿𝐿 𝑊𝑊•𝑇𝑇

109 ]

 109 𝐷𝐷 𝜋𝜋 = 𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 (0

Figure 23

 23 Figure 23 Illustration of the capacitive couplings between interconnect lines over a ground plane

Figure 24

 24 Figure 24 Coplanar lines front view (left figure). {RLCG} compact modelling of the signal line and one ground line of the coplanar waveguide (right figure).Parameters are calculated from the expressions listed below:[START_REF] Rosa | The self and mutual-inductances of linear conductors[END_REF]

Figure 25 :

 25 Figure 25: CPW substrate modelling.

FirstFigure 27

 27 Figure 27 Characteristic impedance ZC and the propagation constant γ parameters of CPW model of High resistive substrate (a)real part of the Zc (b)imaginary part of the Zc (c)absolute value of the Zc (d)propagation constant gamma (e) attenuation constant alpha (f) phase constant beta (g)RLCG parameters (h)S parameters S11&S12 for the de-embedded experimental data

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 42 by giving the maximum and minimum value or giving a percentage of variation. If no restriction is fixed, ADS can freely vary the value of variables.

Figure 28 ADS

 28 Figure 28 ADS setup for CPW model with low resistive substrate

Figure 29 Figure 30 S

 2930 Figure 29 ADS setup parameters for CPW model with low resistive substrate INL (Lyon Institute of Nanotechnology) has developed a program whose name is 3D-TLE (3D Transmission Line Extractor). This program is developed in Matlab which can generate the

Figure 32

 32 Figure 32 Importation in ADS of the extracted 3D-TLE CPW model

Figure 33 S21

 33 Figure 33 S21 magnitude by changing substrate conductivity (red line: optimization; blue line: measurement; pink line: 3D-TLE)

Figure 35

 35 Figure 35 Measurements based transient ADS setup

Figure 36 3D

 36 Figure 36 3D-TLE based transient ADS setup

  First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 49 (g)waveform of optimized circuit (red:original signal blue:LR substrate result pink: HR sub result) (h)eye diagram of optimized circuit (LR) (i)eye diagram of optimized circuit (HR) Figure 38 (a)(d)(h) show the input and output signal of the interconnection, (b)(e)(h) display the corresponding eye diagram for the low resistive substrate, (c)(f)(i) display the corresponding eye diagram for the high resistive substrate.

Figure 39

 39 Figure 39 TSV schematic (a) cross section view (b) compact model (c) geometry parameters 𝑅𝑅 𝑜𝑜𝑡𝑡 = 𝑅𝑅 𝑚𝑚𝑡𝑡 + 𝑇𝑇 𝑜𝑜𝑡𝑡 (2-74) 𝑅𝑅 𝑜𝑜𝑑𝑑 = 𝑅𝑅 𝑚𝑚𝑑𝑑 + 𝑇𝑇 𝑜𝑜𝑑𝑑 (2-75) 𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝑇𝑇 𝜋𝜋𝜋𝜋

Figure 40

 40 Figure 40 2xTSV chain (a) Medium density TSV front view (b) RLCG compact modeling of the mediumdensity TSV including the current path (c) Decomposition of the BEOL ground lines into RLCG serial blocks depending on the considered surface (MI and MII models)

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Figure 41 4xTSV

 41 Figure 41 4xTSV chain side view: representation of the proximity effects between TSVs (inductive couplings). The two chains of 2xTSV are connected at the BEOL level with contact pads and an access interconnection line

Figure 42

 42 Figure 42 Physical geometry of 2 TSVs model

Figure 44 3D

 44 Figure 44 3D-TLE extractor setting

Figure 45

 45 Figure 45 2xTSVs model S parameters (a) S21 magnitude without de-embedding (b) S21 magnitude with deembedding

Figure 46 SFigure 47

 4647 Figure 46 S parameters study setting for 2xTSVs model

Figure 49

 49 Figure 49 Optimized S parameters (blue: measurement, red: optimized, pink: 3D-TLE)

Figure 50

 50 Figure 50 3D-TLE verification by using FEM (COMSOL), ADS and measurements (a) Magnitude of S parameters (b) dB of S parameters

Figure 51

 51 Figure 51 Medium-density TSVs regular matrices. Bottom left: all the TSVs' oxide capacitances join at a single node modeling the substrate (illustration for a 2x2 matrix). Right: 3x3 medium-density TSVs matrix considered for the timing domain analyses.

Figure 52 3x3

 52 Figure 52 3x3 TSV matrix test bench used for Eye Diagram simulations.

Figure 54

 54 Figure 54 shows the result of transmission parameters of configuration A, B and C. And (d) shows the result of comparison between configuration A, B and C. As we can see, the more TSVs the more signal interferences and the lower transmission parameters.

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 60

Figure 53 Figure 54

 5354 Figure 53 3x3 medium-density TSV matrix configurations for generating Eye Diagrams from simulations. Colour legend: grey for grounded TSV, red for signal. Configuration A: data is only transmitted through the matrix central TSV. Configuration B: shielded configuration. Configuration C: data is sent to all the TSVs.

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 61

Figure 55 Generating

 55 Figure 55 Generating Eye Diagrams from simulation based on the three studied configurations. TOP: A configuration. Middle: B configuration. Bottom: C configuration.

Figure 56

 56 Figure 56 Schematic of heterogeneous 3-D IC technique. [132]

Figure 57

 57 Figure 57 Lumped circuit topology of the single-interposer wideband filter.

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonYue MA 2018 64 Through the proposed filter schema shown in Figure57and the corresponding circuit, the filter is almost finished. The parasitic effect of TSVs is added by considering the loss caused by the epitaxial layer. The equivalent model of TSV structure contains the resistive loss RTSV, inductive loss LTSV, epitaxial loss Repi, and coupling parasitic capacitance Cepi between TSV and pad. And the substrate coupling effects can be neglected if low-loss substrate is used, for example, glass or highresistivity material. (a) (b) Figure 58 Layout arrangement of the proposed single-interposer 25.6GHz/2GHz wideband filter (a) ADS layout (b) Physical Schematic for 2 TSVs model The proposed TSV-based filter can be easily designed without much extra fabrication process. The single TSV-based silicon interposer filter was designed using commercial simulator (ADS). For the result of TSV-based filter shown in Figure 59, the maximal transmission coefficient (|S21|) is 0.8, at the frequency of 25.6 GHz. The filter is very selective. The 20% range of simulated S21 coefficient is from 25 to 27 GHz.

Figure 59

 59 Figure 59 Simulated result of single-interposer bandpass filter (S-parameters).

Figure 60

 60 Figure 60 (a) Specific depth profile of a 35-µm technology (p+/p-region), (b) 3-D schematics of the structure

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  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 73

Figure 61 3D

 61 Figure613D TLE substrate extractor, example: Impedance Z17, capacitance and resistance C17 and R17 extracted between one contact and one TSV (valid for frequency lower than 20GHz and of quasi-static assumption)

Figure 62

 62 Figure 62 General steps of 3D-TLE algorithm

Figure 64 Frequency=100

 64 Figure 64 Frequency=100 GHz. (1) Left: top surface potential from 3D-TLE (a) and COMSOL (b) for 12 layers substrate, (2) Right -contacts embedded in layer 4 and layer 8 (see Figure 60). We present in Figure 63(a) and (b) the voltage map and the impedance module, respectively, between some Ci and Cj contacts, at the interfaces L3/L4 and L7/L8. It is typical of a Lorentzian curve (R//C, with R・C = ρε). The comparison between TLM/Green and COMSOL is quite good. Moreover, in Figure 63, surface potentials, from our 3-D transmission line extractor (TLE) simulator Figure 64(a) and COMSOL Figure 64(b) for a 12-layer substrate, at a frequency of 100 GHz, are quite similar. Still, a very good accordance was shown between FEM and TLM. Since calculations are made with current source, we get voltage variation under contacts.

FirstFigure 65

 65 Figure 65 (a) Some different shapes of contacts, which can be apprehended by 3D TLE (b) Impedances' comparison with COMSOL

  Figure 66 Temperature Fourier coefficients' spreading impedance

First

  Figure 67 (a) Temperature source profile; measurement time point: 2.2 μs. (b) Temperature maps: (left) FEM results and (right) Green's results; t=2.3 μs [see Figure 63 (a)]

Figure 68

 68 Figure 68 (a) Schematic of 3D IC structure (without Vias) (b) heat transfer model

  Figure 69 (a) Schematic of 3D IC structure with TSVs (b) Heat transfer model

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Figure 70

 70 Figure 70 Different layer number's influence to the 3D IC top layer temperature

Figure 71

 71 Figure 71 Surface ratio r and dies' number's influence to 3D IC top layer temperature

Figure 73 3D

 73 Figure 73 3D Thermal simulation work flow

FirstFigure 74

 74 Figure 74 (a) Bottom and (b) Top layer temperature distribution of 4 TSVs with surface ratio r = 0.01

Figure 75 4

 75 Figure 75 4 cores CMP model

Figure 76 3D

 76 Figure 76 3D CMP temporary temperature characteristics

Figure 77

 77 Figure 77 Temperature temporary characteristics (a) of core A&B with different heat capacities (b) of core C&D with different heat capacities (c) of core A&B with different power inputs (d) of core C&D with different power inputs (e) of core A&B with different thermal resistances (f) of core C&D with different thermal resistances

Figure 79 3 VinFigure 80

 79380 Figure 79 Dynamic electrical elementary cell

Figure 81

 81 Figure 81 Compact model o 3 RLC segments model

Figure 82

 82 Figure 82 (a) Input voltage source (b) Output comparison between MNA and ADS (c) Relative error between MNA and ADS for 3 RLC segments model 3.4.2.2) Case II: CPW (Coplanar Wave Model)

Figure 84 CPW

 84 Figure 84 CPW geometry and compact model

Figure 85

 85 Figure 85(a) Input voltage source (b) Output comparison between MNA and ADS (c) Relative error between MNA and ADS for CPW model 3.4.2.3) Case III: Two TSVs (through silicon via) U-model

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 103

Figure 87 2xTSVsFigure 88

 8788 Figure 87 2xTSVs chain model geometry and compact model We define two ground lines, two TSVs, and one redistribution layer (RDL). They are treated as a T model. The exact model is shown in the upper Figure 87. The voltage source is a pulse signal, with an amplitude of 1V, rise and down time of 0.05ns, duty cycle of 60%, and working frequency 2GHz. Here we also use the modified nodal analysis method (MNA) and generalized conjugate residual (GCR) solver. In order to verify the method's robustness, the same simulation is done in ADS. The signal is shown in the Figure 88(a), the output signal comparison with ADS is shown in the Figure 88(b), and Figure 88(c) shows the relative error of the MNA+GCR method and ADS.

Figure 89

 89 Figure 89 Our workflow for 3D device design

  the four neighboring nodes' index.

Figure 90

 90 Figure 90 Dynamic thermal elementary cell

Figure 91 ,

 91 Figure 91 Pulse signal definitionOur study takes the dynamics power analysis into consideration by combining parasitic of the 3D multi-layers system. The extracted parasitic deals with the coplanar line, redistribution layer and TSVs. Coplanar line parasitic are modeled by resistance, capacitance and inductance. Redistribution layer is modeled by resistance, inductance and capacitance. The time dependent voltage sources can be represented by the electrical characteristics: 1) switching frequency; 2) rise and fall times; 3) duty cycle; 4) delay time and 5) peak voltage. Here, in our study, the switching circuits are directly replaced by rectangular waveforms, as shown in Figure91.Switching pulse-like voltage sources are expressed as

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 108 𝐺𝐺 𝑡𝑡ℎ 𝑇𝑇 𝑑𝑑𝑚𝑚𝑑𝑑 = 𝑄𝑄 (3-66)

Figure 92 3D

 92 Figure 92 3D IC Electro-thermal coupling flow

3. 4 . 4 . 1 )

 441 Case I: One via model The one via model can be shown in Figure 93(b). The chip is composed of one coating layer, one oxide layer and one silicon layer, the center is a copper TSV. And the bottom is attached to a First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 109

Figure 93

 93 Figure 93 (a) Electrical compact mode (b) 2D Geometry (c) Thermal compact model of one via model

Figure 94 S

 94 Figure 94 S parameters of 1-TSV model from ADS (valid for frequency below 20GHz and of quasi-static assumption)

FirstWhereFigure 95

 95 Figure 95 Signal transient Integrity analysis for 1-TSV model 2.5GHz (a) Input vs Output signal (b) Maximum temperature rise (c) Comparison between ADS(without Electro-thermal consideration), MNA method (with Electro-thermal consideration) and MNA (without Electro-thermal consideration) (d) Output Voltage Error

FirstFigure 96 S

 96 Figure 96 S parameters with (a) error curve (b) maximum temperature curve for one via model (valid for frequency below 20GHz and of quasi-static assumption)

3. 4 . 4 . 2 )Figure 97 Figure 30

 4429730 Figure 97 Figure 30 (a) Electrical compact mode (b) 2D Geometry (c) Thermal compact model of one via with substrate model

  -thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 114

Figure 98 SFigure 99 S

 9899 Figure 98 S parameters with (a) error curve (b) maximum temperature curve for one via with substrate model (valid for frequency below 20GHz and of quasi-static assumption) 3.4.4.3) Case III: One TSV model with a very high thermal resistance

FirstFigure 100

 100 Figure 100 Flat heat pipe with different heating/cooling configurations: a) configuration I, single heat source and sink at the top; b) configuration II, multiple heat sources and sink at top; c) configuration III, heat source at the bottom and heat sink on the top.

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

13 )

 13 𝑡𝑡 𝑣𝑣 (-(ℎ 𝜌𝜌 + ℎ 𝑣𝑣 ) = 0 (4-14)

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

(

  𝜌𝜌𝐶𝐶) 𝑚𝑚 𝜕𝜕𝑇𝑇 𝜕𝜕𝑡𝑡 + (𝜌𝜌𝐷𝐷) 𝑚𝑚 V � �⃗ • ∇T = ∇ • �𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 ∇T� + 𝑄𝑄 𝑣𝑣𝑑𝑑 (4-31) Where (𝜌𝜌𝐷𝐷) 𝑚𝑚 assumes different values in the wall, wick, and vapor core Wall: (𝜌𝜌𝐷𝐷) 𝑚𝑚 = (𝜌𝜌𝐷𝐷) 𝑠𝑠 Wick: (𝜌𝜌𝐷𝐷) 𝑚𝑚 = (1 -𝜑𝜑)(𝜌𝜌𝐷𝐷) 𝑠𝑠 + 𝜑𝜑(𝜌𝜌𝐷𝐷) 𝜌𝜌 Vapor core: (𝜌𝜌𝐷𝐷) 𝑚𝑚 = (𝜌𝜌𝐷𝐷) 𝑣𝑣 All thermos-physical properties are assumed to be constant at a given time instant. The physical setting can be shown in the following Figure 101.

Figure 101

 101 Figure 101 Laminar flow setting of the vapor core

  the derivative form:First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

35 ) 37 )

 3537 𝑎𝑎𝑡𝑡 𝑜𝑜 = 𝜔𝜔 𝑜𝑜 , 𝑠𝑠 = 𝑡𝑡 = 0; 𝑎𝑎𝑡𝑡 𝑦𝑦 = 𝜔𝜔 𝜕𝜕 , 𝑠𝑠 = 𝑡𝑡 = 0;

  𝑑𝑑 ; 0 ≤ 𝑜𝑜 ≤ 𝜔𝜔 𝑑𝑑 In the adiabatic section𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 = 0; 𝑠𝑠 = 𝑡𝑡 = 0; 𝜔𝜔 𝑑𝑑 ≤ 𝑜𝑜 ≤ 𝜔𝜔 𝑑𝑑 + 𝜔𝜔 𝜋𝜋 (4-44)The condenser section has a convection condition with heat transfer coefficient ℎ 𝑙𝑙 and ambient temperature 𝑇𝑇 𝑙𝑙 -𝑘𝑘 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 = ℎ 𝑙𝑙 (𝑇𝑇 -𝑇𝑇 𝑙𝑙 ); 𝑜𝑜 > 𝜔𝜔 𝑑𝑑 + 𝜔𝜔 𝜋𝜋

Figure 102

 102 Figure 102 Heat transfer setting of the whole model And the initial conditions are imposed: 𝑇𝑇(𝑜𝑜, 𝑦𝑦, 0) = 𝑇𝑇 𝑖𝑖 ; 𝑃𝑃 𝑜𝑜𝑑𝑑 (𝑡𝑡 = 0) = 𝑃𝑃 𝑠𝑠𝜋𝜋𝑡𝑡 (𝑇𝑇 𝑖𝑖 ) (4-46)

FirstFigure 103 Figure 104

 103104 Figure 103 Temperature profile (a) comparison between COMSOL and pub with 50W heat source [215] in Matlab configuration I (b) parametrization of power in COMSOL configuration I (c) comparison between COMSOL and pub with 50W heat source [215] in Matlab configuration II (d) parametrization of power in COMSOL configuration IIThe Figure104compares the velocities at the center of vapor chamber.

Figure 105

 105 Figure 105 Capillary pressure at the wick/vapor interface (a) comparison between COMSOL and pub with 50W heat source [215] in Matlab configuration I (b) parametrization of power in COMSOL configuration I (c) comparison between COMSOL and pub with 50W heat source [215] configuration II (d) parametrization of power in COMSOL in Matlab configuration II

Figure 106

 106 Figure 106 Geometry of heated on one side and cooled on the other side

Figure 107

 107 Figure 107 first order thermal resistance model

First

  Figure 108 (a) 1D (b) 2D (c) 3D heat pipe model of FEM (COMSOL)

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 132 analytical one, and the 3D model has less perturbations at the vapor chamber region, maybe 3D model's mesh is too large. And the 1D COMSOL model's maximum temperature is less than the others.

Figure 109

 109 Figure 109 Temperature along the different layers of heat pipe with 1W heat sourceTable 16 1D heat pipe thermal results of COMSOL and analytical one

Figure 110

 110 Figure 110 Temperature along the different layers of heat pipe with 10W heat source

Figure 111

 111 Figure 111 Double sides heat pipe modelThe vapor chamber has a three-dimensional rectangular geometry; Figure113illustrates the wall, wick, and vapor core domains and their sizes in the x, y, and z coordinate directions. The

First 63 ) 1 (

 631 order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon At z = ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,𝜌𝜌𝑤𝑤) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 = (𝜌𝜌𝑤𝑤) 𝑣𝑣𝜋𝜋𝑑𝑑 ; 𝑠𝑠 = 𝑡𝑡 = 0 (4-64) (-𝑘𝑘 𝑑𝑑𝜋𝜋𝜋𝜋 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 -𝑚𝑚̇1 ′′ ℎ 𝜋𝜋𝑙𝑙 = (-𝑘𝑘 𝜕𝜕𝑇𝑇 𝜕𝜕𝜕𝜕 ) 𝑣𝑣𝜋𝜋𝑑𝑑 (4-65) At z = ℎ 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌,1 + ℎ 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘,1 + ℎ 𝑣𝑣𝜋𝜋𝑑𝑑 (𝜌𝜌𝑤𝑤) 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 = (𝜌𝜌𝑤𝑤) 𝑣𝑣𝜋𝜋𝑑𝑑 ; 𝑠𝑠 = 𝑡𝑡 = 0 (4-66)

  -thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 138

139 4. 3 . 3 )Figure 113

 13933113 Figure 112 mass flow comparison between COMSOL and analytical methodThe evaporated and condensed mass are shown in the above Figure112. As we can see, at the center or the heater place, the evaporated mass has the maximum value, and it reduces along X direction. And we can see that, the simulation in COMSOL and analytical model have very good fit. (Error <1%)

Figure 115

 115 Figure 114 (a) Capillary pressure and (b) wick/vapor pressure

Figure 116

 116 Figure 116 Schematic of approximate network of thermal resistance of configuration I

FirstFigure 117

 117 Figure 117 Contour map of the resistance ratio 𝑅𝑅 𝑇𝑇𝑃𝑃 𝑅𝑅 𝑇𝑇𝑇𝑇 ⁄ plotted as a function of length and thickness for an input heat flux of (a) 0.2 and (b) 2 W/cm 2 for length from 10mm to 100mm

First 1 𝑑𝑑

 1 order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon ∇< ∆𝚥𝚥⃗ 𝑙𝑙 (𝑟𝑟 ⃗, 𝑡𝑡) > 𝑙𝑙𝑜𝑜𝑙𝑙𝑑𝑑

  𝜇𝜇 𝑛𝑛 𝐷𝐷) Using the Einstein relationship, First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 158

  very low frequencies, 𝛿𝛿𝑣𝑣 𝛿𝛿𝐵𝐵 tends towards µ 0 and in ohmic regime ∂E ∂x =0, thus, n=Nd δI = -qA(𝑛𝑛 0 δν + 𝜈𝜈 0 δn) + ieAωδE (5-109)

Figure 119

 119 Figure 119 Introduction of a GR process. (a) defaults under contact C4; (b) defaults in 6 th layer

Figure 120

 120 Figure 120 noise spectral densities

Figure 121

 121 Figure 121 Equivalent circuit model and simulation setup of TSV-to-device noise By using the previous 2 equations (5-121) and (5-122), the variation of saturation current can be expressed as

Figure 122

 122 Figure 122 Structure and material parameters of TSV filler (Cu), insulating layer (SiO2) and wafer (Si)

  -thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 169

Figure 123 (

 123 Figure 123 (a) Variation of saturation current with distance from TSV edge to transistor and (b) KOZ resultscaused by the coupling noise, thermo-mechanical stress, and combination of the two aspects.

Figure 124

 124 Figure 124 (a) 3D schematic of vs-CNFET (b) equivalent circuit

Figure 125 I

 125 Figure 125 I-V curve of vs-CNFET (a) Id-Vds curve by changing Vgs (b) Id-Vgs curve by change Vd_bias

  to 0.41V and Vd_bias to 0.71V, in this condition, the Id stays in saturation. We change the 𝜇𝜇 and get the following figure: First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 172

Figure 126 μ

 126 Figure 126 μ-Idsat curve

∆

  = 50 Ω being the input and output impedance controlled by the VNA S-parameters are next converted to [𝐴𝐴𝐹𝐹𝐷𝐷𝐷𝐷] parameters [2] through the relations below: First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon = 50 Ω being the input and output impedance controlled by the VNA Δ𝑇𝑇=𝑇𝑇11 * 𝑇𝑇22-𝑇𝑇21𝑇𝑇12 is the determinant of the S-matrixThe relation between ABCD-parameters and CPW propagation parameters is:

  The line resistance of telegraph equations: First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonWith the new impedance characteristic Zc, we can recalculate the Y parameters by S parameters.

  And then; we can recalculate the S parameter by using the formula above and the impedance of reference: 50 ohm.First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonYue MA 2018 181 les nouvelles versions des GPUs utilisés dans les voitures autonomes ont de très larges mémoires DDR5.

  La Figure B2 b montre le diagramme de dépendance de données équivalent pour une étape de fusion d'un tri binaire d'arborescence. La couche logique jaune en haut montre la fusion de quatre étapes de tri bitonique. Lors de l'application de la structure sur la Figure B2 b, les comparaisons et les échanges peuvent être disposés sur la surface de la couche logique. Les données à traiter (Données A) et un emplacement pour stocker le résultat (Données B) sont placés dans la mémoire orange immédiatement inférieure et connectés via des fils courts traversant la grande surface 2D, plutôt qu'un bord.

Figure

  Figure B2 Avantage de la 3D pour les interconnexions. (a) Les systèmes 2D comprennent des puces de logique et de mémoire, la courbe verte illustrant un calcul de mémoire logique mixte inefficace justement à cause de cette logique et du partitionnement de la mémoire. (b) Les systèmes 3D avec un couplage étroit entre la logique et la mémoire évitent les chemins de latence élevés, les goulots d'étranglement de la bande passante et la conversion des signaux en niveaux d'énergie élevés pour les interconnexions hors puce. La courbe bleue montre une étape représentative du mouvement des données dans le tri.

Figure

  Figure B4 Forces motrices pour l'intégration 3D [4] La combinaison des idées 3D IC conduit à un nouveau chemin d'échelle potentiel. L'interface entre la logique et la mémoire a restreint les systèmes pendant des décennies. La réduction de ce goulot Von Neumann pourrait permettre aux semi-conducteurs de continuer à améliorer les performances du système. Cependant, cela nécessitera des progrès (comme le montrent la Figure B4 et la Figure B5) dont les processus d'ingénierie prendront du temps. Mais chaque avance réduira un peu l'impact du goulot Von Neumann. Pour les applications qui bénéficieraient d'une intégration plus étroite, cela pourrait offrir une augmentation des performances de génération en génération.

Figure

  Figure B5 Aperçu des prévisions de la Feuille de route internationale pour les dispositifs et les systèmes 2017 pour les futures structures 3D. D: drainer; FDSOI: silicium sur isolant entièrement appauvri; G: grille; LGAA: grille latérale tout autour; S: source; TBOX: oxyde mince enterré; VGAA: grille vertical tout autour[2]Dans les années 1970, deux lois fondamentales sont devenues les pierres angulaires de toute l'industrie: les lois d'échelle de Moore et de Dennard. La loi d'échelle de Dennard a identifié comment améliorer les performances des transistors au moyen d'une méthodologie appelée mise à l'échelle géométrique. Au début de la décennie précédente, la mise à l'échelle physique (limite d'épaisseur d'oxyde de grille) s'est arrêtée et l'avènement du nouveau transistor en réduisant les dimensions horizontales et en introduisant de nouveaux matériaux et de nouveaux effets physiques continue la loi Dennard. Les structures verticales commencent à remplacer le transistor planaire. La date de révolution prédictive est 2021. A ce moment, le dispositif construit par l'échelle 2D atteindra une limite fondamentale de l'espace de fabrication 2D, la transition vers des structures de dispositifs verticales complètes, une intégration hétérogène et une réduction de la consommation électrique deviennent les moteurs technologiques.[2],[3]

Figure B6

 B6 Figure B6Les différents âges de mise à l'échelle L'IRDS prévoit également cinq générations de transition fonctionnelle de la 2D à la 3D VLSI: (ici comprennent les dispositifs fonctionnels hétérogènes comme les capteurs, les nouveaux dispositifs de stockage, les circuits alternatifs logiques et de mémoire). Deux couches empilées avec des composants non mis à l'échelle, tels que l'analogique, les E/S et la gestion de l'alimentation dans une couche et la logique et la mémoire hautes performances dans l'autre. Intégration monolithique de deux couches, où chaque couche contient l'un des deux types de transistors fondamentaux en logique, NMOS et PMOS (semiconducteurs à oxyde métallique à canal n et à canal p) empilés les uns sur les autres pour une densité logique accrue. Deux couches: logique et mémoire. Connectivité analogique, E/S et RF en tant que couche supplémentaire, donnant plus de liberté pour inclure dans la conception des périphériques spéciaux.

Figure

  Figure B7Exemple d'architecture 3D des futurs circuits intégrés monolithiques[3]

Figure

  Figure B8Commutation de l'énergie et du délai d'un additionneur 32 bits[START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF]

  (b). La taille des capteurs d'image CMOS utilisant First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonYue MA 2018 188 l'approche "via last" a un diamètre d'environ 50 um[START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF]-[START_REF] Charbonnier | Wafer Level Packaging Technology Development for CMOS Image Sensors Using Through Silicon Vias M1 pad on front side[END_REF]. Et il a une plus petite taille pour la mémoire 3D empilée (NAND, DRAM ...) et les circuits logiques (MPU avec mémoire cache). L'empilage consiste à percer des trous à travers des puces de silicium pour fournir des connexions électriques entre des couches différentes. TSV offre une bande passante plus faible et une connectivité moins efficace entre les couches de puces que l'ajout de couches avec des procédés de photolithographie, mais une bande passante et une efficacité bien plus élevées que l'utilisation d'un encapsulation de puces conventionnels. Il a un avantage de 10X plus de liaisons dans le circuit et une meilleure bande passante, une meilleure latence, une alimentation en moins[START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF],[START_REF] Katti | Electrical modeling and characterization of through silicon via for three-dimensional ICs[END_REF]-[START_REF] Yook | High D ensity and Low-cost Silicon Interposer using Thin-film and Organic Lamination Processes[END_REF]. Cependant, la zone d'attente (KOZ)[START_REF] Wang | An effective approach of reducing the keep-out-zone induced by coaxial through-silicon-via[END_REF]-[START_REF] Yang | Combination of electrical and thermomechanical impacts of through-silicon via (TSV) on transistor[END_REF] requise pour les traversées en silicium (TSV) et les limites de précision d'alignement imposent des limites à la densité d'intégration de l'appareil qui peut être obtenue en utilisant l'empilage 3D TSV[2],[START_REF] Kannan | Device performance analysis on 20nm technology thin wafers in a 3D package[END_REF].

Figure

  Figure B9 Capacité d'alignement par rapport à la largeur de contact 3D dans des schémas d'intégrationparallèles et séquentiels[START_REF] Batude | 3-D sequential integration: A key enabling technology for heterogeneous Co-integration of new function with CMOS[END_REF]

FirstFigure

  Figure B10 Différentes technologies d'interconnexion 3D (a) Liaison filaire (b) Liaison via silicium (TSV haute densité et TSV moyenne densité) (c) Intégration parallèle 3D (d) Intégration séquentielle 3D La mise en oeuvre d'une structure 3D (Figure B11) incluant CNFET, RAM résistive (RRAM) et RAM magnétique de transfert de spin (STT-MRAM) a déjà été proposée et analysée en utilisant N3XT (Nano-Engineered Computing Systems Technology) proposée par l'Université de Stanford et l'Université de Californie Berkeley[START_REF] Aly | Energy-efficient abundant-data computing: The N3XT 1,000[END_REF]. Il a été démontré que le modèle N3XT avait une accélération de 23X et une réduction d'énergie de 37X, c'est-à-dire qu'il aurait un avantage de 851X en le produit énergie X retard.[START_REF] Aly | Energy-efficient abundant-data computing: The N3XT 1,000[END_REF]

Figure

  Figure B12 Relation de connectivité de la puce MNR (TSV, RDL: couche de redistribution et circuits intégrés dans le substrat)

First 193 B. 6 )B. 6 . 1 )

 193661 Figure B13 TSV schématique (a) vue en coupe transversale (b) modèle compact (c) paramètres de géométrie

pFigure

  Figure B14 Chaîne 2xTSV (a) Vue de face TSV moyenne densité (b) Modélisation RLCG compacte du TSV moyenne densité incluant le trajet du courant (c) Décomposition des lignes de masse BEOL en blocs série RLCG en fonction de la surface considérée (modèles MI et MII)

Figure 197 B. 6 . 2 )

 19762 Figure B15 latérale de la chaîne 4xTSV: représentation des effets de proximité entre les TSV (couplages inductifs). Les deux chaînes de 2xTSV sont connectées au niveau BEOL avec des plages de contact et une ligne d'interconnexion d'accès

Figure

  Figure B16 Géométrie physique du modèle 2 TSV

Figure 12 )Figure

 12 Figure B18 Réglage de l'extracteur 3D-TLEA travers l'article[START_REF] Kim | Highfrequency scalable modeling and analysis of a differential signal through-silicon via[END_REF], les paramètres parasites du substrat peuvent être exprimés par un circuit parallèle coustitué de capacités et de conductance. Et leurs expressions sont montrées comme suit

Figure

  Figure B21 Structure pour les réseaux au sol et de puissanceElectrical modeling of VLS circuits Une analyse électrique dynamique peut être réalisée une fois que des équivalents dynamiques parasites ont été définis et estimés pour la structure. Nous nous référons à la modélisation de premier ordre standard de chaque structure élémentaire de structure concernée, en considérant une inductance parasite série L pour chaque connexion entre des noeuds adjacents de la même grille, et une capacité parallèle C entre des noeuds correspondants sur les deux grilles différentes. De cette façon, nous définissons une cellule élémentaire dynamique comme indiqué dans la Figure B22.

FigureFigure

  Figure B24 Modèle compact of 3 segments RLC La résistance des segments est de 3,5 ohms, l'inductance est de 1,2 mH, la capacité est de 7,3 µF et la capacité supplémentaire du côté de la sonde est de 10 µF. La source de tension est un signal sinusoïdal d'amplitude de 3V, et fréquence de travail 200Hz. Ici, nous utilisons la méthode d'analyse nodale modifiée (MNA) et le résolveur général conjugué résiduel (GCR) et aussi la technique de la matrice répartie pour résoudre et accélérer le calcul de matrice différentielle à grande échelle, la description précise de la méthode peut être trouvée en annexe. Afin de vérifier la robustesse de la méthode, la même simulation est faite avec ADS (Advanced Design System de Keysight Technologies [207]). Le signal est représenté sur la figure (a), la comparaison du signal de sortie avec ADS est représentée sur la figure (b) et la figure (c) montre l'erreur relative de la méthode MNA + GCR et de l'ADS. Comme nous pouvons le voir sur la figure (c), notre méthode MNA + GCR a une très bonne précision par rapport à l'ADS, l'erreur maximale est d'environ 4%.

Figure

  Figure B27 Géométrie CPW et modèle compact Nous définissons deux types de lignes, une ligne de signal, une ligne de masse. Chaque ligne est traitée comme un modèle T. Nous définissons un Cinter entre deux lignes quelconques et chaque ligne est isolée du substrat par une couche d'oxyde. La source de tension est un signal impulsionnel, avec une amplitude de 1 V, des temps de montée et de descente de 0,05ns, un cycle de travail de 60% et une fréquence de travail de 2GHz. Ici, nous utilisons également la méthode d'analyse nodale modifiée (MNA) et la résolution résiduelle conjuguée généralisée (GCR). Afin de vérifier la robustesse de la méthode, la même simulation est effectuée dans ADS. Le signal est représenté sur la figure (a), la comparaison du signal de sortie avec ADS est représentée sur la figure (b) et la figure (c) montre l'erreur relative de la méthode MNA + GCR et de l'ADS. Comme nous pouvons le voir sur la figure (c), notre méthode MNA + GCR a une très bonne précision par rapport à l'ADS, l'erreur maximale est d'environ 3,5%.

FigureFigure

  Figure B30 du modèle de chaîne 2xTSVs et modèle compact Nous avons défini deux lignes de masse, deux TSV et une couche de redistribution (RDL). Ils sont traités comme un modèle T. Le modèle exact est représenté sur la figure supérieure 25. La source de tension est un signal impulsionnel, avec une amplitude de 1 V, des temps de montée et de descente de 0,05ns, un rapport cyclique de 60% et une fréquence de travail de 2GHz. Ici, nous utilisons également la méthode d'analyse nodale modifiée (MNA) et le solveur de conjugué généralisé (GCR). Afin de vérifier la robustesse de la méthode, la même simulation est effectuée dans ADS. Le signal est représenté sur la figure (a). La comparaison du signal de sortie avec ADS est représentée sur la figure (b). La figure (c) montre l'erreur relative de la méthode MNA + GCR

Figure

  Figure B32 notre flux de travail pour la conception d'appareils 3D B.7.1.3) Electro-thermal modeling of VLS circuits

Figure

  Figure B33 Flux de couplage électro-thermique 3D IC L'analyse en puissance est basée sur une analyse transitoire qui dérive la distribution de la chute de tension pour chaque niveau où une chute excessive entraîne des températures élevées sur les pistes métalliques. L'augmentation de la température est appliquée pour mettre à jour les modèles thermiques pour l'étape d'analyse thermique. L'analyse thermique est basée sur l'analyse statique 1-D et fournit la distribution de la température pour chaque niveau et TSV, où les températures élevées modifient la résistivité des conducteurs et sont incluses dans l'étape d'analyse de puissance.

First

  Figure B34 Caloduc plat avec différentes configurations de chauffage / refroidissement: a) configuration I, source de chaleur unique et évier en haut; b) configuration II, sources de chaleur multiples et puits en haut; c) configuration III, source de chaleur au fond et dissipateur de chaleur au sommet.

FigureFigureFigure

  FigureB35bmontre le profil de température simulé sous COMSOL avec une source de chaleur de 30W, 40W et 50W. Le profil de température a une température maximale du côté de l'évaporation dans la surface supérieure et une température minimale du côté du condenseur. Les graphiques révèlent une correspondance de haute précision entre COMSOL et la solution théorique. L'erreur maximale est d'environ 6% pour la configuration I et de 0,075% pour la configuration II. D'après les FigureB35 (b) et (d), nous pouvons voir qu'en augmentant de 10W à la source de chaleur, la température gagne environ 3K pour la configuration I, et 4K pour la configuration II respectivement.

Figure

  Figure B37 Pression capillaire à l'interface mèche / vapeur (a) comparaison entre COMSOL et pub avec source de chaleur 50W [215]en configuration Matlab I (b) paramétrisation de puissance en configuration COMSOL I (c) comparaison entre COMSOL et pub avec source de chaleur 50W [215] configuration II (d) paramétrisation de la puissance dans COMSOL dans la configuration Matlab II

1 2

 1 𝜇𝜇 𝑙𝑙 𝐷𝐷 𝑜𝑜𝑜𝑜 𝑊𝑊 𝐿𝐿 (𝑇𝑇 𝐺𝐺𝑇𝑇 -𝑇𝑇 𝑡𝑡ℎ ) 2 (B-13)

Figure

  Figure B38 Equivalent circuit model and simulation setup of TSV-to-device noise En utilisant les 2 équations (B-13) et (B-14), la variation du courant de saturation peut être exprimée comme suit:

  -thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

  𝜃𝜃) = Π × 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑠𝑠𝑖𝑖 (𝑟𝑟) × 𝛽𝛽(𝜃𝜃) (B-23) Où 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑠𝑠𝑖𝑖 est la contrainte radiale induite par le TSV; 𝜇𝜇 est la mobilité du substrat. 𝛽𝛽(𝜃𝜃) représente le facteur d'orientation; 𝜃𝜃 est l'angle entre le canal du transistor et la contrainte radiale induite par TSV. 𝜃𝜃 = 0° and 90° signifient que les canaux de drain et de source du transistor sont parallèles et perpendiculaires à la contrainte radiale induite par le TSV, respectivement [24]; Π est le coefficient piezo-résistif à at 𝜃𝜃 = 0°, qui agit comme une contrainte longitudinale. Pour nMOS, Π = -31 × 10 -11 𝑃𝑃𝑎𝑎 -1 , 𝛽𝛽(0°) = 1, 𝛽𝛽(90°) = 0.5, for pMOS, Π = 71.8 × 10 -11 𝑃𝑃𝑎𝑎 -1 , 𝛽𝛽(0°) = 1, 𝛽𝛽(90°) = -0.6.[23] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 220

Figure

  Figure B39 Structure et paramètres du matériau de la charge TSV (Cu), de la couche isolante (SiO2) et de la plaquette (Si)

Figure

  Figure B40 Variation du courant de saturation avec la distance du bord TSV au transistor et (b) résultats KOZ causés par le bruit de couplage, la contrainte thermosomécanique et la combinaison des deux aspects.

  -thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 222

First

  order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 230 First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 232 IEEE Int. 3D Syst. Integr. Conf. 3DIC 2013, 2013.

Table 1

 1 Evolution of 3D integration options toward 3D VLSI[1]

	Options	Links	Bandwidth Latency Power	Time frame
	Wire-bond stack	100s	Low	High	High	Available for 30 years
	Through silicon via (TSV) or microbump stack	1,000s	Medium	Medium Medium	Available for 10 years
	3D VLSI stack	100,000s	High	Low	Low	<10years

Table 2

 2 Flash memory trends (source: www.itrs2.net)

	NAND flash
	Year of production	2015	2016	2020	2022	2024	2028	2030
	2D NAND flash uncontacted poly ½ pitch-F (nm)	15	14	12	12	12	12	12
	3D NAND minimum array ½ pitch-F (nm)	80nm	80nm	80nm	80nm	80nm	80nm	80nm
	Number of word lines in one 3D NAND string	32	32-48	64-96	96-128	128-192	256-384	384-512
	Product highest density (2D or 3D)	256G	384G	768G	1T	1.5T	3T	4T
	3D NAND number of memory layers	32	32-48	64-96	96-128	128-192	256-384	384-512
	Maximum number of bits per cell for 2D NAND	3	3	3	3	3	3	3

Domain cell type (FG, CT, 3D, etc.) FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D

Table 4

 4 Different aspect ratio TSV RC parasitic parameters extraction comparison result in 45nm CMOS process from[START_REF] -T. Qian | Through-slicon-via-aware interconnect prediction model for 3D integrated circuit[END_REF]

	Aspect ratio 1	3	5
	Diameter d/um	5
	Tox /nm	120
	NA /cm3	2E15
	Theorical resistance/mOhm 0.30 2.80 1.40
	Q3D Resistance/mOhm 0.35 3.03 1.75
	Resistance error/% 1.15 1.77 1.61
	Theorical capacitor/fF 0.14 7.43 5.71
	Q3D capacitor/fF 0.38 8.28 7.21
	Capacitor error/% 2.56 3.10 3.28
	2.1.1.3) Cylindrical TSV Inductance

Table 5

 5 Different size TSV inductance

	TSV diameter	TSV height	TSV oxide thickness	Ltsv
	2um	20um	0.05um	13.827pH
	2um	20um	0.1um	14.049pH
	5um	20um	0.05um	10.185pH
	5um	20um	0.1um	10.262pH
	5um	50um	0.05um	34.262pH

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 27 2.1.1.4) Interconnection delay

𝐺𝐺 11 𝐺𝐺 12 𝐺𝐺 13 𝐺𝐺 21 𝐺𝐺 22 𝐺𝐺 23 𝐺𝐺 31 𝐺𝐺 32 𝐺𝐺 33

				�		(2-70)
		𝑙𝑙 12 + 𝑙𝑙 13	-𝑙𝑙 12	-𝑙𝑙 13
	𝐺𝐺 𝑇𝑇 = �	-𝑙𝑙 13 -𝑙𝑙 12	-𝑙𝑙 23 𝑙𝑙 12 + 𝑙𝑙 23	𝑙𝑙 23 + 𝑙𝑙 13 -𝑙𝑙 23	�	(2-71)

Table 6

 6 Comparison between original parameters, optimized parameters and 3D-TLE

		Original parameter	Optimized parameters	3D-TLE
	R1(ohm)	0.089126	0.000112646	0.011514
	L1(H)	1.9372e-9	0.926605e-15	1.7145e-10
	R2(ohm)	100000 ohm	197985	0.29467
	C2(F)	0.6E-12	0.984205e-12	3.514e-14
	R3(ohm)	100000 ohm	415.987	1.1906
	C3(F)	0.6E-12	14.996e-15	8.6966e-15
	Cox(F)	1.38e-11	5.98365e-12	4.0887e-12
	Cinter(F)	5.4228e-14	6.10788e-14	1.174e-14
	K1(H)	0.65818	0.588136	0.49259
	K2(H)	0.52744	0.320655	0.33268

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA

2018 44 2.2.4) 3D-TLE extraction (homemade extractor) results Figure

31 Extracted S parameters of CPW model for low resistive substrate (red line: optimization; blue line: measurement; pink line: 3D-TLE)

Table 7 Restored layers physical parameters Conductivity(ohm*m) Relative permittivity

 7

	SUBSTRATE	1e-4	11.7
	EPITAXIAL	0.1	13.5
	OXIDE		11
	BEOL	2e-8
	If we change only the substrate, and in ADS, we can establish a substrate changeable circuit,
	shown as following

Table 9 Comparison between original parameters and optimized parameters Name Original value Optimised value

 9

	R1	0.00016381	0.00016381
	R2	0.0012286	0.0012286
	R3	0.0016125	0.0016125
	R4	0.012094	0.012094
	R5	0.0031471	0.0031471
	L1	2.625e-12	2.625e-12
	L2	1.2226e-11	1.2226e-11
	L3	2.827e-12	2.827e-12
	L4	1.3508e-11	1.3508e-11
	L5	1.8915e-11	1.8915e-11
	Repi	378.75	378.75
	Cepi	2.4851e-14	2.4851e-14
	Cox	4.9277e-14	4.9277e-14
	Repi2	50.5	6.65094
	Cepi2	1.8638e-13	1.8638e-13
	Cox2	3.6958e-13	0.73916e-12
	Cdep	0.66e-12	1.32e-12

Table 10

 10

	Restored layers' material parameters
	Marked value	Optimised Value
	Relative Permittivity TSV oxide layer 5.8	6.5001
	Relative Permittivity oxide layer 5.8	11.6001
	Resistivity substrate (Ohm*m) 1e-4	0.2154
	Resistivity epitaxial (Ohm*m) 9.09e-2	1.2e-2

Table 11

 11

	8 dies 3D IC model's parameters

Lsi / (um) Lglue / (um) Lins / (um) ksi / (W/mK) kglue / (W/mK) kTSV / (W/mK) kins / (W/mK) Rhs / (K/W)

										Rpk /	S /
										(K/W)	(mm2)
	2	50	2	8.8	150	0.25	390	0.07	2	20	10*10

Table 12

 12

	Parameters[191]

  First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

	L2 x2_gnd1 x3_gnd1 5.6541e-11
	R2 x3_gnd1 out1 0.03225
	Cox_gnd1 x2_gnd1 nox_gnd1 1.3335e-12
	Repi_gnd1 nox_gnd1 0 312.5
	Cepi_gnd1 nox_gnd1 0 1.6567e-14
	R3 in2 x1_signal 0.028667
	L3 x1_signal x2_signal 5.3965e-11
	L4 x2_signal x3_signal 5.3965e-11
	R4 x3_signal out2 0.028667
	Cox_signal x2_signal nox_signal 1.5002e-12
	Repi_signal nox_signal 0 277.7778
	Cepi_signal nox_signal 0 1.8638e-14
	R5 in3 x1_gnd2 0.03225
	L5 x1_gnd2 x2_gnd2 5.6541e-11
	L6 x2_gnd2 x3_gnd2 5.6541e-11
	R6 x3_gnd2 out3 0.03225
	Cox_gnd2 x2_gnd2 nox_gnd2 1.3335e-12
	Repi_gnd2 nox_gnd2 0 312.5
	Cepi_gnd2 nox_gnd2 0 1.6567e-14
	K1 L1 L3 0.42787
	K2 L2 L4 0.42787
	Cinter1 x2_signal x2_gnd1 6.7837e-15
	K3 L3 L5 0.42787
	K4 L4 L6 0.42787
	Cinter2 x2_gnd2 x2_signal 6.7837e-15
	K5 L1 L5 0.30072
	K6 L2 L6 0.30072
	.ends gnd1_signal_gnd2
	X1_gnd1_signal_gnd2 0 0 1 2 0 0 gnd1_signal_gnd2
	C1 2 0 100e-15
	R1 in_real 1 50
	.TRAN	0.004m 20m
	.PROBE V(2)
	.print V(2)
	.end
	.end
		Figure 83 CPW model Spice script
		Yue MA 2018	98

  First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

	First order Electro-thermal compact models and noise considerations for three-dimensional First order Electro-thermal compact models and noise considerations for three-dimensional
	integration circuits integration circuits
	L2 x2 x3 5.2519e-11 L3 x1_pad3 accesstsv2 1.3508e-11 Coxtsv1_tsv2 x2_tsv2 p1_tsv2 1.9807e-12
	R2 x3 out 0.0032762 L4 accesstsv2 x2_pad3 1.3508e-11 Coxtsv2_tsv2 x2_tsv2 p2_tsv2 1.9807e-12
	Cox x2 0 9.7173e-13 R4 x2_pad3 out2 0.012094 Repi1_tsv2 p1_tsv2 epi1_tsv2 50.5
	.ends line1 Cepi1_tsv2 p1_tsv2 epi1_tsv2 1.8638e-13
	K1 L1 L3 0.74376 Repi2_tsv2 p2_tsv2 epi2_tsv2 50.5
	X1_signal 11 12 line1 K2 L2 L4 0.74376 Cepi2_tsv2 p2_tsv2 epi2_tsv2 1.8638e-13
	Cinter1 accesstsv2 accesstsv1 4.3097e-16 Coxgnd1_tsv2 epi1_tsv2 side3 3.6958e-13
	.subckt line3 in out Coxgnd2_tsv2 epi2_tsv2 side4 3.6958e-13
	R1 in x1 0.0012286 .ends pad1_pad3
	L1 x1 x2 1.2226e-11 K1 L1 L3 0.11406
	L2 x2 x3 1.2226e-11 X1_pad1_pad3 0 3 101 0 5 102 pad1_pad3 K2 L2 L4 0.11406
	R2 x3 out 0.0012286
	.ends line3 .ends tsv1_tsv2
	X1_rdlin 1 11 line3 .subckt pad2_pad4 in1 out1 accesstsv1 in2 out2 accesstsv2 X1_tsv1_tsv2 in 1 101 102 2 out 201 202 tsv1_tsv2
	X1_rdlout 12 2 line3 .subckt gnd1_gnd2 in1 out1 in2 out2 R1_tsv1 in_real in 50 R1 in1 x1_pad2 0.012094 C1_tsv2 out 0 100e-15 L1 x1_pad2 accesstsv1 1.3508e-11 .TRAN 0.004m 20m L2 accesstsv1 x2_pad2 1.3508e-11 .PROBE V(out) R2 x2_pad2 out1 0.012094 .print V(out)
	.end R1 in1 x1_gnd1 0.03225 R3 in2 x1_pad4 0.012094 .end L1 x1_gnd1 x2_gnd1 5.6541e-11 L2 x2_gnd1 x3_gnd1 5.6541e-11 L3 x1_pad4 accesstsv2 1.3508e-11 L4 accesstsv2 x2_pad4 1.3508e-11 Figure 86 2xTSVs chain U model
	R2 x3_gnd1 out1 0.03225 R4 x2_pad4 out2 0.012094
	Cox_gnd1 x2_gnd1 nox_gnd1 9.8554e-13
	Repi_gnd1 nox_gnd1 0 18.9375 K1 L1 L3 0.74376 Cepi_gnd1 nox_gnd1 0 4.9702e-13 K2 L2 L4 0.74376
	Cinter1 accesstsv2 accesstsv1 4.3097e-16
	R3 in2 x1_gnd2 0.03225
	L3 x1_gnd2 x2_gnd2 5.6541e-11 L4 x2_gnd2 x3_gnd2 5.6541e-11 .ends pad2_pad4
	R4 x3_gnd2 out2 0.03225 Cox_gnd2 x2_gnd2 nox_gnd2 9.8554e-13 X1_pad2_pad4 4 0 201 6 0 202 pad2_pad4
	Repi_gnd2 nox_gnd2 0 18.9375
	Cepi_gnd2 nox_gnd2 0 4.9702e-13
	.subckt tsv1_tsv2 in1 out1 side1 side2 in2 out2 side3 side4
	K1 L1 L3 0.30072
	K2 L2 L4 0.30072 R1 in1 x1_tsv1 0.0031471
	Cinter1 x2_gnd2 x2_gnd1 1.1493e-15 L1 x1_tsv1 x2_tsv1 1.8915e-11
	L2 x2_tsv1 x3_tsv1 1.8915e-11
	.ends gnd1_gnd2 R2 x3_tsv1 out1 0.0031471
	Coxtsv1_tsv1 x2_tsv1 p1_tsv1 1.9807e-12
	Coxtsv2_tsv1 x2_tsv1 p2_tsv1 1.9807e-12 X1_gnd1_gnd2 3 4 5 6 gnd1_gnd2 Repi1_tsv1 p1_tsv1 epi1_tsv1 50.5
	Cepi1_tsv1 p1_tsv1 epi1_tsv1 1.8638e-13
	Repi2_tsv1 p2_tsv1 epi2_tsv1 50.5
	.subckt pad1_pad3 in1 out1 accesstsv1 in2 out2 accesstsv2 Cepi2_tsv1 p2_tsv1 epi2_tsv1 1.8638e-13
	Coxgnd1_tsv1 epi1_tsv1 side1 3.6958e-13
	R1 in1 x1_pad1 0.012094 Coxgnd2_tsv1 epi2_tsv1 side2 3.6958e-13
	L1 x1_pad1 accesstsv1 1.3508e-11
	L2 accesstsv1 x2_pad1 1.3508e-11 R3 in2 x1_tsv2 0.0031471
	R2 x2_pad1 out1 0.012094 L3 x1_tsv2 x2_tsv2 1.8915e-11
	L4 x2_tsv2 x3_tsv2 1.8915e-11
	R3 in2 x1_pad3 0.012094 R4 x3_tsv2 out2 0.0031471
	Yue MA 2018 Yue MA 2018 Yue MA 2018	100 101 102

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Table 13

 13 One via model's geometry parameters

Table 14

 14 Properties of the working fluid, copper and porous wick materials used in the heat pipe simulations. Copper thermal conductivity(𝑘𝑘 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 ) 400W/mK Wick effective thermal conductivity(𝑘𝑘 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 ) 1.3W/mK Water vapor thermal conductivity(𝑘𝑘 𝑣𝑣 ) 0.05W/mK Copper specific heat capacity(𝐷𝐷 𝑑𝑑 ) 381 J/kgK Water liquid specific heat capacity(𝐷𝐷 𝑑𝑑 ) 4182 J/kgK Water vapor specific heat capacity(𝐷𝐷 𝑑𝑑 ) 1889 J/kgK Water liquid viscosity(𝜇𝜇 𝜌𝜌 ) 0.00065 Pa*s Water vapor viscosity(𝜇𝜇 𝑣𝑣 ) 0.0000096 Pa*s Enthalpy of vaporization(ℎ 𝜋𝜋𝑙𝑙 ) 2473 kJ/kg Specific gas constant(R_const) 8.3145 J/molK Water vapor mean molar mass(𝑀𝑀 𝑙𝑙 ) 0.018015 kg/mol

	PROPERTY VALUE
	Copper density(𝜌𝜌 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 )	8978kg/m 3
	Water liquid density(𝜌𝜌 𝑤𝑤𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟 ) 992.3kg/m 3
	Water vapor density(𝜌𝜌 𝑣𝑣 ) 0.05122kg/m 3
	Wick porosity(𝜑𝜑) 0.5
	Wick permeability(𝐾𝐾) 1*10 -11 m 2

Table 15

 15 Physical properties of heat pipeFirst order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

	Wick permeability(𝐾𝐾) 2.94*10 -12 m 2
	Yue MA 2018	130

  -108)

	𝜕𝜕 2 𝑃𝑃 𝑑𝑑𝑠𝑠𝑓𝑓𝑓𝑓 𝜕𝜕𝑜𝑜 2 +	𝜕𝜕 2 𝑃𝑃 𝑑𝑑𝑠𝑠𝑓𝑓𝑓𝑓 𝜕𝜕𝜕𝜕 2 =		𝑚𝑚̇1 ′′ 𝜇𝜇 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1	-	𝑚𝑚̇2 ′′ 𝜇𝜇 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2	(4-109)
	𝑃𝑃 𝑠𝑠𝑡𝑡𝑚𝑚 = ∑ ∑ ∞ 𝜌𝜌-0	∞ 𝑘𝑘=0	�𝑑𝑑 𝑠𝑠𝑡𝑡𝑚𝑚,𝜌𝜌𝑘𝑘 cos � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜	� cos �	𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦	��	(4-110)
	𝑃𝑃 𝑑𝑑𝑖𝑖𝜋𝜋𝜋𝜋 = ∑ ∑ ∞ 𝜌𝜌-0	∞ 𝑘𝑘=0	�𝑑𝑑 𝑑𝑑𝑖𝑖𝜋𝜋𝜋𝜋,𝜌𝜌𝑘𝑘 sin � 𝜌𝜌𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜	� sin � 𝑘𝑘𝜋𝜋𝜕𝜕 𝐿𝐿 𝑦𝑦	��	(4-111)
	With
	𝑑𝑑 𝑠𝑠𝑡𝑡𝑚𝑚,𝜌𝜌𝑘𝑘 =	𝛿𝛿 𝑡𝑡𝑘𝑘 ∫ ∫ ( 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 𝑚𝑚 ̇1 ′′ 𝜇𝜇 𝐿𝐿 𝑦𝑦 0 𝐿𝐿 𝑜𝑜 0 -𝜋𝜋 2 � + 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 𝑚𝑚 ̇2 ′′ 𝜇𝜇 𝑡𝑡 2 𝐿𝐿 𝑜𝑜 2 + 𝐿𝐿 𝑦𝑦 2 �𝐿𝐿 𝑜𝑜 𝐿𝐿 𝑦𝑦 𝑘𝑘 2	)	cos�	𝑡𝑡𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜	� cos� 𝑘𝑘𝜋𝜋𝑦𝑦 𝐿𝐿 𝑦𝑦	�𝑑𝑑𝑜𝑜𝑑𝑑𝜕𝜕	(4-112)
	𝑑𝑑 𝑠𝑠𝑡𝑡𝑚𝑚,𝜌𝜌𝑘𝑘 =	4 ∫ ∫ ( 𝐿𝐿 𝑦𝑦 0 𝐿𝐿 𝑜𝑜 0	𝑚𝑚 ̇1 ′′ 𝜇𝜇 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,1 -𝜋𝜋 2 � + 𝜌𝜌𝐾𝐾 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 ℎ 𝑤𝑤𝑠𝑠𝑐𝑐𝑘𝑘,2 𝑚𝑚 ̇2 ′′ 𝜇𝜇 𝑡𝑡 2 𝐿𝐿 𝑜𝑜 2 + 𝑘𝑘 2 𝐿𝐿 𝑦𝑦 2 �𝐿𝐿 𝑜𝑜 𝐿𝐿 𝑦𝑦	)	cos�	𝑡𝑡𝜋𝜋𝑜𝑜 𝐿𝐿 𝑜𝑜	� cos� 𝑘𝑘𝜋𝜋𝑦𝑦 𝐿𝐿 𝑦𝑦	�𝑑𝑑𝑜𝑜𝑑𝑑𝜕𝜕

Table 17

 17 Differences between COMSOL and analytical solution

		Top	Mid	Bottom	Heater side	Cooler side
		temperature	Temperature	Temperature	Mass flow	Mass flow
	Difference	4.5e-2%	1.6e-2%	1.45e-2%	2.5%	2.17%

  Where 𝜆𝜆 𝑃𝑃 = 2𝜇𝜇 𝑃𝑃 𝜐𝜐 𝑃𝑃 (1 -2𝜐𝜐 𝑃𝑃 ) -1 and 𝛿𝛿 𝑖𝑖𝑗𝑗 is the Kronecker delta. Based on the average over the wafer thickness, 𝑠𝑠 𝑃𝑃 (𝑟𝑟) and 𝑤𝑤 𝑃𝑃 (𝑟𝑟) are shown as follows:[START_REF] Berto | Three-dimensional linear elastic distributions of stress and strain energy density ahead of V-shaped notches in plates of arbitrary thickness[END_REF] 𝑠𝑠 𝑃𝑃 (𝑟𝑟) = 𝑎𝑎 𝑃𝑃 𝑟𝑟 + 𝑐𝑐 𝑃𝑃 𝐼𝐼 0 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� + 𝑑𝑑 𝑃𝑃 𝐾𝐾 0 (�𝐴𝐴 𝑃𝑃 𝑟𝑟)] (5-140)Where 𝐼𝐼 𝜌𝜌 and 𝐾𝐾 𝜌𝜌 with 𝑙𝑙 = 0,1, are the 𝑙𝑙 𝑡𝑡ℎ -order modified Bessel functions of the first kind and the second kind, respectively; 𝐴𝐴 𝑃𝑃 = 12(𝜇𝜇 𝑃𝑃 + 𝜆𝜆 𝑃𝑃 )(𝜆𝜆 𝑃𝑃 + 2𝜇𝜇 𝑃𝑃 ) -1 ℎ -2 ; and 𝑎𝑎 𝑃𝑃 , 𝑏𝑏 𝑃𝑃 , 𝑐𝑐 𝑃𝑃 , 𝑑𝑑 𝑃𝑃 are 12 constants to determine the solution of the problem. For the infinite wafer (𝑅𝑅 𝑠𝑠𝑖𝑖 ≫ 𝑅𝑅 2 ), due to the boundedness of the elastic parts of the displacements 𝑠𝑠 𝑟𝑟 𝑊𝑊 and 𝑠𝑠 𝜕𝜕 𝑊𝑊 at infinity, 𝑎𝑎 𝑊𝑊 and 𝑐𝑐 𝑊𝑊 should be zero. Displacement 𝑠𝑠 𝑟𝑟 𝑀𝑀 is zero at via center; 𝑏𝑏 𝑇𝑇 and 𝑑𝑑 𝑇𝑇 should be zero. The remaining eight constants are determined from the boundary conditions for the continuity of the displacements and stresses at interfaces r = 𝑅𝑅 1 and r = 𝑅𝑅 2 as follows:[START_REF] Berto | Three-dimensional linear elastic distributions of stress and strain energy density ahead of V-shaped notches in plates of arbitrary thickness[END_REF] 𝑠𝑠 𝑟𝑟 𝑀𝑀 (𝑅𝑅 1 ) = 𝑠𝑠 𝑟𝑟 𝐼𝐼 (𝑅𝑅 1 ), 𝑠𝑠 𝑍𝑍 𝑀𝑀 (𝑅𝑅 1 ) = 𝑠𝑠 𝑟𝑟 𝐼𝐼 (𝑅𝑅 1 ), 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑀𝑀 (𝑅𝑅 1 ) = 𝜎𝜎 𝑟𝑟𝑟𝑟 𝐼𝐼 (𝑅𝑅 1 ), 𝜎𝜎 𝑟𝑟𝜕𝜕 𝑀𝑀 (𝑅𝑅 1 ) = 𝜎𝜎 𝑟𝑟𝜕𝜕 𝐼𝐼 (𝑅𝑅 1 ) 𝑠𝑠 𝑟𝑟 𝐼𝐼 (𝑅𝑅 2 ) = 𝑠𝑠 𝑟𝑟 𝑊𝑊 (𝑅𝑅 2 ), 𝑠𝑠 𝜕𝜕 𝐼𝐼 (𝑅𝑅 2 ) = 𝑠𝑠 𝜕𝜕 𝑊𝑊 (𝑅𝑅 2 ), 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑀𝑀 (𝑅𝑅 2 ) = 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑊𝑊 (𝑅𝑅 2 ), 𝜎𝜎 𝑟𝑟𝜕𝜕 𝐼𝐼 (𝑅𝑅 2 ) = 𝜎𝜎 𝑟𝑟𝜕𝜕 𝑊𝑊 (𝑅𝑅 2 )Using the expression of 𝑠𝑠 𝑟𝑟 𝑃𝑃 and 𝑠𝑠 𝜕𝜕 𝑃𝑃 , 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑃𝑃 and 𝜎𝜎 𝑟𝑟𝜕𝜕 𝑃𝑃 can expressed in terms of unknown 12constants. With the previous relationships, one can solve the unknown 12 constants: 𝑎𝑎 𝑃𝑃 , 𝑏𝑏 𝑃𝑃 , 𝑐𝑐 𝑃𝑃 , 𝑑𝑑 𝑃𝑃 of the linear algebra system.

	𝜎𝜎 𝑖𝑖𝑗𝑗 𝑃𝑃 = 2𝜆𝜆 𝑃𝑃 𝑑𝑑 𝑖𝑖𝑗𝑗 𝑃𝑃 + 𝜆𝜆 𝑃𝑃 (𝑑𝑑 𝑟𝑟𝑟𝑟 𝑃𝑃 + 𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 + 𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 )𝛿𝛿 𝑖𝑖𝑗𝑗		(5-138)
	𝜋𝜋 𝑃𝑃 𝑟𝑟 (𝜆𝜆 𝑃𝑃 +2𝜇𝜇 𝑃𝑃 )ℎ + 𝑐𝑐 𝑃𝑃 𝐼𝐼 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� -𝑑𝑑 𝑃𝑃 𝐾𝐾 1 (�𝐴𝐴 𝑃𝑃 𝑟𝑟) 𝜆𝜆 𝑃𝑃 �𝐴𝐴 𝑃𝑃 × [The solution for 𝜎𝜎 𝑟𝑟𝑟𝑟 𝑤𝑤 𝑃𝑃 (𝑟𝑟) = -2𝜆𝜆 𝑃𝑃 ℎ 𝜆𝜆 𝑃𝑃 +2𝜇𝜇 𝑃𝑃 𝑎𝑎 𝑃𝑃 -𝑃𝑃 , 𝜎𝜎 𝑟𝑟𝜕𝜕 𝑃𝑃 , 𝑑𝑑 𝑟𝑟𝑟𝑟 𝑃𝑃 , 𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 are [268]	(5-139)
	𝜎𝜎 𝑟𝑟𝑟𝑟 𝑃𝑃 = 2𝜇𝜇 𝑃𝑃 𝜎𝜎 𝑟𝑟𝜕𝜕 3𝜆𝜆 𝑃𝑃 +2𝜇𝜇 𝑃𝑃 𝜆𝜆 𝑃𝑃 +2𝜇𝜇 𝑃𝑃 𝑃𝑃 = -12𝜇𝜇 𝑃𝑃 𝑎𝑎 𝑃𝑃 -2𝜇𝜇 𝑃𝑃 𝜕𝜕 ℎ 2 𝜆𝜆 𝑃𝑃 +𝜇𝜇 𝑃𝑃 𝜋𝜋 𝑃𝑃 𝑟𝑟 2 -2𝜇𝜇 𝑃𝑃 𝐼𝐼 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� × [𝐼𝐼 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟�𝑐𝑐 𝑃𝑃 -𝐾𝐾 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟�𝑑𝑑 𝑃𝑃 ] 𝑙𝑙 𝑃𝑃 𝑟𝑟 + 2𝜇𝜇 𝑃𝑃 𝐾𝐾 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� 𝜆𝜆 𝑃𝑃 𝑃𝑃 = 𝑎𝑎 𝑃𝑃 -𝑑𝑑 𝑟𝑟𝑟𝑟 𝜋𝜋 𝑃𝑃 𝑟𝑟 2 + ��𝐴𝐴 𝑃𝑃 𝐼𝐼 0 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� -𝐼𝐼 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� 1 𝑟𝑟 � 𝑐𝑐 𝑃𝑃 + ��𝐴𝐴 𝑃𝑃 𝐾𝐾 0 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� + 𝐾𝐾 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟� 𝑑𝑑 𝑃𝑃 𝑟𝑟 (5-141) (5-142) 1 𝑟𝑟 � 𝑑𝑑 𝑃𝑃
					(5-143)
	𝑑𝑑 𝜕𝜕𝜕𝜕 𝑃𝑃 = 𝑎𝑎 𝑃𝑃 +	𝜋𝜋 𝑃𝑃 𝑟𝑟 2 + 𝐼𝐼 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟�	1 𝑟𝑟 𝑐𝑐 𝑃𝑃 -𝐾𝐾 1 ��𝐴𝐴 𝑃𝑃 𝑟𝑟�	1 𝑟𝑟 𝑑𝑑 𝑃𝑃	(5-144)
		Yue MA 2018		167

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Table 18

 18 Input parameters of vs-CNFET of Stanford University[START_REF] Lee | Virtual-Source Carbon Nanotube Field-Effect Transistors Model Technical User ' s Manual[END_REF]

	Name	Value	Description
	Lg	11.7nm	Physical gate length
	Lc	12.9nm	Contact length
	Lext	3.2nm	Source/drain extension length
	W	1um	Transistor width
	tox	3nm	Gate oxide thickness
	kox	23	Gate oxide relative dielectric constant
	geo	1	Device geometry
			1:cylindrical gate-all-around;
			2:top-gate with charge screening effect
			3:top-gate without charge screening effect
	Hg	20nm	Gate height

  Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

	Appendix A: Extraction of the CPW propagation
	parameters
	S-parameters extracted from a CPW through a vector network analyzer (VNA):
	[ ] S	 =  	11 21 S S	12 22 S S	  
	S-parameters can be converted from Y-parameters by the following relationship:
	Yue MA 2018		177

  Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018 184 par millimètre carré), comme le montre le tableau 1. L'emballage 3D est disponible depuis des décennies sous des formes primitives, avec des connexions, des performances et une efficacité énergétique croissantes à mesure que la technologie progresse. La 3D entièrement intégrée devrait être disponible en moins d'une décennie.

	Table 1 Evolution des options d'intégration 3D vers 3D VLSI [1]
	Options	Links	Bandwidth Latency	Power	Time frame
	Wire-bond stack	100s	Low	High	High	Available for 30 years
	Through silicon via (TSV) or microbump stack	1,000s	Medium	Medium Medium	Available for 10 years
	3D VLSI stack	100,000s	High	Low	Low	<10years

Table 2

 2 Tendances de la mémoire Flash (source: www.itrs2.net)

	NAND flash
	Year of production	2015	2016	2020	2022	2024	2028	2030
	2D NAND flash uncontacted poly ½ pitch-F (nm)	15	14	12	12	12	12	12
	3D NAND minimum array ½ pitch-F (nm)	80nm	80nm	80nm	80nm	80nm	80nm	80nm
	Number of word lines in one 3D NAND string	32	32-48	64-96	96-128	128-192	256-384	384-512
	Domain cell type (FG, CT, 3D, etc.)	FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D
	Product highest density (2D or 3D)	256G	384G	768G	1T	1.5T	3T	4T
	3D NAND number of memory layers	32	32-48	64-96	96-128	128-192	256-384	384-512

Maximum number of bits per cell for 2D NAND

  First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Rmt et Tmt sont le rayon de la couche de cuivre et l'épaisseur de la couche de cuivre du haut; Rot et Tot sont le rayon de couche d'oxyde et l'épaisseur de la couche d'oxyde du haut; Rmd et Tmd le rayon de la couche de cuivre et l'épaisseur de la couche de cuivre du bas; Rod et Tod le rayon de la couche d'oxyde et l'épaisseur de la couche d'oxyde du bas;

				𝑅𝑅 𝑜𝑜𝑡𝑡 = 𝑅𝑅 𝑚𝑚𝑡𝑡 + 𝑇𝑇 𝑜𝑜𝑡𝑡	(B-1)
	𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝐷𝐷 𝑜𝑜𝑜𝑜(𝑇𝑇𝑇𝑇𝑇𝑇) = 𝑇𝑇 𝜋𝜋𝜋𝜋	𝑅𝑅 𝑜𝑜𝑑𝑑 = 𝑅𝑅 𝑚𝑚𝑑𝑑 + 𝑇𝑇 𝑜𝑜𝑑𝑑 1 2(𝑅𝑅 𝑚𝑚𝑚𝑚 𝑇𝑇 𝑚𝑚𝑑𝑑 -𝑅𝑅 𝑚𝑚𝑑𝑑 𝑇𝑇 𝑚𝑚𝑚𝑚 ) ln ( 𝑇𝑇 𝑚𝑚𝑑𝑑 2(𝑅𝑅 𝑚𝑚𝑑𝑑 -𝑇𝑇 𝑚𝑚𝑑𝑑 ) 𝜀𝜀 0 𝜀𝜀 𝑜𝑜𝑜𝑜 2𝜋𝜋𝑇𝑇 𝑇𝑇 𝑜𝑜𝑚𝑚 -𝑇𝑇 𝑜𝑜𝑑𝑑 [𝑅𝑅 𝑜𝑜𝑡𝑡 -𝑅𝑅 𝑜𝑜𝑑𝑑 + 𝑅𝑅 𝑜𝑜𝑚𝑚 •𝑇𝑇 𝑜𝑜𝑑𝑑 -𝑅𝑅 𝑜𝑜𝑑𝑑 •𝑇𝑇 𝑜𝑜𝑚𝑚 • 2𝑅𝑅 𝑚𝑚𝑚𝑚 -𝑇𝑇 𝑚𝑚𝑚𝑚 𝑇𝑇 𝑚𝑚𝑚𝑚 𝑇𝑇 𝑜𝑜𝑚𝑚 -𝑇𝑇 𝑜𝑜𝑑𝑑 ln ( 𝑇𝑇 𝑜𝑜𝑑𝑑 ) 𝑇𝑇 𝑜𝑜𝑚𝑚 )]	(B-2) (B-3) (B-4)
	𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 =	𝜇𝜇 0 𝜇𝜇 𝑟𝑟 𝑇𝑇 2𝜋𝜋 [𝑠𝑠𝑆𝑆𝑛𝑛ℎ -1 �	𝑇𝑇 𝑅𝑅 𝑎𝑎	� +	𝑅𝑅 𝑎𝑎 𝑇𝑇	+ 0.15 + �(	𝑅𝑅 𝑎𝑎 𝑇𝑇	) 2 + 1]	(B-5)
	𝑀𝑀 𝑇𝑇𝑇𝑇𝑇𝑇 =	𝜇𝜇 0 𝜇𝜇 𝑟𝑟 𝑇𝑇 2𝜋𝜋 [𝑠𝑠𝑆𝑆𝑛𝑛ℎ -1 � 𝑇𝑇 𝑑𝑑 � +	𝑑𝑑 𝑇𝑇 -�(	𝑑𝑑 𝑇𝑇 ) 2 + 1]	(B-6)
	Où:
				Yue MA 2018			194

Table 4

 4 Properties of the working fluid, copper and porous wick materials used in the heat pipe simulations. Water liquid density(𝜌𝜌 𝑤𝑤𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟 ) 992.3kg/m 3 Water vapor density(𝜌𝜌 𝑣𝑣 ) 0.05122kg/m 3 Copper thermal conductivity(𝑘𝑘 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 ) 400W/mK Wick effective thermal conductivity(𝑘𝑘 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 ) 1.3W/mK Water vapor thermal conductivity(𝑘𝑘 𝑣𝑣 ) 0.05W/mK Copper specific heat capacity(𝐷𝐷 𝑑𝑑 ) 381 J/kgK Water liquid specific heat capacity(𝐷𝐷 𝑑𝑑 ) 4182 J/kgK Water vapor specific heat capacity(𝐷𝐷 𝑑𝑑 ) 1889 J/kgK Water liquid viscosity(𝜇𝜇 𝜌𝜌 ) 0.00065 Pa*s Water vapor viscosity(𝜇𝜇 𝑣𝑣 ) 0.0000096 Pa*s Enthalpy of vaporization(ℎ 𝜋𝜋𝑙𝑙 ) 2473 kJ/kg Specific gas constant(R_const) 8.3145 J/molK Water vapor mean molar mass(𝑀𝑀 𝑙𝑙 ) 0.018015 kg/mol Wick porosity(𝜑𝜑) 0.5 Wick permeability(𝐾𝐾) 1*10 -11 m 2

	PROPERTY VALUE
	Copper density(𝜌𝜌 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 )	8978kg/m 3

  Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonYue MA 2018 218𝑇𝑇 𝑡𝑡ℎ = 𝑇𝑇 𝑡𝑡ℎ0 + 𝛾𝛾��2Φ 𝐹𝐹 -𝑇𝑇 𝐵𝐵𝑇𝑇 + �2Φ 𝐹𝐹 � ≈ 𝑇𝑇 𝑡𝑡ℎ0 -Où 𝑇𝑇 𝑡𝑡ℎ0 est la tension de seuil du bulk; 𝛾𝛾 représente le paramètre d'effet de corps; et 2Φ 𝐹𝐹 représente le paramètre de potentiel de surface. 𝑇𝑇 𝐵𝐵𝑇𝑇 est la tension du corps.

	𝛾𝛾 2�2Φ 𝐹𝐹	𝑇𝑇 𝐵𝐵𝑇𝑇	(B-14)

  𝛿𝛿 est la profondeur de la peau; f est la fréquence; 𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇 , h, 𝑅𝑅 𝑚𝑚 and 𝜎𝜎 𝑇𝑇𝑇𝑇𝑇𝑇 sont la résistance, la hauteur, le rayon et la conductance de TSV; L'inductance TSV 𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 est exprimée en𝜔𝜔 𝑇𝑇𝑇𝑇𝑇𝑇 = 𝑅𝑅 𝑚𝑚 -�ℎ 2 + 𝑅𝑅 𝑚𝑚 2 ] (B-19) La capacité de revêtement d'oxyde Cox, et la capacité d'appauvrissement induite par l'effet MOS Cdep sont calculées par 𝐷𝐷 𝑜𝑜𝑜𝑜 =

	𝛿𝛿 = � 𝜋𝜋𝜇𝜇 𝑇𝑇𝑇𝑇𝑇𝑇 𝜋𝜋 𝜌𝜌 𝑇𝑇𝑇𝑇𝑇𝑇				(B-18)
	𝜇𝜇 0 ℎ 2𝜋𝜋 [ln � ℎ+�ℎ 2 +𝑅𝑅 𝑚𝑚 2 𝑅𝑅 𝑚𝑚 � + 2𝜋𝜋𝜀𝜀 𝑜𝑜𝑜𝑜 ℎ ln ( 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜 𝑅𝑅 𝑚𝑚 𝐷𝐷 𝑑𝑑𝑑𝑑𝑑𝑑 = 2𝜋𝜋𝜀𝜀 𝑠𝑠𝑠𝑠 ℎ ln ( 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜 +𝑤𝑤 𝑑𝑑𝑑𝑑𝑑𝑑 ) 𝑅𝑅 𝑚𝑚 +𝑚𝑚 𝑜𝑜𝑜𝑜	)	(B-20) (B-21)
	𝑤𝑤 𝑑𝑑𝑑𝑑𝑑𝑑 = � 4𝜀𝜀 𝑠𝑠𝑠𝑠 𝑘𝑘𝑇𝑇 𝑞𝑞 2 𝑁𝑁 𝑎𝑎	ln (	𝑁𝑁 𝑎𝑎 𝑙𝑙 𝑠𝑠	)	(B-22)
	Yue MA 2018					219

B.9.1.1) Method d'investigation du bruit thermo-méchanic

Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2018LYSEI042/these.pdf © [Y. Ma], [2018], INSA Lyon, tous droits réservés

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de LyonYue MA 2018

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Nous combinons la fréquence de commutation et les effets électrothermiques ensemble. Et en comparant avec les paramètres S, nous avons découvert que les effets électrothermiques n'apparaissent que lorsque les paramètres S changent, et la réduction de la résistance thermique et l'augmentation de la concentration de dopage du substrat limiteront le problème d'intégrité du signal électrothermique.En tant que solution à la dissipation thermique locale, le composant passif de dissipation thermique, caloduc plat (FHP) est proposé comme un composant potentiel dans le chapitre 4. Le modèle basé sur FEM (COMSOL Multiphysics) est très précis dans la simulation 2D et 3D de caloduc. Les conditions aux limites précises peuvent être trouvées dans ce chapitre; il considère la distribution des la pression dans le calcul, et surtout il peut extraire la pression capillaire directement du modèle, ce qui sera très utile dans l'étude future des effets capillaires de la couche de mèche.Le chapitre 5 propose tout d'abord la solution analytique pour la distribution du bruit non stationnaire des substrats et présente des méthodes d'analyse du bruit. Ce chapitre étudie aussi le keep-out-of-zone (KOZ) de TSV à transistor, comme nMOS et CNFET. Les méthodes d'investigation de l'impact du bruit électrique et de l'impact du bruit thermo-mécanique montrent une grande influence sur le dispositif de type nMOS (pMOS, pFET et nFET). Mais pour le CNFET, en raison de l'isolement élevé entre le nanotube de carbone et le substrat, l'effet parasitaire du TSV n'a aucune influence sur celui-ci.En conclusion, ce travail peut, en plus de réaliser la modélisation électrique, thermique et électrothermique de simples TSV, TSV matrix et multicouches 3D IC, clarifier les contraintes de caractéristiques et les processus de bruit de couplage impliqués dans le substrat multicouche, et aussi donner les outils de conception EDA. Mais il reste beaucoup de choses à faire, et un cas réel et complexs doit être étudié. L'extension de ce travail concernera une modélisation électro-thermique M3D (3D Monolithic), qui permet de réaliser directement une conception de niveau nanométrique (un inverseur CMOS peut être obtenu à l'échelle nanométrique par connexion d'un pMOS et nMOS avec un M3D). Et Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2018LYSEI042/these.pdf © [Y. Ma], [2018], INSA Lyon, tous droits réservés

Acknowledgements

Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon Yue MA 2018

Acknowledgements

Over three and a half years of doctoral research in France, this dissertation draws an end of my short PHD research journey. The completion of the work cannot be finished without the support and encouragement of numerous people including my professors, friends, and colleagues. It is a

PROPERTY VALUE Copper density(𝜌𝜌

𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 ) 8960kg/m 3 Water liquid density(𝜌𝜌 𝑤𝑤𝜋𝜋𝑡𝑡𝑑𝑑𝑟𝑟 ) 998.2kg/m 3 Water vapor density(𝜌𝜌 𝑣𝑣 ) 0.02kg/m 3 Copper thermal conductivity(𝑘𝑘 𝑤𝑤𝜋𝜋𝜌𝜌𝜌𝜌 ) 400W/mK Wick effective thermal conductivity(𝑘𝑘 𝑤𝑤𝑖𝑖𝑙𝑙𝑘𝑘 ) 40W/mK Water vapor thermal conductivity(𝑘𝑘 𝑣𝑣 ) 0.0189W/mK Copper specific heat capacity(𝐷𝐷 𝑑𝑑 ) 381 J/kgK Water liquid specific heat capacity(𝐷𝐷 𝑑𝑑 ) 4182 J/kgK Water vapor specific heat capacity(𝐷𝐷 𝑑𝑑 ) 1889 J/kgK Water liquid viscosity(𝜇𝜇 𝜌𝜌 ) 1.79*10 -5 Pa*s Water vapor viscosity(𝜇𝜇 𝑣𝑣 ) 1*10 -3 Pa*s Enthalpy of vaporization(ℎ 𝜋𝜋𝑙𝑙 ) 2473 kJ/kg Specific gas constant(R_const) 8.3145 J/molK Water vapor mean molar mass(𝑀𝑀 𝑙𝑙 ) 0.018015 kg/mol Wick porosity(𝜑𝜑) 0.5

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 149

e -2iл𝜈𝜈𝑡𝑡 dτ = Aδτ [START_REF] Amd | High-Bandwidth Memory ( HBM ) reinventing memory technology industry standards On-die GPUs[END_REF][START_REF] Lee | 25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV[END_REF][START_REF] Xu | Interconnect-Aware Device Targeting from PPA Perspective[END_REF][START_REF] Seabaugh | Low-voltage tunnel transistors for beyond CMOS logic[END_REF][START_REF] Li | Sub-60mV-Swing Negative-Capacitance {FinFET} without Hysteresis[END_REF][START_REF] Ashraf | Electric field induced magnetic switching at room temperature: Switching speed, device scaling and switching energy[END_REF][START_REF] Shulaker | Carbon nanotube computer[END_REF][START_REF] Nikonov | Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits[END_REF][START_REF] Banerjee | 3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration[END_REF][START_REF] Jung | Highly Cost Effective and High Performance 65nm S 3 ( Stacked Single-crystal Si) SRAM Technology with 25F 2 , 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications[END_REF][START_REF] Ramm | 3D System-on-Chip technologies for More than Moore systems[END_REF][START_REF] Wolf | 3D integration of image sensor SiP using TSV silicon interposer[END_REF] When a noise is white, it means that successive events are not correlated. In practice, correlation is nonzero on in small time intervals τ 0 . τ 0 is the relaxation time of the system and we get: Γ X (τ) = 0 si τ > τ 0 . In other words, γ X (ν) is constant when ν < 1/τ 0

5.2) Noise calculation using the Langevin method

• Principle of this Method [START_REF] Thornber | Solid State Electron[END_REF] Of a very general scope, the Langevin method, which is applied to electronic noise, involves replacing the real device with a no-noise device in series with a noise source.

If η is the noise source, then the linear Langevin operator applied to the random variable is the said noise source, i.e.: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] L � X(t) = η(t)

(5-17)

If the average value of X(t) is zero, then we get: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] L � < 𝑋𝑋(t) >=< 𝜂𝜂(t) >= 0 (5-18)

And

Where e 2iπνt is an eigenvector of 𝜔𝜔 ̀, Z(ν) being its eigenvalue. Thus, we can write:

L � e 2iπνt = Z(ν). e 2iπνt

(5-21)

So, the noise spectral densities are connected via:

We see that the phase does not interfere here, with regard to second order properties.

• Example: Generation-Recombination noise

In a semiconductor bar, we can generate ∆𝑁𝑁 number of new carriers, by lighting, for instance. If 𝜏𝜏 is the carrier lifetime, we can write: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] If the source is harmonic:

∆n is also harmonic (cf. linearity):

Then, we get: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] S 𝑁𝑁 (𝑓𝑓) = S ∆n (𝑓𝑓)

(5-27)

(5-28)

If it is white noise, [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

(5-29)

Thus:

(5-30)

We know the spectrum if < ∆N 2 > is white; we then use a master equation that regulates microscopic phenomena.

• Quantities associated to Noise in Electricity

Let us take the Langevin theorem again: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

∆V is complex voltage (cf. sinusoidal regime), superimposed at the quiescent point, continuous and induced by ∆I.

We can then define an equivalent noise temperature 𝑇𝑇 𝑙𝑙 , such as: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] S V (𝑓𝑓) = 4𝑘𝑘T n (𝑓𝑓)Re(𝑍𝑍(𝑓𝑓))

(5-33)

Or S I (𝑓𝑓) = 4𝑘𝑘T n (𝑓𝑓)Re(𝑌𝑌(𝑓𝑓))

(5-34)

Avec

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Finally, we can define an equivalent noise current, 𝐼𝐼 𝑙𝑙 , in the following manner:

Thus, spectral densities are linked to the square modulus of the complex impedance. This concerns macroscopic fluctuations. If the source term is known, the fluctuation of the quantity studied can be deduced. It is also noted that even if the source has white noise, a normal assumption, the variable studied does not, in general, have white noise. Z depends on the frequency.

Observations:

1. To know one of the two terms, I (f) or S (f), we use microscopic conditions, via master equations (Boltzmann, Fokker-Planck equations, etc.), 2. We will see that it is absolutely necessary for the operator to be linear in order for the equation (5-26) to be applied; else, the Langevin description cannot be applied.

It is only when L is linear that we get a noise source with an average value of zero, and thus find the noiseless system equation.

If the system is not linear, equation can be linearized, because, in general, we focus on the small fluctuations around the mean value. So, we can then use X(t) = 𝑋𝑋 0 + ∆X(t) and linearize equation , given that< 𝑋𝑋 0 >= 0.

• Example application: Thermal noise of a Resistor:

Let us take a circuit (L, R); we find the spectral density of the noise current in the circuit, through which a zero average current flows. For this, we insert a source 𝑡𝑡(𝑡𝑡) in the perfect circuit and the circuit obeys the equation [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] 𝜔𝜔 𝑑𝑑𝑖𝑖 𝑑𝑑𝑡𝑡 + 𝑅𝑅𝑆𝑆 = 𝑡𝑡(𝑡𝑡)

(5-37)

We get:

The result is well-known:

Thus:

First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits Institut National des Sciences Appliquées de Lyon & Institut des Nanotechnologies de Lyon

Yue MA 2018 154

Where Green's function ∇ � �⃗ 𝑍𝑍(∆𝐼𝐼 = 1) is called the impedance field .

𝛿𝛿𝐼𝐼𝑑𝑑𝑟𝑟 can be described by the current density 𝛿𝛿𝑗𝑗(𝑟𝑟) in an infinitesimal volume 𝑑𝑑𝑟𝑟 3 :

𝛿𝛿𝑗𝑗 is the current density (A.m -2 )

By injecting in we get:

𝛿𝛿𝑇𝑇 𝜋𝜋 (𝑟𝑟) = ∇ � �⃗ 𝑍𝑍(𝑟𝑟, 𝑓𝑓)𝛿𝛿𝑗𝑗(𝑟𝑟)𝑑𝑑𝑟𝑟 3 (5-57)

Equation means that a current fluctuation in the 𝑑𝑑𝑟𝑟 3 volume produces a voltage difference between two other contacts. Integrating on the domain considered, the total voltage produced by these currents is: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] ∆𝑇𝑇 𝜋𝜋 = ∫ 𝛻𝛻 �⃗ Z (r, f)𝛿𝛿𝑗𝑗(𝑟𝑟)𝑑𝑑𝑟𝑟 3 (5-58)

In order to explicitly calculate the noise density of 𝑇𝑇 𝑇𝑇 (𝑓𝑓), we project devices, for example Cartesian, in x, y and z direction; in a direction, we get:

Thus, the voltage noise spectral density at the junctions becomes

Where Γ δV ( N, r, � �⃗ τ)) is the correlation function:

Density becomes: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF]

(5-63)

If K is a noise source:

Equation (5-65) simplifies into: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] First order Electro-thermal compact models and noise considerations for three-dimensional integration circuits We get:

(5-86) Finally,

(5-87)

It is the noise of the parallel RC circuit, where

(5-88) R = L/(q𝜇𝜇𝑛𝑛𝑇𝑇)

(5-88)

Figure 118 RC noise study circuit [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF] 𝑍𝑍 𝑑𝑑𝑞𝑞 = (

(5-89)

Thus:

(5-90)

5.4) Noise calculation using the transfer impedance method principle: formulation

We get seen in the impedance field method that a current generator in a dx slice induces a voltage variation at the junctions of the whole device. [START_REF] Nougier | IV-V Microelectronics[END_REF], [START_REF] Filicori | A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices[END_REF], [START_REF] Rohrer | Computationally efficient electronic-circuit noise calculations[END_REF] As we get suggested, Green's algorithm may be linked to a transfer impedance, considering the signal fluctuations. Injecting a current variation to a contact creates a potential variation at any other contract. Similarly, we must be able to analyze possible correlations between different noise sources autonomous ab initio but very close (cf. nano-electronics).

We consider another paradigm: the transfer impedance method (TIM); between two points, two slices, or two volume elements, via a linear relationship between the electric field response or the potential difference at a current disturbance, situated far away. Hence, we get the possibility of As for transfer impedance: [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] 𝜖𝜖𝐴𝐴µ 0 E ∂z(x,x,ω) ∂x + (

The solution for this differential equation is then:

Via, for example, the variation of constants theorem, we get K [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] K= -

Where H is the Heaviside step function;

And:

Introducing δI in x' results in x>x' if we ignore the diffusion.

In short:

Hence, we have its gradient:

In ohmic regime (E constant, very weak): λ → ∞ we get:

(5-117)

Diffusion noise power is thus:

Yet, in ohmic regime: 𝑘𝑘𝑇𝑇/𝑞𝑞 = D 0 /µ 0 [START_REF] Ma | Electrothermal modeling for 3-D nanoscale circuit substrates: Noise[END_REF], [START_REF] Ma | A Possible Way to Grasp Electronic Noise, via some Transfer Impedance Methods, in Three-Dimensional Nanoscale Circuit Substrates[END_REF], [START_REF] Yue Ma | Noise theoritical investigations for tri-dimmensional NMR circuit: towards the nanoscale[END_REF] 𝑇𝑇 𝑇𝑇 = 4 kT Aqn 0 µ 0

σ 0 is the ohmic conductivity

We get the well-known Nyquist-Johnson relationship .

Chapter 6: General Conclusion

This thesis provides a global design method for the conception of 3D integrated circuit in electrical, thermal, electro-thermal and also noise field. Hereafter will be included simulation methods for single TSV, TSV matrix, multi-layers substrate, multi-processors and heat dissipation design.

We firstly present some background knowledge on electrical parasitic effects (for instance, MOS effect and Skin current) of TSV. Based on the parasitic effects, two EDA design tools, a substrate extractor and a 3D TLE extractor (3D transmission line extractor), are programmed, which can automatically extract from any contacts (embedded or not): impedance, of arbitrary shape and arbitrary material. The extractors are 100% compatible with SPICE core simulator, like ADS (Advanced design system, dedicated to RF). The extracted data are often verified with measurements and finite element method (FEM) simulation result for Micro-stripe model, 2xTSVs U model. Based on the parasitic effects of TSV, a 26GHz frequency and 2GHz bandwidth RF filter is proposed in this work.

The chapter 3 presents the thermal and electro-thermal modeling method. We propose an analytical thermal solution for multi-layers substrate nonstationary temperature distribution. In the 3D IC design, the thermal issues are crippling issues, especially when we scale down to nanoscale. The electrical resistance increase with temperature, likewise the substrate resistance. Most of thermal simulation works are based on the steady regimes; few people work on the non-stationary case. Non-stationary effects are crippling, like hot spots, which can be enhanced by voltage ramps. We combine 1D thermal compact model by using MNA (modified nodal analysis) and 2D finite volume method (FVM) to solve multi-layers 3D IC temperature calculation, which, comparing with 3D FEM simulation, reduces largely the calculation complexities. This method is suitable for any 3D IC. Besides, a 4 cores processors heat dissipation case is studied in this chapter. The later part of this chapter presents how the electro-thermal simulation works. The electro-thermal simulator can be 100% compatible with SPICE (-like) simulator, and the electrical part is verified with ADS. The MNA method is normally used for 3D PDN (power distribution network) VLSI design; but here, we apply it in the device level simulation. This point is somewhat original, up to our knowledge. This work constructs the electro-thermal analysis framework for substrate, thermal connections (3D via) and system level 3D PDN. We provide an extensive study of power and thermal dissipation issues in 3D integration considering several aspects such as:

• Single and multi-layer auto-heating effects on 3D power and thermal dissipation;

• TSVs and substrate impact on power and thermal integrity and their design implications;

• heat sink's thermal conductivity's influence on the electro-thermal effects.

Appendix B: Résumé en français B.1) Introduction

AI (Intelligence Artificielle) est un nouveau domaine d'application passionnant pouvant bénéficier de l'architecture des puces 3D. Le produit Jeopardy d'IBM Watson et Google AlphaGo ont gagné le meilleur joueur de Go humain, mais tous deux ont fonctionné sur des grappes de serveurs, qui sont trop volumineuses pour être largement utilisées. Les voitures autonomes d'aujourd'hui utilisent des processeurs plus modestes, mais les voitures restent néanmoins peu sûres. Pour les rendre plus sûres, il faudra des systèmes de contrôle plus sophistiqués susceptibles d'augmenter les exigences de calcul.

Comme nous le savons depuis le "von Neumann bottleneck", le MPU (unité de microprocesseur) et la mémoire sont séparées. Les données se déplacent entre les deux. Dans ce cas, la latence est inévitable. Au cours de ces années, les fréquences des processeurs ont largement augmenté et atteint environ 4,2 GHz. Mais la mémoire s'améliore en densité, c'est-à-dire qu'elle peut stocker plus de données dans un espace fixe, au lieu de l'augmentation des vitesses de transfert. Lorsque la fréquence du travail de MPU augmente, le processeur passe de plus en plus de temps d'attente pour écrire et lire depuis la mémoire. Donc, peu importe la rapidité avec laquelle le MPU peut fonctionner; il est limité par la vitesse de transfert de la mémoire. [1], [2]