Y Pascal

Keywords: integrated switching power supply, on-chip voltage regulator, switched-capacitor converter, inductive power converter, resonant converter

The full integration of DC-DC converters offers great promise for dramatic reduction in power consumption and the number of board-level components in complex systems on chip. Some papers compare the numerous published on-chip and on-die converter structures, but there is the need for an approach to accurately compare the main basic DC-DC conversion topologies. Therefore, this paper presents a method to compare the efficiencies of CMOS integrated capacitive-, inductive-and resonant-based switching converters. The loss mechanism of each structure in hard-switching conditions is detailed and the analytical equations of the power loss and output voltage are given as a function of few CMOS technology parameters. The resulting models can be used to accurately predict converter efficiency in the early design phase, to compare the basic structure in particular the technology node or to orient the passive choice. The proposed method is then applied to design, optimize and compare fully-integrated power delivery requirements on a 1mm 2 on-die area in 65nm CMOS technology over three decades of power density. The results also underline the high efficiency of the promising resonant-based converter.

I. INTRODUCTION

OST modern circuits on a single chip in deep submicron CMOS technology integrate various blocks such as multicore digital processing, memories, sensor, actuator interfaces and wireless transmission. Each function often requires a dedicated and variable supply voltage for powersaving techniques and high performance issues. In addition, numerous step-down and step-up DC-DC converters are needed to convert the continuous energy source (generally from a chemical battery in the embedded system) into lower or higher DC power rails. As the power distribution network is at a higher scale (e.g. country level), the power tree definition in modern circuit and board levels is a great challenge to provide multiple power rails with high efficiency and low cost in a small footprint area.

DC-DC switching converters are always composed of the four main functions illustrated in Figure 1. The switching cell is used to modulate the power flow from the battery to the source through the intermediate energy storage. The control block changes the switch state to deliver constant and regulated output voltage against line, own variation, and load variations. The converters are categorized according to the intermediate energy storage type i.e. capacitor-, inductor-or resonant-based converters. Here, the linear regulator is out of scope for it dissipates the intermediate energy into thermal energy, implying low power efficiency, at best equal to the conversion ratio (defined by output to input voltage ratio). Use of an off-chip converter is currently the most efficient way to provide multiple power domains but it is a bulky solution mainly due to the extra components needed around the powered circuit on the motherboard footprint. Nowadays, on-chip power management seems to be a suitable solution to provide clean, fine, high speed and granular power supply modulation for the modern circuit without bulky external components or additional circuits. This paper discusses the integration of a DC-DC converter for chip-scale power management.

There are two levels in which the on-chip power supplies can be integrated. These are the in-package and on-die solutions. In-package converters combine different technologies to integrate the switching cell, and the passive and control in the same package as the powered circuit [START_REF] Lee | High-Frequency Integrated Point-of-Load Converters: Overview[END_REF]. Using non-standard processes such as deep-trench capacitors [START_REF] Andersen | A 4.6 W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF], magnetics on silicon [START_REF] Mathuna | PwrSoC (integration of micro-magnetic inductors/transformers with active semiconductors) for more than Moore technologies[END_REF] or wide band-gap technology [START_REF] Pala | Integrated High-Frequency Power Converters Based on GaAs pHEMT: Technology Characterization and Design Examples[END_REF] lead to the converter being potentially smaller and having a higher power efficiency than an on-die solution, though the 3D heterogeneous assembly of the converter and its load could be a cost issue. The second integration level i.e. on-die consists of the integration of the converter on the same Efficiency Comparison of Inductor-, Capacitorand Resonant-based Converters Fully Integrated in CMOS Technology Y. Pascal and G. Pillonnet M technology as the powered circuit [START_REF] Wang | High frequency DC-DC converter with co-packaged planar inductor and power IC[END_REF], [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF]. The key issue is the integration of the passive for intermediate energy storage (Fig. 1). Some research proposes numerous design refinements to overcome the low energy capability of the integrated passive components. For example, high switching frequency [START_REF] Hazucha | A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing aircore inductors on package[END_REF] [8], series-parallel switching cell connection [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF] [10], or coupling of passives [START_REF] Wibben | A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors[END_REF] help to improve the converter performance. However, the recently published on-die power converters still achieve performance far from the industrial targets [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF] in terms of power density, voltage regulation, efficiency versus conversion ratio or direct battery connection compatibility.

The integration of magnetic material and the permeability at high frequency in standard CMOS technology are the major roadblocks [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF] which account for the fact that most publications focus on on-die capacitor-based converters. By using numerous design refinements, this previous work confirms that the switched capacitor topology is suitable in order to maintain about 80% of the efficiency for a 1W power delivery on a 1mm² die area [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF], though capacitor-based converters still suffer from low power efficiency outside their discrete conversion ratios and efficiency limitation for higher power density. Other converter topologies could overcome the above limitations such as inductor-based converters [START_REF] Hazucha | A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing aircore inductors on package[END_REF], hybrid structures [START_REF] Lim | Two-Stage Power Conversion Architecture Suitable for Wide Range Input Voltage[END_REF] or resonant-based converters [START_REF] Stauth | A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management[END_REF], these topologies being widely used in higher power electronic applications. However, these are not studied mainly due to the poor energy density of their intermediate storage elements on a mm 2 scale [START_REF] Sanders | The Road to Fully Integrated DC-DC Conversion via the Switched-Capacitor Approach[END_REF].

In the on-die context, there is a need to compare converter architectures fully-integrated in CMOS technology, even the two simplest step-down topologies: the buck and switched capacitor converter. Numerous papers compare published results but it is difficult to know if the converter performance comes from the technology or from the topology itself. Work in [START_REF] Villar-Pique | Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach[END_REF] provides a general design survey for the capacitiveand inductive-based converters, but the compact expressions of the converter efficiencies are not given. Discussion in [START_REF] Lee | Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies[END_REF] only compares the inductive converter across the range of technologies from 0.35µm to 90nm. However, [START_REF] Seeman | A comparative analysis of switched-capacitor and inductorbased dc-dc conversion technologies[END_REF] shows some fundamental limits of the converter topologies but it does not provide a complete efficiency comparison in the same context. Based on the state-of-the-art, the system-level designer does not have any compact model to compare the expected performance, in a particular silicon technology, even with the two basic and well-spread inductive and capacitive hard-switching converters. Therefore, this paper aims at comparing those basic topologies and the recently emerging resonant converter [START_REF] Stauth | A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management[END_REF][START_REF] Hamo | Modeling and Analysis of Resonant Switched Capacitor Converters with Free-Wheeling ZCS[END_REF][START_REF] Cheng | New generation of switched capacitor converters[END_REF] for on-die DC-DC conversion. We give the analytical expressions of the efficiency for the three converters using few silicon technology parameters which are extracted from basic simulations. Based on our modeling, we optimize the power efficiency of the three particular converters over a three decade power range (from 0.1 to 10W) using 65nm CMOS technology under similar conditions to derive our approach. Those on-die converters are fully-integrated (active and passive), the passives of each are integrated on 1mm² of die.

In this paper, sections II, III and IV detail the basic operations and key loss mechanisms of capacitive, inductive and resonant converters using basic topology without refinements (i.e. no interleave or soft-switching). In 65nm CMOS technology, these three particular topologies are then compared in Section V. The annexes give the general assumptions of the paper and describe the unified constants used in the paper.

II. CAPACITOR-BASED CONVERTER

The capacitor-based converter topology operates in two phases to transfer the power from the input 𝑉 𝑖𝑛 to the output 𝑉 𝑜 through an on-die flying capacitor 𝐶 𝑓𝑙𝑦 as shown in Figure 2 where 𝑅 𝑠 models 𝐶 𝑓𝑙𝑦 equivalent series resistance, and 𝐶 𝑏𝑜𝑡 models 𝐶 𝑓𝑙𝑦 capacitive coupling with the substrate. In the first phase, both MOSFETs M2 and M4 are closed and the capacitor 𝐶 𝑓𝑙𝑦 is charged from the input source through the output load 𝑅 𝑙𝑑 . In the second phase, the energy previously stored in 𝐶 𝑓𝑙𝑦 is transferred to the output using transistors M1 and M3. Then, the voltage ripple across the flying capacitor is proportional to the transferred energy and the output power can be expressed as:

𝑃 𝑜 = 𝑓 𝑠𝑤 𝐶 𝑓𝑙𝑦 𝑉 𝑜 𝛥𝑉 𝐶 𝑓𝑙𝑦 (1)
where 𝛥𝑉 𝐶 𝑓𝑙𝑦 = 𝑉 𝑖𝑛 -2𝑉 𝑜 .

A. Loss mechanism

Since this topology is well-studied in the literature [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF], [START_REF] Makowski | Performance limits of switchedcapacitor DC-DC converters[END_REF], [START_REF] Kimball | Modeling of Capacitor Impedance in Switching Converters[END_REF], [START_REF] Pillonnet | Dual-Iput Switched Capacitor Converter Suitable for Wide Voltage Gain Range[END_REF] this section briefly describes the loss mechanism for further comparison with inductive-and resonant-based converters. The total losses of the converter, valid both in SSL an FSL regions [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF], can be expressed as:

𝑃 𝑙𝑜𝑠𝑠 = 𝑃 𝑠𝑤 + 𝑃 𝑐𝑜𝑛𝑑 + 𝑃 𝑡𝑟𝑎𝑛𝑠 where the switching losses 𝑃 𝑠𝑤 are due to the switching of the transistors M 1 to M 4 , P cond is the transistor conduction loss due to the load current, and the transfer loss 𝑃 𝑡𝑟𝑎𝑛𝑠 is caused by the flying capacitor being partially charged and discharged by the bottom plate capacitance 𝐶 𝑏𝑜𝑡 and lastly by the equivalent series resistance 𝑅 𝑠 . 𝑃 𝑡𝑟𝑎𝑛𝑠 is dissipated in the power transistors but it is separated to give a unified approach and highlight the loss difference between the converter topologies. According to previous work [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF][START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF][START_REF] Makowski | Performance limits of switchedcapacitor DC-DC converters[END_REF][START_REF] Hamo | Modeling and Analysis of Resonant Switched Capacitor Converters with Free-Wheeling ZCS[END_REF], the total loss can then be expressed by the following equation:

𝑃 𝑙𝑜𝑠𝑠 =
where (𝐴, 𝐵, 𝐶, 𝐷, 𝐸) are constants depending on the technology used and the design constraints (Table 5).

Increasing (𝑊 𝑖 ) 𝑖 leads to a decrease of 𝑃 𝑐𝑜𝑛𝑑 but to an increase of 𝑃 𝑠𝑤 . Likewise, increasing 𝑓 𝑠𝑤 diminishes 𝑃 𝑡𝑟𝑎𝑛𝑠 , though it magnifies 𝑃 𝑠𝑤 . Therefore, an optimal point can be found to maximize the power efficiency 𝜂, defined by:

𝜂 = 𝑃 𝑜 𝑃 𝑜 +𝑃 𝑙𝑜𝑠𝑠 = 𝑉 𝑜 2 𝑉 𝑜 2 +𝑅 𝑙𝑑 ⋅𝑃 𝑙𝑜𝑠𝑠 (4)
From these equations, it should be highlighted that the flying capacitor value 𝐶 𝑓𝑙𝑦 has to be maximised to improve the power efficiency. The efficiency of this topology is then closely linked to the capacitance density allowed by the technology, which enables comparison of previous work using very delicate heterogeneous technologies.

B. Output voltage

The output voltage 𝑉 𝑜 has to be determined to solve equation [START_REF] Andersen | A 4.6 W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS[END_REF] to then find the overall efficiency (4). As described in [START_REF] Arntzen | Switched-capacitor DC/DC converters with resonant gate drive[END_REF], the capacitor-based converter can be modeled in steady-state as an output impedance 𝑅 𝑜 and an ideal voltage source with 2:1 conversion ratio. According to previous publications such as [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF], 𝑉 𝑜 can be expressed as:

𝑉 𝑜 = 𝑅 𝑙𝑑 𝑅 𝑙𝑑 +𝑅 𝑜 𝑉 𝑖 2 (5)
where

𝑅 𝑜 = 1 4𝐶 𝑓𝑙𝑦 𝑓 𝑠𝑤 + 1 2 ∑ 𝛬 𝑖 𝑊 𝑖 + 𝑅 𝑠

III. INDUCTOR BASED-CONVERTER

The schematic of the inductive converter (i.e. buck converter) is given in Fig. 3. For CMOS compatibility, an aircore inductor is used for the intermediate energy transfer; 𝑅 𝑖𝑛𝑑 models the inductor parasitic resistance. In the first phase, the transistor M 1 allows energy to fly from the source to both the inductor and the output; in the second phase, the circuit is free-wheeling and part of the energy stored in the inductor is transferred to the output. The energy transfer is proportional to the average current in the inductor, and the output power can be expressed as 𝑃 𝑜 = 𝑉 𝑜 〈𝐼 𝐿 〉, where 〈𝐼 𝐿 〉 is the mean coil current.

A. Loss mechanism

Since the inductive topology is well-known in the power electronic field, this section briefly describes the loss mechanism and gives compatible expressions with capacitiveand resonant-based converters for further comparison. The effect of the design parameters is also underlined for clarifying the optimization performed in Section V.

In CCM, the expression for the switching and conduction losses 𝑃 𝑠𝑤 + 𝑃 𝑐𝑜𝑛𝑑 is the following:

𝜆 𝐶 𝑖𝑛 𝑉 𝑖𝑛 2 𝑓 𝑠𝑤 ∑ 𝑊 𝑖 + 𝐼 𝐿 𝑅𝑀𝑆 2 (𝐷 𝑐 𝑅 𝑑𝑠 𝑜𝑛 (𝑀 1 ) + (1 -𝐷 𝑐 )𝑅 𝑑𝑠 𝑜𝑛 (𝑀 2 )) (6)
where 𝐼 𝐿 𝑅𝑀𝑆 is the RMS current flowing through the coil and 𝐷 𝑐 ≅ 𝑉 𝑜 /𝑉 𝑖𝑛 is the duty cycle of the clock signal. Assuming that the coil current is triangular (

𝐿 𝑅 ≫ 𝑇 𝑐𝑙𝑘 ), its RMS value is
given by:

𝐼 𝐿 𝑅𝑀𝑆 2 = 𝐼 𝑜 2 + 1 12 (𝐷 𝑐 𝑉 𝑖𝑛 -𝑉 𝑜 𝐿 𝑓 𝑠𝑤 ) 2 (7)
Then, the conduction loss due to the DC and ripple currents can be directly expressed from the design freedom parameters {𝑓 𝑠𝑤 , 𝑊 𝑖 , 𝐿} as:

𝑃 𝑐𝑜𝑛𝑑 = (𝐼 𝑜 2 + 1 12 (𝐷 𝑐 𝑉 𝑖𝑛 -𝑉 𝑜 𝐿 𝑓 𝑠𝑤 ) 2 ) (𝐷 𝑐 𝛬 1 𝑊 1 + (1 -𝐷 𝑐 ) 𝛬 2 𝑊 2 ) (8)
The transfer loss due to the inductor series resistance R ind can be expressed as:

𝑃 𝑡𝑟𝑎𝑛𝑠 = 𝑅 𝑖𝑛𝑑 𝐼 𝐿 𝑅𝑀𝑆 2 = 𝐿 𝐹𝑜𝑀 𝐿 (𝑆) (𝐼 𝑜𝑢𝑡 2 + 1 12 ( 𝑉 𝑜 𝑉 𝑖𝑛 𝑉 𝑖𝑛 -𝑉 𝑜 𝐿 𝑓 𝑠𝑤 ) 2 ) (9)
where 𝐹𝑜𝑀 𝐿 (𝑆) is the Figure of Merit (FoM) 𝐿/𝑅 𝑖𝑛𝑑 of the inductor of surface 𝑆.

The sum of the losses described above can be factorized to highlight the effect of the free design parameters{𝑓 𝑠𝑤 , 𝑊 𝑖 , 𝐿}:

𝑃 𝑙𝑜𝑠𝑠 = 𝑃 𝑠𝑤 + 𝑃 𝑐𝑜𝑛𝑑 + 𝑃 𝑡𝑟𝑎𝑛𝑠 = 𝐴𝑓 𝑠𝑤 ∑ 𝑊 𝑖 + (𝐹 ( 1 𝑊 1 + 𝐺 𝑊 2 ) + 𝐽𝐿) (1 + 𝐻 𝐿 2 𝑓 𝑠𝑤 2 ) (10)
where 𝐹, 𝐺 and 𝐻 are constants depending on the CMOS technology used and the design constraints (load, input voltage).

Only CCM is studied here because this technique is wellspread for high power density converters [START_REF] Villar-Pique | Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach[END_REF][START_REF] Lee | Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies[END_REF]. Then, DCM and BCM are out of the scope of this paper. The softswitching technique for an inductive-base converter could be a relevant solution to decrease the switching loss but we decided to compare the three converter families with the most basic behavior to show the root limitations of each structure without design refinement. As shown in the state-of-the-art, there is a lack of comparison even using the simplest design structures.

As for the capacitor-based converter, the inductor-based converter exhibits an optimal sizing maximizing the power efficiency under particular input and output voltages, die area and load value. Section V gives the optimization results under the specifications targeted in this paper.

B. Output voltage

For the same reason as in Section 2, the value of the output voltage has to be found in order to calculate the loss expression [START_REF] Uzun | Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System[END_REF] and the efficiency. At steady-state, the linear model of the converter is the same as that of a capacitor-based converter (cf. Section 2.B.), except for the value of 𝑅 0 and that the ratio of the ideal transformer is 1: 𝐷 𝑐 . 𝑉 𝑜 can then be expressed as:

𝑉 𝑜 = 𝐷 𝑐 𝑉 𝑖 𝑅 𝑙𝑑 𝑅 𝑙𝑑 +𝑅 𝑜 (11)
where

𝑅 𝑜 = 𝐿 𝐹𝑜𝑀 𝐿 (𝑆) + 𝐷 𝑐 𝛬 1 𝑊 1 + (1 -𝐷 𝑐 ) 𝛬 2 𝑊 2

IV. RESONANT-BASED CONVERTER

Although numerous architectures of resonant-based converters exist, the topology, shown in Figure 4, has been selected for its intrinsic performance (low switch count and straightforwardness) and to provide the finest comparison with the capacitive converter. The structures of those circuits are indeed similar, except that the flying capacitor of the capacitive converter is replaced by an LC tank as published in [START_REF] Stauth | A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management[END_REF][START_REF] Cuk | Storageless step-down switching DC-DC converter[END_REF][START_REF] Kesarwani | Resonant Switched-Capacitor Converters for Chip-Scale Power Delivery: Design amp; Implementation[END_REF][START_REF] Hamo | Modeling and Analysis of Resonant Switched Capacitor Converters with Free-Wheeling ZCS[END_REF][START_REF] Cheng | New generation of switched capacitor converters[END_REF].

A. Loss mechanism

The resonant topology exhibits its highest efficiency at the resonant frequency, here

𝑓 𝑟𝑒𝑠 = (2𝜋√𝐿 𝑟𝑒𝑠 𝐶 𝑟𝑒𝑠 ) -1
. With a high-Q tank at its resonant frequency, and by considering only the fundamental of the Fourier decomposition of the current and voltage signals of the converters, there is no large error and the analysis is greatly simplified. This approximation is used below to describe the loss mechanism.

The switching and conduction losses can be expressed as:

𝑃 𝑠𝑤 + 𝑃 𝑐𝑜𝑛𝑑 = 𝜆 𝐶 𝑖𝑛 𝑓 𝑠𝑤 𝑉 𝑖𝑛 2 ∑ 𝑊 𝑖 + 1 2 𝐼 𝑟𝑒𝑠 𝑅𝑀𝑆 2 ∑ 𝑅 𝑑𝑠 𝑜𝑛 (𝑀 𝑖 ) (12)
where 𝐼 𝑟𝑒𝑠 𝑅𝑀𝑆 2 is the RMS current in the resonator.

At the resonant frequency, the RMS LC tank current can be expressed thus:

𝐼 𝑟𝑒𝑠 𝑟𝑚𝑠 = 𝜋 2√2 𝐼 𝑜 (13)
Then:

𝑃 𝑐𝑜𝑛𝑑 = 𝜋 2 16 𝐼 𝑜 2 ∑ 𝛬 𝑖 𝑊 𝑖 (14)
The transfer losses are due to the tank parasitic resistance R s and the bottom plate capacitance C bot of C res so that: [START_REF] Stauth | A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management[END_REF] where α is the fraction of the resonator die area dedicated to integrating the resonant capacitor.

𝑃 𝑡𝑟𝑎𝑛𝑠 =
Finally, considering only the parameters yet to be optimized {𝑊 𝑖 , 𝑓 𝑟𝑒𝑠 , 𝛼}, the power loss can be expressed as follows (N.B. valid only at the resonant frequency):

𝑃 𝑙𝑜𝑠𝑠 = 𝐴𝑓 𝑟𝑒𝑠 ∑ 𝑊 𝑖 + 𝜋 2 8 𝐵 ∑ 𝛬 𝑖 𝑊 𝑖 + 𝐾 𝛼 (1 + 𝑁 𝑓 𝑟𝑒𝑠 2 √1-𝛼
) + 𝑄𝛼𝑓 𝑟𝑒𝑠 [START_REF] Villar-Pique | Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach[END_REF] where 𝐾, 𝑁 and 𝑄 are technology-and design-dependent constants. As for the other topologies, the resonant-based converter exhibits optimal sizing thus maximizing the power efficiency.

B. Output voltage

The linear model of this converter is identical to that of the capacitive-based converter. Hence, the expression for 𝑉 𝑜 is: The next section compares the power efficiencies of the topologies under study in similar conditions.

𝑉 𝑜 = 𝑅 𝑙𝑑 𝑅 𝑙𝑑 +𝑅 𝑜

V. TOPOLOGY COMPARISON

A. Loss distribution comparison

The expression of the switching, conduction and transfer losses of the three topologies are summarized in Table 1. times lower with the same total width ∑ 𝑊 𝑖 . The resonance phenomena avoids the charge-sharing loss of the capacitive topology (𝐸/𝑓 𝑠𝑤 ) but adds loss due to the equivalent series resistor of the LC tank. Further general comparison is difficult due to the effect of each constant value (𝐴 to 𝑄) depending on the technology, and input and output constraints.

The authors have chosen a particular application target, similar to the common industrial specification, to compare the three structures. It is important to note that the compact equations given above could be quickly solved by an IC designer to find their own optimal design parameters for other converter constraints and technology node. The following sections therefore only illustrate one particular result from the proposed method.

B. Converter specifications and process parameters

The three topologies are compared using the same following constraints:

 Technology = 65nm CMOS technology from STM is chosen to integrate the converters in a standard technology.  Die-size = a constant 1mm² die area is dedicated to the passive components transferring the energy i.e. 𝐶 𝑓𝑙𝑦 , 𝐿, {𝐿 𝑟𝑒𝑠 , 𝐶 𝑟𝑒𝑠 }. The size of the switching cell is not considered in the first step.  Input/output characteristics = the input supply voltage 𝑉 𝑖𝑛 is set at 1.8V, provided by an external DC-DC converter; the output 𝑉 𝑜 is ideally bypassed to limit its ripple to 5%.  Load = the converters are loaded by a resistor 𝑅 𝑙𝑑 inducing 0.1, 1 and 10W power dissipation under ½ conversion ratio (i.e. 𝑉 𝑜 = 0.9V). Thus, nine circuits i.e. three topologies at three different power levels are studied.  Switching cell design = switches are MOSFET-type transistors with thick oxide. The double oxide option is used to have 2.5V breakdown voltage transistors. Although the voltage applied to the transistors of the capacitivebased converter is equal to 𝑉 𝑖𝑛 /2 at steady state for a conversion ratio of ½, it is as high as 𝑉 𝑖𝑛 at start-up and if the output voltage is modulated. Input voltage rated transistors are therefore required. Dead-time effects are also incorporated in the simulation results.  On-die capacitor = n-well polysilicon and metal-metal capacitors are stacked to achieve the highest capacitance density in the considered technological node [START_REF] Aparicio | Capacity limits and matching properties of integrated capacitors[END_REF]. The MIM option is not used.  On-die inductor = the inductors are a stack of five layers of metal (M3-M7). Metal layers M1 and M2 are not used to minimize the coupling with the substrate. Coils are planar and octagonal, and designed to maximize the 𝐿/𝑅 𝑖𝑛𝑑 ratio. Table 2 summarizes the process parameters used in the following optimization.

C. Consideration of the energy densities of the passives

We know that the output power of a capacitor-based converter is proportional to the voltage ripple across its flying capacitor whilst that of an inductive-based converter is proportional to the mean current in its coil. We have observed that there is no direct correlation between the maximum energy densities of integrated passives and the output power of the converters using them. Extreme care should therefore be taken when attempting to compare topologies according to the stored energy density of their passives. The energy density of an inductor being a decade lower than that of a capacitor (see Table 4) should not lead one to believe that the power density of the inductive converters is intrinsically lower than that of the capacitive ones.

D. Two-step optimization procedure

The optimization focuses on the ½ step-down conversion ratio since it achieves the best results for the capacitor-and resonant-based converters.

1) Global optimization

Based on equations ( 2), ( 10) and ( 15), the optimization procedure finds the peak efficiency with respect to the free design variables. Three converters of each topology are optimized using different load resistors, according to the specifications stated above. When a ½ transfer ratio is achievable (i.e. in the inductive converter), we maximize the efficiency at this conversion value; otherwise, the optimization aims to achieve the highest possible efficiency, while disregarding the associated transfer ratio.

Optimization aims at giving the best values to the set of parameters ℱ 𝑡𝑜𝑝𝑜 describing each topology. The analytical computation of the partial derivatives of 𝑃 𝑙𝑜𝑠𝑠 with respect to the converter parameters provides the optimum values of these parameters in the models described in Sections II to IV. For each topology, we hence solve the system 𝒮 𝑡𝑜𝑝𝑜 such that:

𝒮 𝑡𝑜𝑝𝑜 = { 𝑑𝑃 𝑙𝑜𝑠𝑠 𝑑𝑥 = 0 | 𝑥 ∈ ℱ 𝑡𝑜𝑝𝑜 } , { ℱ 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒 = {{𝑊 𝑖 } 𝑖∈⟦1,4⟧ , 𝑓 𝑠𝑤 } ℱ 𝑖𝑛𝑑𝑢𝑐𝑡𝑖𝑣𝑒 = {{𝑊 𝑖 } 𝑖∈⟦1,2⟧ , 𝑓 𝑠𝑤 , 𝐿} ℱ 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑖𝑣𝑒 = {{𝑊 𝑖 } 𝑖∈⟦1,4⟧ , 𝑓 𝑟𝑒𝑠 , 𝛼} 2

) Local optimization

A local post-optimization of these parameters is then conducted through transistor-level simulations in order to take into account the losses neglected in the proposed models such as MOSFET output capacitance. As shown in Table 3, the analytical equation and transistor-based simulation gives similar results. The second step i.e. local optimization improves the result accuracy.

3) Two-step optimization results

The effective metric of the technology used and the optimal component sizing are given in Table 4 when all free variables are adjusted to achieve the highest efficiency close to 1.8V to 0.9V conversion.

E. Discussion of optimal design parameters

In the inductive and resonant converters, the inductor value diminishes with the output load, thus decreasing its losses and allowing a higher energy transfer. Likewise, this phenomena is responsible for the switches of capacitive-based converters being narrower than that of a resonant-based converter.

In buck converters using discrete inductors, potentially exhibiting high efficiency and high inductance, the inductor current ripple 𝑟 = 𝛥𝐼 𝐿 /𝐼 𝐿 is often set to about 20% [START_REF] Sullivan | Integrating Magnetics for On-Chip Power: A Perspective[END_REF]. Nonetheless, in our circuit using a low value inductance and a high switching frequency, simulations have shown that it is best to choose 𝑟 > 100%, hence remaining in continuous conduction mode whilst allowing negative current to flow into the coil.

The 𝐶 𝑡𝑎𝑛𝑘 value required to maintain less than 5% output ripple in non-interleaved converters is at most 450nF and is not integrated on-die. Interleaving allows reduction of 𝐶 𝑡𝑎𝑛𝑘 [START_REF] Stauth | A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management[END_REF], but the need for a bypass is greater in a resonant than a capacitive converter because the flying capacitor of the capacitive topology inherently bypasses the output [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF].

In resonant mode, the overvoltage appearing across the resonant capacitor induces stress thus prohibiting the use of high-density thin oxide polysilicon capacitors (1.2V max in CMOS 65nm). A thick oxide polysilicon capacitor (2.5V max) is thus mandatory, decreasing its density. This topology uses a small inductor to resonate. Small rising and falling times induce high 𝑑𝑖/𝑑𝑡 and 𝑑𝑣/𝑑𝑡, which are potentially detrimental to the circuit. However, the simulations do not incorporate parasitic inductances which would limit the actual stress on the components. The 𝐹𝑜𝑀 of the switches and the capacitor are only technology dependent whereas that of inductors depends on the design. In fact, for first order and for a planar inductor, 𝐹𝑜𝑀 𝐿 (𝑆) ∝ √𝑆. This highlights the fact that inductive-based converters are best suited for high power and large die-area applications.

Figure 5, deduced from [START_REF] Uzun | Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System[END_REF], shows the influence of the FoM of the inductor of the inductive converter optimized according to the specifications stated in Section V.B at 𝑅 𝑙𝑑 = 0.81Ω on the overall efficiency at 𝑉 𝑜 /𝑉 𝑖𝑛 = 0.5. All the parameters but 𝐹𝑜𝑀 𝐿 are those of the 65nm CMOS technology. The point on the x-axis at 8.4nH. Ω -1 indicates the FoM of the coil used in this work. This clearly shows that implementing the inductor of the lowest achievable resistance should be the first concern of the IC-designer.

F. Efficiency comparison of the optimized converters

In an inductive converter, varying the duty cycle of the control signal modulates the output voltage without reducing the efficiency. In the capacitor-and resonant-based converters, the conversion ratio is modulated by the switching frequency, which leads to additional energy transfer losses. Based on transistor level simulations, Fig. 6 shows the power efficiency over the conversion ratio of the nine optimized converters (three per topology, three per load value), where all free variables are adjusted.

The inductor-based topology appears to maintain a more constant efficiency over a wide voltage range, although the study does not include reconfigurable topologies for switched capacitors nor resonant converters. Using the results from Fig. 6, Figure 7 shows the peak power efficiencies of the optimized converters vs power density.

At the lowest power density i.e. at 𝑅 𝑙𝑑 = 8.1Ω, the capacitor and resonant-based converters achieve the best performance. The high switching frequency of the inductorbased converter (160MHz, see Table 4) required to maintain low current ripple, decreases the efficiency at high 𝑅 𝑙𝑑 values. At higher power density, the resonant-based converter is superior to other topologies, due to quite a high LC quality factor and lower switching frequencies. The inductor-based converter dominates the capacitor topology at the highest power density. The higher energy density of the capacitor compared to the inductor (10 times here) does not directly lead to higher efficiency. At those three points, the capacitor-based converter works in SSL [START_REF] Le | Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters[END_REF]. Nonetheless, the switch voltage stress could be a key issue at high input voltage in inductive and resonant-based converters if thin oxide transistors were used. In fact, in those topologies, voltages up to 𝑉 𝑖𝑛 + 𝑉 𝑓 (where 𝑉 𝑓 is the threshold voltage of a body diode) are applied to transistors, while it does not exceed 𝑉 𝑖𝑛 -𝑉 𝑜 in a capacitive-based converter, in steady-state.

It is also important to highlight that the results could vary at other technology nodes or with additional options (high capacitance density or low resistivity metal layer) or using numerous design refinements (interleave, multiple ratio, variable sizing, multiple inputs) or using 3D integration.

Finally, this paper underlines the superior efficiency of the resonant topology compared to the capacitor one mainly because the charge-sharing loss is avoided.

VI. CONCLUSION

This paper provides a technology independent method and a practical use case to compare three particular, but well-spread, DC-DC converter topologies for chip-scale power management. The compact analytical equations of the power losses based on a few CMOS technology parameters are given for three hard-switching converter topologies (capacitive-, inductive-and resonant-based). Derived from these technology independent models, the loss mechanism analysis reviews the loss distribution between the conduction, switching and energy transfer losses and the energy requirement in the intermediate storage element. This method could help the system-level designer to select the passive nature of the converter, predict the achievable efficiency in hard-switching conditions, validate a CMOS technology choice, or compare some technologies. As only three particular topologies are studied here, the circuit-level designer has to find the best design refinement e.g. interleave or coupled passives in the family converter and technology node chosen by the system-level designer.

To derive the proposed method, a common standard 65nm CMOS technology has been chosen to fully integrate the active and passive elements of the converters. Based on the analytical derivations, the three monolithic topologies under study were then designed and optimized over three decades of power delivery on a 1mm 2 passive die area with a focus on the ½ conversion ratio. Refined using transistor-level simulations, the study confirmed that the capacitor-based converter is a good candidate to provide efficient on-die step-down power up to 1W/mm 2 , corresponding to one decade less than the industrial target for an on-chip digital core supply [START_REF] Ramadass | A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS[END_REF]. Above this power density, other topologies appeared more appropriate, especially the resonant-based converter, mainly due to the best passive energy utilization. This promising topology provides more lossless energy transfer than the others, but further research has to study its lossless controllability and its active and passive component stress management related to low voltage CMOS technology.

VII. ANNEXES

A. Assumptions

This paper focuses on a non-isolated DC-DC converter fully integrated in CMOS technology (active and passive parts). For process compatibility, only air-core inductors are considered here. All intermediate energy storage includes an equivalent series resistor and a bottom plate capacitor. The output is ideally bypassed to model the output as an ideal voltage source and simplify the analytical expression. The resonant frequency of the inductive part is assumed to be at least 10 times higher than the switching frequency (verified using a specific tool). For the optimization, we assume that the predominant area is consumed by passives. The areas given in Section V include the passive elements for energy transfer, but not the bypass capacitor 𝐶 𝑡𝑎𝑛𝑘 . The comparison is made without design refinement (no soft-switching, interleave, or DCM) or feedback control to maintain a fair comparison between the power stages of "basic" power transfer topologies.

B. 𝛬 𝑖 parameters

For each topology, the losses have been divided into the switching loss 𝑃 𝑠𝑤 mainly due to the input capacitance of the power transistors, the conduction loss 𝑃 𝑐𝑜𝑛𝑑 due to the load current into the on-state resistance of the power transistors, and the transfer loss 𝑃 𝑡𝑟𝑎𝑛𝑠 caused by the energy transfer mechanism itself. 𝑓 𝑠𝑤 is the switching frequency. 𝑊 𝑖 is the width and 𝑅 𝑑𝑠 𝑜𝑛 (𝑀 𝑖 ) is the on-state resistance of the transistor 𝑀 𝑖 . Moreover, for each transistor 𝑀 𝑖 , we define coefficient 𝛬 𝑖 = 𝑊 𝑖 ⋅ 𝑅 𝑑𝑠 𝑜𝑛 (𝑀 𝑖 ) which characterizes the polarity and gate drive level of each transistor. In fact, in some cases (cf. section III) the actual driving voltage 𝑉 𝑔𝑠 is not the same for all transistors. Moreover, a P-MOSFET is more resistive than the N-MOSFET of the same geometry. Those parameters are accounted for in parameter 𝛬 𝑖 , which can also be expressed as:

𝛬 𝑖 = 𝜆 𝑅 𝑖 𝑉 𝑔𝑠 0 -𝑉 𝑇 𝑉 𝑔𝑠 𝑖 -𝑉 𝑇 or 𝑅 𝑑𝑠 𝑜𝑛 (𝑀 𝑖 ) = 𝛬 𝑖 𝑊 𝑖 [START_REF] Seeman | A comparative analysis of switched-capacitor and inductorbased dc-dc conversion technologies[END_REF] where 𝜆 𝑅 𝑖 is the resistivity of the transistor 𝑀 𝑖 driven by 𝑉 𝑔𝑠 0 , 𝑉 𝑇 is the threshold voltage and 𝑉 𝑔𝑠 𝑖 is the actual driving voltage. It must be emphasized that 𝛬 𝑖 is not a free parameter to be chosen by the designer but constrained by the design. 𝛬 𝑖 might be seen as an effective channel resistance.

C. Unified constant expressions

The unified constant expressions are given in Table 5.

Fig. 1 .

 1 Fig. 1. Switched power converter principle.

Fig. 2 .

 2 Fig. 2. Capacitor-based converter schematic.

Fig. 3 .

 3 Fig. 3. Buck converter schematic.

Fig. 4 .

 4 Fig. 4. Resonant-based converter.

Fig. 5 .

 5 Fig. 5. Efficiency of the optimized inductive-based converter vs. FoM L at 𝑉 𝑜 /𝑉 𝑖 = 1/2 and 𝑅 𝑙𝑑 = 0.81Ω.

  FoM of the Inductor on the max Efficiency of the Optimised Buck Converter FoM L (nH. -1

Fig. 6 .

 6 Fig. 6. Transistor level simulation results: efficiency of the nine converters v. transfer ratio for three nominal loads, for 1mm² passive areas.

Fig. 7 .

 7 Fig. 7. Peak efficiency of the three topologies under test vs power density.

  𝜆 𝐶 𝑖𝑛 𝑓 𝑠𝑤 𝑉 𝑖𝑛 2 ∑ 𝑊 𝑖 ⏟ 𝑊 𝑖 } are the design freedom parameters. The different notations are defined in Table2and the Annex. Equation (2) may be rewritten to highlight the part of each free parameter {𝑓 𝑠𝑤 , 𝑊 𝑖 } so that:𝑃 𝑙𝑜𝑠𝑠 = 𝐴𝑓 𝑠𝑤 ∑ 𝑊 𝑖 + 𝐵 ∑

			+	1 2 ⏟ 𝐼 𝑜 2 ∑	𝛬 𝑖 𝑊 𝑖	+
	𝐼 𝑜 2 𝑅 𝑠 ⏟ Flying capacitor ESR	MOSFET input capacitance impedance 𝑅 𝑑𝑠 𝑜𝑛 + 𝑉 𝑜 2 𝑘 𝑏𝑜𝑡 𝐶 𝑓𝑙𝑦 𝑓 𝑠𝑤 ⏟ Switched Capacitor Bottom plate + 𝐼 𝑜 2 1 4𝐶 𝑓𝑙𝑦 𝑓 𝑠𝑤 ⏟	(2)
	where {𝑓 𝑠𝑤 , 𝛬 𝑖 𝑊 𝑖	+ 𝐶 (1 + 𝐷𝑓 𝑠𝑤 +	𝐸 𝑓 𝑠𝑤	)

TABLE I SUMMARY

 I OF THE EXPRESSIONS OF THE LOSSESFrom this table, it can be seen that the values of the free variables are different in each topology, depending on the global optimization of the overall losses. Compared to the capacitor based-converter, the conduction loss in the resonant

				Inductive			Capacitive	Resonant At resonance
	𝑷 𝒔𝒘	𝜆 𝐶 𝑖𝑛 𝑓 𝑠𝑤 𝑉 𝑖𝑛 2 ∑ 𝑊 𝑖		𝜆 𝐶 𝑖𝑛 𝑓 𝑠𝑤 𝑉 𝑖𝑛 2 ∑ 𝑊 𝑖	𝜆 𝐶 𝑖𝑛 𝑓 𝑠𝑤 𝑉 𝑖𝑛 2 ∑ 𝑊 𝑖
	𝑷 𝒄𝒐𝒏𝒅	[𝐼 𝑜 2 + [ 𝑉 𝑜 𝑉 𝑖𝑛	1 12 𝛬 1 (𝐷 𝑐 𝑊 1 + 𝑉 𝑖𝑛 -𝑉 𝑜 𝑉 𝑖𝑛 -𝑉 𝑜 𝐿 𝑓 𝑠𝑤 𝑉 𝑖𝑛 𝛬 2 ) 2 𝑊 2 ]	] ⋅	1 2	𝐼 𝑜 2 ∑	𝛬 𝑖 𝑊 𝑖	𝜋 2 16	𝐼 𝑜 2 ∑	𝛬 𝑖 𝑊 𝑖
	𝑷 𝒕𝒓𝒂𝒏𝒔	𝐿𝐼 𝑜 2 𝐹𝑜𝑀 𝐿 (𝑆) + (𝑉 𝑖𝑛 -𝑉 𝑜 ) 2 12𝐿𝑓 𝑠𝑤 2 𝐹𝑜𝑀 𝐿 (𝑆)	𝐷 𝑐 2	𝐼 𝑜 2 𝑅 𝑠 + 𝑉 𝑜 2 𝑘 𝑏𝑜𝑡 𝐶 𝑓𝑙𝑦 𝑓 𝑠𝑤 + 𝐼 𝑜 2 1 4𝐶 𝑓𝑙𝑦 𝑓 𝑠𝑤	𝜋 2 8 + 32𝑓 𝑠𝑤 2 𝑅 𝑐𝑎𝑝 (𝑆) 𝐼 𝑜 𝛼 𝐼 𝑜 2 ⋅ (𝛼√1 -𝛼) -1 2 𝑆 𝜆 𝐶 𝐹𝑜𝑀 𝐿 (𝑆) + 𝑘 𝑏𝑜𝑡 𝛼𝑆𝜆 𝐶 𝑉 𝑜 2 𝑓 𝑠𝑤
	topology is	π 2 8

  Stacked thin oxide polysilicon and metal capacitors; (3) Although the analytical study takes into account the capacitor series resistance, it is neglected in the transistor level simulations.

	TABLE II
	65NM CMOS PROCESS PARAMETERS
	Parameter	Notation Value	Unit
	N-MOSFET channel resistivity (1)	𝜆 𝑅	1.3	kΩ. μm
	N-MOSFET threshold voltage(1)	𝑉 𝑇	0.51	V
	Gate capacitance per transistor unit length (1)	𝜆 𝐶 𝑖𝑛	1.7	fF/μm
	Integrated capacitance density for 𝐶 𝑓𝑙𝑦 and 𝐶 𝑟𝑒𝑠 (2)	𝜆 𝐶	16	fF/μm 2
	Bottom plate capacitance coefficient C bot = k bot C fly (2)	𝑘 𝑏𝑜𝑡	2	%
	Figure of Merit L/R ind of an integrated inductor for 1mm 2	𝐹𝑜𝑀 𝐿 (𝑆)	7	nH/Ω
	Equivalent Series Resistance of an integrated capacitor of surface 𝑆 (3)	𝑅 𝑐𝑎𝑝 (𝑆)	0	Ω. μm 2
	Note: (1) Thick oxide 280nm-long channel transistor, driving voltage
	1.8V; (2)

  𝑆 designates the die surface dedicated to the integration of 𝐶 𝑓𝑙𝑦 or 𝐿 or 𝐿 𝑟𝑒𝑠 & 𝐶 𝑟𝑒𝑠 .

					TABLE V
		EXPRESSION OF THE TECHNOLOGY AND CONVERTER-SPECIFICATION
				RELATED CONSTANTS
	A B C	𝜆 𝐶 𝑖𝑛 𝑉 𝑖𝑛 2 1 2 𝑉 𝑜 2 𝑅 𝑙𝑑 2 𝑉 𝑜 2 𝑅 𝑙𝑑 2 𝑅 𝑐𝑎𝑝 (𝑆)	E F G	(4𝐶 𝑓𝑙𝑦 𝑅 𝑐𝑎𝑝 (𝑆)) 𝑉 𝑜𝑢𝑡 2 𝑅 𝑙𝑑 2 𝐷 𝑐 Λ 1 1 -𝐷 𝑐 𝐷 𝑐 Λ 2 Λ 1	-1	2 𝑉 𝑜 2 𝐹𝑜𝑀 𝐿 (𝑆) 𝑅 𝑙𝑑 𝜋 2 8 2 𝑉 𝑜 2 𝑅 𝑐𝑎𝑝 (𝑆) 𝑅 𝑙𝑑 N (4𝜋 2 𝜆 𝐶 𝑆 𝑅 𝑐𝑎𝑝 (𝑆) 𝐹𝑜𝑀 𝐿 ) J K	-1
	D	𝑘 𝑏𝑜𝑡 𝐶 𝑓𝑙𝑦 𝑅 𝑙𝑑 2 𝑅 𝑐𝑎𝑝 (𝑆)	H	𝑅 𝑙𝑑 2 𝐷 𝑐 2 12	(	𝑉 𝑖𝑛 -𝑉 𝑜 𝑉 𝑜	)	2	Q	𝑘 𝑏𝑜𝑡 𝑉 𝑜 2 𝜆 𝐶 𝑆

Note:

This work was supported by the Commissariat à l'Energie Atomique et aux Energies Alternatives (CEA).

His research focuses on integrated power converters and actuators including modeling, circuit design and control techniques. He has published about 50 papers in these areas, especially in loudspeaker drivers.


Gaël Pillonnet

Thomas Martinez

Sub-Threshold Startup Charge Pump using Depletion MOSFET for a low-Voltage Harvesting Application

Keywords: DC-DC converter, charge pump, low-voltage startup, depletion MOSFET, energy harvesting interface, thermoenergy generator. I

This paper presents a fully integrated CMOS start-up circuit for a low voltage battery-less harvesting application. The proposed topology is based on a step-up charge pump using depletion transistors instead of enhancement transistors. With this architecture, we can obtain a self-starting voltage below the enhancement transistor's threshold due to its normally-on operation. The key advantages are the CMOS compatibility, inductor-less solution and no extra postfabrication processing. The topology has been simulated in 0.18µm technology using a transistor-level model and has been compared to the traditional charge pump structure. The depletion-based voltage doubler charge pump enables operation from an input voltage as low as 250mV compared to 400mV in an enhancement-based one. The proposed topology can also achieve other conversion ratios such as 1:-1 inverter or 1:N step-up.

INTRODUCTION

Ambient energy scavenging has become a key alternative to conventional batteries leading to self-powered devices and allowing maintenance-free operation of electronic devices especially wireless sensor nodes [START_REF] Vullers | Micropower energy harvesting[END_REF]. It solves the problem of battery lifetime by harvesting thermal, solar, chemical or mechanical energy directly from the system environment. Among those possibilities, thermo-electric generators (TEGs) exploit a temperature gradient to provide electric energy and are pertinent solutions for numerous applications which consume less than a few mW.

Due to the low temperature gradient in most applications, the TEG only delivers a DC voltage of a few hundred millivolts. The TEG output has to be adapted by a harvesting circuit in order to extract [START_REF] Montecuccp | Simple, Fast and Accurate Maximum Power Point Tracking Converter for Thermoelectric Generators[END_REF], step up the voltage and obtain a sufficient voltage in order to charge a battery or to directly power a sensor node. Due to the low power generated by the TEG, both extraction and conversion steps have to be achieved at the best power efficiency.

Another harvester circuit constraint is the "cold start" i.e. without initial energy when the battery is completely discharged. The harvester circuit therefore has to self-start with only the low voltage delivered by the TEG. The low-voltage cold-start (below 300mV) is a key bottleneck in the harvesting circuit design leading to an increase in size and startup time. This paper will address this key issue.

Several low-input voltage converters have been published in the literature. Some systems [START_REF] Montecuccp | Simple, Fast and Accurate Maximum Power Point Tracking Converter for Thermoelectric Generators[END_REF][START_REF] Carlson | 20mV input boost converter for thermoelectric energy harvesting[END_REF] use an initial energy to kick-start operation of the harvester circuit but it is not a completely autonomous solution after a long black-out period. Specific technology with low threshold voltage transistors could help decrease the lowest self-start voltage of the harvester circuit [START_REF] Shin | A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effet[END_REF]. Some researchers [START_REF] Huang | Low-Threshold Voltage Mutlipliers based on Floating-gate Charge-pums[END_REF][START_REF] Mendez-Delgado | A 300mV start-up circuit for energy harvesting systems[END_REF][START_REF] Chen | 0.18V input charge pump with forward body biaising in startup circuit using 65nm CMOS[END_REF] proposed to reduce the transistor threshold voltage. However, this is not enough to allow a cold start below few 100 mV and need postfabrication tuning. The start-up circuit can also be based on sub-threshold operation of transistors leading to a longer startup time. Other solutions associate transformer and normally-on transistors to enable a very low startup voltage of less than 50mV [START_REF] Degrenne | Self-starting DC:DC boost converter for low-power and low-voltage microbial electric generators[END_REF]. But the need for a larger PCB and cost are non-negligible for compact autonomous sensor nodes. The structures shown in [START_REF] Machado | 10mV-1V step-up converter fir Energy Harvesting Applications[END_REF][START_REF] Veri | A 40mV start up voltage DC-DC converter for thermoelectric energy harvesting applications[END_REF] with a 10mV start-up also require bulky inductors to implement the oscillator. In [START_REF] Ramadass | A batterey-less thermoelectric energy harvesting interface circuit with 35mV startup voltage[END_REF], they use a mechanically assisted startup to operate from a 35mV input but mechanical vibration is needed. Finally, some exotic components could be used to enable a low input cold start as in [START_REF] Shen | DC-DC converter Suitable for Thermoelectric Generator[END_REF] with a tunnel diode.

In this paper, a step-up charge pump using a depletion MOSFET is presented, and is designed to achieve a low-input voltage i.e. below the technology's threshold voltage enabling self-startup operation of a low-voltage harvesting application such as a TEG. Compared to the state-of-the-art, the circuit uses no inductive component or post-fabrication processing and is compatible with standard CMOS technology. The proposed architecture uses a depletion MOSFET to implement the switches instead of the well-known and basic enhancement MOSFET charge pump. The depletion transistor eliminates the effect of the threshold voltage and allows operation below this voltage. As the design is oriented towards self-starting, a second classical converter could be introduced to maintain high efficiency after the cold start. This paper first presents the limitation of the standard charge pump coupled to a low-voltage energy harvester. Then, the proposed architecture is presented. It is designed to maximize self-start low-voltage operation. The lowest achievable startup voltage is given and compared to the basic architecture based on transistor-level simulations in 0.18µm technology. Finally, some design refinements to improve the performance are discussed.

II. INPUT VOLTAGE LIMITATION OF AN ENHANCEMENT-BASED CHARGE PUMP

A. TEG model A TEG converts thermal energy into electrical energy using the Seebeck effect. A temperature gradient across the PN junction forces the charge carriers to move in from the hot to the cold side and thus creates a voltage proportional to the gradient as given below: Its value is around tens of millivolts per Kelvin [START_REF] Vullers | Micropower energy harvesting[END_REF]. Therefore, the harvester provides hundreds of millivolts over a difference of tens of Kelvin. However, this low-voltage generated by the TEG poses a major problem to self-supply the harvesting circuit without an external power supply. Moreover, the voltage generated by the harvester TEG is lower than V oc . In fact, the harvester can be modeled by an ideal voltage source V oc in series with a resistance R t which is proportional to the resistivity of the junction material. Thus, the output voltage of the TEG is lower than V oc depending on the sink current of the harvester circuit.

B. Step-up converter using an enhancement-based charge pump

A step-up converter could be designed using an inductive or capacitive-based converter. However, the former suffers from low performance in a high temperature environment due to the temperature dependence of the magnetic permittivity. In some thermal harvesting applications, the harsh environment does not allow use of magnetic materials. This paper will therefore focus on magnetic-less converter topology. V ϕi through buffers. The converter is connected to the TEG (U oc , R T ), doubles the input voltage V in and stores the harvested energy in a tank capacitor C tank .

C. Enhancement-based charge pump limitation

When a TEG is connected to a low temperature gradient, the input voltage V in could be inferior to the MOSFET's threshold value. Thus, the voltage dynamic prevents the N-and P-type transistors (T 1,2,3,4 in Fig. 1) from being fully turned on or off. Moreover, this structure cannot efficiently operate in the sub-threshold region due to the tiny current difference between the switch states (i.e. between V gs =0 and V gs =V in where V in <V th ). Fig. 2. Conversion ratio versus input voltage using the topology shown in Figure 1 Figure 2 shows the conversion ratio defined by the output to input ratio versus the input voltage using the topology shown in Figure 1. Here, the N-and P-type MOSFET thresholds are 0.56V and -0.7V, respectively (0.18µm technology node). As described above, the structure can start lower than the threshold voltage, but, it cannot be allowed to start below 400mV which is needed in some thermal harvesting applications.

III. LOW-INPUT SELF-STARTING CHARGE PUMP TOPOLOGY

To overcome the limitation of the topology described above, a normally-on device is required for the self-starting circuit. The paper proposes to replace the enhancement N-and P-type MOSFET by only N-type depletion transistors. Due to their negative threshold, the depletion MOSFET conducts at zero gate-source voltage V gs . They could then be used to start the charge transfer at low-input level.

A. Depletion MOSFET characteristic

The depletion transistors are also called "normally-on" or "native" transistors. This mode is only available for N-type in most standard CMOS technologies. It uses only the low-level P-doped silicon substrate (native doping) instead of P-well doping to form the MOSFET channel. This MOS structure forms a conductive channel beneath the gate oxide layer when the gate terminal voltage is at zero, then acts as a "normallyclosed" switch. The gate source voltage must be negative to turn off the transistor. The transfer characteristic comparison between depletion-and enhancement-mode transistors in 0.18µm technology is shown in Figure 3.

The depletion transistor is widely-used in over-voltage protection, power supply startup and telecommunication applications. However, to the best of our knowledge, the depletion MOSFET has not been used in a harvesting circuit to decrease input voltage. In addition, only a few published works [START_REF] Joita | An active switch improved Dickson charge pump implemented in a BCD process[END_REF][START_REF] Oh | Charge pump circuit for depletion-mode oxide TFTs[END_REF] use this type of transistor in charge pumps but for higher voltage applications.

B. Proposed architecture: depletion-based charge pump

The proposed topology of a Depletion-based voltage doubler Charge Pump (DCP) is shown in Fig. 4. It is composed of four N-type depletion MOSFETs T 1,2,3,4 , a flying capacitance C fly and a ring oscillator (not shown As in Fig. 1, the oscillator and gate drivers are still composed of enhancement MOSFETs supplied directly by the input voltage V in . The oscillator then works under the threshold voltage to generate the clock signal between 0 and V in , and the gate drivers deliver the same signal swing to the depletion MOSFET gates (V g,i ). In steady-state, Figure 5 shows the transistor states in both phases. The topology differs from Figure 1 because any transistors are not fully turn-off in both phases. In phase 1, transistors T 1 and T 3 are turned on whereas T 2,4 are blocked. This therefore creates the main conductive path from the input to charge the flying capacitor through T 1,3 . In phase 2, T 2 is conductive but T 3 is still blocked and T 4 is in on-state. The flying capacitor discharges into V out through T 2 and T 4 . The undesired conduction paths (e.g. T 1,3 in phase 2) send charge in the opposite direction making the circuit unable to boost the input to the ideal value (double the input here).

The issue with the proposed architecture is that the transistor cannot be fully turned off. Therefore, the main design consideration consists in distinguishing the different switch states to create a clear conductive path in both phases. Then, the optimal transistor sizing has to be found to balance the desired and undesired conductive paths. In the enhancementbased topology (Fig. 1), the on-state resistance is optimized in another way to balance the conduction and switching losses.

C. A good candidate for a "startup circuit"

The depletion transistor has a higher on-state resistance than the enhancement transistor for the same size, limiting the maximum achievable efficiency. Moreover, a not fully turned off behavior activates some undesired and inefficient conduction paths. Therefore, the proposed circuit is more suitable for a "startup circuit" than the "main harvesting circuit" which needs a higher achievable efficiency. After the startup phase without initial energy, the startup circuit provides enough energy to initialize the main circuit well. Then, a second harvester circuit using an ECP could be used to provide efficient conversion.

D. Topology refinement to reduce the startup time

The architecture presented in Fig. 4 could be improved by introducing two design refinements as shown in Fig. 6. The proposed High Swing Enhancement-based Charge Pump (HS-ECP) consisting of T 1,2,3,4 is now driven by buffers and an oscillator powered by V out and V neg . The V neg signal is provided by the inverter charge pump with 4 depletion transistors (T 5,6,7,8 ). At the beginning, the tank capacitor is directly charged by the input voltage through the normally-on transistors T 1,4 . Then, the ring oscillator can start and provides a clock signal from V neg to V out . The key point is to boost the driving voltage swing V ϕ1 and V ϕ2 by changing the power supply of the ring oscillator. The full turn-off of the switches T 1,2,3,4 avoids the undesired conduction described in the previous section. Using the additional charge pump inverter, this topology produces a better power efficiency and reaches the 1:2 conversion ratio.

E. Higher conversion ratio using DCP approach

A higher conversion ratio can be achieved by adding extra charge pump stages to the proposed converter in Fig. 4. Figure 7 shows the 1:4 DCP.

A. Comparison of ECP and DCP

The proposed circuits (DCP and HS-DCP) and the basic architecture (ECP) were simulated and compared in terms of their start-up input voltage capability. The size of the ring oscillator is the same for the three topologies. The oscillation frequency is 12.8 kHz at 0.3V. The TEG has a 10Ω internal resistance and the value of the flying and tank capacitors are 1nF and 10nF, respectively. The comparison is made using the same overall gate surface i.e.

. Figure 8 shows the conversion ratio regardless of the input voltage for the DCP, HS-DCP and ECP circuits in the doubler (Figs. [START_REF] Vullers | Micropower energy harvesting[END_REF][START_REF] Ramadass | A batterey-less thermoelectric energy harvesting interface circuit with 35mV startup voltage[END_REF][START_REF] Vullers | Micropower energy harvesting[END_REF]. As expected, the depletion modes allow lower input-voltage operation. With the HS-DCP, the output voltage is 150% higher than the input voltage at 250mV compared to 400mV with the ECP. The HS-DCP doubles the input voltage above 400mV compared to 500mV with the ECP. Comparison of the DCP and HS-DCP indicates the need to power the ring oscillator between V neg and V out . It is especially true when the input voltage is higher than 0.4V where the gate-source voltage is insufficient to turn on the transistor T 4 .

Figure 9 shows the performance of the HS-DCP for a higher conversion ratio. The startup circuit can provide conversion ratios greater than 2 (Figure 8) which allows voltages higher than 1V to be reached even with input voltages as low as 250mV for 1:8 topology.

B. Charging Time

Another advantage of the proposed circuit is to speed up the startup operation compared to the ECP. During the charging phase, the ECP transistors operate under their threshold voltage which leads to higher resistance and thus a longer charging time. In the DCP, the transistors always operate above their threshold voltage and allow more charge transfer at each period. Table 1 shows the startup time comparison in ms between both voltage doubler topologies (Fig. 1 and3). As shown in Fig. 8, the ECP cannot reach the step-up operation when the input voltage is below 400mV leading to an infinite startup time.

C. Performance comparison

The key advantages of the charge pump using a depletion transistor compared to the state-of-the-art are:

• standard CMOS process compatibility,

• fully-integrated passive component,

• no post-fabrication processing needed,

• relative low start-up voltage (~250mV in this technology). However, the main drawback of the proposed topology is the relatively low efficiency (around 50%). In fact, the depletion transistors are not fully turned off implying some leakage current. Therefore, this circuit is suitable as a startup function (cold start) but is insufficient for maximizing the power transfer from the harvester to the energy storage. The authors therefore suggest using a classical charge pump or inductive converter when the startup phase is finished.

V. CONCLUSION

To conclude, a low start-up voltage step-up DC-DC converter suitable for a battery-less harvester circuit is presented. The proposed charge pump topology is composed of a depletion transistor instead of an enhancement one to allow sub-threshold operation. The solution improves the low voltage self-starting of the charge pump circuit. The transistor level simulation done in 0.18µm CMOS technology shows a 250mV startup voltage using a depletion-based charge pump instead of 400mV in enhancement-based topology. The advantage compared to a state-of-the-art solution is to achieve a low voltage cold start for an energy harvesting circuit with standard CMOS technology without bulky external components or post-fabrication processing.

  and ∆T are the open-circuit voltage and temperature difference across the PN junction, respectively. The coefficient α represents the Seebeck effect strength [V/K].

Fig. 1 .

 1 Fig. 1. TEG harvester model and basic 1:2 charge pump with enhancement transistor (ECP) Figure 1 presents a basic 1:2 Enhancement-based Charge Pump (ECP) topology. It is composed of four enhancement MOSFETs and a flying capacitor C fly . The two phases are generated by a ring oscillator which drives the MOSFET gate

Fig. 3 .

 3 Fig. 3. Transfer characteristic of depletion-and enhancement-mode transistor

Fig. 4 .

 4 Fig. 4. TEG connection and 1:2 DCP

Fig. 5 .

 5 Fig. 5. Step-up capacitive switching converter in phase 1 and 2

Fig. 6 .

 6 Fig. 6. High Swing Depletion-based Charge Pump (HS-DCP)

Fig. 7 .

 7 Fig. 7. 1:4 depletion-based charge pump IV. RESULTS

Fig. 8 .Fig. 9 .

 89 Fig. 8. Conversion ratio v. input voltage for the three described topologies

TABLE I STARTUP

 I

			TIME (MS)
	Vin	Enhancement-based Charge Pump (ECP)	Depletion-based Charge Pump (DCP)
	0.25		18
	0.30		5.5
	0.35		3.7
	0.40	126	1.6
	0.45	23	1
	0.50	3	0.7
	0.60	0.04	0.5


Yohan Payan

A Perrier Abc

V Luboz

M Bucki

N Vuillerme

Conception and evaluation of a 3D musculoskeletal finite element foot model

Keywords: Foot model, Finite Element, Musculoskeletal, Motion Analysis, Plantar Pressure

Conception and evaluation of a 3D musculoskeletal finite

element foot model.

Introduction

Modelling the foot accurately is essential in understanding its behaviour under healthy and pathological conditions. For example, it has helped analysing risks of injuries in diabetic foot [START_REF] Chen | Effects of internal stress concentrations in plantar soft-tissue[END_REF]. This work aims at developing and evaluating a patient-specific Finite Element (FE) model of the foot in the context of pressure ulcer prevention, orthopedic and motion analysis. Using the most recent functional knowledge about foot anatomy is necessary to simulate functions such as support, weight bearing, locomotion or foot surgery and its consequences.

Methods

Modeling

The model has been developed using the 3D biomechanical simulation platform ArtiSynth (artisynth.org). Starting from a CT and an MRI exam of a single patient, 30 bones have been modelled as articulated rigid-bodies connected with cables that simulate the 210 segmented ligaments in their actual positions and therefore define the articulations with contact. The Aponeurosis is modelled with five parallel multipoint ligaments connected by transversal ligaments. 15 extrinsic and intrinsic Hill's model muscles have been positioned according to their anatomical course and can be independently activated in order to allow a natural movement of the foot. A FE mesh of the soft tissue was created by applying a new automatic FE mesh generator, TexiMesh (texisense.com), to the surfaces resulting from MRI and CT segmentation. The FE mesh has 142,060 elements (mainly hexahedrons) and 66,362 nodes. Three soft tissue layers with Neo Hookean materials (Young moduli, Poisson Ratio) were created to represent a 1mm skin layer (200kPa, 0.485), the fat (30kPa, 0.49) and muscle (60kPa, 0.495) tissues, Fig 2 A. A fourth layer represents the heel anatomical soft structure (100kPa, 0.4998).

Weight bearing evaluation

The foot model was first evaluated for static weight bearing position. We compared (Fig 1) simulated plantar pressure (SPP) with the real plantar pressure (RPP) collected in the same patient standing onto a Zebris FDM-SX platform. For this simulation, half of the patient's weight was applied onto the foot model while in contact with a horizontal finite element plate (Fig 1 B) having the same number of "sensors" as the Zebris platform (one element per sensor). In order to represent dynamic loading, the muscles first make a dorsiflexion before foot contact. We compare the mean pressure (MP) and peak pressure (PP) at platform surface after regionalization [START_REF] Gefen | Biomechanical analysis of the threedimensional foot structure during gait: a basic tool for clinical applications[END_REF] using a dedicated software, TexiLab (texisense.com). The real plantar pressures are the mean of four trials.

Dynamic evaluation

This evaluation was made during an adduction / abduction movement: a 3D motion analysis of the patient's foot was performed using the Leardini's marker set [START_REF] Leardini | An anatomically based protocol for the description of foot segment kinematics during gait[END_REF]. A needle and surface EMG monitoring of the Tibialis Posterior, Tibialis Anterior, Triceps and Peroneus muscles were used as inputs for the simulation. Local referential and regression equations were created to have 3D point comparison between virtual markers from motion analysis and real anatomical markers from CT reconstruction, to assess our model's motions resulting from simulated muscle activations (Fig 2). For the simulated and real kinematics (five trials), we compared the 3D angle formed by the mass center of the tibia, the mass center of the talus and the center of the second metatarsal head, considered as an anatomical axis of the foot. Angle measurements were also performed in 2D after projecting the reference points on the three anatomical planes.

*Corresponding author. Email: antoine.perrier@imag.fr

Movements were split into

• Dorsal/plantar flexion in the sagittal plane • Pronation/supination in the frontal plane,

• Abduction/adduction in the horizontal plane. These categories were made to facilitate a clinical interpretation of the results. In this paper, only the Abduction (ABD) / Adduction (ADD) kinematics is studied.

Results and discussion

Weight bearing simulation

Table 1 compares the simulated and real peak and mean pressures under the second (region 2) and the fourth/fifth (region 3) metatarsal heads. The simulated pressures are close to the real ones considering pressure measurement and subject weight uncertainties. In the second metatarsal area (region 2), the differences between RPP and SPP are about 0.6 N/cm2 for the MP and 1.6 N/cm2 for the PP (Tab 1). In the fourth and fifth metatarsal area (region 3), the differences are 1.9 N/cm2 for the MP and 0.9 N/cm2 for the PP. We assumed that our precise results regarding the literature are due to the use of the vertical component of the simulated platform's Von Mises Stress (VMS) instead of foot's skin plantar VMS in others studies.

Dynamic EMG simulation

Table 1 provides simulated kinematics with muscle activation using real EMG input. The corresponding 3D angle between the tibia and second metatarsal bone is 1.6% greater than real anatomical measurements for the maximum 3D angle and 3.9% smaller for the minimal 3D angle. More than 120° could be considered has a complex motion with adduction and plantar flexion. Less than 120° could be a synergic function of the dorsiflexion and the abduction. The projection angle, in the horizontal plane, is 0.4% greater in adduction and 1.8% smaller in abduction. These excellent results should be carefully analysed since the reference frame is fixed to the tibia during simulation, while it has a skin marker dependency for the real motion analysis. The projected angles could thus be misestimated and the difference could be greater. These results are preliminary and cannot be compared to other biomechanical finite element studies since it is, to our knowledge, the first time real EMG input was used for assessing foot motion during swing phase or unloading. Our work was limited to only one case since we wanted to evaluate the model with real data. It is important to note that our group has already proposed a methodology to easily adapt this single model to other patients' anatomy.

Other patient-specific simulations could thus be performed.

Conclusions

This paper has introduced a new musculoskeletal and finite element foot model providing realistic simulations in both static and dynamic frameworks.

The ranges of motion in dynamic, and plantar pressure in loading condition, are anatomically and clinically realistic.

Other studies using this model will simulate ankle arthrodesis or foot orthotics. The model could also become relevant for the simulation of neuroorthopedic surgical interventions, orthotic devices analysis or educational purposes like functional anatomy

Fig1

  Fig1: A. Real PP, B. Simulated PP, C. Stress visualization of the FE model in weight bearing position 2.3 Dynamic evaluationThis evaluation was made during an adduction / abduction movement: a 3D motion analysis of the patient's foot was performed using the Leardini's marker set[START_REF] Leardini | An anatomically based protocol for the description of foot segment kinematics during gait[END_REF]. A needle and surface EMG monitoring of the Tibialis Posterior, Tibialis Anterior, Triceps and Peroneus muscles were used as inputs for the simulation. Local referential and regression equations were created to have 3D point comparison between virtual markers from motion analysis and real anatomical markers from CT reconstruction, to assess our model's motions resulting from simulated muscle activations (Fig2). For the simulated and real kinematics (five trials), we compared the 3D angle formed by the mass center of the tibia, the mass center of the talus and the center of the second metatarsal head, considered as an anatomical axis of the foot. Angle measurements were also performed in 2D after projecting the reference points on the three anatomical planes.

  Fig 2: A. Finite Element model, B. Abduction kinematic, C. Adduction kinematic.

Acknowledgements

This work is partly funded by the French national project ANR -TecSan 2010-013 IDS


Alessandro Semere
email: a.semere@chu-grenoble.fr

Yohan Payan
email: yohan.payan@imag.fr

Francis Cannard
email: francis.cannard@texisense.com

Bruno Diot
email: b.diot@ids-assistance.com

Nicolas Vuillerme
email: nicolas.vuillerme@agim.eu

Using Sensory Substitution of Median Sensory Deficits in the Traumatized Hand to Develop an Innovative Home-Based Hand Rehabilitation System

Keywords: home rehabilitation, sensory substitution, hand trauma, median nerve

published or not. The documents may come

Introduction

Hand traumas strike 1,400,000 patients every year in France; 620,000 of them lead to severe injuries. They are essentially caused by everyday life, occupational, and road accidents [1]. In the severe cases, sequelae are frequent. This has an important socio-economical impact: according to the FESUM (Fédération Européenne des Services d'Urgence de la Main -European Federation of Hand Emergency Services), 1/3 of the occupational accidents involve the hand, 1/4 of the lost days of work is because of these traumas, 1/10 of the accidents leads to a PPD (Permanent Partial Disability, which is an index rating the permanent handicap resulting of a trauma, after consolidation) and 1/3 of the PPD is the result of hand accidents. On average, a hand accident with a work stoppage costs from 1,000 to 2,000 euro: 80% of this amount is represented by indemnities (half by work stoppages, half by IPPs). This handicap is more important as the lesions impair fine hand use of manual workers. Hand motricity can be restored thanks to palliative interventions: nerve grafts, neurotizations and tendon transfers. Innervated digital flaps can locally restore sensitivity, but the donor site is then shorn of its function. Finally, in case of pluridigital deficit, there is no complete mean of substitution. Multi-daily sensory rehabilitation can help to recover useful (although uneven) sensitivity, but needs motivation, discipline, time and patience. Unfortunately, access to daily training with a specialist is not always possible. The lack of time of the patients or their living distance from the physiotherapy office are also obstacles to the rehabilitation. Finally, the cost of the care can quickly become exorbitant.

The work of Bach-y-Rita on sensory substitution for the blind [START_REF] Bach-Y-Rita | Sensory substitution and the human-machine interface[END_REF] as well as the more recent scientific works on the Tongue Display Unit (TDU) for pressure ulcer prevention [START_REF] Chenu | A wireless lingual feedback device to reduce overpressures in seated posture: a feasibility study[END_REF], balance problems [START_REF] Vuillerme | Sensory supplementation system based on electrotactile tongue biofeedback of head position for balance control[END_REF] and the guiding of surgical gesture [START_REF] Robineau | Guiding the surgical gesture using an electro-tactile stimulus array on the tongue: a feasibility study[END_REF] have inspired the conception of an innovative device enabling to rehabilitate or to palliate these sensory deficits. Following this approach, this paper describes an innovative home-based hand rehabilitation system device that exploits sensory substitution of median sensory deficits in the traumatized hand.

Materials and methods

The device has been designed according to the organic facts and psychomotor theories on haptics. Its actual development was possible by the manufacture of smart textile pressure sensors [START_REF] Chenu | TexiCare: An innovative embedded device for pressure ulcer prevention. Preliminary results with a paraplegic volunteer[END_REF].

Physiopathology of hand nervous injuries

The hand is a complex organ. Its gripping functions are possible thanks to a perfect biomechanical structure made of bones, joints, ligaments and tendons. A two-way circuit controls these motor skills: the efferent nerve fibers command muscle contractions (motricity), the afferent nerve fibers give the central nervous system (CNS) a feedback of the force of these contractions and the actual localization of the fingers and joints in space (sensitivity), and the CNS synthesizes the inputs and outputs, coordinating the movements (integration). The three nerves carrying the efferent and afferent fibers are the median nerve, the ulnar nerve, and the radial nerve. Each of them has a different motor function and sensitive territory. The median nerve is functionally the most important to perform the bidigital grip: it innervates the flexor muscles of the fingers and the abductor muscles of the thumb, and its sensitive area covers the palmar side of the first, second, third, and radial side of the fourth finger. The sensitive and motor fibers circulate in mixed nerves. This implies that in case of complete section of a peripheral nerve, both efferent and afferent paths are interrupted. The treatment is nerve suture under optical magnifying, to restore the continuity of its channels and to guide the axonal regrowth. Nevertheless, the recovery is long and uneven. While motor skills often return to their previous level (or with a force limitation of 25% to 50%, but still functional), sensitivity is more problematic [START_REF] Najeb | Résultats de la réparation primaire des plaies du nerf médian et du nerf ulnaire au poignet[END_REF][START_REF] Lenoble | Résultats de la réparation primaire de vingt-huit plaies isolées du nerf médian au poignet[END_REF]. Recent works specifically implicate sensitive deficits in the troubles of the function of the thumb-index grip [START_REF] Witney | The cutaneous contribution to adaptive precision grip[END_REF]. They suggest that a loss of sensitivity leads to an alteration of the coordination of fine gestures. Actually, we can observe during prehension a degraded control of the values of the pad pressure because of the lack of feedback, which leads to an increase of the security margins [START_REF] Witney | The cutaneous contribution to adaptive precision grip[END_REF][START_REF] Dun | Lower median nerve block impairs precision grip[END_REF][START_REF] Schenker | Precision grip function after hand replantation and digital nerve injury[END_REF][START_REF] Li | Peripheral median nerve block impairs precision pinch movement[END_REF][START_REF] Monzée | The effects of digital anesthesia on force control using a precision grip[END_REF][START_REF] Augurelle | Importance of cutaneous feedback in maintaining a secure grip during manipulation of hand-held objects[END_REF][START_REF] Hermsdörfer | Grip force control during object manipulation in cerebral stroke[END_REF][START_REF] Nowak | Selective deficits of grip force control during object manipulation in patients with reduced sensibility of the grasping digits[END_REF], as well as an increase of the variations of these pressures of 11%-12% (vs 5%-6% for a healthy individual [START_REF] Dun | Lower median nerve block impairs precision grip[END_REF]). This implies that for light charges, objects are involuntarily dropped [START_REF] Dun | Lower median nerve block impairs precision grip[END_REF][START_REF] Augurelle | Importance of cutaneous feedback in maintaining a secure grip during manipulation of hand-held objects[END_REF]. Moreover, the displacement of the center of pressure of digital pads during fine pinch is multiplied by 5 in sensitivity troubles [START_REF] Dun | Lower median nerve block impairs precision grip[END_REF], leading to an increase of the tangential forces followed by a rotation of the object. The patient responds inappropriately by increasing his security margin, which more often can lead to the dropping of the object [START_REF] Dun | Lower median nerve block impairs precision grip[END_REF][START_REF] Li | Peripheral median nerve block impairs precision pinch movement[END_REF]. These troubles are independent of the maximal grip force of the patient, which is reduced by 25% to 35% [START_REF] Witney | The cutaneous contribution to adaptive precision grip[END_REF][START_REF] Dun | Lower median nerve block impairs precision grip[END_REF]. Indeed, the security margins are studied only during the manipulation of light objects (less than 500g), needing a force of 10N for a maximal force of 50N [START_REF] Dun | Lower median nerve block impairs precision grip[END_REF]. Finally, we can note that anticipation of the movement and visual control during its execution tend to normalize these results [START_REF] Augurelle | Importance of cutaneous feedback in maintaining a secure grip during manipulation of hand-held objects[END_REF][START_REF] Hermsdörfer | Grip force control during object manipulation in cerebral stroke[END_REF][START_REF] Nowak | Moving objects with clumsy fingers: how predictive is grip force control in patients with impaired manual sensibility?[END_REF], compensating the lack of touch.

Sensory substitution

Sensory substitution is a concept introduced in the sixties by Professor Paul Bachy-Rita [START_REF] Bach-Y Rita | Vision substitution by tactile image projection[END_REF]. It consists of transforming the characteristics of one sensory modality into stimuli of another sensory modality. This has been used to restore the ability of people to perceive a certain defective sensory modality by using sensory information from a functioning sensory modality. In general, a sensory substitution device consists of one or several sensors, a coupling system and one or several stimulators. The sensor records stimuli and gives them to a coupling system that interprets these signals and transmits them to a stimulator. As stated above, the median nerve is the most important nerve implied in the fine grip, its injuries are fairly frequent, and its recovery is often poor. These facts and the literature [START_REF] Massimino | Improved force perception through sensory substitution[END_REF][START_REF] Visell | Tactile sensory substitution: Models for enaction in HCI[END_REF] led us to think that this concept of sensory substitution could be used to substitute the sensitivity of the median nerve by an artificial system, in order to improve the control of fine grip. The aim was to develop a device capable of transducing the sense of touch of this deficient area through another modality (true sensory substitution), or with the same modality (i.e. touch) but on another healthy localization. This needs a study of the sense of touch, together with a state of the art as concerns the existing artificial input and output systems.

There are 17 000 receptors in the glabrous hand, to sense the different types of stimuli: exteroceptive (pressure, stretching and vibrations), proprioceptive (positioning of joints in space), and thermoalgic (temperature and pain). Their stimulation is the first step of the afferent path. There are four basic types of exteroceptive receptors: Pacinian corpuscle, Meissner corpuscle, Ruffini endings and Merkel nerve endings. Each of them has a different response latency to stimuli (fast adaptive fibers FA or slow adaptive fibers SA), a variable pressure threshold, and various numbers of sensitive endings and depth under the skin [START_REF] Lederman | The physiology and psychophysics of touch. Sensors and sensory systems for advanced robots[END_REF]. This makes them more or less sensitive to pressure discrimination, spatial discrimination (two-point static detection), temporal discrimination (vibration), and stretching. The complexity of this system is high; it is therefore difficult to simulate precisely all of these criteria. Moreover, this is not necessarily suitable: indeed, an excessively exhaustive input information would proportionally complicate the output information. The result would be an increase of the cognitive load, hence a decrease of the accuracy and the speed of interpretation of the signal (which is exactly the opposite we are trying to achieve). For the development of the device, we have decided that our sensors will detect only useful pressure changes with a useful spatial discrimination. This feedback is essential for grip control and shape recognition. We finally dropped the detection of stretching and vibration. The sensitivity of a hand to pressures is high. In clinical routine, it is measured with Semmes-Weinstein monofilaments (SWM), which are semi-rigid nylon threads, calibrated to bend at a precise force [START_REF] Spicher | Manuel de rééducation sensitive du corps humain[END_REF]. A normal hand has a minimal sensitivity of 0.008 gf to 0.07 gf (grams-force, 1 gf=9.80665 mN), with a spatial discrimination of 2 mm to 6 mm. Finally, the high sensitivity of the fingertips is not always needed. Indeed, some zones are functionally more important than others. The grips mostly used are the key grip (pad of the thumb and of the radial side of the index), the needle-thread grip (tip of the thumb and of the radial side of the index), the tridigital grip (thumb, index and radial side of the middle finger), the button push (index tip and pad) and the lighter (pad and tip of the thumb).

To supply a sensory feedback, all of the five senses are theoretically useful and usable. However, for our application, we needed something light and easily bearable all day long in everyday life. Sight is naturally complementary to touch, even in healthy people [START_REF] Whitaker | Vision and touch: Independent or integrated systems for the perception of texture?[END_REF]. The evaluation of shape, volume and size of objects is done by eye control thanks to its wide receptive field, while textures are discriminated essentially by exploratory touch thanks to high vibrotactile accuracy. However, the only visual feedback about grip forces is given by the deformation or the slipping of the lifted objects, respectively translating the application of an excessive or an insufficient grip force, and leading to the breaking by fall or burst of non-deformable or fragile objects. We have decided not to implement a visual control, since it would overload this channel already sufficiently sought. Moreover, the permanent overlooking of a screen didn't seem appropriate for use in daily life. Hearing is a fast and precise modality of feedback, with great discriminatory amplitude, but we did not think that the permanent wearing of a headset would be comfortable for current use. Taste and smell are too slow, too imprecise and too variable according to physiological factors and seemed technically difficult to implement in our study. Touch was the first kind of feedback to be invented, and the simpler to implement. Moreover, simple and portable devices can be easily manufactured. We hence have decided to use this modality in our device.

Finally, touch can be stimulated by different kinds of devices [START_REF] Visell | Tactile sensory substitution: Models for enaction in HCI[END_REF]. Low frequency, low amplitude mechanical deformation, raising bumps against the skin and rendering a relief that can be explored by touch. One can distinguish between continuous contact with an object, and "make-and-break" contact, in which an object is brought in and out of contact with the body. The skin possesses an especially high sensitivity to the latter. For the same reason, Vibrotactile stimulations are also easily recognized, especially if frequencies are chosen to maximize Pacinian FA II receptor sensitivity (highest near 250Hz), and may be effectively transmitted through an air gap. Electrotactile stimulation excites the afferent nerves directly rather than the tactile receptors themselves, via electrodes of different types or by fine wires inserted into the skin. Various afferent types can be excited differentially through the design of the drive signal and electrical contacts. Force feedback is by nature meant to access primarily the kinesthetic haptic channel. However, when force feedback devices interact with the cutaneous tactile sense, friction phenomena, vibration, or contact transients are inevitably generated. We found thermal and air or liquid jets displays too slow or complicated to be implemented in this project.

We decided to develop a vibrotactile device, acting as a low frequency mechanical stimulator. In other words, the various forces sensed would be coded by variable bursts (in duration and/or in frequency) of constant high frequency vibrations.

Results

The device presented here is composed of three distinct elements:

(1) a glove (bearing smart textile pressure sensors), (2) a software (receiving the data form the sensors, treating and recording the signal), and

(3) a wristband, providing vibrotactile feedback.

When the user grasps an object with his fingers, the wristband vibrates according to the pressure measured by the sensors. The sensory-impaired patient would have the possibility to use vibrotactile biofeedback to control his grip and to maintain an appropriate force to avoid the involuntary dropping of objects.

The glove (Texisense®) bears eight textile polyamide (nylon) sensors, thin-film coated with a piezo-resistive polymer (Fig. 1a). Each sensor is circular and has a 1 cm diameter. These sensors are fixed to the glove with glue and threads. They are placed on the three first fingers, four on the tip and pad on radial and ulnar sides of the thumb and two on the tip and pad on radial side of the index and middle finger. Each of them is connected to two conductive threads coated with silver. The threads run across the dorsal side of the glove, and are connected to metal buttons placed on the back of the wrist. Then, sixteen regular soft wires connect the glove to the acquisition circuit, powered by a 32 bit microcontroller unit (STM-32 Cortex from ST Microelectronics), which can be connected to a computer by a regular mini-USB to USB connection.

ST Microelectronics has provided the drivers for Microsoft Windows, which create and manage a virtual COM port between the glove and the computer. The signal acquisition and treatment software (Fig. 1b) has been written in C++ using The feedback system is composed of a rubber and plastic wristband, containing an eccentric-mass brush motor and an USB motor controller. A Bluetooth vibrating wristband for mobile phones (MB20, Movon®) has been disassembled to keep only the motor (1.3 V, 70 mA, 9000-12000 rpm), and a serial resistor (100 Ohm, 1% tolerance) has been added. The power is provided by a 6V external stabilized transformer, via a modified USB cable. The control unit is an USB commercial motor controller (PhidgetMotorControl LV 1060, Phidgets®), powered by USB, and able to control the acceleration and velocity of the low-voltage brush motor thanks to the provided C++ librairies. Bursts of vibrating impulses are generated to provide vibrotactile feedback. The vibrotactile stimulation is absent if the mean value of the activated sensors is lower than 278 gf, becomes continuous if between 278 gf and 555 gf, then alternating gradually slower with the increase of the pressure. Over 1390 gf, the frequency of alternation is slow and constant.

We calibrated the sensors with an electronic precision scale (Mettler PE 1600, Max 1600g, Min 5g, e=0.1g, dd=0.01g), a laboratory articulated chassis, with an infra-millimetric manual movement control, and a metal cylindrical piece (diameter = 8 mm), isolated at its tip by a rubber band. Each sensor has been put on the balance (a) (b)

and under the cylindrical piece. A piece of wood has been put under and inside the glove. This avoids short-circuits between the sensors, the threads and the balance board. After putting the balance to zero, the cylindrical part was progressively lowered, until the desired force was obtained. These forces have been obtained by the conversion of the forces F (in gf) given by SWM in pressures P (Pa), by the formula P=F/S, where S is the surface of the section of the SWM given by the literature [START_REF] Bell-Krotoski | The repeteability of testing with Semmes-Weinstein monofilaments[END_REF].

Then, each pressure value has been converted to a force value considering the section of the 8 mm diameter cylindrical metal piece. Finally, the raw value displayed by the software was then reported in a table. The raw curves have been drawn, and the equations of mean root square deviation lines have been calculated (Fig. 2). The latter are used by the software to convert the raw values to grams-force and to Newtons. The evolution after constant stimulation (278 gf) has been measured, to look for the implication of this mixed effect in time (Fig. 3). After one minute, the evolution is negligible (Maximum = 2.7%).

Discussion

The presented work described an innovative home-based hand rehabilitation system device. It is composed of a glove bearing smart textile pressure sensors and a wristband providing vibratory biofeedback to the user that could be employed for training and rehabilitation exercises at home. This device exploits the concept of sensory substitution of median sensory deficits in the traumatized hand. It is designed to provide for patients an effective method to rehabilitate or to compensate the lack of sensitivity of the finger pads and to recover a functional hand use.

By showing that this device is actually able to sense a pressure and to send a vibrotactile feedback to the user, our results are encouraging and promising. However, because of several issues encountered during the development, several improvements still have to be introduced.

Indeed, while at first sight we could observe a linear relationship between forces and values returned, a more accurate analysis could have shown some unwanted fluctuations.

• Mixed piezo-resistive effect: The sensors are made of fine knit polyamide fibers coated with a piezo-resistive polymer. Like any other piezo-resistive device, the resistance of the sensors decreases with the mechanical stress. This works on the principle of the tension divider bridge. However, these fibers have a far more complex behavior. The force applied on them is distributed considering their geometry, their type of knit, the tightening... The fibers being conductive and deformable, the squeezing increases the surface contact and decreases the resistance independently from the piezo-resistive effect. This mixture of effects implicates that the response of the sensors can only be approached by calibration. Another observation is that the raw value of the sensors, once stimulated and released, drops under the baseline level and progressively rises to return to its starting point. This is probably due to the hysteresis of the fibers, behaving like an elastic body. • Manufacture problems: Each sensor is handmade so individual behavior is rather unpredictable. Moreover, the sensitivity seems to vary with the amount of glue used in the manufacturing. They are also fixed with a different amount of turns of conductive threads. This explains their various profiles of response, and the need for an individual calibration. Also, button connectors are loosely fixed to the glove and their movements and short-circuits cause variations and sudden drops of the sensed values. They tend to decrease the repeatability of the measurements. The measure of the various sensors has been done several times with no load. The result was variable, and some sensors have a more reliable response than others (Fig. 4a). The best sensor has a standard deviation of 6.8 (M=871,6, less than 1%) and the worst 56.3 (M = 553,9, over 10%). This has been repeated with a charge of 278 gf with similar results (Fig 4b). • Calibration method: The precision of the setup for calibration could be questionable. While the pressure measured is digitally precise, the application of the force is not. With the above setup, the pressure applied on the sensors is manually modified, and the observer reads and writes down the value. There is no digital synchronization between the device and the calibration system. Finally, the feedback system has been manufactured with simple and low-cost materials for rapid proof-of-concept purposes. The stimulator needed a minimal discrimination level, to make the difference between "contact" and "no contact". The threshold level has been put to 278 gf, which corresponds to the lower precision of force detection of a normal hand (reported to a 8 mm diameter section). The decision has been taken to have the better compromise between noise and useful signal, but no systematic assessment has been done. The evaluation of the most efficient vibrotactile pattern for discrimination is included in our immediate plans.

Conclusion

Home-based rehabilitation is increasingly used to improve compliance program and to reduce health-care costs. Along these, we have presented here innovative vibrotactile sensory substitution in hand sensitive deficits for hand home-based rehabilitation. Although some technical aspects (e.g., calibration of the sensors) still need to be further studied and developed, these preliminary results are very encouraging. The ultimate aim of this device is to empower the patients in their own rehabilitation, allowing them to become the major players of their healing. They could plan the training sessions at home according to their time schedule and adjust their exercises according to their pain and tireness, without the need to physically move to the hospital or to the physiotherapy office. In the future, medical doctors and physiotherapist could also propose some rehabilitation programs and check the efficacy and treatment compliance of a home-based rehabilitation program, as well as the improvements made by their patients through a connected interface (so to quickly adapt the training protocol).

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  NET framework 3.5, with Microsoft Visual Studio 2008. It offers several basic functions to exploit the capabilities of the device. The acquisition circuit provides a 64-bit signal (8 bit from each sensor) that is recovered from a specific memory address, at a 10 Hz sampling rate. A simple mean 10-values filter has been implemented. The values of the sensors can be displayed in raw state or converted to Newtons (N) or to grams-force. The values for each sensor are displayed in real time in eight textboxes, as well as their minima and maxima. They are also visualized on dynamic .NET windows forms bars. Finally, a color graph (realized using the open source zedGraph library [24]) shows the curves of evolution of these values compared to the maxima. The values can be stored to a .txt file in real time, raw or converted. Finally, to keep the useful values to control the feedback only, two operations are successively executed:(1) a threshold of 278 gf is applied to each value (each sensor exceeding the threshold being considered as "activated"), and (2) the mean value of the "activated" sensors is calculated.

Fig. 1 .

 1 Fig. 1. The glove (a) and the signal acquisition and treatment software (b)

Fig. 2 .

 2 Fig. 2. Sensor responses to increasing applied pressures.

Fig. 3 .

 3 Fig. 3. Sensor responses after constant stimulation to 278 gf.

Fig. 4 .

 4 Fig. 4. Repeatability of the measurements with no load (a) and with 278gf (b).

Acknowledgments. This work was supported in part by funding by IDS company, TIMC-IMAG Laboratory, the French national program "programme d'Investissements d'Avenir IRT Nanoelec" ANR-10-AIRT-05, and Institut Universitaire de France.