J Le Duigou

A Bernard

J C Delplace

S Gabriel

Global Approach for Technical Data Management Application to Ship Equipment Part Families

Keywords: Product Life-cycle Management, Data Model, Axiomatic Design

For several years, digital engineering has increasingly taken a more important place in the strategic issues of mechanical engineering companies. Our proposition is a global approach that enables technical data to be managed and used throughout the product life-cycle. This approach aimed to provide assistance for costing, development and the industrialization of the product, and for the capitalization, the reuse and the extension of fundamental knowledge. This approach has been experimented within a company environment that designs and produces families of ship equipment parts. This case study is presented together with the software that has been developed for this company.

INTRODUCTION

In the present industrial context, French mechanical engineering industries are faced with growing challenges. After having refocused on their primary business in order to increase their production by increasing efficiency, they are now being asked to acquire more diversified skills. Market globalisation and an increase in customer demands has forced companies to produce more complex and individualized products in a shorter lead time. To solve this paradox (refocus on the primary business and need of multiple specific skills), companies have adapted by regrouping in order to pool their mutual skills. When this is done over a short period and on a specific project, it is called 'virtual enterprise', and 'extended enterprise' when it is done over a longer period. One of the key points of the success of such an enterprise is the ability to communicate on the target product. Products that generate a large amount of information, i.e. the classical communication system phone/fax/email used by 90% of companies is not structured enough to enable efficient cooperation. For many years, software has been developed to pool all this information. From the EDM (Electronic Document Management) in the 80's to the PDM (Product Data Management) and the PLM (Product Life cycle Management) nowadays, the companies and particularly the contractors understand the benefit of such software. Within this context Cetim (an industrial technical centre that represents 7000 companies of French mechanical engineering industries) decided to launch a survey on digital and collaborative engineering for the mechanical engineering companies [1]. This survey showed that only 5% of SMEs of fewer than 100 people use a PLM system to manage their technical data. However, a second survey in the same year [START_REF] Cetim | Etude sur les besoins en PLM[END_REF] showed that more than 70% of these same SMEs consider as important the reuse of knowledge, the share of information in the company and with the outside, the security of information access and storage and the follow-up of modifications. These are the exact functionalities offered by the PLM software tools. After many visits to SMEs, the CEOs see the main obstacles to a PLM installation as being the complex nature of the installation, use, and maintenance. It is also very costly. It seems, however, that the SMEs in the mechanical engineering industry have very specific needs in terms of PLM. 70% of these companies have customers in various business fields (mainly in the automobile and aeronautic sectors). As a consequence, they have a lot of technical skills to manage at the same time because the OEMs use different CAD and PLM systems. There is a true need for PLM in SMEs in the mechanical engineering industry, but there are some obstacles that stand in the way of this development. Based on this premise, Cetim launched a project aimed to help the emergence of digital and collaborative engineering in those SMEs. This project links up with the strategy of the IVGI (Virtual engineering for industrial engineering) project in the IRCCyN laboratory that optimizes the integration of technical knowledge in the enterprise processes. These activities need the implementation of specific methods and data models for the mechanical engineering companies. First of all, we will work on the scientific studies that will enable us to establish the starting point of our approach. Then we will present our work method, a research/action approach, based on a spiral cycle structured on successive phases of analysis, development, experimentation, and then linking up with the methods and models modified by the experience feedback. We will describe our contribution and an industrial case study. In prospect, we target a generic method and data model to structure and manage the technical data, adapted to the SMEs in the mechanical engineering industry.

PLM: FROM CONCEPT TO DATA MODEL

In this chapter, we will first of all concentrate on the design of PLM, then we will examine the different methods of modelling which enable the creation of a data model on which are based the PLM functionalities. Finally we will analyse the different standards that enable the communication and sharing of technical data between companies that do not have the same data model.

The PLM concept

For many years, the software providers have been extolling the merits of PLM and the return on investment of that software. But PLM is first of all an enterprise strategy [START_REF] Terzi | Element of Product Lifecycle Management: Definitions, Open Issues and Reference Models[END_REF]. It involves managing all the data concerning a product, throughout its life-cycle, and all the internal and external actors involved in the development of this product. An acceptable definition of PLM is: "A strategic business approach that applies a consistent set of business solutions in support of the collaborative creation, management, dissemination and use of product definition information across the extended enterprise from concept to end of life -integrating people, processes, business system, and information" [START_REF]Product Lifecycle Management "Empowering the future of business[END_REF]. This concept enables, for example, planning departments to access information directly from a design department, and to propose modifications, thus shortening the product development cycle and avoiding retro design which is both long and costly. At a more strategic level, PLM enables CEOs to follow critical information on a product line or the exact time to market of new products. Much work has been done in this field, especially in the aeronautic and automobile sectors in order to propose technical data management methods [START_REF] Bacha | De la gestion des données techniques pour l'ingénierie de production[END_REF][START_REF] Nguyen | System engineering for collaborative data management systems: Application to design/simulation loops[END_REF], but also in smaller companies, such as sand foundries [START_REF] Delplace | L'Ingénierie numérique pour l'amélioration des processus décisionnels et opérationnels en fonderie[END_REF].

The modelling of business objects

PLM relies on a data model being composed of business objects that intervene in the business processes. Several modelling methods and languages have been developed so as to model these objects. The modelling languages enable these objects and related activities to be represented (SADT, IDEF3, BPMN [START_REF] White | Introduction to BPMN[END_REF], FBS-PPRE [START_REF] Labrousse | Process/Product/Resource integration, in Tools and Methods of Competitive Engineering[END_REF]]…). The establishments of patterns, based on this modelling language, describe an approach to represent the processes (CIMOSA [START_REF] Kosanke | CIMOSA modelling processes[END_REF], ARIS [11], GERAM [12], GRAI [START_REF] Doumeingts | Decisional Modelling using the GRAI Grid[END_REF], PERA [START_REF] Williams | The Purdue Enterprise Reference Architecture[END_REF]…). These methods contribute to the adjustment of methods and data models required for PLM implementation. Nevertheless, in an extended enterprise context, it is necessary for these different models to be able to communicate together. Therefore standardized models are required to enable sharing or communication between companies that have not made the same choice of modelling.

The standards of data models

Much work has been done in different sectors to increase the interoperability of data models with the standards, using mainly the STEP norm (STandards for the Exchange of Product model data) [START_REF] Chambolle | Un modèle produit piloté par les processus d'élaboration : Application au secteur automobile dans l'environnement STEP[END_REF][START_REF] El Khalkhali | An information infrastructure to share product models using STEP standard, 9 th IPSE international conference on concurrent engineering: research and applications[END_REF]. STEP is an international exchange standard of ISO (ISO 10303), that describes how to represent and exchange product models by covering the whole life-cycle [START_REF]Industrial Automation Systems and Integration -Product Data Representation and Exchange -Part 1: Overview and Fundamental Principles[END_REF]. STEP uses a formal representation language of data called EXPRESS (ISO 10303-11), and its graphical representation, EXPRESS-G [START_REF]Industrial Automation Systems and Integration -Product Data Representation and Exchange -Part 11: Description Methods: The EXPRESS Language Reference Manual[END_REF]. The Application Protocols (AP) are information models of STEP specific for an industry and/or a life-cycle phase. What is of interest to us is the AP214 [START_REF]Industrial Automation Systems and Integration -Product Data Representation and Exchange -Part 214: Application Protocol: Core Data for Automotive Mechanical Design Processes[END_REF], which is specific to the automobile sector, and AP239 [START_REF]Industrial Automation Systems and Integration -Product Data Representation and Exchange -Part 239: Application Protocol: Product Life Cycle Support[END_REF] which focuses more on the aeronautic sector. Those models are not fully interoperable, despite having common integrated resources, because the objects and the attributes are different depending on the sector of application. Hence the creation of PDM Schema [START_REF]PDM Schema v1[END_REF] that tried to unify the different information models of STEP APs using their common objects. It seems that if many methods exist for modelling business objects, their use for the creation and maintenance of a data model that supports PLM is not detailed enough for industrial exploitation. We will keep the FBS-PPRE modelling method which enables the dynamic representation of objects independently of their roles (the same object can be a product, a resource or a process, depending on the context), which can be useful in an extended enterprise context. Moreover we notice that in spite of the existence of standards, it is still difficult to get a data model both adapted to the company and interoperable with the standards. So we will develop an approach that uses the maximum of the best appropriate standards for SMEs in the mechanical engineering industry. We will explain how we intend to obtain this result in the next chapter.

RESEARCH APPROACH

Our approach aims to propose a methodology in order to structure and manage the technical data of companies in the mechanical engineering industry in the context of extended enterprise. We will propose methods to structure and manage technical data and the data models needed by those methods, using the existing standards.

To define these methods and to reach a common data model for the different companies, we have implemented a three-step research approach, a research/action type, based on a spiral cycle approach, typically consistent in terms of scientific experimentation: proposal of models and methods, development of the experiment, the experiment itself and results, analysis of these results and identification of the limitations of the method and the proposed models, proposition of modifications, implementation of these modifications and definition of the next experiment scenario, and so on until the desired results are obtained.

Phase 1: audit of the companies, typology of SMEs in the mechanical engineering industry and choice of pilot companies

The first phase of our work is to interview several companies to extract the present practices in terms of digital and collaborative engineering, and the best practices to implement. Benchmarking was also done on existing software tools to list the functionalities and their ability to meet SME needs. Now we have to choose a number of pilot companies for our research. For this, we will make a typology of SMEs in the mechanical engineering industry. We took as differentiation axes the number of parts in the product (produced by the SME) and the fact that the product is standard or specific. We obtained four zones (Figure 1). Thereby we deduced that there were four types of SMEs: Type1: SMEs that produce specific products with numerous parts, for example the special machine producers. Type2: SMEs that produce standard products with numerous parts, for example the system integrators. Type3: SMEs that produce specific products with few parts, for example the mould makers. Type4: SMEs that produce standard products with few parts, for example the elementary part producers. This typology classifies the different companies present in an extended enterprise, from the toolmaker to the integrator, through all the intermediaries. Then we chose companies covering the different zones of our typology for our pilot companies.

Phase 2: Immersion in the companies and integration of specific methods

This consists in working in the different companies so as to directly integrate the technical data structuring and managing methods. This phase is coupled with the implementation of the methods with real data in the companies to verify the gap between our proposal and the objectives. From the initial situation of the company, we act by action/research to arrive at the final state that we defined during the audit phase.

Phase 3: Generalisation and proposal

In this last phase, based on the analysis of the different pilot companies, we will generalize the method of managing technical data, and create a global data model. This model will be compatible with the standards and applicable to all the types of companies in the mechanical engineering industry so that it may be used in an extended enterprise context.

A TYPE 2 COMPANY: PSL CONCEPT

This case study must enable us to put into practice methods of technical data structuring and management, adapting to this specific company. In order to do this, we will begin to analyse the needs of this company in terms of PLM. Then we will propose an approach to improve on the initial situation. And finally, we will validate this method by implementing it on a product family.

Description of the company and initial performances

The PSL Concept produces and sells equipment for ships. Among these products, there are reserve rudders, pulleys and tackles, sheaves, jam cleats and various accessories. This company organizes the main part of their products into families. In fact, as many system integrators, their products are made from standard products, to which options and modifications are added to meet customer needs. Various processes are used to produce the parts, the blocks in carbon composite are cast, then cut by milling, and finally they are manually assembled with the other parts.

Needs in terms of PLM

After the audit done in phase 1, it seems that the main needs in this company are as follows: Knowledge capitalisation An improvement of design, resulting from customer feedback, a set of tests or the optimization of the designer, are not reproduced on the other products of the family without the involvement of the designer on each product. This process is lengthy and is a source of error.

BOM management

The BOM are made manually and have to be updated when there is a major modification of the product design. Reference management Due to the diversity of existing products (1200 references only for pulleys), the product references are hard to manage efficiently. Quote Giving a precise quote of a new product is complex because it is difficult to know the quantities of raw materials that will be consumed and the manufacturing time before the detailed design of the product.

Archive management

When a client comes back with a product, it is not always easy to find the original drawings of the product that has been sold with the references of the different parts. Thus the audit phase underlines the main PLM needs of this company. Now we will propose an approach to give a global solution to these needs. It is an information system based on the principles, methods and models previously presented. Then, we will implement prototype software based on our approach and we will compare the results with the objectives of the company.

Proposed approach

First of all we aimed at organizing the technical data of a family of products. The families in PSL CONCEPT could be organized by main functions of the products. It seems that an organisation of technical data by function could be the most efficient way of being able to link the design parameters and the functions of the product. With this organisation we could globally manage the technical data depending on the functions of the family. Suh [START_REF] Suh | The Principle of Design[END_REF][START_REF] Harutunian | Decision Making and Software Tools for Product Development Based on Axiomatic Design Theory[END_REF][START_REF] Suh | Axiomatic Design of Software Systems[END_REF] proposes the axiomatic design linking the functional parameters to the design parameters. He divides the design into four domains (customer, functional, physical, process). Each domain contains specific design objects (customer needs (CNs), functional requirements (FRs), design parameters (DPs) and process variables (PVs)) (Figure 2). The functional requirements are defined as the minimum data that fully complete the customer needs. The design process moves on by breaking down the hierarchical upper level and zigzagging between functional, physical and process domains. To guide the designers' choices, axioms are defined. Two design axioms have been defined as follows: First axiom -independency axiom: maintain the independence of functional requirements. Second axiom -information axiom: minimize the information content (of the design). Design matrix representing the links between FRs and DPs enable the design to be visualized and optimized by applying axioms. We were inspired by this principle to decline it into the technical data structuring and management of a family of products. We broke down the different functions of the family, then we created a set of functional dimensioning parameters for the products in order to link those parameters to the different functions (Figure 3).

Validation of the approach

We focus on a major and well-known family of products for the company: the pulleys. We will start with a brief description of the pulleys (Figure 4). A standard pulley is composed of two flanges (1), of one or more sheaves (2), of fastening and of different accessories as for example a jam cleat. To translate the movement, the fag end (a sailboat string) moves onto the sheave's groove. The flanges have many options such as adding guides (4) to maintain the contact between fag end and sheave in special use conditions or beckets [START_REF] Bacha | De la gestion des données techniques pour l'ingénierie de production[END_REF] and different kinds of openings (3) to fix the pulley. Thus, if a function is not required by the customer, and if this function is only linked to a single sub-product, then this sub-product will not be present in the final product. The word sub-product is for a part in an assembly and for a part of a part. Moreover the modification of a functional parameter leads to the modification of the design parameters which are linked to it. On this basis we have developed several functionalities to meet the needs in terms of PLM of this company. Knowledge Capitalisation When a modification of the design is made, this modification is implemented on all the products of the family that use the function concerned by the modification. There is no longer information loss when a product is improved because if the function or the definition of the design parameter is modified, all the products of the family will be automatically modified and so have the benefit of the improvement.

Reference management

In order not to have to open a large number of references without producing the referenced product, we introduced a system of referencing based on the functions of the product family. This system enables that a new product (an unseen combination of functions) automatically obtains a reference link to the specified functions, without having to open all the possible references beforehand.

Figure 4: Description of a pulley.

Quote

A software program was implemented to automatically construct the CAD file of a pulley from the functional requirements.

After a study of the price of the product family, we noticed that the price of a product is linked to the functions of this product. So ascertaining empirically the relation between the price and each function, we were able to obtain a global price for a product from its functional definition.

To create this program we started by breaking down the functionalities of a pulley (Figure 5). Then we carried out a functional dimensioning of the different sub-parts of the pulley and we set these parameters in the CAD file. Then we brought together the dimensioning parameters in accordance with the functions of the pulley in order to obtain a link between the functions and the parameters in the CAD file. So we obtained a parametric model of the family of pulleys in a single CAD file with a link to the function requirement of each pulley.

Archive management

By registering the modification dates of functional parameters and the former values of these parameters, we are able to find the exact CAD of a past product, by using the parameters at the product sale date.

We have thus defined a global approach of structuring and management of technical data, which enables us to create a software solution to automatically design a family of products and to meet the company needs. This software implementation is presented in the next chapter. Now we will give an example for a specific function of the creation process. We will focus on the function "to keep the contact between the fag end and the sheave" (Figure 5) when the parameter "angle of traction" is greater than 90°. If the maximum angle of traction is greater than 90°, we should add guides to the flanges and a screw between the two flanges ((4) Figure 4). The fag end passes between the sheave and the screw and it is then forced to stay in contact with the sheave. On the CAD model, the feature "guide extrusion" passes automatically from a suppressed state to a resolved state. The construction parameters of the guide are then downloaded and filled in according to the function requirements (Figure 6 and Table 1). Table 1: Design parameters of the guide.

When one of guide parameters is modified, all the pulleys that have an "angle of traction" functional requirement greater than 90° will be modified. We will no longer change the value of the parameters, but will directly change their definition. Let us take an example: if the fag end is often jammed between the screw of the guide and the sheave (cause by an accumulation of impurities), then we can change the definition of the parameter "gap with the sheave" from "fag end diameter +4mm" to "fag end diameter +5mm". Then all the new pulleys with a maximum angle of traction greater than 90° will have 1mm more in the gap between the screw and the sheave, so the impurities will no longer jam the end fag.

All the parameters and their definitions are temporarily stored in a spreadsheet. They will then be stored in the PLM data base. Figure 7 represents the feature management diagram of the old version of a flange created manually and the new version of the same flange, created with the program. We notice that the diagrams differ. In the old version the features are created as the flange is constructed. In the new one the features are organized by functions. We also notice that some features of the new version are not used. These features represent functions not required by the customer and so not present in the functional requirements. The referencing of the flanges and pulleys is automated in the software. It means that if the part or the assembly is new the reference is created. If the part is old the reference is copied. In both cases the references are added to the layouts and the BOMs. When the product is an assembly we add a functionality to automate the creation of the BOM, based on the CAD BOM functionality. The drawings were created automatically in order to keep a paper record of the pulleys and its parts.

A table for the quotes was also made to calculate the price of a pulley depending on its functionalities. Each function has a price depending on the number of sheaves and the diameter of the fag end. Adding all the prices of the functions required by the customer we obtain the global quote of the pulley.

Conclusions and discussions on the case study of a type 2 company

First the software carries out a needs analysis. Then it produces the CAD model for the specific pulley, shows the quote, opens a reference if necessary and creates the layouts and the BOM. The design time for a new pulley has gone from hours to minutes. Moreover there is now a single CAD file to manage, with an associated table of parameter definitions for the 1200 pulley references. With the record of modifications of the parameter definitions and the functional requirements of each sale we can find an old version of a pulley directly from this CAD file. We propose a global approach to meet the specific PLM needs of this company. The implementation of the software based on this approach and the results that we have obtained prove that the approach is in phase with the needs of this kind of company, a type 2 SME in the mechanical engineering industry. Nevertheless we intentionally chose a family of wellknown products. We have to think of the feasibility of this approach if we choose a new range of products. Many parameter definitions were obtained with an empirical value, and it could be difficult to assume those coefficients for a new product range.

[12] GERAM, 1999, GERAM: Generalised Enterprise Reference Architecture and Methodology v1.6.3, IFIP-IFAC Task Force on Architectures for Enterprise Integration.

CONCLUSIONS AND PROSPECTS

We proposed and implemented a global approach to meet PLM needs of a type 2 company. The results obtained confirm that this solution meets the needs in terms of PLM of this type of company. But in an extended enterprise, we cannot limit our approach to one type of company. It must be possible to link integrators, detail parts producers and mould makers or machine tool producers in order to bring a modern industrial project to fruition. That is why our next industrial cases will be an elementary part producer and a machine tool producer. That will enable us to underline the specific problems of the other type of companies and of the other life-cycle steps such as the BOM management or the plan of procedure management in the industrialisation or production phases.

Figure 1 :

 1 Figure 1: Typology of SMEs in mechanical engineering industry.

Figure 2 :

 2 Figure 2: Design domains by Suh.

Figure 3 :

 3 Figure 3: Domain breakdown and links between them.

Figure 5 :

 5 Figure 5: Partial functional decomposition of a pulley.

Figure 6 :

 6 Figure 6: Sketch of the guide on the flange.

Figure 7 :

 7 Feature diagrams of the old version of a flange (a) and the new one (b).

[ 11 ]

 11 Scheer, A.W., 1998, ARIS. Handbook on Architectures of Information Systems, Springer-Verlag., p541-566.


Felipe Almeida
email: †felipe.almeida@taltech.ee

Levent Aksoy
email: levent.aksoy@taltech.ee

Quang-Linh Nguyen
email: ‡quang-linh.nguyen@lirmm.fr

Sophie Dupuis
email: sophie.dupuis@lirmm.fr

Marie-Lise Flottes
email: marie-lise.flottes@lirmm.fr

Samuel Pagliarini
email: samuel.pagliarini@taltech.ee

Resynthesis-based Attacks Against Logic Locking

Keywords: Logic locking, resynthesis, EDA tools, oracle-less and oracle-guided attacks

Logic locking has been a promising solution to many hardware security threats, such as intellectual property infringement and overproduction. Due to the increased attention that threats have received, many efficient specialized attacks against logic locking have been introduced over the years. However, the ability of an adversary to manipulate a locked netlist prior to mounting an attack has not been investigated thoroughly. This paper introduces a resynthesis-based strategy that utilizes the strength of a commercial electronic design automation (EDA) tool to reveal the vulnerabilities of a locked circuit. To do so, in a pre-attack step, a locked netlist is resynthesized using different synthesis parameters in a systematic way, leading to a large number of functionally equivalent but structurally different locked circuits. Then, under the oracle-less threat model, where it is assumed that the adversary only possesses the locked circuit, not the original circuit to query, a prominent attack is applied to these generated netlists collectively, from which a large number of key bits are deciphered. Nevertheless, this paper also describes how the proposed oracle-less attack can be integrated with an oracle-guided attack. The feasibility of the proposed approach is demonstrated for several benchmarks, including remarkable results for breaking a recently proposed provably secure logic locking method and deciphering values of a large number of key bits of the CSAW'19 circuits with very high accuracy.

I. INTRODUCTION

Due to the globalized integrated circuit (IC) supply chain, serious security threats, such as hardware Trojans, piracy, overbuilding, reverse engineering, and counterfeiting, have emerged [START_REF] Rostami | A Primer on Hardware Security: Models, Methods, and Metrics[END_REF]. Many defense techniques, such as watermarking [START_REF] Kahng | Watermarking Techniques for Intellectual Property Protection[END_REF], digital rights management [START_REF] Alkabani | Remote Activation of ICs for Piracy Prevention and Digital Right Management[END_REF], metering [START_REF] Koushanfar | Provably Secure Active IC Metering Techniques for Piracy Avoidance and Digital Rights Management[END_REF], and logic locking [START_REF] Dupuis | Logic Locking: A Survey of Proposed Methods and Evaluation Metrics[END_REF], have been introduced over the years to deal with these threats. Among those, logic locking stands out by being a well-established technique and by offering protection against a diverse array of adversaries [START_REF] Yasin | Provably-Secure Logic Locking: From Theory To Practice[END_REF]. Logic locking inserts additional logic driven by key bits so that the circuit behaves as expected only when the secret key is applied.

On the other hand, many efficient attacks have been introduced to overcome the defenses built by logic locking [START_REF] Azar | Threats on Logic Locking: A Decade Later[END_REF]. However, the impact of an electronic design automation (EDA) tool on the manipulation of the locked netlist before performing an attack has not been investigated thoroughly. In this work, we explore if EDA tools can be used to make a locked circuit vulnerable to existing logic locking attacks. Thus, the main contributions of this work are three-fold: (i) we introduce a resynthesis procedure that is a pre-attack step, where functionally equivalent but structurally different locked circuits are generated by resynthesizing the original locked circuit using different optimization parameters and delay constraints in order to create structural vulnerabilities that can be exploited by existing attacks; (ii) we present an oracle-less (OL) resynthesis-based attack, which applies the prominent SCOPE attack [START_REF] Alaql | SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking[END_REF] to these resynthesized circuits and gathers all its solutions to discover the secret key; (iii) we show that our OL attack can be combined with a traditional oracle-guided (OG) attack for further improving the number of correctly deciphered key bits. The last contribution is essential since we consider circuits from the CSAW'19 contest -these circuits compound the use of two logic locking techniques at the same time.

The main finding of this work is that the use of many resynthesized locked circuits enables us to discover values of more key bits, and even the whole key, when compared to a single attack mounted on the original locked netlist.

The remainder of this paper is organized as follows: Section II presents the background concepts and related work. The resynthesis process and the proposed attacks are described in Section III. Experimental results are given in Section IV. Finally, Section V concludes the paper.

II. BACKGROUND A. Logic Locking and Threat Models

The procedure of logic locking is applied at the gate-level in the IC design flow, as shown in Fig. 1. Note that the layout of the locked circuit is sent to the foundry without revealing the secret key. After the locked IC is produced and delivered to the design house, the values of the secret key are stored in a tamper-proof memory, before the functional IC is sent to the market.

It is assumed that the gate-level netlist of the locked circuit can be obtained directly by an untrusted foundry or by reverse-engineering a functional IC obtained from the open market. An adversary can also use the functional IC programmed with the secret key as an oracle to apply inputs and observe outputs. Thus, in logic locking, there are generally two threat models: OL and OG. In the OL threat model, only the gate-level netlist of the locked circuit is available to the adversary. The adversary has both the netlist of the locked circuit and the functional IC in the OG threat model.

B. Related Work

After the introduction of random logic locking (RLL) using XOR/XNOR gates in [START_REF] Roy | EPIC: Ending Piracy of Integrated Circuits[END_REF], earlier work focused on different types of key gates, such as AND/OR, multiplexors, and look-up tables, taking into account the hardware complexity of the locked circuit [START_REF] Dupuis | Logic Locking: A Survey of Proposed Methods and Evaluation Metrics[END_REF]. However, the OG satisfiability (SAT)-based attack [START_REF] Subramanyan | Evaluating the Security of Logic Encryption Algorithms[END_REF] overcame all the defenses existing at that time. Note that the SAT-based attack iteratively finds distinguishing input patterns (DIPs) that rule out wrong keys. To thwart the SAT-based attack and its variants, circuits are locked using a point function that sets a limit on the number of wrong keys which a DIP can eliminate, forcing these attacks to explore an exponential number of queries [START_REF] Yasin | Provably-Secure Logic Locking: From Theory To Practice[END_REF], [START_REF] Xie | Anti-SAT: Mitigating SAT Attack on Logic Locking[END_REF]- [START_REF] Nguyen | On Preventing SAT Attack with Decoy Key-Inputs[END_REF].

The SAT-resilient methods can be categorized into two groups: single-flip locking technique (SFLT) and double-flip locking technique (DFLT), as shown in Fig. 2. An SFLT has only one critical point, which is responsible to corrupt a protected output under a specific input pattern. Under this category, SARLock [START_REF] Yasin | SARLock: SAT Attack Resistant Logic Locking[END_REF] adds a comparator and a masking circuit connected with the original netlist in a way that it generates a corruption on one input pattern. Anti-SAT [START_REF] Xie | Anti-SAT: Mitigating SAT Attack on Logic Locking[END_REF] utilizes two complementary AND gate trees, whose output is merged with the original circuit. CASLock [START_REF] Shakya | CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme[END_REF] is based on the same concept of Anti-SAT, however it uses both AND and OR gates. SKG-Lock [START_REF] Nguyen | On Preventing SAT Attack with Decoy Key-Inputs[END_REF] uses decoy key bits and provides a tunable output corruption. Note that SFLTs are susceptible to removal attacks [START_REF] Xu | Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks[END_REF]- [START_REF] Sengupta | Breaking CAS-Lock and Its Variants by Exploiting Structural Traces[END_REF]. If an attacker can identify this single critical point, he/she can split the design into a recovered netlist (original) and the locking unit.

A DFLT has two critical points, one that connects the original netlist with a perturbation unit and another one that connects the output of the stripped circuit with the restore unit. Under this category, stripped functionality logic locking (SFLL) [START_REF] Yasin | Provably-Secure Logic Locking: From Theory To Practice[END_REF], [START_REF] Sengupta | Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective[END_REF] initially corrupts an output based on an input combination in the perturbation unit and then, corrects this output only when the secret key is applied in the restore unit. Note that a removal attack becomes inefficient for a DFLT since the original circuit is mixed with the perturbation unit, even though it can easily identify the restore unit. However, there exist efficient structural attacks developed for DFLTs [START_REF] Sirone | Functional Analysis Attacks on Logic Locking[END_REF]- [START_REF] Limaye | Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques[END_REF].

Alternative locking techniques have also been introduced. In [START_REF] Liu | Strong Anti-SAT: Secure and Effective Logic Locking[END_REF], a technique, which has more than two critical points, called the multi-flip locking technique (MFLT), was proposed. However, it leads to a significant increase in area, power dissipation, and delay when compared to other techniques. Compound logic locking techniques were proposed to overcome the main drawback of a SAT-resilient technique, i.e., its low output corruptibility as can be observed in Fig. 2, by locking a design using both low and high output corruptibility techniques, such as SFLL and RLL, respectively [START_REF] Tan | Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking[END_REF]. Recently, efficient attacks have also been introduced against compound logic locking [START_REF] John | SAT Based Partial Attack on Compound Logic Locking[END_REF], [START_REF] Limaye | Fa-SAT: Fault-aided SATbased Attack on Compound Logic Locking Techniques[END_REF].

Moreover, the OL attacks explore patterns in the structure of a locked netlist using statistical analysis [START_REF] Alaql | SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking[END_REF], [START_REF] Li | Piercing Logic Locking Keys through Redundancy Identification[END_REF], [START_REF] Zhang | TGA: An Oracle-Less and Topology-Guided Attack on Logic Locking[END_REF]. For example, the SCOPE attack [START_REF] Alaql | SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking[END_REF] is an unsupervised constant propagation technique, which analyzes each key bit of the locked design for critical features that can reveal its correct value after it is assigned to logic 0 and 1 value. These critical features include area, power dissipation, delay, and many other circuit characteristics obtained by a synthesis tool. These features are analyzed using linear regression and machine learning based clustering.

III. PROPOSED RESYNTHESIS-BASED ATTACK

This section describes our resynthesis-based attack in detail. We assume a scenario, where the design house is the only trusted entity. An attacker has all possible reverse engineering, synthesis, and computing tools and has an access to the gatelevel locked netlist and the functional IC. In this section, we initially introduce the pre-attack stage, where the locked circuit is resynthesized using different synthesis parameters, leading to a large number of structurally different netlists with the same functionality. Then, we present the OL attack that utilizes these resynthesized netlists in order to find the secret key. Finally, in order to handle the compound logic locking efficiently, we present its modified version, where our proposed OL attack cooperates with an OG attack.

A. The Pre-attack Step: Resynthesis of the Locked Netlist

The locked circuit is synthesized multiple times using a different script each time, where the synthesis parameters are explored in a systematic way. We use the following parameters to increase the number of resynthesized locked circuits:

Synthesis Effort: In a synthesis tool, logic optimizations can be applied with different efforts at different synthesis stages. This flexibility enables a designer to explore the trade-off between the quality of results and run time. The following efforts are considered at the given synthesis stage: low, medium, and high at generic transformations (syn_gen); low, medium, and high at mapping (syn_map); and low, medium, high, and extreme at optimization (syn_opt).

Delay Constraint: To meet performance targets, delay constraints are used to guide the synthesis tool. We initially resynthesize the locked circuit without a delay constraint and find the delay of its critical path, i.e., dcp. Then, in an interval between 0 and dcp, d -1 points, which are computed as (dcp/d)i with 1 ≤ i ≤ d -1, are set as delay constraints. Note that d is set to 5 in order to generate a large number of resynthesized circuits. Even though some delay constraints are impossible to meet, the synthesis tool always generates a netlist equivalent to the original one in terms of functionality.

Maximum Transition: The transition time of a net in a circuit is defined as the longest time required for its driving pin to change its logic value. The maximum transition value was chosen to be 5%, 10%, and 15% of the delay constraint for all the nets in the locked circuit to explore different resynthesized circuits.

Key Constraints: To direct the synthesis tool to work intensively on the paths that include the keyed logic, a delay constraint, which is impossible to be satisfied, can also be used. In this case, we force the delay between all key bits and all primary outputs to be 1 ps.

Thus, the combination of parameters given above generates 3 × 3 × 4 × 5 × 3 × 2 = 1080 netlists. We eliminate the resynthesized circuits with identical characteristics and keep only the unique ones. Additionally, we prevent the use of XOR/XNOR gates, which can be problematic for the SCOPE attack, during technology mapping. Note that our resynthesis methodology aims to generate different versions of the locked circuit, making it more vulnerable to existing attacks. Thus, any existing attack, either OL or OG, may potentially benefit from this pre-attack strategy to discover the secret key. The resynthesis process is automated for a commercial synthesis tool in a Perl script. This script, which can be modified for other synthesis tools, is available at https://github.com/Centrefor-Hardware-Security/.

B. Attacks on the Resynthesized Netlists

Time-efficient attacks are chosen in order to handle a large number of resynthesized circuits. In our OL resynthesis-based attack, SCOPE [START_REF] Alaql | SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking[END_REF] is used to predict the values of key bits. In its modified version developed for compound logic locking, a query attack is used to find the values of key bits in a deterministic way.

1) Proposed OL Attack: SCOPE is applied to each resynthesized locked circuit and a solution is found. Note that this solution may return a logic 0, 1, or an unknown value for a key bit. Then, the values of key bits deciphered for each netlist are merged into a single solution that represents the overall guess. To do so, for each key bit, k i with 1 ≤ i ≤ p, where p denotes the number of key bits, we initially count the number of solutions, where k i is deciphered as logic 0 and 1, denoted as dk 0 i and dk 1 i , respectively. Then, if dk 0 i > dk 1 i or dk 1 i > dk 0 i , the value of k i is determined to be 0 or 1, respectively. Otherwise, in the case of a tie, the value of k i is decided to be unknown.

2) Proposed OG Attack: In order to handle a large number of resynthesized netlists efficiently, we introduce a SAT-based query attack, which can determine the actual values of individual key bits. Note that traditional SAT-based attacks rather attempt to find the whole secret key, which increases the computational effort significantly. In this attack, we initially find queries, i.e., values of inputs of the oracle circuit, using two techniques. The first technique uses the ATPG tool Atalanta [START_REF] Lee | On the Generation of Test Patterns for Combinational Circuits[END_REF] to find test patterns for the stuck-at-fault of each key bit on the locked circuit and stores the values of the related primary inputs as queries. The aim is to find input patterns that can propagate each key bit to a primary output, making it observable. The second technique finds queries randomly. The aim is to find input patterns that may make multiple key bits observable at primary outputs. In our experiments, we generate a total of 2p queries, where p denotes the number of key bits.

Then, we describe the locked circuit in a conjunctive normal form (CNF) formula C by expressing each gate in its CNF. Each query is applied to the oracle and the values of primary outputs are obtained. Then, the related input and output values are assigned to the associated nets in the locked circuit, the constant values of these nets are propagated, and the Boolean equations including key bits are derived in a CNF formula E. The SAT problem including the locked circuit in CNF, i.e., C, is augmented with these equations, i.e., C = C ∧ E. After all the queries are considered, the SAT problem C is solved using a SAT solver and the values of key bits are determined. Note that the locked circuit with the found values of key bits behaves exactly the same as the oracle under the given queries, but not under all possible input values. Hence, these key values are not guaranteed to be the values of the secret key.

However, the value found for a key bit can be proved if it is indeed equal to the actual value of the related bit in the secret key using the concept of proof by contradiction. To do so, for each key bit, the complement of its found value is added into C and the SAT solver is run. If there exists no solution to C, i.e., the SAT problem is unsatisfiable, the value of the related key bit is proven to be the one in the found solution.

As a simple example, consider the majority circuit in Fig. 3(a) and suppose that it is locked using XOR/XNOR gates as given in Fig. 3(b). Assume that a query is found as abc = 000 and thus, the value of its output f is obtained as 0 using the oracle. After propagating these values on the locked circuit as shown in Fig. 3(c), a Boolean equation k 0 ∨ k 1 = 0, i.e., k 0 ∧ k 1 in CNF, is obtained. In the SAT solution, the key bit values are found as k 0 k 1 = 01. Note that these are the proven key values since a SAT solver guarantees that there exists no solution to the SAT problem C, which is extended by either k 0 = 1, i.e., k 0 in CNF, or k 1 = 0, i.e., k 1 in CNF, due to a conflict with the found Boolean equation, i.e.,

k 0 ∧ k 1 in CNF.
The query attack is run on all the resynthesized circuits and the proven values of key bits in each netlist are combined into a single solution. It is developed in Perl and is equipped with the incremental SAT solver CaDiCaL [START_REF] Biere | CaDiCaL, Kissat, Paracooba, Plingeling and Treengeling entering the SAT Competition 2020[END_REF]. It is also available at https://github.com/Centre-for-Hardware-Security/.

Finally, the solution of the OG resynthesis-based attack is determined after merging the solution of the SCOPE attack over all resynthesized circuits into that of the query attack on all resynthesized circuits without changing the proven values of key bits.

IV. EXPERIMENTAL RESULTS

This section initially presents the results of the proposed OL resynthesis-based attack on the ISCAS'85 circuits [START_REF] Brglez | A Neutral Netlist of 10 Combinational Benchmark Circuits and a Targeted Translator in FORTRAN[END_REF] and then, those of the OG resynthesis-based attack on the CSAW'19 circuits [START_REF] Tan | Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking[END_REF] including compound logic locking.

A. Results on the ISCAS'85 Circuits

As the first experiment set, five ISCAS'85 circuits were considered. Table I presents their details. For our experiments, these circuits were locked by the Anti-SAT [START_REF] Xie | Anti-SAT: Mitigating SAT Attack on Logic Locking[END_REF], CASlock [START_REF] Shakya | CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme[END_REF], SFLL [START_REF] Yasin | Provably-Secure Logic Locking: From Theory To Practice[END_REF], and SKG-Lock [START_REF] Nguyen | On Preventing SAT Attack with Decoy Key-Inputs[END_REF] techniques. Note that while Anti-SAT and SFLL were taken from the NEOS tool [START_REF] Shamsi | Netlist Encryption and Obfuscation Suite[END_REF], we implemented CASLock and SKG-Lock. Table I also presents details of the locked circuits. Note that the number of keys, i.e., p, was determined based on the number of inputs and overhead of the locking technique, and circuit characteristics, i.e., the number of inputs, outputs, and gates, were taken from the gate-level netlist.

Observe from Table I that all logic locking techniques lead to circuits with a number of gates close to each other, whereas the one locked by SFLL has a slightly large number of gates. Besides, the overhead on the number of gates in circuits locked by SFLL varies from 4.7% to 19.1% when compared to original circuits.

In the following subsections, we present the results of the resynthesis process and OL resynthesis-based attack, analyze the impact of synthesis parameters on the performance of the resynthesis process and SCOPE attack, and introduce improvements to the run-time of the resynthesis process.

1) Resynthesis of the Locked ISCAS'85 Circuits: The resynthesis is performed by Cadence Genus with a commercial 65 nm standard cell library. Table II presents the resynthesis results of locked circuits. In this table, unique denotes the number of unique locked netlists out of 1080 generated netlists and area, delay, and power stand respectively for the average values of the total area in µm 2 , delay in the critical path in ps, and total power dissipation in µW on the unique locked netlists. Finally, time is the total run-time of the resynthesis process. The resynthesized netlists were generated on a computing server with Intel Xeon processing units at 3.9 GHz and a total of 1 TB memory.

Observe from Table II that the number of unique netlists is less than half of the total number of generated netlists, i.e., 540, except the c3540 circuit locked by SKG-Lock. Note that Anti-SAT, CASLock, and SFLL lead to fewer unique netlists when compared to SKG-Lock, which is mainly because the logic added by these techniques is more compact than that added by SKG-Lock, which uses a chain of AND gates. We note that the synthesis tool consumes a large amount of time to fulfill a delay constraint that is impossible to meet, such as strict delay constraints and key constraints described in Section III-A. Hence, the run-time of the resynthesis process depends on the locked circuit and the logic locking technique, and more importantly, if there exists enough room for the synthesis tool to satisfy the constraints.

In order to illustrate the diversity of resynthesized netlists, the c2670 circuit locked by SFLL is considered. Fig. 4 presents the area, delay, and power dissipation of each unique netlist, normalized by their average values given in Table II. Observe that resynthesis generates circuits significantly different from each other in terms of hardware complexity. The standard deviation on area, delay, and power dissipation values of all these netlists are computed as 1578, 235, and 4964, respectively. Note also that in this figure, the netlists after instance number 232 have a distinct profile, since they are generated using key constraints described in Section III-A.

In order to illustrate the differences in the structure of generated netlists, the c2670 circuit locked by SKG-Lock is considered. Fig. 5 presents the graphs of two netlists resynthesized using the same synthesis parameters, except for the delay constraint. In this figure, red, green, and blue circles denote the inputs, key bits, and outputs, respectively; the gray triangles represent the gates. Observe that a small change in the delay constraint can lead to a structurally different netlist, where the difference between the number of gates and logic levels is 599 and 12, respectively.

2) Attacks on the Locked ISCAS'85 Circuits: Table III presents the results of the SCOPE attack on the original locked netlists and those of OL resynthesis-based attack on the unique locked netlists generated in the resynthesis process. In this table, cdk and dk stand respectively for the number of correctly deciphered key bits and the total number of deciphered key bits and time is the total time required for the attack. The attacks were also run on the same server used to resynthesize the locked netlists.

Observe from Table III that the SCOPE attack is not entirely successful on any of the original locked netlists. However, the use of resynthesized netlists enables us to decipher the values of a large number of key bits, and even the whole key, e.g., for the c2670 and c3540 circuits locked by SKG-Lock. Note that the SCOPE attack can decipher almost all of the key bits using the resynthesized netlists locked by SKG-Lock. While the results on the netlists locked by SKG-Lock are all correct, the ones on the netlists locked by Anti-SAT, CASLock, and SFLL are slightly better than a random guess. The run-time of the SCOPE attack and our resynthesis-based attack depends mainly on the number of gates and keys in the locked design.

To find the SAT resiliency of resynthesized locked circuits, the SAT-based attack of [START_REF] Subramanyan | Evaluating the Security of Logic Encryption Algorithms[END_REF] was run on 541 netlists of the c3540 circuit locked by SKG-Lock with a time limit of 2 days. This circuit was chosen since it has the smallest number of key bits. Note that the SAT-based attack was not able to find the secret key of any resynthesized locked netlists. This experiment indicates that the resynthesis changes only the structure of the circuit as shown in Fig. 5, but maintains its SAT resiliency.

3) Redundant Synthesis Runs: Observe from Tables II and III that the total run-time of the proposed attack is dominated by the resynthesis process. However, it is possible to reduce the time required to resynthesize the locked netlist by removing redundant synthesis runs without sacrificing any unique netlists. For example, it is observed that the high value of the syn_gen parameter given in Section III-A can be removed from the parameter list, since all possible synthesis scripts including this parameter generate the same circuit when this parameter is low or medium. Thus, the number of generated circuits, i.e., 1080, reduces to 720.

4) Convergence on the Number of Deciphered Keys:

It is also observed that the number of key bits deciphered by the SCOPE attack on all unique resynthesized netlists can actually be obtained using a small number of netlists. Fig. 6 presents the number of deciphered key bits along the unique resynthesized netlists of the c2670 circuit locked by SKG-Lock. Observe from this figure that although a large number of unique netlists increases the quality of the SCOPE attack, actually a small number of unique netlists, 147 in this case, is sufficient to achieve the same result as when all 521 unique netlists are considered. We note that a similar situation was also observed on circuits locked by other techniques.

5) Promising Resynthesized Netlists: Moreover, it is observed that the SCOPE attack is more successful on specific resynthesized netlists. To find a set of synthesis parameters that enables the SCOPE attack to decipher more key values, we initially define two categories of netlists based on the slack time of the design, i.e., the difference between the required and arrived time in the critical path, as follows: i) netlists with a slack value less than or equal to 0; ii) netlists with a slack value greater than 0. The slack value of a design gives indeed a rough idea of the effort put in by the synthesis tool; for the netlists in the first category, the synthesis tool works extremely hard to meet the delay constraint, trying many logic transformations and optimization techniques. Then, the solutions of the SCOPE attack on all possible 1080 netlists are obtained and sorted based on the number of deciphered key bits in descending order. The top 10% of these sorted netlists are categorized based on their slack values. Fig. 7 presents the results of this experiment on the circuits locked by SKG-Lock. Observe that the netlists that enable the SCOPE attack to decipher more key values generally have a slack value less than or equal to 0. Thus, to generate such circuits, one can easily add strict delay constraints or key constraints as described in Section III-A. We note that a similar result was also observed on resynthesized netlists locked by other techniques.

6) Structural Analysis: In order to improve the performance of the resynthesis process, the logic cone, which is the locking technique is applied on, can be extracted and resynthesized. Note that the output of this logic cone is a single primary output, while its inputs are primary inputs, but not necessarily all the primary inputs of the locked design. Thus, the runtime of the resynthesis process can be decreased, since the logic cone has a small number of inputs, outputs, and gates when compared to the whole locked circuit. Table IV presents details on the resynthesis process on entire locked circuits and logic cones when the circuits locked by SFLL are used. Observe that the resynthesis process on a logic cone generates less number of unique designs and takes significantly less time without a significant loss on the solution quality when compared to the resynthesis process on the entire circuit. We note that similar results were also observed on circuits locked by other techniques.

B. Results on the CSAW'19 Circuits

As the second experiment set, we used the state-of-theart locked circuits from the CSAW'19 contest [START_REF] Tan | Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking[END_REF]. Details of these circuits are given in Table V. Note that two logic locking techniques -RLL [START_REF] Roy | EPIC: Ending Piracy of Integrated Circuits[END_REF] and SFLL-rem [START_REF] Sengupta | Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective[END_REF] -are applied together to lock a circuit.

In the following two subsections, we present the results of the resynthesis process and the resynthesis-based attack.

1) Resynthesis of the Locked CSAW'19 Circuits: Table VI presents the resynthesis results of locked circuits. Observe that the number of unique resynthesized netlists is larger than half of the total number of generated netlists, i.e., 540. As the hardware complexity of designs increases, the run-time of the resynthesis process increases. We note that diverse netlists in terms of complexity are obtained, e.g., the standard deviation on area, delay, and power dissipation values of all the locked netlists of the small circuit are computed as 8526, 1029, and 20074, respectively.

2) Attacks on the Locked CSAW'19 Circuits: Table VII presents results of the attacks obtained, after they are applied to the original locked netlist, denoted as OLN, and all unique resynthesized netlists, denoted as URNs. In this table, prv stands for the number of proven values of key bits. Note that since the secret key is not publicly available, the cdk values are omitted for the SCOPE and resynthesis-based attacks. Observe from Table VII that the original SCOPE attack could only decipher a small number of key bits, all of which belong to RLL, and the query attack can prove the values of a large number of key bits, all of which again belong to RLL, on the original locked circuits. Thus, the resynthesis-based attack could only decipher the RLL key bits on the original locked circuits. However, the use of resynthesized circuits makes the SCOPE attack decipher more key bits that also belong to SFLL-rem and makes the query attack prove the values of more key bits that belong to RLL. Thus, the resynthesis-based attack could decipher almost all the values of the secret key, proving almost all the values of the key bits of RLL. Note that all the unknown key bits belong to SFLL-rem. Observe that the run-time of attacks increases, as the number of gates and key bits increases.

After the values of key bits of the CSAW'19 circuits were determined, they were sent to the contest organizers for evaluation. Table VIII presents the results of the resynthesis-based attack along with those of other techniques which participated in the contest.

Observe from Table VIII that our proposed attack can determine all the key bits of RLL correctly, even though there are unproven key bits in the medium and bonus circuits as shown in Table VII. This observation implies that the guesses of the SCOPE attack on those key bits are actually correct. Moreover, the proposed technique can decipher the key bits of SFLL-rem with a number of deciphered key bits greater than any other OL technique with high accuracy.

V. CONCLUSIONS

This work has shown that EDA tools can be used to generate variants of locked circuits that may be vulnerable to existing logic locking attacks and such circuits can be generated using a specific set of synthesis parameters. It was shown that the run-time of the proposed technique can be improved using a small number of resynthesized netlists without diminishing its solution quality. Experimental results clearly indicated that the use of many resynthesized circuits enables existing attacks to decipher values of a large number of key bits with high

Fig. 1 .Fig. 2 .

 12 Fig.1. Conventional logic locking in the IC design flow (adapted from[START_REF] Yasin | Provably-Secure Logic Locking: From Theory To Practice[END_REF]).

Fig. 3 .

 3 Fig. 3. (a) Majority circuit; (b) Locked majority circuit; (c) Constant propagation on the locked majority circuit.

Fig. 4 .

 4 Normalized complexity of resynthesized netlists of the c2670 circuit locked by SFLL: (a) area; (b) delay; (c) power.

Fig. 5 .

 5 Graphs of resynthesized netlists generated using a difference in the delay constraint dc: (a) dc is 990 ps; (b) dc is 496 ps.

Fig. 6 .

 6 Fig.6. Convergence on the number of deciphered keys over the number of resynthesized netlists in the SCOPE attack.

Fig. 7 .

 7 Fig. 7. Classification of resynthesized netlists based on their slack values on promising solutions of SCOPE attack.

TABLE I DETAILS

 I OF THE ISCAS'85 CIRCUITS.

	Circuit	Original Netlist #in #out #gates	p	Locked Netlist Anti-SAT CASLock SFLL SKG-Lock #gates #gates #gates #gates
	c2670	157 64 1193	64	1321	1320	1421	1401
	c3540	50 22 1669	32	1733	1732	1783	1773
	c5315	178 123 2307	64	2435	2434	2523	2514
	c6288	32 32 2416	32	2480	2479	2531	2516
	c7552	206 105 3512	64	3640	3639	3729	3713

TABLE III RESULTS

 III OF OL ATTACKS ON THE LOCKED ISCAS'85 CIRCUITS.

				Anti-SAT			CASLock			SFLL	SKG-Lock
		Circuit	SCOPE	Resynthesis	SCOPE	Resynthesis	SCOPE	Resynthesis	SCOPE	Resynthesis
			cdk/dk time cdk/dk time	cdk/dk time cdk/dk time	cdk/dk time cdk/dk time	cdk/dk time cdk/dk time
		c2670	0/0	4s	37/64 34m18s	0/0	4s	35/64 33m47s	0/0	4s	34/64 37m32s 32/32 4s	64/64 44m37s
		c3540	0/0	3s	17/32 21m27s	0/0	3s	17/32 18m12s	0/0	2s	19/32 21m29s 17/17 2s	32/32 24m30s
		c5315	0/0	5s	38/64 42m34s	0/0	5s	30/64 43m54s	0/0	5s	33/64 46m23s 32/32 5s	62/62 52m06s
		c6288	0/0	3s	18/32 29m08s	0/0	3s	16/32 27m18s	0/0	3s	16/31 33m19s 16/16 3s	31/31 34m24s
		c7552	0/0	6s	38/64 45m31s	0/0	6s	47/64 49m13s	0/0	6s	38/63 52m26s 32/32 6s	61/61 56m45s
		65
		60
	Number of deciphered keys	40 45 50 55
		35
		30
		0	100		200	300	400		500
					Number of netlists

TABLE IV RESULTS

 IV OF THE RESYNTHESIS PROCESS AND OL RESYNTHESIS-BASED ATTACK ON ENTIRE CIRCUIT AND LOGIC CONE.

	Circuit	unique	Entire Circuit time	cdk/dk	unique	Logic Cone time	cdk/dk
	c2670	468	13h13m23s 34/64	319 7h46m26s 34/64
	c3540	484	1d47m51s	19/32	320 6h29m35s 16/32
	c5315	477	21h57m14s 33/64	313	7h6m16s 32/64
	c6288	523 2d22h15m7s 16/31	302 6h20m57s 19/32
	c7552	504	22h40m29s 38/63	279 6h57m14s 38/63

TABLE V DETAILS

 V OF THE LOCKED CSAW'19 CIRCUITS.

	Circuit	#in	Details #out	#gates	Number of key bits RLL SFLL-rem Total
	small	522	512	15995	40	40	80
	medium	767	757	24008	60	60	120
	large	1452 1445	36584	80	80	160
	bonus	892	1746	23004	128	128	256

TABLE VII RESULTS

 VII OF ATTACKS ON THE LOCKED CSAW'19 CIRCUITS.

	Circuit-Netlist	dk	SCOPE time	prv	Query time	Resynthesis dk time
	small -OLN	19	20s	39	1m21s	40	1m41s
	small -URNs	77 4h10m42s 40 1d10h4m37s 79 1d14h15m19s
	medium -OLN	32	41s	58	6m37s	59	7m18s
	medium -URNs 117 8h33m56s 58 3d19h12m13s 120 4d3h46m9s
	large -OLN	30	1m7s	79	6m19s	79	7m26s
	large -URNs	152 12h56m15s 80 3d2h52m11s 159 3d15h48m26s
	bonus -OLN	64 1m46s	118	3m2s	120	4m48s
	bonus -URNs	233 16h7m17s 125 1d20h29m22s 252 2d12h36m39s

ACKNOWLEDGMENT

The authors thank Nimisha Limaye for evaluating the keys found by the proposed technique on the CSAW'19 benchmarks.

This work has been partially conducted in the project "ICT programme" which was supported by the European Union through the European Social Fund. It was also partially supported by European Union's Horizon 2020 research and innovation programme under grant agreement No 952252 (SAFEST).

Approach