Sehmi Saad
email: sehmi.saad@gmail.com

Fayrouz Haddad
email: fayrouz.haddad@im2np.fr

Aymen Ben Hammadi
email: benhammadiaymen@gmail.com

Impact of multi-finger MOSFET geometry on the electrical performance of RF circuits

Keywords: Multi-finger, MOSFET, RFIC, noise, power consumption, area

The increasing demand of low-cost, low-power and high-efficiency integrated systems is making more complex to design radiofrequency (RF) analog circuits. Using multi-finger MOSFETs is an attractive technique to optimize the circuit performances. It reduces the silicon area, the gate resistance and parasitic capacitances compared to the single finger MOSFET, which mainly impact the high frequency and noise performances. However, selecting the optimal number of fingers remains a challenging issue. This paper investigates the number of fingers (nf) influence on the transistor parameters and assesses its effect on several key functions in RF transceivers. The study focuses specially on the obtained performances of civil RF circuits, implemented in 130 nm CMOS technology, as a function of nf. First, design of a differential RF bandpass filter is presented. The results show that using multi-finger MOSFETs leads to reductions in chip area by 66.5%, in power consumption by 15% and in noise figure by 43% with an improvement in linearity and frequency range compared to the conventional approach. Then, an inductorless LC-VCO and an LNA operating around 2.4 GHz have been designed using three different configurations depending on nf. Obtained results display an improvement in the area, power gain, frequency and noise performances by applying the multi-finger optimization, and show that keep increasing nf can degrade the stability, linearity and power consumption. The proposed circuits are also tested through Monte Carlo simulations confirming their robustness to process and mismatch variations. Detailed analytical comparison between the different proposed circuits and configurations of nf proves that the MF technique is reliable when nf is inferior to 5.

INTRODUCTION

In the last decades, CMOS integrated circuit (IC) design has known several technological advances conducted with a constant technology downscaling [START_REF]International Technology Roadmap for Semiconductors (ITRS)[END_REF]. Size of transistors have been shrinking exponentially and subsequently the continuous miniaturization of devices enters the nanoscale regime. Notably, the challenges associated with using conventional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have increased. Because of performance limitation and parameter variation due to gate leakage (GL) and shortchannel effects (SCEs), new materials, structures and manufacturing techniques against electrical performance effects as well as reliability characterization have been vastly investigated in literature [START_REF] Gimenez | Layout techniques for MOSFETs[END_REF][START_REF] Mahmoud | A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model[END_REF][START_REF] Conde | A review of recent MOSFET threshold voltage extraction methods[END_REF][START_REF] Waltl | Reliability of Miniaturized Transistors from the Perspective of Single-Defects[END_REF].

Modifications of subtract profiles and usage of different insulator materials, i.e. Silicon-On-Insulator (SOI) [START_REF] Kononchu | Silicon-On-Insulator (SOI) technology: Manufacture and applications[END_REF], Silicon Carbide (SiC) [START_REF] Franco | Class-E Silicon Carbide VHF Power Amplifier[END_REF], Silicon-On-Sapphire (SOS) [START_REF] Lam | The silicon-on-sapphire technology for RF integrated circuits: potential and limitations[END_REF], Carbon Nanotube [START_REF] Prakash | A review on carbon nanotube field effect transistors (CNTFETs) for ultralow power applications[END_REF][START_REF] Zhong | Carbon nanotube film-based radio frequency transistors with maximum oscillation frequency above 100 GHz[END_REF], Germanium [START_REF] Tewari | Investigation on high-performance CMOS with p-Ge and n-InGaAs MOSFETs for logic applications[END_REF], Silicon-Germanium [START_REF] Joseph | Status and direction of communication technologies-SiGe BiCMOS and RFCMOS[END_REF] High-k material [START_REF] Kumar | Reliability of high-k gate stack on transparent gate recessed channel (TGRC) MOSFET[END_REF], are examples of well-known optimization transistor techniques. However, besides its high fabrication cost, this technique leads to high-grade electrical performance, in the production of multi-function MMICs for space and aerospace applications, where low voltage and high frequencies are required.

On the other hand, new possible fabrication structures of transistor's gate such as FinFET [START_REF] Chauhan | FinFET Modeling for IC Simulation and Design[END_REF][START_REF] Mahmoud | A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model[END_REF], Double Gate (DGFET) [START_REF] Pakaree | Realization with fabrication of double-gate MOSFET based differential amplifier[END_REF], Multi Gate (MuGFET) [START_REF] Srivastava | Design and performance analysis of cylindrical surrounding doublegate MOSFET for RF switch[END_REF], Ion Sensitive Field Effect (ISFET) [START_REF] Vu | Field-effect transistor biosensors for biomedical applications: recent advances and future prospects[END_REF], Gate-All Around (GAA) [START_REF] Djeffal | Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions[END_REF], Ultra-Thin Body (UTB) [START_REF] Fossum | Fundamentals of Ultra-thin-body MOSFETs and FinFETs[END_REF], Ultra-Thin Body and Buried oxide (UTBB) [START_REF] Raskin | FinFET and UTBB for RF SOI communication systems[END_REF], Multi-Bridge Channel FET (MBCFET) [START_REF] Bae | 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications[END_REF], Junction less MOSFET [START_REF] Lee | Performance estimation of junctionless multigate transistors[END_REF], Tunnel Field-Effect Transistor (TFET) [START_REF] Debnath | DC and analog/RF performance analysis of gate extended U-shaped channel tunnel field effect transistor[END_REF][START_REF] Saravanan | A Review of III-V Tunnel Field Effect Transistors for Future Ultra Low Power Digital/Analog Applications[END_REF], Organic Thin-Film transistors [START_REF] Kaushik | Organic Thin-Film Transistor Applications: Materials to Circuits[END_REF], Nanowires transistors [START_REF] Vizcaino | Fast, effective manipulation of nanowires for electronic devices[END_REF] are eminently pertinent to the development and realization of the new RF transistor generation for communication device. The general goal of each technique is to enhance gate control of the channel charge and to reduce leakage current. For the instance, majority of these techniques have been shown to be effective as a promising technology to mitigate degradation due to short-channel effects (SCEs) and gate leakage [START_REF] Wang | High performance of junctionless MOSFET with asymmetric gate[END_REF]. New manufacturing processes such as plasma [START_REF] Bashir | A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI[END_REF] and photolithograph [START_REF] Kuang | Flexible Single-Component-Polymer Resistive Memory for Ultrafast and Highly Compatible Nonvolatile Memory Applications[END_REF] are other approaches to implement high performant MOSFET. They offer many advantages, including low thermal budget, low fringing gate capacitances and simplified processing. Nevertheless, further study is needed on variability and reliability characterization, for instance. For example, in plasma process, silicon or other material surfaces of transistor is induced by high-energy ion bombardment incident [START_REF] Eriguchi | Impacts of plasma process-induced damage on MOSFET parameter variability and reliability[END_REF]. Hence, a lot of effort has been made by researchers in the recent years to experience new materiel on emergent structures, such as GaN SOI FinFET [START_REF] Kumar | Performance evaluation of linearity and intermodulation distortion of nanoscale GaN-SOI FinFET for RFIC design[END_REF], high-k gate SOI FET [START_REF] Gupta | Assessment of High-k Gate Stack on Sub-10 nm SOI-FinFET for High-Performance Analog and RF Applications Perspective[END_REF], S/D junction less SiNW MOSFET [START_REF] Gupta | Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design[END_REF], etc. to boost the IC electrical performance.

Drawing layout techniques for an efficient IC design is another promise solution still unexplored by the semiconductor foundries [START_REF] Gimenez | Layout techniques for MOSFETs[END_REF]. Namely, PN Junctions Engineering between the Drain/Source and the Channel Regions, the technique consists on changing the classical rectangular form of the gate to non-standard geometries such as ellipsoidal, circular, hexagonal, octagonal, fish and wave style [START_REF] Gimenez | Layout techniques for MOSFETs[END_REF]. In contrast to traditional transistors gate placement approaches, more geometrical design variables concerning longitudinal corner and parallel connection of transistors are added to other unknown electrical effects: new parasitics elements, leakage current pattern… Then, despite the cost manufacturing process still unchanged compared to the current planer transistor, the problem's complexity is raised and analog/RF designer becomes aware of the design tradeoffs.

Other design strategies have been expanded to maximize the RF characteristics of CMOS transistor as well as the noise reduction among series connections and multi-gate stacked transistors [START_REF] Jayamon | Multigate cell stacked FET design for millimeter wave CMOS[END_REF][START_REF] Dabag | Analysis and design of stacked-FET millimeter-wave power amplifiers[END_REF]. In this latter, connecting transistors in series with multiple gates allows a high breakdown voltage and a compact unit cell, but needs a careful implementation to avoid extra parasitic elements that can cause problems in matching and stability. An alternative approach consists in using multi-finger (MF) transistors that can simultaneously decrease the gate resistance and the capacitance parasitics, which directly affect the RF circuit performances [START_REF] Jeonand | Circuit level layout optimization of MOS transistor for RF and noise performance improvements[END_REF][START_REF] Apratim | A power-efficient process selection, gain optimization, and noise canceling technique for a 130nm microwave amplifier[END_REF]. In fact, reducing the gate series resistance impacts the device's figure-of-merit such as noise figure, maximum oscillation frequency, cut-off frequency, etc. [START_REF] Tong | A scalable RFCMOS noise model[END_REF][START_REF] Banchuin | Analytical analysis and modelling of variation in maximum frequency of oscillation of subthreshold MOSFET[END_REF][START_REF] Hee | Fmax improvement by controlling extrinsic parasitics in circuit-level MOS transistor[END_REF]. However, the transistor properties can change depending on the current direction [START_REF] El-Kenawy | Stress-aware analog layout devices pattern generation[END_REF]. Therefore, extra care must be taken when trying to achieve good matching [START_REF] Ahish | DC and analogue/radio frequency performance optimization of heterojunction double-gate tunnel field-effect transistor[END_REF]. The multi-finger layout of an RF transistor consists in splitting the gate into multiple fingers in parallel, as shown in Fig. 1. The width of the transistor is divided by the number of fingers (nf) inducing a smaller area occupation and a better matching compared to the single-finger (SF) configuration. In this work, the impact of number of fingers on the transistor parameters (Rg, fmax, fT, gm) and performances (noise, area, power consumption) is investigated on 130 nm CMOS technology. Afterward, MF transistors have been applied to implement the essential functions of the RF front-end receiver. Such an ample study of the effect of MF MOSFETs is first time proposed as the known of authors, determining the trade-offs to be considered on the design optimization of several main RF circuits (RF filter, Voltage-Controlled Oscillator VCO, Low-Noise Amplifier LNA).

The paper is organized as follows. Section II investigates the influence of multi-fingers on a single MOSFET features. Its application on the design of a differential RF bandpass filter is presented in section III. Then, implementations of an inductorless LC-VCO and an LNA using the multi-finger technique are presented in section IV and V, respectively. The obtained results are discussed for each RF circuit exploring the effect of multi-finger MOSFET on the design optimization. Also, Monte Carlo analysis has been conducted to consider the robustness and reliability of the circuits. Conclusions are drawn in Section VI.

Multi-finger impact on a single MOSFET

In this section, a brief study on the straightforward concept of multi-gate stacked MOSFET, is presented followed by impact of the number of fingers on different electrical parameters for conventional MF layout.

Basic concept of multi-gate MOSFET

In CMOS integrated circuit (IC) design, the gate layout is an essential feature that should be considered. For RF applications, MOS transistor with large gate dimensions is needed to meet the required transconductance together with high frequency, low power and low noise. But, large transistor cannot be arranged with simple gate because of performance degradation and technological restrictions [START_REF] Enz | An MOS transistor model for RF IC design valid in all regions of operation[END_REF]. Therefore, special layout approaches have to be deployed. The most effective technique in RF IC design is the multi-finger gate layout [START_REF] Enz | An MOS transistor model for RF IC design valid in all regions of operation[END_REF][START_REF] Morifuji | Future perspective and scaling down roadmap for RF CMOS[END_REF] (See Fig. 2). Transistors are designed in an interdigitated configuration in which the total channel width (W) is divided by the number of fingers, as illustrated in Fig. 3. All the gates, sources and drains are connected among themselves to make a single transistor. Thus, W can be expressed as follows [START_REF] Aguiar | Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients[END_REF]:

𝑊 = 𝑊 𝑓 . 𝑛 𝑓 ( 1
)
where Wf is the channel width of the transistor after division and nf is the number of fingers.

This results in a reduction of the effective area of the multi-finger transistor, as depicted in Fig. 4. For example, the area of a transistor with 2 fingers is lower by 22% than a single-finger one. Also, area diminution is about 35% for nf = 7. Another interesting layout structure, known as Waffle (WF) structure, has been presented in [START_REF] Wen | Layout effects on design optimization of CMOS LNA and mixer[END_REF] and [START_REF] Wen | High frequency characteristics of MOSFETs with compact waffle layout[END_REF]. It consists in arranging the MOSFET gate fingers in a square grid topology. Two implementation style of the WF structure, called Manhattan Gate (MG-WF) and Manhattan Interconnect (MI-WF) are depicted in Fig. 5. Each square contains a single contact, while drain and source metallization is a series of diagonal stripes [START_REF] Gouveia-Filho Da Costa | Advanced compact model for the charges and capacitances of short-channel MOS transistors[END_REF]. In [START_REF] Wu | Comparative analysis and parameter extraction of enhanced waffle MOSFET[END_REF], a comparative analysis between the WF and MF layout structures, achieved for a given device area, is discussed. It shows that the waffle layout has a better packing density and a smaller parasitic capacitance than the MF layout. Although the compactness of the WF layout, it is not a known gate structure in CMOS RF design and has complex modeling issues especially in high frequencies [START_REF] Lam | An enhanced compact waffle MOSFET with low drain capacitance from a standard submicron CMOS technology[END_REF]. Besides, using the multi-finger technique results in the gate resistance reduction [START_REF] Jeamsaksiri | A Low-cost 90nm RF-CMOS Platform for Record RF Circuit Performance[END_REF] and offers a simple design. But, even though access resistances are reduced, the coupling between the relatively wide metal lines leads to capacitive coupling effects and high parasitic capacitances [START_REF] Morifuji | Future perspective and scaling down roadmap for RF CMOS[END_REF][START_REF] Wen | High frequency characteristics of MOSFETs with compact waffle layout[END_REF][START_REF] Guo | A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs[END_REF][START_REF] Yeh | A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs[END_REF]. Hence, a judicious trade-off between the transistor parameters and number of fingers should be considered in RF circuit design.

Multi-finger effects on the MOSFET parameters

In the following, impacts of the number of fingers on high frequency and noise parameters on a single transistor are investigated. The next extracted parameters are derived through simulations of an NMOS transistor in 130 nm CMOS technology, at the biasing conditions Vgs=Vdd/2=0.6 V and Vds=1.2 V. The transistor channel length (L) is set constant to 0.13 µm.

 fT and fmax

It is known that, as the operating frequency is high, intrinsic components, such as capacitances, of the transistor become significant leading to a limit of operation. The most important frequencies characterizing the RF performance of MOSFETs are fT, the cut-off frequency of unity current gain, and fmax, the maximum oscillation frequency or frequency of unity power-gain [55]. Assuming that the drain-bulk capacitance Cdb is neglected, the fT and fmax can be estimated as [START_REF] Razavi | RF Microelectronics[END_REF]:

𝑓 𝑇 = 𝑔 𝑚 2𝜋(𝐶 𝑔𝑠 +𝐶 𝑔𝑑 )
(2)

𝑓 𝑚𝑎𝑥 ≈ 1 2√2𝜋 √ 𝑓 𝑇 𝑅 𝑔 𝐶 𝑔𝑑 ≈ 1 4𝜋 √ 𝑔 𝑚 𝑅 𝑔 𝐶 𝑔𝑑 (𝐶 𝑔𝑠 +𝐶 𝑔𝑑 ) (3)
where Cgs and Cgd are the gate-source and gate-drain capacitances, respectively, gm is the intrinsic transconductance and Rg is the gate resistance. Both fT and fmax depend on bias conditions and device geometry (nf and W/L). To validate this, an NMOS transistor has been simulated while varying its width and number of fingers. Fig. 6 shows the obtained fT and fmax characteristics versus nf, and their evolution relative to the initial value with single finger (dotted curves). As it can be noted, both fT and fmax increase when decreasing W, for a fixed nf value. For example, when using two fingers, fT is equal to 60 GHz and 75 GHz, for W = 120 µm and 15 µm, respectively. In fact, considering the velocity saturation region, and assuming that the short-channel effect does not change much the total capacitance (Cgs+Cgd), it can be derived that this latter is proportional to the gate width and length of the transistor [START_REF] Razavi | RF Microelectronics[END_REF]. Hence, fT, and so on fmax, is inversely proportional to W. Besides, both fT and fmax increase when increasing nf. For example, for W = 15 µm, using 10 fingers have a higher fT and fmax by 39% and 42%, respectively, compared to the single finger configuration. But, the percentage of evolution of each frequency value is higher when using narrow transistor widths. Also, the variation of the number of fingers has a bigger impact on fT and fmax for the smallest values of nf, essentially nf ≤ 10. After this value, increasing nf does not change the frequencies which remain almost constant around their maximal values.

 Rg, noise and gm

There is a trade-off in the layout of RF MOSFETs between the values of Rg and intrinsic capacitances [START_REF] Tong | Simple and accurate extraction methodology for RF MOSFET valid up to 20GHz[END_REF][START_REF] Yeh | Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40nm Multifinger nMOSFETs and pMOSFETs[END_REF]. Rg can be approximately modelled by:

𝑅 𝑔 ≈ 𝑅 𝑠𝑐ℎ 𝑊 𝐿 1 3.𝑁 𝑐𝑜𝑛 2 .𝑛𝑓 = 𝑅 𝑠𝑐ℎ 𝑊𝑓 𝐿 1 3.𝑁 𝑐𝑜𝑛 2 (4)
where Rsch is the resistance of poly layer (gate layer) and Ncon is the gate contact number (either 1 or 2) [START_REF] Enz | MOS transistor modeling for RF IC design[END_REF][START_REF] Frickey | Conversions between S, Z, Y, H, ABCD, and T parameters which are valid for complex source and load impedances[END_REF][START_REF] Cheng | Parameter extraction of accurate and scaleable substrate resistance components in RF MOSFETs[END_REF]. Since Rg is inversely proportional to nf, increasing nf will result in a reduction of the gate resistance for a constant W/L. The extracted result, given in Fig. 7(a), illustrates the influence of the number of fingers on Rg for different width values. For example, for W = 15 µm, it shows that resistance Rg decreases from 360 Ω to 19 Ω as the number of fingers increases from 1 to 6. Also, increasing W leads to an increase of Rg as given by Eq. ( 4). It can be noted that the variation of Rg versus the number of fingers has the same evolution when changing W, and that it is more important for small nf values.

Therefore, the current distribution in multi-finger transistors makes it possible to decrease the gate resistance, which is valuable for RF and noise performance [START_REF] Jin | An effective gate resistance model for CMOS RF and noise modeling[END_REF]. In order to evaluate the noise of a MOSFET, the function derived from the small signal model is determined by integrating all the sources of noise. The minimum noise factor can be expressed by:

𝑁𝐹 𝑚𝑖𝑛 = 1 + 𝐾 𝑓 𝑓 𝑚𝑎𝑥 𝑓 𝑇 √(𝑅 𝑔 + 𝑅 𝑠 )𝑔 𝑚 (5)
where Kf is the Fukui coefficient and Rs is the substrate resistance [START_REF] Fukui | Optimal noise figure of microwave GaAs MESFET's[END_REF]. The obtained equations Eq. ( 2) and Eq. ( 5) give:

(𝑁𝐹 𝑚𝑖𝑛 -1) = 1 + 𝐾 𝑓 𝜔 𝑚𝑎𝑥 𝐶 𝑔𝑠 √ 𝑅 𝑔 +𝑅 𝑠 𝑔 𝑚 (6)
Accordingly, the minimum noise factor NF can be improved by decreasing Rg. This latter is possible by decreasing the number of fingers as derived previously. Fig. 7(b) presents the variation of NFmin versus nf for different sets of W and frequencies of operation. The larger number of fingers yield to a lower noise factor. For example, as determined from Fig. 7(b), an NMOS with W = 15µm and operating at 2.51 GHz offers 77% improvement in NFmin when increasing nf from 1 to 6. Also, the narrower width will engender a lower noise factor. As it can be observed from Fig. 7(b), a 2.51 GHz NMOS using 3 fingers ensures an NFmin of 0.22 dB and 1.54 dB when W equals to 15 µm and 120 µm, respectively. Note that, by changing the frequency of operation, the same NFmin evolution versus the number of fingers is obtained when using the same width. In addition, increasing the transconductance gm can further improve NFmin as derived in Eq. ( 6). Fig. 8(a) depicts the impact of varying nf on gm. It is evident that increasing the number of fingers enhances the transconductance, and subsequently the minimum noise factor is reduced. Furthermore, power consumption is another important parameter that should be analyzed. Its dependence on the number of fingers is shown in Fig. 8(b) for different W. Since the drain current ID is directly proportional to gm, which is also dependent on nf, ID should have the same variation as gm versus nf. As suspected, it was found that ID, and thus the power consumption, increases when increasing the number of fingers (cf. Fig. 8(b)). Note that large transistors with fixed nf provide a higher consumption, as obviously known. Fig. 8(b) indicates an increase of the DC power from 1.9 mW to 15 mW for W equals to 15 µm and 120 µm, respectively, for fixed nf equals to 10.

It can be concluded that a trade-off is needed during nf selection between the power consumption, the noise and high frequency parameters of MOSFETs. Also, this MF approach is not so simple since it presents additional interferences with losses in silicon substrates, which can degrade the RF circuit performances.

Multi-finger effects on the MOSFET self-heating

Electro-thermal analysis is an important issue when multi-finger gate is used in design. Generally, to evaluate the temperature reached inside the junction, Foser model and Cauer model with the physic characteristics of the device are always used to predict thermal stress inside transistor devices [START_REF] März | Thermal modeling of power electronic systems[END_REF][START_REF] Wang | Temperature nonuniformity and bias-dependent thermal resistance in multi-finger MOS transistors[END_REF]. To provide a detailed dynamic of the time-dependent current distribution, TCAD simulations, i.e. 2D numerical simulations and 3D finites elements, are recommended for microscopic analysis behavior and heatsink.

In [START_REF] Meng | Compact distributed multi-finger MOSFET model for circuit-level ESD simulation[END_REF], a reliable study for 130 nm MOSFET was proposed by Meng et al through an empirical ionization model. Fig. 9 shows a 2D schematic of the architecture of 8-fingers transistor, and its thermal characteristic as a function of current input [START_REF] Meng | Compact distributed multi-finger MOSFET model for circuit-level ESD simulation[END_REF]. The study results show that the lattice temperature is highest near to the central fingers than that outside. At high current levels, the current per each finger consistently decreases as one moves to the outer fingers. Obviously, the thermal effect can be shrunken by increasing the lateral distance between fingers (Finger pitch) [START_REF] Yuan | Modeling and analysis for thermal management in gallium oxide field-effect transistors[END_REF] and hence a new attention to the influence of transistor geometry and layout on RF transistor becomes important. In Table 1, we regroup and focus on the impacts of the finger pitch (P), the finger width (W), and the poly number of fingers (nf) on the transistor parameters and its corresponding parasitic resistances and capacitances. Based on relations (2) and ( 3), fmax is dominated by resistance Rg and the gate capacitance Cgd/Cgs, and fT is dominated by transconductance gm and Cgd/Cgs. Thus, under a fixed W and P, increasing nf will reduce Rg and increase Cgd/Cgs. As a result, fT decreases with increasing nf and this particularly for a large nf. The effect on fmax becomes more complicated due to the parallel effect of Rg and Cgs/Cgd which play a conflicting action on fmax and hence the maximal frequency will be dependent to the dominant parameter. For example, for a small W, the influence of gate capacitance has a higher change than that of the gate resistance, thus resulting in fmax decreasing with increasing the number of finger nf

On the other hand, under a fixed nf and P, increasing W will increase both the resistance and the capacitance gate to decrease fmax. Transconductance gm is also affected, which increases with W, leads to a slightly increase of fT. Furthermore, under a fixed nf and W, increasing the distance of the finger pitch P, decreases slightly fT and fmax.

APPLICATION ON THE DESIGN OF A MF-BASED RF BANDPASS FILTER

After investigating the impact of multi-finger technique on single MOSFET parameters, this approach will be applied to optimize the design of a tunable RF bandpass filter (BPF). Fig. 10 depicts the implemented RF BPF topology along with the dimensions of the components. The circuit is based on a differential tunable active inductor (DTAI) composed of an active part comprising (M1-M8 and M9-M16) and a cross-coupled pair (M17-M18) for loss compensation. The analytical study of such tunable active inductor is detailed in [START_REF] Ben Hammadi | RF and microwave reconfigurable bandpass filter design using optimized active inductor circuit[END_REF][START_REF] Hammadi | An Enhanced Design of RF Integrated Differential Active Inductor[END_REF]. The BPF consists also of a differential input stage (M19 and M20) used to deliver the current applied to the DTAI, and a differential output stage (M21-M22 and M23-M24) utilized for matching and buffering. Note that the tuning of the center frequency of the filter is ensured through voltages Vctr1 and Vctr2, while the quality factor (Q) control is done by Vbias1. The proposed RF bandpass filter using single-finger and multi-finger MOSFETs has been simulated using Spectre-RF ® of Cadence ® considering the parasitic elements of the circuit. Hence, the impact of the MF optimization approach on the filter performances could be clearly assessed. The assessment focuses essentially on the area, voltage gain, noise figure, frequency tuning band, linearity and power consumption.

M 19 RF in+ M 7 V bias2 M 1 M 3 M 5 M 6 M 4 M 2 M 8 M 24 M 22 V ctr2 V ctr1 20
Implemented in 130 nm CMOS technology, distinct layouts of the BPF have been drawn with different aspect ratios. Fig. 11 depicts both optimized and not optimized layouts of the circuit. It is clear that using the multi-finger technique allows a higher layout density by almost 66.5% than that with single finger MOSFETs: 1934 µm² for conventional transistor and 1287 µm² for MF one. In addition to the area enhancement, the arrangement of MF transistors avoids unnecessary parasitic elements.

Furthermore, impact of the MF technique on the filter characteristics has been considered through postlayout simulations. Fig. 12 shows the transmission coefficient S21 response of the reconfigurable BPF with and without the multi-finger optimization. Note that as the control voltages Vctr1 and Vctr2 change, it is possible to tune the center frequency of the filter. The obtained frequency tuning band (FTB) varies from 0.62 to 5.67 GHz when using SF transistors, while it varies from 1.17 GHz to 3.28 GHz in the MF configuration. Despite the FTB reduction in the latter case, the simulated gain (S21) of the filter remains almost constant around 29 dB with the multi-finger optimization, as shown in Fig. 12(b). Also, a high power gain is achieved in the whole covered frequency band when using MF transistors. Such characteristic is important in reconfigurable circuits, which drives the use of this multi-finger optimization, maintaining a high and constant gain in the entire FTB. Due to the higher BPF gain with MF compared to SF configuration, the maximal quality factor is also increased and a Qmax of 107 is attained at 1.85 GHz when using MF transistors. Concerning the DC power consumption of the BPF, it is increased when increasing the number of fingers, as suspected from Fig. 8. An optimal choice of nf in the used MOSFETs gives an appropriate power consumption to the RF filter. It varies from 3.58 mW to 6.44 mW, from 1.2 V supply voltage, in the MF configuration when increasing the BPF center frequency. Whereas, it varies from 0.96 mW to 7.55 mW by using SF transistors. Besides, the noise characteristic of the designed differential BPF with its dynamic range has been examined depending on the MF approach. Fig. 13 shows the obtained noise figure responses versus the frequency for some selected control voltage combinations. It can be observed that the NF is 21.2 dB at 5.67GHz, with SF transistors, while it varies from 16.56 dB at 1.17 GHz to 14.48 dB at 3.28 GHz with MF MOSFETs. Analysis of the BPF linearity has been investigated through the input third-order intercept point (IIP3) and the input referred 1 dB compression point (Pin,1dB). A great improvement has been achieved when applying the MF technique. In fact, by rising the number of fingers, the IIP3 and Pin,1dB increase from -8.3 dBm to 8.43 dBm, and from -7.57 dBm to 2.72 dBm, respectively.

Application on the design of oscillator

Generally, characteristics of the voltage-controlled oscillator (VCO) in terms of phase noise and frequency tuning range impacts the whole transceiver performance. Accordingly, judicious design considerations have to be assessed to ensure high performance VCOs. In this section, the basic idea of NMOS cross-coupled LC-VCO [START_REF] Berny | A 1.8-GHz LC VCO with 1.3-GHz Tuning Range and Digital Amplitude Calibration[END_REF] has been exploited in an alternative topology in which the spiral inductor is replaced by a novel tunable active inductor (TAI). This latter is based on the Gyrator-C principle, often convenient to recognize the impact of multi-finger configurations.

The architecture of the proposed inductorless LC-VCO is shown in Fig. 15 with a focus on the tunable active inductor structure. To simplify the circuit presentation, it is reported that the oscillator is biased using a tail current source Mbias. By adjusting Vctrl, the resulting control current is applied to the cross-coupled M1,2 transistor sources to assure a reliable startup, perpetuate the oscillation and alter the output voltage swing, i.e. the voltage headroom. The LC-tank consists of a PMOS varactor for continuous tuning and two TAIs determining the oscillation frequencies. The topology of the proposed inductor is different from that used in the bandpass filter discussed in the previous section. It consists of three PMOS transistors to emulate the inductive behavior. The presence of an active feedback resistance (Rf) introduces an additional impedance to enhance the quality factor. Furthermore, a network of switched capacitors is added to adjust the inductance value independently. Thus, the circuit is designed to operate as a high impedance at 2.4 GHz to prevent the 2 nd order harmonic, meanwhile the maximum Q-factor of the TAI is 612 at 1.27 GHz. Deeper insight with detailed implementation and results of the TAI in 90nm CMOS process are given in [START_REF] Saad | A New Low Power, High-Q, Wide Tunable CMOS Active Inductor for RF Applications[END_REF][START_REF] Saad | Design of High-Performance CMOS Tunable Active Inductor[END_REF][START_REF] Saad | An Ultra-Compact Multi-Band VCO Achieving -196 dB FoMA with Single-Ended Tunable Active Inductor[END_REF].

In order to investigate the effect of MF technique, a comparison between two separate layouts using conventional gate-above-device (CGAD) and MF technique is given, as shown in Fig. 16. The area occupation of the VCO presents a reduction about 6% when applying the multi-finger approach. In the optimized MF-based circuit, the layout has a total area of 1772 µm², while the original one occupies a size of 1882 µm². In the following study, the obtained results are provided through three different configurations.

• Configuration I: using the conventional SF MOSFETs.

• Configuration II: using the optimized MF technique, with nf = 2 for some transistors.

• Configuration III: using MF transistors too, with nf > 2 to demonstrate the MF technique limits. Fig. 17 depicts the frequency tuning characteristic of the VCO for the different configurations. A narrow frequency tuning range of 0.75% is achieved while changing the control voltage from -1.2 V to 0 V. In configurations I and II, the obtained frequency range is [2.4, 2.418] GHz with a tuning sensitivity of 18 MHz/V. In configuration III, the frequency band increases slightly at the cost of an undesired nonlinear zone. Fig. 18 illustrates the output waveforms of the differential outputs at 2.4 GHz, showing that the voltage magnitude rises from 0.49 V to 0.67 V when changing the MF configurations. Unfortunately, the total harmonic distortion (THD) results show a degradation especially for the multi-finger device when nf is superior to 2. The THD can be defined as follows [START_REF] Ler | CMOS Active Inductor Linearity Improvement Using Feed-Forward Current Source Technique[END_REF]:

𝑇𝐻𝐷 = √∑ 𝐼 𝑛 2 𝐼 1 2 ⁄ ∞ 𝑛=2 (8)
where I1 and In are fundamental and nth harmonic current of the oscillator, respectively.

In fact, due to the increased gm compared to conventional device, the quantity of drain current has a main impact on the total unwanted harmonic current, which also affects the fundamental current, and thus influences the oscillation. Regarding Fig. 20, the THD improvement is more significant while using single finger device (configuration I) or bi-finger transistor (configuration II). For fair comparison, at 2.4 GHz, the THD of the VCO with nf = 1 and nf = 2 is 3.4% and 3.76%, respectively, whereas the THD of the VCO with nf > 2 sharing is 8.21%.

THD [%] Vctr 2 [V]

Configuration I Configuration II Configuration III 8.21%@2.4GHz 8.5%@2.421GHz 3.76%@2.4GHz 3.4%@2.4GHz 4%@2.419GHz 3.67%@2.418GHz . 3 recapitulates the obtained performances of the three designed oscillators. To summarize, the use of multi-finger transistors provides a certain level of enhancements that results in area reduction, but a deliberate nf > 2 would further degrade the KVCO linearity and also the THD, which degrades the performances and limits the reliability of the circuit. Monte Carlo analysis is also achieved to assess the robustness of the optimized VCO to process and mismatch uncertainties. Monte Carlo simulations are performed with 100 runs for random values. Fig. 22, depicts the results for the two fundamental parameters of an oscillator: natural free-running frequency and phase noise. As depicted in Fig. 22(a), the oscillator frequency shows a robustness to process and mismatch variations with 98% of samples between 2404.17 and 2404.18 MHz in distribution of the mean value, i.e. 2404.18 MHz. In addition, a steady PN at 108.5 dBc/Hz has been obtained as shown in Fig. 22(b). These results demonstrate the reliability of the designed oscillator and its stability versus process and mismatch variations.

Application on the design of Low Noise Amplifier

The LNA is one of the most important blocks in RF receivers, since it is the first building block so that its characteristics influence the whole reception chain. To investigate the effect of MF technique on the performances, two principal considerations have been applied to design RF LNAs [START_REF] Cho | An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13 μm CMOS Technology[END_REF]:

 Determine the circuit topology and it is matching network,  Select the bias point of transistors and hence their topology.

In most cases of circuit design, few numbers of transistors are preferred to realize a straightforward core. In LNAs, the design challenge is to ensure a good agreement between wide band gain flatness, low noise figure, high linearity and broadband impedance matching [START_REF] Song | A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications[END_REF]. In the studied application, a common gate (CG) topology has been used as illustrated in Fig. 23. This cascode structure provides a better isolation between input/output, where M2 assures the isolation of Miller capacitance. The input matching network includes the capacitor Cin and the inductor Lg, inductor Ls operates as the resonant frequency. Inductor Ld with capacitors Cd and Cout determine the resonant frequency and form the output matching network. The LNA has been implemented in 130 nm CMOS technology. The total area of LNA is approximately (658 x 435) µm², as shown in Fig. 24. In presence of many passive components, i.e. three spiral inductors and three MIM capacitors, which dominates the space, the MF technique is not beneficial to optimize the surface. As an indication, Fig. 24(b), shows that using two-finger based transistor M1 can reduce the area from 255µm² to 144µm², which is an important feature in inductorless designs. The obtained noise figure is also depicted in Fig. 26(b) showing that it is improved while increasing the number of fingers, as already discussed in section 2. Fig. 27(a) gives an important information about the LNA stability by plotting the Kf parameter. It indicates a stable operation in configurations (I) and (II), while an instability occurs when the number of fingers is superior to 2, i.e. in configuration (III). Thus, although its good outputreturn loss (S22) of -34.8 dB, peak gain (S21max) of 22.1 dB and minimum NF of 3.55 dB, the configuration (III) is instable. This limitation could be avoided through a resizing of the transistors. With the new optimal sizing of the LNA components, it become unconditionally stable (Kf >1) over high frequencies, together with a good power gain of 20.35 dB after matching proof. Under a supply voltage of 1.2 V and a bias current of 5.83 mA, the power consumption of the core circuit is around 7.27 mW as demonstrated in Fig. 27(b). This result is in correlation with the previous study of the nf impact on MOSFETs. To qualify the effect of process and mismatch variations after MF optimization, Monte Carlo simulations have been performed with 100 iterations. They are performed for the principal performances of the LNA, i.e. the gain and noise figure. Fig. 28 depicts the obtained results as statistical histograms. The Gaussian distributions at  3 level show that 98.5% of the total samples of S21max occurs with bound between 20.302 and 20.392 dB, while 93% samples lead to be between 5.582 and 5.585 dB in distribution of NF. Thus, the gain and NF of the LNA are robust to mismatch with only 0.073% and 0.13% deviation, referring to their respective mean values.

It can be seen that the bi-finger structure (Configuration II) gives the best tradeoffs. It achieves a good input matching (S11 < -10 dB) in the desired frequency range with the lowest noise figure of 5.58 dB at 2.4 GHz, a valid stability condition (Kf > 1  frequency) and a suitable power consumption. Note that there is a severe tradeoff between input impedance matching and noise figure. For CG-LNA keeping a good S11 with a noise figure lower than 4 dB is very difficult [START_REF] Song | A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications[END_REF]. By additional optimization effort in configuration (III), the noise performance of the LNA can be further improved at a cost of decreasing the input impedance matching and affecting the linearity. For instance, the geometry of transistor M1 has been adjusted to be 26 µm for an nf = 4. In this case, the LNA returns stable with a new NF of 3.63 dB (< 4 dB). In the present optimization, the circuit requires a careful re-sizing of the components, as changing Ld and Ls in order to maintain input/output matching without sacrificing the gain. But, keeping the increase of nf may destroy the input matching and hence break the stability. Table 5 gives an overview of the obtained results after the final optimization.

CONCLUSION

The effects of the Multi-finger gate on area, power consumption, noise, maximum oscillation frequency fmax and cutoff frequency fT of the 130 nm CMOS MOSFETs has been systematically investigated by Virtuoso ® simulation and compared to the conventional one. Both Rg and NFmin decrease with increasing the number of finger. Moreover, the finger width W, pitch P and number nf modulate the gate capacitance Cg and resistance Rg, and thus, in turn, fmax, fT.

An implementation to a reconfigurable RF differential bandpass filter, inductorless LC-VCO and LNA has been also developed with and without using the MF optimization, showing significant improvements in RF characteristics depending on the number of fingers. Overall, based on design trade-offs required to achieve the best RF performance (stability, noise and gain), MF optimization technique reveals that the influences are more obvious in the finger range of less than 5, thus implying that the MF design is reliable for CMOS technology in RF applications. With suggested configurations, proposed circuits present robustness to Monto Carlo statistical analyses, random process and mismatch, as well as environmental variations when using multi-finger MOSFETs.

Fig. 1 .

 1 Fig. 1. Example of (a) a single-finger (SF), and (b) a multi-finger (MF) transistor layouts

Fig. 2 .

 2 Single connection (a) and double connection (b) gate layout for MOSFET transistor

Fig. 3 .

 3 Fig. 3. Variation of W versus the number of fingers: W=15 µm.

Fig. 4 .

 4 Fig. 4. Area variation versus the number of fingers

Fig. 5 .

 5 Manhattan Gate (a) and Manhattan Interconnect (b) implementation for MOSFET transistor layout.

Fig. 6 .

 6 Fig. 6. Effect of nf on (a) fmax and (b) fT characteristics for different widths

Fig. 7 .

 7 Fig. 7. Effect of nf on (a) the gate resistance and (b) the noise figure

Fig. 8 .

 8 Effect of nf on (a) the transconductance and (b) the power consumption of an NMOS

Fig. 9 .

 9 Fig.9. Temperature distribution profile of an 8-fingers NMOS[START_REF] Meng | Compact distributed multi-finger MOSFET model for circuit-level ESD simulation[END_REF]

Tab. 1 .

 1 Summary on the geometry of the finger impact on parasitic elements

Fig. 10 .

 10 Fig. 10. RF differential bandpass filter using MF transistors

Fig. 11 .

 11 Layouts of the differential BPF: (a) without and (b) with multi-finger optimization

Fig. 12 .Fig. 13 .Fig. 14 .

 121314 Fig. 12. Transmission coefficient S21 versus frequency of the differential BPF: (a) without and (b) with multi-finger optimization

Fig. 15 .

 15 Fig. 15. Architecture of the LC-VCO and its tunable active inductor

Fig. 16 .

 16 Fig. 16. Layouts of the inductorless LC-VCO without and with multi-finger optimization

Fig. 17 .Fig. 18 .

 1718 Fig. 17. Comparison of the frequency tuning characteristics of the VCO for different configurations

Fig. 19 .Fig. 20 .Fig. 21 .

 192021 Fig. 19. Evaluated Phase Noise (PN) at 2.4 GHz of the VCO for different configurations

Fig. 22 .

 22 Monte Carlo analysis of the VCO: (a) central frequency (2.4GHz), (b) Phase Noise@10MHz

Fig. 23 .

 23 Fig. 23.Schematic of the Low Noise Amplifier (LNA)

Fig. 25

 25 Fig.25depicts the variations of S11 and S22 parameters for the different configurations mentioned above. In Fig.25(a), the maximum input-return loss S11 is -44.17 dB in design (II), which is 2.5 dB higher than the obtained results from designs (I) and (III). The measured S22 gives values under -17.4 dB, -23 dB and -24.8 dB for configurations (I), (II) and (III) respectively. Moreover, the LNA achieves a high-power gain (S21max) that varies between 19 dB and 22 dB at 2.4GHz over the three designs, as illustrated in Fig.26(a). It can be noted that the gain performance is slightly sensitive to MF technique.

Fig. 24 .Fig. 25 .

 2425 Fig. 24. (a) Layout of the LNA with and without multi-finger optimization, and a zoom on the (b) transistors: before and after optimization

Fig. 26 .Fig. 27 .

 2627 (a) Transmission coefficient (S21) and (b) Noise Figure versus frequency of the LNA, (a) Stability versus frequency of the LNA and (b) power consumption: with and without multi-finger optimization

Fig. 28 .

 28 Monte Carlo analysis of the LNA: (a) Gain (S21max) and (b) Noise Figure (NF) after optimization

Table 2

 2 summarizes the performances of the designed differential bandpass filter with and without the multifinger optimization. It illustrates that this MF technique allows a high gain, low noise figure, good linearity with suitable frequency tuning range and power consumption. A good robustness to Monte Carlo variations is also observed.

		Tab. 2. Summary of the RF differential BPF performances
			Without optimization With optimization	Gain (), Loss ()
	Tuning frequency	[GHz]	0.62 -5.67	1.17 -3.28	Δf	-58.21%	
	Gain (S21)	[dB]	0.9 -37	13.56 -33.45	S21max	-9.6%	
	NF	[dB]	21.2-25.5	14.48-16.58	NFmax	-43.21%	
	Pin,1dB	[dBm]	-7.57	+2.72		+135.93%	
	IIP3	[dBm]	-8.3	+8.43		+200.56%	
	Qmax @ frequency	-	30@2.5GHz	107@5.4GHz	Qmax	+256.66%	
	Power	[mW]	0.96 -7.55	3.58 -6.44	Pmax	-14.7%	

  Tab. 3. Performances summary of the VCO for the different configurations

						Config. I vs Config. II
			Configuration I	Configuration II Configuration III
						Gain (), Loss ()
	Vpp (V)	[mV]	490	526	668	+7.3%	
	KVCO	[MHz/V]	17.9	17.4	20.6	-2.8%	
	FTR	[%]	0.747	0.722	0.855	-3.4%	
	THD	[%]	3.395	3.76	8.21	+10.8%	
	PN@10MHz [dBc/Hz]	-107.3@2.4GHz	-107.5@2.4GHz	-108.6@2.4GHz	-0.2%	
	Power	[mW]	5.04	5.22	5.49	+3.6%	
	Area	[µm²]	1887	1772	Not released	-6.1%	
	FoM	[dBc/Hz]	-147.88	-147.93	-148.8	-0.04%	
	FoMT	[dBc/Hz]	-170.4	-170.7	-170.1	-0.18%	
	FoMA	[dBc/Hz]	-175.2	-175.5	Not released	-0.17%	

Table 4

 4 Summaries the LNA's design performances. The figure of Merit defines as follows[START_REF] Sayag | A 25 GHz 3.3 dB NF low noise amplifier based upon slow wave transmission lines and the 0.18 μm CMOS technology[END_REF][START_REF] Sanduleanu | 31-34GHz low noise amplifier with on-chip microstrip lines and inter-stage matching in 90-nm baseline CMOS[END_REF] is also compared:

	𝐹𝑜𝑀 =	𝑆21[𝑑𝐵].𝐵𝑊[𝐺𝐻𝑧] (𝑁𝐹[𝑑𝐵]-1).𝑃 𝐷𝐶 [𝑚𝑊]

  Tab. 4. Summary of LNA performances for the different configurations

			Configuration I	Configuration II	Configuration III
	S11	[dB]	-17.068	-44.171	-18.555
	S21	[dB]	19.123	20.355	22.11
	S22	[dB]	-17.393	-24.827	-23.107
	NF	[dBm]	6.326	5.584	3.551
	Power	[mW]	7.256	7.276	7.554
	Pin,1dB	[dBm]	-18.635	-18.665	-18.742
	IIP3	[dBm]	-23.55	-24.11	-24.44
	THD	[%]	10.5	14	15.6
	Gain/PDC	[dB/mW] 2.63	2.8	2.92
	BW	[MHz]	228	256	304
	Kf @ 2.4GHz	-	1.407	2.934	3.456
	Kf along frequency	-	>1  [frequency]	>1  [frequency]	< 1 [4 GHz ; 5.2 GHz]
	FoM	-	0.142	0.156	0.349
	Area	[mm²]		0.286