Keywords: Silicon-on-insulator (SOI), pseudo-MOSFET Silicium-Sur-Isolant (SOI), pseudo-MOSFET (Ψ-MOSFET), statique I

Electrical characterization and modeling of advanced SOI substrates

Silicon-on-insulator (SOI) substrates represent the best solution to achieve high performance devices. Electrical characterization methods are required to monitor the material quality before full transistor fabrication. The classical configuration used for SOI measurements is the pseudo-MOSFET. In this thesis, we focused on the enrichment of techniques in Ψ-MOSFET for the characterization of bare SOI and III-V wafers. The experimental setup for static I D -V G was improved using a vacuum contact for the back gate, increasing the measurement stability. Furthermore, this contact proved to be critical for achieving correct capacitance values with split-CV and quasi-static techniques (QSCV). We addressed the possibility to extract Dit values from split-CV and we demonstrated by modeling that it is impossible in typical sized SOI samples because of the time constant associated to the channel formation. The limitation was solved performing QSCV measurements. Dit signature was experimentally evidenced and physically described. Several SOI structures (thick and ultra-thin silicon films and BOX) were characterized. In case of passivated samples, the QSCV is mostly sensitive to the silicon film-BOX interface. In non-passivated wafers, a large defect related peak appears at constant energy value, independently of the film thickness; it is associated to the native oxide present on the silicon surface. For low-frequency noise measurements, a physical model proved that the signal arises from localized regions surrounding the source and drain contacts.

I am also very grateful to Prof. Gérard Ghibaudo for constant support and help. Despite the fact I was not officially one of his Ph.D. students, he gave me several suggestions and these results were obtained also thanks to him.

Particular acknowledges to Xavier Mescot and Martine Gri. Their help and support in the characterization laboratory were priceless. Without them this thesis would be of lesser quality. I would also like to thank all my colleagues at IMEP-LAHC (and not only). Special thanks to my office-mates in A-287. They helped me during these three years and they supported me during the difficult periods. Professional and personal discussions have been the key to this successful Ph.D.

The SOI samples were provided by Soitec™.

I would like to also thank Dr. Lukas Czornomaz, Dr. Vladimir Dijara and Dr. Jean Fomperyne from IBM for the collaboration with them in Ruschilikon (CH). In one month I learned a lot, and I had the chance to see a different working approach. It was very interesting for me.

I would like to thank Dr. Julie Widiez, Mathilde Lemang and Sebastien Sollier from the CEA, for their collaboration on the characterization of III-V materials.

There are a lot of other people who helped/supported me during this work (directly or indirectly).

Even if their names are not present in this list, I really appreciated their help and working with them. To all of them I give my deepest and most grateful thanks.

I was very lucky to meet and know all of you. Thanks!

Table of contents vii

Table of Contents

I.1 MOS transistors: state of art and trends

The concept for a Field Effect Transistor (FET) was invented by Lilienfeld [1] in 1930. It did not immediately catch the attention of the research community and the idea was not applied until 1948, when the first device was fabricated at Bell Labs [2]. After the fabrication of the first integrated circuit (IC) in the 1958 [3], the topic became hot and a lot of industrial companies and researches focused their attention on transistors.

Nowadays, MOS transistors are the base of all the integrated circuits which constitute the electronic devices largely present in our life: computers, cars, phones, etc., leading to huge market place that changed our social behavior [4].

Metal-oxide-semiconductor field effect transistor

The microelectronics world is based on simple devices that can operate together to compute complex functions. In general, these devices are classified according to their operation principle. We focus here on the metal-oxide-semiconductor field effect transistor (MOSFET), the primary device for circuits.

Figure I-1a shows the structure. It is easier to analyze it along the vertical (x) and horizontal (y) axis separately [5]:

o Along the x-axis we have a metal-oxide-semiconductor (MOS) structure. The semiconductor is typically nearly doped silicon (in the example, it is p-type, thus a n-MOSFET is obtained). On top of it, a silicon-dioxide layer is fabricated and serves as gate oxide. A conductive gate is placed on the top interface of the SiO 2 . The gate bias V G controls the electronic bands bending in the silicon, at the interface with the gate oxide. A conduction channel made of electrons is induced if V G > V T (threshold voltage). For low values of gate bias, no free carriers are present in the channel;

o Along the y-axis two highly doped regions (source and drain) are made by implantation of the silicon next to the conduction channel. Considering the case of p-type silicon film, the source and drain contacts are n ++ type. The source is grounded, while a bias is applied on the drain side (drain bias, V D ).

For V G << V T , no carrier flow is possible and the transistor is off. For gate bias values higher than the threshold voltage, a large current of electrons flows between source and drain contacts (drain current, I D ), making the device "on". o Off-state: V G << V T and no current flow is possible. The current measured for V G = 0, labeled I off , governs the static power consumption. The off-state current has to be as small as possible to reduce power dissipation [5];

o On-state: for V G > V T the conduction channel is completely created. The measured drain current at given V G and V D is labeled I on ;

o Subthreshold region: the channel starts to be created, but it is not yet complete. The slope of the I D in logarithmic scale versus V G (identified as subthreshold swing, S s = 1/slope) defines the speed at which the device can switch between on-state and off-state. High transistor performances are obtained for steep slope (fast on-off transition) [5].

Microelectronics trends

The transistor scaling down and performance improvements are the main topics of microelectronics industry and research. The mainstream is defined by the well-known "Moore's law" [7]: every decade of technology evolution corresponds to an extra order of magnitude in transistor density . In order to drive the microelectronics research & development, the International Technology Roadmap for Semiconductors (ITRS) presents the state-of-art and provides guidelines and targets for the following years.

Today the fabricated transistors have 22-30 nm gate length. The last updated report of IRTS in 2014 predicts that the logic industry will have transistors with sub-10 nm gate length in 2017 (7 nm node) [8]. However, physical limitations can compromise the device scaling down and limit the MOSFET performances:

o The decrease of the gate oxide thickness leads to an exponentially increase of the leakage current through the oxide (gate current, I G ) with consequent loss of transistor-like behavior [9]; o Decreasing the MOSFET dimensions, mobility degradation is due to limitations of fabrication process [10], [11]. The mobility degradation is smaller structures drastically limits the transistor speed;

o In high quality Si-SiO 2 interface, the subthreshold slope is not controlled by the transistor dimensions but is mainly a function of the temperature. Thus, at room temperature in the best case (SOI) it can be ≈ 66 mV/dec [5]. To obtain faster on-off transitions, new device architecture are demanded; o Short-channel effects (SCE): around source and drain contacts, depletion regions are present [5].

When the device becomes smaller, the two depleted regions can overlap, leading to loss of electrostatic control of the gate bias. In order to fabricate faster and smaller transistors, new architectures are required such as multi-gate (MG) structures.

Several solutions were proposed to overcome the problems, such as the replacement of polyscristalline Si used as gate with metal [12], the use of high-κ dielectric material instead of silicon-dioxide [13], the replacement of the silicon channel with new materials with high performances [14], [15], etc. Table I-1 reports the challenge for near-term 2013-2020 according to ITRS predictions.

Near-Term

2013-2020

Summary of Issues

Scaling Si CMOS  Scaling of fully depleted SOI and multi-gate (MG) structures  Implementation of gate-all-around (nanowire) structures  Controlling source/drain series resistance within tolerable limits  Further scaling of EOT with higher κ materials (κ > 30)  Threshold voltage tuning and control with metal gate and high-κ stack  Inducing adequate strain in advanced structures Implementation of high-mobility CMOS channel materials  Basic issues same as for Si devices listed above  High-κ gate dielectrics and interface state (D it ) control  CMOS (n-and p-channel) solution with monolithic material integration  Epitaxy of lattice-mismatched materials on Si substrate  Process complexity and compatibility with significant thermal budget limitations The short-channel effects that strongly affect the performances of small devices can be limited by particular transistor architectures. Two main ways were explored:

o STMicroelectronics®, Samsung® and GlobalFroundries® moved to MOSFET fabricated on siliconon-insulator (SOI technology) (Figure I-4a). Fully-depleted (FDSOI) transistors lead to several practical advantages like the reduction of short-channel effect [16], [17], the possibility to use multiple threshold voltage [18], [START_REF] Fenouillet-Beranger | Efficient multi-VT FDSOI technology with UTBOX for low power circuit design[END_REF] and the capability to achieve high performances (e.g., avoid mobility degradation) [START_REF] Doris | High performance FDSOI CMOS technology with metal gate and high-k[END_REF]- [START_REF] Vandooren | Scaling assessment of fully-depleted SOI technology at the 30nm gate length generation[END_REF]. The transistor structure is still planar (i.e., the conduction channel is on a twodimensional planes, as in Figure I-1a);

o Fin-shaped FET, called FinFET, is the architecture adopted by Intel®, Samsung®, TSMC and Global

Foundries . In this case the gate surrounds 3 sides of the silicon film which acts as conduction channel (3D structure). This allows a better electrostatic control. However, the fabrication process is very different to the planar structure and huge economic effort was required to implement it.

Note also that the FinFET fabrication is easier on SOI substrate [5]. The use of SOI improves the electrostatic isolation of the conduction channel and decreases the leakage current [6]. The feasibility and the interest of FinFET on SOI is documented in [START_REF] Okano | Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length[END_REF]- [START_REF] Hook | SOI FinFET versus bulk FinFET for 10nm and below[END_REF].

Hence, independently of the implemented MOSFET architecture (planar or 3D), it is clear that SOI substrates are superior for improving device performances. Thus, in this thesis we focus on SOI technology and, in the next sub-sections, after showing the schematic of SOI structure, a description of the main advantages and drawbacks arising from the use of SOI technology will be presented. FinFET structure [START_REF] Del Alamo | Nanometre-scale electronics with III-V compound semiconductors[END_REF].

Silicon-on-insulator structure

The SOI substrate is a multi-layer stack with a top silicon film, that acts as active layer for the devices, a buried oxide (BOX) used to isolate the active layer from the substrate and a low-doped p-type substrate used as mechanical support of the structure [6] (see Figure I-5).

Silicon film

Substrate

Buried Oxide (BOX)

Advantages of SOI technology

In MOSFET on bulk silicon (see Figure I-2) the conduction channel is confined close to the oxide interface. Most part of the thickness of the silicon substrate is not used but it is subject to parasitic effects such as current leakage, latch-up. Placing an oxide (called BOX or buried oxide) between the active layer and the substrate (see Figure I-4a), the conduction channel is isolated from the substrate, improving the transistor characteristics. This is the key point of SOI technology. Examples of benefits are:

-Reduction of parasitic capacitances; for example capacitances between source/drain contacts and the substrate are drastically reduced thanks to the presence of the BOX. Hence, devices fabricated on SOI work at higher frequencies than bulk technology [6];

-Reduction of short-channel effects: the surfaces of the source and drain junctions are now defined by the silicon film thickness. Thus, the depletion regions are spatially limited by the presence of the buried oxide and consequently they are reduced compared to a MOSFET on bulk silicon. In case of FDSOI, the gate has a better electrostatic control on the channel [16], [17];

-Improved device isolation: the buried oxide leads to better device isolation. Thus, phenomena like latch-up disappear leading to higher fabrication density [START_REF] Morishita | Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM[END_REF];

-Improvement of subthreshold swing: in FDSOI devices, the depletion region is confined in the top silicon film leading to smaller associated capacitance. Hence, the slope of drain current in weak inversion is improved. Values close to the theoretical 66 mV/dec can be achieved at room temperature [START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI[END_REF], [START_REF] Grenouillet | UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below[END_REF]. This allows the use of smaller threshold voltage and operating voltage, thus reducing the power consumption [START_REF] Banna | Fully depleted CMOS/SOI device design guidelines for low-power applications[END_REF], [START_REF] Munteanu | Modelisation et characterisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultra-mince[END_REF];

-Immunity against radiations: devices fabricated on SOI substrate are less affected by external radiations. Since the active layer (top silicon film of the SOI structure) is isolated from the bulk substrate by the buried oxide, the impact of transient effects or ionization phenomena are drastically attenuated [START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI[END_REF].

Issues with SOI technology

Despite the large numbers of advantages associated to SOI substrates, some drawbacks are still present:

-SOI quality: device performance improvements are obtained only in case of high quality SOI substrates. Thus, the carrier mobility in the silicon film has to be high and the density of defects low at silicon film-BOX interface;

-Production costs: SOI substrates are more expensive than bulk silicon. However, their use for mass production decreases the impact of the substrate price on the IC;

-Interface coupling: in FDSOI device, two silicon-SiO 2 interfaces are present: one between the conduction channel and gate oxide, and the second one between the Si layer and the buried oxide. In case of ultra-thin silicon films, electrical coupling can be present between the two interfaces. The models to describe the characteristics have to be adapted to the FDSOI case;

-Floating-body effect: the holes present in the channel are confined by the buried oxide and cannot be evacuated, affecting the device performances. An example is the enhancing of leakage current [START_REF] Ver Ploeg | Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's[END_REF]- [START_REF] Chen | The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta[END_REF];

-Self-heating effects: the buried oxide has smaller thermal conductivity than bulk silicon material. Thus, for high current flow, the generated heat remains confined in the conduction channel decreasing the device performances. The problem is negligible for dynamic operation of the device [START_REF] Yachou | Self-heating effects on SOI devices and implication to parameter extraction[END_REF].

I.2 SOI substrates

SOI fabrication

The SOI technology started with Silicon-on-Sapphire wafers (SOS) [START_REF] Cristoloveanu | Silicon films on sapphire[END_REF]. SOS substrates improved the resistance of the integrated circuits against radiations. Consequently, this technology was very appealing for space and military applications. However, the high fabrication costs and insufficient crystal quality limited the market.

A step forward was the fabrication of devices on implanted oxygen layer which formed an insulating film under the transistor [START_REF] Izumi | CMOS devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon[END_REF]. This opened the way to new fabrication processes like Separation by Implantation of Oxygen (SIMOX) [START_REF] Izumi | Historical overview of SIMOX[END_REF], Bond-and-Etch-Back SOI (BESOI) [START_REF] Mitani | Wafer bonding technology for silicon-on-lnsulator applications: A review[END_REF] and Epitaxial Layer

Transfer Wafer (ELTRAN) [START_REF] Yonehara | Epitaxial layer transfer by bond and etch back of porous Si[END_REF]. However, the interface quality was not high enough to introduce the SOI substrates in large-scale market.

The development of Smart-Cut™ process [START_REF] Bruel | Silicon on insulator material technology[END_REF] completely changed the SOI production. Today, the use of this technology allows the highest quality of silicon-on-insulator substrate [START_REF] Soitec | Soitec FD-2D -Next generation performance with current technology[END_REF].

The main steps involved in the Smart-Cut™ fabrication process are (see Figure I-6):

o Two silicon wafers are required: a 'donor wafer' labeled A and a 'handle wafer' B;

o Thermal oxidation is performed on the wafer A, to growth SiO 2 , that will be the BOX of the final SOI substrate. The oxidation process allows a precise control of SiO 2 quality and thickness;

o Hydrogen implantation is performed through the fabricated oxide. This induces micro-cavities that define the future plan of fracture (dash line in o The two wafers are put in contact and annealed, in order to increase the pressure of hydrogen molecules in the micro-cavities. This leads to H 2 propagation which induces an horizontal fracture in the wafer A;

o The two wafers are thus separated. The wafer B is now an SOI substrate suitable for device fabrication, while the wafer A can be reused for another SOI fabrication process.

The Smart-Cut™ technology has several advantages which justify its industrial interest:

-Low density of defects is present at the interface between the top silicon film and BOX;

-High quality silicon films are obtained;

-Conventional implantation and annealing tools are used;

-The top silicon film and BOX thickness can be easily adjusted to the wanted values.

SOI characterization

SOI substrates are clearly an asset for high quality devices but they must be of high quality. The huge fabrication progress achieved thanks to Smart-Cut™ leads todays to excellent quality substrates. However, as expressed by ITRS report, further developments on the SOI characterization (and monitoring) are required for two reasons [8]:

-Support the research and drive the next improvements on the fabrication processes;

-Monitor the fabricated substrates and their quality during mass production.

Structural characterization techniques for SOI substrates can be divided into two groups, according to their capability to investigate geometrical dimensions or defects of the material. The characterization of SOI substrates is more complex than standard bulk silicon. The presence of a supplementary oxide (the BOX)

with an additional Si-SiO 2 interface requires adapted characterization methods and new approaches when the standard techniques fail.

Focusing on the geometrical dimensions, the key properties which require very accurate measurements are:

-BOX and silicon film thickness: a small variation of their values drastically affects the electrical performances of the fabricated devices. Thus, they are monitored with variable-angle singlewavelength reflectometry, single-wavelength ellipsometry and spectroscopic ellipsometry [START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI[END_REF], [START_REF] Celler | Frontiers of silicon-on-insulator[END_REF];

-Wafer flatness is mandatory to make the SOI substrate compatible with all the tools required for MOSFET fabrication (especially for lithography steps).

Structural defects are also present in the SOI substrate and they can degrade the performance of the future transistors [START_REF] Munteanu | Modelisation et characterisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultra-mince[END_REF]. The most important are (see the schematic in Figure I-7):

-Dislocations and stacking faults are found as in standard bulk silicon;

-Surface roughness: it is a critical parameter because it can decrease the breakdown voltage on the fabricated device;

-Voids can be present at the BOX interface especially due to dust. Today this type of defects is very rare;

-"Pipes": are conductive vias which can be present in the oxide or in the silicon film. They act as a parallel resistor, increase the off-current and reduce the device immunity against radiations;

-Metal or alkaline ions contaminations: they can affect the fabrication process (metal contaminations)

or the electrical properties of the structure (alkaline ions contaminations). They decrease the minority carrier lifetime and the mobility;

-The level of residual oxygen or carbon in the silicon film: I off is increased and the breakdown voltage is decreased if these impurities are present;

-Fixed charges in the BOX: they affect the transistor threshold voltage and the leakage current;

-Interface traps density (D it ): these defects are due to the silicon-silicon dioxide interface and they can limit the electric properties of the transistor: poor subthreshold swing and low carrier mobility.

All these defects have to be minimized in a high quality SOI substrate. This is possible only improving the fabrication processes and monitoring the SOI production. Some examples of characterization methods for structural aspects of SOI are: AFM (Atomic Force Microscope), TRXF (Total Reflection at X Fluorescence)

and SIMS (Secondary Ion Mass Spectroscopy).

Silicon film

Electrical characterization

The SOI substrate serves to fabricate a MOSFET and if the SOI substrate is low quality, the final transistor will have poor performance. Thus, the key point is to evaluate the electrical impact of the listed defects. The best configuration to electrically characterize a bare SOI wafer without fabrication of the entire device is the pseudo-MOSFET [6].

I.3 Objectives and organization of the thesis

The previous section clearly showed the necessity to electrically characterize the SOI substrates after their fabrication and before the transistor production. The pseudo-MOSFET (see Sec. II.2) is the solution used ever since 1992. Its capability to measure carrier mobility and interface traps density was proved using I D -V G curves [6]. However, the reduction of the top silicon film and BOX thicknesses complicates the characterization and new techniques are required [START_REF] Celler | Frontiers of silicon-on-insulator[END_REF]- [START_REF] Diab | Nouvelles méthodes pseudo-MOSFET pour la caractérisation des substrats SOI avancés[END_REF].

The objective of this thesis is to enrich the characterization techniques suitable for bare SOI substrates in pseudo-MOSFET configuration, mostly focusing on the investigation of the quality of the interface between the top silicon film and the BOX:

o Chapter II reviews the pseudo-MOSFET principle. The importance of measurement setup will be largely detailed. Some precautions on the setup will provide their benefits for stable and reproducible I D -V G analysis. The possibility to characterize new materials like InGaAs will be addressed.

o In Chapter III, the split-CV technique will be revisited. The capability to measure the effective carrier mobility with split-CV was already proved [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF], [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF]. Some aspects concerning the die surface which contributes to the whole signal are here clarified. The possibility to extract the interface traps density will be discussed from experimental and modeling point of view.

o Chapter IV presents the quasi-static capacitance measurements performed for the first time on bare SOI wafers to achieve interface characterization. After discussing the measurement setup, a physical model will be derived and validated in different configurations. A suitable procedure to compute interface traps density will be presented, tested and applied to characterize several SOI geometries, from thick to ultra-thin films and BOXs.

o The low-frequency noise measurements performed in pseudo-MOSFET configuration will be addressed in Chapter V. This technique was expected to allow the characterization of interface traps density. Diab et al. [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF] already applied it in pseudo-MOSFET configuration but the extracted values of traps were not realistic and required explanations. Thanks to modeling, we explain the previous results. The capability to extract D it in Ψ-MOSFET is discussed through model and experiments.

o Chapter VI summarizes our results and addresses perspectives for future work.

Chapter II:

Pseudo-MOSFET for SOI characterization Equation Section (Next)

This chapter presents the characterization of bare SOI wafers performed using static drain current measurements in pseudo-MOSFET configuration. The principle of operation and measuring setup will be discussed. The impact of the quality of back contact and the role of the probes on the characteristics will be addressed. The characterization of III-V layers at different fabrication steps (from bulk material to fully fabricated device) is also shown.

Contents Chapter II

II.

II.1 The state-of-art in SOI electrical characterization

Accurate electrical characterization techniques are required to monitor the SOI material quality before pursuing device fabrication process. High transistor performances can be expected only if the carrier mobility in the top silicon film is high and the density of defects at Si film-buried oxide interface is low. In this context, we review here the electrical methods for SOI.

The simplest way to investigate the electrical properties of a material is the 4-probe resistivity measurement. In case of SOI, four needles are directly placed on the top surface of the Si film. A current I is imposed between the two external probes and the potential difference between the two inner probes is

measured (ΔV diff ) (Figure II-1)
. Knowing the inter-probe distance (d), it is possible to directly compute the material resistivity [START_REF] Schroder | Semiconductor material and device characterization[END_REF]:

diff V 2 d F I         (II.1)
where F is a correction factor taking into account the probe location with respect to the sample edges, the sample thickness and the probe diameter. Equation (II.1) is only valid if all the needles have the same interprobe distance d [START_REF] Schroder | Semiconductor material and device characterization[END_REF]. In case of large semiconductor samples, where the probes are placed far from the edges and in-line configuration is used (see Figure II-1), Eq. (II.1) can be re-written as a function of the sheet resistance R SH :

diff Si Si SH V 4.532 t t R I        (II.2)
where t Si is the silicon film thickness. The carrier mobility can be determined if the doping level is known.

However, with this configuration the interface traps density, that qualifies the quality of the BOX-film interface, cannot be measured. To overcome these limitations, a new method for SOI structure was proposed in 1992: the so-called pseudo-MOSFET (Ψ-MOSFET) (see Figure II-2a) [START_REF] Cristoloveanu | Point-contact pseudo-MOSFET for in-situ characterization of asgrown silicon-on-insulator wafers[END_REF], [START_REF] Liu | Fast turn characterization of SIMOX wafers[END_REF]. The silicon substrate is biased and used like a gate to create a conduction channel at the interface between the top Si and SiO 2 layers. Two probes with controlled pressure are directly placed on the top silicon surface to access the channel; they act as source and drain contacts. The structure is an upside-down MOSFET. Thus, the same characterization techniques classically used for standard MOSFET can be adopted to measure carrier mobility and D it in SOI substrate.

There are two key issues with Ψ-MOSFET:

1 The dimensions of the conduction channel are generally not well defined;

2 The quality of the source and drain contacts and therefore the access resistance is dependent on the probe penetration into the silicon film. Thus, they are sensitive to the pressure applied on the probes.

A variant of the standard Ψ-MOSFET technique was proposed in 1997: the HgFET [START_REF] Hovel | The HgFET: a new characterization tool for SOI silicon film properties[END_REF]. In this case, Hg circular contacts in Corbino configuration were used instead of adjustable pressure probe (see Figure

II-2b

). The channel geometry (length, width) is now clearly identified. However, in order to obtain good ohmic contacts, the silicon surface has to be cleaned to remove any existing oxide, such as the native oxide on the top silicon film. Furthermore the characterization will be time dependent because the contacts quality evolves in time.

Another possibility to characterize SOI substrates is to deposit metal contacts (source and drain) on the top of the silicon film (see Figure II-2c) [START_REF] Park | Pseudo-MOSFET Substrate Effects of Drain Current Hysteresis and Transient Behavior[END_REF], [START_REF] Cristoloveanu | The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications[END_REF]. In this case the channel dimensions are also well defined.

However, the configuration has several drawbacks: it requires fabrication steps, the contacts may not be ohmic, making the extraction procedure more complex.

In order to avoid contact related issues or uncertain channel definition, Ionescu et al. [START_REF] Ionescu | The intrinsic pseudo-MOSFET technique[END_REF] and Van Den Daele et al. [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF] merged the standard pseudo-MOSFET configuration with the 4-probes technique. This made the configuration pressure independent, leading to the characterization of ultra-thin SOI structures [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF].

However, the interface traps density could be determined only through simulations.

Among all these variants, the standard pseudo-MOSFET with pressure probes remains the most suitable configuration for the characterization of bare SOI wafers, because it does not need fabrication steps for the contacts and it adapts easily to any type of measurement already existing in MOSFETs. We will see in the next sections and chapters how the use of optimized measurement setup and different techniques can lead to parameter extractions, suitable for SOI quality monitoring.

II.2 Principle of Ψ-MOSFET and parameter extraction methods

A detailed description of the Ψ-MOSFET and extraction methods for electrical parameters (μ, D it ) from I D -V G characteristics will be provided in this section.

Sample preparation (between film and BOX via the sidewalls)

The pseudo-MOSFET configuration with pressure probes does not need contact process. Nevertheless, in order to avoid parasitic leakage currents, the SOI wafer needs a lithography step followed by etching to create square silicon islands (mesas) separated by 2 mm oxide (Figure II-3a). L is the side size of a mesa.

These mesas define the dies or the tested regions on the SOI. Most of the analyses were performed on structures with 25 mm 2 effective area (i.e., the mask size was 5 mm x 5 mm).

Operation principle

The electrical characterization was achieved using probe stations. Ψ-MOSFET is commonly performed using the adjustable pressure probe station from Jandel®. Four in-line needles with 1 mm interdistance are present. The pressure (p) can be precisely controlled between 0 g and 100 g, for each probe.

Since we have no direct information concerning the effective surface where p is applied, the word "pressure" may sound incorrect. However, note that it is just a reference to better adjust (and repeat) the probe penetration into the silicon film and no direct physical meaning is given to p magnitude. The probe radius typically used was 40 μm. The probe was made of WC.

Manual probe stations with micromanipulators can be also used, but the pressure cannot be precisely controlled.

In the following pages the principle to perform static drain current measurements (I D -V G and I D -V D ) will be explained. The particular setups required for capacitance or low-frequency noise measurements will be detailed in the corresponding chapters.

The SOI wafer is placed on a metallic chuck. Assuming that the top silicon film is grounded, the SOI substrate is polarized by V G applied through the chuck and it acts as a gate.

For V G = 0 V, the electronic bands of the top silicon layer are already bent due to the different Fermi levels between the gate and the top Si film, to D it and to fixed charges in the BOX. The flat band condition is To perform current measurements, one of the two adjustable pressure probes placed on the silicon surface will act as drain, while the second one will be grounded. For symmetry reasons, the two probes have the same pressure. p is a major parameter to achieve good characteristics: if it is too small, Schottky barriers are obtained. In case of too large pressures, the probes can reach the BOX, damaging it and making the die not suitable for any further analysis [START_REF] Ionica | Characterization of silicon-on-insulator films with pseudo-metal-oxide-semiconductor field-effect transistor: Correlation between contact pressure, crater morphology, and series resistance[END_REF].

achieved for V G = V FB (flat-band voltage). For V FB < V G < V T ,
The drain current (I D ) between the source and the drain contacts is obtained applying a bias

(V D > 0 V).

Parameter extraction procedure

In case of fabricated transistors with width W and length L, the drain current measured in linear regime is directly proportional to the applied V G and V D [5]:

  D OX eff G T D W I C V V V L        (II.3)
where C OX indicates the gate oxide capacitance defined as ε OX /t OX , with ε OX the oxide permittivity. The effective mobility μ eff takes into account the first order attenuation factor θ 1 due to access resistance R SD impact [START_REF] Schroder | Semiconductor material and device characterization[END_REF]:

  0 eff 1 G T 1 V V       (II.4)
where μ 0 is the low-field mobility. The transconductance g m is defined as:

  0 D m OX D 2 G 1 G T dI W g C V dV L 1 V V              (II.5)
To extract the low-field carrier mobility from I D -V G characteristics, erasing the effect of access resistance, the Y function method is largely used in MOSFET [START_REF] Ghibaudo | New method for the extraction of MOSFET parameters[END_REF]. Using Eqs. (II.3) and (II.5), the Y function can be written as:

  D 0 OX D G T m I W Y C V V V L g         (II.6)
The same equations are valid also in Ψ-MOSFET with two adjustments:

-The W/L ratio is defined by the so called geometrical factor f G obtained by comparison of 4-probes and two needles configuration [START_REF] Cristoloveanu | Point-contact pseudo-MOSFET for in-situ characterization of asgrown silicon-on-insulator wafers[END_REF]:

G W f 0.75 L  (II.7)
Recent works have shown that small die areas could lead to f G variation [START_REF] Cristoloveanu | A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications[END_REF]- [START_REF] Fernandez | On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates[END_REF]. In this work, large dies with respect to the inter-probe distance were used to avoid geometrical factor incertitude [START_REF] Pirro | Split-CV for pseudo-MOSFET characterization: Experimental setups and associated parameter extraction methods[END_REF].

They will be detailed in the next section.

- the intercept with the x-axis yields V T or V FB , while the slope is directly proportional to the square root of the low-field mobility.

In case of V G < 0 V,
As for MOSFET, the attenuation factor θ is defined as [START_REF] Ghibaudo | New method for the extraction of MOSFET parameters[END_REF]:

  D m G T GT I 1 g V V VV     (II.8)
θ should be constant in strong inversion (or accumulation) regime (see Figure II-6b) and the limit to high gate bias values leads to the calculation of the first-order attenuation factor θ 1 . This allows the computation of the access resistance [START_REF] Ghibaudo | New method for the extraction of MOSFET parameters[END_REF]: The slope of I D in logarithmic scale versus gate bias under threshold voltage (or V G > V FB for holes channel) leads to the subthreshold swing (S s ) which gives access to D it (interface traps density) [5]:

1 0 SD G OX R fC     (II.9) (a)
Si it s OX C q D kT S 2.3 1 qC          (II.10)
where the top silicon film capacitance is C Si = ε Si /t Si . ε Si is the silicon permittivity. Note that in SOI structures, two interfaces are present: one between the top silicon film and the BOX (called bottom interface) and a second one at the top surface of the silicon film (called top interface). Both of them can contribute to D it via coupling effects. In case of thick t Si , the coupling is low and D it is dominated by the contribution of the bottom interface. In ultra-thin silicon layers (< 20 nm) stronger coupling is present and D it gives an effective value of the contribution of both interfaces. Some models [START_REF] Rodriguez | Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX[END_REF], [START_REF] Rodriguez | Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin SOI Wafers[END_REF], based on the double gate approach [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF],

were proposed to separate the defects contribution coming from the top silicon film-BOX interface and the traps placed on the surface of the Si layer.

Before applying these extraction procedures to evaluate material properties (μ 0 , V T , V FB , D it , etc.), we must define the best measurement setup and experimental parameters.

II.3 Impact of measurement

In this section we discuss the precautions on the measurement setup that may reduce parasitic effects.

The importance of choosing good measurement times is presented in Sec. II.

II.3.1 Measurement time setup

In order to avoid transient effects and reduce noise, some measurement parameters have to be optimized [START_REF] Munteanu | Modelisation et characterisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultra-mince[END_REF]:

o Hold time: it is the time before starting the first measurement point and it must be long enough so that the structure is in equilibrium conditions at the beginning of the characterization. Used values range:

1-100 s;

o Delay time: it is the time between two consecutive measurement points and it must be long enough to avoid any transient effects due to out-of-equilibrium state. A too long delay time can stress the device.

All our measurements were obtained using a delay time between 0.4 s and 2 s.

o Integration time: the value obtained for each bias point is computed by integrating several measurements performed by the instrument at the same biasing condition. "Short" integration time means very short integration time range. The analysis is fast but usually the curves are noisy due to trapping/detrapping phenomena induced by surface defects. The use of "long" integration time reduces the noise on the characteristics becaue the structure is close to equilibrium condition; but the measurement is more time consuming. In this work, "medium" integration time was used for SOI structure with t Si = 88 nm, while "long" integration time was adopted in case of ultra-thin Si layers (t Si < 20 nm).

II.3.2 Quality of back contact

In Ψ-MOSFET configuration, V G is directly applied on the structure through the chuck. Hence, the quality of the "back contact" (contact between the back of the SOI substrate and the metallic chuck) may affect the obtained characteristics. This problem never arises in case of fully fabricated transistors, because metallic contacts are used.

Two different cases will be investigated:

o Air contact: the wafer is just placed on the metallic chuck. No particular precautions are used to improve the contact;

o Vacuum contact: a vacuum system is used to "stick" the SOI to the metallic surface. This avoids any possible parasitic contributions due to poor contact.

II.3.3 Role of the probes

The probes have an important role on the obtained Ψ-MOSFET characteristics. It was proved that R SD is directly related to the probe pressure [START_REF] Ionica | Characterization of silicon-on-insulator films with pseudo-metal-oxide-semiconductor field-effect transistor: Correlation between contact pressure, crater morphology, and series resistance[END_REF]. Furthermore, the probe position on the silicon surface can affect f G value [START_REF] Cristoloveanu | A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications[END_REF], [START_REF] Komiya | Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique[END_REF]. Several aspects will be addressed to clarify these effects and how they limit the extraction.

Probe choice

The Jandel® station has four in-line probes. In Ψ-MOSFET configuration only two probes are used, thus it is possible to choose among the four needles. We mainly considered the case with d = 1 mm.

Probes position

Border effects influence the pseudo-MOSFET measurements because they can affect f G [START_REF] Cristoloveanu | A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications[END_REF]- [START_REF] Fernandez | On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates[END_REF]. To verify if the use of vacuum system attenuates their impact, several characterizations were performed on the same die changing the position of the probes. The same needles with the same pressure were used. The II-1. In case of V G > 0 V, the mobility measured close to the edges is underestimated. In the worst case, the impact is lower than 10 %. Even smaller impact is found in case of hole mobility. μ 0 cannot change in an homogenous material according to the contacts position. The different values of μ 0 are due to variation of the geometrical factor (lower than 10 %). In conclusion, placing the probes at the center of the structure, makes f G variation negligible.

Probes pressure

The impact of probes pressure was already studied in pseudo-MOSFET [START_REF] Ionica | Characterization of silicon-on-insulator films with pseudo-metal-oxide-semiconductor field-effect transistor: Correlation between contact pressure, crater morphology, and series resistance[END_REF], [START_REF] Komiya | Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique[END_REF], but without vacuum. The needles were placed on the top silicon film using the lowest pressure. Next, p was gradually increased step by step, without moving the probes. Larger pressure leads to stronger probe penetration into the silicon film [START_REF] Ionica | Characterization of silicon-on-insulator films with pseudo-metal-oxide-semiconductor field-effect transistor: Correlation between contact pressure, crater morphology, and series resistance[END_REF]. The higher the pressure, the higher the measured drain current due to an improved contact (lower R SD ).

Y functions superpose and are stable as soon as the pressure is sufficient to have an acceptable contact (here p > 60 g). Mobility and R SD variation with p are reported in Table II-2, for electrons and holes. Note that pressure effect is much stronger in case of V G > 0 V (electrons) than for the holes, where only one point (p = 60 g) is slightly different from the other values. However, despite a pressure variation higher than ≈ 40 %, the mobility change is less than ≈ 10 %. Once the needles have sufficiently penetrated into the silicon film to contact the channel (p = 60 g in this case), p has only a low impact on μ 0 thanks to the Y function method that removes R SD effects.

Pressure of the probe and vacuum contact

In the previous section (Se. II.3.1) it was proved that the use of vacuum contact is mandatory in case of ultra-thin silicon film. Does the vacuum affect also the mobility-pressure trend?

To answer the question, SOI structure with ultra-thin silicon film (12 nm) and thick BOX (145 nm)

was characterized using different probe pressure.

Radius and probe material

Our Jandel® station has tungsten carbide (WC) probes. Their radius is of 40 μm. To investigate the impact of the probe radius R 0 , we used a manual probe station. The needles were made of WC and they had R 0 = 12 μm. The inter-probe distance was kept constant: d ≈ 1mm. II-4. The obtained electron and hole mobilities are lower in case of sharper tip, due to possible f G and R SD variation. Note that in manual probe station the probe pressure cannot be precisely adjusted. Agreement is found for threshold voltage, while a V FB shift is measured. Thus, the probe radius has a sizeable effect on the characteristics and the extracted physical parameters [START_REF] Munteanu | Modelisation et characterisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultra-mince[END_REF], [START_REF] Komiya | Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique[END_REF].

Additionally, we show the results obtained using tips made of different material, osmium (Os) in this example. The probe radius was 12 μm. The corresponding measured current is shown in Figure (continuous line) and the extracted values are reported in Table II-4. The highest access resistance was found in this case. For V G < 0 V, non-realistic low μ 0 mobility is measured, probably due to a non-ohmic contact. A clear shift of V T and V FB is also present. Thus, the extracted parameters are influenced by the probe material work function.

To perform wafer monitoring, it is important to use all the time tips with the same properties and adapted to the characterized material [START_REF] Microworld | Online document: Four Point Probe Resistivity[END_REF]. In this work, all the measurements performed on Si-SiO 2 wafers were obtained using WC tips with R 0 = 40 μm. V T (V) 3.9 3.9 4.5

μ

Reproducibility of tests

In pseudo-MOSFET configuration, the source and drain contacts are obtained using probes directly placed on top of the silicon surface. This can be a new source of variability added compared to standard transistors with fabricated metal contacts. In this section we investigated the reproducibility of material characterization (i.e., parameter extraction) obtained using the Y function method on static I D (V G ) curves. We also defined the order of magnitude of error bars of calculated μ 0 and V T .

The fitting range of Y function can affect the obtained results: a maximum variation of ± 4.5 % is obtained for μ 0 and ± 3 % for V T .

Figure II-13 shows the extracted low-field mobility (plain symbols) and threshold voltage (empty symbols) for different dies present on the same SOI wafer. The maximum incertitude of μ 0 is around ± 5 %.

Lightly lower variation is found for V T (± 3 %). Thus, total error bars around 15 % represent a good estimation for the measurement technique.

II.3.4 Passivated top silicon film

In the literature, one of the most frequent approaches to identify to which interface the characterization technique is sensitive, is the comparison between passivated and non-passivated SOI structures. 4 nm dry oxide grown on the top silicon film improves the corresponding interface quality. Thus, the D it associated to this interface decreases. Note that the penetration through the top oxide is easier in case of non-passivated sample (native SiO 2 )

than passivated one (thermal SiO 2 ). Thus, different probe pressures have to be used to achieve similar access resistance. In this example, p = 80 g for non-passivated sample leads to R SD = 3.4 kΩ, while p = 100 g on the passivated yields R SD = 4.5 kΩ.

II.4 Extension of Ψ-MOSFET to new materials: III-V-on-insulator

To pursue the transistor scaling down, the use of new materials instead of silicon channel is one of the mainstream topics [START_REF] Del Alamo | Nanometre-scale electronics with III-V compound semiconductors[END_REF], [START_REF] Egard | High transconductance self-aligned gate-last surface channel In0.53Ga0.47As MOSFET[END_REF], [START_REF] Gu | 20-80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63mV/dec[END_REF]. Recent researches focus on the fabrication of In 53% Ga 47% As (Indium-Gallium-Arsenide, labeled InGaAs) transistors thanks to their high electron mobility. InGaAs is a compound of elements of III nd and V th group, usually labeled as III-V. Different studies have proved the capability to fabricate III-V devices with good performances; high carrier mobility (2000-3000 cm 2 /Vs) and low subthreshold swing S s (80-70 mV/dec) were measured [START_REF] Kim | Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors[END_REF]- [START_REF] Czornomaz | Cointegration of InGaAs n-and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates[END_REF]. However, more research is required to make the fabrication processes of high quality III-V layer compatible with the silicon technology.

In this section, InGaAs layers will be characterized during the several fabrication steps:

-Before film transfer on oxide in Sec. II.4.1 (using Van der Pauw and Hall effects);

-After the transfer on oxide (III-V-OI) using Ψ-MOSFET-like configuration with pressure probes (Sec.

II.4.2) and with deposited metal contacts (Sec. II.4.3);

-Fully fabricated transistor (Sec. II.4.4).

II.4.1 Material characterization before bonding

In order to validate the quality of the fabricated III-V before any fabrication process, Hall effect measurements were performed on bulk material. The impact of t III-V was also investigated. Three samples of InGaAs were fabricated on InP substrate.

The same doping target was implanted: 5•10 The Hall mobility decreases with the III-V thickness, due to the stronger coupling between the bottom and top interface [START_REF] Kamins | Hall Mobility in Chemically Deposited Polycrystalline Silicon[END_REF], [START_REF] Hamaide | Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization[END_REF]. A mobility higher than 3000 cm 2 /Vs is measured even in ultra-thin films.

II.4.2 Ψ-MOSFET with pressure probes on III-V-on-insulator (III-V-OI)

In this section, III-V films were characterized after transfer on oxide (III-V-on-insulator). The III-V layer was non-intentionally doped (NID). 5 mm x 5 mm mesas were fabricated on all the wafers, as described in Figure II-3a. The measurements were performed using the adjustable pressure probe Jandel® station.

In order to verify the capability to characterize InGaAs substrate using Ψ-MOSFET technique, Figure A low I D magnitude may be due to high access resistance R SD . In Ψ-MOSFET, the increase of the probe pressure leads to better probe penetration into the silicon film, thus lower R SD (see Sec. II.3.3). studied. Thanks to its work function, Osmium is expected to lead to better contacts with the III-V layer [START_REF] Microworld | Online document: Four Point Probe Resistivity[END_REF].

The drain current magnitude still remains very low, making the characterization of III-V in standard Ψ-MOSFET configuration not possible with pressure probes. Consequently, III-V-OI substrates with metal contacts on top were fabricated and their characterization is shown in the next section.

II.4.3 Ψ-MOSFET with metal contacts on III-V-OI

Impact of fabrication annealing temperature

In this section, several III-V layers on oxide were characterized to find the best annealing temperature.

To succeed on the analysis, one wafer was fabricated (Figure II-20a) and cut in several pieces before annealing. Each piece was annealed using different temperature (T an ): 500 ºC and 600 ºC. To overcome the limitations found on the characterization of III-V material using the standard Ψ-MOSFET configuration, metal contacts were deposited on the top of the InGaAs layer (alloy of Ti/Au). No particular passivation was performed on top of the III-V film. The Y function method was used to extract μ 0 . Using a Corbino structure, the geometrical factor is well defined by the radius of drain contact (R 1 ) and the distance from the source contact to the center (R 2 ) [START_REF] Schroder | Semiconductor material and device characterization[END_REF], [START_REF] Hovel | The HgFET: a new characterization tool for SOI silicon film properties[END_REF], [START_REF] Cristoloveanu | The Corbino Pseudo-MOSFET on SOI: Measurements, Model, and Applications[END_REF] (see Figure II-20c):

G 2 1 22 f 9.06 500 m R ln ln 250 m R                    (II.11)
In order to reduce parasitic leakage currents which can limit the characteristics, each structure was isolated by the others through mesa fabrication (lithography and etching of III-V film). the wafer with T an = 600 ºC. Thus, it was not possible to measure μ 0 .

The Hall mobility was obtained without field effect and represents an average value in the film. On the other hand, μ 0 is the electron mobility in the channel which is notoriously smaller than the volume mobility [6].

μ 0 and μ Hall are related by the Hall scattering factor [5], [6]:

Hall H 0 r    (II.12)
which depends on the carrier mean free time between collisions. In silicon samples, it is 1.18 when phonon scattering is present and r H = 1.93 for Coulomb scattering.

In our case, the Hall scattering factor is non-realistic (> 100) due to the leakage current through the BOX. New samples are in preparation to duplicate the experimental results.

Mobility evolution with the measurement temperature

In this section we investigated the carrier mobility variation with temperature T. The tested structure is shown in the inset of Figure II-23b. The wafer was annealed at 600 ºC and no passivation was performed in the III-V surface. Note that even if the tested structure is similar to the ones characterized in the previous section, the fabrication process was quite different. Thus, a direct comparison of the obtained values is not possible.

μ Hall and the low-field mobility obtained at room temperature from three different dies are reported in The mobility measured at 77 K (μ 0_T=77K ) are equal to 489 cm 2 /Vs, 753 cm 2 /Vs and 675 cm 2 /Vs for the die A, B and C, respectively. However, since the main interest is to investigate the mobility trend with temperature, the obtained μ 0 were normalized with respect to μ 0_T=77K .

The results are presented in Figure II-23b as a function of temperature in logarithmic scale for the three different dies. T decrease leads to higher mobility. In order to identify which scattering phenomena dominates the mobility variations, a linear fit was performed (dashed lines). The slope is between 1.54 dec and 1.64 dec. In case of phonon scattering, μ 0 ∝ T -n , where n is between 1 and 2 [START_REF] Diab | Low-temperature pseudometal-oxide-semiconductor field-effect transistor measurements on bare silicon-on-insulator wafers[END_REF]. These results confirm that in our case the measured mobility variation is due to phonon scattering.

II.4.4 Preliminary results of III-V transistors

During COMPOSE 3 project [START_REF]Compose3 EU project[END_REF], preliminary transistors were fabricated on III-V-OI substrate by IBM. One possibility given by the presence of a buried oxide is the capability to tune the conduction channel with the back gate (V back ). Figure II-25a shows the measured

I D versus V G applying different V back .
Remarkable V T and S s variations are found due to the strong coupling effect.

Figure II-25b presents the obtained low-field mobility normalized with respect to μ 0 for V back = 0 V (μ 0_at_0V = 33 cm 2 /Vs) versus back gate bias. Using V back < 0 V, the conduction channel is more confined and closer to the interface with the top oxide. Thus, the carriers are more sensitive to the interface defects and the mobility is lowered. On the contrary, for V back > 0 V the density of free carriers present in the channel is larger and the electron flow is more localized at the middle of the III-V layer, reducing the interface influence. This variation confirms that the poor device performances (low μ 0 and poor S S ) are due to high density of interface defects.

II.5 Conclusions and perspectives

This chapter was divided into two main parts: one addressing the standard pseudo-MOSFET characterization of silicon-on-insulator and the second one focused on III-V layers.

The first part contains an exhaustive investigation of Ψ-MOSFET configuration and measurement setup. According to our setup, to achieve sound material characterization it is mandatory to use:

-A proper measurement time setup, in order to avoid out-of-equilibrium state and reduce noise. It is dependent on the characterized SOI structure. Ultra-thin films necessitate longer measurement time than t Si = 88 nm.

-A vacuum back contact, to reduce the presence of parasitic effects. Its use is necessary in case of ultrathin films. Thanks to this result, it maybe interesting to try new characterization techniques, such as chanrge pumping, and verify the effective impact of substrate capacitance, already investigated in characteristics obtained without using the vacuum system [START_REF] Rodriguez | Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX[END_REF], [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF].

-The correct probe configuration. The adjustable pressure probes have an important role on static I D -V G characterization. The pressure has to be large enough to achieve low access resistance. p can be different in case of passivated and non-passivated samples. Probe choice and position in the silicon film affect I D -V G characteristics but the use of Y function method attenuates R SD effects.

III-V materials were also characterized during several fabrication steps: before and after bonding on oxide and fully fabricated transistors. The results show that the unprocessed III-V film quality is high (μ Hall > 3000 cm 2 /Vs), also in case of ultra-thin films. However, the fabrication steps (transfer on oxide and device fabrication) degrade the carrier mobility, probably due to the high density of defects present at the interfaces.

Chapter III:

Split-CV in Ψ-MOSFET Equation Section (Next)

In the previous chapter, a detailed investigation of static characterization on SOI wafers has been performed. This chapter presents the split-CV capacitance technique. The impact of measurement setup will be addressed. Capacitance and conductance curves as a function of gate bias and angular frequency will be shown. A model based on physical equations will be examined to understand the experimental results and important questions concerning the possibility of D it extraction will be answered.

III.1 Introduction

Characterization methods based on static drain current measurements are powerful but they can have some limitations. For example, the extracted low-field mobility in very short MOSFETs is proportional to the gate length and the two parameters cannot be separately obtained without making hypothesis; this is inconvenient especially for advanced MOSFETs in which the effective electric length is not the design length [START_REF] Romanjek | Improved Split C-V Method for Effective Mobility Extraction in sub-0.1μm Si MOSFETs[END_REF]. Furthermore, static characterization does not allow direct measurement of effective carrier mobility (μ eff ). Split-CV configuration is largely used to overcome these problems. Originally, the configuration has been proposed by Koomen [87] to characterize interface trap density and substrate doping concentration in silicon MOSFET devices. Next, it has been applied for the study of carrier mobility by Sodini et al. [START_REF] Sodini | Charge accumulation and mobility in thin dielectric MOS transistors[END_REF]. Nowadays it is used for the investigation of the fabrication process impact on μ eff [START_REF] Takagi | Experimental evidence of inversion-layer mobility lowering in ultrathin gate oxide metal-oxide-semiconductor field-effect-transistors with direct tunneling current[END_REF]. The technique is based on two capacitance measurements (gate-to-channel C GC and gate-to-substrate C GS ) plus the I D -V G characteristic. Each of the capacitance terms gives access to different parameters/information: effective carrier mobility and effective electric field (E eff ). The saturation value (C GC_max ) corresponds to the device area (S = W•L) times the gate oxide capacitance (C OX ), which is inversely proportional to the oxide thickness (t OX ) [START_REF] Schroder | Semiconductor material and device characterization[END_REF]:

III.1.1 Split-CV in MOSFET devices

Gate-to-channel capacitance and effective carrier mobility

OX GC _ max OX OX C C S S t      (III.1)
where ε OX is the silicon dioxide permittivity. The integration of C GC leads to the calculation of the inversion charge density (Q i ) present in the channel:

G gacc V i G GC V 1 Q (V ) C (u)du S   (III.2)
where V gacc is the low limit of gate bias, usually taken in the accumulation regime (when C GC ≈ 0 F). Furthermore, a static I D -V G characterization on the same device allows calculating the effective carrier mobility:

      DG eff G i G D IV V W Q V V L   (III.3)
This result emphasizes the main interests of split-CV technique: μ eff extracted by direct measurement instead of the recalculated values typically obtained from Y function method.

Besides the interests of this technique, two precautions need to be taken [START_REF] Romanjek | Characterization of the effective mobility by split C(V) technique in sub 0.1μm Si and SiGe PMOSFETs[END_REF]:

o Device surface: if the device is too small, the characterization instruments reach the resolution limits and they cannot measure the channel capacitance;

o Eventual V T shift between capacitance and current measurements: this is a measurement artefact and it requires shift adjustment between C-V and I-V characteristics for μ eff calculation. The subject is still under investigation in the micro-electronic community [START_REF] Romanjek | Characterization of the effective mobility by split C(V) technique in sub 0.1μm Si and SiGe PMOSFETs[END_REF].

Gate-to-substrate capacitance and effective electric field

In order to measure the gate-to-substrate capacitance C GS , source and drain contacts have to be grounded, the substrate is connected to low potential and the gate to the high one (Figure III-2a). C GS contribution comes from the depletion charges (Q Dep ). Q Dep is directly proportional to the doping concentration (N a ) and the depletion width of the silicon film (x Dep ):

Dep a Dep Q q N x    (III.4)
C GS can be mathematically obtained by the derivative of the depletion charge with respect to the gate bias: Following the same approach as in Eq. (III.2), the integration of C GS leads to the depletion charge density magnitude:

Dep Dep GS a GG Qx C q N VV       (III.5)
G FB V Dep G GS V 1 Q (V ) C (u)du S   (III.6)
where V FB is the flat-band voltage.

Using the inversion charge Q i in Eq. (III.2) and the depletion charge in Eq. (III.6), it is possible to obtain the effective electric field E eff [START_REF] Sabnis | Characterization of the electron mobility in the inverted <100> Si surface[END_REF]:

i Dep eff Si QQ E     (III.7)
where η is the ideality factor. It is equal to 1/2 in case of electrons and to 1/3 in case of holes [START_REF] Byun | Unified charge control model and subthreshold current in heterostructure field-effect transistors[END_REF].

III.1.2 Split-CV in pseudo-MOSFET configuration: state of the art

The capability to directly measure the effective carrier mobility in fully fabricated MOSFETs makes split-CV technique very interesting also to monitor the quality of bare SOI substrates. Nayak et al. [START_REF] Nayak | Unusual C-V Characteristics of High-Resistivity SOI Wafers[END_REF] have presented characteristics obtained on high resistive wafers. Their use of metal contacts on the film inducing Schottky barriers makes the mobility extraction complicated. Diab et al. [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF] and Fernandez et al. [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF] have demonstrated that split-CV capacitance measurements can be performed using pseudo-MOSFET configuration. In this case, pressure probes lead to ohmic contacts between the conduction channel and the source and drain. Thus, the extraction of material properties becomes easier.

The following sections will focus on split-CV characteristics performed with Ψ-MOSFET. A description of measurement setup is presented below.

Measurement configuration

Two types of probe stations already presented for static characterization measurements are used here:

Jandel® station with pressure control probes and a classical probe station from Karlsuss® with manual probes, without pressure control. The SOI wafer is positioned on a metallic chuck that acts as a gate. One (or more) adjustable pressure probe is (are) placed on the top silicon film and connected to low potential (Figure sinusoidal signal δV G which is frequency f dependent, is added to V G . For all the measurements we have chosen δV G = 26 mV. This value is close to thermal potential fluctuations (k•T/q) in case of ambient temperature. δV G induces charge variation in the conduction channel, which is detected by the LCR meter thanks to a Wheatstone bridge. In order to achieve correct characteristics, open and short circuit corrections must be performed before any measurement. This avoids effects due to parasitic capacitances of the cables and the probe station [95], [96].

After the presentation of the measurement setup, the next section shows capacitance characteristics as a function of gate bias obtained in pseudo-MOSFET configuration.

(a) (b)

Si film

High Potential

Low Potential

C m_split BOX Si Substrate G m_split V G (V) t (s) 1/f 26mV

Capacitance versus gate bias

Figure III-4 shows the measured split-CV capacitance as a function of gate bias for different frequencies. For low V G magnitude, C GC is negligible before the conduction channel formation. Above V T (or V FB ) free carriers are induced by V G and the capacitance sharply increases until it saturates. Note that in case of pseudo-MOSFET, the probes placed on the top silicon surface can bring both types of carriers: positive gate bias induces electrons in the conduction channel, while V G < 0 V leads to holes accumulated at the interface between the top silicon film and the buried oxide. The curves behavior is similar to MOSFET device characteristics [START_REF] Takagi | Experimental evidence of inversion-layer mobility lowering in ultrathin gate oxide metal-oxide-semiconductor field-effect-transistors with direct tunneling current[END_REF], validating the technique for SOI wafers.

In the next section, we will show how there results were used to directly access the effective mobility.

Effective mobility extraction

Following the approach described in Sec. III.1.1, the effective carrier mobility can be computed using Eq. (III.3). In pseudo-MOSFET, W/L ratio is given by the geometrical factor f G (see Sec. II.2) [START_REF] Cristoloveanu | Point-contact pseudo-MOSFET for in-situ characterization of asgrown silicon-on-insulator wafers[END_REF], [START_REF] Cristoloveanu | A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications[END_REF]. μ eff values require also the calculation of inversion (or accumulation) charge density (Eq. (III.2)). Note that the measured maximum capacitance (C GC_mac ≈ 1.35 nF) obtained in Figure III-4 is much lower than the oxide capacitance (5.7 nF). Fernandez et al. [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF] proposed to introduce a fitting parameter called effective surface (S eff ) and defined as: from Y function method is also added in plain symbols [START_REF] Ghibaudo | New method for the extraction of MOSFET parameters[END_REF]:

0 eff 1 G T 1 (V V )      (III.9)
The curves perfectly overlap. The results show that effective carrier mobility can be measured using split-CV technique in pseudo-MOSFET configuration as for standard MOSFET devices. o Is it possible to characterize the interface quality using the conductance term from split-CV measurements?

The answers will be given in the following sections. We will start analyzing the reasons behind the use of S eff .

III.2 Effective surface and improved measurement setup

The first characteristics obtained in pseudo-MOSFET configuration [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF], [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF] have shown that contrary to standard MOSFET devices, the measured maximum capacitance is much lower than the expected value C OX •S. However, the use of a fitting parameter (S eff ) leads to correct effective mobility curves. In order to investigate the physics explanation behind this term, we study the impact of SOI die area, silicon film and BOX thicknesses.

III.2.1 Dependency of S eff

The effective surface was considered as issued from the area around the probes that "responds" during the split-CV measurements [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF]. If this is the case, S eff should be somehow related to the geometry of the sample. The corresponding effective surface is also reported. In case of thick buried oxide, S eff is independent of the top silicon film thickness. In case of ultra-thin SOI structures, however, the effective surface becomes very small and related to the properties of the top silicon film. This relation is not obvious, because the measured maximum capacitance should be independent of the film thickness and only related to the BOX characteristics (i.e., area and thickness).

In end, no clear scaling was observed leading to the idea that this effective surface is rather a measurement artefact (parasitic effects) than an actual meaningful parameter. In the next section we will present a better measurement setup that leads to proper characteristics with S eff /S = 1.

Silicon film/BOX

(nm/nm)

C OX •S (nF) C max_air (nF) S eff = C max_air /C BOX

III.2.2 Improved measurement setup

In case of static characteristics (see Sec. II.3.2), the quality of the back contact between the wafer and the metallic chuck plays a minor role. On the contrary, for the split-CV measurements, the quality of this contact, so called "back contact", plays a remarkable role. Figure III-7 shows the obtained capacitance (a)

and conductance (b) versus gate bias from SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. All measurements have been performed at f = 20 Hz, in order to avoid any impact due to frequency attenuation [START_REF] Diab | RC Model for Frequency Dependence of Split C-V Measurements on Bare SOI Wafers[END_REF]. The characteristics have been recorded using either special precautions for the back contact (i.e., vacuum contact) or without any precaution (i.e., air contact). Note that all the results present in the literature [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF], [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF] have been obtained using air back contact. The expected maximum capacitance (dashed line in Figure III-7a) represents the BOX capacitance and it is calculated by Eq. (III.1).

In case of vacuum back contact, the measured maximum capacitance (C max ) is very close to oxide one. On the contrary, without using any particular precaution on the back contact quality, the measured maximum capacitance (C max_air ) is much lower than C OX •S for both electrons and holes. The difference is due to parasitic effects that act as an added capacitance term placed in series with the BOX capacitance [START_REF] Castagné | Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements[END_REF]. Their impact is not removed by the open and short circuit corrections because they appear only in presence of the sample. The threshold and flat-band voltages, which are related to the static bias, are the same for both

Chapter III: Split-CV in Ψ-MOSFET 53
characteristics. This result was predictable since the quality of the back contact has no influence on the static

I D -V G curves.
For the conductance term (Figure III-7b), a perfect overlap is obtained before the channel formation.

However, the measurements performed using vacuum back contact show two sharp peaks after V T and V FB , followed by rapid conductance decrease after channel creation. For air contact, the peaks are smaller and the conductance does not decrease as rapidly. For V G higher than V T or V FB , there should be no current flow through the structure (i.e., low G m_split values). Thus, the characteristic obtained using vacuum back contact is closer to what is expected for standard MOSFET devices [START_REF] Schroder | Semiconductor material and device characterization[END_REF].

The next natural step is to check if the measured maximum capacitance using vacuum back contact scales with the real surface.

Effective surface versus real surface

Different die area samples were tested. Figure III-8 shows the results obtained using vacuum back contact. The SOI structure has 88 nm Si film and 145 nm BOX. All the characteristics present similar threshold and flat-band voltage. C max appears to be proportional to the oxide capacitance. In conclusion, the use of vacuum back contact allows the measurement of the capacitance associated to the whole die as for standard MOSFET devices. and without (empty symbols) using vacuum back contact. For comparison, effective carrier mobility reconstructed by Y function method (Eq. (III.9)) is also added (dashed lines). Remarkable agreement is found between the three curves for both types of carriers. Thus, even if the quality of the back contact could limit the measured maximum capacitance, using a fitting parameter, S eff , it is possible to extract realistic μ eff values. In conclusion, using split-CV technique for mobility investigation, the characteristic could be performed using air vacuum back contact, since S eff can lead to the correct μ eff . On the contrary, if one needs to perform reliable capacitance monitoring or to investigate the conductance term contribution, the use of vacuum back contact is required.

Effective mobility extraction

In the next sections, all the measurements performed in split-CV configuration have been obtained using vacuum back contact. This allowed tracing each time the capacitance (C m_split ) and conductance (G m_split ) curves normalized by the whole die area.

III.2.3 Robustness of the technique (probe effects)

In the case of static characterization, the control of the probe quality contact is the major parameter to achieve low access resistance and perform good characteristics suitable for parameter extractions (see Sec.

II.3.3)

. The probes position is also critical for f G [START_REF] Cristoloveanu | A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications[END_REF]. Are similar effects present also in case of split-CV technique? high pressure (80 g) were also added (dashed line). Using low probe pressures, μ eff is underestimated. For high enough probe pressure, the measured effective carrier mobility overlaps with the reconstructed values from Y function method. The physical explanation is given by Eq. (III.3): μ eff depends on capacitance measurements as well as on I D -V G characteristics. Even if the measured C GC is pressure independent, the drain current is still limited by the access resistance and consequently the obtained effective mobility is also pressure dependent.

Probes pressure

Probe position

In order to achieve the best measurement setup, the effect of probe position on the top silicon film has to be investigated Perfect overlap between the different characteristics was found for C m_split and G m_split . In case of split-CV, the probe placement on the die surface is not effecting the measurements.

In conclusion, we have seen that the access resistance (i.e., probe pressure) and border effects (i.e., probe position) have smaller impact on capacitance measurements than on current characteristics.

Number of probes

Finally, the role played by the number of probes (N probe ) was also investigated. Split-CV technique allows the use of more than one needle placed on top silicon film and connected to the low potential of the LCR meter. It was shown that S eff is dependent on N probe [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF]. In these sections we have discussed about the experimental setup of split-CV and shown how it could affect the measurements. In the next section we will investigate the impact due to frequency effects and point out the possibility to characterize the interface quality.

III.3 Frequency effects

Experimental evidences show clear frequency effects on the C-V characteristics (Figure III-14a).

Increasing f, the measured maximum capacitance becomes smaller than C OX . Figure III-14b presents the measured capacitance as a function of angular frequency (ω =2•π•f) in strong inversion regime for three different V G . Capacitance attenuation is found at high ω magnitude. Diab et al. [START_REF] Diab | RC Model for Frequency Dependence of Split C-V Measurements on Bare SOI Wafers[END_REF] have proposed a physical model based on RC electric circuit to explain the C m_split -V G curves in Ψ-MOSFET configuration. Even if it was initially developed only for C-V characteristics obtained with back air contact, we will discuss its validity also for measurements performed using vacuum back contact. It will be further enriched with the conductance term and the C-ω analysis will be performed. Its mathematical derivation will be also presented in the next section.

III.3.1 Model derivation

The

i Inv G Q C V    (III.10)
Finally, the channel resistance R CH represents the path required by one carrier to go from one probe to any point in the conduction channel. It is proportional to the sheet resistance (R SH ) and the number of probes placed on the top silicon surface N probe [START_REF] Diab | RC Model for Frequency Dependence of Split C-V Measurements on Bare SOI Wafers[END_REF]:

SH CH probe g probe g eff i R 1 R N f N f Q       (III.11)
Thus, the complete SOI equivalent impedance becomes:

EQ CH Inv OX Inv OX 1 ZR CC jS CC       (III.12)
where j is the complex unit. In case of air back contact, the model equations remain the same, except that S eff has to be used instead of S.

The LCR meter analyzer measures the SOI structure through a parallel equivalent circuit

C m_split -G m_split (Figure III-15b).
The obtained impedance has to be the same as Z EQ . Thus, the imaginary and real terms of the equivalent admittance (1/Z EQ ) allow writing C m_split and G m_split as a function of device parameters:

Inv OX Inv OX m _ split EQ 2 Inv OX CH Inv OX CC CC 1 C Im 1 / Z S CC 1 R S CC                  (III.13) 2 Inv OX CH Inv OX m _ split EQ 2 Inv OX CH Inv OX CC RS CC 1 G Re 1 / Z S CC 1 R S CC                       (III.14)
In order to validate the proposed model, experimental results will be systematically compared to calculated curves for different measurement configurations (see next section).

(a) (b)

R CH G pr C pr C OX G p C p R CH C Inv C OX R CH G pr C pr C OX C m_split R CH C Inv C OX G m_split

III.3.2 Model validation

Equations (III.13) and (III.14) are dependent of gate bias as well as of angular frequency. The complete validation of the physical model requires the comparison of measured and calculated characteristics as a function of V G (Sec. III.3.2.1) and of ω (Sec. III.3.2.2). Furthermore, the impact of N probe and of S will be addressed in Sec. III.3.2.3. The capability to characterize ultra-thin SOI structures will be shown in Sec. III.3.2.4. The calculated curves by Eq. (III.13) were also added (dashed line). Measurements have been performed on non-passivated SOI wafer using two probes on the silicon surface. Good agreement was found between the measured curves and the calculated ones. Small differences are present for high frequency in case of holes, probably due to higher access resistance. Note that no fitting parameters were used. For low frequency (i.e., f = 20 Hz) the measured capacitance at high V G is dominated by the oxide capacitance, since C Inv is much higher than C OX . Increasing the measurement frequency, the carriers have less time to go from the probes to the channel, so the measured capacitance decreases. The same behavior is also obtained in case of standard MOSFET devices [5].

III.3.2.1 C m_split and G m_split versus gate bias

III.3.2.2 C m_split and G m_split versus angular frequency

To further validate the frequency dependence, capacitance and conductance characteristics as function of ω for fixed V G were measured. from Eq. (III.14). Also in this case, typical RC shape is obtained and the modeled characteristics are in good agreement with the measured ones.

In the next section, the impact on the characteristics due to die area and number of probes will be addressed.  (rad/s) Another important parameter to take into account during split-CV characteristics is the number of probes placed on the top silicon surface. N probe determines the channel resistance R CH magnitude (see Eq.

V T =3.3V V G =3.6V V G =4V V G =4.5V Model V G

III.3.2.3 Effects of die area and number of probes

(III.11)). Thus, C m_split and G m_split will change proportionally to the number of probes. All the results discussed above have been obtained using two probes. versus ω obtained using one probe on the top silicon film. Measurements (empty symbols) and modeled results (lines) are compared. Also in this case a remarkable agreement was found. Finally, we will discuss about the possibility to characterize ultra-thin SOI structures.

III.3.2.4 Ultra-thin SOI structure

In the previous sections it has been shown that the RC model gives a realistic representation of split-CV characteristics, independently of the regime under analysis, the surface of the die and the number of probes used for the characterization. Here we want to extend split-CV technique to ultra-thin SOI structures.

III.3.3 D it signature

In the literature the capacitance and the conductance measurements are largely used for D it investigation [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]- [START_REF] Engel-Herbert | Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces[END_REF]. The results obtained in the previous section show that a RC model without any interface traps contribution can reproduce the measured characteristics in strong inversion and accumulation regime. This suggests that the D it are not "visible". We performed split-CV measurements with different top surface (after HF treatment, with native and passivation oxide). The aim is to see whether the surface state affects the curves.

Chapter III: Split-CV in Ψ-MOSFET 66

One possibility to induce a lot of dangling bonds on the top silicon surface is to perform HF treatment on the wafer [START_REF] Hovel | Si film electrical characterization in SOI substrates by the HgFET technique[END_REF]. The native oxide is etched and the surface becomes very reactive. In order to verify that the capacitance peak is related to HF treatment, the wafer was characterized at different moments after the cleaning procedure. In ambient condition, the native oxide grows back

III.3.3.1 RC model including D it contribution

Schroder [START_REF] Schroder | Semiconductor material and device characterization[END_REF] proposed to introduce the D it contribution in parallel to the inversion (or accumulation) capacitance (Figure III-25a). The traps are modeled by a capacitor (C Dit_c ) in series with a conductance (G Dit_c ) due to trap lossy process. In case of continuum level of interface traps, one gets [START_REF] Schroder | Semiconductor material and device characterization[END_REF]:

Dit _ c it C q D  (III.15)   2 2 it Dit Dit _ c Dit q D ln 1 G 2              (III.16)
where τ Dit is the trap effective lifetime [START_REF] Daanoune | Photo-pseudo-metal-oxide-semiconductor field effect transistor for characterization of surface recombination in silicon on insulator materials[END_REF]. The electrical equivalent circuit is typically rearranged in order to separate the capacitance and conductance contribution (Figure III-25b).

As done for the RC model derivation (Sec. III.3.1), the total equivalent impedance, including also D it contribution, has to be the same as the measurement equivalent impedance (Figure III-25c). Thus, it is possible to rewrite C m_split and G m_split as:

    22 OX p OX p OX m _ split 2 2 2 2 2 4 2 2 2 p p OX CH p p OX OX p CH C G C C C C G C C 1 R G 2 C C C C R                          (III.17)     2 2 2 2 OX p CH p CH p m _ split 2 2 2 2 2 4 2 2 2 p p OX CH p p OX OX p CH C C R G 1 R G G G C C 1 R G 2 C C C C R                                (III.18)
In the next sections, the analysis of C m_split -V (Sec. III.3.

III.3.3.2 C-V characteristics

To investigate the possibility of D it detection through C-V analysis, measurements performed on passivated and non-passivated samples are compared. It is well known that for passivated top surface the surface trap density is much lower than for non-passivated one [START_REF] Hamaide | Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization[END_REF]. Note that the two samples present similar top film-BOX interface quality.

III.3.3.3 Frequency characteristics in depletion regime

It has been already pointed out that the most sensible regime for D it detection is the depletion one [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]. In order to evidence the traps signature in the conductance term, the contribution of the channel resistance and the oxide capacitance are removed from the measured conductance. Reversing Eq. (III.18), G p is expressed as a function of C m_split and G m_split : The characteristics with and without D it always overlap and no signature due to interface traps is present. The effect due to R CH is very strong and masks any possible signature of interface traps even for large density.

  2 2 3 2 2 OX m _ split CH m _ split OX m CH p 2 2 2 2 2 m _ split OX m CH OX CH m _ split OX m C G 1 R G C C R G G C C R C R G C C                             (III.19)
In order to attempt to reveal the D it influence, the size of the die needs to be reduced. According to Eqs. (III.17 The pseudo-MOSFET technique is used for in situ characterization and it should be able to evidence D it signature of ≈ 10 10 -10 11 cm -2 eV -1 . In principle, this is possible using very small dies. Unfortunately, the pseudo-MOSFET characterization of small SOI samples with area in the order of 100 μm x 100 μm cannot be performed because the probe size is ≈ 40 μm.

III.4 Conclusions and perspectives

Diab et al. [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF] and Fernandez et al. In this chapter, a further investigation of the measurement setup has been performed. The quality of the contact between the wafer and the metallic chuck plays a major role. In order to avoid parasitic capacitances, the use of vacuum contact is mandatory. In this way the active area is the whole die area and the extraction of effective mobility becomes straightforward. It has been also proved the secondary role played by the quality of probe contact. Pressure, position and number of probes on the top silicon film do not limit the characteristics.

Moreover, Diab et al. [START_REF] Diab | RC Model for Frequency Dependence of Split C-V Measurements on Bare SOI Wafers[END_REF] have also presented a RC model to describe the frequency effects on C-V characteristics. During our work, the model validity has been validated using vacuum back contact and for different measurements:

C m_split -V G , G m_split -V G , C m_split -ω and G m_split /ω-ω.
In all the cases, a remarkable agreement has been found. The model was also tested on ultra-thin SOI structures and it can also predict the impact of different number of probes or die area.

The possibility to extract interface trap density has also been investigated. D it contribution was included in the RC model. Experimental and simulation results showed that neither C m_split -V nor G m_split -ω characteristics can help to interface quality evaluation. The analysis has pointed out that the detection limit is due to high τ RC magnitude. The use of smaller dies could make D it extraction possible in split-CV configuration, but this is difficult to achieve in a practical case, due to the probe dimensions.

There are two possible perspectives of this work:

Double G m_split /ω peak

The RC model predicts well the measured G m_split /ω curves before and after the channel formation.

Nevertheless, an interesting effect was obtained for higher gate bias (V G much higher than V T or much lower than V FB ). According to the RC model, after the channel formation the gate bias should only induce a peak shift towards higher angular frequency values, but not a height decrease. It is may be due to self-heating or substrate drop potential effects [START_REF] Kilchytska | Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs[END_REF]. In the previous chapter we have proved that D it detection cannot be achieved using standard LCR meters (split-CV). Nevertheless, the investigation of capacitance measurements for interface quality still remains an interesting goal. A reduced frequency could turn the CV into a successful method: this is the quasi-static CV.

Overcome RC model limitations

It

In this chapter, small signal quasi-static technique will be applied to pseudo-MOSFET for the characterization of bare SOI wafers. After the optimization of the measurement setup, a physical model will be presented to describe the characteristics. A procedure to extrapolate the interface trap density, based on experimental results is discussed. Several types of wafers (geometry, passivation) will be characterized and the nature of the obtained D it will be evidenced.

IV.1 Introduction: quasi-static CV in MOS structures

In MOS capacitors the detection of deep traps is difficult to achieve. Standard C-V analysis performed using LCR meter is limited by frequency effects [START_REF] Clayton | Apparatus to measure metal-oxide-silicon capacitance at very low frequencies[END_REF]. Small signal quasi-static capacitance (QSCV)

technique may overcome the problem [START_REF] Castagné | Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements[END_REF], [START_REF] Hauser | Bias sweep rate effects on quasi-static capacitance of MOS capacitors[END_REF]- [START_REF] Berglund | Surface states at steam-grown silicon-silicon dioxide interfaces[END_REF].

The measurement setup requires connecting the device substrate to low potential. The gate contact is linked to the high potential and it is polarized by static bias (V G ). A small linear a.c. ramp signal (ΔV ramp_ac ) is added to V G [START_REF] Clayton | Apparatus to measure metal-oxide-silicon capacitance at very low frequencies[END_REF]. [START_REF] Schroder | Semiconductor material and device characterization[END_REF]. The interface traps induce a shift between the two curves between accumulation and inversion regimes. The difference between the two capacitance terms (fast and slow) leads to D it estimation (high-low frequency method). This procedure is largely used for the characterization of interface traps density in case of standard MOS capacitors [START_REF] Schroder | Semiconductor material and device characterization[END_REF], [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF].

ΔV
QSCV also allows computing the surface potential, thus the corresponding D it energy in the silicon band gap. Performing the measurement at slow frequency (C LF_MOS ), the device is close to equilibrium condition and the whole channel response is obtained. Dividing C LF_MOS by C OX and integrating the results over V G , one obtains [START_REF] Castagné | Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements[END_REF], [START_REF] Kuhn | A quasi-static technique for MOS C-V and surface state measurements[END_REF], [START_REF] Berglund | Surface states at steam-grown silicon-silicon dioxide interfaces[END_REF]:

  G FB V LF _ MOS G S G G b OX V C (V ) V 1 dV C          (IV.1)
where Ψ b is the bulk potential deduced from the doping concentration. Note that Eq. (IV.1) is not valid in case of gross non-homogeneities present at silicon interface [START_REF] Kuhn | A quasi-static technique for MOS C-V and surface state measurements[END_REF].

Figure IV-1b shows the traps distribution as a function of energy measured on MOS in case of [START_REF] Marquez | In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique[END_REF] (A) and (100) (B) silicon crystal orientation [START_REF] Schroder | Semiconductor material and device characterization[END_REF]. Conductance method (squares) and QSCV technique (circles) were used. Obviously, the quasi-static measurement gives access to deep traps, close to the mid-gap, while the conductance technique is more sensitive to the edge of the band gap.

Besides its attractive features, the QSCV has also some drawbacks:

o It is only sensitive to charged defects [START_REF] Castagné | Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements[END_REF];

o The characteristic may be affected by potential fluctuations due to detrapping effects that lead to instability on the measurements [START_REF] Schroder | Semiconductor material and device characterization[END_REF]; o It is not adapted for D it located at the edges of the band gap [START_REF] Schroder | Semiconductor material and device characterization[END_REF].

QSCV in Ψ-MOSFET may become very interesting if it can lead to similar results concerning the interface quality of bare SOI wafers.

IV.2 Quasi-static capacitance in pseudo-MOSFET

The previous chapter demonstrated that the conductance method is not suitable in Ψ-MOSFET configuration but also suggested that D it characterization on bare SOI wafers could be achieved by low frequency measurements (corresponding to QSCV). In Sec. IV.2.1 we will show the setup of QSCV in Ψ-MOSFET. Sec. IV.2.2 compares measurements performed using quasi-static technique and LCR meter on the same SOI sample.

IV.2.1 Basics of QSCV for Ψ-MOSFET

The samples are probed by Jandel® station. The SOI wafer is placed on a metallic chuck. The substrate is connected to the high potential acting as a gate (similar to LRC meter setup). The low potential is applied on the top silicon film through one (or more) probe (Figure IV-2a). Small signal quasi-static measurements are performed using the Agilent B1500A® [START_REF] Berglund | Surface states at steam-grown silicon-silicon dioxide interfaces[END_REF].

A particular polarization is required to perform the analysis (see Figure IV-2b). Static gate bias V G is applied to the metallic chuck and the vertical current (I) between the high and the low potential is measured.

A small linear a.c. ramp bias is added to V G and a new I is measured at half ramp period. Integrating the current-time evolution leads to the charge and then to the capacitance value for a given V G .

Two important parameters define the a.c. signal: the bias amplitude ΔV ramp_ac and the time period over which it is applied (t m ). Thus, the a.c. scan speed is estimated by:

ramp _ ac ramp _ ac m V v t   (IV.2)
For simplicity reasons we have chosen to keep ΔV ramp_ac = 50 mV for all the characteristics. Hence, different v ramp_ac are obtained using different t m . Therefore, slow a.c. scan speed is given by long time ramp t m and it is equivalent to slow measurement frequency (f = 1/t m ). The static polarization (V G step and delay time) is kept constant when changing v ramp_ac on the same SOI structure.

QSCV

IV.2.2 Comparison with LCR meter measurements

Both split-CV and QSCV techniques lead to capacitance measurements. Thus, one expects that, even if the bias schemes are different (i.e., sinusoidal a.c. bias for LCR meter and linear a.c. ramp polarization for QSCV technique), similar characteristics should be obtained when using comparable frequencies. Figure IV-4 shows the measured capacitance versus gate bias in split-CV (plain symbols) and quasi-static (empty symbols) technique on the same die. Split-CV characterization has been performed using the slowest frequency available on the LCR meter (f = 20 Hz). The equivalent ramp speed can be roughly estimated considering the signal amplitude (δV G ) of the LCR meter and the period over which it is applied (1/f):

3 ramp _ ac G v f V 20 26 10 0.5V s         (IV.3)
This corresponds to a fast a.c. scan performed in QSCV (empty symbols). For the quasi-static experiment,

v

IV.3 Impact of measurement parameters

Before proceeding to any modeling and D it extraction, we need to find the appropriate QSCV experimental setup. Quality of the back contact and probe role will be discussed in Sec. IV.3.1 and Sec.

IV.3.2, respectively. Afterwards, the importance of scan direction will be clarified (Sec. IV.3.3).

IV.3.1 Impact of back contact quality

The quality of the back contact was critical in split-CV to avoid parasitic capacitances which were reducing C max values [START_REF] Pirro | Split-CV for pseudo-MOSFET characterization: Experimental setups and associated parameter extraction methods[END_REF]. Is this the case here for quasi-static CV?

Figure IV-5a shows the measured capacitance using fast a.c. scan speed (1 V/s) without (empty symbols) and with (plain symbols) vacuum. A parasitic capacitance appears in absence of vacuum. Thus, the obtained maximum value is much lower than C OX . On the contrary, when the vacuum was used on the back contact, C m_QST after channel formation is very close to the expected C OX value. Furthermore, V T differs, much more than in case of measurements performed using LCR meter.

Figure IV-5b shows QSCV characteristics in case of slow a.c. ramp speed (v ramp_ac = 10 mV/s). Curve overlap is obtained. v ramp_ac is very slow and the parasitic terms do not affect the results. This conclusion further validates the hypothesis that the use of vacuum system becomes mandatory only in case of rapid time dependent signals. In case of static polarization or for very slow V G variation close to equilibrium, the parasitic effects become negligible. Similar results have also been demonstrated for standard MOS capacitors [START_REF] Castagné | Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements[END_REF]; note that the vacuum contact was related to the silicon substrate and not to the gate.

Even if the curves measured using slow a.c. scan speed are almost independent of the back contact quality, all the characteristics of this chapter were performed using the vacuum system. This increases reproducibility and erases any doubt on possible parasitic capacitance effects.

IV.3.2 Impact of the probes

While performing static characteristics in pseudo-MOSFET configuration, the quality of the probe contact is a major parameter to achieve low access resistance and reliable parameter extraction (Sec. II.3.3).

In case of split-CV measurements, however, R SD had only a minor impact on the obtained characteristics (Sec. III.2.3). It is mandatory to verify the importance of R SD during QSCV characterization.

Pressure effects

Figure IV-6 shows the C m_QST versus V G in case of different probe pressures. Superposition is obtained, showing that, as for the split-CV, in quasi-static configuration the probe pressure plays a minor role [START_REF] Pirro | Split-CV for pseudo-MOSFET characterization: Experimental setups and associated parameter extraction methods[END_REF].

The "shoulders" representing the D it are therefore pressure independent. This indicates that D it extracted in QSCV are not due to only defects induced by probe penetration. Furthermore, good QSCV characteristics can be obtained without particular precautions on the pressure value. Consequently, even very low pressures lead to accurate capacitance curves which is not the case for I D -V G . This fact makes the QSCV more adapted for ultra-thin films than the current measurements. Results on the ultra-thin films and BOX will be discussed in Sec. IV.8.

Different probe quality and number

Figure IV-7a shows the measured QSCV capacitance versus gate bias obtained using two different needles on the silicon surface with the same pressure: probe A (plain symbols) and probe B (empty symbols). The curves superposition confirms that the obtained "shoulders" are independent of the top contact quality.

The number of probes placed on the top silicon film changed the frequency response of the SOI structure in split-CV. The higher the measurement frequency, the stronger the impact on the characteristics (Sec. III.3). On the contrary, in quasi-static configuration, f is sufficiently low and no frequency attenuation is expected. This is confirmed by the measurements in

IV.3.3 Impact of scan direction

In standard MOS capacitor the scan direction is a major parameter for interface characterization [START_REF] Dimitrijev | Slow-trap profiling of NO and N2O nitrided oxides grown on Si and SiC substrates[END_REF].

Starting the measurement from accumulation or strong inversion regime leads to different information [START_REF] Hauser | Bias sweep rate effects on quasi-static capacitance of MOS capacitors[END_REF].

When performing the sweep from accumulation regime, the device may enter the out-of-equilibrium deep depletion regime instead of the inversion regime. Alternatively, a scan started from strong inversion regime makes D it investigation more fruitful, since more defects will be charged. 145 nm BOX thickness and non-passivated surface). The characteristic started from strong inversion regime (empty symbols) shows two "shoulders" when the conduction channel is not yet created. On the contrary, the measurement performed from negative gate bias (plain symbols) presents no D it signature. Before threshold voltage, the curve started from V G < 0 V becomes very noisy, probably because of the lack of carriers [5].

The potential is pinned above V T and just after it the capacitance jumps directly to C OX . This explains the presence of capacitance values higher than C OX which are not physical [START_REF] Shenoy | Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface[END_REF]. Clear hysteresis is also found between the two characteristics probably due to the effects of surface defects or mobile charge [6], [START_REF] Marquez | In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique[END_REF].

In conclusion, measurements started from strong inversion regime represent the more favorable condition to evidence D it signature. All the characteristics shown in this chapter were obtained starting from strong inversion regime (V G > 0 V). IV.4.2). For simplicity reasons, all the analyses in this section were performed on SOI structure with 88 nm thick top silicon film and 145 nm thick BOX. The top surface was passivated.

IV.4.1 Model derivation

The derivation will be divided in three sections. Initially the equations will be presented for a single energy level of interface traps. The model will then be extended to the continuum-like energy distribution of defects and finally the frequency effects will be included.

The experimental quasi-static capacitance will be labeled as C m_QST and the computed one as C QST .

Single energy level of interface traps

The measured peaks obtained before channel formation can be modeled deriving the whole C QST expression. The total density of charges induced by the gate bias (Q ch ) is distributed between the free charges present in the channel Q i and the charges trapped in the defects (Q itrap ) [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]:

ch i itrap Q Q Q  (IV.4)
For a single traps energy level, the filled charges at the interface are given by:

itrap itrap _ s it _ s T Q Q q D f     (IV.5)
where f T is the probability that the traps are charged. D it_s is the density of defects for a single energy level expressed in cm -2 and associated to a precise value of surface potential (Ψ S ), thus to V G .

The derivation of the total charge with respect to the gate bias leads to the QSCV capacitance for a single energy level of D it (C QST_s ):

itrap _ s ch i QST _ s G G G Q Q Q C V V V          (IV.6)
Charge calculations are usually performed as a function of Ψ S . Hence, it is possible to re-write Eq. (IV.6) as:

itrap _ s SS i QST _ s S G S G Q Q C VV             (IV.7)
To make the derivation easier to follow, the two terms will be discussed separately and the final capacitance will be shown at the end.

In standard MOS capacitor, Q i is proportional to exp(β•Ψ S ), where β = q/(k•T) [5]. Thus, the first term present in Eq. (IV.7) becomes:

SS i i S G G Q Q VV            (IV.8)
The derivative of the trapped charges with respect to the surface potential leads to the capacitance associated to a single energy level of

D it : itrap _ s it _ s S Q C    (IV.9)
In order to complete the derivation of C QST_s , the expression of the surface potential with respect to the gate bias is required. V G is distributed between Ψ S , the flat-band voltage and the potential drop due to the inversion charges and Q itrap_s [5]. Ψ S is written as:

i itrap _ s S G FB OX QQ VV C      (IV.10)
Deriving Eq. (IV.10) with respect to V G one obtains:

itrap _ s itrap _ s S S S ii G OX G OX G OX S G OX S G QQ QQ 1 1 1 1 11 V C V C V C V C V                         (IV.11)
Using Eqs. (IV.8) and (IV.9), the derivative of the surface potential with respect to the gate bias becomes:

S OX G OX i it _ s C V C Q C        (IV.12)
Thus, the total channel capacitance with a single energy level of interface traps is (Eq. (IV.6)):

  OX i it _ s QST _ s OX i it _ s C Q C C C Q C          (IV.13)
QSCV technique is only sensitive to the charged defects, so the filling probability needs to be included in C it_s . The probability that electrons (or holes) are trapped by D it can be derived using Shockley-Read-Hall approach [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF], [START_REF] Hall | Recombination processes in semiconductors[END_REF]. It is usually expressed as a function of the electron density present in the channel (n S ), which is proportional to exp(β•Ψ S ), as Q i . Hence, it is possible to perform the derivation using the inversion (or accumulation) charge density instead of n S . In case of small signal variation, the probability f T that the traps are charged is given by the balance between the free charges present in the conduction channel filling the traps Q i •(1-f T ) and the filled defects discharging towards the channel Q itrap_s •f T [START_REF] Masson | An improved time domain analysis of the charge pumping current[END_REF]:

T i T itrap _ s T f Q (1 f ) Q f t q q           (IV.14)
where ϑ is given by the product between the traps cross section σ T and the frequency f s at which the electrons oscillate between the conduction channel and the traps [START_REF] Shockley | Statistics of the recombinations of holes and electrons[END_REF]:

Ts f     (IV.15)
In case of steady-state condition (δf T /δt = 0), f T becomes:

i T i itrap _ s Q f QQ   (IV.16)
Thus, the capacitance associated to a single energy level of traps is:

  itrap _ s T it _ s it _ s it _ s i 2 S i itrap _ s Q f C q D q D Q QQ            (IV.17)
In the next section, the model will be extended to the continuum-like energy distribution of traps in the silicon band gap case.

Continuum-like energy distribution of D it

In case of a single energy level of interface traps, the defects are located only at one precise value of gate bias (i.e., surface potential). As shown also from the QSCV preliminary results (Figure IV-1b and Figure IV-3), D it energy is more homogenously distributed in the silicon band gap instead of a peak at a certain value [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF]. In order to emulate this effect from the mathematical point of view, a sum of several C it_s in the silicon band gap will lead to the continuum-like D it capacitance [START_REF] Balland | Investigation of deep levels in high-resistivity bulk materials by photo-induced current transient spectroscopy. II. Evaluation of various signal processing methods[END_REF]. This corresponds to an integral in the silicon band gap. Since we control the Fermi level in the silicon film with V G (back gate bias), the integral is performed as a function of bias between V FB and a certain value smaller than V T :

  GG FB FB VV itrap _ s it _ c G it _ s it i G 2 VV i G itrap _ s Q (x) C (V ) C (x)dx q D Q (V ) dx Q (V ) Q (x)          (IV.18)
Since we are considering a continuum-like energy distribution of traps, D it is expressed in cm -2 eV -1 . C it_c is the defects capacitance term which replaces C it_s in Eq. (IV.13). Thus, the quasi-static channel capacitance Eq. (IV.13) and 10 11 cm -2 eV -1 for Eq. (IV. [START_REF] Fenouillet-Beranger | Efficient multi-VT FDSOI technology with UTBOX for low power circuit design[END_REF]). As for the experimental results, the calculated curves superpose after channel formation. In case of single energy level of defects, a sharp peak is obtained in absence of conduction channel. For this calculation, the defects were placed at V G = 0 V. Using a continuumlike energy distribution of interface traps density (point-dash line), a "plateau", similar to the experimental results (see Figure IV-3), is obtained. Even if the traps magnitude was similar for the single energy level and the continuum-like energy case, the height of the "plateau" is much lower than the sharp peak. The same trends were also obtained for standard MOS capacitors [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF].

(C QST_c ) is as a function of C OX , β•Q i and C it_c :   OX i it _ c QST _ c OX i it _ c C Q C C C Q C          (IV.19)
To complete the derivation, frequency effects have to be also included in C QST .

Frequency effects

In time, the defects can be filled by free carriers present in the conduction channel or they can discharge. Thus, it is important to include the traps time constant τ Dit in the capacitance term. For a given value of surface potential, τ Dit is related to the density of filled D it (n it ) and the density of free charges present in the channel (n S ) [START_REF] Macdonald | Validity of simplified Shockley-Read-Hall statistics for modeling carrier lifetimes in crystalline silicon[END_REF]. As for a MOS capacitor, τ Dit can be written as [START_REF] Nicollian | MOS (metal oxide semiconductor) physics and technology[END_REF], [START_REF] Heiman | The effects of oxide traps on the MOS capacitance[END_REF]:

Dit T th S T th it 1 v n v n         (IV.20)
where v th is the thermal velocity. The carrier cross section σ T was kept the same for filling and discharging processes. Note that before channel formation n S = n i and it is much lower than n it . Thus, all the free carriers are trapped by the defects.

The capacitance contribution due to interface traps containing the defects time constant contribution becomes [START_REF] Schroder | Semiconductor material and device characterization[END_REF], [START_REF] Nicollian | The Si-SiO2 Interface -Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique[END_REF]:

it _ c it _ c _ 22 Dit C C 1       (IV.21)
In order to include the filling/discharging traps effects, Eq. (IV.21) must be used in the computation of

C QST : it _ c OX i 22 Dit QST _ c _ it _ c OX i 22 Dit C CQ 1 C C CQ 1                      (IV.22)

Extension to split-CV

In the split-CV chapter, it was demonstrated that the free carriers need time to go from the probes to a certain point of the channel (τ RC ) (Sec. III.3.1). Thus, one needs to include also τ RC effects in order to have a full capacitance expression:

  it _ c OX i 22 Dit QST _ LCR 2 it _ c RC OX i 22 Dit C CQ 1 1 C C 1 CQ 1                        (IV.23)
As explained in the split-CV chapter, only traps with τ Dit > τ RC can be detected. Note that in quasistatic configuration, even the characteristics measured with "fast" a.c. ramp speed are actually equivalent to "slow" analysis performed using LCR meter, where τ RC had no impact. Consequently, in QSCV, thanks to its slow equivalent frequency, τ RC can be safely neglected and Eq. (IV.22) will be sufficient for modeling the measured capacitance. This model will be validated in the next section.

IV.4.2 Model validation

In this section, the derived equations will be constantly compared to experimental results in order to confirm the robustness of our model. Note that the aim of this part is not to perfectly fit the curves, but to verify the trends. Frequency effects and characteristics performed at different temperatures will be investigated. Equation (IV.22) is used to compute the total capacitance. Q i is calculated using Lambert equation [START_REF] Tsormpatzoglou | A compact drain current model of short-channel cylindrical gate-all-around MOSFETs[END_REF]. C OX is obtained from experimental capacitance measured in strong inversion (or accumulation) regime. D it was equal to 10 11 cm -2 eV -1 , which is a typical order of magnitude for these types of samples [START_REF] Rodriguez | Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX[END_REF],

[62], [START_REF] Hamaide | Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization[END_REF].

Frequency effects

As discussed in the introduction, fast a.c. ramp scan (v ramp_ac = 1 V/s) hides the traps contribution while v ramp_ac = 10 mV/s reveals them.

ramp time t m (labeled C m_QST_Vg ).

At constant V G , the filling (or discharging) D it kinetics should have an exponential dependency as a function of a.c. ramp time t m [START_REF] Heiman | The effects of oxide traps on the MOS capacitance[END_REF], [START_REF] Vuillaume | Oxide traps in Si-SiO2 structures characterized by tunnel emission with deep-level transient spectroscopy[END_REF]:

m Dit t m _ QST _ Vg m _ QST _ sat C C 1 e         (IV.24)
where C m_QST_sat is the quasi-static saturation capacitance, when the whole density of traps responds to the applied signal. In order to verify if this relation is also valid in our case, we extracted the measured C m_QST for some fixed V G (-0.5 V, -0.3 V, -0.1 V, 0.2 V and 0.4 V) from region not all D it are charged. Thus, partially traps detection is obtained. The time scaling is in the order of seconds, which are typical values for deep traps time constants [START_REF] Dimitrijev | Slow-trap profiling of NO and N2O nitrided oxides grown on Si and SiC substrates[END_REF], [START_REF] Vuillaume | Oxide traps in Si-SiO2 structures characterized by tunnel emission with deep-level transient spectroscopy[END_REF], [START_REF] Masson | Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point-of-view[END_REF]. In conclusion, however, general agreement was found between experimental and calculated results.

In the next section, we discuss the temperature dependency.

Temperature dependency

In order to further validate the physical model, quasi-static measurements were performed at low temperature (T). Figure IV-13a clarifies the mechanism: C m_QST was measured versus V G using the same v ramp_ac = 10 mV/s and different temperatures. Typical V T shift as a function of T is observed [START_REF] Diab | Low-temperature pseudometal-oxide-semiconductor field-effect transistor measurements on bare silicon-on-insulator wafers[END_REF]. The signature due to interface traps is stronger in case of higher temperatures.

In our model the temperature effects are present in the following terms:

o β(T) = q/k•T;
o Q i (T): the inversion charge density Q i in Eq. (IV.22) is calculated using Lambert equation [START_REF] Tsormpatzoglou | A compact drain current model of short-channel cylindrical gate-all-around MOSFETs[END_REF], which contains β(T) and V T (T). The variation of threshold voltage with respect to the temperature is determined by β(T) and the intrinsic carrier concentration n i (T) [5], [START_REF] Diab | Low-temperature pseudometal-oxide-semiconductor field-effect transistor measurements on bare silicon-on-insulator wafers[END_REF]:

G E 3 2 k T/q i C V T n (T) N N exp 300          (IV.25)
where N C and N V are the effective state density at T = 300 K in conduction and valence band, respectively.

o The traps cross sections σ T (T) present in τ Dit (see Eq. (IV.20)) is assumed constant, since the minimum temperature used is still too high for ionization effects to occur [5].

In order to check if the derived model can explain the temperature dependency,

IV.5 D it extraction procedure

After the validation of our model for the quasi-static capacitance, here we propose a procedure to D it extraction. Limitations and possible improvements will be also pointed out.

Physical approach

In the previous sections it was proved that the measured quasi-static capacitance behavior is well predicted by Eq. (IV.22) where the defects capacitance contribution was calculated using Eq. (IV.18). In a practical case the traps are continuously distributed in energy in the silicon band gap and the associated capacitance can be written as [START_REF] Schroder | Semiconductor material and device characterization[END_REF]:

it _ QST it C q D  (IV.

Robustness of the extraction procedure

Figure IV-14a shows the D it profile as a function of V G obtained using our approach (plain symbols)

and the high-low frequency method (empty symbols) [START_REF] Schroder | Semiconductor material and device characterization[END_REF], [START_REF] Nicollian | The Si-SiO2 Interface -Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique[END_REF] in which no assumption concerning β•Q i is performed. The data presented in Figure IV-3 was used. Two measured capacitance curves are required for the high-low f technique: one at high frequency where the traps do not have time to respond (e.g., 1 V/s), and a second one at a much lower a.c. scan speed (e.g., 10 mV/s). Remarkable agreement is found between the two extraction procedures. This result confirms the validity of our approach, which is preferable to the standard high-low frequency because it only requires one QSCV characteristic. In order to confirm the assumption of negligible β•Q i term, the dashed line in Figure IV-14b shows the equivalent free carrier density expressed in cm -2 eV -1 . β•Q i /q was calculated using Lambert equation [START_REF] Tsormpatzoglou | A compact drain current model of short-channel cylindrical gate-all-around MOSFETs[END_REF]. Its

Frequency effects on extracted D it (exponential fit procedure)

In order to analyze the impact of the neglecting τ Dit , Figure IV-15a shows the interface trap density as a function of V G for different v ramp_ac . The characteristics from Figure IV-10a were used. For a given value of V G , curve superposition is obtained below a certain frequency at which all the defects respond. Hence, τ Dit effect is really negligible. This condition is fulfilled for high gate bias magnitude. On the contrary, far from V T and V FB (e.g., V G ≈ 0 V), the traps are more difficult to detect because their associated τ Dit are too large to be neglected.

IV.6 Characterization of non-passivated samples

The previous section focused on the characterization of passivated samples with 4 nm dry oxide on the top silicon layer. To further investigate the technique capabilities, it is important to characterize nonpassivated SOI wafers (different top interface quality with respect to the passivated ones). This will allow evaluating the sensitivity of QSCV and understanding to which interface the technique is more sensitive (BOX-top silicon film or top silicon film-native oxide).

Which of these measurements should be used for D it extraction?

A procedure is needed to obtain stable curves that could permit a reliable material investigation. The physical origin behind this phenomenon needs to be understood.

IV.6.1 Traps charging procedure

Thick silicon film

Figure shows that the starting point mostly affects C peak while the right part of the characteristic slightly shifts. In this section we will focus our attention on this measured peak labeled C peak .

The dependency with the initial gate bias let us think that a possible stress during the characterization induces new defects in the oxide. To deeper investigate this phenomenon, a standard stress procedure was performed and the capacitance versus time evolution was monitored as in MOSFETs [START_REF] Jahinuzzaman | Threshold voltage instability of amorphous silicon thin-film transistors under constant current stress[END_REF], [START_REF] Powell | Time and temperature dependence of instability mechanisms in amorphous silicon thin-film transistors[END_REF]. The investigated sample had 88 nm thick silicon film and 145 nm thick BOX. One probe was placed on the silicon surface and connected to ground. V G stress (labeled "charging bias" V G_charge ) was applied to the SOI substrate for a certain time ("charging time" t s ), and afterwards a QSCV measurement using slow a.c. scan speed was immediately performed. Chapter IV: QSCV in Ψ-MOSFET 96 One possibility to verify if the procedure is degrading the oxide (stress) or not (charging), consists of the characterization of the sample before and after applying the charging bias (Figure . The SOI structure has been initially characterized using v ramp_ac = 10 mV/s (line). Then, V G_charge = 10 V was set for 3000 s and the quasi-static capacitance was measured again (plain symbols). C peak increases, while around V FB and V T the curves superpose. A stress procedure generates new charges in the oxide which should result in a clear shift of V T and V FB [START_REF] Heremans | Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation[END_REF]. Our result suggests the presence of charging effects rather than permanent damage (stress).

Additionally, a third measurement was performed on the same structure 6 hours after the end of the second measurement (empty symbols). The characteristic superposes with the initial one. This confirms that the procedure does not induce new defects but only charges the already present D it . Supported by the results of Figure IV-17, it is reasonable to assume that the defects filled during the procedure are located on top of the silicon surface (confirmed also in Sec. IV.8). If the applied charging bias only fills defects that are already present on the SOI wafer, the measured capacitance should be independent of the applied voltage. On the contrary, if V G_charge is inducing new traps, the use of larger values should lead to stronger C peak .

Three different V G_charge were applied for different t s on a non-passivated SOI structure: 10 V, 20 V, and 30 V. A quasi-static capacitance measurement was performed after each bias condition. C peak and the corresponding bias position (V G_peak ) were identified for each characteristic.

Ultra-thin silicon film

In order to test the validity of the charging procedure on ultra-thin films, SOI structure with 12 nm top silicon film thickness, 145 nm BOX thickness and non-passivated surface was investigated. Figure shows the measured quasi-static capacitance using slow a.c. scan speed for different t s . The charging bias was 10 V. In case of V G > 0 V, the risen "shoulder" is almost constant. On the contrary, C peak increases proportionally to the charging time, as for thick silicon film. Chapter IV: QSCV in Ψ-MOSFET 98 Similar analysis as for thick SOI structure was performed in case of ultra-thin Si layer. Different charging biases were consecutively applied on the same die for different t s : 5 V, 10 V and 15 V. C m_QST was measured and C peak and V G_peak were identified for each characteristic. Figure IV-21a shows the obtained peak magnitude as a function of t s . A larger charging bias induces higher peak. In case of V G_charge = 15 V, the measured value saturates at C OX (238 μF/m 2 ). Figure IV-21b presents V G_peak as a function of t s . The bias value associated to C peak saturates for V G_charge = 5 V and 10 V but no clear overlap is obtained. On the contrary, the characteristic measured after 15 V charging bias constantly increases. This is typical for stress procedure during which new defects are created [START_REF] Marquez | In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique[END_REF].

In conclusion, in case of ultra-thin film, separating the charging and defects generation effects is challenging. However, this is not a limitation for traps investigation because in case of t Si = 12 nm the coupling with the conduction channel is stronger. Thus, the defects become more accessible even without charging them (see Sec. IV.8).

IV.6.2 Example of D it extraction for non-passivated samples

The interface traps profile for non-passivated samples can be extracted following the procedure proposed in Sec. IV.5. However, it is important to evaluate the effects of the charging bias on the obtained

D it .

D it obtained after charging the defects

Comparison of D it extracted from passivated and non-passivated samples

The charging procedure gives us useful information about the characterization setup required for nonpassivated samples. The next natural step is the comparison of the obtained traps profile in case of different interface qualities. Figure IV-25 presents the extracted D it versus gate bias for passivated (empty symbols) and non-passivated (plain symbols) SOI structures. Measurements were performed using v ramp_ac = 3 mV/s and no charging procedure was applied. Despite the large difference in traps density, a detailed comparison is not possible because the different interface quality induces V T and V FB shifts. For comparative analysis, the characteristics must be traced versus surface potential (or energy). This aspect will be investigated in the next section.

IV.7 Surface potential computation

MOS-like surface potential computation and its limitation for Ψ-MOSFET

Equation (IV.1) is used for Ψ S calculation in case of standard MOS capacitor [START_REF] Uren | Conductance measurements on Pb centers at the (111) Si:SiO2 interface[END_REF]- [START_REF] O'sullivan | Si(100)-SiO2 interface properties following rapid thermal processing[END_REF]. Thus, it should be also suitable for the pseudo-MOSFET configuration. Three steps are required to determine the surface potential:

1 Perform one capacitance measurement C m_QST at slow a.c. ramp speed;

2 Calculate δΨ S /δV G term: Poisson equation leads to the computation of the potential distribution over the whole structure. Thus, the variation of the surface potential with respect to the gate bias can be determined (δΨ S /δV G ). These problems may explain why Ψ S calculated using Eq. (IV.1) is overestimated. One of the main assumptions of Eq. (IV.1) is that the semiconductor is at equilibrium condition and all the charges (i.e., free carriers and defects) respond during the measurements. This is obviously not the case in all the experimental v ramp_ac .

m _ QST S G OX C 1 VC    (IV.28) 3 Integrate δΨ S /δV G between V FB and V G , where V G < V T.

Computation of surface potential

Since it is not possible to obtain Ψ S directly from experimental results, a mix between measurements and calculation was proposed to overcome the limitations. It is based on the following steps:

1 QSCV measurement is performed using the slowest v ramp_ac (3 mV/s in our case). Note that the surface potential is directly proportional to the traps energy level in the silicon band gap (E). The 0 of the energy will be placed at the maximum of the valence band (E V ). Hence, the energy in eV can replace V G , thus Ψ S , on the D it profile curves.

In the next sections, all the surface potential values, thus the energy E-E V , were computed using this procedure. This approach will give the defects location in the silicon band gap. The extracted D it magnitude is not affected by Ψ S and E-E V calculation. Only an error in their effective energy level could eventually result from Ψ S miscalculation.

IV.8 Comparison of D it profiles for different samples

In this last part of the chapter, we focus on the characterization of SOI structures with different interface qualities and geometries. In order to perform suitable comparisons, all the extractions were performed using v ramp_ac = 3 mV/s. No charging procedure is necessary at such low a.c. ramp speed and tested ultra-thin t Si . Ψ S was calculated using our approach (mix of experimental and calculated results) and the D it profile will be traced versus energy. magnitude (> 10 12 cm -2 eV -1 ) was measured [START_REF] Hurley | Examination of the Si(111)-SiO2, Si(110)-SiO2, and Si(100)-SiO2 Interfacial Properties Following Rapid Thermal Annealing[END_REF], [START_REF] Poindexter | MOS interface states: overview and physicochemical perspective[END_REF]. Furthermore, the energy position of the obtained peaks suggests the presence of acceptor-type defects (+/0) [START_REF] Grenouillet | UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below[END_REF]. shows the calculated interface time constants versus energy in case of passivated (empty symbols) and nonpassivated (plain symbols) SOI structure (t Si = 88 nm). The non-passivated curves have much higher τ Dit .

Thick BOX

Thus, the traps are more difficult to detect. As a result, almost full D it response is obtained on passivated wafers while it is only partial in case of non-passivated ones, explaining the defects underestimation.

UTBB structure

QSCV technique does not require high probe pressure to achieve good characterization (Sec. IV.3.2).

This makes the procedure suitable for the characterization of UTBB structures.

Impact of BOX thickness

We compare wafers fabricated at the same period and with similar processes but different BOX thickness.

IV.9 Conclusions and perspectives

In this chapter, quasi-static capacitance measurements were performed for the first time in pseudo-MOSFET configuration.

We showed that the QSCV measurements are like an "extension" of the LCR meter (split-CV) case to lower frequencies (even though the measurement principles are not the same). The back side contact of Ψ-MOSFET is very important for fast a.c. ramp speeds, similar to the split-CV. The probes effect, however, is not very strong implying that the access resistance is only a minor parameter. Consequently, QSCV on ultra-thin silicon films using very low probe pressure is feasible while the same pressure for I D -V G does not give appropriate results because too large access resistance.

A physical model capable to explain the measured characteristics, including frequency and temperature effects, was proposed and validated.

One limitation of QSCV technique is that it can only detect traps that are already filled or that can be charged during the scan. If the defects are at too deep energy levels in the silicon band gap and if the measurement is not slow enough, some defects cannot be detected. To overcome the problem, however, it is possible to fill the traps before the detection (charging procedure).

A D it extraction procedure was proposed. The comparison between different SOI structures and interface properties evidenced that in passivated samples we characterize mostly the top silicon film-BOX interface. We proved that for non-passivated surface, larger densities of defects are measured. A sharp D it peak associated to P b center was evidenced. In all the studied cases, D it profile was mostly independent of t Si and t OX .

QSCV stands as a promising technique for the monitoring of interface quality performed with Ψ-MOSFET. Future developments could be:

o The effective mobility can be also calculated using quasi-static analysis. The measurement of inversion (or accumulation) charge density can be computed with the same approach presented in the split-CV chapter (Sec. III.1.2). The obtained effective mobility will coincide with the one measured using LCR meter. Thus, performing one QSCV characteristic, interface traps density can be studied.

Measuring also the drain current on the same device will lead to μ eff .

o The role of substrate capacitance has to be investigated and in case of strong impact on the characteristics, it must be taken into account in the equivalent electric circuit.

o Improvement of Ψ S extraction, if possible only based on experiments.

o Further investigation of UTBB structures and the impact of charging procedure in case of nonpassivated top silicon film.

o Application to new materials as III-V. In case of QSCV the quality of the top contact is much less relevant than for current measurements. Thus, QSCV could become a suitable technique to investigate the interface quality, even for alternative film materials that are normally difficult to contact.

V.1 Introduction to low-frequency noise

The subthreshold swing is a powerful technique for the characterization of interface traps density [6].

However, the decreasing of the top silicon film thickness t Si and the subsequent increase of the associated capacitance may mask the defects signature, making interface quality monitoring problematic. Furthermore, the defects that respond during static characterization are identified as fast traps (D it ) while slow traps (N t ) are partially (or not) detected. Low-Frequency Noise (LFN) offers the opportunity to overcome these limitations and to pursue defects characterization even in case of ultra-thin silicon film.

The word "noise" is largely used in microelectronics and it can be associated to different domains.

Generally, it indicates random fluctuations of a physical characteristic around its average value during time.

Noise is usually something to avoid because it affects the experimental results, and it is also difficult to control. A good example is the "background" noise. Considering an integrated circuit, one area can distort the output signal of another one because of coupling effects. This modifies the signal integrity and limits the circuit performances [START_REF] Nemirovsky | 1/f noise in CMOS transistors for analog applications[END_REF], [START_REF] Brederlow | Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuits[END_REF].

Looking at one single resistor under constant polarization, the current (or voltage) magnitude is not really constant but fluctuates around an average value. II.2). Consequently, the fluctuations are masked and stable results are obtained.

However, the investigation of noise sources could enrich the knowledge about the transistor quality.

Signal fluctuations can be classified into two families according to their origin: they can be due to "external" factors, thus not related to the device properties, or due to "internal" characteristics of the structure. External sources of noise cannot bring any fruitful information concerning the device quality; they just limit the analysis. Noise due to internal factors can also limit I D -V G or quasi-static capacitance techniques, but in case of low-frequency noise measurements, they can be used to extrapolate information concerning the interfaces quality [START_REF] Simoen | Low-frequency noise in silicon-oninsulator devices and technologies[END_REF].

LFN has been widely applied for the characterization of FD-SOI transistors [START_REF] Ghibaudo | Low-frequency noise and fluctuations in advanced CMOS devices[END_REF]- [START_REF] Bennamane | DC and low frequency noise characterization of FinFET devices[END_REF]. It was also used to characterize high resistive SOI wafers with evaporated metal contacts [START_REF] Kushner | SOI Low Frequency Noise and Interface Trap Density Measurements with the Pseudo MOSFET[END_REF], [START_REF] Kushner | Low-Frequency-Noise Spectroscopy of SIMOX and Bonded SOI Wafers[END_REF]. However, the presence of Schottky barriers made the extraction long and complicated. Diab et al. performed first LFN characterization on SOI substrates using pseudo-MOSFET but the obtained D it were not coherent with the expected quality of the fabrication process (> 10 13 cm -2 eV -1 instead of < 10 12 cm -2 eV -1 ) [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF].

After a review of the basic theory of low-frequency noise (Sec. V.1.1 and Sec. V.1.2), we will focus on the pseudo-MOSFET configuration (Sec. V.1.3). In Sec. V.2 results obtained using different experimental conditions will be presented. A physical model supported by numerical calculations will be discussed in Sec.

V.3 and compared with the measured trends (Sec. V.4). In conclusion, Sec. V.5 addresses the impact of defects induced by the probe penetration in the silicon film. In case of LFN characterization, the Power Spectral Density (PSD) of a signal becomes the main parameter. It quantifies the dissipated power on a 1Ω resistive load integrated in time and its unit is W/Hz. For any function R(t) expressed in the time domain, its PSD is computed suing the Fourier transform:

2 j f t S(f ) R(t) e dt         (V.2)
For LFN analysis on MOSFETs, the PSD is measured either for current or voltage characteristics. Thus, S(f) can be associated to the current oscillations (S Id ) or to the voltage ones (S Vd ). The units are A 2 /Hz and V 2 /Hz, respectively. In a practical case, the S Id is computed using the Fast-Fourier Transform (FFT) of the measured signal.

The noise is a statistical phenomenon and in order to perform suitable transformation from time to frequency domain, it is required to measure many samples of the signal. Thus, LFN measurements are longer than the static ones.

Next section shows a brief overview of the main internal sources of noise detected in MOS transistors.

V.1.2 LFN in MOSFETs

The "internal" noise sources in a MOSFET can be classified in two main families:

o White noise: it is a fundamental noise intrinsic to semiconductor materials and it is frequency independent. Thermal and shot noise are part of this group.

o Excess noise: it is frequency dependent and it is mostly visible at low frequency. The main contributions arise from generation-recombination (G-R) and 1/f (flicker) noise.

Thermal noise

Thermal noise is due to random and uncorrelated thermal fluctuations in the material. Consequently, the power spectrum is frequency independent for any applied voltage or current [START_REF] Hida | White Noise: An Infinite Dimensional Calculus[END_REF]. Hence, it is classified as white noise. Note that in all the conductive materials, even in absence of applied bias or current, the room temperature induces electron oscillations which lead to continuous current fluctuations. Consequently, every resistor generates thermal noise. The associated current power spectrum is:

Id 4 k T S R   (V.3)
where R is the resistance value.

Shot noise

The shot noise is due to non-uniformity of the current flow through a junction. The electrons cross it independently and at random times [START_REF] Terrell | Shot-Noise Character of Cygnus X-1 Pulsations[END_REF]. The carrier flow leads to broadband white noise. Its power spectrum is proportional to I:

Id S 2 q I    (V.4)

Generation-recombination (G-R) noise

Generation-recombination (G-R) noise is due to random fluctuations induced by: o A pair of free electron and hole which recombines (or is generated);

o Trapping of electrons by empty defects;

o Trapping of holes by discharging traps filled with electrons.

The PSD associated to the G-R noise due to carrier number (N) fluctuations induced by their interaction with traps (empty and filled) is [START_REF] Hooge | 1/f noise sources[END_REF]:

2 Dit Id 22 Dit 4N S (f ) 1 (2 f )            (V.5)
where ΔN is the average fluctuation of carrier number and τ Dit is the traps time constant. The corresponding current power spectrum as a function of frequency (f) is shown in Figure V-3a. "Lorentzian" behavior versus f is found [START_REF] Ziel | Noise in Solid State Devices and Circuits[END_REF]. For low frequency values, S Id exhibits a plateau, while after a corner frequency f c , the characteristic decreases proportional to 1/f 2 .

The study of the defects time constant (τ Dit ) leads to fruitful information concerning the traps spatial location and energy distribution. τ Dit is independent of the gate bias in case of uniform defects distribution in the device channel [START_REF] Balandin | Noise and Fluctuations Control in Electronic Devices[END_REF]. In contrast, when V G induces a variation of traps time constant, with maximum around V T , the associated D it are located at interface of silicon film-oxide or in a thin depletion layer [START_REF] Lukyanchikova | A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization[END_REF].

When all the traps have the same time constant, the spectrum generated in the time domain is known as Random Telegraph Signal (RTS). Long and tedious RTS measurements lead to the investigation of capture and emission time constants and traps location [START_REF] Celik-Butler | A method for locating the position of oxide traps responsible for random telegraph signals in submicron MOSFETs[END_REF]. However, the random telegraph signal analysis can only be performed in very small area devices with few individual traps [START_REF] Kirton | Individual defects at the Si:SiO2 interface[END_REF].

In case of standard MOSFET a more homogeneous traps distribution is present at oxide interface.

Each group of traps with the same τ Dit shows RT-signal in the time domain (Lorentzian spectrum in the frequency domain). Thus, the whole current spectrum will be given by the sum of several Lorentzian

1/f (flicker) noise

The flicker noise (1/f ) arises from the sum of different "Lorentzian" spectra. It is assumed that the defects are located at the oxide interface or very close to it (3 nm maximum distance inside the oxide) [START_REF] Reimbold | Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion-Influence of interface states[END_REF].

In a general case, the power spectral density has 1/f γ dependency. Uniform traps distribution leads to γ = 1.

In case of non-uniform N t (γ ≠ 1), γ is larger than 1 when the traps density is increasing deeper into the oxide, otherwise γ < 1 [START_REF] Jayaraman | A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon[END_REF].

Even if no universal explanation exists today, it is commonly accepted that flicker noise in MOSFET originates from conductivity σ variation (δσ) [START_REF] Ghibaudo | Improved analysis of low frequency noise in field-effect MOS transistors[END_REF]. δσ can be due to carrier number fluctuations (model proposed by McWhorter [START_REF] Mcwhorter | Semiconductor Surface Physics[END_REF]) or mobility fluctuations (Hooge's approach [START_REF] Hooge | Experimental studies on 1/f noise[END_REF]). Both sources of noise are present in standard transistors, but a dominant one can usually be identified [START_REF] Ghibaudo | Improved analysis of low frequency noise in field-effect MOS transistors[END_REF].

Mobility fluctuation (HMF) model

Hooge proposed that the conductance fluctuations are only due to the variation of the carrier mobility [START_REF] Hooge | 1/f noise sources[END_REF] induced by phonon scattering [START_REF] Hooge | Lattice scattering causes 1/ƒ noise[END_REF]. Hence, the current power spectrum is given by:

2 DH Id i Iq S f S Q      (V.6)
where α H is the Hooge parameter dependent to the crystal quality, S is the die surface and Q i is the inversion charge density.

Carrier number fluctuations (CFN) model

McWhorter proposed that the conductance fluctuations are due to the variation of the mobile charge density induced by trapping or detrapping phenomena taking place in a MOSFET [START_REF] Mcwhorter | Semiconductor Surface Physics[END_REF]. A change of fixed defects produces flat-band voltage (δV FB ) oscillations [START_REF] Ghibaudo | Improved analysis of low frequency noise in field-effect MOS transistors[END_REF], which are detected on the current measurement.

The current power spectrum is:

2 Id m Vfb S g S  (V.7)
where S Vfb is the power spectrum associated to flat-band voltage oscillations. S Vfb is defined in the

McWhorter's model as [START_REF] Christensson | Low frequency noise in MOS transistors-I Theory[END_REF]:

2 t Vfb 2 OX q k T N S f S C         (V.8)
λ is the tunneling attenuation length calculated using Wentzel-Kramers-Brillouin (WKB) theory [START_REF] Wang | Statistical variability and reliability in nanoscale FinFETs[END_REF]. Its value is usually ≈ 1 Å. N t is the density of slow traps per unit volume (cm -3 eV -1 ).

Carrier number with correlated mobility fluctuations (CNF+CMF) model

The two models describe δσ using two different physical phenomena. However, recent studies [START_REF] Ghibaudo | Improved analysis of low frequency noise in field-effect MOS transistors[END_REF], [START_REF] Hung | A unified model for the flicker noise in metal-oxidesemiconductor field-effect transistors[END_REF] have proved that a correlation exists between the two approaches. where α sc is the Coulomb scattering coefficient [START_REF] Sun | Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces[END_REF]. The sign ± identifies the defects type: "+" in case of donor-like traps and "-" in case of acceptor-like N t . Defining Ω C = α sc •μ eff •C OX and the gate bias power spectrum as S Vg = S Id /g m 2 , Eq. (V.9) can be written as [START_REF] Ioannidis | Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs[END_REF]:

2 D Vg Vfb C m I S S 1 g         (V.10)
The mobility contribution becomes important only in strong inversion (or accumulation) regime, while in the subthreshold region its impact is negligible (S Vg ≈ S Vfb ).

V.1.3 State of art of LFN in pseudo-MOSFET

Kushner et al. [START_REF] Kushner | SOI Low Frequency Noise and Interface Trap Density Measurements with the Pseudo MOSFET[END_REF], [START_REF] Kushner | Low-Frequency-Noise Spectroscopy of SIMOX and Bonded SOI Wafers[END_REF] have analyzed the LFN generated in high resistive SOI substrates using ground-signal-ground and circular contacts. The characterization succeeded but the Schottky barriers make the extraction procedure complicate and tedious to apply. Diab et al. [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF] have performed LFN in pseudo-MOSFET configuration. The extracted D it values were surprisingly large (i.e., ≈ 2•10 13 cm -2 eV -1 instead of a maximum of ≈ 10 12 cm -2 eV -1 in case of non-passivated samples). Additionally, the S Id signal was higher for passivated than for non-passivated SOI. No clear explanation for these results was provided.

Was there an issue of the experimental setup? Do we only need to correctly adapt the models for the Ψ-MOSFET configuration in other to obtain reasonable D it values?

The aim of our work on LFN characterization was to find the answers to these questions. We approched the topics with both experiments and modeling. In order to reduce the impact of system noise, S Id (I D = 0 A) was subtracted from S Id (I D > 0 A) before any further data treatment.

To pursue defects extraction, it is required to relate the LFN and the static characterization. Dividing both terms of Eq. (V.7) by I D 2 , the equation becomes: values, small differences are visible between the curves. On the contrary, remarkable overlap is obtained for large I D . We conclude that the extraction frequency does not limit the analysis. Equation (V.8) leads to N t calculation. All the terms are known, except for the surface, S. In case of pseudo-MOSFET, the surface which contributes to the current is apparently given by the inter-probe distance d and the geometrical factor f G = W/L [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF]:

2 2 G W S W L L f d L       (V.12)
Thus, one gets N t = 1.3•10 22 cm -3 eV -1 . This value is clearly too large and not realistic but it is comparable to what was previously found [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF].

For large gate bias values, (g m /I D ) 2 differs from S Id /I D 2 . This is due to mobility variations. To perform a better extraction, Figure V-7b shows S Vfb calculated using Eq. (V.11) versus drain current (plain symbols).

The flat-band voltage power spectrum is almost constant for low values of drain current and decreases when I D increases, confirming the presence of mobility variation effects. A better representation is obtained computing the flat voltage power spectrum using Eq. (V.9) (empty symbols). A good fit was found in case of

V.2.2 Reproducibility issues

As in case of capacitance measurements (see Sec. III.2.2) the quality of the back contact may limit the characterization and consequently the extracted interface traps density. Is this happening for LFN? previously. V G is only used to polarize the substrate, while δI is generated by the current flow between source and drain contacts. However, the use of vacuum system increases the reproducibility, thus it will always be applied to the metallic chuck.

Additionally, the dashed-dot line in Figure V-8 represents the measured S Id /I D 2 obtained using different probes on the same SOI die. Even if the shape is similar, more than one order of magnitude difference is found in the plateau height, which implies a factor of 10 of difference in the extracted N t (since the corresponding (g m /I D ) 2 superpose as shown in the inset). Thus, the probe choice seems to have a tremendous impact for LFN analysis, unlike in the other characterization techniques. The needles contact looks critical, so the natural next step requiring investigation is the impact of the pressure applied on the tips.

V.2.3 Probe pressure impact

The increase of the pressure applied on the probes is known to change the access resistance for I D -V G measurements (Sec. II.3.3). At the same time the craters generated by the probes are larger [START_REF] Ionica | Characterization of silicon-on-insulator films with pseudo-metal-oxide-semiconductor field-effect transistor: Correlation between contact pressure, crater morphology, and series resistance[END_REF]. Could this be related to the obtained N t magnitude? To investigate this aspect, pressure impact was studied on both passivated and non-passivated SOI. In order to isolate the N t contribution from the fast traps, S Vfb was calculated using Eq. (V.9) in case of

V.2.4 Impact of inter-probe distance and die area

In case of Ψ-MOSFET configuration, the surface S is not well defined. The LFN needs S for N t extraction: S Vfb is proportional to 1/S (Eq. (V.8)). In this context, experimental effects of the inter-probe distance or the whole die area should be visible. No clear explanation or trends emerged from the experimental parameters. However, the conclusion is that S is clearly not well defined for the case of Ψ-MOSFET. Modeling is necessary to understand the physical phenomena and identify the surface representative for the noise measurements.

V.3 LFN in inhomogeneous material

Trefan et al. [START_REF] Trefán | 1/f noise in homogeneous and inhomogeneous media[END_REF] have derived the LFN generated in a resistor under constant bias using the power density. The equations will be adapted to the case of constant current flow and the δI source will be associated to the variation of the carrier density (CFN model) (Sec. V.3.1). In Sec. V.3.2, the LF-noise will be computed using a differential equation solver (FlexPDE®) to explain the experimental trends discussed in Sec. V.2.

V.3.1 Physical model

Considering a resistor with a constant current I applied, the dissipated power P is proportional to I and the bias V measured across the resistor:

P I V  (V.13)
Consequently, P is proportional to the material conductivity σ and the electric field ξ:

2 P I V d           (V.14)
where Ω is the resistor volume.

Using Tellegen theorem [START_REF] Penfield | Tellegen's Theorem and Electrical Networks[END_REF], it is possible to show that in a network where constant current I is applied, the current fluctuations δI are due to the sum of conductivity oscillations δσ:

2 1 Id V          (V.15)
Thus, the associated current power spectrum becomes:

2 2 4 Id 2 1 S I d V           (V.16)
The Ohm law relates the conductance G with V and I: I = V•G. Using Eq. (V.13), G can be expressed as a function of power density:

2 22 P1 Gd VV          (V.17)
Hence, I 2 becomes:

  2 2 22 2 1 I V G d V              (V.
               (V.21)
In case of SOI substrates characterized in pseudo-MOSFET configuration, the inversion (or accumulation) channel induced by V G is very close to the silicon film-BOX interface. Thus, Ω eff can be replaced by the effective surface term (S eff_LFN ):

2 2 S eff _ LFN 4 S d SS d             (V.22)
where S is the whole die area. S eff_LFN will be equal to S only for uniform current density [START_REF] Trefán | 1/f noise in homogeneous and inhomogeneous media[END_REF], which is not the case of pseudo-MOSFET. Using Eq. (V.20) and Eq. (V.22), S Id /I D 2 becomes:

2 Vfb _ area Id 2 D FB eff S S 1 I V S          (V.23)
In the next section the distribution of the surface potential Ψ S on the silicon film will be obtained numerically by solving the drift-diffusion equation in the top silicon film and Eq. (V.23) will be used to compute the LFN generated in the Si layer.

V.3.2 Computation of LF-noise

Configuration of the differential equation solver (FlexPDE®)

In order to compute the low-frequency noise obtained in case of bare SOI wafers, a differential equation solver (FlexPDE®) was used. Lambert equation is used to calculate the charge density induced by V G at the interface between the buried oxide and the top silicon film [START_REF] Tsormpatzoglou | A compact drain current model of short-channel cylindrical gate-all-around MOSFETs[END_REF]. Consequently, Ψ S on the whole surface of the Si layer is obtained numerically solving the Laplace equation:

  S div grad( ) 0      (V.24)
The electric field is directly computed from Ψ S :

  S grad    (V.25)
Equation (V.17) leads to the silicon film conductance and consequently to the drain current between the two contacts. Furthermore, Eq. (V.23) allows the LF-noise calculation.

Impact of interface quality

It is known from the literature [START_REF] Hamaide | Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization[END_REF] that passivated and non-passivated top silicon surface have different density of defects placed at the interfaces. Thus, not only N t will change, but also the fast traps D it , which determine the subthreshold swing. represents the largest amount of defects, hence we would expect the highest S Vfb magnitude. This is not the case because the D it variation also induces a shift of the current PSD.

Impact of inter-probe distance and die area

The experimental results presented in

V.4 Effective surface in LF-noise

The experimental and computed results clearly show that the geometry (inter-probe distance or die area) is not relevant for LFN. Where is the noise really coming from in this case?

We investigate the region where most of LF-noise is generated (effective surface, S eff_LFN ) in Sec.

V.4.1 and quantified it in Sec. V.4.2.

V.4.1 Why an effective surface?

Figure V-20 shows the whole die area (dashed line) computed as a function of L (die length of square die). S eff_LNF is calculated with Eq. (V.22) and added to the graph (line). A huge difference between S and the effective surface is found. Figure V-20 proves that the LNF signal measured in the silicon film is generated in a reduced region which is much smaller than S (2 to 3 orders in magnitude difference). This explains why the inter-probe distance and especially the die surface variation have almost no impact on the obtained characteristics. x (cm) y (cm)

Current density: (A/cm) .

Source Drain The effective surface is directly proportional to R 0 in case of sharp probes (region A). Thus, a small variation of the probe radius will strongly affect the obtained LFN signal (i.e., variation of tip crater). This explains the important S Id /I D 2 shift obtained using different probes (see Figure V-8). The use of large contacts leads to constant S eff_LFN magnitude (region B) independent of R 0 . Thus, S Vfb extraction will be less related to the probe diameter and therefore relevant for substrate characterization. After a preliminary calibration to determine the effective surface, continuous monitoring could be performed on samples using always the same probes.

One of the main conclusions of this section is that the obtained LF-noise arises from localized regions around the source and drain contacts and the effective area S eff_LFN is much smaller than S. This explains why the N t calculated using S (Eq. (V.12)) had such unrealistic, overestimated values.

V.5 Probe penetration effects

After proving that the LFN mostly arises from small regions localized around the probe contacts (S eff_LFN ), some questions still remain:

o Is the noise related to defects generated by probe penetration in the Si film?

o Is the LFN in pseudo-MOSFET configuration sensitive to the sample quality?

Experimental results in Sec. V.5.1 and calculations with FlexPDE® (Sec. V.5.2) will try to answer these questions.

V.5.1 Experimental evidences

HF treatment

We still need to understand if the measured signal is related to the interface defects or not. S eff_LFN proved that for sharp probes, as in our case, the signal arises from small regions around the source and drain contacts. Quantifying the effective surface is quite complicated for small R 0 . From the practical point of view it was possible to imagine an experiment in which everything related to the probe contacts is fixed while the samples have a variation of the interface quality. This is achieved by the use of a sample after HF treatment. The native oxide of non-passivated wafer plunged in HF solution (diluated at 5 %) is etched of. The native oxide grows back within hours until the surface will become stable again. Thus, the top interface traps density changes during the re-oxidation [START_REF] Hovel | Si film electrical characterization in SOI substrates by the HgFET technique[END_REF].

LF-noise was performed on this sample at different moments after etching. The probes were initially placed on the surface of the die and not moved during the tests. This allows assuming that the contacts and thus the effective surface are the same for all the measurements. A general overlap between the curves is observed. Contrary to static characterization, no appreciable variation of the curves in time is found. LFN is clearly "blind" to this evolution of the top surface.

Charging procedure

Since the re-oxidation was not visible by LFN, a possibility to modify the quantity of slow traps present on SOI wafer could be the charging procedure discussed in case of QST measurements (see Sec.

IV.6). computed as function of drain current. The flat-band voltage power spectrum is higher before charging procedure (plain symbols) than after it (empty symbols). One expects an increase of the N t density after charging, while a light decrease is obtained. One possibility to explain the phenomenon is that the charged defects are "masked" during the analysis. They require long time to release the captured electrons, thus they will not respond to the applied input, if they are still filled … or, again, the LFN is actually not sensitive to what is happening in the sample.

These two tests (HF clean and charging procedure) show that even if the impact of effective surface was experimentally stabilized, the signature due to interface quality is too small to be convincing. The parameter which seems to mostly impact the experiments is explained in the next section.

V.5.2 Computation of induced defects by probe penetration

A possible explanation of the measured trends is given by the study of the defects induced by probe penetration in the silicon film. In order to investigate this phenomenon, we used the same structure presented cm -2 eV -1 and N t = 10 20 cm -3 eV -1 were used. The contact radius was 5 μm, while ΔR 0 = 500 nm. It is noted that an increased density of defects induced by probes leads to higher LFN plateau. This means that the interface trap density extracted from the plateau value is not representative of the actual density of traps in the SOI material (here D it = 10 12 cm -2 eV -1 ). For example, N t is oversestimated by 173 % for N t_added = 10 21 cm -2 eV -1 . Considering N t = 10 20 cm -3 eV -1 , S Id /I D 2 _red dominates the whole LFN signal for higher N t_added than for low density of traps present on the SOI structure (N t = 10 19 cm -3 eV -1 ). Thus, in higher quality passivated substrates, the LFN is probably more probe damage related than for the non-passivated ones (low quality of top silicon interface). As shown in Sec. V.4.2, higher R 0 radius might stabilize S eff_LFN . It is also known from the literature that larger tips induce a smaller amount of defects on the SOI structure [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF].To further evaluate this solution,

V.6 Conclusions and perspectives

In this chapter, a detailed investigation of low-frequency noise in pseudo-MOSFET was performed.

The aim was to explain the abnormally large D it values previously extracted by LFN in Ψ-MOSFET.

We discussed about the improvements due to the use of vacuum system and we demonstrated that the geometry of the sample has little importance, while the probes have a high impact on the experiments.

A physical model was proposed to explain the LFN in a material in case of inhomogeneous current flow. Simulations were performed and good agreement between experimental and computed trends was found. It was proved that the noise signal arises from small surface localized around the contacts and this is why it is mostly independent of the whole die area or inter-probe distance.

Obviously, this small surface is mostly determined by the probe. The needle radius R 0 plays a major role for LF-noise characterization. Furthermore, the impact of defects induced by probe penetration was studied. It was extensively discussed that using standard Jandel® station with needle radius of 40 μm, the obtained S Id signal is almost independent of the quality of the SOI wafer; the defects induced by the probes dominate the whole detected noise, making the LFN characterization not suitable for interface monitoring.

Using particular precautions it could be possible to increase the sensitivity of noise analysis to the SOI interfaces. Two possible approaches can be envisaged:

o The use of larger probe sizes (R 0 ≈ 150 μm-200 μm) makes S eff_LFN almost constant and the noise signal will be less localized around the contacts. Furthermore, the needles will less penetrate into the silicon film. This should induce less defects [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF] and the signal due to N t might be revealed.

o Perform low-frequency noise in 4-probe configuration. This technique should decrease the impact of contacts and make visible the contribution due to the interface defects.

o The LFN technique may be used to characterize the contact between the probe and the silicon film leading to a better knowledge of defects induced by tips penetration.

VI.1 Conclusions

The pseudo-MOSFET is a powerful measurement method for the characterization of bare SOI wafers [START_REF] Cristoloveanu | Point-contact pseudo-MOSFET for in-situ characterization of asgrown silicon-on-insulator wafers[END_REF]. Several studies pointed out the capability to extract carrier mobility, oxide defects and interface quality using static I D -V G analysis [START_REF] Ionescu | A novel in-situ SOI characterization technique: the intrinsic pointprobe MOSFET[END_REF], [START_REF] Rodriguez | Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX[END_REF], [START_REF] Van Den Daele | Adaptation of the pseudo-metal-oxide-semiconductor field effect transistor technique to ultrathin silicon-on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling[END_REF], [START_REF] Cristoloveanu | The Pseudo-MOSFET: Principles and Recent Trends[END_REF]. However, this measurement shows limits for the material characterization [START_REF] Munteanu | Modelisation et characterisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultra-mince[END_REF], [START_REF] Komiya | Detailed Investigation of Geometrical Factor for Pseudo-MOS Transistor Technique[END_REF], especially for advanced SOI substrates with ultra-thin silicon film. Consequently, new techniques were developed. For example, low-frequency noise measurements were performed in Ψ-MOSFET by Diab et al. [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF], but the obtained values of interface state density were not convincing. The effective carrier mobility was successfully extracted using split-CV technique [START_REF] Diab | A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration[END_REF], [START_REF] Fernandez | Determination of Effective Capacitance Area for Pseudo-MOSFET Based Characterization of Bare SOI Wafers by Split-C(V) Measurements[END_REF]. Nevertheless, the method needed a fitting parameter named effective surface, that was not clearly explained. Furthermore, capacitance measurements were not extended for D it extraction.

In this thesis, we addressed same of these opened topics and we enriched the characterization methods of bare SOI substrates. Starting from the well-known static I D -V G analysis, three other techniques were discussed, from both experimental and modeling point of view: split-CV, quasi-static capacitance and lowfrequency noise. The main results can be summarized by 3 topics: improved measurement setup, effective surface and D it extraction.

Improved measurement setup

We proved that a good measurement setup increases the robustness of the characterization technique, leading to more stable analysis. Note that in Ψ-MOSFET, the critical setups are not the same for all the measurement techniques.

In case of capacitance analysis (split-CV and quasi-static CV), the quality of the back contact between the substrate and the metallic chuck is the major parameter. The use of vacuum system leads to stable characteristics and avoids parasitic capacitance contributions. The adjustable pressure probes play only a minor role. Hence, the possibility to characterize also ultra-thin silicon films and BOX using capacitance analysis makes the technique very promising for the quality monitoring of bare SOI wafers.

The opposite situation was found for the techniques based on drain current measurements (static I D -V G and LFN): here the probes have a dominant role on the experimental characteristics. The use of vacuum for the back contact, even if not critical, is highly recommended in order to attenuate the effect of parasitic terms. The vacuum becomes mandatory in case of ultra-thin SOI structures.

Additionally, in case of low-frequency noise the probes have a supplementary role because they induce defects in the silicon film increasing the measured D it . Reproducible analysis requires systematic precautions.

The Ψ-MOSFET setup was also used for III-V layers where we found that the probe material is critical.

VI.2 Perspectives

In this thesis, we answered some critical questions concerning the split-CV or LFN technique, we introduced the QSCV technique in Ψ-MOSFET and we characterized a variety of SOI films and also III-V layers. However, some aspects need further investigation:

-The setup improvements (quality of back contact) open the way for other new techniques in Ψ-MOSFET configuration, such as charge pumping or the analysis of transitory phenomena.

-The impact of substrate capacitane has to be investigated for measurements performed using vacuum contact. This term can play a role for static I D -V G analsysis and capacitance measurements.

-Other passivated samples can be tested using QSCV technique in order to investigate the impact of the crystal orientation and better separate the contributions due to the several interfaces.

-The D it profile measured using QSCV in non-passivated samples requires deeper investigation, especially for UTBB structures (tests of charging procedure for samples with t OX = 25 nm).

-The use of 4-probes configuration or larger needles could make the LFN technique suitable also in Ψ-MOSFET configuration.

-The low-frequency nosie can be a fruitful technique for the characterization of the contact between the pressure probes and the silicon film. For sharp tips, the signal is mostly determined by defects induced by probe penetration. Thus, its analysis may enrich the knoldge about source and drain contacts.

-The III-V materials clearly represent a possible future for microelectronics. The material characterization is challenging. The standard I D -V G in Ψ-MOSFET configuration did not work, probably because of contact problems. However, the low dependency on the probe penetration makes QSCV a promising technique for D it extraction in III-V layers.

… but I leave all these topics to the next generation of students.

Hall effect measurement

For the Hall effect measurements, the same sample used during Van Der Pauw characterization is gently moved into the center of a magnetic gap. 0.5 T are applied perpendicular to the die surface (+B). The field direction can also be reversed (-B) (see Figure AI-2). The current is set between two diagonal probes and the potential drop is measured between the two other needles.

In a practical case the current is applied between the probes 1 and 3 (I 13 if the current is inject in 1 while I 31 if it is reversed) while the tips 2 and 4 are used to measure the potential (V 24 ). Four different voltage values can be obtained changing current and magnetic field direction: V 24 (I 13 ,+B) where the current is injected in 1 and the applied magnetic field is +B; V 24 (I 31 ,+B) where the current is reversed (I 31 instead of I 13 ) and the magnetic field direction is kept constant; V 24 (I 13 ,-B) and V 24 (I 31 ,-B) where the same characterizations are repeated using I 13 and I 31 but he magnetic field applied is reversed (-B). Hence, the corresponding Hall voltage is: obtenus par oxydation thermique sur la surface du film de silicium, pour améliorer la qualité de la interface supérieure [14]). Deux différentes épaisseurs d'oxyde enterré ont été utilisées : 25 nm (symboles pleins) et 145 nm (symboles vides). La superposition des deux courbes confirme que la variation de l'épaisseur de l'oxyde enterré a un faible impact sur la densité des défauts lents présents dans les structures SOI. Pour les échantillons non passivés, un grand pic dû à des défauts d'interface apparait pour des valeurs d'énergie bien identifiées et correspondant aux défauts à l'interface film de silicium-oxyde natif [15], [16].

  Acknowledgements ................................................................................................................................ iii Abstract/Résumé ..................................................................................................................................... v

Figure I-1b

  Figure I-1b shows a schematic of drain current in logarithmic scale versus gate bias for standard ntype transistor. The characteristic has a clear switch behavior. Three regions related to the state of the device can be identified:

Figure I- 1 :Figure I- 2 :

 12 Figure I-1: (a) Schematic view of n-type MOSFET [5]. (b) Example of drain current in logarithmic scale versus gate bias for n-MOSFET. One of the main advantages of MOSFET is the possibility to co-integrate p-type and n-type devices on the same substrate, thanks to the use of implanted wells (CMOS technology) (Figure I-2). This allows the fabrication of integrated logic circuits which are small and fast. Conduction Channel

Figure I- 3 :

 3 Figure I-3: Evolution of microprocessor transistors count (Moore's law) [7].

Figure I- 4 :

 4 Figure I-4: (a) Example of p-type and n-type MOSFET co-integrated using silicon-on-oxide substrate [6]. (b)

Figure I- 5 :

 5 Figure I-5: Schematic of silicon-on-insulator (SOI) substrate.

Figure I- 6 o

 6 at step 3_oxidation); The donor and handle wafers are cleaned. The surfaces are made hydrophilic;

Figure I- 6 :

 6 Figure I-6: Schematic of Smart-Cut™ process for SOI fabrication [45].

Figure I- 7 :

 7 Figure I-7: Example of defects on SOI structure.

Figure II- 1 : 4 -

 14 Figure II-1: 4-probes measurement on infinite layer. 4 in-line needles are used.

Figure II- 2 :

 2 Figure II-2: (a) SOI structure characterized using standard pseudo-MOSFET configuration [47]. (b) Top view of HgFET contacts [63]. SOI wafer with fabricated source and drain contacts [64].

Figure II- 3 :

 3 Figure II-3: (a) Top view of the SOI wafer after etching process. L x L isolated mesas separated by 2 mm distance were obtained. (b) Vertical cross-section of a SOI island.

  the electronic bands bend down with respect to the flat band condition, depleting the p-type Si film. Beyond V T (threshold voltage), a conduction channel made of electrons is obtained (FigureII-4a). In case of V G < V FB , the conduction channel will be made of accumulated holes (electronic bands bent upwards) (FigureII-4b).

Figure II- 4 :

 4 Figure II-4: SOI structure with positive (a) and negative (b) gate biases applied. Hole and electron channels are induced, respectively.

Figure II- 5 :

 5 Figure II-5: (a) I D versus V D performed on the same die in case of positive (plain symbols) and negative (empty symbols) overdrive bias. (b) Drain current (empty symbols) and transconductance (line) as a function of gate bias. The SOI structure had 88 nm top silicon film thickness and 145 nm BOX thickness and it was nonpassivated.

  a hole channel is induced (FigureII-5). The same equations remain valid but V FB must replace V T ; μ 0 and μ eff represent the hole mobility.

Figure

  Figure II-6a presents the Y function computed from the data in Figure II-5b. In strong inversion (or accumulation) regime, the Y function is linearly dependent with respect to V G (Eq. (II.6)).From the linear fit,

Figure II- 6 :

 6 Figure II-6: (a) Y function versus gate bias (data from Figure II-5a). The slope of the linear fit allows μ 0 calculation, while the intercepts with the x-axis lead to V T and V FB , respectively. (b) θ as a function of V G ; in strong inversion regime the constant value θ is θ 1 .

Figure II- 7 :

 7 Figure II-7: Drain current in semi-logarithmic scale versus gate bias. The slopes of the linear regions lead to the estimation of subthreshold swing for holes and electrons. Same data as in Figure II-5a.

FigureFigure II- 8 :

 8 Figure II-8a shows the drain current versus gate bias on SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. The top surface was non-passivated. The characterization was performed with (empty symbols) and without (plain symbols) vacuum system. The results obtained on SOI structure with the same t OX but thinner silicon layer (12 nm) are presented in Figure II-8b. Variation of V T and S s are obtained in both cases, and there are stronger for the thinner silicon film. Vacuum system will be always used to avoid parasitic effects. In the chapter of split-CV measurements we will show that the vacuum contact is even more critical. (a) (b)

Figure

  Figure II-9a shows the measured I D as a function of V G using different needles. Curves match for low V G but for very large gate bias some differences are present. In this region, R SD (which is probe related) becomes relevant, inducing I D variations. The corresponding Y functions are shown in Figure II-9b. The impact of access resistance is removed in this case (see Eq. (II.6)) and the curves superpose. Thus, the choice of the probe is not critical in case of I D -V G characterization analyzed using the Y function.

Figure II- 9 :

 9 Figure II-9: Measured drain current (a) and Y function (b) versus gate bias on the same SOI structure as in Figure II-8a. Different combinations of probes were used for the analysis. The inter-probe distance was kept constant to 1 mm.

  obtained I D versus V G are shown Figure II-10a. The corresponding positions on the silicon surface are represented schematically in the inset. Very close to the edges, the current flow is affected by border effects decreasing the measured I D value [67]. The corresponding Y functions versus gate bias are shown in Figure II-10b and the computed low-field mobilities are reported in Table

Figure II- 10 :Table II- 1 :

 101 Figure II-10: Drain current (a) and Y function (b) versus gate bias for different probe positions. The SOI structure had 88 nm thick top silicon film and 145 nm BOX. The top surface was non-passivated. The die size L was 8 mm. The inset in Figure II-10a presents the corresponding probe position on the silicon surface.

  Figure II-11 shows the measured I D (a) and Y function (b) as a function of V G for different p.

Figure II- 11 :

 11 Figure II-11: (a) I D versus gate bias in case of different probe pressure. The SOI structure had 88 nm top silicon film and 145 nm BOX. Non-passivated top surface was used and L = 5 mm. The corresponding Y function is computed in Figure II-11b.

Figure II- 12

 12 Figure II-12 shows the measured drain current (a) and corresponding Y function (b) versus gate bias in case of Jandel® station (plain symbols) and manual probe station (empty symbols). The corresponding parameters extracted using Y function method are reported inTable II-4. The obtained electron and hole

Figure II- 12 :

 12 Figure II-12: Drain current (a) and Y function (b) versus gate bias on SOI structure with 88 nm top silicon film and 145 nm BOX. The top surface was non-passivated and L = 2 mm. Different tips were used: WC with R 0 = 40 μm from Jandel® station (plain symbols), WC (empty symbols) and Os (line) tips with radius R 0 = 12 μm from manual probe station. The inter-probe distance d was ≈ 1 mm.

Figure II- 13 :

 13 Figure II-13: Extracted μ 0 (plain symbols) and V T (empty symbols) from different dies present in the same SOI wafer with 88 nm thick Si film and 145 nm thick BOX. The top surface was non-passivated.

  Figure II-14 shows an example of the measured I D versus V G for passivated (plain symbols) and non-passivated (empty symbols) wafers. The different density of defects induces remarkable shifts of V T , V FB and S s .

Figure II- 14 :

 14 Figure II-14: Drain current as a function of gate bias for SOI structure with 88 nm top silicon film and 145 nm BOX. The passivated structure (plain symbols) was measured using p = 100 g, while in non-passivated sample (empty symbols) the tip pressure was 80 g.

Furthermore, we analyzed

  by AFM the tip signature left on the silicon surface (see Figure in passivated (a) and non-passivated (b) samples. The same needle was used but with different pressures: p = 100 g for passivated and p = 80 g for non-passivated Si surface. The images were taken with the same scale (10 μm x 10 μm). The measured fingerprints show comparable dimensions (R 0 ≈ 5-6 μm) which explains the analogous R SD values. In conclusion, to perform suitable data comparison it is important to measure the characteristics with similar access resistance. p is not directly related to physical quantities.With time, the probe station may become old and the tips can oxidize. However, adapting the probe pressure, it is possible to achieve low access resistance, thus robust material characterization.

Figure II- 15 :

 15 Figure II-15: 10 μm x 10 μm AFM image for passivated (a) and non-passivated (b) SOI samples. The same tip was used with different pressure: 100 g in case of passivated and 80 g for the non-passivated one.

Figure II- 16 :

 16 Figure II-16: (a) General shape of III-V layer on InP substrate before bonding. (b) Measured μ Hall versus doping concentration on 160 nm InGaAs with different doping concentrations.

3 )Figure II- 17 :

 317 Figure II-17: μ Hall (plain symbols) and doping concentration (empty symbols) as a function of t III-V for InGaAs layer on InP.

II-18a presentsFigure II- 18 :

 18 Figure II-18: Measured drain current versus V D (a) and V G (b) for different gate and drain bias values, respectively. The structure had 10 nm III-V layer thickness and 110 nm SiO 2 BOX thickness.

  Figure II-19a shows I D versus gate bias for different p. The SOI structure had 50 nm InGaAs thick film and 30 nm Al 2 O 3 BOX. No clear trend is visible. The limitations may be due to a non-ohmic contact between films and probes. Thus, Figure II-19b presents I D (V D ) curves obtained with Os needles of 12 μm radius. The same structure as in Figure II-18 was

Figure II- 19 :

 19 Figure II-19: (a) Drain current versus gate bias for different probe pressure. Structure with 50 nm III-V layer thickness and 30 nm Al 2 O 3 thickness. (b) I D versus V D for different V G values. Os tips were used on the same structure as in Figure II-18.

Figure

  Figure II-20b presents the mask used for the lithography. μ Hall and the low-field mobility (μ 0 ) were measured using the Hall effect and the Corbino configuration, respectively. In case of Corbino contacts the drain contact was placed at the center and the source on the circle surrounding the first contact (Figure II-20c). Applying a back gate bias, the conduction channel is created at the interface between the InGaAs and the BOX. Consequently, I D can be measured versus V G (same principle and extraction procedure as for standard Ψ-MOSFET). The Y function method was used to extract μ 0 . Using a Corbino structure, the

2 Figure II- 20 :

 220 Figure II-20: (a) III-V substrate structure used in this section. Different annealing temperatures were performed on pieces of material coming from the same starting wafer. (b) Layout of the mask fabricated on the III-V layer. (c) Zoom of Corbino structure.

Figure II- 21

 21 Figure II-21 presents the measured resistivity (empty symbols) and doping concentration (plain symbols) as a function of T an . After low annealing temperature (500 ºC), the III-V layer is very resistive, while for high T an , ρ abruptly decreases. The doping concentration shows the corresponding trend. Since the samples come from the same wafer, with the same implanted dose, a higher annealing temperature simply activates more dopants.

3 )Figure II- 21 :

 321 Figure II-21: Measured ρ (empty symbols) and doping concentration (plain symbols) as a function of annealing temperature. Values with ≈ 15 % of incertitude. The corresponding Hall mobility (empty symbols) and μ 0 (plain symbols) values as functions of annealing temperature are reported in Figure II-22. The low-field mobility was extracted using the Y function method performed on I D -V G characteristic. Unfortunately no working die was found applying V G on

Figure II- 22 :

 22 Figure II-22: μ Hall (empty symbols) and μ 0 from Y function (plain symbols) measured as a function of annealing temperature. Measurements performed at ambient temperature.

Figure II- 23 :

 23 Figure II-23: (a) Measured drain current versus gate bias for different temperatures. (b) Low-field mobility normalized by μ 0_T=77K as a function of T in logarithmic scale for three different dies. Linear fit performed at high temperatures (dashed lines). Inset: schematic of measured III-V-OI structure. T an = 500 ºC.

Figure II- 24 :

 24 Figure II-24: Drain current and g m measured versus gate bias obtained from FinFET on oxide. L = 40 nm and W = 2μm. The top oxide has ≈ 1.7 nm EOT while the back-oxide was 30 nm of Al 2 O 3 .

Figure II- 25 :

 25 Figure II-25: (a) Measured drain current versus V G for different back-gate bias. The FinFET on oxide had L =

ForFigure III- 1 :

 1 Figure III-1: (a) Split-CV setup in case of gate-to-channel capacitance for MOSFET device. (b) Typical low frequency C GC shape versus gate bias in case of n-type transistor. C OX added as eye-guide.

FigureFigure III- 2 :

 2 Figure III-2b shows the typical gate-to-substrate capacitance shape versus gate bias for n-type transistor (p-type substrate). Before flat-band voltage, the accumulation charges dominate and C OX •S is measured. No depletion region is present. For V G > V FB , no free charges are present in the channel and the x Dep changes proportionally to V G until C GS becomes negligible at V T [5].(a) (b)

  III-3a). All the measurements have been performed using either the Agilent E4980A® or the Agilent 4284® LCR meter. The chosen equivalent electric circuit configuration is a capacitance (C m_split ) in parallel with a conductance (G m_split ). In this way it is possible to separate the dispersive effects of the resistance (1/G m_split ) from the capacitance characteristics[95],[96]. Figure III-3b shows the applied gate bias signal required to perform capacitance measurements. The LCR meter sets a static bias value to the device under test. An a.c.

Figure III- 3 :

 3 Figure III-3: (a) Measurement setup and equivalent electric circuit for split-CV capacitance in pseudo-MOSFET configuration. (b) Schematic of applied gate bias in split-CV as a function of time.

Figure III- 4 :

 4 Figure III-4: C GC as a function of gate voltage for different measurement frequencies. SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. The die area was 24 mm 2 [53].

S

  eff replaces the actual sample surface S in the computation of Eq. (III.2). It is determined from the maximum capacitance value and BOX thickness. Figure III-5 shows the obtained effective mobility (empty symbols) versus gate bias for electrons (a) and holes (b). To validate the obtained values, µ eff reconstructed

Figure III- 5 :

 5 Figure III-5: Effective mobility as a function of gate bias obtained from Figure III-4 in case of electrons (a) and holes (b). The reconstructed values from Y function method (plain symbols) are also shown [53].

FigureFigure III- 6 (

 6 Figure III-6a shows the measured capacitance as a function of gate bias at low frequency 20 Hz, on SOI structures with 88 nm thick silicon film and 145 nm thick BOX. Different die areas have been used(values added on the curves). The higher the die area, the higher the measured maximum capacitance (C max_air ). The y-axis scale shows that the increasing of C max_air for larger surface is not linear. The effective surface values divided by the surface S corresponding to each curve are plotted as a function of die area in Figure III-6b. Using small size sample (i.e., 4 mm 2 ), S eff /S is close to unity. Thus, the measured capacitance is close to the expected value. Increasing the die dimensions, the surface ratio S eff /S sharply decreases. This dependency is unexpected and difficult to explain. For standard MOSFET devices, the scaling of the maximum measured capacitance is directly proportional to the die area. (a) (b)

Figure III- 7 :

 7 Figure III-7: Capacitance (a) and conductance (b) versus gate bias measured at low frequency (f = 20 Hz). Two different types of back contact have been used: vacuum back contact (plain symbols) and air back contact (empty symbols). The dashed line represents the BOX capacitance. SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. The die had non-passivated top surface and 24 mm 2 area.

Figure III- 8 :

 8 Figure III-8: Capacitance versus gate bias measured at low frequency (f = 20 Hz) using different die areas in case of vacuum back contact. The same SOI structures as in Figure III-6 have been used. To better evaluate the obtained results, Table III-2 compares the calculated C OX •S by Eq. (III.1) with C max and C max_air extracted from Figure III-8 and Figure III-6a, respectively.In case of vacuum contact, the measured maximum capacitance is given by the oxide capacitance. On the contrary, C max_air is always lower than the expected one. For larger die surfaces, the difference between the measured maximum capacitance using back air contact and C OX becomes stronger.

Figure III- 9

 9 Figure III-9 shows the effective mobility as a function of gate bias obtained from Figure III-7a in case of electrons (a) and holes (b). The values are computed from characteristics measured with (plain symbols)

Figure III- 9 :

 9 Figure III-9: Effective carrier mobility as a function of gate bias obtained from Figure III-7a in case of electrons (a) and holes (b) using vacuum (plain symbols) and air (empty symbols) back contact. Reconstructed value from Y function method (dashed line) using Eq. (III.9).

Figure III- 10

 10 Figure III-10 shows C m_split (a) and G m_split (b) curves versus gate bias performed at low frequency using different probe pressures. The inset shows the corresponding drain current characteristics as a function of gate bias. Remarkable overlap between the curves was found for both capacitance and conductance terms.Using split-CV technique the adjustable pressure probes are connected to low potential and the contact quality with the Si film plays a minor role. Even if the access resistance is high (i.e., low probe pressure), the measured capacitance is the same as for low access resistance (high probe pressure).

Figure III- 10 :

 10 Figure III-10: Measured C m_split (a) and G m_split (b) versus gate bias using split-CV technique at low frequency (20 Hz) on SOI wafer with 88 nm top silicon film thickness and 145 nm thick BOX. Non-passivated top surface. Measurements performed using different probe pressures. Inset of (a): corresponding drain current as a function of gate bias.

Figure III- 11 :

 11 Figure III-11: Effective carrier mobility versus gate bias in case of electrons (a) and holes (b). Characteristics obtained with different probe pressures. μ eff reconstructed from Y function method (p = 80 g) is also shown (dashed line) for comparisons.

  . The measured capacitance (a) and conductance (b) curves as a function of V G for different probe positions are shown in Figure III-12. The corresponding drain current versus gate bias and the probe position on the silicon wafer are shown in the insets of Figure III-12a and Figure III-12b, respectively.

Figure III- 12 :

 12 Figure III-12: Measured capacitance (a) and conductance (b) in split-CV configuration for different probe positions on the silicon film (inset Figure III-12b). Same SOI structure as in Figure III-11. The corresponding drain current versus gate bias curves are also presented in the inset of Figure III-12a.

FigureFigure III- 13 :

 13 Figure III-13a shows the measured capacitance versus gate bias using different numbers of probes. Perfect overlap between the several characteristics is found. Similar results are also obtained for the conductance terms (Figure III-13b). In conclusion, at low frequency, the oxide capacitance dominates the characteristics and effects due to the number of probes play a minor role.(a) (b)

Figure

  Figure III-14 (a) C m_split versus gate bias for different frequency values. (b) Normalized capacitance as a function of angular frequency for different V G . Measurements performed on the same SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. Non-passivated top surface.

Figure III- 15 :

 15 Figure III-15: (a) Equivalent electric circuit of SOI structure (Z EQ ). (b) Equivalent electric circuit used by the LCR meter.

Figure III- 16

 16 Figure III-16 shows the measured (empty symbols) capacitance as a function of gate bias for different frequencies in case of holes (a) and electrons (b). The calculated curves by Eq. (III.13) were also added

Figure III- 16 :

 16 Figure III-16: Measured (empty symbols) and calculated (dashed line, from Eq. (III.13)) capacitance versus gate bias in case of holes (a) and electrons (b) for different frequencies. Measurements performed using two probes on non-passivated SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness.

Figure III- 17 Figure III- 17 :

 1717 Figure III-17 shows the corresponding conductance versus gate bias obtained from Figure III-16 at f = 20 Hz: measured (empty symbols) and calculated (dashed line) characteristics. The light difference in the peak height is due to possible V T mismatch between the computed R CH obtained from I D -V G analysis and split-CV measurements. Diab el al. [97] have shown how the RC model can explain only capacitance characteristics using air back contact and S eff . The use of vacuum back contact allows completing C m_split and G m_split modeling without using any fitting parameter.

Figure III- 18 :

 18 Figure III-18: Hole (a) and electron (b) capacitance as a function of angular frequency for different gate bias. Measurement performed with two probes placed on top silicon film. SOI with 88 nm thick top silicon film and

Figure III- 19 :

 19 Figure III-19: Conductance over angular frequency versus ω associated to the capacitance in Figure III-18 for V G < 0 V (a) and V G > 0 V (b).

Figure III- 20 :

 20 Figure III-20: C m_split (a) and G m_split /ω (b) as a function of angular frequency for different die areas. Same SOI structure as in Figure III-18.

  Figure III-21 shows the capacitance and G m_spit /ω

2 )Figure III- 21 :

 221 Figure III-21: C m_split and G m_split /ω curves versus angular frequency obtained with one probe on the top silicon film. Experimental results (empty symbols) and calculated curves (line) are shown. Same SOI structure as in Figure III-18.

Figure III- 22 :

 22 Figure III-22: Capacitance and conductance G m_split /ω characteristics obtained versus angular frequency in accumulation (a) and strong inversion (b) regime on SOI structure with 12 nm top silicon film thickness and 25 nm BOX thickness. Non-passivated SOI structure. The experimental results (empty symbols) are compared to the calculated curves using our RC model (lines).

Figure III- 23 :

 23 Figure III-23: Capacitance as a function of gate bias measured at low frequency (20 Hz) before (continuous line) and after (symbols-line) HF treatment. Non-passivated SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness.

  decreasing the density of active bonds present on the Si surface. The capacitance terms as a function of gate bias are shown in Figure III-24a. The threshold voltage shifts towards the initial value (continuous line). The peak decreases sharply with time. Almost 16 hours after the treatment, effects due to dangling bonds have become very small. The behavior obtained more than one week after the chemical treatment is very similar to the one measured before the HF clean. The conductance term versus gate bias shown in Figure III-24b suggests the same remarks: V T shift, supplementary peak after HF treatment, recovery of the shape after one week. These experiments clearly demonstrate that split-CV capacitance measurements can detect information concerning surface quality. Consequently, including D it effects in the RC model could be interesting for a future extraction procedure.

Figure III- 24 :

 24 Figure III-24: Capacitance (a) and conductance (b) as a function of gate bias measured at low frequency (20 Hz) at different moments after HF treatment. The characteristic obtained before the chemical process is also shown (continuous line). Same structure as in Figure III-23.

Figure III- 25 :

 25 Figure III-25: (a) Equivalent electric circuit for SOI structure where D it contribution was added. (b) Rearranged equivalent circuit. (c) Parallel electric circuit used during the measurements with the LCR meter.

  Figure III-26 shows the measured C m_split (a) and G m_split (b) as a function of gate bias in case of passivated (empty symbols) and non-passivated (plain symbols) SOIstructure, obtained at low frequency (f = 20 Hz). Beside the typical shifts in V T and V FB[START_REF] Hamaide | Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization[END_REF], no D it signature is detected, since the curves have the same behavior.

Figure III- 26 : 69 FigureFigure III- 27 : 1 (

 2669271 Figure III-26: C m_split (a) and G m_split (b) versus gate bias measured at low frequency (20 Hz). Comparison between passivated (empty symbols) and non-passivated (plain symbols) SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness.

  G p /ω characteristics versus ω have been obtained by standard G m_split -ω measurement performed on non-passivated sample (Figure III-28). Since the low quality of top silicon interface with native oxide, strong impact due to D it was expected. Before the channel formation, the signal is very small and after V FB the creation of accumulation channel covers any possibility of D it detection.

Figure

  Figure III-28 G p /ω as a function of ω for different gate bias values on non-passivated SOI structure (same structure as Figure III-25a). Validation of experimental results comes from modelled curves. Figure III-29a shows the G p /ω obtained without (plain symbols) and with (empty symbols) D it contribution for different gate biases before and after channel formation. The SOI structure was the same as in Figure III-27. The die area was 25 mm 2 .

  ) and (III.18), the RC response of the SOI layer should then be attenuated. We simulated the same system as in Figure III-29a but with decreased die area by a factor of 1000 (0.025 mm 2 instead of 25 mm 2 ). The full symbols in Figure III-29b represent the simulation obtained with D it while the empty symbols are computed without interface trap density. We now note a pronounced influence of D it for gate bias values around flat-band voltage (-3.5 V). In contrast, for gate bias exceeding the flat-band voltage, the effect of interface trap density disappears and the system response becomes again dominated by the RC model. In accumulation regime the curves calculated with and without D it overlap. These simulations indicate that the D it extraction, even for quite large traps density, is not possible in our relatively large SOI samples with 10-50 mm 2 area. Detection of larger D it magnitude is limited by oxide capacitance.

1 Figure

 1 Figure III-29 (a) Modeled G m_split /ω versus ω for different V G around V FB without (empty symbols) and with (plain symbols) D it contribution. The same SOI structure as in Figure III-27 was used. Die area of 25 mm 2 . (b) The same SOI structure as in Figure III-29a has been used with die area equal to 25•10 -3 mm 2 .

[ 54 ]

 54 have proposed for the first time the split-CV technique for the characterization of bare SOI wafers in pseudo-MOSFET configuration. Their work focused on the effective mobility extraction and thanks to a fitting parameter which was the effective surface (S eff ), they have obtained realistic results.

  Figure III-30 shows an example of the measured C m_split (a) and G m_split /ω (b) versus angular frequency on a SOI wafer with 88 nm top silicon film thickness and 145 nm BOX thickness for different gate bias after V T . In case of low V G , the capacitance and G m_split /ω curves are similar to the model. Increasing the gate bias magnitude, a "shoulder" rises up in the measured characteristic. At the same time, G m_split /ω peak decreases and for high V G (i.e., V G = 15 V) a second peak appears at higher angular frequency values.

Figure III- 30 C

 30 Figure III-30 C m_split (a) and G m_split /ω (b) versus angular frequency for different gate bias. The SOI structure had

Figure IV- 1 :

 1 Figure IV-1: High and low frequency capacitance measurements performed on MOS capacitor. D it extracted as a function of energy in a MOS capacitor in case of (111) (A) and (100) (B) p-Si. Conductance (square symbols) and quasi-static (circle symbols) techniques were used [56].

Figure IV- 2 :

 2 Figure IV-2: (a) Measurement setup of QSCV technique for bare SOI wafers in pseudo-MOSFET configuration. (b) Schematic of the gate bias required to achieve QSCV capacitance measurements. Preliminary results of quasi-static characterization performed in pseudo-MOSFET configuration are reported in Figure IV-3. The capacitance (C m_QST ) is obtained as a function of V G using slow (plain symbols)and fast (empty symbols) a.c. scan. In strong inversion or accumulation regimes both measured characteristics reach the C OX value. Around V G ≈ 0 V, two "shoulders" rise up for slow f. These signatures may lead to the investigation of traps present at the interfaces of the top silicon film.

Figure IV- 3 :

 3 Figure IV-3: Measured QSCT capacitance C m_QST as a function of gate bias measured in case of slow (10 mV/s) (plain symbols) and fast (1 V/s) (empty symbols) v ramp_ac . SOI structure with 88 nm top silicon film thickness, 145 nm BOX thickness, and passivated top surface.

Figure IV- 4 :

 4 Figure IV-4: Measured capacitance versus gate bias obtained using LCR meter (plain symbols) and quasi-static technique (empty symbols) on passivated SOI structure with 88 nm thick Si film and 145 nm thick BOX using similar v ramp_ac : 0.5 V/s and 1 V/s, respectively.

Figure IV- 5 :

 5 Figure IV-5: C m_QST as a function of V G in QSCV configuration. Characteristics obtained with (plain symbols) and without (empty symbols) using the vacuum system. Analysis performed using two different a.c. ramp speeds: v ramp_ac = 1 V/s (a) and v ramp_ac = 10 mV/s (b). SOI structure with 88 nm thick Si film and 145 nm thick BOX. The top silicon film was passivated.

Figure IV- 6 :

 6 Figure IV-6: QSCV capacitance versus gate bias for different probe pressures. The SOI structure had 88 nm top silicon film thickness and 145 nm BOX thickness. Passivated top surface.

  Figure IV-7b performed using one and three probes on the Si film.

Figure IV- 7 :

 7 Figure IV-7: (a) Measured QSCV capacitance as a function of gate bias using slow v ramp_ac . Two different probes from the same station were used: A (plain symbols) and B (empty symbols). (b) Measured QSCV capacitance as a function of gate bias using one (plain symbols) and three (empty symbols) probes placed on the top silicon film. Characterization performed on the same SOI structure as in Figure IV-6.

Figure

  Figure IV-8a shows the measured capacitance as a function of gate bias using slow a.c. scan speed in Ψ-MOSFET configuration. The analysis of SOI structure with 88 nm thick Si film and 145 nm thick BOX has been started respectively from accumulation (empty symbols) and from strong inversion (plain symbols) regime. After channel formation, the two characteristics overlap at C OX . Between V FB and V T the curve measured from positive V G shows larger instability than for the curve started from accumulation regime. The effects are amplified in case of thin top silicon film (Figure IV-8b for SOI structure with 12 nm Si thickness,

Figure IV- 8 :

 8 Figure IV-8: Measured QSCV capacitance versus V G with two different sweep directions: starting from accumulation (plain symbols) and from strong inversion (empty symbols) regime. Two samples were tested: one with 88 nm top silicon film thickness (a) and another with t Si = 12 nm (b). In both cases the buried oxide was 145 nm thick.

Figure IV- 9

 9 Figure IV-9 shows the simulated QSCV capacitance versus V G in three different configurations: without any defect contribution (continuous line), with a single energy level (dashed line) and a continuumlike energy distribution (point-dashed line) of interface traps density. The used D it magnitude was 10 11 cm -2 in

Figure IV- 9 :

 9 Figure IV-9: Simulated C QST versus gate bias without (continuum line) and with interface traps contribution. A single energy level (D it_s = 10 11 cm -2 , dashed line) and continuum-like (D it_c = 10 11 cm -2 eV -1 , point-dash line) traps energy distribution were used. SOI with 88 nm thick top silicon film and 145 nm thick BOX.

  Figure IV-10a shows C m_QST versus gate bias obtained using different v ramp_ac . Again, the use of slower a.c. ramp speed enhances the D it signature. Figure IV-10b presents the calculated C QST_c_τ capacitance using Eq. (IV.22) for different frequencies. Very similar trends to the experimental results are obtained, validating the evolution with f (or a.c. ramp scan).

Figure IV- 10 :

 10 Figure IV-10: Measured (a) and calculated (b) quasi-static capacitance versus gate bias for varius a.c. ramp speed and frequency, respectively. The passivated SOI structure had t Si = 88 nm and 145 nm BOX. The arrows in Figure IV-10a represents the gate bias values chosen to compute the quasi-static capacitance as a function of a.c.

  Figure IV-10a (vertical arrows). C m_QST_Vg identifies the capacitance values obtained at constant gate bias and they are traced as a function of the a.c. ramp time t m (symbols in Figure IV-11a). t m is computed dividing the bias amplitude ΔV ramp_ac = 50 mV by the a.c. ramp speed (see Figure IV-2b). The exponential fit (dashed line) well matches with the experimental data. Note that for high magnitude of gate bias the characteristics saturate and C m_QST_Vg becomes equal to C m_QST_sat . On the contrary, for V G = -0.1 V and 0.2 V the experimental curve is not yet complete. In this

Figure

  Figure IV-11b shows the measured τ Dit (plain symbols) obtained from the fitting performed in Figure IV-11a as a function of gate bias.The carriers time constants computed using Eq. (IV.20) are also presented (dashed line). These values were calculated using v th = 10 7 cm/s and σ T = 10 -21 cm -2 , which are typical orders of magnitude for deep traps[START_REF] Vuillaume | Oxide traps in Si-SiO2 structures characterized by tunnel emission with deep-level transient spectroscopy[END_REF]. The two characteristics have similar behavior. For large V G magnitude, τ Dit sharply decreases. In this region, the traps respond fast. Between V T and V FB , τ Dit increases implying that deep traps are hard to detect. In case of experimental results (plain symbols) the curve saturates at V G ≈ 0 V. The lowest a.c. measurement ramp is 3 mV/s. Hence, traps with time constant larger than 16 s (50/3 = 16 s) cannot be detected. Contrary, the computed τ Dit (dashed line) increases to very large values that cannot be measured.

Figure IV- 11 :

 11 Figure IV-11: (a) C m_QST_Vg versus t m for different gate bias: V G = -0.5 V, -0.3 V, -0.1 V, 0.2 V and 0.4 V. Experimental data (symbols) from Figure IV-10a and exponential fit (dashed lines). (b) Corresponding traps time constants obtained from the exponential fit performed in Figure IV-11a (symbols) versus gate bias. Calculated values using Eq. (IV.20) are also reported (dashed line).

Figure IV- 12 :

 12 Figure IV-12: Measured quasi-static capacitance versus gate bias at T = 90 K for different a.c. ramp speed. The passivated SOI structure had 88 nm thick Si film and 145 nm thick BOX.

Figure IV- 13 :

 13 Figure IV-13: (a) C m_QST obtained on the same wafer as in Figure IV-12 as function of V G . Measurements performed using slow v ramp_ac (10 mV/s) and different temperatures. (b) Computed C QST_c_τ versus gate bias for different temperatures.

Figure

  Figure IV-14b shows the extracted interface trap density obtained from Figure IV-10a (plain symbols)for v ramp_ac = 5 mV/s as a function of gate bias. Slow ramp speed was used to reduce attenuation effects due to frequency impact. U-shape defects distribution is found (similar to Figure IV-1b). A valley appears around 0 V because the corresponding traps are too slow to be completely detected (τ Dit too long).

Figure IV- 14 :

 14 Figure IV-14: (a) Extracted traps profile as a function of gate bias using our procedure (plain symbols) and the high-low frequency method (empty symbols). Data from Figure IV-3. (b) D it versus V G extracted from slow (v ramp_ac = 5 mV/s) QSCV measurement discussed in Figure IV-10a using our approach (Eq. (IV.27)) (plain symbols). The dashed line represents the density of free charges induced by V G expressed in cm -2 eV -1 .

  One possibility to overcome the underestimation of slow traps magnitude arises from the exponential fit discussed in Figure IV-11a, where the capacitance measured at constant gate bias values C m_QST_Vg where exponentially fitted as a function of a.c. ramp time t m . 5-steps procedure is required: -Perform quasi-static measurements with different v ramp_ac (see inset in Figure IV-15a); -Extract the capacitance values at fixed gate bias (arrows in the inset in Figure IV-15a); -Trace the measured capacitance at constant V G (C m_QST_Vg ) as a function of t m (inset in Figure IV-15b); -Exponentially fit the results (Eq. (IV.24)) as a function of t m (dashed line in the inset in Figure IV-15b); -Use C m_QST_sat , which is frequency independent, instead of C m_QST in Eq. (IV.27) to compute D it values.

FigureFigure IV- 15 :

 15 Figure IV-15b shows the obtained interface trap density versus V G in case of slow a.c. measurement ramp speed (empty symbols) and D it computed using C m_QST_sat (plain symbols) from Figure IV-11a. Note that the curves overlap far from V G = 0 V. A light difference is present close to 0 V, when the measurement v ramp_ac was not slow enough to avoid τ Dit effects, leading to D it underestimation. In summary, for rapid D it characterization, one measurement performed using slow a.c. ramp speed is sufficient for the detection of traps far from the mid-gap (empty symbols in Figure IV-15b). To better detect the whole defect distribution, including also very deep traps, an exponential fit based on different v ramp_ac characteristics is necessary (plain symbols in Figure IV-15b, 5-steps procedure). This procedure can be limited by noise. Furthermore, it can only predict traps that contribute, at least partially, during the scan. In the next sections of this chapter, the D it extrapolated using this exponential fit will be labeled "projected D it ".(a) (b)

Figure IV- 16

 16 Figure IV-16 shows several C m_QST (V G ) curves measured on non-passivated SOI structure with 88 nm thick silicon film and 145 nm thick BOX using the same v ramp_ac . Each characteristic was started from different positive gate bias values. Changing the starting point obviously affects the peak present at V G < 0 V.

Figure IV- 16 C

 16 Figure IV-16 C m_QST as a function of V G for slow a.c. scan speed. The characteristics were started from different positive gate bias values. The SOI structure had 88 nm top silicon film thickness and 145 nm BOX thickness. The top surface was non-passivated. C peak identifies the measured capacitance peak obtained before channel formation.

Figure IV- 17 Figure IV- 17 :

 1717 Figure IV-17 shows the results for passivated (a) and non-passivated (b) top surface. V G_charge had no impact on the characteristics of passivated samples showing that no new defects were created. In case of non-passivated top surface, however, the longer the applied charging bias, the higher the C peak . t s around 3000-4000 s leads to the peak height saturation. The procedure is obviously not affecting the film-BOX interface since the passivated samples show no variations. It is only active for the non-passivated surfaces. However, it is still not clear, if new defects are generated or only charged.(a) (b)

Figure IV- 18 :

 18 Figure IV-18: C m_QST as a function of gate bias before (line) and after (plain symbols) applying V G_charge = 10 V for 3000 s. The characterization performed 6 hours after the end of the second measurement is shown (empty symbols). The SOI structure had 88 nm thick Si film, 145 nm thick BOX and non-passivated top surface.

Figure IV- 19 :

 19 Figure IV-19: Measured C peak (a) and corresponding bias value V G_peak (b) as a function of t s on the same SOI structure as in Figure IV-17b. Three different charging biases V G_charge were applied for different t s : 10 V, 20 V and 30 V.

Figure IV- 20 :

 20 Figure IV-20: C m_QST versus gate bias for different t s and V G_charge = 10 V. The SOI structure had 12 nm thick Si film and 145 nm thick BOX. Non-passivated top surface.

Figure IV- 21 :

 21 Figure IV-21: C peak (a) and V G_peak (b) as a function of t s . Three different charging biases were applied: 5 V, 10 V and 15 V. Same SOI structure as in Figure IV-20.

Figure IV- 22 Figure IV- 22 :Figure IV- 23 :

 222223 Figure IV-22 shows the measured C m_QST as a function of gate bias before (a) and after (b) filling the traps on non-passivated SOI structure. The capacitances were measured using different v ramp_ac . The use of lower a.c. scan speed reveals more defects, as for passivated samples (see Figure IV-10a). After the charging procedure (V G_charge = 10 V for 3000 s) the impact of v ramp_ac is smaller for V G < 0 V, as shown in Figure IV-22b.In the next two sections the traps profile will be extracted in both configurations: before and after charging the defects. The exponential fit procedure describe in Sec. IV.5 will be used to extrapolate the D it profile (projected D it ) and compute the corresponding τ Dit .(a) (b)

Figure

  Figure IV-24a presents the obtained D it profile versus V G computed on measured QSCV characteristics (v ramp_ac = 3 mV/s) after charging procedure (empty symbols). The defects profile obtained before filling the traps are also reported for comparison (plain symbols). The curves overlap. No clear effects due to filled traps is evidenced.

FigureFigure IV- 24 :

 24 Figure shows the projected D it versus V G obtained from characteristics measured before (plain symbols) and after (empty symbols) charging the traps. The extraction was performed using the exponential fit discussed in Sec. IV.5. The defects profile obtained after applying V G_charge = 10 V for 3000 s is larger than the one computed before filling the defects. The charging procedure made accessible slow traps which could not be predicted before.The analysis is supported by the computed τ Dit versus gate bias (inset in FigureIV-24a). After filling the traps, τ Dit decrease and the analysis can be performed on all the V G range (no exponential fit failure). The charging procedure makes D it prediction easier.

Figure IV- 25 :

 25 Figure IV-25: Extracted D it versus gate bias in case of passivated (empty symbols) and non-passivated (plain symbols) silicon layer. The SOI structure had 88 nm top silicon film and 145 nm BOX. QSCV measurements performed using v ramp_ac = 3 mV/s and without charging procedure.

FigureFigure IV- 26 :

 26 Figure IV-26a shows 1-C m_QST /C OX (step 2) measured in case of different v ramp_ac . The curves have a general bell-shape. The presence of a second peak rising up in some characteristics (see for example v ramp_ac = 3 mV/s and 10 mV/s) evidences the presence of deep traps that are not completely detected. Integrating 1-C m_QST /C OX (step 3, Eq. (IV.1)), the surface potential as a function of V G can be computed (Figure IV-26b). Ψ S for silicon should be around 1.1 V [5]. The values obtained from experimental results are higher than expected. In case of fast a.c. ramp speed the situation becomes even worse.(a) (b)

Figure

  Figure IV-27b shows the calculated δΨ S /δV G as a function of V G for different D it density. Higher defect concentrations lead to smaller and wider peak (w δΨ increases while h δΨ decreases). Comparing calculated and experimental results, two problems rise up: -In case of experimental results (see Figure IV-26a), slower a.c. ramp leads to smaller h δΨ but the measured w δΨ is almost constant; -Including in the simulations w δΨ measured from experimental results (es. from Figure IV-26a), the obtained peak height is much smaller than the measured h δΨ .

Figure IV- 27 :

 27 Figure IV-27: (a) Mesh of the vertical SOI structure used in FlexPDE®. (b) Computed δΨ S /δV G versus gate bias in case of different D it placed at the interface between the top silicon film and the BOX.

29 )Figure IV- 28 :

 2928 Figure IV-28: (a) Measured C m_QST and corresponding derivative of 1-C m_QST /C OX with respect to the gate bias traced as a function of V G . The associated 1-C m_QST /C OX as a function of V G is shown in Figure IV-26a. The interpads distance yields w δΨ . (b) w δΨ (symbols) and corresponding fit (line) versus D it computed using FlexPDE® for the same SOI structure as in Figure IV-28a.

Figure IV- 29

 29 Figure IV-29 shows Ψ S versus gate bias computed from Eq. (IV.1) (plain symbols) and using our procedure (line). The data in Figure IV-28a was used. More realistic potential values are obtained with the proposed approach. Ψ S saturates for large V G (strong inversion and accumulation regime), while it is directly proportional to the gate bias in the linear region.

Figure IV- 29 :

 29 Figure IV-29: Ψ S versus gate bias computed from experimental results in Figure IV-28a using Eq. (IV.1) (empty symbols) and using our procedure (line).

  Figure IV-30 shows the extracted D it versus energy in case of 88 nm (empty symbols) and 12 nm (plain symbols) thick silicon film. The samples have 145 nm BOX thickness. Passivated (a) and nonpassivated (b) SOI were tested. To simplify the comparison, the same data are replotted in Figure IV-30c and Figure IV-30d for the same SOI film thickness but with different top surface quality. D it for passivated samples (Figure IV-30a) present the typical U-shape behavior [125]. The two traps magnitudes are similar despite the variation of t Si thickness, underlining that the technique is actually mostly sensitive to the silicon film-BOX interface. However, the detection is not complete, since some deep defects cannot be measured (valleys in the curves of Figure IV-30a) Higher density of traps was measured for the non-passivated samples (Figure IV-30b). In the lower part of the band gap the measured D it shows a peak absent in case of passivated surface. This peak is sharper for ultra-thin silicon film (empty symbols in Figure IV-30b), probably due to the stronger coupling between the top surface and the conduction channel. The shape is in agreement with P b centers studied in the literature for oxidized silicon with too low annealing temperature (see Figure IV-31a). Also in that case very large D it

Figure IV- 30 :

 30 Figure IV-30: D it computed versus E-E V in case of 88 nm (empty symbols) and 12 nm (plain symbols) top silicon film thickness. The BOX thickness was 145 nm. Passivated (a) and non-passivated (b) top surface, (c) thick Si film and (d) thin silicon layer. Comparing the D it density obtained around mid-gap in Figure IV-30c and Figure IV-30d (E-E V ≈ 0.6V), it seems that the non-passivated surface has lower defects density than the passivated one (es. dashed line in Figure IV-30c). To investigate the reason behind this measurement artefact, Figure IV-31b

Figure IV- 31

 31 Figure IV-31 (a) Example of D it behavior due to P b centers obtained on MOS capacitor using QSCV as function of energy, which is referred to the intrinsic level E i [124]. (b) τ Dit versus E-E V for passivated (empty symbols) and non-passivated (plain symbols) SOI structure. Extraction performed in the data discussed in Figure IV-30c.

Figure IV- 32 Figure IV- 32 :

 3232 Figure IV-32 shows the extracted D it level versus energy in case of passivated (empty symbols) and non-passivated (plain symbols) silicon surface. SOI structures with 25 nm thick BOX were used. The top silicon film had (100) (a) and (110) (b) crystal orientation and 12 nm thickness. The passivated wafers (empty symbols) show again the U-shaped behavior. A valley before mid-gap is obtained, resulting from the difficulty to characterize slow defects located in this region. The wafers with non-passivated top surface (plain symbols), for both crystal orientations, evidence P b center peaks in the lower part of the energy band associated to poor top SiO 2 quality (native oxide).(a) (b)

Figure IV- 33 :

 33 Figure IV-33: D it extracted versus energy for non-passivated (a) and passivated (b) SOI surface. The structures had 12 nm top silicon film. The buried oxide was 25 nm (plain symbols) and 145 nm (empty symbols) thick.

Figure V- 1

 1 shows an example of the current (I) measured as a function of time. I should be equal to 1μA but in reality it oscillates. This is due to the presence of noise sources. To overcome the problem, conventional tools like amperemeter, LCR meter or Source Measurement Unit (SMU) give averages of the measured quantities (see Integration time in Sec.

Figure V- 1 : 1 )o

 11 Figure V-1: Example of noise fluctuations in a resistor under constant current flow I [135].

Figure V- 2 :

 2 Figure V-2: Representation in the time domain of a signal modeled by several harmonics in the frequency domain [138].

characteristics resulting in 1 /

 1 f behavior in the frequency domain (Figure V-3b).

Figure V- 3 :

 3 Figure V-3: (a) General trend of S Id versus frequency in case of generation-recombination noise (Lorentzian-like behavior from Eq. (V.5)). (b) S Id as a function of f where different Lorentzian characteristics were added together leading to flicker noise [135].

  Assuming that trapping or detrapping phenomena are the dominant sources of noise, a change of flatband voltage impacts the electric field in the channel, thus the carrier mobility. A universal expression of S Id can take into account both effects: the fluctuations of carrier concentration (McWhorter's model) and the associated impact on the mobility term (α sc •μ eff •C OX ) [148]:

  Figure V-4a shows the measured S Id versus f for different V G . Clear 1/f trend was obtained, proving that flicker noise can be detected also in SOI substrates using adjustable probe pressure contacts. Figure V-4b shows the S Id /I D 2 versus drain current. A plateau is present for low I D ( in weak inversion regime) followed by 1/I D decrease for higher drain current. This behavior is specific to the CNF model.

Figure V- 4 :

 4 Figure V-4: (a) S Id versus frequency for different gate bias values. (b) S Id /I D 2 versus drain current for different probe pressure. The same SOI structure with 88 nm thick silicon film and 145 nm thick BOX was used in both cases. The top surface was non-passivated [55].

Figure V-6aoo

  Figure V-6a shows the measured power spectrum versus f in case of constant drain current (I D = 107 nA) (line) and at I D = 0 A (dashed line). S Id at zero current represents the system noise. 1/f behavior is added as eye-guide. The obtained spectrum is clearly dominated by flicker noise. For low frequency values, S Id obtained using I D > 0 is much higher than S Id at I D = 0. Thus, the LFN signal induced by trapping/detrapping effects can be unambiguously identified. Increasing f, the two curves merge so the flicker noise cannot be isolated. As for standard MOSFET, it is not possible to perform the extraction in the high frequency range[START_REF] Theodorou | Low frequency noise in advanced CMOS/SOI nanoscale multi-gate devices and noise models for applications in electronic circuits[END_REF]. The steps necessary to compute S Id /I D 2 and determine the interface traps density are: o Perform several S Id versus f measurements using different I D values. In case of Ψ-MOSFET configuration, the drain current was swept by changing the applied V G (V D was kept at 100 mV); o Chose an extraction frequency f ext , the same for all the characteristics; S Id at f ext are collected for different I D ; o S Id /I D 2 is then calculated and traced versus I D .

For comparing the obtainedFigure V- 6 : 2 •

 62 Figure V-6: (a) Measured S Id versus f in case of constant drain current (line) and I D = 0 V (dashed line). 1/f is also added as eye-guide. (b) S Id /I D 2 •f ext versus I D for different extraction frequencies. The SOI structure had 88 nm silicon film thickness and 145 nm BOX thickness. The top surface was non-passivated and positive gate bias was applied. An example of defects extraction procedure is shown in Figure V-7a. S Id /I D 2 is traced as a function of drain current obtained from the data in Figure V-6b. The characteristic reconstructed from static drain current multiplied by S Vfb is also added (empty symbols). Good overlap is achieved for S Vfb ≈ 2.5•10 -9 V 2 /Hz.

α SC = 5 • 10 4Figure V- 7 :

 5107 Figure V-7: S Id /I D 2 versus drain current obtained from Figure V-6 (plain symbols). The characteristic computed from static I D -V G and multiplied by S Vfb was added (empty symbols). Good overlap is found using S Vfb = 2.5•10 -9 V 2 /Hz. The inter-probe distance was d = 1 mm. (b) S Vfb was calculated as a function of I D using Eq. (V.11) (plain symbols) and Eq. (V.9) (empty symbols), respectively. The data presented in Figure V-7a was used.

Figure V- 8

 8 Figure V-8 shows S Id /I D 2 versus drain current with (dashed line) and without (line) using the vacuum system on the metallic chuck in case of positive (a) and negative (b) V G . The corresponding (g m /I D ) 2 as a function of I D are presented in the insets. Even if S Id /I D 2 characteristics are lightly different, it is possible to conclude that the quality of the back contact cannot be the main reason behind the large D it values obtained

ForFigure V- 8 :

 8 Figure V-8: S Id /I D 2 versus drain current in case of electrons (a) and holes (b). The characteristics obtained without (line) and with (dashed line) the vacuum system are compared. Measurements performed using different needles of the same Jandel® station are also shown (dash-dot line). SOI structure with non-passivated 88 nm top silicon film thickness and 145 nm BOX thickness. The corresponding measured (g m /I D ) 2 versus drain current are shown in the insets. The probes affect the obtained S Id /I D 2 . Is the reproducibility between measurements responsible? The negative answer is documented in Figure V-9. Three different dies on the same SOI structure were tested. The curves clearly overlap. Even if the probe quality affects the characteristics (see Figure V-8), the use of the same needles ensures good reproducibility of measurements. Thus, in the following sections all the comparisons will involve only curves obtained with same probes.

  Figure V-9: S Id /I D 2 versus I D obtained from different dies coming from the same wafer. Same SOI as in Figure V-8.

Figure V-10aFigure V- 10 :

 10 Figure V-10a shows the measured S Id /I D 2 versus drain current in case of electrons for non-passivated surface. Different probe pressures were tested. The SOI structure had 88 nm top silicon film thickness and 145 nm BOX thickness. To isolate only the pressure impact, the probes were placed on the silicon surface and the pressure was increased step by step, without moving them. The characteristics are almost pressure independent, after p = 50 g. The same analysis was performed on a passivated sample (Figure V-10b). The pressure values are different because in case of passivated top silicon film the 4 nm dry oxide requires higher p for good ohmic contact. Stronger pressure dependency is obtained in this case. The higher the pressure, the lower the measured S Id /I D 2 plateau. Note also that for 100 g the curve does not show the typical CNF behavior anymore. (a) (b)

Figure V- 11 :

 11 Figure V-10b were used. S Vfb obtained in case of non-passivated surface is almost independent of I D and p, making it suitable for N t extraction. On the contrary, for the passivated samples, the flat-band voltage power spectrum is not constant and strongly dependent to p.

Figure V-12aoo

  Figure V-12a shows the measured S Id /I D 2 versus drain current in case of non-passivated (plain symbols) and passivated (empty symbols) SOI wafers. The characteristic on non-passivated sample was performed using the optimum pressure (p = 80 g). In case of passivated surface, the measurements were obtained using similar probe pressure (p = 75 g, circle symbols) and comparable access resistance (p = 100 g, triangle symbols). For large I D , the current power spectrum obtained for passivated samples is larger than for non-passivated one. Note that S Id /I D 2 term contains both D it and N t contributions. Figure V-12b shows the corresponding S Vfb . The conclusion is not clear. However, comparing the curves with similar pressure, the large difference obtained in the S Id spectrum between passivated and non-passivated samples is reduced, especially for large I D . Two conclusions arise from here: o The defects related to the probe pressure play an important role; o Passivated surface seems more complicated to analyze, so we focus on the non-passivated wafers for the next sections.

Figure V- 12 :

 12 Figure V-12: (a) S Id /I D 2 versus drain current in case of non-passivated (plain symbols) and passivated (empty symbols) SOI structure. The data discussed in Figure V-10 were used. (b) The corresponding S Vfb extracted using Eq. (V.9) are shown. Inset: Measured S Id versus f in case of passivated and non-passivated samples [55].

Figure V-13aFigure V- 13 : 9 Table V- 1 :

 1391 Figure V-13a compares S Id /I D 2 versus drain current obtained for different inter-probe distance: 1 mm, 2 mm and 3 mm. To perform these characteristics we were forced to use different needles, because it is not possible to change the probe position in the Jandel® station. The curves present similar behavior and the plateau position is in the same interval. Only for large drain current values significant variations are present, probably due to different access resistance impact [158]. The corresponding S Vfb as a function of drain current is shown in Figure V-13b. Light S Vfb variation is found. Table V-1 shows the S Vfb values obtained at constant I D (dashed circle in Figure V-13b) and the calculated S using Eq. (V.12): S =f G •d 2 . The flat-band voltage power spectrum variation is very small with respect to the real surface variation. Consequently, the inter-probe distance plays a secondary role on LFN characteristics.

Figure V- 14

 14 Figure V-14 compares S Id /I D 2 (a) and corresponding S Vfb (b) versus drain current measured using different die areas. Despite a significant variation of real die surfaces, the obtained S Vfb values are close. Only very large die (8 x 8 mm 2 ), where parasitic factors limit the analysis, has a lower noise.

Figure V- 14 :

 14 Figure V-14: S Id /I D 2 (a) and corresponding S Vfb (b) as function of drain current in different die areas. The same SOI structure as in Figure V-13 was used.

A 2 -Figure V- 15 :

 215 Figure V-15: Mesh of the computed structure with source and drain contacts. R 0 = 200 μm and die surface equal to 2 mm x 2 mm. The inter-probe distance is 1 mm. 3000 nodes were used for meshing.

Figure V-16bFigure V- 16 :

 16 Figure V-16b presents the computed S Id /I D 2 versus I D using different probe radius R 0 : 1 μm, 5 μm and 10 μm. For low I D , more than one decade difference is found between the characteristics. Comparing Figure V-16a and Figure V-16b, it is obvious that R 0 induces S Id /I D 2 plateau shift comparable to N t effects. (a) (b)

Figure V-17aFigure V- 17 :

 17 Figure V-17a shows the AFM image of tip crater on non-passivated silicon surface. The vertical cross section taken at the line in Figure V-17a is presented in Figure V-17b. The probes leave a trace on the silicon surface with radius ≈ 5-6 μm. In reality, however, the effective contact dimensions should probably take into account the irregular tip penetration depth (Figure V-17b). This is more complicated to evaluate. For simplicity reasons, we assume R 0 to be given by the crater radius on the surface, and we will perform the main comparisons with the experimental trends using R 0 = 5 μm. (a) (b) 50.3nm

Figure V-18a

  Figure V-18a shows the computed S Id /I D 2 versus I D for different N t and D it . In this case, the fast and slow traps are directly related by D it = λ•N t . The lowest plateau is achieved for N t = 10 18 cm -3 eV -1 . The increase of the defects density (N t = 10 19 cm -3 eV -1 ) leads to higher plateau position. N t = 10 20 cm -3 eV -1

Figure V- 18 :

 18 Figure V-18: (a) Computed S Id /I D 2 versus I D for different N t values. The calculations were performed using D it = λ•N t . The corresponding (g m /I D ) 2 as a function of drain current is shown in Figure V-18b. In this case the characteristics represent only the static contribution, thus N t has no impact.

Figure V- 19 :

 19 Figure V-19: Computed S Id /I D 2 versus drain current in case of different inter-probe distance (a) and die area (b).

Figure V- 20 :

 20 Figure V-20: Calculated whole die area (dashed line) and S eff_LNF (line) versus die length. The detailed explanation is given in Figure V-21a, where the distribution of the current power density (σ•ξ 2 ) on the silicon surface is shown. In order to enhance the effects, small sample surface (2 mm x 2 mm) and large probe radii (R 0 = 200 μm) were used. Most of the LFN signal arises from the regions around the two contacts where the power current density is localized. Consequently, for LFN in Ψ-MOSFET, only a small percentage of the silicon surface delivers most of the S Id /I D 2 signal. Figure V-21b presents the current density (σ•ξ) distribution for the same sample. Contrary to the LFN distribution, σ•ξ is much more homogenous over the whole die area, confirming that I D -V G characterization is less sensitive to the region around the contacts.

Figure V- 21 : 2 ) 2 _redFigure V- 22 :

 212222 Figure V-21: Power current density (a) and current density (b) computed on the same die. The sample surface was 2 mm x 2 mm and R 0 = 200 μm. The unnatural behavior at the edges of the structure is due to border effects coming from meshing.

Figure V- 23 :

 23 Figure V-23: S eff_LFN versus R 0 for different die areas.

Figure V-24a

  Figure V-24a shows the evolution in time I D (V G ) curves. The corresponding V T , subthreshold swing and D it (extracted from I D -V G ) are reported in Table V-3. Clear variations of both quantities are detected. Immediately after the treatment many free carriers and dangling bonds are present on the top silicon surface [63], inducing strong V T lowering and poor subthreshold slope. The regrowth of the native oxide gradually attenuated these effects: a V T shift is measured, accompanied by subthreshold swing improvement. LFN characterization was performed in parallel and S Id /I D 2 versus drain current curves are shown in Figure V-24b.

Figure V- 24 :

 24 Figure V-24: (a) Drain current versus gate bias performed at different moments after HF treatment. The corresponding S Id /I D 2 as a function of I D are shown in Figure V-24b. Non-passivated SOI structure with 88 nm thick top silicon film and 145 nm thick BOX.

Table V- 3 :Figure V- 25 :

 325 Figure V-25: S Vfb computed form Figure V-24 versus drain current immediately after the HF treatment (plain symbols) and after surface stabilization (empty symbols).

Figure V-26aFigure V- 26 :

 26 Figure V-26a presents the drain current versus V G before (plain symbols) applying V G of 10 V for 3000 s. The characterization was repeated after the end of the procedure (empty symbols). The filled traps induce a V T shift of about 0.4 V. Furthermore, the subthreshold swing remains almost constant: 0.61 V/dec before charging and 0.613 V/dec after it. The corresponding detected noise signal versus I D is shown in Figure V-26b. Before charging (plain symbols), the S Id /I D 2 plateau is lightly higher than after it (empty symbols).(a) (b)

Figure V- 27 :

 27 Figure V-27: Computed S Vfb versus drain current before (plain symbols) and after (empty symbols) charging procedure. The data shown in Figure V-26 was used.

2 _tot

 2 Figure V-22a. Localized defects (N t_added ) were added only in the corona regions between R 0 and ΔR 0 , to mimic the supplementary defects generated by needle penetration inside the film. The whole LF-noise signal (S Id /I D 2 _tot ) will be the sum of the noise term arising from the silicon film (S Id /I D 2 ) and the contribution of the defects due to the probe penetration: S Id /I D 2 _red . Figure V-28a shows the computed S Id /I D as a function of drain current for different N t_added magnitudes. D it = 10

Figure

  Figure V-28b presents the total noise power spectral density S Id /I D 2 and its componets versus N t_added . The continuous horizontal line shows the genuine LFN spectrum without tip induced defects (N t_added = 0) in case of N t = 10 19 cm -3 eV -1 and N t = 10 20 cm -3 , respectively. S Id /I D 2 _red term increases linearly with the density

1 Figure V- 28 : 2 _tot 2 _tot

 12822 Figure V-28: (a) The total S Id /I D 2 _tot versus I D obtained from the Si film when different induced defects densities N t_added were added around R 0 . (b) S Id /I D 2 is traced as function of N t_added in two different configurations: N t = 10 19 cm -3 eV -1 (black line) and N t = 10 20 cm -3 eV -1 (red line). The noise power spectrum only due to N t_added term is also shown (dashed line). S Id /I D 2 _tot is computed versus N t_added for both N t cases (red dotted line): S Id /I D 2 _tot = S Id /I D 2 + S Id /I D 2 _red .

Figure V- 29 2 )

 292 Figure V-29 presents relative contribution (S Id /I D 2 _red )/(S Id /I D 2 _tot ) and (S Id /I D 2 )/(S Id /I D 2 _tot ) versus contact radius for two different probe induced defects density: N t_added = 10 20 cm -3 eV -1 (continuous line) and N t_added = 10 21 cm -3 eV -1 (dashed line). The impact of the generated defects is very strong but it exponentially decreases as a function of needle radius. In case of N t_added = 10 20 cm -3 eV -1 (line), using very large contacts (i.e., R 0 ≈ 100 μm -200 μm) the contribution due to induced defects is almost negligible ((S Id /I D 2 _red )/(S Id /I D 2 _tot) term tends to 0). Unfortunately, high N t_added (dashed line) still dominates the whole LF-noise signal also in case of large R 0 , making the interface quality characterization not possible.

Figure V- 29 :

 29 Figure V-29: (S Id /I D 2 _red )/(S Id /I D 2 _tot ) and (S Id /I D 2 )/(S Id /I D 2 _tot ) versus R 0 for N t_added = 10 20 cm -3 eV -1 (line) and N t_added = 10 21 cm -3 eV -1 (dashed line).

41 Figure AI- 1 :

 411 Figure AI-1: Schematic of Van Der Pauw measurement. The current I 12 (a) and I 23 (b) are injected and the voltage V 34 and V 41 are measured, respectively.

4 )[

 4 , B) V (I , B) V (I , B) V (I , B) Knowing the current direction, the sign of V H,24 allows to determine the doping type of the material. The Hall voltage V H,24 and Hall current I H (average between I 31 and I 13 ) lead to the calculation of the Hall coefficient

Fig. 3 :Fig. 4 :

 34 Fig. 3 : (a) Capacité quasi-statique mesurée en fonction de la tension de grille V G avec vitesse de balayage rapide (symboles vides) et lente (symboles pleins). (b) D it en fonction de l'énergie dans de échantillons passivés avec une épaisseur de BOX de 25 nm (symboles pleins) et 145 nm (symboles vides).

Table I -1: Near-term 2013-2020 challenges defined by ITRS 2013. Table adapted from the document [8].

 I

  1 The state-of-art in SOI electrical characterization ................................................................... II.2 Principle of Ψ-MOSFET and parameter extraction methods .................................................. II.3 Impact of measurement ........................................................................................................... II.3.1 Measurement time setup .................................................................................................. II.3.2 Quality of back contact .................................................................................................... II.3.3 Role of the probes ............................................................................................................ II.3.4 Passivated top silicon film ............................................................................................... II.4 Extension of Ψ-MOSFET to new materials: III-V-on-insulator ..............................................

II.4.1 Material characterization before bonding ........................................................................ II.4.2 Ψ-MOSFET with pressure probes on III-V-on-insulator (III-V-OI) ............................... II.4.3 Ψ-MOSFET with metal contacts on III-V-OI ................................................................. II.4.4 Preliminary results of III-V transistors ............................................................................ II.5 Conclusions and perspectives ..................................................................................................

  3.1. The role played by the back contact is addressed in Sec. II.3.2, while the impact of adjustable pressure probes on the characteristics is pointed out in Sec. II.3.3. Section II.3.4 shows the role of the quality of the top silicon film surface.

Table II-2: Low-field mobility of electrons and holes computed from Figure II-11b and corresponding R SD for different probe pressures.

	Pressure (g)	μ 0 electron (cm 2 /Vs)	R SD electron (kΩ)	μ 0 hole (cm 2 /Vs)	R SD hole (kΩ)
	40	420	7.5	147	22
	60	449	5.1	128	11
	80	460	3.3	150	13
	90	461	2.6	153	12

Table II

 II

	Pressure (g)	μ 0 (cm 2 /Vs) vacuum	μ 0 (cm 2 /Vs) no vacuum
	40	443	195
	50	462	309
	60	426	454
	70	509	713
		-3 shows the extracted low-field electron mobility
	obtained from characteristics measured with and without vacuum back contact for different probe pressure. p
	variation of ≈ 40 % induces almost 20 % μ 0 shift using vacuum back contact. In case of standard
	configuration, the variation is higher than 70 %, proving the importance of using the vacuum system,
	especially for ultra-thin films.

Table II -3: Measured low-field mobility for different p and V G > 0 V. Characterization performed on SOI wafer with 12 nm top silicon film and 145 nm BOX. The top surface was non-passivated. Comparison between measurements obtained with and without vacuum.

 II

Table II-4: Extracted parameters from Figure II-12b for different needle properties.

	0 hole (cm 2 /Vs)	154	137	29
	V FB (V)	-2.3	-2.9	-2.3
	θ 1 electron (1/V)	0.018	0.033	0.054
	θ 1 hole (1/V)	0.089	0.01	-

  17 cm-3 . As previously, the contacts were made of Indium droplets. The measured μ Hall (plain symbols) and doping concentration (empty symbols) are reported in Figure II-17 as a function of t III-V . N D is also affected by the III-V thickness variation and further research is in progress to explain why the effective doping is smaller in thinner sample.

Table II -

 II 5. Again, a strong difference between the two characterization techniques is found. In this case the calculated r H is between 2.7 and 3, which is still large but more reasonable. Since μ 0 is mostly proportional to 1/t III-V , it is dominated by phonon scattering.

	Die	N d (cm -3 )	μ Hall (cm 2 /Vs)	μ 0 (cm 2 /Vs )
	A	6.4•10 17	775	285
	B	6•10 17	760	246
	C	6.1•10 17	737	248

Table II -5: Measured N d , Hall and low-field mobility for three different dies on the same wafer. Structure schematic in the inset of Figure II-23b. T an = 600 ºC. The measurements were performed at ambient temperature.

 II To perform the measurements at different temperature T, the contacts prepared for the Hall effects were used. The two needles (source and drain) were placed in two diagonal corners. Thus, I D flow was measured. Figure II-23a shows the results. Note that the thick BOX requires very large gate bias values to achieve full characterization. However, the range V G supported by the instrument is ± 10 V, thus the characteristics are not complete.

	The low-field mobility can be extracted using the Y function method on the measured I D -V G
	characteristics. The geometrical factor is derived comparing the resistivity measured with two probes placed
	in diagonal contacts and the Van der Pauw technique (Appendix I). Equation (II.2) can be rewritten in a
	general form as:
	G    f	V I 	(II.13)
	where f G is a general geometrical factor. The material resistivity is determined using Van der Pauw
	technique. Hence, applying a current between two diagonal probes and measuring the differential potential
	ΔV, Eq. (II.13) allows the calculation of f G . In this case we obtained:
	G f 0.26 	(II.14)

Table III -

 III

	88/145	5.7	1.9	0.33
	12/145	5.7	1.9	0.33
	83/25	33.1	2.1	0.06
	12/25	33.1	2.6	0.08

1: Calculated oxide capacitance (C OX •S) with Eq. (III.1) for different SOI structure with passivated top surface. The measured capacitance values are shown (C max_air ). The corresponding S eff is calculated with Eq. (III.8) for each structure.

Table III -2: Calculated oxide capacitance (C OX •S) using Eq. (III.1) for different die areas, compared with the measured maximum electron capacitance obtained from Figure III-8 using vacuum (C max ) and air back contact (C max_air ) from Figure III-6a.

 III

		1	1.3	0.9
	9.6	2.3	2.6	1.5
	17.8	4.2	4.4	1.7
	24	5.7	5.8	1.9
	65.6	15.6	16.1	2.2

Using air contact, the results for different SOI thicknesses were not clear. To pursue with the investigation, Table

III

-1 has been enriched with the maximum capacitance obtained with vacuum back contact on the same structures (see Table III-3). C max is always close to C OX •S, for all top-silicon film thicknesses and BOX thicknesses.

Table III -3: Table III-1 enriched with the corresponding maximum capacitance C max obtained performing the characteristics on the same structure using vacuum back contact.

 III The natural question becomes: does the quality of the back contact affect μ eff extraction?

	Silicon film/BOX	C OX •S	C max_air (nF)	C max (nF)
	(nm/nm)	(nF)	Air contact	Vacuum contact
	88/145	5.7	1.9	5.8
	12/145	5.7	1.9	5.8
	83/25	33.1	2.1	32.2
	12/25	33.1	2.6	32.9

  ramp_ac induces charge variations in the conduction channel; ΔI is measured and leads to capacitance values[108]. This configuration allows performing characteristics at slow equivalent frequency f (i.e., few mHz). To perform correct analysis, it is important to verify that leakage currents are negligible through the oxide of the device under test.

Typical examples of low frequency (C lf ) and high frequency (C hf ) capacitance traced as a function of gate bias are reported in Figure

IV-1a

  To perform correct interface quality extraction, S Vfb thus N t , has to be independent of the extraction frequency f ext . Figure V-6b shows S Id /I D 2 •f ext versus drain current for different f ext . In case of low current

	2 m 22 Id DD S g S Vfb II 	(V.11)
	Equation (V.11) clearly shows that S Id /I D 2 is proportional to two terms: (g m /I D ) 2 and S Vfb . The static
	characteristic (g m /I D ) 2 is dominated by the subthreshold slope, therefore, it is sensitive to fast traps called D it
	in this chapter. On the contrary, the flat voltage power spectrum (S Vfb ) is directly proportional to N t (deep
	traps in Eq. (V.8)). Thus, on the S Id /I D 2 curve, both contributions of fast and slow traps are present. In order
	to separate them, (g m /I D ) 2 is evaluated from static measurements. After performing noise measurements, S Vfb
	is computed from the ratio (S Id /I D 2 )/(g m /I D ) 2 . Consequently, it only contains N t term as shown in Eq. (V.8)
	[156].

  Vfb_area is the normalized flat-band voltage spectrum density: S Vfb_area = S Vfb /S. The effective volume (Ω eff ) in Eq. (V.[START_REF] Fenouillet-Beranger | Efficient multi-VT FDSOI technology with UTBOX for low power circuit design[END_REF]) represents the region where the noise is concentrated:

	2  	FB V     	2		Vfb _ area S	(V.20)
	where S 2
		2	d
		
	eff	4	d
		
							18)
	Merging Eq. (V.16) and Eq. (V.18), it is possible to write S Id /I D 2 expression:
	24 2 d      2 d            22 Id D S 1 I 	(V.19)
	To complete the derivation, it is required to include also the conductivity fluctuations. 𝛿𝜎 2 ̅̅̅̅̅ associated
	to carrier number variation (CNF model) is [135]:

Table V -

 V 2 summarizes the main input parameters used in FlexPDE®, knowing that: o The chosen magnitudes (t OX , t Si , μ …) are close to the realistic values measured in pseudo-MOSFET The computation part will focus on SOI structure with 88 nm top silicon film thickness and 145 nm BOX thickness. The LFN signal is calculated for V G > 0 V, as in the experiments.

	configuration; o The interface trap contributions are included using two different terms: D it (fast traps) in the current computation and N t (slow traps) which is present only in the LFN term (Eq. (V.23)); Value / Range BOX thickness t OX 145 nm Top silicon film thickness t Si 88 nm Low-field carrier mobility μ 0 450 cm 2 /Vs Interface trap density (fast traps) D it 10 10 -10 12 cm -2 eV -1 Deep traps used for LFN computation N t 10 18 -10 20 cm -3 eV -1 Traps added in a localized region for LFN calculation N t_added 10 18 -10 22 cm -3 eV -1 Tunneling attenuation length λ 1 Å Die length, square samples (L = W) L 1 mm -10 cm Probe radius R 0 1-200 μm Radius added to R 0 to generate a corona region ΔR 0 1-200 μm Inter-probe distance d 1-3 mm o Parameters Drain bias V D 100 mV

Table V -2: Summary of input parameters required for FlexPDE® computation. Preliminary results

 V

Preliminary simulation results are shown in Figure V-16a. S Id /I D 2 is computed as a function of drain current for different N t values. Note that D it term was kept constant. The three curves have the same shape but higher N t induces higher S Id /I D 2 plateau level. This is in agreement with Eq.(V.23). Keeping constant D it , the change of N t induces only a S Vfb variation, thus a S Id /I D 2 vertical shift.

  12

Table of Acronyms

 of

	Acronym	Nomination
	Acronym QSCV RC	Quasi-static capacitance measurements Nomination Resistance -capacitance (model)
	a.c. RTS	Alternative signal Random telegraph signal
	AFM Si	Atomic Force Microscope Silicon
	Al SiO 2	Aluminum Silicon-dioxide
	As SOI	Arsenic Silicon-on-insulator
	Au Ti	Gold Titanium
	BOX UTBB	Buried oxide Ultra-thin body and buried oxide
	CMOS WC	Complementary MOS technology Tungsten carbide alloy
	CNF III-V	Carrier number fluctuation (model) Label for In 53% Ga 47% As layer
	CMF III-V-OI	Carrier mobility fluctuation (model) III-V film on insulator
	d.c. Ψ-MOSFET	Constant bias term Pseudo-MOSFET
	div	Divergence
	DUT	Device under test
	FDSOI	Fully depleted SOI transistor
	FET	Field Effect Transistor
	FFT	Fast Fourier Transform
	Ga	Gallium
	Ge	Germanium
	grad	Gradient
	HgFET	Mercury contacts FET
	HF	Hydrofluoric acid
	In	Indium
	HMF	Hooge mobility fluctuation (model)
	InGaAs	In 53% Ga 47% As, Indium-Gallium-Arsenide alloy
	LFN	Low-frequency noise
	MOS	Metal-oxide-semiconductor
	MOSFET	Metal-oxide-semiconductor field effect transistor
	NBTI	Negative bias temperature instability
	Ni	Nickel
	NID	Non-intentionally doped
	Os	Osmium
	PBA	Programmable Biasing Amplifier
	PDSOI	Partially depleted SOI transistor
	PSD	Power spectral density

Table of Constants 156 Table of Constants

 of156of

	Symbol	Value / Unit (in SI)	Description
	k	1.38 × 10 -23 m 2 kg s -2 K -1	Boltzmann constant
	j	-	Complex unit
	q	1.6•10 -19 C	Unit charge
	v th	10 7 cm/s	Thermal velocity
	ε 0	8.85•10 -12 F/m 2	Vacuum permittivity
	ε OX	3.9•ε 0 F/m 2	SiO 2 permittivity
	ε Si	11.8•ε 0 F/m 2	Silicon permittivity

  Parallel capacitance between C Inv and C Dit in case of split-CV technique

	Table of Symbols
	Symbol	Unit (in SI) Description
	B
	B	T	Applied magnetic field
	C
	C OX	F/m 2	Oxide capacitance
	C Si	F/m 2	Silicon film capacitance
	C Inv	F/m 2	Inversion channel capacitance
	C GC	F	Gate-to-channel capacitance
	C GC_max	F	Maximum measured C GC
	C GS	F	Gate-to-substrate capacitance
	C m_split	F/m 2	Measured parallel capacitance for split-CV measurements
	C max	F	Measured maximum capacitance in case of Ψ-MOSFET configuration
	C max_air	F	Measured maximum capacitance in case of Ψ-MOSFET configuration with air back contact
	C Dit_c	F/m 2	Capacitance due to D it in split-CV configuration for continuous energy traps distribution
	C p	F/m 2
	C LF_MOS	F/m 2	Low frequency capacitance measured in MOS structure with QSCV technique
	C m_QST	F/m 2	Measured QSCV capacitance
	C QST	F/m 2	General expression for QSCV calculated capacitance
	C QST_s	F/m 2	Total quasi-static capacitance for single energy level of interface traps
	C it_s	F/m 2	Interface traps capacitance in case of single energy level of defects distribution (QSCV technique)
	C it_c	F/m 2	Interface traps capacitance in case of continuum energy distribution of defects (QSCV technique)
	C QST_c	F/m 2	Total quasi-static capacitance for continuum-like energy distribution of interface traps
	C it_c_τ	F/m 2	Interface traps capacitance for continuum-like energy distribution of defects taking into account frequency effects
	C QST_c_τ	F/m 2	Total QSCV for continuum-like energy distribution of interface trap density including frequency effects
	C QST_LCR	F/m

2

Complete expression of capacitance term measured in pseudo-MOSFET configuration taking into account traps time constant and τ RC

Table of Symbols 158 Symbol Unit (in SI) Description

 of 'énergie dans le gap du silicium. Les mesures ont été réalisées sur des couches de passivation de SOI (4 nm de SiO 2

			Table of Symbols
	Symbol Symbol Symbol Name fonction de l	Unit (in SI) Description Unit (in SI) Description Unit (in SI) Description Unit (in SI) Description
	C m_QST_Vg I D R 0 δV FB Greek Symbols F/m 2 A m V	Measured quasi-static capacitance at constant V G Drain current Probe radius Small flat-band voltage variation
	C m_QST_sat I 0 ΔR 0 V T α H	F/m 2 A m V -	Saturation QSCV capacitance obtained by exponential fit of C m_QST_Vg Constant current value time independent Added radius to R 0 Threshold voltage Hoogle parameter
	C it_QST δI R H ΔV diff α sc	F/m 2 A m 3 /Ω V Vs/C	Capacitance of D it obtained from experimental results Current oscillations Hall coefficient Differential potential measured between two probes Coulomb scattering coefficient
	C peak I off r H V H β I on S v ramp_ac γ	A -V eV -1 F/m 2 A V -	Peak of measured capacitance value obtained during charging procedure in Off current in case of transistor characteristic Hall scattering factor Hall voltage β = q/(k•T) case of non-passivated surface On current in case of transistor characteristic a.c. scan speed in case of QSCV measurements Slope of 1/f (S Id (f) characteristic)
	D I H S W η	A m 2 F/cm 2	Hall current Die area: S = W•L Ideality factor constant; 1/2 for electron, 1/3 for holes
	D it L S eff w δΨ ϑ	cm -2 eV -1 --m -2 s -1	Interface trap density Effective surface for capacitance measurements Width of δΨ S /δV G curve versus V G Constant given by: σ T •f s
	D it_s L S Id Y θ 1	cm -2 m A 2 /Hz 1/V	Density of traps for a single energy level of defects Die size Drain current power spectral density First order mobility attenuation factor
	D it_eq E N N D S Vd S Vfb Y X λ	cm -2 eV -1 cm -3 V 2 /Hz V 2 /Hz (V/A) 0.5 m	Equivalent interface traps density computed using FlexPDE® Doping concentration in case of n-type material Voltage power spectral density Flat-band voltage power spectral density Y function Tunneling attenuation length calculated using Wentzel-Kramers-Brillouin (WKB)
	E N a S Vfb_area x dep μ 0	eV cm -3 V 2 /(Hz•m 2 ) m cm 2 /Vs	Energy Doping concentration in case of p-type material Flat-band voltage power spectral density per unit area Depletion region Low-field carrier mobility
	E eff N probe S Vg Z μ eff	V/cm -V 2 /Hz cm 2 /Vs	Effective electric field Number of probes Power spectral density associated to the gate bias (input-inferred noise) Effective carrier mobility
	E G ΔN S eff_LFN Z EQ μ 0_T=77K	eV -m 2 Ω cm 2 /Vs	Band gap Average fluctuation of carrier number Effective surface of LFN technique Equivalent impedance Low-field mobility measured at T = 77 K
	E V N t S Id /I D 2 _red μ 0_at_0V	eV cm -3 eV -1 1/Hz cm 2 /Vs	Maximum energy value of valence band in case of silicon film Density of traps per unit volume Reduced S Id /I D 2 obtained in smaller regions surrounding the probe contacts Low-field mobility measured with V back = 0 V
	F N t_added S Id /I D 2 _tot ξ	cm -3 eV -1 1/Hz V/cm	Density of traps added in localized regions Whole current spectrum given by S Id /I D 2 + S Id /I D 2 _red Electric field
	F N C S s ρ N V T σ T	cm -3 V/dec Ω•m -cm -3 m -2	Correction factor in 4-probe measurements for non-infinite layer Effective density of states in the conduction band Subthreshold swing Material resistivity dimensions Effective density of states in the valence band Carrier cross section
	f n it T σ	Hz cm -3 K S/m	Frequency Density of filled traps Temperature Conductivity
	f G n S T an δσ	0.75 cm -3 ºC S/m	Geometrical factor in pseudo-MOSFET configuration Electron density at surface Annealing temperature Conductivity fluctuations
	f s n i t OX σ Dit P t m τ Dit	cm -3 m m -2 Hz s s	Frequency at which carriers oscillate between the conduction channel and Intrinsic carrier concentration Oxide thickness Traps cross section the traps Measurement time period of QSCV small signal ramp (a.c. ramp time) Trap effective life time
	f T P t τ RC	-W s s	Probability that the interface traps are filled Power Time RC time constant
	f c p t Si Ψ S	Hz g m V	Corner frequency in case of Lorentzian spectrum Probe pressure for Jandel® station Silicon film thickness Surface potential
	f ext Q t s Ψ b	Hz s V	Extraction frequency in case of LFN analysis Charging time Bulk potential deduced from the doping concentration
	f conf Q i t III-V Ω C	-C/m 2 m V	Configuration coefficient for Van Der Pauw measurements Inversion charge density III-V film thickness Term for low-frequency noise analysis defined as: α sc •μ eff •C OX_cm
	G Q acc V Ω	C/m 2 m 3	Accumulation charge density Die volume
	G m_split Q Dep V D Ω eff	S/m 2 C/m 2 V m 3	Measured parallel conductance in case of split-CV measurements Depletion charge density Drain bias Effective Volume
	G p Q itrap δV G Q ch V G ω	C/m 2 V S/m 2 C/m 2 V rad/s	contribution Trapped charges by defects in case of continuum energy traps distribution Small gate bias variation Parallel conductance in case of split-CV measurements including also D it Total density of charge induce by gate bias Gate bias Angular frequency
	G Dit_c G Q itrap_s V gacc V G_peak	S/m 2 S V C/m 2 V	Conductance due to lossy processes of D it in split-CV technique Conductance Trapped charges by defects in case of single energy level of traps Lower limit of integral to compute μ eff , in accumulation region distribution Gate bias associated to C peak_h
	g m R V G_charge	S V	Transconductace; g m = dI D / dV G V G applied for a certain time t S (charging bias)
	H R SD ΔV ramp_ac	Ω V	Access resistance Small signal ramp added to V G to perform QSCV measurements
	h δΨ R CH V back	-Ω V	Height of 1-C m_QST /C OX curve versus V G Channel resistance Back gate bias in case of transistors
	I R SH V FB	Ω/square V	Sheet resistance Flat-band voltage
			159

Acknoledgementes

iii Acknowledgements I would like to thank all the members of the jury for the time spent to evaluate this work and attend my Ph.D defense. Their comments/remarks allowed me to further improve this manuscript and gave me interesting ideas for future research. Thank you, Prof. Cristell Maneux, Prof. Alexander Zaslavsky, Prof.

Jean-Pierre Raskin and Dr. Frédéric Allibert.

I would like to thank my supervisors, Prof. Sorin Cristoloveanu and Prof. Irina Ionica, for constant support and teaching. Thanks to them I have largely improved my professional knowledge. Moreover, I really appreciated the discussions and relations with them.

Chapter V: Low-frequency noise in Ψ-MOSFET Equation Section (Next)

In this thesis several methods for electrical characterization of interface traps have been discussed.

Their capability to access D it and their limits have been constantly pointed out. Another technique used in microelectronics to investigate interface quality is the low-frequency noise (LFN). It has already been

applied to Ψ-MOSFET configuration but the D it values extracted were too high to be realistic. In this chapter, after a fast review of LFN theory, the impact of experimental conditions will be evaluated. A physical model will be derived and it will be used to explain the measured trends. The limitations of LFN in Ψ-MOSFET configuration will be pointed out and some possibilities for improvement will be presented.

Contents Chapter V

V.2 LFN characterization in Ψ-MOSFET

To understand if the obtained large density of interface traps was due to measurement setup issues, in this section we focus on experiments using different configurations. After presenting the setup (Sec. V.2.1), we will discuss the reproducibility (Sec. V.2.2) and the role of the pressure needles (Sec. V.2.3). Finally, in Sec. V.2.4 the impact of inter-probe distance and die area variations will be addressed.

V.2.1 Measurement setup

Low-frequency noise measurements were performed using adjustable probe pressure Jandel® station.

In order to reduce as much as possible the external noise, the probing tool was placed inside an isolated box, built for this type of analysis. The SOI wafer was contacted using similar configuration as for I D -V G measurements (see Sec. II.2). The source was grounded while V D was applied using a Programmable Biasing Amplifier (PBA) and a low-noise amplifier [START_REF] Chroboczek | Automatic, wafer-level, low frequency noise measurements for the interface slow trap density evaluation[END_REF]. All the results presented in this section were obtained using V D = 100 mV. The PBA was remotely controlled by a PC and simultaneous measurements of the d.c.

drain current I D and the a.c. term δI over a large frequency range (1 Hz to 500 kHz) were performed. The software automatically computes the FFT and releases the S Id (f) term [START_REF] Chroboczek | Automatic, wafer-level, low frequency noise measurements for the interface slow trap density evaluation[END_REF].

Programmable bias amplifier characterizes the Device Under Test (DUT) as a resistor where a constant current is applied (Figure V-5). In case of high resistive materials, to minimizes the impact of the experimental tools on the DUT, the best configuration to measure the noise is at constant current I [START_REF] Trefán | 1/f noise in homogeneous and inhomogeneous media[END_REF].

To apply the gate bias, the PBA has a second source but it is limited at ± 5 V. Diab et al. [START_REF] Diab | Lowfrequency noise in SOI pseudo-MOSFET with pressure probes[END_REF] have overcome the problem using a battery in series with the PBA. This setup is not so accurate. To improve it, a Keithley 236® bias source was preferred to control V G . We have chosen this instrument because the voltage can be swept between -100 V to 100 V with 100 μV step and it generates low noise. In this way, higher V G resolution is obtained albeit the measurement setup becomes more complex and time consuming. The programmable biasing amplifier has to work in parallel with the Keithley 236® and manual (V G ) sweep is required. Figure V-5 summarized our setup.

PC for FFT

Silicon film

Substrate

Effective surface

One of the main problems of the standard pseudo-MOSFET configuration is that the conduction channel is not well defined, as for fabricated transistor. The actual geometry responsible for a measured signal (drain current, LFN, capacitance) was investigated and we proved that the effective areas were not the same from one technique to another.

Thanks to the use of improved setup and to modeling studies, we demonstrated that in capacitance measurements the whole die area responds during the characterization. This means that border effects are not present.

As for I D -V G measurements, the current density is more localized and the width over length ratio of Ψ-MOSFET is classically defined by f G [START_REF] Cristoloveanu | Point-contact pseudo-MOSFET for in-situ characterization of asgrown silicon-on-insulator wafers[END_REF]. Note that placing the source and drain probes too close to the edge of the device, the electrical field distribution on the silicon surface is limited by the die borders and f G is modified. To obtain correct mobility values, the probes must be placed in the middle of the tested die.

For LFN, we proved that the signal mostly arises from small regions surrounding the probes, and this effect is enhanced for sharp tips (as the ones we were using). In order to perform suitable D it extraction, the effective surface must be computed using the physical model discussed in Sec. V.4.2.

D it extraction

Static I D -V G characterization leads to interface traps evaluation. However, its capability is more limited as the thickness of the silicon film decreases. For this reason we investigated other techniques for D it characterization.

Unfortunately, we proved that the LFN signal is mostly affected by the defects induced by the probes and almost independent of the material quality. Larger probes could allow overcoming this issue.

Furthermore, even if capacitance measurements performed using LCR meter lead to correct effective mobility values, information concerning the quality of the interfaces is masked by the RC time constant of the channel (τ RC ). τ RC is associated to the time needed for the carriers to go from the probes to any point in the conduction channel. The minimum measurement frequency (f = 20 Hz) was not slow enough to avoid τ RC effects because of large die areas (S ≈ 4-60 mm 2 ). Consequently, neither capacitance-voltage nor conductance technique could reveal D it signature.

The problem was solved using quasi-static capacitance measurements, which we introduced for the first time in the Ψ-MOSFET configuration. Performing very slow analysis, the signature of deep traps was detected. A physical model was derived and validated for different measuring frequencies and temperatures.

A simple extraction procedure was proposed. Its validity, limitations and extensions were addressed from a practical point of view. Several SOI geometries and surface qualities were tested. In samples with passivated top surface, the obtained D it profiles overlapped, independently of the top silicon film and BOX thicknesses,

proving that the measurements mainly reflect the quality of film-BOX interface. In non-passivated samples, larger density of defects was measured. D it peaks at precise energy values were found for non-passivated top surface.

Appendix IEquation Chapter (Next) Section 1

During this thesis, the Hall mobility (μ Hall ), the material resistivity (ρ) and the active doping concentration (N D or N a ) were measured on a "home-made station", totally dedicated to these experiments [6]. The setup is made of a probe station that can be placed inside a magnetic coil. All the tools required for the characterization (amperometers, voltemeters, etc.) are controlled by computer. The whole experiment consists of three consecutive steps:

1 Contact tests: these tests are required to verify if the contacts between the metallic probes and the material are ohmic. If this is not the case, all the other measurements are useless. A current is applied between two contacts and the corresponding voltage is measured. Linear I-V dependency must be obtained to pursue the characterization;

2 The Van Der Pauw measurement is performed to obtain the material resistivity ρ;

3 Hall effect measurement leads to the Hall mobility μ Hall . The active doping concentration is computed at the end of the characterization, using μ Hall and ρ.

The next two sections describe the working principle of Van Der Pauw and Hall effect measurements.

Van Der Pauw experiments

In order to perform Van Der Pauw measurements, the sample is placed on a metallic chuck and four manual probes (labeled 1, 2, 3 and 4) are used to contact it. Figure AI-1 shows an example. To succeed the characterization, the tested material must have an uniform thickness.

The measurement is performed setting the current between two adjacent probes (for example between probes 1 and 2) and measuring the potential drop between the two others (V 34 ) (see Figure AI-1a). The corresponding resistance can be computed as:

In case of perfectly symmetrical samples (R 12,34 = R 23,41 ), f conf = 1. To increase the accuracy of the analysis, the procedure is repeated injecting the currents I 34 and I 41 and measuring the corresponding voltages V 12 and V 23 . The final resistivity value results from averaging all the obtained ρ.

153

To improve the measurement accuracy, the procedure is repeated injecting the current between 2 and 4 contacts (I 24 and I 42 ) and measuring V 31 . The average of all the obtained results leads to Hall coefficient R H .

R H and the material resistivity ρ (obtained from Van Der Pauw technique) allow the calculation of the Hall mobility [6]:

In conclusion, the doping concentration is computed by: [8], [9]. La dernière partie de cette étude concerne l'évaluation de la qualité des interfaces (D it ) en utilisant la méthode de conductance en fonction de la fréquence. Nos mesures ne montrent pas les pics typiques associés aux D it [10]. Pour mieux en comprendre la raison physique, nous avons effectué des simulations numériques. La Fig. 2b montre la conductance (G m ) divisée par la pulsation (ω), calculée en fonction de ω. Les symboles pleins sont obtenus pour une structure SOI avec D it , alors que les symboles vides sont associés aux simulations sans D it . Après la création du canal de conduction (symboles rouges), les deux courbes se superposent. Dans ce régime, la mesure n'est pas sensible aux défauts d'interface, comme dans les transistors à effet de champ [11]. Pour V G ≈ V FB (tension de bandes-plates), les deux courbes se superposent également (symboles noires).

Nous avons montré qu'en configuration Ψ-MOSFET, la surface des échantillons utilisés est trop grande (≈mm 2 ) et elle masque la détection des défauts d'interface [12]. Donc, la méthode de conductance ne peut pas être utilisée pour évaluer la qualité des interfaces pour les structures SOI typiquement utilisées pour le pseudo-MOSFET. Cette limitation sur la détection des D it peut être dépassée en effectuant des mesures de capacité en quasi-statique (QSCV) [10].