Remy Kussener

Vauche

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Keywords: Radio Frequency Identification, Near Field Communication, Impedance measurement, scattering parameters, modulation

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I. INTRODUCTION

FID (Radio Frequency Identification) consists in communication between a reader device, and an object as a smart card, positioned at some distance away from the reader. The RFID technology is used in many applications such as electronic payment or electronic passport. For 13.56 MHz applications, the reading device is composed of a controller, a Radio Frequency (RF) circuit, and an inductive antenna, which sends a modulated RF signal to the card. The card, also called tag, is composed of a chip (integrated circuit (IC)) and an inductive antenna. In the present paper, we will focus on passive cards, which are remotely powered by the reader. The power is carried by the modulated RF wave sent to the card by the reader as depicted in Fig. 1. Throughout this paper, the frequency of the carrier will be 13.56MHz, which is the Near Field Communication (NFC) operating frequency. However, the measurement setup described here, can be generalized to other frequencies, depending on the acquisition speed of the electronic test instrument.

B. Couraud (e-mail: benoit.couraud@isen.fr), T. Deleruyelle (e-mail: thibaut.deleruyelle@isen.fr) and E. Kussener (e-mail: edith.kussener@isen.fr) are with the Electronics and Numerical technologies Institute (ISEN) based in NFC technology has experienced a strong development in the last few years, mainly consisting in an increase of the data rate from 106 kb/s and 424kb/s to 6.78Mb/s, called Very High Bit Rate (VHBR) communication [START_REF]:2010 -Identification cards --Contactless integrated circuit cards --Proximity cards --Part 2: Radio frequency power and signal interface[END_REF]. This increase in the data rate involves a wider bandwidth for communication signals and a reduction of the quality factor for readers electronic circuits (filters, matching circuits), reducing the power transfer capability between the reader and the tag's IC. Thus, it becomes necessary to reduce power losses inside a PICC (Proximity Integrated Circuit Card) by optimizing the power transfer between the tag's antenna and its IC. One way to reduce these losses is to perfectly match the impedance of the antenna to the impedance of the chip (the antenna's impedance has to be as close as possible to the conjugate of the chip's impedance).

Therefore, when it comes to card manufacturing, an accurate measurement of the impedance of the chip is important in order to optimize the antenna design for power transfer. Unfortunately, the impedance of a card's chip is highly dependent on the power received by the card from the reader, as shown in [START_REF] Bjorninen | Wireless Measurement of RFID IC Impedance[END_REF]- [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF]. These impedance changes are due to the different states in which the input power put the chip (Power on, Reset, Read, Write, cryptographic computation…). Moreover, in order to comply with proximity cards standards (like ISO 14 443, NFC Forum or EMVCo), a smart card manufacturer must ensure that the load modulation tested according to ISO/IEC methods achieves the required voltage load modulation amplitude. This amplitude is directly dependent on the chip impedance changes during a communication, for which no measurement setup have been designed yet. Indeed, these measurements cannot be achieved with standard VNA as standard VNA cannot deliver the needed power to activate the card's chip, and cannot measure the impedance changes because of the very short time steps for load modulation impedance changes. Indeed, as it will be shown in this paper, the accepted power by a chip is above 10 dBm for activation of the chip, and above 25 dBm for the highest state of security mode (clamp state), which correspond to a larger 50Ω signal generator output power, depending on the chip impedance variation, according to (1). Indeed, the power accepted by a chip supplied by a signal generator can be expressed as a function of the incident power from the signal generator of impedance 𝑍 0 :

𝑃 𝑎𝑐𝑐𝑒𝑝𝑡𝑒𝑑 = 𝑃 𝐺𝑒𝑛𝑒𝑟𝑎𝑡𝑜𝑟 50Ω [1 -| 𝑍 𝑐ℎ𝑖𝑝 (𝜔) -𝑍 0 𝑍 𝑐ℎ𝑖𝑝 (𝜔) + 𝑍 0 | 2 ] (1)
In the case of this paper, 𝑍 0 is real and equal to 50Ω. Moreover, the IC load modulation changes during a communication with a reader occur in a very short time (between 10µs and 0.2µs depending on the data rate from 106 kb/s to 6.78 Mb/s). Works presented in [START_REF] Angrisani | A digital signal-processing instrument for impedance measurement[END_REF]- [START_REF] Taha | Digital measurement of the polar and rectangular forms of impedances[END_REF] either do not allow measurement with such power, or are not suitable for the considered RFID frequencies. Hence, alternative impedance characterization techniques have been proposed in [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF], [START_REF] Kantz | Measuring System for Time-Variant Impedances[END_REF]- [START_REF] Jurkus | National standards and standard measurement systems for impedance and reflection coefficient[END_REF], that can be used to determine PICC chips' impedance, but not for different input power, nor during a communication.

In the present paper, these measurement techniques have been enhanced to measure chips' impedance from the switched off state (very low voltage sent to the chip) up to the destruction level, and more importantly during a communication at any ISO 14443 data rate.

Section II presents the chip impedance measurement technique for real time measurements, while section III describes how this method is currently used by industrials to assess their chips characteristics, and then to optimize the antenna parameters for actual smart card devices.

II. IMPEDANCE CHARACTERIZATION SETUP FOR PROXIMITY INTEGRATED CIRCUIT CARDS (PICC)

This section presents the tag IC impedance measurement setup. As it has been explained above, in order to optimize the power transfer between a PICC antenna and its chip, it is necessary to match the antenna to the IC, which can only be done if one knows the chip's impedance at operating voltage. Hence, measuring this impedance is the main goal of the proposed measurement setup.

A. Chip Impedance Model

First, it is necessary to define what chip's characteristics are measured. As introduced in [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF], a PICC electrical model can be used as shown in Fig. 2, with the antenna (Ra, La, Ca), the assembly (R, C) and the chip (Rc, Cc). The aim of a chip's impedance characterization technique is to estimate the equivalent circuit constituted by Rc and Cc.

The capacitance C helps the antenna designer to tune the system at the desired frequency, whereas the resistance Rc is inversely proportional to the power consumed by the chip. In common applications, resistances R and capacitance Ca can be neglected. As presented in [START_REF] Pozar | Microwave engineering[END_REF], the admittance of the chip can be expressed as a function of the reflection coefficient of the chip and the corresponding characteristic impedance, as shown below.

(

) 2
where Z0 is the characteristic impedance generally equal to 50Ω and S11, the S parameter of the chip, in this case equal to the reflection coefficient. The aim of the proposed method is to determine Yc from a one-port S parameter measurement using [START_REF] Bjorninen | Wireless Measurement of RFID IC Impedance[END_REF]. Then, Rc and Cc can be expressed as follows:

(3) [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF] where f is the input signal frequency for the S11 measurement. The method proposed in this paper consists in measuring

B. Chip Characterization Setup

S Rc Zo S   - =    +   Re 11 11 1 1 1 2 1 S Cc f Zo S    - =     +  
Im the impedance of the device under test (DUT), without a VNA (which power limits and long measurement time have been emphasized) but with a directional coupler, an acquisition device (as an oscilloscope) and a Personal Computer linked to the acquisition device, as shown in Fig. 3.

The chips under test used in this paper are actual industrial chips used for electronic passport, and capable of communicating at VHBR (Very High Bit Rates). The measurements throughout this paper are realized at ambient temperature (23°C).

In this setup, a waveform generator is used to generate a 13.56 MHz carrier. It can be a common waveform generator, but it can also be any NFC reader device, as it will be shown later. Incident and reflected waves are extracted by the bidirectional coupler and sent to the oscilloscope. The directional coupler and the oscilloscope act as the coupler and the coherent receiver of an actual VNA, with the advantage that the oscilloscope has a large bandwidth of acquisition. Thus, the oscilloscope acts as an acquisition device that will send the recorded incident and reflected voltages to a computer so it can process them. Any other high sampling rate acquisition device can replace the oscilloscope. In order to make this measurement, it is necessary to connect the chip (tag IC) to the bi-directional coupler. This can be done by mounting the chip on a PCB in a standalone configuration, as shown on Fig. 4. a, where PICC chips are soldered to the PCB at their two antenna connectors, and the PCB adopts a single Coplanar Waveguide with Lower Ground Plane architecture, where no differential input is required as one port is taken as the reference. Then, to extract Rc and Cc, a classical de-embedding technique [START_REF] Packard | Network Analysis. Specifying calibration standards for the HP 8510 network analyzer Product Note A[END_REF] associated to the one-port S parameter measurement is used, which consists in determining the reflection coefficient of the chip from the incident and reflected wave records. The aim of the proposed algorithm is to realize this computation for every quarter of a 13.56 MHz carrier period (chosen arbitrarily, any measurement time step will suit), in order to obtain the chip impedance evolution during each step of a communication, without decreasing the accuracy of the measurement. First of all, the definition of the S-parameter of a device is expressed as follows [START_REF] Collin | Foundations for microwave engineering[END_REF]: [START_REF] Angrisani | A digital signal-processing instrument for impedance measurement[END_REF] where b1 is the reflected wave and a1 the incident wave, that are recorded from the two outputs of the coupler.

However, dividing the reflected voltage by the incident wave voltage will not give accurate results for the Measured reflection coefficient (Γ 𝑀 ) [START_REF] Angrisani | A digital signal-processing instrument for impedance measurement[END_REF]: indeed, it is necessary to calibrate the measurement set up. Three kinds of errors may arise in the measurement of the incident and reflected wave: a directivity error, a tracking error, and a port match error. Fig. 5 displays a one-port device flowgraph that represents all possible signal paths and the errors due to these multiple paths. In this simplified model, errors due to the directional coupler, the cables, connectors, and the acquisition device can be considered as due to a fictitious component placed between the coupler and the Device Under test (DUT), that modifies the incident and reflected waves amplitude and phase. Thus the Measured reflection coefficient Γ 𝑀 includes these error sources, and has to be corrected in order to determine the Chip's real reflection coefficient Γ 𝑐 . One can determine the equation that links the Measured (and thus incorrect) reflection coefficient Γ 𝑀 and the chip's real reflection coefficient Γ 𝑐 as shown in [START_REF]Agilent AN 1287-6 Using a Network Analyzer to Characterize High-Power Components[END_REF]:

𝑆 11 𝑀 = Γ 𝑀 = 𝑏 𝑎 = 𝐴 𝑟 𝐴 𝑖 𝑒 𝑗(𝜑 𝑟 -𝜑 𝑖 ) = 𝑒 00 -Δ 𝑒 Γ 𝑐 1 -𝑒 11 Γ 𝑐 (6)
Where Ar and 𝜑 𝑟 are the reflected wave amplitude and phase respectively, and Ai and 𝜑 𝑖 the incident wave characteristics. Thus,

Γ 𝑐 = Γ 𝑀 -𝑒 00 Γ 𝑀 𝑒 11 -Δ 𝑒 =
𝐴 𝑟 𝐴 𝑖 𝑒 𝑗(𝜑 𝑟 -𝜑 𝑖 ) -𝑒 00 𝐴 𝑟 𝐴 𝑖 𝑒 𝑗(𝜑 𝑟 -𝜑 𝑖 ) 𝑒 11 -Δ 𝑒 [START_REF] Taha | Digital measurement of the polar and rectangular forms of impedances[END_REF] with Δ 𝑒 = 𝑒 00 𝑒 11 -𝑒 10 𝑒 01 [START_REF] Kantz | Measuring System for Time-Variant Impedances[END_REF] In order to determine the three unknown quantities 𝑒 00 , 𝑒 11 and Δ 𝑒 , the method consists in measuring the reflection coefficient Γ 𝑀 of three well-known loads whose real reflection coefficient (Γ 𝑖 ) is known, and to solve the following system for the unknown error coefficients listed above:

{ 𝑒 00 + Γ 1 Γ 𝑀1 𝑒 11 -Γ 1 Δ 𝑒 = Γ 𝑀1 𝑒 00 + Γ 2 Γ 𝑀2 𝑒 11 -Γ 2 Δ 𝑒 = Γ 𝑀2 𝑒 00 + Γ 3 Γ 𝑀3 𝑒 11 -Γ 3 Δ 𝑒 = Γ 𝑀3 (9)
The three loads chosen for this measurement method are the ones shown in Fig. 4. b. One could use standard calibration kit if they can sustain the large input power, but custom kits will take into account the connection and the line between the chip and the coupler, and accept larger incident power. Thus, the self-designed calibration kit example consists of a custom Short Open Load (SOL) calibration kit which has the same footprint as the PCB for the chips, displayed in Fig. 4. a. The Load termination consists in two parallel 100Ω ±1% resistances integrated in TO-220 packages, which allow a precise 50Ω load to be obtained and to be used up to 50dBm which is sufficient if 13.56MHz RFID power level is considered. This arrangement leads to a measure of the reflection coefficient seen from the closest plane to the chip (P1 on Fig. 2). Hence, for this known calibration kit, the real reflection coefficients must be: Γ 𝑂𝑃𝐸𝑁 = 1, Γ 𝑆𝐻𝑂𝑅𝑇 = -1 and Γ 50Ω = 0. Once the measurements of Γ 𝑀_𝑂𝑃𝐸𝑁 , Γ 𝑀_𝑆𝐻𝑂𝑅𝑇 and Γ 𝑀_50Ω have been done, it is possible to solve [START_REF] Couraud | A low cost impedance measurement method for integrated circuits[END_REF] for 𝑒 00 , 𝑒 11 and Δ 𝑒 . Then, computing the real reflection coefficient of a given chip from the measure of incident and reflected voltages can be done using [START_REF] Taha | Digital measurement of the polar and rectangular forms of impedances[END_REF], where the reflected wave (𝐴 𝑟 𝑒 𝑗(𝜑 𝑟 ) ) and the incident wave (𝐴 𝑖 𝑒 𝑗(𝜑 𝑖 ) ) still need to be determined, as shown below.

The amplitude Ax and phase 𝜑 𝑥 of a signal x can be computed from the voltage data recorded by the acquisition device. The proposed method consists of a Goertzel algorithm [START_REF] Goertzel | An Algorithm for the Evaluation of Finite Trigonometric Series[END_REF] implemented within the processing device (PC) or the acquisition device, that computes the amplitudes and phases of the two voltages (incident and reflected) at every quarter of a carrier period, depending on the sampling rate of the acquisition device. According to [START_REF] Goertzel | An Algorithm for the Evaluation of Finite Trigonometric Series[END_REF], the amplitude and phase of a signal can be computed using a very limited number of operations which makes it ideal for fast computations, and preferred to the Hilbert transform or even a Radix-2 FFT. Furthermore, it requires very few data points to provide an accurate computation of the two signal characteristics. The amplitude Ax N of a signal x and 𝜑 𝑥 𝑁 its phase are given below, with N the block size to achieve a certain frequency resolution:

𝐴 𝑥 𝑁 = √ [𝑄
𝑄 1 𝑖 = 𝑄 0 𝑖-1 (13) 𝑄 2 𝑖 = 𝑄 0 𝑖-2 (14)
𝑄 0 𝑖 = 2 cos ( 2𝑘𝜋 𝑁 ) . 𝑄 1 𝑖 -𝑄 2 𝑖 + 𝑥(𝑖) (15)
with x(i) the incident or reflected voltage sample at time i, which has been windowed numerically using Blackman windowing. k is the size of the required acquisition sample expressed in number of periods of the carrier (if it is needed to acquire 2 periods of data, then k = 2). The computation of the ) is, the more accurate the result will be. The amplitude and phase of incident and reflected waves are computed for each element of the SOL calibration kit so the three error coefficients can be computed using ( 6) and ( 9). Then, ( 7), ( 3) and ( 4) are used to determine the impedance of the Chip Under Test, every quarter of carrier period for example. The setup displayed in Fig. 3 has been implemented using a National Instrument PXI (Peripheral component interconnect eXtensions for Instrumentation) hosting a custom-made transmitter and a receiver, constituted by an FPGA that drives a Digital to Analog Converter for the transmitter, and an Analog to Digital Converter for the receiver. In order to measure the impedance at every quarter of the carrier period, it is necessary to use an acquisition device with a FPGA or to use a high sample rate oscilloscope in order to achieve enough measurements per carrier period. In the 13.56 MHz NFC domain, this requires acquisition devices with acquisition speed above 300 MSample per second to achieve a measurement error below 1%. However, this sampling requirement can be lowered thanks to Goertzel algorithm. Indeed, the Goertzel algorithm gives very accurate results for the amplitude and phase of a signal in the two following cases: either the acquisition device proposes a high acquisition speed, in which case there are enough samples per carrier period to achieve an accuracy below 1%. Either the acquisition rate is close to a multiple of the carrier frequency, while still respecting Shannon criteria. In the 13.56 MHz RFID case, one could consider an acquisition device with a sampling rate of 40 MS/s. This acquisition speed is close to 3 times the carrier frequency, and would lead to 3 samples per carrier period. This would give a measurement error below 5%. Furthermore, the vertical resolution used in this implementation was 12 bits per sample, with a -3dB bandwidth of 2.27 GHz, but could be reduced without affecting the accuracy of the measurement. will be shown later. The setup is displayed in Fig. 6.

In order to validate this measurement setup, passive loads impedance have been measured using a VNA and using the measurement protocol described above. TABLE 1 shows the comparison of the obtained impedance at a single input power, where the accuracy is computed as follows: One can see that these measurements match the impedance measured by the VNA, as the error is comparable to the measurement errors from the VNA. The validation of this method has also been done on 12 real smart cards chips. Then, the same measurements as those obtained in [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF] using a VNA and an amplifier have been realized. Fig. 7 shows a Smith Chart display of a chip impedance measurement when the input power varies. The curves correspond to a measurement realized with the method described in [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF], that uses a VNA and an amplifier, and the measurement as described above. These measurements demonstrate the ability of the proposed method to realize impedance measurements with large power sweep. In this section, a measurement setup has been proposed for measuring 13.56 MHz PICC's IC impedance. The advantages of such a method are that it can measure a chip impedance at any power, and thus in any state of the chip. Also, as it will be presented in the next section, the other advantage of this method compared to other methods already existing is that it has a very small measurement time step, and can be used to detect chip impedance changes even during a communication. Section III will describe the possible characterization of PICC ICs that can be used to assess the design of ICs.

𝑀𝑜𝑑𝑢𝑙𝑒 𝑒𝑟𝑟𝑜𝑟 = | |𝑍 𝑓𝑟𝑜𝑚 𝑉𝑁𝐴 | -|𝑍 𝑛𝑒𝑤 𝑚𝑒𝑡ℎ𝑜𝑑 | | |𝑍 𝑓𝑟𝑜𝑚 𝑉𝑁𝐴 | (16)

III. PROXIMITY INTEGRATED CIRCUIT CARDS CHARACTERIZATION

This section presents the different characteristics of a PICC chip that can be assessed with the proposed measurement setup.

A. Chip Impedance as a Function of Input Power

As it has been shown in [START_REF] Bjorninen | Wireless Measurement of RFID IC Impedance[END_REF], [START_REF] Angrisani | A digital signal-processing instrument for impedance measurement[END_REF], [START_REF] Vera | RFID Test Platform: Nonlinear Characterization[END_REF] a tag's IC impedance highly depends on the supply power. As an example, a measure of a chip's parallel resistance and capacitance as a function of the input power has been realized, and results are shown in Fig. 8. Measurements were validated by comparing them to the values obtained using the measurement setup described in [START_REF] Gebhart | Chip Impedance Characterization for Contactless Proximity Personal Cards[END_REF].

This measurement makes it possible for industrials to determine the impedance of their chip at different states of operation, and thus to determine the impedance to which the antenna of the final tag will have to be tuned. A good choice is to match the antenna to the chip impedance measured at the lowest input power at which the chip is able to reply to a reader request. One can notice that in this case, the antenna will be matched to the impedance of the chip at one particular power. In real life application, that power will correspond to the power received by the chip when the card is at a particular distance from a reader. However, in these real life applications, a smart card is in motion during a communication. By choosing to design the antenna at the lowest power at which the IC responds, all cases will be covered as the need for matching or tuning is smaller when the smart card comes closer to the reader (which corresponds to larger input power). Finally, the orientation between the reader and a card has also an impact on the input power, but is not covered in this work. In addition, these impedance measurements can be done to determine the optimal design for the chip itself, as shown in the following example. The tested chip for this example is a particular chip that operates in a loop mode, at different Integrated Circuit (IC)-clock frequencies. The jitter deviation level defines these clock frequencies. The larger the jitter is, the lower the operating clock frequency will be (and the performance), and thus, the lower the consumed power will be. Measurements have been done for a large range of input power; > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < and for every power level used, the chip's impedance was measured. These measurements are displayed in Fig. 9. This figure presents the evolution of the impedance (Rc and Cc) as a function of input power and of the operating clock frequency of the chip. Since the power consumed by the chip decreases when the parallel resistance increases, Fig. 9 demonstrates the advantages of implementing a lower clock frequency for the chip in terms of power consumption. As mentioned above, it also makes it possible for the manufacturer to know precisely the impedance of the chip for different operating states. Fig. 9 shows also that the parallel resistance of the given chip is close to constant until the clock frequency falls below 80%. This allows the chip software designers to know that a clock frequency between 80 and 100% will consume the same amount of power, meaning that for a low power mode, the clock rate will have to be decreased below 80%. Finally, the setup has also been applied to assess the uniformity of chips impedance produced by a production line, so the manufacturer can assess the reliability of its production line and detect failures before integrating the chips into a tag. One can see on Fig. 10 that one sample behaves differently from the others, and thus has been rejected. The other chips present a good uniformity, which is important as the same antenna will be used for every chip. Up to this point, the measurements shown have been realized by sending only a single frequency signal at 13.56 MHz on the chip test, and do not give any information about the behavior of a chip when a reader device sends a request, nor what is the exact power at which the chip begins to respond to a request. The next part describe how the measurement method proposed in section II allows chip designers to measure the impedance of their chip during a communication, which gives useful information on the chip's power consumption, and on its ability to communicate when integrated into a tag.

B. Chip Impedance during a Communication 1) Measurement Setup

To realize the measurements of the PICC IC impedance changes during a communication and especially during the load modulation phase, the waveform generator displayed in Fig. 3 has been replaced with a NFC reader. Using this updated measurement setup, the NFC reader's output power is increased until a communication is established with the chip under test through the directional coupler. This communication can be at any data rate, low or VHBR, which requires a negotiation phase. As presented above, the algorithm used computes the impedance at every quarter of carrier period, which makes it suitable to measure a chip impedance even during the load modulation phase at a data rate of 6.78 Mb/s. Thus, using a high sample rate acquisition device, the incident and reflected waves available at the outputs of the directional coupler were recorded from the beginning of the transmitter (NFC reader) request at 1.7Mb/s, until after the end of the chip answer at 3.39Mb/s. The recorded incident and reflected waves are displayed in Fig. 11. With these two incident and reflected waves, one is now able to compute the chip impedance at every quarter of a period, as presented in section II.

2) Impedance Changes during Load Modulation

The results of the impedance computation as a function of time are displayed in Fig. 12. One can see the chip's impedance variations during the reader request phase (due to different input power, as amplitude modulation is used), during the processing phase, and also during the backscattering load modulation > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < phase. During the processing time, the PICC is still harvesting energy, but is also consuming more power, as the parallel resistance is low. Indeed, the parallel resistance, in black in Fig. 13 and 14, represents the consumption of the chip during the communication. Moreover, the parallel capacitance follows the resistance changes in order to maintain a stable power supply of the chip.

Finally, determining this resistance at the lowest communication power allows antennas manufacturers to define the optimized parameters for good power transfer. Hence, the impedance variation in the load modulation phase of the communication can be measured accurately, and can reveal useful information about the ability of the smart card to comply with ISO/IEC 14443 PICC signal transmission requirements for example.

3) Non Linear Characterization

Up to this point, only the carrier frequency was considered to compute the chip's impedance. However, [START_REF] Vera | Redundant backscattering modulation of passive UHF RFID tags[END_REF] shows that due to the presence of the rectifier circuit, an UHF RFID chip has a nonlinear behavior, that affects the response of a tag by reflecting not only the carrier frequency, but also its odd harmonics, and especially the 3 rd one. The same applies to 13.56 MHz RFID systems and can be assessed by taking the power spectral density of the tag response recorded by the acquisition device, which is realized in Fig. 15. One can see the presence of the 3 rd and 5 th harmonics due to the RF to DC conversion, that constitute a power loss at the fundamental frequency, as presented in [START_REF] Vera | RFID Test Platform: Nonlinear Characterization[END_REF].

Finally, according to [START_REF] Vera | RFID Test Platform: Nonlinear Characterization[END_REF], changing the matching between the antenna and the chip could optimize the reflection of odd harmonics of the carrier, and thus increase the efficiency of the system.

4) Smart Card Electro-Magnetic Security

Finally, the last useful information given by this measurement method consists in a very useful security information. Indeed, as one can see in Fig. 12, the chip's impedance during processing (between the reader request and the chip load modulation phase) stays constant, and does not give any information about the ongoing computations of the chip. This characteristic is needed for robustness to hacking situations, in which hackers could determine the chip calculations by decrypting the electrical characteristics during the processing state, as shown in [START_REF] Mahanta | Power analysis attack: A vulnerability to smart card security[END_REF].

IV. CONCLUSION

The method proposed in this article allows most of laboratories to realize their own smart card's IC impedance measurements during a communication with a reader, with common and inexpensive measurement devices. The frequency range of this measurement set up is only restricted by cables quality, distortion of power amplifier and by the sampling frequency of the acquisition device. The results of this method are as accurate as those provided by VNA based setups. Besides, compared to VNA, it also allows designers to measure a chip's impedance at required powers, at very short time steps, and even during a communication. With VHBR evolution, engineers will need to measure accurately chips' impedance in order to optimize the power transfer between antenna and IC in Smart Cards applications (impedance matching). As presented above, this method provides the necessary information to realize this matching, in addition to information about robustness of smart cards IC to power analysis attacks, or about backscattering impedance, that can be used by designers to assess if their chip will comply with load modulation standard requirements. This is why this method of Real Time impedance measurement during communication and over a large power range is a necessary tool that is used to optimize the design of NFC devices.

Fig. 1 .

 1 Fig. 1. Principles of Contactless Smart Card Operation. Power is provided by the reader, and harvested by the antenna of the tag. Data is exchanged in both directions (upward and downward).

Fig. 2 .

 2 Fig. 2. Electrical Model of a PICC

Fig. 3 .

 3 Fig. 3. Setup for Chips Impedance Measurements

Fig. 4 .

 4 Fig. 4. PICC chips mounted in a PCB for characterization (a) and custom calibration kit (b)

Fig. 5 .

 5 Fig. 5. Flow Graph of a One Port Device

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  𝑄 0,1,2 𝑖 coefficients is done for every time sample (i), until 𝑄 0,1,2 𝑁 can be computed to determine the amplitude 𝐴 𝑥 𝑁 and phase 𝜑 𝑥 𝑁 of the considered signal 𝑥. Thus, every N samples, the ratio between the incident and reflected signals is computed. The higher the number of sample per period ( 𝑁 k

Fig. 6 .

 6 Fig. 6. Measurement Environment

Fig.

  Fig. Comparison between Chip Impedance Measurements by the two methods for a large range of input power (0 to 30 dBm)

Fig. 8 .

 8 Fig. 8. Chip impedance as a function of the input power (50 Ω)

Fig. 9 .

 9 Fig. 9. Chip Impedance measurement as a Function of the input power (50 Ω) and the Clock Frequency

Fig. 10 .

 10 Fig. 10. Comparison of ICs impedance from the same Production Line of industrials manufacturers as a function of input power (50 Ω) from -10 to 25 dBm (low power range as requested by the manufacturer to not stress the ICs)

Fig. 11 .

 11 Fig. 11. Incident and Reflected Waves during a VHBR Communication

Fig. 12 .

 12 Fig. 12. Chip Impedance Evolution (parallel resistance Rp and capacitance Cp) during a VHBR Communication with Reader Request at 1.7 Mb/s and Load Modulation at 3.3Mb/s

Fig. 13 .

 13 Fig. 13. Chip Impedance Evolution during a VHBR Communication with Load Modulation at 106kb/s. In black, parallel resistance evolution during time, in gray the parallel capacitance

Fig. 14 .

 14 Fig. 14. Zoom on the Chip Impedance evolution during the processing and at the beginning of the chip response

Fig. 15 .

 15 Fig. 15. Power Spectral Density of the Reflected Response of the Tag

TABLE 1 .

 1 Real Impedance and Measurements Comparison

	Impedance from VNA method (Ω)	Impedance from new method (Ω)	Module error (%)	Phase error (%)
	99.96 + j0.3	99.86 + j0.3	0.1	3.4
	0.46 + j22.1	0.12 + j22.7	2.7	1.0
	0.9 -j458	2.1 -j449	1.9	0.2


R Vauche
email: remy.vauche@univ-amu.fr

R Assila
email: rym.assila@im2np.fr

Belhadj Mefteh

F Haddad

F Wan

B Ravelo

S Lalléchère

P Thakur
email: pthakur@ggn.amity.edu

A Thakur
email: athakur1@ggn.amity.edu

Keywords: BP) negative group delay (NGD), Microwave circuit, Time-domain, Test method, li-topology

This paper details a time-domain (TD) test to visualize impacts on the double-li microstrip circuit behavior of its bandpass (BP) negative group delay (NGD). To determine the central frequency and the bandwidth of the input signal to use during the TD test, a frequency domain (FD) S-parameter analysis of the circuit has been done. This preliminary analysis, carried out first with the aid of simulations and then with the aid of measurements, shows a NGD for a frequency band of 15 MHz (resp. 8 MHz) around 2.345 GHz (resp. 2.364 GHz). To observe in the TD the NGD impact around 2.345 GHz, TD experimentations have been performed using a 2.345 GHz sine carrier shaped by Gaussian pulses. During these TD tests, the BP NGD signature was verified thanks to the output envelopes which presents rising and falling edges in time-advance compared to the input ones. It was also experimentally shown that the output is normally delayed when the input sine carrier is outside of the li-circuit NGD frequency bands.

I. INTRODUCTION

HE GROUP DELAY (GD) estimation [START_REF] Kumar | Time-domain analysis of cross correlation for time delay estimation with an autocorrelated signal[END_REF], which can be defined as the signal envelope delay estimation, is one of the challenging tasks to perform an efficient time-domain (TD) analysis of microwave structures based on transmission lines (TLs) [START_REF] Kouhpayeh-Zadeh-Esfahani | Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Transmission Line Excited by an Arbitrary Modulated Signal[END_REF][START_REF] Sánchez-Alegría | Time Domain Electromagnetic Transient Analysis of Aerial Nonuniform Transmission Lines Excited by an Incident Electromagnetic Field[END_REF]. Indeed, whereas the GD is usually measured in the frequency domain (FD) using a vector network analyzer (VNA) from the transmission parameter, the GD estimation in the TD from the envelope measurement [START_REF] Ben-Yaakov | Envelope simulation by SPICE-compatible models of linear electric circuits driven by modulated signals[END_REF] of modulated signals [START_REF] Kouhpayeh-Zadeh-Esfahani | Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Transmission Line Excited by an Arbitrary Modulated Signal[END_REF] requires investigations. This is all the more important that a TD analysis is particularly interesting to understand the impact of the NGD which can be obtained with several coupled line (CL) structures [START_REF] Chang | Transient analysis of lossless-coupled transmission lines in a nonhomogeneous dielectric medium[END_REF][START_REF] Heh | Multiple LOD-FDTD Method for Multiconductor Coupled Transmission Lines[END_REF].

Recent studies report that unfamiliar negative group delay (NGD) functions have been designed with CL-based microstrip circuits [START_REF] Ravelo | Negative Group Delay Theory on li Topology[END_REF][START_REF] Wan | 0IO-Shape PCB Trace Negative Group-Delay Analysis[END_REF]. It has been emphasized from a FD analysis that the CL li-topology [START_REF] Chang | Transient analysis of lossless-coupled transmission lines in a nonhomogeneous dielectric medium[END_REF] constituted by two parallel I-shape lines is susceptible to have a NGD in function of the CL effective length. However, the interpretation of the NGD function remains an open question for non-specialist electronic and microwave design engineers.

One of the easiest manners to describe an electronic function in terms of NGD is based on the analogy with the filters [START_REF] Zhou | Analytical Design of Dual-Band Negative Group Delay Circuit with Multi-Coupled Lines[END_REF]. Using it, a low-pass NGD function has a NGD for low frequencies and a positive GD (PGD) for high frequencies. The behavior of a low-pass NGD function has been recently illustrated with TD measurement [START_REF] Ravelo | Similitude between the NGD function and filter gain behaviours[END_REF]. It was also emphasized that rising and falling edges of the output signal have been observed in time-advance compared to the input ones when baseband signals are considered [START_REF] Wan | Time-Domain Experimentation of NGD Active RC-Network Cell[END_REF]. But so far, bandpass (BP) NGD functions which can be obtained with the li-topology and the associate TD behavior require further research works.

For this reason, the methodology of BP NGD TD measurement is investigated in the present study and is applied to a microstrip circuit based on the li-topology discussed in [START_REF] Ravelo | Negative Group Delay Theory on li Topology[END_REF]. It can be noted that the designed circuit has the particularity to have two frequency bands for which the GD is negative. Thus, the paper is organized as follows. Section II presents in a first time the specifications of the unfamiliar BP NGD function, and in a second time the design and performances of the circuit under test (CUT) based on FD simulations and measurement. Next, section III focuses on the developed methodology for the TD measurement of BP NGD functions. Then, results from the TD test illustrating the BP NGD signature of the CUT are discussed. Finally, section IV concludes the paper.

II. BP NGD PROTOTYPING AND FD ANALYSIS

This section begins with the introduction of the unfamiliar BP NGD ideal function. Next, the design process of the double-li CUT is described. Then, the BP NGD aspect is validated using a FD analysis based on S-parameter measurements. (1)

The GD associated to the circuit is also defined by:

    21 ( ) arg ( ) / GD S j = -     . ( 2
)
The circuit can be considered as a BP NGD function if it presents a GD<0 for a bandwidth Bn around a frequency fn as illustrated in Fig. 1(b), fn being the frequency for which a local GD minimum denoted GDn is obtained. The frequencies around fn for which the GD is equal to 0 are also called cut-off frequencies by analogy to filters.

To perform the TD BP NGD analysis, an input signal Vin presenting a spectrum centered on fn with a bandwidth B≤Bn is required. This bandwidth B can be defined as a function of an attenuation a with respect to the maximal spectrum magnitude Vmax as shown in Fig. 1(b). Thus, if it is assumed that the circuit is excited by an input signal represented by its Fourier transform Vin(jω), the attenuation of the input signal spectrum at the NGD cut-off angular frequencies Ck  (with k=1..K ; K being equal to 2 for a single passband NGD function) defined as:

  ( ) / max ( ) in Ck in a V j V j  = (3)
must also be chosen low enough to realize the TD analysis (for example a=0.1).

B. Design and Implementation of the BP NGD Prototype

The NGD prototype has been designed with two cascaded stages of the li-microstrip topology proposed in [START_REF] Ravelo | Negative Group Delay Theory on li Topology[END_REF]. The TLs physical widths are the same and chosen equal to 1.09 mm. The li-lines physical lengths and interspaces have been optimized using HFSS® simulations to operate as a dual-band NGD function with arbitrary chosen NGD center frequencies between fmin=2.3 GHz and fmax=2.4 GHz, and with insertion losses at the NGD center frequencies better than 5 dB. By denoting the effective permittivity εreff, the physical length of the li-shape microstrip line dn can be initially calculated as a function of the NGD targeted center frequency fn using: / (2 )

n n reff d c f =  . ( 4
)
The

C. NGD Design Validation in the FD

The following validation study is based on the comparison between the FD simulated ("Sim.") and measured ("Meas.") results which have been carried out in the frequency band from fmin=2.3 GHz to fmax=2.4 GHz. The GDs and S-parameters from simulation and measurement are plotted in Figs. 3. As depicted in Fig. 3(a), the CUT exhibits two NGD center frequencies (f1=2.345 GHz and f2=2.364 GHz) and measurement results confirms that the double-li CUT behaves as a dual-band BP NGD function. Nevertheless, FD response differences between simulations, and measurement can be observed and are mainly due to the substrate permittivity dispersion in addition to inaccuracies between its ideal value and its real one, but equally to the skin effect of the metallization conductor line, the fabrication tolerances, and the numerical computation inaccuracies. Figs. 3(b) and 3(c) illustrate that the insertion and reflection losses are better than 3.5 dB and 9 dB at the NGD center frequencies. Table I summarizes simulated, and measured results. Finally, from the present FD validation, the TD test of the double-li NGD circuit is investigated in the following section. For the oversight understanding of the TD NGD effect, the center frequency fPGD=2. [START_REF] Chang | Transient analysis of lossless-coupled transmission lines in a nonhomogeneous dielectric medium[END_REF] GHz, for which a positive group delay (PGD) can be observed, is considered during the analysis.

III. BP NGD TD EXPERIMENTAL TEST RESULTS OF THE DOUBLE li-MICROWAVE CIRCUIT

After the CUT introduction, the methodology of BP NGD TD experimentation is described in the present section. Next, the method feasibility is verified with the double li prototype described in the previous section.

A. Time Domain Test Methodology of the BP NGD Circuit

The TD test of the BP NGD circuit can be formulated using the following steps. ( ) ( )

max / max out in b Env v Env v =         . ( 5
)
Several characteristics can also be used to determine the NGD value from TD measurement such as the times difference when rising or falling edges of the input and output envelopes reach 50% of their final value. However, the NGD value can equally be characterized by the times difference when the input and output envelopes reach their maximum value as described by the following equation:

with:

( ) ( ) max ( ) max ( ) out out out in in in Env v v t Env v v t  =      =     . ( 7
)
Fig. 4.b depicts the TD experimental setup used here for the double li CUT. During the test, the ultra-wide band (UWB) microwave arbitrary signal generator Tektronix® AWG70001A, which can generate an arbitrary signal using 10 bits samples with a sampling rate of 50 GSps, has been used. This signal generator can deliver two perfectly synchronized opposite signals with a time shift better than 5 ps. To plot the signals, the four-channel oscilloscope referenced Agilent® DSO81204A, which has a bandwidth of 12 GHz and a maximal sampling rate equal to 40 GSps, has been used. As stated in the previous section, each channel of the signal generator (resp. oscilloscope) has an output (resp. input) impedance of 50Ω.

As indicated previously in step 3, the CUT input port has been connected to one channel of the signal generator and the CUT output port to one channel of the oscilloscope through 1 m SMA cables (CUT path). The same cables reference has been used to connect one side of a SMA transition to the second channel of the signal generator, and the other side of the SMA transition to another channel of the oscilloscope (direct path). Finally, the TD test has been done by considering a Gaussian up-converted pulse defined in the following subsection as input signal.

B. Input Signal Definition

In the present study, the chosen input signal is a sine carrier modulated by a Gaussian waveform. This test signal can be analytically defined by: 2 0 () ( ) e sin( 2)

tt in p v t f t -- =   . ( 8
)
where fp is the carrier frequency which can be chosen equal to the NGD center frequency to observe the NGD in TD. From ( 8), the Gaussian signal reaches its maximal value at the t0 time and has a bandwidth BG defined at ζdB which can be computed as follows:

  22 5 / ln(10) G dB B    =- (9)
with: 20log( )

dB a =  . ( 10
)
During the test, it is crucial that the input signal power spectrum is tuned to interleave within the NGD frequency band as illustrated by Fig. 1(b). For this reason, the NGD time-domain experiment must be absolutely preceded by a FD analysis in order to confirm the NGD specifications as aforementioned in section II via the GD response as shown in Fig. 3(a).

Thus, the performed TD measurement tests were carried out using the double-li CUT of Fig. 2(b) for two carrier frequencies and for two Gaussian envelopes having a different bandwidth. The first carrier frequency is fp=f1=2.345 GHz, which corresponds to the minimum GD response frequency of the double-li circuit as shown in Fig. 3(a), and the second one is fp=fPGD=2.5 GHz where the GD is positive. About envelopes, the first one has a bandwidth of BG1=30 MHz with ζdB=10 dB, and the second one has a bandwidth of BG2=15 MHz with ζdB=10 dB. The parameters of the test input signals are summarized in Table II.

The following subsection focuses on the transient measurement results obtained with the experimental setup shown in Fig. 4(b).

C. Analysis of the Time Domain Measurement Results

During the NGD measurement campaign, the output signal envelope should appear in time-advance compared to the input one. Using the test platform shown in Fig. 4

1) Transient Measurement Results

As expected, on the contrary of Fig. 5(b), the output envelope is in time-advance compared to the input one in Fig. 5(a). The double li-circuit TD experimented results must be interpreted as follows:

• In these two screenshot pictures, the yellow curve represents the input signal. Thus, it represents the input Gaussian up-converted pulse as analytically defined in the previous subsection. • The purple curve represents the output signal and the white curve represents the part where the input and the output signals are superimposed. • The output signal was rescaled in order to highlight the output signal advance compared to the input. Thus, at this stage of the experimental study, it has been successfully demonstrated in the TD that the CUT has a NGD around f1.

For more didactic analysis of the results, the corresponding csv-format data saved from the Agilent® DSO81204A digital oscilloscope have been post-processed in MATLAB®. Results are shown in Figs. 5(c)-(g). In these graphs, the full signal and its envelope are respectively plotted in red and black as follows:

• the measured input signal specified by the bandwidth-carrier frequency (BG2,f1) is shown Fig. 5(c) and the associated measured output signal is displayed in Fig. 5(d

2) Discussion on the Measured Signal Envelopes

The results from the TD BP NGD study of the two-stage li-CUT are analyzed by comparing input and output envelopes. I, it can be emphasized that the outputs corresponding to the carrier frequency f1 is significantly attenuated compared to the input. Therefore, the unity-normalized plots of inputs and outputs are shown in Fig. 6(b) (resp. Fig. 6(d)) for the Gaussian with a bandwidth BG2 (resp. BG1). It can be understood from these normalized plots that the rising and falling edges of the output envelopes are in time-advance compared to the input for the carrier frequency f1. Nevertheless, for the carrier frequency fPGD, the rising and falling edges of the envelope outputs are classically positively delayed compared to the input ones. From these results, it has also been verified that when the input signal has a bandwidth in the NGD frequency band, the extraordinary effect of the output envelopes time advance compared to the input ones can be seen. It is equally possible to note that despite the inevitable noise affecting the measured signals, input and output voltages of the double li-circuit remain very well-correlated thanks to a negligible distortion.

The different time-advance signatures for the two considered bandwidths around the dual NGD frequency bands can be understood from the zoom on the input and output envelopes rising edges (resp. falling edges) shown in Fig. 7(e) and Fig. 7(f) (resp. Fig. 7(g) and Fig. 7(h)). The measurement results obtained for every TD test are summarized in Table III. The developed test is highlighted with a double li-microstrip circuit. The double li-circuit has been analyzed in the FD and shows as expected a dual-band BP NGD. The feasibility of the TD test has been validated experimentally using Gaussian envelopes modulating sine carrier frequencies inside and outside the NGD frequency bands. Thus, it has been verified with the help of experimental results that the double-li circuit output can present rising and falling envelope edges in time-advance compared to input ones when test signal bandwidths are set in the NGD frequency bands.

The proposed study also paves the way to real BP NGD applications and notably for the time-delay compensation by exploiting the GD equalization technique [START_REF] Ravelo | Theory and circuit modelling of baseband and modulated signal delay compensations with low-and band-pass NGD effects[END_REF].

  CUT 3-D design and the photograph of the prototype implemented on Cu-metalized Rogers 3210 dielectric substrate are respectively shown in Fig. 2(a) and Fig. 2(b). It can be noted that the CL with physical length d1 (resp. d2) has a coupling coefficient -29.5 dB (resp. -31.5 dB).The BP NGD aspect has initially been validated using frequency domain S-parameter simulations, and experimentally verified with the help of a Vector Network Analyzer (VNA) thanks to[START_REF] Kouhpayeh-Zadeh-Esfahani | Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Transmission Line Excited by an Arbitrary Modulated Signal[END_REF]. Thus, the double-li NGD CUT, previously shown in Fig.2(b), has been measured with the Rohde & Schwarz ZNB 20 VNA from 100 kHz to 20 GHz after a Short-Open-Load-Through (SOLT) calibration. The experimental setup is shown in Fig. 2(c).

Fig. 1 .

 1 Fig. 1. (a) Two-port black box and (b) the typical BP NGD response with the input time domain test signal spectrum.

Fig. 2 .

 2 Fig. 2. Double li-CUT (a) 3-D design, (b) photograph, and (c) experimental setup.

Fig. 3 .

 3 Fig. 3. Comparison of simulated and measured (a) GD, (b) S21, and (c) S11 of the double-li circuit prototype shown in Fig. 2(b).

• Step 1 : 2 : 4 :

 124 The NGD CUT initial validation is based on the FD analysis in order to verify the specifications illustrated in Fig.1(b). S-parameters measurement are used here to accurately determine the NGD center frequency fn, the NGD bandwidth Bn. • Step The second step of the BP NGD analysis is the definition of the input signal required for the test and denoted vin(t). Appropriate signals for the TD BP NGD analysis are impulse signals since they make easier the determination of the envelope propagation delay compared to usual modulated carriers. Nevertheless, their spectrum must be centred on fn and their bandwidth must be lower or equal to Bn. For the case of microwave circuits, the expected configuration of the TD test setup is constituted by a 50 Ω signal generator, the CUT, and a 50 Ω oscilloscope as shown in Fig. 4. • Step 3: The experimental setup shown in Fig. 4(a) must respect certain expectations. Firstly, the signal generator and the oscilloscope must have a bandwidth which matches with the input test signal. In addition, to observe in the same time the input and output CUT signals, they musthave two channels at least, one to directly transmit the input signal from the generator to the oscilloscope (direct path) and another one to transmit the input signal through the CUT (CUT path). Then, the connectors, and the cables interconnecting the CUT and the equipment's must guarantee an accurate synchronization between the two paths.• Step The analysis of the transient signal should start from the simultaneous visualization of vin and vout defined in Fig.4(a). If the corresponding envelopes are denoted by Env(vin) and Env(vout), the TD attenuation b can be defined as the input and output maximum envelopes ratio as follows:

Fig. 4 .

 4 Fig. 4. (a) TD BP NGD test principle and (b) experimental setup used for the double-li CUT.

  (b), the results shown in Figs. 5(a)-(b) have been obtained for the case of a Gaussian input envelope having a bandwidth BG1. Nevertheless, Fig. 5(a) (resp. Fig. 5(b)) corresponds to the case where fp=f1 (resp. fp=fPGD).

  ), • the output measured transient signal corresponding to the input signal configuration (BG2,fPGD) is shown in Fig. 5(e), • the input and output measured transient signals under the configuration (BG1,f1) are respectively shown in Fig. 5(f) and Fig. 5(g). In the next paragraph, the input and output signal envelopes, shown by black curves in Figs. 5(c)-(g) are analyzed to determine the BP NGD specifications from the TD measurement test.

Figs. 6

 6 (a) and 6(b) (resp. Figs. 6(c) and 6(d)) represent the measured and the normalized signal envelopes when a Gaussian envelope having a bandwidth of BG2 (resp. BG1) is considered. The input and output envelopes corresponding to carrier frequency f1 (resp. fPGD) are respectively displayed using black solid and red (resp. blue) dashed curves. As predicted by the FD results of Figs. 3 and specified by Table

Fig. 5 .

 5 Fig. 5. Screenshots of (a) (BG1,f1) and (b) (BG1,fPGD) input and output Gaussian up-converted pulses. Transient (c) (BG2,f1)-input, (d) (BG2,f1)-output, (e) (BG2,fPGD)-output, (f) (BG1,f1)-input and (g) (BG1,f1)-output signals.

Fig. 6 .

 6 Fig. 6. (a) Measured and (b) normalized Gaussian envelope responses for (BG2,f1,fPGD). (c) Measured and (d) normalized Gaussian envelope responses for (BG1,f1,fPGD),. Zoom in rising edge normalized envelopes for (BG2,f1,fPGD) (e) and (BG1,f1,fPGD) (f). Zoom in falling edge normalized envelopes for (BG2,f1,fPGD) (g) and (BG1,f1,fPGD) (h).

  Rémy Vauché, Member, IEEE, Rym Assila Belhadj Mefteh, Fayrouz Haddad, Member, IEEE, Wenceslas Rahajandraibe, Member, IEEE, Fayu Wan, Member, IEEE, Sébastien Lalléchère, Member, IEEE, Glauco Fontgalland, Senior Member, IEEE, Preeti Thakur, Atul Thakur and Blaise Ravelo,

	A. BP NGD Ideal Specifications A circuit can be generalized by a two-port black box as Bandpass NGD Time-Domain Experimental Test shown in Fig. 1(a). Using the Laplace variable s=jω=j2πf, its
	S-matrix can be written as follows: of Double-li Microstrip Circuit   11 12 21 22 ( ) ( ) () ( ) ( ) S s S s Ss S s S s  =  
	Member, IEEE
	T

.

TABLE I

 I

			2
	GD (ns)	-2 0	(a)			Simu.
			-4				Meas.
			2.3	2.32	2.34	2.36	2.38	2.4
			0
	(dB) S 21		-2	(b)
			-4
			2.3	2.32	2.34	2.36	2.38	2.4
		-10
	(dB) S 11	-20		(c)
		-30
			2.3	2.32	2.34	2.36	2.38	2.4
					Frequency (GHz)
							COMPARISON BETWEEN FREQUENCY DOMAIN SIMULATIONS AND
							MEASUREMENT
							Validation	fn	GDn	Bn	S21(fn)	S11(fn)
							method	(GHz)	(ns)	(MHz)	(dB)	(dB)
							Simu.	2.3475	-4.55	10.0	-2.60	-12.02
							Meas.	2.345	-4.44	15.0	-3.64	-9.38
							Simu.	2.3638	-2.73	8.75	-2.01	-13.19
							Meas.	2.364	-1.88	8.00	-2.39	-14.90
							Simu.	2.5	0.5354	N/A*	-0.2024	-32.84
							Meas.	2.5	0.748	N/A*	-0.443	-14.19
							*Not applicable

TABLE III COMPARISON

 III OF THE INPUT AND OUTPUT SIGNAL CHARACTERISTICS FOR THE DOUBLE li-CIRCUIT Prof. Atul Thakur is M.Phil and Ph.D. from Himachal Pradesh University, Shimla, India. He has successfully completed several government funded projects. He is working as Director, Amity Institute of Nanotechnology, Amity University Haryana, India. His current research area is negative group delay and filed eighteen patents till date. Prof. Blaise Ravelo (M'09) is currently Full Professor at NUIST, Nanjing, China. His research interest is on multiphysics and electronics engineering. He is a pioneer of the negative group delay concept. He is member of IET Electronics Letters editorial board and member of IEEE, URSI, GDR Ondes, and Radio Society.

		(Bandwidth,
	Specifications	carrier	Description	Value
		frequency)
	Rise time advance		Δtrise	-2.1 ns
	Fall time advance Voltage attenuation	(BG2,f1)	Δtfall b	-3.9 ns 0.64
	Correlation coefficient		corr(Vin,Vout)	99.5 %
	Rise time advance		Δtrise	-0.9 ns
	Fall time advance Voltage attenuation	(BG1,f1)	Δtfall b	-1.8 ns 0.68
	Correlation coefficient		corr(Vin,Vout)	96.2 %
	Rise time advance		Δtrise	1.7 ns
	Fall time advance Voltage attenuation	(BG2,fPGD)	Δtfall b	0.6 ns 0.96
	Correlation coefficient		corr(Vin,Vout)	99.9 %
	Rise time advance		Δtrise	1.8 ns
	Fall time advance Voltage attenuation	(BG1,fPGD)	Δtfall b	0.8 ns 0.97
	Correlation coefficient		corr(Vin,Vout)	99.8 %

This work was supported in part by the Jiangsu Innovation and Enterprise Group Talents Plan 2015 under Grant SRCB201526, the National Natural Science Foundation of China under Grants 61601233 and 61750110535, the NSF of Jiangsu under Grants BK20150918, and the Priority Academic Program Development of Jiangsu Higher Education Institutions.

R. Vauche received the Ph.D. degree in microelectronics from Aix-Marseille University, France, in 2011. Since 2014, he has been an Associate Professor at IM2NP, Aix-Marseille University, France. His research interests include the design of integrated circuits and systems for ultra-wideband impulse radio, human body communications, and home-care applications.

R. Assila Belhadj


R Vauché

S Bourdel

N Dehaese

O Fourquin

J Gaubert

Fully Tunable UWB Pulse Generator with Zero DC Power Consumption

Keywords: UWB, Tunable Pulse Generator, H-Bridge, Pulse Shape, I

The design of a fully tunable pulse generator using only logic cells is presented and simulated with 0.13µm standard CMOS process. The generator is based on the elementary pulse combination and can synthesize different UWB pulse shapes. The generator uses logic gates to achieve the elementary pulses and a H-bridge to make the combination which leads to a zero DC power consumption. To achieve FCC compliant pulse having 2VPP magnitude the generator consumes 140 pJ by pulse using 1.2V supply voltage.

INTRODUCTION

As a result of mounting need for wireless communications in North America, Federal Communication Commission (FCC) has regulated 3.1-10.6GHz band in 2002 for Ultra-WideBand (UWB) transmission [START_REF]FCC rules and regulations[END_REF]. Other local regulation organizations in telecommunications allocated later frequency bands, in particular 6-8.5GHz in Europe, and 3.4-4.8GHz, 7.25-10.25GHz in Japan. Width of these bands allows the use of Impulse Radio (IR-UWB) techniques which require very simple transceiver architecture [START_REF] Datta | A Transceiver Front-End for Ultra-Wide-Band Applications[END_REF]. Opposed to classical wireless systems, UWB systems do not involve integration of costly functions in terms of consumption and die area as frequency synthesizer and mixer.

In order to be suitable for IR-UWB low cost applications, the pulse generator must be as small as possible and consume a small amount of power while achieving high pulse magnitude in order to be used in low cost systems based on energy detection [START_REF] Duenas | CMOS UWB IR Non-Coherent Receiver for RF-ID Applications[END_REF]. Moreover, the tuning capability of the generator is very important in addressing different applications and different frequency bands.

Several techniques are employed in order to generate UWB pulses such as filter impulse response [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF] or Step-Recovery Diode (SRD) [START_REF] Han | Ultra-wideband electronically tunable pulse generators[END_REF]. The main disadvantage of the first method is that it requires inductors which occupy a large silicon area whereas the second needs diodes not available in standard CMOS design kit. Moreover, previous methods create frozen pulse shape which can't be modified or tuned. Actually, two main techniques are used to achieve tunable pulse generator. The first one consists of using Local Oscillator (LO) to transpose different baseband pulses in different frequency bands [START_REF] Phan | A 18-pJ/Pulse OOK CMOS Transmitter for Multiband UWB Impulse Radio[END_REF]. The tuning capability of this technique is efficient but it is limited by its starting time which impairs the maximum amplitude and bandwidth [START_REF] Phan | Energy-Efficient Low-Complexity CMOS Pulse Generator for Multiband UWB Impulse Radio[END_REF]. Moreover, due to the consumption of the LO and the mixer, the consumed energy by pulse regarding the pulse magnitude is high. Due to increases in technology performances, elementary pulse combination is often used to achieve fully digital pulse generator [START_REF] Kim | All-Digital Low-Power CMOS Pulse Generator for UWB system[END_REF][9] [START_REF] Bourdel | Low-Cost CMOS Pulse Generator for UWB Systems[END_REF]. The main limitation of those generators is the limitation of the pulse magnitude in the upper bandwidth (>5GHz).

In this paper, we propose a fully integrated and tunable UWB pulse generator using H-Bridge principle. The generator structure allows a large variety of pulses to be synthesized. The main limitation is the number of elementary pulse needed which impact the size and the power consumption. Presented version of the generator can create pulse waveform composed by 6 elementary pulses which respects FCC regulation mask and drives 50Ω differential load. Simulation with a 0.13µm CMOS technology design kit shows the generator's ability to achieve 2Vpp pulse magnitude with 1.2V voltage supply in a 10dB bandwidth of 5.3 GHz centered at 7.3 GHz and to use pulse repetition frequency (PRF) of 500MHz. Furthermore, the generator contains only custom-made standard CMOS logic cells and an H-bridge driver which implies zero DC consumption and steady energy dissipation around 140pJ by pulse without turning off the generator. This paper is organized as follows. In Section II, the pulse combination method is explained. Section III introduces the proposed tunable UWB pulse generator based on H-Bridge. Simulation results obtained with 0.13µm CMOS technology are shown in Section IV and compared to others design results.

II. PULSE COMBINATION METHOD

As shown in Fig. 1 [START_REF] Kim | Fifth-derivative Gaussian pulse generator for UWB system[END_REF], UWB pulses can be parsed by a sequence of elementary pulse. Also, an UWB waveform s(t) can be approximated by a sum of elementary pulse where the n th elementary pulse is characterized by a magnitude of An and a width of τn. Sequentially it is possible to synthesize a pulse by combining elementary pulse shapes pn(t) of width τn multiplied by their appropriated magnitude (An). Resulting UWB pulse s(t) can be written with τ0=0 as follows :

st = ∑ n=1 N A n ⋅p n  t -∑ p=1 n-1  p  .
(1) Figure 1. 5 th Gaussian pulse [START_REF] Kim | Fifth-derivative Gaussian pulse generator for UWB system[END_REF] with its approximated spectrum Such method of generation is the more interesting since it is robust against τn or pn(t) variation. As shown in Fig. 1, a good approximation of 5 th Gaussian pulse in TABLE I can be achieved with constant τn and sinusoidal pn(t). This allows easy generator settings and the number of necessary elementary pulse N to be easily predicted. Central frequency spectrum f0 is equal to pulse pseudo-period and can be estimated from the average τn as follows :

f 0 ≃ N 2⋅ ∑ n=1 N  n . ( 2
)
Moreover, 10dB pulse bandwidth (BW) can be approximated as the invert of pulse length and expressed as follows :

BW ≃ 2 ∑ n=1 N  n . (3)
Finally, the minimum number of necessary elementary pulse Nmin to respect a given mask can be written as follows :

N min ≃ 4⋅f 0 BW . ( 4
)
Therefore, the more UWB spectrum to generate is narrow, the more number of elementary pulse to combine is high. For example, FCC mask requires at least 4 elementary pulses whereas the first 500MHz channel centered on 3.5GHz of 802.15.4a IEEE norm needs more than 28 pulses.

To illustrate this point, Fig. 2 and Fig. 3 show respectively a pulse shape in time and frequency domains which can be used respectively to match with FCC and ESTI mask. The first UWB pulse is obtained with an ideal 3 rd order Bessel filter driven by a triangular generator. Its bandwidth (BW) is tuned to 2.5GHz with an attenuation of 1dB and its central frequency is set to 8GHz. The second pulse is the response of an ideal 3 rd order Chebyshev filter centered on 7.55GHz. Its bandpass is equal to 1.2Ghz with a ripple of 1dB and its bandstop is tuned to 2.1 GHz with an attenuation of 30dB. The impulse response of Bessel filter for FCC mask need 7 elementary pulses to be synthesized and the impulse response of Chebyshev filter for ESTI mask needs more than 30 elementary pulses.

III. FULLY TUNABLE PULSE GENERATOR DESIGN

A UWB pulse generator based on the pulse combination method uses two main functions. The first is it generates all elementary pulses with their associated width and the second is it combines each pulse at the output stage with a desired magnitude. A bloc diagram schematic is shown in Fig. 4.

A. Gaussian-like Generator Design

As shown in Fig. 5, elementary pulses are generated by digital triangular generator [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF][8] which uses a digital delay line to propagate a positive edge. Two consecutive edges are then combined using logic gate (OR and AND) to generate an elementary pulse (EPn) and its opposite (EPnN) needed to command the H-Bridge. The delay between two consecutive edges sets the width of the elementary pulse (τn) and must be tunable. Particular attention must be paid to the matching between an elementary pulse and its opposite because mismatch between EPn and EPnN degrades the combination in the H-Bridge. Moreover, the elementary pulse generator must achieve pulse width less than 60ps with the 0.13µm used CMOS technology, to cover the full FCC band. Achievement of a triangular generator is directly bound up by the design of Voltage Control Delay Line (VCDL) which consists of tunable delay buffer. As shown in Fig. 6, a delay cell is built up of two parts (Part_1 and Part_2). Part_1 consists on two stages based on CMOS inverter loaded on a capacitor (C1) in series with a NMOS analog "switch" (M3) and it drives the next delay cell. Variation of voltage applied on M3 (V_W_n) changes the current in C1 and allows elementary pulse width (τn) to be modified. C1 is sized to achieve delay from INn to OUTn, between 50ps and 100ps (C1=500fF). The main advantage of this delay cell structure is its low sensitivity to control voltage variation. The second part of the cell (Part_2) is made up of two CMOS inverters and one "reset transistor" (M5), which enables the propagation through the delay line to limit the number of elementary pulses in case of short pulse generation. As shown in Fig. 6, a phantom cell is inserted to ensure a constant load between each elementary delay cell.

B. H-Bridge Design

To maximize the pulse's magnitude, the presented design uses a customized H-Bridge to drive the 50Ω output antenna. As shown in Fig. 8, the driver circuit consists of CMOS transmission gate and allows the peak to peak magnitude of the UWB pulse to stretch a theoretical value of 2VDD. Each elementary pulse (EPn) and its complementary (EPnN) command two transmission gates (TGnN and TGnP). The magnitude of each elementary pulse (An) is set by the DC voltage (V_M_n) of each branch. Positive and negative elementary pulses are combined by current sum in the load [START_REF] Bourdel | CMOS UWB Pulse Generator Co-Designed with Package Transition[END_REF]. In comparison with classical differential structure, the impact of this driver on the power consumption is minimized because it consumes zero DC power. Moreover, pulse combination method using H-Bridge enables to synthesize UWB pulse composed by a high number of elementary pulses which allows a large tuning of the pulse spectrum. If some transmission gates are not needed (to synthesize short pulse), they are on high impedance state because they are disabled.

As shown in Fig. 8, transmission gates are achieved by a NMOS in parallel with the associated balanced PMOS transistor. For sizing the NMOS transistor width, it is necessary to make a tradeoff between the maximum pulse magnitude and H-bridge power consumption. To achieve pulse magnitude of 2V (peak to peak) on 50Ω load, the width is around 200µm for the 0.13µm used CMOS technology. The PMOS transistor associated is a 460µm width which can lead to a large silicon area in the case of narrow band pulse. Considering the large size of the transmission gate transistors, it is necessary to insert, between the elementary pulse generator and the Hbridge, a buffer based on four CMOS inverter designed using the fan out laws. Due to the shape of the elementary pulse which commands the transmission gate and due to the time response of the gate, there is an aliasing in the conduction time between TGn gates (TGnN and TGnP) and TGn+1 gates (TGn+1N and TGn+1P) which results in narrower generated elementary pulse. This phenomenon is represented in Fig. 8. It implies that delay cells which generate the first and the last effective elementary pulses have to be tuned separately, in order to apply the width reduction to these pulses.

Finally an additional transmission gate stage is added. For a pulse generation using N elementary pulses, this stage is commanded by a N+1 elementary pulse which occurs at the end of the pulse. This stage is tuned at 0V in order to shortcircuit the load at the end of the UWB pulse to discharge the parasitic capacitors and avoid a time spreading of the pulse.

IV. SIMULATION

A. Simulation Results

The proposed UWB pulse generator is designed with standard 0.13µm CMOS technology design kit and simulation results are obtained with the software ADS for a supply voltage of 1.2V.

Pulse generation is based on a tunable delay line. One advantage of this architecture is the delay per stage could be tuned to set the delay in presence of Process Voltage Temperature (PVT) variation and hence the center frequency of the pulse. The elementary pulse generator simulations shows in Fig. 9 its ability to generate a minimum pulse width of 60ps (narrower pulse width leads to lower pulse magnitude and can not efficiently command the transmission gates) which is sufficient to cover the FCC band. This allows pulse to be centered on 8.33GHz.

A six order pulse generator has been designed for the FCC band. A first example of pulse generation is given in Fig. 10. The generator is set to synthesize a Gaussian pulse modulated by a sinusoid. In this case all the elementary pulses have the same width which limits the amount of input of the final circuit and simplifies the circuit measurement. The setting of the different control voltages needed to generate this pulse and the different values of An and τn are summarized in Table II. The pulse is compliant with the FCC spectral mask and it 10dB bandwidth is 5.3GHz centered on 7.3GHz. The pulse magnitude is 2Vpp and its duration 0.42ns. The control voltage used to set the programmable generator is linearly extrapolated from the value of An as shown in Fig. 12. This shows the very small distortion involved by the H-bridge and the ease of tune of the generator. Fig. 11 underlines the generator's ability to generate different UWB pulse shapes. In this case, a Bessel filter response is generated with the values shown in Table III resulting in narrower pulse bandwidth and a different pulse shape.

An approximation of the silicon area of this generator can be made from the size of the transmission gate and the number of elementary pulses needed to synthesize the pulse. In the technology used, a 200µm NMOS transistor and a 460µm PMOS transistor with 10µm finger occupy a silicon area of respectively 170µm 2 and 460µm 2 . The designed generator will occupy 0.02mm 2 and a pulse generator for ECC band having 20 elementary pulses would occupy 0.05mm 2 .

B. Performances Comparison

The simulated power consumption is 26.8mW for a Pulse Repetition Frequency of 200MHz. The energy consumed by pulse is then 140pJ. In comparison to previous published works, this consumption is high, as shown by Table IV. But, it is important to emphasize the fact that the energy by pulse criterion suppose that the power supply is turned off between two consecutive pulses to be independent of frequency. The total power consumption depends on the performances of the power manager circuit and the power consumed during the time needed to turn on and off the system can not be evaluated. As shown in Fig. 13, the presented pulse generator consumes zero DC current. This generator does not need power management to achieve a consumption of 140pJ by pulses. It's high in comparison with other generators but energy efficiency is better than previous works thanks to maximum pulse magnitude.

Moreover, the power consumption of the presented generator is essentially due to the size of the transmission gates. Such widths are used to achieve large pulse magnitudes in order to increase the transmission range. It is trivial to say that smaller pulse magnitude would lead to a smaller transmission gate and smaller consumed energy by pulses. To achieve a comparison of the energy by pulse regarding the pulse magnitude the following figure of merit is introduced:

= E V PP ( 5
)
where E is the consumed energy by pulse and Vpp the peak to peak pulse magnitude. Simulated pulse generator performances are summarized and compared with others generators in Table IV. The consumed energy by pulses by volt is 70pJ. V. CONCLUSION

The use of a H-Bridge as pulse combination circuit in fully tunable generator is proposed and simulated with 0.13µm CMOS technology. Simulation results show the circuit ability to generate different pulse shapes with peak to peak pulse magnitude of 2V with supply voltage of 1.2V. The pulse generator consumes zero DC power and 140pJ by pulse. Finally, the performances of the H-bridge allow the generation of pulse spectrum close to the predicted one which allows simple pulse tuning.

Figure 2 .Figure 3 .

 23 Figure 2. Response of an ideal 3 rd order Bessel filter set for FCC band

Figure 4 .Figure 5 .Figure 6 .

 456 Figure 4. Bloc diagram of pulse generator using combination method

Final

  stage of elementary pulse generator is achieved by standard NAND and NOR logic gates with an inverter at their output. To achieve complementary elementary pulses these gates need to be driven by two complementary command signals issued by the delay line. To generate those signals, buffers based on CMOS inverter are used. The first and the last inverters are sized with the fan out law in order to optimize signal propagation. To obtain synchronized balanced signals, an intermediate series inverter and an intermediate parallel inverter is inserted respectively in the unbalanced and the balanced path as represented in Fig. 7.

7 .

 7 Electrical structure of the designed balun

Figure 8 .

 8 Figure 8. H-Bridge combination principle

Figure 9 .Figure 11 .Figure 12 .

 91112 Figure 9. Maximum elementary pulse magnitude versus it width

Figure 13 .

 13 Figure 13. Consumed current at PRF=200MHz

TABLE I .

 I

			5 TH GAUSSIAN PULSE PARAMETERS
	n	1	2	3	4	5	6
	An (V) 0,06 -0.43 1	-1	0,43 -0.06
	τn (ps)	90	72	68	72	79	90

TABLE II .

 II PULSE PARAMETERS OF SINE MODULATED BY GAUSSIAN

	n	1	2	3	4	5	6
	An (V) 0.22 -0.69 1	-1	0.69 -0.22
	τn (ps)	71	71	71	71	71	71
	TABLE III.	PULSE PARAMETERS OF BESSEL FILTER RESPONSE
	n	1	2	3	4	5	6
	An (V) 0,35 -0.8	1	-0,75 0.37 -0.12
	τn (ps)

TABLE IV .

 IV PERFORMANCE SUMMARIZE OF PROPOSED GENERATOR AND COMPARISON WITH PREVIOUS WORKS


N Vauche

S Bourdel

J Gaubert

O Fourquin

R Vauche

N Dehaese

CMOS UWB Pulse Generator Co-Designed with Package Transition

Keywords: Pulse Generator, UWB, Packaging

CMOS UWB pulse generator co-designed with package transition

I. INTRODUCTION

The demand for low cost wireless systems is constantly increasing due to the development of applications like Piconet, PAN, or RFID, for which the production cost of the transceiver is crucial. For such applications, UWB Impulse Radio is a good solution because of its simplicity, its diversity path immunity and its localization capability.

To address the low cost market, IR-UWB must use energy detector receiver instead of coherent detection to avoid the use of complex synchronization schemes and powerful digital sections. In transceivers using energy detection, the energy of the emitted pulse must be maximized to ensure the range. Such energy maximization is possible since the peak power limitation imposed by the FCC is 0dBm in 50MHz RBW which allows high energy pulses [1]. But, the generation of high pulse using low cost technologies such as CMOS is currently a bottleneck.

Among the various techniques used to generate pulses [START_REF] Norimatsu | A UWB-IR Transmitter With Digitally Controlled Pulse Generator[END_REF][3] [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF], the filter impulse response method has a great potentiality for generating pulses with magnitude around 1Vcc [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF]. Moreover, it appears that for FCC systems, the order of the emission filter is low enough to be fully integrated in CMOS technologies on less than 1 squared millimeter area.

In the case of fully integrated systems, the die must be packaged. For UWB generators, high frequency package transition must be used to preserve signal integrity which is a major drawback for the system cost. To avoid the use of an expensive package, it is possible to co-design the emission filter of the generator using the transition because this transition acts as a filter. In this approach, parts of the emission filter are embedded in the package transition and other parts are implemented On Chip. Such an approach is particularly well suited for low coast packages like BGA since they use bonding [START_REF] Cubillo | RF Low-Pass Design Guiding Rules to Improve PCB to Die Transition Applied to Different Types of Low-Cost Packages[END_REF].

In this paper, we present the design of a fully integrated unipolar pulse generator using filter impulse response. The pulse generator is designed for OOK modulation and is compliant with FCC regulation mask. It achieves 1Vpp pulse magnitude and the die area is 0.38mm 2 . Based on this generator, we propose a method to co-design the emission filter of the generator and the transition used in the package. We show that such a co-design reduces the inductor number which results in a die size of 0.23mm 2 . Moreover, this codesign approach limits the losses of the filter which increases the pulse magnitude since the bonding is a better inductor than integrated inductors. At last, such a co-design approach is useful to other pulse generator topologies since it uses emission filter.

The paper is organized as follows. In section II, the generation method, based on the filter impulse response excitation, is presented. The fully integration of the generator in a 0.13µm CMOS technology is then described in section III. Section IV deals with the interconnection methods and presents a co-design of the generator with the package transition.

II. IMPULSE RESPONSE GENERATION METHOD

The impulse generation method consists on exciting a filter with a very short baseband pulse (g(t)) to generate its equivalent Dirac response (h(t)). g(t) is commonly achieved by a digital baseband pulse generator [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF] which is well suited to CMOS technologies. If we assume g(t) to be a square function of width equal to τ. The spectrum of the emitted pulse is :

(1) ( ) . sinc( . . ). ( )

S f A f H f τ π τ =
In the case of linear modulation such as OOK or BPSK the Power Spectrum Density (PSD) of the emitted signal can be expressed as follows:

(2)

2 2 0 ( ) ( ) ² ( ) ² ² a a e i s s s i PSD f S f S f f T T T σ µ δ ∞ =   = + -     ∑
Where µ a 2 and σ a 2 are respectively the mean and the variance of the data sequence {a k } and Ts the symbol time. If we take into account the filter losses (l) and the antenna impedance (Z 0 ) the emitted signal PSD is given by:

(3) ( ) ( ) 2 2 2 0 . .sinc ( ) ( ) .
.

s e a e a k s s s A fT H f k PSD f f l Z T T T τ π µ σ δ ∞ =-∞       = + -           ∑
where H e (f) is the normalized function transfer of the filter. The signal PSD is composed of a continuous spectrum and, when the mean of the sequence is not zero, a discrete spectrum. The equ. [START_REF] Phan | A 18-pJ/Pulse OOK CMOS Transmitter for Multiband UWB Impulse Radio[END_REF] shows how the PSD is impacted by the main generator parameters such as : modulation type (OOK, BPSK), filter characteristics (order, nature, losses), baseband pulse magnitude (A) and width (τ). Those parameters (summarized in Table I in the case of the presented design) must be set to have a signal PSD compliant with the FCC standard while taking into account the constraints due to technology. In our case of study, the PSD is plotted in Fig. 1(a). Here, the magnitude of the discreet spectrum must be evaluated since it is much higher than the continuous spectrum. To maintain a high pulse magnitude it is possible to decrease the symbol rate in the case of OOK modulations. Moreover, the equ. (3) determines the filter characteristics. For FCC standard, low order filter can be used which is a major advantage since the losses of CMOS integrated filter dramatically grow with the order. At last, Equ. (3) shows the impact of the characteristics of the baseband pulse (g(t)) on the PSD. τ impacts the spectral efficiency of the signal and the energy of the pulse. The decrease of τ increases the spectral efficiency since it limits the influence of the sinus cardinal function but, at the same time, it decreases the energy of the pulse. A value of 75ps is good tradeoff and can be achieved with baseband pulse generator in the targeted technology [START_REF] Bachelet | Fully integrated CMOS UWB pulse genrator[END_REF].

III. FULLY INTEGRATED PULSE GENERATOR DESIGN

As shown in Fig. 2, the pulse generator is composed of three elements: a baseband pulse generator often called triangular pulse generator, a filter driver and an on-chip filter. Because CMOS technologies provide low quality passive devices the design of the on-chip filter is crucial. A major problem lies in the use of inductors which achieve low Q factor. Moreover the value of the Q factor (and also the self frequency resonance) depends on the inductor value. Fortunately, due to large relative bandwidth imposed by FCC (close to 1), the range of L needed to implement the filter is not excessive. It is then possible to choose inductors that have good Q factor to limit losses. In our case, a 3 rd order Bessel using the topology presented in Fig. 2 leads to inductor values between 0.5pH and 2nH. In the targeted technology, such inductors have acceptable Q-factor (higher than 8) and their nominal values do not vary more than 100% in the full UWB bandwidth.

As specified in the previous section, the baseband pulse at the filter input must have a voltage magnitude of 2.9 V to maximize the signal PSD. To reach magnitude greater than V DD the filter must be driven in current mode as shown in Fig. 2. The baseband pulse is applied to the gate of M1, which provides a current pulse at the filter input. M1 must be sized with regard to the pulse magnitude needed at the filter input (A=2.9V) and the filter input impedance (50Ω for a 3 rd order Bessel filter loaded by a 50Ω antenna). In the case where g(t) is a square function with magnitude equal to V DD , the current given by M1 to the load during the time τ can be approximated using the small signal assumption. Under this assumption the width of M1 can be expressed as follows:

(4) ( )

2 0 0 . . . ox DD t L A W Z C V V µ = -
The M1 width is 100µm to generate a current pulse of 60mA magnitude, equivalent to a voltage pulse of 2.9V with a 50Ω impedance. The drain of M1 is biased using the first resonator of the filter and the gate is not biased to operate in C class in order to reduce power consumption.

To drive M1, a buffer must be inserted in the triangular pulse generator. The transistor sizes of the baseband pulse generator are the smallest the technology allows to achieve pulse width of 75ps. The buffer consists of six cascaded inverters. The width of each inverter is twice the width of the previous one to achieve a smooth size transition between the small transistors of the base band generator and M1.

The pulse generator has been realized using a 0.13µm standard CMOS technology from ST-Microelectronics and performs well compared to pulse generators recently published and presented in TABLE II. As shown in Fig. 3 the measured pulse magnitude is 1Vpp with only 1.2V voltage supply. Moreover the power consumption is 2.7mA for a Pulse Repetition Frequency (PRF) of 200MHz and the energy consumed by pulse is very low (2.25pJ/pulse), regarding the pulse magnitude. The power consumption performances of the generator show the efficiency of the current driver which consumes no DC current while no pulses are transmitted. Simulation and measurement shown in Fig. 1(b) concord and the measured spectrum is compliant with FCC regulation mask. The measured BW is 4.3GHz and the pulse width is 0.6ns. The die photograph is presented in Fig. 4. The silicon area is 0.38mm 2 .

III. PULSE GENERATOR PACKAGING

A key point in radio frequency applications and more specifically for UWB applications where large bandwidths are used is to connect the die with the antenna without impairing the signal integrity. To achieve low cost, in UWB applications the antenna can be directly printed on the chip carrier [START_REF] Lee | System On Package Ultra-Wideband transmitter using CMOS impulse generator[END_REF]. In this section we study different ways to connect the pulse generator described in section II to a 50Ω ground coplanar transmission line which is used to drive a 50Ω printed antenna. We used a standard laminate (RO4003) as chip carrier and wire bond attaches. Such a carrier to die transition can be modeled by a π network when the through phase shift associated to the transition is low [START_REF] Cubillo | RF Low-Pass Design Guiding Rules to Improve PCB to Die Transition Applied to Different Types of Low-Cost Packages[END_REF]. Such conditions are achieved in the UWB frequency band for sub millimeter wire bond lengths. The equivalent π model of the wire bond transition is given in Fig 5(a). The values of the model parameters can be obtained accurately from measurements or EM simulations [START_REF] Cubillo | RF Low-Pass Design Guiding Rules to Improve PCB to Die Transition Applied to Different Types of Low-Cost Packages[END_REF]. The value of L WB is linked to the wire bond length while the value C OnDie is mainly given by the pad of the silicon chip. C OnDie do not penalize the bandwidth because it can be included in the 260 fF capacitor of the on chip filter of the pulse generator (see Fig. 2). The wire bond transition bandwidth can be extended by adding a capacitor δC OffDie in parallel to C OffDie in order to synthesize a standard LC second order low pass filter [START_REF] Cubillo | RF Low-Pass Design Guiding Rules to Improve PCB to Die Transition Applied to Different Types of Low-Cost Packages[END_REF] shown in Fig. 5(b). This way the packaged pulse generator performs like the on chip pulse generator cascaded to the second order filter. So to maintain the signal integrity this second order filter must have a cutoff frequency larger than the UWB frequency range. The standard LC second order low pass filter, which is defined by the coefficients g 1 , g 2 , g 3 [START_REF] Zverev | Handbook of filter synthesis[END_REF], is given in normalized values in Fig. 5(b). We used a 1.3 dB ripple Butterworth response with a cut-off frequency of 11 GHz. Such Butterworth response with a low ripple value produces 50Ω termination, low group delay ripple and low attenuation in the UWB bandwidth. The filter element values are given by:

(5)

1 0 2 WB cutoff g L Z f π = (6) 2 0 2 OffDie OffDie cutoff g C C f Z δ π + =
That leads to a 0.8 mm wire bond length, and a shunt capacitance value δC OffDie =190fF. This capacitor value can be implemented on the chip carrier by decreasing the characteristic impedance of the transmission line near the wire bond transition. Fig. 6 shows the HFSS model of the modified wire bond transition which has been used to compute the scattering parameters of the transition. The simulated output spectrum of the pulse generator cascaded with the transition is given in Fig. 1(b). We can notice that the modified WB transition does not significantly impair the signal integrity of the emitted pulse. The simulated pulse magnitude in the time domain is 1.05Vpp and is roughly the same as the on chip pulse generator pulse magnitude. Another way to maintain the signal integrity of the packaged pulse generator is to embed the carrier to die transition in the pulse generator filter. Indeed, as shown in Fig 7, the π model of the transition can be used to build the last π section of the pulse generator filter. The wire bond length must be sized so the inductor LWB of the π model of the transition match the filter inductor value. By using EM simulation tool we obtain a wire bond length of 1.4 mm and C OnDie and C OffDie of 120 fF and 60 fF respectively. In order to synthesize the desired filter a lumped capacitor on die (δC OnDie ) and a distributed capacitor on the chip carrier (δC OffDie ) have been added to match the filter capacitors values. The simulated output spectrum of the co-designed pulse generator is given in Fig. 1(b). Using a co-design process has several advantages. First the silicon area is reduced. Indeed, the last on chip inductor in Fig. 2 is replaced by the wire bond and the silicon area is so reduced to 0.23mm 2 . Moreover, in CMOS technology, inductors have poor quality factor. In the co-designed pulse generator, due to the wire bond which has a high quality factor, the filter losses are reduced and the pulse amplitude is increased from 1Vpp to 1.4Vpp as shown in Fig 3(b).

CONCLUSION

The design of an UWB pulse generator is proposed and implemented in a 0,13mm CMOS technology showing the potential of this design to generate large pulse magnitude (1Vpp) with voltage supply of 1.2V while consuming a small amount of energy by pulse (2.25pJ). Moreover, this generator is well suited to wire bond package transitions and a co-design method can lead to pulse magnitude of 1.4Vpp and reduce the chip size to 0.23mm 2.

Fig. 1 :

 1 Fig. 1: (a) Theoretical signal PSD, (b) pulse spectrum of the different generators

Fig. 2 :

 2 Fig. 2: Pulse Generator Topology

Fig. 3 :Fig. 4 :

 34 Fig. 3 : output of the measured integrated generator (a) and of the simulated co-designed generator (b)

Fig. 5 :

 5 Fig. 5 : (a) Wire bond transition lumped equivalent model. (b) 2 nd order low pass filter based on the bond wire transition model.

Fig. 6 :

 6 Fig. 6 : HFSS model of the modified bond wire transition.

Fig. 7 :

 7 Fig. 7 : Pulse generator co-designed with the wire bond transition.

TABLE I SUMMARY

 I OF THE GENERATOR CHARACTERISTICS

	Filter	fo	6,9GHz
		BW (-3dB)	5,4GHz
		Nature	3rd order Bessel
		Power losses 3dB
	Modulation	Nature	OOK
		ma	0,5
		sa2	0,25
		Rate	36Mbs-1
	Base Band Pulse A	2,9V
		t	75ps

TABLE II PERFORMANCE

 II COMPARISON OF THE PROPOSED PULSE GENERATOR WITH PREVIOUSLY PUBLISHED WORKS

	References Vpp (V)	Vdd (V)	Pulse Width (ns)	BW (-10dB)	Technology (µ µ µ µm)	Power Cons.	(/pulse) Energy Cons.	area (mm 2 )	Modulation
	[2] -2007	1,24	2,2	1,75	1,4GHz	CMOS-0,18	29,7mW@36MHz	-	0,4 (core)	DBPSK
	[3] -2007	0,18	1,5	3,5	500MHz	CMOS-0,18 1,82mW@100MHz	18pJ	0,39 (die)	OOK
	[6]-2006	0,9	1,8	2,5	1,2GHz	CMOS-0,18	1,8mW@10Mp/s	180nJ	1,21 (die) / 0,57 (core)	BPSK
	[7]-2007	0,65	1	3	550MHz	CMOS 0,09	-	47pJ	0,08 (core)	DBPSK
	[8]-2008	0,16	1,5	3,5	520MHz	CMOS 0,18	1,68mW@100MHz	16,8pJ	0,3 (core)	OOK
	This Work	1	1,2	0,6	4,3GHz	CMOS 0,13	2,7mW@200MHz	2,25pJ	0,38 (core)	OOK