help me and share their knowledge with me. Hence, I would like to start be thanking all these people who helped me deepen my knowledge within the complex subject of this thesis and gain many new skills. Alexandre Siligaris, your contribution to my thesis has been very important, thank you for the significant remarks you have made in Chapter 4 of my thesis. Joris Lacord and Josep Segura, thank you for the fruitful discussions.

I would like also to thank the members of my jury, Pr. Cristell Maneux, Pr. Per-Erik Hellström, Pr.

Pierre Magnan and Pr. Gérard Ghibaudo, for reading my manuscript, attending the defense and for all the significant remarks that helped me improve the quality of this manuscript. It was an honor having you all in my jury.

I would certainly like to express my warmest gratitude to my supervisors. Gilles Sicard, smart imager expert, you were always encouraging me in all steps of this thesis and I really enjoyed working in your lab. You were very supportive and eager to help me in every aspect of this thesis. Perrine Batude, process integration expert, I would like to thank you for all your support, you always provided stimulating discussions. I am so grateful you gave me the opportunity to work in this technology. Thank you also for challenging me and pushing me to enhance my communication skills as I have always been more of an introvert. Christoforos Theodorou, device noise expert, my gratitude is beyond words. You have set an example for me of excellence as a researcher, mentor and instructor. Thank you for guiding, encouraging and advising with a good humor always. Your constant passion and enthusiasm for research always motivated me to overcome myself. Thank you all, for the guidance and the rehearsals and review of papers/manuscript/presentations especially during the "end-of-contract" period. I hope I will have the pleasure to work with you again in the future! I am also very grateful to my friends, especially Spiros, Manos, Angeliki, Miltos & Despina, who supported me so much through all these years. I have so many wonderful memories from you that will accompany me my whole life. Spiros, my best friend, your support and mental encouragement was very important for me to carry out this work! I should not forget to mention also all the people in CEA-LETI and the people in the IMEP-LAHC laboratory that I interacted with, whether it was in meetings, lunch, coffee or just discussions in the office. I am incredibly grateful for those of you who stood by to support me along the way. Thank you for helping me during my PhD journey.

INTRODUCTION

This chapter aims to provide a brief overview of the topic of the thesis. We will start by exploring the evolution of CMOS technology and the prevailing future trends. Afterwards, the threedimensional integration technologies will be presented, focusing on the sequential 3D integration.

Then, the analysis methods and tools that helped to carry out this work will be outlined. Finally, the challenges that motivated me to study this topic will be presented, along with the major contributions of this thesis to the state of the art.

A brief historical review of CMOS technology

Since the early 1960s, when the first metal-oxide-silicon field effect transistor (MOSFET) was discovered, it has become the driving force in electronics. Digital integrated circuits nowadays utilize billions of MOSFETs to implement complex systems on the same chip (System on Chip -SoC) with great computing power, facilitating life and boosting the development of modern societies. The increasing need for high performance, accompanied with low power consumption and cost reduction, has led to the continuous miniaturization of these devices [1]. "Moore's Law" has been the guiding light for the evolution of microelectronics and in particular of the MOSFET transistor until nowadays. It relies on the predictions made by Gordon Moore about the density of integrated components in a chip following an exponential trend [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF].

Section 1.1 -A brief historical review of CMOS technology 15

Unlike its name, "Moore's Law" was in fact an empirical relationship based on the financial cost reduction per components of integrated circuits every year. Nevertheless, the increase of the integration density implies the dimension scaling of the components, which by turn reduces their gate delay and power consumption.

However, the microelectronics industry has been facing many challenges arising by the ongoing dimensional scaling of the electronic components. These challenges set barriers to "Moore's

Law" and emerge from several aspects of the device manufacturing such as:

• The need for better electrostatic control of the device channel by its gate electrode. It is crucial that the transistor operates as a switch in digital design, therefore it must always approximate the ideal behavior [3].

• The device must facilitate the flow of the current without posing obstacles and reducing the carrier mobility, when it is in the on-state [3].

• The previous is also true for the interconnections, which must allow the maximum current density to flow. However the device miniaturization has impacted negatively the performance of interconnect wires [4]- [START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF]. As the wires cross-sections, their pitch and length to traverse a chip increases, the resistance and the capacitance of these lines are also rising resulting in a significant increase in signal propagation (RC) delay. As a consequence the performance of advanced ICs is limited [4]- [START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF].

• The limits posed by lithography and the unavailability of sufficiently small light wavelengths to pattern the minimum feature size [START_REF] Harriott | Limits of lithography[END_REF].

Fortunately, research in device engineering in recent years has led to new device architectures comprised of innovative and efficient materials, or structure designs. Planar transistors that have been used for years faced certain limitations with scaling due to Short-Channel-Effects (SCE).

Chapter 1 -Introduction For that reason, device architectures as FinFETs, Fully-Depleted Silicon-On-Insulator (FD-SOI) and more recently Gate-All-Around (GAA) emerged offering approximately ideal electrostatics with the advantage of further dimensional scaling (Fig. 1.1).

Moreover, the use of materials such as High-K (HK) dielectrics permit the increase of the gate capacitance, mitigating problems resulting from ultrathin gate dielectrics such as the high gate leakage current due to direct tunneling of electrons through the SiO2, a difficulty in manufacturing ultra-thin films, and the reliability of SiO2 films against electrical breakdown [START_REF] Robertson | High dielectric constant oxides[END_REF]. On the other hand, Metal Gates (MG) are extensively used between the gate electrode, made out of degenerately doped polycrystalline silicon and the gate dielectric, adjusting the threshold voltage of the device by its work function while providing a higher carrier density and a depletion depth of less than one Angstrom [START_REF] Robertson | High dielectric constant oxides[END_REF].

3D integration technologies overview

Despite the development of new device architectures, capable of overcoming scaling issues, Moore's law is running out of steam and a potential end is envisioned. The latter is mainly because the feature size of the devices is approaching the fundamental limit of an atom. The foreseeable reach of Moore's Law limits, the increased needs in terms of performance, space saving and low power consumption as well as the growing menace of RC delay in recent times led in the 80's to the concept of integrating functionalities in three-dimensional modules [START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF]- [START_REF] Kunio | Three dimensional ICs, having four stacked active device layers[END_REF]. These constitute a System in Package (SiP) combining conventional digital technologies (processor, memory controller, graphics solution, inputs / outputs, network connections, microsystems electromechanical) fabricated in different processes.

Conventional planar integration can be considered as two-dimensional. Thus, threedimensional integration refers to the stacking of integrated circuit layers, interconnected vertically.

The dominant approaches for three-dimensional integration in a single package can be encapsulated in 2 categories: parallel and sequential. The former term is referring to a method where the two wafers are processed separately and stacked -and contacted-afterwards (Fig. 1.2 (a)). In that case the alignment is made during the bonding and its 3-σ error is nowadays around 200nm [START_REF] Jourdon | Hybrid bonding for 3D stacked image sensors: Impact of pitch shrinkage on interconnect robustness[END_REF]. In brief, the 3-σ error accounts for nearly 100% of the total alignment variation and is determined by calculating the standard deviation of the normal (Gaussian) distribution of the variation and multiplying it by three. There are several types of wafer bonding, the most prominent ones being copper-to-copper (Cu-to-Cu) and Hybrid bonding and Through-Silicon Via (TSV). On the contrary, 3D sequential integration technology (3DSI -also named 3D monolithic integration or 3D VLSI) refers to the vertical stacking of active devices that are processed sequentially, i.e. each tier of devices is processed over a pre-patterned one (Fig. 1.2 (b)). This imposes that the alignment is made by lithography and the 3-σ error is around 5nm for a 28nm node [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF].

Consequently, 3DSI can offer the highest density of vertical interconnects (>5x10 6 3D via/mm 2 in [START_REF] Batude | Enabling 3D Monolithic Integration[END_REF] and up to 10 8 3D via/mm 2 in [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF], [START_REF] Batude | 3D sequential integration: Application-driven technological achievements 202 and guidelines[END_REF]), when compared to the other alternatives [START_REF] Garrou | Handbook of 3D Integration[END_REF], [START_REF] Banijamali | Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA[END_REF], as shown in (Fig. 1.3).

Fig. 1. 3 Alignment capability versus 3D contact width in parallel and sequential integration (adopted from [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF]).

There are multiple levels of partitioning a circuit following a three-dimensional integration: core-level, block-level, gate-level and ultimately transistor-level partitioning (Fig. 1.4). The latter, being the last one in the granularity scale can be realized exclusively with 3DSI. Furthermore, 3DSI is the only 3D technology to enable partitioning with all granularity scales. 3DSI offers plenty of opportunities. Traditionally, the main virtue resulting from threedimensional integration has been on the "More Moore" direction, attributed to the drastic decrease in the length of interconnects in an integrated circuit. Indeed, as shown in Fig. 1.5, assuming a planar integrated circuit with an area A, the longest interconnect (i.e., the line between the points X and Y) has a length L max = 2√𝐴. Partitioning the same circuitry in two layers, each having an area of A/2, the length of the longest interconnect is now L max = √2𝐴. Following the same logic, increasing the number of layers to four, the area of each die is further reduced to A/4, and the longest interconnect would have a length of L max = √𝐴. By this simplified example it can be seen that there is a significant reduction of the wiring length and consequently the interconnection RC delay, leading to considerable advantages over conventional planar integration. Specifically, it has been reported that for a two-tier 3DSI there is 50% area reduction, 20% power limitation and 26% performance boost owing to the interconnect length reduction [START_REF] Clermidy | Technology scaling: The CoolCube TM paradigm[END_REF], [START_REF] Shi | On the design of ultra-high density 14nm finfet based transistor-level monolithic 3d ics[END_REF]. Consequently, 3DSI has been envisioned as an alternative to the dimensional scaling of devices which is reaching its limits.

Fig. 1. [START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF] The trends of "More than Moore" as compared to "More Moore" [START_REF] Arden | More-than-Moore' White Paper[END_REF].

Nowadays, the versatility of applications that can be integrated in each sequential tier is emphasized towards the "More than Moore" direction. The latter enables the possibility to integrate heterogeneous complex systems with a large number of functionalities in a reduced form factor,

L max = L max = L max = X Y X Y X Y
while increasing the circuit performance (in terms of enhanced bandwidth and reduced power consumption) as shown in Fig. 1.6.

A highly anticipated application within the More than Moore approach is the smart sensors which embed the sensor interface with all the processing and memory elements stacked on top of it.

In this manner, applications fabricated in different technologies that are connected with low-latency vertical interconnections, enable the acceleration of the signal processing in a reduced form factor.

An example of that is the smart imager that incorporates pixels with stacked analog and digital processing units as illustrated in Fig. 1.7.

Fig. 1. [START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF] Partitioning a pixel of an image sensor through 3D heterogeneous integration [START_REF] Michallet | CoolCube TM : A True 3DVLSI Alternative to Scaling | 3D InCites[END_REF].

Although 3D stacking technologies are widely used for 3D CIS [START_REF] Millet | A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing[END_REF], [START_REF] Kim | A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7μm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology[END_REF], constraints of traditional 3D stacking alignment capabilities forbid the more aggressive pixel miniaturization required for future generations of CIS [START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF], [START_REF] Coudrain | Investigation of a sequential three-dimensional process for backilluminated CMOS image sensors with miniaturized pixels[END_REF]. The feasibility of Back-Illuminated CIS with miniaturized pixels realized in 3DSI has been investigated in [START_REF] Coudrain | Investigation of a sequential three-dimensional process for backilluminated CMOS image sensors with miniaturized pixels[END_REF], where a 44% increased photodiode area for 1.4μm pitch was reported owing to the 3D partitioning at the pixel level. Moreover, 3DSI is the dominant pathway for pixel partitioning with pitch in the 1 μm range [START_REF] Vivet | Advanced 3D Technologies and Architectures for 3D Smart Image Sensors[END_REF].

Electrical measurement and analysis methods

For the purpose of this study, electrical measurements were performed on 3D sequentially integrated wafers, processed with the CoolCube TM technology in CEA-LETI (Fig. 1.8). The simulation study was conducted with the aid of leading EDA tools. For the electrostatic coupling analysis, numerical simulations were performed using Silvaco ATLAS [START_REF] Silvaco | [END_REF], a generic TCAD tool for physically-based two (2D) and three-dimensional (3D) simulation of semiconductor devices.

Additionaly, Silvaco CLEVER [34] was used to extract the parasitic capacitances within the monolithic 3D structures. This tool is a field solver, intended for complex arbitrary structures where layout effects dominate, providing accurate results in a sufficient amount of time.

Due to the small electrical size of the structures simulated (i.e., the ratio between the largest distance between two points in the structure divided by the wavelength of the electromagnetic fields) being in the range up to 1/10, quasi-static formulations have been used to carry out this study.

By using this approximation, the wave propagation delays are small enough to be neglected. Hence, even for frequencies up to the GHz regime, quasi-static tools provide accurate description of the coupling fields without the need of dedicated high frequency simulations. Therefore, the abovementioned simulation tools are adequate for an accurate analysis particularly in the low-frequency domain. Yet, Ansys HFSS (High Frequency Electromagnetic Field Simulation) [START_REF]User's guide -High Frequency Structure Simulator[END_REF], a full-wave EM simulator that predicts non-quasistatic effects, has been utilized for the validation of the TCAD simulations in the high-frequency domain.

Lastly, the circuit simulations were performed within the Cadence Virtuoso Platform [START_REF] Cadence | Spectre ® Circuit Simulator Components and Device Models Reference[END_REF] using a parametrized version of the Leti-UTSOI model [START_REF] Poiroux | Leti -UTSOI 2.2.0 User's Manual[END_REF]. The proper parametrization of the model was employed to reproduce the experimental behavior and also to include the electrostatic coupling via the Back Gate (BG) of the transistor model.

The primary and main challenge of Monolithic 3D integration is associated with the fabrication of the top active layer (or layers) in such manner to preserve the electrical characteristics of the bottom one. Therefore, there is a temperature barrier (Thermal Budget (TB)) in order to avoid the degradation of the bottom tier's device, therefore the classical processing steps for the top tier's device fabrication are forbidden. To cope deal with this obstacle, the TB of the top devices is kept below 500°C to preserve the bottom FET from any degradation [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF], [START_REF] Batude | 3D sequential integration: Application-driven technological achievements 202 and guidelines[END_REF]. Furthermore, the different tiers are linked with 3D contacts, as shown in Fig. 1.10, which has limits in its aspect ratio (AR). This type of contact is a conventional one (Tungsten plug in oxide),

however it has a greater height, predominantly defined by the ILD thickness (illustrated in Fig. 1.9).

The AR of the 3D contact is expressed as

𝐴𝑅 3𝐷𝐶𝑂 = 𝑊 3𝐷𝐶𝑂 𝐻 3𝐷𝐶𝑂 (1-1)
where W 3DCO is the width of the 3D contact which scales with the stacked device technology and H 3DCO is its height. Due to limits imposed by etching, the shape of a standard and 3D contacts is a trapezoid, thus a high AR reduces its bottom-end area. This by turn limits the maximum allowed current density, hence the lowest possible AR is preferable. An AR close to the one of standard contact, is required nowadays in terms of processing, hence the solution to achieve that is to keep the ILD thickness below 350nm.

Challenges & Motivation

Fig. 1.10 Schematic cross-section view of 3DSI scheme indicating the characteristic dimensions of a 3D contact.

Another significant challenge of this technology, which is also the topic of this thesis, is the danger of electromagnetic interference between the sequential tiers. As explained previously, the ILD separating the top-tier device from the bottom one is very thin (few hundreds of nm), so that a good 3D contact AR is preserved. Therefore, the ILD can become a pathway for DC and electromagnetic coupling between adjacent tiers, limiting their performance as a result, or shifting the circuit's operating point.

State-of-the-art studies on electromagnetic coupling in 3D technologies

The design of systems in a single chip is one of the current obstacles in the semiconductor industry. Numerous compatibility issues in terms of materials, process integration and functionality, emerge in this contemporary scheme. Over and above, associating circuits of different nature, functioning and operating frequency range within the same chip, and more importantly placed at close distances, is a major challenge.

It is well known from conventional planar integration that the design of circuits operating within a highly noisy environment is extremely critical and presents many challenges. To minimize the noise impact on the sensitive active parts of a circuit, the solutions often consist in oversizing the critical distances between the functional blocks. However, these solutions limit the benefits of the technological advances (form factor and interconnection delay reduction). For these reasons, the characterization and modeling of noise coupling is of increasing interest.

In the general context of 3D integration, numerous studied have been reported regarding the electromagnetic interference between sensitive parts of the chip, however the majority of them concerns parallel integration. In particular, TSV to active device coupling has been extensively characterized [START_REF] Gu | Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology[END_REF]- [START_REF] Araga | Measurements and analysis of substrate noise coupling in TSV-based 3-D integrated circuits[END_REF] and modeled [START_REF] Yoon | Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer[END_REF]- [START_REF] Ma | First order Electro-thermal compact models and noise considerations for threedimensional integration circuits[END_REF] whereas its impact on the device and circuit performance has been in-depth analyzed in several studies [START_REF] Araga | Measurements and analysis of substrate noise coupling in TSV-based 3-D integrated circuits[END_REF]- [START_REF] Xu | Compact capacitance and capacitive coupling-noise modeling of through-oxide vias in FDSOI based ultra-high density 3-D ICs[END_REF], [START_REF] Chen | Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling[END_REF], [START_REF] Rousseau | Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology[END_REF]- [START_REF] Lee | Noise coupling analysis between TSV and active circuit[END_REF].

On the other hand, to date there is poor amount of literature concerning coupling between the different tiers and particularly active devices in sequential 3D integration. Electrostatic coupling effects in 3DSI have been already presented in principle [51]- [START_REF] Chaourani | Sequential 3D Integration -Design Methodologies and Circuit Techniques[END_REF] and experimentally verified [START_REF] Andrieu | Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation[END_REF],

whereas performance analysis taking into account the impact of electrostatic coupling has been performed in [START_REF] Koneru | Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing[END_REF], [START_REF] Hattori | Interlayer coupling effect on the performance of monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness[END_REF], [START_REF] Koneru | Impact of electrostatic coupling and waferbonding defects on delay testing of monolithic 3D integrated circuits[END_REF]- [START_REF] Ahn | Circuit simulation considering electrical coupling in monolithic 3D logics with junctionless FETs[END_REF]. However, these studies cannot provide significant conclusions about the critical dimensioning of the stacked devices. Moreover, they consider homogeneous integration (specifically the tiers are comprised exclusively of digital circuits) and more importantly they partition the circuit in different tiers of 3DSI.

Several modeling considerations have been reported in [START_REF] Xu | Compact capacitance and capacitive coupling-noise modeling of through-oxide vias in FDSOI based ultra-high density 3-D ICs[END_REF], [START_REF] Xu | Physical modeling of the capacitance and capacitive coupling noise of through-oxide vias in FDSOI-based ultra-high density 3-D ICs[END_REF] concerning capacitive coupling in TOV technology. This process scheme is similar to 3DSI since it refers to stacked SOI devices separated by an oxide medium with Through-Oxide-Vias (TOVs) being the vertical contacts.

The models reported evaluate the coupling capacitances formed between TOVs and active devices placed at the upper tiers, however they cannot evaluate the coupling impact between stacked devices. Nonetheless, although some modeling considerations are reported in [START_REF] Ahn | Parameter extraction and power/performance analysis of monolithic 3-D inverter (M3INV)[END_REF]- [START_REF] Ahn | Circuit simulation considering electrical coupling in monolithic 3D logics with junctionless FETs[END_REF] for the coupling between active devices in monolithic logic circuits, these models rely mainly on parasitic extraction and don't predict the impact of arbitrary geometric configurations and scaling of the devices (layout effects).

Lastly, solutions to coupling effects in 3DSI have also been considered in [START_REF] Jiang | Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges[END_REF], [START_REF] Vandooren | Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications[END_REF], where the inter-tier shielding methods are investigated. Additionally, [START_REF] Vandooren | Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications[END_REF] experimentally presents their technological achievement on a buried metal line, functioning as a shielding layer between two tiers of a 3DSI scheme.

Main contributions and thesis outline

This thesis aims to provide a deep understanding of the underlying physical mechanisms responsible for the electromagnetic coupling between the different tiers in 3DSI as well as a complete study how these coupling effects may impact a circuit's operation. For the latter, a comparative study among planar and 3DSI has been performed. The most critical cases of digital, analog and mixed-signal/RF circuit designs have been examined, in order to draw a reliable conclusion for every case.

Lastly, several techniques to mitigate the impact of coupling effects are suggested for the most sensitive circuits, targeting an efficient process flow, compatible with sequential 3D as well as convenient rules for the design of monolithic 3D circuits.

To highlight, this thesis differentiates from the existing works in the following:

• Utilizes 28nm node FDSOI process for the sequential stacking.

• Incorporates also the heterogeneous integration concept for the different tiers. By that each tier can consist either of exclusively digital, analog and mixed-signal/RF circuit designs or a combination of them.

• Provides reliable conclusions on the critical dimensioning of the 3DSI structures. To accomplish that, the impact of coupling effects on the most prominent metrics at a device and circuit level are examined to ensure their normal operation.

• Solution challenges and methods are in-depth analyzed, employing a thorough simulation analysis for the first time. Moreover, a novel integration scheme is suggested with the integration of an inter-tier shielding layer comprised of a semi-conductive material.

• Provides a novel modeling approach, which predicts accurately the impact of layout effects on the inter-tier capacitive coupling between active devices and merges the gap between pre-and post-layout simulations. Our modeling approach can potentially be integrated in SPICE as a Verilog-A model that predicts accurately the coupling effects. As a consequence, the analysis of complex and large-scale monolithic 3D circuits with SPICE tools can become easier, enabling the circuit designer to take into account any degradation due to the parasitic effects.

The thesis is organized in seven chapters as follows:

• Chapter 1 introduces the topic of this thesis along with the state-of-the-art approaches in the field. The main motivations behind this work, as well as its main contributions are also presented.

• Chapter 2 provides a comprehensive introduction to the theoretical background utilized within this work. The MOSFET device physics, the electromagnetic coupling theory as well as the specificities of noise coupling in digital and analog systems are reviewed.

• Chapter 3 presents an experimental and simulation study concerning the electromagnetic coupling between active devices separated in sequential tiers, as well as the coupling's impact on the performance. The devices that are more susceptible to coupling effects are investigated in terms of the critical alteration of their characteristic electrical parameters in both static and high frequency domain.

• Chapter 4 studies the impact, circuit performance-wise, of the inter-tier electromagnetic coupling. The most critical circuits in digital, analog and mixed-signal/RF design have been selected to construct monolithic 3D circuits that are comprised solely by one kind or a combination thereof.

• Chapter 5 examines a Rolling Shutter (RS) CMOS imager realized in 3DSI technology. At first, a brief disambiguation of the imager functioning is presented, focusing on the circuit operation of a single pixel. Moreover, the figures of merit of each pixel are analyzed and exploited to examine the impact of the inter-tier electromagnetic coupling for each pixel separately and as whole, the interrelation between them.

• Chapter 6 presents the results of parasitic extraction in 3DSI structures and focuses on the modeling of the inter-tier coupling effects. To do so, the coupling through the electric field is modeled utilizing RC networks. Analytic and empirical expressions for the coupling effects are presented for a wide range of channel geometries along with several top/bottom active device configurations.

• In Chapter 7, all the conclusions of the research performed in the framework of the present thesis are presented, along with suggested directions for future research on the field.

28

PHYSICS OF MOSFETS AND COUPLING EFFECTS

In this chapter, a description of the ideal MOSFET transistor (i.e. without any parasitic effects) in the conventional BULK architecture will be presented [65], as well as a more advanced transistor architecture, namely the Fully Depleted Silicon On Insulator (FDSOI) MOSFET [START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI[END_REF]. The latter architecture is a promising candidate for monolithic 3D circuits and the one that this thesis focuses on. Moreover, the theory of electromagnetic coupling under a circuit analysis approximation [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF] will be detailed to allow a deeper understanding of coupling effects in 3DSI. Finally, the basic methods for noise analysis in analog and digital systems will be reviewed [START_REF] Geiger | VLSI design techniques for analog and digital circuits[END_REF], [START_REF] Tsividis | Mixed Analog-Digital VLSI Devices and Technology[END_REF].

The MOSFET transistor

The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) is the basic building block of CMOS (Complementary Metal Oxide Semiconductor) integrated circuits. This device is comprised of four electrodes, the Gate (G), the Drain (D), the Source (S) and the Body (B), illustrated in Fig. 2.1.

The Gate stack is composed of a bilayer structure consisting of a metal on the top of an oxide. The Source and Drain electrodes are comprised of highly doped semiconductor regions (10 20 cm -3 ), P or N-type for PMOS or NMOS device respectively, accessed by metallic contacts.

The minimum distance between the S/D metallic contacts, also referred to as CPP (Contacted Poly Pitch), is a technology parameter that sets the transistor pitch and hence the density of an integrated circuit. Moreover, the channel area of the semiconductor is doped, with doping concentration N A at a level between 10 16 cm -3 and 10 18 cm -3 and polarity depending on the MOS type: N-type well for P-MOS and P-type well for N-MOS devices. Lastly, the Body features a highly doped semiconductor substrate (10 20 cm -3 ) and the applied bias to its rear face is denoted V B .

The MOSFET operation takes advantage of the field effect induced by the applied Gate electrode bias. By that, it can block or allow a current to flow between the Source and the Drain, operating as a switch controlled by voltage. Indeed, the vertical electric field due to the polarization of the Gate electrode, modulates the density of carriers in the semiconductor, leading in two states of operation for the ideal MOSFET transistor as follows:

• The blocked state: no current flows between source and drain

• The passing state: a conduction channel is induced by the gate vertical electric field and under the influence of the horizontal field (due to the higher biasing of the drain against the source), the carriers of the channel (electrons for a NMOS and holes for a PMOS device) form a current flowing between source and drain electrodes (I DS ).

Metal-Oxide-Semiconductor Capacitor operation regimes

The MOSFET owes its voltage-controlled switching properties to the MOS capacitor (Fig. 2.2 (a)). Applying a positive voltage bias at the gate (V G > 0) will cause a voltage drop across the oxide (ΔV ox ) and the semiconductor (ΔV si ), hence

𝑉 𝐺 = 𝛥𝑉 𝑜𝑥 + 𝛥𝑉 𝑠𝑖 (2-1)
Supposing that the substrate (body) is grounded, ΔV si is equal to the surface potential ψ s . The voltage drop across the oxide ΔV ox can be calculated from

𝛥𝑉 𝑜𝑥 = 𝐸 𝑜𝑥 𝑡 𝑜𝑥 (2-2)
where E ox is the vertical electric field and t ox is the thickness of the oxide. Applying Gauss's law at the surface layer of the semiconductor we obtain

𝐷 𝑜𝑥 = 𝜀 𝑜𝑥 𝐸 𝑜𝑥 = -𝑄 𝑠 (𝜓 𝑠 ) (2-3)
with 𝑄 𝑠 being the charge at the surface layer of the semiconductor creating the displacement field

𝜓 𝐵 = 𝑘 𝐵 𝑇 𝑞 ln ( 𝑁 𝐴 𝑛 𝑖 ) (2-6) E c E f E v V G >0 ψ s E f ΔV ox t D E i depth M O S
where q is the elementary charge, k B is Boltzmann constant, T the temperature and n i is the intrinsic carrier concentration.

The flat band voltage equals the gate voltage for which the energy bands across the semiconductor are flat. In any structure it occurs at a finite voltage and is the outcome of two effects.

It can be calculated by

𝑉 𝐹𝐵 = 𝜑 𝑚𝑠 + 𝑄 𝐹 𝐶 𝑜𝑥 (2-7)
where φ ms is the metal-semiconductor work-function difference, Q F is the sheet charge at the oxidesilicon interface and C ox is the oxide capacitance per unit area.

To understand qualitatively the response of the MOS capacitor to the applied gate voltage, we should have a look at the value of the electrostatic potential at the oxide-semiconductor interface.

Relating the value of the surface potential ψ S to ψ B , the operation of the MOS capacitor can be broken down into three separate regimes (Fig. 2.3). In the case of an NMOS capacitor (the majority carriers are the holes and the minority are electrons) the operation is divided in:

• Accumulation region (ψ s <0): The vertical field imposed by the gate electrode, is oriented upwards, the electrons are pushed away from the oxide-semiconductor interface, while the holes are attracted towards the oxide where they accumulate. The variation of the accumulation charge Q A is exponential and increases with |ψ s |.

• Depletion region (0 < ψ s < ψ B ): The gate vertical field has the opposite direction and is facing down. Electrons from the substrate are attracted to the oxide-semiconductor interface, filling the holes creating a zone without free carriers, called depletion zone.

This zone is negatively charged, because it is solely composed of ionized dopants (acceptors in this example because the silicon is of type P). The variation in depletion charge Q D is proportional to √𝜓 𝑆 .

• Inversion region (ψ s > ψ B ): The depletion zone stops increasing in depth and the vertical field is strong enough to attract free electrons (minority carriers) to the oxidesemiconductor interface to the oxide-semiconductor interface. The charge variation of type P silicon is then due to minority carriers; thus, the polarity of the channel is inverted. This region is divided into two parts, the weak and the strong inversion. In weak inversion (ψ s < 2ψ B ) the inversion charge Q I remains proportional to √𝜓 𝑆 .

However, when in strong inversion (ψ s > 2ψ B ) the Q inv reversal charge growth increases exponentially with ψ s .

Fig. 2.3 Variation of surface charge density (accumulation charge and inversion charge) as a function of surface potential.

For a PMOS capacitor the majority carriers are electrons and the minority carriers are holes.

The principle of operation remains the same except that the polarity of the voltage applied to the Gate electrode is reversed. The drain current of a MOSFET can be modeled as a function of the gate-to-source and drainto-source voltages and depending on the region of operation, it can be written as:

Definition of MOSFET electrical parameters

𝐼 𝐷𝑆 = 𝑓(𝑉 𝐺𝑆 , 𝑉 𝐷𝑆 ) = { ~0 , 𝑉 𝐺𝑆 < 𝑉 𝑇𝐻 [𝒄𝒖𝒕𝒐𝒇𝒇] 𝑊 𝐿 • 𝜇 • 𝐶 𝑜𝑥 (𝑉 𝐺𝑆 -𝑉 𝑇𝐻 - 𝑉 𝐷𝑆 2 ) 𝑉 𝐷𝑆 , ( 𝑉 𝐺𝑆 ≥ 𝑉 𝑇𝐻 & 𝑉 𝐷𝑆 < 𝑉 𝐺𝑆 -𝑉 𝑇𝐻 ) [𝒍𝒊𝒏𝒆𝒂𝒓] 𝑊 𝐿 • 𝜇 • 𝐶 𝑜𝑥 (𝑉 𝐺𝑆 -𝑉 𝑇𝐻 )

Threshold voltage (V TH ):

The threshold voltage of a MOSFET is the gate to source voltage V GS at which the conduction channel between source and drain is formed, thus the device turns on. Quantitatively, this means that the amount of minority carriers must be greater than the number of ionized dopants in the channel (acceptors for an NMOS), of density equal to the doping level N A . The threshold is therefore given by the equality between these two quantities. In terms of the surface potential, the threshold is the voltage at which strong inversion occurs, thus when the value of the surface potential is ψ s =2ψ f .

𝑉 𝑇𝐻 = 𝑉 𝐹𝐵 + 2𝜓 𝐵 + 𝑉 𝑆 + 𝛾√𝑉 𝑆𝐵 + 2𝜓 𝐹 [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF] where 𝛾 =

𝑆𝑊 = ln (10) 𝑘𝑇 𝑞 (1 + 𝐶 𝑑 𝐶 𝑜𝑥 ) (2-9)
where C d and C ox are the depletion layer and oxide capacitance respectively.

ON-State current (I on ):

is the drain current when both the drain and gate bias equals the power supply voltage, V DD (V GS = V DS = V DD ). The latter is a technology dependent parameter, i.e., determined by the characteristic dimensions of the device.

Body effect

The bias at the body electrode of a MOSFET is conventionally set to the ground potential.

Hence, if the source electrode is also grounded, which is the typical case for amplifying transistors, then there is no voltage difference between the two. However, in a Source Follower (SF) configuration of the MOSFET, the source of the transistor is at a higher voltage. Thus, there is a source-body voltage V SB which changes the threshold voltage of the MOSFET given by [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF]. The influence of source-bulk voltage in the drain current due to the change of the threshold voltage is named body effect.

As observed from (2-8) the variation of the threshold voltage with the V SB is not linear. However if it is linearized, a simplified expression for the drain current can be defined in linear region [START_REF] Colinge | Silicon-on-Insulator Technology: Materials to VLSI[END_REF],

𝐼 𝐷𝑆,𝑙𝑖𝑛 = 𝑊 𝐿 • 𝜇 • 𝐶 𝑜𝑥 (𝑉 𝐺𝑆 -𝑉 𝑇𝐻 -𝑛 𝑉 𝐷𝑆 2
) 𝑉 𝐷𝑆 [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF] and in saturation region

𝐼 𝐷𝑆,𝑠𝑎𝑡 = 𝑊 𝐿 • 𝜇 • 𝐶 𝑜𝑥 (𝑉 𝐺𝑆 -𝑉 𝑇𝐻 ) 2 2𝑛 (2-11)
where

𝑛 = 1 + 𝑄 𝐷 𝐶 𝑜𝑥 = 1 + 𝜀 𝑠𝑖 𝑥 𝑑𝑒𝑝𝑙 ⁄ 𝐶 𝑜𝑥
is the Body Factor (BF).

Short-channel effects

So far, the ideal MOSFET device behavior was considered. However, there is a significant impact of the dimensional scaling of the MOSFET device on its electrical parameters, hence on its current-voltage characteristics.

As illustrated in Fig. 2.5, the depletion zone formed by the source and drain diffusion areas extends on the side of the junction which is the least doped, therefore in the substrate. For long channel transistors, this extension of the depletion zones is negligible compared to the total gate length and this effect has negligible impact on the electrical behavior of the transistor (Fig. 2.5 (a)).

However, with the downscaling of the gate length, the extension of the depletion zones becomes comparable to the channel length and the gate loses partially the electrostatic control of the channel (Fig. 2.5 (b)). As a result, there is a "V TH roll-off" effect in short lengths (Fig. 2.6). In addition, if a bias is applied to the drain (the source is conventionally grounded), the depletion zone on the drain diffusion area increases deeper inside the channel, decreasing the effective gate length ("Channel Length Modulation" effect) and therefore not allowing the current to saturate above V DS =V GS -V TH . For even higher V DS values, the drain depletion zone extends even further into the substrate until it overlaps with the source depletion zone.

Fig. 2.6

The threshold voltage of a Long channel transistor (V TH,long ) remains constant versus the gate length, however short channel transistors experience an exponential decrease of their threshold voltage (V TH,short ). Nevertheless, due to DIBL effect, the threshold voltage of a short channel transistor is further reduced for a strong drain bias.

I D L G V TH,short (linear)
V TH,short (saturation)

V TH,long
As a result, the electrostatic control of the gate is further reduced by the drain bias in the case of a short channel transistor. This overlapping of the source/drain depletion zones due to a strong drain bias results in a potential barrier lowering at the source-body junction. The resulting threshold voltage reduction defines the DIBL. The overall result is a decrease in the threshold voltage with the downscaling of the gate length which is more evident when the transistor is in the saturation region (Fig. 2.6).

2.2

The FD-SOI device architecture

SOI substrate technology

The SOI technology refers to a silicon semiconductor device in a layered silicon-insulatorsilicon substrate (Fig. Transistors on SOI substrates were used for the first time in military and space fields applications [START_REF] Leray | CMOS/SOI hardening at 100 Mrad(SiO2)[END_REF], [START_REF] Hite | An SEU Resistant 256K SOI SRAM[END_REF] thanks to their immunity to radiation. Nowadays, in consumer electronics, SOI transistors have been commercialized since the 28nm node [START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF]. In particular the FD-SOI (Fully Depleted Silicon On Insulator) in the UTBB (Ultra-Thin Body and BOX) configuration is the MOSFET architecture that is widely preferred for low-power/low-voltage CMOS applications due to superior performance against the BULK architecture (low Sub-Threshold Swing, low DIBL, Body-Biasing efficiency, reduced S/D coupling).

FDSOI device geometry

The three-dimensional representation of a FDSOI MOSFET is illustrated in Fig. bias. Thus the variability is reduced drastically, with values of AΔV TΗ reported, as low as 1.6 mV•μm [START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF].

Due to the thin silicon film, the Source and Drain are elevated to limit the series resistance. In order to accomplish that, the raised S/D regions are epitaxial processed upon the thin silicon film of the active layer as shown in Fig. 2.8 (b).

Finally, the field lines from the source and drain diffusion regions penetrate the BOX resulting in a capacitive coupling between drain and channel, causing DIBL effect to elevate. To limit this effect, the BOX thickness must be as thin as 25nm along with a doped layer (namely Ground Plane (GP)) [START_REF] Ernst | The ground-plane concept for the reduction of short-channel effects in fully-depleted SOI devices[END_REF] of the type opposite to the source/drain regions under the thin BOX. The latter limits the effective thickness of the BOX to its physical thickness and eliminates the capacitive coupling effect between the source and drain regions.

Front/Back interface charge coupling

In SOI MOSFETs, the charge coupling between the front and back interface is characterized by the charge-coupling factor r that expresses the sensitivity of the threshold voltage (V TH ) to changes in the BG voltage (V B ). Due to the existence of the front at back interfaces, there is a front/back channel threshold voltage (V TH,f , V TH,b ), dependent on the front/back-gate biases (V G,f , V G,b ), as well as the other physical quantities (V FB,f , V FB,b etc.).

a) b)

Fig. 2.9 The channel capacitance network formed in a BULK (a) and a SOI (b) MOSFET.

For long-channel devices, early models [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF] have solved the electrostatics of FDSOI MOSFETs Q i is the inversion-charge density within the silicon film. By this assumption, free carriers cannot sufficiently screen the applied potential within t Si , and hence the potential distribution in the entire body is virtually independent of Q i . The second assumption considers inversion-charge sheets at the front and/or back surfaces of the silicon film, due to the high transverse electric field imposed by the gate electrode, which confines the inversion charge carriers near the surfaces in a region much thinner than the silicon film thickness. Since Qi and its effect on the potential distribution are negligible, the charge-sheet approximation is superfluous for subthreshold analysis. Solving the (1-D)

Poisson equation with the charge sheet and the depletion approximation, one can easily obtain the two equations in the Lim and Fossum model [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF]:

𝑉 𝐺𝑓𝑆 -𝑉 𝐹𝐵𝑓 = (1 + 𝐶 𝑠𝑖 𝐶 𝑜𝑥 ) 𝜑 𝑠𝑓 - 𝐶 𝑠𝑖 𝐶 𝑜𝑥 𝜑 𝑠𝑏 (2-12) V S =0 V D =0 V G V B φ s C ox C D X depl n+ n+ p V S =0 V D =0 V G V B φ s C ox C si t si n+ n+ p C BOX 𝑉 𝐺𝑏𝑆 -𝑉 𝐹𝐵𝑏 = - 𝐶 𝑠𝑖 𝐶 𝑏𝑜𝑥 𝜑 𝑠𝑓 + (1 + 𝐶 𝑠𝑖 𝐶 𝑏𝑜𝑥
) 𝜑 𝑠𝑏 [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF] where ϕ sb is the back-surface potential, 𝐶 𝑠𝑖 = 𝑡 𝑠𝑖 𝜀 𝑠𝑖 being the silicon film capacitance per unit area and the subscripts f and b refer to front and back gates of the device respectively. With ϕ sb from [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF] and ϕ sf =2ϕ B (for NMOS), as long as the back surface remains depleted, (2-12) becomes [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF]:

𝑉 𝐺𝑓𝑆 = 𝑉 𝑇𝐻,𝑓 = 𝑉 𝐹𝐵𝑓 + 𝑟𝑉 𝐹𝐵𝑏 + (1 + 𝑟)2𝜑 𝐵 -𝑟𝑉 𝐺𝑏𝑆 (2-14)
where

𝑟 = 𝐶 𝑏𝑜𝑥 𝐶 𝑠𝑖 𝐶 𝑜𝑥 (𝐶 𝑏𝑜𝑥 + 𝐶 𝑠𝑖 ) (2-15)
is the slope of the linear region of the front-gate coupling characteristic (variation of the front gate threshold voltage V TH,f with the back-gate voltage V Gb ). The above expression is referred in the literature as the charge-coupling factor. From the latter, it is evident that the threshold voltage of one gate varies linearly (Fig. 2.10) with the opposite gate bias as long as the back silicon film interface is depleted and saturates with onsets of strong accumulation or inversion at the opposite interface. Similarly to the BULK MOSFET, the BF of SOI MOSFET is defined as

𝑛 = 1 + 𝑄 𝐷 𝐶 𝑜𝑥 = 1 + 𝐶 𝑏𝑜𝑥 𝐶 𝑠𝑖 𝐶 𝑜𝑥 (𝐶 𝑏𝑜𝑥 + 𝐶 𝑠𝑖 ) = 1 + 𝑟 (2-16)

Back accumulation

Back inversion

Back depletion V TH,f V G,b

Electromagnetic coupling and transfer of energy between electrical components

Any circuit element of a network can be coupled with an adjacent one even when they are not physically connected by a conductive material. The transfer of energy can be induced by the electric and magnetic fields that surround the two circuit elements.

Electric fields are caused by electric charges, described by Gauss's law or varying magnetic fields, described by Faraday's law of electromagnetic induction. In the same manner, magnetic fields are formed by changing currents as described by Ampere's circuital law. These principles characterize the complementary nature of the electric and magnetic fields and are summarized in the form of the Maxwell equations, presented in Table 2.1. The vector fields 𝑬 ⃗ ⃗ (V/m) and 𝑯 ⃗⃗⃗ (A/m) represent the intensity of the electric and magnetic field respectively, whereas 𝑫 ⃗⃗ (C⋅m -2 ) is the electric displacement field and 𝑩 ⃗⃗ (Wb) is the magnetic flux density.

Differential Form

Integral Form

Gauss' law

𝛻 • 𝐸 ⃗ = 𝜌/𝜀 0 ∮ 𝐷 ⃗ ⃗ • 𝑑𝐴 𝑆 = ∫ 𝜌𝑑𝑉 ⃗ 𝑉 Gauss'law (magnetism) 𝛻 • 𝐵 ⃗ = 0 ∮ 𝐵 ⃗ • 𝑑𝐴 𝑆 = 0 Faraday's law 𝛻 × 𝐸 ⃗ = 𝜕𝐵 ⃗ 𝜕𝑡 ∮ 𝐸 ⃗ • 𝑑𝑙 𝐶 = - 𝜕 𝜕𝑡 ∫ 𝐵 ⃗ • 𝑑𝐴 𝑆 Ampere's circuital law 𝛻 × 𝐻 ⃗ ⃗ = 𝐽 + 𝜕𝐷 ⃗ ⃗ 𝜕𝑡 ∮ 𝐵 ⃗ • 𝑑𝑙 𝐶 = ∫ 𝐽 • 𝑑𝐴 𝑆 + 𝜕 𝜕𝑡 ∫ 𝐷 ⃗ ⃗ • 𝑑𝐴 𝑆
As a consequence, in order to assess how any electric circuit behaves, the exact solution of

Maxwell's equations is needed. These equations constitute a four-dimensional problem (x, y, z, t), so even the simplest problems can be proven highly complex.

To simplify things, an approximation is often used in circuits, named circuit analysis. This technique facilitates the problem considering a discrete representation of the electric and magnetic fields coupling by lumped electric components (i.e., capacitors and inductors) where voltage and current do not vary significantly over the physical dimension of the elements. The analysis considers the following:

• All electric fields are confined to the interiors of capacitors.

• All magnetic fields are confined to the interiors of inductors.

• Dimensions of the circuit are small compared with the wavelength under consideration.

Specifically, the electrical size of the structures (i.e., the ratio of the largest distance between two points in the structure divided by the wavelength of the electromagnetic fields) must be in the range up to 1/10.

Utilizing this technique, any coupling problem can be described accurately by considering victim-aggressor pairs that consist a network of passive elements within a circuit. It is important to emphasize that in the case where the physical dimensions of the network are comparable to the electrical wavelength, circuit analysis is not valid. Instead, transmission line theory must be used in which the circuit is considered as a distributed-parameter network, where voltages and currents can vary in magnitude and phase over its length.

The most basic lumped elements, adequate to describe any coupling effect in a circuit analysis are summarized in table 2.2. Mutual Inductance (M)

𝑣 1 = 𝑀 𝑑𝑖 2 𝑑𝑡 + 𝐿 1 𝑑𝑖 1 𝑑𝑡 𝑣 2 = 𝑀 𝑑𝑖 1 𝑑𝑡 + 𝐿 2 𝑑𝑖 2 𝑑𝑡 Henry [H]

Noise sources in devices and circuits

Every fluctuation existing in an electrical signal other than the desired one can be considered as noise. We can classify the noise sources as intrinsic and extrinsic. The former is generated in the electronic circuit element itself whereas the second, called also coupled noise, is induced by external interferences.

Intrinsic noise sources

The intrinsic noise of an electronic circuit element is a random process, characterized by stochastic properties such as its variance, distribution, and Power Spectral Density (PSD). The spectral distribution of noise can vary with frequency, so its PSD is measured in Watts per Hertz (W/Hz). Since power in a resistive element is proportional to the square of the voltage across it, noise voltage (density) can be described by taking the square root of the noise power density, resulting in volts per square root hertz (𝑉/√𝐻𝑧). Different types of intrinsic noise sources exist generated by different electronic components. These types are:

Thermal noise or Johnson noise: is caused by the random thermal motion of the charge carriers (holes or electrons), and the voltage PSD associated with it, is given from the expression

𝑆 𝑉,𝑡ℎ𝑒𝑟𝑚𝑎𝑙 = 4 • 𝑘 • 𝑇 • 𝑅 (2-17)
where R the resistance in Ohms, k is the Boltzmann constant, T is the temperature of the conductor in Kelvin degrees. It is also known as Johnson or Nyquist noise. Integrating the PSD of thermal noise over the noise bandwidth ΔF and taking the square root of it, the voltage noise RMS (root mean square) that a resistive element generates is given from the expression

𝑣 𝑛 = √4 • 𝑘 • 𝑇 • 𝑅 • 𝛥𝐹 (2-18)
Shot noise: is a type of noise that originates from the discrete nature of electric charge in semiconductor devices like p-n junctions. It consists of random fluctuations of a DC current I, characterized by a PSD

𝑆 𝐼,𝑠ℎ𝑜𝑡 = 2𝑞𝐼 (2-19)
Low Frequency Noise (LFN): is a type of noise occurring in semiconductor devices with a 1/f γ PSD and is often used for the characterization of material or interfaces quality. The dominant mechanism is the Generation -Recombination (G-R) noise that results in the fluctuation of free carriers inside the channel (Δn) whereas the second mechanism is scattering which leads to mobility fluctuations (Δμ).

In the literature, the LFN modeling is subject to the following three approaches:

Carrier Number Fluctuations (CNF) model

In the CNF approach [START_REF] Mcwhorter | 1/F Noise and Germanium Surface Properties[END_REF], the drain current fluctuations are related to the free carriers located inside channel close to the oxide-semiconductor interface that are tunneled into dielectric traps under a trapping and de-trapping activity.

Individual traps or a group of traps with same characteristics lead to a Lorentzian shaped (1/f 2 ) PSD (Fig. 2.11 (a)) contrary to 1/f in the case of a uniform spatial trap distribution (Fig. 2.11 (b)). In the case of an uneven distribution, it can be considered as a summation of Lorentzian spectra as depicted for instance in Fig. 2.12 (a) and Fig. 2.12 (b).

Mobility Fluctuations or Hooge model

The Hooge noise model [START_REF] Hooge | Experimental studies on 1/f noise[END_REF] suggests that the 1/f noise is the result of bulk mobility fluctuations due to phonon scattering. It is an empirical model that tends to explain better the observed 1/f noise in p-channel MOSFETs, contrary to n-channel devices.

Carrier Number Fluctuations with correlated Mobility Fluctuations (CNF/CMF) model

The The interface charge variation δQ it can be translated into a flat band voltage variation as

𝛿𝑉 𝐹𝐵 = - 𝛿𝑄 𝑖𝑡 𝑊𝐿𝐶 𝑜𝑥 (2-20)
with C ox being the oxide capacitance per unit area and WL the device area. The overall drain current fluctuations become for the linear operation region [START_REF] Hung | A Unified Model For The Flicker Noise In Metal-Oxide-Semiconductor Field-Effect Transistors[END_REF], [START_REF] Ghibaudo | Improved Analysis of Low Frequency Noise in Field-Effect MOS Transistors[END_REF] 𝛿𝐼 𝐷 = -𝑔 with S Vfb being the flat band voltage PSD.

Extrinsic noise sources

In general, noise energy can be coupled into a circuit from many sources of the external environment (light, cell phones, mechanical vibrations etc.). Thus, in our analysis we will focus exclusively on the extrinsic noise originated by adjacent circuit elements. This type of noise is often named crosstalk in electronics and the aggressor is the crosstalk source within a circuit, as opposed to the victim being the receptor of the interference. It can be characterized as capacitive coupling when the transfer of energy is induced by the electric field, contrary to the inductive coupling which is attributed to the magnetic field created by the aggressor. Contrary to intrinsic noise which has a stochastic nature, extrinsic noise originated by adjacent circuit elements has deterministic properties and thus may be predictable.

2.4.2.a Capacitive coupling

Fig. In the case that ω>>1/R(C 12 +C 2G ) equation becomes

𝑉 2 = ( 𝐶 12 𝐶 12 + 𝐶 2𝐺 ) 𝑉 1 (2-25)
However, in the low-frequency case that ω<<1/R(C 12 +C 2G ), the voltage picked by conductor 2 is

𝑉 2 = 𝑗𝜔𝑅𝐶 12 𝑉 1 (2-26)
which is proportional to the frequency of the aggressor's signal and of lower magnitude than the one of . Therefore the capacitive coupling can be modeled as a current source connected between the receptor and ground, of magnitude given by [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF],

𝐼 2 = 𝑗𝜔𝐶 12 𝑉 1 (2-27)

2.4.2.b Capacitive shielding

From EMC theory it is well known that a conductive surface surrounding the 'victim' can act as a shield against the electromagnetic coupling from the 'aggressor'. To understand the effect of shielding against the capacitive coupling, the case of two coupled conductors shall be considered, with the aggressor being the noise source and the victim surrounded by a shield as shown in the equivalent circuit of Fig. 2.15. The shield consists of a conductive material and encloses completely the receptor conductor. In case that the shield is not terminated, R SG is infinitely large. Therefore the capacitance network consists in a voltage divider and hence the noise voltage on the shield is given by [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF],

𝑉 𝑆 = ( 𝐶 1𝑆 𝐶 1𝑆 + 𝐶 𝑆𝐺 ) 𝑉 1 (2-28)
where C 1S is the capacitance between conductor 1 and the shield whereas C SG is the stray capacitance of the shield to ground. Since conductor 2 is floating, there is no current flowing through C 2S , thus the noise voltage picked from the shield is transferred to the receptor conductor (V S =V N ). However, if the shield is grounded properly (R SG =0), the voltage on the shield is V S =0 and so is the noise voltage picked by conductor 2.

In most practical cases, conductor 2 extends beyond the shielding surface so there is a coupling capacitance C 12 between conductors 1, 2 and also a stray capacitance C 2G of conductor 2 to the ground. In that case the voltage picked by conductor 2 is

𝑉 2 = ( 𝐶 12 𝐶 12 + 𝐶 2𝐺 + 𝐶 2𝑆 ) 𝑉 1 (2-29)
As observed from (2-29), V 2 depends primarily on C 12 . The latter may be due to the exposed area of conductor 2 as well as the efficiency of the shielding material to suppress the electromagnetic field of conductor 1. Hence for an effective shielding of the capacitive coupling between two conductors, it is mandatory to properly ground the shield and minimize C 12 .

In most cases the conductor 2 has a finite resistance to ground (Fig. 2.15), and also

𝑅 2𝐺 ≪ 1 𝑗𝜔(𝐶 12 +𝐶 2𝐺 +𝐶 2𝑆 )
, so the noise voltage picked by conductor 2 is

𝑉 2 = 𝑗𝜔𝑅 2𝐺 𝐶 12 𝑉 1 (2-30)
which is the same as for an unshielded conductor, however C 12 is reduced significantly due to the presence of the shield.

2.4.2.c Inductive coupling

A conductor which carries an electric current produces a magnetic field with a form of concentric circles surrounding the conductor. The direction of the magnetic field is perpendicular to the conductor and the magnetic flux is proportional to the current. The ratio of the total magnetic flux Φ T to the current that produces it, determines the self-inductance of the conductor given by [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF],

𝐿 = 𝛷 𝑇 𝐼 (2-31)
When current flows also in an adjacent conductor 2, the magnetic field produced from conductor 1 is coupled to conductor 2, creating a mutual inductance M 12 defined as

𝑀 12 = 𝛷 12 𝐼 1 (2-32)
where Φ 12 is the magnetic flux in conductor 2 from current I 1 flowing through conductor 1. Applying Faraday's law to the closed loop or area 𝑨 ⃗⃗ , the coupled voltage V 2 induced by the magnetic field is derived as

𝑉 2 = - 𝑑 𝑑𝑡 ∫ 𝐵 ⃗ ⃗ • 𝑑𝐴 ⃗ ⃗ 𝑆 (2-33)
If the conductor 1 is stationary and the magnetic flux density is harmonically varying with time but constant over the area of the loop, becomes

𝑉 2 = 𝑗𝜔𝐵𝐴 cos 𝛩 (2-34)
where θ is the angle between 𝐵 ⃗ and 𝐴 . Considering that the term 𝑩𝑨 𝐜𝐨𝐬 𝜣 represents the total magnetic flux Φ 12 coupled to the receptor circuit, (2-32) and (2-34) can be merged and the coupled noise voltage is expressed ultimately as

𝑉 2 = 𝑗𝜔𝑀 12 𝐼 1 (2-35)
The physical representation as well as the equivalent circuit of inductive coupling is illustrated in Fig.

2.16.

Fig. 2.16 Inductive coupling between conductors 1 and 2.

2.4.2.d Inductive shielding

As opposed to the capacitive coupling shielding, the inductive coupling is way more difficult to be reduced. A non-magnetic conductive surface enclosing the receptor conductor 2 has no effect on the geometry or magnetic properties of the medium between conductors 1 and 2, and consequently has no effect on the voltage induced into conductor 2. However, a voltage is coupled to the shield because of the current I 1 flowing through conductor 1, given by [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF],

𝑉 𝑆 = 𝑗𝜔𝑀 1𝑆 𝐼 1 (2-36)
where M 1S is the mutual inductance between the conductor 1 and the shield. A ground connection at one end of the shield has no impact on this magnetically induced voltage. On the contrary, if the shield is grounded at both ends, the voltage V S will cause a current to flow through the shield. As an outcome, the shield current will induce a second noise voltage into the receptor conductor 2, which can potentially worsen its noise coupling level.

Following that, the magnetic field decoupling analysis is rather complex and goes beyond the scope of this thesis. Each case must be treated separately, taking this into account the geometry of the problem. A shield can be effective only if the induced shield current that produces the magnetic field is, cancels a large percentage of the direct induction into conductor 2. In any case the key to reducing magnetic coupling is to avoid loop configurations of both the receptor and aggressor conductors.

Noise coupling in circuits

Analog systems differ substantially from digital ones in terms of signal processing. An analog signal can obtain any value within the power supply range counter to digital signal which has a value between two logic levels.

2.4.3.a Digital noise

Due to the fact that signals in nature are analog, digital electronics utilize by convention the minimum and maximum values of the power supply range to represent the "low" and "high" of a digital signal. As a consequence, the power supply range is divided into the logical high and logical low range and any other value within the two falls into the indeterminate range (Fig. 2.17). In general digital circuits present an inherent immunity to noise injected from external sources. This property emanates from the input-output noise margins, NM L and NM H , which refer to the ability of a logic gate to accommodate input noise without producing a faulty logic output.

The methodology for the noise margins estimation in CMOS technology has been presented in [START_REF] Geiger | VLSI design techniques for analog and digital circuits[END_REF]. Following that, the noise margins of a CMOS logic gate can be found by first examining the DC transfer curve shown in Fig. 2.18. The input noise threshold levels, V IL and V IH are defined as the input voltages that result in a slope of -1 in the dV out /dV in response. From graphical analysis, V IL occurs when the PMOS is in its linear regime and the NMOS is in its saturation regime. Since a CMOS gate is complementary in operation, V IH by symmetry occurs when the PMOS is in its saturation regime and the NMOS is in its linear regime. Considering first the CMOS V IL , equating the NMOS and PMOS currents gives [START_REF] Geiger | VLSI design techniques for analog and digital circuits[END_REF]:

𝑘 𝑛 𝑊 𝑛 𝐿 𝑛 (𝑉 𝑖𝑛 -𝑉 𝑇𝐻𝑛 ) 2 2 = 𝑘 𝑝 𝑊 𝑝 𝐿 𝑝 (𝑉 𝑖𝑛 -𝑉 𝐷𝐷 -𝑉 𝑇𝐻𝑝 - 𝑉 𝑜𝑢𝑡 -𝑉 𝐷𝐷 2 ) (𝑉 𝑜𝑢𝑡 -𝑉 𝐷𝐷 ) (2-37)
where k n/p =μ n/p Again, using the previous assumption, this expression can be simplified such as

𝑉 𝐼𝐻 = 5𝑉 𝐷𝐷 + 5𝑉 𝑇𝐻𝑝 + 3𝑉 𝑇𝐻𝑛 8 (2-41) V in V DD V OH V out V DD V IH V IL V OL V IL V IH NM L NM H
Chapter 2 -Physics of MOSFETs and coupling effects [START_REF] Koneru | Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing[END_REF] The noise margins are given as 𝑁𝑀 𝐿 = 𝑉 𝐼𝐿 -𝑉 𝑂𝐿 𝑁𝑀 𝐻 = 𝑉 𝑂𝐻 -𝑉 𝐼𝐻 where V OL and V OH are 0 and V DD respectively for CMOS technology. Consequently, equations and become

𝑁𝑀 𝐿 = 3𝑉 𝐷𝐷 + 3𝑉 𝑇𝐻𝑝 + 5𝑉 𝑇𝐻𝑛 8 (2-44) 𝑁𝑀 𝐻 = 𝑉 𝐷𝐷 - 5𝑉 𝐷𝐷 + 5𝑉 𝑇𝐻𝑝 + 3𝑉 𝑇𝐻𝑛 8 (2-45)

2.4.3.b Analog noise

From an analog system perspective, noise is typically characterized by its impact as a smallsignal fluctuation. Considering that, noise is modeled as an independent alternating current (AC) source (Fig. 2.19). In a small signal noise analysis, the noise PSD is utilized in order to obtain the noise magnitude (either voltage V N or current I N ) and compare that to the signal magnitude. Hence, a significant quantity for determining the impact of noise in analog circuit is the Signalto-Noise-Ratio (SNR). The SNR represents the ratio of the useful signal to the unwanted parasitic signals. Therefore, it must be as high as possible, achieved by increasing the system's sensitivity and more importantly, by decreasing the noise.

The dominant noise in analog circuits is the intrinsic noise of the MOSFET transistors. The two major sources are the thermal and the LFN, both of them explained in §(2-4). The latter is not only important in conventional analog circuits like operational amplifiers, but also in RF circuits like Voltage Controlled Oscillators (VCOs), where the LFN up-converts to phase/jitter noise [START_REF] Hajimiri | A general theory of phase noise in electrical oscillators[END_REF].

Furthermore, a special case of LFN, namely the Random Telegraph Signal (RTS) noise, becomes of high importance with the MOSFET device downscaling [START_REF] Ghibaudo | Impact of Scaling Down on Low Frequency Noise in Silicon MOS Transistors[END_REF], and consequently for highly miniaturized sensor applications like the pixel readout part of an imager circuit [START_REF] Findlater | Source follower noise limitations in CMOS active pixel sensors[END_REF], [START_REF] Leyris | Impact of random telegraph signal in CMOS image sensors for low-light levels[END_REF].

2.4.3.c Mixed-Signal noise coupling

The mixture of analog and digital applications within the same chip, implies an electromagnetic interference between them unless there is proper shielding. Thus, each of them can be considered as an aggressor or victim to the other. As presented in §2.4.2, the electromagnetic coupling depends both on the amplitude and the frequency of the aggressor's signal. Thus, it is evident that high speed electronic circuits can be an intense noise source, while their amplitude is limited to the power supply range.

Analog microwave circuits, called also RF more commonly, utilize bandpass signals at frequencies above 1GHz [START_REF] Razavi | RF Microelectronics[END_REF], whereas there is a special distinction for circuits at frequencies above 30 GHz which are designated for mmW applications. Except for individual transistors they can also feature micro-strip transmission lines, filters, matching networks and other elements. In the frequency domain, transistors are characterized by the "transition frequency" f T and the f max which set their maximum frequency limit.

On the other hand, digital circuits employ pulse switching signals above 100MHz reaching sub-nanosecond rise time [START_REF] Banerjee | Interconnect modeling and analysis in the nanometer era: Cu and beyond[END_REF] nowadays. The harmonic content of a pulse shaped signal extends to infinity; however, its energy content fades with increasing frequency. Hence, there is a point beyond which it can be neglected and occurs at the break point where the Fourier coefficients start to decay at 40 dB/decade, instead of 20 dB/decade [START_REF] Ott | Electromagnetic Compatibility Engineering[END_REF]. As a result, the bandwidth of a digital signal can be given by

𝐵𝑊 = 1 𝜋𝑡 𝑅 (2-46)
where t R is the rise time of the pulse shaped signal. For instance in 28nm FDSOI technology, rise times of 10ps have reported [START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF], resulting in an equivalent bandwidth of 31.8GHz for a digital signal.

Therefore, the limitation of the harmonic content of digital signals to a certain bandwidth for a given technology, in conjunction with the maximum operating frequency of RF devices can help estimate the impact of electromagnetic coupling in mixed-mode monolithic 3D circuits.

Chapter 2 -Physics of MOSFETs and coupling effects 54

Conclusion

In this chapter the MOSFET device physics have been reviewed accompanied by the specificities of the SOI versus the conventional BULK architecture. Accounting for the MOSFET device operation, the basic electrical parameters utilized within this work, have been highlighted for the two architectures. In addition, the noise sources existing in electronic devices alongside with the noise coupling mechanisms have been assessed. In particular, the PSD generated from an electronic component has been evaluated for each noise mechanism while it has been demonstrated how this noise can be propagated to adjacent components in terms of voltage or current. Nonetheless, noise analysis methods for analog and digital systems have been noted, emphasizing on the noise susceptibility of each one.

INVESTIGATION OF 3DSI ELECTROMAGNETIC COUPLING EFFECTS AT A DEVICE LEVEL

First of all, this chapter describes the 3D sequential process schemes and their main characteristics. Moreover, a detailed overview of the structures utilized in our experiments is presented. Electrical measurements on the structures under test reveal the susceptibility of each active tier to electromagnetic coupling. Regarding the inter-tier electrostatic coupling effects in 3DSI, although prior works have already presented them in principle [51], [START_REF] Koneru | Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing[END_REF], [START_REF] Yu | Electrical Coupling of Monolithic 3-D Inverters[END_REF], [START_REF] Hattori | Interlayer coupling effect on the performance of monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness[END_REF] and experimentally verified [START_REF] Andrieu | Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation[END_REF], this chapter presents the first analytical study examining the coupling between the top and bottom tiers of 3D sequential technology stacking 28 nm FDSOI MOSFETs, under normal circuit operation (V DD = 0.9 V) and its impact on LFN behavior of the stacked devices.

Additionally, concerning the inter-tier dynamic coupling and RF crosstalk of digital circuits in 3DSI, experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for dynamic coupling effects and its impact at device level is investigated. Lastly, the results of this analysis are utilized to conclude on the critical dimensioning of the structures in order to tolerate the inter-tier electromagnetic interference.

3D sequential structure description

3DSI can feature different technologies at each tier in order to take full advantage of a given technology's potential for a specific application (digital, analog, mixed-signal/RF), as illustrated in Fig.

3.1.

A good candidate for 3DSI is any stackable device that follows the SOI device architecture and especially thin-film devices. The last suggests that the devices can be implemented for example using the FD-SOI structure, described in chapter 2.

Fig. 3.1 Device architectures for top and bottom tiers in a 3DSI scheme [START_REF] Michallet | CoolCube TM : A True 3DVLSI Alternative to Scaling | 3D InCites[END_REF].

In summary the FD-SOI structure presents the following differences compared to the conventional BULK MOSFET:

• The channel is un-doped (or very lightly doped). As a result, the short channel effects, as well as the variability of electrical parameters among devices with major source the random dopant fluctuations, are greatly reduced.

• The Body of the transistor is made ultra-thin for better electrostatic control.

• The Source/Drain diffusion areas are elevated to reduce series resistance.

• In order to reduce the capacitive coupling of the Source/Drain diffusion areas, the BOX thickness is reduced and a highly doped silicon layer is placed beneath, commonly called the GP. This more advanced architecture is used widely nowadays and is named Ultra-Thin Body and BOX (UTBB) FD-SOI.

• The GP doping can also help tune the threshold voltage value.

As in a conventional planar process, in 3DSI there are two major sections, the Front-End-Of-Line (FEOL) and the Back End Of line (BEOL). In the former active devices (transistors) and passive elements (capacitors, resistors, etc.) are patterned in a semiconductor layer whereas the latter contains all the metal layers used to interconnect the FEOL devices.

A schematic cross-section view of a 3D sequentially integrated structure is presented in Fig. of 3D integration, enabling the highest density of 3D contacts. In this scheme the Contacted Poly Pitch (CPP) can reach the value of the one in planar integration.

Mixed-signal opportunities by the use of 3DSI

In 3DSI each tier can host either digital, analog or mixed-signal/RF applications separated by an ILD with thickness in the range of 100nm to 1μm, as shown in Fig. 3.3. In particular, the digital tier can consist of logic gates, memory circuits, processors while an analog tier can have op-amps, filters, ADCs/DACs. Mixed-Signal tiers can have all the previous with additional RF blocks such as mixers, PLLs, LNAs. The key parameters that differentiate each tier in terms of electromagnetic interference with its adjacent ones are the maximum voltage swing and the frequency band that they utilize, with typical 28nm node values presented in Table 3.1. The objective of this chapter is to examine the immunity of each tier to the electromagnetic interference by the adjacent one at a device level. However, this does not ensure that a hard conclusion can be drawn for all cases of applications unless the electromagnetic coupling at a circuit level is examined. For instance, digital circuits like logic gates have an inherent immunity to noise in principle, yet there are sensitive digital circuits like memories that noise can be harmful for their stability [START_REF] Takeuchi | Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment[END_REF].

3DSI process flow for digital devices

The 3DSI process flow scheme [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF] for digital devices (EOT≈1nm, V DD =1V) is depicted in Fig. Chapter 3 -Investigation of 3DSI electromagnetic coupling effects at a device level 60

In order to process the upper tier, conventional high temperature methods can degrade the bottom tier device performance. It has been reported in [START_REF] Fenouillet-Beranger | FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration[END_REF], [START_REF] Deprat | First integration of Ni0.9Co0.1 on pMOS transistors[END_REF] that a 950°C annealing results in such degradation. This restricts the TB for the top tier to a time-temperature window (Fig. 3.5) which prevents the bottom tier from any degradation [START_REF] Batude | 3DVLSI with CoolCube process: An alternative path to scaling[END_REF]. Taking this into account, a 10nm thin silicon layer of an oxidized SOI wafer is then transferred by direct bonding, through a low temperature 300°C bonding annealing. Grinding combined with sequential wet and dry etching is utilized to thin down the entire structure. Next, the HfO2/TiN/Poly-Si gate stack is formed followed by a spacer zero deposition at 630°C and a selective SiGe 27% raised source drain epitaxy at 650°C for both NMOS and PMOS transistors. Lastly, Solid Phase Epitaxy Regrowth (SPER) [START_REF] Batude | 3DVLSI with CoolCube process: An alternative path to scaling[END_REF] is used to activate the junctions at a relatively low temperature (600°C for 1 minute) while keeping low variability [START_REF] Pasini | High performance CMOS FDSOI devices activated at low temperature[END_REF].

As observed from Fig. 3.5, the maximum TB for the top tier process, not resulting in a bottom tier device degradation, is 650°C for 20min, due to the raised source/drain processing. As a consequence, compared to the bottom TB, the top tier devices can be referred to as "Low

Temperature" (LT) devices.

In case there is an iBEOL between the tiers, refractory metals are preferred, such as tungsten.

The 3D contacts that are used to link the two tiers, called also Monolithic inter-Vias (MIVs), are done sequentially after the top LT process using standard tungsten plug in oxide connecting iBEOL to the final BEOL, which is a standard Cu/Low-k back-end. It is worth mentioning that the 3D contact scales with the device technology (e.g for a 28nm node it has 40nm width) while it has a higher AR than normal contacts, determined by the ILD thickness. As a result, it is preferred to keep a small 3D contact AR by limiting the ILD thickness to several hundreds of nanometers.

Characteristic dimensions and performance of 3DSI devices under test

The characteristic dimensions of the devices are shown in Fig. 3 The static performance and reliability of top/bottom devices in the 3DSI scheme under study have been analyzed in depth in [START_REF] Tsiara | Performance and reliability of a fully integrated 3D sequential technology[END_REF], highlighting a minor impact of the top-tier processing on the performance and reliability of the bottom-tier devices. Regarding the top-tier devices, their performance has been shown to be comparable to the bottom ones while they satisfy the BTI reliability requirements. In addition, the RF performance of the top/bottom-tier devices has been investigated in [START_REF] Garros | RF Performance of a Fully Integrated 3D Sequential Technology[END_REF]. The authors highlight state-of-the-art RF Figures Of Merit for the present 3DSI scheme, with the top tier PMOS devices featuring f t =55GHz and f max =80GHz at V DD =-1V, without altering those of bottom tier devices.

Structure layout of 3DSI devices under test

The structure of Fig. 3.2 (a) can be characterized as the most critical in terms of electromagnetic coupling due to the direct stacking of active device layers, i.e., each one can be an aggressor to the other. Thus, for the purpose of this study, top-bottom devices were selected in the layout configuration of Fig. 3.7. The minimum gate length of the masks is 30nm as in 28nm FDSOI process, however the density of both the top tier and 3D contacts, is similar to that of a 65nm node. To maximize coupling effects, the gates of top/bottom devices were designed to be equal in dimensions while maintaining the same footprint for the two devices. Indeed, devices placed on the top tier in a 3DSI technology must respect the positioning of bottom tier devices. To accomplish that, the active area is patterned in such a manner that the 3D contacts have been placed between the contacts of the top tier devices (Fig. 3.8). To assess the susceptibility to electromagnetic coupling, it is adequate to begin by selecting the same device type (NMOS or PMOS) for the two tiers in order to observe if there is any coupling impact. Thus for this study, NMOS devices were selected for both top and bottom tiers. Nonetheless,

L G 3D contacts G top G bot W G
the impact of the device type on the coupling induced effects will be investigated in section 3.2.2.a.

The static measurements were performed with the Agilent B1500A device parameter analyzer and the low-frequency noise measurements with the NOISYS7 equipment by Synergie Concept [START_REF] Synergie Concept | NOISYS.7, Low-Frequency Noise Measuring System[END_REF].

Impact of DC coupling on top/bottom device performance

In this section, the impact of static (DC) coupling among top and bottom tier devices is investigated experimentally. Two cases are examined, one where the top device is the aggressor and the bottom one is the victim (Fig. 3.9 (a)) and vice versa (Fig. 3.9 (b)).

Experimental results

3.2.1.a Bottom-tier device electrostatic results

The impact of the static polarization applied to the top tier NMOS device on the performance of the bottom tier NMOS device was studied extracting the input characteristics of the latter while varying the top device gate bias (V Gtop ) from 0 to V DD (0.9V). The results are shown in Fig. 3.10 (a) for

G top D top S top Victim Aggressor G bot D bot S bot G top D top S top Aggressor Victim G bot D bot S bot a. b. 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 -0.2 0 0.2 0.4 0.6 0.8 Bottom SOI Drain Current I Dbot Bottom SOI Gate Voltage V Gbot (V) 0 0.9 V Gtop V Gtop (V) V Dbot = 30mV a. 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 -0.2 0 0.2 0.4 0.6 0.8 Bottom SOI Gate Voltage V Gbot (V) 0 0.9 V Gtop (V) V Dbot = 0.9V b. V Gtop (μΑ/μm)
a V Dbot =30mV and for V Dbot =0.9V in Fig. 3.10 (b).

As observed, there is no impact of V Gtop on the bottom device input characteristics. This result is quite reasonable considering that the bottom device electrodes being polarized, shield the bottom device channel from the top-tier device electrodes electric field (Fig. 3.11).

Fig. 3.11

The bottom-tier device channel is shielded effectively against static coupling from the top-tier device.

3.2.1.b Top-tier device electrostatic results

Applying the same concept but this time inverting the victim-aggressor role for the two devices as shown in Fig. 3.9 (b), the input characteristics of the top device are obtained now varying the bottom device gate bias from 0 to V DD (0.9V). Fig. 3.12 (a) demonstrates the experimental results for a V Dbot =30mV and Fig. 3.12 (b) for V Dbot =0.9V.

Top SOI Gate Voltage V Gtop (V) a. ΔV TH ΔSW V Gbot 1E-6 1E-5 1E-4 0.08 0.18 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 -0.2 0 0.2 0.4 0.6 0.8 Top SOI Gate Voltage V Gtop (V) 0 0.9 V Gbot (V) V Dtop = 0.9V b. V Gbot ΔSW V Dtop = 30mV 5E-3 5E-2 0.3 0.4 19mV 18mV
ΔV TH

MOSFET structure of the top devices, having an equivalent BOX thickness equal to the one of the ILD separating the two tiers. Thus, each one of the bottom device electrodes (G bot , D bot , S bot ) may act like a Back-Gate for the top device modifying its performance. However, the bottom device gate electrode dominates over the other two electrodes due to its proximity to the top device channel.

Hence, the maximum impact on the top device performance occurs when the bottom gate bias equals the power supply voltage (V DD ).

In order to extract the values for the coupling-induced ΔV TH and ΔSW for the given process, statistical measurements were performed with a large set of experimental data at different gate bias of the bottom transistor, i.e., V Gbot = 0 V (bottom device OFF), 0.9 V (bottom device ON) and -0.9 V (lower voltage limit for further verification of V Gbot = 0.9 V), as shown in Table 3.2. The gate voltage of the top tier devices was varied from V Gtop = 0 V to 0.9 V in linear region of operation with the application of a 30 mV to the drain voltage V Dtop in order to avoid saturation effects that might mislead our conclusions.

Bottom OFF Bottom ON

V Gbot -0.9 V 0 0.9 V

For the purpose of this study, we selected a set of 126 dies for the top tier device displaying good characteristics. Fig. 3.13 shows the I Dtop -V Gtop characteristics of NMOS devices with L G = 1 μm with the black trace being the best die characteristic (in terms of I on /I off ).

Fig. 3.13 Drain current versus gate voltage for top-tier NMOS devices stacked on bottom-tier NMOS devices, both with 2 μm 2 area (total of 126 dies) where the black trace refers to the best die characteristic (in terms of I on /I off ).

126 Dies

Best die

Chapter 3 -Investigation of 3DSI electromagnetic coupling effects at a device level 66 A modified Y-function method [START_REF] Subramanian | Parameter extraction of nano-scale MOSFETs using modified Y function method[END_REF] was applied to extract the threshold voltage, V TH , values for all 126 dies. As shown in Fig. 3.14, the coupling-induced V ΤΗ shift, ΔV TH , was found to be equal to -15.6mV ± 3 mV and 14.7mV ± 2.4 mV for positive and negative V Gbot bias, respectively.

3.2.1.c Top-tier device LFN results

The drain current noise spectral density was measured from weak to strong inversion for all bottom gate bias cases shown in Table 3.2. In order to neglect the shift in the DC value of I Dtop , the measured noise was normalized by I Dtop 2 . Fig. 3.15 illustrates the corresponding spectra for three V Gtop values. Fig. 3.16 shows the normalized PSD value as extracted at f = 10 Hz versus drain current for all the bottom gate bias cases shown in Table 3.2 for two different device gate lengths L=1μm and L=0.1μm. The latter is a typical behavior for sub-μm MOSFETs, where the noise spectra are not 1/f-like in most cases, but dominated by Lorentzian noise, responsible for the observed humps [START_REF] Theodorou | Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs[END_REF].

V Gbot =0V V Gbot =0.9V V Gbot =-0.9V V Gtop =0.9V V Gtop =0.2V V Gtop =0.4V
In previous studies, it has been shown that the bottom gate bias of a FDSOI MOSFET can strongly affect the remote Coulomb scattering between carriers and trapped charge [START_REF] Theodorou | Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs[END_REF], [START_REF] Ioannidis | Drain-current flicker noise modeling in nMOSFETs from a 14-nm FDSOI technology[END_REF], leading to a change in the Correlated Mobility Fluctuations (CMF) factor Ω in the 1/f noise model given by [START_REF] Ioannidis | Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors[END_REF]:

√ 𝑆 𝑉𝑔 = √ 𝑆 𝑉𝑓𝑏 (1 + 𝛺 𝐼 𝑑 𝑔 𝑚 ) (3-1)
where S Vg =S Id /g m 2 is the input-referred gate voltage noise PSD, S Vfb the flat-band voltage noise PSD and g m the transconductance.

Therefore, in order to verify if the bottom transistor gate bias under normal operation can affect the CMF factor Ω, we plotted the square root of the input-referred gate voltage noise, S Vg , versus I d /g m for the top-tier device. As one can observe in Fig. 3.17, in all three cases ( )

V Gbot =0.9V
a.

V Gbot =-0.9V

Top SOI Drain Current I Dtop (μΑ)

Table 3.2), there is the same linear dependence, so that the extracted Ω factor (inset) can be considered constant with V Gbot .

Fig. 3.17 Square root of input-referred gate voltage PSD SVg versus Id/gm for a top NMOS with W=2μm, L=1μm, for all the bottomtier NMOS biases shown in Table 3.2.

3.2.1.d Charge-coupling factor extraction and influence of SCE

As analyzed in chapter 2, the back to front interface charge coupling of the depleted silicon film is attributed on the capacitive network formed between the front and back gate electrode of the FD-SOI device. The charge-coupling factor r (mV/V) describes the sensitivity of V TH to changes in the back-gate voltage (in our structure the bottom device gate voltage) and flat-band voltage [START_REF] Fossum | Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs[END_REF]. It is an inherent property of the device structure and is defined by

𝑟 = 𝐶 𝑏(𝑒𝑓𝑓) 𝐶 𝑜𝑥 (3-2)
where C b(eff) is the effective body capacitance and C ox is the gate oxide capacitance, both per unit area.

To experimentally extract the charge-coupling factor for the top devices, the bottom SOI gate 1.0x10

-5 1.5x10 -5 2.0x10 -5 2.5x10 -5 V Gbot =0V S 1/2 (V/Hz 1/2 ) I Dtop /g mtop (V) V Gbot =0.9V V Gbot =-0.9V V Gtop Omega (V -1 ) Bottom SOI Gate Voltage V Gbot (V) a. b.
back interface. On the contrary, for a negative bottom gate bias the back interface is gradually going from depletion to accumulation. The ΔV TH,top /ΔV Gbot slope for the negative and positive gate bias describes the rate of change of the top device threshold voltage with the bottom gate bias. The median of the slopes in the two different modes of back-gate operation yields a value of the charge-coupling factor |r|=16.8mV/V. This value is in line with the extracted threshold voltage shift median value from the statistical measurements, presented in the previous section.

Additionally, Fig. 3.18 reveals the coupling-induced threshold voltage shift by an analog device placed at the bottom tier with V DD =2.5V. Therefore, a ΔV Gbot =2.5V corresponds to a ΔV TH,top =44mV.

Since the charge-coupling factor relies on the device and generally the structure geometry, parameters such as the electron/hole mobility, series resistance and temperature have no influence on the coupling-induced Threshold Voltage shift ΔV TH of the device. In contrast, it has been demonstrated that there is a dependence of the charge-coupling factor on Short Channel Effects (SCEs) and Quantum Mechanical (QM) effects [START_REF] Fossum | Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs[END_REF], [START_REF] Rudenko | Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs[END_REF]. These two effects result in a widening of the back (bottom in our structure) gate-bias range for charge coupling, as they tend to move the inversion-charge centroid away from the two interfaces [START_REF] Fossum | Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs[END_REF].

To assess the impact of SCE, the charge-coupling factor was extracted for devices with 1μm

Top SOI Gate Voltage V Gtop (V) Bottom SOI Gate Voltage V Gbot (V) |r|=16.8mV/V +15.1mV/V -18.4mV/V V THf,top (V Gbot ) V THb,top (V Gbot )

Fig. 3.19 Extracted charge-coupling factor for top devices with L G =1μm and L G =100nm (Total of 5 dies).

Moreover, Fig. 3.20 shows the influence of a top device high drain bias on the charge-coupling factor under the scaling effect. It is worth mentioning that the coupling induced ΔV TH values for the top-tier device were extracted here with the constant current method [START_REF] Tsuno | Physically-based threshold voltage determination for MOSFET's of all gate lengths[END_REF] at

𝐼 𝐷 = 100 • 𝑊 𝐿 𝑛𝐴 since
the Y-function method is not valid in the saturation region. As seen in Fig. 3.20, while there is no change in the charge-coupling factor with the drain bias regarding the 1μm device, a slight increase is observed for the devices with 100nm gate length. An intuitive explanation of this effect may be the worsening of the top device gate electrostatic control of the channel as the drain voltage increases, while the bottom device gate control strength remains the same.

Simulation results

To further extend the analysis at device level, numerical simulations were performed using Coupling Factor (mV/V)

Gate Length L G (μm)

0.03 0.9

V Dtop (V)
Silvaco TCAD device simulation tool ATLAS. The experimental structure was simulated (Fig. 3.21)

setting the geometry and the materials used in the process while the parameters extracted from the experimental characterization were utilized to calibrate the simulation results. In addition, the necessary physics models (carrier continuity, drift, diffusion, generation-recombination, QM effects)

were included in the device electrical simulation, to reproduce the observed experimental behavior.

G top D top S top L G t ILD t si t ox spacer spacer G bot D bot S bot L G t si t ox spacer spacer 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 0 0.2 0.4 0.6 0.8 Top SOI Drain Current I Dtop (μΑ/μm) Top SOI Gate Voltage V Gtop (V) 30 900 V Dtop V Dtop (mV) symbols:exp. lines:TCAD b. V Gbot =0V 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 0 0.2 0.4 0.6 0.8 Bottom SOI Drain Current I Dbot (μΑ/μm) Bottom SOI Gate Voltage V Gbot (V) 30 900 V Dbot V Dbot (mV) symbols:exp. lines:TCAD a. 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 0 0.2 0.4 0.6 0.8 Top SOI Gate Voltage V Gtop (V) 30 900 V Dtop V Dtop (mV) symbols:exp. lines:TCAD c. V Gbot =0.9V

3.2.2.a Impact of device type

The coupling induced threshold voltage shift (ΔV TH (V Gbot )=V TH (V Gbot )-V TH (V Gbot=0V )) was extracted with the aid of TCAD simulations for NMOS and PMOS device type, while the bottom SOI gate voltage was swept from -20V to +20V with a step of 2V and the results are shown in Fig. 3.23.

Fig. 3.23 Coupling induced ΔV TH for top tier devices (blue and red lines for NMOS and PMOS device type respectively).

As observed while the two curves yield nearly the same charge-coupling factor, the rate of change ΔV TH /ΔV Gbot alters between each device type under positive and negative V Gbot . For instance, considering a positive V Gbot , which is the actual scenario under circuit operation, PMOS devices yield a lower sensitivity to coupling effects. Consequently, assuming that the maximum power supply of the bottom devices is 2.5V for analog applications, PMOS experience a ΔV TH slightly reduced by 1.25mV. An intuitive understanding of that effect can be obtained by extracting the carrier concentration versus the silicon film depth for the top-tier device in the threshold voltage condition (V Gtop =V TH (V Gbot )), as shown in Fig. 3.24 (a) for NMOS and in Fig. 3.24 (b) for PMOS. Carrier concentration (cm -3

)

Silicon film depth (nm) 0V -20V +20V V Gbot NMOS (electrons) V Gtop =V TH (V Gbot ) 1E+15 1E+16 1E+17 1E+18 0 1 2 3 4 5 6 7
Silicon film depth (nm

) 0V +20V -20V V Gbot PMOS (holes) V Gtop =V TH (V Gbot ) a. b.
As observed, for PMOS the conduction path (charge centroid) moves from the center of the channel to the front/back interface in the reverse direction than in NMOS devices. Due to majority carriers being holes in a PMOS device channel, a negative bottom gate bias attracts the holes at the back channel while the front interface is depleted, enhancing the modulation by the bottom gate.

On the other hand, a positive bottom gate bias depletes further the back interface setting the conduction path to the front interface, thus the front gate gains a better control of the carriers.

3.2.2.b Influence of SCE on the coupling induced ΔV TH

As remarked in the experimental part, there is a reduction in the coupling induced threshold voltage shift by 1.2mV as the gate length of both top and bottom devices decreases from 1μm to 100nm. Extending the analysis by TCAD simulations, the threshold voltage shift (ΔV TH ) due to electrostatic coupling was extracted as a function of gate length (Fig. In order to assess how the top device threshold voltage reacts to higher bottom device gate bias in case of a 28nm nominal gate length device, the bottom SOI gate voltage was swept from -20V

to +20V with a step of 2V while extracting the input characteristics for both NMOS and PMOS type of device (Fig. 3.26). Comparing in the same diagram the results for a 1μm gate length device, the decrease of the charge-coupling factor with the gate length is apparent for both devices. It is evident from Fig. 3.26 that in the case of higher power supplied devices being at the bottom tier, the couplinginduced threshold voltage shift can have a significantly reduced value. For instance, in the case of a

Gate length (μm)

TCAD Experimental bottom analog device with ΔV Gbot =2.5V the reduction of the coupling-induced ΔV TH can be as high as 21mV for NMOS devices and 16.7mV for PMOS devices, when going from μm-to nm-range lengths. However, it must be noted that for operation in the saturation region, the coupling induced ΔV TH is elevated for short channel devices (L G <1μm), as obtained from the TCAD simulations (Fig.

3.27)

, confirmed also by the experimental results in the previous section. This implies that in the saturation region there is a minimal increase of the coupling induced threshold voltage shift compared to the linear region. Again, the overall ΔV TH decrease, from linear to saturation, obtained by using nominal gate length devices is valuable: 18.35mV for NMOS and 13.8mV for PMOS under a ΔV Gbot =2.5V.

3.2.2.c Impact of bottom/top length ratio on CF with regard to scaling

The impact of bottom/top length ratio (i.e., cases where the gate length of the stacked devices are not equal) on the charge-coupling factor will be investigated in this section. For the purpose of this analysis, an accurate extraction of the front-and back-channel threshold voltage in required, which can be performed by many methods (Constant Current (CC), transconductance, etc). Although the CC method has been utilized so far in order to compare experiments to simulations (unavailability of experimental structures for capacitance measurements), in this section the max(dC gc /d Vg ) method will be used from split C-V simulations.

With the aid of the max(dC gc /d Vg ) method, the threshold voltage has been determined from the position of the derivative peak of the top-tier device gate-to-channel capacitance (C gt-cht ) with respect to the gate voltage V Gtop while varying the bottom-tier device gate voltage V Gbot [START_REF] Rudenko | Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs[END_REF], under V Dtop =30mV. This way the V TH value is only influenced by the electrostatic (charge-related) behavior

and not any transport-related effects (gate-voltage dependent mobility etc.). The procedure used to extract the coupling characteristics is illustrated in Fig. 3.28 for devices with L G =1μm.

Fig. 3.28 TCAD results of the gate-to-channel capacitance C gt-cht of the top-tier device versus its gate voltage (a) and their derivatives (b) for various bottom-tier gate voltages V gbot , illustrating the procedure for extracting coupling characteristics (L G =1μm).

Analyzing the results, for high positive values of V Gbot , the C-V curves exhibit an additional curvature at low V Gtop related to the inversion channel at the back interface; therewith, the corresponding dC gt-cht /dV Gtop curves reveal two clearly pronounced peaks:

• The first, is due to the activation of the back-channel, with its position at various V Gbot yielding a relationship between V Gtop and the back-channel threshold voltage V TH,b .

dC gt,cht /dV gt (fF/V) V Gtop (V) V TH,back_inv V gt (V THb ) V THf (V gb ) L G =1μm a.
b.

• The second, whose position is invariable with V Gbot , corresponds to the activation of the front channel, yielding the front-gate threshold voltage for the inverted back interface V TH,back_inv .

For V Gbot ≤0, only a single peak in dC gt-cht /dV Gtop curves appears, corresponding to the activation of the front channel, and its shift with V Gbot gives the V THf (V Gbot ) dependence (i.e., the frontgate coupling characteristic). The extracted results concerning the coupling-induced ΔV TH for NMOS devices can be seen in Fig. 3.29 along with the constant current method results. A difference among the two can be observed for strong negative and positive device gate bias, becoming more pronounced in the second case. Carrying out the same procedure for a wide range of the top/bottom-tier device gate length combinations, the obtained charge-coupling factor values are plotted versus the ratio L Gbot /L Gtop in Fig. 3.31. Interpreting the results, one can observe that the top-tier devices with L Gtop =1μm approach the long-channel behavior, i.e., when L Gbot ≥L Gtop the charge-coupling factor remains at a constant value, whereas for L Gbot <L Gtop there is a reduction related to the top-tier channel/bottom-tier gate overlapping area. However, for sub-micrometer devices, the charge-coupling factor behavior deviates from the long channel one. As the top-tier device gate length approaches 30nm, the curve shifts towards the right of the diagram while the charge-coupling factor reaches higher values for both extreme cases of L Gbot >>L Gtop and L Gbot <<L Gtop . As a result, when L Gbot =L Gtop the charge-coupling factor and hence the coupling-induced V TH shift of the short-channel top-tier device appears to be reduced compared to a long-channel one (results of Fig. 3.25).

The above behavior is attributed to the SCE which decrease both the effective oxide capacitance (C ox,eff ) and ILD capacitance (C ILD,eff ) of top-tier devices. Indeed, electric field vector plots obtained from TCAD simulations (Fig. Coupling Factor (mV/V)

V Gtop (V) V gt (V THb ) V THf (V gb ) L G =30nm V TH,
L Gbot /L Gtop ratio 0.03 0.1 0.3 1 L Gtop L Gtop L Gtop < L Gbottom L Gtop > L Gbottom Top SOI Gate Length L Gtop (μm) V Dtop =30mV
source and drain diffusion areas on the bottom-tier gate electrode electric flux. These fringing fields cause ultimately a reduction of the top device effective back-gate length L Gbot,eff .

3.2.2.d Impact of top/bottom device misalignment on CF

The relative misalignment of devices is an effect that can also impact the charge-coupling factor of the top-tier device. Misplacing by Δx the gates of two stacked devices, the charge-coupling factor is reduced since it depends on the overlapping area between the top-tier device channel and the bottom-tier device gate electrode (Fig. 3.33 (a)).

For stacked devices having equal gate length (L Gtop =L Gbot ), the impact of their misalignment on the charge-coupling factor is shown in Fig. 3.33 (b) as extracted from TCAD simulations, varying the gate length in the sub-micrometer range.

The concept of the effective front/back gate length for the top-tier device can be also applied here, as described in the previous section. Fig. 3.34 shows the electric field vector plot of two stacked devices with L G =100nm and 50% relative misalignment towards the drain direction. Because of the offset, the effective BG length for the top-tier device should be proportional to the overlapping area between the top-tier device channel and the bottom-tier device gate, and thus L Gbot,eff =L Gbot /2.

However as observed, L Gbot,eff is degraded due to the electric field deformation from top-tier drain diffusion area as shown in Fig. 3.34.

Impact of static coupling on the performance of top-tier digital devices (V DD =1V)

3.2.3.a Digital devices at the bottom tier (V DD =1V)

The small difference between the measured absolute values of the coupling-induced V t shift at positive and negative bottom-tier biases (Fig. accumulation for negative V Gbot , while the ≈15% ΔV TH variability is attributed to the variability in t ILD (estimated to be ±20nm for the wafer under study), due to the SOI coupling relation [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF]:

𝛥𝑉 𝑡 𝛥𝑉 𝐺𝑏𝑜𝑡 = - 𝐶 𝑠𝑖(𝑡𝑜𝑝) 𝐶 𝐼𝐿𝐷 𝐶 𝑜𝑥(𝑡𝑜𝑝) (𝐶 𝐼𝐿𝐷 + 𝐶 𝑠𝑖(𝑡𝑜𝑝) ) (3-3)
where C si(top) , C ox(top) , C ILD are the top-tier channel, the top-tier oxide, and the ILD capacitances per unit area, respectively. Although there is a dependence of the coupling-induced ΔV TH on the device gate length, here it will be considered constant and equal to the maximum value for the simplicity of the analysis. At an ILD thickness of 130nm, the maximum gate area for which the coupling-induced ΔV TH does not exceed the mismatch variations is much higher than the typical gate areas used in digital circuits. This is due to the power supply rails (V DD and GND) distance limitations the device gate is restricted to an area below 0.01 μm 2 . Indeed, digital designs utilize the minimum gate length of each technology node, while the gate width varies from the minimum allowed value of the design rules up to a typical value limited by the power supply rails distance. The latter is demonstrated schematically in Fig. 3.36, considering that in digital design the design follows a common pattern -the power supply rails, GND and V DD , extend throughout the whole design and between them the devices are placed, with NMOS devices always at the upper region of the design next to the GND rail, as opposed to PMOS devices next to V DD rail.

Therefore, for 28nm FDSOI technology, the gate width has a typical maximum of 320nm, while the minimum allowed gate length and width are 30nm and 80nm respectively. The relative weight of variability on the normalized off-currents (green curve) and on-currents (black curve) is demonstrated in Fig. 3.35 (b). Due to the exponential behavior of current in the subthreshold region, the weight is much larger for off-currents than for on-currents. Despite the fact that both on-and off-current seem to be more sensitive to electrostatic coupling the shifts ΔI off and ΔI on , are within the calculated normalized mismatch variations of I off and Ion in 28 nm FDSOI technology, for a typical range of gate areas in digital design, even for the 1-σ consideration.

3.2.3.b Analog devices at the bottom tier (V DD =2.5V)

Devices used in analog design typically possess a thick EOT and thus have a higher power supply.

For 28nm node devices with EOT in 5nm range, their power supply is V DD =2.5V. Therefore, if they are placed at the bottom tier underneath top digital devices, the maximum level of bias at the bottom device gate electrode can be 2.5V. Furthermore, the dashed blue line shows the most critical case of the threshold voltage local variability in the 28 nm FDSOI process, which is the 1-sigma limit for the minimum gate area. From the study presented in the previous section, the threshold voltage shift for 130nm thick ILD is well within

N P GND VDD 1μm W max ≈350nm
Poly Active Metal the local variability limit and can defines a safe coupling-to-mismatch margin for the 3DSI of other applications. Hence, as observed, the values of the Digital1V on Analog2.5V case are higher than the Digital1V on Digital1V case, so in order to maintain the same coupling-to-mismatch margin, the ILD thickness must be greater than 350nm.

Impact of static coupling on the performance of top-tier analog devices (V DD =2.5V)

Devices with power supply of 1V are intended for low power/low voltage digital applications, however they are not preferred for analog design because of their limited voltage swing. Furthermore, the use of a thicker silicon body enables a higher gm/Id ratio, enhancing the performance of analog circuits. To date, LT devices have been successfully processed for Low-Voltage (LV) [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF] as well as High-Voltage (HV) [START_REF] Cavalcante | Low temperature high voltage analog devices in a 3D sequential integration[END_REF] applications. The latter suggests a process scheme for FDSOI devices with 30nm thick undoped channel, 25nm BOX, and SiO2 = 6nm/TiN/Poly-Si gate stack (Fig. 3.38).

Moreover, the in-depth characterization of analog HV devices with thick EOT has been investigated in the same work revealing a performance comparable to high temperature reference s and passing the PBTI reliability criteria. The coupling induced threshold voltage shift when top device is an analog one for the two cases where the bottom device is either digital or analog, was examined with the aid of TCAD simulations. For analog devices being at the top tier, their coupling behavior to the bottom devices deviates from the one studied for digital devices so far, due to their thicker EOT as well as silicon body. Indeed as Fig. 3.39 shows, the coupling induced ΔV TH is shifted to significantly higher values. Taking into account that analog circuits are extremely sensitive to threshold voltage variations, solutions to mitigate the coupling effects must be incorporated (the reader is encouraged to refer to § 4.2). Indeed, analog circuits such as current mirrors and differential amplifiers, require pairs of transistors, which are identically designed and laid out in an identical environment, in order to ensure the same electrical performances. As explained in the previous section, real devices suffer from random local variations in the electrical parameters (mismatch), and from Fig. 3.35 (a) it can be observed that these variations decrease as the gate area of the device increases. Adding to that also the fact that analog designs often tend to utilize transistors of a large gate area, it is apparent that the coupling-induced threshold voltage shift has a stronger impact compared to mismatch, that cannot be tolerable.

Although the obvious solution is the thickening of ILD, this is actually not practical as it will worsen the 3D contact AR dramatically. From a circuit design perspective, the coupling-induced threshold voltage shift can be alternatively viewed as a DC offset for the victim top-tier device, which can be corrected with offset cancellation techniques [START_REF] Razavi | Design of Analog CMOS Integrated Circuits[END_REF]. Yet, this is not valid in the cases that the offset is random and cannot be predicted, e.g., the bit storage value of a SRAM cell.

Impact of AC coupling on top/bottom device performance

The electromagnetic interference between active devices in different tiers is a serious concern in mixed-signal circuits and especially in 3DSI that offers a platform for the heterogeneous integration of applications. Nowadays, digital applications that have been the primary driving force of 3DSI, feature high speed switching signals with a rising/falling edge of several picoseconds. The rise/fall time of a switching clock signal is defined as the time required for the signal to go commonly from 10% to 90% of the LOW to HIGH level difference. This transition time is limited by the gate delay of transistors and the propagation delay of the interconnections. The gate delay expresses the time delay in the path of a signal, from the digital gate's input to the output, and is depended on the ONstate resistance of the transistors and their capacitive loads. It can be divided in a low-to-high (t P,LH )

and high-to-low (t P,HL ) propagation delay as shown in Fig. 3.40. On the other hand the propagation delay of interconnects depends on their resistivity and length. Hence, global interconnects that are used to connect systems within a chip, have a length in

V i V o V i V o
Inverter (NOT gate)

t P,HL t P,LH t R t F
the millimeter range, introducing a high propagation delay in the transmitted signals, contrary to local interconnects that are used to connect adjacent devices and their delay is even lower than the gate delay [START_REF] Banerjee | Interconnect modeling and analysis in the nanometer era: Cu and beyond[END_REF]. This implies that the limitation for the rise time of the switching clock signals emanates from the gate delay. Fig. 3.41 shows the typical delay for global and local Cu interconnects compared to the nominal gate delay in each technology node [START_REF] Banerjee | Interconnect modeling and analysis in the nanometer era: Cu and beyond[END_REF]. As observed from Fig. 3.41, for a 28nm node the rise/fall time of clock signals can be as low as 8ps. The significant frequency of a digital signal, i.e., the highest frequency up to which the amplitude of the corresponding frequency components is significant, is much higher than the frequency of the clock in a digital system. Consequently, the significant frequency for 28nm node clock signals can be as high as 32GHz, as estimated by .

Furthermore, the concept of a hybrid integration of RF and logic functions on adjacent tiers, presents an emerging interest to the electronics community nowadays [START_REF] Choudhury | 3D integration technologies for emerging microsystems[END_REF], [START_REF] Deshpande | DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration[END_REF]. Nevertheless, these applications can be an intense source of RF crosstalk for noise-sensitive analog applications placed among the adjacent tiers.

Small-signal analysis

Before proceeding to the analysis, it is crucial to choose the simulation tool in order to carry out the dynamic coupling analysis. It is true that in order to have an accurate calculation of the electromagnetic coupling between different components, a full-wave approach, i.e. solving the complete set of Maxwell equations without any simplifying assumptions, is necessary. However, since the electrical size of the coupled structures in 3DSI is much smaller than the wavelength in the frequency range under study (<300GHz the upper limit of the mmW band), the analysis can be carried out using quasi-static approximation of Maxwell equations. Under this assumption, the electric and magnetic fields produced by an aggressor signal are not interacting with each other, hence capacitive and inductive coupling can be analyzed separately.

Over and above that, semiconductor-based problems require incorporating the associated physics such as drift, diffusion and generation-recombination, within the solving procedure. TCAD semiconductor device software such as Silvaco ATLAS appears to be the appropriate tool for this type of problem under the previous assumptions. However, TCAD AC simulations calculate the conductance and capacitance between each pair of electrodes, thus focusing on the electric field (capacitive) coupling and neglecting the one occurring from the magnetic field (inductive).

It has been stated in [START_REF] Jiang | Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges[END_REF] that in monolithic 3D-ICs, capacitive coupling dominates the intertier coupling, as opposed to the inductive coupling being negligible due to the small geometries of the interference source. However, in the particular layout configuration studied in this chapter (Fig.

3.7)

, the inductive coupling between the drain terminals of each top/bottom device may be significant.

3.3.1.a Impact of inductive coupling

To assess the strength of the inductive coupling in the structures under study, the methodology used in [START_REF] Xu | Compact capacitance and capacitive coupling-noise modeling of through-oxide vias in FDSOI based ultra-high density 3-D ICs[END_REF] has been followed. In this work, by artificially modifying the permeability of all materials to be 0.01 times the vacuum permeability, the authors estimated the strength of the inductive coupling by extracting the relative error of the g 21 parameter by considering a two-port network configuration. While the S 21 scattering parameter (Fig. 3.42) which describes the power transferred from one tier to the other, has been widely used for electromagnetic coupling studies in ) can be used for this study interchangeably.

V in Two-Port Network R S R L
ANSYS High Frequency Structure Simulator is a pure electromagnetic simulator that can be used to analyze these effects. The structure under test, shown in Fig. 3.43 (a), is the same as the one studied in the static coupling analysis, and the permittivity, permeability and bulk conductivity of the materials have been calibrated accordingly from TCAD simulations. Specifically, the highly doped semiconductor regions are treated as conductors with a bulk conductivity of 1.14x10 5 S/m, accounting for n-type doping of 10 20 cm -3 . The channel region is considered for both devices to be in the on-state, in order to allow for a conductive path between the drain-source electrodes. The gate length and width, noted in Fig. 3. 43 (a), where varied to observe the impact of geometry on the coupling behavior.

Considering the two-port configuration of Fig. 3.43 (b), ports 1 and 2 are assigned to the drain electrodes of the bottom and top device respectively. The source and gate electrodes of both devices have been assigned to the common reference node. Under small-signal analysis, when V GS > V TH in linear region of operation (V DS < V GS -V TH ), the MOSFET is considered as a resistor. On the contrary, in saturation (V GS > V TH and V DS > V GS -V TH ), the transistor behaves as a current source with i ds =g m •v gs , where g m is the transconductance of the device and v gs is a small voltage signal applied at the gate of the device. In this case, the output resistance of the transistor becomes considerably large. Extracting the g 21 parameter of the two-port network, the results are shown in Fig. 3.44, for a device with W=0.5μm and L=30nm. The data labeled as "no inductive" have been extracted by setting the permeability of all materials to be 0.01 times the vacuum permeability, thus excluding the inductive coupling mechanism from the power transmission. The difference between the two is negligible (less than 0.01%) and gets even smaller for a larger gate length (Fig. From the above analysis it is evident that capacitive coupling is the dominant mechanism of power transmission between active devices. Yet, layout-aware techniques must be followed to limit magnetic fields in the direct stacking of short and wide active devices with current flowing in loop paths. Hence, to pursue the dynamic coupling analysis, the inductive coupling will be neglected henceforth.

1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+09 1E+10 1E+11
W G = 0.5μm

3.3.1.b Impact of capacitive coupling

TCAD simulations were used to obtain the crosstalk S 21 (dB) parameter values by considering each electrode of the bottom/top device as an aggressor (port 1) to the other one (port 2). For the sake of conciseness, the crosstalk levels of top devices will be presented here as they are the same for the opposite case due to the reciprocity of the network. Moreover, for top devices there is the additional back-gate effect from the bottom device electrodes, making them more susceptible to noise coupling, prominently in the saturation region. In cutoff mode, for all victim-aggressor electrode pairs, there is an increase of the crosstalk level by 20dB/dec, attributed to the capacitive network between them. In detail, the top device gate electrode is the most susceptible to crosstalk from the bottom device gate electrode as they have a parallel plate capacitance that is essentially the C ILD which dominates in the series combination with C ox , C si as it is weaker than the other two. Regarding the crosstalk between the drain electrodes of the top and bottom device, it is ~12dB lower than the previous one and is attributed to the summation of the parallel plate capacitance from the diffusion area of the two electrodes with the capacitance between the 3D contacts. The crosstalk levels for the two other electrode pairs are weak, associated with fringing field capacitances between them. In saturation region for the top device, there is a plateau of the crosstalk level at low frequencies between the bottom device aggressor electrodes G bot , D bot to the top device drain electrode, due to the BG effect. Indeed, G bot (similarly D bot ) acts as a back-gate of the top-tier device, thus it injects a small-signal current i Dtop =g m,Gbot •v Gbot , where g m,gbot is the back-gate transconductance of the top-tier device due to G bot given by 𝑔 𝑚,𝐺𝑏𝑜𝑡 = 𝑑𝐼 𝐷 𝑑𝑉 𝐺𝑏𝑜𝑡 (3)(4) Moreover, the gate of the top device G top is partially screened by the inversion channel within the top device silicon film, so the crosstalk level is reduced by ~5dB. The most critical pair of nodes in this region of operation is thus G bot -D top .

Shrinking the gate length of the top/bottom device to 30nm, nominal L G in 28nm FDSOI technology, the simulation was repeated and the crosstalk level for each victim-aggressor electrode pair was obtained as shown in Fig. 3.47. Now, the crosstalk level of the G bot -G top electrodes decreases while the one of the D bot -D top electrodes remains the same (Fig. 3.47 (a)). Entering the saturation region of operation (Fig. 3.47 (b)), the top device drain electrode becomes sensitive to the G bot , D bot electrodes due to the BG effect, as explained before. In that case, the crosstalk between the gate of the bottom device and the drain of the top device is the most significant with a high plateau level of -46dB in the frequency range studied.

Transient response of top-tier devices to bottom-tier device aggressor signals

As identified in the previous section, the most critical capacitive coupling for two stacked active devices in 3DSI occurs between the drain of the top device and the gate/drain of the bottom.

Considering a CMOS digital circuit, the bottom device gate bias can switch from 0 to V DD , driven by a clock signal. This pulse-shaped switching of the bottom transistor gate bias, can lead to an important dynamic coupling to the top transistor channel. In order to experimentally determine the importance of this effect, high-speed drain current sampling measurements for a top-tier device were performed using the fast IV module (down to 10ns time resolution) of the Agilent B1530A device parameter analyzer, with the application of a pulse bias from 0 to 1V at the bottom device gate electrode (setup shown in Fig. 3.48). A bottom instead of a top tier device was chosen, because it has a BOX capacitance almost 5 times higher than the ILD, allowing us to capture more accurately the capacitance-related effects. As shown in Fig. 3.49 (a), it is evident that a parasitic spike occurs in the drain current at the beginning of the back-gate voltage pulse. This spike corresponds to the charging current of the drain-substrate capacitance (C d,bg ) and the peak amplitude, i ac , is given by Ohm's law for capacitors. In order to further shrink the rise time of the applied bias, the experimental setup was repeated in TCAD. It can be seen from Fig. 3.49 (b) that as the rise time of the switching event at the BG gets shorter, i ac is increased, making the dynamic more critical than the DC coupling. In order to assess the top device response to the dynamic coupling effect, the architecture of Fig. 3.51 was simulated applying the same bias conditions as previously. The effect appears to be the same with the bottom tier devices, however in this case the capacitance of interest is due to the fringing fields between the top device drain and the bottom device gate electrode.

3.3.2.a Impact of top device biasing

The impact of the top device operating region on the dynamic coupling effect between the bottom device gate electrode and the top device channel, was assessed via TCAD simulations. The top/bottom devices were selected to have equal gate length L G =30nm and width W G =1μm. A periodical trapezoidal signal was applied at the bottom device gate electrode, emulating a clock signal In cutoff region, since the drain current of the device is very small (3pA) due to the subthreshold conduction, the dynamic coupling parasitic spikes have a high amplitude (1μA) due to the very short rise/fall time of the applied clock signal at the bottom device gate electrode. Biasing the device in the linear region (Fig. 3.52 (c)), due to the high ON-state current of the device, the threshold voltage modulation by the static capacitive coupling induces a pulse of the same frequency as the clock signal and magnitude of I dc,coupl . Entering the saturation region (Fig. 3.52 (d)), the parasitic spike induced by the dynamic capacitive coupling vanishes, and the threshold voltage modulation dominates.

3.3.2.b Impact of device geometries and position

To investigate the impact of the geometrical parameters the width W Gtop and the length L Gtop of the top top-tier devices were varied. As shown in Fig. 3.53, there is an evident increase of i ac with W Gtop , while there is no dependence on L Gtop . This increase of the dynamic coupling only with the gate width indicates that the dominating capacitance in this effect is the one between the gate of the bottom and the drain of the top device. To assess the impact of the relative positioning on the dynamic coupling effect, the setup of Fig. 3.54 was simulated in TCAD, with the top device position shifted in the gate length direction, so that its drain electrode gradually overlaps with the bottom gate.

W G2 > W G1 L G1 , W G1 W G L G2 > L G1 G bot S top S bot D top Si substrate I D,top i ac,top V Gbot G top t ILD
Extracting the amplitude of the parasitic spike due to the dynamic coupling versus the misalignment between the two devices, it was found to be maximized (Fig. 3.55 (a)). Consequently, the maximum value of the C Dtop,Gbot capacitance can be given by the classic parallel plate capacitor expression and it can be reduced either by increasing the ILD thickness or decreasing the gate width as well as the drain region length. The latter is a process parameter determined by the Contacted Poly Pitch (CPP) (Fig. 3.55 (b)) which is further reduced with the scaling of the technology.

Inter-tier versus intra-tier coupling

Crosstalk between active devices is a common issue in every technology and is always better if it can be minimized. In conventional planar integration, the substrate crosstalk is the primary cause of interference in mixed-signal circuits. SOI planar technology is known to provide lower substrate crosstalk than the bulk CMOS process [START_REF] Raskin | Substrate crosstalk reduction using SOI technology[END_REF], because of the BOX presence and the use of resistive (>1kΩ-cm) [START_REF] Raynaud | Is SOI CMOS a promising technology for SOCs in high frequency range?[END_REF] or highly-resistive substrate (>1kΩ-cm) [START_REF] Ali | RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate[END_REF]. In addition, the GP underneath the SOI devices added nowadays, effectively shields them from substrate crosstalk [START_REF] Raskin | Analogue and RF performances of Fully Depleted SOI MOSFET Performances analogiques et RF de MOSFETs SOI complétement désertés[END_REF]. With that, mixedsignal interference is limited to the horizontal direction (intra-circuit) coupling through the dielectric medium, an issue that can be solved by proper layout placement of the devices and isolation techniques [START_REF] Ali | RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate[END_REF], [START_REF] Kim | Effective crosstalk isolation through p+ Si substrates with semi-insulating porous Si[END_REF], [START_REF] Stefanou | Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology[END_REF].

In 3DSI, a device placed at one tier can suffer both from horizontal coupling from adjacent devices within the same tier (intra-tier) as well as coupling from the stacked devices (inter-tier), which has been analyzed so far. In order to estimate the relative strength of the two, the simulation setup of Fig. 3.56 was performed in HFSS. The medium that surrounds the devices is SiO 2 . Metal lines at the BEOL layer above the devices have been excluded in order to restrict the analysis at the active device level.

Fig. 3.57 Crosstalk levels for the victim device drain electrodes of a device with W G =620nm (red) in the case of inter-tier coupling (continuous line) and intra-tier coupling (dashed line). Increasing the width of the two devices in each case to W G =2μm (black), the crosstalk difference gets increased

The simulation results of the S21 parameter that illustrate the crosstalk for each case are given in Fig. 3.57. For W G =620nm, the inter-tier crosstalk is 3.4dB greater than the intra-tier, as the former is enhanced by the vertical coupling from the diffusion area plus the horizontal coupling from the 3D contact.On the contrary, the intra-tier crosstalk is associated mostly with the horizontal coupling of the contacts rather than the weak fringing capacitances of the diffusion areas. Furthermore, increasing the width of the two devices in each case to W G =2μm, the crosstalk difference is even more amplified.

From this comparison it is sensible that in order to obtain comparable inter-tier crosstalk values with the intra-tier ones, decoupling techniques are needed and are investigated in §4.2.

Conclusion

In this chapter the vertical electrical coupling between devices placed in two different tiers of a 3D sequential structure has been characterized experimentally and further analyzed with the aid of TCAD simulations. This interference has been demonstrated to cause noise coupling among the two devices and unwanted threshold voltage variations for stacked devices.

All the geometry and biasing related dependencies of these effects have been explored and it has become evident that the static coupling effects are reduced when the two devices are misaligned, as opposed to the dynamic coupling effects. Moreover, regarding noise coupling (crosstalk) it is evident that it is of higher levels for stacked devices with a high W/L ratio, due to the back-gate coupling effect.

Furthermore, a study of the coupling-induced effects in the static and noise behavior of 3D sequential top tier transistors has been presented. Through both measurements and TCAD simulations, it was shown that the coupling-induced ΔV TH , ΔI off and ΔI on have high values considering analog applications, however they are well within the local variability limits of 28 nm FDSOI technology for digital circuits, where sub-μm devices are used. Using these values as a metric for the 3DSI of other applications we have concluded that for digital applications stacked on top of analog applications, the ILD thickness has to be greater than 350nm. Concerning the low-frequency noise performance of the top tier transistor, no coupling-induced impact was observed regardless the transistor area.

COUPLING EFFECTS IN 3DSI CIRCUITS:

IMPACT ON OPERATION AND PROPOSED

SOLUTIONS

This chapter analyzes the effect of inter-tier capacitive coupling on monolithic 3D circuits. The most critical combinations of tier stacking with heterogeneous integration are investigated in order to conclude on the critical dimensioning of the structures and the necessity of inter-tier isolation.

More specifically, the digital tier stacking which has been studied at device level in chapter 3, is further analyzed with the aid of a 2-bitcell Sequential 3D SRAM under the influence of both static and dynamic coupling. Additionally, the sensitive case of a Mixed-Signal/RF circuit like the Ring Oscillator (RO) is examined on top of either a digital or an analog application tier at the bottom with a power supply of 1V and 2.5V respectively. Lastly, for the stacking of sensitive applications where the intertier coupling cannot be tolerated, decoupling methods and techniques are explored targeting an efficient process flow compatible with 3DSI.

Impact of inter-tier coupling on circuit operation

3DSI offers the flexibility of placing circuits on different tiers to achieve high performance and ultimate integration density. However, this is at cost of the undesirable vertical coupling through the ILD having a thickness of several hundreds of nanometers. In Chapter 3, the coupling effects have been deeply examined at device level, resulting in several significant conclusions that can enable to pursue the analysis at circuit level. A brief recapitulation is as follows:

• In monolithic 3D-ICs, capacitive coupling induced by the electric field dominates the inter-tier coupling whereas the inductive one is negligible because of the small geometries of active devices having rectangular shapes in conjunction with the low current densities that result in weak magnetic fields.

• The inter-tier capacitive coupling can cause signal transmission among the devices placed in different tiers and unwanted threshold voltage variation for stacked devices.

• In particular, the coupling induced threshold voltage shift of stacked devices, is identified as the strongest interference as it can potentially increase leakage current/power and decrease the ON-current.

• At a device level, it was proved that for digital device stacking the inter-tier static coupling is negligible compared to the mismatch variations in 28nm FDSOI technology. Thereby, the presence of the inter-tier coupling is not widening much the process corners in digital design and thus can be considered as tolerable.

• Additionally, digital devices stacked on top of analog devices having V DD =2.5V, must employ a thicker ILD (around 350nm) to result in the same level of coupling-induced ΔV TH as digital on digital devices. This thickness of the ILD is tolerable for the 3D contact processing.

• Finally, analog devices stacked on top of either digital or analog devices have been characterized as critical cases of inter-tier coupling as their coupling-induced ΔV TH is shifted to higher values due to their thicker silicon body (higher gm/Id ratio) and oxide (larger voltage swing), compared to top-tier digital devices. Adding to that also the fact that analog circuits are commonly more sensitive to noise and particularly to V TH variations, it is preferable to place analog circuits at the bottom tier of a 3DSI process scheme, or to utilize inter-tier isolation methods to decouple effectively their body potential.

With the above being mentioned, the inter-tier coupling analysis (both static and dynamic) has to be further extended at a circuit level, in order to draw conclusions regarding the necessity of electrical isolation for the remaining cases of tier stacking under a heterogeneous integration scheme. Tiers comprised of either exclusively Digital or Mixed-Signal/RF can be stacked on top of Digital and Analog tiers resulting in the combinations demonstrated in Table 5.1. Except for the case of Digital applications stacked on top of Analog applications where an ILD thicker than 350nm can limit the inter-tier coupling to tolerable levels, the influence of the inter-tier coupling effects for the rest of the cases is examined in this section with the aid of sensitive circuits in each category.

Chapter 4 -Coupling effects in 3DSI circuits: Impact on operation and proposed solutions 100 Specifically, for the victim top-tier applications, the SRAM is selected as a representative example for digital circuits and a RO for the case of Mixed-Signal/RF circuits. An aggressor at the bottom tier can be either a DC voltage equal to the power supply level of either digital or analog circuits, or a high-speed switching pulse such as a digital clock in order to study the impact of dynamic coupling effects. Under the foregoing analysis, the stacked circuit examples which will be studied in the following sections are presented in Table 4.1. In detail, a 2-bitcell Sequential 3D SRAM is selected for the "digital on digital" case and a RO on top of a DC bias of 2.5V for the "Mixed-Signal/RF on Analog" case. Moreover, in order to construct a solid conclusion for the Mixed-Signal/RF on digital circuits, the impact of dynamic coupling has also been studied featuring a digital clock at the bottom tier.

2-bitcell Sequential 3D SRAM (Digital on Digital case)

Within the More-than-Moore paradigm, 3DSI SRAM cells are framed as an extremely appealing architecture as they can provide denser and faster memory blocks, co-integrated among various components (heterogeneous integration). Related works [START_REF] Liu | Ultra-high density 3D SRAM cell designs for monolithic 3D integration[END_REF]- [START_REF] Srinivasa | ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support[END_REF] clearly demonstrate the virtues of this option. Therefore, in order to study the possible impact of the coupling-induced V TH shift on a circuit's operation, a 6-Transistor (6T) SRAM cell has been selected as a reference. Thus, for our analysis, the configuration of a 3DSI 2-bitcell SRAM is examined, i.e. two stacked SRAM cells that are identical in layout design, so that the inter-tier static coupling effects are maximized.

4.1.1.a SRAM bitcell architecture

Before proceeding to the analysis of coupling effects, the reader shall be familiar with the SRAM bitcell architecture. An SRAM bitcell is the basic building block of the SRAM array. Each bitcell circuit is capable of storing single bit of information. It provides non-destructive read operation, write capability and data storage as long as the SRAM bitcell is powered up. Fig. 4.1 shows a schematic view of a 6T SRAM bitcell which can be either at the top-or bottom-tier of the 3DSI process scheme.

However, because of the asymmetrical SOI structure of the top-tier devices, their back-gates will be tied to the bias of the respective bottom-tier devices. and '0'. The data in the SRAM bitcell is stored as long as the power is maintained to the bitcell.

The access transistors are controlled by the wordline (WL) and serve as switches between the inverter pair and the complementary pair of bitlines (BLL, BLR), which are used to read in or write to the bitcell. The bitcells are accessed horizontally by asserting the wordline during read and write operation. When the wordline of a row is asserted 'HIGH', all the memory bitcells in the selected row ae enabled and can be ready for read and write operations. Therefore, an SRAM bitcell can be in three different states: Reading, writing or standby (bit retention). The RSNM is defined as the maximum amount of static noise that can be tolerated by the cross-coupled inverter pair so that the bitcell retains its data [START_REF] Subramanian | Parameter extraction of nano-scale MOSFETs using modified Y function method[END_REF]. Between the two stable states of of an SRAM bitcell there is the meta-stable point, a temporary state that the bitcell content can be flipped to one of the two stable states.

4.1.1.b Simulation setup description

As presented in Chapter 3, the inter-tier coupling results in a Threshold Voltage shift (ΔV TH )

for the stacked devices and decreases exponentially with the ILD thickness. For digital device stacking -i.e. top/bottom tier contain purely digital devices with V DD =1V -it has been demonstrated that the coupling induced threshold voltage shift is nearly 16mV for t ILD =130nm. Except for using coupling advantageously [START_REF] Batude | 3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM[END_REF], previous work considering undesirable coupling impact [START_REF] Fan | Stability and performance optimization of heterochannel monolithic 3-D SRAM cells considering interlayer coupling[END_REF] has been carried out only for a single S3D SRAM bitcell having half of the transistors in each tier. In order to assess whether the bottom SRAM cell operation can significantly affect the top SRAM cell performance, some of the most common stability metrics were investigated: the Read and Write Static Noise Margin (RSNM & WSNM) and the Supply Read Retention Voltage (SRRV), that can provide a deep overview of the top SRAM cell static stability [START_REF] Guo | Large-scale SRAM variability characterization in 45 nm CMOS[END_REF], [START_REF] Singh | Robust SRAM designs and analysis[END_REF]. The impact of bottom-tier coupling was studied and compared to that due to mismatch-induced variations, using SPECTRE [START_REF] Cadence | Spectre ® Circuit Simulator Components and Device Models Reference[END_REF] simulations of the circuit with or without the bottom-tier coupling.

The For the bottom SRAM cell operation 3 cases were examined: 1) no operation (zero power supply), 2) a stored '0' (V CLbot =0V, V CHbot =1V), 3) a stored '1' (V CLbot =1V, V CHbot =0V). Table 5.2

|DV TH |=15.6mV V Dtop =30mV to 0.9V LETI-UTSOI2 V Gbot =0 to 0.9V V Gbot =0V Drain Current I Dtop [µA/µm] Gate Voltage V Gtop (V) V Dtop =30mV
Chapter 4 -Coupling effects in 3DSI circuits: Impact on operation and proposed solutions 104 summarizes the bottom transistor gate bias for each of the 3 cases. These conditions were applied in the BGs of the respective top transistors to emulate the inter-tier coupling effect.

Bottom SRAM OFF

Bottom SRAM ON

Stored '0' Stored '1' V PULbot & V PDLbot 0 V 1 V 0 V V PURbot & V PDRbot 0 V 0 V 1 V

4.1.1.c SRAM stability metrics analysis

The RSNM represents the maximum tolerable DC noise voltage at each storage node before causing a read upset. The extraction of the RSNM was performed by applying mismatch-related Monte Carlo simulations to capture the impact of the mismatch variations. The SRAM cell can be repeated over 1 million times in memory circuits resulting in 6σ of mismatch variations. However, the 3σ limit is critical enough to compare it with the coupling-induced shift and requires 1000 runs rather than over 1 million in the case of the 6σ limit. From the obtained butterfly curves (Fig. 4.5 (a)), the mean represents the typical behavior while the blue curve shows the worst-case of mismatch among the 1000 runs. Following the same methodology as for the RSNM, we also extracted the WSNM that characterizes the write-ability of the SRAM bitcell (Fig. 4.6). Concerning both RSNM and WSNM, the largest square was fit for the worst set to estimate the mismatch related SNM degradation.

Additionally, the mean SNM was extracted and comparing the two values, we extracted the impact of V TH mismatch (-27% for RSNM, -10% for WSNM). As shown in Fig Regarding the SRRV, it is defined as the maximum allowed reduction of cell supply voltage for which the read stability is not affected. It is an equally important stability metric for SRAM cells [START_REF] Guo | Large-scale SRAM variability characterization in 45 nm CMOS[END_REF].

It can be estimated measuring the bitline current I BL while the power supply of the cell (V CELL ) is ramped down. At a specific value of the V CELL (called V flip ), the stored bit is flipped and I BL drops suddenly. Then the SRRV is extracted as

SRRV = 𝑉 𝐷𝐷 -𝑉 𝑓𝑙𝑖𝑝 = 1 -𝑉 𝑓𝑙𝑖𝑝 (4-1)
The simulation results for a typical top-tier bitcell at the three bottom-tier bitcell operation cases are shown in Fig. 4.7 (a). The impact of mismatch can be seen in Fig. 4.7 (b), while with the addition of the coupling induced shift is shown in Fig. 4.7 (c). In this latter case, we obtain an additional SRRV reduction of 3.5% (-34.5%→-38%). From Fig. 4.7, the effects of the value stored in the bottom-tier SRAM on the bitline discharge of the top-tier SRAM can be evaluated. The latter mimics a readout for a stored '1' and for SRRV, it is apparent that the most critical case is when a '1' is stored at the bottom cell. Due to symmetry reasons, the most critical case for a stored '0' will be when a '0' is stored at the bottom cell. Nevertheless, the effect of inter-tier coupling on the SRAM stability metrics (1 to 3.5%) looks negligible compared to the mismatch-induced variations. In conclusion, the fact that SRAM features devices with very small sizes and thus significantly affected by device variability seems to allow for a safe superimposing of SRAM arrays with V DD = 1V across tiers with an ILD of 130 nm thickness.

4.1.1.d Impact of relative misalignment for the stacked SRAM cells

The impact of the relative positioning was also studied, by placing each top-tier transistor drain in different distances with respect to the bottom-tier transistor gate. For the purpose of this study, mixed-mode TCAD simulations were performed on a circuit containing the stacked SRAM cells.

A simplified layout of the top-tier circuit is shown in Fig. The DC characteristics of the top-tier SRAM circuit for each case of bottom-tier operation (no power supply, stored'0', stored'1') and for the two positioning scenarios (gate overlap=0/1), are shown in Fig. 4.9 It is evident that the maximum coupling induced SNM reduction of 10 mV for the top tier SRAM occurs when there is no misalignment between the stacked SRAM cells.

4.1.1.e Impact of dynamic coupling effects on top-tier SRAM bit retention

The immunity of the top-tier SRAM cell to dynamic coupling from the bottom SRAM cell can be studied with transient analysis. As seen from the butterfly curve marked in black color in Fig. 4.10 (a), the intersection point of the voltage transfer characteristic of the SRAM cell is a meta-stable state.

This means that the static SRAM operation can potentially move to any of the two stable states so that any noise applied can cause the bitcell content to flip. Without loss of generality, it is assumed that the output node of the left inverter, Channel-Low (CL) node initially is at '0' and thus the Channel-High (CH) node is at '1'. When both the Bit-Lines (BL and BLL) are pre-charged and Word-Line (WL) is enabled, BL should be pulled down through the transistors PGL and PDL, since they form a potential divider and raise the CL node potential to ΔV (Fig. 4.12 (a)). At that time t 1 , the bottom SRAM can be OFF or write '0' or '1' with the shortest switching time in 28 nm FDSOI, that is t R ~10ps [START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF]. As seen from Fig. 4.12 (b), the potential difference in the CL node of the top SRAM is not exceeding 5 millivolts for all write operation cases of the bottom SRAM cell, remaining well below the meta-stable point even for the worst mismatch case.

Bottom SRAM writes

Top SRAM reads As an outcome, dynamic coupling effects induced by the bottom-tier SRAM cell operation do not result in a read destructive operation for the top-tier SRAM cell. Consequently, the demonstrated immunity of a sensitive digital circuit like the SRAM to both static and dynamic coupling shows that digital on digital circuits with 130 nm thick ILD do not necessarily need an inter-tier GP.

RO stacked on top of an analog tier (Mixed-Signal/RF on Analog case)

In order to assess the sensitivity of top-tier Mixed-Signal/RF circuits on electrostatic coupling due to the direct stacking on top analog tier circuits, the circuit example of a 3-stage RO (Fig. 4.13) has been selected. This 1.68% shift of the fundamental frequency of the RO is far from negligible for RF applications, therefore an inter-tier isolation is necessary. However, regarding the phase noise of the top RO, there is no observable impact of DC coupling from the bottom Analog tier electrode bias (Fig. 4.15).

RO stacked on top of a digital tier (Mixed-Signal/RF on Digital case)

Clock generators are an essential part of digital circuits, as they coordinate actions and synchronize different parts of the circuit. A clock signal produced by a clock generator, is a high-speed switching signal between two logic levels, 0 and 1. In particular, for an EOT in the 1 nanometer range the logic 1 coincides the 1V of the power supply. As a consequence, the high frequency content of a clock signal can be an intensive source of noise coupling for stacked Mixed-Signal/RF.

To evaluate the impact of a digital clock operating at the bottom tier on the top-tier RO, a periodical trapezoidal voltage signal was applied at the BG each top-tier device (Fig. 4.16) with a Frequency (GHz) The result in the frequency domain (Fig. 4.17) is a mixing product with a frequency shift (pulling) of 80MHz and several spurious harmonics appearing in the signal's spectrum. However, it may be noted that the scenario of each top-tier device being stacked upon a digital gate with an applied clock signal is an extreme case and rather unrealististic.

0 2.5 510MHz V bot V bot (V) f osc =30.2GHz Amplitude (V 2

Fig. 4.17 FFT for top-tier RO with the clock signal applied at each SOI back-gate along with the reference case

On the contrary, it is quite possible that a single device of the three-stage RO can be influenced by a clock signal at the bottom-tier. Fig. 4.18 shows the result of the RO spectrum after enabling the clock signal at the BG of one of the PMOS or NMOS devices of the three RO stages independently. As observed, the frequency deviation from the reference state can be around 340MHz while the harmonic purity of the oscillating signal worsens. Taking into account the foregoing analysis, it is rather reasonable to conclude that a decoupling layer is mandatory to ensure the desired operation of Mixed-Signal/RF being stacked on digital circuits.

Methods and techniques to mitigate inter-tier coupling effects in 3DSI

Critical dimensioning of 3DSI structures and 3D design rules

The inter-tier coupling effects depend strongly on the characteristic dimensions of a 3D sequentially integrated structure. These are process depended parameters, i.e., they are determined by the process flow (etching, deposition) and a circuit designer cannot control them. On the other hand, there are certain parameters related to the top layout view of a device which are under the control of a circuit designer, such as the width and the length of an active device. Alternatively, the layout configuration B of Fig. 4.20 can be adopted in case of direct device stacking. This configuration provides a smaller form factor for the stacked structure and the same footprint for both devices. In addition, layout B provides slightly lower crosstalk between top/bottom drain electrodes (4 dB difference for W G =1μm). However, the drawbacks are that: i) the contact density upon the active region is decreased compared to the layout configuration A and ii) the bottom-tier drain electrode can be capacitively coupled to the top-tier gate electrode. The latter is a function of the 3DCO-PC distance with a minimum value determined by the CPP parameter of the technology node. Therefore, it is on the designer's hands to choose the layout configuration of the top-tier devices with respect to the bottom ones, identifying the most critical nodes in his circuit design and isolating them.

4.2.1.a ILD thickness optimization

The ILD thickness t ILD is a process parameter which can be tuned accordingly in order to limit the inter-tier coupling effects. The charge-coupling factor of top-tier digital and analog devices decreases exponentially with the ILD thickness (Fig. 4.22), hence the acceptable level of the threshold voltage modulation at a device level for each application (see chapter 3) sets the minimum limit for the ILD thickness. Coupling Factor (mV/V) ILD thickness (μm)

Digital Analog (V DD =1V) (V DD =2.5V)
The impact of the ILD thickness on the crosstalk performance between the stacked tiers was also examined with the aid of TCAD simulations. Using the simulation setup of Fig. 4.23 (a) and varying the ILD thickness, the extracted crosstalk levels are plotted in Fig. 4.23 (b). It is apparent that increasing the ILD thickness from 0.2 to 1μm, a crosstalk suppression of 17dB can be achieved.

a) b)

Fig. 4.23 (a) Simulation setup in TCAD for evaluation of crosstalk dependence on ILD thickness (b) Crosstalk levels between the top-tier active device and the bottom-tier electrode versus frequency for different ILD thickness

On the other hand, increasing the ILD thickness worsens the 3D Contact AR (3DCO AR) as depicted in the schematic cross-section illustration of Fig. 4.24. Hence ILD thickness is limited by the 3DCO AR with a preferred maximum at 350nm for the digital top-tier devices on analog bottom-tier ones. For greater reduction of the coupling-induced threshold voltage shift and the crosstalk levels between the stacked tiers, other decoupling methods must be investigated to keep the 3DCO AR at low values.

4.2.1.b Top/bottom device misalignment

The inter-tier static coupling impact may be efficiently reduced when there is a misalignment between top and bottom device positions. Indeed, implementing the simulation setup shown in Fig. As observed in Fig. 4.26, TCAD simulations revealed that in cases where the bottom-to-top overlapping area ratio is lower than 0.5, the coupling-induced ΔV TH can be decreased by a factor of 3. This observation may function as a guideline for 3D design rules in the near future.

Inter-tier shielding through GP: challenges and solutions

In 3DSI, vertical coupling between active device tiers has been identified as critical for analog and mixed-signal/RF applications. Therefore, further decoupling is needed for the stacking of tiers incorporating these sensitive applications.

Several methods have been reported concerning the isolation of active devices targeting planar and 3D technologies. Specifically for planar technologies, in [START_REF] Wu | A Faraday cage isolation structure for substrate crosstalk suppression[END_REF] a Faraday-Cage isolation structure was presented that can suppress substrate coupling. It consists of a ring of substrate VIAs connected to the grounded backplane at the bottom of the substrate and shorted together by a ring of metal at the top. On the substrate coupling also, Kim et al. [START_REF] Kim | Effective crosstalk isolation through p+ Si substrates with semi-insulating porous Si[END_REF] have demonstrated RF crosstalk isolation by the use of through-the-wafer porous Si (PS) trenches because of their semi-insulating property. Furthermore, in [START_REF] Chen | An efficient noise isolation technique for SOC application[END_REF], a method to suppress substrate noise for future RFIC design has been investigated using heavily doped pocket structures.

On the other hand, in SOI technology that incorporates a buried WSi 2 (Tungsten disilicide) metal GP beneath the BOX layer, Stefanou et al. [START_REF] Stefanou | Ultralow Silicon Substrate Noise Crosstalk Using Metal Faraday Cages in an SOI Technology[END_REF] have achieved substrate crosstalk isolation using a metal Faraday cage structure where the isolation region is surrounded completely by solid metal walls. In detail, the Faraday cage is comprised of a buried metal tungsten silicide GP beneath the BOX layer as the bottom of the cage, and vertical metal-lined n polysilicon-filled trenches in the active silicon layer as the cage walls. Although the above-mentioned methods provide efficient crosstalk suppression, they require complex process techniques and large form factor structures that are not suitable for 3DSI where the highest possible density is desired.

Recently, [START_REF] Vandooren | Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications[END_REF] demonstrated a buried metal (TiN) line implementation in a 3DSI process scheme (Fig. 4.27). This inter-tier metal layer acts not only as a back-gate to the top-tier device through the back oxide, but also limits the vertical coupling with the bottom-tier device.

In this section an efficient way of inter-tier electrical isolation is investigated with the insertion of an inter-tier thin conductive layer, i.e. a GP, between the sequential tiers made of a semiconductive material. The necessity for an inter-tier GP integration results from the specifications targeted for each application and the estimation of the trade-off between the process complexity and the inter-tier coupling sensitivity. The screening effectiveness of an inter-tier GP against vertical coupling is investigated taking into account its material properties and the FEOL compatibility. digital device (EOT=1nm, V DD =1V) on top of an electrode that can be either the bottom gate or a metal line and in between a layer made of either SiO 2 (no GP case), silicon, polysilicon or copper. The obvious choice for a shield against electric field coupling is a metal, however the use of a semiconductive material has several advantages that will be discussed in detail in the next section. It is worth mentioning that in order to avoid the GP being floating, a grounded contact (GP_CO) has been placed on it. This qualitative analysis can help conclude on the GP material choice, its dimensions and the ground contact pitch. For the purpose of the analysis, TCAD simulations have been performed. Although TCAD provides accurate answers on problems employing semiconductors, its quasistatic approach may not be appropriate for high frequency analysis. For that reason, HFSS has been utilized for the validation of the TCAD simulations in the high-frequency domain.

4.2.2.a Electrostatic screening

As studied in chapter 3, the capacitive coupling of the bottom-tier gate electrode to the top device channel can cause a shift of the top-tier device V TH . This is the most significant coupling mechanism as it provides a direct modulation of the top-tier device drain current by the bottom-tier device electrodes both in DC as well in AC domain via the back-gate transconductance.

With the insertion of an inter-tier GP, the vertical electric fields responsible for the static coupling can be suppressed as seen by equation 4.2, supposing that the GP has a sufficient coverage of the bottom tier bias electrode and contains at least one grounded contact with low resistance.

Then the top-tier device threshold voltage shift induced by the bottom-tier gate electrode, becomes a function of the remaining fringing fields as the GP covers only the bottom part of the active device.

In order for a semiconductor to act as a shield, its conductivity must be comparable to a metal. Fig. 4.29 shows experimental data [START_REF] Mandurah | Phosphorus Doping of Low Pressure Chemically Vapor-Deposited Silicon Films[END_REF] for the resistivity of monocrystal and polycrystal silicon (polysilicon) versus their concentration of phosphorus dopants (n-type). It is apparent that for low doping concentrations, polysilicon presents an enhanced resistivity compared to monocrystal silicon especially, yet for doping concentrations greater than 10 18 cm -3 the difference in the resistivity of the two materials decreases exponentially, becoming negligible above 10 20 cm -3 .

Fig. 4.29 Resistivity of phosphorus-implanted, low pressure poly-crystal silicon films as a function of average dopant concentration.

The resistivity of n-type, single-crystal silicon is shown for comparison [START_REF] Mandurah | Phosphorus Doping of Low Pressure Chemically Vapor-Deposited Silicon Films[END_REF].

TCAD simulations were carried out to probe the impact of doping concentration on the coupling-induced ΔV TH for an inter-tier GP made of silicon. Three cases of GP covering were

Coupling-induced ΔV TH of the top-tier device to the bottom-tier electrode versus average dopant concentration in the intertier GP made of (a) silicon and (b) polysilicon

Before analyzing the impact of GP doping level, it is worth noticing how even the sole presence of an undoped (or lightly doped) grounded GP layer (either Si or polySi) causes a suppression of one order of magnitude, regardless its area. Nevertheless, if a stronger decoupling is necessary, it is evident that for doping concentrations above 10 17 cm -3 the static coupling suppression is exponential, reaching 5 orders of magnitude for 10 20 cm -3 n-type doping when the GP is very large (limited fringing fields). On the other hand, for Area Gbot > Area GP , the suppression obtained by the insertion of the inter-tier GP exhibits a plateau for doping concentrations above 10 19 cm -3 due to

G bot G bot G bot GP GP GP 1E+15 1E+16 1E+17 1E+18 1E+19 1E+20 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2
Si GP doping (cm -3 ) Threshold Voltage Shift (mV)

Case (1) Case (2) Case (3) No GP Case 1E+15 1E+16 1E+17 1E+18 1E+19 1E+20 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2
PolySi GP doping (cm -3 )

Case (1) Case ( 2)

Case (3)
No GP case a. b.

fringing electric fields. Nonetheless, for the intermediate cases where the GP is not very large compared to the top-tier device channel, yet the bottom-tier gate electrode is significantly covered by the GP, the suppression follows the trend of the blue line in Fig. 4.31 (a).

Alternatively, Fig. 4. 31 (b) shows TCAD simulation results obtained by choosing Polysilicon as the material of the inter-tier GP. As observed, the trend is the same for the three cases of GP covering as for the Silicon GP, however higher doping concentrations are needed in order to reach a quasimetallic behavior for the PolySi GP and therefore act as a shield. For comparison, a copper GP was also simulated and the coupling-induced ΔV TH results for the three materials are plotted in Fig. 4.32, considering a doping concentration of 10 20 at/cm 3 for both silicon and polysilicon GP.

Fig. 4.32 Coupling-induced ΔV TH results comparison between silicon, polysilicon and copper as the material in the GP layer region

The insertion of a silicon GP between the active device tiers yields a superior static decoupling performance compared to the plain increase of the ILD thickness when there is no GP as seen from Fig. 4.33. From the lowest to the highest doping concentration of a Si GP the suppression level can be respectively 1-5 orders of magnitude greater than a 1μm thick ILD. Moreover, even the scenario of a very lightly doped (10 15 ) GP layer, combined with minimum ILD thickness, provides better decoupling than almost all cases of ILD thickness when no GP is introduced.

1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 Gbot > GP Gbot = Gtop Gbot << GP

Threshold Voltage Shift (mV)

4.2.2.b High-Frequency electric field screening

An inter-tier GP must provide crosstalk isolation between the sequential tiers, especially when heterogeneous integration is desired. High crosstalk immunity is critical to enable the sequential stacking of tiers that integrate noisy logic and sensitive low-noise RF and analog applications. In order to estimate the RF decoupling efficiency of an inter-tier GP, the methodology proposed in [START_REF] Kim | Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes[END_REF] and [START_REF] Vandooren | Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications[END_REF] was followed, implementing the simulation setup of As observed in Fig. 4.35 (a), the decoupling performance of a silicon GP reveals two significant properties. First, there is an increase of the suppression level with higher doping levels of the silicon GP, a behavior also observed in DC. Considering the semi-conductive nature of silicon, a portion of the electric field manages to get through the GP layer for low frequencies. A second remark is that there is a certain frequency after which the GP layer appears to be capacitively transparent. This can be directly attributed to the resistivity of the inter-tier GP, which is enhanced for higher doping concentration. The frequency beyond which the slope of the S21 parameter gets greater than 20dB/dec can be defined as the maximum decoupling frequency f D,max . Fig. 4.36 (a) and (b) mark f D,max for the minimum and maximum doping concentrations respectively of the silicon GP simulated.

Frequency (Hz)

No GP Si GP f D,max (10 20 cm -3 ) V D V D a. b.
When the device is biased in the saturation region (Fig. 4.35 (b)), the inter-tier GP screens out the coupling through the BG transconductance with a suppression level greater than 70dB. The effectiveness of the GP is again determined by the maximum decoupling frequency as defined for the cutoff region of operation.

The validity of TCAD simulations in the high-frequency domain can be confirmed by employing the full-wave EM simulator HFSS, as long as the bias current of the top-tier device is low (cutoff region). For that scope the simulation setup was repeated in HFSS for three cases: the first excluding the GP and filling the area with SiO2, the second for a silicon GP (10 20 cm -3 n-type doping) and the last for a copper GP. Specifically for the highly doped silicon GP, the material properties had to be defined, assigning a bulk conductivity of 1.23x10 5 S/m as calculated from the experimental data of On the contrary, calibrating the conductivity of the GP layer in HFSS to account for lower doping concentrations of silicon, the simulation results are shown in Fig. 4.37 (b). Although there is an agreement with TCAD simulations concerning the maximum decoupling frequency as a function of the conductivity, the same is not true for the suppression level. The latter is overestimated in HFSS indicating that it is related to the conduction mechanisms being different in semiconductive materials than metals. Consequently, TCAD is the appropriate tool to further evaluate the properties of the GP. On the other hand, it is worth noticing that the cross-sectional magnetic field contour plot in Fig. 4.40 reveals the transparency of the GP to the bottom-tier RF signal. Indeed, the magnetic field penetrates the GP layer reaching the upper active region. In most cases, magnetic field coupling is considered negligible, yet careful layout-aware design techniques must be followed in 3DSI to keep magnetic fields as low as possible.

4.2.2.c Impact of inter-tier GP dimensions and GND contact pitch

Repeating the simulation setup of Fig. 4.34 in TCAD and expanding the GP area with respect to the top tier device active region, the crosstalk suppression was extracted as a function of the well GP coverage of the top tier active device region (Fig. 4.41).

(a) Crosstalk suppression and (b) Maximum decoupling frequency versus the ratio of the inter-tier GP area with respect to the top active region for one GND contact

To address this issue, the number of GND contacts for the GP layer can be increased, so that the TCAD simulation setup becomes that of Fig

4.2.2.d Inter-tier GP processing challenges and solutions

A polysilicon GP offers several advantages compared to a metallic GP. First, it is compatible in terms of Front-End-Of-Line (FEOL) contamination environment for top MOSFET processing. Second, it offers the possibility of dual doping type to propose several V TH flavors without requiring gate stack engineering or channel doping. With the insertion of the inter-tier GP, the top BOX thickness is in the 20/25 nm range in order to ensure good SCE control for L G in the 30nm range. The latter enables also the Back-Gate bias flexibility as in planar SOI technology, which allows the designer to modify the threshold voltage dynamically.

However, especially for RF applications a high GP doping level is required. As a consequence, traditional GP doping through the top channel cannot be applied (Fig. 4.44). To increase the GP doping concentration above this limit, the polysilicon needs to be doped directly after its deposition or deposited using in-situ doped epitaxy. With GP direct doping, a doping concentration of 1.8 x10 20 at/cm 3 has been reached, enabling one to reach a sheet resistance of 295 Ω/sq for a 34nm-thick polysilicon layer (Fig. 4.29). Therefore, this type of GP answers to all the specifications in terms of doping level and sheet resistance (-20 dB up to 100GHz for 1 GND contact to the GP), as well as thickness (to preserve the 3DCO AR) and FEOL contamination category.

Conclusion

In this chapter the coupling effects have been further examined at a circuit level, providing significant results regarding the heterogeneous integration of applications in 3DSI. The overall conclusion is that concerning purely digital 3D sequential circuits there is no major coupling between top and bottom tiers, therefore inter-tier isolation methods and techniques are not necessary.

However, when it comes to mixed signal and RF applications, further decoupling is needed so that the inter-tier coupling. The latter can be achieved either by process optimization (ILD thickness increase) or proper layout (misalignment of the stacked devices, 3D contact positioning). In order to obtain even greater reduction of the capacitive coupling, an inter-tier decoupling layer (GP) is required. By exploring the decoupling efficiency of semiconductive materials, it is demonstrated that even the lowest doping concentration provides greater static decoupling than a 1μm thick ILD.

Consequently, the use of the inter-tier GP maintains the 3DCO AR below 350nm. Concerning high frequency electric field screening, it is shown that the decoupling frequency band of the inter-tier GP is a function of its resistivity, hence for RF applications a high doping concentration is needed. As a consequence, a technological solution is proposed to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

ANALYSIS OF COUPLING EFFECTS IN A 3DSI CMOS IMAGE SENSOR

This chapter examines the impact of 3D Sequential Integration on the performance of a CIS partitioned in different tiers. The CIS serves as an ideal case study of coupling effects as it consists of highly sensitive parts to noise and threshold voltage variations, while it presents also an extremely appealing use of 3DSI to the semiconductor industry. The first section of the chapter is devoted on the contemporary trends of CIS and their operating principles. Afterwards, the coupling effects analysis is conducted for a CIS realized in 3DSI technology, analyzing the impact on the most critical figures of merit at pixel level. The goal of this chapter is to ensure the normal operation of the CIS, underlining the potential advantages emerging from the 3DSI technology.

Introduction

The emergence of user interactive applications is driving the electronics industry towards heterogeneous technologies, in which the analog sensing part is co-integrated with digital processing parts. Key enabler of heterogeneous integration nowadays is the transistor dimensional scaling following Moore's law [START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF] within the More-than-Moore direction (details in Chapter 1). The latter involves a wide variety of applications that enables the interaction with people and the environment [START_REF] Arden | More-than-Moore' White Paper[END_REF].

One of the major driving applications within the More-Than-Moore direction is the CIS, as they require the heterogeneous integration of different technologies. In detail, the sensing interface consists of a photon-to-electron converter (photodiode) in the pixel array, the readout part is made with the aid of an analog circuit which in turn outputs the sensing information to a digital circuit for processing. Thanks to the development of PPDs, CIS have been dominating the consumer electronics market over the last decade. This breakthrough invention, in conjunction with a lower cost fabrication and higher data rates made CIS more appealing than the Charge-Coupled Devices (CCD) that were the primary choice for imaging applications at earlier years. Moreover, due to the increased commercialization of digital cameras integrated in smartphones, the CIS market grows steadily over the years. As reported by Yole Development [START_REF] Developpement | Status of the CMOS Image Sensor Industry 2020[END_REF], the mobile market is the main driver occupying the 69.2% of the CIS Revenue which has increased from $15.5B in 2018 to $19.3B in 2019 (Fig. 5.1)

and is expected to reach $24B in 2023. Chapter 5 -Analysis of coupling effects in a 3DSI CMOS Image Sensor 132

This pixel architecture suffers from poor image quality, slow readout, and high KTC noise level resulting from the mismatch between the small pixel capacitance and the large vertical bus capacitance.

• Active Pixel Sensor (APS)

The Active Pixel Sensor (APS) [START_REF] Yadid-Pecht | A Random Access Photodiode Array for Intelligent Image Capture[END_REF] was a major improvement to the PPS architecture, adding to every pixel its own in-pixel amplifier. Consequently, the pixel is composed out of a photodiode (PD), a reset transistor (RST) and the source-follower (SF) amplifier as shown in Fig. 5.3. The current source of the source-follower is placed at the end of the column bus. The readout output of an APS is a voltage instead of charge transfer, resulting in a reduced power consumption, random access, and high-speed readout. On the contrary adding a transistor per pixel degrades the Fill-Factor.

Furthermore, while it solves a lot of noise issues, the kTC noise generated by the photodiode reset, still remained. [START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF].

Fig. 5.3 Active CMOS pixel based on an in-pixel amplifier

• Active Pixel Sensor with Pinned-Photodiode (4T-APS)

To solve the high reset noise issue of the APS architecture a PPD pixel was introduced [START_REF] Guidash | 0.6 μm CMOS pinned photodiode color imager technology[END_REF]. This is and a second after the transfer of the integrated charge from the photodiode to the SN. Adding to the above also the superior noise performance of the PPD [START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF], the 4T-APS is the preferred choice for CIS pixels nowadays.

➢ Pixel operation

The voltage output of a 3T-APS pixel is presented schematically in Fig. 5.5, where the operation sequence is indicated and consists in three stages:

1. Reset (reset transistor ON): The photodiode voltage is set to a reference voltage V ref .

2. Exposure (reset transistor OFF): Impinging photons decrease the reverse voltage across the photodiode during a fixed integration time (t int ).

Readout (RS and SF ON):

The output voltage level is sampled and further processed at the column.

Fig. 5.5 Operation of a 3T-APS pixel

Depending on the integration time, more or less charges are collected at a given time which in turn affects the sensitivity and DR of the sensor.

V out,px

High light Medium light Low light

Reset time

Exposure time V REF time

• Size & Fill Factor (FF)

One of the main advantages of using CMOS compatible technology is the reduction in size following the scaling law [START_REF] Dennard | Design of Ion-Implanted MOSFET's With Very Small Physical Dimensions[END_REF]. As shown in Fig. 5.6, due to the shrink of transistor gate length and development of advanced process node, the pixel size was reduced, and the power consumption lowered. Today, commercialized consumer electronics pixels are in the micron range. However, the CMOS process evolution could not be directly used in CIS. The high leakage at small dimension, and the dielectrics used in the BEOL, are some of the reasons that led to the development of a process specific to CIS. As can be observed from Fig. 5.6, there is a gap between the CIS process and the main stream CMOS process of about three generations [START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF] however the scaling rate is almost identical.

Also, using Front Side Illumination (FSI) configuration where the pixel is illuminated from the top through the metal layers, with the increase of pixel density the metallization design has become more difficult to deal with. The distance between metal lines is shortened and the light path focused by the micro-lenses might get reflected on the metal lines which causes crosstalk. Therefore, other solutions have been proposed such as integrating waveguides between the microlens and the photodiode to obtain better focus of the light [START_REF] Agranov | Pixel continues to shrink…. Pixel Development for Novel CMOS Image Sensors[END_REF], [134]. However, the best solution came as a natural evolution, consisting in Back Side Illuminated (BSI) sensor, where the light is incident on the back surface of the sensor after thinning it down.

Pixel metrics

The reduction in pixel size results in better spatial resolution at the expense of lower sensitivity. Also, the Signal to Noise ratio (SNR) will be lower due to smaller pixel area and thus less photon absorbed. Reducing the pixel size will also affect the Full Well Capacity (FWC) and thus the DR. All these parameters will be presented in the following sections.

Another important parameter related to the pixel size and scaling is the Fill Factor (FF). FF is defined as the ratio or percentage of photosensitive area to the total pixel area. It represents how much of the total pixel area is used to collect photons, or inversely the area that is shadowed by either transistors or metal lines. A high FF results in a higher sensitivity since more charges are collected by the pixel, therefore it should be maximized. Since the pixel transistors followed the scaling law, their dimensions were reduced which allowed the improvement of the FF. To overcome the reduced FF, micro-lenses are added to the pixel to focus the light on the photodiode area and reduce optical cross talk between pixels.

• Sensitivity & Quantum efficiency

The sensitivity of a linear response sensor such as the 3T/4T-APS, is defined as the slope of the transfer function in V/lux.s or e-/lux.s. It represents the potential change for a given light intensity and integration time. Therefore, it is highly dependent on the Quantum efficiency (QE) of the sensor.

The QE is what quantifies how efficiently the incident photons are collected and converted to electrons. It is wavelength dependent since it depends on the absorption of the photosensitive material, but also accounts for all the optical loses that might occur due to reflection, refraction, and absorption of the incident light before it reaches the photosensitive area. To maximize it, antireflecting coating are used, and the stack between the surface of the sensor and the photodiode is optimized to avoid reflections at the interfaces. Also, the reflections on the metal lines must be minimized when using FSI. For example, using micro-lens greatly improves the QE and thus the sensitivity of the sensor. Using BSI improves the QE by avoiding these reflections.

• Dynamic range

The dynamic range (DR) quantifies the range of light intensity detectable and measurable by the sensor. It is calculated as the ratio between the highest detectable signal (S max ) and the lowest one (S min ), which is essentially the noise floor. Therefore, it can be expressed as 𝐷𝑅 = 20 log 𝑆 𝑚𝑎𝑥 𝑆 𝑚𝑖𝑛

(5-1)

A high DR is desired to ensure image quality at the low and high end of the light intensity. The highest detectable signal is limited by the Full Well Capacity (FWC) and pixel saturation. A common linear pixel sensor exhibits a DR of about 60dB.

• Conversion gain

The conversion gain (CG), measured in V/e-, characterizes the charge-to-voltage conversion.

Hence, a high CG increases the sensitivity especially at low light. It is expressed as:

𝐶𝐺 = 𝛥𝑉 𝑜𝑢𝑡 𝑁 𝑒 (5-2)
where ΔV out is the pixel output (V out,int -V out,ref ) as a response to the number N e of electrons in a single packet. The latter depends on the quantum efficiency and the photon flux. Equation (5-2) can be also expressed as:

𝐶𝐺 = 𝑞 𝐶 𝑆𝑁 + 𝐶 𝑃 (5-3)
with C SN being the SN capacitance and C P is any additional patristic capacitance. Experimentally, the CG is measured by considering the photon shot noise and dividing it by the mean output signal of the pixel.

• Full well capacity

The Full Well Capacity (FWC) is a metric of the charge amount which can be detected before the sensor saturates, measured in number of charges, and determines the DR of the sensor. When the noise is not considered, the number of charges that the well can contain, can be roughly approximated by

𝐹𝑊𝐶 = 𝑞 • 𝐶 𝑃𝐷 • 𝑉 𝑃𝐷 (5-4)
where C PD is the photodiode capacitance, V PD the applied voltage across it and q the elementary charge. From (5-4) it is evident that increasing the capacitance increases the number of charges that can be collected. However, increasing the capacitance will also decrease the CG. The higher is the FWC the higher is the DR, however, the loss in sensitivity due to the reduction in CG will decrease the range at the low intensity end. This results in the well-known DR/sensitivity tradeoff. Also, with the reduction of pixel size, the capacitance of the photodiode is also reduced, which negatively affected the FWC.

• Signal-to-Noise Ratio (SNR)

It represents the ratio of the useful signal to the undesirable noise signals and essentially defines the image quality. Thus, it must be as high as possible, either by increasing sensitivity and CG, or by decreasing the noise floor. For the SNR evaluation, the main noise parameters in a pixel are explained in the following section.

Pixel noise parameters

The noise sources in an image sensor can be divided into the following categories:

• Temporal noise: this includes photon shot noise, dark current shot noise (Q shot ), amplifier flicker 1/f noise, and reset kTC noise (Q reset ).

• Spatial noise: mainly Fixed Pattern Noise (FPN) (QFPN) that includes Dark FPN, the FPN of the in-pixel SF and the column FPN.

• System noise: more related to readout (Q readout ), such as line noise and crosstalk, as well as ADC quantization noise.

The total pixel noise is the sum of the mentioned components and can be expressed as:

𝑄 𝑛 = 𝑄 𝑠ℎ𝑜𝑡 + 𝑄 𝑟𝑒𝑠𝑒𝑡 + 𝑄 𝑟𝑒𝑎𝑑𝑜𝑢𝑡 (5-5)
The FPN contribution (QFPN) is not included in (5-5) since it can easily be corrected using CDS techniques. As illustrated in Fig. 5.7, dark current noise is dominant at low illumination, while the shot noise, particularly the photon shot noise that increases with the signal, is dominant at higher light intensities. We will define in more details the major contributor to pixel noise in our case: dark current, reset kTC noise, and FPN.

Chapter 5 -Analysis of coupling effects in a 3DSI CMOS Image Sensor • Dark current noise Dark current noise is defined as the unwanted output signal when no light is present at the photodiode, hence it is result of a thermal generation process and not of a photo-generation one.

The major causes of dark current are the defects generated in the lattice during fabrication, that generate traps at the interfaces (Si/SiO2), the recombination due to drift in depletion region, and diffusion in the quasi-neutral regions of the diode. Dark current has always been a noise source difficult to deal with, since its underlying physics are not fully understood to date. It depends primarily on temperature variations due to its thermal SRH (Shockley-Read-Hall recombination) component.

To account for the dark current, pixels that are shielded from the incident light (dark pixels), are implemented to measure the dark current variation and apply a correction algorithm to the image. Another way to reduce the dark noise is to subtract a dark frame from the following frames.

This takes into account the dark signal dependence on integration time and gain, however not considering the temperature increase. The progress achieved by the contemporary process technologies and the development of different techniques to reduce it, enable the reduction of the dark signal component. The introduction of the PPD where the pinning layer passivated the interface states [START_REF] Teranishi | NO IMAGE LAG PHOTODIODE STRUCTURE IN THE INTERLINE CCD IMAGE SENSOR[END_REF], drastically improved the presence of dark current noise. Nowadays, it is possible using advanced nodes, to achieve dark current noise in the range of tens of pA/cm² for pixels smaller than 4μm [START_REF] Mcgrath | Dark Current Limiting Mechanisms in CMOS Image Sensors[END_REF]. This type of noise is the result of the thermal noise generated at the reset transistor that switches the capacitive node. Concerning the 4T-APS, this node is the SN. As explained in Chapter 2, the voltage noise that a resistive element generates is defined as:

𝑣 𝑅,𝑛 = √4 • 𝑘 • 𝑇 • 𝑅 • 𝛥𝐹 (5-6)
where R the resistance in Ohms, k is the Boltzmann constant, T the temperature in Kelvin and ΔF is the noise bandwidth Considering the equivalent circuit of Fig. 5.8, it consists a low-pass filter with cut-off frequency

𝑓 𝑐 = 1 2𝜋𝑅𝐶
(5 -7) and transfer function given by

𝐻(𝜔) = 1 1 + 𝑗𝜔𝑅𝐶 (5-8)
Consequently, the total noise voltage generated across the capacitor will be

𝑣 𝐶,𝑛 2 = ∫ 4𝑘𝑅𝑇 • ∞ 0 |𝐻(𝜔)| 2 𝑑𝜔 = 4𝑘𝑅𝑇 • 𝜋 2 • 1 2𝜋𝑅𝐶 = 𝑘𝑇 𝐶 (5-9)
with C being the integration node capacitance. It can also be measured as an amount of charge in Coulomb as:

𝑄 𝐶,𝑛 = √𝑘𝑇𝐶 (5-10)
It is evident that kTC noise decreases with temperature. To reduce 𝑄 𝐶,𝑛 , the capacitance must be reduced (opposite for 𝑣 𝐶,𝑛 ). However, the CG increases by reducing the capacitance. Besides that, a lower capacitance value increases the necessary supply voltage, so it is eventually a tradeoff. In the

• Reset or kTC noise R MOSFET C ideal switch v R,n noise voltage v C
4T-APS the reset noise can be almost completely canceled with the introduction of the PPD and the use of CDS.

• Fixed Pattern Noise (FPN)

The fixed pattern noise is a spatial noise resulting from the mismatch between pixel parameters due to process variations. It results either in a gain or offset variation. For a standard APS circuit, it can be divided as:

1. Pixel FPN, which includes FPN due to photodetector variation (eg. area, C PD , etc.), and the amplifier variation (V TH , W/L ratio, etc.)

2. Column FPN resulting from column current bias variations.

The offset FPN can be evaluated by measuring the variance of the output voltage under uniform illumination condition (including dark) without taking into consideration the temporal noise and is not signal dependent. On the other hand, the gain increases with the signal since it is defined by the variance of the pixel gain multiplied by its photo response. FPN is given in a percentage of the output voltage swing or a percentage of the full well capacity. The gain FPN which includes DSNU (dark signal non-uniformity) and PRNU (pixel response non-uniformity) is more complex to address than the offset FPN. The offset FPN can easily be removed using CDS techniques, while the gain FPN can be limited by using process integration techniques to reduce its dominant sources, such as dark current.

Process integration optimization

• Back-Side Illumination (BSI)

The BSI integration scheme consists in flipping the sensor so that the light will be incident directly on the photodiode without going through the BEOL of the pixel. The process was initially developed in the 70's, intended to specific application that required higher QE such as astronomy imaging. It became mainstream for high-end consumer applications, as the pixel size decreased below 2μm, resulting from the mobile phone market demand where higher resolution at the same sensor size is required [START_REF] Iwabuchi | A back-illuminated high-sensitivity small-pixel color CMOS image sensor with flexible layout of metal wiring[END_REF]- [START_REF] Wuu | BSI Technology with Bulk Si Wafer[END_REF]. When Front-Side Illumination is used, the optical path will include the total thickness of the BEOL. The reflection on the metal lines induced losses and crosstalk between pixels. The optimization of the FSI BEOL techniques [START_REF] Cohen | Fully optimized Cu based process with dedicated cavity etch for 1.75μm and 1.45μm pixel pitch CMOS Image Sensors[END_REF] were no longer enough to adjust to the scaling of the CMOS technology and reduction in pixel pitch, making the distance between metal lines shorter and shorter. Therefore, BSI came as a natural solution to increase the QE, but also to allow the use of more advanced standard BEOL technologies. The industries developed foundry compatible processes, and thanks initially to the contribution of Sony and Omnivision, this

technology is now mainstream. The first to implement BSI in mobile phone cameras were OmniVision in 2007 [START_REF] Rhodes | The Mass Production of BSI CMOS Image Sensors[END_REF]. Nowadays, more than half of the mobile phone market utilize BSI integration [START_REF] Developpement | Status of the CMOS Image Sensor Industry 2020[END_REF].

• Three-dimensional integration

Within the More-Than-Moore context, 3D CIS enable the possibility of smarter and more advanced sensors through the co-integration of different blocks (Analog, Digital, RF) in various tiers.

Today industry has shifted to the 3D stack process integration which allows the integration of the CMOS processing part on top of the pixel enabling the possibility of using more advanced technology nodes for the processing circuit. Since 2010, the trend is the combination of BSI and 3D stack to reach ultimate performance maintaining a small pixel size. Therefore, combined with BSI, it allows the addition of more functionalities without degrading the fill factor.

Nowadays heterogeneous integration of different processing blocks is the main target for a 3D stacked CIS. In 2017, Sony announced their 3-level 3D stack image sensor [START_REF] Haruta | A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM[END_REF] composed of the back illuminated pixel array, a DRAM level, and the digital processing level. The proximity of the DRAM allows fast processing and fast frame rate. Millet et al. [START_REF] Millet | A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing[END_REF] recently presented a vision chip in a 3D stacked BSI implementation with an in-focal-plane matrix parallel communication, exhibiting a frame rate of 5500 frames/s and demonstrates heterogeneous processing features on captured images.

Although 3D stacking technologies have been predominantly used for 3D CIS nowadays, constraints of traditional 3D stacking alignment capabilities forbid the more aggressive pixel miniaturization required for future generations of CIS [START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF], [START_REF] Coudrain | Investigation of a sequential three-dimensional process for backilluminated CMOS image sensors with miniaturized pixels[END_REF]. This drawback can be overcome by using 3DSI which is the leading pathway for pixel partitioning with pitch in the sub-μm range. Another great opportunity that 3DSI offers is the outstanding high-density of the 3D contacts between the tiers (up to 10 8 3D via/mm 2 ) which enables the partitioning of different processing blocks with high connectivity and low latency (Fig. 5.9). Taking that into consideration, 3DSI offers not only the possibility to integrate dense logic and memory layers but also heterogeneous technologies like MEMS/NEMS for tight coupling of sensing and computing [START_REF] Vivet | Advanced 3D Technologies and Architectures for 3D Smart Image Sensors[END_REF].

Chapter 5 -Analysis of coupling effects in a 3DSI CMOS Image Sensor While offering great opportunities in the CIS domain, 3DSI deals with many challenges at the moment. As already mentioned in the previous chapters, the major challenge for the sequential processing is the limited TB for the fabrication of the stacked devices. To date, LT devices have been successfully processed for LV [START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF] as well as HV [START_REF] Cavalcante | Low temperature high voltage analog devices in a 3D sequential integration[END_REF] applications. The feasibility of Back-Illuminated CIS with miniaturized pixels realized in 3DSI has been investigated in the work of Coudrain et al. [START_REF] Coudrain | Contribution au développement d'une technologie d'intégration tridimensionnelle pour les capteurs d'images CMOS à pixels actifs[END_REF] in which the 3D partitioning of the CIS at the pixel level led to an increase of the photodiode area by 44% for a 1.4μm pitch.

Inter-tier Coupling at Device Level

As studied in the previous chapters, the electrical coupling between the sequential tiers due to the ILD that acts as a BG oxide for the top stacked devices is of great concern in 3DSI. Consequently, if no inter-tier GP is introduced, the top devices are asymmetrical SOI MOSFETs, sensitive to the bottom tier electrode voltage variations.

The scope of this section is to analyze the immunity of HV analog devices with V DD =2.5V in the top tier when the bottom tier electrode voltage variations can go up to V DD =2.5V, for a BSI 3D pixel.

With the aid of TCAD simulations, a comparison against the impact of temperature variation on the top-tier stacked devices will be used to draw conclusion on the necessity to introduce an inter-tier GP.

Simulation Setup

For the TCAD simulation setup we consider the cross-section illustrated in

Impact on electrical parameters

The TG placed at the bottom tier toggles from 0V to V DD and vice versa. This voltage node is coupled via a capacitive path to the exposed top device channel resulting in a shift of the I D -V G characteristics, as seen in Fig. 5.11 (a). This is a non-linear effect that becomes more evident in the sub-threshold region and slightly decreases to a fixed value when the device operates in strong inversion [START_REF] Amara | Planar Double-Gate Transistor[END_REF]. b.

Extracting the threshold voltage shift induced by the TG voltage bias sweep from -2.5V to 2.5V (Fig.

(b)

), the charge-coupling factor was obtained, 35mV/V for NMOS and 42mV/V for PMOS.

To assess the impact of the TG coupling on the top tier device, we chose to compare it against the temperature dependence of the device electrical characteristics. Unlike the capacitive coupling, the effect of temperature has a complex behavior depending on the gate voltage V G . As seen in Fig. 5.12 (b), increasing the temperature of the device from 253 K to 353 K (-20 °C to 80 °C) -extended temperature range in commercial electronics -we observe an increase of the subthreshold conduction current as well as a decrease of the saturation current while there is a gate voltage around threshold for which the drain current remains constant. This behavior is attributed to the increase in carrier concentration with temperature for low gate bias, as opposed to the decrease in carrier mobility for high gate bias [START_REF] Groeseneken | Temperature Dependence of Threshold Voltage in Thin-Film SOI MOSFET's[END_REF]. At a specific V G these two mechanisms are counterbalanced resulting in a Zero Temperature Coefficient (ZTC) point. parameter is the leakage current I OFF which is shifted significantly with the TG coupling. The latter can be critical for memory blocks placed at the top-tier above the TG. The CG evaluates the efficiency of this mechanism and for a 4T-APS is given by [START_REF] Fowler | Single Photon CMOS Imaging Through Noise Minimization[END_REF],

𝐶𝐺 = 𝑞𝐺 𝑆𝐹 𝐶 𝑆𝑁 + 𝐶 𝐺𝐷 + (1 -𝐺 𝑆𝐹 )𝐶 𝐺𝑆 (5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF] where q is the elementary charge, G SF is the SF gain, C SN is the sum of parasitic capacitances at the SN node and C GS , C GD are the gate to source and gate to drain capacitances of the SF.

The gain G SF of the SF is expressed as:

𝐺 𝑆𝐹 = 𝑔 𝑚,𝑆𝐹 𝑔 𝑚𝑠,𝑆𝐹 = 1 𝑛 (5-12)
where g m,SF and g ms,SF is the gate and source transconductance respectively and n is the body factor of the SF. In the case where the BG of the SF can be tied to the source then the gain is approximately equal to unity, otherwise it is process-depended and is given as n=1+r, where r is the charge-coupling factor of the top-tier SOI. As the ILD thickness is increased, n approaches unity. In our case, for the r values extracted previously, the gain G SF of the NMOS device is 0.97 and for a PMOS one is 0.96.

The cutoff frequency of the SF is given by [START_REF] Fowler | Single Photon CMOS Imaging Through Noise Minimization[END_REF]:

𝑓 𝑐 = 𝑔 𝑚,𝑆𝐹 2𝜋 • 𝐶 𝑜𝑢𝑡,𝑆𝐹 • 𝐺 𝑆𝐹 • (𝐶 𝑆𝑁 + 𝐶 𝐺𝐷 + 𝐶 𝐺𝑆 )
( [5][START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF] where C out , SF is the capacitance seen at the source of the SF, that is the column-level capacitance if there is no other stage in between. Parasitic extraction was performed concerning a single-tier (2D) and a two-tier layout (3D) implementation of our pixel as illustrated in Fig. 5.16, to evaluate the impact of the latter on CG and f c . The parasitic capacitances contributing to C SN , C GD , C GS , C out,SF and also the CG are presented in Table 5.1. As evaluated, the sum of C SN and C GD as well as C GS are slightly enhanced by 48aF and 44aF

respectively. An even smaller increase of 10aF for the column-level capacitance is obtained. This shows a negligible difference in the conversion gain and the AC response of the 3D pixel (yielding in a ΔCG of 0.377μV/e-and a Δf c of 0.244Hz) compared to the one processed in planar SOI technology as long as the BOX (equivalently the ILD in 3DSI) thickness is the same. The low 3D impact on the CG also implies that noise performance will not be deteriorated.

Impact of TG coupling on pixel electrical parameters

Fig. 5.17 shows the voltage at the output of the in-pixel SF transistor versus the number of photo generated electrons at the SN for the voltage bias limits of the bottom tier TG (0V-2.5V). The CG is the slope of the latter and is not altered with the TG coupling. The constant vertical shift can be considered as an offset that can be easily corrected during the read-out process. Fig. 5.17 Output voltage of the in-pixel SF transistor versus the number of photo generated electrons at the SN for the voltage bias limits of the bottom tier TG (0V-2.5V). The slope gives the CG that is not altered with the TG coupling.

To evaluate the impact of the TG coupling on the pixel readout operation, we simulated a readout cycle as the one shown in Fig. 5.15 (b). We examined two cases, one where the SF is placed at the top-tier above a TG which belongs to the same pixel as in Fig. 5.18 (a), and one for which the SF is placed above a TG of an adjacent pixel, illustrated in Fig. 5.18 (b). In the first case the TG switches ON during the transfer of e -from the PPD to the SN and the sampling is thus performed at t1, t2 without resulting in a readout error. In the second case, where the TG switching is not synchronized with the top-tier SF device, the sampling value may be compromised due to the TG switched ON. To assess the strength of this error we compared it with the readout error caused by temperature variation (253 K -353 K), with the impact of the latter shown in Fig. 5.19(b). As observed, the temperature effect is in the same order of magnitude and for a low SF bias current it can even be worse than the coupling effect. However, because it remains constant with the light intensity it is easier to compensate for it later in the circuit.

Inter-tier GP necessity

The decoupling efficiency of an inter-tier GP between sensitive tiers in 3DSI has been thoroughly examined in §4.2.2, where it has been shown to reduce the vertical static coupling by five orders of magnitude. The necessity for an inter-tier GP integration results from the specifications targeted for each application and is eventually a trade-off between the process complexity and the inter-tier coupling sensitivity.

Fortunately, in a typical rolling readout, each row of a pixel array is enabled sequentially, so there is no overlapping of timing diagrams for adjacent pixels. Consequently, there is no probability of a readout error due to TG coupling. Moreover, the Correlated Double Sampling (CDS) stage that exists commonly after the readout circuit, eliminates possible readout errors. This means that even with no intermediate isolating Ground Plane, the 3DSI CIS readout is immune to inter-tier coupling effects. However, if additional blocks are intended to be placed above the photodiode area, like in- pixel frame memory, where the leakage current is a significant parameter, then an inter-tier GP is mandatory.

Conclusion

A simulation study of coupling-induced effects in a PMOS pixel realized in 3DSI has been presented. At a device level it is shown that the impact of the TG coupling can result in an alteration of the electrical parameters as significant as the one resulting from a temperature variation of 100 degrees, especially for switch transistors for which leakage is a critical parameter. Regarding the inpixel SF transistor at circuit level, it was shown that there is negligible impact on the conversion gain and the AC performance due to the 3DSI compared to a planar one. Furthermore, the SF-TG coupling can result in a readout error only when the SF is placed above a TG of an adjacent pixel, therefore not synchronized with the pixel readout. However, in a typical rolling readout this is not possible due to the sequential pixel activation. Moreover, possible readout errors are eliminated if a CDS stage in included after the readout circuit. Consequently, we demonstrated that despite the strong electrical coupling and consequently high ΔV TH (~100mV) for top-tier devices, there is an inherent readout error immunity of a sequentially integrated 3D CIS.

152

PARASITIC EXTRACTION AND MODELING OF COUPLING EFFECTS IN 3DSI

In this chapter, the results of parasitic extraction on 3DSI structures comprised of stacked devices is presented. In detail, the coupling capacitances that are formed between different electrodes are analyzed. Since the precision of TCAD simulations has been validated against experimental results in Chapter 3, the present analysis has been conducted solely with the aid of TCAD tools. In addition, a comprehensive modeling approach of inter-tier coupling effects between active devices in 3DSI is presented. Our modeling approach predicts accurately the impact of layout effects on the inter-tier capacitive coupling between active devices concerning a wide range of geometries along with several top/bottom device configurations. Consequently, it can help facilitate the analysis of complex and large-scale monolithic 3D circuits with SPICE tools and merge the gap between pre-and post-layout simulations.

Parasitic extraction of lumped coupling elements in 3DSI

Prior to modeling the coupling effects between active devices in 3DSI, one must identify victim-aggressor pairs. Each device is considered as a black box with its terminals (D, G, S, B) exposed.

As a consequence, for the coupling elements extraction between two stacked devices (Fig. 6.1 (a)), the intrinsic capacitances of each device (Fig. 6.1 (b)) shall be neglected.

From the previous chapters it has been proven that quasi-static methods are valid for the analysis of the inter-tier coupling effects between active devices. Additionally, the validity of TCAD simulations in the high-frequency domain has been confirmed against full-wave simulations by HFSS.

As a result, the parasitic extraction at the device level will be accomplished in this chapter with the use of TCAD (Silvaco ATLAS) and quasi-static field solver (Silvaco CLEVER). Although in the conventional parasitic extraction schemes, TCAD is used for the FEOL evaluation (device trans-capacitances including semiconductor material, not dependent on layout)

and field solvers for the BEOL (from contact to top back-end level, layout dependent metal/insulator capacitances), here the line between the two is blurred. For that reason, both tools will be used in conjunction. The parasitic elements model the transfer of energy between the devices and can be divided in:

• Capacitors for the capacitive coupling modeling

• Mutual inductances for the inductive coupling modeling Since in §3. 3.1.a it has been proven that inductive coupling can be considered negligible in monolithic 3D circuits, the extraction and modeling of mutual inductances will be excluded from our analysis.

Definition of coupling capacitances in 3DSI

Α 3D illustration of two stacked devices in 3DSI is presented in Fig. 6.2(a), where the coupling capacitances between the electrodes of the two devices are highlighted. For the simplicity of the analysis, the symmetry of the structure has been exploited (source/drain electrodes can be used interchangeably), hence the coupling capacitances can be defined as seen in the schematic crosssection of Fig. The coupling capacitances between the electrodes of the stacked devices can be analyzed as follows:

• C dbdt /C sbst : This capacitance can be considered as a bias independent parallel plate capacitance between the bottom-tier drain to the top-tier drain electrode. It is related to the drain diffusion length but not the gate length. • C gbgt : This is also a parallel plate capacitance between the bottom-tier gate to the top-tier gate electrode, but it varies with the top-tier gate voltage. It dominates over the others since it is gate area depended, thus it further increases for long devices. As observed from Fig. 6.3, this capacitance has a fixed value below threshold, while above V TH it is screened by the inversion charge formed in the top-tier channel.

• C gbdt /C gbst : This is the most critical coupling capacitance since it is responsible for the backgate effect of the top-tier device. In the absence of the inversion charge within the top-tier device channel, the capacitance has a minimum value C gbdt_0 /C gbst_0 ) due to the fringing electric field between the bottom-tier gate and the top-tier source/drain. For V Gtop >V TH , the formed inversion channel maximizes the capacitance value (C gbdt,max /C gbst,max ) so that we can define the effective oxide capacitance as: 𝐶 𝐼𝐿𝐷,𝑒𝑓𝑓 = (𝐶 𝑔𝑏𝑑𝑡,𝑚𝑎𝑥 -𝐶 𝑔𝑏𝑑𝑡,𝑚𝑖𝑛 ) + (𝐶 𝑔𝑏𝑠𝑡,𝑚𝑎𝑥 -𝐶 𝑔𝑏𝑠𝑡,𝑚𝑖𝑛 ) (6-1)

• C dbgt /C sbgt : The fringing fields created by the bottom-tier drain/source electrodes reach the top-tier device gate electrode through its depleted channel forming C dbgt /C sbgt respectively for V Gtop >V TH . However, above threshold these fringing fields are screened by the inversion channel, thus this capacitance is limited.

• Lastly, there is an additional capacitance C dbst /C sbdt not shown in Fig. 6.3. This capacitance forms between the bottom-tier drain and top-tier source electrode and is extremely small since it is screened by the electric field of the adjacent electrodes. Moreover, it depends on the diagonal of the structure (Fig. 6.4 (a)) and thus proportional to

≈ √𝐿 𝐺 2 + 𝑡 𝐼𝐿𝐷 2
, so that it is even more limited when the gate length increases. TCAD simulations reveal the variation of C dbst /C sbdt with the top-tier device gate voltage and the results are shown in Fig. 6.4 (b).

To further analyze the C gbdt /C gbst capacitance of the top-tier device, Fig. 6.5 shows the potential contour plot of the stacked devices when the gate of the bottom-tier device is at V DD =1V.

The OFF-state (V Gtop = 0V) and the ON-state (V Gtop = V DD ) of the top-tier device are demonstrated in Ultimately, for the rest of the coupling capacitances there is no major difference. It is worth mentioning that this 3D layout configuration represents just a critical case study where the impact of 3D contacts can be examined, however it is not restrictive and a designer can in fact exploit a variety of possible configurations. Over and above, this layout configuration can provide the minimum form factor of the stacked structure as the distance of 3D contacts to the gate of the top-tier device (depicted in Fig. 6.7 (c) as 3DCO-PC) has the minimum value allowed by the technology. The latter is defined by 65nm-node design rules for the structures analyzed in this work.

The analysis can be carried out by splitting each capacitance into different components, based on the layout layer levels (RX, POLY, CT, 3DCO), as follows:

• Parasitic extraction was performed on the structure of Fig. 6.12, which contains the stacked devices in the layout configuration analyzed above with both devices in cutoff mode.

L G W G
The results of the parasitic extraction are shown in Fig. 6.13 (a) in which the gate length of both devices was varied with constant gate width (W G =1μm), whereas in Fig. 6.13 (b) the gate width was varied under a constant gate length (L G =1μm). Then, each capacitance component was obtained adding a thin 0 permittivity layer between the source/drain diffusion area and the 3D contact as Fig. 6.14 shows. By this method the electric field shaping of each component is not disturbed and the extraction is accurate.

As Fig. 6. [START_REF] Akiyama | MULTILAYER CMOS DEVICE FABRICATED ON LASER RECRYSTALLIZED SILICON ISLANDS[END_REF] The coupling capacitances also depend on the distance between the 3D contact on the bottom-tier active and the top-tier device gate (3DCO-PC) as Fig. 6.16 (a.) illustrates. The minimum value of this distance follows the highest density allowed in each technology node, thus moving from a 65nm-to 28nm-node the density increases. These two capacitances can be further analyzed by estimating the contribution of the 3D contacts to each total capacitance. For that reason, the previous extraction was repeated following the methodology described previously for the capacitance decomposition. As Fig. 6.17 (a) shows, decreasing the distance between the 3D contact and the gate of the top-tier device, the contribution of 3D contacts to C dbdt /C sbst increases reaching 38% for 28nm-node. Accordingly, the same is true for C dbgt /C sbgt (Fig. 6.17 (b)) however in that case the 3D contact capacitance component essentially accounts for the total capacitance value. center towards the interface, in the subthreshold region. For SOI MOS transistors with an ultra-thin silicon film (<10nm) the charge centroid is further confined at the center of the silicon film [START_REF] Fossum | Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs[END_REF], [START_REF] Rudenko | Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs[END_REF],

due to the Quantum Mechanical (QM) effects.

In this section, an efficient way of modeling the inter-tier coupling between active devices is suggested, considering the impact of both inter-tier static and dynamic coupling on the performance of victim top-tier digital devices (EOT=1.12nm, t si =1nm, t BOX =130nm). To accomplish this, both static and dynamic coupling effects are modeled through capacitance networks formed between the active devices and in particular to the BOX capacitance of the stacked devices.

This work is therefore organized as follows: in the first part, a first order approximation of the charge-coupling factor expression between the front and back interfaces of the stacked device is derived for low V Dtop (uniform channel). Then, the effective oxide and ILD capacitance (C ox,eff and C ILD,eff respectively) for the stacked device are extracted from TCAD simulations for a wide range of top/bottom device geometries and positioning combinations. Afterwards, the capacitances are modeled with the aid of electrical field decomposition, considering an effective front and back gate area. The resulting capacitance models are inserted to the charge-coupling factor model which is later compared to the extracted values from I D -V G TCAD simulations.

Charge-coupling factor expression for long-channel top-tier devices

The behavior of the charge-coupling factor in SOI devices as predicted by the classic Lim-

Fossum model [START_REF] Lim | Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's[END_REF] has been reviewed in §2.2.3, however it is observed that in UTBB (Ultra-Thin Body and Buried oxide) architectures with t si <20nm, it differs significantly [START_REF] Rudenko | Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs[END_REF], [START_REF] Ohata | Coupling effect between the front and back interfaces in thin SOI MOSFETs[END_REF]- [START_REF] Eminente | Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects[END_REF]. Among these deviations are the increased slope and the absence of saturation in the experimentally measured coupling curves.

Advanced models [START_REF] Trivedi | Scaling fully depleted SOI CMOS[END_REF], have corrected this error by taking into account the fact that an inversion charge can appear at the back interface when a strong Forward Back Bias (FBB) is applied.

In particular, the BG bias V G,b modulates the position of the inversion charge conduction path, i.e. the charge centroid. Fig. 6.18 presents qualitatively the threshold voltage versus back-gate voltage diagram for UTBB SOI devices, assuming the critical cases where the conduction channel is formed either at the front or at the back interface for a reverse or FBB, respectively. Obviously, the transition between these two regions is not abrupt and the charge centroid moves progressively across the channel thickness towards the front/back interface under a reverse/forward BG bias respectively. The work of [START_REF] Fasarakis | Analytical modeling of threshold voltage and interface ideality factor of nanoscale ultrathin body and buried oxide SOI MOSFETs with back gate control[END_REF], [START_REF] Poiroux | Leti-UTSOI2.1: A compact model for UTBB-FDSOI technologies -Part II: DC and AC model description[END_REF] exploits the above-mentioned behavior, capturing effectively the back-bias influence on the I-V characteristics of UTBB SOI devices.

Indeed, these models can accurately provide the charge centroid position by using relatively complex analytical expressions. A simpler expression for the charge centroid has been presented in [START_REF] Hiblot | Compact model of short-channel effects for FDSOI devices including the influence of back-bias and fringing fields for Si and III-V technology[END_REF], to model the SCE in FDSOI devices. However, a common characteristic of all these models is the need for an accurate calculation of the surface potential φ s or the localized surface charge Q iy .

To examine the influence of the back-bias on the charge centroid of stacked FDSOI devices in 3DSI, Fig. previously. However, one can easily observe that for a back-gate bias in the range of -2.5V to 2.5V, the position of the charge centroid remains relatively close to the center of the channel (3.5 nm) with a slight deviation. That being so, the equivalent oxide capacitance becomes

𝐶 𝑜𝑥,𝑒𝑞 = ( 1 𝐶 𝑜𝑥 + 1 𝐶 𝑐ℎ ) -1 (6-5)
whereas the equivalent silicon film capacitance can be considered as [START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF] Inserting the calculated charge centroid position (Fig. 6.20) into the above simplified generic expression for the charge-coupling factor, the threshold voltage shift ΔV TH of the top-tier device can be obtained as a function of the bottom-tier device gate bias. The results are plotted in Fig. 6.23, along with the TCAD data extracted from the CC and max(dC gc /d Vg ) methods previously. As expected, (6-7) captures efficiently the sensitivity of the top-tier device threshold voltage to the bottom-tier device gate bias variation.

𝐶 𝑠𝑖,𝑒𝑞 = ( 1 𝐶 𝑠𝑖 - 1 𝐶 𝑐ℎ ) -1 (
The aforementioned analysis enables two useful assumptions for the charge-coupling expression to be used in our modeling approach. First, the charge centroid position can be considered unaffected of the bottom-tier device gate bias due to the relatively thick ILD. Indeed, assuming that the range of the bottom-tier device gate bias is limited to the power supply voltage (V DD ), the maximum value of the latter can be as high as 2.5V for bottom-tier analog devices. The aforementioned analysis enables two useful assumptions for the charge-coupling expression to be used in our modeling approach. First, the charge centroid position can be considered unaffected of the bottom-tier device gate bias due to the relatively thick ILD. Indeed, assuming that the range of the bottom-tier device gate bias is limited to the power supply voltage (V DD ), the maximum value of the latter can be as high as 2.5V for bottom-tier analog devices.

Furthermore, a second simplification can be made by placing the charge centroid at the center of the channel. Having that in mind, the distance of the charge centroid position from the front interface t ch is now t si /2, thus (6-7) becomes

𝑟 = 𝑑𝑉 𝑡ℎ,𝑡𝑜𝑝 𝑑𝑉 𝐺𝑏𝑜𝑡 = - 𝐶 𝑏𝑜𝑥 (2𝐶 𝑠𝑖 + 𝐶 𝑜𝑥 ) 𝐶 𝑜𝑥 (2𝐶 𝑠𝑖 + 𝐶 𝑏𝑜𝑥 ) (6-8)
Fig. 6.24 shows the comparison between (6-7) (varying centroid position) and (6-8) (fixed centroid position), along with the TCAD data obtained with CC and max(dC gc /d Vg ) methods. As observed, within the power supply range of bottom-tier devices, the simplifications adopted for the charge-coupling factor expression yield only a minor error (<4%) for the negative edge of V Gbot , which is actually unrealistic, since the bottom-tier device gate shall always vary between 0 and 2.5V

(maximum V Gbot in the case of analog bottom-tier devices with V DD =2.5V) regardless the MOSFET polarity.

6.1.1.a Impact of bottom/top length ratio with regard to scaling

The expression (6-8) derived for the charge-coupling factor in the previous section is valid for long-channel top-tier devices that have their back-gate being the bottom-tier device gate electrode.

However, this is an ideal case and in reality the charge-coupling factor value can deviate from the calculated one as shown in Chapter 3, due to the impact of SCE and the relative misalignment.

To describe the dependency of the top/bottom length ratio vs with regard to L Gtop scaling, the effective ILD capacitance (C ILD,eff ) was extracted from TCAD simulations and an effective length for the bottom-tier device gate electrode was associated, as if C ILD,eff was an equivalent parallel plate capacitance with value

𝐶 𝐼𝐿𝐷,𝑒𝑓𝑓 = 𝜀 𝑜𝑥 𝑡 𝐼𝐿𝐷 𝑊 𝐺 𝐿 𝐺𝑏𝑜𝑡,𝑒𝑓𝑓 (6-9)
Beginning with a long-channel top-tier device of L Gtop =30μm (no impact of SCE), Fig. 6.25 (a)

shows the corresponding L Gbot,eff values plotted versus the designed gate length of the bottom-tier devices. As expected, when the bottom-tier device gate length is equal or greater than the length of the top-tier device channel (L Gtop ), the effective bottom-tier device gate length L Gbot,eff is fixed to the value of L Gtop and represents the upper limit. On the contrary, the lower limit of L Gbot,eff is imposed by the fringing electric fields when L Gbot << L Gtop . For instance, a top-tier device with gate length 30μm stacked on top of a bottom-tier device with gate length 30nm, experiences an effective back-gate length L Gbot,eff = 150nm.

Moving on to top-tier devices with sub-micrometer gate length, Fig. 6.25 (b) shows their effective back-gate length L Gbot,eff versus the actual gate length of the respective bottom-tier device.

While the L Gbot,eff versus L Gbot trend seems similar to the long channel top-tier devices, as L Gtop scales down, the bottom-tier device gate length for which L Gbot,eff = L Gbot , becomes greater. As a consequence, a top-tier device with gate length 30nm will experience the maximum effective backgate length when the bottom-tier device is equal or greater than 500nm. On the other hand, the lower limit (L Gbot << L Gtop ) of the top-tier device effective back-gate length, is again determined by the fringing fields of the bottom, which are however dramatically limited due to the charge sharing effect of the bottom-tier device gate electrode with the top device diffusion regions of D top , S top . This effect of the bottom-tier gate electrode length variation can be visualized qualitatively in Fig. 6.26, where it is illustrated schematically. For L Gtop > L Gbot the effective bottom-tier gate length is always larger than the actual value due to fringing electric fields. When L Gbot increases, L Gbot,eff is always smaller and there is a critical length where L Gbot,eff saturates. The latter is equal to L Gtop for long channel devices, yet for sub-micrometer devices it is much greater than L Gtop . The behavior described above is further enhanced due to the presence of the source and drain diffusion areas of the bottom device. Indeed, Fig. 6.27 (a) shows the electric field vector plot generated in TCAD for a structure where the bottom device is a regular SOI MOSFET and Fig. the first case due to the high electric field created by the bottom device source and drain diffusion areas. The slight deviation from the designed gate length of the top-tier device in Fig. 6.30, attributed to SCE, is responsible for the increase in the charge-coupling factor when L Gbot >>L Gtop , observed in Fig. 3 For the calculation of the fringe capacitance, analytic expressions can be utilized from prior modeling approaches in CMOS devices [START_REF] Bansal | Modeling and optimization of fringe capacitance of nanoscale DGMOS devices[END_REF]- [START_REF] Hiblot | Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR[END_REF]. These models define as a fringe capacitance the electric field lines between two perpendicular electrodes separated by an insulator. As opposed to a parallel-plate capacitance, the electric field lines of a fringe capacitance are not linear but elliptical.

C ov C f C f G top G bot S bot D bot t si C ov C' f C' f G bot t si G top a.
b.

Potential (V) 1 0 Potential (V) 1 0
The majority of the existing models use conformal mapping to perform an accurate fringe modeling.

The exact formulations of this transformation are beyond the scope of this work and thus can be excluded.

Lacord et al. [START_REF] Lacord | Comprehensive and accurate parasitic capacitance models for two-and three-dimensional CMOS device structures[END_REF] suggested in his model (which will be referred as [ Lacord 12] henceforth) two expressions for the evaluation of the fringe capacitance between two perpendicular conductors C1 and C2, as Fig. 6.33 shows. Considering that the two conductors are separated by dielectric (e.g., SiO 2 ), the capacitance due to elliptical electric field lines is given by -14) whereas the capacitance due to the region x < x1 and y < y1 (gray area in Fig. 6.33) where electric field lines are neither elliptical nor regular, the model suggests the equation

𝐶 𝑓,1 = 2𝑊 𝐺 𝜀 𝑜𝑥 𝜋 [sinh -1 (√ √𝑥 1 2 + 𝑚𝑖𝑛(𝑦 2 , 𝑥 2 ) 2 + 2 • 𝑦 1 𝑚𝑖𝑛(𝑦 2 , 𝑥 2 ) √|𝑥 1 2 -𝑦 1 2 | ) -sinh -1 ( √ 𝑥 1 √|𝑥 1 2 -𝑦 1 2 | )] (6
𝐶 𝑓,2 = 0.35 • 𝑊 𝐺 𝜀 𝑜𝑥 2𝜋 𝑙𝑛 ( 𝜋 • 𝑊 𝐺 𝑡 𝐼𝐿𝐷 ) (6-15)
Therefore, the total fringe capacitance is the sum of (6-14) and (6-15)

𝐶 𝑓 = 𝐶 𝑓,1 + 𝐶 𝑓,2 (6-16)

y 1 y 2 x 1 x 2
Electric field lines C1

In our case the dimensions in [START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF][START_REF] Kawamura | Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization[END_REF] and (6-15) must be replaced by the ones presented schematically in Fig. 6.34, so that x 1 =0, x 2 ≈L Gtop /2 (since L Gbot << L Gtop ), y 1 =t ILD and y 2 =H G (height of the bottom-tier gate electrode).

Under the above modeling approach, respectively substituting the values of x 1 , x 2 , y 1 , y 2 in [START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF][START_REF] Kawamura | Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization[END_REF] The model can be compared to the accurate value of C f in our structures, which can be extracted from TCAD simulations in the case where the bottom-tier device gate length L Gbot is significantly smaller than the top-tier device gate length L Gtop . For that purpose, a ratio of L Gbot L Gtop = 0.001 was selected, so that C f dominates over C ov . In order to estimate the impact of the bottom-tier S/D regions, on the fringe capacitance component, the setup was repeated excluding them.

The calculated value of the total fringe capacitance from the model of [Lacord 12] and the one obtained from TCAD simulations (labeled w/ bottom S/D) are presented in the diagram of Fig.

6.35.

As shown, the extracted value from simulations appears to be smaller, approximately half the value of the one calculated from the analytical equations. Apparently, this reduction is an outcome of the charge sharing effect in the presence of multiple electrodes on both sides of the bottom-tier gate electrode (S bot , D bot ) [START_REF] Zhao | Field-based capacitance modeling for sub-65-nm on-chip interconnect[END_REF].

D bot G b D top G b G bot G top ~Lgtop /2 t ILD H G

Fig. 6.35 Fringe capacitance component of C ILD,eff

For comparison, Fig. 6.35 includes also the value of the fringe capacitance C f extracted from TCAD simulations for the same structure, yet excluding the S/D diffusion regions of the bottom-tier device (Fig. 6.32 (b)). Evidently, the C f value in the latter case is closer to the one calculated analytically. Continuing our analysis, the total back-gate oxide capacitance is given by So far, only long channel top-tier devices have been considered in our modeling approach.

𝐶 𝐼𝐿𝐷,𝑒𝑓𝑓 = 𝐶 𝑜𝑣 + 2 • 𝐶 𝑓 (6-19)
However, in order to model the C ILD,eff capacitance for a wide range of dimensions of top/bottom tier devices, the impact of the gate length scaling needs to be included. For that reason, the total C ILD,eff as well as its components (C ov ,C f ) were extracted with TCAD while decreasing the gate length of the top-tier devices in logarithmic scale from 1μm (Fig. 6.37 (a)) to 30nm (Fig. 6.37 (b)). While for a 1μm long top-tier device the C ILD,eff components follow the behavior of a longchannel device, this is not the case for a top-tier device having 30nm gate length. For the latter, as the gate length of the bottom-tier device is enlarged, the fringe capacitance component gradually degrades while the overlap capacitance component seems to increase according to

𝐶 𝑜𝑣 = 𝑎 𝜀 𝑜𝑥 𝑡 𝐼𝐿𝐷 𝑊 𝑜𝑣 𝐿 𝑜𝑣 (6-20)
where α is an empirical fitting parameter. For top-tier device of L Gtop =30nm this parameter has a value of 0.45 and increases with the top-tier device gate length until it reaches unity (long-channel behavior).

Furthermore, as the bottom-tier device gate length reaches the critical value where L Gbot,eff saturates, the overlap capacitance component progressively approaches its maximum value, differing from the abrupt transition in long-channel devices. The maximum value of the overlap capacitance is again given by (6-12) and is independent of the short channel effects. Indeed, as it has been shown in Fig. 6.27 (a), the electric field is shaped in such a way that needs complex analytical equations to be modeled. This task is beyond the scope of this thesis; hence a table model can be utilized to capture the variation of the C f component with the top-tier device scaling. Our modeling approach can be compared next to the charge-coupling factor results as extracted from I-V simulations (Fig. 6.40), where a good match among the two can be observed. This validates our simplifications concerning the charge-coupling factor expression and the effective gate length concept for the front/back interface of the top-tier devices.

Fig. 6.40 Charge-coupling factor versus L Gtop /L Gbot ratio for different top-tier device gate length as extracted from TCAD simulations along with our modeling approach

6.1.1.b Impact of top/bottom device misalignment

The relative misalignment of devices is another parameter that should be accounted for in the charge-coupling factor modeling. Misplacing by Δx the gates of two stacked devices, the chargecoupling factor is reduced since it depends on the overlapping area between the top-tier device channel and the bottom-tier device gate electrode (Fig. 6.41 (a)).

Once again, C ILD,eff can be modeled by splitting it in two capacitance components, C ov and C f as ιillustrated in Fig. On the other hand, the fringe capacitance component increases exponentially reaching its peak when there is 100% misalignment. Specifically for 30-nm stacked devices the maximum value of the fringe capacitance will be approximately equal to the overlap capacitance under zero misalignment. Nevertheless, in a more general scheme, two stacked devices being misaligned can have different gate lengths as depicted in Fig. 6.43, hence the derived effective back-gate length L Gbot,eff in the previous section must handle this asymmetry. To address this issue, the top-tier device can be split in two parts with the axis of symmetry at its center (Fig. 6.43), while the bottom-tier device is divided in two regions having gate length L' Gbot /2 and L'' Gbot /2, so that

𝐿 𝐺𝑏𝑜𝑡 = 𝐿′ 𝐺𝑏𝑜𝑡 2 + 𝐿′′ 𝐺𝑏𝑜𝑡 2 (6-23)
as if half of the top-tier device was stacked upon a device with L' Gbot /2< L Gtop /2, when the other half being stacked upon a device with L'' Gbot /2> L Gtop /2. This enables to set an effective back-gate length L Gbot,eff /2 for each half top-tier device channel region, from the extracted values in the previous section. Under this approach, the overlap capacitance component of C ILD,eff can be further split into C ov,1 and C ov,2 as Fig. 6.44 illustrates. The model along with the TCAD simulation results are displayed in Fig. 6.45, where a nice match between the two can be observed. Concerning the misalignment in the width direction of the devices, there shall be no SCE or S/D related impact, so the long channel modeling is valid regardless the scaling of the device.

Inter-tier dynamic coupling effects modeling

The inter-tier dynamic coupling effects emanate from the coupling capacitances created between the stacked devices. Consequently, the values obtained from the parasitic extraction can be utilized to evaluate the importance of dynamic coupling effects. The simplest equivalent model to describe the inter-tier dynamic coupling effects of the stacked structure illustrated in Fig. 6.46 (a), is shown in Therefore, the crosstalk S 21 parameter can be calculated transforming the transfer function to sparameters [START_REF] Lu | The determination of S-Parameters from the poles of voltage-gain transfer function for RF IC design[END_REF] with the two port network illustrated in Fig. 6.47, where V 01 =V S , V 2 =V Noise and when Z 1 =Z 2 =50Ω.

Inter-tier GP shielding modeling

The impact of the inter-tier GP on both the coupling-induced ΔV TH of the stacked devices as well as the noise coupling between both devices is investigated is this section. Specifically, a first-order equivalent circuit model is targeted examining the decoupling properties of the inter-tier GP in both DC and AC. This is accomplished by associating capacitive and resistive networks which depend on the material and geometry of the GP layer. Thus, the inter-tier GP can be viewed as a capacitive network forming between the stacked active device and an aggressor, e.g., an iBEOL metal line as Fig. 6.49 illustrates or a bottom-tier active device. devices, hence the resistance of the GP can be neglected in our modeling approach. However, this does not imply that there is no need for the optimum conductivity of the GP as it has a direct impact on the decoupling efficiency (Chapter 4).

Based on the theoretical concepts presented in Chapter 2, Fig. 6.50 illustrates the equivalent capacitive network between the staked devices with the insertion of an n-type inter-tier GP. The GP is coupled to the back-interface of the top-tier device channel through C GP-cht , given by 𝐶 𝐺𝑃-𝑐ℎ𝑡 = 𝜀 𝑜𝑥 𝑡 𝐵𝑂𝑋 𝑊 𝐺𝑡𝑜𝑝 𝐿 𝐺𝑡𝑜𝑝 where t BOX =25nm. Furthermore, the bottom-tier device gate electrode is coupled to the GP though C GP-cht , which can be considered a parallel plate capacitance supposing that it dominates over fringing electric fields between them, given by 𝐶 𝑔𝑏-𝐺𝑃 = 𝜀 𝑜𝑥 𝑡 𝐼𝐿𝐷 𝑊 𝐺𝑏𝑜𝑡 𝐿 𝐺𝑏𝑜𝑡 with t BOX being 130nm. Lastly there is also the capacitance between the bottom-tier device gate and the top-tier device channel, C gb-cht , with a value that depends on the GP decoupling effectiveness.

The latter depends on the GP area with respect to the bottom-tier device gate area and the material resistivity, as analyzed in chapter 4. In order to obtain the charge-coupling factor under the influence of the inter-tier GP, the split C-V method was once again followed with the aid of TCAD simulations and the threshold voltage was obtained as a function of V Gbot using the max(dC gc /dV g ) method. The results are shown in Fig. 6.53

and Fig. 6.54 for various values of Si-GP (10 15 -10 20 at/cm 3 ). In the same diagrams the charge-coupling factor is plotted for comparison, which was calculated from eq. with the extracted values of C gb-cht for each doping concentration of the Si-GP.

From Fig. 6.53 (a) it can be seen that for 10 15 at/cm -3 n-type doping concentration the decoupling behavior of the GP varies with the bottom-tier device gate bias. In detail, when V Gbot <0, the GP becomes essentially transparent to the bottom-tier gate electric field and there is no decoupling. This behavior is the outcome of an electron concentration decrease within the GP in the presence of a negative bias at the bottom-tier gate electrode. On the contrary, when V Gbot >0, accumulation of electron takes place at the back side of the GP layer, enhancing its shielding behavior. Thus, in that case, the calculated charge-coupling factor is only valid under a small-signal approach and for positive V Gbot . As analyzed in chapter 4, in order to reach a metal-like behavior, the n-type concentration of the Si-GP must be greater than 10 18 at/cm 3 . This is reflected in Fig. 6. 53 (b) where it is evident that the sensitivity of the top-tier device threshold voltage to bottom-tier gate bias variations becomes uniform. The error between the calculated charge-coupling factor and the TCAD is reduced especially for positive V Gbot . Further increasing the doping concentration of the Si-GP (Fig. 6.54) results in a linear dependence of ΔV TH,top on V Gbot , and the estimated charge-coupling factor presents minor errors from TCAD results. All the above can be summarized in Fig. 6.55 where the coupling induced ΔV TH of the stacked devices is plotted against the Si-GP doping for two different cases, the first (Fig. 6.55(a)) when there is a digital device at the bottom-tier (V DD =1V) and the second (Fig. 6.55(b)) for a bottom-tier analog device (V DD =2.5V). It is evident that in both cases, as the Si-GP doping concentration increases, the calculated ΔV TH,top from our modeled charge-coupling factor expression matches well the extracted values. is stacked on top of an electrode that can be either the bottom gate or a metal line and in between a GP made of silicon/polysilicon. A simple equivalent circuit that can be adequate to describe the decoupling efficiency offered by the inter-tier GP is suggested in Fig. 6.56(b). Here, the capacitance between the bottom-tier gate electrode (G 1 ) and the GP is represented by C g1.gp , the capacitance between the top-tier drain electrode (D 2 ) and the GP is defined as C gp,d2 and finally the coupling capacitances between G 1 -D 2 and G 1 -S 2 , decoupled by the GP layer, are displayed as C g1,d2 and C g1,s2

respectively. Additionally, a single lumped resistance R GP,gnd models the distributed resistance of the GP to the AC ground. To model the active device behavior, two current sources are included, controlled by V g1 and V gp via the transconductances g m,g1 and g m,gp respectively. Specifically, V gp is the noise voltage generated within the GP layer induced by V g1 . Considering this simplified circuit, the aggressor input signal is applied at node G 1 whereas the noise voltage is generated at the victim output node D 2 .

Applying Kirchhoff's current law at the output node D 2 , we derived the noise transfer function of the equivalent circuit as 𝐻(s) = V d2 V g1 = 𝐻 0 (𝑠)

1 + α(s) 𝑠C g1,gp 𝑠C g1,d2 -𝑔 m,g1 1 -α(s) 𝑠C g1,d2 𝑠C gp,d2 + 𝑠C g1,d2 + 𝑔 ds + 𝐺 𝐿 where α(s) = 𝑠C gp,d2 -𝑔 m,gp 𝑠C g1,gp +𝑠C gp,d2 +𝑠C gp,s2 + 1 𝑅 GP,𝑔𝑛𝑑 , and H 0 (s) is the suppression level offered by the intertier GP, derived as 𝐻 0 (𝑠) = 𝑠C g1,d2 -𝑔 m,g1 𝑠(C gp,d2 + C g1,d2 ) + 𝑔 ds + 𝐺 𝐿 Transforming the transfer function to s-parameters, the S 21 parameter with matched inputoutput impedance (Z 1 =Z 2 =50Ω) is given by 𝑆 21 = 2 • 𝑉 𝑁𝑜𝑖𝑠𝑒 𝑉 𝑆 = 2 • H(s) and for sinusoidal signals s=j2πf.

The maximum decoupling frequency f D,max can be defined as the frequency limit beyond which the GP layer appears to be capacitively transparent (as explained in §4.2.2.b). To validate equations (6-28)- , an accurate parameter extraction from our simulation data is needed. The capacitances C g1.gp , C gp,d2 , C g1.d2 shown in Fig. 6.57 where extracted from the split CV simulations for the two biasing states of the top-tier device. To extract R GP,gnd from the simulation data the input admittance extraction method at high frequency was used from the small-signal equivalent circuit of Fig. 6.56(b). The results are shown in Fig. 6.58, varying the number of GND contacts on the GP. It can be noticed that there is a dependency on the biasing conditions of the toptier device for doping concentrations below 10 18 cm -3 , related to the non-metallic behavior of the GP. The extracted parameters were inserted into equation and the results are plotted in Fig. 6.59. The well-fitting of the calculated and extracted crosstalk levels versus frequency for different doping concentration of the GP and biasing states of the top-tier device, validates our simple equivalent circuit for the frequency range studied. However, larger device geometries may need a more complex circuit representation due to distributed effects. Furthermore, the resistivity of the GP can be estimated from the values of the lumped resistance R GP,gnd used to fit the TCAD data for each doping concentration of the Si-GP. For that reason, the distance of the grounding contact on the GP to the active device was utilized, and the results are demonstrated in Fig. 6.60. The comparison with the experimental data [START_REF] Mandurah | Phosphorus Doping of Low Pressure Chemically Vapor-Deposited Silicon Films[END_REF] for the resistivity of monocrystal silicon reveals the validity of our equivalent model.

Conclusion

In this chapter the coupling capacitances between active devices have been thoroughly investigated through an extensive TCAD analysis, mainly focusing on the capacitive coupling effects.

Through a parasitic extraction procedure, the bias and layout dependency of the coupling capacitances has been assessed. Furthermore, the contribution of 3D contacts on the total capacitance has been evaluated for different density values. The results prove that the 3D via density of a 28nm-node limits significantly C dbdt , which is responsible for dynamic coupling effects between the devices. Nevertheless, as the density of 3D contacts increases (CPP/2=28nm), their contribution to the overall coupling capacitances is enhanced, since the lateral coupling dominates over the vertical (inter-tier) one due to the ILD thickness being 130nm.

Moreover, a modeling approach of the inter-tier coupling effects has been presented focusing on the coupling-induced ΔV TH of stacked digital devices. Under our analysis, two critical simplifications for the charge centroid have been considered:

• It is confined near the center of the top-tier device channel under zero gate bias.

• It remains near the center of the top-tier device channel for the maximum bias range of the bottom-tier devices (0V-2.5V) due to the thick ILD.

Along with the above approximations, the concept of the effective front/back gate length has been employed in our analysis for the top-tier device to handle the electric field deformation due to SCE and the presence of the bottom-tier S/D regions. The result of our modeling approach covers a

Resistivity (Ω•cm)

Si-GP doping (at/cm 3 )

Extracted resistivity from equiv. circuit to fit data Exp. Results of Si resistivity Si resistivity [START_REF] Mandurah | Phosphorus Doping of Low Pressure Chemically Vapor-Deposited Silicon Films[END_REF] wide range of top/bottom-tier device gate areas and under various geometric configuration. The comparison with the extracted threshold voltage shift from I-V simulations confirms our initial simplifications. Lastly, modeling considerations have been suggested for the AC coupling between the stacked devices as well as the capacitive network formed by the insertion of an inter-tier GP.

Additionally, the inter-tier dynamic coupling effects have been investigated at a device level, exploring both the small-signal and large-signal response of victim devices to the aggressor signals.

Again, the stacked devices and specifically the ones with a high W/L ratio reveal greater noise coupling levels, due to their back-gate coupling effect.

Over and above, all the geometry and biasing related dependencies of both static and dynamic coupling effects have been assessed. It has been proven that the coupling induced ΔV TH can be significantly limited when the two devices are misaligned. Yet, dynamic coupling effects must be taken into consideration since they are enhanced due to the direct overlapping of the top-tier drain with the bottom-tier gate electrode. As a consequence, the switching noise can be increased.

Concerning the results at a circuit level, different combinations of tier-stacking have been studied under a heterogeneous integration scheme. For the purpose of this analysis sensitive circuits in digital (SRAM) and mixed-signal/RF (RO) design have been selected as victim cases. In addition, aggressor signals have been selected to emulate a bottom-tier device being either digital, analog, mixed-signal/RF. The results confirm that inter-tier isolation methods and techniques are not mandatory for purely digital 3D sequential circuits. On the contrary, mixed signal/RF applications require further decoupling as the coupling effects impact significantly their normal operation and coincide in the frequency spectrum. The proper decoupling can be achieved either by process optimization (ILD thickness increase) or proper layout (misalignment of the stacked devices, 3D contact positioning).

In order to get an even greater reduction of the vertical capacitive coupling, the integration of an inter-tier decoupling layer (GP) is suggested for sensitive tier stacking combinations. The decoupling efficiency of the inter-tier GP has been thoroughly evaluated as a function of its material properties, its size and the number of grounding contacts. Specifically, the use of a semiconductive material has been evaluated with its resistivity defined by the doping concentration. Additionally, the inter-tier GP also functions as a back-gate for the top-tier devices, adjusting their threshold voltage via its workfuction and also by utilizing the back-biasing technique. Therefore, depending on the toptier device (Digital, Analog, Mixed-Signal/RF) different flavors of GP can be utilized, optimizing their performance Specifically for RF applications a high doping concentration of the inter-tier GP is needed in order to achieve the maximum decoupling efficiency. As a result, this work proposes a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 ndoping and 295Ω/sq sheet resistance.

This work has also evaluated the impact of the coupling-induced effects on the performance of a RS CIS with its pixels partitioned in different tiers of a 3DSI process. The device electrical parameters (V TH , I off and I on ) of a single pixel were initially studied comparing their coupling-induced shift with the one resulting from temperature variation in sensing circuits. The results prove that the coupling-induced effects can result in a shift of the device electrical parameters as significant as a temperature variation of 100 degrees. This deviation is far from negligible especially for switch transistors for which leakage is a critical parameter. Concerning the in-pixel SF transistor at circuit level, it was shown that there is negligible impact on the CG and the AC performance due to the 3DSI partitioning compared to the conventional single-tier one. Furthermore, the SF-TG coupling can result in a readout error only when the SF is placed above a TG that wouldn't be synchronized with the pixel readout. However, for RS exposure mode this is not possible due to asynchronous pixel activation. Therefore, although the electrical coupling has proven to be strong, the special case of a RS CIS presents an inherent immunity to coupling effects in a 3DSI partitioning.

Lastly, parasitic extraction was performed on 3DSI structures at a device level. The coupling capacitances responsible for the inter-tier coupling effects, were analyzed in depth. Through the electric field decomposition method, the components of each coupling capacitance were evaluated investigating also all their biasing/geometry related dependencies. Moreover, the impact of 3D contacts was studied, proving that their contribution to the overall coupling capacitances can be significant when their density is increased. In addition, a comprehensive modeling approach of intertier coupling effects was presented. Though an extensive simulation study, expressions were suggested to describe the impact of layout effects on the inter-tier coupling. The models predict accurately the amount of the coupling-induced ΔVTH for stacked devices for a wide range of device geometries and layout configurations of the top/bottom devices. Additionally, some considerations were suggested concerning the modeling of AC coupling and also the impact of an inter-tier GP on the coupling effects.

  ABBREVIATIONS

Fig. 1. 1

 1 Fig. 1.1 Evolution of the Field Effect Transistor (FET) Architecture (Courtesy of [9]).

Fig. 1. 2

 2 Fig. 1.2 Parallel (a) versus Sequential (b) 3D integration.

Fig. 1. 4

 4 Fig. 1.4 Partitioning types in three-dimensional integration.

Fig. 1. 5

 5 Fig. 1.5 Reduction in wire length where the original 2-D circuit is composed of two and four tiers.

21 Fig. 1. 8

 218 Fig. 1.8 CoolCube TM technology process flow [21].

Fig. 1. 9

 9 Fig. 1.9 TEM cross-section of two stacked transistors fabricated in 3DSI.

Fig. 2 .

 2 Fig. 2.1 3D representation of a BULK MOSFET.

Fig. 2 .

 2 Fig. 2.2 (a) Cross-section schematic view of a MOSFET indicating the MOS capacitor and (b) its energy band diagram for V G >0.

Fig. 2 .

 2 Fig. 2.4 (a) presents the drain current to gate voltage (I D -V G ) dependence, named also input characteristics of the MOSFET transistor. On the other hand, the output characteristics that show the drain current versus drain voltage (I D -V D ) are demonstrated in Fig. 2.4 (b).

Fig. 2 .

 2 Fig. 2.4 I D -V G input (a) and output (b) characteristics of a MOSFET .

.

  Subthreshold swing (SW): Below threshold voltage (V G <V TH ), the drain current is not zero due to the subthreshold conduction (Fig.2.4 (a)), instead it is increasing exponentially. The subthreshold swing, is defined as the inverse of the slope of the I D (V G ) curve in the subthreshold regime, presented on a semi-logarithmic plot. It is expressed in volts or millivolts per decade and an approximation for BULK MOSFETs is given by

  current (I off ): is the drain current for zero gate bias. It is a leakage current and its level is a function of the threshold voltage of the device in conjunction with the subthreshold slope.

Fig. 2 . 5

 25 Fig. 2.5 Depletion regions indicated by the dashed lines for a long channel (a) and a short channel (b) MOSFET.

Fig. 2 . 7

 27 Fig. 2.7 Schematic view of the SOI substrate.

Fig. 2 .

 2 Fig. 2.8 3D representation of (a) a SOI MOSFET and (b) a cross-section schematic view of that.It is evident that the device structure is similar to the BULK architecture, however there are major differences. The most prominent one is the drastic reduction of the silicon film which constitutes the channel alongside with the presence of the buried dielectric layer (Buried OXide -BOX) which physically limits the depth of the depletion region inside the channel to the thickness of the silicon film.As a consequence, the FDSOI structure presents excellent Short Channel Effect (SCE) control allowing decreasing gate length down to 24nm. Moreover, it enables the possibility of utilizing an undoped silicon channel. This allows FDSOI devices to overcome the main source of variability in BULK transistors which is the Random Dopant fluctuation (RDF). With the absence of dopants, the threshold voltage becomes mainly a function of the gate-metal workfunction and the back-gate (V B )

  in 1-D employing two fundamental "classical" assumptions. The first concerns the depletion approximation, which assumes |Q b | >> |Q i |, where Q b = -qt Si N B is the depletion charge density and

Fig. 2 .

 2 Fig. 2.10 Schematic diagram of the Threshold voltage sensitivity of the front-gate versus the back-gate bias in the Lim-Fossum model.

Fig. 2 .

 2 Fig. 2.11 (a) Lorentzian type spectrum example and (b) result of adding two six uniform different level Lorentzians[START_REF] Theodorou | Low-frequency noise in advanced CMOS/SOI nanoscale multi-gate devices and noise model development for circuit applications[END_REF].

Fig. 2 .Frequency

 2 Fig. 2.12 (a Spectrum result of adding two different level Lorentzians and (b) eesult of adding non-uniform Lorentzians[START_REF] Theodorou | Low-frequency noise in advanced CMOS/SOI nanoscale multi-gate devices and noise model development for circuit applications[END_REF].

Fig. 2 .

 2 Fig. 2.13 Schematic representation of (a) the CNF model (b) The Hooge model and (c) the unified CNF/CMF model.

Fig. 2 .

 2 Fig. 2.15 Equivalent circuit model of capacitive coupling shielding between conductors 1 and 2.

Fig. 2 .

 2 Fig.2.17 Noise margin of a driving (left) and a receiving (right) device.

Fig. 2 .

 2 Fig. 2.18 DC transfer curve of an inverter.

Fig. 2 .

 2 Fig. 2.19 (a) noisy MOSFET and its equivalent model comprised of an ideal MOSFET and (b) voltage or (c) current noise source.

3. 2 .

 2 The top tiers of devices can be stacked right after the bottom tier process as shown in Fig.3.2 (a), or there can be an intermediate Back-End-Of-Line (iBEOL) between the active device tiers, as depicted in Fig.3.2 (b). The direct stacking of devices (Fig.3.2(a)) is considered as the ultimate level

Fig. 3 . 2

 32 Fig. 3.2 Arrangement scheme of sequential tiers in 3DSI. (a) Direct device stacking (b) Tiers separated by an iBEOL.

Fig. 3 . 3

 33 Fig. 3.3 Heterogeneous tier stacking in 3DSI.

3. 4 .

 4 On the bottom tier, standard high temperature (maximum TB of 1050°) CMOS devices are fabricated on 300mm SOI wafers with raised source and drain junctions activated at 1050°C. In addition, the bottom device gate stack is comprised of a HfSiON/TiN/Poly-Si sequence. Afterwards, NiPt 10% silicidation and pre-metal dielectric deposition are done, followed by a Chemical-Mechanical Polishing (CMP) process which planarizes the whole structure surface.

Fig. 3 .

 3 Fig. 3.4 3D sequential process flow[START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF].

Fig. 3 . 5

 35 Fig. 3.5 TBs tested on FDSOI technology with SiGe channel for pFET and SiGe:B/ SiC:P RSD with preserved N &PFET I ON I OFF performance [89].

Fig. 3 .

 3 Fig. 3.6 (a) Schematic of the structure under study (b) TEM cross-section of two stacked transistors in 3DSI [19].

Fig. 3 . 7

 37 Fig. 3.7 Layout view of (a) bottom device and (b) top device. (c) Combined top+bottom layout view.

Fig. 3 . 8 3D

 38 Fig. 3.8 3D Schematic view of the structure under test.

Fig. 3 . 9

 39 Fig.3.9 Cases studied for the interference of adjacent devices in 3DSI. Aggressor is the top device while victim is the bottom one in(a) and vice versa in (b).

Fig. 3 .

 3 Fig. 3.10 Drain current versus gate voltage for bottom tier NMOS device with L G =1μm.

Fig. 3 .

 3 Fig. 3.12 Drain current versus gate voltage for top tier NMOS device with L G =1μm.As can be observed there is a shift of the top device I D -V G curve with the application of a positive bias at the bottom device gate electrode resulting in a threshold voltage shift ΔV ΤΗ , as well as a slight change in the sub-threshold swing ΔSW. This behavior is attributed to the asymmetrical SOI

Fig. 3 .

 3 Fig. 3.14 Threshold voltage shift of top-tier NMOS devices in linear regime (V Dtop = 30 mV), at different bottom-tier NMOS biases.

Fig. 3 .

 3 Fig. 3.15 Normalized drain current PSD vs frequency for a top-tier NMOS with W = 2μm, L = 1μm, for all the bottom-tier NMOS biasesshown in Table3.2.

Fig. 3 .

 3 Fig. 3.16 Normalized PSD at f = 10 Hz vs drain current for a top NMOS with W = 2 μm, L = 1 μm (a) and L = 0.1μm (b), for all the V Gbot cases shown in Table3.2.

Fig. 3 .

 3 Fig.3.15 and Fig.3.[START_REF] Sugahara | SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices[END_REF] show that, contrary to the impact on the static behavior, no noticeable coupling effect is observed in the current-normalized LFN spectra behavior. As Fig.3.16 (a) shows, the LFN level at L = 1 μm can be considered unchanged whatever the bottom-tier gate bias, from subthreshold to strong inversion region. The same is true for the top-tier devices with L = 0.1 μm, however, as shown in Fig.3.16 (b), the general LFN dependence on top-tier gatebias is not the same.

  voltage was swept from -20V to +20V with a step of 2V while extracting the top NMOS device input characteristics. Following the same procedure as previously for the threshold voltage extraction, the results for each bottom gate bias are shown in Fig.3.18. As observed, the threshold voltage of the top device decreases with a positive bottom gate bias because of the weak inversion occurring at the

Fig. 3 .

 3 Fig. 3.18 Top SOI Gate Voltage versus the Bottom SOI Gate Voltage. The charge-coupling factor is the slope of the curve.

  and 100nm gate length corresponding to the same die, for 5 dies in total and the results are shown in Fig.3.19. An apparent decrease of ~1.2mV is observed, attributed to the reduction of the BG effective length of the top device.

Fig. 3 .

 3 Fig. 3.20 Extracted median value of the charge-coupling factor for top devices versus the gate length, under V D =30mV and V D =0.9V.

Fig. 3 .

 3 Fig. 3.21 Cross-section view of the TCAD structure simulated comprised by stacked NMOS devices showing the electron concentration.The results (Fig.3.22) show very good fitting between measurements and simulations concerning the static characteristics for the required transistor biasing. In detail both linear and saturation behavior as well as the 15.6mV shift of the top transistor's threshold voltage due to bottom gate coupling, are accurately captured.

Fig. 3 .

 3 Fig. 3.22 Drain current versus gate voltage for a bottom-tier NMOS device (a) and a top-tier NMOS device for V Gbot =0V (b) andV Gbot =0.9V (c). Circles and lines denote experimental and simulation results.

Fig. 3 .

 3 Fig. 3.24 Carrier concentration versus silicon film depth for NMOS (a) and PMOS device (b).

  3.25) and is in line with the experimentally extracted values. The static coupling decreases with the gate length due to the screening by the high source/drain electric field of the top-tier transistor and results in a reduction of the coupling-induced ΔV TH by around 5mV for nominal gate length devices in 28nm FDSOI technology.

Fig. 3 .

 3 Fig. 3.25 ΔV TH,coupl vs. gate length for a top tier device. 28FD nominal L Gtop devices show better immunity to inter-tier DC coupling.

Fig. 3 .

 3 Fig. 3.26 Impact of gate length on the coupling induced ΔV TH vs. V Gbot for NMOS and PMOS top tier devices.

Fig. 3 .

 3 Fig. 3.27 Coupling induced ΔV TH vs. V Gbot for NMOS (a) and PMOS (b) top tier devices with L G =30nm under low and high V Dtop.

Fig. 3 .

 3 Fig. 3.29 Top SOI Gate Voltage versus the Bottom SOI Gate Voltage extracted from the C-V method described in this section comparedto the I-V method followed in chapter 3.

Fig. 3 .

 3 Fig. 3.30 (a) shows the C-V results with its derivative in Fig. 3.30(b) for the critical case of stacked devices having both L G =30nm, where an evident decrease of the back-bias sensitivity is observed. The latter corresponds to the impact of SCE as investigated in §3.2.2.b.

  Fig. 3.30 TCAD results of the gate-to-channel capacitance C gt-cht of the top-tier device versus its gate voltage (a) and their derivatives (b) for various bottom-tier gate voltages V gbot , illustrating the procedure for extracting coupling characteristics (L G =30nm).

Fig. 3 .

 3 Fig. 3.31 Charge-coupling factor versus L Gbot /L Gtop ratio for different top-tier device gate length as extracted from TCAD simulations.

Fig. 3 .

 3 Fig. 3.32 Electric field vector plot showing the shape of the flux induced by the bottom-tier device gate electrode to the top-tier device channel for devices with equal gate length of (a) L G =1μm and (b) L G =30nm.

Fig. 3 .

 3 Fig. 3.33 (a) Schematic 3D illustration of the stacked devices with the top-tier having a relative misalignment from the bottom one and (b) Charge-coupling factor versus misalignment for different gate length (L Gtop =L Gbot ) as extracted from TCAD simulations

  3.14) is attributed to the weak bottom interface b.

Fig. 3 .

 3 Fig.3.35 (a) shows the expected amount of threshold shift at 1-σ (black line) and at 3-σ (red line) due to mismatch of 28nm FDSOI technology[START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF], as a function of the reciprocal of the geometrical mean of the device dimensions. The extracted average ΔV TH of around 15 mV is also plotted (blue line). Although there is a dependence of the coupling-induced ΔV TH on the device gate

Fig. 3 .

 3 Fig. 3.35 (a) Coupling-induced shift and mismatch-related variations (28nm FDSOI versus reciprocal of gate area square root) for a) threshold voltage and (b) I off and I on current shift. The vertical marker in figure (a) indicates the mismatch standard deviation for the minimal transistor surface in 28 nm FDSOI (W = 80nm, L = 30 nm).

Fig. 3 .

 3 Fig. 3.36 Schematic top layout view of a digital standard cell in 28nm FDSOI technology. The distance limitations between the power supply rails (V DD and GND) restrict the gate area of the devices below 0.01 μm 2 .

Fig. 3 .

 3 37 shows the Threshold Voltage shift due to coupling versus the ILD thickness extracted by TCAD simulations, for the two cases of bottom tier devices. The experimentally extracted values for both cases are denoted with the open symbols while an exponential decrease as a function of the ILD thickness is evident.

Fig. 3 .

 3 Fig. 3.37 Threshold voltage shift due to static coupling for 2 different stacks of devices. To preserve the same coupling-to-noise marginfor Analog bottom-tier devices a thicker ILD (≥350nm) is needed.

  Fig. 3.38 TEM cross-section of the fabricated analog SOI architecture using LT processing [102].

Fig. 3 .

 3 Fig. 3.39 Threshold voltage shift due to static coupling for 2 different stacks of devices with analog on top. The black markers recallthe results obtained for digital device stacking.

Fig. 3 .

 3 Fig. 3.40 Rise/fall time of a pulse shaped signal and propagation delay of a NOT gate.

Fig. 3 .

 3 Fig. 3.41 Typical delay for global and local Cu interconnects compared to the nominal gate delay in each technology node[START_REF] Banerjee | Interconnect modeling and analysis in the nanometer era: Cu and beyond[END_REF].

Fig. 3 .

 3 Fig. 3.42 Equivalent circuit of a two-port network in terms of s-parameters. mixed-signal 3D circuits, other network parameters such as g 21 which represents the forward voltage gain (𝑔 21 = 𝑉 2 𝑉 1 | 𝐼 2 =0

Fig. 3 .

 3 Fig. 3.43 Simulated structure in HFSS (a) and port configuration for the network parameter extraction (b).Therefore, the lowest value of the resistance from drain to the common source node occurs in the linear region of operation for V GS = V DD . The resistance value in this biasing state was obtained with the aid of a TCAD small signal simulation, and was used to calibrate the resistance seen by the D top electrode to the reference electrodes S top , S bot in HFSS.

  3.45 (a)) On the other hand, varying the gate width the relative shift of g 21 increases, indicating that magnetic fields become stronger (Fig. 3.45 (b)).

Fig. 3 .

 3 Fig. 3.44 Extracted g21 parameter from HFSS simulation for a device with L G =30nm and W G =0.5μm. The g 21 parameter indicates the noise voltage at the top device drain terminal divided by the bottom device drain terminal.

Fig. 3 .

 3 Fig. 3.45 Variation of the g 21 parameter with the gate length (a) and width (b) of both devices.

Fig. 3 .

 3 Fig. 3.46 shows the crosstalk level in the frequency range from 1MHz to 100GHz, for both devices having equal gate length and width of 1μm, whereas the top device is in cutoff (Fig. 3.46 (a)) and in saturation region of operation (Fig. 3.46 (b)).

Fig. 3 .

 3 Fig. 3.46 Crosstalk levels for the top-tier device electrodes of L G =1μm, in cutoff (a) and saturation region (b), extracted by the Sparameter technique.A small-signal noise voltage is applied in each electrode of the bottom device.

Fig. 3 .

 3 Fig. 3.47 Crosstalk levels for the top-tier device electrodes of L G =30nm, in cutoff (a) and saturation region (b), extracted by the Sparameter technique.A small-signal noise voltage is applied in each electrode of the bottom device.

Fig. 3 .

 3 Fig. 3.48 Setup for bottom-tier SOI dynamic coupling characterization.

Fig. 3 .

 3 Fig. 3.50 shows the amplitude of the parasitic spike due to the dynamic coupling versus the rise time of the applied pulse at the BG, both in log scale, the circles indicate the experimental results while the dashed line refers to the TCAD simulation results. The agreement between the two is apparent and also the extrapolation to shorter rise times reveals the Ohms law dependence of this

Fig. 3 .

 3 Fig. 3.49 Dynamic coupling transient results for a bottom tier SOI (W G =30μm, L G =0.5μm) at V G =0.1V. (a) Experimental transient for t R = 30μs with the applied pulse at the BG of the device (blue) and the measured drain current (red) revealing the parasitic spike i ac,coupl . (b)TCAD simulation for a shorter rise time (t R =3μs) shows that the i ac,coupl becomes greater than the coupling-induced DC shift (I dc,coupl ).

Fig. 3 .

 3 Fig. 3.50 Peak amplitude of i ac,coupl vs rise time of the applied pulse at the BG of the bottom SOI for Fig. 3.48 case. TCAD simulations are in-line with experimental results.

Fig. 3 .

 3 Fig. 3.51 Setup for top-tier SOI dynamic coupling characterization.with a swing voltage of V swing =1V, a frequency of f clk =5GHz, a rise/fall time of 8ps, and a pulsewidth of 92ps as shown in Fig.3.52 (a). The transient response of the top device drain current to the applied clock signal was then obtained for the top device under biasing in the 3 regions of operation, cutoff in Fig.3.52 (b), linear in Fig.3.52 (c) and saturation in Fig.3.52 (d).

Fig. 3 .

 3 Fig. 3.52 Transient response of the top-tier device drain current to the applied clock signal (V swing =1V, f clk =5GHz, t R /t F =8ps, t pulse = 92ps) at the bottom device gate electrode (a), for 3 different regions of operation, cutoff (b), linear (c) and saturation (d).

Fig. 3 .

 3 Fig. 3.53 Peak amplitude of i ac,coupl vs rise time of the applied pulse at the BG of the bottom SOI for Fig. 3.51 case.

Fig. 3 .

 3 Fig. 3.54 Setup for top-tier SOI dynamic coupling characterization under the worst case scenario (max. C Dtop,Gbot ).

Fig. 3 .

 3 Fig. 3.55 (a) Peak amplitude of i ac,coupl vs relative misalignment between the gates of the devices. (b) top-tier SOI layout view.

Fig. 3 .Chapter 3 -

 33 56 (a) examines the inter-tier crosstalk employing two stacked devices that consist a two-port network where the drain of the bottom device D bot is selected as port 1 and the drain of the top D top as port 2, whereas the rest of the electrodes are set to the Investigation of 3DSI electromagnetic coupling effects at a device level 96 common ground.On the other hand, the setup of Fig.3.56 (b) features a critical case of adjacent devices in planar SOI technology. It consists of two devices placed at the same tier (intra-tier), mirrored to each other and separated by the minimum distance dictated by the technology. This time, the drain of the left device is assigned to port 1 while the drain of the right device is set to port 2 and all the other electrodes are set to common ground.The devices simulated in both cases have equal gate length L G =30nm and widths W G =620nm, while the density of the contacts in the first case is reduced due to the direct stacking of the devices.

Fig. 3 .

 3 Fig. 3.56 Simulation setup in HFSS to estimate the relative difference between inter-tier (a) and intra-tier coupling.

Table 4 . 1

 41 Possible stacking combinations under heterogeneous integration in 3DSI TOP TIER (EOT=1nm, V DD =1V) Digital Mixed-Signal/RF BOTTOM TIER Digital (V DD =1V) Analog (V DD =2.5V)

Fig. 4 .

 4 Fig. 4.1 Schematic view of the top-tier SRAM cellThe 6T SRAM bitcell configuration of Fig.4.1 consists of two identical cross coupled inverters (left: INV 1, right: INV 2) and two access transistors connected to each data storage node. The inverter pair is connected in a positive feedback loop that forms a latch and holds the binary information. It can be in one of the two stable states of an SRAM bitcell, corresponding to the bit value stored '1'

Fig. 4 .

 4 Fig.4.2 shows the voltage transfer characteristics of inverter 1 (VTC) and voltage transfer characteristics of inverter 2 (VTC -1 ) in a 6T SRAM during the read cycle. The metric to quantify the stability of an SRAM bitcell during the read cycle and in hold state is the Read Static Noise Margin (RSNM). The RSNM is defined as the maximum amount of static noise that can be tolerated by the

Fig. 4 . 2

 42 Fig. 4.2 The VTC and inverse VTC of the cross-coupled inverter pair in a 6T SRAM during the read cycle.

Fig. 4 .

 4 3 shows a simplified layout representation of the S3D 2-bitcell SRAM under study. Because of the asymmetric double-gate SOI structure of the top-tier transistors, the Interlayer dielectric functions as their BOX and therefore their BG terminals are indeed the front gate terminals of the respective bottom tier transistors.

Fig. 4 .

 4 Fig. 4.3 (a) Simplified layout representation of the superimposed monolithic 3D SRAM bitcells under study with (b) a zoom-in view of the stacked device configuration.

  model chosen to describe the behavior of the top-tier transistors is the LETI-UTSOI MOSFET model (version 2.11) [37] that accurately captures the device characteristics after proper parametrization with the experimental data presented in § 3.2.1. The results (Fig. 4.4) show very good fitting between measurements and model concerning the static characteristics for the required transistor biasing. In detail both linear and saturation behavior as well as the 15.6mV shift of the top transistor's threshold voltage due to bottom gate coupling, are accurately captured.

Fig. 4 . 4

 44 Fig. 4.4 Drain current versus gate voltage for a top-tier NMOS device (L = 0.1 μm). Circles and lines denote experimental and simulation results, respectively.

Fig. 4 .

 4 Fig. 4.5 (a) Impact of V TH mismatch on RSNM of a top-tier SRAM bitcell, (b) Addition of the static coupling because of the bottom tier SRAM operation.

  . 4.5 (b) and Fig. 4.6 (b), the coupling-induced V TH shift can further reduce both the RSNM and the WSNM by 1%.

Fig. 4 .

 4 Fig. 4.6 (a) Impact of V TH mismatch on WSNM of top tier SRAM, (b) Addition of the static coupling because of the bottom tier SRAM operation.

Fig. 4 .

 4 Fig. 4.7 Bit-line current versus cell supply voltage. (a) Typical results for the three bottom-tier bitcell operation cases (b) Monte Carlo simulations with mismatch variations (c) Monte Carlo with the same random number generation seed, adding also the static coupling induced shift.

4 . 8 :

 48 each transistor is composed by a TCAD structure including the stacked transistors and all the necessary physical models. Moreover, we considered two cases: a gate overlap=1 when all bottom-and top-tier transistor gates are perfectly aligned (Fig. 4.8 (a)) and a gate overlap=0 when the bottom-tier gates are aligned below the respective top-tier transistor drain regions (Fig. 4.8 (b)).

Fig. 4 . 8

 48 Fig. 4.8 Simplified layout representation of the superimposed SRAM. Each top-tier SOI is comprised by the TCAD structure shown here

Fig. 4 . 9

 49 Fig. 4.9 Butterfly diagram of a top-tier SRAM bitcell for the two cases of relative misalignment between stacked devices

Fig. 4 .

 4 Fig. 4.10 (a) Mean and worst MC butterfly diagram of a top-tier SRAM bitcell indicating the meta-stable point (b) Addition of the static coupling because of the bottom tier SRAM operation.

Fig. 4 .

 4 Fig. 4.11 Simplified layout representation of the superimposed SRAM where the top SRAM reads at the moment that the bottom SRAM attempts a write operation.

Fig. 4 .

 4 Fig. 4.12 (a) Read operation for top-tier SRAM cell: The WL top is enabled and BLL top discharges to V CLtop . (bottom SRAM off). (b) V CLtop during a write operation (0→1V and 1→0V from t 1 to t 2 ) with 10ps rise time (shortest in 28FD) at the bottom SRAM.

Fig. 4 .

 4 Fig. 4.13 Top tier RO composed of three NOT gates. The back-gate bias of each SOI device can go up to either 1V (V DD for bottom-tier SOI with EOT=1nm) or 2.5V (V DD for bottom-tier SOI with EOT=5nm)In this configuration, each top-tier device is considered to have its back-gate tied to the voltage bias of the bottom gate electrode which can go up to 2.5V. Fig.4.14 shows a frequency shift of 510MHz for a 30.2 GHz oscillating signal due to the 2.5V shift of the bottom-tier electrode bias.

Fig. 4 .

 4 Fig. 4.14 FFT for top-tier RO with 0V,1V and 2.5V bias application at each SOI back-gate.

Fig. 4 .

 4 Fig. 4.15 Phase noise shift for top-tier RO with 0-2.5V bias application at each SOI back-gate.

112 Fig. 4 .

 1124 Fig. 4.18 FFT for top-tier RO with the clock signal applied at PMOS or NMOS back-gate along with the reference case

Fig. 4 .

 4 Fig. 4.19 recalls the characteristic dimensions of a 3DSI structure comprised of 2 stacked devices under a specific layout configuration A. In particular, Fig. 4.19 (a) illustrates the top layout view whereas the respective cross-section A'A is shown in Fig. 4.19 (b). The parameters affecting the inter-tier coupling which can be altered by a circuit designer are the gate width and length of the two devices (here they are considered identical in dimensions), the distance of the 3D contact to the top active (3DCO-RX) as well as the distance of the 3D contact to the top gate electrode (3DCO-PC). The minimum allowed values for the last two parameters are process depended.

Fig. 4 .

 4 Fig. 4.19 Layout configuration A of two stacked devices in 3DSI with the characteristic dimensions. (a) Top layout view and (b) Crosssectional AA' view

Fig. 4 .Fig. 4 .

 44 Fig. 4.20 Layout configuration B of two stacked devices in 3DSI with the characteristic dimensions. (a) Top layout view, (b) Crosssectional AA' view and (c) Cross-sectional BB' view

Fig. 4 .

 4 Fig.4.[START_REF] Batude | 3D sequential integration: Application-driven technological achievements 202 and guidelines[END_REF] Crosstalk at 1GHz between different electrodes of the two stacked devices under the layout configuration B (Fig.4.20) versus the distance between the top-tier gate electrode and the 3D contact connected to the bottom-tier drain diffusion area.

Fig. 4 .

 4 Fig. 4.22 Charge-coupling factor of top-tier digital and analog devices versus the ILD thickness

Fig. 4 .

 4 Fig. 4.24 Schematic cross-section view of 3DSI scheme indicating the characteristic dimensions of a 3D contact

4. 25 (

 25 a) for a device with L G =1μm, the bottom device can be misaligned from the top by Δx either along the gate length or width direction. The potential contour plot of Fig. 4.25 (b), as obtained from TCAD simulations, reveals the deformation of the electric field induced by the bottom-tier gate electrode due to the relative misalignment of the two devices. The overlapping area region indicated by the dashed rectangle defines the coupling-induced ΔV TH as shown in the extracted TCAD results (Fig. 4.26).

Fig. 4 .

 4 Fig. 4.25 Relative misalignment by Δx between two stacked devices (a) Schematic 3D representation (b) Potential contour plot of the structure extracted from TCAD simulations.

Fig. 4 .

 4 Fig. 4.26 Coupling-induced ΔV TH of top-tier digital devices vs overlapping area of bottom gate poly to top channel ratio.

118

 118

Fig. 4 .

 4 Fig. 4.27 Cross-sectional TEM image of fabricated 3D stacked devices with an inter-tier BG (Courtesy of [64]) Targets for the GP properties are the suppression level and frequency response, minimum thickness and front-end of line compatibility. The simulation setup that was used, is shown in the 3D illustration of Fig. 4.28 (a) and the corresponding cross section AA' in Fig. 4.28 (b). It consists of a

Fig. 4 .

 4 Fig. 4.28 (a) Simulation setup to determine the GP decoupling efficiency. The GP area is 2x the top active area with 1 GND contact. (b) Cross-section AA' view.

  first (1) for a GP area 2 times the active area and a large bottom-tier gate electrode (Fig. 4.30 (a)), the second (2) for the same GP area as previously and equal areas of top/bottom-tier gate electrodes (Fig. 4.30 (b)) whereas the last one (3) features a very large GP (Fig. 4.30 (c)) covering completely the top device active area. The results are shown in Fig. 4.31.

Fig. 4 .

 4 Fig. 4.30 Simulation setup in TCAD to evaluate the decoupling efficiency of the inter-tier GP when it has an area 2 times the active one and the bottom-tier gate electrode is (a) large or (b) equal in area with the top-tier gate electrode, and (c) when the GP is very large, covering completely the top device active area

Fig. 4 .

 4 Fig. 4.33 Coupling-induced ΔV TH of the top-tier device to the bottom-tier electrode versus the ILD thickness for different doping concentrations of a silicon inter-tier GP. The insertion of the Si GP (10 20 cm -3 ) reduces the DC coupling by ~10 7

Fig. 4 .Fig. 4 .Fig. 4 .

 444 Fig. 4.34 (a) Simulation setup to determine the GP decoupling efficiency for a GP area 2x the top active. (b) Port configuration for the S21 network parameter extraction

Fig. 4 .

 4 Fig. 4.35 Crosstalk vs. frequency for the top-tier device in cutoff (a) and saturation region (b) and a GP made of silicon.

Fig. 4 .

 4 Fig. 4.36 Crosstalk vs. frequency for the top-tier device in cutoff and saturation region for No GP case (red trace) and a silicon GP (blue trace) with doping concentration of (a) 10 15 cm -3 and (b) 10 20 cm -3 . The frequency beyond which the slope of the S21 parameter gets greater than 20dB/dec is defined as the maximum decoupling frequency f D,max

Fig. 4 .

 4 Fig. 4.29. The S 21 parameter results obtained by both HFSS and TCAD are shown in Figure Fig. 4.37 (a) and they are in line. This confirms the validity of TCAD simulations for the high-frequency EM analysis in our structures.

Fig. 4 .

 4 Fig. 4.37 (a) Comparison between TCAD and HFSS simulations to validate the results of the formerin the high-frequency domain. (b)The results obtained by TCAD are reproduced calibrating the resistivity of the GP material from fata of Fig.4.29.

  where the material of the inter-tier GP is polysilicon, its decoupling performance is shown in Fig.4.38 (a) and (b) for the device being in cutoff and in saturation region respectively, as obtained by TCAD simulations. It is evident that greater doping concentrations are needed for the GP to function as an effective shielding layer, directly related to the resistivity of polysilicon (Fig.4.29).

Fig. 4 .

 4 Fig. 4.38 Crosstalk vs. frequency for the top-tier device in cutoff (a) and saturation region (b) and a GP made of polysilicon.The above extracted results can be visualized with the aid of the cross-sectional electric field contour plots obtained by HFSS simulations for an excitation by a 1GHz signal of 1V amplitude upon the bottom-tier gate electrode. Results without and with an inter-tier n + Si GP (10 20 cm -3 ) are shown in the figure. As seen in Fig.4.39 (b), the GP isolates and attenuates nearly the entire electric field induced from the bottom-tier gate electrode whereas in Fig.4.39 (a) without a GP a large portion of the induced electric field reaches the upper active region.

Fig. 4 .

 4 Fig. 4.39 HFSS simulation of electric field contour plots showing the magnitude of electric fields without (a) and with (b) n+ Si GP. A 1-GHz, 1-V signal is excited upon the lower metal line. As seen on the bottom, the n + GP shadows the upper active region from the electric field induced by the metal line.

Fig. 4 . 2 -

 42 Fig. 4.40 HFSS simulation of magnetic field contour plots showing the magnitude of magnetic fields for a n + Si GP. A 1-GHz, 1-V signal is excited upon the lower metal line. The magnetic field penetrates the GP reaching the upper active region.

Fig. 4 .

 4 Fig. 4.41 The GP area now is 3x the top active with one GND contact. Inset:Top-tier layout view As Fig. 4.42 (a) shows, expanding the GP area with respect to the top active region the crosstalk suppression increases and reaches a maximum attenuation level for a certain GP sizing. On the contrary the maximum decoupling frequency has the inverse trend as shown in Fig. 4.42 (b). Thus, the increase of the GP area yields a decrease of the decoupling frequency range, related to the potential attenuation across the GP for one ground (GND) contact on it.

Fig. 4 .

 4 Fig. 4.42 (a) Crosstalk suppression and (b) Maximum decoupling frequency versus the ratio of the inter-tier GP area with respect to the top active region for one GND contact

Chapter 4 -Fig. 4 .

 44 Fig. 4.43 (a) The GP remains 3x the top active and gradually up to 6 gnd taps are added. Inset:Top-tier layout view. (b) Extracted crosstalk vs. frequency. A larger n + Si GP needs greater number of GND contacts to maintain the decoupling frequency up to 100GHz

Fig. 4 .

 4 Fig.4.[START_REF] Xu | Compact capacitance and capacitive coupling-noise modeling of through-oxide vias in FDSOI based ultra-high density 3-D ICs[END_REF] Examples of GP doping conditions (N&P type) through thin channel for SOI devices. GP concentration cannot exceed the 1x1018 at/cm 3 in order to avoid top channel parasitic doping[START_REF] Sideris | Inter-tier Dynamic Coupling and RF Crosstalk in 3D Sequential Integration[END_REF].

Fig. 5 . 5 . 2

 552 Fig. 5.1 CIS Revenue breakdown by market in 2019 (Courtesy of [128])5.2 Principles and operation of a CMOS imager

Fig. 5 .

 5 Fig. 5.2 Passive CMOS pixel based on a single in-pixel transistor[START_REF] Theuwissen | CMOS image sensors: State-of-the-art and future perspectives[END_REF].

  concept was already popular in CCD image sensors and allowed the pixel to have considerable reduction of dark current, increase of saturation level and improved sensitivity. The architecture, displayed in Fig. 5.4, is the same as APS with the PPD connected to the readout circuit by means of an extra Transfer Gate (TG) and a Sense Node (SN). Furthermore, the 4T-APS architecture offers the possibility of implementing the Correlated Double Sampling (CDS) technique. With this, two sequential measurements of the output voltage are performed, one after reset of the readout node

Fig. 5 .

 5 Fig. 5.4 Active CMOS pixel based on an in-pixel amplifier in combination with a pinned-photodiode [30].

Fig. 5 . 6

 56 Fig. 5.6 Evolution of pixel size, CMOS technology node used to fabricate the devices and the minimum feature size of the most advanced CMOS logic process [30].

Fig. 5 . 7

 57 Fig. 5.7 Output voltage curve of a CMOS APS for a given integration time with the main noise components

Fig. 5 . 8

 58 Fig. 5.8 Equivalent circuit of the reset transistor connected at the SN.

Fig. 5 . 9

 59 Fig. 5.9 Realization of a CIS with planar (left) and three-dimensional partitioning (right)

Fig. 5 .

 5 10 (a). It consists of a 4T pixel partitioned in two tiers, the PPD and the TG at the bottom whereas the readout transistors are placed at the top. The two tiers are separated by a 200nm thick ILD, and a 3D contact connects the SN with the drain of the RST transistor and the gate of the SF. In the most critical case of inter-tier coupling, each one of the top devices is placed above the TG electrode as shown in Fig.5.10 (b).

Fig. 5 .

 5 Fig. 5.10 Cross-section of 4T pixel, partitioned in 3DSI. (b) In the most critical case, the top device is placed right above the TG electrode carrying a voltage that can go up to V DD =2.5V.

Fig. 5 .

 5 Fig. 5.11 (a) Impact of TG coupling (V TG =0-2.5V) on the input characteristics for NMOS and PMOS devices (b) Extracted thresholdvoltage shift versus TG voltage bias (-2.5V to 2.5V with 0.5V step).

Fig. 5 .

 5 Fig. 5.12 Impact of coupling (a) and temperature variation (b) on the top-tier SOI input characteristicsThe impact of both coupling and temperature variation can be expressed through the change in the device electrical parameters, i.e. the Threshold Voltage (V TH ), OFF-state current (I OFF ) and the ON-state current (I ON ). Fig.5.13 and Fig.5.14 show the comparison of V TH and I OFF , I ON respectively, for the two effects. It is evident that they are in the same order of magnitude whereas the slight prominence of the coupling impact regarding the Threshold Voltage Shift is due to the decrease of the temperature impact near the ZTC point at V TH . For switch transistors the most important

Fig. 5 .Fig. 5 . 5 . 4

 5554 Fig. 5.13 Comparison of the V TH variation of the top-tier NMOS and PMOS due to TG coupling or due to a 100K temperature increment.

Fig. 5 .

 5 Fig. 5.15 4T pixel read-out circuit (b) Chronogram of a read-out cycle.

Fig. 5 .

 5 Fig. 5.16 Shared pixels at photodiode layer: 2D (a.) vs. 3D (b.). Photodiode area (in grey) is increased by 44% when the three readout transistors are placed at the top tier. Courtesy of [4]..

  PhotodiodeActive Poly Contact 3D Contact

Fig. 5 .

 5 Fig.5.[START_REF] Jourdon | Hybrid bonding for 3D stacked image sensors: Impact of pitch shrinkage on interconnect robustness[END_REF] For TG corresponding to the SF above, the TG switches ON during the transfer of e-from PPD to the SN. The sampling is thus performed at t 1 , t 2 without read-out error. (b) In the scenario of a TG not corresponding to the SF above, the sampling can contain erroneous value due to TG coupling.

Fig. 5 .

 5 Fig. 5.19 (a) shows the readout error resulting from the non-corresponding TG-SF case versus the number of photo generated electrons at the SN, for three bias currents of the SF, from low to

Fig. 5 .

 5 Fig. 5.19 Read-out error of the in-pixel SF transistor versus the number of photo generated electrons at the SN resulting from (a) the SF-TG coupling of Fig. 5.18(b), and (b) the sensor temperature variation.

Fig. 6 .

 6 Fig. 6.1 (a) Stacked device structure in 3DSI (b) Zoom-in view of a top/bottom-tier device illustrating its intrinsic trans-capacitances.

Fig. 6 .

 6 Fig. 6.2 (a) Schematic 3D illustration of 2 stacked devices in 3DSI (b) respective cross-section cut by the symmetry axis For the bottom-tier device, none of the coupling capacitances is depended on the respective bias, as long as its body potential is shielded by its polarized electrodes. Consequently, for the stacked top-tier device the bias-dependency of the capacitances needs to be investigated. Considering at first stacked devices without relative misalignment, Fig. 6.3 demonstrates C-V TCAD simulations results, sweeping the top-tier device gate voltage in the range from -1V to 1V.

Fig. 6 . 3

 63 Fig. 6.3 Gate bias dependency of coupling capacitances for the stacked top-tier device with L G =1μm.

Fig. 6 . 4

 64 Fig. 6.4 Schematic illustration of the coupling capacitance C dbst /C sbdt along with its geometric dependencies (b) C dbst /C sbdt versus the top-tier device gate voltage

Fig. 6 .

 6 Fig. 6.5 (a) and Fig. 6.5 (b) respectively. Concerning the OFF-state, the C gbdt /C gbst capacitance can be decomposed in an outer fringe component C gbdt,of /C gbst,of as well as an inner fringe component C gbdt,if /C gbst,if as noted in Fig. 6.5 (a). On the contrary, when the top-tier device is ON, the inner fringe component of C gbdt /C gbst is screened by the inversion channel and the C ILD,eff capacitance is formed.

Fig. 6 .

 6 Fig. 6.5 C gbdt /C gbst components in (a) OFF-state of the stacked top-tier device and (b) in the ON-state Moving on to short channel devices and repeating the TCAD simulations, the coupling capacitances versus the top device gate voltage are shown in Fig. 6.6. Now the dominant coupling capacitance is C dbdt . The drastic reduction of the gate area is reflected in the values of C gbgt and the maximum values of C gbdt /C gbst , hence C gb-cht . On the other hand, an increase can be observed for C dbst /C sbdt with the downscaling of the gate length, however this capacitance remains very weak.

Fig. 6 . 6

 66 Fig. 6.6 Gate bias dependency of coupling capacitances for the stacked top-tier device with L G =30nm 6.1.2 Effect of 3D contacts on coupling capacitances

Fig. 6 .

 6 Fig. 6.7 (a) Schematic top layout view of two stacked devices with the respective cross-sections (b) AA' and (c) BB'.

Fig. 6 .Fig. 6 . 9 (Fig. 6 .Fig. 6 .•Fig. 6 .

 669666 Fig. 6.8 C dbdt decompositionThis capacitance can be divided into the components depicted in Fig.6.8. In detail, C db,RX-dt,RX is the capacitance between the bottom-tier device drain diffusion and the top-tier device drain diffusion, as analyzed in the previous section. It is mainly a parallel plate capacitance that depends on the ILD thickness and the RX layout pattern. The 3D contacts that extend vertically from the BEOL to the bottom active tier, create the additional capacitances C db,3DCO-dt,RX and C db, 3DCO-dt,CT . The former is the capacitance between the 3D contact and the top-tier device drain diffusion whereas the latter is the one between the 3D contact and the top-tier device drain contact. Therefore, the overall contribution of the 3D contact to C dbdt is

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].12 Structure simulated in TCAD for the 3D contact capacitance contribution evaluation.

Fig. 6 .

 6 Fig. 6.13 Variation of coupling capacitances when both devices are in cut-off mode, versus (a) gate length for constant gate width (W G =1μm) and (b) gate width for constant gate length (L G =1μm) The results reveal an approximately linear dependence of C gbgt on the gate length of both devices while the rest of the capacitances can be considered constant with L G . Additionally, all the capacitances increase with the gate width, as expected. To estimate the contribution of the 3D contacts to the total coupling capacitance of each top/bottom electrode pair, parasitic extraction was performed on the stacked device structure with the devices having the nominal gate length of 28FD (30nm).

Fig. 6 .

 6 Fig. 6.14 Simulation setup for the evaluation of the C dbdt capacitance component concerning the 3D contact

Fig. 6 .

 6 Fig. 6.15 Contribution of 3D contacts for each coupling capacitance with respect to the total one

Fig. 6 .

 6 Fig. 6.16 Variation of the coupling capacitances as a function of the distance between 3D contact and the top-tier device gate

Fig. 6 .

 6 Fig. 6.17 Contribution of the 3D contact capacitance component with respect to the total one, versus the distance between 3D contact and the top-tier device gate, for (a) C dbdt (b) C dbgt 6.2 Coupling-induced V TH shift modeling for stacked devices

Fig. 6 .

 6 Fig. 6.18 Schematic diagram of the Threshold voltage sensitivity of the front-gate versus the back-gate bias in an FDSOI device taking into account the effect of back-gate inversion.

4 )Front

 4 [START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].19 recalls the TCAD simulation results for the carrier concentration of N and P-type FDSOI MOSFETs under threshold voltage bias condition, varying the bottom SOI gate voltage from -20V to +20V with a step of 5V. From the extracted carrier concentration n(x) (and p(x)) for both types of the top-tier devices, the charge centroid x c can be calculated as The calculated charge centroid from TCAD simulations is shown in Fig.6.20 (a) as a function of the back-gate bias in the range of -20V to 20V, whereas a zoom-in view in the range of -2.5V to 2.5V is presented in Fig.6.20 (b). It is evident that the charge centroid gradually moves across the channel thickness according to the polarity and the strength of the back-gate bias, as explained

Fig. 6 .Fig. 6 .

 66 Fig. 6.19 Carrier concentration versus the distance along channel for NMOS (a) and PMOS device (b)In addition, Fig.6.21 shows the extracted charge centroid position versus the front gate bias of the top-tier device under zero bottom-tier device gate bias. It can be seen that the charge centroid position is placed around the center of the top-tier device channel until its gate bias overcomes the threshold voltage V TH where it moves significantly towards the front interface

Fig. 6 .

 6 Fig. 6.22 Simplified schematic view of the carrier centroid position under 1-D approximation (Long channel device).

Fig. 6 .

 6 Fig. 6.23 Comparison of calculated threshold voltage shift using the obtained centroid values and the extracted results from I-V, C-V simulations, versus the bottom SOI gate voltage.

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].[START_REF] Clermidy | Technology scaling: The CoolCube TM paradigm[END_REF] Comparison of calculated threshold voltage shift from eq. (6-7), eq.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF] and the TCAD results extracted with CC and max(dC gc /dV g ) methods, versus the bottom SOI gate voltage.

  Modeling the effective ILD capacitance of stacked devices (C ILD,eff )

Fig. 6 .

 6 Fig. 6.25 Extracted effective gate length versus the designed gate length for the bottom-tier device when (a) L Gtop =30μm (longchannel behavior) and (b) for sub-μm gate lengths of the top device.

Fig. 6 .

 6 Fig. 6.26 Schematic view of the "effective back-gate length" for the top-tier device when the bottom-tier device gate length is (a) smaller (b) equal and (c) larger than the top gate length.

Fig. 6 .

 6 Fig. 6.27 Electric field vector plot showing the shape of the flux induced by the bottom-tier device gate electrode of L Gbot =30nm to the top-tier device channel (a) w/ and (b) w/o the bottom-tier S/D regions. The extracted values for the effective back-gate length of top-tier devices with (w/) and without (w/o) the bottom-tier device source/drain regions are shown in Fig. 6.28. It can be seen that the presence of the bottom-tier source/drain regions reduces the effective back-gate length of L Gbot,eff of top-tier devices by a factor of ~1.6 for L Gbot <<L Gtop .

Fig. 6 .

 6 Fig. 6.32 Potential contour plot generated in TCAD for stacked devices with 𝐿 𝐺𝑏𝑜𝑡 𝐿 𝐺𝑡𝑜𝑝 = 0.001, in order to extract the fringe capacitance components of C ILD,eff . The bottom-tier device has been simulated (a) w/ and (b) w/o the bottom-tier S/D region, in order to assess their impact on C f .

Fig. 6 .

 6 Fig. 6.33 Electric field lines between two perpendicular electrodes.

Fig. 6 .

 6 Fig. 6.36 (a) shows the values for the effective ILD capacitance (C ILD,eff ) obtained from TCAD simulations (open circles), and our long-channel model. Furthermore, the resulting effective backgate length of the long-channel top-tier device is demonstrated in Fig. 6.36 (b) along with the extracted data from TCAD. The very good agreement between the two validates our modeling approach.

Fig. 6 .

 6 Fig. 6.36 (a) C ILD,eff and (b) effective gate length versus the designed gate length for the bottom tier device for a long channel top device. The symbols indicate the TCAD capacitance values in (a) from which the effective back-gate length for the top-tier device has been extracted in (b). The C ov component has been calculated from (6-13) and C f has been extracted from TCAD.

Fig. 6 .

 6 Fig. 6.37 Effective ILD capacitance versus the designed gate length for the bottom tier device and its respective parallel and fringe components as extracted from TCAD for (a) L Gtop =1μm and (b) L Gtop =30nm.

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].38 Variation of the empirical parameter a used in equation[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF][START_REF] Kawamura | Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization[END_REF][START_REF] Akiyama | MULTILAYER CMOS DEVICE FABRICATED ON LASER RECRYSTALLIZED SILICON ISLANDS[END_REF][START_REF] Sugahara | SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices[END_REF][START_REF] Kunio | Three dimensional ICs, having four stacked active device layers[END_REF][START_REF] Jourdon | Hybrid bonding for 3D stacked image sensors: Impact of pitch shrinkage on interconnect robustness[END_REF][START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF][START_REF] Batude | Enabling 3D Monolithic Integration[END_REF] versus the top-tier device gate length.

Fig. 6 .

 6 Fig. 6.39 shows the fringe capacitance component of C ILD,eff versus the top-tier device gate length, plotting the values obtained from TCAD simulation (with and without the bottom-tier source/drain region) together with the ones calculated from the model [Lacord 12]. It can be observed that the TCAD results deviate significantly from the calculated values and the difference becomes more pronounced as L Gtop reaches 30nm in the presence of the bottom-tier device source/drain regions.

Fig. 6 .

 6 Fig. 6.39 Variation of the fringe capacitance component of C ILD,eff with the top-tier device scaling. For the accurate extraction of C f ,L gtop is considered to be 1000x greater than L gbot .

Fig. 6 .

 6 Fig. 6.41 Schematic view of the (a) stacked devices with a misalignment of the bottom-tier device in its length direction and (b) the C ILD,eff components (C ov , C f ) under the misalignment.

Fig. 6 .

 6 Fig.6.42 shows C ILD,eff as well as its components (C ov ,C f ), extracted with TCAD versus misalignment of two stacked devices having gate length of 30nm (Fig.6.42 (a)) and 1μm (Fig.6.42 (b)). For both cases, the decrease of the overlap capacitance component follows the decrease of the overlapping area between the top-tier device channel and the bottom-tier gate given by[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF][START_REF] Kawamura | Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization[END_REF][START_REF] Akiyama | MULTILAYER CMOS DEVICE FABRICATED ON LASER RECRYSTALLIZED SILICON ISLANDS[END_REF][START_REF] Sugahara | SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices[END_REF][START_REF] Kunio | Three dimensional ICs, having four stacked active device layers[END_REF][START_REF] Jourdon | Hybrid bonding for 3D stacked image sensors: Impact of pitch shrinkage on interconnect robustness[END_REF][START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF][START_REF] Batude | Enabling 3D Monolithic Integration[END_REF][START_REF] Batude | 3D sequential integration: Application-driven technological achievements 202 and guidelines[END_REF][START_REF] Garrou | Handbook of 3D Integration[END_REF].

Fig. 6 .

 6 Fig. 6.42 Effective ILD capacitance versus the relative misalignment of the bottom tier device with respect to the top-tier device and its corresponding parallel and fringe components as extracted from TCAD for (a) L Gtop =1μm and (b) L Gtop =30nm

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].[START_REF] Xu | Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs[END_REF] Splitting the top/bottom-tier device length as well as the L Gbot,eff by the top-tier device axis of symmetry when there is relative misalignment.

Fig. 6 .

 6 Fig. 6.44 Capacitance component modeling under the relative misalignment of stacked devices splitting the overlap capacitance component by the top-tier device axis of symmetry

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].[START_REF] Le Maitre | Device and electromagnetic cosimulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix[END_REF] Charge-coupling factor versus misalignment for different gate length (L Gtop =L Gbot ) as extracted from TCAD simulations along with our modeling approach

Fig. 6 .Section 6 . 3 -Fig. 6 .

 6636 Fig. 6.46 (b). Considering first the simple case of the coupling between the bottom-tier device gate and the top-tier device drain, C 12 represents C dbdt , and C 2G , R 2G are the capacitance and resistance respectively of the top-tier drain electrode to the ground.

Fig. 6 . 25 )Fig. 6 .

 6256 Fig. 6.47 Two-port network configuration for the estimation of S-parameters via the transfer function transformation method.Consequently, the S 21 parameter is given by

Fig. 6 .

 6 Fig. 6.49 3D schematic view of a top-tier device stacked on top of the last metal of the iBEOL, having in-between an interiter GP. Additionally, the formed RC network is illustrated, with the blue lines indicating the remaining coupling components of C gbdt 6.4.1 DC modeling of inter-tier GP -Impact on coupling induced ΔV TH of the stacked devices

Fig. 6 .

 6 Fig. 6.50 Schematic cross-section view of two stacked devices with inter-tier GP and the capacitances forming among them

Fig. 6 .Fig. 6 .

 66 Fig. 6.51 recalls the structures under study of §4.2.2.a which were utilized to examine the DC decoupling behavior of the inter-tier Si-GP. The TCAD simulation results extracting C gb-cht from C-V characteristics of the top-tier device are shown in Fig. 6.52.

Fig. 6 .

 6 Fig. 6.52 Extracted C gb-cht values from the parasitic extraction versus the doping concentration of the inter-tier Si-GP.

Fig. 6 .Fig. 6 .

 66 Fig. 6.53 Coupling induced ΔV TH for top devices vs V Gbot for an inter-tier Si-GP with doping concentration of (a) 10 15 and (b) 10 18 cm -3 .

Fig. 6 .

 6 Fig. 6.55 Coupling induced ΔV TH for top-tier devices varying the doping concentration of the inter-tier Si-GP when the bottom-tier gate bias is at (a) 1V and (b) 2.5V.6.4.2 AC modeling of inter-tier GP

Fig. 6 .

 6 Fig. 6.56 Schematic view of the capacitance network forming with the integration of an inter-tier GP (b) corresponding equivalentcircuit of the GP shielding.

Fig. 6 .Fig. 6 .

 66 Fig. 6.57 Extracted capacitances C g1.gp , C gp,d2 , C g1.d2 versus doping concentration of the inter-tier Si-GP.

Fig. 6 .

 6 Fig. 6.59 Crosstalk vs. frequency for the top-tier device (a) in cutoff and (b) in saturation with an inter-tier GP made of silicon. Lines indicate the equivalent circuit results whereas symbols show TCAD data.

Fig. 6 .

 6 Fig.[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF].[START_REF] Ahn | Electrical coupling and simulation of monolithic 3D logic circuits and static random access memory[END_REF] Resistivity of the inter-tier GP extracted from the equivalent circuit (rectangles) compared to the experimental data in[START_REF] Mandurah | Phosphorus Doping of Low Pressure Chemically Vapor-Deposited Silicon Films[END_REF].

  les performances du dispositif / circuit est étudié en profondeur. Cette étude présente également l'impact des effets de couplage sur la performance d'un capteur d'image CMOS (CIS) en intégration séquentielle 3-D partitionné en différents niveaux, est examiné. Le CIS constitue un cas d'étude idéal des effets de couplage car il est constitué de parties très sensibles au bruit, tout en présentant une utilisation extrêmement attrayante de l'intégration séquentielle 3D pour l'industrie de semiconducteurs. Les chiffres de mérite les plus critiques sont donc analysés au niveau du pixel pour assurer le fonctionnement normal du circuit. Enfin, une approche de modélisation des effets de couplage entre les niveaux est présentée. Les modèles prédisent avec précision l'impact des effets de disposition sur le couplage capacitif inter-niveaux entre les dispositifs actifs, et peut être intégré dans les outils SPICE pour analyser des circuits 3-D monolithiques complexes et à grande échelle, en fusionnant le fossé entre les simulations de pré et post-disposition.

  Fig. 2.2 (b) illustrates the energy band diagram for the applied bias at the gate electrode,where E c is the conduction band energy level, E f is the Fermi energy level, E v is the valance band energy level and E i is the intrinsic energy level. The difference between the Fermi level E f and the intrinsic level E i is denoted ψ B and is given by

	𝛥𝑉 𝑜𝑥 = -	𝑄 𝑠 (𝜓 𝑠 ) 𝜀 𝑜𝑥	𝑡 𝑜𝑥	(2-4)
	and by defining the oxide capacitance per unit area, 𝐶 𝑜𝑥 =	𝜀 𝑜𝑥 𝑡 𝑜𝑥	, we can get the expression for the
	applied gate voltage
	𝑉 𝐺 = -	𝑄 𝑠 (𝜓 𝑠 ) 𝐶 𝑜𝑥	+ 𝜓 𝑠	(2-5)

𝐷 𝑜𝑥 , which is a function of the surface potential ψ s . From (2-2) and (2-3) we can write

  2

Table 2 .

 2

1 Maxwell's Equations

Table 2 .

 2

2 Basic passive elements

  𝑚 𝛿𝑉 𝐹𝐵 -𝑎 𝑠𝑐 𝐼 𝐷 𝜇 𝑒𝑓𝑓 𝛿𝑄 𝑖𝑡[START_REF] Moore | Cramming More Components Onto Integrated Circuits[END_REF](3)(4)(5)[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF][START_REF] Fahad | Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?[END_REF][START_REF] Robertson | High dielectric constant oxides[END_REF][START_REF] Geis | CRYSTALLINE SILICON ON INSULATORS BY GRAPHOEPITAXY[END_REF][START_REF] Colinge | ST-CMOS (STACKED TRANSISTORS CMOS):A DOUBLE-POLY-NMOS-COMPATIBLE CMOS TECHNOLOGY[END_REF][START_REF] Goeloe | VERTICAL SINGLE-GATE CMOS INVERTERS ON LASER-PROCESSED MULTILAYER SUBSTRATES[END_REF][START_REF] Kawamura | Three-Dimensional CMOS IC's Fabricated by Using Beam Recrystallization[END_REF][START_REF] Akiyama | MULTILAYER CMOS DEVICE FABRICATED ON LASER RECRYSTALLIZED SILICON ISLANDS[END_REF][START_REF] Sugahara | SOI/SOI/Bulk-Si Triple-Level Structure for Three-Dimensional Devices[END_REF][START_REF] Kunio | Three dimensional ICs, having four stacked active device layers[END_REF][START_REF] Jourdon | Hybrid bonding for 3D stacked image sensors: Impact of pitch shrinkage on interconnect robustness[END_REF][START_REF] Brunet | First demonstration of a CMOS over CMOS 3D VLSI CoolCube TM integration on 300mm wafers[END_REF][START_REF] Batude | Enabling 3D Monolithic Integration[END_REF][START_REF] Batude | 3D sequential integration: Application-driven technological achievements 202 and guidelines[END_REF]

	where g m is the transconductance, μ eff is the effective mobility and a sc is the Coulomb scattering
	coefficient. The normalized drain current noise is
	𝑆 𝐼 𝐷 𝐼 𝐷 2 = 𝑆 𝑉𝑓𝑏 (	𝑔 𝑚 𝐼 𝐷	)	2	(1 + 𝑎 𝑠𝑐 𝜇 𝑒𝑓𝑓 𝐶 𝑜𝑥	𝐼 𝐷 𝑔 𝑚	)	2	(2-22)
	which can be converted to an input-referred gate voltage noise as
	𝑆 𝑉 𝐺 =	𝑆 𝐼 𝐷 𝑔 𝑚 2 = 𝑆 𝑉𝑓𝑏 (1 + 𝑎 𝑠𝑐 𝜇 𝑒𝑓𝑓 𝐶 𝑜𝑥	𝐼 𝐷 𝑔 𝑚	)	2	(2-23)
	Gate									Gate
	Source			Drain	Source	Drain
	Δn									Δμ
	Substrate						Substrate
						Gate
		Source			Δn				Drain
						Δμ/Δn
		Substrate

Table 3

 3

	.1 Typical 28nm node power supply range and frequency band utilized by each tier
		V DD	Typical frequency band
	Digital	1V	> 1 GHz
	Analog	2.5V	< 1 MHz
	Mixed-Signal/RF	1V/2.5V	> 1 GHz

Table 3 .

 3

2 Bottom-tier NMOS gate biasing cases

Table 4 .

 4 2 Cases of bottom transistor gate bias.

Table 5

 5

	.1 2D vs 3D parasitic capacitances & CG

C SN + C GD [fF] C GS [fF] C out,SF [pF] CG (μV/e -) 2D

		4.432	1.093	2	34.319
	3D	4.48	1.137	2	33.942

  shows, 3D contacts can contribute by 18% to C dbdt /C sbst , 58% to C dbgt /C sbgt while for C gbdt /C gbst there is negligible contribution. Practically, this means that in C dbdt /C sbst and C gbdt /C gbst the vertical coupling dominates, whereas in C dbgt /C sbgt both vertical and horizontal coupling co-exist.

charge centroid position (nm) Top SOI gate voltage V Gtop (V) t si /2 V TH

  Parasitic extraction and modeling of coupling effects in 3DSI 168 with C ch =ε si /t ch being the capacitance of the hypothetically depleted silicon film with thickness t ch , i.e. the distance of the charge centroid position from the front interface. Consequently, the charge-

	5 6 7 Chapter 6 -coupling factor expression becomes
	𝑟 =	𝑑𝑉 𝑡ℎ,𝑡𝑜𝑝 𝑑𝑉 𝐺𝑏𝑜𝑡	=	2 3 4 𝐶 𝑜𝑥,𝑒𝑞 (𝐶 𝑏𝑜𝑥 + 𝐶 𝑠𝑖,𝑒𝑞 ) 𝐶 𝑏𝑜𝑥 𝐶 𝑠𝑖,𝑒𝑞	=	1 𝐶 𝑜𝑥 𝐶 𝑏𝑜𝑥 1 +	1 𝐶 𝑐ℎ 𝐶 𝑠𝑖 + 1 -	1 𝐶 𝑐ℎ
	Top SOI Oxide	0 1 Top channel 0 0.2	0.4		0.6	0.8 ILD	1
	V Gtop				x c				V Gbot
	t ox	t ch			t si -t ch			t box
					SiO		Si
					2
									6-6)

10 -1 10 0 L Gtop (μm)

	0.03
	0.1
	0.3
	1
	Top

SOI Effective Back-Gate Length L Gbot,eff (µm) Bottom SOI Gate Length L Gbot (µm)

  Fig.6.[START_REF] Kim | A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7μm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology[END_REF] Extracted effective back-gate length for the top-tier device versus the designed bottom-tier gate length, varying t ILD for L Gtop. =30nm. The critical effective bottom gate length increases as a function of the ILD thickness.On the other hand, the critical bottom gate length, L Gbot,critical , is a function only of the ILD thickness as shown in Fig.6.29. Thus, in our case (t ILD =130nm), L Gbot,critical ~300nm.Similarly to the effective length of the bottom-tier device gate electrode L Gbot,eff , an expression for the effective length of the top-tier device gate electrode L Gtop,eff , can be derived. Indeed, L Gtop,eff

	S top	Top SOI Effective	G bot G top Back-Gate Length L Gbot,eff (µm)	0.005 0.010 0.015 0.020 0.025 0.030	D top L Gtop =30nm	S top	L Gbot,critical t ILD (nm) 10 30 100 300	G top	D top
	S bot			D bot 1E-3 0.01	0.1	1	10
				Bottom SOI Gate Length L Gbot (μm)
	a.							b.
	is extracted from C ox,eff according to
				𝐶 𝑜𝑥,𝑒𝑓𝑓 =	𝜀 𝑜𝑥 𝑡 𝑜𝑥	𝑊 𝐺 𝐿 𝐺𝑡𝑜𝑝,𝑒𝑓𝑓		(6-10)
	with the results shown in Fig. 6.30.
				1
			L Gtop,eff (μm)	0.1
				0.01
				0.01			0.1		1
							L Gtop (μm)

Fig.

[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF]

.

[START_REF] Millet | A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing[END_REF]

Extracted effective back-gate length for the top-tier device versus the designed bottom-tier gate length, varying LGtop. Solid and open symbols indicate a structure w/ and w/o the bottom-tier S/D regions respectively. L Gtop TCAD Fig. 6.30 Effective front-gate length for the top-tier device versus its designed gate length.

  .31. With the above analysis, it is obvious that in order to efficiently model the effective lengths of both top-and bottom-tier gate which are virtually seen at the front/back interface of the top-tier device channel, analytic expressions for C ox,eff and C ILD,eff are needed.In the case where there is asymmetry between top-and bottom-tier device gate areas, the capacitance values in expression[START_REF] Oh | Looking at the materials and thermal alternatives for scaled, nextcentury VLSI/ULSI interconnects[END_REF][START_REF] Bohr | Technology for advanced high-performance microprocessors[END_REF][START_REF] Harriott | Limits of lithography[END_REF] have to be replaced with the effective ones, i.e., to be multiplied by the effective "back-gate" area seen by the top-tier device. Considering two stacked long channel devices as in Fig.6.31, when the bottom-tier device gate length is larger than the top-tier device gate length, the BOX capacitance of the latter is due to the overlapping area of the top-tier device channel over the bottom-tier device gate electrode, noted C ov in Fig.6.31 (a). Therefore, the top-tier device effective back-gate length L Gbot,eff remains constant at the value of L Gtop .On the contrary, in the case where the bottom-tier device gate length is smaller than the toptier device gate length, the BOX capacitance is reduced and can be split in a parallel plate capacitance component C ov as well as fringe capacitance components C f as shown in Fig.6.31 (b). Alternatively, the same concept is valid if there is an asymmetry in the gate width of the devices, so that the overlapping area of the top-tier device channel to the bottom-tier device gate electrode defines with W ov , L ov being the overlapping width and length respectively between the top-tier device channel and the bottom-tier device gate electrode. The maximum value of this capacitance is reached when the bottom-tier device gate electrode area is equal or greater to the top-tier device channel Since the device geometrical parameters such as gate mask width and length are not biasdependent, there shall be no discontinuity issues in a SPICE simulation even if we utilize regional functions. Such a function can has been introduced to handle the case of the overlapping capacitance component C ov , as

	𝐶 𝑜𝑣 =	𝜀 𝑜𝑥 𝑡 𝑜𝑥	𝑊 𝑜𝑣 𝐿 𝑜𝑣	(6-11)
	area and so (6-11) becomes
	𝐶 𝑜𝑣 =	𝜀 𝑜𝑥 𝑡 𝑜𝑥	𝑊 𝐺𝑡𝑜𝑝 𝐿 𝐺𝑡𝑜𝑝	(6-12)
	a. 𝐶 𝑜𝑣 (𝐿 𝐺𝑏𝑜𝑡 ) = { G top S top 𝜀 𝑜𝑥 𝑊 𝐺𝑏𝑜𝑡 𝐿 𝐺𝑏𝑜𝑡 , D top 𝑡 𝑜𝑥 𝜀 𝑜𝑥 𝑡 𝑜𝑥 𝑊 𝐺𝑡𝑜𝑝 𝐿 𝐺𝑡𝑜𝑝 ,	b. S top S top 𝐿 𝑜𝑣 < 𝐿 𝐺𝑡𝑜𝑝 G top G top 𝐿 𝑜𝑣 ≥ 𝐿 𝐺𝑡𝑜𝑝	D top D top	(6-13)
					C ov
	C ov			C f	C f
	G bot				G b
	S bot				D bot	S bot	D bot
	C ILD,eff .
	It becomes rather obvious that the parallel component of C ILD,eff , has to be proportional to the
	overlapping area of the top-tier device channel to the bottom-tier device gate electrode (Fig. 6.31
	(a)), given by the parallel plate capacitance equation

Fig. 6.31 Schematic view of the C ILD,eff components (C ov , C f ) when the bottom device gate length is (a) smaller and (b) larger than the top device gate length.

  where k=(C g1,gp C gp,d2 +C gp,d2 C g1,d2 +C g1,d2 C g1,gp )R gp,gnd .

				•
	f 𝐷,𝑚𝑎𝑥 =	1 4π	C g1,d2 k	•	(6-31)
				•
			•

ACKNOWLEDGEMENTS

I carried out my three years thesis research at IMEP-LAHC and CEA-LETI. During this time, I had the opportunity to meet experts from different laboratories, who were always willing and benevolent to

CONCLUSIONS AND PERSPECTIVES

Through this work the impact of noise and electromagnetic coupling has been investigated at both a device and a circuit level in a 3DSI process scheme. The dominant mechanism of the coupling effects has been identified as the capacitive one, contrary to the inductive which has been evaluated as weak between active devices.

Moreover, the inter-tier static coupling results in a threshold voltage modulation for the stacked devices due to their channel being exposed at their back-interface. The coupling induced threshold voltage shift of stacked devices, has been identified as the strongest interference as it can potentially increase leakage current/power and decrease the on-state current Exploring critical device parameters such as the V TH , I off and I on it has been demonstrated that their coupling-induced shift can be considered as tolerable concerning purely digital circuits. This implies that the static coupling effects are not widening much the process corners in digital design. On the contrary, in the case that digital are stacked upon analog devices, an ILD of 350nm thickness shall maintain the coupling effects to tolerable levels. On the bright side, the impact of static coupling on the LFN of stacked digital devices is negligible.

In contrast, analog devices stacked on top of either digital or analog devices are critical cases of inter-tier coupling with their coupling-induced ΔV TH resulting in higher values. Considering that analog circuits such as current mirrors and differential amplifiers require matched transistors, the high coupling-induced ΔV TH values prohibit the direct stacking above other devices. Hence, analog devices must be placed at the bottom-tier of a 3DSI process scheme, or employ an inter-tier GP so that their body potential is sufficiently decoupled from the aggressor devices.

LIST OF PUBLICATIONS

ABSTRACT

Impact of noise and electromagnetic coupling in sequential 3D technologies:

Study, modeling and impact on circuit performance

As an alternative to the scaling-down of transistor feature-size in order to keep up the Moore's law, three dimensional (3-D) integration technologies offer higher integration density, lower power consumption and provide a unique platform for heterogeneous integration of different activelayer materials through the vertical stacking of integrated circuit tiers. 3-D Sequential Integration, (also named 3-D monolithic integration or 3-D VLSI), is a type of 3D integration scheme, where the multiple stacked tiers are fabricated sequentially on top of each other on the same wafer. Each tier consists of active and BEOL layers insulated by interlayer dielectric (ILD) layers. The fundamental property that differentiates this technology is the very close distance between the 2 (or more) layers which introduces very small parasitic capacitances allowing digital signals to have a high frequency while at the same time being generated with a low energy. As a result, 3-D Sequential Integration brings new possibilities for mixed architectures with performances in both speed and low power consumption that cannot be easily met with other 3-D technologies schemes (TSV, copper to copper bonding etc.). However, the high frequency signals, the spatial localization, the strong interconnection density can all be a major source of interference between stacked tiers, modulating the expected behavior of devices as well as adding noise. Therefore solutions and techniques have to be found in order to limit these effects. This work, aims to respond to this challenge and ensure the technology robustness. The impact of the electromagnetic and noise interference between stacked tiers in 3-D Sequential Integration technology is thoroughly investigated in this work at both device and circuit level. To accomplish that, the most critical digital, analog and mixed-signal/RF designs have been selected to construct monolithic 3-D circuits. Experiments in conjunction with TCAD simulations reveal the coupling mechanisms responsible for the electromagnetic and noise propagation between stacked tiers. Additionally, the strength of the propagated signals is assessed and its impact on the device/circuit performance is deeply explored.This study also examines the impact of 3-D Sequential Integration is examined on the performance of a CMOS Image Sensor (CIS) partitioned in different tiers. The CIS serves as an ideal case study of the coupling effects as it consists of highly sensitive parts to noise while it presents also an extremely appealing use of 3DSI to the semiconductor industry. The most critical figures of merit are therefore analyzed at a pixel level to ensure the normal operation of the circuit. Lastly, a comprehensive modeling of inter-tier coupling effects is presented. The models predict accurately the impact of layout effects on the inter-tier capacitive coupling between active devices, and can be integrated in SPICE tools to analyze complex and large-scale monolithic 3-D circuits, merging the gap between pre-and post-layout simulations.

RESUME