Tomasz Toczek

Dominique Houzet

Stéphane Mancini

Modeling and Instrumentation of Memory Hierarchies using Functional Programming

We propose a methodology for the modeling, instrumentation and design space exploration with prototyping of complex designs exhibiting difficult to anticipate performance caveats. It relies on monadic functional programming as a design specification means. Its advantages lie in its model-of-computation (MoC) mixing capabilities, its suitability for both human-assisted and automatic design space exploration, as well as its relative ease of use compared to other functional approaches. We show those aspects on a case study involving memory fetches from a set of tomographic backprojection coprocessors working in parallel.

I. INTRODUCTION

Memory hierarchies have become an essential part of highperformance hardware, yet rely on spatial and temporal locality as well as other often difficult to control aspects of applications' memory reference patterns. It is therefore interesting to wisely choose the structure of a memory hierarchy, and to tune the parameters of the components involved to maximize the performances of the targeted applications. Such parameters include on-chip memory sizes, cache associativities, data replacement policies, possible prefetching mechanisms, and so on. Oftentimes, it is difficult to predict ahead of time which strategy will bring the best results.

A common way to tackle this problem is to specify the design using generic components, and use a set of scripts meant to test which combinations are the most efficient. While often being acceptable, this solution presents several drawbacks. The additional effort required to write the scripts themselves is non-negligible as soon as the design grows too complex for all the parameter combinations to be tested exhaustively. Also, third party components often ship with their own instantiation scripts (this is especially true of caches and networks-on-chip, for instance). As the number of such components involved in a project grows, it becomes increasingly difficult to use them together. Often, the optimal performances are obtained with a subtle combination of parameters of all the components involved that the individual instantiation scripts have trouble to find.

We propose a novel approach based on monadic programming. Alternative implementations and possible parameterizations of the components described by the designer are specified from the ground up. While still allowing heuristic policies for individual component instantiation, the different combinations of alternatives are also meant to be explored designwide, either be providing adequate feedback to the designer, or automatically through the use of stochastic optimization algorithms. We illustrate the approach through the extraction of relevant design information on a set of tomographic backprojection units, each being connected to a cache. The caches fetch their data from the external memory via an arbiter, which merges their requests if possible. Each of the described components is able to "tune" itself as necessary thanks to the facilities our approach allows.

II. STATE OF THE ART

The general reasons for employing functional programming for hardware description [START_REF] Sheard | Types and hardware description languages[END_REF], [START_REF] Sheeran | Hardware design and functional programming: a perfect match[END_REF] include its adequacy to handle the data representations likely emerging during such a task. Pattern matching can significantly ease the expression of graph transformations, and lambda calculus permits to write efficient and flexible combinator-based component libraries. What is more, it is suited for techniques such as staged programming (i.e. execution of code generated at runtime), embedded languages and quasi-quotation (i.e. seamless integration of a userdefined syntax within the language), which find their use quite naturally in the HDL domain or closely related domains such as hardware simulation.

Bluespec System Verilog (BSV) [3] is one of the most well known commercial tools employing functional programming as a foundation. It works on the RTL level, and brings most of the advantages of equational reasoning to hardware design. It is possible to describe very generic and flexible libraries in BSV, thereby increasing code reuse. Resulting designs are concise and little prone to errors, often showing very little amounts of glue logic.

Lava [START_REF] Bjesse | Lava: Hardware design in haskell[END_REF] presents itself as a Haskell library, and was an inspiration for our approach on many levels. It makes use of polymorphism and monadic programming as well. A given polymorphic construct can be used for tasks such as simulation, synthesis or verification depending on the actual type it is bound to. Lava designs are implemented on the RTL abstraction level.

ForSyDe [START_REF] Sander | System modeling and transformational design refinement in ForSyDe[END_REF] allows to specify designs using several models of computation. It typically takes high level specifications as an input and makes use of transformational design refinement to process them. It is discouraged to mix different MoCs within a design using this approach, however.

III. PRINCIPLES

A. Overview

Our approach is implemented as a Haskell library strongly relying on the language's class system. It has two rather distinct parts:

• A set of classes representing different MoCs (see section III-B), as well as a set of polymorphic functions and types on top of them • A set of engines, that is a set of types implementing the MoC classes, typically making use of the explorable state monad (see section III-C) The part of the program corresponding to the design description is meant to be expressed polymorphically, using one or more MoCs. This allows its different parts to be interpreted in several ways -as hardware, as software running on a dedicated processor, as a thread on a processor, etc. -and also makes it easier to embed one MoC into another, as we will later see.

A design is bound to an engine depending on what is meant to be done with it. The engines implementing a given MoC differ among themselves by their internal data representation, and hence criteria such as level of abstraction, simulation and performance estimation capabilities and accuracies, code generation capabilities...

B. Models of computation

A model of computation is simply a class providing the designer with the primitives for specifying a design. Those include basic element instantiation, communication means, as well as possible means of integration with other MoCs. For our case study, we chose to use two models of computation: single clock domain register transfer level (RTL) and imperative. It is possible to integrate imperative computations within a RTL design through processes, which behave much like their VHDL counterparts. Common aspects of models of computations, such as the possibility to use combinatorial nodes (ie. signals not needing associated registers), can be factorized by using a common "ancestor" class: Transfer is a type representing either an object, such as a combinatorial node, a register or a variable, or a computation on a set of such objects. A set of arithmetical and logical operators is defined on it. The ty argument is a representation of the "type" of the transfer (signed, unsigned, floating point, and so on). Type safety is therefore to some degree enforced by Haskell's typing system, but not entirely. For instance, the burden of checking the operand size consistency during arithmetic operations is on the engine. This is not a severe drawback, since such errors can easily be caught at the elaboration. (Dependently typed languages, such as Ωmega [START_REF] Sheard | Programming in omega[END_REF], could handle all the checks at compile time.)

Essentially, the models of computation contain the classical control structures one would expect of them. We define "#=", an affectation operator similar in behaviour to the ":=" or "<=" operators in VHDL. Its semantic varies depending on what it is used on. Applied on combinatorial nodes, it specifies the value taken on the next delta cycle. On registers, the value taken on the next clock cycle. On variables, the value change is immediate so it impacts the subsequent statements. Please also take note of the type of process, which embeds imperative processes in RTL designs. It underlines the fact that the user is expected to specify their design in a fully polymorphic way.

One key difference between such an implementation and other approaches such as Lava, beside the polymorphism of the user design specification, is the constraint of explorability on all the above classes. Explorable designs are instances of the Explorable class, described in the next section. Since even Transfer is an instance of Explorable, the designer is free to provide alternatives wherever she sees fit. Also, the nesting of MoCs in equivalent to the transformation of an explorable design into another explorable design, bringing a degree of flexibility hard to reach with ordinary instantiation or exploration scripts. What is more, exploration strategies are clearly separated from the design itself, just as they should.

C. Explorable state monad

The explorable state monad is one of the key elements of the proposed approach. From the outside, an explorable state simply offers the possibility to express alternative "implementations" of some monadic computations, and their relative probabilities: We also define ExpState, a variant of the state monad [7] instancing this class. The state monad used in conjunction with the do-syntax can be seen as a simple way to express sequences of statements in a functional language, defining a transformation of a "state" type. A statement may put a value in the monad (similar to returning a value in imperative languages), and also have some side effects on the state. This is often used to artificially recreate paradigms such as imperative or declarative programming in a functional context. When it comes to HDL design, the possible "state" types would express the design, in part or in whole, at a given abstraction level. Hence, using the explorable state monad instead of the ordinary one makes the design explorable. Our engines (that is, the instances of our MoC classes) are implemented through this explorable state monad: c l a s s E x p I n f o i n f o where e i C a l l : : ( s ->(a , s ) ) Essentially, it is a variant of the state monad whose encapsulated transition function acts not only on the state s, but also on an instance of the ExpInfo class.

-> i n f o -> s -> ( i n f o , a , s ) e i E q u i p
We also provide a set of exploration functions, by carefully defining some instances of the ExpInfo class. Envisaged exploration algorithms range from simple random walk or stochastic hill climbing to simulated annealing or genetic programming. The use of non-stochastic algorithms (such as simple hill climbing or exhaustive exploration) is also possible. Finally, user assisted exploration methods are also implementable. We limited ourselves to exhaustive exploration in order to obtain the results presented in this article.

The automatic optimisation algorithms typically require the user to provide an energy function from s to Float to minimize or maximize -possibly a closure. Diverse engines provide diverse kind of such functions, with different accuracy/speed trade-offs.

On important aspect of the proposed methodology is the possibility to mix several MoCs. This is done through nesting (see the nest and eiN est functions in the above listings). As can be seen, the way nesting is implemented makes it in practice virtually impossible to use any other instance of Explorable than ExpState.

IV. CASE STUDY

A. Described Design

We chose positron emission tomographic reconstruction (that is, volume reconstruction from raw MRI scanner data, called a sinogram) as a case study. The overall design schematic used can be found on the figure 1. It is composed of a set of tomographic backprojection coprocessors, their caches and a central arbitration mechanism. Each of the tomographic units processes several voxels, in order to maximize cached data reuse: the computation of each reconstructed voxel value involves 256 memory references to a 3D sinogram [START_REF] Gac | High speed 3d tomography on cpu, gpu and fpga[END_REF] stored in the SDRAM, and nearby voxels generate similar reference patterns during reconstruction. Tomographic units process nonrecovering yet adjacent sets of voxels, and therefore produce memory references to some degree similar. To make use of this . Fig. 2: Typical 3D reference pattern for a backprojection unit locality, the arbiter not only coordinates each cache's requests to the SDRAM, but also merges the ones that overlap.

The caches themselves are fully associative, but since they are rather small and contain only a few slots (see IV-B for the sizes used), this is not an unrealistic design choice. The sinogram itself is stored as a regular 3D array. The impact of the cache associativity and of the addressing scheme has already been studied [START_REF] Toczek | Another take on functional system-level design and modeling[END_REF], so we did not focus on those aspects in this paper.

All of the components were described using the RTL MoC with embedded imperative processes as necessary. In each of the blocks we have selected several performance-related parameters, and set several realistic possible values for each of them through the use of alternatives.

B. Results

As it stands, our approach permits to use the design in several ways:

1) It can be simulated directly using a simulator specified in Haskell (or another language by providing bindings) 2) It can be converted into RTL-level VHDL code, which in turn can be simulated using a third party tool or prototyped on a FPGA. In order for this method to properly work for exploration purposes, this simulation or synthesis needs to be called directly from the exploration function coded in Haskell, and performance data extracted and fed back to the tool. Hopefully, this is easily feasible from an implementation standpoint. We chose to do the former, but since our simulator is cycle and bit accurate, both approaches would have yield the same results. For larger designs, FPGA prototyping would be a wiser choice.

Several significant design parameters were selected and assessed for their influence on the overall performances. The resulting performance figures are shown on tables I and II. The ranges given are obtained by automatically varying the parameters which are not fixed for a given table cell.

The table I shows that short cache lines perform the best, despite the fact that burst accesses to the SDRAM are not pipelined in our setup. It can also be seen that 512 byte caches perform no better than their 256 byte counterparts. This is due to the fact that the back projection units iterate on psi (as seen on figure 2), and never "go back". Reuse mostly happens when a given sinogram element is required for several voxels in the block a backprojection unit reconstructs. If the cache is too small and overwrites those elements before they can be taken in account for all the voxels it impacts, trashing happens (one 128-byte slot cache case on the table I).

The table II is much more interesting because less predictable. First of all, we put some additional logic int the arbiter allowing it to detect overlapping requests, and fetch the data corresponding to those requests in a single burst. As can be seen, this bit of logic tends to help; given that the SDRAM bursts are not pipelined as is, this was to be expected. When this logic is removed, only exactly identical requests are detected, and grouped into a single burst. The block size parameter exhibits a somewhat stranger behavior. To keep things fair, when varying the block size, we also vary the number of tomographic units, in such a way that the whole system always computes the same overall block of 4 × 4 × 2 voxels. Increasing the block size of each backprojection unit increases to locality, while adding additional units increases parallelism. It is not immediately obvious which strategy is the most efficient. The table II shows the best trade offs are 4 units with 2 × 2 × 2 blocks with "simplified" request merging, and 2 × 4 × 1 blocks with "advanced" request merging. Situations of this kind arise frequently, and that very fact is one of the reasons for using approaches such as the described.

V. PERSPECTIVES

So far, we have merely evaluated a few parameter combinations and introduced a limited number of variable design parameters. However, on a setup such as the one used for our tests, a higher number of alternatives could have been specified:

• possible set associative caching (as done in [START_REF] Toczek | Another take on functional system-level design and modeling[END_REF]) • alternative sinogram addressing schemes (as done in [START_REF] Toczek | Another take on functional system-level design and modeling[END_REF]) • the choice of the permutation of coordinates for sinogram indexation should be left the tool • the arbiter could be further simplified by possibly removing the request grouping logic • several content replacement policies could have been implemented in the cache model • several prediction mechanisms could be implemented in the cache model • the whole cache hierarchy could have been possibly made 3D aware While keep a small number of variable parameters can be justified in order to ease the interpretation of the results, it would be equally interesting to implement a great number of those parameters as alternatives, and try and stress stochastic exploration algorithms using prototyping on a very large design space. This is what we aim for in the short term.

VI. CONCLUSION

We have presented a methodology allowing to describe, parametrize and instrument IPs in a design. Its strong points reside in the easy specification of alternative implementations of parts of the design, hereby efficiently dealing with difficult optimization cases arising in complex systems. The alternative implementations are effectively "hidden" in the hardware blocks they concern, making it possible to design efficient black boxes capable of adapting themselves to the context they will be used in. The approach does not impose any particular level of abstraction, and several models of computation can be seamlessly mixed within a design. Future prospects include the evaluation of stochastic optimization methods on very large design spaces expressed in such an approach.

  c l a s s E x p l o r a b l e em => W i t h A f f e c t a t i o n em where ( # = ) : : T r a n s f e r t y -> T r a n s f e r t y -> em ( ) c l a s s W i t h A f f e c t a t i o n em => WithNodes em where --. . . ( c o m b i n a t o r i a l node h a n d l i n g p r i m i t i v e s ) c l a s s WithNodes em => I m p e r a t i v e em where --. . . ( i m p e r a t i v e c o n t r o l s t r u c t u r e s ) c l a s s WithNodes em => RTL em where p r o c e s s : : ( f o r a l l em ' . I m p e r a t i v e em '=>em'()) ->em ( ) --. . . ( r e g i s t e r i n s t a n t i a t i o n , and s o on )

  c l a s s Monad m => E x p l o r a b l e m where e q u i p r o b a b l e : : [m a ] -> m a n e s t : : ( S t a t e s 1 a -> m a ) -> E x p S t a t e s 1 a -> m a


Wenbo Shen
email: wenbo.shen@intel.com

Xinxin Zhang
email: xinxin.zhang@intel.com

Qigang Wang

Shunyu Zhu

Xiangbin Wu

Prabhat Gupta

Dong Liu

An FPGA-Based Emulation Platform For Optical-Enabled System

This paper introduces an FPGA-based emulation platform for optical-enabled computer system researches. As electrical links are reaching their physical limits, optical technologies begin increasingly to play a role in computer systems by enabling high speed IO, optical memory extension and system bus links. With its excellent latency, bandwidth, power and scalability performance, optical links will move steadily closer to the processor in the future. New design challenges and tradeoffs must be considered at the system level to make a balanced and efficient system from both power and cost perspectives. With an IO-centric research methodology in mind, we try to explore the broad design space of optical-enabled computer systems by implementing an FPGA-based emulation platform as the research vehicle. On this platform, high speed IO device is connected to an FPGA-based IO controller through optical fiber and the IO controller talks to the FPGA-based synthesizable processor core via PCIe link. With the in-field-configuration characteristic of FPGA, it gives us the freedom to modify both the CPU part and the IO part of the emulated system. The first system implementation is up and running with the an example application at this stage.

I. INTRODUCTION

Optical links have been playing a role at the metropolitan and wide area distance scales and is becoming a good alternative in LAN and cluster networks [START_REF]White paper of Apple Computer Inc[END_REF], [2]. Thanks to its excellent latency, bandwidth, power and scalability characteristics, system architects expect that optical links will approach the processing element even closer by enabling high speed IO, optical memory extension [START_REF] Katayama | Optical Interconnect Opportunities for Future Server Memory Systems[END_REF] and system bus links [START_REF] Petracca | Design Exploration of Optical Interconnection Networks for Chip Multiprocessors[END_REF], [START_REF] Kirman | Leveraging Optical Technology in Future Bus-based Chip Multiprocessors[END_REF], with IO system as the first focus [START_REF] Benner | Exploitation of optical interconnects in future server architectures[END_REF]. Amdahl's balanced system law indicates that for a balanced system, a 1MB IO throughput needs a 1MIPS processing power. Accordingly, with the high data throughput [7] and low latency brought in by optical IO subsystem, we may need to revisit the design methodologies and architectures for the CPU, the optical IO subsystem and the interconnection between them together with the whole SW stack to make a balanced and efficient system. We don't see any processor with native optical IO links in mass production yet, so we think optical technologies tightly coupled with the computer system are still in exploration stage and there should be a broad design space to look into.

Both industrial and academia researchers are working around optical technologies and come up with new ideas and innovative technologies [START_REF] Lemoff | MAUI: Enabling Fiber-to-the-Processor with Parallel Multiwavelength Optical Interconnects[END_REF]. Each new idea and technology needs to be evaluated exhaustively before it's adopted seriously by industry. Simulation and emulation are two most commonly used approaches when architects evaluate new technologies.

However, with the current trends of multi-core, system-on-chip (SoC), diversified IO devices with ever increasing complexities, both approaches are being challenged.

Simulation is flexible and cost effective, but it usually suffers from slow simulation speed and insufficient simulation model accuracy. FPGA emulation is seen as a solution to this problem. The flexibility, speed, high integration level, and capacity of modern FPGA qualify itself as an ideal choice for system level emulation [START_REF] Wang | Intel Atom processor core made FPGA-synthesizable[END_REF]. Emulation can run orders of magnitude faster than simulation and is able to accurately model the full system. We adopt this approach to address our research purposes, with a goal to make the emulation platform flexible enough to explore the design space at both the processor side and the IO side.

In this paper, we will share our view of the system with optical IO links first, then we will present the abstract system model and our research methodology, which is followed by an FPGA-based research platform implementation. We will describe our first experiment done on this platform and conclude the paper by briefing the next research topics.

The key contributions of this paper are

• IO-centric research methodology. We think when optical links are introduced in the computer system with 100Gbps or even higher throughput, the fundamental design methodology and system architecture should be revisited. IO subsystem will be as important as the processing element and more innovations should be done at the IO side. • An FPGA-based emulation platform implementation. To make the research platform as flexible as possible, we use FPGA as one of the building blocks of the platform. We implemented both the processor core and the IO controller on FPGAs to give us the flexibility to change them when needed.

II. OUR VIEW ON OPTICAL-ENABLED SYSTEM AND RESEARCH MOTHODOLOGY

In the next 5-10 years, people will have many reasons for higher bandwidth. Lots of attractive applications that significantly improve user experiences are depending on huge volume of data capturing, transfer, storage, and reconstruction. People will have more and more electrical devices, such as High Definition (HD) video camcorders, HD monitors, Mobile Internet Device (MID) s, laptops and other handheld devices, and they want to be able to share data between these devices smoothly, quickly and easily. All these user requirements call for higher bandwidth. But existing electrical cable technology in mainstream computing devices is approaching the practical limit for higher bandwidth and longer distance, due to the signal degradation caused by electro-magnetic interference (EMI) and signal integrity issues. Higher bandwidth can be achieved by sending the signals down with more wires, but apparently this approach increases cost, power and difficulty of PCB layout, which explains why serial links such as SATA, SAS, USB are becoming the mainstream. However optical communications do not create EMI by using photonics rather than electrons, thus allowing higher bandwidth and longer distances. Besides, optical technology also allows for small form factors and longer, thinner cables.

It's important to design flexible and effecient protocol to leverage the raw bandwidth enabled by optical fiber. Intel has announced its high speed optical cable technology, Light Peak (LPK) [START_REF] Paniccia | A Hybrid Silicon Laser: Silicon photonics technology for future tera-scale computing[END_REF], which delivers high bandwidth starting at 10Gbps and has the ability to multiplex multiple protocols simultaneously over a single optical cable.

Combining the high bandwidth of optical fiber with Intel's practice to mulplex multiple protocol over a single fiber, optical technology may change the landscape of IO system design in the future. It's possible that most of the legacy IO protocols can be tunneled by optical-capable protocols, so some of the legacy IO interfaces can be converged to one single optical interface, significantly simplifying the form factor design of computers. This change in IO system will definitely affect the design of systems. The ultimate goal of system architects is to make a balanced and efficient system, on both power and cost grounds. It makes no sense to have a high throughput IO system with insufficient processing power or overloaded interconnections between IO system and the processor.

Mobile and handheld devices are two fast growing market segments which attract interests from processor vendors including Intel and they are our targets for application selection. For mobile and handheld devices, user interface and IO are two important factors besides computing power that affect end users' purchase decision. Taking power into account, it's possible that more carefully tuned IO workload offloading engines will be integrated into the IO controller, saving the power to move the data from IO a long way to the system memory.

Because we think that the future computing devices, especially low-end and consumer electronics will be more IOcentric, our research philosophy is an IO-oriented one. We try to identify the future IO devices and their usage models first, then we investigate the requirements of the interconnection from the IO's standpoint, after that we move up to the processor level, trying to figure out the needs of processing power and thus the best architecture for it.

With this philosophy in mind, an optical-enabled system model can be illustrated in Fig. 1. There are four main components in this figure, the IO devices, the IO controller which connects to the IO devices through optical fiber, the processing Fig. 1: Abstract model of the optical-enabled system unit and the interconnection between the IO controller and the processing unit, whatever it can be implemented as. We are looking at the system from IO to processor as shown by the arrow.

III. THE EMULATION PLATFORM IMPLEMENTATION

We tried to map the abstract model dictated in Fig. 1 to a real implementation. FPGA is a popular prototyping platform and it's a natural choice for us to implement Intel Architecture (IA) cores and the IO controller since we want the full freedom to change the core and the IO controller when doing experiments.

As for the IO device, after evaluating a few options, we decided to take SATA HDD as the starting point because HDD is an important component in modern computer systems which has remarkable influence on the whole system performance if the storage traffic is heavy.

We spent quite a long time to evaluate the possible interconnection implementations between the processor and the IO system. Based on the facilities available in the current system, we have a few alternatives, such as Intel Front Side Bus (FSB), Intel QuickPath Interconnection (QPI), PCIe. In an ideal scenario, the IO system should be as close to the processor as possible, and it should meet the bandwidth and latency requirements. FSB or QPI may be a better solution than PCIe because of their advantages of latency and bandwidth as CPU bus between CPU and chipset, but in the real world, we have to balance the requirements with the development effort. FSB and QPI links are much challenging to develop, and PCIe is an evolving open IO standard with good bandwidth capacity and moderate development effort. We think PCIe is an appropriate candidate to begin with.

After all component selections are done, we get the full emulation platform implementation as illustrated in Fig. 2 (we keep a copy of Fig. 1 in this figure to make the mapping clear). Synthesizable IA cores are hosted by an FPGA module, which is plugged into the CPU socket, working as a real CPU to boot unmodified Linux distributions (Ubuntu, CentOS, OpenSuse) as well as WindowsXP and run applications. The SATA HDD connects to the IO controller via optical fiber on which the Intel Light Peak technology runs. The IO controller is implemented with FPGA also and is connected with the IA core through PCIe. Fig. 2: Map the abstract model to the real implementation Fig. 3 shows the picture of the real system when the system is booting BIOS. On the in-socket module which is hosted by a Xeon-based server, there are three Altera PFGA devices, marked as FPGA1, FPGA2 and FPGA3, with FPGA1 to implement the FSB protocol so that the IA core can talk with the chipset. The other two FPGAs, FPGA2 and FPGA3, are used to implement IA cores and we put two Pentium cores into them. The capacity of the FPGA2 and FPGA3 is big enough to accommodate other IP blocks. To make the Pentium core run on the Xeon based server, we modified the system BIOS and implemented some FSB features which are not present on a Pentium silicon.

The first processor core used in our platform is the sec ond generation Pentium. It is a 32bit in-order 5 stage dual pipeline processor supporting the IA32 instruction set in cluding floating point instructions using an pipelined floating point module. It is equipped with two separate level 1 caches for code and data and implements the MESI protocol for use in multi-processor environments. It also includes local Advanced Programmable Interrupt Controller (APIC) and a processor bus supporting dual processors. Although Pentium is not a modern processor design, the current trend of multi-core draws much attention back to such simple cores [START_REF] Seiler | Larrabee: a many-core x86 architecture for visual computing[END_REF]. Atom is the next processor to be used in this platform. It is a two-way Hyper-Threading in-order pipeline processor supporting the complete This platform supports all synthesizable IA compatible processors and any optical IO device theoretically. As for the PCIe interconnection, we may use reserved fields in the protocol packets for any enhancements we want. The flexibility of FPGA allows one to make quick change to the system and evaluate the effect immediately, which offers a much shorter turnaround cycle time than software simulation. And, data collected with a real emulation platform is more convincing to architects.

To the best of our knowledge, there is no such an emulation platform for optical-enabled system as flexible to this level.

IV. THE FIRST EXPERIMENT WITH THE PLATFORM Fig. 4 shows the main components of our first experiment. Some of them run on the host and some of them run on FPGA boards as illustrated by the figure. To make the system up and running is our initial goal, without any performance considerations yet. Essentially, we implemented SATA traffic over Light Peak protocol on optical fiber. At the software side, we implement a standard SATA driver which provides APIs to applications. Take HDD write as example, when application writes to SATA SSD, these APIs are responsible for preparing SATA Frame Information Structure (FIS) packets in memory , and call host controller driver to send these FIS packets to downstream device. On board 1, a Light Peak host controller is integrated in FPGA 4 and communicates with processor over PCIe link. The host controller gets the FIS packets from memory, encapsulate them into Light Peak packets, and sends them to board 2 over optical fiber. On board 2, a Light-Peak-to-SATA adapter is implemented in FPGA 5. The adapter resolves the Light Peak packets from board 1 and sends these FIS

V. CONCLUSION AND FUTURE WORK

We presented a view of the future computer system enabled by optical technologies and we built this FPGA-based emulation platform as the first implementation of the research vehicle. We are trying simple data copy on this platform now. The use of this platform greatly accelerates prototype implementation and testing. As the next step we plan to tunnel more legacy protocols, such as Ethernet, DisplayPort over the optical links, and study how to improve the system QoS, power management, processor utilization and system latency. We can find a more efficient SW/HW partitioning and a host interface with higher convergence level for the system architecture.

We will replace the PCIe interconnection with more aggressive ones such as Intel QPI or even direct optical link to the CPU package enabled by silicon photonics. Without the bottleneck of bandwidth introduced by PCIe link, we can analyze the impact to system architecture when optical IO bandwidth scales from 10Gbps to 100Gbps.

Fig. 3 :

 3 Fig.3shows the picture of the real system when the system is booting BIOS. On the in-socket module which is hosted by a Xeon-based server, there are three Altera PFGA devices, marked as FPGA1, FPGA2 and FPGA3, with FPGA1 to implement the FSB protocol so that the IA core can talk with the chipset. The other two FPGAs, FPGA2 and FPGA3, are used to implement IA cores and we put two Pentium cores into them. The capacity of the FPGA2 and FPGA3 is big enough to accommodate other IP blocks. To make the Pentium core run on the Xeon based server, we modified the system BIOS and implemented some FSB features which are not present on a Pentium silicon.The first processor core used in our platform is the sec ond generation Pentium. It is a 32bit in-order 5 stage dual pipeline processor supporting the IA32 instruction set in cluding floating point instructions using an pipelined floating point module. It is equipped with two separate level 1 caches for code and data and implements the MESI protocol for use in multi-processor environments. It also includes local Advanced Programmable Interrupt Controller (APIC) and a processor bus supporting dual processors. Although Pentium is not a modern processor design, the current trend of multi-core draws much attention back to such simple cores[START_REF] Seiler | Larrabee: a many-core x86 architecture for visual computing[END_REF]. Atom is the next processor to be used in this platform. It is a two-way Hyper-Threading in-order pipeline processor supporting the complete Core 2 Duo compatible instruction set architectures including Streaming SIMD Extension (SSE) 3 and Intel64. It is built for low power devices and targets mobile and low-cost PC market segments.IO board No.1 is connected to the motherboard through PCIe interface and an optical fiber links IO board No.1 and IO board No.2. There is an FPGA on each of the IO board. Since the protocol running on the optical fiber is Intel Light Peak,

Fig. 4 :

 4 Fig. 4: Components of the SATA HDD experiment

ACKNOWLEDGMENT

We would like to thank Bhushan Chitlur, Nelson Ijih, Arthur Sheiman, Rolf Kassa, Michael Konow, Zhiyuan Zhang, Lu Cao, Qianying Zhu, and XtremeData for their help and contribution to this project.


O Hammami
email: hammami@ensta.fr

X Li

L Burgun

S Delerse

Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator

Keywords: Very large scale MPSOC, multi-FPGA, NoC I

Future generation embedded multicore will be based on hundreds of processors connected through Network on Chip (NOC) . Design productivity of embedded multicore is a major challenge for the semiconductor industry. In this paper, an automatic very large scale NoC design methodology based on FPGA IP is proposed to accelerate the embedded multicore design productivity using very large scale multi-FPGA platform emulation. The large scale multiprocessor is divided into pieces of FPGA IP. Local NoC is designed for each FPGA IP. Then a top level NoC connects all the local NoCs together to form the large scale multiprocessor. In this paper we extend our previous work to reach 2400-cores NoC based multiprocessor which is generated using this methodology within 3 days.

INTRODUCTION

ITRS Semiconductor roadmap [START_REF]International Technology Roadmap for Semicoductors(ITRS) )[END_REF] projects that hundred of processors will be needed for future generation embedded multicore designs. Among the various challenges of embedded multicore design, productivity with constraints is paramount [START_REF] Jerraya | Multiprocessor Systems-on-Chips[END_REF]. Very large scale multiprocessor (VLSM), which has beyond 512 PEs or even more [START_REF] Kelm | An Architecture and Scalable Programming Interface for a 1000-core Accelerator[END_REF], is very difficult to be implemented on to ASIC or FPGA circuit because of its complexity and the lack of EDA supported design framework. To the best of our knowledge there is no reported work in the world in 2010, besides the RAMP project, for prototyping multiprocessor larger than 512 cores on multi-FPGA platforms or on single ASIC chip. [START_REF]CHIPit Platinum Edition -ASIC Emulation and Rapid Prototyping System[END_REF] To our best knowledge, there is no report on either high level modeling (e.g. SystemC) or high level performance evaluation of VLSM. As the simulation wall blocks the VLSM design path, FPGA platform based emulation is selected as the only solution for billion cycle applications. Automatic design work flow is mandatory at this scale to accelerate the design and debug process.

In this paper we describe our automatic design and prototyping methodology, which is based on FPGA IP reuse. The large scale multiprocessor is divided into pieces of FPGA IP, which fills one FPGA device. Local NoC is designed for each FPGA IP. Then a top level NoC connects all the local NoCs together to form the large scale multiprocessor. A 2400-core NOC based embedded multicore is generated and implemented on a large scale multi-FPGA emulation platform of 100 FPGA circuits. Comparing to RAMP Blue framework, our system is purely NoC based, which is more flexible in communication architecture based on multi-FPGA Platform.

II. RELATED WORK

Emulation and FPGA-based emulator have been recognized as efficient techniques for the performance evaluation and validation of multiprocessors. In [START_REF] Li | NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis, Industrial Embedded Systems[END_REF] design space exploration of multi-processor on multi-FPGA platform [START_REF]CHIPit Platinum Edition -ASIC Emulation and Rapid Prototyping System[END_REF] have been conducted with masters on chip, network on chip on a second chip and slaves on a third chip. Automatic design space exploration of multiprocessor on chip on a single large scale FPGA chip have been conducted [START_REF] Mouhoub | MOCDEX: Multiprocessor on Chip Multiobjective Design Space Exploration with Direct Execution[END_REF] with automatic tuning and test of the multiprocessor. The combined effects of compiler, architecture and place and route have been addressed for a single chip in [START_REF] Hammami | Heterogeneous Multiprocessor on chip Compiler, Architecture, PLace and Route Design Space Exploration[END_REF]. A complete network on chip emulation platform has been proposed in [START_REF] Genko | A Complete Network-On-Chip Emulation Framework[END_REF] and a multiprocessor platform in [START_REF] Nava | An open platform for developing multiprocessor SoCs[END_REF]. Finally large scale multiprocessor project have emerged in [START_REF] Chung | Mai Virtualized Full-System Emulation of Multiprocessors using FPGAs[END_REF].

The state of the art of 512+ cores multiprocessor is restricted in 2010 to the University of California Berkeley project, RAMP (Research Accelerator for Multiple Processors) [START_REF] Wawrzynek | RAMP: Research Accelerator for Multiple Processors[END_REF].

Design flow

Not reported Full automatic

The RAMP project has evolved through different versions in the communication paradigm and in the number of processors.

To the best of our knowledge, the RAMP blue [START_REF] Asonvic | RAMP: Research Accelerator for Multiprocessors, 2nd Workshop on Architectural Research Prototyping[END_REF] and our platform [START_REF] Hammami | Automatic Design Methodologies for Large Scale MPSOC and Prototyping on Multi-FPGA Platforms[END_REF] are the only two multiprocessors which have surpassed the milestone of 512 cores on multi-FPGA platforms. The basic idea of multi-FPGA platform emulation is the same, while the approaching framework is quite different. Although Berkeley decided to go for its own board designs we selected industry-class emulator in order to focus on the methodologies and design flows. In this paper we address a study case of 2400-core MPSOC using our automatic NoC design methodology based on L-T level topology and multi-FPGA platform emulation.It is important to note that our project is based on EVE multi-FPGA platform which is presented in section IV; there are no interconnection constraints. The emulator allows any type of communication architecture to be implemented. So comparing to RAMP framework, our system can be fully NoC based. And consequently, our communication architecture is more flexible. More NoC topologies can be used in our system design on both local and top levels of NoC architecture.

B. FPGA IP architecture

This important multiprocessor architecture requires efficient IP design and reuse. Although we use Xilinx EDA tools and IPs for the Xilinx target Virtex-5 LX-330 no multiprocessor soft IP is available which matches our need. The architecture of the FPGA IP is based on a mesh-based network on chip connecting 24 processors organized as with 3 processors and 2 SRAM on chip memories per switch. Mesh is chosen as the NoC topology for an easy multi-FPGA implementation in this case.

C. Emulation Platform: EVE Zebu Server

Large scale emulators are composed of dozens of large scale FPGA chip and are unbeatable in terms of performance accuracy tradeoffs. We target large scale emulator such as the Eve Team [START_REF]EVE TEAM Zebu-XXL Emulation platform[END_REF] Zebu Server emulation platform composed of up to 100 Xilinx Virtex-5 LX330 chips. ZeBu-Server is a flexible, scalable emulator, with a capacity up to 1 Billion ASIC gates. Providing high bandwidth and multi-MHz performance at any level, ZeBu-Server primarily aims at largescale, multi-core chip and system emulation applications. The automatic workflow of our VLSM multiprocessor design is presented in the Figure 5. Design automation tools of 3 commercial companies are combined together to generate our multi-FPGA MPSoC. The Xilinx EDK tool is used to generate our FPGA multiprocessor using Xilinx IPsOnce the RTL files of FPGA are generated, they are reused for the multi-FPGA large scale multiprocessor synthesis, which can largely reduce system design time.erent NoC files are synthesized for each FPGA on different FPGA chips of Zebu platform. These NoC RTL files are generated by Arteris NoCcompiler tool, which allows the export of NoC using the Arteris Danube Library. Eve Zebu compiler takes the EDIF files converted by Xilinx synthesis tools for the implementation. Different FPGA IPs are analyzed and distributed onto FPGAs. Xilinx place and route tools are used to generate the download bit files of FPGA. This phase can be parallelized to reduce the turnaround time. Finally the compiled execution files and download bits files are downloaded to EVE Zebu Server multi-FPGA platform using Zebu download tools. The execution time is recorded after the execution. There are 100 Xilinx Virtex 5 LX330 FPGAs available on the Zebu Server platform we used. By duplicating the FPGA IP onto the 100 FPGAs with 2 FPGA IPs on each FPGA, a VLSM of 2400-cores is generated automatically. In the Figure 2, each rectangle represents one FPGA IP. The general architecture and interconnection between FPGA IPs are presented in the figure. The global architecture stays as 10x10 cluster mesh topology. Based on the local NoC architecture of FPGA IP, two more external input and output ports are added to each switch to connect their neighbor FPGA IPs. Our architecture is symmetrical and based on the local NoC, which makes it a good candidate for design modularity and IP based design and reuse. Table I shows the resource utilization of FPGA IP on each FPGA circuit.

D. Automatic Design Flow based on multi-FPGA platform

IV. FUTURE WORK

We have currently achieved the hardware design and validation of directory-based cache coherency support for our embedded multicore. This next version will be evaluated using multicore benchmarks from the embedded world EEMBC [START_REF] Eembc | MultiBench™ 1.0 Multicore Benchmark Software[END_REF] and eventually to general purpose multicore benchmarks [START_REF] Bienia | PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors[END_REF].

V. CONCLUSION

Next generation embedded multicore will be based on hundreds of processors. Network on chip design is very complex and in order to reach efficient working silicon in reasonable time large scale prototyping is needed. We proposec an automatic design methodology based on FPGA IP and multi-FPGA platform emulation. This elegant and technology scalable technique eases the implementation of 2400 cores multiprocessors on large scale commercial emulator. We plan to complete this work with directory based cache coherency support and intensive benchmarking. We believe that time has come fort EDA to move up the scale and integrate with parallel computer architecture, automatic parallelization compiler and operating system research results to efficiently tackle in a unified and integrated framework the design productivity gap.

Figure 1 FPGAFigure 2

 12 Figure 1 FPGA IP architecture with 24 MicroBlaze processors and 16 SRAMs

Figure 3 (

 3 Figure 3 (a)Processor Tile (b) MicroBlaze core block diagram MicroBlaze soft IP is used as basic processor element in SSM IP. It is a 32-bit 5-stage single issue pipelined Harvard style embedded processor architecture provided by Xilinx as part of their embedded design tool kit (ED. The MicroBlaze processor is flexible, and gives the user control of a number of features such as the cache sizes, interfaces, and execution units like: selectable barrel shifter (BS), hardware multiplier (HWM), hardware divider (HWD), and floating point unit (FPU). Our SSM design is OCP-IP compliant which implies that we can change processor IP by any other OCP-IP compliant processor IP while leaving the overall design identical. The OCP-IP protocol is used for the communication between the processors and Network on Chip. A FSL-OCP network interface is designed in order to make MicroBlaze processor compatible to OCP-IP protocol as shown in Figure (a). This interface gets data from MicroBlaze processor through FSL link and transfers data to SRAM through Network on Chip under OCP-IP protocol. It encapsulates and decapsulates data between FSL links and OCP-IP bus interface.A NoC communication service library of driver is written in C for the FSL-OCP network interface to support OCP-IP basic and extended communication modes. As FSL link works like 32 bits FIFO interface, the address and data are transferred in two phases between MicroBlaze processor and FSL using basic micro C code 'putfsl()' and 'getfsl()' in EDK library. In the service library, 5 OCP-IP compliant communication modes are supported: Write, Read, Read Exclusive, Write Non-Post and Write Conditional. Parallelized application codes use these drivers for data communication and synchronization between processors and SRAMs.

Figure 4 EVE

 4 Figure 4 EVE Zebu Server multi-FPGA platform

Figure 5

 5 Figure 5 Automatic Embedded Multicore Design Flow

RAMP Blue BB-672 Max number of processor 1008 672 FPGA number and type 84

		Virtex-II Pro 70	56 Virtex-4 LX200
	Emulation frequency	90 MHz	10 Mhz
	Processor	MB V4.0 no optional units	MB V6.0 full optional units
	OS & compiler	ucLinux & GCC	Standalone & GCC
	FPU	64 bits FPU / 12 cores	32 bits FPU / core
	DDR memory	250 MB / processor	Not implemented
	Monitoring &	Control network	Monitoring network
	Debug	Debug interface	Dynamic probes
	Network topology	Cluster 3D mesh	Cluster mesh
	Interconnection	Crossbar switch + Ethernet	Network on Chip
	Communication	Message passing	Distributed shared memory
	Language	MPI or UPC	ENSTA proper C driver
	Benchmarks	Netpert (for network) NPB class-S (on 256 cores)	OCP-IP micro-benchmarks (on 672 cores)

Table I FPGA IP resource utilization FPGA Virtex5 LX330 Resource Utilization

 I

	Number of DSP48s	87 %
	Number of RAMBs	78 %
	Number of SLICEs	79 %
	Number of LUTs	58 %


The uncanny in Howard Hawks's The Big Sleep

Christophe GELLY

Dealing with

The Big Sleep as a work fraught with uncanny representations now seems self-evident, after so many critics-whether in the field of literary or film studiesunsuccessfully strove to recapture the true development of the criminal plot unravelled by Marlowe: one piece still insists on being missing and points to the unsatisfactory closure of the text as well as the movie. It may be the mystery around Owen Taylor's death, a minor character (but are there really minor characters in the detective genre, before the final solution supposedly sets up the characters' roles for good?), or the main criminal protagonist in the movie, Eddie Mars, whose guilt is problematic in the plot. In other words, the disturbing, uncanny quality in the novel and the movie stems from this problematic closure and from the mystery on who did what precisely in the story-hence this quality derives from a debunking of the genre as self-contained and purely self-explanatory, an "ideal" of the text by which the text fails to abide. In the following discussion of the movie adaptation of Chandler's novel, I shall dwell on this problematic nature of the plot, which results from Hawks's deliberate designs, instead of trying to explain away the gaps in the logical development of the film narrative. These gaps are indeed the places where the director expresses his own viewpoint in the novel and develops a personal discourse on the uncanny quality within reality, a quality that duplicates-with a difference-the initial mystery that, in the novel, Geiger's death constitutes as the starting point for the investigation by Marlowe.

With respect to the specific quality of the uncanny in the movie, I shall distinguish three categories. First of all, an epistemological or cognitive type of uncertainty in the plot is instrumental in a perception of the movie diegesis as uncanny, from a strictly referential and logical perspective-that will be the basis of our criticism of the movie as adaptation. Beyond this, the movie also stages a whole materialization of the uncanny in formal terms, first through an aesthetics peculiar to it, then through self-representation as a way of questioning the cinematographic medium itself within the movie. We shall first, then, deal with the uncanny feeling inspired by the movie as a result from the many inconsistencies, from a logical viewpoint, in the plot, that tend to present it as unaccountable really, before tackling the topic as a deliberate design pointing to a new aesthetics enacted in the movie. We shall also integrate the psychoanalytical definition of the uncanny as a feeling resulting from the return of the repressed, but the theoretical orientation of this paper will not be psycho-critical in itself.

The entropy of adaptation

The prevailing approach to the movie The Big Sleep as an adaptation enhanced Hawks's reading of Chandler as informed by ideological censorship and teleological bowdlerizing. Thus, Ronald Librach 1 contends that, unlike the novel, the movie chooses to confirm Joe Brody's defence when the latter claims he is not guilty of Geiger's death and instead accuses Owen Taylor, the Sternwoods' chauffeur, whom he says he followed after and before the murder. As a matter of fact, if we watch the scene carefully, in the movie we do see two cars leaving Geiger's house before Marlowe finds the blackmailer dead, and one of those cars is the station wagon which we will see driven by Brody some time later (when Marlowe follows Brody as he moves out books from Geiger's shop). This mystery, at least, is apparently solved in the movie, which here appears as a simpler version of the same story in novel form. Likewise, the enforcement of the Hays Code-a set of regulations having to do with censorship self-imposed by the movie producers from 1930 to the late 1960s-results in several changes from the plot of the novel to the scenario, especially with respect to the sexual content of the story: for instance, the topic of homosexuality is virtually non-existent in the movie compared to its importance in the novel. 2 The movie becomes as it were uncannily estranged from its literary model, owing to its subservience to the production context and to the spectators' expectations of a simpler, more "conclusive" plot than what we get in the novel. Cinema as estranged from literature-this is of course a simplistic vision which we shall reform immediately.

Hawks's movie, in fact, does not deliver a simpler, subdued version of the novel, but testifies to the entropic nature of the adaptation process that results in stressing, not erasing, the original uncanny quality of the novel's plot. If we remember for instance the way Marlowe reluctantly accepts Brody's embarrassed explanation about how he became possessed with Geiger's compromising photographs of Carmen, and about why he tried to blackmail Carmen Sternwood, we understand that through paralipsis the detective insists very much on the gaps and the lack of verisimilitude of Brody's tale: "We'll pass that […] That's a little weak but we'll pass that too". We are very far indeed from any smoothing of the rough edges off the narrative-which leaves us in doubt as to whether we may really believe Brody or not. This holds true for the novel too, for instance when Marlowe explains to Mona Mars how he got information from Jones after the latter learnt the detective was hired by General Sternwood: Marlowe says, in the novel and in the movie: ""How he found out is a long story". We have to think of Agnes Lozelle as the "linking element" between Marlowe and Jones, but Marlowe does not explain this and stresses instead the difficulty in getting a complete vision of the connections between the protagonists. Thus, the uncanny in the movie and the novel-resides not in the erasure of an entropic reading of the text, but in the deliberate exhibition, the exposure of this entropic reading. But how could this epistemological uncertainty resulting in gaps and an uncanny feeling within the plot relate to the place of the uncanny as a concept in the movie itself?

A first step to answer that question is to distinguish several types of inconsistenciesin the movie-from a logical perspective. A first type concerns the viewpoints from the various characters. When he first meets Vivian Sternwood, for instance, Marlowe refers 3 to Carmen's words on his size ("You're not very tall, are you?", as contrasted with what Carmen says to Marlowe in the novel, "Tall, aren't you?" 4 ), and yet Vivian was not there when he met Carmen and when she told him that. The reference thus seems unaccountable, unless we understand Marlowe here suspects (and accuses) Vivian of spying on him (Marlowe's dialogue with Norris, the Sternwoods' butler, may confirm this reading, since Marlowe wonders then how Vivian knew he was visiting the General). Likewise, later on, in the restaurant scene added by Hawks in 1946, a scene in which both characters playfully sustain a horserace metaphor with sexual connotations, Marlowe tells Vivian that Regan, General Sternwood's missing son-in-law, left her for Mona Mars, gangster Eddie Mars's wife-and Vivian seems genuinely taken aback, whereas she had brought that information to Marlowe herself some time earlier, when she had come to his office to see him. Those two examples are typical illustrations of the cognitive puzzlement the movie deliberately plunges its spectators into, thus depicting an uncanny diegetic universe that derives from-but does not mimic-the overall blurring of roles in the novel. We shall see it is quite important that such conspicuous inconsistencies should be concerned with the issue of viewpoints.

Secondly, the movie develops an entropic representational strategy having to do with the adaptation process as a superimposition of a specific cinematographic reading over the literary medium. In other words, Hawks's interpretation is not a substitute for Chandler's text; it adds up to it and develops some lines of reading which would not appear so clearly in the text but for the movie itself. Such elements as revolve around Marlowe's (possible) guiltimpossible to integrate in any univocal reading of the novel-belong to that second category. Christopher Orr argued that Harry Jones's death could be read as a symptom of Marlowe's aggressive death-wish against his informer, in a desire to ward off the figure of the dominated male which Jones represents, in his relation to Agnes Lozelle. 5 Many other elements point indeed to Marlowe's possible guilt, even if this be only at a "fantasy" level. For example, we may think of Vivian's asking Marlowe when he brings Carmen back unconscious to the Sternwoods' residence after Geiger's death, "Did you do this?"; but also Marlowe's repeated answer to Eddie mars when he refuses to speak to the gangster in Geiger's house ("I already got a client") is a subtle, if not sustained, suggestion that Marlowe might indeed have worked for Mars under other circumstances. Both examples are also present in the novel. What Hawks adds lies in another scene, where after he brings Marlowe on the pier to examine Owen Taylor's corpse, inspector Bernie Ohls unaccountably tells the sleuth, with obvious reference to Taylor's death: "This doesn't look like the way you'd handle it." This departure from the novel materializes a new reading around Marlowe's potential guilt and once again adds up to the potential interpretations of the plot (in an entropic way) without the least concern for the compatibility of those interpretations. 6 Let us notice also that we shall never know what Marlowe was about to say when he was interrupted by this remark from Bernie Ohls, which is another way of drawing the spectator's attention to the lack of closure in the movie through the problematic viewpoint this movie develops on the novel's plot. Bernie Ohls's interruption of Marlowe's speech in this scene creates a mystery on what Marlowe was about to say, and the content of this interruption is itself problematic as we have just seen: the enigma is thus uncannily duplicated at the point when it was possibly going to be partially explained by Marlowe's interrupted sentence bearing on Taylor's death.

The uncanny and the movie's aesthetics

Our first development focused on the uncanny deriving from the illogicality or incompleteness in the management of the criminal plot by the detective and the narrative at large, pointing thus to Hawks's adaptation as "refusing" to be reduced to any teleological orientation supposedly peculiar to the detective genre. This refusal constitutes in itself a reading of Chandler's novel, opening up several leads that were not in the original text. Apart from the diegetic content studied so far, the movie adaptation arranges these heterogeneous elements from the story to build up a whole aesthetics, which will turn the uncanny into an essential issue in terms both of content and formal structure. We shall first tackle this aesthetics as a narrative, trying to locate the presence of the uncanny in that filmic narrative.

We already saw that Hawks deliberately handles the adaptation process as a means of providing a specific uncanny dimension to the plot-which was initially to some extent steeped in that kind of atmosphere. But the cinematographic adaptation in itself contributes to add up some measure of artificiality to Chandler's work, for instance when he chooses to transpose directly the somewhat literary speeches from the novel to the movie-when we hear General Sternwood about the orchid analogy linking his daughters to flowers: "They are nasty things. Their flesh is too much like the flesh of men. And their perfume has the rotten sweetness of a prostitute" (p. 8). This analogy reveals a lack of verisimilitude in the movie situation whereas the same sentence in the novel-not actually uttered-is perceived on a more abstract level, outside the actual utterance of a literary comparison that appears artificial in context. This is only one example-of limited validity per se-but pointing to a whole strategy of artificiality focused, among other elements, on the dialogues between characters. The first meeting between Marlowe and Vivian in the movie is thus characterized by a way of delivering her speech in which Vivian clearly contradicts the denotation of that speech: when she invites Marlowe to help himself to a drink she keeps the same aggressive, hurt tone as that with which she began the encounter, thus strangely opposing the literal content and the formal expression of her speech. Vivian utters her speech in the same breath, whether she tackles one topic (what the General has just said to Marlowe) or another (and a sensitive one), i.e. alcohol-drinking. The same strategy is repeated when Marlowe and Eddie Mars first meetthis emphasis on the artificiality of expression may be related, as we shall see, to the specificity of the cinematographic medium.

Another element in that aesthetics of artificiality has to do with the use of stereotypes which, again, tend to present the diegesis as unreal and to defamiliarise the story universe which the spectator faces. Thus, Marlowe is repeatedly presented as a "stock character", as the resourceful, wise guy, which fits very well his role as a detective. To embody this intelligence and vivacity in visual terms, Hawks attributes to Marlowe some kind of twitch that consists in touching his right ear whenever he has a clever idea, an insight or when he is faced with a difficult situation (for instance when he discovers Geiger's corpse or when he cross-examines Joe Brody after he has found out Vivian had gone to his place). An interesting instance of this device takes place when Marlowe sits in a restaurant and decides to call the Sternwoods' residence on the phone 7 -just when he has that idea (and consequently touches his ear) the waitress lights up the bulb just over his head, thus ironically stressing the stereotypical episode which points to a reflexive dimension in the movie. That undermines the filmic representation of the detective as ingenious and through an ironical slant which further associates the compulsory figures of the genre with the ironical distance taken from them. Likewise, if we think of the "gimmicks" that characterize Eddie mars and Lash Canino (the former toying with keys and the latter with coins) we are taken back to Hawks's 1932 movie Scarface that also staged the same kind of gimmicks for its main character; this becomes at the same time a sign of the stereotypical representation of criminals and a clue pointing to an interfilmic quotation within the same director's work. Lastly, we cannot but quote the scene where Marlowe quickly disguises himself as a "bookworm" before entering Geiger's shop, simply by tilting up the brim of his hat, and putting on dark glasses-this very basic disguise, which apparently functions correctly in the confrontation with Agnes Lozelle that ensues, shows that reality and identity are easily faked, since they rely mainly on preconceived ideas and visual stereotypes.

We are then faced with a fictional world in which characters are stereotyped and reality artificially corresponds to those stereotypes, which results in the depiction of a very strange and disquieting diegesis. This corresponds to Freud's definition of the uncanny as a feeling that mixes the recognition of a familiar element for the subject's psyche and the confrontation with otherness, a feeling that he accounts for by the return of what has been repressed (and hence is approached as alien to the subject) but which was before repression part and parcel of the psyche (hence the feeling of familiarity). 8 The types presented in Hawks's movie contribute to destabilise the spectator in that same way, by staging extremely recognizable and familiar roles in a strange, ironical light that questions our own habits of interpreting the movie. Thus, Annette Kuhn showed that in the movie Geiger's house can be analysed as a place that obsesses Marlowe (he returns there four times) connected to the mystery of femininity that is situated (as far as Carmen Sternwood is concerned) outside the symbolic order.9 I would like to point to another polysemic image in the movie, that of Carmen as she bursts in on Brody to retrieve the compromising photographs taken at Geiger's house. Dressed as a Madonna, Carmen-whom Vivian watches anxiously as she makes eyes at Marlowe, a sign of morbid attention already experienced by Regan-subsumes the presence of fantasy as ambivalent and deadly, since she appears here at once as a child sucking her thumb, a saint, a murderer, a lunatic. This ironical and distanced rereading of all those roles is the hallmark of Hawks's staging of the scene, in which once again he puts forward those stereotypes to present them as uncanny and question their validity and function-in short, defamiliarising what ought to be recognised as a set landmark and make it appear strange. How does that distanced reading appear as a discourse on representation itself?

Reflexivity and unreality

We have seen how the movie builds up a whole aesthetics founded on the uncanny through several narrative and more largely representational strategies. Now I intend to show how Hawks's movie holds a discourse on its own aesthetics, on its own ways of telling the story. The first and most obvious of those reflexive discourses has to do with verbal communication. If we remember for instance the two scenes in which Eddie Mars's laughable thugs appear, i.e. when they rush to Geiger's house to prove Mars right when he claims he did not come alone, and when in Mars's casino at Las Olindas they tell Marlowe Vivian Sternwood wants to speak to him-we are struck by the fact that both scenes revolve around the impediment on speech, as both grotesque characters cannot decide who said what, and who is to speak or to listen. The same holds true for the famous phone hoax improvised by Marlowe and Vivian (a scene that was an add-up to the novel, in the script) in which the call to a police officer (named Reilly, like Doghouse Reilly, the name Marlowe humorously claims to be his when first meeting Carmen, which makes it a further intrafilmic reference) again raises the question of who is talking to whom. This question keeps recurring, especially in the frequent arguments between Marlowe and Vivian, often consisting in a fight to have the last word, literally speaking. The failure of verbal communication is indeed a key feature in the movie, as shown also by the scene in which the two usherettes in Mars's casino cannot speak intelligibly to Marlowe for they speak at the same time, and thus have to wait for his "signal" to organize communication efficiently. Another sign of that failure appears in the scene added in 1946 by Hawks, in which Marlowe and Vivian have a witty conversation in a restaurant about horseracing and (figuratively) sex, a scene that ends up in a split between them. That scene is also a problem in narrative terms since just after that split Marlowe meets (by chance) Vivian singing at the Cypress Club in Las Olindas and she unaccountably joyfully greets him with a wave of her hand. We may consider this oddity, this rupture in the narrative continuity, to originate from the fact Hawks had to add that scene at a later period (that was a request from the producers), but it can also be read as a staging of the limits in verbal communication entailing a relative narrative inconsistency.

What is then the discourse held by the movie on its own representational strategy? Are images more reliable than words in it? Not if we remember the scene in which Mars stages a fake assault on Vivian after the latter won a large amount of money at his casino. This scene is a show put on for Marlowe to have him believe there is no friendly connection between Mars and Vivian, but Marlowe observes the assault through a car window in the parking lot of the casino, so that in the movie-where Hawks uses a point-of-view shot-the scene appears as "framed" by a window car reproducing a camera frame; this is a clear sign that cinema is also, or can also be, the medium of a fake, artificial representation. We could also quote the scene of the murder of Harry Jones by Canino, which was analysed by Marc Vernet as a scene which equates Marlowe's position as a witness of that death with the position of a dupe, since the detective wrongly believes Jones gave Agnes Lozelle's real address to Canino before dying, whereas in fact he sacrificed his life for her. 10 If the discourse held by the movie stresses the artificiality of the representational strategy even in terms of images, does this work keep a place for its spectator outside the feeling of unreality and manipulation that characterizes its protagonists? It seems the movie's discourse on this point is quite original and interesting in the sense that it locates the agency that is liable to organize that unreality of the diegesis off-screen-that is, potentially, in the spectator. For instance, in the scene where Carmen comes back to Geiger's place and is surprised by Marlowe who asks her questions about Brody, we see her answering "yes" to Marlowe's question (i.e. did Brody kill Geiger?) with a smile on her face indicating that she thus wishes to take her revenge on Brody her former lover, a smile which potentially Marlowe who is off-screen then does not see. Marlowe's attitude in this scene where he drives Carmen into a corner no doubt reveals that Carmen's answer is not reliable, and he makes fun in the following sequence of the way she naively tries to fool him. Yet, this ambiguous management of the off-screen dimension reveals the necessity of the spectator's participation (Marlowe being here the "spectator" of Carmen's intended manipulation of him) for the movie to make sense. Through representing an openly deceptive device, the cinematographic medium stresses the all-important presence of another vision, which is always in the making through the spectator, whether he is intradiegetic (Marlowe) or extradiegetic (you and me). Inscribing the presence of another vision off-screen (or in the shot-reverse shot technique, which amounts to the same phenomenon) requests the spectator to invest the movie with a distanced reading of images (for instance as far as the stereotypes already described are concerned) and to consider the uncanny in that work as a discourse that is in fact addressed to him or to her.

LIBRACH Ronald S., « Adaptation and Ontology: the Impulse towards Closure in Howard Hawks's version of The BigSleep", Literature Film Quarterly, vol. 9, n° 3, July 1991, pp. 164-175.

On that point, see LUHR William, Raymond Chandler and Film, New York, Ungar, 1982, chapter 7.

The reference appears in the following exchange of words, taken from the movie : "Now you're a mess, aren't you? -I'm not very tall either. Next time I'll come on stilts, wear a white tie and carry a tennis racket."

CHANDLER Raymond, The Big Sleep (1939), Harmondsworth, Penguin Books, 2005, p. 3.

ORR Christopher, "The Trouble with Harry: on the Hawks Version of The Big Sleep", Wide Angle: A Film Quarterly ofTheory, Criticism & Practice, 1982, 5 (2): pp.

66-71. See p. 70: "What Jones represents is[…] the male that allows himself to be dominated by a woman. Thus Canino's violence towards the castrated male and Marlowe's complicity in that violence originates in their fear of women as castrator." 6 For instance, we may think of the hypothesis according to which Marlowe "wished" Owen Taylor dead (whether in an abstract or concrete manner-we do not know what he really could do to provoke that death) so as to revive a plot that will eventually bring him to fulfil his desire for Vivian.

Marlowe calls the Sternwoods' residence but Norris, the butler, tells him that the General in too ill to talk to him. Yet, Vivian tells him on the phone that Shawn Regan has just been found alive and safe in Mexico and that his investigation has thus come to an end. Marlowe will no more believe that lie than he believed Vivian's presentation of the blackmail by Brody, which was meant to get rid of the detective in fact and to enable her to deal with the blackmail, concerning the compromising pictures of Carmen, on her own. This scene is then at once, in its content, pointing to the tenacity and wit of the sleuth and from a formal viewpoint an ironical presentation of Marlowe's handling of the case.

FREUD Sigmund, "The Uncanny," in The Standard Edition of the Complete Psychological Works of SigmundFreud, ed. & trs. James Strachey, vol. XVII, London, Hogarth, 1953, pp. 219-252.

KUHN, Annette, "The Big Sleep: A Disturbance in the Sphere of Sexuality", Wide Angle 4, n°3, 1980: pp. 4- 11.

« Le Grand sommeil est un bloc magique », Avant-scène cinéma, n°329-330 : juin 1984.