Keywords: MEMS, CMOS, Electrostatic Actuator, Switch, Diagnosis

This paper introduces the design of High-Voltage CMOS drivers for Electrostatic MEMS switches. In order to perform online diagnosis, the proposed architecture implements a dedicated circuitry that can detect the pull-in event. This way, stuck or broken switches are identified during operation. The pull-in event corresponds to a rapid change in the actuation capacitance thus producing a current peak during actuation. The idea is therefore to measure the charging current, using a differential method that cancels the effects of any parallel parasitic capacitance.

I. INTRODUCTION

FTER years of continuous development and improvement, MEMS based electrostatic switches have become quite popular. They are now considered for various applications related to RF telecommunications where they advantageously replace the traditional PIN diodes as switching components, due to their unbeatable low insertion loss. Although much works have been done to improve MEMS switches reliability in the past years, the design of high addedvalue systems integrating such devices is not considered without some level of robustness against possible MEMS failure. This study is part of a project that target the design of reflect arrays antennas for telecom applications. In this application, thousands of MEMS switches are embedded into RF cells to open or short RF paths so that a continuous phase shift is achieved between incident and reflected waves. As different switches configurations may achieve the same phase shift, the architecture features an intrinsic redundancy so that alternate RF path may be used if non-working MEMS are well identified [START_REF] Salti | MEMS breakdown effects on the radiation of a MEMS based reconfigurable reflectarray[END_REF]. Moreover, a huge quantity of MEMS is used in a small surface, so that the control and driving circuitry, including the diagnosis functionality, must be integrated into small ASICs.

The proposed diagnosis approach is non-invasive from a RF point of view since RF path is not directly altered. It is based on the monitoring of the actuation current as used in [START_REF] Caillard | A highly simple failure detection method for electrostatic microactuators: application to automatic testing and accelerated lifetime estimation[END_REF] or [START_REF] Merlijn Van Spengen | Experimental Charaterization of Stiction Due to Charging in RF MEMS[END_REF] and thus only concerns the actuation circuitry. Note that the quality of the contact (either resistive or capacitive) is not monitored using this method.

II. SWITCH MODELING & SIMULATION

A. Device Architecture

This study addresses generic MEMS actuators or switches. It is only assumed that the actuation is based on electrostatic force in a parallel plate capacitor. The contact nature can be resistive or capacitive, using both serial or shunt configuration. For the simulations however, the pseudorealistic case sketched in Fig. 1 is considered. It represents basic capacitive shunt architecture, which is very common in RF applications. The function of the switch is to connect two planes together in order to provide a path for the RF waves into the patch. The moving part of the switch is a metal cantilever beam attached (both mechanically and electrically) to a ground plane. It is actuated by means of a large bottom electrode which is positively biased. When actuated, the cantilever beam lands on a thin dielectric layer thus connecting the two planes through the capacitor C RF . Since the thicknesses of the planes is greater than the thickness of the actuation electrode, the air gap between the cantilever and the actuation electrode never closes, preventing the device from known reliability issues associated with high electric fields in dielectrics. The price to pay is a higher actuation voltage and a lower ratio C Act,up /C Act,down which makes the use of C Act measurement more challenging for the diagnosis, as it will be developed later on in this paper. In addition, the parasitic capacitor C P that results from the routing of the actuation electrode makes the measurement even more complicated.

B. Modeling

According to Fig. 2, the switch model is based on a springmass-damper system (kMD), translating along the vertical axis. The mass displacement z is controlled by an electrostatic actuator made of two parallel plates of surface S A , separated by an initial gap g 0 . Assuming that the bottom electrode is covered by a dielectric layer of thickness t ox and of relative permittivity ε r , the resulting capacitance between the two electrodes is given by:

ܥ ௧ ൌ ఌ బ ௌ ಲ (1)
where g eff is the effective gap calculated by taking into account the two serial capacitances:

݃ ൌ ݖ െ ݐ ௫ ௧ ೣ ఌ (2)
The switch travel is practically hard-limited by the signal plane height. In order avoid convergence troubles within the simulator a squeeze-film damping effect is modeled into a socalled limiter block. This somehow makes the landing of the beam onto the finger surface smoother. Within a short range above the finger surface, the limiter acts in force-source mode and the squeeze film effect is modeled by an additional damping force given by:

ܨ ൌ ߙ ቀ ఎௌ ಷ ௭ି௦௧ ቁ ݖሶ (3)
where η represent the air viscosity in Pas.s, S F is the overlap surface between the bridge and the finger and α an exaggeration factor (set to 1 by default). If the conditions ݖ ൎ ݐݏ and ݖሶ ൎ 0 are reached, the limiter switches to position-source mode and holds the bridge at ݖ ൌ ݐݏ as long as the electrostatic actuator forces the cantilever down. 3 shows the straightforward implementation of this model under Cadence®. Each part of the model is described using the proprietary Verilog-A language. The discipline kinematic is used to represent the z node. Using this discipline, the "across" quantity (same as voltage) represent the vertical position of the bridge, while the "through" quantity (same as current) represents the forces. Forces equilibrium of on node z is therefore a direct application of Kirchhoff's circuit laws. Table I summarizes the model parameters used in following simulations for further reference.

eff Act A E g V S F 2 2 0 ε = dt dV C I Act Act Act = ( ) 0 g z k F k - = z D F D & = z M F M & & = L F z

III. SMART DRIVER DESIGN

The primary function of the driver is to provide the actuation voltage V Act that is close to 46V in our case. For this, the High-Voltage (HV) 0.35µm CMOS technology (h34b4c3) from Austria MicroSystems (AMS) was chosen to develop the integration of such drivers in the context of a multiple channels chip. The design of the basic driver stage is addressed first. Then two approaches are proposed to upgrade the driving circuitry with a diagnosis capability.

A. High-Voltage Driver

The challenge when designing a HV driver is to combine the low voltage level of the control circuitry (typically 3.3V) with the higher voltages that bias the output stage (50V). In this study, it was assumed that only two external supply voltages were available: a low 3.3V and a high voltage supply that may vary from 20V to 50V to adapt various switch pull-in conditions.

The proposed driver is shown in Fig. 4. It is based on a pair of HV transistors Q 3 and Q 4 . In this configuration, the gate of Q 4 can be directly driven by the low-voltage levels (0-3.3V). The gate of Q 3 must be driven between V CC and a lower voltage that turns Q 3 on, while keeping the magnitude of V GS3 within 20V which is a technological constraint. This condition is ensured by the level-shifter stage made of Q 1 , Q 2 and V b . When input is 0, Q 2 is off. There is no current flowing in the level-shifter and V GS3 is 0. When input is 3.3V, Q 2 is turned on. The current flowing in the level shifter is regulated by the voltage drop across R 1 so that V GS1 ≈-V tp ≈-1,7V. The voltage drop V b is designed to be about 10V (50% of the 20V limit). It is implemented by means of few diode-mounted transistors in series, biased by a resistive load tied to the ground. Doing-so ensures that V b stays constant for a wide range of supply voltage. It finally comes that the voltage on the gate of Q 3 in on-state is close to V CC -V b +V tp ≈41.7V. Note that the static consumption of the driver is here mainly determined by R 1 whose value is practically restricted by its cost in term of silicon area.

B. Diagnosis Principles

Fig. 5 illustrates the transient response of the switch to an actuation pulse. It is obtained by the simulation of the HV driver previously described together with the switch model and a RC network (R ser =1MΩ and C par =5pf) representing a rather bad case for the routing. As mentioned before, the diagnosis approach must not interfere with the RF path. Fortunately, the switch pull-in produces a distinctive actuation current profile which is a good start for an investigation.

The driver output is turned on at t 0 =0, providing an almost instant and stable 40V voltage for V Act . The transient current then exhibits a first peak corresponding to the charge through R ser of the capacitance C par +C Act,up . The charge is almost completed when V cap reaches its final value of 40V (t 1 ≈30µs) and before the cantilever starts its travel. At t 2 =75µs, the cantilever gets close to its lower position producing a fast increase of C Act . This causes a new small current overshoot corresponding to the charge of ∆C Act =C Act,down -C Act,up . Note that during this charge, the V Cap voltage exhibits a small notch that can be neglected. Finally, all signals become stable after t end =150µs. Since the second current peak will not occur in the case of broken or stuck MEMS, it makes sense to develop a diagnostic strategy based on the measurement of the actuation current. An obvious method would be the simple measurement of the amplitude of the second overshoot (A peak ), however the peak amplitude strongly depends on the routing parameters (R ser , C par ) that may vary in a significant range. This is shown by the simulation in Fig. 6.a, where A peak varies by 120% with the routing parameters. On the other hand, the amount of electric charges transferred in the electrostatic actuator when C Act changes from C Act,up to C Act,down is relatively insensitive to Iact(µA) Vcap (V)

Q 1 Q 2 Q 3 Q 4 R 1 V b 0 3.3V 0 HV In V Act V CC (

Time (µs) IAct

A peak A int routing parameters. Fig. 6.b shows that the current integral (A int ) measured within the time window corresponding to the second current peak only varies by 4% for the same routing parameters range. As a consequence, a diagnostic approach based on the actuation current integration seems more appropriate in our case. The total amount of charges stored in C par and C Act during the whole actuation process does not depend on R res and writes:

ݍሺݐሻ ൌ ܸ ௧ ሺݐሻ ቀܥ ܥ ௧ ሺݐሻቁ (4)
Looking at the actuation current, we have:

݅ ௧ ሺݐሻ ൌ ௗሺ௧ሻ ௗ௧ ൌ ൫ܥ ܥ ௧ ሺݐሻ൯ డሺ ಲ ሺ௧ሻሻ డ௧ ܸ ௧ ሺݐሻ డሺ ಲ ሺ௧ሻሻ డ௧ (5)
The second spike of current is caused by the second term of Eq. 5 when the actuation voltage is constant and the capacitance changes. As the derivative of the actuation voltage is null during the second spike, the integration of the actuation current from the beginning of the second spike t 2 to t end results in:

 ݅ ௧ ݐ݀ ൌ  ܸ ௧,ௗ ௗሺ ಲ ሺ௧ሻሻ ௗ௧ ݐ݀ ൌ ܸ ௧,ௗ ܥ∆ ௧ ௧ ௧ మ ௧ ௧ మ (6) With: ܥ∆ ௧ ൌ ܥ ௧,ௗ െ ܥ ௧, ൌ ܥ ௧,ௗ௪ െ ܥ ௧,௨
Eq. 6 clearly expresses that the result of integrating the actuation current during the second spike does not depend on the parasitic capacitance. However, it is valid only if the two spikes can be well separated. It implies that the time constant of the first spike, i.e. R res × C par , should be much lower than the time response of the switch.

C. Smart-Driver Architecture #1

The first improved version of the HV driver presented above is depicted in Fig. 7. In this circuit, the actuation current is mirrored into the capacitor C int so that the voltage across C int represents the integration of I Act . A cascode mirror configuration, with a copy ratio ߚ ൌ ܹ ொ,ொ଼ ܹ ொହ,ொ ⁄ , has been preferred to improve the V DS matching of the pair Q 5 /Q 6 and thus guaranty a better accuracy of the copy. Transistor Q 9 is used to initialize the integrator state and then start the integration process upon falling edge of the Reset control input. Note that the gate Q 9 is associated with dummy transistors (not represented) to minimize integration errors due to charge injection. If the voltage across C int reaches V th , a '1' is stored in the latch meaning a successful commutation of the switch, otherwise the diagnosis output is '0'. The independent control of the Reset pin allows the integration process to start anytime.

Two strategies have been investigated: If the MEMS time constant is short, or uncertain, the integration may start from t 0 . In that case, the total actuation current is summed up in the integrator and the result depends strongly on the parasitic capacitance. Therefore, the parasitic capacitance should be known in order to make the diagnosis. Otherwise, if the MEMS time constant is long and well characterized, the integration may start from t 2 so that only the current associated with the pull-in event is accumulated. This second method has been validated with results reported in [START_REF] Merlijn Van Spengen | Experimental Charaterization of Stiction Due to Charging in RF MEMS[END_REF].

D. Smart-Driver Architecture #2

The previously proposed method requires the good knowledge of the switch dynamic behavior, which must feature a slow-enough, predictable and stable time response to detach the pull-in from the charge of the parasitic capacitance. If these conditions are not met, a different approach to eliminate the effects of the routing parameters is necessary. A possible solution is proposed with the architecture shown in Fig. 8. The measurement sequence start with an initialization of the charge in C int by turning on both Q 9a and Q 9b so that V Cint = V ref . During phase #1, V cc is set to provide only half of the final actuation voltage V Act at the driver output, Q 9b is turned off and the driver is activated (In='1'). The actuation current is summed up in C int . After the integration time, and assuming that the driver output is below the pull-in voltage the voltage, V int,B is given by:

I Act β.I Act Q 3 Q 4 V CC (HV) V Act Level Shifter In Q 5 Q 6 Q 7 Q 8 Q 9 C int V th Diag Out '1' Reset
ܸ ௧, ൌ ఉ ಲ ଶ ൫ܥ ܥ ௧,௨ ൯ (7)
During phase #2, the transistor Q 9a is turned off, and Q 9b is closed to connect the node V int,B to ground. At this moment, the voltage V int,A is:

ܸ ௧, ൌ ܸ െ ܸ ௧, ( 8
)
V CC is now adjusted to make the driver outputs V Act so that another V Act / 2 voltage step is applied on the switch. The pull-in occurs and then after another integration period, V int,A becomes:

ܸ ௧, ൌ ൫ܸ െܸ ௧, ൯ ఉ ಲ ଶ ൫ܥ ܥ ௧,ௗ௪ ൯ ܸ ௧, ൌ ܸ ఉ ಲ ଶ Δܥ ௧ (9)
In summary, the amount of current charging C par is summed up in C int during the first V Act / 2 step, and then subtracted during the second V Act / 2 step, leaving the integrator output with an image of the ∆C Act charge only.

The complete sequence shown in Fig. 9 with no MEMS connected to the driver. Because Δܥ ௧ ൌ 0 in this case, the diagnosis output (V int,A ) is V ref at the end. The simulation is performed with R ser =1MΩ, C par =10pF, β=1/16 and C int =15pF. With V cc =40V, the actuation voltage is roughly V act =37.2V. According to Eq. ( 7), the voltage V int,B after phase #1 reaches 775mV, which is verified by the simulation. In Fig. 10, the simulation is performed with the electrostatic switch connected to the driver. The change in capacitance during the pull-in produces an increase of V int,A of about 60mV. According to Eq. ( 9), it corresponds to a change in capacitance of Δܥ ௧ ൌ 770fF. This value is in the range of expected change according to the model parameters reported in table I. The robustness of the approach against routing parameters (R ser , C par ) has been investigated with results reported in Fig. 11. It appears that for each case, the working MEMS produces a result well distinguishable from the result obtained with a broken switch. Note that the result strongly depends on the ability to set the correct V cc that produce a precise V act /2. In this simulation, this V cc is set manually to 21V. Practically, this half-supply voltage can be generated onchip within a dedicated circuit that will address process variations and better separation between working and failing case is then expected.

I Act β.I Act Q 3 Q 4 V CC (HV) V Act Level Shifter In Q 5 Q 6a Q 7 Q 8a Q 9b C int mes B β.I Act Q 6b Q 8b Q 9a mes A V ref V int,A V int

IV. EXPERIMENTAL RESULTS

A test chip including 18 driver channels has been fabricated using the High-Voltage 0.35µm CMOS technology from Austria Microsystems. The chip has been connected to both fixed capacitors and MEMS switches (Fig. 11). First experiments have demonstrated that the driver part operates as specified with MEMS switches regarding actuation. For the characterization of the diagnosis function, fixed capacitors representing C par have been initially connected to the driver without MEMS. For three values of C par , the diagnosis output (V int,A ) voltage is presented in Fig. 12. The corresponding sensitivity is 3.6mV/pF, which is low enough to consider that the effect of C par is correctly rejected (rejection ratio is about 30). Fig. 13 displays the output of the diagnosis circuit during a MEMS actuation. Qualitatively, the waveform is very similar to the one obtained by simulation (Fig. 10). An additional 25mV is brought across the integrator capacitor (C int ) during pull-in, corresponding to a 260fF change in the MEMS actuator capacitance.

Figure 1 .

 1 Figure 1. Structure of the MEMS switch under consideration.

Figure 2 .

 2 Figure 2. Switch model.

Fig.

  Fig.3shows the straightforward implementation of this model under Cadence®. Each part of the model is described using the proprietary Verilog-A language. The discipline kinematic is used to represent the z node. Using this discipline, the "across" quantity (same as voltage) represent the vertical position of the bridge, while the "through" quantity (same as current) represents the forces. Forces equilibrium of on node z is therefore a direct application of Kirchhoff's circuit laws. TableIsummarizes the model parameters used in following simulations for further reference.

Figure 3 .

 3 Figure 3. Model implementation within Cadence®.

Figure 4 .

 4 Figure 4. Structure of the HV driver.

Figure 5 .

 5 Figure 5. Transient simulation of an actuation event.

Figure 6

 6 Figure 6. a-(left) Variation in amplitude of the second actuation current peak as a function of routing parameters. b-(right) Variation of the actuation current integral during the second peak.

Figure 7 .

 7 Figure 7. Structure of the HV driver with Actuation Current integrator.

Figure 8 .

 8 Figure 8. Structure of the HV driver with a Differential Actuation Current integrator.

Figure 9 .

 9 Figure 9. Simulation of the HV driver diagnosis sequence without MEMS.

Figure 10 .

 10 Figure 10. Simulation of the HV driver diagnosis sequence with working MEMS.

Figure 11 .

 11 Figure 11. Comparison of diagnosis output for different routing parameters (Rser, Cpar) with working and non-working MEMS.

Figure 11 .

 11 Figure 11. Custom PCB for the assembly of the test chip with fixed capacitors and MEMS switches.

Figure 12 .

 12 Figure 12. Measured diagnosis output voltage, for three values of Cpar, without MEMS

TABLE I ELECTROSTATIC

 I

								SWITCH MODEL PARAMETERS
						Cell	Symbol	Quantity	Value
		k	D			acapacitor	SA ε0 tox εr	Actuation Electrode Surface Abs. Permittivity thickness Bottom dielectric Bottom dielectric relative permittivity	100 10 -9 m² 8.85 10 -12 F.m -1 1µm 3.9
			M			spring	k d0	Spring Constant Initial gap	0.5 N.m -1 17µm
						mass	M	Mass	1 10 -10 kg
						damper	D	Damping Factor	5 10 -6 N.m -1 s 2
	Electrodes Actuation S A	z	g 0	S F	stop Limiter	limiter	sflayer SF η	Gap for squeeze-film damping action Finger overlap surface Air viscosity	0.5µm 25 10 -9 m² 18 10 -6 Pas.s
							stop	Finger height	2.65µm
			t ox

ACKNOWLEDGMENT

This work is supported by the French Ministry of Research in the framework of the ANR project (Agence Nationale de la Recherche) entitled "R3MEMS".


Lothar Thiele

Ji Ji

Jian-Jia Chen

Iuliana Bacivarov

Kai Lampka

Wolfgang Haid

Simon Perathoner

Nikolay Stoimenov

Kai Huang

Andreas Schranzhofer

Marco Caccamo

Rodolfo Pellizzoni

 Real-Time Calculus  Artificial Example

Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative:

γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Intersection + Maximal Age"
How many memory blocks can be in the must-cache? Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative: Join should be conservative:

γ(A) ⊆ γ(A B)
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Union + Minimal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Union + Minimal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Union + Minimal
γ(A) ⊆ γ(A B) γ(B) ⊆ γ(A B) "Union + Minimal

Fill

Number of accesses to complete may-and must-information.

I.e. when can an analysis predict each access?

-→ Evict and Fill bound the precision of any static cache analysis.

Can thus serve as a benchmark for analyses. In the worst-case k -1 hits and k misses:

(k = associativity) -→ Evict(k ) = 2k -1 Another k accesses to obtain complete knowledge: -→ Fill(k ) = 3k -1 Reinhard Wilhelm
Policy P is (k , c)-miss-sensitive if m P (q, s) ≤ k • m P (q , s) + c
for all access sequences s ∈ M * and cache-set states q, q ∈ C P . LRU 1,2 1,3 1,4 1,5 1,6 1,7 1,8 FIFO 2,2 3,3 4,4 5,5 (p, j, d), where p denotes the period, j the jitter, and d the minimum inter-arrival distance of events in the modeled stream distance of events in the modeled stream.

B s i c s i c-s i c 2 Delay? Buffer? Stream 1 T3 CPU3 T1 CPU1  GPC GPC  1  1  3 Stream 1 T3 T1  GPC GPC  1  2 Stream 2 T2 CPU2 T4  GPC GPC  2  2 54
44% GPC GPC  1  1  3  GPC GPC  1  2  GPC GPC  2  2  40% 55

  information where control-flow merges.

  information where control-flow merges.

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  the example: Evict = Fill = 4 In general: Evict(k ) = Fill(k ) = k , where k is the associativity of the

Information processing system that is physically embedded within a larger system ABS gear box entertainment motor control climate control 4 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Target Platforms Target Platforms

	6, 6 -MRU 1, 2 3, 4 5, 6 7, 8 MEM MEM MEM 7, 7 8, 8 PLRU 1, 2 -∞ --∞ LRU is optimal. Performance varies in the least possible way. For FIFO, PLRU, and MRU the number of misses may vary strongly. Case study based on simple model of execution time by Hennessy and Patterson (2003): WCET may be 3 times higher than a measured execution time for 4-way FIFO. Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 computer science 40 / 64 saarland university Caches: Summary Cache Analysis for Least-Recently-Used . . . efficiently represents sets of cache states by bounding the age of memory blocks from above and below. computer science saarland university Caches: Summary Cache Analysis for Least-Recently-Used . . . efficiently represents sets of cache states by bounding the age of memory blocks from above and below. . . . requires context-sensitivity for precision. Predictability Metrics . . . quantify the predictability of replacement policies. -→ LRU is the most predictable policy. computer science saarland university Caches: Summary Cache Analysis for Least-Recently-Used . . . efficiently represents sets of cache states by bounding the age of memory blocks from above and below. . . . requires context-sensitivity for precision. Predictability Metrics . . . quantify the predictability of replacement policies. -→ LRU is the most predictable policy. Sensitivity Analysis . . . determines the influence of initial state on cache performance. Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 41 / 64 computer science saarland university Outline Timing analysis and predictability of caches Caches Cache Analysis for Least-Recently-Used Beyond Least-Recently-Used Predictability Metrics Sensitivity -Caches and Measurement-Based Timing Analysis Predictability of architectures Pipeline Analysis Timing anomalies Classification of architectures Extension to multi-core Why multi-core? Predictable multi-core Analysis of current multi-core computer science saarland university Outline Timing analysis and predictability of caches Caches Cache Analysis for Least-Recently-Used Beyond Least-Recently-Used Predictability Metrics Sensitivity -Caches and Measurement-Based Timing Analysis Predictability of architectures Pipeline Analysis Timing anomalies Classification of architectures Extension to multi-core Why multi-core? Predictable multi-core Analysis of current multi-core computer science saarland university Pipeline analysis Cyclewise evolution of processor model Basic Block Instruction Instruction Cycle semantics: Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 44 / 64 computer science saarland university (Concrete) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 45 / 64 computer science saarland university (Concrete) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 1 = 4 Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 45 / 64 computer science saarland university (Concrete) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 1 = 4 30 3 6 = 41 Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 45 / 64 computer science saarland university (Abstract) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 46 / 64 computer science saarland university (Abstract) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 30 Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 46 / 64 computer science saarland university (Abstract) Instruction Execution instruction MUL Fetch I-cache miss? Issue Unit occupied? Execute Multicycle? Retire Pending instructions? 30 1 3 1 3 6 30 1 1 3 Reinhard Wilhelm Timing Analysis and Timing Predictability saarland university Timing anomalies When local worst-case does not lead to the global worst-case A A Resource 1 Resource 2 Resource 1 C B D E D E C ready A Cache Hit Branch Condition Evaluated Prefetch B -Miss C computer science saarland university Smart configuration of existing multi-core MPC5668G -An automotive processor e200z0 No Cache e200z6 32KB Cache AMBA crossbar switch (AXBS) Reinhard Wilhelm Timing Analysis and Timing Predictability Tutorial ISCA 2010 61 / 64 computer science saarland university Smart configuration of existing multi-core MPC8641D -An avionics processor e600 32KB L1 Cache 1MB L2 Cache e600 32KB L1 Cache 1MB L2 Cache MPX Bus Embedded Systems Embedded Systems Tutorial ISCA 2010 computer science Resource 2 B C A Cache Miss MPX Coherency C Scheduling anomaly. Speculation anomaly. FLASH 2MB SRAM A 80KB SRAM B 512KB Peripherals e.g. CAN Module DDR SDRAM Controller DDR SDRAM Controller Ethernet Controller Ethernet Controller Peripherals e.g. PCI ACC ABS ESP ASR
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	Swiss Federal Institute	5

. . . requires context-sensitivity for precision.

of Technology Computer Engineering and Networks Laboratory A Sample HW Architecture (EU-SHAPES) A Sample HW Architecture (EU SHAPES)

						OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP
						MEM MEM MEM MEM	MEM MEM MEM MEM	MEM MEM	MEM MEM MEM MEM
	Heterogeneous Tiles Heterogeneous Tiles		Tile Tile	Tile Tile	Tile Tile	Tile Tile	F P P F	ADC ADC	sensor sensor
	Regular Tile-Structure Regular Tile-Structure					G A A G A A
	On-chip and off-chip On-chip and off-chip		Tile Tile	Tile Tile	Tile Tile	Tile Tile		DAC DAC	actuator actuator
	networks networks				OFF-CHIP MEM OFF-CHIP MEM	OFF-CHIP MEM OFF-CHIP MEM	OFF-CHIP MEM OFF-CHIP MEM	OFF-CHIP MEM OFF-CHIP MEM
						OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP
						MEM MEM	MEM MEM	MEM MEM	MEM MEM
						Tile Tile	Tile Tile	Tile Tile	Tile Tile		ADC ADC	sensor sensor
	3DT Off-chip communication 3DT Off-chip communication	DNP DNP	NoC RISC NoC RISC	DSP DSP	Tile Tile	Tile Tile	Tile Tile	Tile Tile	Tile Tile		DAC DAC	actuator actuator
						OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP	OFF-CHIP OFF-CHIP
			Multi-Layer BUS Multi-Layer BUS		MEM MEM	MEM MEM	MEM MEM	MEM MEM
			DXM DXM	POT POT
				ADC/DAC ADC/DAC
	Swiss Federal Institute of Technology Swiss Federal Institute				6 7			Computer Engineering and Networks Laboratory

of Technology Computer Engineering and Networks Laboratory IBM Cell Processor IBM Cell Processor 8 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Contents Contents

	Drivers
	Compositional Analysis  Overview Compositional p  Real-Time Calculus  Artificial Example A hi l I i Architectural Interactions Analysis y
	 Shared Resources in Multicore Systems
	 Compilation for Multiprocessors Challenges -Overview -
	Swiss Federal Institute of Technology	10	Computer Engineering and Networks Laboratory

11 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Analysis and Design Analysis and Design

	Embedded System =
	Computation + Communication + Resource Interaction
	Analysis:
	I f Infer system properties from t ti f
	subsystem properties.
	Design:
	Build a system

from subsystems Build a system from subsystems while meeting requirements. 12 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory System Composition System Composition Communication Templates Computation Templates DSP SDRAM ECU C CAN interface RISC Scheduling and Arbitration Templates Architecture proportional share WFQ EDF TDMA FCFS RISC SDRAM priority EDF share WFQ static dynamic fixed priority FCFS ECU priority ECU 13 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory ECU ECU Why Performance Analysis ? Why Performance Analysis ?

	Why Is Evaluation Difficult ? Why Is Evaluation Difficult ?
	Prerequisite for design space exploration (design decisions Non-determinism: Prerequisite for design space exploration (design decisions  uncertain system environment, e.g. load scenarios and optimization)  part of the feedback cycle part of the feedback cycle  (non-deterministic) computations in processing nodes
	Interference:  get inside into design characteristics and bottlenecks  support early design decisions pp y g  sharing exclusive resources (scheduling and arbitration)
	 interaction between resource types: exclusive
	Design validation g (computation, communication) and shared (energy)
	 verify system properties Long-term dependencies
	 resource feedback: internal data streams interact on  used at various design stages from early design until final l i hi h i t h t exclusive resources which in turn change stream implementation characteristics

18 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Difficulties Difficulties Processor Processor Task ab acc b Buffer Input Stream ab acc b Stream

	System-Level Evaluation Methods System Level Evaluation Methods
	e g delay e.g. delay
	Worst-Case
	Task Communication Task Communication Task Scheduling Best-Case	Variable Resource Availability Variable Execution Demand Variable Resource Availability
	Complex Input: Complex Input: -Timing (jitter, bursts, ...) Real System Measurement Simulation -Input (different event types) Worst Case Probabilistic Real System Measurement Simulation Worst Case Probabilistic -Input (different event types) -Internal State (Program, Cache, ...) Analysis Analysis
	-Different Event Types Different Event Types
	Swiss Federal Institute of Technology Swiss Federal Institute	19 20	Computer Engineering and Networks Laboratory

of Technology Computer Engineering and Networks Laboratory Overview System Overview

	Performance Estimation Methods Performance Estimation Methods
		designers		component
		experience p		simulation
			model of
	Measurements input	Formal Analysis application	Simulation	Statistics data
	traces				sheets
	model of model of	system system		model of model of
	environment	model		architecture
	Use existing spec. of Use existing instance of the system to inputs	Develop a mathematical mathematical abstraction of the system and estimation tool (method) program which Develop a program which implements a model of the	platform Develop a statistical benchmarks statistical abstraction of the system and
	perform pe o	derive formulas de e o u as	system. Perform syste e o	derive statistic de e stat st c
	performance	which describe		experiments by	performance via
	measurements.	the system performance. p estimation	running the program. p g	analysis or simulation.
	Swiss Federal Institute of Technology Swiss Federal Institute		21 22		Computer Engineering and Networks Laboratory

of Technology Computer Engineering and Networks Laboratory results Formal Analysis -Dynamic Models Formal Analysis Dynamic Models

	Combination between
	 Static models possibly extended by non-determinism in run-
	time and event processing
	D  Dynamic models for describing e.g. resource sharing i d l f d ibi h i
	mechanisms (scheduling and arbitration).
	Existing approaches

 Classical

real-time scheduling theory Classical real time scheduling theory  Stochastic queuing theory (statistical bounds)  Non-deterministic queuing theory (worst case

	o dete	/best case st c queu g t eo y ( o s case/bes case
	behavior)
	Swiss Federal Institute	23

of Technology Computer Engineering and Networks Laboratory Example -Queuing Systems Example Queuing Systems  Example: clients

  request some service from a server over a network  Example: clients request some service from a server over a network.

	24

Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Stochastic Models -Queuing Systems Stochastic Models Queuing Systems

	A queuing system is described by	Performance measures
	 Arrival rate Arrival rate	 average delay in queue average delay in queue
	 Service mechanism	 time-average number of customers
	 Queuing discipline	in queue.
		 proportion of time server is busy
	The classical M/M/1 queuing system:
	(M M k i ( (M = Markovian (exp.) distribution ) ) di t ib ti )

25 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Nondeterministic Models -Queuing Systems Nondeterministic Models Queuing Systems

	A queuing system is described by	Performance measures
	A i l f  Arrival function (bounds on ti (b d	t  worst case delay in queue d l i
	arrival times)  Service functions (bounds on ( Compositional p  worst-case number of customers in queue. q
	server behavior)  Resource interaction	 worst-case and best-case end-to-end delay in the system Analysis y
			TDMA TDMA
	GPC -Real-Time Calculus -GPC GPC
	GPC	GPC
	Swiss Federal Institute of Technology	26	Computer Engineering and Networks Laboratory

27 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Network/Real-time Calculus Methods Network/Real time Calculus Methods Advantages

  More powerful abstraction than "classical" real-time analysis  Resources are first-class citizens of the method

	Modular System Composition Modular System Composition
	CPU	BUS		DSP
	f ( )  Allows composition in terms of (a) tasks, (b) streams, (c) ( ) ( )
	resources, (d) sharing strategies.
	RM	TDMA
	Disadvantages
	 Needs some effort to understand and implement  Needs some effort to understand and implement TDMA
	 Extension to new arbitration schemes not always simple
	GPC	GPC	GSC	GPC

TDMA GPC GPC 30 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory GPC GPC Load Model (Environment)

				Service
				Model
	Load Model (Environment) Example 1:	Load Model Model	Processing Model Model
		events
	E Event Stream t St
	number of events in number of events in
	in t=[0 .. 2.5] ms
		2.5	t [ms] [ ]
	Arrival Curve 	d demand d	 u
			 l
	maximum / minimum
	arriving demand in any
	interval of length 2.5 ms g	2.5	 [ms]
	Swiss Federal Institute of Technology	31	Computer Engineering and Networks Laboratory

Periodic with Jitter Example 1: Periodic with Jitter

	A common event pattern that is used in literature can be
	ifi d b h specified by the parameter triple i l ( j d) h	d

of Technology Computer Engineering and Networks Laboratory Example 2: TDMA Resource Example 2: TDMA Resource

	Example 2:
	periodic periodic periodic jitter Swiss Federal h that are executed on a resource with bandwidth B that p p j  d 32 d ihb d idhB h controls resource access using a TDMA policy. Analogo sl e co ld consider a distrib ted s stem ith n Analogously, we could consider a distributed system with n communicating nodes, that communicate via a shared bus with bandwidth B with a bus arbitrator that implements bus with bandwidth B, with a bus arbitrator that implements a TDMA policy. TDMA policy: In every TDMA cycle of length , one single c p y y y g , g resource slot of length s i is assigned to application i. appl 1 appl 2 appl n appl 1 appl 2 appl n appl.1 appl.2 appl. n appl.1 appl.2 appl. n ... ... 35 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Institute Consider a real-time system consisting of n applications c c c c s n

TDMA Resource Example 2: TDMA Resource Service curves available

  to the applications / node i:

Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Delay? Internal Re-Shaping Delay? -7.4% Internal Re Shaping 44% Buffer? -

67 Task executing on Core 1 L1 Cache accessed L2 Cache accessed Main Memory accessed Task executing on Core 2 L1 Cache accessed L2 Cache is blocked by Core 1 -stall Task is executing on Core 1 L1 Cache accessed L2 Cache accessed Main Memory is blocked by CPU 1 -stall Main Memory request served Main Memory is accessed L2 Cache request served L2 Cache accessed Main Memory blocked by CPU 2 -stall Main Memory request served Main Memory accessed L1 Cache request served L2 Cache request served L1 Cache request served Main Memory access served L2 Cache request served L1 Cache request served Motivation (2)

	Interferences:
	CPU1/Core2 blocked by CPU1/Core1 on L2 Cache
	CPU2/Core1 blocked by CPU1/Core1 on Main Memory y y
	CPU1/Core2 blocked by CPU2/Core1 on Main Memory Task / Superblock Model (1) Motivation Related Work Task / Superblock Model (2) Static execution on the processing element Static Arbitration (2) Analysis for static arbitration -Summary Resource Access Models (1) Resource Access Models (2) -Reminder Resource Access Models (3) Comparisons of Access Models Conclusion
	 COTS Systems use shared resources (Memory, Bus) Multi-Core Architecture with shared resource  Tasks are structured as sequences of superblocks  3 Models to specify resource accesses:  Generate worst-case  Generate worst-case  analysis is complex  3 Models to specify resource accesses:  Resource Sharing in Multi-Core Systems is an important
	63  Multiple entities competing for shared resources Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory S5 4 4 C5.1 4 T5.1 T5.2 p p g  waiting for other entities to release the resource  accessing the resources C C C C C C C M i M t d C C C C  shared memory, communication peripherals, I/O peripherals Stalling due to Interference Stalling due to Interference  Depends on structure of tasks on the cores  Depends on blocking vs. non-blocking execution semantics  Depends on arbitration policy on the shared resource  static access, for example TDMA  dynamic access, for example round robin, FCFS, priority driven y p p y  Schliecker et al. [CODES 2006, CODES 2008, DATE 2010] [ ]  Event models specify tasks interference in time windows  tasks active time increases by number of interferences  Iterative approach to compute WCET  Iterative approach to compute WCET  Rosen et al. [RTSS 2007]  static analysis delivers feasible execution traces i TDMA h d l th WCET i t d  a given TDMA schedule the WCET is computed  efficient TDMA schedules are obtained using EA  fixed order of execution b d i d i i d d  upper bounds on execution and communication demands  Dedicated phases for resource access and computation  phases have different amount of access requests  phases have different amount of access requests  structure increases predictability (in terms of WCRT)  model motivated by industrial applications in the automotive industry di d d l  Dedicated Model  General Model  Hybrid Model  2 Models to execute superblocks:  Sequential Ti t i d ( bl k h ) 71  Time-triggered (superblocks, phases) trace  Read/Write access whenever slot is active whenever slot is active  Execution is performed p immediately A PE2 t 74  Assume PE2 grants 75 76 78 82 access: trace  Where to place the access requests ? access requests ?  Algorithm for WCCT g by maximizing stalling  Assume PE2 grants Assume PE2 grants access:  makes use of arrival and service curves (real-time calculus)  has been extended to dynamic resource sharing as well  analysis handles dedicated and general phases y g p  Influence of different access models on schedulability y  Influence of the execution model on predictability (equivalent WCRT) di d d l  Dedicated Model issue in terms of  Intuition:  Separation of resource access and computation increases predictability  Analyzability  Predictability ?  Everything time-triggered increases predictability  Everything time triggered increases predictability  Efficiency  Efficiency  General Model  sequential and time-triggered execution  analysis of mixed models possible by composition analysis of mixed models possible by composition  superblocks can be specified using different models  Time complexity  Time complexity  Dedicated phase:  General phase: ( ) O M Q ( lo ) g m ax O M exec  General phase: ( lo ) g O M exec Q  Static arbitration policies  Intuition:  Separation of resource access and computation increases predictability  Everything time-triggered increases predictability ? Everything time triggered increases predictability Eli i ti f I t f  Elimination of Interference  Hybrid Model  Excessive time-triggering may degrade performance  Tight bounds on WCCT can be derived ?  2 Models to execute superblocks: Ti t i d  Time-triggered  Separate Memory Access and Computation Separate Memory Access and Computation  Sequential  No advantage in terms of predictability  No advantage in terms of predictability  Model DS is model choice for resource sharing systems  Excessive time-triggering is counter productive

Even for simple models: 83 Even for simple models: Resource Sharing is a hard Problem Target Platform Abstraction (1) Target Platform Abstraction (1) Topology modeled by a graph

	 two node types:  two node types:			DXM interface DXM interface	DXM DXM
	• execution and comm. resources		Multi-layer BUS	NoC
	• storage resources g	DSP sub-system		AHB Master	DNP sub-
	Execution resources	AHB Slave	DMA	system
	 RISCs, DSPs, …	DSP	Int. Data Memory
	Communication resources	core
	 buses, switches, links, I/Os
	Storage resources  RAMs, HW FIFOs, …	DMX interface DMA	DXM	buf mem.
				bus bus	of switch of switch
		DSP	switch
				DNP
	Swiss Federal Institute	88

of Technology Computer Engineering and Networks Laboratory Target Platform Abstraction (2) Target Platform Abstraction (2)

	Mapping Specification Mapping Specification
	Binding
	 Processes to
	execution
	ATMEL Diopsis resources ATMEL Diopsis  SW channels to Platform read/write paths
	Scheduling g
	 Processors  Communication		Specification in XML syntax
	Constraints Constraints Specification  For Hardware-in XML syntax dependent
	Software (HdS) Software (HdS)
	generation
	Swiss Federal Institute of Technology Swiss Federal Institute	89 90	Computer Engineering and Networks Laboratory

of Technology Computer Engineering and Networks Laboratory DOL Design Flow DOL Design Flow

				Scheduling -Mapping Optimizer
	Performance Estimation	Performance Estimation
	application	architecture	mapping	architecture	application	mapping
					HdS / OS HdS / OS
					Compiler
				binary	VP simulator
	Swiss Federal Institute	91

of Technology Computer Engineering and Networks Laboratory Multiobjective Optimization Multiobjective Optimization

	x2	decision space	y2	objective space	Pareto optimal Pareto optimal = not dominated
					dominated
		x1		y1
	Swiss Federal Institute	92

of Technology Computer Engineering and Networks Laboratory Design Space Exploration Design Space Exploration 93 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Design Space Exploration Design Space Exploration Example for ATMEL Multitile Platform

  : 64 processes, 16 processors, optimal mapping known  32 processes execute efficiently on ARM, 32 efficiently on mAgic  different interconnection structures between processes  16 64  1.15  10 77 possible mappings (including symmetric ones)  Evaluation of 10 000 mappings Evaluation of 10.000 mappings

	diff	t i t	ti	t t	b t

max processor load 94 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory max. processor load max. interconnect load PISA Website PISA Website http

  ://www tik ee ethz ch/pisa http://www.tik.ee.ethz.ch/pisa

95 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory DOL Design Flow DOL Design Flow

			calibr. data data	Scheduling -Mapping Optimizer
	Performance Estimation	Performance Estimation
	application	architecture	mapping	architecture	application	mapping
					HdS / OS HdS / OS
					Compiler
				binary	VP simulator
	Swiss Federal Institute	96

of Technology Computer Engineering and Networks Laboratory Multitile Calibration Multitile Calibration 97 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Functional Simulation Functional Simulation

	Workload Extraction Workload Extraction WCET WCET (Timing) Predictability (Timing) Predictability
	process network p (with iterators) x = a + b; functional simulation response time p	LOAD LOAD LOAD	iterator_i accumulated r1, _b workload bounds r2 a r2, a	processes p behavior
	accumulated amount after amount after communication event	C2_0 generator ADD	C2_i consumer workload r3,r2,r1	.c .c WCRT .c .c … Bound
	flattened (w/o iterators) process network		XML Execution Time (Clock Cycles) XML Flattener PPC 755	WCRT WCRT
		350		square_1	square_2
	visualization	300 250 generator C2_0 200 150 200		C2_1	C2_2 consumer Clock Cycles	Simulation Generator number of consecutive BCRT BCRT
		0 50 100 0	Best Case	Worst Case	SystemC Si l ti Simulation events © R i h d Wilh l © Reinhard Wilhelm BCRT year Bound
	Swiss Federal Institute of Technology Swiss Federal Institute of Technology Swiss Federal Institute of Technology Swiss Federal Institute					98 99 109 110	Computer Engineering and Networks Laboratory Computer Engineering and Networks Laboratory Computer Engineering and Networks Laboratory

of Technology Computer Engineering and Networks Laboratory Bound WCET WCET © Reinhard Wilhelm 111 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Acknowledgement Acknowledgement

Classification of architectures

Timing compositional

No timing anomalies e. g., ARM7

Compositional with bounded effects Timing anomalies but no domino effects e. g., TriCore (probably)

Non-compositional architectures

Greedy Processing Component Greedy Processing Component

C ti t i db

Behavioral Description

• Component is triggered by incoming events.

• A fully preemptable task is

GPC

A fully preemptable task is instantiated at every event arrival to process the incoming event.

• Active tasks are processed in a greedy fashion in FIFO order.

P i i t i t db th

Tight Bounds Tight Bounds

[ , ]

Interfaces

WCET arbitration scheduler

Interfaces HW/SW

A task is (classically) characterized by its WCET.

 May be useful in case of simple processors, but we have long range state dependent uni processor behavior long-range state-dependent uni-processor behavior (pipelines, caches, speculation).  In case of multi-processors, we have additional interferences p , on the communication system which heavily influences WCET. We also may have intra-task parallelism.  WCET can no longer be considered as a useful interface between these abstraction layers.

What about the other interfaces ? What about the other interfaces ?

 Is the classical ISA (using instructions that abstract away time) still appropriate?


Nicolas Pous

Florence Azaïs

Laurent Latorre

Jochen Rivoir

AM-Demodulation of Analog/RF Signals Using Digital Tester Channels

Keywords: test, digital ATE, analog/RF circuits, level-crossing, coherent under-sampling, AM demodulation

This paper investigates a signal acquisition protocol based on level-crossings that permits the demodulation of AM analog/RF signals using only standard digital ATE. The fundamental concept is to capture the signal through the 1-bit comparator available in digital tester channels and to process the resulting bit stream to retrieve the analog/RF signal characteristics. The proposed solution is evaluated through both simulation and hardware experiments.

I. INTRODUCTION

The production test of analog and RF circuits traditionally involves dedicated instruments to perform the acquisition or generation of analog signals. This instrumentation is found in ATE platforms in the form of specific boards that are typically characterized by their sampling frequency and resolution (number of bits). Compared to traditional digital resources, these equipments are extremely expensive.

The requirements regarding instrumentation performance are obvious in the context of a final test, where the quality of the product has definitively to be guaranteed. Wafer-level test is less demanding, in particular if we consider that it must only be good enough to avoid throwing away too many packages. In this context, simpler tests with less capable equipment may be developed.

Our idea is to use standard digital ATE channels to perform some level of RF testing without increasing the cost of the ATE. More precisely, we investigate the opportunity of using the 1-bit digitizer available on low-cost digital channels boards to analyze analog/RF signals. This approach is motivated by the fact that devices operate at ever lower supply voltage while speed is ever increasing. Our idea is to exploit this trend and to convert the analysis of analog/RF signals from the voltage domain to the time domain [START_REF] Rivoir | Analog to digital signal conversion method and apparatus[END_REF]. In addition, it is worth noting that because digital channels are widely available on most ATE platforms, multi-site testing can be actually considered with almost no additional cost.

More specifically, our work investigates the reconstruction of analog/RF modulated signals to address wafer-level testing of telecommunication devices. Standard modulation schemes commonly involve phase/frequency or amplitude-shift keying, or a combination of both. In this paper, we focus on amplitude-modulated signals.

The paper is organized as follows. Section II summarizes our previous work on the reconstruction of phase/frequencymodulated signals based on zero-crossings. Using a similar approach, section III introduces the AM-demodulation concepts and examines the effects of acquisition parameters such as the sampling frequency or the crossing-level in the reconstruction properties. Simulation and experimental results are then discussed in sections IV and V respectively. Finally section VI concludes the paper.

II. PREVIOUS WORK

Our strategy to reduce the cost of testing analog/RF functions is to develop test solutions applicable with standard low-cost test equipment in order to provide wafer-level test coverage; the final product will be then tested at package-level using traditional solutions. This approach slightly differs from the main strategies presented in the literature, which consist in either inserting BIST features within the circuit in order to reduce the requirements of the test equipment [START_REF] Khaled | Frequency-based BIST for analog circuit Test Symposium[END_REF][START_REF] Hong | On-chip analog response extraction with 1 modulators[END_REF][START_REF] Negreiros | Low cost analogue testing of RF signal paths[END_REF][START_REF] Staszewski | RF Built Wireless Transmitter[END_REF], or applying shorter alternative tests instead of classical specification-based tests [START_REF] Variyam | Enhancing test effectiveness for analog circuits using synthesized measurements[END_REF][START_REF] Haider | Low receiver systems[END_REF]. Our strategy consists in complementing standard low-cost test equipment with signal processing techniques to enable the analysis of analog/RF signals. In particular, the approach is based on the concept of level-crossing detection, which has been widely used in many different application domains such as image and speech processing, wireless communications… but more sparingly in the context of analog/RF testing [START_REF] Brosa | Digit mixed-signal circuits[END_REF][START_REF] Su | Dynamic analog testing via ATE digital test channels Proc[END_REF].

As illustrated in figure 1, the proposed approach relies on the use of the comparator of a standard digital test channel as a 1-bit digitizer in order to convert the analog/RF signal into a bit stream whose transition time information represents the analog/RF signal characteristics. Signal processing algorithms can then be developed to extract the analog/RF signal characteristics. This approach has been introduced in [START_REF] Pous | Exploiting zero-crossing for the analysis of FM modulated analog/RF signals using digital ATE[END_REF] and a dedicated algorithm based on zero-crossing detection has been developed for the analysis of FM-modulated signals. Furthermore, coherent under-sampling has been exploited in 978-1-4244-7791-3/10/$26.00 ©2010 IEEE [START_REF] Pous | on the analysis of phse/frequency tester channels[END_REF] to extend the capabilities of test equipment with limited sampling frequency for the analysis of high-frequency signals.

In this section, we briefly recall the procedure for FMdemodulation of high-frequency signals. The procedure is based on the precise determination of the signal zero-crossing times. To illustrate the approach, let us consider an analog sine-wave sampled by a 1-bit comparator with a zero reference level. The resulting signal at the comparator output is a digital signal that switches from logical "0" to logical "1" and Time Stamps (TS) can be associated to the rising/falling transitions. Then for each pair of rising/falling transitions, the signal frequency can be computed as f=1/2∆TS , where ∆TS corresponds to the time delay between a pair of successive rising and falling transitions. In the ideal case, zero-crossings of the analog sine-wave result in unique transitions at the output of the comparator. However in practice, the analog signal is not a perfect but a noisy signal. As a consequence, multiple transitions at the vicinity of zero-crossings may be present in the digital signal delivered by the comparator (see figure 2). To filter these multiple transitions and associate a single Time Stamp to each zero-crossing, we have proposed a simple and robust algorithm based on a running average, i.e. counting the ratio between the numbers of "0" and "1" on a given number of samples. A Time Stamp TS is then associated to a transition when the ratio reaches 50%.

The FM-demodulation principle is directly based on the zerocrossing TS determination. More precisely, the principle consists in estimating the deviation of the signal frequency from the carrier frequency, for each period of the FMmodulated signal. Practically, the FM-modulated signal is sampled by the ATE comparator with zero reference level. To handle high-frequency signals, coherent under-sampling can be implemented. In this case, the signal is repeated an integer number of times (M), while an integer number of samples (N) is captured at a sampling rate f sample . To ensure coherency, the sampling frequency f sample , the message frequency f m , the number of samples N and the number of repetitions of the message signal M must fulfill the following relationship:

m sample f M f N = (1)
where N and M are whole positive integer values. Moreover, N and M must be chosen as co-prime integers to guarantee that samples will differ from one message signal period to another.

The first step of the post-processing algorithm is then to perform sample reordering on the digital bit stream stored in the ATE memory, also called the zero-crossing vector. The second step corresponds to running average computation and associated TS determination. Finally for each pair of successive rising and falling transitions (TS R,i /TS F,i ), i.e. for each period of the carrier signal, the deviation of the signal frequency from the carrier frequency f c is estimated by: 2 time at

) ( 2 1 ) ( , , , , i F i R i c i F i R i TS TS t f TS TS t f + = - - = ∆ (2)
This reconstructed signal is a discrete signal that corresponds to the modulating signal and that can be further analyzed using FFT for instance.

III. AM-DEMODULATION

In this section, we introduce the principle of AMdemodulation based on level-crossing. The concept is similar to FM-demodulation but this time, the idea is to convert the amplitude information contained in an analog/RF signal into timing information contained in the digital bit stream. The comparator should therefore be set with a reference level different than zero.

A. Basics of amplitude estimation

First to illustrate the approach, we consider an ideal analog sine-wave expressed by: ) Assume that this analog sine-wave is sampled by a 1 comparator with a reference level C different than zero sampling rate f sample . The resulting bit stream can be processed to determine the Time Stamps TS R/F associated with the level crossings of the signal.

Figure 3 illustrates the Time Stamps associated to level crossings for two ideal sine-waves with different amplitude. It can be seen that the larger the sine-wave amplitude, the larger the difference ∆TS between a rising and transitions. This difference is actually directly related to the sine-wave amplitude with:

) cos( i i TS f C A ∆ * * = π
The assumption here that the signal frequency is known is not a strong requirement. Indeed, either the frequency is effectively known from the application, either it can be easily determined from two successive rising (or falling) transitions of the zero-crossing vector with:

1 , / 1 , / i F R i F R TS TS f - = +
Finally, note that in practice we will not have ideal sine waves but noisy ones, so the running average algorithm will be used to have a correct estimation of the Time Stamps. Besides, coherent under sampling can be implemented to handle high-frequency signals.

B. Amplitude demodulation

Let us now consider the case of an amplitude signal defined by:

) 2 sin( ) ( ) ( t f t A t S AM * * * = π
In the specific case of a modulation with we have: [ ]

0 0 / and with sin( )) 2 cos( 1 ( ) ( A A A A t f t S m c m AM = + = * + * * + = β α ϕ π β α
where A c and f c are the amplitude and the frequency of the carrier signal, A m and f m are the amplitude and crossings for two ideal waves of different amplitude wave is sampled by a 1-bit different than zero, at a . The resulting bit stream can be processed associated with the levelillustrates the Time Stamps associated to levelwith different amplitude. It wave amplitude, the larger between a rising and consecutive falling transitions. This difference is actually directly related to the (4) that the signal frequency is known is not a strong requirement. Indeed, either the signal frequency is effectively known from the application, either from two successive rising (or crossing vector with:

(

Finally, note that in practice we will not have ideal sinewaves but noisy ones, so the running average algorithm will be used to have a correct estimation of the Time Stamps. Besides, coherent under sampling can be implemented to Let us now consider the case of an amplitude-modulated [START_REF] Variyam | Enhancing test effectiveness for analog circuits using synthesized measurements[END_REF] modulation with a sinusoidal signal,

) 2 sin( t f c * * π (7)
are the amplitude and the frequency of the are the amplitude and the frequency of the modulating signal (further called "the message"), and is the offset voltage.

Here again the demodulation principle is based on the Time Stamp determination previously introduced. The idea is to estimate, for each period of the AM the modulated signal with e corresponds to the amplitude of the reconstructed signal at time

t i = (TS R,i + TS F,i ) / 2.
Figure 4 summarizes the proposed flow, which is very similar to the FM-demodulation case. The only differences are that the comparator should be set with a reference level different than zero, and eq message amplitude from the Time Stamps.

IV. SIMULATION RESULTS

In this section, we investigate the effectiveness of the proposed algorithm through simulations. First, we analyze on a simple sine-wave the impact of the comparator threshold, number of acquired samples, and noise level, on the accuracy of the estimated amplitude. Then, we evaluate the performances of the AM-demodulation algorithm on a practical case study.

A. Amplitude estimation results

A number of MATLAB simulations have been performed considering a simple sine amplitude 1V and varying the sampling rate, for different values of the comparator reference level. For each simulation, we have estimated the amplitude over 10,000 periods of the signal, and we have computed the mean value and the standard deviation of the estimated amplitude. Results are summarized in figure which gives the estimation error on the mean value together with measurement standard deviation under different conditions.

the modulating signal (further called "the message"), and Α ο Here again the demodulation principle is based on the Time Stamp determination previously introduced. The idea is to estimate, for each period of the AM-signal, the amplitude of eq (4). This amplitude directly corresponds to the amplitude of the reconstructed signal at summarizes the proposed flow, which is very demodulation case. The only differences uld be set with a reference level different than zero, and eq (4) is used to compute the message amplitude from the Time Stamps. demodulation using ATE digital channel

ESULTS

In this section, we investigate the effectiveness of the proposed algorithm through simulations. First, we analyze on wave the impact of the comparator threshold, number of acquired samples, and noise level, on the accuracy mplitude. Then, we evaluate the demodulation algorithm on a Amplitude estimation results A number of MATLAB simulations have been performed considering a simple sine-wave signal of amplitude 1V and varying the noise level and the ATE sampling rate, for different values of the comparator reference level. For each simulation, we have estimated the amplitude over 10,000 periods of the signal, and we have computed the mean value and the standard deviation of the imated amplitude. Results are summarized in figure 5, which gives the estimation error on the mean value together with measurement standard deviation under different Figure 5.a analyzes the influence of the comparator reference level for different numbers of samples per period in case of a sine-wave with 5% noise. A first comment is that better results are obtained when the comparator reference level is higher than 50% of the signal amplitude. Indeed for all values of the comparator reference level above 0.5V, the estimation error on the mean amplitude value remains below ±1%; the estimation error increases with a overestimation of the signal amplitude for lower values of the comparator reference level.

These results show that the amplitude can be with a good accuracy whatever the comparator reference level, provided that enough samples are collected. Indeed, the estimation error on the amplitude mean value can 5% when using only 60 samples per period with a comparator reference level at 0.2V whereas this error remains below ±1% when 220 samples or more are collected whatever the comparator reference level. So a first recommendation to achieve good accuracy in amplitude estimation is to collect at least 200 samples per signal period. Nevertheless, measurements show a relative dispersion, with a standard deviation that goes from 10% down to 1% when the comparator reference level increases from 20% to 80% of the signal amplitude range, for 220 or more samples per period. So a second recommendation is to set the comparator reference level as high as high as possible with respect to the signal amplitude.

To further validate these results, we have performed experiments varying the level of noise injected in the signal from 1% up to 10%. As illustrated by figure samples collected per period, the noise level has an impact on the accuracy of prediction but even in presence of 10% noise in the signal, the estimation error on the mean .a analyzes the influence of the comparator reference level for different numbers of samples per period in with 5% noise. A first comment is that ed when the comparator reference level is higher than 50% of the signal amplitude. Indeed for all values of the comparator reference level above 0.5V, the estimation error on the mean amplitude value remains below ±1%; the estimation error increases with a systematic overestimation of the signal amplitude for lower values of the hese results show that the amplitude can be estimated with a good accuracy whatever the comparator reference level, provided that enough samples are collected. Indeed, the estimation error on the amplitude mean value can be as high as 5% when using only 60 samples per period with a comparator nce level at 0.2V whereas this error remains below ±1% when 220 samples or more are collected whatever the comparator reference level. So a first recommendation to achieve good accuracy in amplitude estimation is to collect at period. Nevertheless, measurements show a relative dispersion, with a standard deviation that goes from 10% down to 1% when the comparator reference level increases from 20% to 80% of the signal amplitude range, for 220 or more samples per period. ond recommendation is to set the comparator reference level as high as high as possible with respect to the To further validate these results, we have performed experiments varying the level of noise injected in the signal 10%. As illustrated by figure 5.b for 380 samples collected per period, the noise level has an impact on the accuracy of prediction but even in presence of 10% noise in the signal, the estimation error on the mean amplitude value remains in the range of ±1 comparator reference level. However dispersion on the measurements can be relatively important depending on the comparator reference level.

B. AM-demodulation results

To validate the AMconsider an AM-signal with a carrier frequency and a modulating frequency study. The ratio between the maximum amplitude and minimum amplitude of the AM A 0 =2V and A c =A m =1V. Moreover, to be able to perform an FFT with an acceptable resolution on the reconstructed message, the signal to be analyzed is made of 32 message periods.

The AM-demodulation algorithm has been simulated for different values of the comparator reference level from 20% up to 80% of the minimum AM corresponds to about 6% up to signal amplitude. A clock-jitter, random time-shift of the sampling event with been included in all simulations in order to consider realistic practical conditions.

Figure 6 gives the time-domain and representations of the reconstructed signal, for two different time resolutions of 2.5ps and 1ps both cases the post-processing algorithm permits the message, and this, whatever the value of the comparator reference level. However as expected, the quality of the reconstructed signal is better for higher comparator level and time resolution. amplitude value remains in the range of ±1% whatever the comparator reference level. However dispersion on the measurements can be relatively important depending on the demodulation results -demodulation algorithm, we signal with a carrier frequency f c = 2.5GHz quency f m = 40MHz as a practical case study. The ratio between the maximum amplitude and minimum amplitude of the AM-signal is set to 3 with =1V. Moreover, to be able to perform an FFT with an acceptable resolution on the reconstructed e, the signal to be analyzed is made of 32 message demodulation algorithm has been simulated for different values of the comparator reference level from 20% up to 80% of the minimum AM-signal amplitude, which about 6% up to 26% of the maximum AM--jitter, modeled as a Gaussian shift of the sampling event with σ =1ps, has been included in all simulations in order to consider realistic domain and the spectral-domain the reconstructed signal, for two different time resolutions of 2.5ps and 1ps. It clearly appears that in processing algorithm permits to retrieve the message, and this, whatever the value of the comparator reference level. However as expected, the quality of the is better for higher comparator level These first results demonstrate the capability of the technique to perform AM-demodulation. In order to further validate the technique, we have performed similar simulations including noise in the signal. Results a summarized in Table I, which reports the SNR values measured over 160MHz bandwidth on the reconstructed signal with 2.5ps and 1ps resolution, for different levels of noise injected in the AM-signal. Results are in agreement with the preliminary study performed in the previous section. We observe a smooth degradation of the quality of the reconstructed signal when the level of noise increases, with an SNR value that reduces by about 5dB when the noise level increases from 0 to 10%. In addition, we clearly observe the im quality of the reconstructed signal when increasing the number of acquired samples and for higher values of the comparator reference level. Note that even a comparator reference level at 80% of the minimum A amplitude is not the most favorable case for accurate amplitude estimation, as it only corresponds to 26% of the maximum AM-signal amplitude. To further improve the accuracy, a potential solution may consist in combining multiple level-crossings.

V. HARDWARE EXPERIMENTS

Hardware measurements have been performed to support these results. Hardware measurements have been carried out using the test setup depicted in figure analyzed is generated by an RF source (Agilent N9310A) directly connected to a PS3600 digital channel 93K ATE. The 10MHz output signal of the RF source is used to synchronize the tester. Indeed, the sample reordering process associated with the under-sampling method requires a very precise synchronization between the analog signal to be captured and the ATE sampling clock.

These first results demonstrate the capability of the demodulation. In order to further validate the technique, we have performed similar simulations including noise in the signal. Results are summarized in Table I Results are in agreement with the preliminary study previous section. We observe a smooth degradation of the quality of the reconstructed signal when the level of noise increases, with an SNR value that reduces by about 5dB when the noise level increases from 0 to 10%. In addition, we clearly observe the improvement in the quality of the reconstructed signal when increasing the number of acquired samples and for higher values of the . Note that even a comparator reference level at 80% of the minimum AM-signal amplitude is not the most favorable case for accurate amplitude estimation, as it only corresponds to 26% of the signal amplitude. To further improve the accuracy, a potential solution may consist in combining measurements have been performed to support these results. Hardware measurements have been carried out 7. The signal to be analyzed is generated by an RF source (Agilent N9310A) ly connected to a PS3600 digital channel of the Verigy 93K ATE. The 10MHz output signal of the RF source is used to synchronize the tester. Indeed, the sample reordering sampling method requires a ion between the analog signal to be We have considered the case study used in simulation to experimentally validate the AM However due to the limited capabilities of our RF source, hardware measurements are performed with a downscaling of 1,000 with respect to simulation, i.e. t to output an AM-modulated frequency, 40kHz modulation frequency depth of 50%. To maintain the same number of samples as in the simulation experiments, the downscaling of 1,000 is also applied on the ATE sampling frequency, which results in a time resolution of 2.5ns and 1ns for 320,000 and 800,000 captured samples respectively. resolution can be achieved with a direct acquisition of the samples without reordering, but that coherent under sampling and reordering is mandatory to achieve the 1n resolution (ATE sampling frequency e have considered the case study used in simulation to the AM-demodulation algorithm. However due to the limited capabilities of our RF source, hardware measurements are performed with a downscaling of 1,000 with respect to simulation, i.e. the RF source is set modulated signal with 2.5MHz carrier 40kHz modulation frequency and a modulation maintain the same number of samples as in the simulation experiments, the downscaling of 1,000 is also applied on the ATE sampling frequency, which results 2.5ns and 1ns for 320,000 and 800,000 captured samples respectively. Note that the 2.5ns resolution can be achieved with a direct acquisition of the samples without reordering, but that coherent undersampling and reordering is mandatory to achieve the 1ns ATE sampling frequency limited to 400MHz). Figure 8 gives the time-domain and the spectral representations of the reconstructed signal for the 2.5ns resolution and two different values of comparator reference level set at 30% and 80% of the minimum AM amplitude. Analyzing these results, it can be clearly observed that a better reconstruction of the message is achieved when increasing the compara The quantization in the time-domain reconstructed signal is visibly reduced, the overestimation is lessened; and the SNR improves from 15dB up to 25dB. These good agreement with simulation results. Figure 9 gives the time-domain and the spectral representations of the reconstructed signal when using a 1ns resolution and a comparator reference level at 80% of the minimum amplitude. A good accuracy on the message reconstruction is achieved with a clean time representation, an estimated signal well 1V and 3V minimum and maximum amplitudes, SNR that improves up to 34dB. Here again, these results are in accordance with simulation results.

More generally, these hardware experiments validate the proposed technique since they actually show that the message of an AM-signal can be reconstructed from the sampling of the signal through a digital tester channel. reconstruction depends on both the time resolution and the comparator reference level. Considering the practical case study investigated in this paper, an SNR obtained when using only 160 samples per carrier period and around 21dB when using 400 samples per carrier period, for a comparator reference level at 30% of the AM amplitude. When the comparator reference level is set to 80% of the AM-signal minimum amplitude, the SNR improves up to 25dB when using 160 samples per carrier when using 400 samples per carrier period.

VI. CONCLUSION

This paper investigates a signal acquisition protocol based on level-crossing and dedicated post-processing reconstruction algorithm in order to develop low-cost domain and the spectral-domain representations of the reconstructed signal for the 2.5ns resolution and two different values of comparator reference level set at 30% and 80% of the minimum AM-signal these results, it can be clearly observed that a better reconstruction of the message is achieved when increasing the comparator reference level.

domain reconstructed signal is visibly reduced, the overestimation is lessened; and the SNR from 15dB up to 25dB. These values are in rather signal for 1ns resolution and 0.8V comparator reference level domain and the spectral-domain representations of the reconstructed signal when using a 1ns resolution and a comparator reference level at 80% of the A good accuracy on the message reconstruction is achieved with a clean time-domain , an estimated signal well-centered between 1V and 3V minimum and maximum amplitudes, and an SNR that improves up to 34dB. Here again, these results are experiments validate the proposed technique since they actually show that the message signal can be reconstructed from the sampling of the signal through a digital tester channel. The accuracy of the reconstruction depends on both the time resolution and the comparator reference level. Considering the practical case study investigated in this paper, an SNR around 15dB is obtained when using only 160 samples per carrier period and when using 400 samples per carrier period, for a comparator reference level at 30% of the AM-signal minimum amplitude. When the comparator reference level is set to 80% signal minimum amplitude, the SNR improves up 0 samples per carrier period and 34dB when using 400 samples per carrier period. This paper investigates a signal acquisition protocol based processing reconstruction cost test strategies for analog/RF devices. The idea is to use the comparator available in ATE digital channels to perform the signal capture and conversion in the digital domain; the resulting bit stream is then processed to retrieve the analog/RF signal chara In this paper, we have focused on the analysis of amplitude modulated signal. First, we have investigated the impact of acquisition parameters on the reconstruction quality, leading to basic rules for the determination of the sampling frequency and the comparator threshold. Then, we have investigated through simulation the performance of the AM algorithm on case study. Finally, hardware experiments have been presented demonstrating the viability of the proposed technique.

Figure 1 .

 1 Figure 1. Primary idea

Figure 2 .

 2 Figure 2. Time Stamp determination from running average

Figure 3 .

 3 Figure 3. Time Stamps associated to level-crossings sine-waves of different amplitude

Figure 4 .

 4 Figure 4. AM-demodulation

Figure 5 .

 5 Figure 5. Amplitude estimation error: mean value and standard deviation

  a) Influence of the comparator reference level for different numbers of samples period with a noise level of 5% b) Influence of the noise level for different values of the comparator signal period estimation error: mean value and standard deviation

Figure 6 .

 6 Figure 6. Reconstructed signal for different time resolutions comparator reference levels

Figure 7 .

 7 Figure 7. AM-demodulation

Figure 8 .

 8 Figure 8. Reconstructed signal for 2.5ns resolution and different values of the comparator reference level

Figure 9 .

 9 Figure 9. Reconstructed signal for 1ns resolution and 0.8V comparator reference level

TABLE I

 I

	.	SNR VALUES MEASURED ON THE RECONSTRUCTED SIG
	FOR DIFFERENT TIME RESOLUTIONS AND DIFFERENT
		INJECTED IN THE AM-SIGNAL
				Comparator reference level
			0.2	0.4
		without noise	15dB	22dB
	2.5ps	SNRIN=34dB	15dB	21dB
	time
	resolution	SNRIN=26dB	12dB	20dB
		SNRIN=20dB	9dB	17dB
		without noise	20dB	26dB
	1ps	SNRIN=34dB	19dB	26dB
	time
	resolution	SNRIN=26dB	17dB	24dB
		SNRIN=20dB	14dB	22dB

ACKNOWLEDGMENTS

The authors would like to acknowledge Dr. Beatrice Pradarelli for technical support during hardware validation. Hardware experiments have been performed using the equipment of the CNFM Test Resource Center in Montpellier sponsored by Verigy® and Région Languedoc Roussillon.

analog/RF devices. The idea is to use the comparator available in ATE digital channels to perform the signal capture and conversion in the digital domain; the resulting bit stream is then processed to retrieve the analog/RF signal characteristics. In this paper, we have focused on the analysis of amplitudemodulated signal. First, we have investigated the impact of acquisition parameters on the reconstruction quality, leading to basic rules for the determination of the sampling frequency and the comparator threshold. Then, we have investigated through simulation the performance of the AM-demodulation algorithm on a case study. Finally, hardware experiments have been presented demonstrating the viability of the proposed The authors would like to acknowledge Dr. Beatrice Pradarelli for technical support during hardware validation. Hardware experiments have been performed using the equipment of the CNFM Test Resource Center in Montpellier égion Languedoc Roussillon.