Salim El Ghouli
email: salim.elghouli@st.com

Patrick Scheer

Michel Minondo

André Juge

Thierry Poiroux

Jean Michel Sallese

Christophe Lallement

Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model

Keywords: FDSOI, UTBB, Leti-UTSOI, Analog and RF, Compact Model, low-power I

Ultra-Thin Body and Box (UTBB) Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs exhibit very high transit frequency granting advantageous RF and low-power circuits design. This requires accurate models describing transistor behavior in all operating regimes including low levels of MOSFET channel inversion. In this paper, Leti-UTSOI based RF model will be compared against electrical measurements from 28nm FDSOI devices operating down to low bias conditions. The outcome demonstrates the accuracy and efficiency of Leti-UTSOI for lowpower and RF applications design.

INTRODUCTION

Both FinFET and planar Fully Depleted SOI (FDSOI) technologies fulfill the International Technology Roadmap for Semiconductors (ITRS) requirements for device downscaling. The two architectures allow excellent channel control for high digital performances [START_REF] Chevillon | Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling[END_REF][2] [START_REF] Hartmann | FD-SOI Technology Development and Key Devices Characteristics for Fast, Power Efficient, Low Voltage SoCs[END_REF]. However, analog and RF performances are affected unevenly.

It has been demonstrated that planar FDSOI technology with ultra-thin Body and BOX (UTBB) transistors exhibits excellent analog and RF performances and outperforms bulk and FinFET technologies on various RF aspects [START_REF] Flandre | Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits[END_REF] [START_REF] Kilchytska | Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications[END_REF]. Furthermore, FDSOI is claimed to outperform FinFET in terms of cutoff frequencies [START_REF] Raskin | FinFET versus UTBB SOI -a RF perspective[END_REF]. In recent low power and high performance circuits such as those implemented in FDSOI for IoT market, one needs to operate MOSFET transistors from weak to strong inversion levels [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. It is worth pointing that moderate inversion region has been found to be a good compromise while power consumption and speed are valued equally [START_REF] Mangla | Figure-of-merit for optimizing the current-efficiency of low-power RF circuits[END_REF][9] [START_REF] Ghouli | Dynamic behavior of the UTBB FDSOI MOSFET[END_REF].

In order to fully benefit from the advantages of the FDSOI technology, MOSFET compact models should accurately reproduce transistor behavior in all regions of operation especially in low inversion. Leti-UTSOI is the first available independent double-gate compact model able to describe accurately the UTBB MOSFET in all bias conditions, including strong forward back bias [START_REF] Poiroux | Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies -Part I: Interface Potentials Analytical Model[END_REF].

Leti-UTSOI model was validated against numerical simulations and measurements for DC operation showing excellent predictability and scalability properties [START_REF] Poiroux | Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies -Part II: DC and AC Model Description[END_REF]. However, its RF capabilities have been only highlighted in [START_REF] Barbé | 4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors[END_REF] and clearly ask for more in depth analysis. This paper will focus on the ability of Leti-UTSOI model to describe the small signal RF behavior of UTBB MOSFET at low voltage biases. The paper will first focus on the DC operation of the Leti-UTSOI model, especially for low inversion levels, introducing electrical parameters normalization process. Secondly, RF figures of merit will be compared versus measurements with emphasis on moderate inversion.

II. DC AND LOW FREQUENCY OPERATIONS

A. Leti-UTSOI model

Leti-UTSOI (UTSOI) is a surface potential based compact model describing the ultra-thin fully depleted SOI MOSFET with a lightly doped silicon film [START_REF] Poiroux | UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs[END_REF]. UTSOI physical core is suitable for any independent double gate transistor with lowdoped channel, and in particular for UTBB-FDSOI architectures as depicted in Fig. 1. The device parameters are TSi = 7 nm (silicon film thickness), Tox2 = 25 nm and Tox1 = 1.3 nm (equivalent back and front gates oxide thicknesses respectively), and a Well-type implantation is used for the ground-plane or back gate region under the BOX [START_REF] Planes | 28nm FDSOI technology platform for high-speed low-voltage digital applications[END_REF].

Explicit formulations of the front and back surface potentials (ψs1, ψs2) are used to calculate the drain current (ID) and the intrinsic mobile charge (Qinv). Short and narrow channel effects, series resistance, overlap capacitance, fringing capacitance and backplane related parasitic capacitances are all accounted for. UTSOI small-signal equivalent schematic valid in lowfrequency operation is depicted in Fig. 2. It includes intrinsic MOSFET components and extrinsic elements such as source and drain series resistances (Rs and Rd respectively). Even though explicit resistances are shown in Fig. 2, UTSOI takes series resistances effect implicitly. Gate-to-source (Cgs), gate-to-drain (Cgd) and front-to-back gates (Cgb) capacitances are also included as shown in Fig. 2. The UTSOI satisfies continuity requirements for currents and capacitances as well as for their higher order derivatives. It is compliant with all MOSFET standard models criteria such as DC and AC symmetry and robustness in all operating conditions [START_REF] Li | Benchmark Tests for MOSFET Compact Models With Application to the PSP Model[END_REF].

B. DC Model extraction and normalization

DC and CV operations accuracy is a prerequisite for RF modeling. External connections related resistances are extracted before proceeding to a standard extraction flow similar to the one described in [START_REF] Smit | PSP 103.3 User's manual[END_REF]. Parasitic series resistances are extracted using dedicated RF "SHORT" structures DC and S-parameters measurements. The SHORT structure represents the measured Device Under Test (DUT) where gate, drain and common source and back gate are all shorted (Fig. 3).

Several gate lengths and widths are measured and used for DC parameters extraction purpose. Long and wide structures are first used to extract main model parameters such as front oxide and BOX thicknesses, gates work-functions, effective and saturated mobility parameters and gate leakage. Short and narrow devices are then used to extract small geometry effects parameters. In saturation, fine tuning requires an estimate of the structure environment thermal resistance.

In the following, measured and simulated quantities are normalized as described in Table I.

C. DC model assessment

In this section DC and CV UTSOI operation is compared against measurements of short and long (L = 30 nm and 2 µm respectively) NMOS and PMOS devices. To be consistent with RF operation assessment, multi-finger structures are used (with a number of fingers of Nf = 10). NMOS convention gate voltage overdrive Vgt = TYPE.(VG -VT0) is used for current, transconductance and capacitances plots.

1) IV operation

Accurate transfer characteristic Id(VG) simulation is a critical condition for rigorous analog and RF modeling. Not only is the drain current accuracy required but also its first (transconductance) and second derivatives to estimate parasitic signal distortions in RF operation. Fig. 4 shows the transfer characteristic for NMOS and PMOS considering short and long channels. The normalized drain current in logarithmic scale is convenient to capture weak and moderate inversion behaviors while the linear scale highlights the strong inversion region, see Fig. 5. Subthreshold slope is accurately captured in weak inversion for both long and short channels. In strong inversion, series resistance impact, length modulation as well as mobility saturation effects (noticeable even at low |VD|) are correctly reproduced. UTSOI is also correctly describing the complex moderate inversion region.

Normalized transconductance gm is shown in logarithmic and linear scales in Fig. 6 and Fig. 7 (inset being the second order derivative of the current) respectively vs. overdrive voltage (linear scale) for short and long channel NMOS and PMOS. An excellent matching with the transconductance and its derivative in weak, moderate and strong inversion is observed. The normalized transconductance efficiency FOM is depicted in Fig. 8 vs. the normalized drain current. This FOM is important for low-power analog and RF design [START_REF] Silveira | A g m/I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA[END_REF]. Transconductance efficiency chart allows accurate hand calculation in all MOSFET inversion regions including moderate inversion that is complex to model and no analytical model is required. The results show UTSOI capability to accurately reproduce the UTBB DC behavior.

2) CV operation

For accurate low-voltage analog and RF modeling, MOSFET capacitances should be predicted in all operating conditions including moderate and weak inversion regions. In Fig. 9 and Fig. 10

III. RF AND HIGH FREQUENCY OPERATION

Only DC-based extraction leads to RF performance overestimation therefore RF extraction is required to mitigate high frequency operation real performances. To this purpose, Multi-finger MOSFET structures are embedded in Coplanar Waveguide (CPW) pads for RF characterization. Multi-finger and wide structures are used to obtain higher RF gain since gm ~ Nf.W/L. S-parameters are measured in a frequency range from 100 MHz up to 110 GHz in linear, saturation and for all channel inversion levels: weak, moderate and strong. A standard 2-port measurement setup shown in Fig. 11 is used where Gate and Drain represent port 1 and 2 respectively, source and back gate being shorted and grounded.

A. RF extraction and equivalent schematic

Capacitive and resistive extrinsic contributions (outside MOSFET channel) must be characterized and excluded carefully. In order to get rid of these parasitic contributions, RF For high frequency operation, UTSOI requires the addition of a distributed front gate resistance Rg similar to the PSP standard model one [START_REF] Smit | PSP 103.3 User's manual[END_REF] and a back gate resistance Rb. The final equivalent schematic is shown in Fig. 12 (right) where series resistances Rs and Rd are included in UTSOI and already extracted in previous DC related section. Front gate resistance Rg takes into account several contributions shown in Fig. 12 (left): (a) the contact resistances, (b) the horizontal gate sheet resistance and finally (c) the vertical gate resistance related to the processed gate stack. Rg is calculated as:

𝑅 𝑔 = 1 𝑁 𝑓 (𝑅 𝑐𝑜𝑛𝑡𝑎𝑐𝑡 + 𝑅 𝑠ℎ . 𝑊 𝑓 3×𝐿 + 𝑅 𝑖𝑛𝑡 . 1 𝐿×𝑊 𝑓 ) ( 1
)
where Rcontact is the unitary contact resistance, Rsh is the horizontal sheet resistance and Rint is the interface vertical resistance. Back gate resistance Rb describes the resistive access to the ground plane underneath the BOX. Rb resistance takes into account the structure layout in a simple manner using access perimeter Pbgate. In the following Rb expression, the horizontal resistive path under the box is considered to be negligible in comparison to the vertical strap access.

𝑅 𝑏 = 𝑅 𝑏𝑠ℎ × 1 𝑃 𝑏𝑔𝑎𝑡𝑒 (2)
In order to extract Rb and Rg related parameters, deembedded S-parameters are transformed into Y-parameters and following two expressions are fitted in high frequency operation:

𝑅 𝑔 = 𝑅𝑒[𝑌 11 ] (𝐼𝑚[𝑌 11 ]) 2 (3)
This expression is used to calculate the effective high frequency gate resistance. The second expression is the well-known Mason's Unilateral Gain that is sensitive to Rb:

Transconductance is extracted in DC using drain current derivative and also in RF using Re(Y21-Y12) expression. It is important to point out that in low-frequency, the two quantities must be equal and should diverge at high frequency operation as the effective transconductance and consequently gain decreases with frequency increase. Mason's unilateral power gain. The first quantity denoted fT is an interesting FOM for high-speed digital applications where speed and high swing are required. It is extracted at 0 dB current gain |H21|dB (or |H21| = 1). Fig. 13 shows the current gain plots for several inversion levels. We notice that gain becomes practically constant for low levels of inversion. This occurs at higher frequencies and fT extraction at |H21| = 1 is still valid provided a suitable -20 dB asymptote is used. Current gain |H21| vs. frequency presented in Fig. 13 as well as fT vs. Id shown in Fig. 14 are accurately reproduced with UTSOI model. fT alone is not sufficient to assess MOSFET performance at high frequency operation as it does not account for the impact of some important parasitic elements such as the gate resistance. fmax however, defined as the frequency at which the extrapolated Mason's gain given by expression (4), is a more suitable FOM for RF analog applications such as microwave amplifiers. Both front gate and back gate resistances impact is accounted for using fmax FOM vs. Id.

Fig. 15 shows the simulated and measured fmax vs. Id demonstrating the enhanced UTSOI RF model accuracy at high frequency operation. At weak inversion, Mason's gain slope increases with frequency and this behavior is captured with Rb resistance [START_REF] Dormieu | 4-Port isolated MOS modeling and extraction for mmW applications[END_REF]. Back gate resistance Rb impact is revealed and correctly reproduced in the frequency dependence of fmax vs. Id curves particularly in weak inversion up to 80 GHz (Fig. 16).

C. Performance and consumption tradeoff FOM

fT and fmax figures of merit are suitable for applications where only speed/performance is valued. The maximum value of these FOMs is obtained in strong inversion where transconductance efficiency (gm/Id) is low. Consequently, these FOMs are not suitable for low-voltage RF applications where performance and consumption are valued equally. The more convenient FOM for such low-consumption and high speed applications is the one introduced in [START_REF] Shameli | Ultra-Low Power RFIC Design Using Moderately Inverted MOSFETs: An Analytical/Experimental Study[END_REF] and given as:

𝐹𝑂𝑀 𝑅𝐹 = 𝑓 𝑇 .
𝑔 𝑚 𝐼 𝑑 [START_REF] Kilchytska | Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications[END_REF] This FOM captures both the transconductance efficiency and RF performance. It is also convenient as it allows to keep the noise factor in sight [START_REF] Mangla | Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model[END_REF]. The maximum value of this RF FOM represents the best tradeoff between power consumption and speed.

In Fig. 17

IV. CONCLUSION

In this work we demonstrate that Leti-UTSOI based model is well-suited for modeling 28 nm UTBB FDSOI NMOS and PMOS RF devices. Characterization conditions include length scaling down to nominal value, a wide frequency range up to 110 GHz, and operation under different channel inversion levels down to low current and low voltage regime. An excellent agreement is shown over more than eight decades of current density for DC and four decades for RF. The optimum operating point for low-power RF lies in the moderate inversion where UTSOI model is very well-suited. In particular, this work demonstrates the accuracy of Leti-UTSOI based RF models to enable RF and Low Power circuit design applications in UTBB FDSOI technology.

Fig. 1 .

 1 Fig. 1. UTBB transistor architecture (cross-section) with modeled charges as well as front and back surface potentials.

Fig. 2 .

 2 Fig. 2. UTSOI equivalent schematic for small signal and low-frequency operation including series resistances Rs and Rd.

Fig. 3 .

 3 Fig. 3. SHORT structure equivalent schematic used to extract parasitic external resistances Rg_ext, Rd_ext and Rsb_ext (gate, drain and common source and back gate terminals series resistances respectively, source and back gate being shorted).

Fig. 4 .

 4 Fig. 4. Id vs. gate voltage overdrive in linear operation |VD| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C.

Fig. 5 .

 5 Fig. 5. Id vs. TYPE.(VG -VT0) in linear operation |VD| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C.

Fig. 6 .Fig. 7 .

 67 Fig. 6. Transconductance (gm) vs. overdrive TYPE.(VG -VT0) in linear operation |VD| = 0.3 V for two NMOS and PMOS lengths (L = 30 nm and 2 µm), Wf = 2 µm and Nf = 10 at T = 25°C.

Fig. 8 .

 8 Fig. 8. Normalized Transconductance efficiency vs. Id in linear operation |VD| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10 at T = 25°C). NMOS and PMOS for L = 2 µm is included in inset figure.

Fig. 9 .

 9 Fig. 9. Cgg and Cgd vs. gate voltage overdrive TYPE.(VG -VT0) in linear operation |VD| = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C and frequency = 100 MHz. Wf and Nf refer to one finger width and number of fingers respectively.

Fig. 10 .

 10 Fig. 10. Cgg and Cgd vs. gate voltage overdrive TYPE.(VG -VT0) in linear operation |VD| = 0.3 V for PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C and frequency = 100 MHz. measurements are de-embedded using dedicated OPEN and SHORT structures for each measured device. DC-extraction flow undergone in the previous section is a prerequisite for RF extraction. No fine-tuning is required for UTSOI DC extracted capacitances and series resistances, SHORT structure being used for parasitic resistances extraction before DC-extraction flow.For high frequency operation, UTSOI requires the addition of a distributed front gate resistance Rg similar to the PSP standard model one[START_REF] Smit | PSP 103.3 User's manual[END_REF] and a back gate resistance Rb. The final equivalent schematic is shown in Fig.12(right) where series resistances Rs and Rd are included in UTSOI and already extracted in previous DC related section. Front gate resistance Rg takes into account several contributions shown in Fig.12(left): (a) the contact resistances, (b) the horizontal gate sheet resistance and finally (c) the vertical gate resistance related to the processed gate stack. Rg is calculated as:

Fig. 11 .

 11 Fig. 11. 2-port RF structures S-parameters measurement setup.

  𝑅𝑒𝑎𝑙(𝑌 11 ).𝑅𝑒𝑎𝑙(𝑌 22 )-𝑅𝑒𝑎𝑙(𝑌 12 ).𝑅𝑒𝑎𝑙(𝑌 21 ))

Fig. 12 .

 12 Fig. 12. Left: UTBB transistor architecture (3D). Right: RF equivalent schematic proposal with additional front-gate (Rg) and back-gate (Rb) resistances.B. fT and fmax figures of meritTwo important RF Figures of Merit (FOMs) are the transit frequency of the current gain and the cut-off frequency of the

Fig. 13 .

 13 Fig. 13. Small signal current gain (|H21|) vs. frequency (F) in linear operation |VD| = 0.3 V for NMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

Fig. 14 .

 14 Fig. 14. Transit frequency (fT) vs. Id in linear operation |VD| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

  , FOMRF vs. Id is shown for NMOS and PMOS. Both MOSFET types present a maximum and consequently an optimum trade-off in moderate inversion region. UTSOI model is accurately reproducing this RF FOM measurements too.

Fig. 17 .

 17 Fig. 17. FOMRF vs. Id in linear operation |VD| = 0.3 V for NMOS and PMOS (L = 30 nm, Wf = 2 µm and Nf = 10) at T = 25°C.

TABLE I .

 I NORMALIZATION Fx f x= Fx / Fx_max where Cox is the oxide capacitance density, VT0 is the threshold voltage, TYPE is 1 for NMOS and -1 for PMOS, Vgt is the gate overdrive voltage, Gm_max is the maximum transconductance and Fx_max is the maximum value of the related cutoff frequency.

	Quantity	Normalization
	Drain Current: ID	Id = ID/(W/L)
	Capacitance: C	C/(Cox.W.L)
	Gate Voltage: VG	Overdrive: Vgt = TYPE.(VG -VT0)
	Transconductance: Gm	gm = Gm / Gm_max
	Cutoff frequency:

  normalized total gate capacitance Cgg and Cgd capacitance are displayed vs. gate voltage overdrive at |VD| = 0.3 V and Source and Back Gate terminals grounded. Cgg and Cgd capacitances are correctly captured using UTSOI despite possible strong fringing capacitances impact.

ACKNOWLEDGMENT

The authors would like to thank Clément Charbuillet, Vincent Quenette, Gilles Gouget, Frederic Dauge, Michel Buczko, Sebastien Jan and Hervé Jaouen from STMicrolectronics for their collaboration, support and advice.


Octavian Maciu

Wilfried Uhring
email: wilfried.uhring@unistra.fr

Jean-Baptiste Kammerer

Jean-Pierre Le Normand

Norbert Dumas

Foudil Dadouche

Hebrard Luc

Icube

Sub-Nanosecond Gated Photon Counting for High Spatial Resolution CMOS Imagers

Keywords: ultra-fast gating, SPAD, CMOS image sensor, imager array, photon counting, skew, line delay I

Ultra-fast photon counting in standard CMOS imagers can become very challenging at sub-nanosecond temporal resolutions. This is due to the delay and skew of signal propagation along large pixel arrays. A new edge-based solution is presented, circumventing these limitations. This solution is applied to a Single Photon Avalanche Diode based pixel with an embedded analog counter for time gating photon counting. The analog counter has an adjustable sensitivity ranging from 0.1 mV/photon up to 100 mV/photon. This concept was applied to an image sensor with a row length of approximately 15 mm and 330 pixels per row. The pixel counts 55 transistors with a pitch of 45 µm.

INTRODUCTION

In recent years, the field of ultra-fast imaging has experienced many key breakthroughs. The ability to push past the sub-nanosecond barrier shown in [START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF] is particularly interesting as it enables the counting of photons at a very high rate. Several works report Time Correlated Single Photon Counting Systems (TCSPCS) integrating a Time to Digital Converter (TDC) [START_REF] Villa | High linearity SPAD and TDC array for TCSPC and 3D ranging applications[END_REF] [START_REF] Richardson | A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging[END_REF]. The main advantage of TCSPCS is the high sensitivity, except during its dead time, the Single Photon Avalanche Diode (SPAD) is sensitive to all photons able to trigger the SPAD. The drawback of the TCSPCS is the need to extract the measured data before being able to measure a new photon. This operation generates a high data rate while the number of detected photons is increasing, leading to a possible saturation of the sensor. In some specific cases, the data extraction can be optimized by means of an embedded FIFO and/or an event driven readout [START_REF] Malass | Efficiency improvement of high rate integrated time correlated single photon counting systems by incorporating an embedded FIFO[END_REF] [START_REF] Nie | A Full Parallel Event Driven Readout Technique for Area Array SPAD FLIM Image Sensors[END_REF] but this approach is more suitable for the sensors limited to a one-dimensional spatial information, called a streak sensor (i.e. a sensor with a single row of photo detectors). In the general case of a 2D image sensor, the sensitivity of the high spatial resolution TCSPCS is bottlenecked by the sensor's digital IO. Generally, at least 10 bits per photon are generated in a TCSPCS. The state of the art high speed video sensors generate a data rate up to 40 Gb/s [6]. Based on this, the expected maximal number of photons/s for TCSPCS will be restricted to 4 Giga photons/s. Time information can also be acquired by time gated operation. Several time windows are used to sample the signal at different times. Regardless of some saturation or pile up effects, the maximal number of detected photons for a time gated pixel with an embedded photon counter is equal to the product X×Y×F, where X and Y are the number of columns and rows of pixels of the sensor and F is the gating rate, or F=1/P where P is the minimal dead time of the SPAD sensor. For instance, a 330×330 pixel sensor array and a gating rate of 10 MHz leads to a maximum photon rate of more than 1 Tera photon/s (i.e. an order of magnitude above the TCSPCS). Thus, thanks to an internal counting process, the time gated sensors can be much more sensitive than TCSPCS as the sensor's I/O bottleneck is avoided.

However, a high time resolution requires a short gating time. Sub-ns gating of a single SPAD down to 300 ps has already been reported in [START_REF] Nissinen | A sub-ns time-gated CMOS single photon avalanche diode detector for Raman spectroscopy[END_REF]. Nevertheless, ensuring a sub-ns gating time is quite challenging in a large sensor array as both the skew and the limited bandwidth of a long line across the sensor alter the time precision. Binary trees can be used in streak imagers to insure a low skew along the sensor. For instance, a 700 ps gate width has been reported in a 1024x8 (24.6mm long) array sensor with a 100 ps skew variation across the entire chip [START_REF] Maruyama | A 1024×8 700ps timegated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration[END_REF]. With 2D image sensors, this method is only applicable to the row (or column) signal buffers with a clock tree beside the sensor [START_REF] Perenzoni | A 160×120 Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging[END_REF]. However, the skew along the row (or column) can be as high as the temporal window's width. In [START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF], we proposed a method for a dedicated row driver and in-pixel fast signal generation for a sub-ns gating operation that maintains the skew below 20 ps rms along an entire row of 20 mm. This technique is used in this work in combination with an in-pixel photon counting unit in order to design a subns Time Gated Single Photon Counting Systems (TGSPCS).

Digital counters are cumbersome and better suited for streak TGSPCS [START_REF] Pancheri | A SPAD-based pixel linear array for highspeed time-gated fluorescence lifetime imaging[END_REF]. In order to preserve the fill factor, an analog counter architecture employing a small number of transistors and a capacitor is used [START_REF] Panina | Compact CMOS Analog Counter for SPAD Pixel Arrays[END_REF]. It has already been successfully integrated within a pixel of a 2D SPAD image sensor [START_REF] Pancheri | Compact analog counting SPAD pixel with 1.9% PRNU and 530ps time gating[END_REF]. Most of the works report counters with a fixed step size around a few tens of a mV. In this work, we present a versatile analog counter architecture suitable for sub-ns operation with an externally adjustable step size for a commutable high sensitivity or high dynamic measurement mode.

II. ULTRA-FAST GATING

Due to the well-known RC distributed effect and signal skew challenges on propagating sub-nanosecond pulses across a long pixel row (greater than 1 cm), conventional techniques involving pulse propagation are inadequate. In Fig. 1, the effect of the RC delay is shown at the beginning, middle and end of a 20 mm image sensor. Evidently, at the end of the row, the pulse no longer crosses half of the supply voltage, thus still seen as a logical zero. A more robust approach using the edge-based technique as described in [START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF] is more appropriate. It consists of generating two delayed signals instead of one to produce the fast pulse inside the pixel. A signal generator based on this approach can be used to drive the sensitive signals for each row (Fig. 2). The signal skew is compensated using a sensor row split into 10 segments with tuned-threshold inverters. This way, using the techniques developed in [START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF], we ensure that the pulses are generated locally in each pixel with minimal skew. Due to signal skew, the switching threshold is lowered in each segment across the line so that each segment switches at the same time as the preceding segment. This approach is validated by the simulation in Fig. 3. While the signal skew is not entirely eliminated, it only measures approximately 10 ps between the beginning and end of a 20 mm long imager array. It is greatly reduced and no longer has a fatal effect on the gating operation of each pixel.

Signal Generator

However, certain discrepancies are expected to appear due to fabrication mismatches. Monte-Carlo simulations on the statistical dispersion show that this approach incurs an expected dispersion of 18.42 ps rms [START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF]. Moreover, the skew compensation approach is based on the slew rate of the two delayed signals, thus it is mandatory to use a variable slew rate driver (Fig. 4), to compensate for its mismatch.

III. PHOTON COUNTING

A. Analog Counter Circuit

A compact, analog photon counting circuit is preferred to a digital one for fill factor considerations. Using a signal generator as in Fig. 2, an ultra-fast TGSPCS can be embedded in each pixel using the analog accumulation technique detailed in [START_REF] Morel | A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections[END_REF]. In Fig. 6, this analog counter circuit is detailed. It uses the low integrated capacitance of a floating node C INC , a charge transfer and reset circuit and an integrating capacitor C INT to count the number of detected photons. This system is highly flexible as it can count anywhere between 10 and 10 000 photons by adjusting the V Gain biasing voltage. The M TX can transfer charges as long as its V GS is greater than its threshold voltage. This positive excess voltage is given by:

TX TX ex GS T V V V = - (1)
The total transferable charge, initially stored in C INC , is given by:

ex INC ex Q C V = × ( 2
)
The transferable charges flow from C INC to C INT leading to the following voltage variation:

ex INC INT ex INT INT Q C V V C C Δ = = × ( 3
)
C INT is typically several times greater than C INC (10 fF and 2 fF respectively in our case). The count step size can be set by three variables: V Gain , V TX and the TX Pulse duration. By changing V Gain or V TX , V ex is varied. As V Gain increases, V ex becomes smaller; hence there is less charge to transfer. This results in a smaller step size and larger counting range up to 50 000. However, once V Gain gets too high, using (3), the transferred charge becomes too close to the single electron range and it is statistically unreliable. Furthermore, for a TX Pulse duration of a few ns, the charge transfer is not completed entirely and can be increased with larger pulse widths.

B. Analog Counter Simulation Results

The analog integration circuit has been simulated to show a versatile photon counting range (10-10 000) which is suitable for ultra-fast imaging applications using SPADs. The simulation window in Fig. 8 shows that the analog counter is capable of reaching a pre-determined threshold of 1 V in a wide range of step sizes. As each photon is counted, the counter circuit steps down its output voltage. Remarkably, the response is highly linear. Furthermore, in Fig. 9, it can be seen that the response of the analog counter circuit is linear with an R 2 of 0.9982 and a 2 quantum maximal error.

IV. SIMULATION RESULTS

Using the edge-gating technique, SPAD imager arrays can be gated using ultra-fast signals. Moreover, using the analog counter circuit for photon counting applications, we are able to count up to 10 000 photons for each pixel. Furthermore, as the edge-gating technique used for this application can reach subnanosecond temporal resolutions, a system can be designed to obtain a gating of 200 ps. The previous simulations show that this approach is ideal for time gated photon-counting large CMOS image sensors.

A. Ultra-fast Gating

Ultra-fast gating has been simulated using the test bench setup seen in Fig. 2 and Fig. 10. The simulated pixel uses the SPAD model seen in [START_REF] Zappa | Spice modeling of single photon avalanche diodes[END_REF]. A simulation of the photon arrival in function of the temporal position of the gating window was performed. A total skew of 25 ps peak-to-peak across the 10 33-pixel segments was obtained for a total row length of 15 mm. This solidifies that sub-ns gating is possible on large imager arrays. The simulation in Fig. 11 shows the integration quantum at the output before and after the arrival of a photon. This simulation does not take into account the SPAD jitter. Generally, SPAD jitter is approximately 100 ps FWHM (Full Width at Half Maximum) [START_REF] Malass | A Single Photon Avalanche Detector in a 180 nm CMOS Standard technology[END_REF]. In practice, the jitter will further smooth the gating window. This shows that the temporal resolution is limited by the SPAD's characteristics rather than the surrounding electronics.

B. Monte-Carlo Simulations

For sub-ns resolutions, it is important to consider the expected dispersion due to fabrication process mismatches. This approach is highly sensitive to transistor size variations, such as those used for skew compensation. The expected dispersion between the first two segments is 38.32 ps and between the first and last, 31.47 ps. Therefore, the dispersion is constant throughout an entire row and similar to previous works [START_REF] Maruyama | A 1024×8 700ps timegated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration[END_REF] [START_REF] Pancheri | Compact analog counting SPAD pixel with 1.9% PRNU and 530ps time gating[END_REF].

V. CONCLUSION This paper presents an application of a sub-nanosecond ultra-fast gating technique of a SPAD applied to large imager arrays in conjunction with a versatile analog photon counter. The analog counter offers a wide counting range from several photons to tens of thousands. The gating obtained for this pixel can go as short as 200 ps FWHM with a 38 ps rms skew across the entire array. Contrarily to the streak imaging sensors (1D) in [START_REF] Maruyama | A 1024×8 700ps timegated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration[END_REF] and [START_REF] Pancheri | Compact analog counting SPAD pixel with 1.9% PRNU and 530ps time gating[END_REF], our approach does not require a signal distribution tree and it is applicable to 2D imagers with a shorter gating time. To our knowledge, it is the first large size sub-ns gated 2D image sensor reported. CMOS ultra-fast gated image sensors could be an alternative for the current state of the art, ultra-fast gated intensified cameras using vacuum tube technology [START_REF] Uhring | 200 ps FWHM and 100 MHz repetition rate ultrafast gated camera for optical medical functional imaging[END_REF].

Fig. 1 .

 1 Fig. 1. Illustration of lost signal integrity across a row of pixels.

Fig. 2 .

 2 Fig. 2. Schematic of signal generator driving each pixel row.

Fig. 3 .

 3 Fig. 3. Simulation of nearly skew-less 330 ps pulse across 20 mm sensor. The solid line represents the signal at the beginning of the sensor and the dotted line the signal at the end.

Fig. 4 .Fig. 5 .

 45 Fig. 4. Variable slew-rate driver used to drive each signal across pixel row.In Fig.5, the SPAD's control circuit is controlled by ultra-fast signals (SPAD RST and GATE). The approach is applied by adding SPAD RST DELAY and GATE DELAY for edge propagation. Its operation is further detailed in[START_REF] Maciu | Sub-nanosecond Gating of Large CMOS Imagers[END_REF]. The tunedthreshold inverters used for skew elimination are added for each ultra-fast signal. This approach is integral in driving sensitive ultra-fast signals used for the gating of a photon counting CMOS image sensor.

Fig. 6 .Fig. 7 .

 67 Fig. 6. Analog counter circuit based on charge transfer dependent on the ratio between C INC and C INT. The timing diagram in Fig. 7 shows two cases, first with a SPAD IN pulse arriving between the RST INC and TX PULSE signals, causing the counter circuit to count and second without the SPAD IN pulse, therefore not counted.

Fig. 8 .

 8 Fig. 8. Simulation of analog integrator for different values of V Gain showing versatile counting range reaching 1 V in 10 to 10000 steps.

Fig. 9 .

 9 Fig. 9. Analog counter output simulation for V Gain = 0.4 V with fit curve showing a linear response at 99.98%.

Fig. 10 .

 10 Fig. 10. Test bench used for simulating a gating window across a 15 mm sensor where each ultra-fast signal is injected into 10 segments for skew compensation.

Fig. 11 .

 11 Fig. 11. Simulation of a single photon counting voltage change with a 220 ps gating window showing a near simultaneous results across all 10 segments of the imager.

ACKNOWLEDGMENT

We thank the Agence Nationale de la Recherche for financial support under grant ANR-14-CE26-0024-01.


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Evaluation of size influence on performance figures of a Single Photon Avalanche

Single Photon Avalanche Detectors or SPAD are PN junctions biased in Geiger Mode i.e. beyond their breakdown voltage, as a result the electric field in the multiplication region is so intense that a single photon carrier, ideally due to photon generation, is enough to start a selfmaintained avalanche by impact ionization, thus generating a high current pulse signaling the detection of a photon to the associated electronic circuitry. SPADs are capable of detecting individual photon arrivals with tens of picoseconds time of arrival resolution [START_REF] Pancheri | SPAD Image Sensor With Analog Counting Pixel for Time-Resolved Fluorescence Detection[END_REF], they offer many advantages in comparison to the traditional photomultiplier tubes (PMT) as they allow low noise and low jitter photon detection without requiring high reverse bias voltage and are more cost-effective, less bulky and compatible with standard CMOS technology. In the last 10 years many works have been done to optimize the SPAD technology and numerous SPADs have been implemented in both dedicated and standard CMOS technologies [START_REF] Ghioni | Progress in Silicon Single-Photon Avalanche Diodes[END_REF], and while SPADs manufactured using dedicated technologies have been able to reach great performances in term of noise and detection efficiency, SPADs fabricated in standard CMOS technologies allows the highest level of miniaturization and integration with lower power consumption and a reduced overall cost [START_REF] Palubiak | CMOS SPADs: Design Issues and Research Challenges for Detectors, Circuits, and Arrays[END_REF] making them very appealing to integrate in single photon applications such as Fluorescence Life Time Imaging (FLIM) [START_REF] Field | A 100 fps, Time-Correlated Single-Photon-Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS[END_REF] [5] Positron Emission Tomography (PET) [START_REF] Braga | A Fully Digital 8 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output[END_REF] and Time of Flight (TOF) measurements [START_REF] Villa | SPAD Smart Pixel for Time-of-Flight and Time-Correlated Single-Photon Counting Measurements[END_REF].In this paper we present a SPAD structure fabricated in a standard 0.18 µm CMOS technology with the characterization results of its main performance parameters; the remaining of this paper is thus structured as follows: in section II we represent the implemented SPAD structure, in section III we describe the characterization setup, the characterization results are shown in section and we conclude in section IV.

II. SPAD DESIGN

A high quality SPAD should offer a low dark noise and a high Photon Detection Probability (PDP). This requires a structure design that allows a uniform high electric field in the multiplication region and limits the premature edge breakdown effect [START_REF] Richardson | Scaleable Single-Photon Avalanche Diode Structures in Nanometer CMOS Technology[END_REF]. The proposed SPAD cross section is illustrated in Fig. 1, the active area is a P+/Nwell junction in a retrograded Deep Nwell on a high resistivity P-substrate. To avoid premature edge breakdown a double Pwell/STI guard ring was implemented. The low doped Pwell guard ring was added to separate the multiplication region from the STI implant to reduce high dark noise due to faulty detections triggered by carrier injections from the STI interface into the multiplication Area. Eight devices with the presented SPAD structure were implemented using a 180 nm standard CMOS image sensor technology, the devices have 8 different active area diameters ranging from 5 µm to 40 µm. The eight sensors were implemented in an integrated circuit that uses the approach, described in [START_REF] Uhring | A 64 Single photon avalanche diode array in 0. 18 μm CMOS standard technology with versatile quenching circuit for quick prototyping[END_REF], that allows a quick prototyping and characterization of SPAD structures implemented in any CMOS process. The large and versatile array makes it possible to test a large number of different structures in a single chip thus limiting the number of iteration to find the best SPAD. Each SPAD was integrated with its quenching circuit in a characterization pixel (Fig. 2) and can be individually activated and characterized without any interference of the other devices. The quenching circuit (Fig. 2) includes a voltage controlled PMOS transistor for passive quenching, a NMOS transistor (Mq) for active quenching and a PMOS transistor (Mr) for active reset. The quenching and reset transistors are switched on and off by the quench control block [START_REF] Uhring | A 64 Single photon avalanche diode array in 0. 18 μm CMOS standard technology with versatile quenching circuit for quick prototyping[END_REF] which also allows to set the quenching mode (passive, active, mixed) and the durations of the quenching phase and the reset phase. Due to the use of the additional Pwell guard ring that imposes restrictions on the minimum active area diameter [START_REF] Faramarzpour | Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18-µm Technology[END_REF], the 5 µm diameter SPAD was not functional but the remaining 7 devices showed an abrupt avalanche around a measured reverse bias of 11.4 V (Fig. 3).

IV. CHARACTERISATION RESULTS

A. Dark Count Rate

Dark Count Rate (DCR) represents the measure in the dark of spurious avalanche events which are not the result of a photon interaction. The DCR is triggered by several generation mechanisms: thermal generation, trap assisted generation and band to band tunneling; it is strongly dependent on the SPAD design as well as the used CMOS technology process. Primary DCR is random and statistically uncorrelated but SPADs also display secondary avalanche pulses statistically correlated to primary events known as afterpulsing. Afterpulsing is due to trapping and de-trapping of charges flowing through the multiplication region during the primary avalanches, it is dependent of the current amplitude, the associated electronics as well as temperature and can be reduced by increasing the SPAD hold-time to allow the releasing of the trapped charges before activating the SPAD again. The probability of the afterpulsing for the 7 SPAD implementations was measured at room temperature for an excess bias of 300mV with a dead time of 30 ns which is the minimum achievable dead time by the associated quenching circuit. Fig. 5 shows the afterpulsing probability measurement results using the inter-arrival time histogram method [START_REF] Veerappan | A Substrate Isolated CMOS SPAD Enabling Wide Spectral Response and Low Electrical Crosstalk[END_REF] for the 20 µm SPAD with an excess bias of 300mV. The afterpulsing probability of the 7 SPAD devices are illustrated as a function of their active area diameter in Fig. 6, the measured probability was around ~0.21% at 300mV for the 7 devices, indicating that the afterpulsing probability in not related to the surface of the device. Furthermore the interarrival time histograms obtained from the measurements by calculating time durations between 2 consecutive avalanche events showed that the undesirable afterpulsing can be eliminated by increasing the dead time to 1 µs. The total DCR was measured for the 7 devices at different excess bias values and with a temperature ranging from -30°C to 60°C. The DCR variation against temperature for an excess bias of 100 mV and 400 mV is represented in Fig. 7 which shows that the measured DCR increases with the SPAD active area, at 15°C it is lower than 5 kHz for SPADs with an active region diameter below 30 µm and lower than 10 kHz for the 30 µm and 40 µm SPADs. Raising the excess bias from 100 mV to 400 mV increases the DCR value with a mean factor of 2.2 over the whole range of considered temperatures for all the SPAD diameter variations, which proves that the effect of the excess bias on the DCR do not depend of the device area. To better illustrate the effect of SPAD diameter on the measured DCR, the ratio DCR/Surface variation against temperature for the 7 devices at an excess bias of 400 mV is plotted in Fig. 8. The SPADs showed the same DCR/Area value with the exception of the 30 µm SPAD that generated more noise/µm 2 most likely due to a higher defects concentration compared to the rest of the SPADs. The results also show a linear variation below 20°C with the DCR doubling every 10°C thus suggesting that it is mostly dominated by the tunneling mechanism. Above 20°C the DCR increases exponentially and the thermal generation becomes the dominating mechanism.

B. Photodetection probability

Photon Detection Probability (PDP) represents the ratio of the number of detected photons over the number of incident photons; it represents the sensitivity of the SPAD to incident photons. PDP is the result of the absorption probability and the triggering probability [START_REF] Ghioni | Progress in Silicon Single-Photon Avalanche Diodes[END_REF] [12], it depends of doping levels [START_REF] Charbon | SPAD Based Sensors[END_REF], noise, excess bias [START_REF] Ghioni | Progress in Silicon Single-Photon Avalanche Diodes[END_REF] and the area of the active region. We measured the PDP of the 7 devices over a wavelength range between 350 nm and 1000 nm at room temperature for various excess biases between 100 mV and 400 mV and a dead time of 30 ns. Fig. 9 shows the PDP of the 7 devices with an excess bias of 300mV. The measurements showed that the PDP peaks around 430 nm for the 7 devices, the maximum PDP value for a given active area increases with the excess bias (Fig. 10) and the maximum PDP value for a given excess bias value increases with the active area although the amount of PDP enhancement tends to decrease as the active area diameter increases and it becomes very minor for active area diameters higher than 20 µm (Fig. 9). The measured peak PDP is equal to 11% for the 7.5 µm SPAD and 19% for the 40 µm SPAD. This probably results from a smaller active area really formed during the CMOS process for the SPAD below 20 µm. The difference of the PDP for the 7.5, 10 and 15 µm can be explained by a real diameter reduced by 1.35, 1.15 and 0.9 µm respectively. In general, the measured PDP values are quite good giving the relatively low excess bias which was due to limitations imposed by the associated quenching electronics

C. Timing Jitter

Timing jitter represents the timing incertitude due to statistical variation of delays between photon absorption and the subsequent avalanche detection by the SPAD's associated electronics. It decreases with bias voltage and increases with the active area [START_REF] Bronzi | Lownoise and large-area CMOS SPADs with timing response free from slow tails[END_REF]. The timing jitter values of the 7 devices were characterized using a TCSPC setup with a 20 MHz picoseconds laser diode source [START_REF] Uhring | A low-cost high-repetition-rate picosecond laser diode pulse generator[END_REF] with an excess bias ranging between 200 mV and 500 mV, and a dead time of 30 ns. The timing response of the 7 SPADs are shown in Fig. 11 for 2 wavelength values λ=450 nm and λ=808 nm at an excess bias of 300 mV. The pulse widths (Pulsewidth) of the light emission have been measured with the streak camera described in [START_REF] Uhring | Very high longterm stability synchroscan streak camera[END_REF] to 67 ps FWHM and 99 ps FWHM for the 450 and the 808 nm laser diode respectively. The distributions show a sharp Gaussian peak and an exponential tail. The sharp Gaussian peak is due to photons absorbed in the multiplication area while the tail is due to minority charge carriers diffusion and photons absorbed below the multiplication region and is more marked for higher wavelengths [START_REF] Palubiak | CMOS SPADs: Design Issues and Research Challenges for Detectors, Circuits, and Arrays[END_REF]. In general, the timing response FWHM for a giving excess bias increases with the active area diameter due to lateral and vertical dependence of timing uncertainty on photon absorption location thus better timing resolutions are obtained with the smaller SPADs for the2 laser source wavelength values.

Furthermore the 450 nm laser yields better timing resolutions due to the fact that photons with higher wavelength can go deeper into the neutral region thus requiring more time before reaching the multiplication region and triggering the avalanche process. This is better illustrated in Fig. 12

At 300 mV the best measured timing resolution is equal to 34 ps and was achieved using the SPAD with an active area of 7.5 µm for λ=450 nm. The maximum jitter for λ=450 nm is obtained using the 40 µm SPAD and it is equal to 300 ps. Similarly for λ=808 nm, the minimum measured jitter is equal to 67 ps and the maximum jitter is equal to 350 ps and was measured using the 40 µm SPAD. Fig. 13 shows the timing jitter variation of the 7.5µm to 25 µm SPADs as a function of the excess bias for λ = 405 nm. Unsurprisingly the timing jitter At 300 mV the best measured timing resolution is equal to 34 ps and was achieved using the SPAD with an active area of 7.5 µm for λ=450 nm. The maximum jitter decreases as the excess bias increases, as it leads to an increase of the electric field strength in the multiplication region thus reducing the time needed for a photodetection to generate a reverse current high enough to be detected by the SPAD's associated electronics. For λ=450 nm (Fig. 13), the measured timing jitter of 7.5 µm device is around 100 ps at 200 mV and decreases to 65 ps at an excess bias of 500 mV. Similarly the measured jitter for the 25 µm is 166 ps at an excess bias of 200 mV and decreases to ~130 ps at an excess bias of 500 mV.

V. CONCLUSION

In this paper we presented and characterized 7 implementations of a SPAD structure fabricated in a 180 nm Standard CMOS image sensor technology with active area diameters between 7.5 µm and 40 µm. Despite a limited excess bias value, the reported SPAD compares relatively well with several reported SPADs fabricated in standard CMOS process (c.f. TABLE I). The measurements showed a DCR below 5 kHz at 15°C with a highly suspected strong band to band tunneling and field-enhanced generation effects due to the relatively low breakdown voltage (11.4 V). The afterpulsing probability of the device was characterized using the inter-arrival time histogram method and the measurements yielded a probability of 0.2% for a hold time of 30 ns. The PDP measurements showed a peak at 20% around 430 nm and the measured timing resolution was less than 100 ps FWHM for λ =450 nm at an excess bias of 500 mV. SPADs characterization is known to be a very delicate process as their performances is sensitive to many variables (excess bias, temperature, size, etc.) and the importance of the active area value was very obvious in the results of our measurements as it affected all the SPAD parameters except for the afterpulsing probability The DCR was proportional to the devices area, the jitter was improved when the diameter is reduced whereas the PDP decreased for SPAD diameter below 20 µm.

In our case ,the tradeoff between all the SPAD performance parameters yields the conclusion that the best compromise was obtained with SPADs that have an active area diameter between 15 µm and 25 µm as they showed a reasonable DCR (less than 5 kHz), a good PDP probability (~18%) and a timing jitter lower than 100 ps.

  Diode fabricated in a 180 nm standard CMOS technology Imane Malass, Wilfried Uhring, Jean-Pierre Le Normand, Norbert Dumas, Foudil Dadouche To cite this version: Imane Malass, Wilfried Uhring, Jean-Pierre Le Normand, Norbert Dumas, Foudil Dadouche. Evaluation of size influence on performance figures of a Single Photon Avalanche Diode fabricated in a 180 nm standard CMOS technology. Analog Integrated Circuits and Signal Processing, 2016, NEWCAS 2014-2015, 89 (1), pp.69 -76. 10.1007/s10470-016-0763-8. hal-03513621 I. NTRODUCTION

Fig. 1 -

 1 Fig. 1 -Cross section of the presented SPAD structure

Fig. 2 -

 2 Fig.2 -Versatile pixel architecture for SPAD characterization

Fig. 3 -

 3 Fig.3 -I-V Charasteristics of the 7 SPAD devices

Fig. 4 -

 4 Fig.4 -Electroluminescence light emission test performed over the 25 µm SPAD (third device from the right) at a reverse excess bias of 300 mV Furthermore the electroluminescence emission test performed on these devices showed a uniform avalanche process over all the surface of the active region. Fig.4 shows the electroluminescence light emission of the 25 µm SPAD at a reverse excess bias of 300 mV. The other visible devices with diameters of 10, 15, 20, 30 and 40 µm are switched off.

Fig. 5 -Fig. 6 -

 56 Fig. 5 -Afterpulsing measurement results for a dead time of 30 ns and an excess bias of 300 mV

Fig. 7 -Fig. 8 -

 78 Fig.7 -DCR of the 7 devices versus temperature at an excess bias of 100 mV (top) and 400 mV (bottom)

Fig. 9 -Fig. 10 -

 910 Fig.9 -Photodetection probability of the 7 SPADs for an excess bias of 300 mV

  which shows the raw measured jitter (JitterMeasured) values (solid line) of the7 SPADs for the 2 wavelength values and for an excess bias of 300 mV. The effect of the optical pulse width have been decorrelated to the measured jitter to obtain a value closer (JitterReal) (dotted line) to the real device performances according to the equation

Fig. 12 -

 12 Fig.12 -Timing jitter results for λ = 450 nm and λ = 808 nm at an excess bias of 300 mV

Fig. 11 -

 11 Fig.11-Normalized timing response measurement results using a 450 nm and a 808 nm laser with an excess bias of 300mV for the 7 SPAD diameters

TABLE I .

 I PERFORMANCES FIGURES OF SEVERAL SPADS FABRICATED IN STANDARD TECHNOLOGIES

			Performance figures
		DCR	Afterpulsing	PDP	Jitter
	This work	<10 kHz	0.2%	20%	100 ps
	(5)	1 kHz
	(10)	100 kHz		5.5%
	(14)	<43 Hz		40%	77 ps 120 ps
	(18)	13 kHz		17.4%
	(19)	1 MHz
	(20)	<100 kHz			55ps
	(21)	600 Hz	2.6%	45%
	(22)	100 Hz	2.1%	30%	170 ps


Laurent Millet
email: laurent.millet@cea.fr

Margaux Vigier

Gilles Sicard

Nils Margotat

Fabrice Guellec

Wilfried Uhring
email: wilfried.uhring@unistra.fr

A 5 Million Frames Per Second 3D Stacked Image Sensor With In-Pixel Digital Storage

Keywords: burst imaging, digital storage, 3D stack, CMOS

A CMOS burst image sensor reaching 5Mfps with 52 frames in-pixel digital memory has been designed and tested. It fully takes advantage of 3D stacked technology to implement a scalable architecture for 8-bits quantization and data storage at pixel level in CMOS technology. This imager also benefits from backside illumination (BSI) for improved fill factor and wide spectrum sensitivity. A demonstrator has been fabricated, embedding two types of 3D based pixel. In this paper we present the very first experimental test results of 3D stacked in-pixel digital burst image sensor. These results show advantages of using 3D technology to obtain a very high frame rate with both relaxed design conditions and readout timing constraint compared to conventional high speed burst image sensors.

I. INTRODUCTION

High speed imaging is a key technology to study high speed phenomenon such as micromechanics, explosives, plasma formation mechanisms or laser ablation. In a classic image sensor (IS), images are acquired with on the fly chip readout. However, for high speed IS this read-out process is a bottleneck limiting the frame rate to about 10 kilo-frame-persecond (fps) for a 1 mega-pixel resolution as presented in [START_REF] Meynants | Limitations to the frame rate of high speed image sensors[END_REF]. To tackle this limitation, burst IS uses an on-chip memory to store the burst video sequence recorded during the acquisition. Images are then read-out at lower speed. While the frame rate of burst IS can exceed 10 M frames per second (Mfps), they suffer from the small embedded memory limiting the video length to a maximum of hundreds frames.

Burst image sensors are currently divided into two technological categories: CMOS and CCD. CCD imagers can achieve high frame rate with high in-pixel analog memory density [START_REF] Nguyen | Design an event detection system for 16-Mfps extremelyhigh-sensitivity video camera[END_REF], [START_REF] Arai | A 252-V/luxs, 16.7-Million-Frames-Per-Second 312kpixel Back-Side-Illuminated Ultrahigh-Speed Charge-Coupled Device[END_REF] and they also benefit from a very high fill factor when using BSI process. However this technology involves several drawbacks. First, they have a huge power consumption to supply the high gate control voltages. Secondly the analog memory is placed in the focal plane. While BSI configuration is much better for fill factor considerations, it exposes the memories to backside photo-current generation which can degrade the stored data. It requires thick substrate to cut wavelengths above 700nm [START_REF] Nguyen | Design an event detection system for 16-Mfps extremelyhigh-sensitivity video camera[END_REF], [START_REF] Arai | A 252-V/luxs, 16.7-Million-Frames-Per-Second 312kpixel Back-Side-Illuminated Ultrahigh-Speed Charge-Coupled Device[END_REF]. This in-pixel constraint also limits the memory to 100 frames. In addition the CCD technology impedes the use of embedded functions such as Analog to Digital Converter (ADC), or processing features which arise in smart CMOS solutions e.g. compressive sensing [START_REF] Mochizuki | Single-Shot 200Mfps 53-Aperture Compressive CMOS Imager[END_REF]. Up to now, high speed Fig. 1. Overview of our 3D stacked CMOS image sensor partitionning image sensors using CMOS implementation hardly compete with CCD sensors. The CMOS local memorization is also performed thanks to very small capacitors despite large KTC noise. We distinguish two kinds of implementations regarding analog memories: either using memory banks outside the pixel array [START_REF] Suzuki | 10Mfps 960 Frames Video Capturing Using a UHS Global Shutter CMOS Image Sensor with High Density Analog Memories[END_REF], [START_REF] Kuroda | A 20Mfps Global Shutter CMOS Image Sensor with Improved Light Sensitivity and Power Consumption Performances[END_REF], or using in-pixel memory [START_REF] Wu | In-Pixel Storage Techniques for CMOS Burst-Mode Ultra-High-Speed Imagers[END_REF]. In this last case, the main drawback is the very small pixel fill factor. The use of memory banks limits the scalability of the array size and faces power penalty due to signals propagation on the entire array through high capacitance lines at high speed. In both cases, there is also a strong limitation on the readout phase due to leakage on small capacitor memories. They require a fast readout and hence high working frequencies before data deterioration. Some works [START_REF] Mochizuki | Single-Shot 200Mfps 53-Aperture Compressive CMOS Imager[END_REF] circumvent this limitation by using time coded multi-capture, but are still limited to 15 frames memory.

A 3D stacked IC approach overcomes these restrictions by allowing a distribution of electronic functions on dedicated tiers [START_REF] Uhring | A Scalable Architecture for Multi Millions Frames per Second CMOS Sensor With Digital Storage[END_REF]. Top tier photodiodes can benefit from imaging technology and backside illumination for a maximal sensitivity, while the bottom tier provide room for in-pixel memories without sacrifying the fill factor (Fig. 1). We designed a scalable 3D pixel using direct bonding stacking, which causes no dead area in the silicon [START_REF] Benaissa | Next Generation Image Sensor via Direct Hybrid Bonding[END_REF] on the contrary of TSV solutions. We also take advantage of this topology to design an in-pixel ADC for embedded digital storage. Our Image Sensor benefits of a 40nm advanced technological node on bottom tier for high density capability. Using RAM-based memory could easily overcome the current hundreds of stored images and allows a video memory of thousand images [START_REF] Bonnard | New 3Dintegrated burst image sensor architectures with in-situ A/D conversion[END_REF]. This paper describes the architecture and electrical results of the very first 3D-stacked BSI burst image sensor with in-

II. OVERALL DESCRIPTION

As said, the 3D stacked implementation is very suitable for mixing analog and digital circuits with dedicated technological nodes. Our prototype uses an 90nm image sensor layer over a 40nm digital layer connected by hybrid bonding process. The selected partitioning is illustrated in Fig. 2. The top tier embeds an array of 20 × 20 BSI pixels. Each top tier pixel contains a photodiode with its associated readout structure and the analog frontend of a ramp ADC, while the bottom tier pixel contains the counter and digital memory to store 52 images. The bottom chip embeds the control circuits, power distribution, interface controls, and a PLL to drive the counters. The IO ring is also located on bottom tier involving that control signals come from the same die for both top and bottom chips. The top tier is supplied by the bottom chip through 3D Cu-Cu contacts.

III. TOP TIER PIXEL STRUCTURE

The 3D partitioning relaxes area constraints on readout and ADC circuits. We designed a scalable pixel with a total area of 50µm × 50µm.

A. Photodiode

The 3T BSI photodiode dimensions are 40µm×50µm and reach a fill factor of 80%. It is surrounded by a deep trench isolation to avoid inter-pixel interferences and to protect the photosensitive elements from disturbances of the nearby active CMOS circuits (leakage and electron harvesting).

Due to large photodiode dimensions we used multiple collecting contacts. Two different photodiode designs were implemented: A-type version with 4 contacts and B-type version with 15 contacts. These two designs bring different integrating capacitances values (made by junction photodiode and parasitics). A-type shows a lower value (25fF) than the Btype (50fF), but the B-type may exhibit a better time response during charge collection. The chosen frontend readout structure is a 3T pixel with a sample and hold stage, selected for its fast time response. A CTIA could be implemented for better voltage control on sensing node and signal gain thanks to feedback capacitances. Yet, since the photodiode capacitance is expected to be low, the source follower has been considered as better option.

A sample and hold circuit is used to stop integration and ensure a clean signal for the ADC. The acquired signal is then quantized while next frame is already integrating on photodiode capacitance.

C. Analog to Digital Converter

The ADC topology is a ramp converter. The comparator is designed in the top tier (Fig. 3) while the counter circuit is in the bottom layer. The comparator is a double stage amplifier followed by a level shifter for voltage compatibility with digital layer. It performs a correlated double sampling on pixel signal, and embeds a double offset cancellation circuits through AZ1 and AZ2 stages. Note that a comparator usually produces kickback noise on reference voltage lines and power supply, magnified by the matrix dimensions. This is an issue at our operating frequencies, since the references take time to come back to their initial level. To tackle this problem we implemented a clamp circuit to drift current even after the comparator triggering, which ensure a constant power consumption over the matrix array and brings a significant kickback noise reduction.

There are two 3D contacts per pixel. The first is the comparator output signal called "stop conv", from the top to bottom. It freezes the counter value. The second one comes from the bottom chip. It brings the 1.2V power supply to the top tier for the level shifter.

D. Top tier pixel overview

The layout implementation of an A-type pixel and the readout circuits is shown in Fig. 4. A metal 1 and 2 shield is drawn over the photodiode, and the BSI implementation allows to use free space for fringe capacitances. One of the 3D connections hangs over the neighbor pixel.

IV. BOTTOM TIER PIXEL STRUCTURE

The bottom tier pixel embeds counters for the ramp ADC, a bank of 52 Bytes memory, and top/bottom synchronization circuits.

A. Analog to Digital Conversion

Digital pixel comprises an 8 bit counter, driven by a clock up to 2,56GHz generated by a peripheral PLL circuit. This frequency ensures an 8bits conversion at 5Mfps. When the conversion begins, the counter value is incremented at each clock rise and stops as soon as the top tier comparator has switched. The digital value is then automatically stored in the selected 13 bytes FIFO out of the 4 available per pixel (Fig. 5). This implementation enables continuous recording while no event occurs. This is convenient if the imager is waiting for an specific event, since the acquisition can be stopped with a dedicated external trigger. Data are then read-out through a low frequency serial link. Each pixel memory can be selected through "Row SEL" gate. There is no time constraint here since digital memories do not suffer from leakage issues like in CCD or CMOS analog storage solutions.

B. Signal control and synchronization

C. Embedded Digital Memory

For this first prototype digital memories are realized with D Flip-Flops for a total memory area of 45µm × 45µm. This memory topology allows 52 pictures of 8 bits to be sequentially written. A much larger memory depth could be achieved by using a high density SRAM instead of D-Flip Flops. It would involve an important increase of storable pictures. Typically it could allow around 775 frames in 28nm technology and 387 frames in 40nm technology for the same pixel pitch pitch while including the SRAM control circuit. Implementing SRAM will involve partitioning issues (one cut for several pixels) and local pixel addressing considerations. For instance this SRAM partitionning has already been investigated in the context of high speed imaging [START_REF] Uhring | A Scalable Architecture for Multi Millions Frames per Second CMOS Sensor With Digital Storage[END_REF].

V. ELECTRICAL MEASUREMENTS

To evaluate our demonstrator performances, two kind of measure analysis have been performed. First photodiodes have been characterized thanks to a test structure allowing access to the internal nodes. Secondly we also demonstrated standard full frame electrical acquisition.

A. Photodiode caracteristics

Photodiode characterization measures were performed on optical bench with a monochromator. The extracted spectral sensitivity is shown in Fig. 7. Since we are not limited by CCD constraints which needs to use thick oxide to prevent large wavelength from corrupting the analog memories, our measured diagram exhibit a wide spectrum range from 360nm to 900nm. The visible oscillations are known as etalon effect and they appear when a beam of monochromatic light causes constructive and destructive reflection interferences when reaching two parallel interfaces.

B. Dynamic captures: pulse response

We performed several transient measures to evaluate the IS response to fast moving scenes. On the first example shown in Fig. 8 the imager is illuminated with a stream of laser pulses adjusted at 660nm wavelength. It emits a 10pJ, 100 ps Full Width at Half Maximum (FWHM) long pulse of light that illuminates the whole sensor sensitive area [START_REF] Uhring | A low-cost high-repetition-rate picosecond laser diode pulse generator[END_REF]. The acquisition mode is full frame and the ADC dynamic is set to 8 bits with a 5 Mfps frame rate.

On the first acquisition (stream A) a single pulse focused on the upper side of the imager is sent during the frame 2 to test the A-type pixel response. The laser spot is surrounded by a diffraction circle. The high illuminated central spot causes a small residual remanence illustrated by a 20 codes dot visible on the frame 3 (red arrow). This effect is not visible when the B-type pixel is illuminated on the lower side of the imager (stream B). This means that the A-type pixel has a small amount of residual drifting charges due to insufficient collecting contacts, which is not the case for the B-type photodiode. The circuit exhibits a pixel aperture ratio of 73.7%, measured thanks to the FWHM light pulse.

C. Dynamic captures: sine response

This second example evaluates the response to a half-sine wave exposition. 5 different acquisition streams where made at 5Mfps. Each capture is slightly shifted by 300ns from the previous one, and is presented on Fig. 9. Several pictures of the first capture stream are displayed for assessment. For a better estimation of the captured signals, a graph shows the median value of each photodiode type (A or B) for each picture. We clearly see that the B-type photodiode is less sensitive than the A-type variation. This is due to the higher junction capacitance, hence a higher full well capacity. However in both cases each sine is perfectly visible and we demonstrated that the process is realiable and replicable. In this paper with presented electrical results of the very first burst image sensor exploiting 3D stacked technology. Our scalable pixel with digital memories allows robust data storage, and then suppress the spectrum limitations inherent to CCD technologies. With 52 images video memory at 8bit quantization, our prototype paves the way to high density high resolution CMOS burst imagers. A list of technical specifications of our imager is summarized in TABLE I.

Fig. 2 .

 2 Fig. 2. Top and bottom layout view, with pixel cross section detail

Fig. 3 .

 3 Fig. 3. Top tier readout and comparator circuits with clamp detail for current stabilization

Fig. 4 .Fig. 5 .

 45 Fig. 4. Layout implementation of the top tier BSI pixel (A-type)

  Bottom tier handles synchronization signals. Since the frame capture global shutter based, the 20 × 20 pixels of the array work in parallel. Hence, 3D drive signals from bottom to top tier are sent outside the focal plane for line-broadcast communication, as well as ramp distribution. Start conversion signals are sent to top and bottom tier outside pixel array for conversion synchronization of both layers, as depicted in Fig. 6.

Fig. 6 .

 6 Fig. 6. Digital pixel control time diagram

Fig. 8 .

 8 Fig. 8. Two 3 frames sequences to evaluate beam persistance on A-type and B-type pixels (left), and the test bench (right)

Fig. 9 .

 9 Fig. 9. Median value of 5 sinewave captures with 300ns shift @5Mfps

TABLE I

 I

		.	TECHNICAL SPECIFICATIONS SUMMARY
	Scalable Pixel specifications	Readout characteristics
	Technology		4M1P 90nm	Read Noise	0.59 mV rms
			7M1P 40nm
	Pixel size		50µm × 50µm	Dynamic range	1 V
	Fill factor		80%	Convertion gain	7.3 µV /e-
	Framerate		5 Mfps	full well capacity	137k e-
	Memory depth		52 (8 bits images)	Chip Considerations
	(frames)	(387 in 40nm SRAM)*	Pixel count	20 × 20
		(775 in 28nm SRAM)*	chip size	2.7 × 2.7mm
			* estimated

ACKNOWLEDGMENT

The authors acknowledge the support of ST Microelectronics for technological contribution, and Emilie Huss for advices on photodiode design.


Salim El Ghouli
email: salim.elghouli@st.com

Władysław Grabiński

Jean Michel Sallese

André Juge

Christophe Lallement

Analog RF and mm-Wave Design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

Keywords: Transconductance efficiency, gm over Id, Doublegate FETs, FDSOI, UTBB, Analog, RF, Low-Power, Low-Voltage, mm-Wave, LNA I

The state-of-the art RF and millimeter-wave firstcut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and inaccurate concepts. Moreover, the pessimistic rules of thumb proposed for older bulk technologies are no more useful and lead to overdesign. This work takes advantage of the Moderate Inversion and uses low and high frequency figures of merit to provide a convenient sizing method for a 35 GHz Low Noise Amplifier (LNA) in 28 nm UTBB FDSOI technology.

INTRODUCTION

More and more wireless devices and IoT building blocks rely on CMOS analog and RF circuits to efficiently interact with the physical world. Thanks to the geometry down-scaling, CMOS MOSFETs have been widely used in low-cost and low-power RF integrated circuits (RFIC). Short-channel related issues, as side effects of the geometry shrink, have been controlled using new architectures and new materials [START_REF] Hisamoto | A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra-thin SOI MOSFET[END_REF] [START_REF] Planes | 28nm FDSOI technology platform for high-speed lowvoltage digital applications[END_REF]. The new architectures allow for excellent electrostatic control [START_REF] Balestra | Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance[END_REF].

Clearly the UTBB FDSOI technology has proven to be suitable for Analog and RF applications, especially when both power consumption and performance are valued equally. UTBB FDSOI MOSFETs exhibit high analog and RF performances thanks to the reduced parasitic capacitances and resistances [START_REF] Raskin | FinFET versus UTBB SOI -a RF perspective[END_REF]. Moreover, the independent back gate provides an interesting degree of freedom that allows tradeoff between power consumption and performance [START_REF] Noel | Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit[END_REF] [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF].

Several circuit-topology-based techniques such as current reuse are proposed in analog design to optimize performance and power consumption [START_REF] Karanicolas | A 2.7-V 900-MHz CMOS LNA and mixer[END_REF]. These techniques are out of this paper scope. In this work, the UTBB FDSOI characteristics are used for first-cut analog sizing method. In particular, the transconductance efficiency versus inversion coefficient (IC) studied in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF] is used to determine the width of the MOSFET while the transit frequency (fT) versus IC charts are used for length selection. The design method, using relaxed length and Moderate Inversion (MI) regime, provides a valuable tradeoff between gain, power consumption and performance while MOSFET width is kept reasonably large and short channel effects are mitigated. An eye is also kept on passive devices limitations from the very beginning of the sizing flow. This paper is organized as follows. First, the classical analog design methods, based on inherited rules of thumb, are briefly discussed in Section II. Second, the UTBB FDSOI technology capabilities for Analog and RF applications are reminded in Section III. Third, the transconductance (gm) over drain current (ID) based design method is presented in Section IV. Fourth, the high frequency performance versus IC and MOSFET length is assessed in Section V. Finally, a 35 GHz LNA design tradeoff in Moderate Inversion is proposed in Section VI and a conclusion is given in Section VII.

II. CLASSICAL DESIGN SIZING METHODS IN ANALOG AND RF

Sizing MOSFETs through iterative simulations and trial and error practices takes considerable amount of the precious design time. Optimum design tradeoff is hardly achieved using these methods [START_REF] Foty | Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id[END_REF]. Furthermore, hand calculation based analog design remains the method of choice to minimize iterative simulations and enables intuitive design. The classical hand calculation sizing methods are still based on inaccurate and questionable concepts such as the gate voltage overdrive (Vov = VGS -VTH, where VTH is the threshold voltage), and pessimistic rules of thumb such as the shortest possible length for higher fT, higher Vov constraint, and a maximum operation frequency of fT/10. Design in Moderate Inversion has become attractive in advanced technologies as it offers the optimum trade-off between speed, transconductance, and power consumption [START_REF] Shameli | Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study[END_REF] [START_REF] Ghouli | Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model[END_REF]. However, the classical gate voltage overdrive is becoming a poor metric for MOSFET inversion level assessment in advanced technologies as it is based on conflicting definitions of the threshold voltage [START_REF] Ortiz-Conde | Revisiting MOSFET threshold voltage extraction methods[END_REF]. The latter is defined as the VGS value at the onset of the Strong Inversion (SI) and extracted using several methods and criteria leading to uncorrelated definitions. Moreover, gate overdrive voltage can only be used for the hand calculation sizing method based on SI square law that miserably fails to predict gm/ID in MI as seen in Fig. 1. Even for a long channel device, the error is more than 100% at Vov = 100 mV. For short channel devices (e.g. L = 30 nm in Fig. 1), the simple square law is not valid in all levels of inversion. Moreover, for a double gate transistor such as the UTBB FDSOI MOSFET, we experimentally observe two separate threshold voltages in the forward back gate bias condition while considering the C-V and its derivative both shown respectively in Fig. 2 and its Inset. Consequently, the gate overdrive voltage becomes impractical for describing the level of inversion of the advanced MOSFET architectures. It should be noted that Vov can become negative in MI and for lower levels of inversion, and thus becomes useless.

In RF circuits, designers tend to use shortest devices to get highest possible transit frequency fT and consequently better performance. However, shortest MOSFETs are subject to detrimental short channel effects, lower intrinsic voltage gain, and higher mismatch. In Fig. 3, Drain-Induced-Barrier-Lowering (DIBL) versus the gate length is shown for bulk and FDSOI technologies. Using relaxed and non-minimal lengths provides lower DIBL effect and lower variability while frequency performance is still high enough for the majority of today's applications in the RF spectrum as shown in Erreur ! Source du renvoi introuvable. where fT is plotted versus the Inversion Coefficient (IC) for various MOSFET lengths in 28 nm UTBB FDSOI technology. IC is defined as:

𝐼𝐶 = 𝐼 𝐼  • 𝑊 𝐿 (1)
where ID, W and L are respectively the drain current, the width, and the length. I is the square current at the middle of the moderate inversion with a value of about 0.7 µA for 28 nm UTBB FDSOI [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. For L = 100 nm, the maximum transit frequency is still in the mm-Wave spectrum (> 100 GHz) for the FDSOI technology while DIBL is reduced by 23mV/V with respect to L = 28 nm. Moreover, according to (1) and for fixed ID and inversion level IC, the device area increases as L 2 , which is beneficial for local mismatch effect.

Normalized module and phase of the transadmittance Y21 are respectively shown in Erreur ! Source du renvoi introuvable. and Erreur ! Source du renvoi introuvable. versus frequency for different lengths and at VGS = 0.5 V. The transadmittance is normalized using I/UT where UT is the thermal voltage. All devices are operating in the MI regime. At VGS = 0.5 V, shorter channels (L < 100 nm) are biased at an inversion coefficient of 6.3, while for L = 100 nm, IC = 5.1. For L = 100 nm and at IC = 5.1, with a transit frequency fT of 70 GHz, the fT/10 rule of thumb gives, 7 GHz. At this limit frequency no degradation on the Y21 module is observed and a phase shift of less than 4° is measured. The finger length of the measured structures is 1 µm and the lateral gate distributed effect is largely contributing to the measured phase shift. Though, a phase shift of 10° is measured at 19 GHz with no degradation on |Y21|. In summary, it is clearly evidenced that non minimal channel lengths (i.e. L> 30nm in 28 nm node) in advanced technologies provide high enough fT values that can still be used to design RF circuits, while the conservative fT/10 rule of thumb is misleading, in particular at low inversion levels. 'Common' rules are then inaccurate and lead to overdesign. To overcome these issues, optimal geometries and bias conditions are approximated using time-consuming iterative numerical simulations. Other sizing methods based on the Inversion Coefficient concept have been proposed [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. However, in many circuits where passive elements play a key role such as Low Noise Amplifier (LNA), circuits are optimized using time-consuming iterations of the IC based method since no passive part related constraints are considered in the active part optimization [START_REF] Fadhuile | Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient[END_REF].

III. ADVANTAGES OF UTBB FDSOI TECHNOLOGY

In the UTBB FDSOI technology, MOSFET channel is formed in a thin silicon film separated from the substrate by an oxide film called the Buried OXide (BOX). In 28 nm FDSOI technology, the final silicon film is 7nm thick after process [START_REF] Planes | 28nm FDSOI technology platform for high-speed lowvoltage digital applications[END_REF]. This architecture provides with multiple advantages for high performance and low power applications. In the addition of the well-known SOI technology advantages [START_REF] Adan | SOI as a mainstream IC technology[END_REF][15], UTBB FDSOI technology features lower parasitic capacitances and then high-speed operation. The harmful parasitic substrate coupling is avoided in the UTBB FDSOI by introducing the Ground Plane (GP) which is a highly doped region underneath the thin BOX [START_REF] Fenouillet-Beranger | FDSOI devices with thin BOX and ground plane integration for 32nm node and below[END_REF]. The ground-plane implantation under the BOX is well-type in the structures studied in this work. FDSOI technology allows co-integration of both bulk and SOI devices on the same die thanks to BOX opening for the bulk parts with a dedicated mask [START_REF] Fenouillet-Beranger | Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology[END_REF].

V GS (V) C gc (n.u.) V bG = -10 V V bG = -5 V V bG = -2 V V bG = -1 V V bG = 0 V V bG = 1 V V bG = 2 V V bG = 5 V V bG = 10 V 10 - 8 10 -7 10 -6 10
With less parasitic capacitances, supply voltage can be lowered for reduced power consumption with still high speed operation. Other advantages of UTBB FDSOI are steep subthreshold slope [START_REF] Foty | Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id[END_REF], reduced SCE (cf. Fig. 3), tolerance to radiation as for standard SOI and high temperatures, even though buried oxide isolation is known to give birth to temperature increase because of self-heating effect [START_REF] Fenouillet-Beranger | Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology[END_REF]. However, thanks to a thinner BOX in the UTBB FDSOI, thermal effects influence on device parameters are limited in comparison with standard SOI [START_REF] Sallese | A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism[END_REF].

The advantages of the UTBB FDSOI technology make it possible to implement high performance MOSFETs operating at a low voltage, specifically in the moderate inversion regime. An understanding of the fundamental behavior of the UTBB FDSOI MOSFETs at high frequency is essential for circuit design and a sizing method in MI is a must.

IV. GM OVER ID INVARIANCE BASED METHOD

In digital CMOS circuits, static power consumption is mainly related to the leakage current. However, in analog circuits, biasing current is the main contributor for circuit power consumption. Thus, the devices used in analog blocks need to be permanently biased in the appropriate region. Besides power supply voltage lowering in recent technology nodes, the current budget should be reduced as well.

In RF circuits, a good tradeoff between speed and low current budget is satisfied in moderate inversion. However, for advanced devices such as the asymmetric double gate MOSFETs, the validity of classical hand calculation expressions is questionable. The lack for simple expressions for hand calculation can be reasonably contained using measurement based charts. The measured transconductance efficiency charts assessed in [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF], can be used to size the transistor and to ensure its operation in moderate inversion. The invariance of the gm over ID chart in MI for L ≥ 100 nm makes is easy to generate the required chart. If we take into account the slope degradation using the slope factor n1, shorter geometries can also be accounted for with same merged chart. In Erreur ! Source du renvoi introuvable., gm over ID charts are shown versus IC. A longer geometry (L = 1 µm) is also shown for comparison. Using these charts, the gm over ID value can be reasonably retrieved for any selected IC and for each displayed geometry from WI to SI.

Recently, it is claimed that preselecting drain current (ID), IC, and channel length is the most efficient way to size MOSFETs in analog circuits [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF]. However, the proposed simple expressions of MOS performance mainly rely on EKV formalism which has been extrapolated to a symmetric DG in [START_REF] Sallese | A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism[END_REF] but not yet transposed to the asymmetric DG. However, the choice of the inversion coefficient as a measure of the inversion level in the channel happens to be totally justified since it accurately describes the inversion charge and consequently the operating regime for single or double gate MOSFETs [START_REF] Binkley | Tradeoffs and Optimization in Analog CMOS Design[END_REF] [START_REF] Ghouli | Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET[END_REF]. According to Erreur ! Source du renvoi introuvable., selecting an IC value is equivalent to setting gm over ID of the device. Moreover, based on (1), once IC an ID are known, the geometry ratio (W/L) can be calculated.

V. HIGH FREQUENCY PERFORMANCE ASSESSMENT

One of the interesting high frequency FoM is the transit frequency fT that estimates the high frequency amplification limit and also provides an insight of the transconductance to input capacitance ratio (fT ≈ gm/Cgg) of the MOSFET. The transit frequency versus IC charts for several lengths provide high frequency performance limits since fT represents the frequency at which current gain falls to unity. However, it should be noted that the transistor can operate at any frequency even beyond this limit, provided that non-quasi-static related limitations are carefully taken into account and modeled. The module and phase of the transadmittance versus frequency charts (e.g. Erreur ! Source du renvoi introuvable. and Erreur ! Source du renvoi introuvable.) can also be used to estimate the phase shift and module drop when frequency is set beyond fT. As stated in Section II, the rule of thumb stating that maximum frequency of operation must be lower than fT/10 is too stringent. This rule of thumb finds its origin in the validity of the quasi-static model proposed in [START_REF] Tsividis | Operation and modeling of the MOS transistor[END_REF] and thus is essentially a misinterpretation.

VI. LNA DESIGN USING MI TRADEOFF IN UTBB FDSOI

In this Section, the focus will be on another challenge which is the transistor sizing. The RF designer dilemma is to calculate transistor geometry and current in order to get maximum amplification, minimum degradation of the signal-to-noise ratio, and minimum power consumption. The goal is to provide an illustration of a design method mainly based on the charts and properties described in Section IV and V.

One of the key building blocks in a wireless system is a Low Noise Amplifier (LNA). The LNA circuit amplifies the input signal with minimum degradation of the signal-to-noise ratio. One of the challenges RF designers must face is the simultaneous matching of the noise and the input impedance for the same source impedance. This challenge is beyond the scope of this paper therefore ideal impedance matching is considered here. However, a constraint on the value of the inductors is considered in order to account for integrated inductors with acceptable quality factors.

One of the most used circuit topologies for an LNA is the narrowband cascode. The cascode transistor is used to isolate the input from the inductive load. In particular, the Miller effect is reduced for the input transistor. However, using a cascode topology leads to a minimal room for drain to source voltage required to set both transistors in saturation. This also corroborates the need for MI operation as VDSAT is lower in this regime. The circuit of the cascode LNA is shown in Fig. 8. The transistor M1 is the input transistor and M2 is the cascode transistor. Both transistors are chosen to have same geometry. Degeneration inductor Ls and input series inductor Lg are used for input impedance matching. The following specifications are taken as an example: Drain current is 2 mA, power gain is greater than or equal to 8, operation frequency is F0 = 35 GHz, minimal noise figure NFmin is no more than 2 dB, and input impedance is matched for 50 ohm. In order to size the circuit components and meet the aforementioned specifications, the following 3 steps are followed:

A. IC selection

The maximum value of the FoM given in ( 2) and representing the trade-off between high frequency performance, power consumption, and noise figure is located in the second half of the MI for short channels as shown in Erreur ! Source du renvoi introuvable. for two channel lengths (L = 30 nm and 1 µm).

𝐹𝑂𝑀 = 𝑔 𝐼 • 𝑓 𝑁𝐹 (2)
Optimal IC lays, at least theoretically, between IC = 4 and IC=10. Depending of the length selection, corresponding IC will be chosen where FOM is maximum.

B. Passives related constraints and Length selection

In order to avoid passive components with degraded quality factors Q, some constraints are considered prior to MOSFETs sizing. The values are chosen within the integrated mm-Wave inductor values [25 pH -100 pH] as in [START_REF] Brinkhoff | Scalable Transmission Line and Inductor Models for CMOS Millimeter-Wave Design[END_REF]. The real part of the LNA input impedance is mainly tuned using degeneration inductor Ls. The expression of this real part is given in (3), provided that M1 intrinsic conductance influence on input impedance is neglected:

𝑅𝑒[𝑍 ] = 𝑔 𝐿 𝐶 ≈ 2𝜋𝑓 𝐿 (3)
where Cgs, and fTi are the gate-source, and intrinsic transit frequency of M1, respectively. The specification related to impedance matching fixes the real part of Zin at 50 ohm and consequently a relation between the inductance Ls and the transit frequency is given by ( 3). If we consider a maximum Ls inductance of 100 pH, M1 transit frequency fTi should be greater than 80 GHz. According to Inset of Erreur ! Source du renvoi introuvable., for operation at IC = 4, the MOSFET length that guarantees the required fT is strictly greater than L = 100 nm. To obtain acceptable noise figures and using NFmin versus IC charts (not shown here), length should also be lower than 100 nm. In order to verify the noise figure specification and inductor value The LNA is designed to operate at F0 = 35 GHz and consequently, to cancel the input impedance imaginary part at this resonance frequency, the inductor Lg is tuned with a target value given by [START_REF] Razavi | RF Microelectronics[END_REF]:

𝐿 = 1 (2𝜋𝐹 ) • 𝐶 -𝐿 (4)
where Cin is including the total M1 gate capacitance Cgg and the Miller effect of the gate-drain capacitance (Cgd).

C. Width and VGS calculations

The Width is calculated using the following expression:

𝑊 = 𝐼 𝐼𝐶 • 𝐼  • 𝐿 (5)
Close width values of 22.8 µm and 22.1 µm are found for respectively L = 40 nm and L = 70 nm based LNA circuits.

The gate voltage overdrive with respect to IC charts (not shown here) are used to retrieve the gate to source voltage corresponding to the two IC values for each length. The calculated VGS values are respectively 0.49 V and 0.55 V.

The results of the above sizing are shown in Fig. 10 versus frequency and summarized in Table 1 for the operation frequency F0 = 35 GHz. Power gain is lower for the L = 70 nm based LNA because of the higher IC and consequently lower transconductance efficiency. The input impedance matching is acceptable for both LNA circuits. The NFmin value is higher for the longer channel based LNA as expected, however this can be lowered using optimized layout. The power consumption of both LNAs is 2 mW which is excellent for low-power applications.

VII. CONCLUSION

In this work, a constrained sizing methodology is proposed for the UTBB FDSOI MOSFET. The methodology is based on fT versus IC measured or simulated curves for the length selection, and on gm over ID charts for the width calculation. The Inversion Coefficient is fixed to a value where the MOSFET optimum performance is expected, making this analysis dependent only on the channel current, and 'independent' of the front and back gate biases, a great simplification in terms of analysis. The methodology takes into account the passive components limitations and thus requires less if not minimal iterations.

Fig. 1

 1 Fig. 1 Square law model (SI) and weak inversion exponential model failures to predict measured gm/ID in MI for a long and short channel devices.VTH is defined here as the VGS at the maximum of ∂Cgc/∂VGS.

Fig. 2

 2 Fig. 2 Measured gate to channel capacitance normalized using front oxide capacitance (Cox.W.L) with respect to VGS for various VbG and its derivative (Inset) for N-type UTBB FDSOI MOSFET.

Fig. 3

 3 Fig. 3 Comparison of DIBL between FDSOI and Bulk in saturation (VDS=1V) and VbG = 0 V.

Fig. 4 Fig. 6

 46 Fig. 4 Measured fT versus IC for various MOSFET lengths in saturation (VDS=1V). Inset gives a focus on the second part of the MI (1 < IC < 10)

Fig. 7

 7 Fig. 7 gm over ID charts versus IC for several short NMOS along with a longer channel (L = 1 µm) for comparison.

Fig. 8

 8 Fig. 8 LNA cascode circuit.

Fig. 9 FOM

 9 Fig. 9 FOM versus IC for two lengths. FOM maximizing respectively at IC = 5 and IC = 9. Both geometries provide acceptable high frequency performance. Moreover, L = 40 nm and L = 70 nm MOSFETs are less subject to DIBL and Mismatch than minimal length. Thus, an Ls value of 33 pH and 39 pH for respectively L = 40 nm, and L= 70 nm MOSFET based LNAs are found.

Fig. 10

 10 Fig. 10 Power gain S21, Input Match S11, and minimal noise figure NFmin with respect to frequency for two LNA circuits (first with MOSFET length of 40 nm and second with 70 nm).

Table 1

 1 Summary of the two LNAs parameters at F0 = 35 GHz.