R Vauche

E Bergeret

J Gaubert

S Bourdel

O Fourquin

N Dehaese

A Remotely UHF Powered UWB Transmitter for High Precision Localization of RFID Tag

Keywords: Power Harvesting, Pulse Generator, Remotely Powered, RFID, Tag Localization, UWB, I

The design of a remotely UHF powered UWB transmitter is presented in 0.13µm CMOS standard process. Power harvesting unit is based on a Dickson voltage multiplier and UWB pulse generator uses filtered combined edge method. Multi-Vt technique and CMOS logic allows pulse generator power consumption between two consecutive pulses to be reduced enough to be remotely powered. It achieves FCC compliant pulses having 1.82Vpp and a PRF of 15kHz at 10m thanks to the power harvesting unit.

INTRODUCTION

Due to its rapid adoption in industry, RFID technology is facing new application demands. Especially, accurate Real Time Location (RTL), robust, and secure identification and management of large Tag number are needed to address new purposes, and new markets. Such a demand is all the more difficult to satisfy since the Tag cost must be lower than few tens of cents. Consequently the tag must be fabricated using, low cost technologies: a single CMOS chip in a low cost technology with no external devices such as crystals or filter and moreover the chip must be remotely powered to avoid the use of costly cells or battery.

Since UHF RFID technology uses narrowband continuous waves around 900MHz, it is intrinsically limited for high resolution location, sensitive to multipath cancellation and affected by multi-users interference. Even if improvements can still be achieved on UHF RFID systems, a technological breakthrough is needed to overcome all those limitations. According to recent works, UWB-IR is a promising technique for the next generation of RFID systems [START_REF] Dardari | Ultrawide Bandwidth RFID: The next generation?[END_REF]. The very short time duration of the emitted pulse enables (i) accurate localization with TOA or TDOA techniques [START_REF] Dardari | Ultrawide Bandwidth RFID: The next generation?[END_REF], (ii) efficient power gating which allows power consumption to be reduced, (iii) high multipath resolution which allows coverage area to be increased, (iv) efficient multiple access and interference mitigation which allow the number of Tags to be increased [START_REF] Ha | Replacing cryptography with ultra wideband (UWB) modulation in secure RFID[END_REF][3][4] [START_REF] Shen | Fundamental limits of Wideband localization -Part I: A general framework[END_REF] [START_REF] Shen | Fundamental limits of Wideband localization -Part II: Cooperative networks[END_REF].

Several communication techniques can be implemented to achieve the uplink in a Remotely Powered UWB Tag. A first solution is to use UWB backscatter propagation [START_REF] Guidi | Backscatter communication using ultrawide bandwidth signals for RFID applications[END_REF]. Backscattering is very well suited to passive Tag because it consumes a very small amount of power since it consists in varying the input impedance of the circuit. Unfortunately, the backscatter signal has very low energy which degrades the localization accuracy [START_REF] Dardari | Ranging with ultrawide bandwidth signals in multipath environments[END_REF]. Another solution is to use an ultra low power UWB pulse generator remotely powered by an UHF downlink [START_REF] Baghaei-Nejad | A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS[END_REF]. Indeed UWB pulse generators are known to consume a very small amount of energy for a pulse emission.

In [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF] we demonstrated an energy consumption of 9pJ per pulse with 10dBm pulse peak power. Such low energy per pulse consumption enables ultra low power consumption at low data rate (few tens of microwatt for 1Mbs -1 bit rate) which can be supplied by a standard UHF energy harvesting unit.

Recent works showed the feasibility of UHF/UWB hybrid RFID Tags [START_REF] Baghaei-Nejad | A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS[END_REF] [START_REF] Pelissier | A 112Mb/s full duplex remotely-powered impulse-UWB RFID transceiver for wireless NV-Memory applications[END_REF]. It appears that achieving high energy pulse with a very small power budget is a bottleneck which finally limits the localization accuracy and the range. To improve the energy efficiency of the pulse generator, high energy pulse must be used [START_REF] Dardari | Ultrawide Bandwidth RFID: The next generation?[END_REF]. But in the same time, energy consumed per pulse must be minimized. Especially, reducing the power consumed between the emissions of two consecutive pulses is highly required to reach ultra low power consumption at medium or low rate. Moreover, efficiency of the energy harvesting unit must also be maximized to increase the available power and so, the localization accuracy and the tag reader range.

In this paper, we present a remotely powered UHF/UWB transmitter for a passive RFID Tag for high precision localization. As shown in Fig. 1, the Tag consists of an UWB ultra low power pulse generator powered by an UHF energy harvesting unit. The tag, which can be power supplied by conventional UHF RFID readers, is designed to be used with high sensitivity UWB coherent receivers such as described in [START_REF] Masson | A 1 nJ/b 3.2-to-4.7 GHz UWB 50 Mpulses/s double quadrature receiver for communication and localization[END_REF] which are beyond the scope of this paper. The presented pulse generator is based on the topology presented in [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF] which enables the generation of high energy pulses. In this work, we present a new design optimized to minimize the power consumed between the emissions of two consecutive pulses in order to be supplied by an UHF energy harvesting unit. This UHF energy harvesting unit is based on the topology presented in [START_REF] Bergeret | Modeling and design of CMOS UHF voltage multiplier for RFID in a EEPROM compatible process[END_REF] which has been optimized to improve the power efficiency in the technology used. We show that the tag can generate 1.83Vpp pulses at a continuous Pulse Repetition Frequency (PRF) of 15kHz at 10 meters. Section II presents the principle of the proposed Tag and gives an analysis of the power budget according to EPC Gen2 standard regulation. Then, the design of the pulse generator and of the UHF energy harvesting unit is detailed in section III. Based on measurements of the power harvesting unit, the simulated performances of the transmitter using a 0.13µm CMOS design kit are then presented in section IV to validate our approach.

II. PRINCIPLE AND POWER BUDGET

Pulse generator power consumption and harvesting unit efficiency are the design key parameters. These parameters set the system performances in terms of bit rate and range. Due to gated nature of the emitted signal, instantaneous current absorbed by the pulse generator can be very high during the pulse emission. Fig. 2 shows typical current consumption of a pulse generator [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF].

The mean power consumption is a function of the mean bit rate (D b-mean ) and can be written as follows:

_ 0Hz cons PG ap b mean P E D P - = ⋅ + (1)
where P 0Hz is the constant DC power consumed at a PRF of 0Hz and E ap is the active energy added while pulse is generated.

To properly power supply the pulse generator, the harvesting unit must provide an available power (P av-HU ) at least equal to P cons_PG . P av-HU depends on efficiency η of the harvesting unit and on regulated UHF downlink EIRP as follows:

2 _ _ 4 cons PG av HU P P EIRP d λ η π   = = ⋅     (2)
where λ is the wavelength of UHF downlink. The maximum theoretical range is reached when D b-mean is null, i.e. all the harvested energy is consumed by the P 0Hz . To be able to generate one or several UWB pulses, an energy tank must be included in the system. This energy tank is the capacitor C TANK (see Fig. 1) which must be sized to supply energy consumed when UWB pulses are emitted, while a sufficient supply voltage V DD is maintained. For a given technology, with a minimum and a maximum voltage supply, respectively V DD-min and V DD-max , and assuming that the capacitor voltage is V DD-max at the beginning of UWB pulses burst, the minimum tank capacitor value is given by: ( )

0 _ 2 2 max min 2 ap S Hz av HU TANK DD DD N E T P P C V V - -   + -   = - ( 4
)
where N is the number of UWB pulses emitted into one burst and T S , the symbol time into the burst period. It should be highlighted that if the system need transmission of an only one UWB pulse into one burst, the value of T S is not defined and should be replaced by the pulse duration τ in (4).

It appears clearly that using an important number of pulses into one UWB burst leads to a large capacitor value which can lead to a large silicon area if the system is fully integrated. If the bit sequence is not very large (e.g. 96 bits for an EPC code), and if the technology is able to work with a large gap V DD-min and V DD-max , it may be possible to transmit such short bursts with a system using an integrated tank capacitor.

As a summary for this section we can note that: (i) the mean bit rate D b-mean is set by harvesting power, energy consumption per pulse E ap , and pulse generator DC power P 0Hz , (ii) the length N of bit sequence emitted during one burst depends only on tank capacitor value C TANK .

III. SYSTEM DESIGN

A. Harvesting power unit design

The power harvesting unit is based on a Dickson voltage multiplier architecture implemented with MOS diodes in a CMOS technology as shown on Fig. 3. In [START_REF] Bergeret | Modeling and design of CMOS UHF voltage multiplier for RFID in a EEPROM compatible process[END_REF] we give an analysis of this multiplier architecture and we show that the power efficiency depends, for a targeted output power, on the transistors sizing (width and length), and on the number of the multiplier stages.

In typical UHF RFID tags, no matching circuit between the antenna and the voltage multiplier are used and so, antenna must match input impedance of the harvesting unit. In addition it should be pointed that all impedance values are not achievable for a tag antenna and so, voltage multiplier must be designed with this constraint. As a consequence some designs have to be ignored thanks to impossible antenna matching [START_REF] Bergeret | UHF RFID Tag Robustness[END_REF].

The voltage multiplier design has been optimized for the 0.13µm CMOS technology used in this work. To reach the best power harvesting efficiency, design key parameters are: (i) a MOSFET length and width of respectively 0.13µm and 15µm, (ii) a value of 1.2pF for multiplier capacitors Cm and (iii) a three stages multiplier.

A test chip has been realized including a standalone voltage multiplier with an ESD protection circuit at its input. The measured power efficiency of the harvesting unit as a function of its input power is shown in Fig. 4. The efficiency measurements are performed on chip at 900MHz, by using a Vector Network Analyzer (VNA) in a sweep power mode. As a consequence, the VNA provides the input power to the harvesting unit input while measuring its impedance. The power absorbed by the harvesting unit (P IN_ABS ) is then calculated from the VNA RF output power and the measured input impedance. The harvesting unit output is connected to a resistive load and an oscilloscope in order to measure the output voltage and the output power P AV_HU . With an EIRP of 4W according to US regulation and a tag antenna of 0dBi the available input power is -15.5dBm at 10m range leading to an available power at the harvesting unit output P AV_HU of 3.5 µW.

B. Pulser design

Among the different UWB pulse generation techniques, many works show that filtered combined edge method is wellsuited when an high energy efficiency is required as in remote powered UHF applications [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF][14] [START_REF] Wentzloff | A 47pJ/pulse 3.1-to-5GHz alldigital UWB transmitter in 90nm CMOS[END_REF]. The presented generator is a derivative of a previous designed pulse generator which consumes a static current of 2.6mA due to integrated digital edge combiner based on Current Mode Logic (CML) gates [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF]. To reduce the static power consumption, the choice of a standard CMOS logic associated to a power manager is assumed.

In wireless emitters design, leakage currents of CMOS logic are often negligible compared to bias currents, however it becomes sizeable when no bias current are required. Furthermore, leakage currents which are channel width dependent increase owing to Drain-Induced Barrier Lowering (DIBL) effect when channel length and Threshold Voltage (Vt) decrease. For example, with ST 0.13µm design kit, the use of low-VT transistors for the pulse generator based on CMOS digital edge combiner leads to an unwanted leakage current greater than 50uA. To minimize this static leakage power consumption, multi-Vt and Multi-Threshold CMOS (MTCMOS) techniques can be used [START_REF] Amelifard | Low-power fanout optimization using MTCMOS and multi-Vt techniques[END_REF]. The first consists in using the most appropriate threshold type for transistors according to their function whereas the second implies the design of hybrid logic gates.

As shown in Fig. 5, UWB pulse generator can be divided in four parts: the band-pass filter, the high-Vt current driver, the low-Vt digital edge combiner and the high-Vt power manager.

Band-pass Filter uses Bessel-Thompson coefficients which allow UWB pulse duration to be minimized. Its input and output are matched to 50Ω impedance in order to maximize power transfer to 50Ω antenna. High-Vt Current Driver linked to Band-pass Filter is a class-C amplifier where current driver drain is biased by L. C1 capacitor prevents V DD biasing of others filter nodes. Finally, a baseband pulses must be applied on High-Vt Current Driver gate to emit UWB pulses. A sizing method of the driver regarding the application needs and the filter characteristics is given in [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF]. To generate an UWB pulse, a rising edge has to be applied on High-Vt Power Manager input (CK) which allows power management to be disable (PM='0' and PM\='1'). Then, a 500ps delayed rising edge is generated on CKd in order to ensure that all V-VDD and V-GND supplies of Low-Vt Digital Edge Combiner are enable when it is propagating into itself. Delay cell consists in three strings of balanced and unbalanced inverters which mainly delays rising edges for a duration of 500ps.

In Low-Vt Digital Edge Combiner, rising edge from CKd is propagating in a string of buffered inverters loaded by a capacitor. Next, the buffered rising edge A2 is combined with the buffered falling edge B2 to make an inverted baseband pulse thanks to fast NAND logic gate. Capacitors in buffered inverters string are sized with the help of post-layout simulations to have a 75ps width buffered baseband pulse on driver current gate. This baseband pulse width is sized regarding the designed band-pass filter [START_REF] Bourdel | A 9pJ/pulse 1.42Vpp OOK CMOS UWB pulse generator for the 3[END_REF]. After the baseband pulse and so UWB pulse are issued, a falling edge is generated on CKd and Low-Vt Digital Edge Combiner is put in its sleeping state. When the falling edge arrives on CKend, END is set to '1' and power manager is enable (PM='1' and PM\='0'). Finally, END is set to '0' when CK is reset.

The pulse generator presented in this work has been postlayout simulated in a 0.13µm CMOS from STMicroelectronics. Voltage supply is 1.2V and die area is 0.64mm². It achieves FCC compliant pulses with 1.83Vpp on 50Ω resistive load as shown on Fig. 6. Central frequency and 10dB bandwidth are respectively equal to 7.25GHz and 6.25GHz.

As shown on Fig. 7, power consumption for a pulse frequency of 0Hz is 2.07µW and dynamic energy consumption is 68.6pJ/pulse which leads to a power consumption of 70.6µW at 1Mpulse/s. Duration of an UWB pulse generation cycle is greater than 4ns between CK rising edge and END rising edge. It imposes also a maximum power consumption of 13.7mW at the maximum PRF of 200Mpulse/s.

IV. RESULTS AND VALIDATION

To validate the proposed system, the mean bit rate is evaluated as a function of the communication range. The bit rate is derived from (3) and is given by:

2 0Hz 1 . . 4 b mean ap D EIRP P E d λ η π -     = -           (5)
The bit rate is plotted in Fig. 8 using the characteristics (η, E ap , P 0Hz ) of our system. The theoretical maximum range is 11.83m and a mean bit rate of 15kb.s -1 is obtained at 10m which corresponds to a received power of -15.5dBm.

The needed value of the capacitor C TANK , regarding the number of pulses in a burst is calculated from (4). Assuming a maximum V DD variation of (V DD-max -V DD-min =∆V=0,9V), the minimum capacitor value is 56pF for N=1. A burst of N=100 pulses can be generated with a 5,6nF capacitor. The instantaneous bit rate during the burst can be increased up to 200Mb/s. Using high instantaneous bit rates allow the channel time occupancy to be significantly reduced. Indeed the 96 bits of an EPC gen2 frame could be transmitted in less than 500ns instead of 167us in the best case of UHF gen2 uplinks. However on chip integration of high value capacitors increases significantly the silicon area. The main characteristics of the proposed system are summarized in TABLE II. It especially shows the good energy efficiency of pulse generator which allows high energy pulses required for high accuracy localization to be generated.

V. CONCLUSION

A transceiver for hybrid UHF/UWB Tag has been presented for localization applications. This transceiver is based on an UHF energy harvesting unit which can supply a pulse generator, operating at a mean bit rate of 15kb.s -1 at 10m. The pulse generator achieves high energy pulses increase the localization accuracy in the case of TOA estimation. The transceiver can be fully integrated since the C tank of energy harvester is equal to 56pF and the overall area is estimated to be 0.8mm².

Figure 1 .

 1 Figure 1. Tag system

Figure 2 .

 2 Figure 2. Pulser consumption

Figure 3

 3 Figure 3. Power harvesting architecture

Figure 4 .

 4 Figure 4. Measured efficiency vs input power

  Low-Vt Digital Edge Combiner generates baseband pulses needed by High-Vt Current driver for UWB pulses generation. It is only designed with low-Vt MOS devices and supplied by Power Managed Supply thanks to V-VDD and V-GND supply buses. High-Vt Power Manager consists in D flip-flops, a delay cell, logic buffers, and a balun and uses only high-Vt MOS devices. It allows complementary power management signals which drive Power Managed Supply (PM and PM\) to be generated.

Figure 5 .

 5 Figure 5. Pulse generator design

Figure 6 .Figure 7 .

 67 Figure 6. Pulse obtained with the proposed pulse generator on 50Ω in time domain and frequency domain,

Figure 8 .

 8 Figure 8. Mean bit rate as a function of the communication range.

TABLE I .

 I CAPACITOR NEEDED FOR ∆VMAX=0.9V

	Number of bit by burst (N)	1	50	100
	CTANK		56 pF	2,8nF	5,6 nF
	TABLE II.	PERFORMANCE COMPARISON OF RECENT WORKS
			This Work**	[10]	[8]
	UWB tx
	V pp		1.83V	220mV	220mV
	P cons		7.09mW (@100Mbs -1 )	6.5mW (@112Mbs -1 )	918uW (@100Mbs -1 )
	E c		70.9pJ	58.8pJ	9.2pJ
	E p *		3.77pJ	0.24pJ	0.08pJ
	η=E p /E c		5,3%	0.4%	0.86%
	Pulse width (τ)		450ps	2ns	620ps
	Harvesting
	V dd		1.2 V	-	2.75V
	C		56pF	-	211nF
	System
	D b_max (burst mode)	200Mbs -1	-	100Mbs -1
	D b (mean)

  Vpp 2 /(8.τ.Z0); **Mixed measurement and simulation results

		15,4kbs -1	112Mbs -1	570kbs -1
	Range	10m	10cm	13,9m
	Sensitivity	-15.5dBm	14dBm	-18.5dBm
	*Approximation:


Sylvain Bourdel

R Vauche

O Ramos

E Muhr

Jean Gaubert

N Dehaese

Herve Barthelemy

An inductorless CMOS UWB pulse generator with active pulse shaping circuit

Keywords: Pulse Generator, UWB, FCC, CMOS, Impulse Radio, Pulse Shaping

des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

I. INTRODUCTION

Interest has grown for Ultra Wide Band (UWB) Impulse Radio (IR) applied to low cost communication systems since it was proposed as a possible physical layer for the IEEE 802.15.4 standard. Recent works show the potential of IR for power saving thanks to the low energy of the emitted pulse and also for multipath resistance, due to the use of energy detectors in low cost receivers [START_REF] Lee | A 2.5 nJ/bit 0[END_REF]. Since of those advantages, IR is also well suited to other low cost applications such as Body Area Network (BAN) [START_REF] Ryckaert | Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation[END_REF], Radio Frequency IDentification (RFID) [START_REF] Baghaei-Nejad | A Remote-Powered RFID Tag with 10Mb/s UWB Uplink and -18.5dBm Sensitivity UHF Downlink in 0.18µm CMOS[END_REF] and Sensor NetWork (SNW).

Currently, most pulse generator topologies for UWB-IR require inductors or a passive pulse shape networks to operate which is a major drawback for CMOS integration and production cost. Typically, the LO switching technique uses LC topologies [START_REF] Phan | Energy-Efficient Low-Complexity CMOS Pulse Generator for Multiband UWB Impulse Radio[END_REF] and the filter excitation technique needs a passive resonator [START_REF] Bourdel | A 9pJ/Pulse 1.42Vpp OOK CMOS UWB Pulse Generator for the 3[END_REF] for their implementation. To limit the use of inductors, architectures based on ring oscillators or based on digital pulse shaping have been proposed [START_REF] Wentzloff | A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS[END_REF] [START_REF] Norimatsu | A UWB-IR Transmitter With Digitally Controlled Pulse Generator[END_REF][10] [START_REF] Sim | A CMOS UWB Pulse Generator for 6-10 GHz Applications[END_REF]. However, according to recent publications, those techniques still use passive components (filters, baluns or matching cells) that shape the pulse in order to comply with regulation spectrum masks. To reduce the need for such passive networks, a solution is to design pulse generators with active pulse shaping circuits. Active pulse shaping techniques enable a better control of the output spectrum. It can especially be used to reduce the side lobes of the output spectrum which limit the Adjacent Chanel Power Ration (ACPR) in the case of multi-band communications. For example, a side-lobe rejection of 20dB is needed to comply with IEEE 802.15.4a standard. Among the different pulse shaping techniques already presented [START_REF] Dokania | A 6µW, 100Kbps, 3-5GHz, UWB impulse radio transmitter[END_REF], only a few of them enable the reconfiguration of the shape. The elementary pulse combination technique appears to be well suited to the design of pulse synthesizers with pulse shape tuning capabilities [START_REF] Bourdel | Low-Cost CMOS Pulse Generator for UWB Systems[END_REF] [9] [START_REF] Vauché | Fully Tunable UWB Pulse Generator with Zero DC Power Consumption[END_REF].

In this paper, we present a practical implementation in a 0.13µm CMOS technology of a technique described in [START_REF] Bourdel | Low-Cost CMOS Pulse Generator for UWB Systems[END_REF]. Some measurement results of different pulse shapes are also presented to validate the efficiency of the tuning capability of the proposed pulse generator. The first section of this paper presents the principle of pulse synthesis used in the proposed pulse generator. The circuit design is detailed in the second section and the measurement results are given in the last part.

II. PULSE SYNTHESIS PRINCIPLE

The pulse synthesis technique consists in combining elementary baseband pulses (e n (t)) in order to generate a more complex signal. A bandpass pulse (p(t)) can be expressed as follows :

S. Bourdel

  = - =     ∑ ∑ (1)
where g n and τ n refer to the magnitude and the width of the n th elementary pulse (e n (t)). In Fig. 1 two different bandpass pulses are plotted with their associated coefficients (g n and τ n ): the 5 th derivative of a Gaussian pulse (named 5 th Gaussian pulse in this paper) and the impulse response of 3 rd order Bessel filter (named Bessel pulse in this paper). The 5 th Gaussian pulse is known to be FCC compliant [START_REF] Kim | All-digital low-power CMOS pulse generator for UWB system[END_REF] and the Bessel pulse presented here has a 4GHz bandwidth centered at 8GHz. Moreover, p(t) spectrum is slightly dependant on e n (t) shape. This enables FCC compliant pulses to be synthesized with the same elementary pulse (e(t)) having the same width τ [START_REF] Vauché | Fully Tunable UWB Pulse Generator with Zero DC Power Consumption[END_REF] which reduces the system complexity.

III. UWB PULSE SYNTHESIZER DESIGN

The principle of the synthesizer is given in Fig. 2. It consists of a Voltage Controlled Delay Line (VCDL) that propagates a rising edge. Two consecutive edges (A n-1 and A n in Fig. 2) are then combined to produce complementary elementary baseband pulses (C n and n C in Fig. 2). Varying delay cells are used in the VCDL to control the width (τ n ) of the elementary pulses. Complementary pulses are needed here because differential pairs in the elementary pulse combiner are used. Once the elementary pulses are combined, the resulting bandpass pulse is applied to a 50Ω antenna using a driver. The antenna is driven in a differential mode in order to maximize the output power.

The delay cells are MOS Current Mode Logic inverters [START_REF] Bourdel | A 9pJ/Pulse 1.42Vpp OOK CMOS UWB Pulse Generator for the 3[END_REF] shown in Fig. 3a The antenna driver is presented in Fig. 5 and consists of a common source amplifier with a resistive load driven by a common source stage with an active load. Both stages operate in A class. The output stage is designed in order to drive a simple dipole antenna in differential mode. Thus, the 100Ω output loads leads to a 50Ω differential impedance and no coupling capacitors are used. Active loads (MAL p and MAL n ) are biased with the same current copy structure used in the elementary pulse combiner. Since this topology is sensitive to common mode effect, the driver has been intensively characterized with Monte-Carlo simulations in order to maintain the gain over a large range of PVT variation.

IV. MEASUREMENT RESULTS

The pulse synthesizer has been implemented in a 0.13µm CMOS technology from ST-Microelectronics. The order of the implemented synthesizer is N=7 to generate a signal composed of seven elementary pulses. Seven external current sources connected to nodes Ig 0 to Ig 6 are used to control the elementary pulse magnitudes and only one voltage source (Vτ) is used to set their width at the same value (τ n =τ). The use of a unique control voltage to tune the width of the elementary pulses reduces the number of I/O pads. All the presented pulses are obtained only by tuning these external sources. Measurements are performed with a two channel Agilent DSO81204B real-time oscilloscope.

The two pulses presented in Fig. 1 have been synthesized and their measured time responses are presented in Fig. 6 without cable loss compensation. The values of I n have been slightly tuned resulting in the pulse spectrums which are compliant with FCC as represented in Fig. 7. Suppressing the lower side lobes present in the output power spectrum is commonly a difficult issue which limits FCC standard compliance [START_REF] Dokania | A 6µW, 100Kbps, 3-5GHz, UWB impulse radio transmitter[END_REF]. Using the tuning capabilities of the pulse generator, the lower side lobe has been significantly reduced as shown in the Fig. 6 and Fig. 7. The generated Bessel and 5 th Gaussian pulse exhibit a lower side lobe rejection of 30dB and 38dB respectively. When FCC compliant pulses are synthesized, the maximum output peak to peak magnitude is 220mV (taking into account 3dB cable loss). In this case, the maximum 10dB bandwidth is 3.5 GHz and is centered at 4.9GHz. Compared to the theoretical pulses of Fig. 1, the bandwidth is reduced. This is due to the limited bandwidth of the antenna driver and also due to the long interconnection wires between all the differential pairs (nodes O + and O -in Fig. 4).

As shown in Fig. 8, this filtering effect changes the pulse shape and needs to be compensated. Here, the compensation is achieved directly by tuning the values of I n . Due to this compensation, the values of I n are not a linear function of g n and are, for the 5 th Gaussian pulse: I 0 =0, I 1 =520uA, I 2 =1.9mA, I 3 =3.1mA I 4 =1.98mA, I 5 =0.6mA, I 6 =0.07mA. The value of V τ is 0.4V. Such a compensation technique could also be applied to cancel other effects that might change the pulse shape like PVT variations.

As presented in Fig. 9a, the measured minimum width of an elementary pulse is 100ps. This minimum width (τ min ) set to 1/(2.τ min )=5GHz the maximal center frequency which can be achieved by the synthesizer. For such a width, the magnitude of an elementary pulse can be tuned from 0 to 80mV. Depending on the number of elementary pulses used, the pulse generator can synthesize baseband pulses (Fig. 9a), monocyle pulses (Fig. 9b) or arbitrary waveforms (Fig. 9c and Fig. 9d).

The maximal measured Pulse Repetition Frequency (PRF) is 800MHz and is presented in Fig. 9d using an arbitrary waveform of 7 elementary pulses. With such a high PRF, this topology is able to generate quasi-continuous waves having a time period equal to T=Nτ.

The measured jitter is lower than 25ps pp and could be further reduced by using a DLL instead of a simple VCDL. The total power consumption for the pulse presented in Fig. 9d is 87.6mW@800MHz and is the maximum measured power consumption. For such a PRF, the energy consumed by pulses is 110pJ. Here more than 50% of the power is consumed by the output stage which is designed with no inductor in order to reduce the silicon area. This design strategy results in a circuit (shown in Fig. 10) having an active silicon area (excluding the pads) of 0.06mm 2 only. TABLE I shows the good performance of the generator in terms of tuning capabilities and integration. The design of an UWB generator based on pulse synthesis is proposed and implemented in a 0.13µm CMOS technology which is well suited for low cost applications. The pulse generator can be programmed to synthesize different pulse shapes. The tuning capabilities that are demonstrated can be used for different needs such as side lobe suppression or impairment reduction. Our pulse generator is fully integrated in a 0.13µm CMOS technology. It is designed without inductors, baluns or additional passive networks and it can synthesize FCC compliant pulses.

Fig. 1 .

 1 Fig. 1. Bessel impulse response (a) and 5 th Gaussian pulse (b) with their associated parameters (g n and t n ) for pulse synthesis.

Fig. 4 .Fig. 2 .Fig. 3 .Fig. 5 .

 4235 Fig. 4. Elementary pulse combiner

Fig. 6 .Fig. 7 .Fig. 8 .

 678 Fig. 6. Measured time response of the differential output (s(t)) for a Bessel pulse synthesis (a) and a 5 th Gaussian pulse synthesis (b)

Fig. 10 .Fig. 9 .

 109 Fig. 10. Chip micro-photograph

  1 , R. Vauché 2 , O. Ramos 1 , E. Muhr 1 , J. Gaubert 1 , N. Dehaese 1 , H. Barthelemy 3 ,

	An Inductorless CMOS UWB Pulse Generator
	with Active Pulse Shaping Circuit
	1 Aix-Marseille University, 2 ISEN-Toulon, 3 Toulon University, IM2NP, and CNRS
	Campus de Saint-Jérôme, Case 142
	Avenue Escadrille Normandie Niemen
	F-13397 Marseille, France

VI. ACKNOWLEDGEMENTS

This work was carried out within the GRECO project which was supported by the french Agency of the National Research (ANR) and the Secured Communicating Solutions (SCS) world class cluster.

VII. REFERENCES


L Ouvry

G Masson

M Pezzin

B Piaget

B Caillat

Sylvain Bourdel
email: sylvain.bourdel@minatec.inpg.frnicolas.dehaese

N Dehaese

O Fourquin

Jean Gaubert

S Meillère

R Vauché

A 4GHz CMOS130nm IR-UWB dual front-end transceiver for IEEE802.15 standards

Keywords: UWB, CMOS IC, Emitter, Receiver, Coherent, Non Coherent, BAN

    A 4GHz CMOS 130 nm IR-UWB dual front-end transceiver for IEEE802.15 standards

I. INTRODUCTION

Over the last decade, the development of innovative architectures for the transmission and reception of UWB-IR signals benefitted from the publication of IEEE standards aiming different application areas. The IEEE802.15.4a [1] had first being published in 2007 to unify a specification based on the UWB impulse radio technology to cover the need for 1 Mbits/s class wireless systems offering sub-meter precision location at tens of meter range. Then, the emergence of devices in the smart phone eco-system for leisure and healthcare, but also in the medical area, called for the Body Area Network (BAN) and wearable devices concepts. It led to the development of the dedicated IEEE802.15.6 standard published in 2011 in which a UWB based specification is given with strong similarities with 15.4a but with simplifications aiming at reducing power consumption [START_REF][END_REF] [START_REF] Schwoerer | Body Area Network standardization effort in Europe[END_REF].

UWB-IR has significant advantages to address the large span of BAN applications in a disruptive manner compared to narrowband solutions in ISM bands. They are robustness to narrow band fades, protection against ISM bands interferers, bit rate scalability from 400 kbits/s to 12.6Mbits/s with the same hardware, reduced transmit power well below -10dBm, ultra-low power implementations especially at transmitter side at the milli-Watt scale, reduced antenna size, etc [START_REF] Wang | A meter-range UWB transceiver chipset for around-the-head audio streaming[END_REF].

Being in 15.4a or 15.6, the specification enables the implementation of coherent and non-coherent approaches at the receiver side, thus giving opportunities for power consumption, performance and complexity tradeoffs. Purely non coherent front-ends based on threshold crossing or energy detection offer low power high-frequency-synthesis-free conversion to baseband at the expense of reduced sensitivity and lower robustness to blockers, whereas mixer-based quadrature down conversion front-ends propose the opposite compromise. Once in baseband, the conversion to the digital domain can be done at Nyquist rate over one several bits, enabling afterwards fast and parallel synchronization and channel estimation by the Digital Base Band (DBB). It may also be done at a lower rate, e.g. the Pulse Repetition Frequency (PRF), if prior processing is done in the analog domain with the aim to reduce ADCs consumption at the expense of serial search done by the DBB during synchronization. This paper presents a smart combination of a non-coherent (NC-Rx) and a coherent receiver (C-Rx) front-end to offer several possible tradeoffs at once for the reception of 15.4a or 15.6 signals [START_REF]UWB Radio for BodY area network[END_REF]. This dual-front-end receiver is assembled with a transmitter in a single CMOS chip called "RUBYLB" and operates in the 4-GHz band. Its architecture and design principles are presented in Section II. The measurement results are given in Section III and Section IV concludes the paper.

II. CHIP ARCHITECTURE AND DESIGN

A. Chip Architecture and dual-front-end concept

The RUBYLB chip architecture is shown on Fig. 1. On the receiver side, the output of the shared LNA feeds the remainder of the coherent Rx on the one side and the NC-Rx on the other side.

The C-Rx is made of a quadrature down conversion stage, an anti-aliasing and blocker rejection filter, a second quadrature down conversion stage and a bank of four integrators which will integrate the signal over 2ns windows. The position of the four windows is set by the DBB through a 125MHz Double Data Rate (DDR) parallel port at the PRF. It has as its corollary that a synchronization and channel estimation algorithm would perform a serial-parallel search with 16 serial steps to reach 1ns resolution with half overlapping windows, thus needing at least 16 consecutive preamble symbols to complete it.

The NC-Rx is made of a rectifier followed by a detector which output feeds a LVDS converter to interface the digital baseband. Given the detector bandwidth, an equivalent 1bit 1GHz sampling is performed. Therefore the capture of a complete channel impulse response is ultimately possible within a single preamble symbol. In the case of IEEE802.15.6, preamble symbols are made of Kasami sequences of length 63 pulses. In [START_REF] Miscopein | Low complexity synchronization algorithm for non-coherent UWB-IR receivers[END_REF] a thorough description of how the DBB would perform the preamble detection and synchronization in a few symbols can be found. The justification of the dual front-end receiver therefore lies in the capability of the system to perform preamble detection, synchronisation and initial channel estimation in a very short time with a low power receiver and then move to a higher sensitivity coherent receiver which will complete the channel estimation and perform symbol detection and demodulation, either in a coherent or non coherent manner.

B. Transmitter Design

The transmitter was originally designed to provide a nontunable 2GHz bandwidth with maximal voltage swing [6] and not expected to be fully compatible with the standards spectrum masks, the objective being essentially a successful integration for further use in a demonstrator. It is based on an UWB pulse generator followed by a band-pass filter as shown on Fig. 1. The baseband pulse generator generates two τdelayed excitations and then, when the trigger is reset (resp. set), a positive (resp. negative) pulse is generated on the clock rising edge thanks to the balanced output "RF out".

C. Non Coherent Receiver Design

The Non-Coherent Receiver architecture is described in Fig. 1. The receiver consists of a high gain wideband LC filter LNA [START_REF] Battista | Design and implementation of UWB CMOS LC filters LNA for carrier less impulse radio receivers[END_REF] followed by a non coherent pulse detector and a CMOS to LVDS converter which provides received data to the digital base band (DBB). The non-coherent pulse detection is performed by rectifying the RF signal and low pass filtering instead of squaring the RF signal. The threshold detection is achieved with biased CMOS inverters [START_REF] Dehaese | Low-power CMOS energy detector for non coherent impulse-radio UWB receivers[END_REF]. A 1ns 0-V DD square signal is obtained at the detector output for each incoming UWB pulse. A CMOS to LVDS converter is used to drive this wideband digital signal to the Digital Base Band input. The pulse detection principle is depicted in Fig. 2. The rectifier is composed of a cascade of an odd number of CMOS biased inverters. Consecutive inverters are biased alternatively at V P and V N values (see Fig. 2.b) in order to achieve a strong non linear response which amplifies the positive half cycle of the incoming signal and saturates the negative half cycle (see Fig. 2.c). V P and V N bias values are set by the DBB and strongly impact the receiver sensitivity. As we can see in Fig. 2.c this detector architecture provides an additional gain.

D. Coherent Receiver Design

The coherent receiver original principle is exposed in [10] and its architecture, design details and key performances are detailed in [START_REF] Morche | Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision[END_REF]. In the implementation presented in this paper, the main modifications concern the LNA, the operating frequencies to comply with the IEEE802.15.4a/6 band plans and PRFs, and the interface with an external DBB.

E. Chip Layout

The RUBYLB chip was designed in CMOS130nm from STmicroelectronics. Its overall size is 20mm² with an active part size of 12mm². Its layout is shown on Fig. 3. It was assembled in a QFN88 package.

III. MEASUREMENT RESULTS

A. Transmitter Measurements

The transmitted pulse was acquired with an Agilent Series 90000 40Gsps Digital Sampling Oscilloscope (DSO) and then post-processed with Matlab TM to calculate its time and frequency domains characteristics (Fig. 4). The transmitter produces 1.52V peak to peak pulses with 4 GHz center frequency and 2.1GHz 10dB bandwidth. It is noted that the receiver performances presented in next sections were measured using an Anritsu MP1800A generator configured to produce a pulse shape with 15.6MHz PRF very close to the actual transmitter one. To further calculate the sensitivity, a Gaussian pulse with 10dB bandwidth of 2000MHz adequately approximates the transmitted pulse.

B. Non Coherent Rx Measurements

The sensitivity of the NC-Rx was measured using an oscilloscope triggered on the pulses emissions. An extraction of the statistics at the expected LVDS output pulse position provides a measurement of the detection and miss-detection rates, whereas the integral of LVDS high level crossings at all other positions provides the false alarm rate. The settings of the NC-Rx (V G , V T then V P and V N ) are adjusted so as to set the probability of false alarm near to 0% and the probability of good detection near to 100% with 0.1% tolerance. The voltage supply of the LNA was raised to 1.35V to achieve the expected gain and noise figure performances obtained in simulation. Once the other blocks of the receiver are activated, and especially the frequency synthesis, the level of internal noise due to clock couplings is a little degraded. The settings have been revisited accordingly but an acceptable penalty of 2dB on the receiver pulse detection sensitivity remains. The best settings together with the best obtained sensitivity are reported in TABLE I.

C. Coherent Rx Measurements

In the C-Rx, the frequency synthesis is composed of an 8GHz VCO which through a PLL and a quadrature divider-by-2 delivers the 4GHz LO to the first stage mixer and a 500MHz reference clock for the analog baseband, ADCs, external DBB and transmitter. The phase noise specification complies with the coherent reception at the lowest symbol rates in the IEEE802.15.6 standard. The supply voltage was raised to 1.3V to optimize the phase noise performance reported in TABLE II. . Next, the transfer function of the C-Rx was measured to characterize the receiver gain and bandwidth. The maximum in-band gain is tunable from 54dB to 66dB with around 4dB steps. Measurement of the gain in pulse mode gives 61dB with a ~600MHz 10dB bandwidth pulse compliant with IEEE802.15.6 and 57dB with a 2000MHz 10dB bandwidth pulse close to the transmitter one. Finally, the sensitivity was measured in pulse mode supposing perfect synchronization for the receiver and a BER target of 10 -3 for the 2-ary pulse position modulation (2-PPM) as used in IEEE802.15.4a/6 at the highest uncoded bit rate of 15.6Mbits/s. Fig. 6 shows the BER curves for a transmitter compliant with channel 2 of the standard. The processing gain obtained with a coherent integration over 7 pulses is about 8dB, close to the theoretical value of 8.5dB. The sensitivity measurements for the C-Rx are summarized in TABLE III. IV. provides the current consumption measured on the different supplies available on the test board. Expectations are met for the different blocks, except for the transmitter for which the trigger signal did not have the expected duty cycling (50% instead of a few %). The NC-Rx total consumption is about half the C-Rx one, which also justifies the choice for the dual front-end combination, providing fast bloc-level power up and power down is possible during frame reception.

IV. CONCLUSIONS AND FUTURE WORK

A fully functional dual front-end CMOS130nm transceiver aiming partial compliance with IEEE802.15.4a/6 standards was assembled and measured. The pulse detection sensitivity for the non-coherent receiver is -72dBm for a 33mA current consumption whereas the bit demodulation sensitivity of the coherent front-end is -84dBm at 15.6Mbits/s with 61.9mA drawn from the supply. Future works aim at interfacing the chip with the DBB in an FPGA and work on the acquisition speed, sensitivity, consumption tradeoffs.

Fig. 1 .

 1 Fig. 1. RUBYLB Overall Architecture

Fig. 2 .

 2 Fig. 2. Rectifier architecture and pulse detection principle

Fig. 3 .

 3 Fig. 3. Chip Layout

Fig. 4 .

 4 Fig. 4. Tx Pulse Shape in Time and Frequency Domains with spectrum masks for FCC, ECC (ETSI) and IEEE802.15.4a/6

Fig. 5 .

 5 Fig. 5. LVDS Output for the Non Coherent Rx

  Fig. 6. C-Rx BER curves for IEEE802.15.6 2-PPM and OOK modulations under perfect synchronisation

TABLE I

 I

	.	NC-RX PULSE DETECTION SENSITIVITY
		Nominal	Best settings	Best settings
		Settings @	@ 1.35V	with all blocks
		1.2V		active @ 1.35V
	VT (mV)	724.7	757	743
	VN (mV)	635.3	640	649
	VP (mV)	343.5	339	334
	VG (mV)	400	400	649
	Sensitivity (dBm)	-66	-72	-70

TABLE II

 II

	.	FREQUENCY SYNTHESIS PHASE NOISE AT 8GHZ
	Phase Noise	@ 10kHz	@ 100kHz	@ 1MHz	@ 10MHz
	(dBc/Hz)
	Expected	-74	-67	-87	-115
	Measured	-70	-67	-85	-104

TABLE III

 III

		.	C-RX BIT DEMODULATION SENSITIVITY
	Bit rate	RUBYLB Tx	MHz	IEEE802.15.6
		bandwith	bandwidth	channels bandwidth
	15.6 Mbits/s	-82 dBm	-84 dBm	-84 dBm
	2.23 Mbits/s	-89 dBm	-91 dBm	-92 dBm
	D. Current Consumption
	TABLE

TABLE IV

 IV

		.	RUBYLB CURRENT CONSUMPTION
	Regulator	Expected consumption	Measured consumption
			(@1.2V)(mA)	(@1.2V) (mA)
	LNA and NC Det.		28.1 (20.1 for LNA)	28.0 (@ 1.35V)
	Mixer, Integrators		17.1	14.4
	Digital, DIOs, Ring		6.7 (DIOs off)	8.5 (DIOs off)
	LVDS		6.0	5.0
	Frequ. Synthesis		16.2	17.9 (@1.3V)
	VCO		0.9	1.1
	TOTAL for full RX		75.0	74.9
	Total for NC-RX		34.1	33.0
	Total for C-RX		61.0	61.9
	TOTAL for TX		3.0 (@15.6MHz)	0.06 (no trig)
	(without PRF clock)			10.9 (continuous trig)

ACKNOWLEDGMENT

This work has been carried out within the French RUBY project and supported by the National Agency for Research (ANR). The authors thank H. Chougrani and J. Schwoerer from Orange Labs and F. Dehmas from CEA-Leti for their contribution to this work.


I Benamor

N Tall

N Dehaese

Jean Gaubert

Sylvain Bourdel

R Vauche

O Ramos Sparrow

S Meillère

A Fully Differential 7.2-8.5GHz LNA for a Self Synchronized and Duty-cycled UWB OOK Receiver

Keywords: UWB, impulse radio, IEEE 802.15.4a, Non-Coherent Detection, Low Power, High Voltage Gain

published or not. The documents may come

I. INTRODUCTION

Many applications such as Body Area Networks, Radio-Frequency IDentification (RFID), Wireless Sensor Networks or Biomedical Networks need Ultra Low Power (ULP) transceivers for the short or medium communication ranges and for low data rates. In Impulse-Radio Ultra-WideBand (IR-UWB), due to the short time duration of IR-UWB pulses, the receiver can be turned off between two received pulses. In [START_REF] Dokania | A Low Power Impulse Radio Design for Body-Area-Networks[END_REF] authors show that UWB impulse radios with aggressive dutycycling can strongly reduce the radio power consumption compared to Continuous Wave (CW) radios especially for low data rates and short communication ranges. Indeed many ULP Non Coherent UWB receivers have been published last years in the 3-5GHz low band of the UWB spectrum [START_REF] Dokania | A Low Power Impulse Radio Design for Body-Area-Networks[END_REF]- [START_REF] Vigraham | A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation[END_REF]. Recently, a self-synchronized and duty cycled UWB receiver implemented in a single chip for the 3-5 GHz UWB frequency band has been reported in [START_REF] Vigraham | A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation[END_REF].

In this paper we propose an ULP non coherent UWB receiver for the high band of the UWB spectrum. This paper focuses on the fully differential Low Noise Amplifier (LNA) of the receiver and its duty cycling ability. The transient response of the LNA including package parasitic effects is presented. The power consumption capabilities of the front-end receiver are analyzed in the particular case of a self synchronized and duty-cycled receiver working at 1Mbps data rate.

Section II presents the architecture of the high band selfsynchronized and duty-cycled On-Off Keying (OOK) UWB receiver. In section III a fully differential LNA architecture is presented with its fast power switching implementation. Section IV presents the post layout simulation results in realistic environment including package parasitic effects. Finally, in section V, the power consumption performance of the receiver is compared to the state of the art duty cycled UWB receivers.

II. RECEIVER ARCHITECTURE

Fig. 1 shows the block diagram of the non coherent receiver architecture. This paper focuses on the front end receiver (blocks in grey in Fig. 1). The 7.2-8.5 GHz fully differential LNA is duty-cycled by a power duty-cycling controller which provides the turn On/Off command (Vctrl) of the LNA synchronized with the incoming UWB pulses. The symbol frequency of 1 MHz is recovered by an analog Clock and Data Recovery (CDR) based on the design presented in [START_REF] Tall | Low-Power Clock and Data Recovery Circuit for IR-UWB Receiver Power Management[END_REF]. An asynchronous UWB pulse detector composed of a self mixing squarer, a low pass filter and a threshold detector directly follows the LNA output [START_REF] Sparrow | high rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF] and drives the CDR with a short duration 0-V DD OOK 3ns RZ signal. It is worth noting that the proposed architecture does not need any external frequency reference.

After a searching mode cycle where a "111..." pulse sequence allows the CDR synchronization, the LNA is dutycycled with a steady state turned-on duration T on . T on has to be set according to the peak to peak CDR jitter, the settling time of the LNA and the pulse duration. An overview of the ULP receiver signals and the power control signal during the steady state is presented in Fig. 2.

RFin

RX front end

III. LNA ARCHITECTURE AND POWER SWITCHING CIRCUIT

IMPLEMENTATION

The fully differential LNA presented in Fig. 3 includes three stages: a LC matched input stage which achieves the wide band matching to the antenna and two gain stages which provides an additional amount of voltage gain. A fully differential topology is selected because the common mode parasitic signal generated by the turn On/Off process is rejected at the LNA differential output which allows the LNA to have a fast turn On/Off time and enables aggressive duty-cycling.

A. Differential input matching cell

The input matching cell of the LNA is deduced from a standard differential LC ladder filter. Since the fractional bandwidth of the 7.2-8.5GHz is low (less than 17%), we have used a LC ladder filter implemented by means of capacitive admittance inverters [START_REF] Battista | High Voltage Gain CMOS LNA For 6-8.5 GHz UWB Receivers[END_REF]. The differential ended input matching cell is given in Fig. This topology gives inductor values which can be integrated with a standard CMOS process and with high self frequency resonance (SFR) value and a high Q factor within the LNA operating bandwidth. Such LC filter input matching cell achieves the wide band matching to the antenna, a broadband response with constant group delay in the bandwidth, a noise equivalent bandwidth limitation and an out of band signal rejection.

B. LNA first stage

The first gain stage of the LNA is shown in Fig. 3. It is implemented using a differential cascode architecture with a resonant LC load and inductive source degeneration. The sizing methodology and the noise figure and the voltage gain optimization strategy, similar to the ones used for the single ended architecture presented in [START_REF] Battista | High Voltage Gain CMOS LNA For 6-8.5 GHz UWB Receivers[END_REF].

A fast turn On/Off capability is obtained by applying the control command (Vctrl) at the gate of the cascode transistors (Mn3) and (Mn4). By using this technique, only the biasing current of the stage is modulated during the turn-on process while the potential of the outputs (Outp1, Outm1) remains nearly unchanged.

C. LNA second stage

The second stage is implemented using a differential cascode amplifier with resonant load as shown in Fig. 3. At the resonance frequency the voltage gain of the half circuit is given by (1) where g m5 , g m7 , g mb7 , r ds5 and R p represent respectively the transconductance of Mn5, the transconductance of Mn7, the back-gate transconductance of Mn7, the drain-source resistance (Mn5) and the parasitic resistance of the inductance L D2 [START_REF] Razavi | Design of Analog CMOS Integrated Circuits[END_REF]. The gain expression shows that to obtain a high voltage gain, a large transistor should be used which increases considerably the power consumption of this stage. Nevertheless, the power consumption can be reduced with the implementation of the power management solution.

+ = + + (1)
Similarly to the first stage the turn On/Off command (Vctrl) is applied at the gate of the cascode transistors (Mn7) and (Mn8). The second stage is AC coupled to the first stage but the voltage potential of the gates of the transistors (Mn5) and (Mn6) remains nearly unchanged during the turn On command, so the voltage at the terminals of the AC coupling capacitors is unchanged too. The inductive load allows the LNA to be DC-coupled to the pulse detector.

IV. POST LAYOUT SIMULATION RESULTS

The receiver has been implemented using a 130nm standard CMOS technology from ST-Microelectronics with a voltage supply of 1.2V. The circuit die, presented in Fig. 5, occupies a silicon area of 1.5mm 2 including the bonding pads.

The transient response of the LNA is strongly influenced in the presence of the parasitic inductance given by the bond wires. In addition large on chip decoupling capacitor values have been used to avoid common mode coupling between the different blocks of the receiver. The package technology was carefully chosen to minimize the turn On/Off time. The receiver is implemented with multiple supply voltage and ground pins to minimize oscillations during the turn On/Off process.

Fig. 6 presents the test chip used to evaluate the effect of parasitic elements given by the bond wires on the turn On/Off time. The value of the parasitic inductors on the supply voltage, the on-chip decoupling capacitors and the parasitic resistors are 3nH, 350pF and 1Ω respectively. The value of the parasitic inductor on the ground pins is 1nH. Fig. 7 and Fig. 8 show the results of AC (LNA loaded by detector) and S-parameters postlayout simulations. The frequency response of LNA stages is presented in Fig. 7. The LNA achieves a voltage gain of 40 dB in 7.2-8.5 GHz frequency bandwidth within a minimum noise figure of 3.2dB. The return loss, S11, is low than -10 dB within all the bandwidth. To evaluate the turn-On/Off time, the control command is applied while a continuous wave at the center frequency of the LNA bandwidth (7.9GHz) is applied to the LNA input. Fig. 9 shows the control command signal of the LNA (Vctrl) generated at the power duty-cycling controller with the LNA differential output voltage. As shown in Fig. 9. The LNA output voltage is settled within 3ns.

The whole receiver transient response has been simulated using the circuit environment described in Fig. 6. The transient response of the receiver is presented in Fig. 10. Fig. 10 shows one period of the control command (Vctrl). A pulse signal with a peak amplitude of 400µV is applied at the LNA input. When the LNA is turned On and Off, glitches are generated at LNA outputs. The amplitude of the glitches is strongly reduced at the LNA differential output. Since the pulse detector is also sensitive to the common mode, these glitches lead to spurious detections that increase the on time duration Ton. In Fig. 10 the first response observed at the detector output is due to the turn On process of the LNA. Indeed, the UWB signal must be sent with a delay margin of 5ns to avoid false detections. A logical function has been implemented at receiver output (Out_RX) to eliminate these false detections.

V. POWER CONSUMPTION PERFORMANCE OF THE RECEIVER

The receiver power consumption P Rx is calculated according to equation ( 2). The turned-on time duration T ON is given in (3) where t ON-RFfunctions , τ and t synch represent respectively the turn on time (equal to 5ns in our case), the pulse duration (~2ns) and the synchronization uncertainty. The LNA is synchronized and duty-cycled with an analog CDR [START_REF] Tall | Low-Power Clock and Data Recovery Circuit for IR-UWB Receiver Power Management[END_REF] which presents a 23ns peak to peak jitter. The static and leakage power of the LNA are respectively 49.2mW and 36µW. The low power detector and the CDR are always on and consume respectively 216 µW and 16 µW.

Table I compares the simulated performance of the proposed receiver with state of the art duty-cycled UWB receivers. The proposed receiver consumes 49.5 mW when continuously turned-on in the searching mode. Indeed, it is implemented to meet the needs of the UWB high band for IEEE 802.15.4a standard with 130 nm CMOS process. After synchronization, in the locked mode with self duty-cycling active, the RX consumes only 1.95 mW at 1 Mbps OOK data rate. Although operating in the high band, the power consumption performance of the proposed receiver in the duty cycled mode is quite good, approaching the power consumption performance of low band receivers which are self-synchronized and duty cycled.

VI. CONCLUSION

In this paper a fully differential LNA for a self synchronized and duty-cycled receiver for the 7.2-8.5GHz bandwidth of the IEEE 802.15.4a standard is proposed. The LNA achieves a flat and high gain of about 40dB in the desired bandwidth. Post layout simulations taking into account the parasitic effects of the package show that the LNA output voltage is settled within 3ns. When synchronized and duty cycled with an analog CDR with 23ns peak to peak jitter the receiver consumes 1.95mW at 1Mbps data rate.

Fig. 1 Fig. 2

 12 Fig.1Self synchronized and duty-cycled receiver architecture.

Fig. 3

 3 Fig.3LNA transistor level implementation.

Fig. 4

 4 Fig. 4 Fully differential input matching cell: (a) Normalized (by R0=50Ω and ω0) differential LC ladder filter with capacitive admittance inverters, (b) Normalized input matching cell. (c) Input matching cell implementation.

Fig. 5 Fig. 6

 56 Fig. 5 Layout of the receiver in 130 nm CMOS Process.

  Fig. 7 LNA voltage gain with the frequency response of each stage.

Fig. 8

 8 Fig.8The return loss S11 and the noise figure.

Fig. 9 Fig. 10

 910 Fig. 9 Post layout simulated LNA differential output voltage.


R Vauche

S Bourdel

J Gaubert

N Dehaese

H Barthelemy

Emitters and Receivers for Impulse Radio Ultra-WideBand and Their Healthcare Applications

Keywords: Healthcare Applications, Impulse Radio, Power Gating, Data Rate Management, UWB, Transceiver

Healthcare applications requirements are presented in this paper and a state-of-the-art analysis shows that Impulse Radio Ultra-WideBand (IR-UWB) is particularly suitable in terms of energy efficiency for this type of short range communications for which different data rates are needed. Power saving strategies for emitters and receivers are then discussed and three examples of implementations are presented with their measurement results. The first is a versatile transmitter with tunable bandwidth which exhibits 0.9Vpp pulses and a power consumption of at least 11.03mW at 50Mbps. The second is a 3.1-10.6GHz transmitter with a power management scheme implemented on-chip which exhibits 2Vpp pulses and a power consumption of 7.3µW at 100kbps and 3.4mW at 100Mbps. The last is a non-coherent 3-5GHz receiver with -89dBm sensitivity at 100kbps and 144pJ/bit energy consumption when used in a power gated 100Mbps burst mode.

I. INTRODUCTION

Modern biomedical monitoring or stimulation systems use wireless communications to avoid the use of wires which is uncomfortable for the patient and the medical workers, and reduces the reliability of the overall system. The needs in biomedical application are very specific and depend on the monitored parameters or the stimulated parts [START_REF] Widya | Telematic Requirements for a Mobile and Wireless Healthcare System derived from Enterprise Models[END_REF][2] [START_REF] Suzuki | Super multi-channel recording systems with UWB wireless transmitter for BMI[END_REF]. As presented in TABLE I. , physiological monitoring needs low or medium data rates and can be realized with an unidirectional link, whereas next generation of brain machine interfaces needs a large number of interconnections which leads to high data rates up to 100Mbps [START_REF] Suzuki | Super multi-channel recording systems with UWB wireless transmitter for BMI[END_REF]. Concerning the power consumption, the needs are also very widespread since the transmitter life can vary from few hours for ElectroCardioGraphy (ECG) to few years when in-body stimulation systems are considered. The communication range appears to be the most relaxed constraint since the on-body or in-body transmitters are close to the receiver which can consist of a simple hub that concentrates the data and sends it to a remote monitoring system.

Due to this large variety of needs, several wireless technologies have been used to implement biomedical monitoring and stimulation systems as: i) High Frequency Radio Frequency IDentification (HF-RFID; 13.56MHz) [START_REF] Xiao | An Implantable RFID Sensor Tag toward Continuous Glucose Monitoring[END_REF] [START_REF] Ahmadi | A Wireless-Implantable Microsystem for Continuous Blood Glucose Monitoring[END_REF], ii) Ultra-High Frequency RFID (UHF-RFID; 900MHz) [START_REF] Nazari | An implantable continuous glucose monitoring microsystem in 0.18µm CMOS[END_REF] [START_REF] Radiom | Far-field RF powering system for RFID and implantable devices with monolithically integrated on-chip antenna[END_REF], iii) 400MHz Narrow Band (400MHz-NB) [START_REF] Nezhad-Ahmadi | A 2mW 400MHz RF transceiver SoC in 0.18um CMOS technology for wireless medical applications[END_REF] [START_REF] Carrara | A 400-MHz CMOS radio front-end for ultra low-power medical implantable applications[END_REF][10], iv) 2.45GHz-NB [START_REF] Vidojkovic | A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications[END_REF] [START_REF] Devita | A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications[END_REF] [START_REF]nRF51822 SoC for Bluetooth low energy and 2.4GHz ultra low-power wireless applications[END_REF], and v) Impulse Radio Ultra-WideBand (IR-UWB) [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF][15] [START_REF] Soldà | A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13µm CMOS[END_REF]. The most encountered systems are based on HF-RFID and 400MHz-NB technologies which are the most mature. Moreover, biomedical standards have been specified for the 400MHz-NB whereas HF-RFID is quite attractive since remotely powered transponders can be achieved with commercial off the shelf RFID devices. However, 2.45GHz-NB systems are recently emerging essentially due to the growth of Bluetooth Low Energy (BLE) [START_REF] Devita | A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications[END_REF][13] and the ease of interconnecting the transponder with standardized systems.

In the field of biomedical applications, IR-UWB appears first to be a new comer since it seems to offer a large number of advantages such as low power consumptions, high data rates or low radiated power which allows IR-UWB to comply with Specific Absorption Rate (SAR) specifications [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF]. As shown in Fig. 1 which compares four essential performances of a wireless link (ie. range, data rate, TX and RX energy efficiency in bit/nJ equals to the data rate divided by TX and RX power consumption), NB technologies are the best suited to achieve long range and data rates around 1Mbps. RFID systems appears to be the best suited when ultra-low power is needed since it can operate without battery but it fails to achieve medium or high data rates and are quite limited in terms of range (lower than 1m for HF-RFID systems). IR-UWB is a technology that allows both high and low data rates communications at low power. This is due to the ease of duty cycling transceivers which allows the energy efficiency to be always maximized. However, IR-UWB can only achieve short range communications when non-coherent receivers are used but this is not critical for the considered applications. This paper is organized as follows. Section II deals with power saving strategies for IR-UWB emitters and receivers, and provides design considerations and power management schemes. In section III, prototypes of two emitters and of one receiver are presented with their measurement results and their expected power saving abilities.

II. POWER SAVING STRATEGIES IN IR-UWB

IR-UWB systems use pulse modulations to transmit data and the emitted symbols can also be coded by the presence or the absence of a particular pulse at a particular time. Since pulses duration (few ns) in UWB is generally short compared to the mean Pulse Repetition Period (PRPMEAN), the power consumed by an IR-UWB emitter (resp. receiver) can be considered equal to a constant power PDC when no pulse is emitted (resp. received). Otherwise, an extra energy EAC is consumed when a pulse has to be emitted (resp. received). In IR-UWB, it is also possible to write the power consumption PC as follows:

C DC AC MEAN P P E PRF = +  ()
where PRFMEAN is the mean Pulse Repetition Frequency (PRF).

A. Pulse Modulation Choice

The dynamic part PAC of the power consumption PC can be written as a function of the bit rate Db (bit/s) as follows:

/ AC AC MEAN AC b P E PRF E D N =  =  ()
where N is the mean number of bits convoyed by pulse which depends on the modulation used. To reduce the PAC, a tradeoff must be done. On the TX side, the higher N is and the lower the PAC is. On the RX side, a high N increases the complexity and reduces the PAC. Thus, On-Off Keying (OOK) type modulations (N = 2) is a good compromise and can be demodulated with simple non-coherent receivers whose power consumption is less than the coherent receivers [START_REF] Morche | Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision[END_REF]. Moreover, standard OOK can be replaced by the Randomly Alternate OOK (RA-OOK) defined in [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF] which allows the authorized bit rate and/or range to be increased compared to BPSK at the same mean Equivalent Isotropically Radiated Power (EIRP) thanks to the properties of pulse modulations [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF].

B. Design Considerations for IR-UWB emitters

In IR-UWB, emitters are based on pulse generators which emit a pulse according to their control inputs when an active edge is provided on their trigger input. However, the pulse generator inputs need to be controlled with the help of a baseband manager in order to implement pulse modulations. For usual Pulse Amplitude Modulations (PAM) as OOK, the baseband manager requires only CLOCK and DATA digital inputs to provide the input signals needed by the pulse generator and its required trigger signal.

By using the following definition of the emitted power PE:

E P MEAN P E PRF = ()
where EP is the emitted energy by each pulse, it is possible to defined the power efficiency P of an IR-UWB emitter as follows:

P MEAN E P C DC AC MEAN E PRF P P P E PRF   == + . ()
When this equation is differentiated with respect to PRFMEAN, it appears that the power efficiency remains constant and maximized regardless of PRFMEAN if PDC is null. Thus, to optimize the power efficiency of an IR-UWB emitter, it is necessary to minimize PDC by using functions for which most of the power consumption is dynamic and depends on the number of switching per second as CMOS logic gates, or by using fast on/off switchable architectures [START_REF] Vauche | High efficiency UWB pulse generator for ultra-low-power applications[END_REF] which can be easily implemented since pulse generation times are known from the pulse generator point of view on contrary to the receiver side. However, it exists a particular value of PRFMEAN for which PDC can be considered negligible compared to PAC without the use of power saving methods. Depending on the bit rate needs, it is critical to reduce the PDC for energy efficiency optimization. Thus, for low rate applications, this parameter is the most limiting as far as the power consumption is concerned.

To illustrate this subsection, the design of an all-digital pulse generator, where different logic families can be used as CMOS logic or Current Mode Logic (CML), is considered. In the first case, the main component of the power consumption is PAC and to improve power efficiency it is necessary to implement leakage reduction techniques to decrease PDC [START_REF] Vauche | High efficiency UWB pulse generator for ultra-low-power applications[END_REF], whereas in the second case the main part comes from PDC. However, in this case, it is easy to change the power sharing between PDC and PAC by switching on/off CML gates by disabling their current sources [START_REF] Vauche | Ultra-WideBand Voltage Controlled Oscillator with Commutable Phases for BPSK Implementation[END_REF] with the help of the baseband manager since pulse generation times are known.

C. Power Management Schemes of IR-UWB receivers

Low-power consumption can be achieved for both NB and UWB receivers by using very simple architectures. Such architectures operate with OOK modulation scheme in noncoherent receivers when an envelope detector can be used for the demodulation of the encoded data. By using this technic, low power consumption can be achieved for the RF front end at the cost of sensitivity degradation. In [START_REF] Pletcher | A 52uW wake-up receiver with -72 dBm sensitivity using an uncertain-IF architecture[END_REF], a NB receiver is presented with 54µW power consumption at 100kbps data rate with -72dBm sensitivity. An example of usual non-coherent IR-UWB receiver is shown in Fig. 2 and Fig. 3. The circuit is composed of a Low Noise Amplifier (LNA) and an OOK pulse detector. Non-coherent IR-UWB receivers can also achieve low power consumption at low and medium data rate by duty cycling RF front end blocks between two received symbols. [START_REF] Lee | A 2.5 nJ/bit 0.65V Pulsed UWB Receiver in 90 nm CMOS[END_REF][22] [START_REF] Vigraham | A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation[END_REF] give some examples of duty cycled UWB receivers where microwatt range power consumptions are achieved for low and medium data rates.

Typical architecture of a self-synchronized and duty cycled receiver is given in Fig. 2. A duty cycled operation at the pulse scale which is used here needs the synchronization of the receiver with the emitter. This operation can be achieved by a Clock and Data Recovery (CDR) which can be implemented with low power consumption [START_REF] Lee | A 2.5 nJ/bit 0.65V Pulsed UWB Receiver in 90 nm CMOS[END_REF] [START_REF] Dokania | An Ultralow-Power Dual-Band UWB Impulse Radio[END_REF]. However, an acquisition mode time slot, where the RX is always on while receiving a synchronization frame, is necessary. This acquisition mode, which has duration greater than several tens of bits [START_REF] Lee | A 2.5 nJ/bit 0.65V Pulsed UWB Receiver in 90 nm CMOS[END_REF], degrades the power consumption efficiency especially when a short amount of data has to be sent. After the acquisition mode cycle, the LNA is duty-cycled with a steady state on time duration Ton. Ton has to be set according to the peak to peak CDR jitter, the settling time of the RF front end blocks, and the pulse duration. The settling time of the RF front end blocks is typically around few nanoseconds, while the CDR jitter depends on the symbol rate and is typically equal to tens of nanoseconds at 1Msps. In [START_REF] Lee | A 2.5 nJ/bit 0.65V Pulsed UWB Receiver in 90 nm CMOS[END_REF], a self-synchronized and duty cycled UWB receiver exhibits 750µW power consumption for the entire receiver at 2Mbps data rate with -76.5dBm sensitivity.

To avoid the long acquisition mode time slot a duty cycle operation at the frame scale can be used instead of duty cycle operation at the pulse scale. The sequence of regularly spaced pulses is replaced by bursts giving the same mean data rate. To avoid changes in the mean EIRP, PRFMEAN must be kept constant during 1ms which is the spectrum analyzer sweep time imposed by Federal Communications Commission (FCC) to measure the mean EIRP. The maximal burst duration is then given by:   ms 1ms 1ms

MEAN BURST BURST BURST PRF T PRF  =  =  ()
and the receiver can be turned off during:

    ms 1ms ms

IDLE BURST T T = - ()
By using PRFBURST much greater than PRFMEAN, the frame scale duty cycling ratio BURST is low and a great improvement in the power consumption can be achieved with relaxed synchronization constraints. The receiver does not also need a CDR and its associated acquisition time slot, since its output (data out) can be sampled and stored in a memory sized according to TBURST and PRFBURST, and demodulated during TIDLE. Obviously, this communication scheme is only practicable for low and medium mean data rates since the instantaneous data rate is increased. Such frame scale duty cycled receiver architecture is depicted in Fig. 3. The synchronization between the burst position and the turn on command has relaxed constraints and can be achieved by a low power microcontroller where the clock could be synchronized with other clocks of the network using standard synchronized networks protocols or by using an ultra-low power wake up triggering protocol which is out of the scope of this paper.

III. EXAMPLES OF MEASURED PROTOTYPES

To illustrate the proposed power saving strategies for IR-UWB, two emitters and one receiver are presented. They have been designed using the 130nm CMOS technology from STMicroelectronics and measured under a supply voltage of 1.2V.

A. Versatile IR-UWB emitter

A versatile transmitter with tunable bandwidth has been proposed in [START_REF] Vauche | Fully tunable UWB pulse generator with zero DC power consumption[END_REF]. This pulse generator uses elementary pulse combination method which allows an arbitrary pulse to be synthesized according to the targeted bandwidth. As shown in Fig. 4, it is constituted of an elementary pulses generator using a CMOS Voltage Controlled Delay Line (VCDL) and a combination circuit using multiple parallel H-bridges. Its core area is 0.25x0.45mm 2 and its die area is 0.6x1.3mm 2 . From measurement results, it is able to generate pulses composed of 1 to 8 elementary pulses with a central frequency between 2.35GHz and 5.55GHz. When it is programmed to generate a 3-5GHz pulse, it achieves 0.9Vpp pulse which leads to an energy emitted by pulse EP of 2.08pJ on a 100Ω differential load. In the worst case (when all elementary pulses are set to their maximum values), PDC is equal to 0.58mW and EAC is equal to 209pJ/pulse. As CMOS logic has been only used, PDC is only due to high leakage currents since MOS transistors have been designed large enough to achieve very fast pulses. To stay energy efficient for low data rate applications, leakage reduction methods are required but not implemented here. For high data rate application the maximum energy efficiency is close to 4.78bit/nJ whereas it falls to 0.17bit/nJ@100kbps. B. Ultra low-power 3.1-10.6GHz emitter To reach energy-efficient IR-UWB transmitter for low bit rates and high bit rates, a pulse generator based on filter excitation technique has been presented in [START_REF] Vauche | High efficiency UWB pulse generator for ultra-low-power applications[END_REF]. As shown in Fig. 5, this method requires the generation of a baseband pulse which is filtered by a band-pass filter. The baseband pulse generator is constituted of a CMOS VCDL and the band-pass filter is a 3.1-10.6GHz third order Bessel filter. To reduce the static part of the power consumption and also the leakage currents, an on/off system which uses low leakage MOS transistors has been designed to supply the baseband pulse generator using high speed MOS transistors. The measured pulse generator has a die area of 0.7x0.8mm² and exhibits 2Vpp pulses centered at 6.3GHz with a 10dB bandwidth of 5.2GHz, which leads to an energy emitted by pulse of 2.15pJ on a 50Ω load. From measurement, PDC is equal to 3.91µW and EAC is equal to 68pJ/pulse which gives a power consumption of 7.3µW at 100kbps and 3.4mW at 100Mbps for an OOK modulation. This leads to a maximum energy efficiency of 14.7bit/nJ when high data rate applications are targeted and an energy efficiency of 13.7bit/nJ@100kbps.

C. 3-5GHz IR-UWB Front End receiver

In [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF], a low power 3-5GHz IR-UWB receiver front-end for WBAN and biomedical applications is proposed. This noncoherent receiver is designed for OOK signaling and uses very simple front end architecture, such as depicted in Fig. 2 and Fig. 3, based on a high gain LC filter LNA followed by a pulse detector composed of a self-mixing squarer, a low pas filter and a threshold detector. This asynchronous front end receiver does not need any external frequency reference. The LC filter LNA provides a second order band pass response helpful for unwanted signals rejection. Since self-mixing squarer conversion gain drops drastically at low input levels, the LNA must provide enough gain to allow the signal to be higher than the noise floor of the following stages at the targeted maximum communication range. For this purpose the voltage gain of the LNA has been maximized resulting in a high power consumption which represents the main contribution of the whole front end receiver consumption. Fig. 6 shows the microphotograph of the die. A summary of the front end receiver performance is given in TABLE II. . RX energy consumption @ maximum data rate 144pJ@100Mbps RX energy efficiency 6.94bit/nJ@100Mbps 0.007bit/nJ@100kbps RX sensitivity@BER=10 -3 -59.3dBm@100Mbps -89.3dBm@100kbps RX minimum consumption in burst mode for TBURST=1us, TFRAME=1ms 50.4µW@100kbps RX energy efficiency in burst mode for TBURST=1us, TFRAME=1ms 1.98bit/nJ@100kbps

The receiver sensitivity is -89.3dBm@100kbps. The receiver power consumption is 14.4mW at the maximum data rate of 100Mbps and shows an energy efficiency of 6.94bit/nJ@100Mbps which falls to 0.007bit/nJ@100kbps. This front end has not been designed to allow pulse scale duty cycling which requires nanosecond scale Ton time and it is also not possible to optimize the energy efficiency easily. However, it can be easily used with a burst frame duty cycling such as described in Fig. 3. In this case, the receiver could consume only 50.4µW at 100kbps mean data rate which leads to an energy efficiency of 1.98bit/nJ if turn on/off times are considered instantaneous with TBURST equals to 1us, PRFBURST equals to 100Mbps, and TIDLE equals to 999us. The total frame period is also set to 1ms to comply with the FCC requirements for EIRP measurement.

IV. CONLUSION

Due to the gated nature of IR-UWB communications, it appears that the higher the data rate is, the more energyefficient IR-UWB emitters and receiver are. IR-UWB is intrinsically well-suited for short range healthcare applications when high data rate are required. However, many healthcare applications require low data rate applications. It is then feasible to drastically reduce the static part of the power consumption to achieve an energy efficiency closed to its maximum. To do so, some design strategies for emitters and power management schemes for receivers have been proposed and their efficiency is demonstrated on existing circuits.

Fig. 1 .

 1 Fig. 1. Wiresless technologies comparison from averaged results of previous published works (HF-RFID: [4][5], 400MHz-NB: [8][9][10], UHF-RFID: [6][7], 2.45GHz-NB: [11][12][13], IR-UWB: [14][15][16]).

Fig. 2 .Fig. 3 .

 23 Fig. 2. Self synchronized and duty-cycled receiver architecture.

Fig. 4 .Fig. 5 .Fig. 6 .

 456 Fig. 4. Architecture (a) and die photography (b) of the versatile transmitter.

TABLE I .

 I TECHNICAL REQUIREMENTS FOR BIOMEDICAL APPLICATIONS

			Sample	Sampling	Bit
	Application	Location	Size	Frequency	Rate
			(bit)	(Hz)	(bps)
	Oxygen Saturation,
	Blood Pressure,	On-body
	Body Temperature		16	1/3600	4.4m
	Drug Dosage, Glucose Monitoring	In-body
	Heart Beat Rate	On-body	8	1	8
	ElectroCardioGraphy a (ECG)	On-body	12	250	3k
	ElectroMyoGraphy (EMG)	On-body	16	4k	64k
	Hearing Aid	On-body	16	22.05k	200k
	Deep Brain Stimulation	In-body	-	-	1M
	Capsule Endoscopy b	In-body	307.2k	6	1.8M
	Brain Machine Interface	In-body	-	-	>10M

a. For one channel only.

b. Resolution of 320x320.

TABLE II .

 II SUMMARY OF 3-5GHZ UWB-IR RECEIVER PERFORMANCE

	Parameters	Values
	Die Area	1.43mm 2
	Bandwidth	3-5GHz
	LNA : Voltage gain || Noise figure	35.3dB+/-0.2dB || 3.8-5dB
	RX power consumption: Always On || Always off	14.4mW || 36µW


R Vauche

E Muhr

N Tall

A Haloua

S Bourdel

J Gaubert

N Dehaese

H Barthelemy

Ultra-WideBand Voltage Controlled Oscillator with Commutable Phases for BPSK Implementation

Keywords: BPSK, CML, Impulse Radio, Phase Switching, Power Gating, UWB, VCO

An ultra-wideband Voltage Controlled Oscillator (VCO) is presented in this paper. The circuit achieves fast startups and stops which allow wideband pulses to be generated. In addition, the VCO allows bipolar modulations as Binary Phase Shift Keying to be implemented without the need of a shaping circuit as a mixer. The proposed VCO has been integrated on a silicon area of 0.003mm 2 in a 65nm CMOS technology operating with a supply voltage of 1.2V. The oscillator output provides large differential oscillations from 2.6GHz to 12.3GHz. Measurement has demonstrated the frequency agility of the proposed VCO which covers the mandatory channels of the low (resp. high) bands centered on 4492.8MHz (resp. 7987.2MHz) defined by the IEEE 802.15.4 standard. The VCO power consumption is about 3.2mW/GHz. By using Current Mode Logic (CML) gates, the power consumption can be reduced to 3.84uW only when the VCO is not running (switch off).

I. INTRODUCTION

Since 2002, the Federal Communications Commission (FCC) released the frequency band 3.1-10.6GHz called Ultra-Wide Band (UWB) [START_REF] Barthelemy | Code of Federal Regulations[END_REF], but did not specify communication mode. So, it is possible to take advantage of the UWB bandwidth by using Impulse Radio (IR) instead of conventional carrier modulations. This allows emitters with low power consumption to be designed and gives the possibility to power down most functions between the transmission of two pulses [START_REF] Dokania | A 6µW, 100Kbps, 3-5GHz, UWB impulse radio transmitter[END_REF] [START_REF] Vauche | A remotely UHF powered UWB transmitter for high precision localization of RFID tag[END_REF].

Following this, different standards using the UWB band have emerged as the IEEE 802.15.4 standard [START_REF]Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs)[END_REF] which made the choice to cut the UWB into several channels whose bandwidth is between 500 MHz and 1.35GHz. However, two channels located around 4.5GHz and 8GHz must be covered to be compliant with this standard which implies a certain agility on behalf transmitters and receivers.

To implement modulations used by UWB-IR, three architectures of pulse generators are commonly integrated in emitters. The first uses pulse generators based on impulse filter response which has low power consumption but having quasi no tunable frequency responses [START_REF] Vauche | A remotely UHF powered UWB transmitter for high precision localization of RFID tag[END_REF]. The second uses pulse synthesizers which provide highly tunable frequency responses but are complex to implement [START_REF] Norimatsu | A UWB-IR transmitter with digitally controlled pulse generator[END_REF]. Finally, the last uses switched oscillators which allows a limited number of IEEE 802.15.4 channels to be addressed by their available oscillation frequency ranges [START_REF] Phan | Energy-efficient low-complexity CMOS pulse generator for multiband UWB impulse radio[END_REF] [START_REF] Xu | Power-Efficient Switching-Based CMOS UWB Transmitters for UWB Communications and Radar Systems[END_REF]. Moreover, their startup and stop durations are not always short enough to make generated oscillations compliant with spectrum masks defined by the IEEE 802.15.4 standard. In this case, a mixer is required to shape the generated oscillations [START_REF] Wentzloff | Gaussian pulse generators for subbanded ultra-wideband transmitters[END_REF] since the width of frequency response is inversely proportional to the pulse duration. It allows an up-conversion of the baseband pulse; and the derivate UWB pulse-generator architecture is, similar to a classic modulator that permits the On-Off Keying (OOK) modulation or the Binary Phase Shift Keying (BPSK) modulation.

Furthermore, in UWB-IR communications, it is important to be able to implement bipolar modulations as BPSK or Randomly Alternate OOK (RA-OOK) [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF]. Indeed, for this type of communications, the Power Spectrum Density (PSD) is composed of two parts proportional to the energy emitted per symbol which are named here continuous and discontinuous spectrum [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF]. Since the discontinuous spectrum dominates the continuous spectrum for high bit rates, and since it is proportional to the mean value of emitted symbols, the use of bipolar modulations increases the maximum allowed bit rates compared to OOK modulation at the same energy emitted per symbol [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF]. By contrast, it is possible to increase the energy emitted per symbol and also the communication range for a fixed bit rate.

A differential Voltage Controlled Oscillator (VCO) with a sufficient frequency range for IEEE 802.15.4 standard is presented in this paper. It achieves fast startups and stops and also does not require a mixer to shape oscillations. Moreover, the positive and the negative paths of its differential voltage output can be switched around and allows also bipolar modulations as BPSK to be implemented. Thus, it can be used for UWB-IR communications as well as conventional carried modulations. Finally, it can be powered down between the emissions of two consecutive pulses where it consumes only 3.84uW. This paper is organized as follows. Section II deals with UWB-IR emitters based on switched oscillators. In this section, a pulse model is provided and allows the adequate pulse width to be computed as a function of the targeted spectrum mask. Section III presents the architecture of the proposed VCO designed with a 65nm design kit. In section IV, simulation results demonstrate its frequency agility while measurement results show its compliancy with the IEEE 802.15.4 standard.

II. UWB-IR EMITTERS BASED ON SWITCHED OSCILLATORS

A. Architecture of switched oscillators

As shown in Fig. 1, UWB-IR emitters based on switched oscillators use an oscillator whose duration τ P (resp. the frequency f M ) of the gated oscillations determines the bandwidth (resp. the central frequency) of the emitted pulse in frequency domain. To allow the oscillator to be loaded by the antenna, a driver stage is necessary between the oscillator and the antenna. The design of the driver stage between the oscillator and the antenna is not discussed in this paper.

To obtain a compliant pulse with a given spectrum mask, a switched oscillator must have a frequency control, and a startup and stop command. In Fig. 1, the oscillation frequency f M is selected by the control voltage VCTRL and the pulse duration τ P is set by the time during which the ON signal is active.

Considering a Pulse Amplitude Modulation (PAM), the signal emitted by the antenna s(t) can be written as a sequence of pulses as follows:

0 ( ) ( ) k S k s t d p t k T +∞ = = ⋅ -⋅ ∑ (1)
.

where d k is the k th emitted symbol, T S is equal to the multiplicative inverse of the symbol rate, and p(t) is the waveform of the generated pulse.

B. Model of pulse generated by switched oscillators

By supposing a sinusoidal switched oscillator, the pulse shape p(t) can also be expressed as follows:

( ) ( )

sin 2 2 P P M p t A f t t τ τ π   = ⋅ ⋅ Π -     (2)
.

which allows the duration τ P to be estimated when a particular frequency mask is targeted. In (2), A is the peak voltage of generated pulse and Π τ (t), the rectangular function equals to 1 within [-τ/2 ;τ/2] interval and 0 outside. τ P can also be written as a function of the frequency f M by: 2

P M N f τ = (3) .
where N is the number of sinus half-periods of the generated pulse. Thus, the modulus value |P(f)| of the p(t) mono-lateral Fourier transform can be computed and is given by: ( ) ( )

sinc 2 P M P A P f f f τ π τ ⋅   = -   (4)
For impulse modulations, by considering that the emitted power spectrum density is directly linked to the square of |P(f)| [START_REF] Sparrow | High rate UWB CMOS transceiver chipset for WBAN and biomedical applications[END_REF], it is possible to compute the number N of half-periods as a function of the bandwidth BW -XdB defined as follows:

( )

2 2 10 log 10 log 2 XdB M M BW XdB P f P f -   = - +     . ( 5
)
This allows the minimum value of N to be estimated by solving:

2 10 log sinc 2

XdB P BW XdB π τ -     ≤ -         (6)
which gives:

min M XdB f N BW α - = (7)
where α is a scalar equals to 1.8 (resp. 3 and 10.1) when an attenuation XdB equals to 3dB (resp. 10dB and 18dB) is considered.

From (3) and ( 7), the minimum value of the pulse duration τ P , that is only BW -XdB dependent, can also be computed by:

min 2 P XdB BW α τ - - = (8)
and allows the energy emitted per pulse to be estimated by:

2 2 P P A A E Z τ = ( 9
)
where Z A is the antenna impedance.

III. ARCHITECTURE OF THE DESIGNED VCO

The proposed oscillator is based on a conventional ring oscillator for which one of its stage is replaced by a NAND logic gate as shown in Fig. 2. This allows the oscillation duration to be controlled by the ON signal applied to the free input introduced by the NAND gate. Thus, when ON is active, the NAND gate has the same logic equation as an inverter between the 120° input and the 0° output. This makes the system unstable and capable of oscillating. By contrast, when ON is inactive, the NAND gate imposes a logic state on its output which is independent of the 120° signal. In this case, the system becomes stable and cannot oscillate.

Here, to avoid oscillations frequency shift when one of its outputs is loaded by an additional element as a mixer or an antenna, it is necessary to add an output buffer. Moreover, to ensure optimal oscillation conditions, each stage must have the same electrical characteristics; so it is necessary to add an identical buffer on the other outputs too.

A. Design of the three stages ring oscillator

The proposed 3-Stages VCO is shown in Fig. 3. To obtain large oscillations with a frequency range wide enough to address the mandatory channels of the IEEE 802.15.4a standard, a Current Mode Logic (CML) is used for each stage of the proposed ring oscillator. In Fig. 3, VCTRL controls the oscillations frequency f M , and the complementary ON input is used to fix the duration of oscillations τ P . The complementary DATA input allows the positive and negative paths of the differential OUTVCO output to be commuted (OUTVCO+ becomes OUTVCO-and OUTVCO-becomes OUTVCO+). The EN input enables the standby mode (switch off) when it is reset.

B. Design of one stage used in the ring oscillator

One of the 3 identical stages of the proposed VCO in Fig. 3 is shown in Fig. 4. Each stage is constituted of two CML gates, a tunable delay cell (a) and an output buffer (b). These two gates are based on the same CML XOR gate which has the advantages to be strictly balanced and to be powered down when EN is inactive.

Considering the tunable delay cell (a), the input wiring has been modified compared to the classical XOR gate in order to have a similar logic function as the NAND gate shown on Fig. 2. Consequently, when S is active, the tunable delay cell works as an inverter and when S is inactive, complementary logic states are provided on its differential output. To obtain the designed ring oscillator, two stages (stages 2 and 3 according to Fig. 3) are used in inverter mode by keeping S active whereas the last stage (stage 1 according to Fig. 3) is able to be in the two modes according to the state of ON. Thus, even if each stage operates different logic equations, all the stages remain similar from an electrical point of view; consequently optimal oscillation conditions are reached.

Considering the buffer (b), the wiring has not been modified since the gate is used to implement bipolar modulations thanks to the logic equation of the XOR gate. Thus, according to the state of the complementary SB input, it is possible to logically connect OUT (resp. OUT\) to OUTB or OUTB\ (resp. OUTB\ or OUTB). It also works as an inverter or a follower and then allows bipolar modulations as BPSK to be implemented.

For the tunable delay cell (a) and the buffer (b), the VCTRL input modifies the biasing of active loads which allows the delay and also the oscillations frequency to be tuned (a), and sinusoidal waveform to be kept at the OUTVCO output of the oscillator (b).

IV. SIMULATION AND MEASUREMENT RESULTS

The proposed oscillator has been simulated and realized using the 65nm CMOS design kit from STMicroelectronics under a supply voltage of 1.2V. The VCO die area is about 35µm by 78µm and its layout is shown in Fig. 5. Here, all the connections have been made to ensure that each stage is similar to the others from an electrical point of view.

In Fig. 6, pulses, designed in frequency domain to have a bandwidth BW -10dB (α=3) equals to 500MHz and centered on 4.5GHz (a) and 8GHz (b), have been generated in post-layout simulations where the buffered differential output OUTVCO is loaded by the same equivalent input capacitance as the buffer (b) in Fig. 4. As predicted by ( 8), the ON input has been activated for 3ns. In time domain, according to Fig. 6, and the state of DATA, the differential OUTVCO voltages (obtained by subtracting OUTVCO-to OUTVCO+) are in phase opposition and consequently have the same response in frequency domain. Providing fully differential outputs as shown in Fig. 6, the circuit is able to implement bipolar modulations as BPSK modulation. Moreover, the quasiinstantaneous starts and stops give the advantage and the opportunity that any additional circuit to obtain a short duration pulse is not necessary.

From post-layout simulations, Fig. 7 shows the oscillations frequency and variation of the power consumption versus VCTRL in the same simulation conditions than Fig. 6. The VCO total power consumption is about 3.2mW/GHz (resp. 3.84µW) when EN is active (resp. inactive). The VCO gain is about 14.8GHz/V. This result demonstrates the wide frequency range of operations which is compatible with the mandatory channels of the IEEE 802.15.4 standard, centered on 4492.8MHz and 7987.2MHz. This gain has been validated in measurement until 8.5GHz since the VCO has been integrated, currently, in a more complex system where VCO output signals cannot be directly observed by measurement.

Always in the same simulation conditions than the Fig. 6, the differential OUTVCO output provides a minimum peak to peak voltage of 1.2V. Finally, the main characteristics of the proposed VCO are summarized in Table I.

V. CONCLUSION

A VCO using fast CML gates has been presented in this paper. It demonstrates its capability in measurement to address the mandatory channels of the IEEE 802.15.4 standard. Moreover, it allows bipolar modulations as BPSK to be implemented without the need of a mixer or other shaping circuits. In the case of UWB-IR communications, this allows the range and/or the rate to be increased for a fixed power spectrum density compared to an OOK modulation. Finally, the circuits can advantageously be switched off between the emissions of two consecutives pulses where it consumes only 3.84µW only.

Fig. 1 .

 1 Fig.1. Architecture of an UWB-IR emitter using a switched oscillator.

Fig. 2 .Fig. 3 .

 23 Fig. 2. Conventionnal three-stages ring oscillator for startup & stop control.

Fig. 4 .

 4 Fig. 4. Design of one CML stage: tunable delay cell (a) -XOR buffer (b).

Fig. 5 .

 5 Fig. 5. Layout of the designed oscillator (35um by 78 um).

Fig. 6 .

 6 Fig. 6. Simulated response of the differential OUTVCO voltage for a BW-10dB of 500MHz (τP-min = 3 ns) centered on 4.5GHz (a) and 8GHz (b).

Fig. 7 .

 7 Fig. 7. Oscillation frequency and power consumption versus VCTRL.

TABLE I

 I

			.	SUMMARY OF VCO CHARACTERISTICS
	Tech	Vdd	Size	τ τ τ τP	fM	Vpp
	(nm)	(V)	(um 2 )	min	(GHz)	(V)

Power Cons.

							Running	Standby
	65	1.2	2730	1/fM	2.6 -12.3 a 2.0 -8.5 b	>1.2 a	3.2mW /GHz a	3.84µW

a a. Post-layout simulations of the full VCO with capacitive load (identical to buffer input capacitance).

b. Verified in measurement.