Keywords: Optical Network-On-Chip, Forward Error Correction, Optical Network Interface, Energy Efficiency, Design Space Exploration

Electrical network-on-chip (ENoC) has long been considered as the technology to improve the bandwidth and the performance of the interconnects in multiprocessor systems-onchip (MPSoCs). However, with the increase of the intellectual property (IP) cores integrated on a single chip, electrical interconnects are less and less suitable to adapt the bandwidth and latency requirements of the nowadays applications. In recent years, with low power consumption, low latency, and high data bandwidth properties, optical interconnect became an interesting solution to overcome these limitations. Indeed, Optical network on chip (ONoC) is based on waveguides and optical signals can be driven from source to destination with very low latency. But unfortunately, the optical devices used to built ONoCs suffer from some imperfections which introduce losses during communications. These losses (crosstalk noise and optical losses) are the very important factors which contribute to the energy efficiency and performance of the system. Furthermore, Wavelength Division Multiplexing (WDM) technology can help the designer to improve ONoC characteristics, especially the bandwidth and the latency. However, using the WDM technology leads to introduce new losses and crosstalk noises which negatively impact the Signal to Noise Ratio (SNR) and Bit Error Rate (BER). In detail, it can result in a higher BER and increases the power consumption and therefore reduces the energy efficiency of the optical interconnects.

In order to address these problems, we first model and analyze the optical losses and crosstalk in WDM based ONoC. The model can provide the analyzing of the worst case of loss and crosstalk with different parameters of optical ring network-on-chip. Based on this model, we propose a methodology to improve the performance and then to reduce the power consumption of optical interconnects rely on the forward error correction (FEC).

We present two case studies of lightweight FEC with low implementation complexity and high error-correction performance under 28nm Fully-Depleted Silicon-On-Insulator 1 Contents 2 (FDSOI) technology. The results demonstrate the advantages of using FEC on the optical interconnect in the context of CHAMELEON ONoC. Secondly, we propose a complete design of optical network interface (ONI) which ic composed of the data flow allocation, integrated FECs, data serialization/deserialization, and the laser power driver. These different elements are presented in this manuscript. Rely on this interface, an energy efficiency allocation management can be supported at runtime due to the application demands. This runtime management of energy-performance can be integrated into the ONI manager through configuration manager which located at each ONI. Finally, the design of an ONoC configuration sequence (OCS) located at the centre of the optical layer is presented. By using the ONI manager, the OCS can configure ONoC at runtime according to the applications performance and energy requirements.

Chapter 1

Introduction

Since several decades, Moore's law and International Technology Roadmap for Semiconductors (ITRS) forecasted that the number of transistors in an Integrated Circuit (IC) will double every 18 months. This increase now leads to the integration of hundreds of intellectual property (IP) cores into a single chip. In these multi-core parallel architectures, the data exchanges between cores can raise a major concern in overall system design: need for high performance interconnects for high data bandwidth communication. In this context, the design of on-chip interconnect plays a very important role for energy efficiency and performance of the overall system. Electrical interconnects are the traditional candidate technology which can adapt to the application communication requirements. However, due to the characteristics of metal wire capacitance and inductive coupling [START_REF] Ho | The future of wires[END_REF], the increase in interconnect noise and propagation delay of global signals limits the overall system performance. Although a lot of effort has been made to solve these problems using many different interconnect architectures, until now, finding effective solutions to overcome these limitations remains a critical challenge.

New interconnects technologies such as three-dimensional (3D) stacking and optical interconnects could be a key solution for future on-chip interconnects. Nanophotonics interconnects are considered as one of the promising technologies, which is a key for the design of such next-generation of multi-processor system-on-chip. Optical interconnect allows for the increase of bandwidth as well as the reduction of noise, latency and power consumption. Another approach to improve the power and the performance of system performance is 3D-stacked technology. Indeed, 3D stacking is a new technology that stacks many silicon wafers or multi-layers and interconnects vertically by using Through Silicon Vias (TSVs). This technology can improve the performance of a system in terms of power consumption, interconnection length and footprint. However, the combined use of 3D stacking and Optical Interconnect (OI) does not completely ensure overall performance. Instead, the exploration in terms of energy efficiency and performance, as well as the trade-off between Electrical-Optical exchanges, must be studied in this context.

Context of 3D Optical Network-on-Chip

Optical Interconnect Technology

Photonics links have been often used from long distance communication to off-chip interconnects such as rack to rack, board to board, chip to chip or data central networks [START_REF] Vahdat | The emerging optical data center[END_REF][START_REF] Vahdat | Delivering scale out data center networking with optics -why and how[END_REF][START_REF] Farrington | Helios: A hybrid electrical/optical switch architecture for modular data centers[END_REF]. But since a couple of years, Silicon photonics seems to be a very interesting emerging technology for the integration of NoC on Multi-Processor System-On-Chip (MPSOC). This technology is based on the use of an optical wave-guide medium to transport optical signals from source to destination with a very short latency.

The key of this technology is the ability to use Complementary Metal-Oxide Semiconductor (CMOS) fabrication in larger-scale. Compared to electrical interconnects, the advantages of this technology are the reduction of crosstalk, the high bandwidth immunity to electromagnetic interference (EMI) and the potential lower power consumption.

These advantages can make optical technology becoming a promising technology to solve the problems of the electrical links. For future multi-core processors, this evolution can offer the possibility to replace electrical links by on-chip optical links. By using this technology, the power consumption can be reduced and the bandwidth can be adapted to the requirements of data exchanges between a large number of cores in a single chip. The major advantages of Optical Interconnects (OI), compared to electrical interconnects in terms of latency and energy efficiency, appear for long distances between source and destination nodes. Furthermore, two important advantages must be considered. Firstly, the increasing data rate will not change energy efficiency because the optical loss does not depend on the data rate. Secondly, optical interconnects can increase bandwidth and data rate by using wavelength multiplexing division (WDM) technology. WDM multiplexes multi-optical carrier signals into a single optical wave-guide by using different wavelengths. Finally, compared to electrical links, optical links can also provide many communication strategies: point to point, broadcast, and varying bandwidth.

There are many reasons to claim that OI can overcome the bottleneck of electrical interconnects based on the signal propagation principle. In the optical domain, the optical signal carries information at a very high frequency and this signal is carried within the optical wave-guide. Then the optical signal is crosstalk and reflection immune. These advantages ensure that optical link has significant ability to support communications not only for long distances but also for on-chip interconnect multiprocessor systems.

Three-Dimensional Integration

Future on-chip multi-core processor systems face a challenge due to the increasing amount of integrated IP cores on a single chip. These challenges are putting inflexible requirements for the MPSOC designer. Recently, optical interconnects show the possibility to become an emerging solution for on-chip interconnects due to their advantages of high bandwidth, high energy efficiency and low latency. Some of the approaches using ONoC have been recently proposed. These approaches are based on the integration of Optical NoC (ONoC) on a specific silicon wafer/layer. However, the disadvantages of this integration are the complexity and the optical wave-guide crossing losses. 3D-stacked technology is one of the promising solutions which can solve the communication problem between these layers. This technology allows for the integration of ONoC in multi-layer.

This approach can reduce the wave-guide crossing, one of the main factor impacting the power budget of optical interconnects. Furthermore, 3D stacking provides a significant cost advantage, which leads to the simplification of designs as well as the manufacturing process.

As we can see in Figure 1.2, a 3D ONoC is composed of an optical layer located between several electrical layers. Each electrical layer contains the Electrical NoC (ENoC) which is used to route the control packets and configure the Optical Network, whereas the optical layer includes the ONoC which consists of optical components such as lasers2 [START_REF] Zhou | On-chip light sources for silicon photonics[END_REF], modulators [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF][START_REF] Rylyakov | A 3.9ns 8.9mw 4x4 silicon photonic switch hybrid integrated with cmos driver[END_REF], photo-detectors [START_REF] Kirman | Leveraging optical technology in future bus-based chip multiprocessors[END_REF], wave-guides [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]. In order to transfer data among Architecture organization of a 3D Optical NoC [START_REF] Beux | Layout guidelines for 3d architectures including optical ring network-on-chip (ornoc)[END_REF] electrical and optical layers, vertical interconnects through TSVs are employed. Communications between nodes of the different electrical layers (inter-layer communications) are supported by ONoC. Nodes on the same electrical layer communicate by intra-layer communication. Recently, some companies have used 3D stacked technology in their chip manufacturing. For example, in 2007, IBM introduced chip with 3D-stacked technology [START_REF]Ibm moves moore's law into the third-dimension[END_REF]. In 2010, a new 3D-stacked technology which can integrate 100 silicon chips in a single package was proposed [START_REF]Ibm moves moore's law into the third-dimension[END_REF]. Even if 3D stacked technology can be interesting, it also induces new challenges, such as thermal problems. Indeed, thermal increase can lead to several undesirable effects such as the increase in power consumption, performance degradation and it generally reduces the reliability of the overall system. Recently, several approaches have been proposed for thermal issue management, for example by addressing new network topologies or task mapping.

To conclude, 3D ONoC is one of the most promising technologies for the next generation of MPSoC interconnects since it has the potential to reduce the interconnect length and the power consumption. However, 3D ONoC still has many open problems such as the design of optical network interface.

Thesis Contributions

3D ONoC is a potential candidate in future MPSoC architecture. In this type of architecture, the electrical layers are connected to the ONoC by using vertical interconnects (TSVs) to upload and download the data between the different layers. More precisely, to emit optical data, the TSV is directly connected to an optical modulator to drive an on-chip laser source which is located in the transmitter of the optical network interface (ONI). At the receiver part of the destination ONI, a TSV is connected to a pair of microresonator and photo-detector. The transmission will be performed in a serial manner in order to reduce the number of TSVs. According to the capacity of optical interconnects with high throughput, the data serialization requires a high-performance ONI which has to be designed to modulate and demodulate data emitted between electrical and optical domains. Modulation and demodulation need to be performed at high frequency to provide high bandwidth.

To address the Optical Network integration challenges, we propose a set of contributions which are summarised in the Figure 1.3. This figure illustrates the contributions of the thesis according to three main problems. proved their abaility in optical communications [START_REF] Nitta | Addressing system-level trimming issues in on-chip nanophotonic networks[END_REF][START_REF] Song | 10-and 40-gb/s forward error correction devices for optical communications[END_REF] or wireless sensor networks (WSN). From this context, we take advantage of ECC to improve the energy efficiency of optical interconnects for MPSoC. Our approach demonstrates the improvement of optical interconnects in terms of energy efficiency and communication reliability. The aim of this contribution is to find a trade-off between energy and performance.

• Design of high-performance optical interface based on the ECC (Step 2 and Step 4): The design of the ONI is one of the most important factors that contribute to the overall system performance. To the best of our knowledge, there are no global solution in the state of the art. Therefore, in this thesis, we propose the first complete optical network interface for WDM ONoC. This interface allows bandwidth and latency adaptations according to the different communication strategies.

• Management unit for the optical network interface (Step 4 and Step 5):

Based on the interface architecture and the design of the laser driver, we propose a management unit for the optical network interface. This ONI manager consists of an ONI configuration memory, which receives data from allocation protocol, and a controller which is driven by allocated tasks and operating system. We have designed this interface, and evaluations and synthesis results of this unit are provided.

Dissertation Organization

The thesis dissertation is organized as follows. In Chapter 2 , we present the state of the art in which the detail of optical devices and structure of optical link are firstly described. Secondly, our target architecture and Optical Network Interface are presented.

Thirdly, state of the art in terms of Error Correcting Code (ECC) with related works in optical communication and WSN are presented. In Chapter 3, we model and analyze the optical losses and the crosstalk in WDM communications. We define the mathematical formulations of the different losses and we also propose a global mathematical model for a point to point communication. In Chapter 4, we propose an energy efficient optical interconnect based on ECC. In this chapter, we propose to use ECCs to improve the energy efficiency in order to meet the communication requirements. Since we model the structure and losses of optical interconnects, we establish the trade-off between energyefficiency and system performance. In Chapter 5, we propose the complete design of the optical network interface in which the ONI has to be implemented as a co-design of both electronics and photonics domains, and where network issues, such as flow control, serialization, deserialization, and ECC integration, must be carefully evaluated. Furthermore, in this chapter, we also present the design of a management unit located in the electrical layer to control the interface and optimize the number of allocated wavelength according to the application requirements. Finally, conclusions and issues for future researches are discussed in Chapter 6.

Chapter 2

State-of-the-Art

Currently, optical interconnect is an attractive solution to address scalability issues in on-chip communication with low-power consumption, low latency, and high data rate and bandwidth. Some techniques, like error-correcting codes (ECC) have been used to improve the communication quality. In this chapter, an overview of optical interconnects including optical devices, like microring resonator, waveguide, photo-detector, and laser, is firstly presented in Section 2.1. Secondly, the classification of optical interconnects is described in Section 2.2 and several optical network-on-chip architectures are also presented. Thirdly, the main principle of ECC is presented in Section 2.4 and the use of this technique for ONoC is introduced. Finally, Section 2.5 concludes this state-of-the-art chapter.

Photonics Interconnect

Compared to electrical interconnects, on-chip optical devices show a great potential to become an emerging candidate for on-chip interconnect due to their properties (low latency, high bandwidth, and low power consumption). In this section, we present an overview of the candidate optical interconnect of Figure 2.1 that directly connects a source and a destination. It is composed of three main parts: a transmitter, a receiver, and a medium. In Figure 2.1, the laser is an off-chip laser which can emit multiple wavelengths for the communication. These wavelengths are injected into the waveguide and they are modulated by the microring resonators (MRs). The transmitter consists Overview of an optical interconnect using off-chip laser [START_REF] Nitta | On-Chip Photonic Interconnects: A Computer Architect's Perspective[END_REF] of the combination of the external laser, waveguides, serializer, electrical drivers and microring resonators. The signal is driven on the medium (waveguide) until it reaches a resonator which extracts and drives it towards the photodetector. At the receiver side, the signal is converted from the optical domain to the electrical domain by the photodetector and the serial data are converted into parallel data. Finally, the signal is transmitted to the destination by an electrical network which is located in the electrical layer.

Transmitter

The transmitter converts the electrical signal into the optical signal. An optical transmitter includes a laser, a driver network, and a micro-ring resonator. In the following sections, the main optical devices are introduced step by step.

Lasers

The position of the laser source can be categorized into two main types: on-chip and off-chip lasers. In this thesis, we focus on on-chip laser integrated into the same die with the other parts of the interconnect, without using an optical coupler to bring the light into the chip. We consider both modulation schemes: indirect and direct modulation. Compared to the off-chip laser, the on-chip laser can provide three key following advantages:

• First, it simplifies the integration in the design by relaxing constraints on the layout. Furthermore, the additional cost from an external laser source to the onchip modulator is removed.

• Second, the flexibility and scalability of the network can be improved by optimizing the laser source placement on the layout.

• Third, the power consumption reduction can be enhanced by run-time management which can turn-on the laser when the communication occurs or turn-off when there is no communication to ensure. Furthermore, on-chip lasers with low-power consumption can be obtained by reduction of loss due to communication crosstalks.

Moreover, for off-chip laser, the loss path is not only from source IP to destination IP, but also from the off-chip laser to source IP. Therefore, by using the on-chip laser, we can reduce the global loss and then reduce the required laser output power.

On-chip light source is an imperative and important device of silicon photonics technology. With features advantages, the on-chip laser shows the potential to become the enabling technology of on-chip light source. Recently, some new technologies have been presented for on-chip laser like Fabry-perot (FR), Distributed Feed-back (DBR) and Micro-disk [START_REF] Van Campenhout | A compact soi-integrated multiwavelength laser source based on cascaded inp microdisks[END_REF][START_REF] Park | Hybrid silicon evanescent laser fabricated with a silicon waveguide and iii-v offset quantum wells[END_REF][START_REF] Fang | Electrically pumped hybrid algainas-silicon evanescent laser[END_REF][START_REF] Sun | Electrically pumped hybrid evanescent si/ingaasp lasers[END_REF][START_REF] Fang | A distributed bragg reflector silicon evanescent laser[END_REF].

Vertical cavity surface emitting laser (VCSELs) is also an interesting technology due to the footprint size as well as straightforward fabrication [5]. Particularly, VCSEL can provide the output power in the range of hundred microwatts, which can adapt the requirement of current and future nanophotonic interconnect. Additionally, double photonics crystal mirror VCSEL (PCM VCSEL) based on a complementary metal-oxide semiconductor are CMOS compatible, which allows for DWDM direct modulation and indirect modulation [START_REF] Sciancalepore | Thermal, modal, and polarization features of double photonic crystal vertical-cavity surface-emitting lasers[END_REF]. Thus, VCSELs are sufficiently compact to implement a large number in a single chip. By specializing the topology, we can avoid the waveguide crossing losses, which is a very costly element contributing to the power budget of the overall system.

As previously mentioned, the main role of the laser is to produce the optical signal that will be sent into the waveguide. But this optical signal must also transport the information (data) from sender to receiver and, to ensure this feature, the optical signal must be modulated. There are two methods to modulate the signal: direct modulation (internal) and indirect modulation (external). The direct modulation method is the technique for which the optical signal is directly modulated by turning on or off the laser source (Fig- The resonated wavelength depends on both MR's diameter and effective refractive index [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]. These parameters are affected by the electrical charge and the thermal issue.

Based on the fabricated method, there are two types of MR: passive MR and active MR.

The active micro-ring is used as a modulator to modulate the light which is emitted from the laser source (see Section 2 perpendicular and parallel waveguides configurations, respectively. In the perpendicular waveguide configuration, multi-layer technology are used to avoid the waveguide crossing losses (0.05dB to 0.2dB [10]). Communication between layers can be implemented by using vertical grating couplers as we can see in Figure 2.6.a. The perpendicular waveguide configuration is shown in Figure 2.6.b using vertical grating couplers. Due to its simple response, MRs can be used to build many important optical components such as optical router, optical switch, optical modulator and detector. However, MR is a device that is very sensitive to temperature issues. Therefore it can become a major source of errors if the temperature is not stable. In particular, MRs can suffer from the important shift in its resonant wavelength due to temperature increase, which can lead to stopping extraction from a waveguide or injection to a waveguide. Thus, architecture considerations need to be explored in order to improve interconnect energy efficiency.

Modulators

As explained before, the modulation can be direct or indirect. When the modulation is direct, the photonics device which supports this feature is the laser. But when the modulation is indirect, the photonics device which supports this functionality is generally a microring. Indeed, because the resonance frequency of MR can be changed (by the carrier depletion), it can be used as a modulator. In this case, the MR is an active component which is controlled to modulate the optical signal from data to transport.

In the context of optical interconnects, on-off keying (OOK) coding is the simplest modulation technique which can adapt the communication speed and bandwidth requirements due to its simple implementation. In this method, logic '1' is represented by the presence of light in a given wavelength and logic '0' is the absence of light in this wavelength. This coding can be created by controlling an active MR (see Section 2.1.1.2) to:

• extract a wavelength from a waveguide and drop it onto another waveguide (case of '1'),

• let the wavelength pass through the MR without extraction (case of '0').

In order to control the MR, an electrical current is used to change the refractive index by changing the bias voltage applied on the modulator.

Optical Medium

Optical medium is the key component to transfer the optical signal between the transmitters and receivers in 3D ONoC. Based on the material, we can classify into different kinds of media: Air, SiO 2 , Si 3 N 4 , etc. In this section, we present some transmission media with different configurations and materials.

Waveguide

As depicted in Figure 2.8, there are four main configurations of waveguides: channel, ridge, slot, and photonics-crystal. Among them, the channel and ridge (Figure 2.8.a and Figure 2.9 shows the cross-sectional structure of a waveguide which consists of different refractive indexes: a core with high refractive index surrounded by a lower refractive index material which is called cladding material. In the context of on-chip interconnects, there are many materials to construct the optical waveguides such as: glass, polymer, or semiconductor. Among them, semiconductors show the potential to become an emerging material due to their characteristics which can make a very high contrast between core and cladding. Especially, Silicon has shown its ability to become an attractive candidate due to CMOS compatibility in the fabrication. Therefore, in this thesis, we assume that the material to construct waveguide is Silicon, although it could be glass, polymer or another semiconductor materials.

In addition, insertion optical loss is an important factor which affects the overall power consumption of the optical interconnect. Therefore, the loss of waveguide must be analyzed to explore carefully the optical network-on-chip architecture trade-off. In the optical waveguide, optical losses are composed of material absorption, scattering and two-photon absorption (TPA) [START_REF] Senior | Optical Fiber Communications: Principles and Practice[END_REF]. Furthermore, the bending loss and waveguide crossing loss are the other sources of loss [START_REF] Joshi | Silicon-photonic clos networks for global on-chip communication[END_REF][START_REF] Yan Pan | Flexishare: Channel sharing for an energy-efficient nanophotonic crossbar[END_REF][START_REF] Koka | A micro-architectural analysis of switched photonic multi-chip interconnects[END_REF]. According to [START_REF] Lipson | Guiding, modulating, and emitting light on silicon-challenges and opportunities[END_REF], the absorption of light in silica and silica oxide is negligible compared to the others. However, the crossing loss is the most important factor which directly impacts the power consumption in ONoC due to its high effect on communication quality. Therefore, in order to avoid the waveguide crossing and improve the power efficiency, the multi-layer technology could be used to replace single layer as illustrated in Figure 2.10. Waveguide crossing can be avoided by using multi

Through Silicon Via

In the 3D integrated circuit paradigm, Through Silicon Via (TSV) [START_REF] Jeddeloh | Hybrid memory cube new dram architecture increases density and performance[END_REF][START_REF] Motoyoshi | Through-silicon via (tsv)[END_REF][START_REF] Woo | An optimized 3d-stacked memory architecture by exploiting excessive, high-density tsv bandwidth[END_REF] is used for data transfer between different layers. electrical layer with the optical layer, then the electrical signal is used to modulate the optical signal. A downloading TSV is used for connecting the optical layer to the electrical layer. At the optical layer, a photo-detector is used to convert the optical signal into the electrical signal, which is then transported by TSV. Size and pitch of TSVs are very important factors which impact the overall footprint. It is then clear that a trade-off must be found between the area needed for an Optical Network Interface (ONI) and the area of a set of processor cores, grouped in a cluster, which is connected to this ONI. Figure 2.12 shows the TSV size evolution according to ITRS. In this figure, the Figure 2.12: TSV for three-dimensional large-scale integration (3D-LSI) technology roadmap from [START_REF] Motoyoshi | Through-silicon via (tsv)[END_REF] current TSV technologies for 3D-LSI are classified into two types, according to their sizes, and it appears that TSVs can become a dominating technology in the future of threedimensional large-scale integration. In particular, TSV reduces the length of interconnects as well as the size and pitch of interconnects compared with the other interconnect technologies. Although TSVs provide many advantages such as electrical performance, low-power consumption and higher data bandwidth, it also presents some drawbacks which lead to some design challenges such as testing process, power distribution and thermal issue.

Therefore, the need for design exploration is very necessary to evaluate the interest of this technology. The structure of a typical optical receiver is illustrated in Figure 2.13. It consists of a photo-detector (PD), a trans-impedance amplifier (TIA), a limiting amplifier (LA), and a clock data recovery (CDR) block. For the case of WDM scheme communications, each PD is associated to an MR to extract the corresponding optical signal from the main waveguide [START_REF] Chen | Ultra-low capacitance and high speed germanium photodetectors on silicon[END_REF].

Receiver

In Figure 2.13, the optical signal is directly extracted from the optical waveguide and sent to the photo-detector. The photo-detector converts optical signals into electrical currents. This current is transformed into a voltage which is then amplified by the transimpedance amplifier. The limiting amplifier acts as a comparator with a threshold voltage V th . Clock-data recovery will then restore the original signal.

As one of elements of the optical receiver, PD is an optical device that directly converts optical signals into electrical signals. Currently, there are many types of photo-detectors used in Optical Network on-Chip with a variety of materials and structures such as silicon photo-detector [START_REF] Chen | High performance germanium photodetectors integrated on submicron silicon waveguides by low temperature wafer bonding[END_REF], III-V semiconductors [START_REF] Ishi | Si nano-photodiode with a surface plasmon antenna[END_REF] and Germanium photo-detector [START_REF] Tang | C-shaped nanoaperture-enhanced germanium photodetector[END_REF].

Based on their structure, we can classify photo-detectors in two types: P-I-N photo-diode (PIN) [START_REF] Going | Germanium wrap-around photodetectors on silicon photonics[END_REF] and avalanche photo-diode (ADP) [START_REF] Huang | 25gbps low-voltage waveguide si-ge avalanche photodiode[END_REF]. In the context of on-chip optical interconnects, PIN photo-detector has been widely used as the optical receiver [START_REF] Going | Germanium wrap-around photodetectors on silicon photonics[END_REF], [START_REF] Kirman | Leveraging optical technology in future bus-based chip multiprocessors[END_REF] due its its advantages in terms of dark current, responsivity, operation speed, and footprint.

To obtain the power budget of the optical link, one important factor that needs to be considered is the photo-detector sensitivity. The sensitivity (in dBm) is the minimum optical power required at the receiver to achieve a given BER value. For example, if a sensitivity is P sen = -25dBm at BER = 10 -9 , this means that if the optical power at the optical receiver is greater than or equal to -25dBm, the system can operate reliably with BER = 10 -9 . The computing of sensitivity and power budget will be presented in Section 4.4.3 in more details.

Optical Network on-Chip -Some Case Studies

Recently, many WDM-based ONoCs have been presented in the literature with different designs. The differences between these designs come from their architectures and the components used to build the communication infrastructure.

More generally, ONoCs can be classified into two main categories: i) Circuit Switching ONoC and ii) ONoC based on Optical Crossbar. They will be described in more details in the following sections.

ONoC based on Circuit Switching

As mentioned in Section 2. For instance, [START_REF] Gu | Design of 3d optical network on chip[END_REF][START_REF] Werner | Amon: An advanced mesh-like optical noc[END_REF][START_REF] Ye | 3d optical networks-onchip (noc) for multiprocessor systems-on-chip (mpsoc)[END_REF] present ONoCs with Mesh topology, [START_REF] Ye | A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip[END_REF][START_REF] Shacham | On the design of a photonic networkon-chip[END_REF] with Folder Torus, and [START_REF] Gu | A low-power fat tree-based optical networkon-chip for multiprocessor system-on-chip[END_REF] with Fat-Tree topology. All of them suffer from reservation time in the optical path which can be long.

Therefore, switching circuit technique can become a major challenge of the ONoC design.

This problem can be solved by using the ONoC based crossbar introduced in the next section.

ONoC based on Optical Crossbar

Crossbar ONoC is based on passive MRs which are set up to select a given wavelength.

Therefore a source IP can directly send the data through the optical router with one or several predefined wavelengths. In crossbar ONoC, due to the property of passive microring which does not need to be tuned (MRs are already set up before the communication occurs), the message transmission does not require the time to set up the optical path and the time to relax the MRs after finishing the transmission. Compared to switching ONoC, this technique has the advantage to reduce the overall latency. However, conflicts can appear in optical routers of the crossbar ONoC when many communications occur at the same time. These conflicts can be solved by using an arbitration that can be implemented by an optical network or an electrical network. For instance, when a communication occurs between a source and a destination at a given time, the destination cannot receive any data from other sources. Then, the destination sends a message to the arbitration to decline other connected requirements from other sources. The potential of the arbitration compared to the electrical control network of switching circuit network is the latency.

Because passive MR does not require the time for reservation as well as the time to relax after finishing the communication, this technique can exploit all the properties of the optical network which are the high bandwidth and the low latency. Furthermore, the power consumption of passive MRs is less than the power consumption of active MRs which require a bias current to be controlled. Then the power consumption of the overall system can be reduced. In this thesis, we focus on crossbar ONoCs with four different communication schemes. The following section introduces some of the existing ONoCs based on optical crossbars.

Survey of

Single Writer Single Reader

SWSR is the simplest interconnect scheme. It relies on the wavelength routing between a source and a destination IP. For instance, Figure 2.15 illustrates the architecture and the connectivity strategy of the SNAKE ONoC [START_REF] Ramini | Contrasting wavelength-routed optical noc topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis[END_REF]. SNAKE is a wavelength routing archi- Another example of SWSR is the λ-Router represented in Figure 2.16 [START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]. This ONoC is a contention-free network, meaning that the λ-Router ONoC does not need any arbitration network. This property can be ensured because all destinations can receive the data without any conflict.

In ORNoC [START_REF] Beux | Optical ring network-on-chip (ornoc): Architecture and design methodology[END_REF], Le Beux et al. present a new communication scheme for which SWSR channels can be reused by reusing the same wavelengths for different communications in .17: Optical Ring Network On-Chip (ORNoC) [START_REF] Beux | Optical ring network-on-chip (ornoc): Architecture and design methodology[END_REF] different parts of the waveguide. This technique is really interesting in particular because it can improve the energy efficiency. Figure 2.17 illustrates the architecture of ORNoC.

In this architecture, the IPs are connected by ring topology waveguides. In the example presented in this figure, the waveguide supports 6 wavelengths which can be used together as communication channels to improve the bandwidth. As we can see, the red wavelength can be reused to connect the IPs from A to H. In order to improve the scalability and bandwidth as well as the energy efficiency, the SWSR can be extended to MWSR as presented in the following section.

Multiple Writers Single Reader

In MWSR, each IP source (processor core or cluster of cores) can send the data to all the remaining IPs but can only receive the data from one of them. This scheme of communication is illustrated in Figure 2.18 where an MWSR with four nodes is presented.

In this example, Node 2 transmits data to Node 4. In this architecture, all of the three

Single Writer Multiple Readers

SWMR (also called "broadcast" communication scheme) is implemented by allowing the communication between one source IP and all remaining destination IPs [START_REF] Pan | Firefly: Illuminating future network-on-chip with nanophotonics[END_REF][START_REF] Kurian | Atac: A 1000-core cache-coherent processor with on-chip optical network[END_REF]. Figure 2.20 illustrates the SWMR communication scheme with the Firefly architecture. The source router R 0 broadcasts data to all the other (N -1) routers. To ensure this communication, all the receivers must extract part of the optical energy from the waveguide, and all the photo-detectors must be aligned to the wavelength used by the sender. Therefore the laser power at the source side must be high enough to ensure that all receivers obtain sufficient optical power. In this case, more than N -1 times of the normal power must be produced by the sender to ensure detection on each receiver. In this communication scheme, by default, all the destinations are turned off. In step 1, by sending a reservation flit which contains the receiver address information and packet length (Figure 2.20.d), the corresponding receiver is turned ON to receive the data in step 2, while the others are turned OFF. Then, the power consumption needed for broadcast can be saved.

Multiple Writers Multiple Readers

In MWMR, the combination of SWMR and MWSR is implemented in order to allow for all the source and destination IPs to access the interconnect medium. Compared to SWMR and MWSR, this communication scheme leads to the increase of optical insertion loss which is the main reason of high power consumption. Figure 2.21 illustrates the Flexishare architecture which uses a token-stream based arbitration network to assign the wavelengths. Figure 2.21.a shows the waveguide for the token streams which passes each router twice. Figure 2.21.b presents the credit streams in which the laser must be routed to the router distributing the credits first and then traverse all the routers twice, as highlighted with different colors.

R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 Credit Stream R 0 R 1 R 2 R 3 R 4 R 5 R 6 R 7 Token Stream (a) (b) R 0 R 1 R 2 R 3 R 4 R 5

Error Correction Codes to Improve Energy Efficiency

In this thesis, we present some methods that use error correction codes to improve energy efficiency and reliability of optical interconnects. Considering the power consumption of optical devices, the implementation of ECC in a global communication path can be very interesting. In this section, we present the basic concept of ECC and the state of the art of this technique from different perspectives: Wireless Sensor Networks, Optical

Communications, and On-Chip Optical Interconnect, respectively.

Basic Concepts

Reliability and energy efficiency are the most important factors in digital communications. In such systems (digital communications, storage systems, etc.), error control is one of the most important techniques which contribute to the reliability and energy efficiency of the links. Hence, the use of error correction codes has become a critical problem in the design of such systems.

The basic concepts of ECC rely on the principle that some redundancy is added to the data to correct the errors which occur during the transmission. the concept of block codes (systematic code1 [START_REF] Lin | Error Control Coding, Second Edition[END_REF]) in which the right side (redundancy bits) is a function of the left side (information bits). Figure 2.22.b illustrates a coded digital communication in which a source sends the information bits (u), the encoder adds redundancy bits into the information bits. The data output of the encoder is called codeword (v) which consists of the information and redundancy bits (e.g., parity bits).

During transmission through the medium, if some errors occur (due to the transmission noise), the decoder recovers the received bit (r) into the estimated information bits (û).

ECC in Wireless Sensor Networks (WSN)

Recently, there were many researchers focusing on error correcting codes for WSN. ECC has a very important role in this domain due to the error correction probability and energy efficiency properties. Studies of [START_REF] Howard | Error control coding in low-power wireless sensor networks: When is ecc energy-efficient?[END_REF] and [START_REF] Sadeghi | Analysis of error control code use in ultra-low-power wireless sensor networks[END_REF] examine the use of ECC in WSN for a range of ECC types which consist of both convolution and block codes. In addition, these publications provide the generic equation for the critical distance at which the ECC becomes energy efficient. Also, the implementation of several ECC schemes has been presented in these studies. In [START_REF] Vuran | Cross-layer analysis of error control in wireless sensor networks[END_REF] [START_REF] Howard | Error control coding in low-power wireless sensor networks: When is ecc energy-efficient?[END_REF]. As we can see in this figure, using ECC can provide significant lower SNR compared to an uncoded system.

ECC in Optical Communications

ECC is considered as a typical approach used to improve the reliability and to reduce the power consumption in optical communications. In long-distance optical communications, the development of ECC can be divided into three generations which correspond to the increase of ECC coding gain. In early day, D.Grover presents FEC in dispersion limited light-wave system which provides 2.5dB at BER = 10 -13 [START_REF] Grover | Forward error correction in dispersion-limited lightwave systems[END_REF]. The first fully-fledged ECC for submarine optical transmission was deployed in the early 1990s. A typical example of the first generation is presented in [START_REF] Reed | Polynomial codes over certain finite fields[END_REF] with Reed-Solomon codes RS(255,239). The second generation of FEC consists in the use of concatenated codes [START_REF] Gol | Forward error correction in dwdm fiber-optic transmission system[END_REF] for high-throughput DWDM submarine communications. The typical example of second generation FEC is RS(239, 223) + RS(255, 239) [START_REF] Mizuochi | Forward error correction based on block turbo code with 3-bit soft decision for 10-gb/s optical communication systems[END_REF]. The most powerful FEC is the third generation which are based on soft decision decoding technique [START_REF] Mizuochi | Next generation fec for optical communication[END_REF]. A comparison between the three Table 2.1: Summary of three generations of FEC (data extracted from [START_REF] Mizuochi | Next generation fec for optical communication[END_REF]).

Gen. Decision

Coding Code rate NCG(dB) @10 -13

ECC for On-Chip Optical Interconnects

In optical interconnects (chip-to-chip interconnect or optical data link), ECC is also an approach to improve energy efficiency and reliability of communications links. In [START_REF] Oprisan | Arq in optical networks[END_REF][START_REF] Guan | The impact of error control on energy-efficient reliable data transfers over optical networks[END_REF][START_REF] Nguyen | Tcp over free-space optical links with arq and amc: A cross-layer performance analysis[END_REF], the authors present the use of ECC based on ARQ to reduce the BER and optimize the bandwidth. In [START_REF] Guan | The impact of error control on energy-efficient reliable data transfers over optical networks[END_REF], the authors show the ability of FEC to relax the throughput and to improve the performance. The potential of FEC in two-dimensional optical data link with Golay codes to improve performance and reduce on-chip power consumption was demonstrated in [START_REF] Faucher | Application of parallel forward-error correction in two-dimensional optical-data links[END_REF]. For chip-to-chip optical interconnects, Jun Wang et al. present the comparison of different types of ECC using 90nm CMOS technology [START_REF] Wang | An efficient error control scheme for chipto-chip optical interconnects[END_REF]. The experimental results presented in this paper conclude that ECC with Hamming code [START_REF] Rakowski | Low-power, low-penalty, flip-chip integrated, 10gb/s ring-based 1v cmos photonics transmitter[END_REF][START_REF] Park | Hybrid silicon evanescent laser fabricated with a silicon waveguide and iii-v offset quantum wells[END_REF] is suitable for chip-to-chip optical interconnects. For on-chip interconnects, many methods of ECC using ARQ or Cyclic Redundancy Check (CRC) to provide a reliability optical link are presented in [START_REF] Nitta | Design and Analysis of Large Scale Nanophotonic On-Chip Networks[END_REF]. Also, Berger codes [6] are evaluated to detect any number of unidirectional errors. However, Berger code implementations are too costly to become a good candidate for on-chip optical interconnects. In [START_REF] Fougstedt | Low-power low-latency bch decoders for energy-efficient optical interconnects[END_REF], a low complexity non-interactive BCH code2 [START_REF] Chen | Error-Control Coding for Data Networks[END_REF] is proposed to reduce the laser power and relax the stringent optical modulation amplitude requirements. This work is implemented using a 28 nm CMOS technology and results in 25% reduction of energy dissipation.

Conclusions and Thesis Contributions

In this chapter, we first presented the state of the art of optical interconnects with various optical devices in three main parts: transmitter, medium, and receiver. Then, some architectures of existing ONoCs were introduced. With low-power consumption, low bandwidth, and high bandwidth property, optical interconnects show the ability to become an emerging candidate for future of on-chip interconnects. However, in order to limit the effect of optical losses and crosstalk noise and to improve energy efficiency, we propose in this thesis the use of error correcting codes. ECC is not only used to improve performance but also to reduce power needed for the laser due to its error-correcting ability. Considering the solutions proposed in the state of the art, we address the three major following problems in this thesis.

Energy efficiency on-chip optical interconnects based on the state of the art of Error Correcting Codes (ECC). The advantages of optical interconnects rely on the optical devices properties which provide high bandwidth, low latency and low-power consumption. However, due to the optical loss and crosstalk noise which can lead to errors occurring during the transmission, these optical devices can reduce the performance of the system. In this thesis, we take advantages of the ECC to provide an energy efficiency optical interconnect for 3D MPSoC. Our approach demonstrates some improvements of optical interconnects in terms of energy efficiency as well as communication reliability.

Design of high performance optical interface based on ECC. In this thesis, we propose a complete optical network interface for coded optical WDM ONoC. This architecture of the interface leads to a simple design layout and allows for the adaptation of bandwidth and latency according to different communication strategies.

Optical network interface management unit. Based on the architecture of the optical network interface and the design of the laser driver which has been already addressed, we propose a management unit for the optical network interface. This ONI manager consists of several components, such as ONI configuration memory (which receives data from allocation protocol) and a controller (which is driven by allocated tasks and operating system).

In the next chapter, we model and analyze the optical loss and crosstalk noise which are two important factors contributing to the energy efficiency of the optical interconnect.

Chapter 3

Modeling and Analyzing

Attenuation and Crosstalk in WDM

ONoC

The attenuation and the crosstalk noise are very important factors contributing to the energy efficiency of the optical interconnect. The ONoC is constructed using MRs, which are one of the main sources of attenuation and crosstalk noise. In order to address the energy efficiency problem of optical interconnects, attenuation and crosstalk noise need to be explored and analyzed. This chapter is organized as follows. Section 3.1 introduces models of attenuation and crosstalk in ONoC. The architecture of CHAMELEON 3D

ONoC is presented in Section 3.2. Section 3.3 details the fundamental analysis of attenuation and crosstalk noise at the device level. Based on this analytical model, Section 3.4 presents the analysis of crosstalk noise at the network level. Section 3.5 shows the results and discussion. Finally, Section 3.6 concludes this chapter.

Introduction

The technology scaling down shows the potential of optical interconnects to replace the electrical interconnects with high-bandwidth and low-latency properties. Furthermore, in order to adapt to application requirements, WDM technology can help the designer to improve ONoC characteristics, and, in particular, to increase the bandwidth and to reduce the latency. However, using the WDM technology leads to the appearance of attenuation and crosstalk noise between the signals which are transferred on different wavelengths. Depending on the architecture of the ONoC and the structure of the Optical Network Interface (ONI), the value of crosstalk noise and attenuation can be different.

In [START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF], the author present an analysis model of attenuation and crosstalk noise in ONoC with three different topologies: Mesh, Folded-torus, and Fat-tree. In [START_REF] Duong | A case study of signal-to-noise ratio in ring-based optical networkson-chip[END_REF], Duong et al.

Chameleon Architecture

Relying on the potential of optical interconnect properties with high bandwidth and low latency, ONoC is considered as one of the emerging solutions for future on-chip interconnects. In this section, we present a new version of ONoC architecture which is named CHAMELEON 1 [START_REF] Beux | Chameleon: Channel efficient optical network-on-chip[END_REF] with three following features: a simple architecture, the optical network interface eases layout synthesis and run-time configuration, and various communication schemes. We step by step present these features in the following subsections. Chameleon consists of two layers: an electrical layer implementing the IP network and an optical layer performing the optical interconnect. The ONI is located between the . By using multiple-waveguides, we can reduce the communication distance to minimize the worst-case of attenuation of ONoC. In the electrical layer, the unit management is implemented to configure the MRs and the laser power level according to communication requirements. Compared to the other existing ONoCs, one of the most potential features of CHAMELEON is the regularity of its architecture and the possibility of reconfiguration at run-time. Indeed, the most straightforward architecture of ONI can lead to the ease in layout synthesis, and the run-time configuration feature contributes to the higher energy efficiency. Moreover, the combination of the reuse of wavelengths and WDM technology can increase the bandwidth and reduce the power consumption of the overall system.

Architecture Overview

Optical Network Interface Architecture

In Chameleon, the ONI architecture is one of the most important factors that impact overall system performance. Each ONI is composed of a transmitter and a receiver, as described in Figure 3.2. The transmitter is composed of on-chip lasers and MRs, which operate as injectors (to inject the signal into the waveguide). The receiver part is composed of photo-detectors and MRs, which operate as ejectors (to drop the signal from the waveguide and guide it to the photo-detector). MRs are configured to be switched • Pass-through. In this case, all the MRs in the transmitter and the receiver parts are in the OFF state. An optical signal propagating along the waveguide will not be ejected, and no optical signal with the same wavelength will be injected for the sake of coherency and to avoid interference. Then, the signal crosses the ONI without being modified, as represented by the signal at wavelength λ 2 (in blue color) in

Communication Schemes

To support the communication requirements, an ONI manager can configure the MRs at to other ONoC. However, it can lead to high complexity for the design of the ONI manager, and it can also increase the latency as well as the power consumption of the system.

To make Chameleon more efficient, we need to consider the architecture exploration of the ONoC regarding power consumption and latency. To do this, the models of attenuation and crosstalk are primarily considered. In the next section, we analyse the optical attenuation and crosstalk noise at both the device level and system level.

Model of Attenuation

This section presents a model of the different communication losses in a 3D architecture integrating the CHAMELEON ONoC. The goal of this model is to provide a general platform for the exploration of energy efficiency properties in a 3D ONoC, as it will be

Fundamental Analysis

Crosstalk noise and loss are intrinsic problems of optical devices caused by the undesirable coupling among optical signals when they are transferred into a single waveguide.

Crosstalk results in a small portion of the power of one signal leaking to other signals and thus becoming considered as noise with regards to the other signals. On the other hand, the evolution of optical technology has demonstrated that MRs are one of the WDM-compatible devices that are the most compact and energy efficient [START_REF] Miller | Device requirements for optical interconnects to silicon chips[END_REF]. They are designed to resonate when presented with specific individual wavelengths and to remain quiescent in all other cases. These MRs are imperfect devices and they are the main source of crosstalk noise and attenuation loss.

In Chameleon, MRs with perpendicular configuration are used as injector/ejector to inject/eject the optical signal according to communication requirements. In this section, we focus on analyzing the loss and crosstalk in the MRs as injectors/ejectors. In this analytical model, MR is evaluated by Lorentzian power transfer function [START_REF] Xiao | Silicon-on-insulator microring adddrop filters with free spectral ranges over 30 nm[END_REF] peaked at the MR's resonant wavelength λ j . For the signal in λ i the power of signal at drop port can be calculated as

P drop P in = 2κ e κ d κ 2 e + κ 2 d + κ 2 p 2 δ 2 (λ i -λ j ) 2 + δ 2 (3.1)
where the -3dB bandwidth of 2δ is expressed as 2δ = λ i Q with Q is the Q-factor of a particular MR and λ j is the center resonance wavelength of MR.

To simplify our analytical equations in the later stages, we assume that κ 2 e + κ 2 d ≫ κ 2 p and κ d ≤ κ e . Therefore,

2κeκ d κ 2 e +κ 2 d +κ 2 p 2
can be approximated to 1. We note the ratio

P drop P in as Φ D (i, j), which becomes Φ D (i, j) = δ 2 (λ i -λ j ) 2 + δ 2 . (3.2)
Considering the Free-Spectral Range (FSR) of a signal as the difference between the MR's resonant wavelength λ j and the examined signal wavelength λ i , we have

∆(i, j) = λ i -λ j = (i -j)( F SR n )
, where we assume equal spacing between two consecutive wavelengths and n is the total number of wavelengths in the network. Furthermore, the power of signal at input includes the power of signal at drop port and the power of signal at through port (P in = P T hrough + P drop ). Therefore, the power of through port can be determined by

Φ T (i, j) = P through P in = 1 -Φ D (i, j). (3.3)
Furthermore, the ON and OFF states of MR are represented in Figure 3.9. We can see that the state of MR corresponds to the resonant wavelength. According to [START_REF] Xu | 12.5 gbit/s silicon micro-ring silicon modulators[END_REF][START_REF] Kiyat | Low-power thermooptical tuning of soi resonator switch[END_REF] with the thermo-optical method, when the resonance wavelength of MR is λ M R = λ j , the MR is turned ON. When the wavelength shifted to λ j + ∆λ, the MR is at OFF state. Based on this theory, we present the analytical eveluation of the crosstalk noise and loss at the device level and system level in the next sections.

Analyzing loss and crosstalk at device level

In Chameleon, the optical network interface is constructed by the active micro-ring with perpendicular configuration. This configuration is based on the advantage of multi-layer technology which has been introduced in Section 2.1.2.2. In the following section, we analyze the optical loss and crosstalk noise in MRs with the perpendicular configuration which is the basic optical element in Chameleon ONoC. There are two types of MRs in this configuration: the first one is the injector which is used to inject the signal from the laser source into the waveguide channel, and the second is the ejector which is used to drop the optical signal from the main channel into the photo-detectors.

MRs as perpendicular injector (Figure 3.10)

According to the Lorentzian transfer function, when the MR is OFF, the signal travels toward the drop port. In this case, the signal power in dB at the drop port when the MR is OFF is

λ j λ j On-chip Laser MR -Injector ON OFF Signal X-talk Channel Waveguide Perpendicular Waveguide λ N λ 1 λ j Laser OFF Laser ON λ N λ 1 λ N λ 1 λ j λ j λ N λ 1 λ j λ j λ j a) b) Input Input Through Drop Add Drop Add Through X inc X inc X coh
P s,D,OF F (i) = P in (i) + L inj-OF F (λ i , λ j + ∆λ) i = 0, 1, ..., n -1 (3.4)
where L inj-OF F (λ i , λ j + ∆λ) is the power loss of all signals passing through the injectors in OFF-state defined as

L inj-OF F (λ i , λ j + ∆λ) = Φ D dB (λ i , λ j + ∆λ) = 10 log 10 (Φ D (λ i , λ j + ∆λ)). (3.5)
Because of the imperfection of the couplers, a portion of the light from all the wavelengths can leak into the perpendicular waveguide. This crosstalk noise (X inc ) is incoherent crosstalk and this does not have any effect on the photo-detector thanks to the perpendicular structure.

When the injector is turned ON, the signal of wavelength λ j is injected to the channel.

The MR is turned ON with wavelength λ j , but it is turned OFF with all remaining wavelengths (λ i ≠ λ j ). Therefore, the signal power in dB at the drop port when the MR is ON is given by P s,D,ON (j) = P Laser (j) + L inj-ON (λ j , λ j )

P s,D,ON (i) = P in (i) + L inj-OF F (λ i , λ j ) (i ≠ j) (3.6)
where L inj-OF F (λ i , λ j ) is the loss of the optical signal with wavelength λ i (i ≠ j) when MR is at OFF-state (with λ j ) and L inj-ON (λ j , λ j ) is the loss of the optical signal with wavelength λ j when the MR is ON-state. These parameters are respectively expressed as

L inj-OF F (λ i , λ j ) = Φ D dB (λ i , λ j ) = 10 log 10 (Φ D (λ i , λ j )) (3.7)
and

L inj-ON (λ j , λ j ) = Φ D dB (λ j , λ j ) = 10 log 10 (Φ D (λ j , λ j )). (3.8)
When the light is coupled into the MRs, a portion of the optical signal from wavelength λ j can go straight to the through port due to the imperfection of the couplers. Another imperfection is the incoherent noise which comes from other wavelengths which are leaking into the MRs and can also come to the through port. However, they do not have any impact to the photo-detector at the receiver thanks to the perpendicular structure and multi-layer technology. For an ejector in the OFF-state, the signal travels toward the through port. According to the Lorentzian transfer function, the signal power in dB at the through port when the MR is OFF is

λ j λ j On-chip Laser MR -Injector ON OFF Signal X-talk Channel Waveguide Perpendicular Waveguide λ N λ 1 λ j λ N λ 1 λ j λ j Input
P s,T,OF F (i) = P in (i) + L eje-OF F (λ i , λ j + ∆λ) i = 0, 1, ..., n -1 (3.9)
where L eje-OF F (λ i , λ j + ∆λ) is the power loss of all signals passing through the ejectors in OFF-state defined as

L eje-OF F (λ i , λ j + ∆λ) = Φ T dB (λ i , λ j + ∆λ) = 10 log 10 (Φ T (λ i , λ j + ∆λ)). (3.10)
Due to the imperfection of the coupling mode, a portion of light from all the wavelengths can leak into the perpendicular waveguide. This crosstalk noise power is incoherent and can be expressed as

P n-inc,D,OF F (i) = P in (i) + L eje-OF F (λ i , λ j + ∆λ). (3.11)
For an ejector in the ON-state, the signal with wavelength λ j is dropped into the photodetector. Therefore, the signal power in dB at the through port when the MR is ON can be expressed as

P s,T,ON (i) = P in (i) + L eje-ON (λ i , λ j ) i ≠ j. (3.12)
The signal power in dB at drop port when the MR is ON is

P s,D,ON (j) = P in (i) + L eje-ON (λ j , λ j ), (3.13)
where L eje-ON (λ j , λ j ) is the power loss of signal with λ j when passing through the ejectors in ON-state defined as

L eje-ON (λ j , λ j ) = Φ D dB (λ j , λ j ) = 10 log 10 (Φ D (λ j , λ j )). (3.14)
Due to the imperfection of the coupling mode, a portion of light from wavelength λ j can leak to the through port. This crosstalk noise is coherent and its power is denoted by

P n-coh,T,ON (j) = P in (i) + L eje-ON (λ j , λ j ) i = 0, 1, ..., n -1 (3.15)
where L eje-ON (λ j , λ j ) is the crosstalk coefficient at ON-state of ejector, which represents the loss of signal power corresponding to the wavelength λ j when dropped into the drop port, defined as

L eje-ON (λ j , λ j ) = Φ T dB (λ j , λ j ) = 10 log 10 (Φ T ). (3.16)
Another crosstalk noise comes from other wavelengths which are leaked into the MRs and come to the drop port. This noise is incoherent crosstalk and is defined by

P n-inco,T,ON = P in (i) + L eje-OF F (λ i , λ j ) i ≠ j (3.17)
where L eje-OF F (λ i , λ j ) is the signal loss coming from other wavelengths when passing through the MR ejector of wavelength λ j in ON-state, defined as

L eje-OF F (λ i , λ j ) = Φ D dB (λ i , λ j ) = 10 log 10 (Φ D (λ i , λ j )).
(3.18)

Signal to noise ratio and loss model at system level

This section presents the analysis of crosstalk and attenuation at the system level in the context of Chameleon ONoC. Due to the ring topology and layout properties of CHAMELEON with no waveguide crossing, the total attenuation in the optical path depends on

• the propagation loss in the waveguide L wg (in dB),

• the bending loss L b , and

• the injector/ejector loss.

The injector (ejector) loss L injector (L ejector ) in dB is based on the status of the MRs which can be ON-state or OFF-state. The total attenuation in the optical path is then

L total = L P + L B + L injector + L ejector . (3.19)

Propagation Loss

L P is obtained from the intrinsic waveguide losses of the optical signal in the waveguide L wg and from the distance d com between the source and destination clusters.

L P = L wg × d com , (3.20)
where L P is the loss by signal propagation from source to destination cluster, L wg in dB/cm is the loss of signal power when the signal is transferred in a 1 cm waveguide, d com is the distance in cm of the considered communication from source to destination ONI.

This distance and all the estimations are derived automatically from the architecture by a Matlab program developed during this thesis.

Bending Loss

The bending loss L B is the additional propagation loss when the waveguide is bent. For 90 o or 180 o bends, there are two sources of loss: bending loss and mode mismatch loss at the junctions between bending and straight waveguide. Bending loss depends on the bending radii and the loss with large bend radii is rather small. However, at system level, with a high number of bends, the bending loss must be considered as

L B = N b × L b , (3.21)
where L b is the loss of signal when passing through 90 o of bend and N b is the number of bends along the communication.

Injector Loss

When a cluster sends the data to another cluster, the on-chip laser must be turned ON.

Then, the light is emitted and injected into the channel and continues to propagate until reaching the destination ONI. Meanwhile, the MR-injector is in ON-state. Injector loss occurs in this mode of communication. The injector loss can be calculated as

L injector = L inj-ON × N inj-ON + L inj-OF F × N inj-OF F , (3.22)
where L inj-ON and L inj-OF F are the loss of an injector in ON state and OFF state, respectively. These parameters are calculated based on the analytical model at the device level presented in Section 3.3.2. N inj-ON and N inj-OF F are the number of injectors in ON-state and OFF-state along the communication.

Ejector Loss

When the light propagates along the channel to reach the destination ONI, signals whose wavelength matches with the resonance wavelength of microring will be ejected into the perpendicular waveguide and dropped on the photo-detector. Similar to the injector loss, the loss of signal in ejector can be defined as

L ejector = L eje-ON × N eje-ON + L eje-OF F × N eje-OF F , (3.23)
where L eje-ON and L eje-OF F are the loss of an ejector in ON state and OFF state, respectively. These parameters are calculated based on the analytical model presented in Section 3.3.2. N eje-ON and N eje-OF F are the number of ejectors in ON-state and OFF-state along the communication.

Simulation Results

In this section, we first present the parameters used in the model of attenuation and crosstalk which are due to the architecture and technology chosen. Then, simulation results for different sizes of Chameleon are shown. These results include the worst-case of attenuation and crosstalk used to improve the energy efficiency in the next chapters.

Technological and Architectural Hypotheses

In this section, we present an example with an architecture corresponding to 3 × 3 ONIs (see Figure 3.12). We use three wavelengths (λ 0 , λ 1 , λ 2 ) to implement the communication and two waveguides (clock and counter clock) for signal propagation. Furthermore, notations and values for parameters of the optical components used in this model are given in Table 3.1. [START_REF] Xiao | Modeling and measurement of losses in silicon-on-insulator resonators and bends[END_REF] To determine the impact of crosstalk noise in the optical interconnects, we use the SNR, the ratio between the received signal and the crosstalk noise power at the detectors.

Results and Analysis on the Proposed Model

In this section, we examine the communication between ONIs in the Chameleon architecture shown in Figure 3.12. By using the analytical model at the device level, we investigate the signal power loss and crosstalk noise of this architecture with 3 × 3 ONIs.

Each ONI consists of a receiver and a transmitter. In the transmitter, three on-chip lasers (VCSELs) located in perpendicular waveguide emit three wavelengths (λ 0 , λ 1 , λ 2 ) which are injected to the waveguide channel by three MR injectors. In the receiver, three ejec-

tors
λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 0 λ 1 λ 2 λ 1 ONI 1.
P rx (λ 0 ) = P Laser (λ 0 ) + L P (λ 0 ) + L B (λ 0 ) + L injector + L ejector . (3.24)
By applying the injector loss, ejector loss and the different parameters, the total attenuation becomes

P rx (λ 0 ) = P Laser (λ 0 ) + L P (λ 0 ) + L B (λ 0 ) + L M R-ON × N M R-ON + L M R-OF F × N M R-OF F = P Laser (λ 0 ) -(5 × 0.5 × 0.1 + 2 × 0.00215 + 5 × 0.0736 + 23 × 0.0436) = P Laser -1.63(dB). (3.25)
The incoherent crosstalk noise is generated from signal with wavelengths λ 1 and λ 2 , corresponding to communications 2 ○ and 3 ○ happening in the same waveguide. This crosstalk noise is expressed as

P n-inc (1) = P Laser (λ 1 ) + L P (λ 1 ) + L B (λ 1 ) + L M R-ON × N M R-ON + L M R-OF F × N M R-OF F (3.26)
and

P n-inc (2) = P Laser (λ 2 )+L P (λ 2 )+L B (λ 2 )+L M R-ON ×N M R-ON +L M R-OF F ×N M R-OF F .
(3.27)

Conclusions

In this chapter, we present the analytical models of loss and crosstalk noise in the optical network-on-chip. In our model, both the losses and crosstalk noises are carefully analyzed at two levels: device level and system level. First, we analyze the loss and crosstalk at the device level with the transmission function of the micro-ring resonator. Based on the device level, we explore the architecture of Chameleon ONoC and provide the analyses of the worst case of loss and crosstalk noise. By using this model, we can provide a generic analysis of attenuation and crosstalk among various parameters of an optical networkon-chip. This result will be used to provide in the next chapter to estimate the power consumption of optical interconnects.

Chapter 4

Error Correction Codes for Energy-Efficient Optical

Interconnects

In on-chip optical interconnects, there are two main major issues contributing to overall system performance: Energy Efficiency and Bit Error Rate (BER). Unfortunately, for the definition of an optical interconnect, these two elements evolve in opposite directions: to reduce the BER, we need to increase the power of the laser, which will increase the energy consumption of the optical link.

Problem Statement

Recently, reliable optical interconnects with high bandwidth and low latency can be obtained by using the Wavelength Division Multiplexing (WDM) technology. In WDM, micro-ring resonators (MRs) are used to modulate, switch, inject and extract the optical signal. However, these MRs are one of the main components introducing crosstalk noises and power losses [START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF] during communications. These losses degrade system performance via the reduction of Signal to Noise Ratio (SNR). This chapter aims to improve the energy efficiency of the system by using some coding techniques. The problem statement and the proposed approach are illustrated in In order to reduce the power consumed, there are two possibilities. The first one is the straightforward method in which the power of the laser is reduced to decrease power consumption. Figure 4.1.b illustrates this solution with a small laser power (P B ). At the receiver side, the signal is attenuated with the same loss, but crosstalk noise is not reduced. Hence, as the laser power is reduced, the SN R B is lower than SN R A .

The

Proposed Approach

ECC is one of the key-enabling elements to enhance the reliability and the energy efficiency in on-chip optical interconnects by reducing the error probability during the transmissions. There are two main approaches using ECC. The first approach, called ARQ (Automatic Repeat Request or Automatic Repeat Query), is an error-control method for data transmission, relying on the re-transmission of the messages until the errors disappear. The second approach is FEC (Forward Error Correction), an error-control technique in data transmission over unreliable communication channels [START_REF] Nitta | Addressing system-level trimming issues in on-chip nanophotonic networks[END_REF] which adds some redundancy bits to the information bits and corrects them at the receiver side by a decoder.

During data transmission, some errors can arrive due to the sensitivity of optical filters and optical switches as weel as to crosstalk noise and thermal issues. For ARQ protocol, the re-transmission is very complex due to the need of feedback communication. It leads to an increase in latency in optical interconnects and also consumes power to support the re-transmissions of the data. Another solution is the combination of ARQ and FEC.

However, this technique can increase the latency as well as the implementation complexity. In this context, FEC is an exciting solution which can be used to reduce the global power consumption and to improve the reliability of the communication channel.

As mentioned in Chapter 2, there exists a lot of FEC techniques used in Wireless Sensor Networks (WSN) and in optical communications [START_REF] Howard | Error control coding in low-power wireless sensor networks: When is ecc energy-efficient?[END_REF][START_REF] Song | 10-and 40-gb/s forward error correction devices for optical communications[END_REF][START_REF] Wang | An efficient error control scheme for chipto-chip optical interconnects[END_REF]. However, in order to determine which solution is the best suited FEC technique for on-chip optical interconnect environment, we have to take some of their properties into account, in particular regarding bandwidth and latency. On-chip nanophotonics interconnects are composed of on-chip laser sources, micro-ring resonators (MRs), waveguides and photo-detectors. Compared to traditional electrical interconnects, the optical devices are more power hungry. By considering this problem, new approaches to share the power consumption between the electrical and optical domains are needed to reduce the global power consumption.

This chapter addresses this challenge and proposes to add data protection in the electrical domain, which allows for the reduction of the power consumption of optical transmission without any reduction of the communication quality. For this purpose, FEC encoders are used on the transmitter side, and faulty bits are detected by the receiver and corrected. Since additional faulty bits are acceptable using FEC, the optical power emitted by the laser source can be significantly reduced. The laser having a significant contribution to the power consumption, the global power of the optical interconnects can therefore be significantly reduced under specific scenarios without compromising the energy-per-bit figures.

Point-to-point Link and Energy/Performance Trade-offs

Communication Without ECC

To communicate, the source core i) sets the corresponding MR to the modulation state and ii) sends the data (d 0 , d 1 and d 2 in the figure). The data are serialized, and the corresponding stream of information bits leads to an On-Off-Keying (OOK) modulation of the optical signal at the wavelength λ x , which is emitted by the laser. The modulation is realized by the electro-optic effect on the MR. Forward bias is applied to perform voltage tuning, which leads to a blue shift of the MR resonant wavelength. In our model, data '1' and '0' lead to OFF state and ON state, respectively:

• OFF state: the MR resonant wavelength is detuned from the optical signal and the optical signal continues propagating with low losses.

• ON state: the MR resonant wavelength and the optical signal are aligned. Most of the optical signal power is absorbed by the MR, which leads to a strong attenuation on the output.

The difference between OFF and ON attenuations defines the extinction ratio. As an example, a 9.2dB extinction ratio at 9Gb/s with 4.32mW and for a 2Vpp CMOS driver has been reported in [START_REF] Li | An energy-efficient silicon microring resonator-based photonic transmitter[END_REF]. In Figure 4.2, this is illustrated by the gap between the two optical signal power levels (marked as 1 ○). The modulated signal then propagates along the waveguide until the receiver, where it is dropped to the photodetector (the optical signal is dropped by MR, by putting it in ON state). The photocurrent is then converted back to a digital data transmitted to the destination core. The transmission can be characterized as follows:

• Power: during the transmission, the modulated optical signals experience losses (not shown in the figure but discussed later on). The laser thus must emit a high enough optical power in order to reach the targeted BER (e.g. 10 -9 ), knowing the losses, the MR extinction ratio, and the photodetector dark current. Because the laser efficiency is relatively low (e.g. around 5%), its contribution in the optical link power budget is significant.

• Performance: thanks to the direct modulation of the data (i.e. without ECC), the transmission time is reduced to the minimum if the target BER is reached.

The following section discusses how the use of ECC impacts the optical communications.

Communication With ECC

When an ECC is included in the communication link, the data to be emitted are first encoded (ed 0 , ed 1 and ed 2 in Figure 4.2, marked as 2 ○) before serialization and modulation. Due to the added bits to be transmitted, the communication time is longer (marked as 3 ○). In the receiver, the optical signal is converted back into electrical signal, and the data are decoded. This receiver allows for detecting and correcting errors, which in turns improves the BER. Hence, assuming the same target BER as for the communication without ECC, the constraints on the SNR are leveraged when ECC is used. This leads to reducing the power of the optical signals, as suggested in the figure with the decreased amplitudes of the emitted signal (marked as 4 ○) and the modulated signal (marked as 5 ○). It is worth mentioning that the extinction ratio is the same. Hence, a global reduction of the optical link power is achievable if the energy saved on the laser side is larger than the energy consumed in the data coding/decoding and the transmission of the added bits.

BER and Laser Power Trade-Offs

In short, without ECC, communications are fast, but the power needed to ensure quality (specific BER) can be important. At the opposite, with ECC, the communication time is increased but the power consumption is potentially reduced, and the communication can be more efficient. This complementary trend well suits execution constraints of nowadays applications running on complex MPSoCs. Although execution deadlines have to be met for real-time applications, energy saving strategies can be applied for power-hungry multimedia-like applications (e.g., by degrading the BER).

This chapter presents how to configure nanophotonics interconnects by jointly i) selecting the ECC used for data transmission and ii) tuning the laser output power. Hence, by considering i) application requirements and power budget and ii) ECC performance and power figures, a manager configures at run-time the optical link. The configuration is two-fold: First, the most appropriate communication scheme with or without ECC (w ECC or w/o ECC in the figure) is selected, and both writer and receiver are configured accordingly; Second, the optical power of the signal emitted by the laser is set in order to respect the BER requirement which is achieved by tuning the laser current.

The use of a shared or centralized manager to configure one ONI emitter and one ONI receiver is a standard solution in ONoCs [START_REF] Wu | Suor: Sectioned undirectional optical ring for chip multiprocessor[END_REF]. In this type of architectures, a source sends a request to the manager by specifying the destination and the communication requirements and the manager responds with the suitable configuration to apply on both source and destination sides. Hence, adding the communication scheme (with or without ECC) within the responses has a limited impact on the manager cost (this problem is addressed in Chapter 5). The choice of the communication scheme is handled by the Operating System (OS) through evaluation of losses due to other communications in the waveguide.

Power and Energy Saving in Optical Interconnects

Energy is one of the important factors impacting overall system performance of ONoC. To determine the impact of FEC to the optical interconnects as well as the trade-off between the energy saving and the BER, we must consider the power budget which consists of the transmitted laser power, the power consumption of FEC, the photo-detector sensitivity and the optical losses.

Transmitted Laser Power

In optical network-on-chip, to ensure a "correct" communication (with the required BER), the transmitted laser power must be adapted to be sure that a minimum power level is received on the photo-detector [START_REF] Wu | Variation-aware adaptive tuning for nanophotonic interconnects[END_REF]. This BER condition is linked to the ratio between signal and noise powers. If the power of the received signal at the photo-detector is too small, the optical link will operate unreliably. The signal to noise ratio at the photodetector is defined as

S N = R.E b B.N 0 = k E b N 0 , (4.1)
where R is the information bit rate (in bits per second), E b the energy per bit (in Joules per bit), B the signal bandwidth, N 0 the noise power spectral density, and k the spectral efficiency (ratio of the information rate to the bandwidth).

Additionally, the power S of the signal arriving at photo-detector is given by

S = P O Laser -L optic , (4.2)
where P O Laser is the transmitted laser power in dBm and L optic is the total loss of optical components during the optical communication from the transmitter ONI to the receiver ONI. This loss value can be extracted from the model of loss which was already provided before in [START_REF] Van | Gestion de la consommation d'un réseau optique intégré dans un MPSoC[END_REF] (see Chapter 3)

From Equations 4.1 and 4.2, we can write

P O Laser = L optic + S N N = L optic + k E b N 0 N (4.3)
where N is the power of noise at the photo-detector.

Power and Energy-per-Bit Saving

Using ECC allows for a coded system to operate at lower SNR than the uncoded system at a given BER. This section presents the power and energy-per-bit saving due to the lowered transmitted power in terms of the power consumption in the ECC codecs.

Communication Without ECC

For uncoded communication, at a given BER, the minimum required laser power P O Laser,U (in Watt) to achieve SN R U at the photo-detector is

P O Laser,U = 10 L optic 10 × k U E b N 0 N = 10 L optic 10 × k U 10 SN R U 10 N (4.4)
where k U = R B is the uncoded spectral efficiency and SN R U is the required signal to noise ratio in dB of the uncoded communication.

One of the main factors significantly contributing to the optical link power budget is the laser efficiency (Laser ef f ) as it could be very low (e.g. 5%). The meaning of this parameter is that the cost of any additional Watt for the laser in the optical domain requires more 20 times power in the electrical domain to drive the laser. Then the electrical power (in Watt) to drive the laser during a communication without ECC is

P E Laser,U = P O Laser,U Laser ef f = 10 L optic 10 × k U × 10 SN R U 10 × N Laser ef f . (4.5)

Communication With ECC

For the communication with ECC, the minimum transmitted laser power (in Watt) to obtain the target SN R C at the photo-detector is

P O Laser,C = 10 L optic 10 × k C E b N 0 N = 10 L optic 10 × k U 10 SN R C 10 N (4.6)
where k C = R B C is the coded spectral efficiency and SN R C = E b N 0 is the required signal to noise ratio in dB of the coded communication.

Similarly, the electric power required to drive the laser during a communication with ECC is

P E Laser,C = P O Laser,C Laser ef f = 10 L optic 10 × k C × 10 SN R C 10 × N Laser ef f (4.7)

Power Saving Using ECC in Optical Interconnects

For a fair comparison, the communication with ECC must show the same information rate R as the uncoded communication. As we can see in Figure 4.3, after encoding, the number of bits of the codeword is greater than the number of information bits (N > K) due to the addition of M redundancy bits. Then, it is unfair to compare the two schemes if the communication with ECC has the same transmission rate. In this case, the information bit rate will be decreased to R.R C , with R C the ratio between some information bits and codeword bits (R C = K N ). This means the uncoded communication decodes R information bits while only R.R C information bits are decoded in ECC communication. where

ECC gain = SN R U -SN R C (4.9)
is the coding gain when ECC is used. Then, Equation 4.8 can be rewritten as Furthermore, the minimum transmitted power of laser can be directly determined from the photo-detector sensitivity, such as P O Laser,U (dBm) = P sen (dBm) + L wc (dB) (4.12)

P E Laser,C = K C K U P E Laser,U 10
where P sen (dBm) is the sensitivity of the photo-detector and L wc (dB) the worst-case of losses of the system. These parameters will be carefully discussed in the next section.

Finally, the power saving of the communication (in milliWatt) can be written as

P O Laser,U = 10 P O Laser,U (dBm) 10
.

(4.13)

Energy-per-Bit Saving Using ECC

The required transmit energy per information bit is determined by dividing the required transmit power P T X by the transmission information rate R:

E T X = P T X R (J bit). (4.14)
For the communication without using ECC, the minimum transmitted energy per bit is

E b,U = P E Laser,U R (J bit). (4.15)
Similarly, for the communication with ECC, the minimum transmitted energy per bit is

E b,C = P E Laser,C R = B B C
E b,U 10 ECC gain 10 (J bit). The energy cost per information bit for the encoder and the decoder could be expressed as Eb codecs = P encoder + P decoder R (J bit) (4.17

)
where R is the information bit ratio. Therefore, from Equations 4.15, 4.16 and 4.17, the total energy saving using ECC to ensure the communication properly operate at a given BER is

∆E save = E b,U -E b,C -E codecs = E b,U 1 - B B C 1 10 ECC gain 10
(J bit).

(4.18)

Sensitivity of the Photo-Detector

To obtain the minimum power of laser (dBm), we should know the sensitivity of photodetector P sen (dBm) and the worst case of losses of the communication path. As discussed in the previous chapter, the worst case of loss depends on the following parameters of the ONoC architecture: number of wavelengths per waveguide, channel distance (∆λ), allocated wavelengths, number of IPs, length of the waveguide and distance between two neighbouring optical network interfaces. This latter parameter is a significant factor contributing to the energy efficiency of the overall system. Indeed, at a given BER and photo-detector sensitivity, the worst case loss is directly proportional to the minimum laser power. These parameters can be extracted from the model of losses developed in the previous chapter.

The photo-detector is the optical device which converts the optical signal into the electrical signal. In order to ensure the optical interconnects to operate properly at a given BER, the received signal power should not be lower than the photo-detector sensitivity P sen (dBm), which gives P Laser,min -L wc ≥ P sen (4. [START_REF] Dong | Low loss silicon waveguides for application of optical interconnects[END_REF] where P Laser,min (dBm) is the minimum transmitted laser power and L wc is the total loss between sender and receiver.

There are two kinds of photo-detectors usually used for optical communications: PIN photo-detector and APD photo-detector (the avalanche photo-diode). However, PIN photo-detector is the most often implemented receiver in optical interconnects [START_REF] Kirman | Leveraging optical technology in future bus-based chip multiprocessors[END_REF]. Anyway, in both cases, the sensitivity of the photo-detector is computed as

P sen = 10 log 1000 × OM A(r e + 1) 2(r e -1) (dBm) (4.20)
where r e is the extinction ratio of the received optical signal and OM A the optical modulation amplitude defined as the difference between the power levels representing a logic one (P 1 ) and logic zero (P 0 ). OM A can be expressed as

OM A(µW ) = i n × SN R ρ (4.21)
where responsivity ρ is the conversion efficiency of the photo-detector in Amperes per Watt (A/W) and input-referred noise i n is the noise floor of the transimpedence amplifier (in A RM S ). These values can be extracted from the device parameters of the transimpendence amplifier part. The signal to noise ratio SN R is the peak-to-peak signal to noise ratio. This value can be obtained by the error probability function of the system.

Assuming a 10 Gbps receiver with typical input-referred noise of 1.1µA RM S , photodetector responsivity of ρ = 0.85(A W ) and extinction ratio of r e = 6.6, the evaluation of photo-detector sensitivity is shown in Figure 4.4.

Trade-off Between BER and FEC Coding Gain

P U = Q( √ SN R) (4.22)
where Q(x) is the Q-function of errors. When the t-error correcting code is used, all the errors which are less than or equal to t will be corrected by the decoder. In this case, the error probability function of the ECC can be generalized as

P B = 1 n n j=t+1 j n j P j U (1 -P U ) n-j . ( 4
P B = P U -P U (1 -P U ) n-1 (4.24)
where n is the length of codeword, m is the number of the redundant bits and k is the

length of data input k = n -m.
The error probability of Reed-Solomon code RS(n, k, d) is to the other codecs. However, each codec comes also with a different hardware complexity of the error correcting algorithm. Therefore, to make a fair comparison in terms of power saving and energy saving between the different ECC methods, we must consider the power consumption and the hardware cost needed for the encoders and decoders. This point is discussed in the following section. Bit Error Rate (BER)

P B = 2 q-1 2 q -1 1 n n j=t+1 j n j P j U (1 -P U ) n-j . ( 4

Hardware Evaluation of ECC Techniques

Using error correcting codes can reduce the minimum laser power needed for a communication due to the coding gain. However, we also need to consider the power consumption consumed by the encoders and decoders (P codecs ). Power consumption consists of static power and dynamic power. Static power (due to leakage current) P s depends on the state of the inputs, temperature, process and voltage. P s can be modelled as

P s = I leak .V (4.26)
where V is the voltage supply and I leak the leakage current. Dynamic power consumption P d is composed of internal power and switching power and can be modelled as

P d = C.V 2 .f (4.27)
where C is the total switched capacitance and f the frequency. Therefore, the total power consumption is

P t = P d + P s = C.V 2 .f + I leak .V (4.28)
To estimate the power consumption of encoder and decoder blocks, each hardware component was designed using Verilog and synthesized using Synopsys Design Vision for a 28nm FDSOI technology. Power metrics were calculated by back annotating the switching activity of internal nets and then importing files in the Synsopys PrimeTime tool.

Clock gating was applied and energy-per-bit was computed by assuming 50% switching activity of the inputs.

Table 4.1 shows the power consumption of the following codec H(7,4), H(71,64) and RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) and provides static, dynamic and total power reports. The lowest power consumption is for Hamming [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) due to its simple implementation. Because of the larger data size, the power consumption of H(71,64) is higher than for Hamming [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4). Figure 4.7 shows that RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) has the best performance in coding gain. However, it also consumes the highest power with 13.1 µW due to the complexity of decoding algorithm.

In order to know which codec is the best candidate in energy and power efficiency, the energy and power saving will be evaluated at the system level in the next section. In order to compute the power and energy-per-bit saving using ECC in the optical interconnect, we assume the Chameleon architecture [START_REF] Beux | Chameleon: Channel efficient optical network-on-chip[END_REF] with 4x4 IPs (or clusters) and a system using four wavelengths per waveguide. The laser efficiency is set to Laser ef f = 5%.

Based on the model of losses, we can extract the worst case of loss for this architecture as L wc = 3.25 dB.

Power and Energy-per-Bit Saving

According to As shown in Figure 4.9, RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) ECC provides the best performance concerning the power saving due to its highest performance in ECC coding gain. However, it also consumes the highest power in its codecs, and therefore RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) does not provide the best performance in energy-per-bit saving. Then, Hamming(7,4) is the best candidate in terms of energy saving.

BER and Laser Power Trade-Offs

For on-chip light sources, we assume an integrated CMOS-compatible vertical-cavitysurface-emitting lasers (VCSEL) [START_REF] Sciancalepore | Thermal, modal, and polarization features of double photonic crystal vertical-cavity surface-emitting lasers[END_REF]. The temperature of the VCSEL depends on i) the optical power to be emitted (OP laser ) and ii) the activity of the electrical layer. Following the methodology detailed in [START_REF] Li | Towards maximum energy efficiency in nanophotonic interconnects with thermal-aware on-chip laser tuning[END_REF], the laser power consumption P laser is estimated assuming 25% chip activity. As illustrated in Figure 4.11, P laser linearly increases within the 0 -500µW optical power range but follows an exponential trend for larger values. This trend is due to the efficiency of the laser which drastically drops with high temperature. Using the model described previously, we evaluate in Figure 4.12 the optical power signal needed to reach the targeted BER according to a given coding technique. For this purpose, we assume an MWSR architecture with 12 ONIs, 16 wavelengths, 6cm waveguide length, 0.274 dB/cm waveguide loss [START_REF] Dong | Low loss silicon waveguides for application of optical interconnects[END_REF] and extinction ratio ER = 6.9 dB [START_REF] Rakowski | Low-power, low-penalty, flip-chip integrated, 10gb/s ring-based 1v cmos photonics transmitter[END_REF].

We assume transmissions with H(7,4), H(71,64) and without ECC, and targeted BER values range from 10 -3 to 10 -12 . As expected, the transmission without codes leads to a higher laser power consumption. For instance, each laser source consumes 14.3 mW for BER = 10 -11 . In case H(71,64) is used, P laser drops to 7.12 mW and it further decreases to 6.64 mW for H [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4). This significant reduction in the laser power is due to the added redundancy bits, which improve the optical channel robustness. Since additional errors in the transmission are acceptable, the optical power emitted by the light sources is reduced. Interestingly, targeting a 10 -12 BER without ECC is not possible since it exceeds the maximum optical power deliverable by the laser (i.e. 700µW). However, reaching this BER is possible using H [START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF] and H(7,4) (P laser = 7.1 mW and 7.6 mW respectively).

Conclusions

In this chapter, we investigated the use of Error Correcting Code (ECC) to reduce the laser output power according to the communication quality requirement. We have shown that using ECC not only allows reducing the laser power consumption but also allows to target BER not reachable without coding techniques and without compromising energy per bit. Since lasers significantly contribute to the optical channel power, the global power reduction of the optical interconnect is also possible under a specific scenario. This trend has been observed especially for H [START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF] ECC.

This chapter has demonstrated the advantages of using FEC on the energy efficiency of the optical interconnect based on a novel architecture [START_REF] Beux | Chameleon: Channel efficient optical network-on-chip[END_REF] an some case studies of lightweight FEC with low implementation complexity and high error-correction performance for a 28 nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology.

Based on these advantages of using FEC, we present in the next chapter the optical network interface which is located between the optical and electrical interfaces. The architecture of the interface can adapt some communication requirements like communication speed and throughput. Furthermore, the optical interface manager is also presented.

Chapter 5

Optical Network Interface Design

Optical Network-on-Chip is a promising technology to leverage the interconnection bottleneck in manycore architectures. Indeed, this technology offers high bandwidth and low latency for communications between cores or clusters of cores. However, the high static power consumption of Optical NoCs (ONoCs) calls for reconfiguration of the interconnect in order to meet the performance requirements while minimizing the required energy. This section addresses this challenge and proposes a method to define, at design time, a set of ONoC execution modes to be loaded, at run-time, according to the applications' performance and energy requirements. The proposed methodology relies on an Optical Network Interfaces (ONI).

In ONoCs, the interface between the optical and electrical domains has an essential role on overall system performance. Indeed, even if the optical components show interesting performance, the associated digital architectures must satisfy some characteristics to not limit the communication medium. This interface is called Optical Network Interface (ONI). For instance, the operating frequency of both domains are not similar and the throughput must be adapted. Moreover, the way an ONI is designed also provides more or less flexibility to use the ONoC, like an adaptive number of wavelengths for each communication or tuning the power of the laser.

In this chapter, we propose an ONI architecture providing high flexibility: the data of a core can be associated to any number of wavelenghts, using or not ECC. Moreover the power of the laser can be tuned by acting on the laser driver. Finally we propose a high level shared component called ONoC Configuration Sequencer (OCS) allowing for the sources and destinations ONIs to be configured at run time.

Introduction

Multiprocessor System-on-Chip (MPSoC) are evolving towards the integration of hundreds of cores on a single chip. Designing an efficient interconnect for such complex architectures is challenging due to the ever growing data exchange between processors.

Networks on Chip (NoCs) have been proposed to overcome these issues but they are now reaching their performance limits. Indeed, packetization and depacketization of data drastically impact NoC latency [START_REF] Owens | Research challenges for on-chip interconnection networks[END_REF] and the same bandwidth for all router ports is usually assumed whereas processor bandwidth requirements vary significantly [START_REF] Cilardo | Design automation for applicationspecific on-chip interconnects: A survey[END_REF]. NoC efficiency thus needs to be further improved in order to interconnect systems with ever increasing number of cores and required bandwidth density efficiently [4].

To overcome the limitations of classical NoCs, nanophotonic interconnects are a promising technology to support communications in MPSoCs. Indeed, Wavelength Division Multiplexing (WDM) allows for the propagation of multiple signals simultaneously on a same waveguide [1], thus leading to high aggregated bandwidth. However, WDM also leads to inter-channel crosstalk noise [START_REF] Duong | Coherent and incoherent crosstalk noise analyses in interchip/intrachip optical interconnection networks[END_REF], which negatively impacts the Signal to Noise Ratio (SNR) and, therefore, the Bit Error Rate (BER). The BER to be reached depends on the application requirements and is closely related to the optical devices characteristics, since it depends on the photodetector sensitivity [START_REF] Fusella | Lighting up on-chip communications with photonics: Design tradeoffs for optical noc architectures[END_REF], on the Microring Resonator transmission spectrum, and on the optical signal power emitted by the laser sources. The higher the number of signals propagating simultaneously, the higher the crosstalk and the higher the laser output power needed. This thus leads to the following conflicting objectives: high performance communications tend to rely on an exhaustive use of the available wavelengths while energy efficient communications involve a parsimonious use of signals which occupy distinct and separate wavelengths. Using an Optical NoC (ONoC)

to support the communications of a given application is thus a tedious task, especially if performance, power and BER objectives are likely to evolve with the execution context.

Hence, for an application executed on a given architecture, several solutions allow implementing the communications, each one providing an optimal solution but with a unique trade-off between energy and performance. In the state of the art, ONoCs can be classified into two families regarding the communication allocation strategy: online or offline.

However, to the best of our knowledge, there is no architecture allowing run-time adaptation of the ONoC to meet energy and performance application requirements for both types of allocations.

To allow run-time adaptation of the ONoC according to energy and performance requirements of the executed applications, a method has been proposed by J. Luo et al. in [START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF]. The method relies on an offline framework to generate a set of ONoC configurations to be stored in a particular ONIs that we propose in this chapter. This ONI works in conjunction with an ONoC configuration sequencer located in the center of the optical layer (Figure 5.1), that we also propose in this chapter. The ONI then selects at run-time the configuration to be loaded according to the application needs.

Run-time Adaptation of ONoC Energy and Performance

Considered Architecture and Applications

We consider a 3D ONoC, i.e., a 3D integrated circuit supporting mixed-technology with an electrically controlled Optical NoC. It combines the benefits of silicon photonics and 3D stacking to overcome traditional electrical network limitations. Photonic interconnect delivers high on-chip bandwidth and low latency while 3D stacking can reduce the interconnect distance. Figure 5.1 shows a ring-based 3D ONoC architecture composed of two layers interconnected by TSV: i) on the bottom, an electrical layer implementing processing cores and ii) on the top, an optical layer with optical routers and waveguides.

Following the layout defined in [START_REF] Wu | Suor: Sectioned undirectional optical ring for chip multiprocessor[END_REF], a centralized ONoC configuration sequencer driven by an Operating System allows run-time adaptation of the ONIs, as illustrated in red in Figure 5.1. The OS is responsible for deploying tasks among the cores and defining the strategy to adapt the ONoC to meet application requirements, such as energy consumption or execution time (called performance within this paper). The sequencer is responsible for reconfiguring the ONoC according to the mode selected by the OS. (DAG) as depicted in Figure 5.2.a, where each vertex t i represents a task and each directed edge (c i→j ) represents a communication from t i to t j . In this example, we assume that tasks t 0 , t 1 , and t 2 are mapped onto different processors. Communications c 0→1 , c 0→2 , and c 1→2 are implemented using an ONoC which is configured according to execution performance and energy requirements.

As we consider WDM communication and laser power tuning, the energy consumption and the execution time of the application are linked to the resources allocated for each communication of the DAG. Indeed, it is possible to adapt the bandwidth for each communication, by varying the number of wavelengths, and to adapt the power laser to meet a targeted communication quality through the BER (not illustrated in this figure).

t 0 t 2 t 1 c 0à1 Q init Q A Q B Q C Q D Q init c 0à2 c 1à2 p 0 p 1 p 2 c 0à1 Q init Q A Q B Q C Q init t 2 t 1 t 0 (f) Energy Execution time … … HP: High Performance LP: Low Power Start C 0->1 & C 0->2 End C 0->1 Start C 1->2 End C 1->2 End C 0->2 Q init Q A Q B Q C Start C 1->2 Start C 0->1 & C 0->2 End C 0->1 End C 0->2 End C 1->2 Q A Q B Q D Q C Q init t 0 t 1 t 2 c 0à1 c 1à2 c 0à2 (b) (d) (e)

Architecture of the Sequencer

The proposed approach requires two hardware blocks, as depicted in Figure 5.3: i) an ONI manager, located in each ONI, in charge of activating the Lasers and MR, and ii)

an ONoC configuration sequencer, shared among all the ONIs, in charge of sequencing the configurations of the ONIs.

An Optical Network Interface, ONI (illustrated on the right part of Figure 5.3), integrates a receiver Rx and a transmitter Tx. The transmitter is composed of on-chip laser sources that can emit and inject optical signal at a specific wavelength into the waveguide. The power generated by the Lasers can be configured. In this example the Lasers can be configured independently among four levels of power. The data are directly transmitted from these lasers through current modulation (OOK) and each laser source can also be turned OFF for energy saving. As the lasers are sending data in serial and as a core sends data in parallel on N bits , a WDM stream serialization is required in order to perform the serialization and allocation of the serial data to the selected wavelengths (i.e. lasers). The receiver part includes wavelength-specific MR that can be turned ON Finally, the resources are released and become available for the next iteration.

ONoC Configuration Sequencer

Generation of Configuration

We consider the use of the framework presented in [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF] to generate the ONoC configuration sequences. This flow takes as inputs an application mapped onto the 3D architecture illustrated in Figure 5.1. The application is modeled as a task graph characterized by task execution times, amount of data transmitted between tasks, and minimum BER to be reached. The design flow relies on device parameters since they impact the performance of optical communications. Instance of parameters are photodetectors sensitivity, waveguide losses and MR model. Regarding the laser, we take the data-rate, the efficiency, the maximum output power, and the number of power levels available into account. The aim of the flow is to optimize both power consumption and application execution time.

For this purpose, our framework explores both device-level and system-level parameters.

Based on a set of device and system input parameters, a multi-objective optimization is carried out using a genetic algorithm due to the two contradictory objectives. In the genetic algorithm, the ONoC configuration modes are represented by chromosomes and the genes encode both wavelength allocations and laser power levels. Finally the resulting ONoC configuration modes on a Pareto front from the multi-objectives optimization are thus reported, including low-power solutions, which tends to minimize the number of used wavelengths, and high-performance solutions, for which multiple wavelengths are allocated to shorten the communication time. It has to be noticed that the framework also optimized the selection of the wavelengths in order to reduce the crosstalk. Then the obtained trade-off configuration modes could be embedded in the system and be loaded on run-time according to the execution context (e.g. high performance and low power) which is out of the scope of this paper. Refer to [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF] for more details on the generation of solutions. interface) and four laser output power levels. Tasks t 0 , t 1 and t 2 are mapped on processor p 0 , p 1 , and p 2 , respectively, which leads to optical communications between p 0 and p 1 (c 0→1 ), p 0 and p 2 (c 0→2 ), p 1 and p 2 (c 1→2 ). The chromosome is divided into as many parts as there are communications (three in the example) [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF]. gives the selected laser output power level; it is an integer value corresponding to the laser configuration. The following genes correspond to the wavelengths utilization: value 0 or 1 indicates that a wavelength is used or unused, respectively. In the example, both c 0→1 and c 1→2 use λ 0 and λ 1 while c 0→2 is implemented using only λ 2 . Obviously, the more wavelengths are allocated for a given communication, the higher the bandwidth.

t 0 t 1 t 2 c 0à1 c 1à2 c 0à2 p 1 λ 0 λ 0 λ 0 λ 1 λ 1 λ 1 λ 1 λ 0 λ 2 λ 2 λ 2 λ 2 λ 3 λ 3 λ 3 λ 3 Rx Tx Rx p 2 Tx p 0 2 1 2 1 4 1 0 0 2 1 2 1 0 0 0 0 1 1 0 0 1 1 1 0 2 1 1 0 0 4 0 0 1 0 2 1 1 0 0 c 0à2 p 0 (Tx) ⇨ p 2 (Rx) c 1à2 p 1 (Tx) ⇨ p 2 (Rx) c 0à1 p 0 (Tx) ⇨ p 1 (Rx)
The configuration of each interface is obtained as follows and is illustrated in Figure 5.5.b.

MR state and Laser power levels are extracted from the chromosome for each Tx and Rx of the ONIs. As we can see in this example, the Tx of p 0 will handle two communications that use different wavelengths and power levels. Then, the configurations are merged and the results configuration of each Tx and Rx are obtained, as shown in 5.5.c.

Finally the configuration can be applied to the ONIs as illustrated in 5.5.d. First, optical channels are open by switching ON the MRs involved in communications (i.e. MRs localized in the transmitter Tx of the source processor and the receiver Rx of the destination). Then, the power of the optical signals propagating through the channels is defined according to the selected lasers power level. In the example, at the transmitter of p 0 interface, three MRs are turned ON to implement communications c 0→1 (λ 0 and λ 1 ) and c 0→2 (λ 2 ). On the receiver side, the MRs corresponding to λ 0 and λ 1 are set to the ON state in p 1 interface, while the MR corresponding to λ 1 remains OFF to let the signal reaching p 2 interface were it will be dropped. In the chromosome part dedicated to c 0→1 , the laser output power level is set to 2: in p 0 interface, the lasers emitting at wavelength λ 0 and λ 1 are set to 50% of the maximum power. In the same interface, laser at λ 2 is set to 100% to match value 4 in corresponding gene for c 0→2 . Regarding the sequencing of steps within a sequence, the ONoC configuration sequencer sends the order to apply the ONI configuration for Tx Rx by using a one-bit signal to the ONI manager. The ONI Manager reads the associated memory containing the Tx and Rx configurations, hence the communication can start.

ONoC Sequencing Illustration

When the communications are over for a processor, or when no communication are necessary in a step, the ONI manager associated to a core sends back a one-bit signal to the ONoC configuration sequencer. When all the communications are completed, the ONoC configuration sequencer indicates to all the ONI to go through the next step.

Hence, the aforementioned sequencing is repeated.

Performance Results

In this section we show the energy versus performance trade-offs available in an ONoC.

We consider the architecture in Figure 5.1 in which each ONI is connected to a cluster of four electrically connected cores. We assume two waveguides, eight wavelengths per waveguide, five configurable levels of electrical power for the Lasers: 2, 4, 6, 8, and 10 mW. Table 5.1 summarizes the technological parameters used to generate the ONoC configurations with the framework proposed in [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF]. Regarding the applications, we use a random task graph generator that provides applications including from 52 to 107 tasks selected within [START_REF] Song | 10-and 40-gb/s forward error correction devices for optical communications[END_REF]1000] bytes. The targeted BER is 10 -9 and each task is randomly mapped on a dedicated core. As we assume shared memory within a same cluster, no latency is assumed for intra-cluster communications.

Design of the ONI and OCS

As it was already shown, to allow run-time dynamicity in the ONoC performance, the ONoC must integrate specifics blocks, like the OCS and the ONIs. In this section, we present the different proposed blocks required to apply the aforementioned methods. ple, a modulation frequency F mod set to 10GHz provides a throughput of 10Gbit/s on 1-bit serial data transmission. According to [2], this is the optical bandwidth to obtain good trade-off between throughput and energy efficiency of each separated wavelength.

Transmitters and Receivers for WDM in ONIs

Whereas, in the electrical domain, IPs would rather communicate at a much lower frequency, noted F IP , e.g. 1GHz, but with parallel data bus of N data width, such as 64 bits.

Source core The operated clock of the serializer register equals the modulation speed. In this chapter, we did not investigate data flow control and multiple-wavelength allocation, which have already been effectively addressed in [START_REF] Wang | A holistic modeling and analysis of optical -electrical interfaces for inter/intra-chip interconnects[END_REF] and [START_REF] Ortin-Obon | Capturing the sensitivity of optical network quality metrics to its network interface parameters[END_REF], respectively.

(Sending data) Destination core (Receiving data) (Transmitter) (Receiver) ... λ 1 λ 2 λ Nw-1 ...
In order to understand the operation principle of the interface, we take an example of the architecture which has been presented previously with Hamming codes. Other cases are shown in the rest of this chapter (see Section 5.5.2). Figure 5.8 illustrates the architecture of ONI based on the Hamming codes with different size of data input. The management part allows the system to control the related components of the interface: i) the configurations of encoders, (ii) the serialisation in one or several serial streams, and iii) the allocation of wavelengths for these data serial flows. In Figure 5.8, this control is represented by the enable input of each block. The initiator of the communication is a task application, shown in Figure 5.8 for task T 3 in the bottom left. The requirement of this task is captured by the energy/performance management system that has a precise knowledge of the number of wavelengths and which wavelength takes part in the communication. From this global information, the system evaluates the number of wavelengths that can be allocated for the communication initiated by task T 3 . We assume Source core

(transmitting data) Cluster 4 R 1 0 0 i i NW-1 0 0 i i NW-1
Energy/ Performance Manager Optical link here that the allocation system decided to allocate three wavelengths (λ 0 blue, λ i green and λ N W L -1 red) for this communication.

In Figure 5.8, we assume that the allocation decides for the encoding of data by H [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) encoder. Then the encoding requires 16 H [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) encoders in parallel to encode 64-bit data.

This encoding led to the addition of redundancy bits, 3 bits of redundancy for 4 bits of data, leading to the addition of 48 bits to encode a 64-bit bus. Therefore, the output of the encoding is a 112-bit codeword that is sent to the serializer. The allocation of three wavelengths for communication leads to dividing the flow of 112-bit codewords into three serial streams. Finally, three serial streams are used in order to modulate selected lasers and to switch on the micro-resonators to inject the wavelengths in the waveguide.

At the receiver side, a symmetrical structure is implemented. According to the allocated wavelength, the control system can configure the ONI receiver by activating i) the corresponding micro-resonators for ejecting the wavelengths, ii) the deserialization of the binary data streams to restore the information bits from the 112-bit codeword, and iii) the decoder to receive the data bits.

The interfaces with the proposed three possible communication modes (H [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) According to the communication requirements, the number of allocated wavelength can be extended by using more shift registers with similar architecture. The specific feature of this block is that each communication could be implemented by one or several wavelengths to improve the communication time and increase the bandwidth through Wavelength Division Multiplexing (WDM) scheme. In general, the serializer could be configured to produce N λ wavelengths. In this case, the serializer must be able to generate multiple streams of data serial outputs which are operated in parallel. The modulated signal is transferred in the waveguide of ONoC until reaching the photodetector where the lightwave signal is converted into electrical current. This signal then passes through the trans-impedance amplifier (TIA) and comparator (CMP) circuit [START_REF] Polster | A tia for optical networkson-chip in 65nm cmos[END_REF], [START_REF] Georgas | Addressing link-level design tradeoffs for integrated photonic interconnects[END_REF]. Finally, the signal is recovered in the receiver interface which is presented in the following section.

Transmission Allocator

Receiver Similarly, the design of the receiver interface is presented in Figure 5.8. The receiver is composed of the micro-ring resonator which can be turned ON or turned OFF in order to drop or pass through the optical signal. The optical signal injected in the wave-guide propagates until reaching the photo-detector which converts the optical signal into electrical signal. A parallel link transmits several serial streams of transformed data into the receiver-allocator. The architecture of this block is similar to the transmitterallocator. Figure 5.12 presents the architecture of the receiver-allocator in which the number of input N max is greater than the number of outputs. The energy/performance Transmitted-Allocator ... GHz.

CLK D Q Q F119 Q[119] q116 q112 ... SEL D Q Q F118 Q[118] q115 q111 D Q Q FF4 Q[4] q0 IN4 D Q Q FF7 Q[7] q3 IN7 D Q Q FF0 Q[0] IN0 D Q Q FF3 Q[3] IN3 q3 ... ... DES4-8 D Q Q CLK FF0 Q[0] IN1 D Q Q FF1 Q[1] D Q Q FF2 Q[2] D Q Q F119 Q[119] IN2

Synthesis Results

In this section, we present the synthesis results of the interface in which two case studies of FEC are included: Hamming codes and Reed-Solomon codes. [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5). The total interface area of the transmitter and the receiver are 889µm 2 and 3513.9µm 2 , respectively. The total power consumption is 19.2mW , which is larger than the 9.5mW of the interface using Hamming codes due to the use of a more complex FEC.

The difference in E b N 0 (or SN R) to achieve a given BER of a given codec compared to the uncoded configuration is called coding gain. Figure 5.13 plots the BER performance as a function of the signal-to-noise ratio for the three codecs: RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5), H(7,4) and The result shows that the RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) provides the best coding gain (4.83 dB) compared to the other codecs due to its higher ability to correct the errors. Reed-Solomon code RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) can correct two errors whereas the Hamming code H(7,4) can correct only one error.

Typically, there is a trade-off between coding gain and decoder complexity. Some codes can provide higher BER performance, but also require higher power consumption, and similarly for decoding algorithms. RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) provides the best coding gain but the highest cost and power, whereas H(7,4) offers the lowest cost and power, but the lowest coding gain.

Communication Latency Along with the development of technology, latency is one of the essential factors of the growing interest in photonics interconnects. Indeed, the potentials of the optical network on chip rely on the properties of optical interconnects with high bandwidth, low latency, and less crosstalk noise. To exhaust all of the features of optical interconnects, the design of the ONI not only ensures energy efficiency but also adapts bandwidth and latency requirements. In detail, the interface is located between two frequency domains, and all the components must operate as fast as possible in order to adapt the modulation speed to the optical domain. EbNo(dB) Furthermore, the transfer delay of the optical signals into the waveguide must be considered 1 . The communication latency of the optical interface with the corresponded delay 1 Delay in the optical waveguide depends on the communication distance and the material of the waveguide (from 0.023 ns to 0.320 ns [START_REF] Ortin-Obon | Capturing the sensitivity of optical network quality metrics to its network interface parameters[END_REF]) of components is defined as τ comm = τ Enc Dec + τ Ser Des + τ T X-allo RX-allo + τ wg .

(5.1)

The latency values of the different elements are obtained from the synthesis results under 28 nm technology (Section 5.5.2). In this architecture, the most important factors contributing to the communication latency of the optical interconnects are the latency of SER and DES (τ Ser Des ) which are a function of number allocated wavelengths (N W L ).

Indeed, the special structure of the proposed SER/DES allows for the WDM scheme to be used, and thus to allocate several wavelengths in a single waveguide to increase the bandwidth and reduce the communication latency. The allocation protocol can manage this configuration according to the application requirements. For instance, instead of using one wavelength for the connection, the management unit can configure eight wavelengths to increase the bandwidth and reduce the communication latency by eight.

We are studying the implementation in the interface of Hamming Codes and Reed-Solomon ECC. According to the implementation and synthesis results under 28 nm technology, a more accurate expression of the communication latency of the interface using Hamming codes as a function of the number allocated wavelengths is

τ comm,H = 2clk e + 3 + nN kN W L clk o + τ wg (ns), (5.2)
where clk e = 1 (ns) is the clock period in the electronic domain, clk o = 0.1 (ns) is the clock period in the optical domain and N W L is the number of allocated wavelengths. N is the number of data bits input. n and k are the code-word width and data input width of a single Hamming code H(n,k), respectively.

The latency of the interface using RS codes is expressed by

τ comm,RS = 80 + m(2 m -1) N W L clk o + τ wg (ns), (5.3)
with m is the primitive polynomial of Galois field in Reed-Solomon codes.

Figure 5.15 plots the evaluation of the communication latency of the interface using Hamming H [START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4), H(71,64) and RS [START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5), respectively, as a function of the number of [START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF] show lower latency due to the simplification of the decoding algorithm. Interestingly, by using more wavelengths, the communication time can be significantly reduced.

On the other hand, due to the probability of correcting errors, Reed-Solomon codes can provide the best coding gain compared to the Hamming codes and thus give the best performance regarding energy efficiency. Therefore there exists a trade-off between the energy performance and the communication time which is addressed by the allocation part. This part is defined according to the application requirements. In this section, we focus on the actual architecture of the network interface and its evaluation. The tradeoff between the unit control and the wavelengths allocation protocol has already been addressed in [START_REF] Luo | POSTER: Wavelength Allocation for Efficient Communications on Optical Network-on-Chip[END_REF].

Laser Driver

Nowadays, optical network-on-chip are becoming a reality due to the feasible of the integration of optical devices with CMOS technology. The use of on-chip optical interconnects leads to higher bandwidth, lower latency and lower power consumption. In order to reduce the laser power and improve the performance of optical interconnects, we proposed the use of error correcting codes. In this method, the output power of the on-chip laser must be tuned according to match the expected propagation losses along the optical path. In this section, we will focus on the design of a laser driver for on-chip laser modulated by the direct method at a single wavelength of the optical signal.

There are many integrated laser devices like the Microdisk, VCSEL, and Distributed Brag

Reflector. In this thesis, we will only focus on the VCSEL device due to its advantages.

Compared to other integrated lasers, VCSEL has the capability of delivering the needed output power with the minimal integration area. VCSEL presents the good trade-off between area and power. Figure 5.16 shows the behavior of a typical VCSEL [17]. In the direct modulation technique, the driver interfaces directly with the laser, hence the current intensity has to be changed to modulate the laser power. Different values of current are set up to create different levels of output powers that would represent a logical 1. Meanwhile, just only one bias current value was selected to represent a logical 0. This bias current is set as high as possible while getting an output power close to zero, to ensure fast dynamic switching between logical values. These values were the fundamental parameters for the design of the laser driver circuit.

In the context of optical modulation, On-Off Keying (OOK) coding is the simplest modulation technique which can adapt the communication speed and bandwidth requirements due to the simple implementation. In this method, logic '1' is represented by the presence of light in a given wavelength and logic '0' is an absence of light in this wavelength. This coding can be done by turn ON or turn OFF the laser directly.

Design of Laser Driver Circuit

In this section, we first introduce the methodology based on 28 nm FDSOI technology and then present the design of the multi-level driver. Finally, we discuss the results and the needed design procedure and some essential elements which impact the output current of laser power in this design.

Methodology and Tools

This section explores the methodology of the design under 28 nm FDSOI transistor technology which is provided by STMicroelectronics. This technology provides and supports a full design kit library that is compatible with Cadence software and is verified and tested on silicon. To perform circuit schematics and layout, we use Virtuoso schematic and layout tool. Also, Cadence provides a SPICE simulator (Spectre) to validate the performance of the integrated circuit design, by considering the transistor's dedicated technology parameters and model, which are well defined in the design kit library. By using Cadence, we can compute all the needed results regarding power and energy consumption. Moreover, we can extract node current and branch voltage values that are selected on the schematic design interface. This will also provide the designers with the needed tools like the eye diagram measurement tool to validate the signal quality and integrity. To verify our design performance, we can also extract the parasitic elements of our layout by using the Calibre tool that is also provided by Cadence and perform the post-layout simulation to confirm that the performance of the circuit is not degraded by the introduction of the circuit parasitic elements. With the use of the full set of tools provided by Cadence, the analog design procedure will be compact and time efficient.

Besides, To verify the driver circuit, we need a model of laser model which includes the load impedance characteristics. The load impedance is an important factor for the driver design procedure, and we can extract different results from the same driver when interfaced with different load impedance characteristics. To simulate the device impedance, we use VerilogA model to describe the laser device as an impedance behaviour, by defining a polynomial function that relates the current and the voltage between two pins of laser that was extracted from the laser (V, I) curve. VerilogA [START_REF] Fitzpatrick | Analog Behavioral Modeling with the VERILOG-a Language[END_REF] provides an extension for the Spice simulator, which can describe the analog and mixed-signal systems. As a result, we will get an analog behavioural model that is included in Spice simulation environment with other defined devices and components.

Similarly, in order to extract the results of the data modulation, we need a signal generator to provide the control signal for the driver input of transistors. According to the references, we use the LFSR (linear-feedback shift register) data generator in [START_REF] Poorghanad | Generating high quality pseudo random number using evolutionary methods[END_REF], this shift register can create a pseudo-random number generator to provide for the driver design. After synthesizing the code, we can extract the netlist and import the VHDL component back to the SPICE then use it likes the other defined components and devices.

Multi-Level Driver

By considering the advantages and disadvantages of some perspective designs, we illustrate the proposed design in Figure 5.17. The design can adapt to the communication data rate at 10 Gbps and provide good performance regarding area and power consumption. Figure 5.17 shows the schematic and principle of the proposed design which based on the multi-level concept. To obtain a two-level current output, the main tail current source of different pair consists of two transistors.

When both of the tail transistors are activated, we can achieve the worst case scenario current demands. However, if N5 is deactivated the logical high output current will decrease according to the current step which is directly related to the number of needed current levels. As for the footprint area budget, for each added output current level, we have to provide a separate transistor bias circuit and a deactivation CMOS transistor to pull low the voltage level at the gate of the desired tail transistor once we want to deactivate the current contribution of the biased current source. Finally, we can confirm that this implementation of the multiple current level concept is scalable without having a significant impact on the footprint area and energy consumption budget. Having many output current levels can have a very beneficial effect on the whole optical link and network concerning efficiency and thermal manager. Thus proving that a dynamic driver approach is achievable without occupying an extensive footprint area to implement the needed hardware while maintaining the control circuitry as simple as possible to improve our overall system performance. We discuss in the next section the achieved results, the required design procedure and the most critical parameters that can affect our output current level.

Results

The design is simulated for three different scenarios corresponding to two, three, and five output current levels, respectively. Results are reported in Tables 5.5, 5.6, and 5.7. The current level can be changed according to the variation of current step C step which is defined as

C step = I max -I min N Levels .
(5.4) Adjusting the bias voltage for the different current can reduce the number of adjustable parameters and the output level variation. However, it will also reduce the complexity of the whole design since we do not have to provide the needed voltage source for each of them. Moreover, in our proposed technique, we simplified and ensured that all the required voltage sources could be supplied from the primary power source that falls into the technology limit. Hence, we rely on the physical dimensions of the transistors, which limits our post fabrication intervention. In this section, we present the design and hardware implementation of the ONI manager under 28 nm technology. Figure 5.20 shows the overview of the design and its configuration memory. The input "M ode" is taken from the output "Changeconf ig" of OCS block (see section 5.5.5). In this design, we assume that there are only three modes automatically generated by the framework in [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF]: High Performance, Balance and Low

Power. These modes are illustrated in Furthermore, Table 5.8 shows the synthesis results of the ONI manager with a different number of MRs. We can conclude from these results that the proposed design is scalable with negligible effect on the footprint area and energy consumption. The results demonstrate that the design is deployable in a wide range of sizes and configurations. Finally, the OCS supports the run-time management of energy-performance trade-off.

ONoC Configuration Sequencer

In this section, we present the architecture of the ONoC configuration sequencer (OCS) in charge of synchronizing all the ONI Managers of the ONoC. In Figure 5.22, we assume that the modes are generated by the framework from [START_REF] Luo | Offline optimization of wavelength allocation and laser power in nanophotonic interconnects[END_REF].

With this framework, we can extract the configuration modes with any parameter from ONoC. For instance, Table 5.9 reports five modes with different configurations in term of energy and performance. Among them, Mode 2 has the maximum number of steps with 10 steps. The number of modes is a parameter that indicates the number bits of the counter (in this case, we need 4 bits width to count up to 10 steps). Therefore, the number of modes contributes to the hardware cost as well as the power consumption and the area of the design. The OCS counter receives the agreement signal (all of the communications are completed) from all ONIs to activate the counter begin to count until the maximum step. Then, the output of the comparator is set at the high level to reset the counter and enable to set up the configuration for ONIs. Finally, the current mode is connected to all the corresponded ONIs to configure the transmitters and receivers. With the proposed design, the communication requirements and operation of the interface are adapted. In this section, we present the synthesis results of OCS for various resource and input parameters. The results are synthesized under 28 nm FDSOI technology. Table 5.10 shows the comparison of OCS synthesis results according to the number of ONIs, the number of modes as well as the number of steps at each mode. The power consumption is not significantly impacted with 21.13 µW , 21.27 µW and 21.56 µW when the number of ONIs equal to 8, 16 and 32, respectively. However, there is a slight increase in power consumption (2,4 %) when the number of steps at a given mode increases from 10 up to 1024 steps. Especially, when the number of modes increases from 5 to 32 modes, a 31.25 % increase in total power is shown, although staying not significant in the overall ONI power budget. It is clear that the area increases with the number ONIs from 8 to 16 and 32. Furthermore, the total area is almost twice when the number of steps increases from 10 to 1024 steps.

Similarly, the number of modes does not significantly impact the area thanks to the simple architecture of the OCS. Finally, the critical path obtained demonstrates that all of the OCS can operate at 1 Ghz frequency in the electrical domain. As a conclusion, we can confirm that this implementation of the proposed design is scalable without having a great impact on the footprint area and energy consumption budget of the overall ONI. The results demonstrate that the design is deployable in a wide range of sizes and configurations.

Conclusion

In this chapter we presented a method to offer dynamicity to ONoC in terms of energy versus performance trade-offs. The hardware blocks in charge of the run-time management of the ONoC have been presented and the method generates the allocation so- This dynamicity in the ONoC is closely linked to the use of the proposed ONI. We shown that our ONI is composed of several parts enhancing the efficiency of the ONoCs. The proposed ONI is scalable and meets all the constraint need by the association of electrical and opctical domains.

Chapter 6

Conclusions and Perspectives

3D Optical Network-on-Chip is probably one interesting emerging technology for the future generation of on-chip interconnects. Indeed, this technology provides several advantages such as low latency, high bandwidth and high energy efficiency properties. Furthermore, wavelength multiplexing division (WDM) technique can be used to allocate several wavelengths for one specific communication leading to improve the bandwidth and to reduce the latency for data exchanges between IP cores. This technique can lead to the appearance of attenuation and crosstalk noise for optical signals, and in this case, it can reduce energy efficiency and increase the Bit Error Rate of the overall system.

To address these issues, we present in this thesis some energy efficiency improvements through the following aspects.

Firstly, we model and analyze the optical losses and crosstalk for WDM used in ONoC.

The model provides an analytic evaluation of the worst case of loss and crosstalk with different parameters for the optical ring topology. More precisely, based on the Chameleon architecture, both worst-case loss and average loss are modelled for a different number of IP cores. Results prove that the loss and crosstalk noise in Chameleon less impact the energy compared to the state-of-the-art in ONoC. This feature can be obtained thanks to the ring topology, the regular layout of the optical interface and the multilayer technology.

Secondly, based on this model of attenuation and crosstalk, we propose a methodology to improve the performance and then to reduce the power consumption of optical interconnects relying on the use of forward error correction (FEC). We present two case studies of lightweight FEC with low implementation complexity and high error-correction performance. We also present the hardware blocks supporting FEC which have been developed Moreover, the design of an ONoC configuration sequencer (OCS), located at the center of the optical layer, is presented. By using the ONI manager, the OCS can configure the ONoC at run-time according to the application performance and energy requirements.

However, several future works based on the proposed techniques and contributions in this thesis can be foreseen.

In order to improve the energy efficiency of ONoC, a run-time configuration of laser power based on the communication requirements will be further developed by considering the energy consumption of each communication. A global ECC configuration algorithm could also be developed to manage the parameters of all the communications of the system.

To evaluate this perspective, we will further investigate the achievable energy efficiency improvement by simulating the execution of standard benchmark applications on nanophotonic interconnects.

As discussed in state of the art, thermal dissipation is one of the most important issues contributing to the overall system performance. Indeed, thermal effects can lead to MR resonance wavelength drift, which is the main reason for errors and loss along the communication path. In order to reduce the impact of this problem, we will investigate an algorithm to manage the laser power by taking the thermal issue into account. In particular, this algorithm can be integrated into a more intelligent ONI manager considering the trade-off between the thermal problem and the energy efficiency. Then, hardware implementation and synthesis of the algorithm will thus be studied. To do this, an analytic model of attenuation and crosstalk when considering the thermal effect must be carefully addressed. Furthermore, to improve the sensitivity of the receiver to adapt the requirement of the multi-current transmitter, the design of multilevel receiver needs to be considered too.

Finally, the global architecture composed of a set of clusters connected by ONoC needs to be considered and studied. More precisely, the size of the clusters, the organization of the network, the number of waveguides and wavelengths, the number of level for laser powers, etc, have to be determined, with respects to the energy, performance, and thermal constraints. These different parameters are not all independent, and a trade-off between them needs to be studied in order to optimize the general performances of the system. thanks to their low power consumption, low latency, and high data bandwidth properties. However, the optical devices used to build ONoCs suffer from some imperfections which introduce losses during communications. Furthermore, Wavelength Division Multiplexing (WDM) technology can further help to improve ONoC's bandwidth and latency. However, using WDM introduces new losses and crosstalk noises which negatively impact the Signal to Noise Ratio and therefore reduces energy efficiency of optical interconnects.

MWSR Multiple

To address these issues, we first provide a model of optical loss and crosstalk in WDM-based ONoC. We then propose a methodology to reduce the power consumption of optical interconnects relying on forward error correction (FEC). We present two case studies of lightweight FEC with low complexity and high error-correction and implement them on a 28nm FDSOI technology. Finally, we propose the complete design of the optical network interface (ONI) composed of allocation and FEC controller, serial to parallel converters, and laser power driver, which creates a runtime allocation management according to application performance and energy requirements.

Figure 1 .

 1 Figure 1.1 illustrates the latency and energy efficiency of electrical and optical interconnects as a function of distance between source and destination nodes. The data are extracted from ITRS 1 for a 16nm SOI technology. As we can see in this figure, the dotted lines present the potential of optical links compared to the electrical links (solid lines).

Figure 1 . 1 :

 11 Figure 1.1: Latency and energy efficiency of electrical and optical interconnects as a function of distance for a 16nm technology (source ITRS)

  Figure 1.2: Architecture organization of a 3D Optical NoC [9]

λ 0 λ 1 λ 2 λ 3 MR:

 3 State of associated MR('1' for ON; '0' for OFF) PM: Power level of associated laser

Figure 1 . 3 :•

 13 Figure 1.3: Representation of the components required for ONoC and highlight of the thesis contributions

  Photodetectors

ure 2 .

 2 2.a). In the indirect method, the optical signal is always on. Meanwhile, the light is modulated by an external device (MRs modulator) in order to control the light flow through the optical waveguide as illustrated in Figure2.2.b.

Figure 2 . 2 :

 22 Figure 2.2: Modulation schemes: a) direct modulation technique and b) indirect modulation technique [81]

Figure 2 .

 2 Figure 2.3 illustrates the structure of an MR with a diameter of 12µm. This is a passive

Figure 2 . 3 :

 23 Figure 2.3: Structure of an actual 12µm-diameter passive microring

Figure 2 .Figure 2 . 4 :

 224 Figure 2.4: Microring Resonators states a) Off state; b) On state.

Figure 2 . 5 :

 25 Figure 2.5: Waveguides and MR positions; a) parallel configuration; b) perpendicular configuration

Figure 2 . 6 :

 26 Figure 2.6: a) The MR in parallel configuration is turned ON to select λ 1 wavelength;b) The MR in perpendicular configuration is turned ON to select λ 1 .

Figure 2 . 1 . 1 Figure 2 . 7 :

 21127 Figure 2.7: a) Layout of the ring resonator-based modulator b) Transmission spectra of the ring resonator at the bias voltages of 0.58 V, 0.87 V, and 0.94 V, respectively.

Figure 2 .

 2 Figure 2.8.b) are the most popular configurations used in on-chip interconnects [50]. Slot and photonics-crystal configurations (Figure 2.8.c and Figure 2.8.d) are less common.

Figure 2 . 8 :

 28 Figure 2.8: a) Channel b) Ridge c) Slot and d) Photonic-crystal waveguide configurations.

Figure 2 . 9 :

 29 Figure 2.9: Cross-sectional structure of a typical cladding waveguide.

Figure 2 . 10 :

 210 Figure 2.10: Waveguide crossing and Switching Element for both single-layer and3D-integrated approaches[10]

Figure 2 .Figure 2 . 11 :

 2211 Figure 2.11: TSV's position in the optical network interface in the context of 3DONoC[START_REF] Sébastien | System level exploration for the integration of optical networks on chip in 3d mpsoc architectures[END_REF]

Figure 2 . 13 :

 213 photo-detectors which convert signals from optical to electrical domains, a classification of photo-detectors and the sensitivity of optical receivers are also presented.

Figure 2 .

 2 Figure 2.14: a) Basic optical router based on MRs, b) Qualitative timing diagram of a successful optical path setup and a blocked setup request [97]

Figure 2 .

 2 Figure 2.14.a and Figure 2.14.b show the structure of router based on the Switching Circuit and the setup process in optical switching circuit interconnects [97].Figure 2.14.a

Figure 2 .

 2 14.a presents an optical router structure based on the four PSE (photonic switching elements) controlled by an electronic router (ER). In Figure2.14.b, the timing diagram illustrates the timing discrepancy which includes the time to reserve the path before sending the packet to the destination. The disadvantage of an ONoC based on switching circuits is the time to set up the optical path which can reduce the latency and increase system power consumption. Recently, several ONoC based on switching circuits have been presented.

Figure 2 . 15 :

 215 Figure 2.15: SNAKE ONoC a) architecture and b) connectivity strategy[START_REF] Ramini | Contrasting wavelength-routed optical noc topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis[END_REF]

Figure 2 .

 2 Figure 2.16: λ-Router a) architecture and b) connectivity matrix [11].

Figure 2

 2 Figure2.17: Optical Ring Network On-Chip (ORNoC)[START_REF] Beux | Optical ring network-on-chip (ornoc): Architecture and design methodology[END_REF]

Figure 2 . 18 :

 218 Figure 2.18: A four-cluster single-bit MWSR bus

Figure 2 . 19

 219

Figure 2 .

 2 Figure 2.19: A Four Wavelength Data Channel Example of CORONA [105].

Figure 2 . 20 :

 220 Figure 2.20: Implementations of the Firefly nanophotonic crossbar (a) Single-writemulti-read bus (SWMR), (b) Reservation flit [79].

Figure 2 . 21 :

 221 Figure 2.21: (a) Token stream waveguide, (b) Credit stream waveguide, (c) Waveg-uides for all the three types of channels[START_REF] Yan Pan | Flexishare: Channel sharing for an energy-efficient nanophotonic crossbar[END_REF].

Figure 2 Figure 2 .

 22 Figure 2.22: a) Concept of redundancy codes b) Example of a digital communication scheme [58]

Figure 2 . 23 :

 223 Figure 2.23: BER performance vs. SNR for several error-correcting codes [36].

Figure 2 .

 2 Figure 2.23 compares the BER performance of some ECCs schemes [36]. As we can see

  present the analysis of crosstalk based on the SUOR ring topology.This chapter proposes an analytical model of attenuation and crosstalk noise for both device level and network level in a WDM-based ONoC which is discussed in the next section. To address these problems and explore the contribution regarding energy efficiency, we first give an overview of CHAMELEON architecture. Secondly, we present the fundamental analysis of the signal power attenuation and crosstalk noise at the device level. Based on the model at the device level and the architecture of the network, we develop an analytic model, providing the worst case of attenuation and crosstalk for different network sizes of the CHAMELEON's architecture. The models proposed in this chapter are used in Chapter 4 for energy efficiency optimization and in Chapter 5 for the design of the ONI manager unit.

Figure 3 .

 3 Figure 3.1 illustrates the Chameleon architecture and its optical network interface (ONI).

Figure 3 . 1 :

 31 Figure 3.1: Chameleon optical interconnect and its Optical Network Interface (ONI)

Figure 3 . 2 :

 32 Figure 3.2: Illustration of the three operations in an ONI: injection, ejection and pass-through

Figure 3 .

 3 Figure 3.2 illustrates the injection of a signal with wavelength λ 1 (in green color) into the waveguide.

Figure 3

 3 Figure 3.2.

  run-time. Therefore, Chameleon provides many communication schemes corresponding to the application requirements: Single Writer Single Reader (SWSR), Single Writer Multi Reader (SWMR), Multi Writer Single Reader (MWSR), and High-Bandwidth Channel (HBC), as illustrated in Figure 3.3, Figure 3.4, Figure 3.5, and Figure 3.6. SWSR (Single Writer Single Reader): By configuring the MRs, the point-to-point communication can be opened by using one or several wavelengths. Furthermore, by reusing one given wavelength, the channel partitioning can be obtained by performing multiple independent communications in the same waveguide. For instance, Figure 3.3 shows the point-to-point communications between: ON I A → ON I B , ON I B → ON I C and ON I C → ON I A using λ 0 (in red); ON I C → ON I B using λ 1 (in green); ON I A → ON I D using λ 2 (in blue), respectively.

Figure 3 . 3 :

 33 Figure 3.3: Single Writer Single Reader communication scheme

Figure 3 . 4 :

 34 Figure 3.4: Single Writer Multi Reader communication scheme

Figure 3 . 5 :

 35 Figure 3.5: Multi Writer Single Reader communication scheme

Figure 3 . 6 :

 36 Figure 3.6: High-Bandwidth Communication scheme

Figure 3 . 7 :

 37 Figure 3.7: Bi-directional communication channels

Figure 3 . 8 :

 38 Figure 3.8: Theoretical model (a) and power responses (b) of a micro-resonator[START_REF] Xiao | Modeling and measurement of losses in silicon-on-insulator resonators and bends[END_REF]

Figure 3 .

 3 Figure 3.8 illustrates the theoretical model and the power resonance responses of an MR. In Figure 3.8.a, κ 2e and κ 2 d are the fraction of optical power that the input waveguide and the drop waveguide couple into and out of the MR, respectively. κ 2 p is a fraction of the inherent power losses per round-trip in the MR. R is the radius of the MR. Figure

Figure

  3.8.b illustrates the power transmission responses of the MR. The power transmission response of through port and drop port are presented.

λλ

  Figure 3.9: a) ON state and b) OFF state of MR[START_REF] Li | Thermal aware design method for vcsel-based on-chip optical interconnect[END_REF]

Figure 3 . 10 :

 310 Figure 3.10: Analysis of perpendicular injector elements in (a) OFF-STATE and (b) ON-STATE

Figure 3 . 11 :

 311 Figure 3.11: Analysis of perpendicular ejector elements in (a) OFF-STATE and (b) ON-STATE

Furthermore, due to

  errors created by the thermal effect onto the MRs as well as errors occurring during the optical signal transmission, the reliability and energy efficiency of communication channels can be decreased. Especially, in complex MPSoCs composed of hundreds of cores, reliability and energy are major challenges requiring a lot of effort to be solved. In this chapter, we propose a new method based on Forward Correction Codes (FEC) to improve the reliability and the energy efficiency of a communication channel by exploring the trade-off between the laser power and the quality of the communication (BER). This chapter is organized as follows. Section 4.1 presents the introduction and the related work. Section 4.2 presents the approach we propose to address this issue. Section 4.3 illustrates the channel modeling and energy/performance trade-offs. The problem formulation and FEC's evaluation are presented in Section 4.4. Section 4.6 shows the results and their analysis. Finally, Section 4.7 concludes this chapter.

Figure 4 .

 4 1 where a point-to-point optical communication between the source IP (IP T X ) and the destination IP (IP RX ) is illustrated. The left side of Figure 4.1 shows the transfer function of the transmitted laser power which can be modulated by the micro-ring modulator. In Figure 4.1.a, the laser power is set to its maximum value (P A ) in order to reach a given bit error rate BER A . At the receiver side, the optical signal is detected by a photodetector. The signal is reduced due to the losses during the propagation on the optical waveguide (see Chapter 3). Furthermore, the signal is also noisy due to crosstalk between other optical signals on the waveguide. These two effects reduce the Signal-to-Noise Ratio SN R A . The amount of laser power during transmission is directly linked to SN R A and is represented by the bit error rate BER A . Figures 4.1.d and 4.1.e illustrate the plots of energy and BER versus communication time.

Figure 4 . 1 :

 41 Figure 4.1: Impact of laser power on energy and latency for a point-to-point communication.

Figure 4 . 1 .

 41 d and Figure 4.1.e show the relation of the Energy and BER versus communication time. The communication time of the system with ECC (point C○) is higher than the system without ECC ( A ○ and B ○), but it can be used to reduce the power consumption while ensuring the required communication quality.

Figure 4 . 2 :

 42 Figure 4.2: General principle of the use of ECC in an ONoC[START_REF] Killian | Energy and performance trade-off in nanophotonic interconnects using coding techniques[END_REF]

Figure 4 .

 4 Figure 4.2 illustrates our approach in the context of a simple optical link with one laser source, one writer (source core) and one reader (destination core). We first detail the basic communication schemes without ECC. Then, we revisit the transmission schemes when ECC is used.

Therefore, the uncodedFigure 4 . 3 :From

 43 Figure 4.3: Size of input and output data for communication with ECC (N,K) encoder

( 4 .

 4 [START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF] where P O Laser,U (in Watt) is the minimum transmitted laser power of the uncoded communication and P codecs is the power consumption of the ECC encoders and decoders.

Figure 4 . 4 :

 44 Figure 4.4: Sensitivity of a photo-detector shown for 10 Gbps with i n = 1.1µA RM S , r e = 6.6 and ρ = 0.85(A W ).

Figure 4 .

 4 Figure 4.5 illustrates an optical interconnect without the encoder and decoder, assuming that bits passing through the channel suffer from independent noise. Without coding technique, the error probability function of the channel in terms of OOK modulation is expressed as

Figure 4 . 5 :

 45 Figure 4.5: Optical interconnect without ECC

Figure 4 . 6 :

 46 Figure 4.6: The optical interconnect with ECC

. 25 )

 25 Based on the analyzed equations, BER performance of Hamming[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF] 4), Hamming[START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF] and RS[START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF] 5) is illustrated in Figure 4.7. In this figure, the difference in E b N 0 (or SN R) to achieve a given BER of a given codec compared to the uncoded version is called coding gain. At BER = 10 -12 , the corresponded SN R of the channel with RS(15, 9, 6), H(7, 4), H(71, 64) and uncoded (points a, b, c, and d in the figure) are 12.11, 14.26, 13.85 and 16.94 dB, respectively. The chart of Figure 4.8 shows that at BER = 10 -12 , the RS(15, 11, 5) code provides the best performance in coding gain with 4.83 dB compared

Figure 4 . 7 :Figure 4 . 8 :

 4748 Figure 4.7: BER versus E b N 0 of Hamming(7, 4), Hamming(71, 64) and RS[START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF] 5)

Figure 4 . 7 , 31 )Figure 4 . 9

 473149 Figure 4.9 provides the power saving obtained by using several ECCs in Chameleon with size 4x4 IPs, N wavelength = 4 for a laser efficiency of Laser ef f = 5% and a worst case of losses of L wc = 3.25 dB. Meanwhile, Figure 4.10 provides energy-per-bit saving using the same Chameleon configuration.

Figure 4 . 9 :

 49 Figure 4.9: Power saving by using ECCs in Chameleon with size 4x4 IPs, N wavelength = 4. Laser efficiency is Laser ef f = 5% and worse case of losses is L wc = 3.25 dB

Figure 4 . 10 :

 410 Figure 4.10: Energy saving by using ECCs in Chameleon with size 4x4 IPs, N wavelength = 4. Laser efficiency is Laser ef f = 5% and worse case of losses is L wc = 3.25 dB.

Figure 4 . 11 :

 411 Figure 4.11: P laser estimated from the output optical power OP laser with 25% chip activity.

Figure 4 . 12 :

 412 Figure 4.12: P laser for a given MWSR channels calculated from the targeted BER and the selected ECC code.

Figure 5 .

 5 Figure 5.2 illustrates the dependencies between the application tasks, the allocated bandwidth and the performance. Applications are represented as a Directed Acyclic Graph

Figure 5 . 1 :

 51 Figure 5.1: Considered 3D ONoC architecture with the configuration sequencer located in the center of optical layer.

Figure 5 . 2 .

 52 figure).Figure 5.2.b illustrates energy versus execution time plot and shows a Pareto front of communication solutions for the architecture. This figure also highlights HP (High Performance) and LP (Low Power) modes on the Pareto front, which either tries to maximize performance or minimize energy or power consumption.

Figure 5 . 2 :

 52 Figure 5.2: Energy-performance trade-off: a) Application represented as a DAG, b) Energy versus Performance plot highlighting High Performance (HP) and Low Power (LP) modes, c-d) ONoC configuration sequence for HP mode and the resulting execution traces, e-f) ONoC configuration sequence of LP mode and the resulting traces.

Figure 5 . 3 :Figure 5 . 4 :

 5354 Figure 5.3: Proposed Optical Network Interface architecture.

Figure 5 .

 5 Figure 5.5 illustrates individual coding and the corresponding ONoC configuration and how we generate the communication configuration that are embedded in each ONI. As depicted in Figure 5.5.a, we assume three interfaces, four wavelengths (i.e. four lasers per

4 •Figure 5 . 5 :

 455 Figure 5.5: Generation of the configurations: a) DAG description, architectural assumptions and the results of the offline optimization framework, b) Extraction of each ONI configuration, c) Result of the ONI configurations, d) Configuration of each ONI with respect to the extraction configurations.

Figure 5 . 5 .

 55 a shows one of the solution given by the framework. It is represented as a chromosome given the bandwidth and power allocation for each communication. The first gene of each chromosome part

Figure 5 .

 5 Figure 5.6 illustrates the relation between the Operating System (OS), the ONoC configuration Sequence, and the ONIs. Regarding the communication through the ONoC, the OS is only in charge of defining the mode (energy-performance trade-off) of the communication. It is possible to change the mode at the beginning of a new sequence.

Figure 5 . 6 :

 56 Figure 5.6: Sequence diagram detailing the interactions between the Operating System, the ONoC configuration sequencer, and the ONIs.

Figure 5 . 7

 57 Figure 5.7 illustrates that the ONI is located between optical and electrical domains, each domain having different signal frequency for receiver and transmitter. For exam-

λ 1 λ 2 λFigure 5 . 7 :

 257 Figure 5.7: Illustration of the different clock domains for the electrical and optical domains

Figure 5 . 8 :

 58 Figure 5.8: Architecture of the optical network interface using Hamming code with three communication strategies

  In order to limit the crosstalk between the signals which has the very closed wavelengths, the signal is allocated by the allocation part before coming to the driver circuit of the laser sources which operate at F optical = 10 GHz[2]. This feature is presented in Figure5.10. The block has N max MUX (N W L , 1), N W L inputs and N max outputs. The inputs are connected directly to the output of SERIALIZER block, the outputs are connected to the laser driver circuit for a given wavelength. By controlling the select input pin of each MUX (N W L , 1), the output is connected to the corresponding input. In order to avoid the crosstalk, in this block, the number of outputs is greater than

Figure 5 . 9 :

 59 Figure 5.9: a) Overall structure of the data SERIALIZER b) Shift register with 1 and 2 outputs, respectively c) Shift register with 4 and 8 outputs, respectively

Figure 5 .

 5 Figure 5.10: a. Overview of the transmission allocator b. Corresponding detailed structure

Figure 5 .

 5 Figure 5.11: a) Overall structure of the data DESERIALIZER b) Shift register with 1 and 2 inputs, respectively c) Shift register with 4 and 8 inputs, respectively

Figure 5 . 12 :

 512 Figure 5.12: Receiver allocator crossbar

Figure 5 . 14 :

 514 Figure 5.14: Communication latency of the proposed ONI using FECs

Figure 5 .

 5 14 also illustrate the communication latency of the optical interconnects based on the optical network interface designed in this chapter. As we can see in this figure, the communication latency accumulates the latency of FECs, SER/DES, and Transmitter/Receiver Allocator.

Figure 5 . 16 :

 516 Figure 5.16: LIV curve of a VCSEL[17]

Figure 5 . 17 :

 517 Figure 5.17: Multi-level driver design

Figure 5 .

 5 Figure 5.18 shows the relationship between the energy consumption and the output current from the synthesis results obtained for different levels of output current. It is obvious that energy consumption increases almost linearly according to the number of output levels. The chart demonstrates that the multi-level concept is scalable. Regarding the added hardware, Figure 5.19 illustrates the linear relationship between the number of output levels and the number of transistors used in this design.

Figure 5 . 18 :

 518 Figure 5.18: Relation between the energy consumption and the current level

Figure 5 . 19 :

 519 Figure 5.19: Relation between the number of current levels and number of used transistors

Figure 5 .

 5 20.b by three rectangles in blue, green, and red, respectively. The input "Currentstep" is taken from the internal counter of OCS. With this input, the ONI manager can know when the communications are finished and prepare setting up for communication of the next steps. The outputs of the ONI manager are connected to MR and Laser source in three ways. The first one (M R RX ) is connected to the MRs in the receiver to drop out the optical signal from the waveguide. The second one (M R T X ) is used for configuration the MRs in the transmitter to inject the signal from the laser source into the waveguide. The last one (P Laser ) is the control input of the laser power driver. This input indicates which level of laser power is emitted to adapt the communication requirements.

Figure 5 . 20 :

 520 Figure 5.20: ONI manager and its configuration memory

Figure 5 .

 5 Figure 5.21 shows the simulation result of an ONI manager, in which, we assume four ONIs, four wavelengths, and five configurable levels of electrical laser power: 3.12mW, 3.84mW, 4.5mW, 5.21mW, and 6mW (see Table 5.7). As we can see in the blue rectangle

  .7). As we can see in the blue rectangle of Figure 5.21, the values of M R T X , M R RX and P Laser are 15, 12 and 2340, which corresponds to the configuration of step QA at HP mode. Similar results are obtained with the other cases of configuration mode. Finally, the configuration can be applied to the ONIs as illustrated in the bottom of Figure 5.21. First, optical channels are opened by switching ON the involved MRs in the transmitter and the receiver. Second, the power of

Figure 5 . 21 :

 521 Figure 5.21: Manager ONI simulation result

Figure 5 .

 5 [START_REF] Fang | Electrically pumped hybrid algainas-silicon evanescent laser[END_REF] shows the general architecture of OCS which includes a counter, an enable block, a mode configuration memory and a comparator. The input signal of OCS comes from the Operating System to select the configuration mode satisfying application requirements. Moreover, the outputs of OCS are connected to the ONIs through two signals: The first is a signal generated by the counter indicating that a step is over. The bit-width of this signal depends on the maximum number of steps in all modes. The second signal bit-width depends on the number of modes embedded in the ONI configuration memory located at each ONIs.

Figure 5 . 22 :

 522 Figure 5.22: The general architecture of the optical network interface configuration sequencer

Figure 5 .

 5 Figure 5.23 shows the simulation result of the OCS connected with eight ONIs and the number of configuration presented in table5.9 with the corresponded number of steps.The simulation demonstrates the correct principle of the proposed OCS. In the next section, we present the synthesis results of OCS in different parameters of ONoC.

Figure 5 . 23 :

 523 Figure 5.23: Simulation of the OCS

  figurations is then controlled step by step by the Operating System to ensure the current requirements.

  under 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology. More precisely, based on Chameleon architecture defined for 4x4 IPs size, and for the following parameters: number of wavelengths equal to N wavelength = 4, laser efficiency Laser ef f = 5%, worse case of losses L wc = 3.25(dB), BER = 10 -12 , and for Hamming codes[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) and Reed-Solomon RS[START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5) FEC, our solution leads to energy saving equal to 71.1 % and 80.3 % respectively. Regarding this power saving, RS shows its ability to become the best candidate compared to Hamming codes. Furthermore, we also present the trade-off between the BER and laser power at the range of BER from 10 -4 to 10 -12 . The results demonstrate the potential of the proposed approach to overcome performance and power issues of the optical interconnect in the context of the ONoC.Thirdly, a complete design of Optical Network Interface (ONI) is presented to support, at run-time, all communication schemes of Chameleon architecture. This optical interface is composed of FECs hardware blocks: data serialization/deserialization, allocator and laser power management. The hardware implementation and synthesis results show the scalability of the interface and demonstrate that the design is deployable in a wide range of sizes and configurations. Relying on this network interface, an allocation management block to improve energy efficiency can be supported at runtime in order to adapt the application requirements. This run-time management of energy vs performance can be integrated into the ONI manager through configuration manager located in each ONI.

Titre:

  Exploration architecturale des interfaces pour les réseaux optiques sur puce efficaces en énergie Mots clés : réseaux optiques sur puce, interface réseau, codes correcteurs d'erreurs, performance, énergie Résumé : Depuis quelques années, les réseaux optiques sur puce (ONoC) sont devenus une solution intéressante pour surpasser les limitations des interconnexions électriques, compte tenu de leurs caractéristiques attractives concernant la consommation d'énergie, le délai de transfert et la bande passante. Cependant, les éléments optiques nécessaires pour définir un tel réseau souffrent d'imperfections qui introduisent des pertes durant les communications. De plus, l'utilisation de la technique de multiplexage en longueurs d'ondes (WDM) permet d'augmenter les performances, mais introduit de nouvelles pertes et de la diaphonie entre les longueurs d'ondes, ce qui a pour effet de réduire le rapport signal sur bruit et donc la qualité de la communication. Les contributions présentées dans ce manuscrit adressent cette problématique d'amélioration de performance des liens optiques dans un ONoC. Pour cela, nous proposons tout d'abord un modèle analytique des pertes et de la diaphonie dans un réseau optique sur puce WDM. Nous proposons ensuite une méthodologie pour améliorer les performances globales du système s'appuyant sur l'utilisation de codes correcteurs d'erreurs. Nous présentons deux types de codes, le premier (Hamming) est d'une complexité d'implémentation faible alors que le second (Reed-Solomon) est plus complexe, mais offre un meilleur taux de correction. Nous avons implémenté des blocs matériels supportant ces corrections d'erreurs avec une technologie 28nm FDSOI. Finalement, nous proposons la définition d'une interface complète entre le domaine électrique et le domaine optique permettant d'allouer les longueurs d'ondes, de coder l'information, de sérialiser le flux de données et de contrôler le driver du laser pour obtenir la modulation à la puissance optique souhaitée. Title: Architectural Exploration of Network Interface for Energy Efficient 3D Optical Network-on-Chip Keywords: optical networks on chip, network interface, error correcting codes, performance, energy Abstract: In recent years, Optical Networks on Chip (ONoC) became an attractive solution to overcome the limitations of current electrical interconnects,

Table 3 . 1 :

 31 Notations and value for parameters of the optical components

	Parameter	Sym. Value	Ref.
	Propagation loss	L p	-0.1dB/cm	[47]
	Bending loss	L b	-0.00215dB/90 o [46]
	Q-factor	Q	3383	[115]
	Free-Spectral Range F SR 15.74nm

  are used to drop out the signal whose wavelength matches with the MR wavelength resonances.

	PD PD	PD PD	PD PD		PD PD	PD PD	PD PD			PD PD	PD PD	PD PD
			PD PD	PD PD			PD PD	PD PD	PD PD	PD PD	PD PD
	PD PD	PD PD	PD PD		PD PD	PD PD	PD PD			PD PD	PD PD	PD PD
		Micro-resonator	on-chip laser	photo-detector		waveguide	optical signal	crosstalk
		MR	MR				PD PD
		OFF	ON	OFF	ON

  operating point of this state is represented by point B ○ in Figures 4.1.d and 4.1.e.

However, reducing the SN R B for a communication can lead to a BER B out of the acceptable BER for this communication link.

Table 4 . 1 :

 41 Power consumption results for simple Hamming and Reed Solomon ECC blocks

		Static	Dynamic	Total
	ECC	Power	Power	Power
		(nW )	(µW )	(µW )
	H(7,4)	0.268	0.433	0.434
	H(71,64)	3.960	4.960	5.160
	RS(15,11,5) 43.58	12.99	13.10
	4.6 Power and Energy Saving using ECC in Optical Inter-
	connects

Table 5 .

 5 2 summarizes the characteristics of the task graphs and the total energy and execution time in clock cycles (cc) required. Since the generation of the ONoC configuration leads to a Pareto front with several solutions, we only show the solutions with i) the lowest energy consumption (denoted Low Power in the table) and i) the lowest execution time (High Perf.). As shown in Table5.2, the solutions offer, on average, 44% energy variation and 71% execution time variation trade-offs. From these solutions, the designers can implement in the configuration memory of the ONI manager several solutions that provide intermediate trade-offs. These results demonstrate the efficiency of flexible wavelengths allocation and laser output power tuning to adapt the nanophotonic interconnects according to application requirements.

	Parameter	Value	Ref
	Waveguide propagation loss -0.274 dB/cm [19]
	Photodetector sensitivity	-20 dBm	[42]
	Laser efficiency	15%	[42]
	∆λ	0.4 nm	[3]
	FSR	8 nm	[3]
	-3dB MR bandwidth	0.26 nm	[3]

Table 5 . 1 :

 51 Technological parameters.

	Graph	Number of		Energy (nj)	Execution Time (kcc)
	ID	Tasks/Comms	Low Power	High Perf.	Variation	Low Power	High Perf.	Variation
	TG 1	55/80	141	187	1.33	41.2	23.8	1.73
	TG 2	52/78	118	194	1.64	37.9	23.6	1.62
	TG 3	57/82	102	120	1.18	39.9	24.6	1.84
	TG 4	60/92	141	195	1.38	37.3	22.8	1.62
	TG 5	63/93	128	193	1.51	41.2	24.6	1.89
	TG 6	62/92	147	236	1.61	43.2	24.4	1.75
	TG 7	56/87	103	148	1.44	31.7	19.9	1.57
	TG 8	63/91	112	156	1.39	37.5	23.3	1.60
	Average		124	179	1.44	38.7	22.7	1.71

Table 5 . 2

 52

: Energy-performance trade-off variation possibilities.

  , H[START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF], and uncoded) have been synthesized using 28nm FDSOI technology library using Synopsys Design Vision. The interfaces have been designed for 64-bit data width (N data = 64) to operate at F IP = 1 GHz and allowing to reach F mod of 10 Gbps. The synthesis results are presented in Table5.3 page 91. In this table, in order to encode the 64-bit data, the interface requires 16 parallel H(7,4) coders and decoders, whereas only one H[START_REF] Nikdast | Crosstalk noise in wdm-based optical networks-on-chip: A formal study and comparison[END_REF][START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF] codec is required. The Hamming blocks are clocked at F IP and compute the result in one clock cycle. The Serializer and Deserializer are operated at F mod = 10Gbps. In the following section, we introduce the details of the ONI transmitter (Electrical -Optical Interface) with its corresponding blocks. 5.5.1.2 Design of the Electrical -Optical Interface Serializer Figure 5.9 presents the structure of the data serializer block. The serializer in this figure can be able to support the allocation with 1, 2, 4, 8 wavelengths respectively.

Table 5 .

 5 3 shows the synthesis results of the interface with the area, timing, and power reports. The interface has been designed for 64-bit data, and the operating frequency in the IP domain F IP is 1 GHz. According to the previous chapter, there are two modes of communication: with Hamming code (Hamming[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) or uncoded). As we can see in Table5.3, to encode the 64-bit data, the interface needs 16 parallel Hamming[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) encoders/decoders. These FEC codecs operate at F IP frequency, and they take one clock cycle to compute the result. In order to select the coding technique which takes part in the communication, these Hamming codes are selected by the MUX and DEMUX blocks. The encoded data are serialized by serializer block at F mod frequency to modulate the laser source. This serializer is a well-known architecture based on shift-registers, with a depth equal to the input size. These registers can be loaded with the input data by the use of a two-bit MUX located in each register input. Regarding the deserializer, its architecture is also based on shift-registers with a depth equal to the output size. These straightforward solutions allow achieving a high throughput required by the optical modulation speeds while limiting the area. Table5.3 also shows the critical path of this block is 70 ps. It means this block can operate at 10 GHz frequency to meet the transmission condition speed of the optical domain (10 Gbps).The total area cost of the transmitter and receiver interfaces is 2795µm 2 and 2493µm 2 , respectively. The static power is low with 28.4µW and 17.2µW respectively thanks to the 28 nm low-leakage technology.

Table 5 . 3 :

 53 Synthesis results of the proposed ONI using Hamming[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4) codes

			Critical	Total	Static	Dynamic	Total
	TX	Amount	Path	Area	Power	Power	Power
			(ns)	(µm 2 )	(µW )	(mW )	(mW )
	H(7,4) Enc	16	0.21	551.04	1.76	3.13	3.14
	DEMUX	1	0.03	762	10.69	1.45	1.46
	Serializer	1	0.09	1664	25.80	1.2	1.23
	TX Allocator	1	0.09	90.10	0.843	0.072	0.073
			Critical	Total	Static	Dynamic	Total
	RX	Amount	Path	Area	Power	Power	Power
			(ns)	(µm 2 )	(µW )	(mW )	(mW )
	H(7,4) Dec	16	0.3	783.36	2.53	3.80	3.81
	MUX	1	0.8	676	10.8	1.55	1.56
	Deserializer	1	0.07	966.5	13.6	1.03	1.04
	RX Allocator	1	0.09	95.3	1.07	0.171	0.172

Table 5 .

 5 4 summarizes the synthesis results of the optical network interface using Reed-

	Solomon code RS

Table 5 . 4 :

 54 Synthesis results of the proposed ONI using Reed-Solomon codes As it can be noticed, at BER = 10 -12 , the corresponding SN R of the channel with RS[START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5), H[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4), and uncoded are 12.11 dB, 14.26 dB, and 16.94 dB, respectively.

			Critical	Total	Static	Dynamic	Total
	TX	Amount	Path	Area	Power	Power	Power
			(ns)	(µm 2 )	(µW )	(mW )	(mW )
	RS Enc	1	0.4	251.3	3.28	1.190	1.200
	DEMUX	1	0.03	762	10.69	1.45	1.46
	Serializer	1	0.08	546.6	10	0.403	0.413
	TX Allocator	1	0.09	90.10	0.843	0.072	0.073
			Critical	Total	Static	Dynamic	Total
	RX	Amount	Path	Area	Power	Power	Power
			(ns)	(µm 2 )	(µW )	(mW )	(mW )
	RS Dec	1	0.4	2888.1	40.3	11.8	11.9
	MUX	1	0.8	676	10.8	1.55	1.56
	Deserializer	1	0.05	530.5	7.52	5.409	5.417
	RX Allocator	1	0.09	95.3	1.07	0.171	0.172
	H(71,64).

  Figure 5.13: BER performance comparison between Hamming and Reed-Solomon codes

				BER Comparision
		10 -10
		10 -20
	(BER)	10 -30
	Rate
	Error	10 -40
	Bit
		10 -50
		10 -60	Nocode H(7,4) H(71,64) RS(15,11,5)
	0	τ ENC	τ SER	τ TX-Allo	τ wg	τ RX-allo	τ DES	τ DEC	τ comm
	Source Cluster	Encoder	SER	Transmitted Allocator	optical waveguide	Receiver Allocator	DES	Decoder	Dest. Cluster

  Figure 5.15: Communication latency (τ comm ) of the proposed ONI using various FECs or no FEC as a function of the number of allocated wavelengths

				Communication time of ONI
		12 14				Nocode H(7,4) H(71,64) RS(15,11,5)
		10
	Tcomm(ns)	6 8
		4
		2
		1	2	3 Number of allocated wavelength 4 5	6	7	8

allocated wavelengths to send a message composed of 64 bits. According to the chart, the latency due to the interface using RS codes is the highest. This problem can be explained by the complexity of the decoder algorithm which can correct multiple errors compared to only one error with Hamming codes. In our implementation, the latency of RS

[START_REF] Chen | Error-Control Coding for Data Networks[END_REF][START_REF] Briere | System level assessment of an optical noc in an mpsoc platform[END_REF]5)

decoder takes 76 clock cycles with Berlekamp's algorithm decoding, whereas only one clock cycle is needed in the RS encoder. H

[START_REF] Bergman | Photonic Network-on-Chip Design[END_REF]4)

and H

Table 5 . 5 :

 55 Energy efficiency with two-level output currents

	Current Level	Driver Energy Consumption	Laser Energy Consumption
	(mA)	(pJ/bit)	(pJ/bit)
	4.2	0.102	0.904
	6	0.23	1.2

Table 5 . 6 :

 56 Energy efficiency with three-level output currents

	Current Level	Driver Energy Consumption	Laser Energy Consumption
	(mA)	(pJ/bit)	(pJ/bit)
	3.6	0.0687	0.837
	4.8	0.133	1.01
	6	0.23	1.2

Table 5 . 7 :

 57 Energy efficiency with five-level output currents Tables 5.5, 5.6, and 5.7 show that a considerable reduction in the energy consumption of the driver is achieved when the output current level is decreased. Therefore, by implementing the multi-level concept, we can save some energy consumption since the cost of additional hardware has a very minimal effect on the energy budget.

	Current Level	Driver Energy Consumption	Laser Energy Consumption
	(mA)	(pJ/bit)	(pJ/bit)
	3.12	0.045	0.77
	3.84	0.08	0.87
	4.5	0.115	0.96
	5.21	0.16	1.06
	6	0.23	1.2

Table 5 . 8 :

 58 Synthesis results of ONI manager according to number of MRs and the level of laser power

	Number	Level of	Number		Synthesis Reports
	of	Laser	of	Total	Static	Internal	Switching	Total
	Modes	Power	MRs	Area	Power	Power	Power	Power
				(µm)	(µW )	(µW )	(nW )	(µW )
			4	30.028 0.6055 0.0163	5.018	0.6268
			8	42.59 0.9688 0.02561	7.252	1.002
	3	5	16	63.158 1.313 0.03393	10.05	1.357
			32	85.843 1.873 0.05215	9.817	1.935
			64	172.50 3.463	0.1212	19.22	3.604

Table 5 . 9 :

 59 Example of ONoC configuration modes

	Modes Number of Steps
	Mode 0	5
	Mode 1	5
	Mode 2	10
	Mode 3	4
	Mode 4	6

Table 5 .

 5 10: Synthesis results of the OCS according to number of ONIs and number of modes

	Number	Number	Number		Synthesis Reports
	of	of	of	Critical	Total	Static	Dynamic	Total
	ONIs	Modes	Steps	Path	Area	Power	Power	Power
				(ns)	(µm)	(µW )	(µW )	(µW )
		5	10	0.89	41.126 0.8276	20.3	21.13
		5	128	0.80	67.075 1.241	33.00	34.25
		5	1024	0.73	92.371 1.604	51.40	53.02
	8	16	10	0.89	35.577 0.7269	20.6	21.37
		16	512	0.76	70.176 1.212	43.8	44.99
		16	1024	0.73	77.030 1.331	51.3	52.62
		32	10	0.89	35.904 0.7635	42.0	42.74
		5	10	0.89	44.553 0.8296	20.3	21.17
		5	128	0.80	70.502 1.253	33.2	34.45
		5	1024	0.73	95.798 1.615	53.0	54.59
	16	16	10	0.89	39.004 0.7392	20.7	21.48
		16	512	0.76	73.603 1.224	44.5	45.75
		16	1024	0.73	80.457 1.342	52.7	54.04
		32	10	0.89	39.331 0.7757	42.2	42.97
		5	10	0.89	51.408 1.142	20.4	21.56
		5	128	0.80	77.356 1.548	33.6	35.14
		5	1024	0.73	102.65 0.7392	20.7	21.48
	32	16	10	0.89	45.859 1.044	21.0	22.00
		16	512	0.76	80.457 1.452	46.1	47.59
		16	1024	0.73	73.929 1.266	50.3	51.56
		32	10	0.89	46.185 1.068	42.6	43.71

See http://www.itrs2.net/2011-itrs.html

The term "lasers" originated as an acronym for "light amplification by stimulated emission of radiation."

In coding theory, a systematic code is any error-correcting code in which the input data is embedded in the encoded output.

In channel coding theory, the BCH codes (Bose-Chaudhuri-Hocquenghem) form a class of cyclic error-correcting codes that are constructed using polynomials over a finite field (also called Galois field).

Qinit

Author's Publications

The following publications have been co-authored by the author of this thesis and partly rely on this thesis work [START_REF] Luo | Run-time management of energy-performance trade-off in optical network-on-chip[END_REF], [START_REF] Killian | Energy and performance trade-off in nanophotonic interconnects using coding techniques[END_REF], [START_REF] Luo | Performance and Energy Aware Wavelength Allocation on Ring-Based WDM 3D Optical NoC[END_REF], [START_REF] Luo | POSTER: Wavelength Allocation for Efficient Communications on Optical Network-on-Chip[END_REF], [START_REF] Van | Gestion de la consommation d'un onoc intégré dans un mpsoc[END_REF], [START_REF] Van | Gestion de la consommation d'un réseau optique intégré dans un MPSoC[END_REF].

List of Acronyms