Kees Goossens

John Dielissen

Om Prakash Gangwal

Santiago González Pestana

Andrei Rȃdulescu

Edwin Rijpkema

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The AEthereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims.

Introduction

A SOC is naturally composed of computation and storage elements (intellectual property blocks or IP) that are interconnected by communication elements (busses, networks on chip or NOC). In this paper, we focus on NOC interconnects because of their modularity, scalability, and other advantages for large SOCs.

Mature tooling exists to design individual IP, such as RTL synthesis and processor synthesis. Moreover, extensive IP re-use (of memories, processors, and application-specific blocks) is common practice. In contrast, an interconnect is specific to a SOC because the communication requirements depend on the composition of IP, which is application specific. Its design costs cannot be amortised over multiple SOCs, because it cannot be re-used whole. Tools for NOC synthesis are therefore essential for fast and efficient SOC design. These tools depend on the modularity of NOCs; i.e. (application-specific) NOCs are composed of two re-usable parametrised components: routers and network interfaces (NI).

In this paper we describe our design flow to dimension and generate application-specific NOC instances, given the communication requirements of the application. The NOC hardware (router and NI topology), and the IP port to NI port mapping are described in XML, which are translated to synthesisable RTL VHDL, and to Sys-temC. Minimum buffer sizes can also be computed. Every NOC instance is programmable, and its configuration (software) is generated in XML format for SystemC and VHDL simulation, and in C format for embedded processors in the SOC. VHDL simulation is bit and cycle-accurate, and SystemC transaction-level simulation is flit-accurate. If IP are not yet available for simulation, traffic generators are used that mimic their communication behaviour, as specified in the application communication requirements. A powerful new element in our design flow is performance verification, described below.

Impact of guaranteed NOC services on design flows

One of the major challenges in SOC design is ensuring that the SOC fulfills the (real-time) application requirements under all circumstances, such as video throughput and latency for set-top boxes, or packet loss and throughput for network processors. Assuming the IPs have the right performance (operations per second, storage capacity, etc.), we must generate a NOC with the right performance. We will show that using a NOC with guaranteed services (such as minimum throughput, maximum latency and jitter, etc.) as opposed to a best-effort NOC has important benefits for a design flow. In particular, this results in a fundamental difference in how performance is validated.

Using a NOC with best-effort services, any method can be used to generate a NOC. Then, the NOC performance must be validated by simulating the complete SOC (i.e. NOC and IPs) because the behaviours of IPs and NOC may be interdependent and influence each other. Simulation of a single trace is relatively slow, and the number of traces is huge. Therefore, given that not all possible traces can be simulated, no 100% guarantee can be given that performance requirements are met. Moreover, the performance observed in the simulated traces and the worst-case performance of a system may differ substantially, which means that adding a "safety margin" (e.g. sizing a buffer to twice the maximum observed during simulation) is not safe (e.g. see Section 3.6).

Only analysis can cover all cases. However, the distributed arbitration in NOCs often leads to statistical performance models [START_REF] Bolotin | QNoC: QoS architecture and design process for network on chip[END_REF][START_REF] Guerrier | Un Réseau D'Interconnexion pour Systémes Intégrés[END_REF], which offer no guarantee that performance requirements are always met. 1 NOCs with guaranteed services take provisions in their architectures to offer connections with guaranteed performance, such as absence of data loss, minimum throughput, and maximum latency. This enables analytical reasoning about NOC performance. Examples are AEthereal [START_REF] Gangwal | Building predictable systems on chip: An analysis of guaranteed communication in the AEthereal network on chip[END_REF][START_REF] Goossens | Guaranteeing the quality of services in networks on chip[END_REF], Nostrum [START_REF] Millberg | Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip[END_REF], aSOC [START_REF] Liang | aSOC: A scalable, single-chip communications architecture[END_REF], using time-division-multiple-access (TDMA) schemes, and [START_REF] Felicijan | An asynchronous on-chip network router with quality-ofservice (QoS) support[END_REF][START_REF] Kavaldjiev | A virtual channel router for on-chip networks[END_REF] using (virtual)-circuit-switching schemes.

NOC communication guarantees have several positive effects on the design flow. First, all IPs and the NOC are decoupled [START_REF] Sgroi | Addressing the system-on-a-chip interconnect woes through communication-based design[END_REF], meaning that the communication behaviour of one IP cannot affect that of other IPs. As a result, they can be designed and validated independently (compositionality). (In contrast to best-effort NOCs where all IPs and NOC have to simulated together.) Second, the NOC performance model can be used to generate an applicationspecific NOC that meets the communication requirements under all circumstances (correct by construction). Third, the performance of any given NOC (hand made, or generated by a tool) can be analytically verified to fulfill application requirements or not, instead of using simulation. As a result, verification time is shortened, and fewer design cycles are necessary. However, the use of guaranteed services relies on the explicit description of the communication requirements (or behaviour) of the IPs. This information is normally already available as part of the specification of SOC.

Overview

In this paper we describe a design flow that addresses the two problems that we identified above: the need for tools to quickly and efficiently generate application-specific NOCs, and the requirement for SOC and NOC performance validation. In Section 2 we describe the prerequisites for our NOC design flow. In Section 3 we define the design flow and explain its inputs (e.g. application requirements), outputs (NOC hardware and software, and resulting performance), and details of the individual tools (generation, configuration, verification, and simulation). We apply our design flow in Section 4, where we generate several NOCs for a MPEG SOC. [START_REF] Pinto | Efficient synthesis of networks on chip[END_REF] IPs and a single task graph containing 21 guaranteed connections, the tools automatically dimension and generate the Sys-temC and VHDL for a NOC with 3 routers and 6 NIs, and 21 traffic generators and their mapping. Including the configuration, buffer sizing and performance verification, this takes less than a minute. We review related work (Section 5), and conclude in Section 6.

NOC Design Flow Prerequisites

In this section we first describe the prerequisites for a design flow, independent of the NOC services.

To be able to generate an application-specific NOC, the NOC must be modular, i.e. be constructed of simpler, re-usable parametrised components: the router and network interface (NI). At design time, these components must be instantiated and connected in an appropriate topology. Moreover, the IP ports must be connected to particular NI ports (mapping). The result is a structural description (hardware) of the NOC. The router and NI of the AEthereal NOC have been documented in [START_REF] Rȃdulescu | An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming[END_REF][START_REF] Rijpkema | Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip[END_REF], here we mention only the relevant features. For the purposes of the design flow, the router is parametrised by its arity (number of input and output ports), and the best-effort queue sizes. Here, we fix the router link width to 32 bits. The NI is parametrised by the number of ports (to which IP ports can be connected, as specified in the mapping), the number of connections per port, and the buffer sizes per connection. The type of the IP and NI ports (AXI, various DTL profiles, their word width, etc.) is also a parameter, but kept fixed in this paper. The NOC as a whole is parametrised by the size of the slot table, and by the operating speed (500MHz in all examples, which is the speed of the router and NI implementations).

All instances of the AEthereal NOC are (re)configurable at run time. This means that the NIs can be (re)programmed at run-time, using standard memory-mapped IO ports on the NOC, to support a variety of connections [START_REF] Rȃdulescu | An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming[END_REF]. (Routers are stateless and require no configuration.) Within the NOC's hardware limits (number of connections per port, slot table size, credit counter bit widths, etc.) connections can be configured with different (guaranteed) properties, such as throughput and latency, by programming the path from master to slave, the number of slots and flow-control credits, etc. A configuration for a use case, is a list of NOC memory registers and their values.

The AEthereal NOC offers both best-effort and guaranteed services. The design flow described in this paper can be used for any mix of services. However, the advantage of NOCs with guaranteed services, as discussed at length in the introduction, is that the they implement router and NI arbitration schemes that allow analytical reasoning about the performance of guaranteed connections independently of the behaviour of other connections. This prerequisite is essential for correct-by-construction NOC generation and configuration, as well as compositional NOC performance verification (of any NOC, hand-made or generated), see Sections 3.3 to 3.5.

The final prerequisite for a design flow is the description of the application communication requirements. It is not possible to generate a NOC without knowing what the requirements of the application using it will be. This will be described in Section 3.1 because this information is given as an input to the design flow.

The prerequisites are therefore: a modular NOC offering guaranteed services with parametrised components (router, NI), and a description of the application requirements. The next section uses these foundations to offer a NOC design flow.

NOC Design Flow

Figure 1 shows the NOC design flow, which is fully implemented. Input files are underlined and shown at the top. The tools that we will discuss are shown by boxes; for simplicity some format conversion tools are not shown (in particular xls→XML, XML→VHDL, and XML→HTML). Below, we discuss each of the files and tools in turn. Although a major motivation for NOCs is their promise to improve back-end issues, such as global timing closure, we omit details of the "RTL synthesis and back-end."

First, however, note that NOC generation and configuration are interdependent, and part of one complex optimisation problem (find topology, mapping, and throughput assignments that minimise the number of routers, NIs, buffer sizes, and latencies). If this is done correctly (by construction), no performance verification and simulation is required (for guaranteed connections). Simulation is still useful, e.g. to check if the communication behaviour of IPs has been correctly characterised. With guaranteed services, this can be checked independently for every connection.

Nonetheless, our design flow has been split into separate tools (generation, configuration, verification) for several reasons. First, breaking the design flow in smaller steps, simplifies steering or overriding heuristics used in each of the individual tools, enhancing user control. Second, it reduces the complexity of optimisation problem, and simpler, faster heuristics can be used. Higherlevel optimisation loops involving multiple tools can then be easily added, such as the "smallest mesh loop," cf. Section 3.3. Third, parts of the flow can be more easily customised, added, or replaced by the user to tailor the flow or improve its performance. For example, mesh XY routing can be replaced by load-balancing turnprohibiting routing. Finally, redundancy in the sense of checking what should be generated automatically and correct by construction, such as simulation and performance verification (of guaranteed connections), minimises impact of potential programming errors, and acts as a safety net when allowing the user to manually create or modify intermediate results.

The design flow is very simple for the user. It is based on a makefile with few targets corresponding to the major activities: generate, configure, gtverify, simsystemc, and simvhdl. All files are in XML, which is human readable, but also robust and extensible. The user can use the flow in fully automatic mode (supply only the required underlined input files), or manually create or modify selected intermediate files (topology.xml, mapping.xml, configuration.xml, tg.xml). In case of manual intervention the remainder of the flow works automatically. For example, an automatically generated NOC can be configured manually, yet still have its performance automatically verified. The input files contain all information (options, settings, etc.), for deterministic batch-mode replay of results.

Specification of the Application Requirements

The starting point of the design flow is the description of the application's communication requirements (communication.xls,xml). An application consists of a number of task graphs, or use cases. Each of these contains a number of tasks, to be executed in hardware or software, using storage, and communicating using the NOC. For the design flow only the communication is relevant, i.e. which ports on which IPs communicate with each other. Figure 2 shows an example specification in Microsoft Excel. This is the de facto format for design documentation, and readily available from SOC designers. The Excel document is translated to XML, which the user can also write directly. An Excel document represents a single application, and each worksheet represents a single use case. (Currently, multiple use cases are entered as independent applications.) A use case is specified as a list of connections. A connection specifies a communication between a master port and a slave port, the required (minimum) bandwidth, the (maximum) allowed latency, and burst size for read and/or write data, and the traffic class (best-effort or guaranteed).

Specification of the IP

The second input file is the specification of the architecture around the NOC. The ip.xml file, an example of which is shown in Figure 3, contains a list of all IPs connected to the NOC and the IP ports. Each port has a number of attributes, such as protocol (AXI, various DTL profiles), and data word width. (Currently, all ports are of type DTL MMIO (memory-mapped IO) or MMBD (memorymapped block data), with 32-bit data words.) The ip.xml file is used to generate the right protocol-conversion shells for NIs [START_REF] Rȃdulescu | An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming[END_REF].

<architecture id="MPEG"> <IP id="display"> <initiator id="p1" protocol="MMBD" word="32"/> </IP> <IP id="decoder"> <initiator id="interp" protocol="MMBD" word="32"/> <initiator id="mc" protocol="MMBD" word="32"/> <initiator id="fifo" protocol="MMBD" word="32"/> </IP>

NOC Generation and IP Mapping

The first tool in the design flow is the NOC dimensioning and generation and IP mapping tool. It uses the application communication specification communication.xml, the IP specification ip.xml, and the NOC generation constraints constraints.xml. The tool defines the design-time hardware topology.xml: the number of routers, network interfaces, and topology. Parameters are specified for the NOC (flit duration, number of slots in TDMA table), for each router (arity, best-effort buffer size), and for each NI instance (number of NI ports, connections per port, buffer sizes per connection). To reduce NOC cost, all routers and NIs are dimensioned precisely for the application, giving many different router and NI instances per NOC. Modular router and NI architectures are therefore essential. Figure 4 shows a partial topology.xml.

<AENetwork id="MPEG" flitClk="6" slots="128"> <AERouter id="R0000" iq="8"> <AEPort id="NI" link="L_0000" /> <AEPort id="South" link="L_0000_0100" /> <AEPort id="West" link="L_0000_0001" /> </AERouter> <AENI id="NI0101"> <AEPort id="Router" link="L_0101" /> <SlaveP id="CONFIG" conn="1" iq="4" oq="4"/> <MasterP id="display.p1" conn="1" iq="40" oq="21"/> <MasterP id="decoder.mc" conn="1" iq="40" oq="21"/> <MasterP id="decoder.fifo" conn="1" iq="40" oq="21"/> ... </AENI> A synthesisable RTL VHDL description of the NOC is also produced, in a form compatible with the standard Philips back-end design flow. An area estimate of the NOC is given (using a model calibrated with existing router and NI implementations [START_REF] Rȃdulescu | An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming[END_REF][START_REF] Rijpkema | Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip[END_REF]).

The buffers per connection in the NIs are dimensioned to avoid stalling of data by hiding the round-trip delay of credits for lossless connections, and to compensate for difference in master and slave burst sizes. Although they are part of the hardware, they are not computed at this point in the design flow, because they depend on the configuration, which is computed later. As an example of the flexibility of the design flow, for guaranteed connections, the buffer sizes computed by the NOC performance validation tool can be back-annotated in the topology.xml file, as indicated by the dashed arrow labelled "buffer sizing" in Figure 1.

A second output is the mapping.xml file, containing the assignment of IP ports to NI ports. The mapping has a significant impact on the size (i.e. cost) of the NOC and its performance (e.g. Table 1). The constraints.xml file allows the user to influence the mapping by specifying if sets of ports must be mapped on the same NI or must be mapped on different NIs, to reflect e.g. floor-planning constraints. For example, <SameNI> <Module id="display"> <Module id="decoder" port="mc"/> </SameNI> places all IP ports of the display IP, and the decoder's mc port of Figure 4 on the same NI.

The NOC topology can be computed in three modes: either a mesh of given size is generated with a IP mapping, or the smallest mesh and IP mapping accommodating the application are generated, or a user-defined topology and IP mapping can be used. Automatic shortest-path routing can be used in all cases, and XY routing also in the first two cases. The computation of the smallest mesh and IP mapping for the given application, depends, like the buffer computation, on the configuration (e.g. the heuristic slot allocation may fail). The design flow therefore implements the automatic loop (the dashed arrow labelled "smallest mesh loop" in Figure 1) as the makefile target "minmesh." Determining the maximum slot table size, which is a hardware constant but also depends on the configuration, can be computed with a similar loop.

Briefly, the mapping algorithm works as follows, for both besteffort and guaranteed connections. It balances the IP port bandwidths over the NIs, clustering IP ports that communicate heavily on the same NI, and then minimising the distance (number of hops) between heavily communicating NIs, taking care not to overload any link. Packetisation overhead and latency constraints are ignored at this point.

NOC Configuration

The generation and mapping tool produces the design-time hardware (topology.xml and mapping.xml). Using these, the NOC configuration tool computes the run-time software that contains all the information to program the hardware. The configuration.xml file contains the values for all programmable registers of the NIs (the routers are stateless), such as connection identifiers, and for each connection, the path from master to slave port, and flow control credits. For connections with guaranteed throughput or latency (as specified by the user in communication.xls), a slot allocation must be determined (i.e. each hop along the path the slot increases by one, and at most one connection can use a given slot at a router [START_REF] Rijpkema | Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip[END_REF]).

The configuration algorithm works as follows. For each connection a path is generated, like by the mapping tool (or it can be supplied by the user). The flow control credits are equal to buffer sizes. Slots are allocated using a heuristic using a combination of each connection's path length and required bandwidth.

Figure 5 shows a partial configuration in (equivalent) XML and C. Section 3.6 describes how the configuration.xml and configuration.c files are used by the SystemC and RTL VHDL simulations.

<Connection master="decoder.mc" cidm="0" slave="mem.p2" cids="2"> <Request type="GT" path="3 1 0" credits="33" slots="22 23 24 25 26 27 28 29 30 31 32"/> <Response type="GT" slots="7 8 9 10 11 12 13" path="2 1 0" credits="21"/> </Connection> open_connection ("decoder.mc",0,"mem.p2",2, "GT","22-32","3 1 0",33, "GT","7-13","1",60); Using the topology and configuration the worst-case and average energy consumption of the NOC can be estimated [START_REF] Dielissen | Power measurements and analysis of a network on chip[END_REF]. This, and the area estimate of the NOC, computed from the topology, are important indicators of NOC cost. The verification and simulation steps, discussed below, compute the NOC performance.

NOC Verification

The rationale for decomposing the design flow into smaller tools has been given at the start of this section. Thus, the NOC hardware (topology.xml) and software (configuration.xml) are computed sequentially, earlier in the design flow. Therefore, the generation, mapping, and configuration tools must work with some simplifying assumptions (e.g. that NI buffers are adequately sized, ignore latency constraints). As a result, configuration (for guaranteed connections) may fail for a NOC topology and mapping, and latency constraints may not be met for a configured NOC.

For best-effort connections, the latter can only verified by simulation (next section). For guaranteed services, on the other hand, AEthereal's TDMA performance model can be analysed mathematically, and throughput, latency, and buffer sizes can be computed for the worst case [START_REF] Gangwal | Building predictable systems on chip: An analysis of guaranteed communication in the AEthereal network on chip[END_REF]. Therefore, although the generation and configuration tools do not generate NOCs that are correct by construction for the specified application, the final verification step checks whether the NOC topology and configuration are guaranteed to fulfill the application requirements or not. Any AEthereal topology and configuration, automatically or manually generated, can be verified against its application requirements.

Given the topology.xml, mapping.xml, configuration.xml files the verification tool computes the worst-case (minimum) throughput, (maximum) latency, and (minimum) buffer sizes per connection. These are compared to the requirements (communication.xml) and shown in an intuitive colour-coded table (gtperf.xml,html), cross-linked with communication.xml,html (Figure 6). Green entries meet the requirements, red ones do not. Yellow buffer sizes meet the requirements but are overdimensioned. It is possible (and, in fact, the norm) to automatically back-annotate the computed buffer sizes in the topology.xml file, as can be seen from the zero slack in the figure.

The verification checks each GT connection independently.

This compositionality is a useful consequence of AEthereal's TDMA model. The model is also relatively simple to reason about [START_REF] Gangwal | Building predictable systems on chip: An analysis of guaranteed communication in the AEthereal network on chip[END_REF]. As an example, a lossless (flow-controlled) request-only connection (e.g. writes without acknowledgements) consists of a outgoing (master→slave) channel for requests and a return (slave→master) channel for flow control. First, compute the amount of write data that can be sent in one slot table revolution. Then compute the worst-case duration to send a complete burst (this may take several slot table revolutions, and includes the worst-case wait for the initial slot). Add to this the latency in the routers (flit delay times the length of connection's path). As a complicating factor, the availability of request credits must be taken into account: this depends on the bandwidth and latency of the return channel, computed similarly. The sizes of the buffers at the master and slave for both outgoing and return channels are derived from the above computation. Note that to guarantee throughput or latency for a connection with only request transactions, the bandwidth and buffer sizes and credits must be sufficient on both the outgoing and return channels. Other types of connections are verified similarly.

NOC Simulation

The verification tool works for guaranteed connections only, and not for best-effort connections. Moreover, it computes worstcase throughput and latency numbers and buffer sizes, not actual or average figures. To assess the average performance of both guaranteed and best-effort connections for a particular execution trace two types of simulation are supported: RTL VHDL and SystemC. The former is a bit and cycle-accurate simulation of the RTL VHDL implementation. In the SystemC simulation, the NOC is simulated at the flit level, and the IP-NI interface is at the transaction level. The SystemC simulation is orders of magnitude faster than the VHDL simulation.

Simulation must be flexible to cope with automatically generated and configured NOCs. For this reason, our SystemC simulation is based on XML files for topology, mapping, NOC configuration, and IP configuration, to enable fast run-time NOC and IP instantiation and configuration [START_REF] Pestana | Cost-performance trade-offs in networks on chip: A simulation-based approach[END_REF].

The configuration is produced as an XML and C file (Figure 5). The XML file is used by the SystemC and VHDL simulation. The AEthereal NOC is configured through memory-mapped IO (MMIO) NOC ports (the id="CONFIG" port in Figure 4), using the NOC itself [START_REF] Rȃdulescu | An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming[END_REF]. In the VHDL simulation a behavioural IP configures the NOC, based on configuration.xml. The SystemC simulation can use configuration.xml directly, or model the MMIO programming.

The configuration.c file is intended to be run on an embedded processor connected to the NOC. The C file contains a function per use case, e.g. configure usecase one(), that (re)programs the NOC at run-time, using the MMIO port of processor's NI. For every connection an AEthereal library function (re/open/close connection) is called with the appropriate parameters (e.g. path, slots, credits; see Figure 5).

Traffic Generation and Measurements

SOC simulation requires that all IPs are available for simulation, as a model (e.g. at a behavioural or cycle-accurate level) or as an implementation. Early in the design cycle, this is usually not the case. To enable early SOC simulation to evaluate the NOC performance, our design flow produces XML-configurable SystemC and VHDL traffic generators, see Figure 1. All IP ports of IPs for which no model or implementation is available, are modelled with traffic generators. The traffic is generated according to the IP requirements as given in the communication.xls file. Traffic generators can be replaced by IP models, as these become available. At all times, however, a complete SOC can be simulated, in both SystemC and VHDL. The traffic generators also automate the measurement of throughput and latency of all connections in the NOC, for both SystemC and VHDL, and NI buffer statistics (SystemC only). The SystemC and/or VHDL results are reported in colourcoded tables (gtbe-*-perf.xml,html), cross-linked with communication.xml,html (Figure 7). Like the verification output (Section 3.5) green entries meet the requirements, and red ones do not. Due to simulation artifacts (random number generators in traffic generators, run-in effects due to insufficiently long simulation, etc.) a guaranteed connection may not use its required bandwidth (e.g. write data of connection 0). Note that this is due to the traffic generators, not the NOC: the bandwidth and latency of guaranteed connections is available, but it is not used.

Note that using simulation as a basis for e.g. buffer dimensioning can lead to buffers that are too small. Analytical performance evaluation shows that connection 3's write data requires a buffer of 54 words, but the maximum filling during simulation is only 8. Overdimensioning all buffers by the same factor of 7 = 54/8 , would lead to buffers that are up to 6 times too large (7x24 instead of 28, for connection 3), doubling the NOC size ("simulation," in Table 1). Of course, without verification, the factor 7 would have to be guessed in the first place.

MPEG Codec Case Study

We applied the design flow to an existing MPEG codec SOC with 16 IPs. The architecture uses a single external SDRAM with three ports to implement all communication between IPs. We specified the read and write bandwidths and latencies of the 21 guaranteed-throughput connections (Figure 2). Running the design flow in fully automatic mode (generating the minimum mesh and smallest slot table, with back-annotated minimum buffer sizes) resulted in a 2x3 mesh with 128 slots, with a total estimated area of 2.35 mm 2 in a 0.13 micron process, in minutes (cf. Table 1). Figures 4-7 refer to this NOC instance. For comparison, a naive mapping (one IP per NI) is almost double the size. "Simulation" shows that using simulation and a "safe" overdimensioning factor to determine buffer sizes (see Section 3.6), is more than twice as big. The average worst-case write latency per connection, computed by the performance verification tool, is more or less constant.

To highlight the scope for manual intervention, we also optimised the NOC. We explored several different IP-NI mappings to improve the IP distribution and clustering, to reduce the constraints on the routing and slot table configuration. A 21% smaller mesh (3x1, 1.86 mm 2 ) then suffices. Despite the resulting bandwidth overallocation, it also reduces the slot table (8 slots), and the latency (almost four-fold reduction of average worst-case write latency) and buffer sizes (compare Figures 6 and8). The minimum buffer sizes were computed by the verification tool and automatically back-annotated in the custom topology. The case study shows that the NOC design flow work generates a RTL VHDL implementation of a NOC, which has a guaranteed performance for the MPEG codec SOC. Retrofitting a NOC to an existing SOC architecture is possible, although for example, the single external memory underutilises the parallelism offered by NOCs. It also shows that manual optimisation gives worthwhile improvements for a small SOC. We are currently evaluating the design flow for a very large SOC, and will see if manual optimisations are still feasible (many IPs and many use cases) and significant.

Related Work

QNoC's design flow [START_REF] Bolotin | Automatic hardware-efficient SoC integration by QoS network on chip[END_REF] is similar to ours, but differs in relying on system simulation to verify SOC performance, expressed as statistical properties. They first generate the NOC topology generation and NI-IP mapping, followed by balancing bandwidth in the NOC, whereas we perform both at the same time.

XpipesCompiler [START_REF] Jalabert | XpipesCompiler: A tool for instantiating application specific networks on chip[END_REF] and NcGEN [START_REF] Chan | NoCGEN: a template based reuse methodology for networks on chip architecture[END_REF] generate optimised Sys-temC (and VHDL for NcGEN) descriptions for manually specified NOC topologies, which can be simulated together with traffic generators for performance validation. [START_REF] Hu | Energy-aware communication and task scheduling for networkon-chip architectures under real-time constraints[END_REF][START_REF] Murali | SUNMAP: A tool for automatic topology selection and generation for NOCs[END_REF][START_REF] Pinto | Efficient synthesis of networks on chip[END_REF] synthesise NOCs, map IPs, and/or configure NOCs based on bandwidth requirements and link bandwidths. However, when using worm-hole routing, the capacity of the links is not independent, especially in the presence of links of different speeds. (e.g. a packet spanning a slow and a fast link will reduce the capacity of the fast link, in the absence of virtual-channel buffering.) Applying these sophisticated synthesis and mapping algorithms to NOCs with guaranteed services, requiring the inclusion of NOC configuration, will be very beneficial for design flows, and speed up SOC and NOC design.

Conclusions

We have described a flexible operational design flow to generate application-specific network-on-chip (NOC) instances and configurations. The application's requirements are specified in Excel, which is readily available from system architects. Applicationspecific NOC instances, consisting of routers and network interfaces (NIs) are automatically dimensioned and generated. An IP-NI port mapping is also computed. The result is SystemC and synthesisable RTL VHDL, compliant with the Philips back-end flow.

The NOC hardware is run-time (re)programmable to support different task graphs. The configuration (software) to program the network is generated in XML (for SystemC and VHDL simulations) and in C for embedded processors that program the NOC using memory-mapped IO. The NOC hardware and configuration can be simulated in SystemC and VHDL, using custom traffic generators. These mimic the IP behaviour, as specified in the application requirements; thus, the SOC can be simulated at all times.

A unique feature of our design flow is the fast automatic performance verification: given the NOC hardware and configuration, the guaranteed minimum throughput, maximum latency, and minimum buffer sizes are analytically computed for all guaranteed connections. The guaranteed communication services of AEthereal are essential to achieve this. Any NOC instance and configuration can be verified, whether automatically or manually created. Analytical performance verification eliminates lengthy simulations for the guaranteed connections, and hence reduces verification time, leading to fewer design cycles.

Using the design flow we automatically generated and verified a NOC for an MPEG codec SOC (2x3 mesh, 2.35 mm 2 in 0.13 micron) in minutes. The design flow's flexibility was demonstrated by manually optimising a NOC, leading to a 21% area reduction.

Figure 1 .

 1 Figure 1. The AEthereal NOC Design Flow

Figure 2 .

 2 Figure 2. MPEG Application Communication Specification.

Figure 3 .

 3 Figure 3. Part of the IP description of MPEG example.

Figure 4 .

 4 Figure 4. Part of the Topology Description of MPEG example.

Figure 5 .

 5 Figure 5. Part of the MPEG example Configuration (XML and C).

Figure 6 .

 6 Figure 6. Performance Verification Output of MPEG example.

Figure 7 .

 7 Figure 7. SystemC Simulation Output of MPEG example.

Figure 8 .

 8 Figure 8. Performance Verification of Optimised MPEG.

Table 1 . Comparison of MPEG NOCs.

 1

				NI	router	total	area	avg wc
	generation	mesh	slots	area	area	area	diff	latency
	automatic	2x3	128	1.83	0.51	2.35	ref	1570 ns
	naive	3x6	128	2.17	2.32	4.49	+91%	1583 ns
	simulation	2x3	128	4.61	0.51	5.13	+118%	1570 ns
	optimised	3x1	8	1.51	0.35	1.86	-21%	399 ns

With 99.9% of packets meeting their required service[START_REF] Bolotin | QNoC: QoS architecture and design process for network on chip[END_REF], for every high-definition video frame

pixels are too late. Delayed control traffic (e.g. programming a DMA engine for every 100Hz frame) can have much larger impact, and would occur every 10 seconds.

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05)

Acknowledgement. S. González Pestana is supported by Marie Curie Fellowship IST-GH-99-80002-02.


Tim Xiao
email: tim.xiao@cibc.com

A Simple and Precise Method for Pricing Convertible Bond with Credit Risk

Keywords: hybrid financial instrument, convertible bond, convertible underpricing, convertible arbitrage, default time approach, default probability approach, jump diffusion

This paper presents a new model for valuing hybrid defaultable financial instruments, such as, convertible bonds. In contrast to previous studies, the model relies on the probability distribution of a default jump rather than the default jump itself, as the default jump is usually inaccessible. As such, the model can back out the market prices of convertible bonds. A prevailing belief in the market is that convertible arbitrage is mainly due to convertible underpricing. Empirically, however, we do not find evidence supporting the underpricing hypothesis. Instead, we find that convertibles have relatively large positive gammas. As a typical convertible arbitrage strategy employs delta-neutral hedging, a large positive gamma can make the portfolio highly profitable, especially for a large movement in the underlying stock price.

Introduction

A company can raise capital in financial markets either by issuing equities, bonds, or hybrids (such as convertible bonds). From an investor's perspective, convertible bonds with embedded optionality offer certain benefits of both equities and bonds -like the former, they have the potential for capital appreciation and like the latter, they offer interest income and safety of principal. The convertible bond market is of primary global importance.

There is a rich literature on the subject of convertible bonds. Arguably, the first widely adopted model among practitioners is the one presented by Goldman [START_REF] Sachs | Valuing convertible bonds as derivatives[END_REF] and then formalized by [START_REF] Tsiveriotis | Valuing convertible bonds with credit risk[END_REF]. The Goldman Sachs' solution is a simple one factor model with an equity binomial tree to value convertible bonds. The model considers the probability of conversion at every node. If the convertible is certain to remain a bond, it is then discounted by a risky discount rate that reflects the credit risk of the issuer. If the convertible is certain to be converted, it is then discounted by the risk-free interest rate that is equivalent to default free. [START_REF] Tsiveriotis | Valuing convertible bonds with credit risk[END_REF] argue that in practice one is usually uncertain as to whether the bond will be converted, and thus propose dividing convertible bonds into two components: a bond part that is subject to credit risk and an equity part that is free of credit risk. A simple description of this model and an easy numerical example in the context of a binomial tree can be found in [START_REF] Hull | Options, Futures and Other Derivatives[END_REF]. [START_REF] Grimwood | The valuation of convertible bonds: a study of alternative pricing models[END_REF] indicate that the Goldman Sachs model is incoherent because it assumes that bonds are susceptible to credit risk but equities are not. [START_REF] Ayache | The valuation of convertible bonds with credit risk[END_REF] conclude that the Tsiveriotis-Fernandes model is inherently unsatisfactory due to its unrealistic assumption of stock prices being unaffected by bankruptcy. To correct this weakness, [START_REF] Davis | Convertible bonds with market risk and credit risk[END_REF], [START_REF] Andersen | Calibration and implementation of convertible bond models[END_REF], Bloomberg (2009), and [START_REF] Carr | A jump to default extended CEV model: an application of Bessel processes[END_REF] etc., propose a jump-diffusion model to explore defaultable stock price dynamics. They all believe that under a risk-neutral measure the expected rate of return on a defaultable stock must be equal to the risk-free interest rate. The jumpdiffusion model characterizes the default time/jump directly.

The jump-diffusion model was first introduced by [START_REF] Merton | Option pricing when underlying stock returns are discontinuous[END_REF] in the market risk context for modeling asset price behavior that incorporates small day-to-day diffusive movements together with larger randomly occurring jumps. Over the last decade, people attempt to propagate the model from the market risk domain to the credit risk arena. At the heart of the jump-diffusion models lies the assumption that the total expected rate of return to the stockholders is equal to the risk-free interest rate under a riskneutral measure.

Although we agree that under a risk-neutral measure the market price of risk and risk preferences are irrelevant to asset pricing [START_REF] Hull | Options, Futures and Other Derivatives[END_REF] and thereby the expectation of a risk-free2 asset grows at the risk-free interest rate, we are not convinced that the expected rate of return on a defaultable asset must be also equal to the risk-free rate. We argue that unlike market risk, credit risk actually has a significant impact on asset prices. This is why regulators, such as International Accounting Standards Board (IASB),

Basel Committee on Banking Supervision (BCBS), etc. require financial institutions to report a credit value adjustment (CVA) in addition to the risk-free mark-to-market (MTM) value to reflect credit risk [START_REF] Xiao | An accurate solution for credit value adjustment (CVA) and wrong way risk[END_REF]. By definition, a CVA is the difference between the risk-free value and the risky value of an asset/portfolio subject to credit risk. CVA implies that the risk-free value should not be equal to the risky value in the presence of default risk. As a matter of fact, we will prove that the expected return of a defaultable asset under a risk-neutral measure actually grows at a risky rate rather than the risk-free rate.

This conclusion is very important for risky valuation.

Because of their hybrid nature, convertible bonds attract different type of investors. Especially, convertible arbitrage hedge funds play a dominant role in primary issues of convertible debt. In fact, it is believed that hedge funds purchase 70% to 80% of the convertible debt offered in primary markets. A prevailing belief in the market is that convertible arbitrage is mainly due to convertible underpricing (i.e., the model prices are on average higher than the observed trading prices) (see [START_REF] Ammann | Are convertible bonds underpriced? An analysis of the French market[END_REF], [START_REF] Calamos | Convertible arbitrage: Insights and techniques for successful hedging[END_REF][START_REF] Choi | Convertible bond arbitrage, liquidity externalities, and stock prices[END_REF], [START_REF] Loncarski | The rise and demise of the convertible arbitrage strategy[END_REF], etc.). However, [START_REF] Agarwal | Liquidity provision in the convertible bond market: analysis of convertible arbitrage hedge funds[END_REF] and [START_REF] Batta | Valuation consequences of convertible debt issuance[END_REF] argue that the excess returns from convertible arbitrage strategies are not mainly due to underpricing, but rather partly due to illiquid. [START_REF] Calamos | Convertible arbitrage: Insights and techniques for successful hedging[END_REF] believes that arbitrageurs in general take advantage of volatility. A higher volatility in the underlying equity translates into a higher value of the equity option and a lower conversion premium. Multiple views reveal the complexity of convertible arbitrage, involving taking positions in the convertible bond and the underlying asset that hedges certain risks but leaves managers exposed to other risks for which they reap a reward.

This article makes a theoretical and empirical contribution to the study of convertible bonds. In contrast to the above mentioned literature, we present a model that is based on the probability distribution (or intensity) of a default jump (or a default time) rather than the default jump itself, as the default jump is usually inaccessible (see [START_REF] Duffie | Swap rates and credit quality[END_REF], [START_REF] Jarrow | Structural versus reduced form models: a new information based perspective[END_REF], etc).

We model both equities and bonds as defaultable in a consistent way. When a firm goes bankrupt, the investors who take the least risk are paid first. Secured creditors have the best chances of seeing the value of their initial investments come back to them. Bondholders have a greater potential for recovering some their losses than stockholders who are last in line to be repaid and usually receive little, if anything.

The default proceedings provide a justification for our modeling assumptions: Different classes of securities issued by the same company have the same default probability but different recovery rates.

Given this model, we are able to back out the market prices.

Valuation under our risky model can be solved by common numerical methods, such as, Monte

Carlo simulation, tree/lattice approaches, or partial differential equation (PDE) solutions. The PDE algorithm is elaborated in this paper, but of course the methodology can be easily extended to tree/lattice or Monte Carlo.

Using the model proposed, we conduct an empirical study of convertible bonds. We obtain a data set from FinPricing (2017). The data set contains 164 convertible bonds and 2 years of daily market prices as well as associated interest rate curves, credit curves, stock prices, implied Black-Scholes volatilities and recovery rates.

The most important parameter to be determined is the volatility input for valuation. A common approach in the market is to use the at-the-money (ATM) implied Black-Scholes volatility to price convertible bonds. However, most liquid stock options have relatively short maturates (rarely more than 8 years). As a result, some authors, such as [START_REF] Ammann | Are convertible bonds underpriced? An analysis of the French market[END_REF], [START_REF] Loncarski | The rise and demise of the convertible arbitrage strategy[END_REF], [START_REF] Zabolotnyuk | An empirical comparison of convertible bond valuation models[END_REF], have to make do with historical volatilities. Therefore, we segment the sample into two sets according to maturity: a short-maturity class (0 ~ 8 years) and a long-maturity class (> 8 years). For the short-maturity class, we use the ATM implied Black-Scholes volatility for valuation, whereas for the long-maturity class, we calculate the historical volatility as the annualized standard deviation of the daily log returns of the last 2 years and then price the convertible bond based on this real-world volatility.

The empirical results show that the model prices fluctuate randomly around the market prices, indicating the model is quite accurate. Our empirical evidence does not support a systematic underpricing hypothesis. A similar conclusion is reached by [START_REF] Ammann | Simulation-based pricing of convertible bonds[END_REF] who use a Monte-Carlo simulation approach. Moreover, market participants almost always calibrate their models to the observed market prices using implied convertible volatilities. Therefore, underpricing may not be the main driver of profitability in convertible arbitrage.

It is useful to examine the basics of the convertible arbitrage strategy. A typical convertible bond arbitrage employs delta-neutral hedging, in which an arbitrageur buys a convertible bond and sells the underlying equity at the current delta (see [START_REF] Choi | Convertible bond arbitrage, liquidity externalities, and stock prices[END_REF], Loncarski et al (2009), etc.). With delta neutral positions, the sign of Gamma is important. If Gamma is negative, the portfolio profits so long as the underlying equity remains stable. If Gamma is positive, the portfolio will profit from large movements in the stock price in either direction [START_REF] Somanath | International financial management[END_REF].

We study the sensitivities of convertible bonds and find that convertible bonds have relatively large positive gammas, implying that convertible arbitrage can make a profit on a large upside or downside movement in the underlying stock price. Since convertible bonds are issued mainly by start-up or small companies (while more established firms rely on other means of financing), the chance of a large movement in either direction is very likely. Even for very small movements in the underlying stock price, profits can still be generated from the yield of the convertible bond and the interest rebate for the short position.

The rest of this paper is organized as follows: The model is presented in Section 2. Section 3 elaborates the PDE approach; Section 4 discusses the empirical results. The conclusions are provided in Section 5. Some numerical implementation details are contained in the appendices.

Model

Convertible bonds can be thought of as normal corporate bonds with embedded options, which enable the holder to exchange the bond asset for the issuer's stock. Despite their popularity and ubiquity, convertible bonds still pose difficult modeling challenges, given their hybrid nature of containing both debt and equity features. Further complications arise due to the frequent presence of complex contractual clauses, such as, put, hard call, soft call, and other path-dependent trigger provisions. Contracts of such complexity can only be solved by numerical methods, such as, Monte Carlo simulation, tree/lattice approaches, or PDE solutions.

From a practitioner's perspective, Monte Carlo is a "last resort" and "least preferred" method, whereas lattice or PDE approaches suffer from the curse of dimensionality: The number of evaluations and computational cost increase exponentially with the dimension of the problem, making it impractical to use in more than two dimensions.

Three sources of randomness exist in a convertible bond: the stock price, the interest rate, and the credit spread. As practitioners tend to eschew models with more than two factors, it is a legitimate question: How can we reduce the number of factors or which factors are most important? [START_REF] Grimwood | The valuation of convertible bonds: a study of alternative pricing models[END_REF] conduct a sensitivity study and find that accurately modeling the equity process appears crucial. This is why all convertible bond models in the market capture, at a minimum, the dynamics of the underlying equity price. Since convertible bonds are issued mainly by start-up or small companies (while more established firms rely on other means of financing), credit risk plays an important role in the valuation. [START_REF] Grimwood | The valuation of convertible bonds: a study of alternative pricing models[END_REF] further note that the interest rate process is of second order importance. Similarly, [START_REF] Brennan | Analyzing convertible bonds[END_REF] conclude that the effect of a stochastic interest rate on convertible bond prices is so small that it can be neglected. Furthermore, [START_REF] Ammann | Simulation-based pricing of convertible bonds[END_REF] notice that the overall pricing benefit of incorporating stochastic interest rates would be very limited and would not justify the additional computational costs. For these reasons, most practical convertible models in the market do not take stochastic interest rate into account.

We consider a filtered probability space (  , F ,   0

 t t F , P ) satisfying the usual conditions,
where  denotes a sample space, F denotes a  -algebra, P denotes a probability measure, and

  0  t t F denotes a filtration.
The risk-free stock price process can be described as

) ( ) ( ) ( ) ( ) ( t dW t S dt t S t r t dS    (1)
where

) (t S denotes the stock price, ) (t r
denotes the risk-free interest rate,  denotes the volatility,

) (t W
denotes a Wiener process.

The expectation of equation ( 1) is

  dt t S t r t dS E t ) ( ) ( ) (  F (2) where   t E F  is the expectation conditional on the t F .
Equation (2) tells us that in a risk-neutral world, the expected return on a risk-free stock is the risk-free interest rate ) (t r , i.e., the discounted stock price under the risk neutral measure is a martingale process.

Next, we turn to a defaultable stock. The defaultable stock process proposed by [START_REF] Davis | Convertible bonds with market risk and credit risk[END_REF], [START_REF] Andersen | Calibration and implementation of convertible bond models[END_REF][START_REF] Andersen | Calibration and implementation of convertible bond models[END_REF]Bloomberg (2009), etc., is given by

  ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( t dU t S t dW t S dt t S t h t r t dS         (3) where ) (t U is an independent Poisson process with 1 ) (  t dU
with probability dt t h ) ( and 0 otherwise,

) (t h is the hazard rate or the default intensity, ) (  t S
is the stock price immediately before any jump at time t. The expectation of

) (t dU is dt t h t dU E t ) ( ) ) ( (  F .
The expectation of equation ( 3) is given by

    dt t S t r dt t h t S dt t S t h t r t dS E t ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) (     F (4)
It is shown in equation ( 4) that the expected return of a defaultable stock under a jump-diffusion model also grows at the risk-free interest rate. Equation ( 3) is a simpler version of the Merton's Jumpdiffusion model where the number of jumps is 1.

The jump-diffusion model was first proposed in the context of market risk, which naturally exhibits high skewness and leptokurtosis levels and captures the so-called implied volatility smile or skew effects. [START_REF] Ederington | How markets process information: News releases and volatility[END_REF] find that the markets tend to have overreaction and underreaction to the outside news. The jump part of the model can be interpreted as the market response to outside news. If there is not any outside news, the asset price changes according to a geometric Brownian motion. Since the market price of risk and risk preferences are irrelevant to asset pricing within the market risk context, the expected rate of return to the stockholders is equal to the risk-free rate under a risk-neutral measure.

However, we wonder whether it is appropriate to propagate the jump-diffusion model directly from the market risk domain to the credit risk domain, as credit risk actually impacts the valuation of assets. This is why financial institutions are required by regulators to report CVA. In fact, we will show in the following derivation that the expected return of a defaultable asset under a risk-neutral measure is actually equal to a risky rate instead of the risk-free rate. This conclusion is very important for risky valuation.

The world of credit modeling is divided into two main approaches: structural models and reduced-form (or intensity) models. The structural models regard default as an endogenous event, focusing on the capital structure of a firm. The reduced-form models do not explain the event of default endogenously, but instead characterize it exogenously as a jump process. In general, structural models are based on the information set available to the firm's management, such as the firm's assets and liabilities; while reduced-form models are based on the information set available to the market, such as the firm's bond prices or credit default swap (CDS) premia. Many practitioners in the credit trading arena have tended to gravitate toward the reduced-from models given their mathematical tractability. The reduced-form models can be made consistent with the risk-neutral probabilities of default backed out from corporate bond prices or CDS spreads/premia.

In the reduced-form models, the stopping (or default) time  of a firm is modeled as a Cox arrival process (also known as a doubly stochastic Poisson process) whose first jump occurs at default and is defined as, It is well-known that the survival probability from time t to s in this framework is defined by

       t
            s t du u h Z t s P s t p ) ( exp ) , | ( : ) , (   (6)
The default probability for the period (t, s) in this framework is given by

               s t du u h s t p Z t s P s t q ) ( exp 1 ) , ( 1 ) , | ( : ) , (   (7)
We consider a defaultable asset that pays nothing between dates t and T. Let ) (t V and ) (T V denote its values at t and T, respectively. Risky valuation can be generally classified into two categories: the default time approach (DTA) and the default probability (intensity) approach (DPA).

The DTA involves the default time explicitly. If there has been no default before time T (i.e.,

T   ), the value of the asset at T is ) (T V . If a default happens before T (i.e., T t  
), a recovery payoff is made at the default time  as a fraction of the market value 3 given by

) (

V

where  is the default recovery rate and ) ( V is the market value at default. Under a risk-neutral measure, the value of this defaultable asset is the discounted expectation of all the payoffs and is given by

    t T T V t D T V T t D E t V F | 1 ) ( ) , ( 1 ) ( ) , ( ) (          (8)
3 Here we use the recovery of market value (RMV) assumption.

where Y  is an indicator function that is equal to one if Y is true and zero otherwise, and ) , (  t D denotes the stochastic risk-free discount factor at t for the maturity  given by

         du u r t D t   ) ( exp ) , ( (9)
Although the DTA is very intuitive, it has the disadvantage that it explicitly involves the default time/jump. We are very unlikely to have complete information about a firm's default point, which is often inaccessible. Moreover, in a derivative transaction, the market-value-at-default ) ( V usually reflects the replacement cost of the transaction, where the replacement is also defaultable 4 . Therefore ) ( V should be determined via another risky valuation and so forth. Usually, valuation under the DTA is performed via Monte Carlo simulation.

The DPA relies on the probability distribution of the default time rather than the default time itself. We divide the time period (t, T) into n very small time intervals ( t  ) and assume that a default may occur only at the end of each very small period. In our derivation, we use the approximation

  y y  1 exp
for very small y. The survival and default probabilities for the period ( t , t t   ) are given by

  t t h t t h t t t p t p          ) ( 1 ) ( exp ) , ( : ) ( ˆ (10)   t t h t t h t t t q t q          ) ( ) ( exp 1 ) , ( : ) ( ˆ (11)
The binomial default rule considers only two possible states: default or survival. and the default payoff is a fraction of the market value:

) ( ) ( t t V t t     
. Under a risk-neutral measure, the value of the asset at t is the expectation of all the payoffs discounted at the risk-free rate and is given by 4 Many people in the market use the risk-free value as the market-value-at-default, which is inappropriate as any contract in the OTC market is risky when taking counterparty risk into account.

         t t t t V t t y E t t V t q t t p t t r E t V F F ) ( ) ( exp ) ( ) ( ) ( ) ( ) ( exp ) (             (12) where   ) ( ) ( ) ( 1 ) ( ) ( ) ( t c t r t t h t r t y      
denotes the risky rate and

  ) ( 1 ) ( ) ( t t h t c    is called the (short) credit spread.
Similarly, we have

    t t t t V t t t y E t t V            F ) 2 ( ) ( exp ) ( (13)
Note that

  t t y   ) ( exp is t t F   -measurable.
                t i t t t t t t V t t i t y E t t V t t t y E t t y E t t V t t y E t V F F F F ) 2 ( ) ) ( exp ) 2 ( ) ( exp ) ( exp ) ( ) ( exp ) ( 1 0                          (14)
By recursively deriving from t forward over T and taking the limit as t  approaches zero, the risky value of the asset can be expressed as

               t T t T V du u y E t V F ) ( ) ( exp ) ( (15)
Using the DPA, we obtain a closed-form solution for pricing an asset subject to credit risk.

Another good example of the DPA is the CDS model proposed by J.P. [START_REF] Morgan | The J. P. Morgan guide to credit derivatives[END_REF].

The derivation of equation ( 15) takes into account all credit characteristics: possibility of a jump to default and recovery rate. It tells us that a defaultable asset under the risk-neutral measure grows at a risky rate. The risky rate is equal to a risk-free interest rate plus a credit spread. If the asset is a bond, the equation is the same as Equation ( 10) in [START_REF] Duffie | Modeling term structure of defaultable bonds[END_REF], which is the market model for pricing risky bonds. The market bond model says that the value of a risky bond is obtained by discounting the promised payoff using the risk-free interest rate plus the credit spread 5 .

5 There is a liquidity component in the bond spread. This paper, however, focuses on credit risk only.

Under a risk-neutral measure the market price of risk and risk preferences are irrelevant to asset pricing [START_REF] Hull | Options, Futures and Other Derivatives[END_REF] and thereby the expectation of a risk-free asset grows at the risk-free interest rate.

However, credit risk actually has a significant impact on asset prices. This is the reason that regulators, such as IASB and BCBS, require financial institutions to report a CVA in addition to the risk-free MTM value to reflect credit risk.

In asset pricing theory, the fundamental no-arbitrage theorems do not require expected returns to be equal to the risk free rate, but only that prices are martingales after discounting under the numeraire.

For risk-free valuation, people commonly use a risk-free bond as the numeraire, whereas for risky valuation, they should choose an associated risky numeraire to reflect credit risk. The expected return is that of the numeraire.

If a company files bankruptcy, both bonds and stocks go into a default status. In other words, the default probabilities for both of them are the same (i.e., equal to the firm's probability of default). But the recovery rates are different because the stockholders are the lowest priority in the list of the stakeholders in the company, whereas the bondholders have a higher priority to receive a higher percentage of invested funds. The default proceedings provide a justification for our modeling assumptions: Different classes of securities issued by the same company have the same default probability but different recovery rates.

According to equation ( 15), we propose a risky model that embeds the probability of the default jump rather than the default jump itself into the price dynamics of an asset. The stochastic differential equation (SDE) of a defaultable stock is defined as Equation ( 16) is the direct derivation of equation ( 15). The formula allows different assumptions concerning recovery on default. In particular, 0  s  represents the situation where the stock price jumps to 0, and 1  s  corresponds to the risk-free case. The expectation of equations ( 16) is

  ) ( ) ( ) ( ) ( ) ( ) ( ) ( )) ( 1 )( ( ) ( ) ( t
    dt t S t t h t r t dS E s t ) ( )) ( 1 )( ( ) ( ) (     F (17)
Equation ( 17) says that the expected return of a stock subject to credit risk is equal to a risky rate rather than the risk-free rate. The risky rate reflects the compensation investors receive for bearing credit risk.

PDE Algorithm

The numerical solution of our risky model can be obtained by either PDE methods, tree approaches, or Monte Carlo simulation. In this paper, we introduce the PDE procedure, but of course the methodology can be easily extended to the tree/lattice or Monte Carlo algorithms.

The defaultable stock price process is given by

  ) ( ) ( ) ( ) ( ) ( ) ( ) ( )) ( 1 )( ( ) ( ) ( ) ( t dW t S dt t S t t dW t S dt t S t t h t q t r t dS s            (18)
where )

(t q is the dividend and )) ( 1 )( ( ) ( ) ( ) ( t t h t q t r t s       .
The valuation of a convertible bond normally has a backward nature since there is no way of knowing whether the convertible should be converted without knowledge of the future value. Only on the maturity date, the value of the convertible and the decision strategy are clear. If the convertible is certain to be converted, it behaves like a stock. If the convertible is not converted at an intermediate node, we are usually uncertain whether the continuation value should be treated as a bond or a stock, because in backward induction the current value takes into account the results of all future decisions and some future values may be dominated by the stock or by the bond or by both. Therefore, we arrange the valuation so that the value of the convertible at each node is divided into two components: a component of bond and a component of stock, i.e.

dW S G S dt S G S t G S G S dG                        2 2 2 2 2 1 (19)
Since the Wiener process underlying S and G are the same, we can construct the following portfolio so that the Wiener process can be eliminated.

S G S G X     (20) Therefore, we have dt S G S t G dS S G dG dX                   2 2 2 2 2 1  (21)
In contrast to all previous studies, we believe that the defaultable equity should grow at the risky rate of the equity including dividends, whereas the equity part of the convertible bond should earn the risky rate of the equity excluding dividends, i.e.,

    dt S G S t G dX Sdt S G h q r Gdt h r s s                        2 2 2 2 2 1 ) 1 ( ) 1 (    (22)
So that the PDE of the equity component is given by

    0 ) 1 ( ) 1 ( 2 1 2 2 2 2                G h r S G S h q r S G S t G s s    (23)
Similarly applying Ito Lemma to the bond part of the convertible ) , ( t S B

, we obtain

dW S B S dt S B S t B S B S dB                        2 2 2 2 2 1 (24)
Let us construct a portfolio so that we can eliminate the Wiener process as follows

S B S B Y     (25) Thus, we have dt S B S t B dS S B dB dY                   2 2 2 2 2 1  (26)
The defaultable equity should grow at the risky rate of the equity including dividends, while the bond part of the convertible bond grows at the risky rate of the bond. Consequently, we have

    dt S B S t B dY Sdt S B h q r Bdt h r s b                        2 2 2 2 2 1 ) 1 ( ) 1 (    (27)
where b  is the recovery rate of the bond.

The PDE of the bond component is

    0 ) 1 ( ) 1 ( 2 1 2 2 2 2                B h r S B S h q r S B S t B b s    (28)
Equations ( 23) and ( 28) are coupled through appropriate final and boundary conditions reflecting the terms and conditions of each individual convertible and need to be solved simultaneously. Convertible bonds often incorporate various additional features, such as call and put provisions.

The final conditions at maturity T can be generalized as The upside constraints at time One can use finite difference methods to solve the PDEs ( 23) and ( 28) for the price of a convertible bond.

          otherwise C N P P S if S G p c T T T , 0 , max , min ,   (29)               
] , 0 [ T t  are                       else B B G G P L if else P B G P L if else P B G L P P S if B S G t t

Empirical results

This section presents the empirical results. We use two years of daily data from September 10, 2010 to September 10, 2012, i.e., a total of 522 observation days. This proprietary data are obtained from an investment bank. They consist of convertible bond contracts, market observed convertible prices, interest rate curves, credit curves, stock prices, implied Black-Scholes volatilities and recovery rates.

We only consider the convertibles outstanding during the period and with sufficient pricing information. As a result, we obtain a final sample of 164 convertible bonds and a total of 164 × 522 = 85,608 observations. None of the convertibles in this sample actually defaulted during the time window.

As of September 10, 2012, the sample represents a family of convertible bonds with maturities ranging from 2 months to 36.6 years, and has an average remaining maturity of 4.35 years. The histogram of contracts on September 10, 2012 for various maturity classes is given in Figure 1.

Convertible bond prices observed in the market will be compared with theoretical prices under different volatility assumptions. The sample is segmented into two sets according to maturities: a shortmaturity class (0 ~ 8 years) and a long-maturity class (> 8 years). We first select a convertible bond from each group: a 7-year (or 5-year outstanding) contract and a 20-year (or 17-year outstanding) contract shown in Table 1.

Figure 1. Maturity distribution of convertible bonds

This histogram splits the total number of convertible bonds of the sample into different classes according to the maturity of each convertible bond. The x-axis represents maturities in years and the y-axis represents the number of convertibles in each class. The n maturity class covers contracts with maturities ranging from n-1 years to n years.

Table 1. Convertible bond examples

We hide the issuer names according to the security policy of the investment bank, but everything else is authentic. In the market, either a conversion price or a conversion ratio is given for a convertible bond,

where conversion ratio = (face value of the convertible bond) / (conversion price). products for certain time horizons. Normally the curve is divided into three parts. The short end of the term structure is determined using the London Interbank Offered Rates (LIBOR). The middle part of the curve is constructed using Eurodollar futures that require convexity adjustments. The far end is derived using mid swap rates. The LIBOR-future-swap curve is presented in Table 2. We bootstrap the curve and get the continuously compounded zero rates. Consequently, prices and spreads derived from the CDS market tend to be more reliable. Said differently, CDSs on reference entities are often more actively traded than bonds issued by the same entities.

Convertible bond

Unlike other studies that use bond spreads for pricing (see [START_REF] Tsiveriotis | Valuing convertible bonds with credit risk[END_REF], [START_REF] Ammann | Are convertible bonds underpriced? An analysis of the French market[END_REF], [START_REF] Zabolotnyuk | An empirical comparison of convertible bond valuation models[END_REF], etc.), we perform risky valuation based on credit information extracted from CDS spreads. Given the recovery rates and the CDS premia, we can compute the hazard rates via a standard calibration process (J.P. [START_REF] Morgan | The J. P. Morgan guide to credit derivatives[END_REF]. The most important input parameter to be determined is the volatility for valuation. A common approach in the market is to use ATM implied Black-Scholes volatilities to price convertible bonds. For the 5-year outstanding convertible bond (case 1 in Table 1), we find the ATM implied Black-Scholes volatility is 31.87%, and then price the convertible bond accordingly. The results are shown in Table 5.

Our analysis actually indicates an overpricing of 0.42%.

For the 17-year outstanding convertible bond (case 2 in Table 1), however, most liquid stock options have relatively short maturates (rarely more than 8 years). Therefore, some authors, such as [START_REF] Ammann | Are convertible bonds underpriced? An analysis of the French market[END_REF], [START_REF] Loncarski | The rise and demise of the convertible arbitrage strategy[END_REF], [START_REF] Zabolotnyuk | An empirical comparison of convertible bond valuation models[END_REF], have to make do with historical volatilities. Similarly, we calculate the historical volatility as the annualized standard deviation of the daily log returns of the last 2 years (from September 10, 2010 to September 10, 2012), and then value the convertible bond based on this real-world volatility. The result shown in Table 5 reports an underpricing of 1.07%. The test results demonstrate that the model prices are very close to the market prices, indicating that the model is quite accurate.

Table 5. Model prices vs. market prices

This table shows the differences between the model prices and the market prices of the convertible bonds under different volatility assumptions, where Difference = (Model price) / (Market observed price) -1.

The convertible bonds are defined in Table 1.

Case 1 (a 7-year convertible) Case 2 (a 20-year convertible) We repeat this exercise for all contracts on all observation dates. For any short-maturity convertible bond, we use the ATM implied Black-Scholes volatility for pricing, whereas for any longmaturity convertible bond, we perform valuation via the historical volatility. The results are presented in Tables 6.

Table 6. Underpricing statistics for different maturity classes

An observation corresponds to a price snapshot of a convertible bond at a certain valuation date.

Underpricing is referred to as the model price minus the market price. Next, our sample is partitioned into subsamples according to the moneyness of convertibles. The moneyness is measured by the ratio of the conversion value to the equivalent straight bond value or the investment value. The underpricing of each daily observation with respect to the degree of moneyness is shown in Table 7, where moneyness between 0 and 0.9 corresponds to out-of-the-money; moneyness between 0.9 and 1.1 represents around-the-money; and moneyness higher than 1.1 is related to in-themoney.

Maturity

Table 7. Underpricing statistics for different moneyness classes

The moneyness is measured by dividing the conversion value through the associated straight bond value.

An observation corresponds to a snapshot of the market used to price a convertible bond at a certain valuation date. From Tables 7, it can be seen that the model prices fluctuate randomly around the market prices (sometimes overpriced and sometimes underpriced), indicating the model is quite accurate. Empirically, we do not find support for presence of a systematic underpricing as indicated in previous studies (see [START_REF] Carayannopoulos | Convertible bond prices and inherent biases[END_REF], [START_REF] Ammann | Are convertible bonds underpriced? An analysis of the French market[END_REF], etc.). If there is no underpricing, how has the arbitrage strategy been successful in the past? Maybe convertible arbitrage is not solely based on underpricing.

Moneyness

In a typical convertible bond arbitrage strategy, the arbitrageur entails purchasing a convertible bond and selling the underlying stock to create a delta neutral position. The number of shares sold short usually reflects a delta-neutral or market neutral ratio. It is well known that delta neutral hedging not only removes small directional risks but also is capable of making a profit on an explosive upside or downside breakout if the position's gamma is kept positive. As such, delta neutral hedging is great for uncertain stocks that are expected to make huge breakouts in either direction. Since convertible bonds are issued mainly by start-up or small companies, the chance of a large movement in either direction is very likely.

Even for very small movements in the underlying stock price, profits can still be generated from the yield of the convertible bond and the interest rebate for the short position.

We calculate the delta and gamma values for the two deals described in table 1. The Greek vs.

spot equity price graphs are plotted in Figures 2~ 5. It can be seen that the deltas increase with the underlying stock prices in Figures 2 and4. At low market levels, the convertibles behave like their straight bonds with very small deltas. As the stock price increases, conversion becomes more likely. At certain market levels the convertibles are certain to be converted. In this case, the convertibles are similar to the underlying equities and the deltas are equal to the number of shares (i.e., conversion ratios). This graph shows how the delta of the 7-year convertible bond (described in Table 1) changes as the underlying stock price changes. This graph shows how the gamma of the 7-year convertible bond (described in Table 1) changes as the underlying stock price changes. This graph shows how the delta of the 20-year convertible bond (described in Table 1) changes as the underlying stock price changes.

Figure 5. Gamma variation with spot price for a 20-year convertible bond

This graph shows how the gamma of the 20-year convertible bond (described in Table 1) changes as the underlying stock price changes.

The gamma diagrams in Figures 3 and5 have a frown shape. The gammas are the highest when the convertibles are at-the-money. It is intuitive that when the stock prices rise or fall, profits increase because of favorably changing deltas. For this reason, convertible bonds are very good candidates for delta neutral hedging. Relatively large positive gammas of convertibles could be one of the main drivers of profitability in convertible arbitrage.

Conclusion

This paper aims to price hybrid financial instruments (e.g., convertible bonds) whose values may simultaneously depend on different assets subject to credit risk in a proper and consistent way. The motivation for our model is that if a company goes bankrupt, all the securities (including the equity) of the company default. The recovery is realized in accordance with the priority established by the Bankruptcy Code. In other words, different securities have the same probability of default, but different recovery rates.

Our study shows that risky asset pricing is quite different from risk-free asset pricing. In fact, the expectation of a defaultable asset actually grows at a risky rate rather than the risk-free rate. This conclusion is vital for risky valuation.

We propose a hybrid framework to value risky equities and debts in a unified way. The model relies on the probability distribution of the default jump rather than the default jump itself. As such, the model can achieve a high order of accuracy with a relatively easy implementation.

Empirically, we do not find evidence supporting a systematic underpricing hypothesis. We also find that convertible bonds have relatively large positive gammas, implying that convertible arbitrage can make a significant profit on a large upside or downside movement in the underlying stock price.

Appendix

In this section, we describe the numerical method used to solve discrete forms of ( 23) and (28). 23) and ( 28) can be rewritten as

  0 ) 1 ( 2 ) 1 ( 2 1 2 2 2 2                         B h r x B h q r x B B b s      (A1)   0 ) 1 ( 2 ) 1 ( 2 1 2 2 2 2                         G h r x G h q r x G G s s      (A2)
The equations (A1) and (A2) can be approximated using Crank-Nicolson rule. We discretize the x to be equally spaced as a grid of nodes 0 ~ M. At the maturity, T G and T B are determined according to (29) and (30). At any time i+1, the boundary conditions are

                          0 ) )) 1 ( ( 5 .

  where N denotes the bond principal, C denotes the coupon, denotes the conversion ratio. The final conditions tell us that the convertible bond at the maturity is either a debt or an equity.

  continuation value of the equity component. Equation (31) says that the convertible is either in the continuation region or one of the three constraints (called, put or converted).

Figure 2 .

 2 Figure 2. Delta vs spot price graph for a 7-year convertible bond

Figure 3 .

 3 Figure 3. Variation in gamma vs. spot price for a 7-year convertible bond

Figure 4 .

 4 Figure 4. Delta plotted against changing spot price for a 20-year convertible bond

  By definition, an

	variable is a random variable whose value is known at time known and tower properties of conditional expectation, we have	t  . Based on the taking out what is t  -measurable random t t  F 

Case 1 (a 7-year convertible) Case 2 (a 20-year convertible)

  Let valuation date be September 10, 2012. An interest rate curve is the term structure of interest rates, derived from observed market instruments that represent the most liquid and dominant interest rate

	Issuer	X company	Y company
	Principal of bond	100	100
	Annual coupon rate	2.625	5.5
	Payment frequency	Semiannual	Semiannual
	Issuing date	June 9, 2010	June 15, 2009
	Maturity date	June 15, 2017	June 15, 2029
	Conversion price	30.288	13.9387
	Currency	USD	USD
	Day count	30/360	30/360
	Business day convention	Following	Following
	Put price	-	100 at June 20, 2014

Table 2 : A list of instruments used to build a USD interest rate curve

 2 This table displays the closing prices as of September 10, 2012. These instruments are used to construct an interest rate curve.The equity information and recovery rates are provided in Table3. To determine hazard rates, we need to know the observed market prices of corporate bonds or CDS premia, as the market standard practice is to fit the implied risk-neutral default intensities to these credit sensitive instruments. The corporate bond prices are unfortunately not available for companies X and Y, but their CDS premia are observable as shown in Table4. Usually the CDS market leads the bond market, in particular during crisis situation. Liquidity in the bond market is typically drying up during a financial crisis. Demand for insurance against default risk, on the other hand, increases if the issuer is experiencing financial stress.

	Instrument Name	Price
	September 19, 2012 LIBOR	0.6049%
	September 2012 Eurodollar 3 month	99.6125
	December 2012 Eurodollar 3 month	99.6500
	March 2013 Eurodollar 3 month	99.6500
	June 2013 Eurodollar 3 month	99.6350
	September 2013 Eurodollar 3 month	99.6200
	December 2013 Eurodollar 3 month	99.5900
	March 2014 Eurodollar 3 month	99.5650
	2 year swap rate	0.3968%
	3 year swap rate	0.4734%
	4 year swap rate	0.6201%
	5 year swap rate	0.8194%
	6 year swap rate	1.0537%
	7 year swap rate	1.2738%
	8 year swap rate	1.4678%
	9 year swap rate	1.6360%
	10 year swap rate	1.7825%
	12 year swap rate	2.0334%

Table 3 . Equity and recovery information

 3

	This table displays the closing stock prices and dividend yields on September 10, 2012, as well as the
	recovery rates
		Company X	Company Y
	Stock price	34.63	23.38
	Dividend yield	2.552%	3.95%
	Bond recovery rate	40%	36.14%
	Equity recovery rate	2%	1%

Table 4 .

 4 CDS premiaThis table displays the closing CDS premia as of September 10, 2012.

	Name	Company X	Company Y
	6 month CDS spread	0.00324	0.01036
	1 year CDS spread	0.00404	0.01168
	2 year CDS spread	0.00612	0.01554
	3 year CDS spread	0.00825	0.01924
	4 year CDS spread	0.01027	0.02272
	5 year CDS spread	0.01216	0.02586
	7 year CDS spread	0.01388	0.02851
	10 year CDS spread	0.01514	0.03003
	15 year CDS spread	0.01544	0.03064
	20 year CDS spread	0.01559	0.03101

Here, risk-free means free of credit risk, but not necessarily of market risk

Then, we conduct the backward induction. The procedure is as follows.