Christoph Sandner
email: christoph.sandner@infineon.com

Martin Clara

Andreas Santner

Thomas Hartig

Franz Kuttner

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS

A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realized in a standard digital 0.13µm CMOS copper technology is presented. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400fF, which leads to an easily drivable analog converter interface.

Operating at 1.2GSps the ADC achieves an effective resolution bandwidth (ERBW) of 700MHz, while consuming 160mW of power. At 600MSps we achieve an ERBW of 600MHz with only 90mW power consumption, both from a 1.5V supply. This corresponds to outstanding Figure-of-Merit numbers (FoM) of 2.2 and 1.5pJ/convstep, respectively. The module area is 0.12mm².

Introduction

Flash Analog-to-Digital Converters (ADCs) are still the architecture of choice, where maximum sample rate and low to moderate resolution is required. A typical example is e.g. the read-write channel of a disk drive system, where customers often ask for the maximum sample rate that is offered by the currently available technology generation.

However, there are additional applications in the wireless area coming up, where a flash-ADC gives sufficient accuracy at the required large analog bandwidth, for example in ultra-wideband (UWB) systems. Since a lot of wireless applications are hand-held as well, this poses an important constraint to the specification of the ADC, which is power consumption. The ADC can be the dominant block in terms of power consumption for the whole analog frontend of such a system.

In this paper we describe the concept, design and measurement results of a 6bit flash-ADC, optimized for low power at sufficiently high data rates and analog bandwidth. With 1.2GSps and ERBW of 700MHz the ADC fulfils the requirements currently under discussion for multi-band OFDM UWB systems [START_REF] Batra | Multi-band OFDM Physical Layer Proposal[END_REF]. Due to the large ERBW different receiver topologies, like low-IF or zero-IF can be supported, both at Nyquist rate, and under sub-sampling operation. However, the presented ADC architecture is not limited to these applications.

Although almost all recently published high-speed full-flash-ADCs employ resistive interpolation and averaging, the capacitive interpolation structure with distributed front-end sample-and-hold seems to have advantages in terms of power and area, even at GSps-speed. The outstanding FoM numbers prove the efficiency of the implemented architecture, when compared to stateof-the-art 6bit flash ADCs.

Converter Architecture

Averaging is a well known technique to improve the linearity of a flash-type ADC beyond the matching limit of the single comparator [START_REF] Bult | An Embedded 240-mW 10-b[END_REF]. Multiple gain-stage architectures allow the use of interpolation to reduce the number of front-end amplifiers and thus the input capacitance of the converter. By scaling the amplifiers in the analog preprocessing chain from front to back also the overall power consumption can be optimized under the given gain/bandwidth constraints. There exist basically two different strategies for implementing a flash Fig. 1: ADC frontend portion using capacitive interpolation ADC employing interpolation and averaging.

Resistive interpolation employs averaging resistors between the outputs of adjacent amplifiers. [START_REF] Kattmann | A technique for reducing differential non-linearity errors in flash A/D converters[END_REF]. A common problem of such architectures is the need for overrange comparators to maintain linearity at the edges of the conversion range. Special circuit techniques [START_REF] Scholtens | A 6-b 1.6-Gsample/s Flash ADC in 0.18-um CMOS Using Averaging Termination[END_REF] allow reducing the number of overrange comparators, but they rely on matching the termination resistor with the output resistance of the overrange blocks. Furthermore, an external sample-and-hold circuit is almost always required, which consumes a significant fraction of the total power budget in wide-band applications.

Capacitive interpolation, on the other hand, uses a purely reactive averaging network between the outputs of adjacent amplifiers [START_REF] Kusumoto | A 10b 20MHz 30mW Pipelined Interpolating CMOS ADC[END_REF]. A big advantage of capacitive interpolation is that it requires neither power consuming overrange comparators nor any static averaging termination. Also, no external sample-and-hold is required, because the interpolation capacitors at each stage are readily used as sampling capacitors implementing a multistage input-offset-sampling (IOS) architecture with distributed front-end sample-and-hold.

The principle of capacitive interpolation combined with distributed front-end sample-and-hold is illustrated in Fig. 1, showing a portion of the converter input. The inverting first stage amplifiers drive the interpolating capacitive network of the second stage, here implementing an interpolation factor 2. The interpolation factor at the converter input is given by the total number of frontend amplifiers minus 1. The total input capacitance of the converter in the sampling phase is given by the sum of the front-end capacitors plus wiring parasitics.

One drawback of the capacitive interpolation structure is the capacitive divider formed by the sampling capacitor and the input capacitance of the amplifier during the amplification phase. The overall gain of each stage is given by the intrinsic gain of the amplifier and the capacitive divider ratio. In order to minimize the total input capacitance of the converter, the sampling capacitors will be chosen as small as possible, for a resolution of 6 bits ultimately limited by capacitor mismatch. For minimum gain loss the amplifiers' input devices should therefore be as small as possible. Here, IOS helps to further reduce the input devices' effective mismatch, thus allowing additional downscaling to save power and area.

Implemented Design

The block diagram of the implemented A/D-converter is shown in Fig. 2. The circuitry is fully differential, although drawn single ended for simplicity. The input signal is sampled in the first clock phase φ 1 by the front-end amplifiers forming a distributed sample-and-hold, while the subsequent stages sample the offset voltage. During the second clock phase φ 2 the reference voltage is applied to the bottom plates of the front-end sampling capacitors and the difference between input voltage and reference voltage is amplified before it is latched by the comparators at the end of this clock phase.

The capacitive load at each amplifier output and thus the bandwidth of the amplifier is linearly related to the interpolation factor. To optimize the power-bandwidth product of the amplifier, while still profiting from the averaging property, the minimum possible interpolation factor of 2 is chosen at the output of each gain stage. To reach 64 decision levels after three interpolating stages, an interpolation factor of 8 is implemented at the converter input, thus formed by 9 parallel input amplifiers. A fourth gain stage directly drives the latching comparator, leading to an 8-2-2-2-1 interpolation topology. Since the overall interpolation factor is 64, only two reference voltages are needed at the input of the 6 bit ADC, thus avoiding the silicon area and power penalty of a lowresistance reference ladder. Instead, the reference voltages are generated by capacitive voltage division during the amplification phase φ 2 (referring to single-ended representation in Fig. 1): ( )

REFN REFP REFN i REF V V C C C V V - + + = 2 1 1 (1)
Through optimized sizing of the converter front-end, it was possible to reach a very low input capacitance of only 400fF. The subsequent gain stages are progressively scaled down by a factor of 2, thus achieving a very compact layout, since all 4 gain stages end up to have the same height (Fig. 4).

Regarding DC performance, the input referred offset is the most important specification. Since, due to minimum sizing for maximum speed, the offset of the final comparator stage is dominant, this offset must be reduced by achieving sufficient gain in the preamplifiers, thus reducing the input referred offset. The amplifier block (Fig. 3) consists of a differential pair with resistive load. PMOS switches connected between inputs and outputs provide the offset sampling. The gain of each stage is chosen to be 2.5 for achieving maximum bandwidth.

The final comparator latch is shown in Fig. 5. The input voltage difference is first converted into a current difference and then fed to the cross-coupled latch, formed by transistors N2. During the sampling phase, when the amplifiers sample the analog input signal, the CLK signal is high, thus keeping the comparator outputs OUTP and OUTN at the same level. During amplification phase CLK goes low, thus releasing the outputs, and the latch can decide whether the input voltage difference was positive or negative. The use of a single NMOS clock switch between both outputs is not possible, due to the low supply voltage of 1.5V. The gm of transistors N2 must be chosen such that the desired Bit Error Rate (BER) specifications are met. Main advantages of this topology are the almost rail-to-rail output swing, and the reduced kick-back to the pre-amplifiers due to the current mirrors.

For increasing the BER the 64 outputs of the comparator row are again latched twice by differential latches, before entering a first order bubble correction stage, which also converts the thermometer code to a 1out-of-N code. Finally, this code is converted into a 6 bit Gray-code using a ROM-table based on a current steering topology optimized for high frequency operation. For test purposes the digital data is downsampled by a factor of 64, thus standard CMOS pads can be used for the digital outputs.

Fig. 4 shows the layout plot of the implemented testchip. It was fabricated in a 0.13µm digital CMOS technology with standard-threshold MOS devices (no low-VT option), single poly, 4 thin copper metals, and 2 thick copper metals. The capacitors are of metal-metal sandwich type, taking advantage of both vertical and lateral capacitances.

Measurements

All measurements are done on a standard PCB with ceramic TQFP-44 package and no socket, at room temperature and nominal supply of 1.5V. Both, analog input and sampling clock are applied differentially to the chip by using baluns.

Fig. 6 shows the DNL of the converter, measured at 600MSps with a full-scale 50MHz sine-wave input employing a histogram method. The measured peak DNL of 0.4LSB thus already includes dynamic effects at that sampling rate. Peak INL is measured <0.6LSB.

In Fig. 7 the maximum sampling rate of the ADC is explored for nominal bias current. The analog signal frequency is kept constant at 121MHz, while the sampling clock frequency is varied on the x-axis. The ADC shows 5bit ENOB up to a sample rate of 1.4GSps. The clock frequency limit for the digital circuitry is around 1.6GSps. Fig. 8 shows the SNR and SNDR for a sample rate of 600MSps, at reduced bias current to save power. The SNDR at 51MHz is 35.5dB, with an SFDR of 52dB and a THD of 49dB, thus proving the excellent linearity of the capacitive interpolation topology. The SNDR drops by 3dB at an ERBW of 600MHz. In Fig. 9 the same measurement is done for 1.2GSps at nominal bias current. SNDR starts at 35.8dB for low frequencies (THD is 46dB), dropping by 3dB at an ERBW of 700MHz. These measurements show that this ADC topology is very well suited for applications with wide analog bandwidth.

To do a comparison with state-of-the-art 6bit flash-ADCs, a Figure-of-Merit (FoM) is calculated [START_REF] Jiang | A 2GS/s 6b ADC in 0.18µm CMOS[END_REF]:

ERBW Power FoM DC ENOB ⋅ ⋅ = 2 2 , [pJ/convstep] (2)
For our ADC we achieve a FoM of 2.2pJ/conv at 1.2GSps, and 1.5pJ/conv at 600MSps. As can be seen in Fig. 10 these are the best FoM numbers for flash ADCs ever published [START_REF] Scholtens | A 6-b 1.6-Gsample/s Flash ADC in 0.18-um CMOS Using Averaging Termination[END_REF][START_REF] Choi | A 6-b 1.3-Gsample/s A/D Converter in 0.35µm CMOS[END_REF][START_REF] Geelen | A 6b 1.1GSample/s CMOS A/D Converter[END_REF][START_REF] Jiang | A 2GS/s 6b ADC in 0.18µm CMOS[END_REF][START_REF] Uyttenhove | A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25µm CMOS[END_REF]. Although a smaller feature size technology is used in this work, the achieved performance nevertheless proves the efficiency of the capacitive interpolation architecture with distributed sample-and-hold for flash ADCs in the GHz range.

5.

Fig. 2 : 3 :

 23 Fig. 2: Implemented ADC Block Diagram Fig. 3: Amplifier Block Diagram

Fig. 4 Fig. 5 : 6 :

 456 Fig. 4: ADC Layout

Fig. 10 :

 10 Fig. 7: Measured Dynamic Performance vs. fsample (fsig = 121MHz)

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

Acknowledgements

We thank C. Kropf for layout work, P. Schreilechner for board design, P. Bogner, D. Draxelmayr and G. Knoblinger for fruitful discussions.

6.


P Bernardi

G Masera

F Quaglio

M Sonza Reorda

Testing logic cores using a BIST P1500 compliant approach: a case of study

In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.

Introduction

Continuous technological improvements allow designing a complex system into a single chip (System-On-Chip or SoC). A SoC is composed of different reusable functional blocks, called embedded cores. Typical embedded cores include processors (such as CPUs, DSPs, and microcontrollers), memories (such as ROMs, DRAMs, SRAMs, and flash), I/O devices, etc. System designers can purchase cores from core vendors and integrate them with their own User-Defined Logic (UDL) to implements SoCs. Core-based SoCs present important advantages: the size and the cost of the end-product are decreased, and thanks to the design re-use, the time-to-market is greatly reduced.

Conversely, testing a core-based SoC is a major challenge [START_REF] Zorian | Testing embedded-core based system chips[END_REF]. The main problem is that accessibility to cores and UDL is greatly reduced. Traditional approaches [START_REF] Zorian | Testing embedded-core based system chips[END_REF][START_REF] Touba | Using Partial Isolation Rings to test Core-Based Designs[END_REF] for testing corebased SoCs completely rely on additional Design for Testability (DfT) structures such as test busses for test transfers from/to the core under test. The access mechanism requires additional logic (such as a wrapper around the core) and wiring (such as a test access mechanism or TAM) to connect cores to the test source and sink. A critical point to be solved in SoC testing is the extra cost introduced by the DfT logic, i.e., the area, delay and test application time overheads. Some approaches have been proposed to solve this problem. A class of test approaches [START_REF] Bouwman | Macro Testability: the results of production device applications[END_REF][START_REF] Ghosh | A Fast and Low-Cost Testing Technique for Core-Base System-Chips[END_REF] adopts the reuse of existing functionalities for test access. These methods assume that every core has a transparent mode in which data can be propagated. However, these methods are not general enough to handle all the possible kinds of cores and all the possible test schemes, such as scan or Built-In Self-Test (BIST). Some researchers [START_REF] Papachristou | Microprocessor based testing for core-based system on chip[END_REF][START_REF] Rajsuman | Testing a System-On-a-Chip with Embedded Microprocessor[END_REF][START_REF] Tsai | Processor-Programmable Memory BIST for Bus-Connected Embedded Memories[END_REF] proposed to exploit an embedded processor to test the other components of the SoC: first the processor core is tested (e.g., by means of functional patterns or full-scan test), and then a test program, executed by the embedded processor, is used to test the on-chip memories and other cores. The use of embedded processors to test cores presents many advantages: the size of the test controller is normally negligible, the test program (being in software) guarantees a high flexibility, and the testing process can often be done at-speed. Moreover, the test process is done inside the chip and the tester can work at a lower speed, thus reducing the costs for the test equipment. The main disadvantage is related to the need for an on-chip processor and to the dependence on the one possibly present in the SoC. In case of different processors, the test program has to be adapted to each of them causing an increased cost in the test development. Moreover, this approach cannot be applied to embedded cores not suitably connected to the processor.

When considering logic cores, the adoption of deterministic BIST is becoming increasingly popular, mainly due to the availability of efficient commercial tools supporting this technique. However, this approach has serious limitations when delay faults are of interest, since it relies on scan chains to access the internal points of the circuit.

In this paper we report the experience gathered by adopting a test strategy for logic cores based on a custom BIST engine wrapped to the embedded device under test. From the test point of view, the core complies with the P1500 standard, thus easing the connection of the core to other test resources on the chip (e.g., a 1149.1 TAP controller for accessing the SoC from outside). The advantages of this solution are first the high re-usability of the IP core, even in terms of testing features: only the test protocol must be delivered to the user (no vectors). As a second advantage there is the high fault achieved by the BIST engine (especially in terms of delay faults, as it performs the test at-speed). Finally, the approach provides the test engineer with some diagnostic feedback about the executed test; low area overhead and negligible costs in terms of wiring and performance reduction are the main drawbacks. The P1500 standard structure integrated with the BIST finally provides plug and play characteristics to the core to be easily inserted into powerful SoC level test structures. A case study will be reported allowing to better evaluating the advantages and disadvantages of the adopted test strategy.

Section 2 summarizes the possible architectural solutions for core-based SoC testing and introduces the one adopted in our work. Section 3 describes the proposed test architecture in terms of internal organization, detection and diagnosis properties evaluation, and external layers. Section 4 describes the considered case study and, finally, section 6 draws some conclusions.

Core test architectures

Testing core-based SoCs is a complex problem that can be divided in two parts: core-level and chip-level testing. Core-level testing involves making each core testable, i.e., inserting the necessary test structures and generating test sequences. Chiplevel testing involves defining a test access mechanism architec-ture for applying the test sequences to the input peripheries of the cores, and for propagating the test responses from the core outputs to the chip outputs.

In this paper we mainly focus on the core-level testing problem, resorting to a custom TAM for connecting the core to a standard 1149.1 TAP controller, thus providing an easy interface between the SoC and an external ATE.

Different approaches can be adopted for testing logic cores; they are normally grouped in the following classes: scan based pseudo-random based [START_REF] Stroud | A designer´s Guide to Built_In Self_Test[END_REF][START_REF] Bardell | Built-In Test for VLSI: Pseudorandom Techniques[END_REF] logic BIST.

In scan based and logic BIST approaches, a set of patterns are generated using automatic tools (ATPGs) and applied to the circuit. In the sequential approach, the calculated patterns are sequentially sent to the circuit and responses read after each application and any additional internal structure is added in order to improve the effectiveness of the patterns. On the contrary, in the scan approach, the controllability and the observability of the circuit are improved by modifying the common flip flop: the socalled scan cells allow writing and reading the content of the memory element during the test apply, and are connected to compose a scan chain. However, as a serial process is required to load and upload the scan chain, that approach requires onerous application time and heavy ATE requirements in terms of storage needed for test data and test application program.

An alternative technique is the pseudo-random pattern generation. Such approach is based on the Galois theories for the generation of pseudo-random number sequences starting from the definition of a characteristic polonium. Particular structures, called Autonomous Linear Feedback Shift Registers (ALFSR) provides a perfect hardware implementation for such kind of pattern generation strategy.

In this paper, a BIST implementation based on pseudo-random pattern generation is proposed and its effectiveness in coping with cores composed of many functional modules is underlined. In particular we focussed on the definition of a low-intrusive techniques guaranteeing high performance in term of fault coverage and high reusability in SoC structured. The proposed architecture is accessible through the test standard interfaces (IEEE 1149.1 and P1500) in order to make the test completely accessible from the outside: the test of the core can thus be executed by means of 1149.1 instructions and the core test details are completely transparent to core designers, maintaining the core Intellectual Properties.

The adopted approach

The approach adopted in this paper is based on the insertion of a BIST engine in charge of generate and apply patterns to the device under test. The adopted BIST circuitry has been designed to achieve two goals: on one hand we want to simplify the introduction of any modification in the pattern generation algorithm; on the other hand we aim at adopting the same architecture to a large set of logic cores. The adopted architecture exploits the current test standard interface in order to simplify the designer effort. The BIST engine is not directly visible from the outside, since the core is P1500 compliant, and includes a P1500 wrapper.

The BIST engine

The BIST engine internal architecture is divided into the following functional blocks:

a Control Unit to manage the test execution; a Pattern Generator to produce and apply the test patterns; a Result Collector to manage the memory access timing. In figure 2 a generic environment for the considered approach is presented: the A, B and C modules are parts of the same logic core and communicate among them in order to process inputs and generate outputs. In the picture, inputs and outputs of each module are considered separately to ease the test approach comprehension. The Control Unit manages the test execution; by receiving and decoding commands from the control signals, this module is able to manage the test execution and the upload of the results. In particular, it covers three tasks: it receives from the data signals the number of patterns to be applied it drives the test_enable signal that starts and stops the test execution and provides the information about the end of the test it selects the result to be uploaded.

Control unit

This choice allows easy reuse in different applications, like the application of test vectors generated according to different algorithms, or the test of logic cores with different characteristics.

The Pattern Generator is in charge of the application of the patterns to the DUT and is composed of:

an ALFSR module [START_REF] Stroud | A designer´s Guide to Built_In Self_Test[END_REF][START_REF] Bardell | Built-In Test for VLSI: Pseudorandom Techniques[END_REF] a set of Constraints Generators (CG).

The ALFSR module generates pseudo-random patterns according to the chosen polynomial characteristics; for cores composed of many functional blocks, only one ALFRS circuitry can be employed. On the contrary, a Constraint Generator is a custom circuitry able to drive constrained inputs. The adoption of such blocks provides great improvements in terms of effectiveness of the applied test, where a particular state machine controls the behavior of the circuit.

In the design of the pattern generation circuitry, we identified four architectural situations: a. the block under test does not have constrained inputs and the ALFRS size fits the input port width b.

the block under test does not have constrained inputs and the input port width is larger than the ALFRS dimension c.

the block under test does have constrained inputs and the ALFRS size fits the input port width d.

the block under test have constrained inputs and the input port width is bigger than the ALFRS dimension.

While in a) the designer task consists just in connecting the ALFRS output with DUT input port, in b), c) and d) scenarios more care in choosing connections is required. Respectively, designers have to replicate the ALFSR outputs to reach the input port width identify the constrained inputs to build the CG and connect the ALFRS output to the remaining inputs. identify the constrained inputs to build the CG and replicate the ALFRS outputs to drive all the remaining inputs.

These three situations are shown in figure 2 where respectively w_B > w_ALFSR, w_A < w_ALFSR + w_CG_A and w_C > w_ALFSR + w_CG_C.

The Result Collector is in charge of storing and making the results reachable from the outside. It is composed of a set of MISR modules [START_REF] Stroud | A designer´s Guide to Built_In Self_Test[END_REF][START_REF] Bardell | Built-In Test for VLSI: Pseudorandom Techniques[END_REF] an Output Selector module.

The ability of MISR modules to compact information with a low percentage of aliasing makes them suitable to store the results of the test. In our approach we coupled each module under test with a MISR: whereas the size of the MISR cannot exceed a predefined size, a xor cascade has been used. Each MISR module is reachable from the outside by programming the Output Selector.

This organization allows reducing the re-design operations and supports the reuse of the internal structures: changing ALFSRs and MISRs dimension is a trivial task. Only the individuation of inputs constraints and the design of the Constraints Generator require a bigger effort to designers.

Fault coverage and diagnosis ability evaluation

To obtain high fault coverage and guarantee high ability in terms of fault location, we identified three steps:

1.

Statement coverage and toggle activity evaluation 2.

Fault coverage measure 3.

Equivalent fault classes computation.

In the first step, pseudo-random patterns are applied to the RTL description of the modules composing the logic core and the measure of the percent number of VHDL lines executed is performed. Such measure, usually called statement coverage, together with the calculation of the percent number of variables toggled by the patterns, called toggle activity, gives to the designer a first degree of confidence about the effectiveness of the generated patterns [START_REF] Zhang | A data flow fault coverage metric for validation of behavioral HDL descriptions[END_REF] and can be performed using a simulation tool. Until this step, the evaluated patterns can be generated using the VHDL description of the Pattern Generator or simply calculated with ad-hoc tools generating pseudo-random sequences. Figure 3 represents the first step.

The second step refers to the synthesized component and can be performed using a fault simulator. In order to obtain reliable results, the design to be evaluated in this step should already include the Pattern Generator and the MISRs embedded into the Result Collector, as the final layout optimization will merge their circuitry with that of the device under test.

Whereas the fault coverage reached is less than the required, three actions can be performed:

apply a larger number of patterns modify the ALFSR or MISRs structure redefine the Constraints Generator where included.

Pseudo-random patterns

Logic core VHDL(RTL)

Simulation tool

Statement coverage Toggle activity

Enough? no

Step 2 yes Fig. 3: Statement coverage and toggle activity evaluation loop.

While the first action does not require any modification in the designed circuitry, the number of patterns can be increased only until the time for test requirements are not exceeded. In this case, the flow backs to the first step with the evaluation of new patterns. This loop, reported in figure 4, ends when the desired fault coverage is reached or when exceeding the manufacturing constrains. The thirst step aims at reaching high diagnosis ability: this characteristic of the performed test can be evaluated by means of the size of the equivalent fault classes [START_REF] Smith | A variancereduction technique via fault-expansion for fault-coverage estimation[END_REF]. Such measure allows establishing the precision in terms of fault location provided by the analyzed patterns. The size of the equivalent fault classes mainly depends on the ability of the chosen patterns to produce a different syndrome for every fault possibly affecting the DUT.

Logic

To reach this purpose, a tool able to apply patterns and store the circuit response is needed. The collected information, by means of the obtained syndromes, can be used to build the so-called diagnostic matrix [START_REF] Corno | GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits[END_REF], allowing to identify the faults belonging to the same equivalent fault class.

To improve the diagnostic properties of the generated patterns, it is possible to operate in two ways: adding test patterns changing the test structure characteristics.

The P1500 wrapper module

The wrapper, shown in Fig. 5, contains the circuitry necessary to interface the test processor with the outside in a P1500 compliant fashion, supporting the commands for running the BIST operation and accessing to its results. The wrapper is compliant with the suggestions of the P1500 standardization group [START_REF] Marinissen | Towards a Standard for Embedded Core Test: An Example[END_REF]. The wrapper can be connected to the outside via a standard TAP. In addition to the mandatory components we propose the introduction of the following Wrapper Data registers:

Wrapper Control Data Register (WCDR): through this register the TAP controller sends the commands to the core (e.g., core reset, core test start, the Status register read, etc.). Wrapper Data Register (WDR): it is an output register. The TAP Controller can read the test information stored into the status register.

The case study

We applied the outlined approach to a Reconfigurable Serial Low-Density Parity-Checker decoder core [START_REF] Gallagher | Low Density Parity Check Codes[END_REF][START_REF] Mackay | Correcting Codes Based on Very Spares Matrices[END_REF][START_REF] Masera | Reconfigurable Serial LDPC Decoder Architecture[END_REF]. This core was developed by our institution in the frame of a project involving several semiconductor, equipment, and telecom companies; to make it more easily usable by core integrators, a test solution was required: in the following we give details about the adopted solution.

Low-Density Parity-Check (LDPC) codes are powerful and computationally intensive error correction codes, originally proposed by Gallagher [START_REF] Gallagher | Low Density Parity Check Codes[END_REF] and recently rediscovered [START_REF] Mackay | Correcting Codes Based on Very Spares Matrices[END_REF] for a number of applications, including Digital Video Broadcasting (DVB) and magnetic recording. LDPC codes can be represented as a bipartite graph (Fig. 1), where two classes of processing elements iteratively exchange information according to the Message Passing algorithm: Bit Nodes (BN) correspond to the codeword symbols, while Check Nodes (CN) are associated to the constraints the code poses on the bit nodes in order for them to form a valid codeword; at each iteration, the reliability of the decoding decisions that can be made on basis of the exchanged information is progressively refined.

Fully and partially parallel solutions for the implementation of the decoder exploit the regularity of the bipartite graph mapping directly CN's and BN's into hardware blocks; graph edges either are mapped to proper interconnect infrastructures or are implemented by means of memory banks. The complexity of check and bit nodes is strongly related to the number of incoming/outgoing edges; additional complexity comes from the requirement of supporting different edge numbers that is typical in the most powerful, irregular codes.

Fig. 6: Bipartite graph for an LDPC code

In [START_REF] Masera | Reconfigurable Serial LDPC Decoder Architecture[END_REF] the implementation of an LDPC decoder is proposed, based on the use of a shared memory that emulates the interconnection between BIT_NODEs and CHECK_NODEs. In [START_REF] Masera | Reconfigurable Serial LDPC Decoder Architecture[END_REF], a further implementation is proposed, introducing programmability in the architecture proposed in [START_REF] Mackay | Correcting Codes Based on Very Spares Matrices[END_REF]. In this approach, a configurable BIT_NODE and a configurable CHECK_NODE are described. Their ability consists in emulating more than one module, by mapping more "virtual" nodes to the two physically available processing elements; the interconnections are simulated by means of two "interleaving memories" and thanks to its reconfigurable characteristics, this decoder is able to support codes of different sizes and rates, up to a maximum of 512 check nodes and 1,024 bit nodes. A CONTROL UNIT is introduced in order to manage the memory access and the reconfiguration information. The schematic of this enhanced circuitry is reported in Figure 7. Additionally to the use of the showed core in conjunction with external memories to achieve a serial reconfigurable decoder, it can also be adopted as the basic building block for the implementation of a fully parallel architecture. The BIST engine has the following structure. The Control Unit contains a counter register (pattern_counter) on 12 bits, allowing to apply up to 4,096 patterns for each test execution, and generates a 2 bits signal connected with the Result Collector, in charge of selecting the output to be read.

The Pattern Generator is equipped with a 20-bit ALFRS module and only one Constraints Generator connected both to the BIT_NODE and the CHECK_NODE of the serial LDPC while the CONTROL UNIT does not need it. The Constraints Generator manages a 4 bits sized port that internally selects the data path into the circuitry: it allows applying a limited number of patterns when a small data path is selected, while holding selection values that maximize the used circuitry.

The Result Collector is composed of three 16 bit sized MISR modules, each one connected to the DUT outputs through a xor cascade, and a Output Selector, whose behavior is driven by the Control Unit.

The total area occupied by the DfT additional logic is reported in Tab. 2, and have been worked out by using a commercial tool (Synopsys Design Analizer) using an industrial 0.13 µm technological library.

The TAM logic (which includes the Wrapper module) represents a fixed cost necessary to manage the chip-level test. Its area overhead can be quantified as the 16% of the global cost of the additional core-level test logic.

Component

Area The fault coverage percentage reached by our approach is reported in table 3 and refers to both Stuck At Faults (SAF) and Transition Delay Faults (TDF). Such results have been obtained employing a commercial fault injection tool (Synopsys Tetramax). In order to provide the reader with reference figures, we also included in the table the data related to the cases in which sequential and full scan patterns produced by a commercial ATPG tool (again Synopsys Tetramax) are used. It is important to note that these patterns could not be easily applied to the core, if embedded in a SoC, while the BIST approach is very suitable to deal with this situation. The number of scan cells inserted is 75 for the BIT_NODE, 803 for the CHECK_NODE and 42, divided in two scan chains including 14 and 28 cells, for the CONTROL_UNIT. These values have been calculated using a SUN workstation equipped with a SPARC V8 microprocessor and the CPU times reported in the above table working at 431.03 Mhz in the case of the BIST engine approach (at-speed testing) and at 100 Mhz (supposed ATE frequency) in the Sequential and Full scan approach.

With respect to the Sequential and Full Scan approaches, the use of the BIST approach is desirable for at least the following reasons: the fault coverage reached is higher than Sequential patterns coverage and comparable with Full Scan the BIST patterns are the same for all modules to be tested, so that they can be tested simultaneously the test time is significantly lower for the BIST approach than for the full-scan one such patterns are generated and applied one for each clock cycle and results read in the end of the execution, while Sequential and Full scan patterns have to be sent serially by the ATE and results uploaded serially after each operation, thus drastically increasing the ATE storage requirements the test patterns are applied by the BIST engine at the nominal frequency of the circuit while the Sequential and Full scan patterns are applied at the ATE frequency that could be lower, guaranteeing more efficiency in the fault coverage.

In table 4, the measure of the performance reduction in terms of frequency lost is reported. This is due to the introduction of the BIST engine and the wrapper. This value is compared with the ones coming from the analysis of the Sequential and Full Scan approach, supposing that:

for the Sequential approach, patterns are applied using a standard P1500 wrapper for the Sequential approach, patterns are applied using a standard P1500 wrapper and introducing into the design multiplexed scan cells.

Fig. 1 :

 1 Fig.1:The general architecture of the adopted approach.

Fig. 2 :

 2 Fig. 2: BIST engine overall structure.

Fig. 4 :

 4 Fig. 4: Statement coverage and toggle activity evaluation loop.

Fig. 5 :

 5 Fig. 5: Details of the Wrapper Architecture.

Fig. 6 :

 6 Fig. 6: Architecture of the Reconfigurable Serial Low Density Parity Checker decoder [15]. The BIT_NODE (BN), the CHECK_NODE (CN) and the CONTROL_UNIT (CU) are connected to the two interleaved memories to perform error detection and correction during transmission of high data volumesAs far as this design is considered, we partitioned the analyzed logic core in BIT_NODE, CHECK_NODE and CONTROL_UNIT modules. The characteristics of each module in terms of input and output port size is reported in table 1. The test of the two interleaved memories and the buffers is not con-

table 1 .

 1 The test of the two interleaved memories and the buffers is not con-

	CN
	EDGE
	BN

Table 1 : Input and output port size in bits.

 1

Table 2 : Area overhead evaluation.

 2

Table 3 :

 3 Fault coverage.

	Component	BIST patterns		Sequential patterns	Full scan patterns
	Fault type	SAF	TDF	SAF	TDF	SAF	TDF
		Faults [#]	7,532	7,532	7,532	7,532	7,836	7,836
	BIT NODE	FC [%] clock cycles	97.8 4,096	95.6 4,096	93.8 11,340	84.3 16,580	98.5 21,248	91.2 39,168
		CPU time	-	-	489 sec	2,628 sec	197 sec	277 sec
		Faults [#]	86,104	86,104	86,104	86,104	89,412	89,412
	CHECK NODE	FC [%] Clock cycles	91.6 4,096	90.7 4,096	82.9 8374	76.4 7844	93.1 380,064	87.1 866,272
		CPU Time	-	-	~ 54 h	~ 43 h	428 sec	692 sec
		Faults [#]	3,038	3,038	3,038	3,038	3,216	3,216
		FC [%]	97.5	95.3	89.8	84.0	98.6	91.3
	CONTROL UNIT	Clock cycles	4,096	4,096	3060	4,860	16,965	27,405
		CPU time	-	-	2422 sec	5909 sec	91 sec	123 sec

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Finally, table 5 shows the size of the equivalent fault classes for the three components obtained for the BIST engine, Sequential patterns and Full Scan approach applying the number of patterns reported in table 2. That result have been obtained exploiting an in-home developed tool in C language: this tool is able to build and analyze the diagnostic matrix by collecting each fault syndromes obtained by using Synopsys Tetramax as a fault simulator.

Component

Conclusions

In this paper we presented a case study in which a logic core for telecom applications was equipped with test features suitable to guarantee a high fault coverage (especially with respect to delay faults) and a high modularity and easy integrability into a SoC, even from the point of view of testing.

The adopted approach is based on a BIST engine that is in charge of applying test patterns and observing the module behavior. Such BIST engine has been designed to allow high flexibility in order to easily adopt the same approach to a large set of different core models and easily allow the upload of test results. Thanks to the adopted solution, the test can be applied at-speed, thus reaching a very high fault coverage with respect to delay faults. The proposed architecture exploits the current test standards interface (IEEE 1149.1 and P1500 standards) in order to simplify the design effort. Moreover, the P1500 wrapper eases the integration of the core into the overall SoC test strategy. The test architecture is transparent to the core user, thus guaranteeing the protection of the intellectual property.


Dan Hillman
email: danh@virtual-silicon.com

Virtual Silicon

Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm

At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of dynamic and static power reduction achieved implementing Tensilica's 32-bit Xtensa microprocessor core, using Virtual Silicon's Power Management IP. Independent voltage islands are created using Virtual Silicon's VIP PowerSaver standard cells by using voltage level shifting cells and voltage isolation cells to implement power islands. The VIP PowerSaver standard cells are characterized at 1.2V, 1.0V and 0.8V, to accommodate voltage scaling. Power islands can also be turned off completely. Designers can significantly lower both the dynamic power and the quiescent or leakage power of their SoC designs, with very little impact on speed or area using Virtual Silicon's VIP Gate Bias standard cells.

Overview

Designers today are challenged not only by new process technologies capable of incorporating more and more devices on a single chip, but also managing the increase in the power that goes along with it. Techniques such as clock gating, low power processes, low power IP and lower supply voltage used with each new generation of process technology have helped designers of mobile applications to stem the tide of ever increasing power. Configurable processors such as the Xtensa [1] core used here can also optimize the instruction set to minimize power and energy. As technology moved down to 180nm, leakage power was not a major issue. The old techniques produced acceptable results.

However, the130nm and 90nm technologies are reaching the point where leakage power is nearly the same as dynamic power. And both dynamic and static powers are increasing at such a rate that the old rules just don't work. Unless new techniques are found, 130nm and 90nm technologies for handheld devices will be adopted more slowly.

Significantly reduce both dynamic and static power of SoC using Virtual Silicon Mobilize Power Management IP. A 32-bit Xtensa microprocessor will be synthesized and taken all the way through routing in order to benchmark the power reduction in dynamic power and static (leakage) power.

Dynamic power reduction

Dynamic or switching power is expressed by P dynamic = k*C*V2*F*SA: where), k = Constant (usually varies from 0 to 1), C represents capacitance, V is the operational voltage and F is the frequency for the design, and SA = Switching activity.

The configurable Xtensa attacks most variables in the dynamic power equation to achieve low power designs, e.g., smaller microprocessor configuration without unused features hence reduces C, advanced Xtensa architectures allow more tasks get done within each clock cycle or at minimum F, and Xtensa's extensive clock gating makes possible the lowest SA. For a detailed presentation see [2]. This work focuses on minimizing the operating voltage to reduce dynamic power. The libraries for most of today's designs are characterized for small process variations at a single voltage. The performance is guaranteed for process, temperature and voltage variations. What if you could get a library that was characterized for several voltages? You could then design each part of the SoC at its minimum voltage for its required operating frequency.

Design overview

The example design shown in Figure 1 is made up of three components: an Xtensa processor, a memory block and a USB core. We divided the design into three autonomous power islands, Xtensa, memory and USB. The goal was to get the minimum system dynamic power by running each power island at its minimum required voltage. For a 512K embedded SRAM, commercial memory compilers can deliver the access times such that the critical paths between Xtensa and memory can run up to 181MHz at 0.8V worst case TSMC G process. The USB is a hard core and it requires a supply of 1.2V. The minimum processor system performance is 150MHz at the 130nm node [3], which the designer wants to obtain at the lowest voltage possible. To find the minimum operating voltage for the Xtensa core at 150MHz, we used Virtual Silicon's PowerSaver library. The library is characterized at three voltages, 1.2V, 1.0V and 0.8V.

Design flow

Figure 2 shows the design flow used to find the Xtensa's minimum operating voltage at 150MHz. The Xtensa was synthesized at 1.2V, 1.0V and 0.8V using worst case wireload corner .db in DC. The best case corner was used for hold time fixing in SE. Routing used 5 layers in a 6 layer system. Post route simulation was used to create SAIF files for measuring power in Power Compiler.

Synthesis and layout results

For each voltage the design was synthesized and routed at 167MHz (6.0ns), 182MHz (5.5ns), 200MHz (5.0ns), 222MHz (4.5ns), 250MHz (4.0ns), 286MHZ (3.5ns), 333MHz (3.0ns) and 400MHz (2.5ns). The goal for the design is 150MHz post layout. The results for the 1.2V, 1.0V and 0.8V libraries after place and route are shown in Figure 3. Not surprisingly, for the 1.2V library all of the synthesis and post SE runs meet timing. The utilization for this set of designs was 80%. Higher utilization resulted in too many DRC violations. The area curve generally looks as you would expect. A faster design yields a larger area. The best area result that still met post route timing was for the 167MHz design. Actual post layout clock was 155MHz, and the post route area was 141,429 µm2. For the 1.0V library, all but the 167MHz constrained design met the required timing. The utilization for this set of designs was 80% to begin with; the post layout ending utilization is 89%. Higher utilization resulted in too many DRC violations. The best result that still met timing was for the 182MHz design. Actual post layout clock was 155MHz and the post route area was 165,424 µm2. For the 0.8V library, only the 333MHz constrained design met the required timing. Synthesis and routing for 167MHz and 182MHz designs were not done. The initial utilization for this set of designs was 75%; the post layout final utilization was 83%. Higher utilization resulted in too many DRC violations. Actual post layout clock was 151Mhz and the post route area was 183,551 µm2. A summary of the post route results vs. the library voltages for the smallest area design that still met timing is shown in Figure 4. The minimum required performance of 150MHz was met by all three libraries. For the 1.0V and 0.8V libraries performance was achieved at the cost of increasing the design area. Since the design is small the increase in area is worth the power reduction obtained.

Dynamic power simulation results

Our goal was to minimize the dynamic power used by the Xtensa core. To measure dynamic power, we took the post layout back annotated netlist and ran six different Verilog test suites to generate SAIF files. The SAIF files were fed into Power Compiler to generate dynamic power numbers. The results are shown in Figure 5. Compared to the 1.2V design, the 1.0V design reduced power by 17% while increasing area by 10%. The maximum theoretical power reduction for a design going from 1.2V to 1.0V is 30.5% ((1.22 -1.02)/1.22). The actual dynamic power savings was less than the theoretical results because of the increased capacitance from the extra gates and routing area. Compared to the 1.2V design, the 0.8V design reduces power by 53% while increasing area by 31%. The maximum theoretical power reduction for a design going from 1.2V to 0.8V is 55.5% ((1.22 -0.82)/1.22). Again, the actual dynamic power savings was less than the theoretical results because of the increased capacitance from the extra gates and routing area.

Dynamic Power vs. Voltage

Putting the soc together

The islands of the SoC have been optimized for their minimum voltage for proper operation. Xtensa and the memory can operate at 0.8V and the USB can operate at 1.2V. Level shifters will be needed to ensure proper operation for the SoC as a whole. One way to employ level shifters is be to put a level shifter on all output signals that are less than 1.2V. In the SoC shown in Figure 6, all the muxes then operate off a common 1.2V supply. Therefore gates tied to a VDD less than 1.2V can safely be driven to 1.2V without damage. However, if your library has transmission gates, down shifters may be required to prevent unwanted currents or latch up. Some optimization of level shifter usage can also be done. Level shifters are not needed for signals that only go between the memory the Xtensa. Likewise, level shifters are not needed for signals that only go from the USB to the Xtensa or memory.

Xtensa

Dynamic power reduction summary

We were able to achieve our performance goal of 150MHz post-route performance at 0.8V. Our simple SoC can be divided into two power islands; USB at 1.2V, memory and Xtensa at 0.8V. This voltage reduction on the Xtensa power island netted a 53% power reduction with the Mobilize IP. The level shifters and voltage isolation gates allowed us to easily create power islands in order to realize this dynamic power reduction in our SoC. Multi voltage designs using power islands created with Molbilize IP can be implemented.

Static (leakage) power reduction

Power reduction techniques such as voltage scaling and clock gating will work well for dynamic power, but not for leakage power. Leakage power for 130nm and 90nm is approaching that of dynamic power. This section will deal with incorporating static (leakage power) reduction in addition to dynamic power reduction

Device leakage mechanisms

To minimize leakage power it important to understand the leakage sources in a device. Figure 7 is a diagram of those leakages. I1 is the reverse bias junction leakage from the drain to the substrate. This leakage is about two to three orders of magnitude less than the other leakage mechanisms. I2 is sub-threshold leakage. This is the leakage when the gate to source voltage is zero volts. For 130nm and 90nm this the major source of leakage power. I3 is leakage through the gate oxide to the substrate, source and drain of the device. For 130nm and 90nm the gate oxide is only several atoms thick. At 90nm this leakage is two orders of magnitude less than gate leakage. I4 hot-carrier injection and I5 off state leakage are both minor sources of leakage. Shown in Table 1 Virtual Silicon has developed a standard cell library that puts an NMOS sleep transistor into the path to ground with SLPB as the sleep gate bias. The concept of sleep devices, both PMOS and NMOS, has been around for some time. What makes this library unique is that a sleep device is in every library cell and the sleep gate is driven to a negative voltage. Figure 8 shows how these devices are connected in two different cells. The sleep device is a regular threshold device and not a high threshold device. Because this library is built on a standard process more IP is available and the wafer costs are less than for a low power process.

Placing the sleep device in every cell has a number of benefits. It is easy to sleep small sections of logic for example, an ALU. The sleep signal may be turned on be an already existing global clock gating signal. By using a clock gating signal, not only does clock stop to reduce dynamic power, but also the logic is put sleep to reduce static power. Also, as compared to one large sleep device the sizing and placement of the sleep device is done for you. The Gate Bias technology allows the creation of data retention flip-flops for fast save and restore operation. There is only a minor impact on speed because the sleep device is NMOS.

Figure 9 shows the leakage reduction obtained by driving the NMOS gate voltage negative. At zero volts on the gate, the leakage current is about 0.5µA. At a sleep voltage of -0.3V, the leakage current is reduced by 260x (to about 2nA). The sub-threshold leakage, which is the dominant leakage, is effectively lowered by this technique.

Example design

Figure 10 shows an example of small SoC with CPU, memory and a logic block. In Figure 10, LS stand for level shifter and ISO stands for isolation gate. For purposes of this discussion we will optimize the logic block for minimum leakage using the Gate Bias library. The minimum frequency requirement for the logic block is 200MHz. Since there is no RTL construct for sleep, the sleep functionality can only be simulated at the gate level. A script was used to add the sleep pin to the netlist. The simulator uses gate level primitives which has the sleep functionality in it.

Synthesis

The 200MHz minimum frequency requirement for the logic module could only be met at 1.2V supply.

Managing static power

Now that we have a design with the sleep device in it, we need to generate the negative voltage for sleep and control the isolation gates. The Virtual Silicon Power Island Manager is IP that generates the negative voltage for sleep, controls going in and out of sleep, isolation gates, and data retention flip-flops. The Power Island Manager can be controlled by the CPU with write and read commands. Figure 12 shows the Power Island Manager connected in the design. Although the CPU could also be put to sleep, presentation on this topic is beyond the scope of this paper.

Static power reduction

The logic block contains 108,000 gates and needs a Power Island Manager to bring it in and out of sleep. For the 'G' process, 108,000 typically consume 208µW. With the Gate Bias library the typical power for the 108,000 gates and the Power Island Manager is 4.9µW. Figure 13 shows the power comparison for 'G' and Gate Bias library. While in sleep, the Gate Bias technology saves 97.6% of the static power. We have shown a 97.6% static power reduction using the Gate Bias library and Power Management IP.

Static Power Comparison

Test chip results

A Gate Bias test chip containing the standard cells, memory and I/O has been fabricated and evaluated. The standard cells got even better leakage reduction than predicted by the Spice models. Results for the two input Nan gate are shown in Figures 14 and15.

Nand Gate TT Model vs Measured 25C At 125ºC, the model predicts a leakage reduction of 197x and the measure result gives a leakage reduction of 326x.

The on-chip negative bias generator was proven to function as designed. Gate Bias technology was added to SRAM to reduce leakage and retain data. A sleep and data retention signals were applied to the test chip SRAM. The data was retained down to 0.3V V DD supply. The leakage reduction at 125ºC is shown in Figure 16. At 125ºC, the model predicts a leakage reduction of 8.1x and the measure result gives a leakage reduction of 10.0x. The leakage current was reduced from 719µA to 71.5µA.

Based on test chip results, an SRAM design has been done which will reduce the leakage from 20x to 65x depending on the SRAM size and configuration.

Summary

We have demonstrated how dynamic power has been cut by 53% by running the Xtensa processor at 0.8V, while still meeting performance goals using the Virtual Silicon Mobilize power management IP. Static power has been dramatically reduced by 97% using the Gate Bias library and Power Management IP.

  Figure 1: Simple SoC

Figure

  Figure 2: Design Flow

Figure 3 :

 3 Figure 3: Post Route Results

  Figure 4: Library Voltage vs. Area

Figure 5 :

 5 Figure 5: Dynamic Power vs. Library VoltageAs expected, you can see dynamic power varied by suite. Compared to the 1.2V design, the 1.0V design reduced power by 17% while increasing area by 10%. The maximum theoretical power reduction for a design going from 1.2V to 1.0V is 30.5% ((1.22 -1.02)/1.22). The actual dynamic power savings was less than the theoretical results because of the increased capacitance from the extra gates and routing area. Compared to the 1.2V design, the 0.8V design reduces power by 53% while increasing area by 31%. The maximum theoretical power reduction for a design going from 1.2V to 0.8V is 55.5% ((1.22 -0.82)/1.22). Again, the actual dynamic power savings was less than the theoretical results because of the increased capacitance from the extra gates and routing area.

Figure 6 :

 6 Figure 6: Simple SoC with Level Shifters Down shifters are not required because in the Virtual Silicon library, all the inputs to cells drive gates.Therefore gates tied to a VDD less than 1.2V can safely be driven to 1.2V without damage. However, if your library has transmission gates, down shifters may be required to prevent unwanted currents or latch up. Some optimization of level shifter usage can also be done. Level shifters are not needed for signals that only go between the memory the Xtensa. Likewise, level shifters are not needed for signals that only go from the USB to the Xtensa or memory.

Figure

  Figure 7: Leakage Mechanisms

Figure 8 :

 8 Figure 8: Inverter and NAND Gate with Sleep Device

Figure 9 :

 9 Figure 9: NMOS Leakage Current vs. Gate Voltage

Figure 11 :

 11 Figure 10: Example SoC

Figure 12 :

 12 Figure 12: Example SoC with Power Management To put the logic to sleep the CPU writes to the sleep bit in the Power Island Manager. The Power Island Manager has a state machine that controls the isolation signal, sleep signal, and data retention signal. The state machine ensures the timing of these signals to give proper operation to the design. To come out of the sleep state the CPU writes the sleep bit. A status bit in the Power Island Manager can be read by the CPU to know when the logic is out of the sleep state and ready to resume operation. Times enter or leave sleep are approximately 60ns.Although the CPU could also be put to sleep, presentation on this topic is beyond the scope of this paper.

  Figure 13 Static Power Comparison 10. 2 Static power reduction summary

Figure 15

 15 Figure 15 Model vs. Measured 125ºC

  Figure 16 SRAM Leakage Reduction

Post Layout Frequency vs. Area

	190,000
	180,000
	170,000
	160,000
	150,000
	140,000
	130,000
	130	150	170	190	210	230	250	270
			Post

SE Frequency (MHz) Post SE Cell Area ( m2)

	1.2V Library
	1.0V Library
	0.8V Library

Table 1 : Leakage vs. Process 8.0 Gate Bias, what is it?

 1

		is how the different device leakage
	mechanisms change with process.
		180n	130nm	90nm
		m
	I1 = reverse	minor minor	minor
	bias junction
	I2 = sub-	minor major	major+
	threshold
	I3 = gate oxide	minor relevant	significant
	tunneling
	I4 = hot-carrier	minor minor	minor
	injection
	I5 = off state	minor minor	minor
	leakage

  At 25ºC, the model predicts a leakage reduction of 33.9x and the measure result gives a leakage reduction of 78.6x.

						Nand Gate TT model 125C vs Measured
						1.00E-07
						-0.4	-0.35	-0.3	-0.25	-0.2	-0.15	-0.1	-0.05	0	1.2
						1.00E-08
					Leakage	1.00E-09
						1.00E-10
						1.00E-11
										Sleep Voltage
								Nand Model	Nand Measured
		1.00E-08
	Leakage Current	1.00E-11 1.00E-10 1.00E-09	-0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0	1.2
		1.00E-12
			Sleep Voltage
			Nand Model	Nand Measured
		Figure 14 Model vs. Measured 25ºC

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05) 1530-1591/05 $ 20.00 IEEE

The Gate Bias technology has been validated by test chip results to get better than the predicted leakage reduction.

1. Each configuration of the extensible, configurable Xtensa processor is created by the Xtensa Processor Generator from a unique designer-defined specification of both predefined configuration options and designerdefined instruction extensions. The generator can create a wide range of processor cores, including small task engines, high performance DSPs, media processors and network processors all sharing the common base Xtensa instruction set architecture. The configuration used in this paper has the minimum set of configuration options and includes only the base ISA elements without custom instruction extensions. The power minimization techniques discussed can be applied equally to any Xtensa processor configuration.

2