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Final

  Report to the IKY Foundation Concerning his Dissertation on Hellenistic Rhetoric (Issue of Atticism and Asianism in Hellenistic Rhetoric). Dimitrios Papanikolaou To cite this version: Dimitrios Papanikolaou. Final Report to the IKY Foundation Concerning his Dissertation on Hellenistic Rhetoric (Issue of Atticism and Asianism in Hellenistic Rhetoric). . [Research Report] IKY Foundation. 2008, pp.11. hal-01827045


O Bichler

D Roclin

C Gamrat

D Querlioz
email: damien.querlioz@u-psud.fr

Design Exploration Methodology for Memristor-Based Spiking Neuromorphic Architectures with the Xnet Event-Driven Simulator

We introduce an event-based methodology, and its accompanying simulator ("Xnet") for memristive nanodevicebased neuromorphic hardware, which aims to provide an intermediate modeling level, between low-level hardware description languages and high-level neural networks simulators used primarily in neurosciences. This simulator was used to establish several results on Spike-Timing-Dependent Plasticity (STDP) modeling and implementation with Resistive RAM (RRAM), Conductive Bridge RAM (CBRAM) and Phase-Change Memory (PCM) type of memristive nanodevices. We present several simulation case studies that illustrate the event-based simulation strategies that we implemented, including unsupervised features extraction and Monte Carlo simulations. A discussion comparing event-based and fixed time-step simulation is included as well, and gives some metrics to guide the choice between the two depending on the application to simulate.

I. INTRODUCTION

F OLLOWING the advancements in computational neu- roscience, spiking neuromorphic hardware has gained momentum over the last years [START_REF] Furber | High-performance computing for systems of spiking neurons[END_REF]- [START_REF] Arthur | Building block of a programmable neuromorphic substrate: A digital neurosynaptic core[END_REF]. This trend is reinforced with the latest proposals to use memristive nanodevices as synapses, which are particularly attractive to implement efficient timing-based learning rules like Spike-Timing-Dependent Plasticity (STDP) in dense crossbar arrays [START_REF] Snider | Spike-timing-dependent learning in memristive nanodevices[END_REF]- [START_REF] Zamarreño-Ramos | On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex[END_REF]. A major focus of Spiking Neural Network (SNN) hardware is to capture biological processes with a much higher realism than earlier Artificial Neural Networks (ANN), thus enabling richer interactions with neuroscience, large-scale hardwareaccelerated neural simulations and real-time behaving systems [START_REF] Indiveri | Neuromorphic silicon neuron circuits[END_REF]. Another emerging field of applications for SNN are hardware Intellectual Property (IP) cores, especially in embedded computers, where efficiency is a major focus. SNN could indeed complement or replace otherwise computationally heavy sensor processing, like audio or video patterns extraction, learning, recognition and tracking. To model such systems, hardware description languages such as VHDL [START_REF]VHDL Language Reference Manual[END_REF], Verilog or SystemC [START_REF]SystemC Language Reference Manual[END_REF] do not provide the appropriate level of abstraction for fast and efficient architectural exploration, which generally implies tuning the network topology, neural parameters or learning rules depending on the intended task. At the opposite, neural network simulators popular in the This work has been supported by EU-FET grant "SYnaptic MOlecular NEtworks for Bio-inspired Information Processing (SYMONE)" (318597). neuroscience community such as Neuron [START_REF] Carnevale | The NEURON Book[END_REF], Brian [START_REF] Goodman | Brian: a simulator for spiking neural networks in python[END_REF] or NEST [START_REF] Gewaltig | NEST (NEural Simulation Tool)[END_REF] can provide a higher level of abstraction. However, they lack the integration of synaptic memristive device modeling, hardware constraints and any custom features required for the targeted application.

Additionally, aggressively scaled down analog sub-threshold CMOS neurons and memristive nano-devices are plagued by device-to-device variations and intrinsic device variability to a large extend [START_REF] Alibart | High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm[END_REF], [START_REF] Suri | CBRAM devices as binary synapses for low-power stochastic neuromorphic systems: Auditory (cochlea) and visual (retina) cognitive processing applications[END_REF]. Tacking into account this variability at a system level is becoming increasingly critical as it is more and more challenging to conceal it at the device level. This is however typically hard and expensive to tackle with both hardware description languages and high-level NN simulators.

To provide an intermediate modeling level for neuromorphic hardware, we introduce several event-based simulation strategies that are implemented in our event-driven simulator ("Xnet"). It is aimed to be a simple and effective simulator, which is designed from the beginning to integrate variability and stochasticity in both synaptic and neural models. With semi-physical synaptic device models, event-based simulation can also be used to estimate the synaptic power consumption of the system and to give direct feedback for technological optimization.

In the first section of this paper, we briefly introduce the event-based model used for memristive devices based neuromorphic hardware. Several case studies are presented in section II, namely event-driven spike shape modeling, unsupervised features extraction with LIF neuron model equipped with STDP and lateral inhibition introduced earlier, phasechange memory detailed device and system modeling, Monte Carlo simulations and genetic optimization of parameters. Finally, event-based simulation is compared with the Brian fixed time-step one in section III, in order to illustrate the main differences between the two types of simulation and give some metrics to guide the choice between the two depending on the parameters of the problem.

II. METHODOLOGY

The programming and reading pulses applied on the nanodevices (or "synapses") constitute the base events in our spiking neuromorphic hardware. They are sent or received by the networks nodes -its "neurons". These neurons are the active elements in the network and are implemented with analog or digital CMOS. In Xnet, the neurons are modeled functionally for computational efficiency. To simulate the system, we propose a mixed and flexible event processing model. The use of the C++ programming language [START_REF][END_REF] fulfills the need for a systems level language that provides high-level abstractions and fast simulations.

A. Events Processing

The simple yet flexible event processing engine, which is used in Xnet, is presented in figure 1. It is organized around an event queue, implemented with a priority queue of the C++ standard library. This turned out to be the most efficient structure for this purpose. The events are sorted by their timestamp. The event on top of the queue is therefore the next event scheduled to take place. When an event is processed, it induces new events. Their timestamp is calculated using the voltages in the system, and the models for the neurons and the synapses. The new events are inserted and sorted in the event queue. Events that have been processed are removed from the queue. An event can be a neuron spiking, or a voltage in the system changing. Some events cause some memristive nanodevices to change their conductance, and thus the system to learn.

This event processing engine differs from some spiking neural networks simulators that do not compute the events' exact timings (like SpikeNET [START_REF] Delorme | SpikeNET: A simulator for modeling large networks of integrate and fire neurons[END_REF]), but just model the events' order. Knowing the exact timings is necessary for using nanodevices models. Events processing in Xnet. The next scheduled event is processed by its destination node in the incomingSpike() method (1), which can create internal events (2) that are inserted into the priority queue [START_REF] Choudhary | Silicon neurons that compute[END_REF]. Internal events are processed by the emitSpike() method (4), which can then emit events towards output nodes by calling their propagateSpike() method (5).

#2 #1 #4 #3 #5 #1, #

B. Input Stimuli Generation

The input nodes of a network can be mapped to various types of external stimuli summarized in figure 2. Static frames and auditory stimuli can be temporally coded to emulate spiking retina-or cochlea-like sensors [START_REF] Lichtsteiner | A 128×128 120 dB 15 µs latency asynchronous temporal contrast vision sensor[END_REF], [START_REF] Liu | Event-based 64channel binaural silicon cochlea with Q enhancement mechanisms[END_REF]. Address Event Representation (AER) data can be loaded directly to form the input stimuli. AER is a standard asynchronous communication protocol, widely used in the neuromorphic hardware community for communication between spiking neurons. Possible input stimuli: AER recording, static image and audio waveform. The pre-processing and temporal coding steps can be adapted to emulate hardware sensors or pre-processing units.

The basic building block to implement competitive learning is a group of neurons fully connected to the inputs with global lateral inhibition, as shown in figure 3. Lateral inhibition can be of any form, the simplest one implementing a winnertake-all between all the neurons. Considering its nano-scale hardware implementation, the canonical form of this building block is a crossbar of memristive synaptic devices.

C. Synapse and Neuron Models

Xnet is fundamentally synapse-centric. This differs from the neural network simulators which are neuron-centric, where the synapses are usually modeled as a single floating number parameter. In Xnet, the neurons and associated synaptic learning rule always emulate programming pulses on the synaptic devices: the two rules used in our modeling methodology are (1) they cannot change the conductance of the nanodevices in absolute value, and (2) they do not have any knowledge of the current value of the conductance (no free read before write).

Functional and/or semi-physical modeling is possible with event-based modeling. We developed models for PCM, CBRAM and RRAM devices that fit experimental characterizations for selected programming conditions: programming pulses voltage, duration and initial device conductance state. For PCM, cumulative conductance increase through progressive crystallization with identical programming pulses is modeled. The models also include the variability and stochasticity in device conductance change. Each parameters is thus modeled with a normal or log-normal distribution, with a mean and a standard deviation: minimum/maximum conductance, conductance increment/decrement upon successive programming pulses, increment/decrement damping depending on the conductance of the device, or increment/decrement effective conductance change probability, which are the main parameters used for CBRAM and RRAM devices.

By choosing experimentally a fixed programming condition, in terms of pulse voltage and duration, a simple behavioral model for conductance change can be established, using the above-mentioned parameters, without requiring a deep understanding of the underlying physics.

III. CASE STUDIES

In this section, several system-level simulation examples using Xnet are presented. They show the versatility of the simulator by integrating various hardware constraints such as voltage pulse width, lateral inhibition, phase-change memory behavioral modeling and system modeling. Monte Carlo simulations and genetic optimization of parameters capabilities are also presented.

A. Spike Shape Modeling

Although Xnet is an event-based simulator, modeling nonzero duration pulses is possible, without the performances penalty that would incur the switch to a fixed time steps simulation. Spike shape modeling is essential to model the more complex synaptic behaviors at the electrical level and reliably predict circuit performances at this level, while still working with a highly abstract description for the system and the network nodes, that can be either implemented with an analog or a digital circuit for example.

To allow spike shape modeling in Xnet, events have a type and each node in the network can define its own types. An example of a node modeling square pulses on its synapses is shown in figure 4. Event-based modeling is by nature only possible for piece-wise analytically solvable pulse and/or synaptic behavior. Moreover, because the simulation time is directly proportional to the number of events, multi-events spike modeling is suitable only up to a few events per spike or synaptic updates, compared to fixed time step simulations.

A square pulse model was used for the simulated results reported in [START_REF] Querlioz | Simulation of a memristorbased spiking neural network immune to device variations[END_REF], [START_REF] Querlioz | Immunity to device variations in a spiking neural network with memristive nanodevices[END_REF], which show unsupervised learning of the MNIST handwritten digits database through STDP on RRAM memory devices with classification performances comparable to classical ANN. Homeostasis and semi-supervised learning were also shown, using a global reward mechanism, which is easy to implement at the network level in the simulator.

B. Unsupervised Features Extraction

In this example, we present a biologically inspired approach to extract temporally correlated patterns from an asynchronous event stream using unsupervised STDP learning implemented with memristive devices. We have simulated the development of selectivity in an array of 60 neurons receiving spikes from a 128×128 pixels silicon retina chip that generates spikes in response to local increases ("positive" events) and decreases ("negative" events) in luminance at the pixel level [START_REF] Delbrück | Activity-driven, event-based vision sensors[END_REF]. The neurons implement a special form of STDP, that increases the conductance of memristive devices that were activated just before a post-synaptic spike and decreases the conductance of all the other memristive devices uniformly. The memristives devices are modeled as in [START_REF] Querlioz | Learning with memristive devices: How should we model their behavior?[END_REF]. When tested with a recorded input sequence of 10 minutes of traffic on a freeway, the system develops neurons that respond to cars moving at particular locations within the image. The complete study, featuring a two-layers system and robustness to noise and variability analysis can be found in [START_REF] Bichler | Unsupervised features extraction from asynchronous silicon retina through spike-timing-dependent plasticity[END_REF].

C. Phase-Change Memory System Modeling

The following case study present the implementation of the previous example using Phase-Change Memory (PCM) devices as synapses. PCM is a mature resistive memory technology, which is a good candidate for neuromorphic applications because of CMOS compatibility, high scalability, strong endurance, and good retention characteristics. The complete system was introduced in [START_REF] Suri | Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction[END_REF] and described in details in [START_REF] Bichler | Visual pattern extraction using energy-efficient '2-PCM synapse' neuromorphic architecture[END_REF]. Because of the specific phase-change physical process, only the increase of PCM conductance can be made gradual with identical programming voltage pulses (shown in figure 6(a)), a scheme using two PCM devices per synapse was devised and validated with Xnet (figure 6(b)). For each connection, the synaptic state is stored in a special purpose Synapse_PCM object, inherited from the base Synapse object, containing two complete sets of parameters for the behavioral model exposed in figure 6(a). Contrary to related work on PCM [START_REF] Kuzum | Low-energy robust neuromorphic computation using synaptic devices[END_REF], the simulation proposed here avoid relying on an experimental STDP characterization, but rather uses directly the device behavior for simple potentiating pulses to implement STDP, which is done very easily thanks to the event-driven nature of Xnet. Experimentally measured device variability, modeled with normal or log-normal distribution, is therefore included at the device level and its impact on the STDP characteristic can be studied through Monte Carlo simulations (see next section).

This also offers the possibility to perform detailed synaptic learning analysis and estimate the total synaptic power consumption for a given technology, as shown in table I. The energy consumption is estimated by counting the total number of read, set and reset pulses during the learning. The energy of a pulse is estimated as E ≈ V × I × t, where V , I and t are respectively the pulse voltage, current and duration. For the set and reset pulses, the current during phase change is essentially independent on the device conductance due to the threshold switching effect, and the average current measured experimentally is used. For the read pulses, the current is computed with Ohm's law according to the modeled device conductance. [START_REF] Suri | Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction[END_REF]).

D. Monte Carlo Simulations and Genetic Optimization of Parameters

Xnet includes facilities to perform distributed Monte Carlo simulations and genetic evolution on (synaptic and neural) network parameters, which are essential for variability robustness analysis and parameter space exploration. To this end, it implements a transparent, efficient and type-safe mechanism (derived from "Chameleon Objects" [START_REF] Simonis | Heterogeneous, nested STL containers in C++[END_REF]) to declare any type of C++ variable as a model parameter that can be read and write into configuration files. Configuration files can be shared within a layer or distinct for each node of the network, allowing to load and save the entire state of the simulation. We use the standard Mersenne twister MT19937 pseudorandom number generator, which is optimized for Monte Carlo simulations [START_REF] Matsumoto | Mersenne twister: a 623dimensionally equidistributed uniform pseudo-random number generator[END_REF].

In a first case study, Monte Carlo simulation is used to evaluate the robustness of the learning to variability on minimum (GOFF) and maximum (GON) synaptic device conductance. The results presented in figure 7 show the recognition rate for the MNIST handwritten digit database, in function of the relative standard deviation on GOFF and GON (for extrinsic, device to device variation and intrinsic, device variation during switching) [START_REF] Querlioz | Simulation of a bio-inspired system capable of learning thanks to stochastic nanodevices[END_REF]. In this experiment, each synapse is constituted of five binary resistive devices and the learning exploits the device switching stochasticity to implement STDP.

In a second case study, genetic evolution of neural parameter is used to evaluate the performance impact of system modifications and simplifications based on the setup presented in section III-B. The figure 8 illustrates how a new set of neural parameters can be found automatically through genetic evolution for a new system, with 4 bits digital synapses, linear neural leak instead of exponential and order-based STDP, Synapses are constituted of binary resistive devices and learning is stochastic [START_REF] Querlioz | Simulation of a bio-inspired system capable of learning thanks to stochastic nanodevices[END_REF].

where only the synapses activated by the latest 8192 events are potentiated upon activation of the output neuron [START_REF] Roclin | Design study of an efficient digital order-based STDP neuron implementation for temporal features extraction[END_REF].

IV. EVENT-BASED VS. FIXED TIME-STEP SIMULATION

In the following, we compare the Xnet event-based simulation with the Brian fixed time-step one, in order to illustrate the main differences between the two types of simulation. We give some performance metrics, to help choosing the simulation type that is the most adapted depending on the parameters of the problem, regardless of the absolute figures obtained for this particular benchmark. Brian is used in its default configuration (according to the documentation, typical gains of 30% can be expected when activating compiled C code optimizations).

Xnet is not designed for biological systems modeling and simulation, contrary to neurosciences simulators, which are not designed to simulate neuromorphic hardware. The Brian simulator [START_REF] Goodman | Brian: a simulator for spiking neural networks in python[END_REF] however integrates more and more features towards this end. Using some Brian 1.4 experimental features, it is possible to emulate approximately the unsupervised features extraction presented earlier, from an AER recording. One limitation is that it does not allow to reset the membrane potential of the neurons through lateral inhibition directly, however this can be circumvented by disabling the presynaptic pulses integration during the inhibitory period, which allows the membrane potential to leak to zero.

The results in table II show that for 60 neurons (∼2 millions synapses), Xnet is ∼400% faster than Brian with a default time step of 0.1 ms. In this simulation, each neuron is fully connected to the AER retina. The number of events is therefore proportional to the number of neurons, as each AER event is distributed to every neuron. With five times more neurons (300 neurons), the event-based simulation is as expected more than five times longer and uses five time more memory. As the number of events per time-step increases, clock-based simulation becomes more efficient and the Brian simulation is almost as fast as Xnet for 300 neurons. However, this can have side effects such as ineffective lateral inhibition, if multiple neurons fire in the same time-step, or poor precision during learning, if the time-step is several percents of the LTP or LTD windows. These issues are non-existent in event-based simulation, where the time precision is arbitrary (one femtosecond in Xnet). Parallelization of the event-driven priority queue is possible, although not implemented in Xnet, where code correctness and simplicity are preferred over simulation speed (which is not restrictive for our current needs). A one order of magnitude smaller time-step in Brian does not multiply the simulation time by ten, because synaptic updates are event-driven even in Brian and there is lateral inhibition in the simulated network.

The memory consumption is dominated by the synaptic parameters, which can be significant for semi-physical memristive device models. With a simple behavioral model, ten state variables are used for each synapse in Xnet, compared to only one state variable per connection in the equivalent Brian simulation, where synaptic variability is not modeled. V. CONCLUSION Xnet was developed to allow fast and efficient design exploration of spiking neuromorphic architectures by providing a framework that can mix high-level behavioral modeling with hardware constraints integration. More specifically, it was designed with spiking retina and memristive nano-devices based architectures in mind. The Xnet source code is currently not licensed, but is available through partnership with CEA LIST. Additional information on implementation details is available upon request.

This simulator, along with its accompanying methodology was used for the simulations in several papers published by our group [START_REF] Querlioz | Simulation of a memristorbased spiking neural network immune to device variations[END_REF], [START_REF] Bichler | Unsupervised features extraction from asynchronous silicon retina through spike-timing-dependent plasticity[END_REF]- [START_REF] Bichler | Visual pattern extraction using energy-efficient '2-PCM synapse' neuromorphic architecture[END_REF] and is now mature and useful to be introduced to the community, in addition to the necessity to provide means of reproducing and validating scientific results.

Until now, the neuromorphic hardware community lacked a generic and efficient framework for high-level memristorbased spiking neuromorphic architectures exploration. We hope that Xnet will be a first step towards such a framework, as it proved to be extremely valuable for rapid evaluation of new nanodevices and for a better understanding of STDP-like learning rules. Xnet is always under active development, with current integration of magnetic tunnel junction synaptic device model and audio processing and learning simulations.

Fig. 1 .

 1 Fig.1. Events processing in Xnet. The next scheduled event is processed by its destination node in the incomingSpike() method (1), which can create internal events (2) that are inserted into the priority queue (3). Internal events are processed by the emitSpike() method (4), which can then emit events towards output nodes by calling their propagateSpike() method[START_REF] Snider | Spike-timing-dependent learning in memristive nanodevices[END_REF].

  Fig. 2.Possible input stimuli: AER recording, static image and audio waveform. The pre-processing and temporal coding steps can be adapted to emulate hardware sensors or pre-processing units.

Fig. 3 .

 3 Fig. 3. Basic building block for a group of neurons, which can feature lateral inhibition. Left: topological view. Right: flattened view in a crossbar of synaptic elements.

Fig. 4 .

 4 Fig. 4.Non-zero duration pulse modeling in Xnet. The EventOn and EventOff event types model respectively the rising edge and the falling edge of the electrical pulse.

Fig. 5 .Fig. 6 .

 56 Fig. 5. Output reporting for a typical simulation. (a) Raster plot for 10 output nodes. (b) Internal integration state of a neuron. (c) Firing rate for 10 output nodes. (d) Weights reconstruction for an output neuron.

  Total Synapses: 1,966,680 [= 1st Layer (2×128×128×60) 2nd (60×10)] Total PCM cells: 3,933,360 [= 2× Total Synapses (LTP and LTD)] Total learning duration = 680 s Quantity Values for Number of pulses Energy consumption Total read pulses 4,975,830,080 0.12 pJ Total set pulses 416,334,080 121 pJ Total reset pulses 16,585,048 1552 pJ Total synaptic power consumption 112 µW

Fig. 7 .

 7 Fig. 7. Monte Carlo robustness analysis on digit recognition for intrinsic and extrinsic min. (GOFF) and max. (GON) synaptic conductance variability.Synapses are constituted of binary resistive devices and learning is stochastic[START_REF] Querlioz | Simulation of a bio-inspired system capable of learning thanks to stochastic nanodevices[END_REF].

Fig. 8 .

 8 Fig.8. Genetic evolution on neural parameters in Xnet to evaluate the performances of the simplified unsupervised features extraction system with 4 bits digital synapses, linear leak and order-based STDP[START_REF] Roclin | Design study of an efficient digital order-based STDP neuron implementation for temporal features extraction[END_REF]. The insets show the weights map of an output neuron after the learning of the car sequence, for four sets of parameter obtained at different point in the genetic evolution.

  , ∆T =0.01 ms) 5168 s (×39) 4881 MB (×14)

TABLE I LEARNING

 I STATISTICS FOR THE PCM-BASED NEUROMORPHIC CIRCUIT, USED TO ESTIMATE THE SYNAPTIC POWER CONSUMPTION OF THE SYSTEM (FOR LANCE-TYPE GST-PCM TEST DEVICES, WITH A 100 NM THICK PHASE CHANGE LAYER AND 300 NM DIAMETER TUNGSTEN PLUG

TABLE II XNET

 II AND BRIAN PERFORMANCES COMPARISON. THERE ARE 1,966,080 SYNAPSES FOR N=60 NEURONS AND 9,830,400 SYNAPSES FOR N=300 NEURONS. XNET PROCESSES IN AVERAGE 2 MILLION EVENTS/SECOND. Setup Exec. time Memory cons.


Giorgio Palma

Manan Suri

Damien Querlioz

Elisa Vianello

Barbara De Salvo

Stochastic neuron design using Conductive Bridge RAM

We present an original methodology to design hybrid neuron circuits (CMOS + non volatile resistive memory) with stochastic firing behaviour. In order to implement stochastic firing, we exploit unavoidable intrinsic variability occurring in emerging non-volatile resistive memory technologies. In particular, we use the variability on the 'time-to-set' (tset) and 'off-state resistance' (R Off ) of Ag/GeS2 based Conductive Bridge (CBRAM) memory devices. We propose a circuit and a novel self-programming technique for using CBRAM devices inside standard Integrate and Fire neurons. Our proposed solution is extremely compact with an additional area overhead of 1R-3T. The additional energy consumption to implement stochasticity in Integrate and Fire neurons is dominated by the CBRAM set-process. These results highlight the benefits of novel non memory technologies, whose impact may go far beyond traditional memory markets.

I. INTRODUCTION

Neuroinspired (or 'neuromorphic') hardware research has gained a lot of importance in recent years due to its promising low-power, fault-tolerant, and ultra-adaptative computing paradigms [START_REF] Modha | Cognitive computing[END_REF], [START_REF] Snider | From Synapses to Circuitry: Using Memristive Memory to Explore the Electronic Brain[END_REF], [START_REF] Merolla | A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm[END_REF], [START_REF] Suri | Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction[END_REF], [START_REF] Sharad | Spin-Based Neuron Model with Domain-Wall Magnets as Synapse[END_REF]. Neuromorphic computing is usually accomplished with deterministic devices and circuits. However, literature in the fields of neural networks [START_REF] Alspector | Performance of a stochastic learning microchip[END_REF], [START_REF] Van Daalen | A stochastic neural architecture that exploits dynamically reconfigurable FPGAs[END_REF] and of biology [START_REF] Fusi | Cascade models of synaptically stored memories[END_REF] suggests that in many situations, actually providing a certain degree of stochastic, noisy or probabilistic behavior in their building blocks may enhance the capability and stability of neuroinspired systems. Some kind of neural networks even fundamentally rely on stochastic neurons, like Boltzmann machines [START_REF] Hinton | Reducing the Dimensionality of Data with Neural Networks[END_REF], [START_REF] Salakhutdinov | An Efficient Learning Procedure for Deep Boltzmann Machines[END_REF]. Finally, stochastic neurons may perform signal processing in extremely noisy environments using a phenomenon known as 'stochastic resonance' [START_REF] Wiesenfeld | A Stochastic resonance and the benefits of noise: from ice ages to crayfish and SQUIDs[END_REF], [START_REF] Querlioz | Stochastic Resonance in an Analog Current-Mode Neuromorphic Circuit[END_REF].

In neuromorphic hardware, providing stochastic behavior to neurons using pseudo-random number generators will lead to significant overheads. This explains interest in developing silicon neurons with an intrinsic stochastic behavior, but which may be controlled. In previous works, different techniques to implement controlled stochasticity in hardware neural networks have proposed. It is possible to exploit the thermal noise in the CMOS but this may lead to silicon overheads and unwanted correlations [START_REF] Alspector | Performance of a stochastic learning microchip[END_REF]. Other techniques exploit CMOS circuits with using noise but have significant area overhead [START_REF] Alspector | A VLSIefficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks[END_REF], or the noise of photons with photodetectors [START_REF] Cameron | Poisson distributed noise generation for spiking neural applications[END_REF] or even special kinds of 'noisy transistors' [START_REF] Chiu | An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise[END_REF]. Finally it was proposed to use fundamentally probabilistic nanodevices like single electron transistors [START_REF] Oya | Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks[END_REF], but which might suffer from poor CMOS compatibility and room temperature operation. In this paper, we describe an original circuit and methodology to design a neuron with stochastic firing behavior exploiting certain physical effects of emerging non-volatile resistive memory technology devices such as Conductive Bridge memory (CBRAM). There are significant advantages of our approach because of the easiness of fabrication in the Back-End-Of-Line (BEOL), CMOS compatibility [START_REF] Dietrich | A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control[END_REF], predicted scalability to sub-20 nm [START_REF] Kund | Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm[END_REF] and low programming voltages of CBRAM memory devices [START_REF] Vianello | Sb-doped GeS 2 as performance and reliability booster in Conductive Bridge RAM[END_REF]. The remainder of this paper is organized as follows: in Section II, we describe the structure and the working principle of our CBRAM devices, and the stochastic effects which we exploit for designing the non-deterministic firing neuron. Section III, describes the basic concept and an example of simple circuit for obtaining a stochastic neuron. Section IV discusses transient simulations that we performed on a basic circuit, which validates our concept.

-0.2 -0.1 0 0.1 0.2 0.3 V c [V]

II. CBRAM TECHNOLOGY

A. Structure and working principle

Fig. 1 shows a TEM image of the CBRAM device structure used in this work. A Tungsten (W) plug, typically used as interconnect between two metal levels, is used as bottom electrode for the CBRAM. The solid electrolyte consists of a 30 nm thick GeS 2 layer deposited by radio frequency physical vapour deposition (RF-PVD). A 3 nm Ag layer is dissolved into the GeS 2 using the photo-diffusion process [START_REF] Mitkova | Silver incorporation in GeSe glasses used in programmable metallization cell devices[END_REF]. Then a 2 nd layer of Ag is deposited to act as top electrode. CBRAM working principle relies on the reversible formation of a conductive filament (CF) through a solid electrolyte that results in transition to low and high resistance, respectively, which are referred to as set and reset processes (Fig. 1) [START_REF] Ielmini | Modeling the universal Set/Reset Characteristics of Bipolar RRAM by Field-and Temperature-Driven Filament Growth[END_REF]. During the set process a positive voltage is applied to the anode which oxidizes, generating Ag + ions. The latters, under the influence of the electric field, migrate by hopping to the W cathode where they are reduced and nucleate, building-up an Ag-rich CF. Upon reversal of voltage polarity, besides an electronic current flowing in the CF, an electrochemical current gives rise to Ag + ions, inducing a collapse of the filament radius resetting the system to the high resistance state [START_REF] Waser | Redox-based resistive switching memories-nanoionic mechanisms, prospects, and challenges[END_REF].

B. Stochastic effects

By cycling many times our devices a statistical distribution of the high resistive state (R Off ) was obtained. Dispersion in R Off may be interpreted in terms of stochastic breaking of the filament during the reset process, due to the unavoidable defects close to the filament which act as preferential sites for dissolution. In previous work [START_REF] Suri | CBRAM devices as binary synapses for lowpower stochastic neuromorphic systems: Auditory (Cochlea) and visual (Retina) cognitive processing applications[END_REF] we showed, with the help of modeling, that a distribution in R Off leads to a spread in others physical quantities like the left-over filament height (h) and the t set . In this work we push further the analysis by matching the modeled t set distribution with experimental data. In particular, we characterized the kinetic of the set operation by pulse measurements. Fig. 2 inset shows an example of the oscilloscope trace for the evolution of voltage drop across the cell (V c ) during a set pulse. Initially, the cell is in the high resistive state (R Off ≃ 10 6 Ω) and most of the applied voltage drops on the cell. Then at time t set an abrupt decrease of V c is observed, revealing a sudden drop of the cell resistance corresponding to the switching from high to low resistive state. Starting from some of the measured values of R Off (Fig. 2(a)) we collected the spread in t set when the applied pulses were V a =3 V and t pulse =5 µs (Fig. 2(b)). The dotted line in Fig. 2(b), shows the simulated values of t set . To obtain the simulated curve of t set , first the distribution of h was calculated using [START_REF] Strukov | The missing memristor found[END_REF], [START_REF] Yu | Compact modeling of a Conducting Bridge Random Access memories (CBRAM)[END_REF]:

R Off = ρ on h + ρ off (L -h) πr 2 (1)
where ρ on is the resistivity of the Ag-rich nanofilament, ρ off is the resistivity of the GeS 2 , L is the chalcogenide thickness and r is the conductive filament radius, then t set using:

t set = L -h v h exp -EA kB T sinh αq Vc-∆ kB T ( 2
)
where q is the elementary charge, v h is a fitting parameter for the vertical evolution velocity, E A is the activation energy, k B is the Boltzmann constant, T is the temperature (300 K), α and ∆ are fitting parameters to take into account vertical electric field dependency and the overpotential that controls the kinetic of the cathodic reaction respectively (Table I). In the following section we show how the spread in t set can be used to make the firing of an Integrate and Fire neuron non-deterministic.

III. STOCHASTIC NEURON DESIGN

A. Integrate and Fire Neuron

The complexity of a neuron circuit depends on the overall functionality of the neural network and of the chosen biological models. For our purpose of concept validation, we chose one of the simplest, the Integrate and Fire neuron model. Fig. 3(a) shows the concept of a simple Integrate and Fire neuron model. It constantly sums (integrates) the incoming synapticinputs or currents (excitatory and inhibitory) inside the neuron integration block using a capacitor. More advanced designs also work with this principle [START_REF] Indiveri | Neuromorphic silicon neuron circuits[END_REF]. This integration leads to an increase in the membrane potential of the neuron V mem . When the membrane potential reaches a certain threshold value V th , the neuron generates an output spike (electrical signal). After the neuron has fired the membrane potential goes back to a resting value (initial state), through discharging of the capacitor C mem . Usually, the output firing activity of a Integrate and Fire neuron is deterministic because the neuron fires every time the membrane potential reaches a defined threshold value.

Parameter

Value Parameter Value

v h 2 m/s E A 0.35 eV ρon 2.3 × 10 -6 Ω m ρ off 10 -3 Ω m α 0.08 ∆ 0.15 V r 2.2 nm L 30 nm inter spike interval V t t t t V V V a) b) c) d)

B. Stochastic-Integrate and Fire principle and circuit

To introduce non-deterministic or stochastic behavior in Integrate and Fire neuron, we propose to connect a CBRAM device to the capacitor C mem , such that C mem could only discharge through the CBRAM device by switching it to the low-resistive state (Fig. 3(b)). The anode of the CBRAM and the V mem net of the capacitor should be connected. The duration for which current can flow through the low-resistive CBRAM device can be controlled using a transistor. In such a configuration, the spread on the t set of the CBRAM would translate to a spread on the discharge-time (t dsc ) of the capacitor. For consecutive neuron spikes, this would lead different initial state of C mem , thus making the firing of the neuron stochastic. Fig. 4 illustrates conceptually the impact of four different values of t set (keeping constant pre-synaptic weights), on the inter-spike interval. In case (a), t set is very long thus the capacitor has a very weak discharge. As a consequence just few additional incoming preneuron spikes are required to charge back the V mem to the level of V th , thus leading to an output pattern with the shortest interspike interval. In case (b), t set was the shortest, and hence the capacitor discharged the most.

Thus for this case, more incoming pre-neuron spikes are needed to recharge V mem . Case (c) represents a deterministic Integrate and Fire situation with full V mem discharge. Finally, case (d) depicts a situation with different t set durations for consecutive output spikes. It is a possible representation of neuron inter-spike intervals for a random sequence of t set values that can be obtained by cycling the CBRAM device multiple times.

The circuit equivalent of the Stochastic-Integrate and Fire neuron concept shown in Fig. 3(b) is presented in Fig. 5. It consists of a current-source to simulate input currents coming from synapses and pre-neurons, a capacitor C mem to integrate the current and build up the neuron membrane-voltage V mem , a nMOS transistor M1 to perform set operation, two nMOS transistors M2 and M3 to perform the reset operation, a comparator block, a spike-generation block, a delay-element ∆t and a CBRAM device. The delay element is used to perform the reset operation of the CBRAM device at the end of each neuron spike.

In Fig. 5, initially the CBRAM is in high-resistive state. As incoming pre-synaptic current is accumulated in C mem , V mem would constantly build up at the anode of the CBRAM. During this time M1, M2 and M3 are off. When the neuron spikes, the spike-generation block will generate an output-spike and two additional pulsed-signals (S1, S2) going to M1 and ∆t respectively. S1 acts as a gating signal to turn on M1. V mem build-up and switching on of M1 will enable set-operation of the CBRAM since a positive voltage drop is established between the anode and the cathode. However during the set-operation, M2 and M3 are not turned on, as ∆t delays the signal S2. At the end of the set-operation, the signal S2 will turn on M2 and M3 thus building up the voltage at the cathode to switch the CBRAM to the off-state (reset). Thus, before the next consecutive neuron spikes the CBRAM device is automatically reset and reprogrammed to a different initial R Off state. Note that the flow of current through the CBRAM, during the setoperation, leads to a discharge of the capacitor C mem thus decreasing the membrane voltage V mem . The amount of decrease in V mem can be estimated by calculating the total duration (t dsc ) for which current flows through the switched CBRAM. t dsc is the difference of the pulse-width of the signal S1 and the t set (inset of Fig. 2). Depending on the value of t set every time the neuron spikes, different amount of C mem discharge will occur. Thus, in between any two firing cycles, the neuron may require different amount of incoming current to charge V mem to the level of V th .

1.05e-05 1.1e-05 Time [s] 0 1 2 3 4 Voltage [V] V mem (tset=300ns) V mem (tset=400ns) V mem (tset=500ns) V mem (tset=600ns) 0 2e-05 4e-05 Current [A]

IV. RESULTS AND DISCUSSION

A. Set-and reset-operation

We performed SPICE transient simulation, with Eldo simulator, to validate the proposed concept using a simplified circuit shown in Fig. 6. Transistors and capacitors sizing were not optimized with respect to a real implementation, but to give a simple proof-of-concept. Fig. 7(a) shows a simulated train of incoming pulses (excitatory currents) and the corresponding evolution of the V mem (Fig. 7(b)) between two consecutive neuron spike-cycles. When V mem reaches a threshold voltage V th (V th ≃ 3.5 V in our simulation), the CBRAM device undergoes set-operation, and C mem begins to discharge. Fig. 7(b) shows the discharging and re-charging of C mem for four different simulated values of t set (in the range 300 ns -600 ns). Fig. 7(c), shows the expected output of the neuron. Note that different number of incoming pulses are required to reach the neuron firing threshold again, since the initial V mem value is dominated by the stochasticity in t set . Five additional incoming pulses are needed to reach the threshold for the shortest value of t set (300 ns). Fig. 8 shows the zoomed version of C mem discharging for the the different simulations shown in Fig. 7. Note that the longest t set (600 ns) corresponds to the least amount of C mem discharge, and vice-versa. To simulate the reset operation, a pulse of 45 ns with an amplitude of 3 V was applied at M2 and M3, while keeping M1 off. Such high voltage on M3 is required to build up a voltage on V cathode . Fig. 9 shows the time evolution of V cathode and V mem when the initial value of V mem was generated by a t set of 300 ns for two different width of M3. The actual voltage drop on the CBRAM can be increased increasing the size of the nMOS as shown in Fig. 9. Moreover, during the reset, an additional discharge of V mem is possible depending on the size of M3, since M2, that is directly connected to V mem , is turned on by S2 (Fig. 10(a)).

B. Parameter constraints

Due to the intrinsic physics of CBRAM device, some constraints in implementing the proposed circuit should be considered. In particular, V th has to be greater than the minimum value of the voltage-drop required to set the CBRAM device for a given pulse-width. The amplitude of S1 should be sufficient to turn on the gate of M1, while the pulse-width of S1 depends on the V th and the spread on t set . If S1 pulse-width is very long it would always lead to a complete discharge of C mem and the t set stochasticity cannot be exploited. However S1 cannot be arbitrarily small, it has to be greater than the minimum t set value at a given voltage applied on the anode of the CBRAM device. In a previous work, we have shown the dependence of applied pulse-width and the amplitude of V a for the CBRAM set-operation [START_REF] Vianello | Sb-doped GeS 2 as performance and reliability booster in Conductive Bridge RAM[END_REF]. Thus, by tuning the characteristics of S1, the stochastic response of the neuron can be controlled. The amplitude of S1 would determine the amount of current flowing through M1 (compliance current) and thus the final value of the CBRAM resistance in the set state. The set state resistance would determine the programming conditions for the consecutive reset-operation [START_REF] Longnos | On disturb immunity and P/E kinetics of Sb-doped GeS 2 /Ag Conductive Bridge Memories[END_REF]. Thus, the characteristics of S2 can be tuned based on the final CBRAM resistance obtained after the set-operation.

C. Energy consumption

For the proposed S-IF, additional energy consumption per spiking cycling of the neuron will be devoted to perform set and reset operation. The extra-energy consumption is dependent on the ratio R Off /R On ; in particular on R On since hundreds of µ A can flow before M1 would be turned off, if the low resistance state is ≃ 10 4 Ω, thus raising the power consumption. We estimated the energy consumption during the set operation using: E set =V set I set t set . In our simulations we used V set =3.5 V (i.e. V th ), I set =350 µ A, t set in a range between 300 ns and 600 ns that gives a E set energy mean value of 55 n J. The energy devoted to reset the CBRAM is negligible. For a real system, E set can be strongly reduced increasing the resistance of the low resistive value thus reducing I set , since for the proposed application the ratio R Off /R On is not a major constraint.

V. CONCLUSIONS

In this paper, we showed how CBRAM used in an unexpected fashion may allow designing stochastic neurons with low area overheads. We described how CBRAM physics naturally leads to a stochastic behavior in the programming time (t set ), which may be exploited in a circuit. SPICE simulations validate the concept on a simple Integrate and Fire neuron. The concept could be extended to more complex neuron designs like [START_REF] Indiveri | Neuromorphic silicon neuron circuits[END_REF] and [START_REF] Arthur | Silicon-Neuron Design: A Dynamical Systems Approach[END_REF], paving the way for the fabrication of complex neuromorphic networks. Other emerging memory technologies might be used for the same purpose provided a certain range of stochasticity in t set as reported in [START_REF] Sakamoto | A Ta2O5 solid-electrolyte switch with improved reliability[END_REF] and [START_REF] Kaeriyama | A nonvolatile programmable solid-electrolyte nanometer switch[END_REF]. These results highlight the benefits of novel non memory technologies, whose impact may go beyond traditional memory markets.

Fig. 1 .

 1 Fig.1. Quasi-static I-V curve for the CBRAM device showing the switching from high (reset) to low resistive states (set). TEM image of the CBRAM resistor element[START_REF] Suri | CBRAM devices as binary synapses for lowpower stochastic neuromorphic systems: Auditory (Cochlea) and visual (Retina) cognitive processing applications[END_REF]. The GeS 2 layer has a thickness of 30 nm.

Fig. 2 .

 2 Fig. 2. (a) R Off distribution obtained in GeS 2 based 1R CBRAM devices.(b) Experimental (line) and simulated (dotted) tset distribution obtained cycling the CBRAM cell with a pulse amplitude Va=3 V. (b in the inset) Example of a typical oscilloscope trace tracking the voltage on the CBRAM (Vc) and the applied pulse (Va). Between every set operation a reset operation was performed (not shown).

Fig. 3 .

 3 Fig. 3. (a) Schematic image shown the basic concept of a Integrate and Fire neuron [26]. (b) Schematic showing the basic concept of our proposed Stochastic Integrate-Fire neuron (S-IF).

Fig. 4 .

 4 Fig. 4. (a)-(d) Schematic of output neuron firing patterns for different example test cases.

Fig. 5 .

 5 Fig. 5. Proposed circuit-equivalent of the S-IF neuron.

Fig. 6 .

 6 Fig.[START_REF] Alspector | Performance of a stochastic learning microchip[END_REF]. Circuit used to demonstrate the concept of a S-IF effect when the CBRAM is in the set state.

Fig. 7 .

 7 Fig. 7. Full evolution of Vmem simulating the circuit shown in Fig. 6. (a) Preneuron incoming pulses are used to build up Vmem. (b) Initially Vmem builds up as consequence of incoming currents (charging phase). Set operation lead to different discharge of Cmem (t dsc ). During the recharging phase a different number of incoming pulses will raise Vmem till V th . (c) Expected different interspike intervals depending on the tset.

Fig. 8 .Fig. 9 .

 89 Fig. 8. (a) Pre-neuron incoming pulses are used to build up Vmem. (b) Zoom on Vmem during the discharging phase for different tset in the range 300 ns-600 ns. Lower tset leads to lower residual membrane voltage Vmem.

Fig. 10 .

 10 Fig. 10. (a) Time-evolution of Vmem during the reset operation for tset in the range 300 ns -600 ns. Different residual voltages are obtained. (b) Pulse applied to M3.

TABLE I PARAMETERS

 I USED IN THE SIMULATIONS.

ACKNOWLEDGMENT

The PhD of M. Suri is co-financed by DGA-France. The authors would like to thank ALTIS semiconductors for providing the CBRAM devices for this study.


Damien Querlioz
email: damien.querlioz@u-psud.fr

Vincent Trauchessec

Stochastic Resonance in an Analog Current-Mode Neuromorphic Circuit

Keywords: stochastic resonance, neuromorphic, spiking neural networks, noise. I

Stochastic resonance is a general phenomenon by which the sensitivity of a system to small inputs may be increased by the addition of noise. In this paper, we show that a neuro-inspired analog circuit naturally exhibits stochastic resonance. Transient circuit simulations allow the recognition of the evidence of this phenomenon. Detailed analyses show the importance of well choosing a specific neuronal parameter, the refractory period, so that the resonance can be used in practice. These results open the way for neuromorphic designs to process noisy data without signal processing, or to work in extremely noisy environments.

INTRODUCTION

Noise and unpredictability are becoming central issues in electronics circuits and systems research. Many modern applications of electronics (biological, medical or ubiquitous sensing applications) have to process naturally noisy information from the real world, using a low power budget. Furthermore, microelectronics technology itself becomes noisier in advanced technologies [START_REF] Campbell | Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs[END_REF]. This should be even more crucial if the channel material in CMOS switches to nanostructures like silicon nanowires, which exhibit high noise [START_REF] Zhuge | Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs[END_REF]. A higher noise tolerance could also allow reducing supply voltage, thus leading to power savings. Electronic circuits that work like the brain with asynchronous spikes -neuromorphic circuits -have been developed since the late 80s [START_REF] Livi | A current-mode conductance-based silicon neuron for address-event neuromorphic systems[END_REF], [START_REF] Arthur | Silicon-Neuron Design: A Dynamical Systems Approach[END_REF] and are known to operate well with real life natural data [5], [START_REF] Chan | AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface[END_REF]. It it thus natural to assess their potential for working in extremely noisy environments. This is all the more significant since it has been shown in Neuroscience works that biological neurons have extreme noise tolerance. They may even in some instances benefit from noise, exploiting an apparently paradoxical phenomenon known as stochastic resonance. This has been observed theoretically [START_REF] Longtin | Stochastic resonance in neuron models[END_REF] and experimentally [START_REF] Douglass | Noise enhancement of information transfer in crayfish mechanoreceptors by stochastic resonance[END_REF].

Stochastic resonance was originally introduced in the 80s to explain climatologic cycles, and has been observed in various physical and biological systems [START_REF] Benzi | The mechanism of stochastic resonance[END_REF], [START_REF] Wiesenfeld | Stochastic resonance and the benefits of noise: from ice ages to crayfish and SQUIDs[END_REF], and largely theorized [START_REF] Gammaitoni | Stochastic resonance[END_REF]. It states that, in some situations, the response of a system to a small stimulus may be improved by noise, and that a noise optimum may exist. The goal of this paper is to analyze if a CMOS-based neuromorphic neuron can express stochastic resonance, and to analyze its behavior. For this purpose, we perform transient circuit simulations.

The idea of getting an electronic system to express stochastic resonance has previously been proposed using nanoelectronics devices: carbon nanotubes [START_REF] Lee | Nanosignal Processing: Stochastic Resonance in Carbon Nanotubes That Detect Subthreshold Signals[END_REF], single electron devices [START_REF] Oya | Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks[END_REF] and tunnel diodes with negative differential resistance [START_REF] Hartmann | Nanowatt logic stochastic resonance in branched resonant tunneling diodes[END_REF][START_REF] Hartmann | Light-induced stochastic resonance in a nanoscale resonant-tunneling diode[END_REF][START_REF] Samardak | Spiking computation and stochastic amplification in a neuron-like semiconductor microstructure[END_REF]. It has also been proposed in bistable CMOS circuits [START_REF] Harmer | A review of stochastic resonance: circuits and measurement[END_REF], [START_REF] Luchinsky | Stochastic resonance in electrical circuits. I. Conventional stochastic resonance[END_REF], which implement the traditional equations of stochastic resonance.

In this work, we propose to use a spiking neuromorphic CMOS circuit that can be fabricated with current commercial technologies. Unlike the previous proposals of stochastic resonant circuits, this kind of spiking design is developed widely and has been proven to scale to large systems [START_REF] Gao | Dynamical System Guided Mapping of Quantitative Neuronal Models Onto Neuromorphic Hardware[END_REF][START_REF] Serrano-Gotarredona | CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing-Learning-Actuating System for High-Speed Visual Object Recognition and Tracking[END_REF][START_REF] Merolla | A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm[END_REF][START_REF] Indiveri | Neuromorphic silicon neuron circuits[END_REF][START_REF] Partzsch | VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality[END_REF]. Exploiting stochastic resonance could be a significant advance for this kind of circuits.

The paper is organized as follows. First, we introduce the circuit and its simulation methodology. Second, we present our results and identify the stochastic resonance. Third, we discuss its meaning and significance.

II. CIRCUIT AND METHODS

The circuit is the log-domain current-mode generalized integrate-and-fire neuron from [START_REF] Livi | A current-mode conductance-based silicon neuron for address-event neuromorphic systems[END_REF], and presented in Figure 1. We stripped it from the adaptation sub-circuit, which was not necessary for this work. As many neuromorphic circuits [START_REF] Indiveri | Neuromorphic silicon neuron circuits[END_REF], the circuit uses transistors operating in the subthreshold regime, and exploits the exponential dependence of current to gate voltage. As an output, it generates digital asynchronous spikes, which can be routed to other neurons, synapses or generic digital circuits. The neuron works in real time (meaning, with time scales similar to the ones of biological neurons), which makes it appropriate to process real world dynamic data in real time. The circuit is built around a low pass filter block [START_REF] Bartolozzi | An ultra low power currentmode filter for neuromorphic systems and biomedical signal processing[END_REF]. The input is applied as a voltage on the gate of a PMOS transistor. Another block implements a positive feedback. When C mem is charged enough, the positive feedback becomes dominant, which leads to the switch of the digital transistors: the neuron spikes (or "fires"). After the neuron has spiked, the refractory period block keeps C mem discharged for a given duration, preventing the neuron from firing again. The refractory period duration is controlled directly by the V ref bias and the C ref capacitance value. All details and theory about the circuit are given in [START_REF] Livi | A current-mode conductance-based silicon neuron for address-event neuromorphic systems[END_REF].

The input was a sine function (at 10 Hz in most of the paper). In all simulations, the amplitude of the input is small enough, so that when no noise is present, the neuron does not spike. Any spike is thus caused by noise.

Noise was introduced in the circuit with an artificial voltage noise source in series with the input. This noise source was a custom device programmed in the Verilog-A language, and generated white noise.

To design the circuit, we used the design kit of a 65 nm Low Power technology from a commercial vendor. The analog transistors were implemented with the I/O transistors of the technology (regular transistors had too high leakage for an operation of the circuit in biological real time). The two capacitors C mem and C ref were also implemented with I/O transistors.

The circuit was simulated with Cadence Spectre, in transient noise simulation, with various biases and C mem and C ref capacitance values. Considering the low currents, and the permanent discontinuities introduced by noise, simulations required extremely strict tolerance criteria (vtol, itol, reltol, gmin) to ensure a reliable result. Simulation convergence was thus extremely slow, in comparison with traditional transient simulation of analog circuits. To initiate the circuit properly, the leakage bias V leak was originally set at 0 volts and then rapidly increased to its final value. The circuit was simulated during 20 s of circuit time (which is 200 periods of the input's sine function). Controls with up to 200 s of circuit time showed that the spectral analyses in this paper were not affected. Simulation time for 20 s of circuit time on a Xeon E5-1650 CPU reached several hours for the simulations with the highest noise. Output waveforms of the circuit were exported and signal processed in the Mathworks MATLAB software. A binary signal was first generated, which reproduced the spikes generated by the circuit: it is 1 when the neuron declares a spike, and 0 the rest of the time. We performed FFT on this binary signal, and not on an actual voltage waveform from the circuit. That way, subthreshold oscillations of the circuits cannot affect the FFT, and any spectral feature is really on the spiking pattern of the neuron.

III. RESULTS

Figure 2 presents the behavior of the circuit, as simulated with different noise level. We plot the input voltage with noise (superimposed with the input voltage without noise to guide the eye), as well as the "membrane current" I mem , which represents the internal state of the neuron. We materialize the neuron's spike by a thick vertical blue line on the time axis.

When there is no added noise (Figure 2(a)), the membrane current I mem oscillates, but the positive feedback is never sufficient to generate a spike: the neuron has no answer. When there is moderate noise (Figure 2(b), 0.04 V²/kHz), the membrane currents appears noisy and the positive feedback can sometimes be sufficient to generate spikes. These remain rare and seem random. Where there is higher noise (Figure 2(c), 0.1 V²/kHz), the behavior looks very different. A spike is generated almost every period of the AC input. Two spikes are never generated during the same AC input period. Basically, the neurons spikes in phase with the input, missing a period occasionally. It should be noted that, in this regime, there is so much noise that the sine function cannot be perceived in the input voltage. When there is even higher noise (Figure 2(d), 0.6 V²/kHz), the neuron spikes frequently and erratically.

If we perform FFT on the firing pattern, we get a spectrum as in Figure 3(a) (which corresponds to the signal of Figure 2(c)). A clear peak is seen at 10 Hz, the frequency of the sine function in the input voltage. We define the signal-to-noise ratio of the spiking output as the ratio of the height of this peak to the average level of the FFT on the 1-100 Hz range (excluding the peak). If we plot the signal-to-noise ratio as a function of the input noise levels, a bell curve is seen (Figure 4, full line "V ref = 0.20 V"). For zero noise, there is no signal since the neuron is not answering. For high noise, the peak is decreasing (the neuron starts to spike randomly). A maximum is existing in-between. This kind of bell curve is a signature of the stochastic resonance phenomenon [START_REF] Gammaitoni | Stochastic resonance[END_REF].

Similarly, in Fig 3(b), we plot a histogram of interspike interval in the situation of Fig 2(c). We see that the most likely interspike intervals are around the input's sine function period (0.1s). Interspike intervals around twice and three times this period also occur, and correspond to the situation where the neuron missed an input's period. This kind of inter-event intervals curve is also a signature of stochastic resonance [START_REF] Gammaitoni | Stochastic resonance[END_REF].

The results presented in Figures 2 and3 are presented with an input's frequency of 10 Hz. A similar bell curve and similar interspike interval histograms were obtained for input frequencies from 4 to 25 Hz, without changing any bias or capacitance in the circuit. IV. DISCUSSION Interestingly, stochastic resonance was easily obtained whatever the values of most of the biases and of the capacitors in the neuron's circuit. In particular it is obtained whatever the time constant of the low pass filter (which is determined by capacitance C mem and bias V leak [START_REF] Livi | A current-mode conductance-based silicon neuron for address-event neuromorphic systems[END_REF]), and the values of V thresh (provided they do not impair the circuit's basic functionality). However, we found that the parameters regarding the refractory period played a more important role. The refractory period is the time during which a neuron is prevented from firing after it has fired. It is determined by the capacitor C ref and the bias V ref in the circuit. The refractory period has a linear dependence with C ref and an exponential dependence with V ref . [START_REF] Livi | A current-mode conductance-based silicon neuron for address-event neuromorphic systems[END_REF]. This is well seen in Figure 4.

V ref = 0.30 V V ref = 0.21 V V ref = 0.19 V V ref = 0.20 V V ref = 0.15 V
For short refractory period (e.g. V ref = 0.30 V), the neurons may spike multiple times by input period. A nice bell curve is not seen, and the interspike interval histogram is broad and does not show peaks around 0.1 s and 0.2 s like in Fig. 3(b). For long refractory period (e.g. V ref = 0.15 V) the neurons rarely spike, since the refractory period is longer than one input's threshold. In both of these situations, the firing pattern of the neuron does not follow the input's periods and stochastic resonance cannot be useful. Real stochastic resonance, characterized by interspike interval histogram similar to Fig. 3b, is observed on a 60 mV range of V ref (0.18-0.24 V), which corresponds approximately to a factor five on the refractory period.

V. CONCLUSION

In this work, we have observed by circuit simulation that a neuromorphic neuron circuit could naturally exhibit stochastic resonance. The methodology consisted in applying a small sine input (which would trigger no spike in the neuron without noise), embedded in noise to the neuron. When noise is present, the neuron spikes, and the spiking response shows a spectral response at the input's frequency. This response has a maximum for a given range of noise: the stochastic resonance. The maximum resonance is not sharp. When at this maximum, if the refractory period is appropriate, the neuron spikes in phase with the input (sometimes missing a period). This means that it turned the input, a sine function embedded in noise, into a regular spiking pattern, which may be exploited by other neuromorphic circuits directly.

Exploiting this idea could allow neuromorphic circuits to work with weak and extremely noisy signals, for example coming from inexpensive sensors, and to develop new concepts and model of computation. Future work should focus on demonstrating functions associating several neurons with the stochastic resonance property.

Figure 1 .

 1 Figure 1. Neurons circuit used in this work (based on [3])

Figure 2 .

 2 Figure 2. For different noise levels, input voltage Vinput (black), small AC input without the noise (light blue), membrane current Imem (grey). Neurons spikes are materialized by the vertical blue lines on the time axis. (a) No input noise (b) 0.04 V²/kHz (c) 0.1 V²/kHz (d) 0.6 V²/kHz

Figure 3 .

 3 Figure 3. (a) FFT (b) Histogram of interspike intervals (both correspond to the case of Figure 2(c), input noise of 0.1 V²/kHz).

Figure 4 .

 4 Figure 4. Height of the spectral peak at 10 Hz in the FFT, as a function of noise level, for different refractory periods.

ACKNOWLEDGMENT

The authors would like to thank A. Bournel and P. Dollfus for helpful discussions, and C. Chassat for computer assistance.