École Sigle

Doctorale

Renée El

Melhem Bât

Pascal Blaise

R Gourdon

M Stéphane

ÉLECTROTECHNIQUE E E A Électronique

M Gérard Scorletti
email: gerard.scorletti@ec-lyon.fr

M Fabrice

Mme Emmanuelle
email: emmanuelle.canet@univ-lyon1.fr

Étage

M Luca

Jean-Yves Buffière
email: jean-yves.buffiere@insa-lyon.fr

M Philippe Boisse

Viviane Polsinelli
email: viviane.polsinelli@univ-lyon2.fr

Brigitte Dubois

J Y Toussaint

M Christian Montes

Transistors from Platinum Nano-island Matrices Produced via Atomic Layer Deposition

The introduction of the single electron transistor (SET) shook the semiconductor industry, with promises of unrivaled efficiency. However, the cost and complexity associated with achieving stable operation have heavily hindered their adoption. Having fallen out of the graces of industry, academic research has continued to push, demonstrating novel techniques for SET creation. At the core of this stability issue is a need to controllably build nanoislands smaller than 10nm. Among the methods available for this nanoisland formation, atomic layer deposition (ALD) sets itself apart as an industrially scalable, highly controllable process. The second barrier to entry is the creation of nanogap electrodes, used to inject current through these nanoislands, for which researchers have leaned heavily on non-scalable fabrication techniques such as electron beam lithography and focused ion beam. The shadow edge evaporation technique overcomes the complexity and scaling issues of nanogap fabrication, opening new possibilities.

In this work, ALD will be demonstrated as a superb technique for growing vast 3D arrays of sub 2nm platinum nanoparticles encapsulated in Al2O3. ALD provided a means of growing these nanoparticle matrices in a single process, under vacuum, and at low temperatures. Through shadow edge evaporation, UV lithography was then utilized to form nanogap electrodes with high lateral widths (100µm), with gaps demonstrated below 7nm. The combination of these techniques results in a high yield, low requirement fabrication process for building full SETs.

From the resulting transistors, thin lamellas were prepared using FIB and 3D models were reconstructed via TEM tomography for analysis. Electrical characterization was performed down to 77K, with modeling revealing Poole-Frenkel transport alongside possible cotunneling. Stable Coulomb blockades, the signature of SETs, were observed with regular periodicity and were identifiable up to 170K. Optimization of this process could yield high surface area SETs capable of stable operation at room temperature.

Thank you to my family back home and here in Lyon for always being my guiding light Don't stop fightin' and don't stop believin' You can make the world better For your kids before you leave it -

INTRODUCTION

The single electron transistor stands an elusively pivotal key for technological innovation, prevailing just beyond the grasp of industry. With the theory behind single electron transistors (SETs) dating back nearly 50 years to 1969, the first working demonstration in 1989 invigorated the research community. Based on Coulomb blockades in metal-insulator-metal structures, the central work of the primary paper from 1969, SETs are capable of operating as "perfect" transistors. With the transistor positioned as arguably one of the most important discoveries of the 20 th century, research has continued to develop new ways of fabricating these structures and advancing their performance. These advancements lie at the heart of nearly all modern technology, most notably marked by the debut of the automation and machine learning revolution of today. As the performance needs of these advanced applications has continued to push, the semiconductor industry has fought to provide an adequate response, astoundingly managing to keep Moore's law alive to this day. The inevitable end of the traditional CMOS transistor still creeps nearer day by day as research searches for ways to continue reducing their size all while maintaining control of their output, taming power losses, and managing heat generation. Novel solutions to this issue have intrigued the research community as it has searched for alternative means of addressing these issues. Back to the topic at hand, the SET, due to its unique operation, poses as an interesting solution to these control and power loss issues. The Coulomb blockade phenomenon at the heart of SETs grants the ability to finely control the current flow down to a single electron, thus the name of the device itself. This extreme amount of control presents a means of drastically improving computing performance, conceiving new logic capabilities, and even creating new forms of devices. However, this same Coulomb blockade also carries with it heavy requirements that have thus far kept SETs relegated to the laboratory. The ability to control single electrons requires a strong control over electrostatic conditions which are heavily influenced by their surroundings. Building single electron transistors that operate stably at room temperature requires nanofabrication techniques capable of reaching resolutions of a few nanometers. While numerous techniques have been demonstrated, the pursuit of industrially applicable methods is still open. Therefore, the work of this project has been centered on fabricating single electron transistors with scalable techniques. Through this manuscript, the full transistor fabrication and characterization process will be presented, focusing on each of the methods created and utilized throughout the duration of this project.

In order to have a good overview of single electron transistors, their strengths, and their overall raison d'être, it is important to first look at the semiconductor industry, and parallel works in the field of nanoelectronics. As such, the first chapter, presented herein, will first discuss commercial transistor trends, especially focused on computing needs, following recent developments and as of yet unsolved hurdles faced by the research and development community. Next, single electron transistors themselves will be presented, first outlining their operating principles before diving into some of the more exciting developments and

INTRODUCTION Page | 2
applications in this field. Next, we will shift a bit to discuss SETs and other novel nanoelectronics founded upon multi-island arrays, and methods for fabricating such arrays. This nanoparticle array portion will culminate in a presentation of the rich and unique history of atomic layer deposition followed by discussions of advancements of this industrially proven technique. Finally, a myriad of methods for fabricating nanogap electrodes will be shown. Of these presented techniques, the best suited method for integration in this project will be presented in full, discussing its conception and novel demonstrations.

Next, the development of several fabrication techniques will be presented with details on the processes and final results of each. These SET structures were fabricated using Pt nanoparticles embedded in an Al2O3 matrix acting as the active transistor layer. Several electrode device geometries were created and tested for injecting current through these nanoparticle films. The first development in the device creation stage was a shadow edge evaporation technique capable of flexibly forming nanogap electrodes around any patterning technique. This technique was invaluable as it allowed for the creation of size tunable nanogaps without the requirement of advanced equipment. Next, the fabrication of the Pt nanoparticle matrices was developed, leaning heavily on atomic layer deposition (ALD). As a well-studied self-limiting process, ALD lends itself as an industrially adopted method for controllably and reproducibly building thin films of a myriad of materials, monolayer by monolayer.

After the development of these techniques, two terminal devices in various geometries were fabricated and characterized in order to gain a better understanding of these new Pt island matrix layers. Transmission electron microscopy was performed on thin lamellas of key structures, prepared via focused ion beam liftout techniques. Two-terminal electrical measurements were performed, sending current through the Pt island matrices and measuring the response. These I-V responses were plotted and analyzed using transport model fitting, to determine the physical makeup of the films.

Finally, following a series of surprising results found during the two terminal characterization, full three terminal transistor structures were fabricated and TEM tomography was performed on a new thin lamella in order to create a 3D reconstruction of the full device. This advanced characterization technique allowed for a new level of analysis on the formed nanogap. Succeeding these new electron microscopy characterization results, three terminal electrical measurements were applied to the transistors. The resulting gating responses are presented for various Pt nanoparticle matrix configurations, and the full stack of fabrication techniques is analyzed for Coulomb blockade behavior.

I. Introduction

The semiconductor revolution marked a historic transition in our modern society. Computing has revolutionized the way we approach all facets of life, from automation to communication and leisure. This revolution continues to this day, seemingly unheeded, as the pioneering move to personal computing has given way to mobile computing and beyond. At the core of this has been continuous breakthroughs and novel approaches to the production and scaling of the transistors sitting at the heart of these devices. The most well-known term in the domain of semiconductors, Moore's law 1 , has been the driving beacon at the heart of the continuous and timely miniaturization of transistors from their original size down to a modern day 10nm size 2 .

Looking at a timeline of transistor scaling, paints a rosy picture, but there have been several hiccups along the way. The first modern transition came in 2006 when Intel and AMD were forced to abandon their pursuit of higher clock speeds and faster throughput. As they pushed and competed, active transistor counts became too high and two things occurred: power consumption skyrocketed, and heat production became astronomically high. Too high in fact for the packages containing them, thus leading to a major shift: the move to multi-core processors. Figure I.1 below, shows a compilation of CPU statistics up through 2009, compiled by Herb Sutter 3 . The stagnation of clock speeds, power usage and performance/clock cycle, are immediately visible, marking the packaging limits of processors at the time. The saving grace for Intel, and the CPU industry in general, was the shift to dual core processors around 2006. This shift allowed manufacturers to continue to increase the density of transistors, and increase performance, without needing to increase clock speeds. However, two more recent issues related to Moore's law have thrown up a roadblock, leading R&D in search for alternate solutions. As of 2014, the major semiconductor foundations have been unable to keep up with the constant scaling of transistors due to steep fabrication and operational constraints. This is especially highlighted by Intel's development pipeline demonstrated during their 10nm FINFET unveiling, shown in Figure I.2. While Moore's law is still very much alive and well, the time between transistor scaling landmarks is noticeably increasing. This is due to the extreme feature sizes currently required to fabricate high yield 10nm node transistors. At some stage, size-scaling limitations will begin to play a very large factor. 4 The second, as processors continue to pack in more cores and faster clock speeds while transistor sizes stagnate, energy restrictions are slowly reappearing. In their same presentation, shown in Figure I.3, Intel claims a 25% increase in power consumption vs. performance with the reduction from 14nm down to 10nm. Power consumption is proportional to transistor size, but without the ability to continue scaling, industry has, by necessity, needed to look for alternative methods for reducing energy consumption. Adding to this, the major societal shift away from the personal computer, to the portable computer has exacerbated the need for energy efficient transistors. The reduction in gate spacing, sought by Moore's law, drives down the maximum power draw, but also leads to an increased level of leakage current 5 . As the gate dielectric spacing is reduced, it loses its intended ability to fully block the movement of electrons. This leakage current has thus continuously increased, just as today's computing needs require reduced power loss. One proposed solution is to change the material used for the gate dielectric. The pursuance to high-k dielectric materials marks the drastic need of mitigating these leakage losses 6 . While these materials have the ability to reduce or even potentially eliminate the leakage current, they also bring with them several drawbacks. First, even after the time and resources have been spent on R&D, new manufacturing methods must be implemented. Second, many of the proposed materials are not cheap, and do not have pre-existing easily implemented mass production fabrication methods, necessitating a great deal of R&D. Another approach to reducing the amount of energy consumed and lost is to redesign the transistor for the modern age. Enter the single electron transistor.

Figure I.2 -Intel's presentation of their new 10nm transistor designs

II. Single Electron Transistors 1. A Brief History

Single electron transistors (SETs) were first introduced to the world, by chance, as we entered the last decade of the 20st century. The first such discovery came from a group out of MIT in 1989, sprouting from research on nano-structured transistors at low temperatures 7 . What they discovered surprised them, and started a growing movement in transistor research. By building a multi-gate structure, they were able to confine electrons within their silicon device, creating a controllable, 1D electron gas. This new device, at low temperature, exhibited reproducible oscillating conductance responses vs. an applied gate, a new phenomenon in the semiconductor field. Just shortly after this, Meirav, Kastner, and Wind, achieved more evident oscillations while building GaAs transistors 8 . Ultimately, these oscillations of the conductance were studied and were found to be the result of adding and removing electrons from the confined conductive region itself. Further study showed that this phenomenon was due to a Coulomb blockade being formed, allowing for precise control over the flow of electrons 9 . The concept of the Coulomb blockade, developed by Zeller and Giaever in 1969, and coined by Averin and Likharev, described metallic nanoparticle systems and the specific and unique behavior of electrons traversing these nanoparticles 10,11 . This Coulomb blockade concept was adapted in what would be come to known as the Orthodox Theory for SETs by Kulik and Shekther in 1975 12 and later improved by Beenakker in 1991 13 . The first single electron charging effects were reported in 1987 by Fulton and Dolan from Bell laboratories. This pioneering device was fabricated from aluminum, forming Coulomb blockading junctions off of a main electrode line as reshown below in To better understand this Coulomb blockade at the heart of the SET, we again turn to the pioneering works on SETs. Figure I.5 shows a diagram presented by Kastner in his original review of the SET phenomenon 7 . The figure shows a traditional Coulomb blockade forming structure, whereby a metallic island is separated from two metallic leads by dielectric spacers. As a voltage is applied between the leads, while the electric field is low enough to prevent direct tunneling from one lead to another, any carrier flow that occurs must occur through the sandwiched island. As an electron enters the island, it will grant its charge to the metallic island, bringing its net charge to 15 :

𝑄 𝑠𝑖𝑛𝑔𝑙𝑦 𝑐ℎ𝑎𝑟𝑔𝑒𝑑 𝑖𝑠𝑙𝑎𝑛𝑑 = -𝑒
This charged island will generate an electric field 𝐸 ∝ 1 (𝐼𝑠𝑙𝑎𝑛𝑑 𝑆𝑖𝑧𝑒) 2 As this local electric field acts to repel additional carriers, the amount of energy required to bring an additional carrier from a lead to the island can be explicitly calculated as

𝐸 𝑐 = 𝑒 2 2𝐶
where e is the charge of the carrier, and C is the capacitance of the island 7 . The capacitance of the island can further be defined as: 16 𝐶 = 𝐶 𝑇𝑢𝑛𝑛𝑒𝑙 + 𝐶 𝐺𝑎𝑡𝑒 This charging energy Ec lies at the core of the Coulomb blockade. Any carrier with an energy potential lower than this charging energy will not be able to traverse the charged island. The charge on the island must first be released, before another charge may enter. The higher this energy, the more capable the island is of blocking the flow of carriers.

At these scales, one major source of potential energy that must be avoided is thermal energy. As the temperature of the system is increased beyond absolute zero, energy is given to each of the carriers in the system following 𝐸 𝑡ℎ𝑒𝑟𝑚𝑎𝑙 = 𝑘 𝐵 𝑇 Thus, the temperature must be held below a point limited by

𝐸 𝑐 ≫ 𝐸 𝑡ℎ𝑒𝑟𝑚𝑎𝑙 And 𝑒 2 2𝐶 ≫ 𝑘 𝐵 𝑇
This underlying equation dictates one of the main focuses for SET fabrication. To build SETs operating at nominal temperatures, room temperature for example, the self-capacitance must be held small enough to compensate. If we choose to deal with spherical islands in a vacuum, this self-capacitance follows the wellknown equation

𝐶 = 4𝜋𝜀 0 𝑅
Where ε0 is the permittivity of free space and R is the radius of the island. From this relation, it is clear to see that the island size must be reduced in order to achieve higher operating temperatures. According to Likharev, the charging energy in fact should be held at 10 larger than the thermal contribution energy, requiring island sizes below 10nm 15 . This size restriction makes up one of three requirements for SET operation as dictated by the Orthodox Theory, and summarized by Likharev as follows 15 :

1. The energy of the electrons is continuous over the medium, thus satisfying 𝑒 2 2𝐶 ≫ 𝑘 𝐵 𝑇 2. The time of electron tunneling, τt through the dielectric barrier must be much smaller than the time for other transport. This defines a limitation on the dielectric barrier such that τt ~ 10 -15 s 3. The resistance barrier imposed by the dielectric must be high enough to block cotunneling events (simultaneous tunneling events that will be discussed below). This defines a limitation that the resistance must be higher than the quantum resistance R = 6.5kΩ

When these requirements are met, Coulomb blockade functionality may be maintained on an isolate island. If a bias is applied across the leads, an IV response such as the one seen in Figure I.6 appears. With Qe << e/2, at low voltages, the applied potential energy is unable to overcome the electrostatic repulsion of a charge on the island, and no current flows. As the voltage bias is increased sufficiently the blockade is overcome and the blockading electron on the island is evicted, instigating current flow. Likharev notes that in real world conditions, current may still exist at low biases as cotunneling events(discussed in the next section) overtake the Coulomb blockade resulting in weak, but measurable, current levels 15 . If a sufficient bias Ug is applied across this gate, the energy of the island will be reduced enough to expel and accept new electrons. More concretely, if the bias applied on the gate

𝑈 𝑔 = 𝑒 𝐶 𝑔𝑎𝑡𝑒
where Cgate is the capacitance between the island and the gate, then the external charge of the island Qe changes by e. This change in charge opens up the possibility for additional tunneling events to occur where either an extra electron may tunnel to the island, or electrons may tunnel off, thus propagating a current flow of one electron. As the gate bias Ug is increased or decreased just past the value 𝑒 𝐶 𝑔𝑎𝑡𝑒 , the external charge will increase, thus again repelling electron flow to the island. Likharev 15 Extending this gate bias variation further, we see that at discrete values of the gate voltage, the Coulomb blockade will be lifted, and charges will be allowed to move through the island. This can be seen in Figure I.8. At gate voltage values set at fractions of e/2, the external charge falls to zero and the Coulomb blockade is bypassed. This phenomenon leads to the oscillating electrode current vs. gate voltage that Kastner saw, known as Coulomb oscillations 7 . While these equations and explanations describe perfect Coulomb blockade and SET systems, they often cannot describe real world, imperfect, or multi-island devices. As novel SET systems have been developed, the literature has evolved to better describe them.

Modern Conduction Mechanism Explanations

Studying the conduction mechanisms in SET structures and nanoparticle arrays has been a hot topic of discussion, however the results of each study depend heavily on the configuration and materials involved. El-Atab et al. found that conduction through silicon nanoparticles embedded in a zinc-oxide matrix exhibited a Poole-Frenkel hole emission response 18 . In his thesis, Deshpande reported on conduction through Si nanowires, finding conduction to follow a Schottky model 19 . Several other works reported soliton, rather than single electron, conduction, as charge soliton waves moved and became blocked as uniform bodies within the matrix [20][21][22] . Another work, conducted on Au nanodots, showed a direct tunneling response as electrical biasing was applied 23 . Other works have focused on defining new models to better describe the state of the electrons as they travel through a matrix of nanoparticles. Of note, a work from Noda et al. conducted on gold nanoparticle arrays found that conduction shifted from Efros-Shklovskiitype variable-range hopping to the Middleton and Wingreen model as temperatures fell from 50 K to 10 K 24 . The Middleton Wingreen Model was created to explain electron transport through nanoparticles while also considering random charges existing on the particles in the film 25 , and has been well documented [26][27][28][29] .

From these developments across the field of single electronics, countless applications have been developed and demonstrated.

Applications

The most exciting applications of SETs stem from their vast reduction in power consumption and complete control over on/off current levels. The most obvious impact of such gains lies directly in the semiconductor industry, with promises of more tightly controlled transistor current levels and devices which last far longer due to a reduction in both the leakage current and current required to register an "on" state. This is most directly marked by IBM's previous insistent pursuance of such devices.

Kastner perhaps said it best in his review paper, "Few new technologies are likely to compete successfully with conventional silicon technology. However, arrays of devices with novel properties may turn out to be valuable" 7 . This statement has stood the test of time, perhaps better than Kastner would have liked when he made it.

Digital Systems

The principles and traits that make SETs so exciting for mainstream computing, namely their single electron nature, are also one of the main principles barring their direct entry to the processor world. Single Coulomb blockading islands simply cannot generate sufficient current for today's processors, as they are limited to single electron flow. A second detrimental outcome of this Coulomb blockaded operation is a limit in the switching speed of the transistor, which should be necessarily high for industrial computing. However, a few principle approaches may overcome or circumvent these issues.

Digital Circuit Components

The most straightforward implementation of SETs is to build them directly into existing transistor gates. Many of these applications were summarized by Mahapatra et al. in their simulations of SET devices 30 . Mahapatra 30 By placing a current blocking SET in series with a traditional transistor gate, the SET itself may be used to fully block the current flow through the circuit, thanks to its Coulomb blockading nature, while the traditional transistor maintains an industry standard voltage and current input/output. An example schematic and output of such a device can be seen in Figure I.10. Sahafi et al. performed simulations of novel SET digital circuits, also looking at the feasibility of one day integrating these devices into our mainstream devices 31 . Through their work, they successfully simulated functioning threshold gate transistors, buffer inverters, several latches and flip-flops, and NAND and NOR circuit elements.

Figure I.10 -Traditional MOSFET with included SET presented by

Alternatively, due to their ability to form oscillating current responses, some novel circuit elements have been proposed using SETs as a base. Devoret and Schoelkopf proposed taking advantage of SETs extreme sensitivity abilities to build amplifiers for quantum and other extremely low power signals. SETs provide a foundation capable of filtering out noise in extremely low signal level scenarios when paired with more traditional amplifying circuits 32 .

Memory Devices

One of the more promising areas in which SETs could still make an impact on traditional computing resides in memory devices. Back in 1999 Konstantin Likharev put together an excellent review paper, summarizing both the principles of SETs and their many applications, both aspirational and prospective 15 . The bulk of these were focused on memory devices as the many technological constraints mentioned previously could be avoided or sidestepped. Since 1999, several works have been presented, furthering the discussion on single electron memory devices.

One recent demonstration of such a device was presented by Azuma et al. [START_REF] Azuma | Nanoparticle single-electron transistor with metal-bridged top-gate and nanogap electrodes[END_REF] and are shown in Figure I.11. They used e-beam lithography to pattern electrodes, and chemisorbed colloidal gold particles, suspended in toluene, separated from the electrodes using decanedithiol spacers. These parallel islands exhibited Coulomb blockades and were used to form memory. Using several control gates, the memory was set and reset by applying large biases of +20V and -15V. The resulting outputs after setting were found to be reproducible and easily distinguishable as shown in the same figure. Azuma 33 In digital circuitry and especially in memory applications, the long-term stability and reproducibility of operation is critical. Due to the extreme sensitivity of SETs to gate fluctuations, parasitic electric charges wreak havoc on stable operation. A lot of the research presented herein has been focused on reducing these fluctuations, working towards achieving overall stability. Looking to new areas of applications such as sensing could circumvent or even take advantage of this extremely sensitive gating response.

Sensors

Perhaps the most interesting of modern proposals for SET applications lie in their ability to form ultrasensitive sensors. In a perfect SET, the level of current can be controlled down to the single electron via control over the bias applied to the gate. Slight fluctuations in the gate bias will either form or erode Coulomb blockades, thus modulating the current on or off. By functionalizing or tuning the gate material to be sensitive to a given impulse, sensors can be made to detect displacement [START_REF] Knobel | Nanometre-scale displacement sensing using a single electron transistor[END_REF] , ions and biomolecules [START_REF] Kudo | Highly sensitive ion detection using Si single-electron transistors[END_REF][START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF] , gasses [START_REF] Ray | First-principles study of MoS2, phosphorene and graphene based single electron transistor for gas sensing applications[END_REF] , and even electron spins [START_REF] Hanson | Spins in fewelectron quantum dots[END_REF] .

To build their ion and biomolecule sensors, Takashi Kudo and Anri Nakajima used e-beam lithography and etching to pattern a nanowire into 11 nanoislands in series within a 3μm gap as shown in Figure I. 12 [START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF] . This island structure allowed them to build SETs operating at room temperature. [START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF] Atop these islands, a Si3N4/SiO2 gate dielectric was deposited to isolate the channel and the devices. To build a functioning ion detector, they used a PDMS microfluidic mold to direct solutions with varying pH levels directly over their active dielectric covered islands. A back gate was used to modulate the Coulomb blockade and control the location of the oscillation peak. Figure I. 13 shows both the sketch of their device, along with their measurement curves for varying pH levels. The simple change to pH in the solution was enough to induce a varying bias to the gate dielectric through increased or decreased ionic charges, thus shifting the oscillation peak seen in this same figure. Kudo 35 They employed the same strategy to build more advanced biomolecule detectors, shown in Figure I.14 [START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF] . Kudo 36 Using the same SET structure from their previous work, they functionalized their gate dielectric surface by first formed an aminopropylsiloxane top surface and used this to react and attach biotin receptors to form their gate. When streptavidin was introduced to the gate electrodes, its binding with the biotin receptors was sufficient to change the surface energy of the gate, thus shifting the oscillation peak. They chose to perform their measurements at the half maximum value of their oscillation peaks as they found this region to yield the highest sensitivity. In the same figure from above, it is clear to see that the functionalization and subsequent reaction of the gate dielectric was sufficient to yield 150mV shift in the gate voltage level.

Figure I.14 -Biomolecule detector based on SETs presented by

Improvements

Many of the applications list previously, still must overcome the hurdle of overall current levels. For consumer processing, high levels of current are obviously necessary, but moving towards sensing, current levels must be high enough to be easily measurable without advanced equipment. One obvious approach to increasing the level of current is to simply place more islands in parallel. However, the addition of new islands brings with it the direct hurdle of modulating and forming Coulomb blockades on each additional island. However, multi-island SET devices seem to bring about positive benefits such as higher operating temperatures, easier stability in control, and reduced sensitivity to parasitic electric charges, and are still of vast interest to the research community 20,22,[START_REF] Kudo | Highly sensitive ion detection using Si single-electron transistors[END_REF][START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF][START_REF] Ohkura | Cotunneling current in Si single-electron transistor based on multiple islands[END_REF][START_REF] Kitade | Room-temperature operation of an exclusive-OR circuit using a highly doped Si single-electron transistor[END_REF][START_REF] Kano | Chemically assembled double-dot single-electron transistor analyzed by the orthodox model considering offset charge[END_REF][START_REF] Sato | Single electron transistor using a molecularly linked gold colloidal particle chain[END_REF] . In their devices, they determined that higher peak-to-valley ratios were found as islands were added, with the highest ratios found with 22 islands. The reported devices even worked at room temperature [START_REF] Kitade | Room-temperature operation of an exclusive-OR circuit using a highly doped Si single-electron transistor[END_REF] .

Multi-Island SETs

Kudo and Nakajima built SET sensors, as presented above, using islands patterned in series with up to 11 Si patterned islands. They found that by increasing the number of islands placed in series, it was easier to achieve room temperature operation and the sensitivity of their sensors increased [START_REF] Kudo | Highly sensitive ion detection using Si single-electron transistors[END_REF][START_REF] Kudo | Biomolecule detection based on Si single-electron transistors for highly sensitive integrated sensors on a single chip[END_REF] . 16. They performed electrical measurements and simulations on their results and found that the charging energy of the islands was increased as additional islands were added [START_REF] Kano | Chemically assembled double-dot single-electron transistor analyzed by the orthodox model considering offset charge[END_REF] .

CHAPTER 1 An Introduction to Single Electron Transistors and Fabrication Techniques

Page | 16 [START_REF] Kano | Chemically assembled double-dot single-electron transistor analyzed by the orthodox model considering offset charge[END_REF] Ohkura et al. also found benefits from multiplexing islands in SETs, concluding that placing multiple islands in series reduced the inelastic cotunneling, leading to more reliable device operation [START_REF] Ohkura | Cotunneling current in Si single-electron transistor based on multiple islands[END_REF] .

III. Nano-Island Applications and Fabrication Methods

Arrays of nanoislands have played a central role in many facets of nanotechnology today. Numerous methods for controllably fabricating and manipulating nanoparticles have been developed and perfected by the scientific community as nanotechnology has moved to the forefront of modern day science. To avoid becoming lost in discussion, I will focus this brief introduction first on the many prominent applications of nanoisland arrays in the field of electronics, before shifting to a presentation of the mainstay methods for obtaining these arrays.

The Importance of nanoisland arrays in Research and Industry

Focusing on just a few of the countless applications of nanoparticles in electronics, we have chosen to spotlight memories, optics, and photonics. Flash memory and storage has long stood as a pillar of computing, enabling faster storage speeds and higher durability. A general review of flash memory, its fabrication processes, and application can be found in a review paper by Bez et al. [START_REF] Bez | Introduction to flash memory[END_REF] . A basic schematic taken from that review can be seen in Figure I.17 Bez 43 In this structure, a floating gate is completely surrounded by dielectric barriers, forming a charged island. The control gate is used to set the charge level of this floating gate, and the source and drain are used to read out the charge level, with a neutral charge corresponding to a digital "1" and a charged island corresponding to a digital "0". From this example, it can easily been seen why nanoparticle arrays, embedded in dielectric films, are perfect candidates for flash memory structures. [START_REF] Mikhelashvili | Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance[END_REF] Mikhelashvili et al. demonstrated this principle wonderfully by building flash memory cells from dielectric embedded Pt nanoparticles [START_REF] Mikhelashvili | Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance[END_REF] . A summary of their structure and results can be seen in Figure I. 18. In their devices, Pt nanoislands were formed using thin film dewetting, and were encapsulated in a matrix of HfO2 deposited by ALD. [START_REF] Liu | Nonvolatile memory capacitors based on Al2O3 tunneling and HfO2 blocking layers with charge storage in atomic-layer-deposited Pt nanocrystals[END_REF] . They conclude that encapsulated Pt nano-island arrays are well suited for high-density memory applications, and that ALD is a great technique for forming these structures.

Figure I.18 -Pt nanoparticle memory cells fabricated and demonstrated by Mikhelashvili

Moving from memory, a very similar but much more novel innovation seen in nanotechnology research is the memristors. Memristors were first introduced to the world in 1971 as the 4 th , missing 2-terminal device [START_REF] Chua | Memristor -The Missing Circuit Element[END_REF] . Leon Chua postulated that of the basic electrical componentsresistors, capacitors, and inductors there lacked a possible device forming a relationship between the flux-linkage and the charge. The basic structure of a memristors relies on an instable oxide layer that may be reformed. Under high voltage stress, migration of ions, traps, or even metal particles can occur, changing the resistivity. A great review presented by Hu et al. details many fabrication methods and applications of this novel structure [START_REF] Hu | Review of Nanostructured Resistive Switching Memristor and Its Applications[END_REF] . Nanoparticle arrays also have a strong foothold over the fields of optical sensing, optical absorption, plasmonics, and photonic emission. This is due to the quantum confining nature of metals and semiconductors when reduced to the nanoscale. Quantum dots present perhaps the most pervasive example of nanoparticles in optics and photonics, exhibiting brilliant properties both in emission and absorption [START_REF] Alivisatos | Semiconductor Clusters, Nanocrystals, and Quantum Dots[END_REF] . Likewise, nanoparticles tuned for optical absorption or specific plasmonics resonance are proving to be strong contenders for solar cell enhancement technologies [START_REF] Elkhidir Suliman | Preparation of ZnO nanoparticles and nanosheets and their application to dye-sensitized solar cells[END_REF][START_REF] Atwater | Plasmonics for improved photovoltaic devices[END_REF] . Perhaps the most exciting of these solar cell technologies is perovskites as they present moderately high conversion rates paired with extraordinarily low fabrication needs and costs [START_REF] Burschka | Sequential deposition as a route to high-performance perovskite-sensitized solar cells[END_REF] . Nanoparticles could also revolutionize the way we approach optical data transfer and IR sensing as ZnO research becomes more advanced and fabrication methods become more accessible [START_REF] Hamza | Tunable mid IR plasmon in GZO nanocrystals[END_REF] .

Behind each of these exciting and novel nanoparticle applications lies an equally complex and developed fabrication process that must also be discussed and presented.

Methods for Obtaining Nanoislands Thin Film Dewetting

Perhaps one of the simplest methods for fabricating metallic nanoparticles is through metallic dewetting. By merely depositing a thin film of metal on a substrate and subjecting it to annealing at high temperatures, metallic nanoparticles will be formed as the metal film begins to crack and reform [START_REF] Hanief | Solid-state dewetting of continuous thin platinum coatings[END_REF] . Looking into the literature, two great examples highlight the ability to form the very metallic nanoparticles we seek, at sizes below 10nm [START_REF] Prakash | Phenomenological understanding of dewetting and embedding of noble metal nanoparticles in thin films induced by ion irradiation[END_REF][START_REF] Strobel | Sub-10 nm structures on silicon by thermal dewetting of platinum[END_REF] . In a paper by Strobel et al. the process of dewetting Pt thin films was studied at varying temperatures, and the resulting island structures were presented [START_REF] Strobel | Sub-10 nm structures on silicon by thermal dewetting of platinum[END_REF] Due to the simplicity of this technique, and having all of the required equipment readily at hand, we chose to pursue our own development of this technique in our pursuit of forming SET islands.

Chemical Synthesis

One of the principle methods for controllably fabricating nanoparticles is through colloidal synthesis techniques. Chemical techniques have proven themselves able to handle countless materials, shapes, and even sizes. A great deal of these works have been summarized in a great review from Finney and Finke Rioux 67 The main drawback of colloidal synthesis techniques is the throughput provided. These colloidal fabrication processes rely on the mixing of precise precursors at a driving reaction temperature. At these reaction temperatures, nanoparticle seeds begin to grow, ultimately culminating in Ostwald Ripening, whereby the colloids begin to aggregate and monodispersion is lost. These reactions must be strictly controlled to maintain uniform growth of seeds, but must also be quenched with quick and precise timing in order to stop growth and prevent aggregation. This process, while easy to reproduce in a lab, is difficult to bring to industrial scales. Great strides have been made to scale this process, and one day breakthroughs may unlock industrial possibilities [START_REF] Zhang | Scaling up the production of colloidal nanocrystals: Should we increase or decrease the reaction volume?[END_REF] .

Figure I.22 -Chemical growth of Pt nanoparticles in controlled shapes by

Pulsed Laser Deposition

One of the most precise physical vapor deposition techniques, pulsed laser deposition (PLD), has many parallels to atomic layer deposition, our preferred technique that will be discussed further below. PLD relies on high-powered laser ablation of a target material under high vacuum. The plasma formed by the target ablation carries nanoparticles with it, which will deposit on a substrate. By calibrating the laser power, pulse duration, target distance, and number of pulses, nanoparticles and thin films of finely controllable size can be fabricated [START_REF] Sun | Growth of aligned ZnO nanorod arrays by catalyst-free pulsed laser deposition methods[END_REF][START_REF] Craciun | Characteristics of high quality ZnO thin films deposited by pulsed laser deposition[END_REF] .

The PLD technique has been demonstrated and properly studied as a proper means of fabricating Pt nanoparticles [START_REF] Dolbec | Growth dynamics of pulsed laser deposited Pt nanoparticles on highly oriented pyrolitic graphite substrates[END_REF] . However, much like colloidal synthesis techniques, PLD faces a very steep hill towards the path to industrial scaling. Relying on very high-powered lasers, very high-level vacuum chambers, and very small plasma cones, PLD's finesse largely loses out to time and expense beyond the scale of research.

Other Techniques

More generic evaporative physical vapor deposition has also been demonstrated as a sound technique for fabricating nanoparticles [START_REF] Moreau | PVD Synthesis and Transfer into Water-Based Solutions of Functionalized Gold Nanoparticles[END_REF][START_REF] Yumoto | In situ synthesis of titanium-aluminides in coating with supersonic free-jet PVD using Ti and Al nanoparticles[END_REF] . Verelli et al. demonstrated methods for the fabrication of metallic nanoparticles at room temperature [START_REF] Verrelli | Nickel nanoparticle deposition at room temperature for memory applications[END_REF] .

Masked deposition has also been shown to be a strong contender for potential nanoparticle fabrication. Larger, easier to fabricate, microstructures or particles can be produced in bulk, and deposited onto a substrate using spin-coating, Langmuir Trough, or any other traditional method. After, etching can be performed through this mask, resulting in nanostructured surfaces. Two such examples are shown in Figure I.23 [START_REF] Wang | Silicon nanotips formed by self-assembled Au nanoparticle mask[END_REF][START_REF] Glass | Block copolymer micelle nanolithography[END_REF] . [START_REF] Wang | Silicon nanotips formed by self-assembled Au nanoparticle mask[END_REF] and B) Au nanoparticles by Glass 76 Perhaps the most interesting process however, is atomic layer deposition due to ALD's heavy adoption in industrial fabrication processes. Heavily mirroring many of the same working principles as the methods above, ALD has been a heavy player in the field of microelectronics fabrication. Below, a section has been dedicated to ALD, detailing its rich and unique history, as well as some state of the art works being developed today.

Figure I.23 -Nanoparticles and structures fabricating via etching using nanoparticles as an etching mask A) Si nanostructures by Wang

IV. Atomic Layer Deposition

Background

At the heart of our work, lies a groundbreaking innovation with a hazy history. A more detailed description of the ALD process will be presented along with its intended usage in the second chapter on fabrication. In brief, modern ALD's comprise a heated vacuum chamber where precursors may be injected and evacuated. These precursors are introduced one at a time into the chamber in pulses, whereby heat or plasma energy is used to trigger a self-limiting reaction that deposits desired molecules on the all exposed surfaces within the chamber. This method is most often used to deposit thin films in monolayer by monolayer growth. Unlike most modern day technological advancements, the story of atomic layer deposition owes itself to two unique beginnings. The method of atomic layer deposition was independently developed first in the Soviet Union, but perhaps more influentially, in Finland as well several years later. The history of these two techniques have been well reviewed in the works of Puurunen and Malygin [START_REF] Puurunen | A short history of atomic layer deposition: Tuomo Suntola's atomic layer epitaxy[END_REF][START_REF] Malygin | Aleskovskii's 'Framework' Hypothesis to the Method of Molecular Layering/Atomic Layer Deposition[END_REF] . For the sake of the reader, I will briefly cover the histories of each of these developments, but will suggest further reading into these provided sources if there is any desire for a deeper understanding of the material.

Work began on the topic of solid material deposition through chemical phase in 1940 when Valentin Borisovich Aleskovskii laid out the original hypothesis of such a method [START_REF] Malygin | Aleskovskii's 'Framework' Hypothesis to the Method of Molecular Layering/Atomic Layer Deposition[END_REF] . He continued this work with several students, culminating in the thesis defense of one of his students, Stanislav Ivanovich Kol'tsov in 1971. In their work, they laid out the theory and methods they had developed for a technique they called "Molecular Layering" (ML). Their first experimental works on this topic involved studying the surface interactions of carbon tetrachloride and silica gels. Through the early 1970's, efforts were focused heavily on further developing and better understanding this technique. Thin films of silicon oxide as well as titanium oxide were grown through their ML reactions and the condensation of these materials during reactions was studied using ellipsometry and IR spectroscopy. Through their developments, further material depositions were studied, all relying on the same vapor phase deposition using chlorides and oxychlorides of the desired thin films. Advancing on these developments, Vladimir Smirnov deposited and studied thin films of TiO2 and alternating thin films of titanium oxide and phosphorous oxide. Through studies of the catalytic activity during growth, he determined that monolayers of material had been deposited. Unfortunately for their own credit, and perhaps unfortunately for the rest of the scientific community, the USSR remained quite closed during this period, and little research was shared with the rest of the research community.

Alongside these developments, and in fact coming some years after Aleskovskii and Kol'tsov's works, Tuomo Suntola was hard at work in Finland developing methods for fabricating electroluminescent displays [START_REF] Puurunen | A short history of atomic layer deposition: Tuomo Suntola's atomic layer epitaxy[END_REF] . In 1974, while working for Instrumentarium in Finland, Suntola began postulating methods for successfully fabricated thin-film electroluminescent displays. He saw that flat-panels would be the future of display technologies, but the working principles of electroluminescent displays needed better thin film uniformity than was attainable at the time. Through Puurunen's interviews of Suntola, his original thoughts that lead to the development of what he called Atomic Layer Epitaxy (ALE) were as follows "Monoatomic layers may be obtained if the complementary elements make a stronger bond with each other than they do with their own kind of atoms". In this case, his complementary elements, Zn and S doped with Mn, were prepared and supplied for reaction in a vapor phase, just as Aleskovskii et al. had done. A homemade ALD (or ALE as he referred to it) was built, and the precursors were introduced and reactions allowed to occur, inside of a vacuum chamber. He performed observations both visually and later via XRD, and determined, just as the Soviets had before him, that this method indeed resulted in very high quality thin films. These high quality films proved to have excellent properties, exhibiting optical and electrical properties far better than the other thin film display panels they were able to produce. Patents were quickly filed and granted, protecting this new process for thin film deposition. From these promising results, they then switched to compound precursors, and developed methods for depositing aluminum and titanium oxide as well. He presented his works in San Diego in the spring of 1980, thus introducing the world to this new, brilliant technique; unknowingly stealing the thunder from the likewise brilliant Soviet researchers who preceded him. The majority of the developments to follow were conducted under the supervision of Suntola as he followed his patents and invention. He additional worked on applications of his ALE for photovoltaic thin films, depositing CdTe with unfortunately poor results, before eventually moving to semiconductors.

State of the Art

Since the Suntola's contributions, countless developments and improvements have been made on ALD. Many of these works have been focused on the fabrication of SETs, the very same structures at the heart of this thesis, precisely because of the high level of control and quality afforded by ALD deposition [START_REF] Karbasian | Single electron transistors with hydrogen treatment of ALD SiO2 in nanoscale metal-insulator-metal tunnel junctions[END_REF][START_REF] Luo | Coupling graphene nanomechanical motion to a single-electron transistor[END_REF][START_REF] Karbasian | Single electron transistors with hydrogen treatment of ALD SiO2 in nanoscale metal-insulator-metal tunnel junctions[END_REF][START_REF] Karbasian | Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition[END_REF] .

Two additional noteworthy reviews have been written by Steven George and Johnson et al. focused on covering the fundamentals as well as more modern research applications [START_REF] George | Atomic Layer Deposition: An Overview[END_REF][START_REF] Johnson | A brief review of atomic layer deposition: From fundamentals to applications[END_REF] . These works do a great deal to lay out the core strengths of ALD, and the myriad of industrial applications unlocked by the finesse of this atomic technique.

Following the display innovations of Suntola, it seems only fitting that ALD would be found employed in the study and fabrication of thin films for modern displays [START_REF] Levy | Stable ZnO thin film transistors by fast open air atomic layer deposition[END_REF] . Likewise, these pure, highly uniform thin films are excellent for the fields of power electronics [START_REF] Barik | Ultralow-Power Electronic Trapping of Nanoparticles with Sub-10 nm Gold Nanogap Electrodes[END_REF] and solar cell coatings and active layers [START_REF] Poodt | High-speed spatial atomic-layer deposition of aluminum oxide layers for solar cell passivation[END_REF][START_REF] Werner | Very low surface recombination velocities on p -and n -type c-Si by ultrafast spatial atomic layer deposition of aluminum oxide[END_REF][START_REF] Barbos | Characterization of Al2O3 Thin Films Prepared by Thermal ALD[END_REF] . There have also been great strides taken to improve the technique itself through both deeper studies of known materials and deposition of new materials [START_REF] Aaltonen | Reaction Mechanism Studies on Atomic Layer Deposition of Ruthenium and Platinum[END_REF][START_REF] Goldstein | Enhancing the nucleation of palladium atomic layer deposition on Al2 O 3 using trimethylaluminum to prevent surface poisoning by reaction products[END_REF][START_REF] Mackus | Roomtemperature atomic layer deposition of platinum[END_REF] , but perhaps the most exciting for industrial applications are the developments in the field of Spatial ALD [START_REF] Levy | Stable ZnO thin film transistors by fast open air atomic layer deposition[END_REF][START_REF] Werner | Very low surface recombination velocities on p -and n -type c-Si by ultrafast spatial atomic layer deposition of aluminum oxide[END_REF][START_REF] Ellinger | Selective area spatial atomic layer deposition of ZnO, Al2O 3, and aluminum-doped ZnO using poly(vinyl pyrrolidone)[END_REF][START_REF] Rand | Solar Cells Utilizing Small Molecular Weight Organic Semiconductors[END_REF] The traditional precursor pulses and reaction chamber are replaced by a spatial, planar reaction system. A substrate is placed on a moving platform, which is then moved back and forth, underneath precursor gas outlets. These outlets are separated by inert gas exhaust ports to control and limit the reaction times. The beauty of spatial methods is that the time for each reaction cycle can be drastically reduced as the spatial orientation removes the need for purge steps. The removal of this purging step also removes the need for vacuum chambers, allowing ALD deposition to be performed at ambient pressures. Several wafers can also be loaded on the stage side-by-side, allowing for several samples to be fabricated at once. Poodt et al. have since developed this technique to reach deposition rates of up to 3600nm/h, moving to eliminate one of the largest hurdles for industrial adoption of this technique [START_REF] Johnson | A brief review of atomic layer deposition: From fundamentals to applications[END_REF] . [START_REF] Cui | Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals[END_REF] Coming closer to our own developments, often sharing many of the same fabrication goals, ALD has been proven as a great tool for the fabrication of memory structures 18,[START_REF] Cui | Mass Production of Nanogap Electrodes toward Robust Resistive Random Access Memory[END_REF] . These structures very often employ the use of ALD grown nanoparticles as charging islands [START_REF] Liu | Nonvolatile memory capacitors based on Al2O3 tunneling and HfO2 blocking layers with charge storage in atomic-layer-deposited Pt nanocrystals[END_REF][START_REF] Cui | Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals[END_REF][START_REF] Novak | Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications[END_REF] . These nanoparticle memory devices rely on islands embedded in dielectric matrices, used for building capacitances and holding charges. This application field approaches the same needs of our own quite closely. Looking at two recent works from China, groups have been studying ALD as a method for directly growing and encapsulating Pt nanoparticles in a one shot process [START_REF] Liu | Nonvolatile memory capacitors based on Al2O3 tunneling and HfO2 blocking layers with charge storage in atomic-layer-deposited Pt nanocrystals[END_REF][START_REF] Cui | Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals[END_REF] . The resulting structure from these papers can be seen in

Platinum Island Growth via Atomic Layer Deposition

Moving on to the topic of ALD grown Pt, many works have been performed to better understand the deposition methods for this particular material through this method [START_REF] Aaltonen | Atomic layer deposition of platinum thin films[END_REF][START_REF] Puurunen | Island growth as a growth mode in atomic layer deposition: A phenomenological model[END_REF][100][101][102][103][104] . These works demonstrated the growth metrics of Pt using MeCpPtMe3 and O2 precursors. Using these precursors, we find an interesting phenomenon. During pulse cycles of platinum precursors, we do not obtain the standard ALD thin film monolayer growth, but instead find a nucleation delay that leads to island formation. In their study on the growth mechanics, Shrestha et al. determined this growth mechanism to be Volmer-Weber island formation that eventually forms thin films after sufficient surface covering 103 .

Of particular interest for us, were the works of Baker, Liu, and Novak [START_REF] Liu | Nonvolatile memory capacitors based on Al2O3 tunneling and HfO2 blocking layers with charge storage in atomic-layer-deposited Pt nanocrystals[END_REF][START_REF] Novak | Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications[END_REF]100 . Each of these teams performed in depth studies on the nucleation delay of Pt via ALD, tuning their setups and processes for island formation. Liu et al. focused on forming islands for memory devices, as mentioned above. Baker turned to XPS and XRR to more concretely study the growth mechanics and plot the nucleation delay, and a few images of their resulting TEM, XPS, and XRR analyses can be seen in Figure I.26 100 . A very clear nucleation delay can be seen, with clear evidence of island formation. Novak et al. took this research one step further, really studying how the ALD process itself affected the resulting islands. They performed the same growth vs. cycle studies and while their unique parameters resulted in unique growth metrics, they saw the same nucleation delay [START_REF] Novak | Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications[END_REF] . However, they also observed that it was possible to modulate not only the size of the particles, but also the density. They fixed their number of ALD cycles to 30, and by changing the exposure time of for precursor reactions, they were able to observe an increase in both island size and distribution as a function of increased exposure, shown in In our own pursuit to build encapsulated metallic nanoparticles to act as Coulomb blockades, we could find no better candidate than ALD. The use of ALD would allow us to capitalize on what many of the above groups were able to do: grow well dispersed and size controlled Pt islands below 5nm, and embed them in a high quality Al2O3 dielectric matrix, all in one process without needing to break vacuum. This would result, we hoped, in islands and alumina layers of the highest purity.

V. Nanogap Electrodes

Alongside these incredibly diverse and flexible methods for nanoisland fabrication, researchers required means of contacting and probing these nanoparticles.

Electron Beam Lithography

Perhaps the most standard technique used today for creating micrometric electrodes with nanometric gaps is electron beam lithography 105 . This technique has seen vast improvements over the years, drastically increasing its resolution limits, even beyond those originally thought to exist 106 . E-beam lithography has been demonstrated creating patterns down to 1nm with extreme care and preparation 107 . On the other hand, extreme resolution pattern achievements may not always translate to full electrode fabrication and gap formation as high control over beam exposure does not ensure control over negative space exposure. However, great strides have been made in nanogap electrode formation as well, with demonstrations of electrodes below 10nm 108 However, e-beam lithography still faces a bit of an uphill battle concerning industrial adoption. At these extreme resolutions, reproducibility becomes an issue that is still under development. This can be seen directly in the previous figure, as one of the electrode lines failed to resolve at these extreme resolutions. Additionally, e-beam lithography in its current form is still a very slow process as it relies on direct write methods for electrode formation. Each portion of the patterned electrode must be scanned directly with a dosing time dictated by the chosen resist. In the case of Fischbein's work, while the results were incredibly impressive, they required two exposure steps, thus even further increasing the time needed for electrode patterning. Many researchers mitigate these long write times by adding in a UV lithography step to write larger patterns, such as contact pads and the electrode lines to connect them. This can be seen directly in the inset of Figure I.28 where Fischbein has patterned larger electrode arms and contact pads through a secondary technique.

Other techniques

Several other techniques have been developed in efforts to simplify the process of nanogap development and will be presented below. A strong evaluation of many of these techniques and more can be found in a review by Li et al from Advanced Materials 110 . In nearly the opposite manner, nanogap electrodes can be fabricated from larger spaced electrodes through electrodeposition. Figure I.33 shows images from an article by Morpurgo et al. showing the stages of electrodeposition on gold electrodes 115 . The initial electrodes seen in 'image a' had a spacing of nearly 100nm. These electrodes were submerged in a solution of gold leaflets. By applying a bias over the electrodes, with a free-floating gold wire acting as a second contact, gold particles could be attracted and deposited on the electrodes. This process was monitored by reading out a constantly measured resistance and could be stopped or even reversed as necessary. The final result can be seen in image c showing a 20nm gap. The mechanically controllable break junction technique also presents a novel way to form gaps, with Reed et al. demonstrating gaps even below 1nm 116 . Using this technique, which was reported in their article and is reshown in Figure I.34, they were able to fabricate electrodes with a spacing of ~8Å. They did this by building a gold wire and coating them in self-assembled monolayers. Next, these wires were mechanically pulled to the point of fracture whereby the monolayers coated the broken tips. These tips were then allowed to move back together, keeping a separation dictated by the length of the monolayer ligands. Electromigration, electrodeposition, and mechanically controlled break junctions all rely on chemical techniques that may encounter scaling issues when moving to industrial scales. Mitigating many of the industrial barriers presented for the methods above, shadow edge evaporation opens up the ability to fabricate sub10nm gaps using traditional, industrial patterning techniques.

Shadow Edge Evaporation Basic Principle

The shadow edge evaporation technique, also known as shadow edge lithography or simply shadow evaporation, relies on a simple geometric configuration of the sample to form a "shadowed" area on a substrate. This technique, perhaps easier shown than described, was well illustrated by Bai et al. and has been reshown below in Figure I.35 117 . A substrate with a pre-patterned object of a given height is placed in an evaporation chamber with a fixed angle with respect to the evaporation point source. This pre-patterned object will shadow a portion of the substrate from the evaporation of material in a pattern predictable from the geometry of the components.

Background

This technique has long been employed, with the first reported use of it coming from Gerald Dolan at Bell Labs in 1977 118 . In this first demonstration of the technique, Dolan used a complex series of resist layering, aluminum deposition, and etching, to form a shadowing pattern held up by a support. This was used as the shadow edge to form small gaps between electrodes. He used this technique to build superconducting microbridges from indium and lead. He later used this technique again along with Fulton in 1987 to study single electron effects in small aluminum nanogap junctions 14 .

Our uses

The beauty of the shadow edge evaporation technique is its adaptability to nearly any combination of patterning and deposition method. Standard methods for forming electrodes in research applications rely on a combination of lithography for patterning and evaporation for metal deposition. The two most commonly seen being UV lithography or e-beam lithography paired with thermal or e-beam evaporation. This technique can easily be adapted to laser lithography, nano-imprint lithography, or even direct hard masks for patterning. With some work, it should be possible to adapt it to FIB or sputtering as well. Gaps have been well demonstrated in the sub-lithographic range [START_REF] Strobel | Sub-10 nm structures on silicon by thermal dewetting of platinum[END_REF]121,122 , with gaps presented down to 4nm 119 .

In our work, we intend to pair traditional UV lithography with e-beam evaporation to form nanogaps via shadow edge evaporation below the resolution limits of most e-beam lithography devices. The use of these techniques in synergy will allow us to take advantage of several benefits. The first, UV lithography has long been a steeple of microelectronic design. As such, it has been incredibly well defined, and should yield resolutions down to several micrometers. Next, as it is a one-shot patterning process, we have the ability to design numerous custom mask designs which will allow us to fabricate a large number and a wide range configurations in a single, quick, optimized process. We are thus empowered to be able to pattern truly nanometric electrodes through traditional micrometric technologies. As a future outlook, while not only being much more time efficient, UV lithography carries with it far lower associated costs and necessary amounts of training to use versus e-beam lithography. This opens up further possibilities for potential paths towards industrialization. Likewise, the employment of traditional e-beam evaporation techniques allows access to a wide range of material options, as well as fast and controlled deposition rates. The widths of fabricated electrodes are only limited by the size of the mask and equipment, whereby nanogaps with micrometric widths can be easily achieved. These very large length to width ratios provided a larger surface area that can vastly improve performance of devices such as sensors, which rely on large sensing areas. This total combination resulted in us being able to fabricate fully realized and etched samples containing more than 100 devices in a matter of 10-12 hours comprising fully manual processes and waiting times for vacuum levels.

VI. Presentation of Thesis Contents

Herein, our developments on single electron transistor fabrication techniques and characterization methods, conducted over the past three years, will be presented. Several techniques and ambitious applications of novel SET approaches have been briefly summarized and presented. In keeping with these findings alongside the equipment at hand in our own facilities, we chose to base our developments around UV lithography, e-beam evaporation, and ALD.

We used UV lithography in conjunction with shadow edge evaporation to form nanogap electrodes. We then looked to pair these nanogap electrodes with Pt nanoparticles, comparing those formed via thin film dewetting and directly by ALD. Finally, we looked to fully encapsulate our islands in a dielectric matrix of Al2O3, building the tunneling junctions that would form our Coulomb blockades. A great deal of work had been performed to calibrate our Al2O3 process by PhD theses lead by Khalil El Hajjam and Corina Barbos, looking closely at the optimal growth parameters for forming pure, high quality films, with strong dielectric properties 17,[START_REF] Barbos | Characterization of Al2O3 Thin Films Prepared by Thermal ALD[END_REF] .

To begin our research project, much work needed to be done to optimize our UV lithography and electrode deposition for shadow edge lithography. While the pairing of these techniques is perhaps the most widely spread technique for forming micrometric electrodes, it is rare that care is taken into controlling the surface roughness and edge uniformity of said electrodes. This was the first area we investigated, performing optimization steps to develop smooth and uniform electrodes. Next, the shadow edge evaporation technique needed to be developed for our own evaporation setup and electrode materials needed to be chosen. While evaporation was well optimized and controlled in our own laboratory, these steps needed to be reanalyzed for their purposes in forming nanogaps. Finally, we needed to investigate and choose a proper method for building our Pt nanoparticles. With the ability to quickly fabricate thin films of Pt, prototyping Pt island devices via dewetting was an obvious first approach. With many examples to view showing successful Pt island formation, thin film dewetting was the first technique we would approach. To build a comparative study, and having a proper plasma equipped ALD at our disposal, we also chose to investigate plasma enhanced ALD for growing our Pt islands. Having a well-studied nucleation delay, resulting in Pt nanoislands, ALD looked to be a promising solution, allowing us to build and encapsulate Pt islands in one shot. Our final steps would be to fabricate full devices from these techniques, characterizing both their structural integrity and electrical performance with the aim of achieving Coulomb blockades.

Our unique take on the SET was the following: 1) single electron transistors perform best with arrays of uniform islands, 2) ALD and dewetting present optimal methods for obtaining uniform islands, and 3) the shadow edge evaporation technique allows for the simple employment of micrometric electrodes with nanometer gaps using UV lithography. Thus, we would capitalize on these building blocks, and fabricate novel SET structures, placing islands both in series, through a nanometric gap, and in parallel, through electrodes several microns in lateral width. What's more, thanks to the strongly conformal growth afforded by ALD, we could build individually separated layers of islands. These processes would culminate in a fabrication process capable of generating single electron transistor structures with customizable 3D Pt nanoisland arrays.

CHAPTER 2

Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

I. Introduction

Since the advent of modern nanofabrication techniques, industrial fabrication methods have struggled to keep up with the demand of the scientific community. In traditional electronics research, scientists could turn to standard UV lithography and other various patterning techniques to fabricate electrode structures with resolutions down to several hundred nanometers. However, with the introduction of novel nanoparticle and thin film characterization, the foundations of modern electronic research, researchers now rely on having access to methods by which to probe the objects they have produced. To do this, devices with nanometric distances must be fabricated, a not insignificant task without incurring burdensomely high equipment costs. Advanced UV techniques have been developed and employed in industrial settings with incredibly precise writing resolutions, however due to the costs and space required by such machines, most institutions are blocked right from the gate. A key interest for research teams is finding alternative solutions to reduce these exorbitant costs and creating novel methods for rapidly prototyping testing platforms.

UV lithography, chosen in this work due to its prevalence both in research and in industry, is arguably the backbone of transistor fabrication and stands a proven technique for complex substrate patterning. When paired with another standard, e-beam evaporation, researchers are capable of rapidly creating complex and reproducible metal patterns from a myriad of material choices, on a plethora of substrates. However, standard UV lithography suffers from a resolution limit nearing one or two micrometers, typically eliminating its consideration for nanofabrication from the outset; enter the shadow edge evaporation technique. This chapter will focus on the research and development of the fabrication building blocks that would later be integrated to form full SET devices. After a brief overview of shadow edge evaporation, the central component of the formation of these transistors, each of the following developments will be discussed: UV lithography, E-beam evaporation, and ALD growth of alumina dielectric and Pt nanoislands.

II. Nanogap Electrode Fabrication 1. Introduction to Shadow Edge Evaporation

First pioneered by Dolan in 1977 1 , shadow edge evaporation has become a steeple in scientific communities looking for ways to create nanoelectronics [2][3][4][5][6][7][8][9] . By taking advantage of simple geometries that are formed during the evaporation process, nanogaps below 10nm have been demonstrated, with the theoretical limit of these gaps only being limited by the dispersion and grain size of the evaporated material 8 . As the nanogap is formed during the evaporation step itself, any form of patterning and any anisotropic evaporation technique can be used with any available material. In this section, I will be discussing the fabrication of metallic source/drain electrodes by means of shadow edge evaporation via a combination of UV lithography patterning and electron beam evaporation. The shadow edge evaporation technique utilizes two evaporation stages; an illustration of this technique can be seen in Figure II.1 for clarification.

In the first stage of evaporation, a primary layer is deposited on the substrate. This first layer can be patterned by any means available, with the only stipulation being that a portion of the substrate should be left bare for the second layer. In this work, this first layer was patterned as a straight horizontal bar. The length of this bar was only limited by the uniformity resulting from the fabrication platform, while the height was critical to control as it dictated the length of the gap. The second stage of evaporation is performed at an offset angle from the first. The angle applied during this evaporation in conjunction with the first deposited layer forms a small shadowed area of the sample. In basic terms, the length of this shadow, and thus the length of the gap, is dictated by the trigonometric function:

𝐿𝑒𝑛𝑔𝑡h 𝑔𝑎𝑝 = 𝐻𝑒𝑖𝑔h𝑡 1𝑠𝑡 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑑𝑒 * Tan 𝜃 Using this shadowing along with a very specific pattern, allows for the formation of two clearly and precisely formed electrodes, with fine-tuned gaps separating them. Following the trigonometry, the length of the gap can be tuned by either modulating the angle of deposition, the height of the first electrode, or a combination of the two. This technique was employed for device formation for building the source and drain electrodes. In the following sections, the UV lithography and E-beam evaporation process optimization steps will be outlined, culminating in a fully developed process for creating nanogap electrodes. Further details of the specific steps of UV lithography and E-beam evaporation can be find in the appendix.

Initial Patterning and Electrode Fabrication Choices Photoresist Selection and Lithography Preparation

The work presented here began with the task of creating proper metallic leads, suitable for shadow edge evaporation. These leads were built atop Si/SiO2 substrates and to do this, UV lithography was employed for its previously mentioned adaptability and ease of use. Here in this text I will present an overview of the development path followed for building nanogap electrodes, from electron beam evaporation material selection, to photoresist and UV lithography optimization, and finally to the shadow edge evaporation technique development. Two standard negative photoresists were extensively tested, MicroChemicals' AZ nLOF 2020 and AZ 5214E. AZ nLOF 2020 was chosen as a promising candidate for its flexibility to reproducibly produce the same results under varying ambient conditions. Due to the nature of the cleanroom setup where these samples were prepared, a wide temperature gamut, ranging from 10°C to 30°C, was often observed following the temperatures outdoors. We also chose to work with AZ 5214E for its incredibly wide adoption and development. We chose to use negative resists due to the undercut created by their processes. Figure II.2 shows the general photoresist process (a), walking through each of the steps: initial spin coating and baking to evaporate excess solvent (not shown), UV light exposure, post exposure baking (PEB), flood exposure (only for AZ 5214E), and development. A short illustration of undercut benefits versus positive resists seen in (b) details the specific need for negative mode resists, and specifically shows the shape of the formed metallic layer that will remain after lift-off. A yellow and red triangle has been added to emphasize the slight angle that exists on the edge of any metal electrodes formed through this manor. While the ideal electrode should be completely upright on each edge, the actual outcome has a slight angle. This angle plays a role in the shadow edge gap formation, which will be seen later. The process began with spin coating a chosen photoresist on silicon wafers, atop which 500nm of thermal oxide was formed by CIME Nanotech in Grenoble. The photoresists were stored in a refrigerator and were allowed to rest at room temperature for 20 minutes before use. During this waiting time, silicon wafers were cut into smaller pieces before being washed with acetone in a sonication bath for 5 minutes, rinsed off with an isopropanol spray bottle, and cleaned under an oxygen plasma for 90 seconds. After this, wafers were ready for photoresist application. The oxygen plasma recipe can be found in the appendix.

Figure II.3 -UV Lithography Mask a) pattern on mask b) resulting transferred pattern following two exposures c) SEM image of a fabricated sample showing resolution issues e-f) zooms of top right corner of a and b. The final gap locations are shown in red

A mask was created specifically for this two-time UV lithography process. It was designed to form 252 nanogaps from a single rotatable design, with electrode widths ranging from 1um to 100 µm. Images of the mask design are shown in Figure II.3 along with a scanning electron microscope (SEM) image taken of the center of the mask after fabrication. For this image, a Tescan Mira3 SEM was used. Image a) shows the mask actual design of the mask while b) represents the final pattern after the mask has been rotated and a second patterning has been performed. c) shows an SEM image (poor resolution, limited the formed electrodes below 10µm). e) and f) both show zooms of a) & b), giving further details of the purpose of the mask. The gaps will be formed by the shadow of each horizontal bar. Each vertical bar, made in the second patterning, will dictate the width of the gap (shown in red in the figure). By virtue of rotating the pattern, samples will have gaps spanning 100μm to 1μm. This ensures that every configuration may be tested redundantly from a single mask. The mask also contains top gate and contact pad areas (not shown). The UV lithography machine used was an EVG 620 with a KarlSuss CT 62 spin-coater. After photoresist preparation, metal evaporation was performed.

Electron Beam Evaporation Metal and Evaporator Selection

The deposition settings utilized for the E-beam evaporation processes were strongly dependent on the machine and metal we employed. CMOS compatibility was the most important factor considered when selecting metals to work with. In order for any transistor technology to be readily adoptable, it must be integrable into current SiO2 processes. To achieve this, the chosen materials must be processed at low temperatures and must adhere to SiO2 layers without migrating through this layer over time. With these requirements in mind, we investigated electrodes fabricated from the metals in Table II.1. Two evaporators were present in the clean room, an Alcatel EVA 450 and an Edwards Auto 306. The first decision to investigate in this work was which of these evaporator platforms would be best suited as a basis for the development of shadow edge evaporation and electrode fabrication. Each of these evaporators was equipped and tuned for the deposition of specific metals and thus the choice of metal largely dictated which evaporator would be employed and vice versa. I will first speak to the evaporators themselves, explaining why the Alcatel was better suited for shadow edge evaporation. Next, I will explain why our first developments were performed using Al, before ultimately switching to Ti/Pd as the foundation for device structures. The specific details of the procedures for each metal and machine are laid out in the annex.

Preparing for Shadow Edge Evaporation and Evaporator Selection

The Edwards evaporator was much more flexible in terms of material selection, making it a strong candidate for development. However, in the end several aspects of its deposition and chamber setup necessitated the shift to using the Alcatel for its reliability.

In order to introduce fixed deposition angles in the evaporation chambers, we fabricated angled sample holders at fixed angles of 30°, 45°, and 60°. These smaller sample holders were then fixed on the planar sample holder plate of either evaporator's chamber. These can all be seen in Figure II.4. In order to fabricate specific gap lengths, the height of the first layer was tuned with respect to the fixed angle holders. It may be intuitive here, but it is imperative that the sample holder is not rotated during the second evaporation stage, in order to maintain the geometric angle. It is from these sample holders that we encountered the first issues with the optimization of the shadow edge evaporation technique. As geometries play a central role in the resulting gaps from the shadow effect, the angles within the evaporator must be controlled and reproducible, whereby the angle between the substrate itself and the deposition source are consistent. Next, the height of the deposited electrodes must also be held constant, and be highly reproducible down to a few nanometers. Developments were pursued based on these requirements, and the Alcatel was deemed better suited than the Edwards for four reasons:

1. Angle: In the Edwards evaporator, the sample holder plate was manually mounted on a pin on the roof of the chamber. This plate was held in place by a single screw, resulting in slight tilts or height differences between mountings of said plate. The Alcatel setup had a fixed structure for the sample holder for the crucibles, creating a more reproducible geometric environment. 2. Height: What's more, the quartz in the Edwards was mounted at the end of a flexible lever arm that would move periodically, causing some margin of error in the measured thickness of the deposited metal. 3. Speed: The Alcatel setup contained separate vacuum chambers for samples and crucibles, which decreased the time required to reach adequate vacuum levels by several hours. 4. Reproducibility: Finally, with the Edwards being a single chamber system, the sample was mounted close to the material source. As a result, for metals requiring a higher current, the sample holder could easily reach temperatures over 100˚C. Many samples produced at these higher temperatures produced odd structural defects, leading us to surmise that perhaps this high temperature was affecting the structural integrity of the photoresist.

Thus, for the sake of developing and optimizing shadow edge evaporation on a stable platform, the combinations requiring the use of the Edwards evaporator needed to be abandoned. This decision was reflected in the final materials that were selected for electrode fabrication and optimization, detailed below. For future reference however, speaking simply to the viability of these materials, both chromium/gold and titanium/platinum appeared to be strong candidates for low temperature measurement, shadow edge lithography electrodes.

Metal Selection

The first metal we tested was aluminum, chosen for its efficiency in cost and required evaporation energy, and because of its CMOS compatible properties and ability to directly adhere to SiO2 and Al2O3 layers without the need for an additional sticking layer. For this reason, we used aluminum to conduct the majority of photoresist calibration and early nanogap fabrication research. In fact, the best nanogap we

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

Page | 46 achieved was formed via the Alcatel evaporator using aluminum, on the order of 6nm. However, all was not roses and rainbows as a great deal of troubleshooting was necessary to obtain such a feat. The parameters used for aluminum deposition (as well as Ti/Pd, discussed later) via the Alcatel EVA 450 evaporator are shown in Table II Ultimately, we had to depart from aluminum in search of alternatives. The electrical measurement setup, discussed in much further details in the next chapter, employed metallic probe stations controllable via screws. While these metallic probes were easy to manipulate, they lacked the precision necessary to properly place the probe atop the electrodes without scratching them. This problem was exacerbated while performing measurements under liquid nitrogen cooling. At 77 K, it became nearly impossible to reproducibly form a proper contact between the probe and the electrode, while avoiding damaging the electrodes. Secondly, Al often exhibited delamination issues while performing a second lithography lift-off step, most likely due to adhesion between the photoresist and the Al electrode. Tests with chromium yielded overall similar results. Thus, we moved to investigate more robust electrodes made from titanium and titanium/palladium combinations available in the Alcatel. Titanium was chosen due to its strong adhesion, and palladium was chosen due to its robust nature. The stronger adhesion of thicker titanium layers during lift-off resulted in poor electrode formation reproducibility. On the other hand, titanium proved to be an excellent sticking layer when used at just 5nm thick, with no issues of lift-off. The sticking layer/noble metal combinations all proved to be much better candidates, however as reasoned above, in order to continue developments with the Alcatel setup, titanium/palladium electrodes were selected for full device fabrication. The final parameters for these Ti/Pd depositions are presented above in Table II

.2.
Moving into the patterning and electrode formation stages, Al was used for the majority of the optimization process, while the switch to Ti/Pd was made at the end when building full devices. The final step to present before discussing full device developments is rapid ion etching cleaning.

Reactive Ion Etching -Sample cleaning and Alumina Etching

Reactive Ion Etching (RIE) was used at several stages throughout the fabrication process. A simple oxygen plasma was used for cleaning the sample, both before spin coating, and before metal evaporation, to ensure the purity of the surface. Additionally, a CHF3 etching was used to remove Al2O3 and clean our contact pads before electrical measurements (discussed in the next chapter). The recipes in Table II With our technology stack fixed, we then moved to developing UV lithography patterning, to begin building devices.

Parameter Optimizations for Electrode Formation

The second half of the shadow edge evaporation development process was to optimize the UV lithography patterning procedure. As the shadow edge evaporation technique relies on the edge of the first deposited metallic electrode to form the second electrode line, this first edge must be straight, flat, and continuous by necessity. It was also necessary to be able to accurately transfer the mask pattern to the substrate. Any reproducibility issues in the length and width of the electrodes would create direct issues in the ability to compare fabrication processes. To this end, we optimized processes for AZ nLOF 2020 and AZ 5214E for electrode surface and edge uniformity.

AZ nLOF 2020 Optimization Photoresist Studies

It is here we began the research and optimization stages of photoresist preparation, UV exposure, photoresist development, metal evaporation, and lift-off. The substrates utilized were 275µm thick, <100>, boron doped, Si wafers coated with 500nm of thermally grown oxide, purchased from CLYM in Grenoble. Starting with the standard AZ nLOF 2020 recipe, seen in Table II.4, we were promisingly able to reproducibly reach resolutions down to 2µm for evaporated metallic leads. AZ nLOF 2020 is advertised and was chosen for being relatively stable under a wide range of ambient conditions. Despite this reproducibility however, we encountered several issues. Atomic Force Microscopy (AFM) images taken using an NTMDT NTEGRA over numerous Al sample batches proved three-fold the difficulties we would have using AZ nLOF 2020. First, we suffered from an effect MicroChemicals refers to as 'mouse-bites' where imbalances in the exposure due either to an imbalance of the UV source itself, improper hard-contact, or uneven spin coating lead to badly formed straight edges. This can be seen in Figure II.5a where an electrode edge was very badly formed. Second, we suffered from surface roughness uniformity due to the strength with which AZ nLOF 2020 sticks to the substrate, shown in Figure II.5b. Each of these issues was observed right off the bat. Thus, we began our optimization, changing each of the parameters in turn while looking for improvements.

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum

In the first trials, a primer sticking layer was used to improve photoresist deposition. However, we quickly removed this primer to reduce excess photoresist remaining after development. We also found early on that by removing the stage rotation during evaporation, a more reproducible electrode edge could be formed. Thus, these two steps will not be included. Here, the most prominent parameter changes will be presented, namely optimizations in the dose and the development time to straighten out the edges and remove the surface roughness.

Dose Optimization

The first step taken to improve electrode fabrication was to increase the dose to 75mJ/cm 2 showed immediate improvements with "mouse-bites" and slightly improved the overall roughness. However, it also introduced a non-uniform sharp peak on the left edge as seen in Figure II.6. This sharp peak would ultimately result in undesired gap sizes when performing the second shadowing evaporation.

Figure II.6 -AFM images and associated graphs of AZ nLOF 2020 electrodes. Each image demonstrates 2 recurring issues: the surface roughness (seen best in image c) and large peaks on the edges of the electrode lines

Development time optimization

Figure II.7 -AFM image of AZ nLOF 2020 electrodes demonstrating both surface defects and edge defects

Increasing the development time to 2 minutes in the next batch of samples, shown in Figure II.7, helped to reduce this surface roughness but did not do enough to eliminate it completely. This also had the obvious drawback of increasing the lateral dimensions of the electrodes beyond the intended width. Although this process was not yet perfected, we attempted a shadow edge lithography second stage nonetheless. The results, seen in Figure II.8 taken using a Tescan MIRA3 SEM, perfectly summarize the issues present in nLOF 2020 development. Following the strong adhesion, we believe to be at the center of the surface roughness issues, upon lift-off of the AZ nLOF 2020, the thin aluminum electrodes appear to have delaminated.

Delamination during Shadow Edge Evaporation

Extreme Development and Attempts to Correct Delamination

Next, extreme measures were taken, and development times were increased up to four fold the recommended amount. While we lost any semblance of resolution control, we obtained samples smooth enough that we felt comfortable attempting shadow edge evaporation. A second patterning and evaporation step was conducted and the results can be seen in Figure II.9. For orientation, the lighter colored line running top left to bottom right was the first deposited layer, while the darker line running bottom left to top right was the second. Several things should be noted from these samples.

Figure II.9 -AFM images of nanogap attempt of AZ nLOF 2020 electrodes showing A) the lack of a gap at the shadow edge B) a gap defect that formed on the side of the overlapping electrodes, most likely due to an offset angle and C) a trace taken following the dotted line

First, while the surface roughness issue has been drastically reduced, there are still roughness defects as well as edge defects along each of the electrodes. More importantly, as a result of the geometry and order of deposition, the gap should have been formed in the area marked by the dotted box. However, we can easily see a gap forming on the side of the electrode overlap, and a sharp peak of metal forming on the opposite edge. We believe this is a shadowing effect due to offset angles resulting from issues caused by the photoresist.

Ultimate failure of AZ nLOF 2020

While metallic lines with the above characteristics would be perfectly adequate for simple electrical measurements, they were insufficient for use in the shadow edge evaporation process. While not all mousebite structures will necessarily cause issues, there is a strong likelihood that an errant metal trace will cause a short circuit due to improper shadowing. Non-uniform surface roughness, especially along the edges, will not cause short circuits, but will create spots that will cast a longer shadow, leading to further nonuniformity in the gap. Finally, the stripping of the substrate around the edges of the metallic lines caused yet another uncontrollable factor that affected the height and distance of the evaporated shadowed second layer. While rigorous cleaning methods enabled the reduction of the surface roughness issues, adequate optimization of AZ nLOF 2020 for shadow edge evaporation was never achieved, and attention was shifted to AZ 5124E which resulted in better electrodes.

AZ 5214E Optimization and Nanogap Formation Photoresist Optimization

The preliminary work performed with AZ 5214E attempted to optimize the UV lithography parameters. Although standard lithography processing recipes are provided by MicroChemicals, they must often be modified, sometimes heavily, to achieve optimal results under potentially widely varying cleanroom conditions. This standard recipe for AZ 5214E can be seen in Table II.5.

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

Page | 51 While AZ nLOF 2020 is promoted as delivering reliably stable results under a range of ambient conditions, AZ 5214E's post exposure bake step is critical to the quality of the resulting trenches and must be kept within 1°C of a previously determined optimal temperature. If this temperature is not kept stable or is not set to its optimized temperature, even cross-linking will not occur, leading to uneven development and nonuniform metallic leads. Due to temperature control irregularities a great deal of optimization and study of this photoresist was pursued while developing the own shadow edge evaporation process. While adapting the shadow edge technique for the setup presented herein, optimizing the dose proved to be the most critical for combating the lack of temperature control. Ultimately, however, after proper improvements were performed in the cleanroom, we were able to work in a stable and controlled environment, producing wellformed electrodes with the standard recipe. Figure II.10 shows an AFM image of an electrode fabricated using AZ 5214E under optimal conditions. The edges and surface are immediately more uniform and smooth than those using AZ nLOF 2020. Note here that we can see a slight slope to the formed surface, seen in image b. This slope is most likely due to an offset angle in the sample holder plate of the Alcatel evaporator, discussed more below.

Figure II.10 -AFM images of Al electrode fabricating using AZ 5214E

Therefore, the dose optimizations used only during initial developments while combatting suboptimal conditions will be left out of the main text, as they do not contribute to the reproduction of the nanogap structures. Formations of nanogaps will be discussed directly below as AZ 5214E proved to be the best suited and was chosen as the photoresist for device development. Using the nanogap developments made via nLOF 2020 experiments, we were able to quickly realize shadow edge evaporation nanogaps using AZ 5214E so long as the environment was kept constant.

Nanogap Formation and Structural Analysis Theoretically, the length of the gap should follow the trigonometric relation between the height of the first electrode and the angle of deposition described above. These two variables, the height of the layer and the angle, must be calibrated and controlled in order to reproducibly form gaps smaller than 10nm. Any offset angles within the evaporation chamber must also be accounted for, requiring a thorough analysis of the structural makeup. However, top down SEM and AFM images did not provide sufficient information with this regard. To visually confirm the structure inside the gap, we turned to ion milling to cut a nanogap for cross sectional analysis. We fabricated a sample at 45˚ with Al electrodes formed via the Alcatel and used an Ilion argon ion beam miller to cut a cross section. This sample was then viewed from this side under standard SEM.

The resulting image of a two nanogap electrodes from the same sample (thus with the same electrode heights), seen in Figure II.11, verified not only the formation of a clean gap, but also the geometries of the chamber. First, it is clear to see that it is possible to obtain a dispersion of gap sizes for a given sample made at one angle.

Figure II.11 -SEM image of the cross-section from a 45° aluminum sample showing a nanogap and two electrode lines

This is most likely due to irregularities in the sample holder itself. Therefore, it is best to compare gaps in a given plane to reduce this error margin. From the images, we can see perceive that a small offset angle is present in the chamber itself. While the heights of the deposited layers are nearly at their targets of 90 and 30nm, the gap itself is smaller than the anticipated 90nm. The easiest piece to observe is the slope of the edge of the first aluminum layer. While this is predicted for negative resists in the literature provided by MicroChemicals (as seen in Figure II.2), we have little way of predicting the magnitude of the formed slope as we lack precise control over the resolution of the pattern. The strong contrast between the height of the resist layer and the deposited metal layers may come into play as the comparatively large undercuts provide space for electrodes to deform. We can also see that between these two samples, the sloped edge angle varies. We measured the heights, spacing, and the area of the II. 6, we can see that the 45° angle deposition actually saw an angle of closer to 40° in both gaps, either due to an inaccuracy in the support itself or in the deposition chamber. The conclusion here was that we would need to take both this offset angle, and the length of this sloped edge into consideration when building new gaps. To do so, a new diagram was created, shown in Considering these new geometries, a simple geometric formula was made in an attempt to create a model by which future gaps could be predicted.

𝐿𝑒𝑛𝑔𝑡ℎ 𝑔𝑎𝑝 = [ℎ𝑒𝑖𝑔ℎ𝑡 * 𝑡𝑎𝑛(𝜃 -𝜑)] -[ℎ𝑒𝑖𝑔ℎ𝑡 * 𝑡𝑎𝑛(𝛽)]

As β was not constant, as indicated above, such a simple model would never be perfect, but was tested nonetheless to see if it could produce proper estimations. Using this new equation, we extracted values for the offset angle and the sloped edge angle and compared the extracted values to ensure parity with the measured structures. The results, seen in Figure II.14, shows fit results that closely resemble the schematic seen above, with the exception of the 11nm gap found at 45˚. This outlier resulted from a very large β angle, which again shows the imperfection of this model. Fitting over the entire set, we find that the chamber has an offset angle of roughly 8˚, and the angle of this sloped edge is closer to 28 degrees as an average.

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

Page | 55 While not a perfect model for the SEM image we analyzed, these extracted fit values are not far off, lending an initial conclusion that these extra angles could be roughly predicted and accounted for when producing new gaps. However, the next samples produced, disproved this fact.

The next nanogap process attempt produced the smallest nanogap of this work, measured at 6nm. These samples were also made from Al via Alcatel evaporation, with 50nm and 30nm respective electrode heights. The resulting electrodes measured up to 100μm in width, exhibiting limited current under electrical measurements. With these samples, it was not possible to find values that mathematically fit all three data points using the model provided. It is immediately clear that this model is too simple, as it does not account for large individual variations on β. It was also necessary to fix the offset angle to 5˚ in order for the model to fit at all. In Table II.7, we took the reverse approach, attempting to calculate the sloped edge angle while assuming an identical offset angle to the previous devices. Of interesting note, the β value coming from the fit is nearly the average of the three independently calculated β values in the table suggesting that rough estimations are possible. Overall, the calculated angles were acceptable given our knowledge of the system, but highlight a large β variable that was not controlled within the confines of this study. It is thus clear that in order to more reproducibly build targeted nanogaps, it will be necessary to further understand this sloped edge angle formation. Reducing the resist thickness to reduce the 7.5-to-1 height ratio (900nm vs. 120nm) could reduce this sloped edge by reducing the undercut area of the resist itself. Nonetheless, while we were not able to obtain such small open gaps again as a result of the above issues, we were able to use this process to reproducibly form gaps averaging 10nm. These devices were then used to study ALD alumina growth on top of the electrodes and eventually Pt island inclusion, discussed in the next sections. From these unfortunate fitting results however, it became clear that any samples requiring direct comparison would need to be fabricated at the same time to ensure identical gap sizes. The final electrode fabrication process involved the following: Having demonstrated the ability to reproduce nanogap electrodes, we were able to move forward with developments, working towards building fully working transistors, complete with aluminum oxide and Pt island layers.

III. Platinum Nano-Islands Encapsulated in an Aluminum Oxide Matrix 1. Introduction

As previously mentioned, M-I-M SETs function via Coulomb blockades formed when electrons, attempting to tunnel through a dielectric barrier, are blocked by a charged metallic island. In this section, I will discuss the methods and processes employed to build platinum nanoparticle islands and encapsulate them in an aluminum oxide dielectric matrix.

With a background in ALD development using a FIJI F200, we chose to investigate atomic layer deposition techniques for the basis for these layers. Following the work of Corina Barbos and Khalil Hajjam, we chose aluminum oxide thin films as the encapsulating dielectric matrix 11,12 . Aluminum oxide is well documented for having an extremely uniform growth via ALD, with a high dielectric constant and high robustness 13,14 .

Platinum was chosen for several reasons. The primary reason lies in its strongly inert nature as a noble metal, and resistance to oxidation seen in other materials. As non-Nobel metals begin to scale down in size, the exposed surface area begins to outweigh the area of the bulk, thus facilitating the rate of oxidation as oxygen first attacks the exposed surface atoms [15][16][17] . This would be especially pronounced, as the metallic islands will be fully surrounded by oxygen-rich alumina. Second, Pt typically exhibits a very large work function vs. standard oxides, enabling large carrier confinement and retention 18 . Third, two well proven techniques were readily available, thin film dewetting and PEALD growth [18][19][20][21][22][23][24][25][26] . Dewetting immediately presented itself as a strong candidate for its simple implementation. Requiring only a metal evaporator and a furnace, dewetting was not only readily accessible within our facilities, but was is also readily scalable 21 . The major benefits of using ALD for island growth were two-fold. The first, we would be able to build a

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

Page | 58 dielectric matrix with encapsulated nanoislands in one fabrication process. This unified process would allow for fabrication at a constant, CMOS compatible, temperature without exposing the substrates to the atmosphere, thus improving the purity, conformity, and reproducibility of device formation. Secondly, as ALD growth is solely a function of the reaction temperature, the number of cycles, and precursor exposure time, the size of the resulting dielectric layer and islands can be easily calibrated 24 .

The results of these fabrication developments will be presented below, with full procedures and descriptions of the full process found in the appendix.

Matrix and Island Formation Atomic Layer Deposition of Aluminum Oxide

For the formation of tunnel junctions and SET nanoislands, we turned to atomic layer deposition, known for its ability to grow highly uniform monolayers over a very large surface area 13,27 . An image of the FIJI F200 ALD utilized in this work can be seen in Figure II.17. Atomic layer deposition relies on selflimiting chemical synthesis to grow homogenous layers.

To implement, coupled reactive gaseous precursors are loaded in gas canisters and connected to a reaction chamber behind controllable valves. By alternatively pulsing the two precursors into the reaction chamber with a set cadence and pattern, monolayers of a desired material may be deposited on any surface inside of the chamber. For building dielectric thin film tunnel junctions, we chose aluminum oxide for its well-studied and documented growth rates and robustness. The growth process of aluminum oxide serves as a prime example of the mechanisms and expected outcomes of ALD.

Figure II.17 -Image of an Ultratech FIJI F200 ALD (not pictured: gas lines behind and vacuum pump below)

To begin, an ALD structure must be assembled containing a reaction chamber whose inlet is connected to chemical transfer lines, and whose outlet is connected to an evacuating vacuum pump. Two precursors are bottled and connected to the transfer lines. In the case of aluminum oxide, these two precursors were trimethylaluminum Al(CH3)3 (TMA) and H2O. Further gas sources are connected to the transfer lines, namely argon, used as a carrier gas for the TMA and H2O and to evacuate the chamber between each reaction cycle. Once this setup is complete, samples may be introduced into the reaction chamber. To facilitate faster fabrication speeds, the reaction chamber was kept at a constant 200°C as all of the fabrication processes here were employed at this temperature. Next, the chamber was sealed, put under vacuum, and the heaters were brought to the desired reaction temperature. The reaction process was then First, constant flows of argon and nitrogen were introduced to the transfer lines and reaction chamber respectively. Next, TMA is pulsed into the chamber, and the molecules are allowed time to settle out of gas suspension on all open surfaces in the chamber(a). The TMA molecules will bind with the OH molecules already residing on the surface of the substrate, forming AlOAl(CH3)2 on the substrate while CH4 gas will be released into the chamber(b). After adequate time has been allowed for TMA to coat the entire surface of the substrate, an argon flow is introduced to the chamber, carrying away the excess CH4 gas. After this purge, H2O is pulsed into the chamber(c). Again, time is allotted to allow H2O to fully react with the adsorbed molecules resulting in a monolayer of Al2O3 being formed on the substrate while further CH4 is released as a gas into the chamber(d). Once more the chamber is purged of any excess gas and the process is repeated(e-f). As the only possible reactions form via the monolayer of TMA that is allowed to adsorb on the surface, each process cycle will form a precise monolayer of Al2O3, 1.1Å, atop the previous layer allowing high precision thin film growth. The resulting layers are amorphous, highly uniform, and defect free if parameters are fixed well. Following the standard recipes provided by Ultratech, it was trivial to begin fabricating controllable thin films of aluminum oxide. This setup allowed for an automated control of the precursor introductions and overall number of reaction cycles. A large study was undertaken by Khalil Hajjam to study and optimize the growth of various dielectric materials on this very setup, ultimately arriving at the best recipes to employ 12 . This was backed up by a deep material study of Al2O3 grown using this reactor by Corina Barbos 11 . We used this to our advantage to build alumina tunneling barriers tuned to specific thickness needs. When building nanogap devices, very specific thicknesses were employed either to add spacers matching the size of the gap without filling it, or to add spacers directly between islands. The deposition speed was dictated by the delays between each precursor pulse, which, in this instance, fixed the deposition rate to 20s per cycle. With the alumina growth parameters fixed, we moved to build the underlying island layers.

Platinum Island Growth Techniques

To build the Coulomb blockade inducing nanoislands we investigated two techniques: dewetting of platinum thin films and direct PEALD growth of islands. Metallic thin film dewetting has been thoroughly

CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth

Page | 61 studied 19 , with strong examples of Pt nanoisland formation 20,21 . The second was PEALD Pt deposition, well demonstrated as a technique for forming nanoparticles 22,[24][25][26]29 .

Platinum Island Formation via Dewetting of Platinum Thin Films

To begin testing island formation via dewetting, 10nm of Al2O3 were deposited via ALD atop SiO2 wafers and copper TEM grids. 1nm of platinum, evaporated via an Edwards setup, was then deposited on top and pairs of samples were subjected to rapid thermal annealing at peak temperatures of 400°C, 600°C, 800°C, and 1000°C as summarized in Table II.8. The samples were annealed in an ADDAX rapid thermal annealer at atmospheric pressure with a nitrogen flow over the samples. The ADDAX setup only allowed manual control over the delivered power. Therefore, it was only possible to control the ramp up time and maximum temperature, but not the ramp down. Therefore, the times to ramp down to 100˚C and 50˚C were recorded to give an understanding of the amount of time the samples spent at higher temperatures. TEM and AFM analysis, seen in Figure II. 19, revealed this to be a great technique for quick nanoparticle formation but a very poor method if control over size and shape of particles was necessary. As thermal energy is introduced to the metallic thin film, defects in the crystalline lattice will begin to propagate, stopping as they reach various grain boundaries. As these defects build up at the edges of the grains, cracks will begin to form and grow, eventually splintering the thin film into grains of varying size. Additional heat energy will cause this process to continue, and spherical nanoparticles will begin to form as the metallic system attempts to reduce its surface energy. The beginning of this process is apparent comparing images A and B, where it is evident that even at 400°C, particles are beginning to form at the edges of the film, where surface defects are higher. These particles were on the order of 0.5-4nm, but did not propagate fully across the whole grid. It is clear to see past 10nm from the edge of the film, the Pt is still holding together in aggregates. Next, looking at 600°C and then at 800°C, we can see that distinct particles are clearly separating from the film, with particles averaging 4-20nm at both 600°C and 800°C, but the uniformity is much higher at 800°C. However, at each of these conditions, the islands are not yet forming the spherical shapes we desire for symmetrical operation in these structures. We finally see fully spherical shapes appearing under 1000°C, but by this point, the thermal energy is so high that the particle size has become widely dispersed, and very large, over 20-30nm on average. Ultimately, dewetting required prohibitively high temperatures, making it a poor choice while selecting industrializable processes. We also had very little ability to uniformly produce islands below 5nm as we were pursuing. As such, dewetting was dropped from the lineup of candidates for Pt island formation.

Figure II.19 -TEM images of Pt nanoislands formed via dewetting at a) just alumina b) 1nm of Pt before annealing c) 400°C d) 600°C e) 800°C and f) 1000°C

Plasma Enhanced Atomic Layer Deposition of Pt Islands

We then turned to PEALD deposited platinum techniques. Unlike Al2O3, which shows exemplary monolayer growth, platinum exhibits a nucleation delay during its growth process, leading to randomly dispersed island formation. This nucleation delay has been well studied and documented by Ultratech directly, with their results presented in Figure II.20. They found that the largest nucleation delays were seen under thermal conditions, with these delays increasing with a decrease in the applied temperature. Ultimately, it pointed to thermal deposition at 100˚C or 270˚C to be strong candidates for island formation. 100˚C was out of the question, as it required a hydrogen precursor setup that this Ultratech was not equipped for. In order to avoid the use of hydrogen, higher thermal temperatures were required. However, as we wanted to encapsulate these islands in ALD grown alumina directly, the use of a common reaction temperature would improve the speed of fabrication, and avoid unnecessary thermal cycling of the samples. This led us to begin development with plasma enhanced deposition techniques, which allow for a reduction in the reaction temperature. The data points offered by Ultratech were inconclusive for plasma deposition at 200˚C, the same temperature as that of the chosen alumina deposition parameters, and thus we began here.

Figure II.20 -ALD grown Pt film thickness vs. # of cycles for MeCpPt-Me3 employed in a FIJI ALD under varying conditions, grown atop SiO2 30

An additional precursor bottle must be introduced to the transfer lines for platinum deposition. For this, the precursor (methylcyclopentadienyl)trimethylplatinum, or MeCpPt-Me3 (CH3C5H4)Pt(CH3)3 was connected to the ALD and was constantly maintained at 80°C via a heating jacket throughout the lifetime of the bottle. To begin this process, the chamber was maintained at 200°C and platinum deposition was initiated immediately after the final purge of the aluminum oxide deposition stage. The full list of parameters we employed can be found in the annex. Although the basic principle of dual precursor selflimiting reactions, seen in Figure II.18 for alumina, still holds, the fundamental reaction that takes place during platinum island nucleation are different. Several works have been conducted on the study of Pt deposition to fully understand the reactions and processes involved 31 . Based on a study by Kessels, we will present the Pt deposition process along with its understood reactions below 31 .

Following the standard procedure, the argon valves are opened allowing it to flow through the transfer lines as a carrier gas. Oxygen valves are also opened this time, allowing a flow through the plasma head mounted at the top of the reaction chamber. MeCpPt-Me3 is pulsed into the chamber and allowed to settle on the surface of the substrate for 10s. During this time, MeCpPt-Me3 molecules will react with adsorbed oxygen on the surface of the substrate, oxidizing some of the molecule's surface ligands, releasing H2O, CH4, and CO2 gases into the chamber. After adequate settling time, oxygen is pulsed into the chamber and a plasma exposure is applied for 20s. In this case, the oxygen plasma was set to 300W. Here, the oxygen plasma will react the remaining molecules, oxidizing and breaking any remaining precursor ligands surrounding the platinum atoms, releasing hydrogen and carbon in the forms of H2O and CO2 until only platinum remains on the substrate surface. At this time, the plasma head is turned off and the oxygen pulse is cut. Another delay of 10s is set to allow argon to carry the remaining gases out of the reaction chamber and the process is repeated. During each cycle, platinum molecules will adsorb on the surface of the substrate. The differentiating factor here is the surface coverage of platinum during each pulse. Platinum will not form monolayers as aluminum, but instead will create independent Pt molecule sites that will Once the setup was outfitted with Pt precursors and the proper procedures were automated and attempted, we moved to TEM observations of growth rates to verify this process.

Transmission Electron Microscopy and Platinum Island Study TEM Observation

We started this study of dielectric and island growth through transmission electron microscopy with high-resolution in-plane analysis. In order to observe the particles we grew alumina and Pt islands on SiO2 TEM grids to study growth rates. The SiO2 grids, purchased from Oxford Instruments, contained an 8nm SiO2 mesh layer atop which materials could be deposited and observed. Following the standard recipe, we inserted SiO2 wafers paired with TEM grids into the ALD chamber and in a single run deposited 5nm of Al2O3 and either 15, 30, 45, and 60 cycles of Pt. The TEM grids were observed using a JEOL 2010F TEM equipped with a Gatan CCD Camera and the resulting images can be seen in Figure II.21. The wafers were set aside for RBS analysis reported below. Two samples were formed at 45 cycles in entirely separate runs on separate days in order to verify the reproducibility of this process. From these images, we can easily see the nucleation rate of Pt under a plasma-enhanced environment. We can also confirm the crystalline nature of these particles. The growth rates we encountered are similar to those of Novak et Al.'s, although their particles were grown at 270˚C 24 . They obtained similar results, finding roughly 1.5nm particles at 30 cycles, 3nm particles at 45 cycles, and conceivably 4-5nm sized particles at 60 cycles if their data had continued. It is likely that the larger particles they found while employing similar cycle numbers were simply due to the temperature difference of the reactor. Comparisons to the rest of the articles on Pt ALD growth (cited above) used parameters that varied too greatly from those produced in this work, either in temperature or in substrate, and produced growth metrics too far from own to draw direct comparisons. Using the software ImageJ, the size distribution was analyzed, as shown in the inlays of the previous figure, and the particle density was measured 3-11E12 particles/cm 2 . This density is quite high, relating well to the needs of nonvolatile memory particle densities 20 .

Although the size range was easily tunable via the number of PEALD cycles, reproducibility proved to be hit or miss. Throughout the fabrication of devices, shown in the next section, all devices built in the same run all resulted in identically sized and spaced islands. Performing the same process on a different day, however, seemed to result in slightly altered growth metrics, as indicated between images c and d above. It is not yet understood whether this variance of growth per cycle is due to the equipment itself, due to the age of the sensitive precursor itself, or whether it is simply a characteristic of Pt island nucleation delay varying between experiments. Turning to the literature, it is possible to find nucleation delays of 20 cycles 24 , 40 cycles 26 , and 50 cycles 22 depending on the growth parameters employed, showing a) that the nucleation delay can vary and b) that the process employed herein falls right at the edge of the nucleation delay, perhaps resulting in this non-reproducibility. From here, the optimal conditions were chosen as best as possible for future island growth. The work reported above, studying the growth of Pt islands, showed that not only was the size of the islands controlled via the number of cycles, but also that the spacing between each island was also controllable via precursor exposure times. The control over island size was sufficient for this study and thus we chose to work with both 30 cycles and 50 cycles, targeting 1.5nm and 5nm particles respectively, in order to have a strong spread of small particle sizes. Selecting two cycle quantities would also enable us to measure the differences brought on by varying particle sizes.

RBS Analysis

Islands were also deposited on SiO2 bulk wafers alongside these grids and were characterized using Rutherford Backscattering Spectrometry to further verify the formation of pure Pt particles 32 . The results can be seen in Figure II.22, showing not only a very distinct Pt peak in each case, but also the growth rate as the density of platinum on the surface increased. From these measurements, we were able to verify that at 15 cycles, Pt had in fact been deposited on the surface, just not in any visually observable quantity. We can also see that the growth rates are not linear, as the peak increases dramatically over the course of the 30-60 cycle range. This affirms the existence of a strong nucleation delay in the growth of Pt within the setup. It also indicates that the Pt islands are growing in size not only from new depositions, but also from aggregation. In the jump from 30 to 45 cycles, the Pt islands roughly increased 60% in size, while the density of Pt overall increased 30%, showing that islands must be coalescing during deposition. This finding of island coalescence was mirrored in the work of Baker et Al. and Christensen et Al. 22,25 . After validating

IV. Conclusion

Through this work, we developed the foundations for full SET device fabrication. Ultimately, in the pursuit of a scalable process, the most industry-ready techniques proved to also be the best suited for our fabrication requirements: UV lithography, E-beam evaporation, and ALD. In order to accomplish these developments, non-trivial calibration of both UV lithography and evaporation parameters was required. We also investigated Pt thin film dewetting while attempting to study and weigh optimal techniques for island formation but ultimately settled on ALD enabled dielectric encapsulated Pt nanoislands to form the SET paths.

The final electrode fabrication process relied on a combination of patterning via UV lithography with AZ 5214E negative photoresist, and electrode formation via E-beam evaporation of a titanium sticking layer and palladium conductive layer. The photoresist AZ 5214E proved to be a strong candidate for forming smooth and flat-surfaced electrodes in negative mode above 2μm, but required a very stable ambient environment to reach the high level of reproducibility required. Eventually, studying devices with much larger aspect ratio electrodes, made possible thanks to the shadow edge evaporation technique, and by employing electron beam lithography to achieve very narrow electrodes, a deeper understanding, and perhaps improved device metrics, can be reached.

In order to work with the two fixed evaporation setups that were employed, we machined angled sample holders with fixed angles and combined this with a second stage of patterning to form nanogaps via shadow edge evaporation. By employing this two-step evaporation process, we have been able to achieve 100um wide electrodes with open nanogaps down to 6nm. This process allowed for rapid prototyping and ultimately, paired with ALD and PEALD, provided an ample platform for the fabrication of hundreds of SET structures in a single fabrication run. In modern evaporation machines, the sample holding stage itself can be controllably and measurably rotated to introduce this shadowing angle, providing a greater degree of control. In the future, such a setup could be used to tune the size of the gaps down even further, to produce devices with more direct tunneling paths. ALD techniques were studied for fabricating and encapsulating Coulomb blockade inducing islands and dielectric barriers. We used thermal ALD and PEALD at 200˚C to build island layers with uniform and evenly spaced islands of less than 5nm with controlled dielectric spacers. The results mirrored the wellreported results of others, exhibiting controllable monolayer growth of alumina and a calibrated nucleation delay of platinum, resulting in nano-island formation. Next, the exposure times could be studied and calibrated within the setup we employed, leading to even more control over the island placement and spacing. It has also been shown that PEALD grown alumina shows fewer defects, and a more robust study should be performed within the setup to determine if this could result in better device control.

Finally, with these fabrication steps well studied and the results well controlled, we moved to integrating these steps into full devices, looking to study both the conduction mechanism of these new island layers and eventually probing for Coulomb blockade effects.

CHAPTER 3 Two-Terminal Platinum Nanoparticle Nanogap Device Characterization

I. Introduction

Having fully calibrated procedures to fabricate and tune both metallic nanogap electrodes, alumina dielectric barriers, and Pt nanoislands, the next steps involved testing devices made from these techniques. We designed several device configurations from the developed methods, each with the intention of testing how the introduction of Pt nanoparticles would influence conduction. With the intention of pursuing Coulomb blockades through these Pt islands, it was important to understand the imposed transport mechanism and determine whether they could be modulated. Thus, we developed full fabrication stacks of the previously reported processes to develop each of the proposed device designs. Next, we characterized these structures using electron microscopy to verify these fabrication combinations. Two-terminal electrical measurements were conducted on each configuration to gain a better understanding of the carrier transport through these ALD grown Pt islands and alumina layers. Finally, the resulting I-V responses were fit using different mathematical transport models typically seen in nanoparticle matrices with conclusions drawn as to the nature of the films.

II. Two Terminal Device Fabrication

To begin fabricating full devices, the same Si/SiO2 wafers from CLYM in Grenoble were used as a foundation. These wafers were selected to test for proper CMOS compatibility, but mainly served as a stable and easily manipulated base layer with which to grow the device structures. From here, several strategies of device geometries were employed for careful examination of the transport properties through the island layer. Each fabrication process will be described in the sections below, while a summary of these samples and the names used to refer to them can be seen in Table III.1. The optimized fabrication processes combine the following:

1. UV photolithography patterning with AZ 5214E negative photoresist 2. E-beam evaporation of Al, and Ti/Pd for electrodes 3. Shadow edge evaporation for forming nanogaps (where applicable) 4. ALD grown Al2O3 thin films 5. PEALD grown Pt nanoparticles 6. RIE etching to clean the samples and uncover contact pads Each of these techniques has been developed and detailed in the previous chapter. In this section, the process of Pt island integration, as well as the development of full electrode devices will be presented.

Encapsulated Pt Islands Layers

As previously presented, Pt was chosen to implement nanoisland matrix conductive paths. Three configurations of Pt islands were investigated, built using PEALD, and encapsulated in an Al2O3 dielectric matrix using ALD. These configurations are shown in the last column of Table III.1, but will be rewritten in Table III.2 for ease of reading. In the previous chapter, it was shown that PEALD growth of Pt islands produced size controlled, well-dispersed islands, but the exact sizes produced were not precisely reproducible from one day to the next. Therefore, all samples sharing island configurations listed below were fabricated not only on the same day but also in the same run itself. This allowed for a direct comparison between, for example the vertical multistack and planar buried multistack were placed side by side in the ALD chamber to fabricate the 50 cycle island layers. It was then necessary to characterize the islands of the subsequent samples to verify the sizes produced. The first configuration was a simple monolayer of 50 cycle Pt islands, intended to be captured in between two electrodes in a planar fashion. The second monolayer of 30 cycle Pt islands, was used in a buried configuration, completely encapsulated in dielectric, and separated from the electrodes by 2.4nm of alumina. The third configuration was a multistack composed of 5 layers of 50 cycle Pt islands, each separated by 2.4nm of alumina that were simultaneously grown in vertical and buried devices. The final configuration consisted of 5 layers of 30 cycle Pt islands, each separated by 2.4nm of alumina, that were built into buried island devices. These multistack structures se rved two fold. They enabled an investigation of the current density scaling and increased the total current output for eased measurements. As a reference point, samples were fabricated without Pt nanoparticles, with equivalent amounts of alumina. The ALD/PEALD process, detailed in the previous section, enabled us to fabricate each of these island configuration types in one reaction chamber, under vacuum, at a constant temperature. The full recipe can be found in the annex.

Next, electrode structures were built in vertical and planar configurations to connect with these nanoparticles.

Filled Gap Planar Structure

The goal of the planar structures was to trap a single row of parallel Pt nanoparticles inside of a sizecontrolled nanogap. By first building electrodes with a gap smaller than 6nm, several nanometers of alumina can be grown to precisely tune the gap to fit Pt particles, grown to perfectly fit this gap. A block diagram of this device can be seen in Figure III.1.

Figure III.1 -Block diagram of filled gap planar structure

To build these truly planar structures, aluminum nanogap electrodes were built directly on top of an Al2O3 coated SiO2 substrate using the shadow edge evaporation process. Next, 10nm of ALD alumina was again grown, partially filling in the gap, and completely isolating the electrodes. In the same process, 50 cycles of PEALD Pt particles were deposited along with a top coat of alumina, filling in the gap with nanoparticles. Several samples were fabricated in this method, with twin devices being set aside after electrode deposition, with no material filling the gap. These devices provided a reference point to gauge the conductive contribution of the islands.

Vertical Structures

Figure III.2 -Block diagrams of stacked structures, left) alumina reference right) with 5 layers of Pt islands

Vertical capacitor structures, which were easier to control and fine tune, were built to observe and test the transport properties of the nanoparticle/dielectric matrix. These capacitor structures were built using e-beam evaporation and ALD, obtaining easily controllable tunnel barriers due to ALD's direct monolayer growth. Multistack island structures with thin barriers and accompanying reference devices without islands were studied and compared. We fabricated bottom electrodes, atop SiO2 wafers, made of 200nm thick films of aluminum deposited via the Alcatel evaporator. After, we used the previously presented ALD recipes to create both multistack and reference capacitor structures, capped with another 200nm thick film of shadow mask patterned aluminum to act as a top electrode. These top contacts were formed as circular contact pads, 500μm in diameter. We also developed a second planar geometry, burying Pt nanoparticles beneath the nanogap electrodes. This structure was not only more flexible as it did not rely on finely tuned nanogap sizes, but also allowed us to build the previously mentioned multistack structures to control the spacing between nanoparticles. The reason this spacing came into play in this configuration was as follows: looking back at the TEM analysis of the island growth and distribution process in the previous chapter, we can see that while ALD equips us with a means of finely tuning the size of the particles, we had no independent control over the spacing between these islands. To add a level of control to this structure, we chose to mimic the multistack of Pt particles from before, depositing 2.4nm alumina layers between each layer of islands, thus introducing a new, controlled, shortest tunneling path between islands.

Buried Island Structures

The same two Pt configurations from above were pursued here, building monolayer and multistack Pt films as detailed above. A bottom gate electrode was added to these structures, built directly atop the SiO2 wafers. The electrode itself was made of 5nm of Ti and 80nm of Pt deposited by e-beam evaporation. These bottom gate structures were then isolated with 55nm of ALD grown Al2O3. Directly atop this alumina layer, both the monolayer structure was built with 30 cycles of Pt and two multistack structures were created with 30 and 50 cycles. This change in cycle count allowed us to directly compare the effect of island sizes.

Mask Design and Top Gate Electrodes

Figure III.4 -Newly developed shadow edge lithography mask design with each color indicating a new patterning stage blue) first and second electrode layers green) gate electrode purple) etching for contact pads

After initial transistor electrical measurements, we quickly found that while we had obtained an isolated bottom gate, biasing this gate had no effect on the conduction of the Pt film. These results and our understanding of the system will be discussed in the next chapter, but this development led us to deposit a top gate on the buried structures to complete the transistors. A new mask was designed to accommodate the need for these additional steps, which can be seen in Figure III.4. The long horizontal bar acts as a first shadowing layer, with each end (in green) acting as an electrode contact point. After, each vertical line forms its own nanogap, each terminating in an isolated (green) contact point. Finally, gates are formed over the gap (maroon). The top gates were fabricated from a 20nm thick ALD Al2O3 layer, capped with a 5nm Ti/20nm Pd gate electrode.

Figure III.5 -A block diagram of the buried multistack island structure with a top gate

This new configuration allowed each equivalently wide gap to be formed in the same plane, in an effort to reduce the angle dispersion seen in the previous chapter. The addition of this gate oxide layer ensured that no foreign species was able to adsorb inside the gap and that conduction would pass through the Pt layer.

Finally, this same gate oxide alumina on top of the green contact pads is etched away using RIE to ensure a strong metallic contact. A block diagram of the filled in gap and top gate can be seen in Figure III.5, which includes measurements and material labels for clarification. Here, we paid careful attention to study buried devices both with and without a top coating of alumina, to verify conduction was truly occurring through the Pt matrix.

III. Characterization Methods

TEM Thin Lamella Characterization

Once structures were built it became necessary to have information not only on the surface but also on the geometry inside the gap. This was especially critical for the planar structures as they involved island layers built underneath and inside the gap directly. To achieve this, we sent samples to two organizations, a company SERMA in Grenoble, and our own FIB preparation team. Each group performed FIB lift-out, delivering thin lamella samples varying between 20-100nm in thickness, lifted out of the gaps. These thin lamellas were prepared and observed using a transmission electron microscope after electrical characterization to avoid any beam damage or charging of the samples brought on by the high power electron beam. The TEM employed for this work was a FEI Titan ETEM G2 80-300kV. For the sake of clarity, these TEM results will be presented before the electrical measurements in each section, as to give a view of what we are discussing. With these thin lamella samples we were able to perform deep structural characterizations via TEM. Each of these characterizations will be shown below. For these samples, we performed TEM in scanning mode (STEM), high-resolution mode (HRTEM), and with energy-dispersive x-ray spectroscopy (EDX) and tomography.

HRTEM employs a large objective aperture to direct the electron beam and measure the diffracted electrons. This mode allows for the analysis of crystal lattices as it can detect and display diffraction patterns used for indexing materials. STEM, instead, adds additional focusing coils, which allow for focusing the electron beam on a very fine spot that is then rastered over the sample to form an image. STEM was employed in dark-field in order to increase the contrast and visibility of the Pt nanoparticles. Using scanning also allows for the employment of EDX and Tomography. EDX uses the electron beam to excite and eject electrons from a sample. These electrons, known as Auger electrons, carry an energy dependent on the material they were ejected from, thus allowing an electron detector to measure the materials present. Tomography is an advanced technique whereby the sample is rotated about a fixed point and multiple images are taken in order to reconstruct a 3D model.

Electrical Measurements

Once the fabrication of nanoparticle devices was completed, it was necessary to characterize and validate their contributions to the conduction. Measurements were conducted by placing each device atop a non-conductive mica slide inside of a temperature controlled vacuum chamber. The chamber itself was connected to a vacuum pump, allowing us to reach a minimum pressure of 10 -5 mbars. Inside of the vacuum chamber, the stage was connected to both a transfer line for cooling and a controlled heater. Once samples had been loaded and proper time was allotted to allow the pressure to reach 10 -4 mbars, this setup enabled us to controllably sweep over a temperature range of 77 K to 400 K by introducing liquid nitrogen for cooling and controlled heating for regulation. Using this temperature control setup, each sample underwent a short heating at 400 K under vacuum to ensure excess water vapor was removed from the surface before freezing. Once set, conducting micromanipulator arms were used to place metallic probes on the contact pads, connecting them to a Keithley 4200-SCS.

Speaking quickly about the fabrication process, it was necessary to remove the alumina from the contact pads to facilitate proper contact with the probes, as even a thin layer of alumina proved detrimental to forming a stable connection. Despite clearing the contact pads, it was still a non-trivial matter to form stable contacts between the probes and the contact pads at temperatures below 200 K. In order to ensure proper contact, the probes were lowered into contact with the contact pads, and were dragged back and forth across the surface of the pads until a full I-V measurement could be performed without a drop in signal. This proved to be too harsh a process for Al based contact pads, leading to the transition to harder Ti/Pd contacts. Despite employing these procedures to ensure proper contact, or perhaps as a result of this lack of finesse, obtaining reproducible measurements were few and far between. Many nanogaps of each type were produced and measured, and the results presented herein are believed to be representative of the average response of each. A major consideration results from this difficulty to obtain stable contact at lower temperatures. There is a possibility that an additional resistance is being added at lower temperatures due to the contact between the probes and the contact pads.

The SMUs of the Keithley were capable of both delivering steady voltage levels while also measuring incoming current with a noise floor of 1fA through triax connectors. This allowed current to be independently measured across each contact point, and this current was then fed to amplifiers capable of measuring signals as low as 1E-13 A with little to no noise. In order to reduce this noise threshold and avoid hysteresis, the voltage steps, timing, and caliber were all optimized. In order to optimize for quick but accurate measurements, typical settings were chosen as thus: a voltage step chosen to give a total of 200 steps over the whole measurement, an initial hold delay of 10 seconds, a step delay 0.4-1 second, and a caliber chosen to match the range of measurement. The maximum current passing through each probe at a given instant was limited appropriately by setting a compliance level on the Keithley, whereby the voltage was automatically reduced if current levels rose past this limit. It was necessary to impose strict limits on the applied electric field levels as the alumina layers were prone to dielectric breakdown, where a change in the response can be observed after the application of a large voltage. Preset measurement settings were used, tuning the amount of signal averaging and speed of acquisition to reduce noise levels.

Current vs. voltage measurements were chosen as a straightforward method for probing the conduction properties of the various devices. By employing the same measurement methods across each of the devices, any changes in the conduction would be readily visible in the resulting I-V curve. What's more, thanks to numerous works in the world of conduction theory, we could directly apply fitting based on well-studied analytical models, allowing us to thoroughly probe the properties of the particles 1,2 .

IV Response Analysis Methods

From the resulting current vs. voltage I-V responses, we applied conduction model fits to the data. The following electron transport models, presented with further details in Table III.3, were studied: Schottky, Fowler-Nordheim, Poole-Frenkel, and nearest neighbor hopping 1,2 . Each of these mechanisms is hallmarked by distinct driving phenomena and diagrams of their actions can be seen in Figure III.6. The Schottky and Fowler-Nordheim models are characteristically electrode-limited transport mechanisms, meaning the interface formed between the electrodes and the dielectric medium drive the conductive properties. In these instances, the specified barrier height, so prominent in the two equations, refers to the barrier height between the electrodes and the dielectric. Poole-Frenkel and hopping on the other hand are bulk-limited transport mechanisms, meaning the properties of the dielectric film itself drive the current response. We also pursued two hybrid models, variable range hopping and cotunneling, both reported for planar nanoparticle structures and SETs 3,4 . Variable range hopping presents itself as a random hopping mechanism that appears at low voltages follows a very strong dependence on the temperature 5 . Cotunneling, as the name implies, features tunneling events of paired electrons. In elastic cotunneling, electrons are able to tunnel from one site to another given the pair each share the same eigenstate. In inelastic cotunneling however, any two neighboring electrons may pair and tunnel concurrently from one particle to the next 3,6 . Variables: Going into to further details, on each of these, we can see the large temperature dependence Schottky, Poole-Frenkel, and hopping each has. This comes as a result of these mechanisms relying on thermal energy to lift the electrons up over energy barriers present at interfaces or traps in the dielectric. In the case of Schottky, this barrier is the electrode/dielectric barrier, and in the case of PF and hopping, this barrier is between the dielectric and intermittent energy level inclusions in the matrix. With Schottky and Poole-Frenkel, sufficient levels of thermal energy can excite electrons up over the dielectric energy barrier, facilitating conduction through the typically insulating dielectric layer. In Schottky conduction, this occurs through a direct transfer of the electrons to the conduction band of the insulator, while Poole-Frenkel conduction is facilitated by intermittent energy levels presented in the insulator, typically via traps. FN, on the other hand, is entirely voltage bias driven, and thus should exhibit a direct transport mechanism that is largely immune to thermal fluctuations but may still see an overall change due to physical changes within the conductive medium. Hopping, functions similarly to FN, where if the barriers are sufficiently thin, these electrons can tunnel directly through from one intermittent energy level to the next. To probe these states, measurements were conducted across a temperature range varying from 77 K to 300 K. Each of these proposed models was fit over the I-V response measurements collected using the methods presented in the previous section. OriginPro was used for plotting and fitting the electrical results, employing a Levenberg Marquardt iteration algorithm for fitting. It should be noted that most of these fits rely on the electric field and current density. This means that a precise understanding of the length, width, and height of the active region must be identified. Performing thin lamella analysis presented a strong understanding of the structures, but the dimensions extracted from the TEM images may not yield perfect values. Likewise, we do not know if the full Pt island films are contributing to conduction, or only portions of it, thus adding to the margin of error of fits. Ultimately, this means that we may use the extracted fit parameters to obtain a good understanding of the range but not a precise value corresponding with each device. Still, these parameters allow for drawing comparisons between samples. From this clear cross-section, we can begin to verify the fabrication of a single layer of islands atop the Al2O3 coated electrodes, and the successful filling of the gap. While the image appears to have multiple layers of islands, it is imperative to keep in mind the thickness and tilt of the sample with respect to the detector. In-situ, we could rotate the detection region enough to verify the monolayer nature of the layer but unfortunately, no one image could show a continuous single layer. The island sizes at 50 cycles were measured at roughly 2.4nm on average from a zoom of the image of Figure III.7. The gap here was not well controlled, and fell in a range of about 50nm, much longer than desired. Nonetheless, the sample provided reasonable two-terminal electrical results. We can also see a defect has appeared in the 1 st aluminum layer, seen as a large black region, most likely due to over-volting during measurements that occurred during the electrical characterization.

J = current

IV. Results

Planar Filled Gap

T (K)

A (m -1 .V - Four main mathematical conduction fits, discussed above, were applied over the Pt island I-V response. Schottky and Poole-Frenkel demonstrated the closest fits, with Poole-Frenkel displaying a marginally higher R-square fit. While at this stage the conduction is not strongly understood, fit parameters for the stronger Poole-Frenkel fit are shown in Table III.4 for later comparisons. The applied fit yielded a value of 60 for the dynamic permittivity and a combined A variable from which it is difficult to distinguish distinct physical properties. This promising first result proved that it was possible to use ALD to lay particles inside of a formed gap and that they, in turn, would increase conduction. Ultimately, however, it proved to be overly time consuming to optimize the proper balance of spacing between the electrodes, the thickness of the dielectric spacer, and the size of the islands. As such, we moved to alternative configurations.

Vertical Structures

Next, we turned to vertical structure configurations, which would afford a higher level of control, yielding the potential for more precise conduction studies. Mainly, vertical configurations allowed us to perform the same comparative study as that above in the planar filled gap configuration, with more easily measured and analyzed current levels. To begin these studies, measurements were conducted on each of the vertical capacitor structures we fabricated. In order to access the bottom electrode, the corners of each wafer were cleaved with a diamond tip and silver paste was applied, creating a direct contact path to the bottom electrode layer. These samples were introduced to the measurement chamber through the process described above, and probes were connected to both the circular top electrode and the silver paste connected bottom electrode. Measurements were conducted sweeping the voltage from zero up a safe limit in controlled steps while measuring the current at each probe. This process was performed at room temperature and repeated down to 100 K and back up to 280 K at even steps of 50 K. The resulting voltage vs. current measurements can be seen in Figure III.10. We can immediately see a clear separation between the conduction responses of the alumina reference and Pt nanoisland vertical structures. From here, we attempted to apply standard conduction fit analytical models to each curve to better understand the conduction change brought on by this multistack island inclusion. Fit Attempts & Fowler-Nordheim Again, multiple mathematical fits were applied to study the conduction properties of the Pt films. These fits can all be seen in Figure III.12, showing fits at both 280 K and 100 K. Across these fits, we can see a large cluster of fit responses, all closely resembling the obtained data. The large tail of data that is not fit can simply be attributed to the noise floor of the measurement setup in the configuration utilized at the time of measurement. However, it was not necessary to accommodate these noise floor values. The Levenberg Marquardt fitting algorithm applies more weight to higher values and more clustered results, which we find in the fitting region. While each of these mechanisms can be mathematically modeled with any of the main proposed fit models, according to literature FN tunneling is the main transport mechanism in MIM devices based on ALD grown Al2O3 [7][8][9][10][11] . We thus began a deeper investigation into the Fowler-Nordheim parameters that fit with each of the curves. The sharp and sudden increase seen from the alumina reference samples, seen isolated in Figure III.13, matched closely with the Fowler-Nordheim tunneling. In this transport mechanism, electrons characteristically tunnel directly through the imposed triangular energy barrier under high biasing. This result is quite fitting as we see 1) the need for a voltage to induce a current and 2) a sharp and sudden increase as the electrons gain enough energy to tunnel between Al electrodes through the alumina dielectric layer, as the model implies. From the measured data, seen in Table III.5, it was possible to create a closer fit by modifying the electric field variable to include a parasitic electric field parameter (Ep). We believe this is due to localized trap charges within the alumina, resulting from defects during the growth process, which marginally modulate the current response. This parasitic electric field contribution seems to carry a steep dependence on the temperature as we see half an order of magnitude difference between 280 and 100 K. This perhaps indicates that the nature of this parasitic electric field lies in thermally activated traps within the dielectric. We also see modulations of the energy barrier height and effective mass with the temperature, in line with the changes of the physical properties of the dielectric medium under temperature fluctuations. Looking at the next grouping of responses, seen isolated in Figure III.16, we find a close fit for each curve using the Poole-Frenkel bulk limited trap assisted hopping model. By rearranging the equation and grouping the unknownsthe mobility, the carrier concentration, and the barrier heightwe can extract an effective permittivity of this Al2O3/Pt nanoparticle matrix material. The resulting parameters are summarized in Table III. 6. From these parameters, we can see a trend emerging as the permittivity increases with the decrease in temperature. Two things here should be noted with regards to these extracted parameters. First, it is clear in this graph, and in all subsequent fitting curves, that while a standard Poole-Frenkel equation fits the data best, it does not fit perfectly over the whole range. What's more, later fitting results indicate the strong likelihood that a secondary mechanism is also present. These two points can introduce a large variability in the extracted parameter values which should be taken as general trends and perhaps not at face value. Taking a look at the A parameter which has been extracted from the fit results, we plotted its natural log as an Arrhenius plot following the equation 𝑙𝑛(𝐴) = -𝑞𝜙 𝐾 𝑏 𝑇 + 𝑙𝑛(𝜇𝑁 𝑐 ).

These results can be seen in

Figure III.17 -Natural logarithm ln(A) plotted as a function of the inverse of the absolute temperature 1/T. Parameters extracted from vertical Pt island structure

From this plot, we can extract the slope, giving us an energy barrier level of 50meV. This energy barrier level falls well below the 3eV presented by a typical Al2O3/Pt interface 9 . Again, while we cannot definitively use the extracted parameters as proof, the extracted value leads us to believe that conduction is largely occurring not across the Pt islands directly, but across intermittent trap levels. As stated previously, PF conduction occurs via thermionic excitation of the electrons as they move across intermittent energy levels existing below the conduction band. In this case, these intermittent energy levels must be a result of defects lying on the Pt island surfaces or throughout the dielectric medium resulting from their inclusion. Regardless of their nature, the inclusion of Pt islands in the alumina matrix has clearly increased the conduction.

Buried Island Structures

Moving on from the characterization of these vertical structures, we then shifted our gaze towards the buried island nanogap structures. While the island and dielectric growth parameters were identical, yielding equally sized and spaced particles, we predicted that the conduction path itself could vary as a result of the modified geometry. In a multistack island configuration, it was conceivable that current may not pass through all island layers. To verify this, both monolayer and multistack buried island configurations were built. It was necessary at this stage to confirm the full conduction of the electrons through the Pt islands in this planar configuration as these devices would later be used to build full transistors. In order to form and modulate a proper Coulomb Blockade for single electron operation, it is imperative to guide conduction through the islands. We employed the same measurement methods as before, connecting the two probes to the source and drain electrode lines and measuring the I-V response.

Buried Multistack Islands

First, we analyzed buried multistack island devices, whose island matrix is identical to that of the vertical structure. The first samples we tested were built with a bottom gate electrode, thus the gap between the electrodes on the surface of the island layers was left open and exposed. A second sample was later fabricated and studied with a top gate, whereby the gap was filled with alumina as described in the device fabrication section. Structural Characterization With new thin lamellas in hand from FIB lift-out, we eagerly performed TEM analysis. We were especially intent on verifying the size of the gap, the size and spacing of the Pt islands, and the study of any migration that may have occurred through the life of the samples. The STEM image of the sample formed at 60˚, shown in Figure III.18, confirmed not only the proper formation of the islands, but again reaffirmed the previous structural analysis of the formed electrodes and gap.

Figure III.18 -TEM cross-section image of the buried island multistack bottom gate structure after FIB lift out. Inset shows zoom on islands for measurement, area indicated by red box

From this analysis, we were able to verify the formation of five distinct layers of islands, each separated by a roughly measurable 2.4nm dielectric spacer. Although these thin lamellas did not provide higher resolution images of the islands due to the thickness of the sample, the islands can still be measured to be roughly 2.6nm in diameter on average. This finding is in keeping with the previous island growth studies and seems to indicate an average of 2.5nm diameter islands at 50 cycles, falling in line with the 1.8 and 2.7nm averages found at 45 cycles in chapter 2. The most important detail however, is that these islands are identical to those of the vertical structures as they were all formed at the same time, allowing for a direct comparison. We can measure a gap of 30nm, and again find the same shadow edge evaporation geometry we have grown to expect.

We also performed chemical mapping to ensure no molecular migration occurred into either the gap or the island layers. This chemical mapping, seen in Figure III.19, perfectly showed the structural integrity of this device. We find distinct layers of Ti and Pd coming from the electrodes, and Pt, coming from the multistack of particles.

The 45° sample from the same Batch was also sent away for investigation, allowing us to verify the gap size distribution and their relation to the angles introduced by the angled supports. Of note, nearly all device on this sample were electrically shorted, increasing our curiosity at what this thin lamella would reveal.

Figure III.19 -EDX chemical mapping taken on the buried island multistack bottom gate structure after FIB lift out Figure III.20 -EDX spectrum of region shown in inlay verifying the sole presence of desired materials

An EDX spectrum with an inset of the STEM image can be seen in Figure III.20. From these images, we can easily identify the same structural makeup as the 45˚ sample. The gap here was measured to be 15nm, with the same five islands layers easily identifiable. Interestingly, no matter how the sample was tilted, we could find no visual evidence of a metallic contact between the two electrodes. We concluded that across the width of a 2μm-100μm electrode, there must have existed small defects in the gap, causing the short circuit characteristics that were not present in this section. We performed a broad EDX mapping over the whole sample to identify the materials, verifying that no other chemical contaminants were found. We identified strong signals from C, Pt, Ti, Cu, Al, and Si. The carbon and copper found are from the grid and sample holder of the TEM, while the rest are from the electrodes and conductive Pt layer. We performed chemical mapping of the gap itself at both low and high resolution to make sure that with this reduced spacing, no Ti or Pd had leached into the gap from the electrodes, seen in Figure III.21.

Figure III.21 -EDX spectra taken soley across the gap at both low and high magnification

This mapping was the first hint that some undesired material might exist within the gap. In the image on the left, Ti and Pd peaks can be seen as the spectrum sweeps from the Pt particles into the gap. This signal could indicate an improper electrode deposition that has left Ti and Pd in the gap. However, the resolution limit of this EDX setup could well be pulling signal from the nearby electrodes, thus it is not possible to draw any conclusions. The second, higher resolution spectrum shows a much more dominant Pt signal but small speak of Al, Ti, and Pd are all visible with the onset of a brighter material within the gap.

Electrical Results

Figure Again unfortunately, the resolution afforded does not allow for further conclusions on the makeup of the gap. Having largely confirmed the integrity of these buried multistack structures, we moved to probe them to fill out our understanding of the active Pt layers.

The electrical results, seen in Figure III.22, show a very familiar Poole-Frenkel fit across the applied temperature range. These PF fits closely resemble those of the vertical Pt nanoisland structures, with the results summarized in Table III With these samples containing islands of equal size to those of the vertical structures, we can directly compare the conductive properties between the two. Analyzing the two extracted parameters, we see that while elevated, the A term is within a few orders of magnitude as those extracted before. The dynamic permittivity however, sees a swing, reducing and then increasing again as the temperature is reduced. It should be noted again that the parameters extracted through these mathematical models may not correctly represent reality due to dependencies between the parameters. That said these parameters provided the closest fit possible to the data. We were not able to find similar studies in literature. Performing the same Arrhenius plot as before, shown in Figure III.23, we were able to extract a barrier height of 93meV, in the same range as the vertical Pt island structure.

Figure III.23 -Natural logarithm ln(A) plotted as a function of the inverse of the absolute temperature 1/T. Parameters extracted from buried island multi-stack device with 50 cycle 2.6nm islands

Effect of Changing Geometry

Figure III.24 -Current density vs. electric field comparison between vertical and buried multistack island structures. Both devices made with 5 identical stacks of 2.6nm islands

Normalizing the data extracted from the measurements, we compared the current density vs. electric field values of the planar and vertical Pt island structures. Looking at Figure III.24, we see an increase in the current density of 10,000 times at an equivalent electric field of 5E+7 V/m at 100 K thanks to the multistack configuration. This is an interesting discovery as from a geometric perspective, only considering the platinum islands as the conductive contributions, we should find a very similar inter-particle spacing between configurations. The planar spacing between the islands depends heavily on the number of cycles utilized, but ranges between 2-4 nm. The vertical spacing is fixed to 2.4nm as a result of the control over the ALD grown alumina. Considering the conductive path of least resistance, it is conceivable that the overall path of electrons would be similar. Thus, finding such a large difference begins to reveal the material makeup of the films. Comparing the two configurations, the extracted permittivity values fall within the same range, as do the extracted trap energy levels. We do however, see a 4 order of magnitude increase of the A term at 100 K from vertical to buried orientations. As the extracted trap barrier heights can be considered equivalent at this magnitude, we believe this drastic difference must stem from a change in the carrier mobility.

We believe this large difference between the two configurations to be a result of the assumed defect trap conduction predicted through the reported fitting results. Although we cannot resolve the specific shapes of the islands via the characterization techniques available, it is conceivable that they are forming as domes on the surface of each alumina layer, and not perfect spheres. We also predict that the defects present in the film are formed surrounding the Pt particles. More specifically, as Pt islands start to form on the top surface of each alumina interlayer during PEALD cycles, some partially formed islands could create trap sites before full islands formation. As the ALD grown dielectric thin films are built, they form defects surrounding the Pt islands, but quickly begin to form pure Al2O3 layers as the ALD cycles increase towards the total 24 cycles. This creates a film where defects are more closely located in a planar geometry, while vertically we find defect free spacing between island layers. A diagram of this behavior has been given in Figure III.25. Thus, in a purely vertical configuration, the electrons must traverse these pure alumina barriers, drastically decreasing the electron mobility, while in a planar directions, the electrons are able to hop from trap to trap more easily.

Effect of Filling Gap with Alumina

Figure III.26 -HRTEM image of 50 cycle Pt islands below electrode layer

New samples were built using the same exact process, and a top gate oxide and gate electrode were added. Unfortunately, the only thin lamella prepared from this group was that of one prepared at 45˚, which resulted in a gap of nearly 60nm. While unsuitable for measurements, a HRTEM image of the island layer, seen in Figure III.26, at least gives information on the island sizes, which were found to be ~2.3nm on average. The 30˚ shadow angle device that was chosen for direct electrical comparison does not have accompanying TEM images, however based on the current response we assumed the gap length to be 20nm for the sake of fitting, based on the observed current density. The measured electrical responses, seen in Figure III.27, revealed new information.

As hoped, after filling the gap with alumina we find similar looking Poole-Frenkel curves with fit parameters roughly in line with those before, as seen in Table III.8. It should be repeated that we do not know the precise morphological measurements of this device. The parameters extracted here give only a very rough range of the physical properties, but inputting different gap lengths within the same range have no effect on the shape of the fit curve itself. We do however see one new addition. At 100 K, at lower voltages below 0.2V, the response has deviated slightly from Poole-Frenkel.

Figure III.27 -I-V response of buried multistack island structure with 50 cycle Pt nanoislands with a top gate. Nanoparticle diameter = 2.3nm Table III.8 -Fit parameters corresponding to Figure III.27 T (K)

A (m -1 .V - We have formed two main hypotheses for the origin of this deviation. The first possibility is that this deviation stems simply from a resistance that has been added in series and which is more pronounced at lower temperatures due to the lower mobility. This is supported by the fact that the measured curve falls below that of the model. This resistance could very well originate from a contact issue between the contact pads and the probe tip. Contact issues had already been encountered at low temperatures, with mechanical scratching required to form a solid connection. The presence of the gate oxide covering the contact pads compounded these issues, especially at low temperatures. Etching steps were employed to remove this gate oxide from the contacts, but it is plausible that these etching steps were not sufficient, or that the low temperature alone affected the results. The second possibility is that a second transport mechanism is present and is masked by Poole-Frenkel at higher applied bias. In these new samples, the islands resulting from 50 PEALD cycles could be smaller than the previous sample. In this case, the smaller island size could affect the Poole-Frenkel response. This theory is reinforced in the next section below when analyzing samples formed with smaller 1.8nm islands. This second transport mechanism believed to be the source as the measured current response is slightly elevated from that of the PF model at higher temperatures. The move to 100 K possibly results in the beginning formations of Coulomb blockades on the PF transport while this ulterior mechanism continues to function. We could not find any references to Poole-Frenkel being blocked in literature, but it is possible that the trap site pathways seen in Poole-Frenkel could form Coulomb blockades as well under the right conditions. This would explain the reduced current response seen at this lower temperature. If Coulomb blockades truly are blocking Poole-Frenkel conduction and revealing a secondary conduction mechanism, said mechanism must be resistant to Coulomb blockades. Cotunneling presents itself as an obvious candidate as it is not blocked by standard Coulomb blockades, and can still be observed when classic Coulomb blockades are formed 12 .

Having verified the acceptable inclusion of a top gate and with the intent of working towards optimal SET structures, full transistor structures were fabricated and studied with smaller island sizes. The scaling of the island sizes should permit for higher operating Coulomb blockade temperatures.

Deviation from Poole-Frenkel with Reduced Island Size 3.1.2.1.

Structural Characterization . These islands were measured at ~1.8nm in diameter on average, falling in line with the 1.7nm average found for 30 cycle Pt islands built on TEM grids seen in chapter 2. Turning back to the formed gap, we find a spacing of 30nm for the 45˚ sample and 70nm for the 60˚ sample. This time however, an apparent line of material inside of the gap presented itself, leading us to question the makeup of the conductive layer. These devices were not electrically shorted, as this seemingly solid form inside of the gap would indicate.

Figure III.31 -EDX mapping of 30 cycle, 45˚ buried multistack structure. Inset shows this mapping overlaid on the TEM image, rotated by 90˚

We thus turned to EDX to perform a deeper chemical analysis, shown in Figure III.31. While the resulting EDX spectrums again verified the structural integrity and purity of the selected fabrication methods, it could not resolve the material in the gap. Due to the small size of the islands, a slight drift during acquisition was enough to hinder proper analysis in the gap region. To add to this, the signal from the Pt layers was so low that it became difficult to distinguish between material signals and noise.

Figure III.32 -STEM image of 45˚ gap, with sample tilted to reveal gap. Image is rotated 90˚ from that seen above

Tilting the sample to take a deeper look at the makeup of material within the gap revealed the nature of this line. From the tilted image in Figure III. 32 we can clearly see that this apparent short of the electrodes is in fact a visual artifact and the line is not continuous. The largest of these surface clusters was measured at 4nm, with the average at about 2nm, however with this skewed perspective the measurements may not be perfectly accurate. The source of these clusters must still be studied, but several initial theories were made. The first theory, while promising, was later proven wrong. We first theorized that as the number of Pt island layers increased, the roughness of the top exposed layer would also increase due to these buried islands. Thus, when depositing the 5 th and final layer of islands, it was conceivable that this uneven surface would present lower energy nucleation sites that would lead to the formation of aggregates instead of dispersed islands. Unfortunately, this theory does not hold as this same line of aggregates is seen later in the monolayer sample as well. Next, if these aggregates are not formed during ALD deposition, they must be a result of the electrode fabrication. They could be the result of the top most particles aggregating, underneath the thin alumina protective layer, during oxygen plasma, photoresist development, or metallic lift-off. It is also possible that any of these processes are stripping or etching away the top layer of alumina, and the exposed Pt particles are aggregating thereafter. It was also theorized that electromigration of Pt or Ti/Pd from the electrodes had occurred on this sample under high enough biasing as this sample was prepared after electrical testing. The final theory is that these aggregates are not Pt at all, but in fact are Ti or Pd that has been improperly deposited during the shadowed evaporation.

Electrical Results

With these new smaller islands, we found results resembling the previously measured buried island samples. Following the TEM findings, we were spurned on to attempt two new fits alongside Poole-Frenkel: variable range hopping and cotunneling.

With the mask shown above in Figure III.4, 30 nanogaps could be fabricated, all branching from the same main electrode line. This allowed us to measure numerous responses of ideally identical devices to test for reproducibility. After measuring across 26 of these devices, the most stable results were compiled and can be seen below in Figure III.33. While each of these curves falls within the same general range, they each vary in current response levels. The thin lamella observation presented above was performed on device 6, whose response falls right in the middle of those measured. It is possible that the observed gap is not representative of the other measured devices. While the nominal size of the gap should be consistent, as indicated by the fact that each different thin lamella sample holds nearly the same gap size when fabricated at the same angle, any sudden outcrop of the electrode within the gap would change the applied electric field. It is also possible that the arrangement of islands under each of the gaps is varying, by virtue of the randomness of their dispersion. More likely, this dispersion stems from the aggregates found in each gap as they have been seen to be randomly dispersed throughout the gap area. Either of these views is slightly reinforced by the fact that devices 10, 16, 21, and 23 produced similar results while 6 and 19 were likewise similar. More work will need to be performed to study the similarity between each formed gap on a line. A full temperature sweep was performed on device 26, measuring Ids vs. Vds I-V responses as before. III.9. However, following the improperly fit curves from the previous samples, we begin to see a more pronounced departure from Poole-Frenkel transport that must be noted. While the Poole-Frenkel model fits these curves overall, we can now see that at low applied electric fields, the responses are not fit by Poole-Frenkel at all. Here, the hypotheses made during analysis of the previous samples should be revisited. In the previous fits in Figure III.27 it was proposed that a second conduction mechanism may be present but masked at higher voltages. These new responses reinforce the previous arguments as these responses clearly show a higher current response at 150-300K and a lower current response at low temperatures. We attempted new Poole-Frenkel fits over this shorter voltage range with the results seen in the same figure and table. Over this shorter voltage range, the Poole-Frenkel model was able to conform strongly to the measured responses over the whole temperature range perhaps indicating two separate Poole-Frenkel transport paths. Measurements were also taken with a negatively applied Vds bias, as shown in Figure III. 35. In order to perform fitting, absolute values of the responses were required, and these absolute values have been shown here to facilitate direct comparison with the positive bias response above. The overall higher current response for the same electric field indicates some small level of asymmetry, perhaps reinforcing the hypothesis of an asymmetric distribution of islands within the gap. That said, Poole-Frenkel still presents a very strong fit, with the curves very much carrying the same shape as the positive bias side. The extracted parameters, seen in Table III.10, also fall in line with previous results. Finally, we again see a nonconformity with Poole-Frenkel over the low voltage range from 0-0.4V. Looking to gain clarity on the barrier heights, we performed the same linear fit over the A variable, shown in Figure III.36. It is immediately apparent that the data points are not linear, so the extracted 30meV energy barrier level extracted from the slope should be used only as a general guideline and should be taken with a very large grain of salt.

Figure III.36 -Natural logarithm ln(A) plotted as a function of the inverse of the absolute temperature 1/T. Parameters extracted from buried multi-stack with 1.8nm 30 cycle islands

Of particular interest here, although we were able to apply well-fitting Poole-Frenkel fits over a low range of the curves as before, the resulting lower voltage range fit parameters seen in Table III.9 make little sense. The lower voltage range fit, found to be in strong agreement with the raw data, resulted in absurd permittivity values above 4500. While these parameters should not be taken as precise physical properties due to the nature of the fit models, this ultimately points towards a likelihood that another transport mechanism is responsible. If these measurements truly indicate competing mechanisms, the fact that the responses at 100K and 77K fall well below that of the Poole-Frenkel model again suggests the possibility of forming Coulomb blockades in Poole-Frenkel conduction. With the shift to smaller islands facilitating eased Coulomb blockade formation, this second transport mechanism theory makes sense. Thus, we Variable Range Hopping In a work from Bayle et al., planar devices were built with buried silver nanoparticles. Through their characterization, they were able to identify the presence of variable range hopping and perform analysis determining if their response was Arrhenius or Efros-Shklovskii in nature 4 . Having a very similar structure, we attempted to apply variable range hopping fits across these measurements. The results of these fits can be seen in Figure III.37 where we extracted resistance values taken at a low voltage of 0.1V. Fits were attempted with values extracted at both 0.02V and 0.5V as well with mirrored results. We attempted fits with gamma fixed to 0.5, 1, and set to a free range but could never reach a proper fit. We see a much stronger fit from just 150 to 300 K, but with only three data points, these findings are inconclusive. It is possible that VRH is competing with Poole-Frenkel conduction at higher temperatures, causing the deviation from straight Poole-Frenkel, but this deviation is more pronounced at lower temperatures. VRH is primarily attributed to disordered nanoparticle films 4,5,13 , and thus further studies on these PEALD formed particles may be necessary to determine further size and distribution statistics.

Figure III.37 -Variable range hopping fit results across the whole range and from 150-300 K Cotunneling

Again, turning to the literature, an article from Tran et al. presented cotunneling findings on arrays of 5nm gold nanoparticles in both vertical and planar configurations 6 . They found that within their monolayer and multistack gold nanoparticle configurations, inelastic cotunneling dominates is overtaken by sequential tunneling at biases larger than the Coulomb blockade threshold voltage. The full equation, presented above, was not able to conform to the data we obtained. By applying a simplified fit following:

𝐼 = 𝐴 * (𝑉 𝐵 ) * (1 + 𝐶 𝑉 2 )
we were able to fit across the lower, nonconforming voltage range from 0-0.4V. The graph is reshown below along with the new fits in that in Table III.11. Both the B and C parameters can be used to extract a value j, the number of tunneling junctions traversed across the gap using the equations

𝐵 = 2𝑗 -1 𝐶 = 𝑗 2 (𝑗 -1) ( 𝑘 𝐵 𝑇 𝑒 ) 2
A summary of these values can be seen in Table III.12. The B parameter yields a value of ~2 junctions.

Considering the length of the formed gap and the size and spacing of the underlying particles, this should not be possible and a value closer to 5 or 6 might be expected. However, looking at the tilted STEM images revealed larger particles within the gap, thus it is possible that fewer tunneling junctions would be required to traverse the gap. Switching to the C parameter muddles things more, finding an average value of ~7. This value falls much more in line with the number of series islands found buried inside the gap. In the original equation, the j term is shared between these B and C parameters and should be consistent. This mismatch of extracted terms indicates why the original function would not fit over the measured data points. As Poole-Frenkel appears to be the dominant transport mechanism acting in parallel, it is likely that this cotunneling model is too simplistic and thus provides inaccurate parameter values. Nonetheless, the two extracted tunneling junction values seem to fall in line with possibilities in this system. Much further work should be performed to gain a better understanding of this second possible mechanism, but cotunneling poses as a possible candidate.

3.1.2.3.

Effect of Changing Gap Length: 70nm Gap We then measured the electrical response of the larger 70nm gap devices from the same series, formed at 60˚, and applied another Poole-Frenkel fit, seen below in Figure III.39 and Table III.13.

Figure III.39 -I-V response of buried multistack island structure with 70nm gap with PF fits (green) across whole range (blue) from 0-5V Table III.13 -Fit parameters corresponding to Figure III.39 T (K)

A (m -1 .V -1 .s -1 ) εi 300 3.5E+12 88 Now a direct comparison in the variation in gap size can be drawn. The transport mechanism seems to have changed very little with the two-fold increase to the gap. We find a decrease to the current response as the measured current at 1V has dropped by an order of magnitude, certainly from the increased Pt island conduction path. The permittivity is found to be within the same range as before, and we find a similar nonconformity to Poole-Frenkel fitting, thus indicating that over longer gap distances, conduction should still be flowing through the same path as the smaller gap device. This demonstrates evidence that through these measurements we are probing the gap itself.

3.1.2.4.

Effect of reducing island sizes Building off the working theory that intermittent defects in the alumina, from Pt ALD, result in Poole-Frenkel causing trap levels, we can begin to draw conclusions about these smaller island measurements. Looking at the extracted PF fit parameters, permittivity levels fall within the same level of the 50 cycle multistack buried island structure, however the A term has fallen a few orders of magnitude. Again, we attribute this drop to the electron mobility as the, albeit simply, extracted barrier height falls within the same range as before. The hypothesis here is that the reduced Pt deposition cycles results in a lower trap surface density, thus reducing the electron mobility, and subsequently the PF response. This reduced PF conduction more readily reveals another transport mechanism at low voltage and low temperature. We do not yet have enough information on these films to conclude on this transport mechanic, but cotunneling could be a candidate. There may also be a contribution from these larger surface clusters seen via STEM, but further fabrication work will need to be performed to determine the validity of this claim.

Buried Monolayer Islands Structural Characterization

Right from the get-go, we can determine that the nanogap process has yielded identically spaced electrodes allowing us to compare this structure directly to the previous multistack island structures. Moving to this 30 cycle Pt island monolayer structure, we stumbled upon an interesting result that initially puzzled us. Not only did we not find a clear buried monolayer of Pt islands underneath the electrodes, we again found what appeared to be a line of unknown material inside of the gap, seen in Figure III.40. Although we cannot measure the islands, as they were fabricated immediately following the multistack 30 cycle structures, it is believed that the islands are of the same size. At an assumed size of just 1.8nm, it is probable that a single monolayer would not create a contrast high enough to resolve with this equipment. Again, while the EDX spectra confirmed the presence of Al, Ti, Pd, Pt, Si, and O, we were still unable to resolve the nature of the material within the gap. The measured responses presented below indicate an identical conduction mechanism. It was therefore concluded that Pt islands in some form must still be present. Going back to the hypotheses surrounding these aggregates, these findings on a monolayer device rule out the possibility of surface roughness creating aggregation sites during PEALD deposition. It was still not possible to rule out electromigration, aggregation of Pt during the lithography process, or improper electrode deposition. While the previous results deviating from Poole-Frenkel showed a higher current response than that of the model at higher temperatures, this device provided a response well below the standard PF model across all temperatures. These results point more towards the existence of a series resistance, likely from the contacts themselves. However, the presence of secondary transport mechanisms cannot yet be ruled out, as they may still exist, masked under the combination of the assumed PF conduction and contact resistance. Poole-Frenkel fits were applied over a lower voltage range as well as cotunneling. The former can be seen on the right in Looking first at the fit results of Poole-Frenkel, shown in Table III.14, we can also see a large temperature dependence of the dielectric permittivity, with this value increasing as the temperature was reduced. Again, we begin to reach abnormal dielectric permittivity values for the overall fit, further leading us to believe that we have another unidentified transport mechanism at play, skewing these fit results.

Figure III.41 -I-V response of buried monolayer island structure with 30nm gap with PF fits (left) across whole curve (right) from 0-1V Table III.14 -Fit parameters corresponding to Figure III.41 across both (left) full range and (right) 0-1V T (K)

A (m -1 .V -1 .s -1 ) εi T (K) A (m -1 .V - identical. There is still an issue fitting with the original model, with a mismatch found between the B and C terms, which we believe due to interference from Poole-Frenkel.

T (K)

A (m -1 .V -1 .s -1 ) εi 300

3.8E+12 110

Moving to the larger 70nm gap device, formed at 60˚ in the same series, we find results reinforcing those found from the previous gap increase. The measured response and corresponding parameters can be seen in Figure III.43 and Table III. 16. The fitting parameters fall in line with those found before, and again we find that the PF fit conforms quite well, but we still see a discrepancy in the fitting parameters when changing the fitting range down to 0-4V. Overall, comparing the monolayer devices to the multistack devices yields an interesting conclusion. The 5 fold reduction in parallel islands has had almost no effect on the apparent transport mechanism seen, with very similar results being found compared to the multistack samples above. The only major change seen is a reduction in the current response from the reduction in parallel pathways. It thus becomes apparent that electrons must be traveling through several layers of islands within the multistack structures, and not just through the top conductive layer. Most importantly, this means that while the unknown aggregates seen in the gaps of all structures may still play a role in the transport properties, it is not the dominant cause. Ultimately, we can conclude that not only are we probing the gap itself, we are probing the island layers within the gap.

V. Conclusion

Through this chapter, full Pt nanoisland devices were built from several optimized fabrication techniques. To begin, filled gap monolayer structures were also built, in the pursuit of obtaining transport through a single layer of parallel islands. This configuration however proved too difficult to optimize with the provided setup, and other structures were pursued to probe the Pt islands. Vertical structures both with and without islands were built to analyze the change in conduction brought on by the introduction of the islands in the most readily controllable and adaptable configuration. These vertical structures clearly demonstrated the electrical enhancement brought on by the inclusion of PEALD Pt islands and through transport mechanism fitting revealed a clear transition from Fowler-Nordheim to Poole-Frenkel transport thanks to these islands. This switch to Poole-Frenkel indicates the addition of traps within the alumina layer while incorporating Pt islands.

Next, buried island multistack structures and buried island monolayer structures were fabricated, resulting in more easily tunable structures with readily integrated gate, source, and drain electrodes. Each of these structures was all analyzed for the changes each configuration would bring to the electron transport. As the buried island devices proved to be the most efficiently optimized, we further studied these structures through both gap size and the island size variations. By performing FIB lift out, we were able to produce thin lamellas that opened up new observational opportunities versus the previous combination of cleaving, ion milling, and SEM. Through this technique, we were able to morphologically validate the following successful fabrication optimizations:  ALD formation of Al2O3 dielectric spacers for the islands  PEALD formation of distinctly separate Pt islands in multistack configurations  Shadow edge evaporation formation of tunable nanogap electrodes formed from Ti sticking layers and Pd electrode layers  The formation of a gate dielectric barrier via ALD and top gate made of Ti/Pd.

The proper chemical makeup of each of these layers was confirmed through EDX, and displayed the purity of these chosen fabrication techniques. Many STEM images appeared to show aggregates within the formed gaps of several samples. Performing STEM imaging at an angle verified that these aggregates did not form a continuous connection between the electrodes, but the EDX measurements performed herein were not able to identify the nature of these aggregates.

Looking over the results from each device family, the overarching conclusion seems to be that Poole-Frenkel conduction has been introduced by the ALD formed Pt nano-islands, but it appears that some variables are skewing the measured responses from the classic Poole-Frenkel model. We believe these variables to have to have two sources:  A resistance, added in series, between the measurement probe and the contact pad that is exacerbated under lower temperatures.  An ulterior, weak, masked conduction mechanism hiding behind the dominant Poole-Frenkel conduction.

In fact, looking back over the result of adding Pt nanoparticles into the mix, it is a bit striking to find the Poole-Frenkel mechanism dominating given the high-energy barriers between the Pt/Al2O3 interfaces. Poole-Frenkel conduction results from thermionic excitation providing sufficient energy to electrons to allow them to hop over the imposing energy barriers within the dielectric matrix. In this case, if the conduction path truly flows through the Pt nanoparticles, it must mean that the thermal energy of the surrounding environment, even at 77 K, is sufficient to boost the electrons over the Pt/Al2O3 energy barrier. This case seems highly unlikely, leading us to conclude that perhaps unseen defects exist along the circumference of the nanoparticles, or that their inclusion has caused defects to form within the alumina matrix during its own growth. These deviations from Poole-Frenkel are much more present when smaller island sizes are introduced. These findings reinforce the hypothesis that unseen defects may exist on the surface or surrounding the Pt particles. We hypothesize that with such small islands, in such a configuration, electrons under bias are hopping between both defect traps and Pt islands, yielding two cumulative currents. At low electric fields and low temperatures, Poole-Frenkel conduction is reduced below levels predicted by its model, revealing this secondary mechanism. We hypothesize that the reduction of Poole-Frenkel at low temperatures results from Coulomb blockades forming over these trap sites while this secondary mechanism is still able to traverse the gap. While cotunneling fits did not readily present conclusive results, we postulate that cotunneling is working alongside trap assisted Poole-Frenkel. Modifying both the length of the gap and the number of parallel islands verified that electrons are predominantly traveling through the island matrix. It will be interesting to study the behavior of these smaller island sizes under gating, to see how conduction is modulated, and if it is possible to clearly form Coulomb blockades. Although each of the devices' responses were similar in nature, the buried multistack structures with gaps at 30nm proved to be the best suited for obtaining easily measurable current levels at low applied voltages. These devices will be studied in the next section on three terminal gating responses.

CHAPTER 4 Three-Terminal Platinum Nanoparticle Transistor Device

Fabrication and Characterization

I. Introduction

Thus far, ALD has been shown to be an excellent technique for both creating highly uniform Pt nanoparticles encapsulated in alumina. Monolayer and multistack island configurations were fabricated in a single ALD process and the shadow edge evaporation technique was used to build nanogap electrodes atop these island layers. The transport properties of these devices were probed concluding that Poole-Frenkel and another unidentified mechanism were in competition. TEM was performed on thin lamellas to verify the fabrication process and while each of the electrodes and island layers were confirmed, aggregates of an unknown source were found inside of the gap.

In this final chapter, the best devices were selected for further analysis. Additional TEM was performed, utilizing tomography to build 3D reconstructions of the aggregates in the gap. Full three-terminal electrical characterization was also performed, further probing these island layers via gating while looking for the telltale current response oscillations that accompany Coulomb blockades.

II. Completing the Transistors: Gate Fabrication and Device Preparation

To begin, in summary of the fabrication section, we built monolayer and multistack buried island structures comprising Pt nano-islands, each separated laterally by 2-4nm depending on island size and placement, and vertically by exactly 2.5nm of Al2O3. A recollection of such a device is shown in Figure IV.1, from the previous chapter. This block diagram shows both a top gate and a bottom gate, each of which were tested for transistor operation. Nanogap electrodes with spacing defined by the deposition angle were built on top of these island arrays.

Figure IV.1 -Block diagram of a transistor device tested herein with both a top gate and bottom gate electrode. Islands were made using 30 cycles of ALD forming 1.8nm diameter islands

These electrodes ranged in width from 2µm to 16µm. As an example, a monolayer device with a 2µm width and a 30nm gap would have roughly 6 islands in series and 600 islands in parallel. Adding in the 4 additional island layers seen in the multistack structures extends this to roughly 3000 parallel islands. A full wafer Ti/Pd bottom gate, separated by a 50nm alumina dielectric barrier, was used as a base substrate for device fabrication, as reported in chapter 2. This bottom gate configuration was tested on both multistack buried island and filled planar gap devices, but to no avail. Even to the point of dielectric breakdown, no gating effect was ever observed. We believe this is a result of several factors. First, the fact that the bottom gate spanned the entire surface of the substrate meant that any applied gating necessarily formed very large capacitor structures, matching the size of the grounded electrodes in question. In this case, the largest electrode was 1.5cm x 0.5cm with a dielectric spacing of roughly 70nm. If we consider the basic permittivity of alumina of 8 1,2 , we arrive at a gate capacitance of 76nF using the parallel plate approximation equation 3,4 𝐶 = 𝜀 𝑟 𝜀 0 𝐴 𝐷 , quite high for such a device. To add to this, as these overlapping surfaces were so large, there existed a higher chance of defects existing in the dielectric layer of the formed capacitors, increasing the likelihood for dielectric breakdown at low voltages. In fact, on many devices, we measured a direct short circuit between the bottom electrode and the large electrode line.

After this minor setback, we went back to the drawing board, fabricated top gate samples and attempted to gate the samples again, looking for modulations in current response. These new patterned gate electrodes were fabricated by depositing an ALD grown 20nm alumina dielectric barrier and using UV lithography and e-beam evaporation to deposit Ti/Pd gate electrodes of 5/20nm respectively. The combined mask pattern used can be seen in Figure IV.2 with each color indicating a different mask layer. The blue layer was used to form the source and drain electrodes with a nanogap at their overlap. The green layer was used to form the gate electrode, which used an extended electrode line to reduce the amount of area overlapping the source/drain electrodes. Finally, the purple layer was used to etch away the gate dielectric to free the contact pads. The full steps and processes for each of these fabrication steps can be seen in chapter 3. The metal gate itself measured 14μm x 15μm and formed an overall overlap gate capacitance of only 0.7pF. Once the final wafer was fabricated and placed on the same measurement bench, a third probe, also connected to an amplifier on the Keithley-4200, was placed atop the new gate electrode in the same manner as before: placing it in contact and dragging it across the electrode surface until a stable measurement was attainable. Samples were again submitted to the same preparation: they were placed under vacuum and heated at 400K for one hour, to remove any potential moisture from the chamber, before introducing liquid nitrogen to bring the ambient temperature down to 77K.

Figure IV.2 -Transistor UV lithography mask pattern showing parts in blue) source/drain electrodes green) gate electrode purple) etching for electrode contacts. Right shows a zoom on the location of the nanogap and gate electrode itself

Two families of devices will be tested and presented herein, originating from samples fabricated and tested in Chapter 3. These devices have been summarized in Table IV.1. The first family consists of buried multistack devices such as that shown in Figure IV.1. From this family of devices, electrodes with a 30nm gap length and 2μm width, a 30nm gap length a 4μm width, and a 70nm gap with a 2μm width are compared. These are then compared to a buried monolayer device with a standard 30nm, 2μm gap. The characterization methods used to analyze each of these samples is presented below.

III. Transistor Device Characterization 1. Transmission Electron Microscope Tomography

Building from the TEM analysis performed and presented in the previous chapter, full electron tomography was performed to have a full view of the three electrodes, formed gap, and island layers. The same FEI Titan ETEM G2 80-300kV was utilized with thin lamellas likewise prepared by FIB. Tomography was performed on an unstressed gap from the buried multistack, 1.8nm 30 Pt cycle device. A conscious decision was made to choose an unstressed, unmeasured gap, as a means of determining if the apparent Pt aggregates were created under heavy electrical stress, or existed from the fabrication process itself. To perform this tilted analysis, a thin lamella was prepared, as previously discussed, and was coated in drop cast colloidal Au nanoparticles before being loaded in a double-tilt TEM holder, capable of turning on both X and Y axes. The sample was magnified to 450kx and images were captured from -70˚ to 70˚ in steps of 2˚. These images were later reconstructed, using the highly contrasted Au nanoparticles as reference points, to create a 3D image of the device and gap.

Three Terminal Electrical Measurements

In order to find the voltage limitations of the gate dielectric, we applied a voltage between the gate and the large mainline source electrode, sweeping first from 0V to -10V, and then from 0V to 10V, stopping once the current began to rise above the noise threshold of the amplifiers. Figure IV.3 shows an example response with a stable current up to 5.5V, with a slight hysteresis due to quick measurement steps. This current response corresponded to a tunneling current passing directly through the alumina gate dielectric, unsurprisingly exhibiting the same Fowler-Nordheim current response we saw before from the stacked reference samples. Although each device responded differently depending on the local stability of the alumina layer sitting atop the gap, the voltage range typically fell between -6V to 4.5V. Finding this range was critical, as any contributions to the overall measured current response, originating from the gate electrode, would immediately affect the results. As the Fowler-Nordheim current observed from this leakage current is marked by a sudden activation of high tunneling current at a sufficiently high voltage, as seen previously, the effect on the measured Ids current was also sudden and high. For each sample, presented in the next section, once the proper gating range had been found, a constant voltage was applied across the source and drain electrodes. The gate voltage was then swept across the determined stable range, for example the average range starting from -6V, going up to 4.5V, and returning back to -6V. This dual-sweep was employed each time to ensure that any modulations observed were stable but also to rule out the possibility of noise or transient currents playing a large role. To create transconductance mappings, a measurement script was set up on the Keithley that would perform a Vgs sweep for several Vds values which were swept from -300mV to 300mV in steps of 50mV. From these data sets, the transconductance, dI/dV was calculated and mapped vs. Vds and Vgs. These transconductance mappings give an idea of the full operating ranges of the devices. As with the previous two-terminal measurements, obtaining a stable contact between the probe tips and the metallic electrode contact pads proved difficult at low temperatures. At 77 K, the probe tips would often lose contact with the contact pads, thus leading the measured current to drop suddenly, and it was necessary to scratch the surface of the contact pad numerous times to remedy this. This lead to an environment where many devices would not function, or were damaged during the measurement process creating low result yields for a given sample. We strategically chose to perform tomography analysis on a fresh nanogap electrode from the buried island multistack structure, fabricated with 1.8nm islands and a 30nm gap. This sample, formed at a shadowing angle of 45˚, can be seen in Figure IV.4a. A thin lamella was prepared using FIB and direct STEM observation and tomography was performed. A fresh nanogap was chosen for two reasons. The first, a history of the devices could be built by comparing this device to the twin device thin lamella from Chapter 3. That sample, shown again in Figure IV.4b, originated from the same main electrode line, ideally forming an identical gap. As a refresh, the thin lamella shown in image b was created after electrical testing. Therefore, by comparing the two thin lamellas we could easily determine the following: first, nanogaps formed across the same mainline are largely reproducible, resulting in almost identical geometries. Second, electrical stressing does not appear to have had any effect, eliminating the possibility of electromigration occurring on a measurable scale. Third, the aggregate material seen inside the gap exists across multiple samples. As to clues of what the material makeup is, the observed contrast points to the likelihood that it originates from Pd incorrectly deposited during electrode formation. All of the Ti in the image has oxidized due to the thin nature of these lamellas and appears dark. The only other candidate would be Pt, which in its smaller nanoparticle form presents a seemingly darker contrast. These observations however are not enough to definitively determine the material or its origins. Tomography was performed on the device seen in 'image a' in order to extract additional information. The resulting tomography images can be seen below. Although much of this information could be perceived through the previous TEM thin lamella analysis, performing full tomography and reconstruction provided a real look at the geometries and structural integrity of each component of this transistor. The model was reconstructed from tomography performed as described above. Due to the contrast edge detection methods of the reconstruction, all oxides have been filtered out and are shown in white. This includes the TiO2 that formed immediately following this thin lamella's exposure to air. Through this new model, we can identify the full geometry of the horizontal Pd electrodes. In image b), a view of the bottom side of the gap can be seen, verifying the largely uniform spacing between the electrodes. The 30nm edge to edge distance measured between the electrodes mirrors that shown in Chapter 3 of a different device from the same main electrode line. This reconstruction also provided a means of isolating the aggregates lying directly between the electrodes on the surface of the gap. The more circular of these aggregates averaged 4nm in diameter, with the largest measuring roughly 20nm end to end. These aggregates highlight the asymmetry of the particles in the gap, at least along the surface. These 3D reconstructions were able to confirm that the aggregates do not bridge the two electrodes however they might still largely contribute to electron transport. From these reconstructions however, we were still unable to determine the nature of these aggregates. With electromigration ruled out, the two standing hypotheses are:

IV. Results

Thin Lamella Characterization and Tomography

1) These particles are Pt that has aggregated during one of the electrode fabrication stages.

2) These particles are Pd that has been deposited inside of the gap due to improper shadowing of the gap region.

We believe the second hypothesis to be the most likely as the top most Pt island layer, protected by a thin film of alumina, should be largely resistant to the steps involved in electrode fabrication. Direct spot EDX analysis via TEM should be performed as it may reach the resolution required to render the material composition of these individual aggregates.

Electrical Measurements

For all tested device families, every nanogap transistor formed across the large source electrode was tested in turn. Gate voltage sweep measurements were taken, looking for changes in the Ids current. These measurements were performed on three families of the previously reported buried island structures shown above in Table IV.1.

For each device, an Ids vs. Vgs I-V curve is presented. From this spread of device family characteristics, we could look for changes in periodicity and peak-to-peak ratios to further probe these Pt island layers.

Gate Response of Buried Island Multistack Structure

Results from Device with 2μm-wide Electrode Our first success proved to be the strongest response we measured, found on the multistack buried island 30 cycle device formed at 45°. This device exhibited clear, reproducible oscillations revealing themselves across a range of Vds from -350mV to 350mV, at temperatures of 77K up to 170K. This first device comprised a 2µm wide electrode with a 30nm gap and five layers of 1.8nm diameter Pt islands. A thin lamella of this exact device was shown previously above in Figure IV.4b.

Figure IV.6 -Ids vs. Vgs current response plots for a 30cycle 30nm gap buried multistack structure at varying Vds voltages as indicated in each graph, taken at 77K

Several IV curves of these results across varying Vds values have been selected and can be seen in Figure IV.6. To reiterate, the gate voltage was applied in a dual sweep manner to ensure the validity of the resulting curves. In several of these images, contact issues between the measuring probes and the contact pads resulted in signal spikes or irregularities between the -6 to 4.5 sweep and the 4.5 to -6 sweep. The largest offender of this contact noise has been circled in red in the image above. The measured max peakto-peak ratios fell in the range of 110pA:96pA = 1.1 at 350mV to -210pA:-170pA = 1.2 at -350mV. The highest ratio was found at 150mV due to the increasing slope of the curve, with a ratio of 1.9.

Observing the period of oscillations, we find that the device exhibits a period of about 2.5V for each applied Vds, until passing -300mV, whereby the period begins to stretch out to 3V. Analyzing this, we can extract the gate capacitance a single island, with 𝑒 𝐶 𝑔 = 𝑉 𝑝𝑒𝑟𝑖𝑜𝑑 (where e is the elementary charge and Cg is the gate capacitance) 5 resulting in Cg=0.06aF. This falls within the same range of an 11 series multistack study performed by Ohkura et al. where they calculated a gate capacitance of 0.1aF. Analysis performed in that same article also reasoned that this gate capacitance should still follow the above relation with the period even in multistack structures as long as the variations between islands was minimal. With this incredibly low gate voltage, finding it must be noted that the multistack configuration employed here may lead to varying capacitances depending on a Pt island's location and depth in the matrix.

The large number of islands incorporated in these devices also may explain the increasing slope seen while applying negative Vds biases. It has been shown that including a second island in series can shift the period of oscillations and quench some peaks as the varying capacitances can both enhance and quash the current 6 . As the electric field is increased, it is likely that the cross section of the current path is increased, as more islands are able to be charged and begin to contribute to the current, explaining the shift in period.

Turning to literature, these results seem to mirror the work of Ohkura, who used three Si islands in series to form an SET 7 . In their work, they found that placing three islands in series led to oscillations whose valley current had a positive slope. Two things occurred in their experiments as they increased the applied temperature.

Figure IV.7 -A full compilation of the previous graphs and other measurements across a range of Vds swept from -400mV to 350mV taken at 77K

First, the slope was seen to increase, and second, the magnitude of the oscillations decreased steeply, both mirrored by the results here. Their discussion of their results again precede our own, with their explanation for such results being that multiple conduction mechanisms must be at play. Figure IV.7 shows a culmination of all of the IV responses obtained at 77 K with this device. Although too much of a macro view to perform any form of deep analysis, especially at low Vds values, it again highlights the reproducibility of these measurements, but also highlights the increasing slope found for increasingly negative Vds. This range of gate response data was also used to map out the transconductance, shown in Figure IV.8, in order to have a global overview of all of the responses of the device. The measurement settings employed prevented us from capturing further information at Vds values near zero or beyond 350mV, but we can still see the fringing resulting from the oscillations. The experimental setup presented here lacked fine control when nearing applied voltages below a few hundred mV's, thus reducing the ability to resolve transconductance at Vds values near zero. While this result is a long-shot from the nice Coulomb Diamond's typically seen for low temperature single island devices, if we ignore the center of the diamonds found in most results 8 , this fringing seems to be match sufficiently with the edges of other Pt based devices 9 .

- We would have been remise not chase the Shangri-La of SETs, and test the stability of devices at higher temperatures. We set a constant Vds voltage, choosing a low value of 50mV to combat the increase in conductivity that higher temperatures were previously shown to bring, we believe due to Poole-Frenkel conduction. We then increased the temperature within the chamber by heating the sample holder, waiting for the ambient temperature to stabilize with each step. Gating response sweeps were run at steps of 10K, with the device still holding strong at up to 170K as seen in Figure IV.9. Here we can see that while the period shifted across high Vds voltages, it remains largely constant as the temperature is increased, meaning the overall capacitance is independent of the temperature. We do however see some hysteresis appearing at 170K, as the blockades are possibly becoming less stable. While this maximum operating temperature result was perhaps a tad disappointing, it is still promising to see that these multistack SETs can maintain a Coulomb blockade behavior at higher temperatures despite the large potential for variances. This attests to the regularity of island sizes, and opens doors to the possibility that a simple tuning and calibration of island and device fabrication could very well see stable behavior at even higher temperatures.

Moving on to other 2µm devices on the same electrode line, we found more oscillating responses, albeit with less pronounced results. Several alternative device responses can be seen in Figure IV.10. From these results, we see a much larger spread of oscillatory response shapes but we still see that the period largely conforms to the previously seen 2.5 V. Here, we see peak-to-peak ratios of 1.11, 1.08, 1.01, and 1.04 respectively clockwise starting from the top. These are accompanied by a wide range of current levels, differing slightly from the previous device. While these oscillations were clearly visible across these various other devices, a large quantity of devices exhibited poor gating responses or quickly underwent irreversible dielectric breakdown during testing. Likewise, a spread of results is seen directly here in the results presented above. This all attests that although the electrodes, dielectric thicknesses, and nanogaps should all be identical throughout each of these specific devices, variations such as defects existing within the dielectric layers, differences in the size and arrangement of the islands underneath the gaps, or the aggregates are resulting in variances in responses.

Results from Device with 4μm-wide Electrode We also performed testing across wider electrodes and wider gaps. The first such results, conducted on a 30nm gap and 4µm electrode can be seen in Figure IV.11. First the obvious: the increased electrode width has clearly contributed to the current level, as a larger number of islands in parallel are contributing to the conduction.

Here, oscillations are less obvious and we believe the reduced number of peaks is directly related to the larger number of islands contributing to the conduction. As there is a higher statistical likelihood of finding defects in the matrix, it becomes more difficult to properly activate and control the Coulomb blockades. Although more difficult to quantify, the period of oscillations appears to be close to 6V, with peak-to-peak ratios of a little more than 1 each. Moving on to the study of larger gaps, we looked at devices fabricated at a larger 60 degree angle, which resulted in a roughly 70nm gap seen in Figure IV.12. Here, a new challenge arose. As much higher Vds voltages were required to reach stable Ids responses, the maximum gate voltage we could reach was drastically reduced before current would leak between the gate and the now non-zero drain. Regardless, measurements were performed and the results can be seen in Figure IV.13.

Figure IV.11 -Ids vs. Vgs current response plots for a 30cycle 30nm gap buried multistack structure with a wider 4 micron electrode, at varying Vds voltages as indicated in each graph, taken at 77K

Gate Response of Buried Multistack with Increased Gap Length

Figure IV.13 -Ids vs. Vgs current response plots for a 30cycle 70nm gap buried multistack structure at varying Vds voltages as indicated in each graph, across 2 and 4 micron electrodes, taken at 77K. Peaks indicated by blow arrows

Here again, we can see a clear and reproducible modulation of the current, but it is much harder to conclude the presence of oscillations. We believe them to still be a result of a Coulomb blockade formation, albeit with both secondary conduction mechanisms and competing island capacitances beginning to dominate and drown out the oscillations. Looking especially at the results of the 4μm wide electrode, we can discern two small peaks within the upwards sloping current response. These peaks correspond to a period of about 2.5V, and a peak-to-peak ratio of near 1 again. This new period leads to a calculated 0.08aF gate capacitance, still within a similar range to the samples from before. Again, this incredibly small capacitance level corresponds to the overall gate capacitance and it is difficult to further extract more detailed capacitance values due to the lack of device properties.

Gate Response of Buried Monolayer Structure

Figure IV.15 -Ids vs. Vgs current response plots for a 30cycle 30nm gap buried monolayer structure at varying Vds voltages as indicated in each graph, across 2 and 4 micron electrodes, taken at 77K. Peaks and period are indicated in blue markings

Here at 2µm we see a very similar result of a period of 2.5V, albeit with only two clear peaks. Interestingly, shifting to 4µm reveals a clearly reproducible modulation with three clear peaks indicating a period of about 4V. Overall, it appears that the oscillations in both devices have been drowned out due to the higher Vds employed.

V. Discussion of Measurement Results

Following these results, we can attempt to perform classical analysis on the nanoparticle film, taking into account previous works 8,9 . Looking at the results from the first functioning SET, at 150mV and 77K, we can begin to extract information on this system. First, addressing the self-capacitance of the islands, we can focus on the equation

𝐸 𝑐 = 𝑒 2 2𝐶 𝑠 ,
where Ec is the charging energy, e is the elementary charge, and Cs is the self-capacitance of a given island, given by

𝐶 𝑠 = 2𝜋𝜀 𝑟 𝜀 0 𝐷,
where D is the diameter of the nanoparticles 5 . Taking the values of 1.8nm for the diameter and 8 for the permittivity 1,2 , from the previous results, we arrive at a self-capacitance of 0.8aF and a charging energy Ec of 100meV. These values fall in line with those, again, from Ohkura's work 5 on series multistack SETs where they found a self-capacitance of 1aF and a charging energy of 60meV for 11 islands placed in series. From these results, we can look at the temperature limits of this system, from the equation

𝑇 ≪ 𝐸 𝑐 𝐾 𝑏 = 1100𝐾,
where Kb is the Boltzmann constant 10 . Given Likharev's analysis that consistent Coulomb blockade operation is best found at temperatures 10 times lower than that given by the equation, we find a target operating temperature of around 110K. This estimated best operating temperature falls within the range of those seen here where the above devices ceased to function at around 180K.

Using the parallel plate approximation, we calculated an active region gate capacitance above the matrix to be 20fF. Looking at the islands themselves, this same approximation results in a gate capacitance of 0.01aF for a single island. This approximate value falls in the same range as the previous result of 0.06aF, calculated from a period of 2.5V. While low, these values are within the same range as other multistack SET studies where single island gate capacitances fell in the range 0.1-1aF 3,5,11,12 .

Figure IV.16 -Two-terminal I-V response showcasing Poole-Frenkel fits with possible masked conduction mechanism

Looking back over trends in the gating responses, while the observed oscillations were reproducible, as marked by the dual sweep stability of the responses, the period and corresponding peak voltages depended on the level of the drain-source voltage. In addition, as the drain-source voltage was increased in the positive or negative direction, two phenomena could be observed: 1) the peak-to-peak ratio of the oscillations was reduced, and 2) a slope begins to develop across the negative responses. These two observations are interesting to analyze, as they seem to be linked to the simple two-probe IV responses we previously measured in chapter 3. In those responses, shown in Figure IV. 16, we saw that although Poole-Frenkel conduction clearly dominated the current response through the nanoparticles, the conduction fit itself was altogether different at low and high voltage values. It was also shown that while the Poole-Frenkel model fit over the responses at positive and negative biases, the current response was much higher over the negative range. These results seem to be seen directly here where the slope of the gating responses increases when moving from low to high biases and from positive to negative biases. Looking further at the previous findings, it was concluded that while Poole-Frenkel is the dominant conduction mechanism through the Pt nanoparticle matrix, it is unclear if there are two Poole-Frenkel regimes or if another, weaker conduction mechanism such as cotunneling is masked and can only be seen at low applied Vds voltages. The running hypothesis is that cotunneling and Poole-Frenkel are both acting in competition through these nanoparticle films. Numerous articles from literature show that as cotunneling is not blocked by Coulomb blockades, it's effects can be observed in Coulomb oscillations and responses 5,10,13 . More specifically, cotunneling current observed during Coulomb blockades in Ids vs. Vgs responses leads to both increasing valley current levels and lower maximum operating temperatures. Both of these phenomena have been observed and reported herein. Regardless, it is clear that Coulomb blockades are being formed under an applied gate bias through one of two methods. One possibility is that Poole-Frenkel is the only conduction mechanism and that the trap levels, accessed through thermally activated hopping, are being electrostatically charged and are forming Coulomb blockades themselves. Another possibility is that this lower voltage range really does reveal a weaker conduction mechanism over which Coulomb blockades are created 7 .

VI. Conclusion

Through this work, three terminal nanoparticle devices were characterized and evaluated for gating effects. These devices were unique in the field of multistack transistors due to the sheer number of islands placed in both series and parallel. Thanks to the synergy created by combining ALD with shadow-edge evaporation, we were able to place an estimated 20,000 islands within a gap of close to 30nm. While bottom gate configurations did not seem to have any effect on the current response, top gate devices exhibited what appear to be Coulomb blockade induced oscillations across the Ids current when sweeping the applied gate voltage. These oscillations were most notable with the buried island multistack devices across 30nm electrode gaps, with oscillations visible across a wide Vds range, and up to 170 K before being lost. While the period of oscillations was found to be on average 2.5V across devices, the peak-to-peak ratios and general slope of the curves were varied. While the underlying transport mechanism must still be studied, it is clear that single electron transistor operation is achievable in very large, 3D, multistack arrays.

First and foremost, the optimization and further research steps mentioned in the conclusions of chapter 2 and 3 should shed more light on the nature of these films. At the core, understanding the source of the aggregates inside of the gap, and building a better understanding of the transport mechanisms at play should be achievable through further device fabrication and characterization studies. Given the size and dispersion of these PEALD grown Pt islands, the pursuit of room temperature operation should be achievable given proper optimizations in electrode formation, gap formation, and island growth.

CONCLUSION & PERSPECTIVES

The work herein has been dedicated to developing scalable techniques for the fabrication of single electron transistors, working towards obtaining stable room temperature operation. The targeted structures included large arrays of islands, shown to improve Coulomb blockade stability, and well suited for increasing the active area in sensor applications. Through this text, functioning single electron transistors based on 3D arrays of Pt nanoparticles have been fabricated and characterized.

An electrode fabrication process was developed, using negative resist UV lithography and e-beam evaporation. These two basic techniques were combined in a two-step shadow edge evaporation process for the formation of nanogap electrodes. This shadowing technique was optimized for transistor electrode fabrication through trials and studies of several photoresists, metal evaporators, and metal sources. This combination was utilized to demonstrate the fabrication of source and drain electrodes from 2-100μm in width with gap lengths down to 6nm. In the end, a full fabrication stack was developed to build gate, source, and drain electrodes from a Ti sticking layer and a Pd contact layer. The lengths of each gap were able to be modulated via sample holder supports which provided an angle to the deposition for shadowing. As this process can be applied to any patterning technique, adapting for the use of e-beam evaporation or laser lithography would allow for further studies on the scaling of the utilized Pt island layers. Further optimizations should be performed on the evaporation technique itself to create a more reproducible process, allowing for the precise creation of targeted gap lengths. To do this, further studies may be drawn on the counter and offset angles seen in cross sections of resulting electrodes.

Atomic layer deposition was studied for the formation of Al2O3 dielectric barriers and Pt nanoislands. Taking advantage of the nucleation delay inherent in the formation of Pt via PEALD, full wafer island arrays were built and studied using TEM for verification. Island sizes could be largely controlled via the number of PEALD cycles, allowing us to build arrays of islands with 1.7nm, 2.5nm, and 4nm average diameters. ALD also provided control over the growth of alumina down to 1.1A/cycle. This ALD grown Al2O3 was used to encapsulate these islands in a dielectric matrix and vast 3D arrays were built by stacking island layers sandwiched between alumina thin films. The ALD platform provided a means of growing these 2D and 3D Pt nanoisland arrays in a single vacuum cycle, at a constant 200˚C. While the nucleation delay and growth characteristics must be tested and mapped for a given machine and process, studies have shown that not only the size, but the spacing of PEALD grown Pt islands can be controlled. This opens a wide range of parameters which may be fine-tuned, further optimizing the size, size dispersion, island spacing, and even defect levels of these arrays. Similar studies and improvements may be performed on the growth of alumina to grow potentially more uniform layers with fewer defects. Next steps should include a deeper study over the mechanics and reproducibility of growing these Pt nanoisland dielectric matrices.

Several device configurations were created and used to probe the transport characteristics of the Pt nanoisland arrays. Devices spanned: planar nanogap filled with Pt islands, vertical Pt island stack, reference alumina stack, buried multistack of Pt islands, and buried monolayer of islands. These device configurations, provided a platform for testing changes brought on by the introduction of Pt islands in the alumina matrix, changes brought on by moving from 2.5nm to 1.8nm islands, and changes brought on by modulating the transport distance from 30nm to 70nm. Two-terminal electrical measurements at varying temperatures down to 77K revealed a clear transition from Fowler-Nordheim transport through the ALD grown alumina, to a Poole-Frenkel transport through the Pt island arrays. The observation of Poole-Frenkel indicates the existence of traps, believed to originate from defects in the alumina layer resulting from the presence of Pt during growth. FIB prepared thin lamellas observed via HRTEM and STEM revealed unidentified, discontinuous aggregates inside the gap in several buried island devices. EDX performed on these samples verified the purity of the materials deposited through this fabrication stack but was not able to resolve the materials of the aggregates. Performing EDX spot analysis in the future, while irreversibly damaging to the sample, has hope of resolving the materials of individual aggregates. These aggregates appeared to have little effect on the observed transport, as modulating both the number of island layers and the gap length revealed the same transport response. Reducing the island size revealed a departure from the traditional Poole-Frenkel model at low temperatures and low applied biases. Several models were applied and while inconclusive, it is believed Poole-Frenkel transport across these traps is masking secondary cotunneling transport, revealed under these specific conditions. Further studies on newly fabricated devices, specifically following the fabrication optimizations suggested above, should reveal further information on the nature of this seemingly dual transport mechanism. Additional research should be performed on the growth mechanics of these PEALD Pt islands and ALD alumina layers. Improved growth parameters, or perhaps the introduction of atomic layer etching, could improve the purity of these layers and quench the visible Poole-Frenkel transport trap assisted transport.

Using TEM tomography, 3D models of the electrodes, gaps, and most importantly the aggregates were made from new thin lamella observations. These models verified the non-continuity of these aggregates traversing the gap. Three terminal transistor measurements were performed on several buried island devices, comparing monolayers to multistacks of islands, and comparing changes to the gap length and gap width. These studies revealed Coulomb oscillations in all devices with an average period of 2.5V and a maximum peak-to-peak ratio of about 1.9. Oscillations were visibly and reproducibly stable up to 170K. Increasing the drain-source bias introduced more noise to the system but seemed to have little effect on the slope of the overall. Applying increasingly negative biases however increased this slope to the point of drowning out the oscillatory peaks. It is not yet understood where the origin of these Coulomb blockades lie, but given the transport mechanisms observed, Poole-Frenkel, cotunneling, or perhaps both should be blocked as seen in most single electron transistors. Hindered by the resources available, this study was only able to perform measurements down to 77K, but performing additional studies under liquid helium cooling would likely reveal further information on the nature of these Coulomb blockades.

In summation of these developments, readily scalable and accessible processes have been effectively demonstrated as fully capable of producing single electron transistors. These SETs were demonstrated in numerous configurations with clear and reproducible oscillations at moderate temperatures. Combining the perspective optimization stages presented above for each step, room temperature operations should be achievable. Introducing further control to the formation of the nanogap itself and the Pt island layers would allow for the creation of new structures such as a planar filled-gap structure capturing a targeted number of parallel islands in series. These fabrication optimizations will be aided by further characterization at each stage. Performing electrical measurements under helium should further reveal the true nature of the underlying physical properties of these nanoisland arrays, increasing our understanding of these systems and allowing us to increase their stability and operating temperature.

ANNEX E-beam Evaporation Process and Recipes

After wafers were properly patterned with photoresist, we next moved to coat these wafers with metal, thus depositing metal inside the photoresist trenches. For this we experimented using both an Edwards and an Alcatel evaporator and tested the efficacy of several metallic combinations for building electrodes. The working principle of each of these machines was the same: Under a high vacuum environment, an electron beam is created and aimed at a crucible containing the desired deposition material. The high energy of this electron beam vaporizes the deposition material, scattering its atoms out in a cone where it will settle and deposit on any surfaces in a direct line of sight. The desired deposition material target is loaded into a sturdy crucible, and loaded into the center of the chamber. Opposite this crucible, a sample is fixed to a sample holder to be coated. To create the electron beam, tungsten filaments are placed under an ultra-high voltage, feeding thermal energy to the filament. As the energy within the filament grows, electrons within the lattice of the tungsten will be emitted. A magnetic field is formed within the chamber, guiding and focusing these emitted electrons directly on the surface of the crucible. Typically, the magnetic field is fluctuated to force the electron beam to trace back and forth across the crucible, ensuring an even vaporization of the target. High vacuum environments are required to ensure the reduction of molecular interference within the chamber. As both the electron beam itself and the cone of the vaporized target are conformal, any stray molecules that block their path will cause uncontrollable, scattering within the chamber. If vacuum levels are high enough, the atoms emitted from the target will travel through the chamber without interference and will strike the substrate in a direct line from the e-beam striking point on the crucible. The highly anisotropic nature of this deposition method enables the use of shadow edge evaporation technique. By strategically placing specific structures in the path of emitted atoms, specific regions of the substrate will be shadowed as described above. Finally, by placing a quartz piezoelectric sensor inside the chamber, it is possible to measure the amount of material deposited by monitoring the resonance change of the quartz due to the growing coat of material atop its surface.

Encapsulated Pt Island ALD Recipe

The below recipe was used to build the reported monolayer and multistack platinum island structures. Line 37 was modified to make either 30 or 50 cycles of Pt and line 41 was modified to make either a monolayer or 5 stacks of islands Cette méthode est utilisée dans ce travail pour fabriquer les nanogaps séparant la source et le drain métalliques des futurs transistors. Les nanogaps sont réalisés pendant l'étape d'évaporation : ainsi n'importe quelle forme de motif, qui peut être réalisée par photolithographie UV standard, est utilisable, ainsi que n'importe quel matériau, indépendamment de sa nature chimique. Le point clé est l'anisotropie de la technique de dépôt, ce qui est le cas par exemple pour l'évaporation.

Deux étapes d'évaporation sont nécessaires comme illustré dans la figure I.1. Une première couche métallique est déposée par évaporation et microstructurée suite à une étape de photolithographie puis gravure ou utilisation de la technologie de lift-off. Nous avons choisi un motif en forme de barreau. A ce stade, l'épaisseur de la couche déposée et la qualité de la coupe transverse du motif, et de ses bords en particulier, sont cruciales, en termes de rugosité et régularité, puisque c'est l'arête de cette première couche qui va servir d'ombrage à la seconde couche métallique déposée et être à l'origine du nanogap ainsi créé.

Choix des résines et développement d'un masque pour la photolithographie

Concernant les résines, notre choix s'est orienté vers des résines négatives ou inversibles dont les flancs obtenus rentrants à l'issue de l'étape de photolithographie sont favorables au lift-off ainsi que montré figure I.2a. L'avantage présenté par les flancs rentrants de la couche de résine négative ou inversible (par rapport à une couche de résine positive) pour faciliter le dégagement de la couche métallique déposée lors du lift-off est illustré figure I.2b. Le triangle jaune entouré de ligne pointillée rouge a été ajouté pur montrer que l'arête de la couche métallique déposée n'est pas forcément parfaitement verticale. Cet écart par rapport au procédé idéal n'est pas sans conséquence au niveau du nanogap formé dans le cadre de l'évaporation à angle comme nous le pourrons le constater lorsque nous aborderons les résultats expérimentaux. -Position du quartz plus variable sur l'Edwards que sur l'Alcatel -La durée de la mise sous vide, beaucoup plus longue sur l'Edwards (avec une seule chambre) que sur l'Alcatel (deux chambres)

-La forme du réacteur, avec une distance cible -échantillons plus faible sur l'Edwards, avec des montées en température pouvant dépasser 100°C au niveau du porte-échantillon et certainement nocives par rapport à la forme des profils de résine utilisées pour le lift-off.

Concernant le choix du métal à déposer dans ce réacteur, des échantillons ont été réalisés avec l'aluminium mais le meilleur choix s'est avéré être une bicouche titane-palladium, finalement utilisé dans les dispositifs finaux. L'aluminium présentait l'avantage d'être compatible CMOS, d'adhérer sur SiO2 et l'Al2O3 sans la nécessité d'une couche d'adhésion intermédiaire. La majorité des expérimentations de calibration et les premiers résultats ont été réalisés avec ce métal. C'est d'ailleurs aussi avec ce métal que la plus petite longueur de gap (6 nm) a été obtenue. Les paramètres expérimentaux utilisés dans l'Alcatel pour l'Al et la bi-couche Ti/Pd sont rapportés dans le tableau I.1. A partir de ce choix de conditions initiales, des procédés de lithographie ont été affinés afin de fournir des microstructures appropriées.

Optimisation des paramètres pour la formation des électrodes

Comme l'ensemble du procédé de l'évaporation à angle repose sur le premier motif réalisé, qui doit, par effet d'ombrage, former un nanogap lors de la 2 nde évaporation réalisée avec l'échantillon pivoté, l'arête de ce premier motif doit être la plus droite et la plus régulière possible et présenter un relief minimum. Les dimensions nominales du motif doivent être reproduites le plus fidèlement possible et le procédé doit si possible être très reproductible. A cette fin, les étapes de photolithographie avec les résines nLOF 2020 et AZ 5214 E ont été évalués et optimisées.

Résumé Page | 7 AZ nLOF 2020 Optimization

Les conditions standard d'utilisation de la nLOF 2020, réputée comme une résine assez stable même dans de conditions expérimentales variables, par exemple en terme de température..) sont rapportées dans le tableau I.3. On observe tout d'abord que l'arête de la première couche d'aluminium n'est pas parfaitement verticale ce qui aura pour conséquence de réduire la longueur du nanogap obtenu par rapport à la longueur nominale. Bien que cet angle additionnel soit présent dans la fiche technique de la résine proposée par MicroChemicals (et donnée dans le paragraphe du choix des résines), il est difficile à quantifier. On observe également sur la figure I.7 qu'il peut prendre des valeurs assez dispersées, même sur des dispositifs placés sur un même échantillon. Il est à noter que l'on a un facteur important (7.5 ici) entre l'épaisseur de la résine (900nm) et l'épaisseur du métal déposé (150nm) qui ne facilite pas à priori un contrôle très fin de la géométrie du métal déposé.

Par ailleurs, l'angle entre la verticale à l'arête de la première couche d'aluminium et la seconde couche d'aluminium n'est pas de 45° comme prévu mais de 40°, ce qui laisse penser à une imperfection de la chambre ou du support porte-échantillon pouvant être à l'origine d'un contreangle. Afin d'évaluer plus précisément l'influence des différents paramètres sur la longueur du gap, on représente en figure I.9 le positionnement de l'échantillon lors de la seconde évaporation. Sur ce schéma, φ représente un éventuel contre-angle par rapport à l'horizontale, α le nouvel angle utilisé dans la seconde évaporation pour l'effet d'ombrage et β l'angle formé par la première électrode métallique avec l'arête verticale. En conclusion, il apparaît que l'angle que fait l'arête du premier motif métallique est assez mal contrôlée lors du 1 er lift-off et varie sur une grande gamme de valeurs. Ce manque de contrôle dans la forme de l'arête de ce motif est potentiellement lié au grand facteur (>7.5) entre l'épaisseur de métal déposée et l'épaisseur de la résine qui induit un manque de reproductibilité lors du lift-off.

Le contre-angle qui est mis en évidence lors de la seconde évaporation est probablement lié au support pour l'évaporation à angle et il est inférieur à 10°. Globalement, les longueurs de gap obtenues sont donc plus faibles que les longueurs nominales mais restent difficiles à prévoir précisément compte tenu de la variabilité de la forme de l'arête du premier motif métallique.

Fabrication de nanoparticules de platine encapsulées dans une matrice d'alumine

Nous avons choisi l'alumine comme diélectrique en raison de sa robustesse, sa grande constante diélectrique et la possibilité de le déposer de façon extrêmement contrôlée à la monocouche près grâce à la technique de l'ALD. Le platine quant à lui présente l'avantage d'être un métal noble avec un grand travail de sortie permettant une meilleure rétention. Pour l'obtention des nanoparticules de platine, nous avons initialement envisagé deux méthodes : la méthode de démouillage d'une part et le dépôt par ALD d'autre part. Comme nous le verrons plus loin, la méthode par ALD s'est avéré donner de meilleurs résultats en terme d'uniformité de nanoparticules. D'autre part, l'association de ces deux dépôts dans le même réacteur, en l'occurrence par ALD thermique pour l'alumine et ALD assistée plasma pour les nanoparticules de platine présente l'avantage d'être effectuée dans une seule et même étape sans remise à l'air. Les dépôts ont été réalisés dans un réacteur de type FIJI F200 (figure I.13). Les clichés issus de l'observation par TEM de couches de platine déposées avec des durées de cycles variant entre 30 et 60 cycles sont donnés en figure I.17. Ces couches ont été déposées sur des grilles de 8nm de SiO2. : ;

Avec S la section de la jonction MIM, q la charge électrique élémentaire, E le champ électrique appliqué, Ep le champ électrique parasite (lié à la présence de charge dans la couche d'Al2O3), h la constant de Planck, φ la hauteur de barrière et m* la masse effective des porteurs dans la couche d'alumine. Les paramètres extraits des courbes d'ajustement théoriques sur les données expérimentales sont présentés dans le tableau II.1.

avec kb la constant de Boltzmann, T la température absolue, εi la permittivité relative du milieu effectif, ε0 la permittivité diélectrique du vide et A le produit de la mobilité électronique et de la densité de porteur dans la bande de conduction à champ nul. Le paramètre A s'exprime de la manière suivante : Les caractéristiques I-V de cette structure planaire sur la gamme de température 100K-300K sont présentées en figure II.6. A partir de ces caractéristiques I-V, nous avons à nouveau identifié un mécanisme de transport assisté par piège de type Poole-Frenkel. Les paramètres issus des ajustements des courbes théoriques sur les données expérimentales sont présentés dans le tableau II.3. Les valeurs extraites de permittivité relative sont du même ordre de grandeur que celles obtenues sur la structure verticale. A partir de la dépendance en température du paramètre A, nous avons extrait une profondeur de pièges de l'ordre de 80meV, très inférieure à la hauteur de barrière Pt/Al2O3 de 3eV. Cette extraction confirme que les îlots de Pt ne jouent pas eux-mêmes le rôle de piège dans le mécanisme Poole-Frenkel. Les écarts observés sur les valeurs de permittivité et de profondeur des pièges pour les 2 structures verticales et planaires proviennent possiblement de l'imprécision de notre méthode d'extraction. Anisotropie du transport électronique En figure II.7, nous avons comparé les caractéristiques J-E (densité de courant en fonction du champ E appliqué) obtenues à 100K sur les structures verticales et planaires. Bien que le mécanisme de transport identifié soit le même pour les deux structures, un écart significatif de plus de 4 ordres de grandeur apparaît sur la densité de courant, sur toute la gamme du champ E appliqué. Il est à noter que cet écart significatif sur les densités de courant est observable sur toute la gamme de température comprise entre 100K et 300K. D'après les extractions effectuées dans la section précédente (tableaux II.2 et II.3), il semblerait que cette anisotropie provienne principalement du paramètre A qui est de l'ordre 8,5x10 11 m -1 .V -1 .s -1 pour la structure planaire et de 3,5x10 7 m -1 .V -1 .s -1 pour la structure verticale à 100K. Nous rappelons que le paramètre A dépend directement de la mobilité électronique µ et de la profondeur des pièges Ф (Cf. équation(3)). Comme les profondeurs de piège extraites pour les deux arrangements sont du même ordre de grandeur, nous avons donc cherché une explication du côté de la mobilité des porteurs pour expliquer cette anisotropie du transport électronique. Les caractéristiques I-V d'une structure planaire incluant une grille supérieure sont présentées en figure II.10. Nous avons pu à nouveau identifier un mécanisme de transport de type Poole-Frenkel avec des paramètres extraits A et i (Cf. Tableau II.4) du même ordre de grandeur que sur les structures planaires précédentes qui n'intégraient pas de grille supérieure. Toutefois, il est important de souligner qu'une déviation non négligeable par rapport au modèle Poole-Frenkel apparaît à bas champ (V<0,2V) sur la caractéristique I-V mesurée à 100K. Deux hypothèses ont été émises à ce stade pour expliquer cette déviation :

perte de la qualité des contacts avec les pointes de test à basse température apparition d'un nouveau mécanisme de transport à basse température avec éventuellement du blocage de Coulomb. Ces hypothèses seront discutées plus en détail dans la section suivante.

Résumé Page | 27

Tableau II.4 -Paramètres extraits pour la structure planaire incluant une grille supérieure

T (K)

A (m -1 .V - Influence de la réduction de taille des nanoparticules Dans l'optique de maximiser la température de fonctionnement des transistors, nous avons développé de nouvelles structures planaires intégrant des îlots de Pt de plus petit diamètre, de l'ordre de 1,8nm. Sur ces nouvelles structures, les îlots de Pt ont été obtenus à partir de 30 cycles de croissance ALD au lieu de 50 cycles pour les échantillons précédents. Tableau II.4 -Paramètres extraits sur toute la gamme de tension appliquée (à gauche) et sur la gamme 0-0,2V (à droite)

T (K)

A (m -1 .V -1 .s -1 ) εi T (K) A (m -1 .V - La couche verte a été utilisée pour former l'électrode de grille. Enfin, la couche violète a été utilisée pour décaper le diélectrique de grille afin de permettre la réalisation des contacts. La grille Résumé Page | 33 métallique elle-même mesurait 14 μm x 15 μm et formait une capacité de grille de chevauchement globale de seulement 0,7 pF. Une fois que la plaquette finale a été fabriquée et placée sur le même banc de mesure, une troisième sonde, également connectée à un amplificateur sur le Keithley-4200, a été placée au-dessus de la nouvelle électrode de grille de la même manière qu'auparavant : mise en contact et traînée sur la surface de l'électrode jusqu'à ce qu'une mesure stable soit atteignable. Les échantillons ont ensuite été soumis à la même préparation : ils ont été placés sous vide et chauffés à 400K pendant une heure, pour éliminer toute l'humidité potentielle de la chambre, avant d'introduire de l'azote liquide pour ramener la température ambiante à 77K. Tomographie par microscope électronique à transmission Une tomographie complète a été réalisée pour avoir une vue complète des trois électrodes, des espaces formés et des couches d'îlots. La tomographie a été effectuée sur un dispositif multicouche présentant des nanoparticules de Pt de 1.8nm de diamètre, avec un gap 30nm non stressé électriquement, afin de déterminer si les agrégats de Pt apparents ont été créés sous stress électrique, ou sont dus au processus de fabrication lui-même. Pour effectuer cette analyse, une mince lamelle a été préparée, et a été revêtue de nanoparticules Au colloïdal avant d'être chargée dans un support TEM à double inclinaison, pouvant être déplacé à la fois sur les axes X et Y. L'échantillon a été agrandi à 450kx et les images ont été capturées de -70˚ à 70˚ par pas de 2˚. Ces images ont ensuite été reconstruites, en utilisant les nanoparticules Au très contrastées comme points de référence, pour créer une image 3D du dispositif et de l'espace entre les électrodes. En observant la période des oscillations, nous constatons que le dispositif présente une période d'environ 2,5 V pour chaque tension Vds appliquée, jusqu'à Vds  -300 mV, par lequel la période commence à s'étendre jusqu'à 3 V. En analysant cela, nous pouvons extraire la capacité de grille globale Cg  0,06aF, à partir de

[ ] X é _
(où e est la charge élémentaire et Cg est la capacité de la grille) [2] Cette valeur se situe dans la même gamme d'une étude réalisée par Ohkura et al. où ils ont calculé une capacité de grille de 0.1aF [2], sur une structure multi-îlot. L'analyse effectuée dans ce même article a également motivé que cette capacité de grille devrait encore suivre la relation cidessus avec la période, même dans les structures multi-îlots, tant que les variations entre les îles étaient minimes.

Le grand nombre d'îlots incorporés dans ces dispositifs peut également expliquer la pente croissante observée lors de l'application des tensions Vds négatifs. Il a été démontré que l'inclusion d'un deuxième îlot en série peut déplacer la période d'oscillations et supprimer certains pics, car les capacités variables peuvent à la fois améliorer et annuler le courant [6]. À mesure que le champ électrique est augmenté, il est probable que la section transversale du chemin actuel augmente à Résumé Page | 37 mesure que de plus en plus d'îlots peuvent être chargés et commencent à contribuer au courant, en expliquant le changement de période. En ce qui concerne la littérature, ces résultats semblent refléter le travail d'Ohkura, qui a utilisé trois îlots en silicium en série pour former un SET [7]. Dans leur travail, ils ont constaté que placer trois îles en série conduit à des oscillations. Deux choses se sont produites dans leurs expériences quand ils ont augmenté la température appliquée. Tout d'abord, la pente a augmenté, et deuxièmement, la grandeur des oscillations a diminué de façon abrupte, toutes deux reflétées par nos résultats. Leur explication était que de tels résultats sont dus à des mécanismes de conduction multiples. La figure III.6 montre toutes les réponses IV obtenues à 77 K sur ce dispositif, elle indique la reproductibilité de ces mesures et souligne également la pente croissante trouvée pour Vds de plus en plus négatif. Nous avons ensuite augmenté la température dans la chambre, en attendant que la température se stabilise à chaque étape (figure III.7). Nous pouvons voir que, la période des oscillations reste largement constante à mesure que la température augmente, ce qui signifie que la capacité globale est indépendante de la température. Nous voyons cependant une hystérésis apparaissant à 170K, car le blocage est peut-être moins stable. Bien que la température maximale de fonctionnement ait été peut-être un peu décevante, il est prometteur de voir que ces dispositifs multi-îlots peuvent maintenir un blocage de Coulomb à des températures plus élevées. Cela témoigne de la régularité de la taille des îlots et ouvre les portes à la possibilité qu'un réglage et un étalonnage simples de la fabrication des îlots et des dispositifs puissent très bien voir un comportement stable à des températures encore plus élevées.

Caractérisation électrique des composants avec une largeur d'électrode de 4 m

Nous avons également effectué des essais à travers des électrodes plus larges et des distances entre électrodes plus larges. Les premiers résultats de ce genre, obtenus pour un gap de 30nm et une électrode de 4 μm, sont présentés à la figure III.8. L'augmentation de la largeur de l'électrode a clairement une influence sur le niveau du courant, car un plus grand nombre d'îlots en parallèle contribuent à la conduction. Ici, les oscillations sont moins évidentes et nous croyons que le nombre réduit de pics est directement lié au plus grand nombre d'îlots contribuant à la conduction. Comme il existe une probabilité statistique plus élevée de trouver des défauts dans la matrice, il devient plus difficile d'activer et de contrôler correctement le blocage de Coulomb. Bien que plus difficile à quantifier, la période d'oscillations semble encore être proche de 2,5 V.

Résumé Page | 42

Pour un échantillon de largeur 2 μm, nous obtenons un résultat très similaire d'une période de 2,5 V, bien qu'avec seulement deux pics clairement identifiés. Fait intéressant, l'augmentation de la largeur à 4 μm révèle une modulation clairement reproductible avec trois pics clairs indiquant une période d'environ 4V. Dans l'ensemble, il semble que les oscillations dans les deux échantillons aient été noyées en raison de la tension Vds plus élevée utilisée. L'augmentation de la période est intéressante à noter car elle indique que la capacité globale du film, correspondant à 0,04aF, a diminué avec l'élimination des autres couches, mais aussi avec une augmentation de la largeur latérale. Cela signifie que la capacité de la grille ne dépend pas uniquement du nombre d'îlots placés en parallèle, mais aussi de leur configuration dans la direction verticale.

Discussion sur les résultats électriques À la suite de ces résultats, nous pouvons essayer d'effectuer une analyse en prenant en compte les travaux antérieurs [1,8]. En regardant les résultats du premier SET opérationnel, à 150mV et 77K, nous pouvons commencer à extraire des informations sur cet échantillon. Tout d'abord, abordant la capacité des îlots, nous pouvons nous concentrer sur l'équation

= - 7[ `,
où Ec est l'énergie de charge, e est la charge élémentaire, et Cs est la capacité d'une îlot donnée, donnée par a 2cd d e f, où D est le diamètre des nanoparticules [2]. Prenant les valeurs de 1.5nm pour le diamètre et 8 pour la permittivité [4,5], à partir des résultats précédents, nous arrivons à une capacité de 0.7aF et une énergie de charge Ec de 120meV. Ces valeurs sont en ligne avec ceux, encore une fois, du travail d'Ohkura sur les jeux multi-îles série où ils ont trouvé une auto-capacité de 1aF et une énergie de charge de 60meV pour 11 îles placées en série [2]. À partir de ces résultats, nous pouvons examiner les limites de température de ce système, à partir de l'équation g ≪ * i P @ 1400l, où Kb est la constante de Boltzmann [3]. Compte tenu de l'analyse de Likharev [3] selon laquelle une opération de blocage constante de Coulomb nécessite une température 10 fois inférieure à celle donnée par l'équation, nous trouvons une température de fonctionnement cible d'environ 140K, valeur très proche de celle trouvée expérimentalement dans notre étude (170K).

En utilisant l'approximation du condensateur plan à faces parallèles, nous avons calculé une capacité active de la grille de la zone active de 20fF. Si on calcule plutôt la capacité d'un seul îlot situé sous la grille, on trouve une valeur de 0,01aF. Toutefois, à partir de la période, nous avons trouvé une valeur de capacité de grille de 0,06aF, calculée à partir d'une période de 2,5V. Ces écarts sont probablement dus au fait que nous avons tant d'îlots dans la région active, chacun ayant une Résumé Page | 43 capacité de grille variable en fonction de sa profondeur ou de l'influence des capacités locales des îlots voisins. The introduction of the single electron transistor (SET) shook the semiconductor industry, with promises of unrivaled efficiency. However, the cost and complexity associated with achieving stable operation have heavily hindered their adoption. Having fallen out of the graces of industry, academic research has continued to push, demonstrating novel techniques for SET creation. At the core of this stability issue is a need to controllably build nanoislands smaller than 10nm. Among the methods available for this nanoisland formation, atomic layer deposition (ALD) sets itself apart as an industrially scalable, highly controllable process. The second barrier to entry is the creation of nanogap electrodes, used to inject current through these nanoislands, for which researchers have leaned heavily on non-scalable fabrication techniques such as electron beam lithography and focused ion beam. The shadow edge evaporation technique overcomes the complexity and scaling issues of nanogap fabrication, opening new possibilities.

In this work, ALD will be demonstrated as a superb technique for growing vast 3D arrays of sub 2nm platinum nanoparticles encapsulated in Al2O3. ALD provided a means of growing these nanoparticle matrices in a single process, under vacuum, and at low temperatures. Through shadow edge evaporation, UV lithography was then utilized to form nanogap electrodes with high lateral widths (100µm), with gaps demonstrated below 7nm. The combination of these techniques results in a high yield, low requirement fabrication process for building full SETs.

From the resulting transistors, thin lamellas were prepared using FIB and 3D models were reconstructed via TEM tomography for analysis. Electrical characterization was performed down to 77K, with modeling revealing Poole-Frenkel transport alongside possible cotunneling. Stable Coulomb blockades, the signature of SETs, were observed with regular periodicity and were identifiable up to 170K. Optimization of this process could yield high surface area SETs capable of stable operation at room temperature.

MOTS-CLÉS

INTRODUCTION CHAPTER 1

 1 An Introduction to Single Electron Transistors and Fabrication Techniques I. Introduction II. Single Electron Transistors III. Nano-Island Applications and Fabrication Methods IV. Atomic Layer Deposition V. Nanogap Electrodes VI. Presentation of Thesis Contents CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth I. Introduction II. Nanogap Electrode Fabrication III. Platinum Nano-Islands Encapsulated In an Aluminum Oxide Matrix IV. Conclusion CHAPTER 3 Two-Terminal Platinum Nanoparticle Nanogap Device Characterization I. Introduction II. Two Terminal Device Fabrication

Figure I. 1 -

 1 Figure I.1 -Graph of Intel CPU trends from Sutter showcasing growth of transistor packing and stagnation of traditional performance metrics 3

Figure I. 3 -

 3 Figure I.3 -Active power vs. performance for 14nm and 10nm nodes from Intel 4

Figure I. 4 .

 4

Figure I. 4 -

 4 Figure I.4 -Figure from Fulton and Dolan's pioneering first single electron transistor 14 2. The Coulomb Blockade and Current through SET Structures Basic Rules for SETs

7

 7 Figure I.5 -Diagram of a Coulomb blockade forming metal island presented byKastner 7

CHAPTER 1 An

 1 Introduction to Single Electron Transistors and Fabrication TechniquesPage | 8

Figure I. 6 -

 6 Figure I.6 -Two-terminal IV response of a Coulomb blockading device such as that found in Figure I.5. This diagram was originally presented by Likharev showing results for several values of Qe 15

Figure I. 7 -

 7 Figure I.7 -Diagram of a basic metal island SET adapted from Kastner 7

Figure I. 8 -

 8 Figure I.8 -External Charge dependence on gate voltage for SET at T = 0 as demonstrated byLikharev 15

Figure I. 9 -

 9 Figure I.9 -Coulomb oscillations seen in the current response vs. gate bias for a) an ideally simulated SET shown by El Hajjam 17 and b) one of the first real world oscillatory responses observed by Kastner 7 These Coulomb oscillations, shown in Figure I.9, are one of the telltale signs of full SET operation. Of note, the period of oscillations can easily be extracted utilizing information from Figure I.8 above, yielding 𝑃 = 𝑒 𝐶 𝑔𝑎𝑡𝑒 .

Figure I. 11 -

 11 Figure I.11 -Gold nanoparticle SET for memory applications presented byAzuma 33

Figure I. 12 -

 12 Figure I.12 -11 nanoislands patterned in Si using e-beam lithography for SET based sensors 36

Figure I. 13 -

 13 Figure I.13ion detector based on SETs presented byKudo 35

  Kitade et al. studied Coulomb blockades in multi-island devices with up to 60 islands in series. A figure from their paper can be seen in Figure I.15, showing their many islands in series.

Figure I. 15 -

 15 Figure I.15 -Diagram and SET image of series islands fabricated and presented by Kitade 40 Kano et al. mirrored these findings, building series multi-island devices from gold nanoparticles, shown in Figure I.16. They performed electrical measurements and simulations on their results and found that the charging energy of the islands was increased as additional islands were added 41 .

Figure I. 16 -

 16 Figure I.16 -SET formed with two Au islands in series byKano 41

  .

Figure I. 17 -

 17 Figure I.17 -Basic flash memory structure (right) and reading/writing mechanism (left) presented by Bez 43

Figure I. 19 -

 19 Figure I.19 -Pt nanoparticle memory cells fabricated and demonstrated by Liu 45 Liu et al. presented very similar structures, shown in Figure I.19, fabricating Pt nanoparticles on top of Al2O3, both grown via ALD, and encapsulating them in ALD grown HfO2[START_REF] Liu | Nonvolatile memory capacitors based on Al2O3 tunneling and HfO2 blocking layers with charge storage in atomic-layer-deposited Pt nanocrystals[END_REF] . They conclude that encapsulated Pt nano-island arrays are well suited for high-density memory applications, and that ALD is a great technique for forming these structures.

Figure I. 20 -

 20 Figure I.20 -Memristors based synapse fabricated and demonstrated by Jo 48 Neuromorphic computing has especially come into prominence in research fields with the explosion of artificial intelligence research. Jo et al. fabricated memristors made of Si doped with Ag nanoparticles and studied their candidacy as synapses in neuromorphic computing systems 48 . Building crossbar structures with their silver layer sandwiched between, Jo et al. were able to combine these memristors with classic MOS semiconductors to build neuromorphic circuits, shown in Figure I.20. They demonstrated this feasibility by pulsing a bias across these memristors structures and comparing them to the neuron responses of a rat's brain, finding incredibly similar results.

  . An image from their findings is shown in Figure I.21 showing clear and unique island formation at temperatures above 400˚C. Page | 19

Figure I. 21 -

 21 Figure I.21islands formation via Pt thin film dewetting as presented byStrobel 56

57 .

 57 One of the most prolific examples of the advantages and utility of chemical colloidal techniques are quantum dot fabrication. Time and time again, quantum dots have proven their usefulness across every major field of nanotechnology 49,58-64 . Lhuillier et al. impressively demonstrated the versatility of this technique fabricating and comparing CdS, Cu2S, ZnS, CdSe, CdSe/CdS, Cu2Se/Cu2S, and ZnSe, ZnS nanoparticles 64 . Although quantum dots are wont to steal the limelight of colloidal chemical processes, they are also equally capable of producing metallic nanoparticles, as was wonderfully demonstrated by McPeak et al. in their fabrication and study on UV plasmonics of aluminum nanoparticles 63 . Likewise, Narayanan et al. and Temer et al. have demonstrated colloidal techniques for fabricating Pt and Pd 65,66 . Rioux et al. managed to fabricate sub 5nm particles in controllable shapes, with incredibly fine control over dispersion. Their impressive resulting TEM images have been reshown here in Figure I.22 67 .

Figure I. 24

 24 Figure I.24 -A diagram of spatial ALD as shown byPoodt 87

Figure I. 25 -

 25 Figure I.25 -Two works performed on encapsulating ALD grown Pt nanoparticles in ALD grown dielectric matrices. Left) nonvolatile memory from Liu 45 et al. Right) TFT Memory from Cui et al.[START_REF] Cui | Unique UV-Erasable In-Ga-Zn-O TFT Memory With Self-Assembled Pt Nanocrystals[END_REF]

  Figure I.25, showing very conformal growth of their dielectric layers, and strong, clear formation of the Pt nanoparticles.

Figure I. 26 -

 26 Figure I.26 -Pt island growth studies performed by Baker et al. using TEM, XRR, and XPS 100

  Figure I.27.

Figure I. 27 -

 27 Figure I.27 -With ALD Pt cycles fixed to 30, Novak 97 studied the effects of increasing precursor exposure time a-c

  and even shown below 1nm in extreme cases 109 . Images of the incredibly impressive sub 1nm devices fabricated and presented by Fischbein et al. can be seen in Figure I.28. By applying a double exposure and taking advantage of beam scattering, they were able to reach extreme electrode features.

Figure I. 28 -

 28 Figure I.28 -Sub 1nm nanogap electrodes fabricated using double exposure of e-beam lithography presented by Fischbein 109

Figure I. 29 -

 29 Figure I.29 -2nm nanogap electrodes fabricated via STEM lithography presented by Manfrinato 107

Figure I. 30 -

 30 Figure I.30 -Au nanogap electrodes formed via FIB cutting as demonstrated a) down to 5nm by Li 111 b) down to 1.2nm by Cui 112 Focused ion beam (FIB) cutting and patterning has been well demonstrated as a reproducible method for electrode fabrication. Li et al. used a finely tuned Ga+ FIB to cut 5nm nanogaps in pre-patterned gold electrodes, as shown in Figure I.30a 111 . Cui et al. similarly used a finely tuned Ga+ FIB, but cut along the grain boundaries of patterned Au thin films, allowing them to break the electrodes, forming very small gaps down to 1.2nm as shown in Figure I.30b. Much like SEM and TEM based techniques, FIB relies on heavily specialized, and often prohibitively expensive equipment. Once set up and calibrated however, it provides an ideally reproducible method for cutting nanogap structures.

Figure I. 31 -

 31 Figure I.31 -Nanogap arrays fabricated and demonstrated by Ji using nanosphere lithography 113

CHAPTER 1 An

 1 Introduction to Single Electron Transistors and Fabrication Techniques Page | 27 Ji et al. demonstrated arrays of nanogap electrodes with gaps down to 5nm using nanosphere lithography 113 . They started by depositing a monolayer of polystyrene nanospheres on a pre-patterned substrate, and etched the spheres to obtain the exact sizes they wanted. Then they evaporated metal through the gaps left by the spheres, forming controllable arrays of nanogaps over the entire surface. A figure from their paper can be seen in Figure I.31 detailing these steps and showing their resulting structure. Their process resulted in functioning gaps below 10nm with yields of 50%. They postulate that additional improvements can improve both the resolution and yield of gaps. Electromigration is a technique whereby metallic electrodes are placed under an applied bias, resulting in the formation of a gap as the metallic atoms migrate with relation to the electric field. Zhang et al. have presented just such work, shown in Figure I.32 114 . In this work, they created a unique process whereby parallel electrode bridges, seen in image a, were all submitted to bias as shown in image b, whereby each one broke down to form sub 5nm gaps as seen in the inset of image b.

Figure I. 32 -

 32 Figure I.32 -Nanogap electrodes fabricating via electromigration, demonstrated by Zhang 114

Figure I. 33 -

 33 Figure I.33 -Nanogap electrodes fabricated via electrodeposition, demonstrated by Morpurgo 115

Figure I. 34 -

 34 Figure I.34 -The mechanically controlled break junction technique as presented by Reed 116

Figure I. 35 -

 35 Figure I.35shadow edge evaporation diagram from Bai 117 In more recent history, this technique has been used by Philipp et al. in 1999, Dayen et al. in 2000, and Bai et al. in 2007 to push the technique forward, each demonstrating the flexibility of the technique 117,119,120 .

Figure I. 36 -

 36 Figure I.36 -Original shadow edge evaporation technique as illustrated by Dolan 118 A brilliant demonstration of the technique came in 2014, when Rousseau et al. used shadow edge evaporation to form 100nm wide permalloy/Al electrodes with a 6nm gap 121 . This was achieved through a combination of e-beam lithography patterning and e-beam evaporation. Their resulting structure, also used to form Coulomb blockades, can be seen in Figure I.37.

Figure I. 37 -

 37 Figure I.37 -6nm nanogap electrodes fabricated by Rousseau et al. 121

  Photoresist Selection and Lithography Preparation ........................................................ Electron Beam Evaporation Metal and Evaporator Selection ......................................... Reactive Ion Etching -Sample cleaning and Alumina Etching ..................................... 3. Parameter Optimizations for Electrode Formation ................................................................. AZ nLOF 2020 Optimization .......................................................................................... AZ 5214E Optimization and Nanogap Formation .......................................................... III. Platinum Nano-Islands Encapsulated in an Aluminum Oxide Matrix ........................................ 1. Introduction ............................................................................................................................. 2. Matrix and Island Formation ................................................................................................... Atomic Layer Deposition of Aluminum Oxide .............................................................. Platinum Island Growth Techniques ............................................................................... 3. Transmission Electron Microscopy and Platinum Island Study ............................................. TEM Observation ............................................................................................................ RBS Analysis .................................................................................................................. IV. Conclusion .................................................................................................................................. V. Bibliography ...............................................................................................................................

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 41

Figure II. 1 -

 1 Figure II.1 -Block diagram of the shadow edge evaporation technique

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 42

Figure II. 2 -

 2 Figure II.2 -Example of a negative mode photoresist a) process, b) electrode formation via metal evaporation. The yellow/red triangle has been added to emphasize the angled edge of the formed electrode10

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 43

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 45

Figure II. 4 -

 4 Figure II.4 -Sample Holders mounted on sample plate with samples displayed

Figure II. 5 -

 5 Figure II.5 -AFM images of samples showcasing a) mouse-bites and b) surface roughness

Figure II. 8 -

 8 Figure II.8 -SEM images of the first nanogap attempt showing a major defect where the layers have become delaminated. The gap location is enclosed in a white box in each image.

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 53

Figure II. 12 -

 12 Figure II.12 -Analysis of cross section seen in Figure II.11b. Numbers were extracted from the SEM images using ImageJ and recreated here to determine the angles

  Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 54 sloped portion of each gap, with a recreated a diagram of image b seen in Figure II.12 for clarity. These measurements were mapped and used to determine the actual angle of deposition. From the results, seen in Table

  Figure II.13, based on this new understanding. Included in the new diagram were: φ -The offset angle of the base α -The new deposition angle including the offset angle β -The angle of the sloped edge

Figure II. 14 -

 14 Figure II.14 -Gaps formed at 30, 45, and 60˚ vs. their expected values. Values have been fit using the provided formula, graphed in radians to accommodate software

Figure II. 15 -

 15 Figure II.15 -Optimized fabrication process yielding aluminum electrode samples fabricated at the indicated angles with their respective gaps labeled in each These samples can be seen in Figure II.15 and they do a brilliant job of demonstrating the affect the deposition angle has on the resulting gap, as well as indicating the inaccuracies in the angle mounting system we employ. We attempted to fit the, admittedly limited, data points to determine the offset angle as well as the sloped-edge overlap as seen in Figure II.16.

Figure II. 16 -

 16 Figure II.16 -Gaps formed at 30, 45, and 60˚ vs. their expected values. Values have been fit using the provided formula, graphed in radians to accommodate software. Very poor fit indicates basic model will not work

  CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island GrowthPage | 59 keyed into the control program, defining the specific order and procedure with which the gas control should open and close the transfer lines to trigger the intended reactions. We followed the standard recipe provided by Ultratech, which called for the following steps, illustrated in FigureII.18.

  CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 60

Figure

  Figure II.18 -ALD process for AL2O3 adapted from Ultratech28

  CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island GrowthPage | 64 aggregate over time, forming islands. This aggregation continues with further cycles, eventually growing large enough to aggregate into thin films.

  CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island Growth Page | 65

Figure

  Figure II.21 -TEM images of SiO2 TEM grids with a) bare alumina and PEALD Pt deposited at b) 30 cycles c) 45 cycles d) 45 cycles e) 60 cycles and f) High resolution of 60 cycles. Inlays: b-e) histogram of size distribution f) diffraction pattern analysis confirming crystalline Pt

  CHAPTER 2 Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum Island GrowthPage | 66 the Pt growth parameters, we moved to fully integrate these various fabrication processes to build devices for electrical characterization.

Figure

  Figure II.22 -RBS measurements performed on PEALD Pt deposited on 5nm of Al2O3 atop SiO2 wafers at A) 15 cycles B) 30 cycles C) 45 cycles and D) 60 cycles

4 .

 4 Buried Island Structures .......................................................................................................... III. Characterization Methods ........................................................................................................... 1. TEM Thin Lamella Characterization ...................................................................................... 2. Electrical Measurements ......................................................................................................... 3. IV Response Analysis Methods .............................................................................................. IV. Results ......................................................................................................................................... 1. Planar Filled Gap .................................................................................................................... Structural Characterization ............................................................................................. Electrical Results............................................................................................................. 2. Vertical Structures................................................................................................................... Alumina Reference ......................................................................................................... Platinum Island Multistack ............................................................................................. 3. Buried Island Structures .......................................................................................................... Buried Multistack Islands ............................................................................................... Buried Monolayer Islands ............................................................................................. V. Conclusion ................................................................................................................................

Figure III. 3 -

 3 Figure III.3 -Block diagrams of studied planar structures, Left: buried monolayer islands Right: buried multistack islands

  density E = the applied electric field q = electron charge h = Planck's constant φ = the energy barrier height m0 = the free electron mass m* = the effective electron mass in the dielectric μ = carrier mobility Nc = carrier density Kb = Boltzman's constant T = temperature εi = the dielectric constant ε0 = the vacuum permittivity a = mean hopping distance n = electron concentration in conduction band of dielectric ν = frequency of thermal vibrations or electrons at trap sites Ea = activation energy T0 = constant that varies based on gamma value γ = ranges from 0 to 1, with 1 indicating Arrhenius behavior and 0.5 indicating strong Coulomb interactions g=junction conductance gq=quantum conductance j=number of tunneling junctions Ec=energy cost for dipole creation

Figure III. 6 -

 6 Figure III.6 -Conduction model diagrams, adapted from Chiu 1

Figure III. 7 -

 7 Figure III.7 -TEM image of FIB lift-out thin lamella of the planar filled-gap structure. Right: zoom of image for measuring islands, area indicated by red box The resulting thin lamella analysis performed via FIB lift-out and TEM can be seen in Figure III.7. While we had hoped to capture a single parallel row of islands, the actuality proved to be scientifically interesting albeit not as exciting. A block diagram of the final structure can be seen along with dimensions in Figure III.8.

Figure III. 8 -

 8 Figure III.8 -Block diagram of resulting planar filled gap deviceElectrical ResultsThese first full device experiments, comparing a Pt island filled gap to an open-air gap, conclusively demonstrated a change in transport with the introduction of Pt islands. We measured the electrical response of these two devices and plotted the results, seen in Figure III.9. In this configuration both current responses were rather poor, due to having such a large, 50nm gap. The open-air gap, with transport ostensibly occurring through the underlying alumina layer, showed no current at an applied 15V Vds bias. While these first two responses readily presented a clear separation in responses, the null response of the alumina layer did not afford us an ability to perform transport mechanism analysis. Therefore, we applied conduction model fitting to the Pt island device's current response to have a first glimpse at the properties of these metallic nanoparticle matrices.

Figure III. 9 -

 9 Figure III.9 -I-V response of planar filled gap structure with various fit attempts Table III.4 -Poole-Frenkel Fit parameters corresponding to Figure III.9

Figure III. 10 -

 10 Figure III.10 -Vertical structure I-V response curves for (left) Pt island devices and (right) alumina reference devices. Pt island device made with 5 stacks of 2.6nm islands and reference device made with 15nm of alumina.

  Figure III.11 -Alumina reference vertical structure The first measurements performed on reference alumina vertical capacitors, shown again in Figure III.11, yielded fits with very sudden increases in the current, after passing moderately high voltage values.

Figure III. 12 -

 12 Figure III.12 -Fit attempts for reference vertical structures at 280 K and 100 K. 15nm alumina tunneling barrier

Figure

  Figure III.14 -5-layer multistack of 2.6nm Pt islands in a vertical structure configurationWe next investigated the vertical structures, shown again in Figure III.14, built including 5 layers of 50 cycle Pt nanoislands. These islands were later found to be on average 2.6nm in diameter based on measurements on the identical islands from a separate device. These island layers can be seen in FigureIII.18 in the next section. Again, we attempted several fitting mechanisms, presented below, and delved deeper into the mechanism that fit best.

Figure III. 15

 15 Figure III.15 shows two Pt island vertical structure device I-V responses, both at 280 K and at 100 K. Each of the standard fits was attempted, with Poole-Frenkel clearly standing apart above the rest. Next, we used this fit across each of the responses, making note of the parameters found. Fit Attempts & Poole-Frenkel

Figure III. 15 -

 15 Figure III.15 -Fit attempts for Pt island vertical structures at 280 K and 100 K

  .

17

 17

  .

  0

Initial 50 Cycle

 50 Platinum Island Devices 3.1.1.1.

  Figure III.25 -Block diagram of island vs. trap configurations

Figure III. 28 -

 28 Figure III.28 -30 cycle, buried multistack structure formed at an evaporation angle of 45˚. (Left)STEM mode (Right)bright field

29

 29

Figure

  Figure III.33 -I-V response dispersion shown across 7 nanogaps on the same device Poole-Frenkel Performing measurements over a full temperature sweep on device 26 resulted in familiar looking curves, exhibiting largely Poole-Frenkel like shapes. These curves can be seen in Figure III.34 with the corresponding parameters presented in TableIII.9. However, following the improperly fit curves from the previous samples, we begin to see a more pronounced departure from Poole-Frenkel transport that must be noted. While the Poole-Frenkel model fits these curves overall, we can now see that at low applied electric fields, the responses are not fit by Poole-Frenkel at all. Here, the hypotheses made during analysis of the previous samples should be revisited. In the previous fits in Figure III.27 it was proposed that a second conduction mechanism may be present but masked at higher voltages. These new responses reinforce the previous arguments as these responses clearly show a higher current response at 150-300K and a lower current response at low temperatures. We attempted new Poole-Frenkel fits over this shorter voltage range with the results seen in the same figure and table. Over this shorter voltage range, the Poole-Frenkel model was able to conform strongly to the measured responses over the whole temperature range perhaps indicating two separate Poole-Frenkel transport paths.

Figure

  Figure III.34 -I-V response of buried multistack island structure with 30nm gap with PF fits across (left) whole range (right) 0-0.2V

Figure

  Figure III.35 -Absolute value of I-V response with a negative of buried multistack island structure with 30nm gap with PF fits

Figure III. 38 .

 38 The extracted parameters A, B, and C are shown just below

Figure III. 38 -

 38 Figure III.38 -Cotunneling fit applied from 0-0.4V

Figure III. 40 -

 40 Figure III.40 -30 cycle, buried monolayer structure formed at an evaporation angle of 45˚ Electrical Results Starting with 30 Pt cycle buried monolayer island structures, the I-V curve resulting from the measurements can be seen in Figure III.41 and Figure III.43. Looking first at the 30nm gap formed at 45˚, we still see a clear Poole-Frenkel response but find a new departure from the standard fit at low voltages.While the previous results deviating from Poole-Frenkel showed a higher current response than that of the model at higher temperatures, this device provided a response well below the standard PF model across all temperatures. These results point more towards the existence of a series resistance, likely from the contacts themselves. However, the presence of secondary transport mechanisms cannot yet be ruled out, as they may still exist, masked under the combination of the assumed PF conduction and contact resistance. Poole-Frenkel fits were applied over a lower voltage range as well as cotunneling. The former can be seen on the right in Figure III.41 while the latter can be seen in Figure III.42.

  Figure III.41 while the latter can be seen in Figure III.42.

1 .

 1 Transmission Electron Microscope Tomography ................................................................. 2. Three Terminal Electrical Measurements ............................................................................. IV. Results ....................................................................................................................................... 1. Thin Lamella Characterization and Tomography ................................................................. 2. Electrical Measurements ....................................................................................................... Gate Response of Buried Island Multistack Structure .................................................. Gate Response of Buried Multistack with Increased Gap Length ................................ Gate Response of Buried Monolayer Structure ............................................................ V. Discussion of Measurement Results ......................................................................................... VI. Conclusion ................................................................................................................................ VII. Bibliography .........................................................................................................................

Figure IV. 3 -

 3 Figure IV.3 -Electrical measurement showing leakage current beginning at 5.5V, slight measurement artifact visible at 5.5V

Figure IV. 4 -

 4 Figure IV.4 -STEM images of buried island multistack structures: 30nm gap, 1.8nm islands with two devices from the same electrode line a) new unstressed device b) device tested and presented in Chapter 3

Figure IV. 5 -

 5 Figure IV.5 -Reconstructed 3D models of samples centered on the gap. The left image shows a standard view of the thin lamella shown above. The right image is angled looking up into the gap. All oxides are shown in white due to their contract. Aggregate particles are shown in red.

Figure IV. 5

 5 Figure IV.5 shows a 3D model of the buried island multistack sample with 1.8nm islands and a 30nm gap. The model was reconstructed from tomography performed as described above. Due to the contrast edge detection methods of the reconstruction, all oxides have been filtered out and are shown in white. This includes the TiO2 that formed immediately following this thin lamella's exposure to air. Through this new model, we can identify the full geometry of the horizontal Pd electrodes. In image b), a view of the bottom

Figure IV. 9 -

 9 Figure IV.9 -Increased temperature measurements on a 30cycle 30nm gap buried multistack structure at 150 to 170K

Figure IV. 12 -

 12 Figure IV.12 -30cycle 70nm gap buried multistack structure

Figure

  Figure IV.14 -30cycle 30nm gap buried monolayer structure

Figure I. 1 -

 1 Figure I.1 -Schéma de la méthode "shadow edge evaporation"

Figure I. 2 -

 2 Figure I.2 -Exemple d'un procédé de photolithographie a) mode négatif, b) formation d'électrode par évaporation de métal. Le triangle jaune/rouge a été ajouté pour mettre lumière le bord de l'électrode formée Nous avons choisi d'évaluer les résines nLOF2020 et AZ 5214E. Un masque de photolithographie a été spécifiquement conçu à cet effet. Il permet de réaliser un grand nombre de nanogaps par échantillon (252) dont la largeur varie entre 1 µm et 100 µm. Sa particularité est que les deux étapes de photolithographie utilisent ce même masque grâce à une simple rotation de 90°.

Figure I. 3 a

 3 Figure I.3 a montré la disposition des motifs sur le masque : ces motifs correspondent également à ceux qui sont présents au niveau d'un échantillon à l'issue de la première évaporation. Lors de la réalisation de la seconde photolithographie, on fait faire une rotation au masque de 90°. Les motifs obtenus à l'issue de ces deux étapes correspondent à ceux montrés figure I.3b aussi montré en figure I.3c ainsi que visualisés au MEB. Les nanogaps sont obtenus grâce à l'effet d'ombrage induit par les motifs horizontaux (figure I.3e). C'est donc chaque motif vertical, réalisés lors de la 2 nde évaporation, qui définit la largeur des nanogaps (montré en rouge en figure I.3f). Les électrodes de largeur variables induisent donc des nanogaps de largeur variable, dont la largeur est comprise entre 1 et 100 µm.

Figure I. 3 -

 3 Figure I.3 -Masque de lithographie UV a) motif sur le masque b) motif transféré résultant de deux expositions c) image SEM d'un échantillon fabriqué montrant des problèmes de résolution e-f) zooms sur le coin supérieur droit des image a et b. Le décalage final est affiché en rouge

Figure I. 4 -

 4 Figure I.4 -Porte-échantillons montés sur le bâti avec des échantillons affichés

Tableau I. 3 -

 3 Recette standard AZ nLOF 2020 Spin Coating (Speed, Accel, Time, Thickness) 5000 RPM, 3000 RPM/s, 30s, ~1., 60s Lift-off after Evaporation Acetone, 5min sitting + 30s sonication Les premiers résultats expérimentaux obtenus dans les conditions d'utilisation standard de cette résine ont montré des problèmes en termes de régularité des bords et rugosité (figure I.5).

Figure I. 5 -

 5 Figure I.5 -Images AFM d'échantillons montrant a) des « mouse bites » et b) une rugosité de surfaceQuelques améliorations sensibles de la qualité des bords et de la rugosité de la résine ont été obtenues en augmentant le temps d'insolation et la durée du développement. Des problèmes d'arrachement de la 2nde couche d'aluminium déposée se sont néanmoins ajoutés dans la 2 nde partie du procédé de l'évaporation à angle. Compte tenu de meilleurs résultats obtenus avec l'autre résine de type AZ5214E, l'utilisation de la résine NLOF 2020 a finalement été abandonnée au profit de la AZ5214E.AZ 5214E Optimization and Nanogap Formation and analysisLes conditions d'utilisation standard de la résine AZ 5214E sont données dans le tableau I.4. Contrairement à la résine nLof 2020 qui n'est pas très sensible aux variations de température, cette résine, et plus particulièrement son PEB (recuit post-insolation ou post exposure bake) sont extrêmement sensibles ne serait-ce qu'à un écart de 1°C de la température. Le risque est alors que la polymérisation de la résine ne s'effectue pas correctement, menant un développement inégal et à des lignes métalliques mal définies. Dès que les conditions de travail en salle blanche ont pu être

Figure I. 6 -

 6 Figure I.6 -Images AFM d'électrode en Al fabrique avec de la résine AZ 5214E

Figure I. 7 -

 7 Figure I.7 -Image MEB de la section d'un échantillon d'aluminium à 45° montrant un nanogap et deux lignes d'électrodes Les longueurs de gap mesurées sont plus faibles que les longueurs nominales calculées à partir de la formule : h h * Tan cette formule ayant été justifiée au début du paragraphe sur la fabrication des électrodes à nanogaps. La figure I.8 représente schématiquement les angles et dimensions mesurés dans le second cliché de la figure I.7.

Figure I. 8 -

 8 Figure I.8 -Analyse de la section transversale correspondent à figure I.7b.

  Dans ces conditions, la longueur du gap est donné en fonction de la géométrie par :* !"# * $"#Les longueurs de gap nominales et mesurées pour une épaisseur de couche également de 90 nm puis 30 nm sont rapportées sur la figure I.10 tandis que celle obtenues pour des épaisseurs de 50 nm et 30 nm sont rapportées sur la figure I.12 avec les clichés SEM correspondants en figure I.11.

Figure I. 9 -

 9 Figure I.9 -Schéma amélioré de la méthode « shadow edge evaporation »

Figure I. 10 -

 10 Figure I.10 -Analyse des gaps formés à 30, 45 et 60˚.

Figure I. 11 -Figure I. 12 -

 1112 Figure I.11 -Procédé de fabrication optimisé donnant des échantillons d'électrodes en aluminium fabriqués avec différents angles

Figure I. 13 -

 13 Figure I.13 -Image d'un Ultratech FIJI F200 ALD Pour l'alumine, dont le dépôt par ALD est particulièrement bien documenté dans la littérature, le dépôt s'effectue par cycle de deux réactions distinctes et auto-limitantes. Les deux réactifs sont le trymethyl aluminium (TMA) et l'eau.Les différentes étapes d'un dépôt sont illustrées figure I.14. On part d'une surface (par exple Si) sur laquelle de l'eau est adsorbée, formant des groupements hydroxyle (OH). Après avoir mis le substrat dans le réacteur on injecte le premier précurseur TMA (triméthylalumium) dans la chambre. Le triméhylalumium réagit avec les groupements hydroxyle adsorbés sur le Si et produisent du méthane comme produit de la réaction. Le TMA continue à réagir jusqu'à ce que la surface soit passivée (il ne réagit pas avec lui-même). La réaction se termine avec une couche unique. C'est ce qui fait la parfaite uniformité de l'ALD. Le TMA en excès est pompé avec le méthane, produit de la réaction. Après que le TMA et que le méthane aient été pompés, de l'eau sous forme de vapeur est envoyée dans la chambre de réaction. L'eau réagit avec les groupements méthyl (CH3) qui constituent la nouvelle surface en formant des ponts (Al-O) et des groupements hydroxyles (OH). Le méthane est à nouveau un produit de la réaction. Le méthane est ensuite pompé. L'excès de vapeur d'eau ne réagit pas avec les groupements hydroxyles, ce qui cause une passivation parfaite de la surface avec une seule couche atomique. Ce cycle est reproduit autant de fois que nécessaire jusqu'à ce que l'épaisseur de couche désirée soit obtenue, chaque monocouche d'alumine ayant une épaisseur de 0.11nm et est de structure cristalline amorphe.

Figure I. 14 -

 14 Figure I.14 -Procédé ALD pour AL2O3 adapté d'UltratechConcernant le dépôt de nanoparticules de platine, deux méthodes ont été testées : l'une par démouillage d'une très fine couche métallique, et l'autre par dépôt par ALD. La méthode par démouillage, dont les paramètres de recuit de démouillage sous azote sont donnée dans le tableau I.5 pour une couche de 1 nm initialement, a donné des résultats en terme de forme et de taille de nanoparticules plus dispersé que l'ALD (figure I.15) c'est pourquoi cette méthode n'a pas été poursuivie.Tableau I.5 -Procédures RTA pour le démouillage du Pt sur les réseaux TEM

Figure I. 15 -

 15 Figure I.15 -Images TEM de nanoparticule de Pt formées par démouillage en a) alumine seule b) 1 nm de Pt avant recuit c) 400 ° C d) 600 ° C e) 800 ° C et f) 1000 ° C Concernant le dépôt de platine par ALD, le précurseur utilisé est le (methylcyclopentadienyl)trimethylplatinum, ou encore MeCpPt-Me3 (CH3C5H4)Pt(CH3)3. Différentes études, dont une menée par Ultratech et dont des résultats sont donnés figure I.16, ont montré qu'il existait un temps de nucléation avant que le dépôt ne commence réellement en mode thermique mais pas en mode plasma, c'est pourquoi nous nous sommes tournés vers ce type de dépôt, le plasma étant ici un plasma d'oxygène, la température choisie étant 200°C. Le dépôt de platine est de nature différente de celui de l'alumine : le platine ne forme pas de monocouche comme l'alumine mais préférentiellement sur certains sites et il y a agrégation des atomes si la durée du dépôt augmente et formation d'îlots qui finissent par se rejoindre et former une couche si la durée du dépôt est suffisamment élevée.

Figure I. 16 -

 16 Figure I.16 -Épaisseur d'une couche Pt déposé par ALD, en fonction du nombre de cycles de MeCpPt-Me3, dans un ALD FIJI pour diffèrent conditions, sur SiO2

Figure I. 17 -

 17 Figure I.17 -Images TEM de grilles en SiO2 avec a) de l'alumine nue et Pt déposées par PEALD en b) 30 cycles c) 45 cycles d) 45 cycles e) 60 cycles et f) Haute résolution de 60 cycles. Inlays: b-e) histogramme de la distribution de taille f) analyse de la structure de diffraction confirmant le Pt cristallinNous observons que la taille moyenne des nanoparticules croît de 1.7 nm pour 30 cycles à 3 nm pour 45 cycles puis 4-5 nm pour 60 cycles avec une densité de particules dans la gamme 3 à 11. 10 12 particules par cm 2 , ce qui est assez élevé.

Figure II. 1 -

 1 Figure II.1 -Représentation schématique des structures verticales avec, à gauche, une structure MIM référence et, à droite, une structure comportant 5 couches d'îlots de Pt Les caractéristiques Courant-Tension (I-V) des structures verticales de référence et incluant des nanoparticules de Pt sont présentées en figure II.2. Une tendance assez claire apparaît sur ce graphique : l'ajout des nanoparticules de Pt dans la matrice diélectrique d'Al2O3 augmente considérablement le niveau de courant sur toute la gamme de tension et de température.

Figure II. 2 -

 2 Figure II.2 -Caractéristiques Courant-Tension des structures MIM verticales D'après le tableau II.1, il apparaît que la hauteur de barrière Al/Al2O3 est comprise entre 1,75 et 1,90 eV et que la masse effective des porteurs dans l'alumine est de l'ordre de 0,4. La variation significative du niveau de courant avec la température semble provenir principalement d'une augmentation drastique du champ parasite Ep lorsque la température augmente.

  μ la mobilité des porteurs, Nc la densité d'état dans la bande de conduction du milieu diélectrique effectif et Ф le niveau d'énergie des pièges impliqués dans le mécanisme Poole-Frenkel. Tableau II.2 -Paramètres extraits à l'aide du modèle Poole-Frenckel sur la structure incluant des nanoparticules de Pt et εi extraits des courbes d'ajustement théoriques du modèle Poole-Frenkel sur les données expérimentales sont présentés dans le tableau II.2. Nous avons cherché à exploiter la dépendance en température du paramètre A pour extraire la profondeur Ф des pièges impliqués dans le mécanisme Poole-Frenkel. En effet, d'après l'équation (3), le logarithme népérien du paramètre A peut s'exprimer comme suit : du paramètre A est représenté graphiquement en figure II.3 en fonction de l'inverse de la température absolue 1/T.

Figure II. 3 -

 3 Figure II.3 -Représentation du logarithme népérien du paramètre A en fonction de 1/TA partir de la régression linéaire représentée en figure II.3, nous avons extrait une profondeur de piège Ф de l'ordre de 50meV. D'après la littérature, la hauteur de barrière d'une interface Pt/Al2O3 est de l'ordre de 3eV. La valeur extraite de 50 meV est bien inférieure à 3eV ce qui signifie que les îlots de Pt ne joue pas eux-mêmes le rôle de pièges dans le mécanisme Poole-Frenkel. La présence de défauts à l'interface Pt/Al2O3 et/ou dans le volume de la matrice diélectrique d'Al2O3 est donc possiblement à l'origine de ce mécanisme de conduction assisté par pièges.

Figure II. 4 -

 4 Figure II.4 -Représentation schématique d'une structure planaire. Nous avons utilisé le procédé d'évaporation à angle (présenté dans le chapitre précédent) pour développer des structures planaires. Comme indiqué sur la figure II.4, nous avons intégré des électrodes à nanogap directement sur une couche mince d'Al2O3 incluant 5 couches d'îlots de Pt. Les conditions de croissance par ALD de la couche nanostructurée (multicouche Al2O3/îlots de Pt) sont identiques à celles utilisées pour développer la structure verticale décrite dans la section précédente.

Figure

  Figure II.5 -a) Vue en coupe STEM d'une structure planaire, b) Cartographie chimique des éléments Pt, Pd et Ti par EDX.

Figure II. 6 -

 6 Figure II.6 -Caractéristiques Courant-Tension d'une structure planaire sur une gamme de température de 100K à 300K

Figure II. 7 -

 7 Figure II.7 -Comparaison des caractéristiques J-E à 100K des structures verticales et planaires

Figure II. 8 -

 8 Figure II.8 -Illustration schématique de position des pièges dans l'empilement Pt NPs/Al2O3

Figure II. 10 -

 10 Figure II.10 -Caractéristique I-V d'une structure planaire incluant une grille supérieure.

Figure II. 11 -

 11 Figure II.11 -Vues en coupe STEM d'une structure planaire en a) champ sombre et b) champ clair. Deux vues en coupe STEM d'une structure incluant des îlots de Pt de 1,8nm sont présentées en figure II.11. Sur ces deux images, nous pouvons observer distinctement les 5 plans d'îlots intégrés sous un nanogap d'une longueur de 30nm. Ces analyses STEM nous ont également permis de valider le bon alignement de la grille supérieure avec le canal du transistor. Toutefois, une couche très mince d'un matériau inconnu apparaît nettement au fond du nanogap sur la partie supérieure du canal. Au vu du contraste observé sur les images en champ sombre et champ clair, il semblerait que ce matériau inconnu soit du métal. Afin d'identifier la nature chimique de cette couche mince parasite, nous avons réalisé une analyse EDX, présentée en figure II.12. A partir de cette analyse, nous n'avons malheureusement pas pu identifier la nature de ce matériau du fait d'un rapport signal sur bruit trop faible.

Figure II. 12 -

 12 Figure II.12 -Cartographie chimique des éléments Pt, Al, Ti et Pd par EDX. Afin d'avoir une idée plus précise de la morphologie de cette couche mince inconnue, nous avons réalisé de nouvelles images STEM en inclinant la lamelle par rapport au faisceau d'électrons. Un exemple d'image STEM en vue inclinée est présentée en figure II.13. Le matériau inconnu qui semblait être une couche mince continue sur les images STEM en incidence normale est en fait constitué d'agrégats métalliques présentant des diamètres maximum de 4nm.

Figure II. 13 -

 13 Figure II.13 -Vue STEM inclinée d'une structure planaire en champ sombre.

Figure II. 14 -

 14 Figure II.14 -Caractéristiques I-V d'une structure planaire incluant des îlots de 1,8nm avec des courbes d'ajustement Poole-Frenkel sur toute la gamme de tension appliquée (à gauche) et sur la gamme 0-0,2V (à droite) Les caractéristiques I-V des structures planaires incluant des îlots de 1.8nm de diamètre sont présentées en figure II.14. Les ajustements des courbes théoriques issues du modèle Poole-Frenkel sur les données expérimentales donnent des coefficients de détermination R² supérieurs à 0,98. Les paramètres extraits correspondants (cf. tableau II.4) sont d'ailleurs du même ordre de grandeur que ceux obtenus pour les structures précédentes. Cependant, une déviation assez nette apparaît à bas champ et à basse température. Nous avons donc testé de nouveaux ajustements Poole-Frenkel en restreignant la gamme de tension entre 0 et 0,2V. Les paramètres extraits sont présentés dans la partie droite du tableau II.4. Des valeurs de permittivité relative aberrantes (de l'ordre de 4500) ont été obtenues ce qui indique qu'un autre mécanisme de transport, concurrent du mécanisme Poole-Frenkel, apparaît à bas champ et à basse température sur ces structures intégrant des îlots de petite taille.

  testé de nouveaux ajustements sur les données expérimentales obtenues à bas champ à partir de deux autres modèles de transport : le modèle VRH (en anglais, Variable Range Hopping) et un modèle de Cotunneling. D'après la littérature, ces deux mécanismes de Résumé Page | 30 transport ont déjà été observés sur des dispositifs électroniques incluant des réseaux de nanoparticules semiconductrices ou métalliques. D'après le modèle VRH, la résistance électrique R du réseau suit la loi suivante : température, T0 une constante et  une valeur comprise entre 0,5 et 1. Lorsque  vaut 1, la résistance est supposée suivre une loi d'Arrhenius et lorsque   0,5, la résistance dévie fortement d'un comportement de type Arrhenius du fait d'un phénomène de blocage Coulombien.

Figure II. 15 -

 15 Figure II.15 -Résistance de la structure planaire à 0,1V en fonction de la température avec 2 courbes d'ajustement théoriques issues du modèle VRH.

Figure II. 16 -

 16 Figure II.16 -Ajustement des courbes théoriques issues du modèle Cotunneling sur les caractéristiques I-V à bas champ.

Figure III. 1 -

 1 Figure III.1 -Schéma du transistor réalisé avec une électrode de grille supérieure et une électrode de grille inférieure Ces électrodes ont une largeur de 2 μm à 16 μm. Une grille inférieure de Ti / Pd, séparée par une barrière diélectrique d'alumine de 50 nm, a été utilisée comme substrat pour la fabrication des dispositifs. La grille supérieure a été fabriquée en déposant une barrière diélectrique d'alumine à 20 nm de ALD et en utilisant une lithographie UV et une évaporation par faisceau électronique pour déposer respectivement des électrodes Ti / Pd de 5 / 20nm. Le schéma du masque utilisé est présenté à la figure III.2 avec chaque couleur indiquant une couche de masque différente. La couche bleue a été utilisée pour former les électrodes de source et de drain avec un nanogap à leur chevauchement. La couche verte a été utilisée pour former l'électrode de grille. Enfin, la couche violète a été utilisée pour décaper le diélectrique de grille afin de permettre la réalisation des contacts. La grille

Figure III. 1 -

 1 Figure III.1 -Masque de lithographie UV du transistor montrant des pièces en bleu) électrodes de source / drain vert) électrode de grille violette) gravure pour contacts d'électrode. La droite montre un zoom sur l'emplacement de l'électrode de nanogap et de porte elle-mêmeLes dispositifs testés sont résumés dans le tableau III.1. La première famille se compose de dispositifs multicouches enterrés tels que ceux illustrés à la figure III.1. À partir de cette famille de dispositifs, des électrodes avec un gap de 30nm et une largeur de 2 μm, un gap de 30nm et une largeur de 4μm et un gap de 70nm avec une largeur de 2 μm sont comparés. Ceux-ci sont ensuite comparés à un dispositif avec une monocouche enterrée avec un écart standard de 30nm et une largeur de 2 μm.

Figure III. 3 -

 3 Figure III.3 -Images STEM des structures multicouches : espace de 30nm, nanoparticule de 1.8nm avec deux dispositifs situés sur la même ligne d'électrode : a) nouveau composant non stressé, b) dispositif testé et présenté précédemment Nous avons stratégiquement choisi d'effectuer une analyse de tomographie sur une nouvelle électrode provenant de la structure multicouche, fabriquée avec des îlots de 1.8nm et un espace de 30nm. Cet échantillon, formé avec un angle de 45 °, est présenté à la figure III.3a. Premièrement, les nanogaps formés sur la même ligne principale sont largement reproductibles, ce qui entraîne des géométries presque identiques. Deuxièmement, le stress électrique ne semble pas avoir d'effet, éliminant ainsi la possibilité d'une électro-migration sur une échelle mesurable. Troisièmement, le matériau vu à l'intérieur du gap existe sur plusieurs échantillons. Dans l'ensemble, cela a permis de vérifier la reproductibilité de la croissance des ilots et du procédé de réalisation des nanogaps. Bien qu'une grande partie de cette information puisse être perçue à travers l'analyse antérieure de la lamelle mince TEM, la réalisation d'une tomographie complète et d'une reconstruction nous a

Figure III. 4 -

 4 Figure III.4 -Des modèles 3D reconstruits d'échantillons centrés sur le gap. L'image de gauche montre une vue standard de la lamelle mince montrée ci-dessus. L'image de droite est inclinée en regardant le gap. Tous les oxydes sont indiqués en blanc en raison de leur contraste. Les particules de surface sont indiquées en rouge.La figure III.4 montre un modèle 3D de l'échantillon multicouche avec un gap de 30nm. Le modèle a été reconstruit à partir d'une tomographie effectuée comme décrit ci-dessus. En raison des méthodes de détection de bord de contraste de la reconstruction, tous les oxydes ont été filtrés et sont affichés en blanc. Ceci inclut le TiO2 qui s'est formé immédiatement après l'exposition de cette lamelle mince à l'air. Grâce à ce nouveau modèle, nous pouvons identifier la géométrie complète des électrodes Pd horizontales. Dans l'image 4b), on peut voir une vue du côté inférieur de l'espace, en vérifiant l'espacement largement uniforme entre les électrodes. Nous mesurons une distance entre les deux bords de 30 nm. Cette reconstruction a également fourni un moyen d'isoler et d'identifier la nature des agrégats situés directement entre les électrodes. Les plus circulaire de ces agrégats ont une moyenne de 4nm de diamètre, le plus grand mesurant approximativement 20nm de bout en bout. Ces agrégats mettent en évidence l'asymétrie des particules dans le gap, au moins le long de la surface.Caractérisation électrique des composants avec une largeur d'électrode de 2 m Notre premier succès s'est avéré être la réponse la plus forte que nous avons mesurée, trouvée sur le dispositif multicouches à 30 cycles formé à 45 °. Ce dispositif présentait des oscillations claires et reproductibles se révélant sur une gamme de Vds de -350 mV à 350 mV, à des températures de 77K jusqu'à 170K. Ce dispositif avait une électrode de 2μm de large avec un gap

Figure III. 5 -

 5 Figure III.5 -Courbes Ids vs. Vgs pour un composant multicouche 30cycle 30nm gap à différentes tensions Vds , T= 77KPlusieurs courbes IV des résultats obtenus ont été sélectionnées et son présentés sur la figure III.5, pour plusieurs valeurs Vds. La tension de grille a été appliquée aller-retour pour s'assurer de la validité des résultats obtenus.

Figure III. 6 -

 6 Figure III.6 -Réponses IV obtenues à 77 K, Vds varie entre -400mV et 350mV.

Figure III. 7 -

 7 Figure III.7 -Courbes Ids(Vgs) obtenues à températures plus élevées (150-17K) sur un échantillon multicouches 30 cycle, gap= 30nm

Figure III. 8 -

 8 Figure III.8 -Mesures Ids vs. Vgs pour un échantillon mult-couches 30cycle, gap = 30nm gap, largeur de l'électrode 4m, pour plusieurs valeurs, T=77KCaractérisation électrique des composants avec un gap plus important

Figure III. 9 -

 9 Figure III.9 -Echantillon multicouche 30cycle, gap= 60nm.En passant à l'étude des gaps plus importants, nous avons examiné les composants fabriqués avec un angle plus grand de 60 degrés, ce qui a entraîné un écart d'environ 70nm observé à la figure III.9. Ici, un nouveau défi est apparu. Des tensions Vds plus élevées étaient nécessaires pour

Figure III. 10 -

 10 Figure III.10 -Mesures Ids vs. Vgs pour un échantillon multicouche 30cycle, gap= 60nm et largeurs de 2 et 4 m, pour plusieurs tensions Vds, T= 77K.Ici encore, nous pouvons voir une modulation claire et reproductible du courant, mais il est beaucoup plus difficile de conclure sur la présence des oscillations. Nous croyons qu'ils sont toujours le résultat d'un blocage de Coulomb, bien que les mécanismes de conduction secondaires et les capacités concurrentes des îlots commencent à dominer et à supprimer les oscillations. En regardant particulièrement les résultats de l'électrode d'une largeur de 4μm, nous pouvons discerner deux petits pics dans la réponse de courant avec une pente positive. Ces pics correspondent à une période d'environ 2 V, et un rapport de crête à pic de près de 1. Cette nouvelle période conduit à une capacité calculée de grille de 0,08aF, toujours dans une gamme similaire aux échantillons d'avant. Encore une fois, ce niveau de capacité incroyablement petit correspond à la capacité de grille globale.

Figure III. 11 -

 11 Figure III.11 -Echantillon monocouche 30cycle, gap = 30nm La transition entre les dispositifs d'îlots multiples et les dispositifs monocouches (figure III.11), a apporté de nombreuses modifications dans les réponses Id-Vg. L'élimination des quatre autres couches d'îlots de platine a considérablement réduit la réponse actuelle, nécessitant des niveaux de tension similaires à ceux des échantillons multi-coyches avec un gap de 70nm. La figure III.12 montre la réponse Id-Vg pour un dispositif monocouche de 2 μm et 4μm, le gap étant de 30nm.

Figure III. 12 -

 12 Figure III.12 -Mesures Ids vs. Vgs pour un échantillon multicouche 30cycle, gap= 30nm et largeurs de 2 et 4 m, pour plusieurs tensions Vds, T= 77K.

Figure III. 13 -

 13 Figure III.13 -Mesures I-V montrant une conduction de type Poole-Frenkel associée à un mécanisme de conduction supplémentaire En regardant en arrière les tendances observées dans les courbes Id-Vg, lorsque les oscillations observées étaient reproductibles, marquées par la stabilité lors du balayage aller-retour, la période et les tensions de crête correspondantes dépendaient du niveau de la tension drain-source. En outre, lorsque la tension drain-source a été augmentée dans la direction positive ou négative, deux phénomènes ont pu être observés : 1) le rapport crête-crête des oscillations a été réduit et 2) une pente commence à apparaitre à travers les réponses négatives. Ces deux observations sont intéressantes à analyser car elles semblent être liées aux réponses simples I-V sur la structure planaire que nous avons déjà présentée auparavant. Dans ces réponses, montrées à la figure III.13, nous avons vu que bien que la conduction de Poole-Frenkel domine clairement la conduction à travers les nanoparticules, l'ajustement de la conduction était tout à fait différent aux valeurs de tension faible et élevée. Nous avons également vu que si l'ajustement global des courbes est le même à des tensions positives et négatives, le courant était beaucoup plus élevé pour des tensions négatives. En examinant plus en détail les résultats précédents, on a conclu que si Poole-Frenkel est le mécanisme de conduction dominant à travers la matrice des nanoparticules Pt, il n'est pas clair s'il existe deux régimes Poole-Frenkel ou si un autre mécanisme de conduction moins marquant est masqué et ne peut être que vu à de faibles tensions Vds appliquées. Quoi qu'il en soit, il est clair que les blocages de Coulomb se forment sous une tension de grille appliqué par l'une des deux méthodes. Une possibilité est que Poole-Frenkel est le seul mécanisme de conduction et que les défauts activés thermiquement sont chargés électrostatiquement et forment des blocages de Coulomb eux-mêmes. Une autre possibilité est que cette gamme de tension inférieure révèle vraiment un mécanisme de conduction moins visible, comme le cotunneling par exemple, qui contribue au blocage de Coulomb.

  FOLIO ADMINISTRATIF THESE DE L'UNIVERSITE DE LYON OPEREE AU SEIN DE L'INSA LYON NOM : Thomas DATE de SOUTENANCE : 2017-12-15 Prénoms : Daniel TITRE : Réalisation de transistors à un électron par encapsulation d'îlots nanométriques de platine dans une matrice diélectrique en utilisant un procédé ALD NATURE : Doctorat Numéro d'ordre : 2017LYSEI131 Ecole doctorale : Électronique, Électrotechnique, Automatique (EEA) Spécialité : Électronique, Micro et Nano-électronique, Optique et Laser RESUME :

  : Nanotechnology, Nanoelectronics, Single electron transistor, Pt nanoparticles, ALD, Shadow edge evaporation, Nanogap Laboratoire (s) de recherche : Institut des Nanotechnologies de Lyon (INL) Directrice de thèse : Martine le Berre Co-Directeur de thèse : Liviu Militaru Président de jury : Jérémie Grisolia Composition du jury : Tony Kenyon, Christophe Vallée, Lucian Roiban, Martine le Berre, Liviu Militaru, Etienne Puyoo

Table of Contents

 of

Table II . 1 -

 II1 Summary of metal electrode trials and their paired evaporators. The / indicates 'thin sticking layer/electrode'

	Electrode type	Evaporator	Final Verdict
	Aluminum	Alcatel and Edwards	Too malleable for low temp measurements
	Chromium	Edwards	Too malleable for low temp measurements
	Titanium	Alcatel and Edwards	Adhesion and oxidation caused issues
	Chromium/Gold	Edwards	Good candidate, poor evaporator
	Titanium/Platinum	Edwards	Good candidate, poor evaporator
	Titanium/Palladium	Alcatel and Edwards	Best candidate

  .2. II.2 -Table of final metal e-beam evaporation settings. The / indicates 'thin sticking layer/electrode'. The setup was not sensitive enough to give a current readout for Ti or Pd

	Table Metal	1st layer thickness	2nd layer thickness	Chamber Vacuum Level	Deposition Rate E-beam Current
	Al	20-50nm	50-100nm	1E-7 mBar	2Å/s	190mA
	Ti/Pd	5/20nm	5/45nm	1E-7 mBar	2Å/s	~1 turn of knob
						for both

  .3 were used in a Nextral NE 110 RIE

	CHAPTER 2
	Single Electron Transistor Building Blocks: Results on Nanogap Electrode Fabrication and Platinum
	Island Growth
	Page | 47

Table II .

 II 3 -RIE Recipes for substrate cleaning (top) and contact pad cleaning (bottom)

							Voltage
	Gas	Pressure	Vacuum	Power	Load	Tune	Bias	Time
	O2	15 sccm	15 mTorr	60 W	200	6038	200 V	180 s
							Voltage
	Gas	Pressure	Vacuum	Power	Load	Tune	Bias	Time
	CHF3	50 sccm	15 mTorr	75 W	174	6038	150 V	300 s

Table II .

 II 4 -AZ nLOF 2020 standard recipe

	Spin Coating (Speed, Accel, Time, Thickness)	5000 RPM, 3000 RPM/s, 30s, ~1.2μm
	1 st bake	110˚C, 120s
	Contact Type	Hard
	Exposure Dose	66 mJ/cm 2
	PEB	110˚C, 60s
	Development	AZ MIF 726, 60s
	Lift-off after Evaporation	Acetone, 5min sitting + 30s sonication

Table II .

 II 5 -AZ 5214E standard recipe

	Spin Coating (Speed, Accel, Time, Thickness)	5000 RPM, 3000 RPM/s, 30s, ~900nm
	1 st bake	120˚C, 120s
	Contact Type	Hard
	Exposure Dose	45 mJ/cm 2
	PEB	120˚C, 60s
	Flood Exposure	200 mJ/cm 2
	Development	AZ MIF 726, 60s
	Lift-off after Evaporation	Acetone, 5min sitting + 30s sonication

Table II .

 II 6 -Measured and calculated angles and gaps for the series of samples partly shown in Figure II.11. * indicates values measured via SEM and ImageJ

	Sample Angle θ	β (˚)	φ (˚)	Expected Gap (nm) Measured Gap (nm) Gap Loss (nm)
	30˚	20	5	52	10*	42
	45˚a	35*	5*	90	11*	79
	45˚b	20*	5*	90	43*	47
	60˚	30	5	156	95*	61

Table II .

 II 7 -Measured gaps and calculated angles for the series of samples shown in Figure II.15. * indicates values measured via SEM and ImageJ

	Sample Angle θ	β (˚)	φ (˚)	Expected Gap (nm) Measured Gap (nm) Gap Loss (nm)
	30˚	20	5 (est.)	28	6*	22
	45˚	35	5 (est.)	50	10*	40
	60˚	50	5 (est.)	86	20*	66

  1. O2 plasma cleaning of Si/SiO2 substrates (TableII.3) 2. 1 st electrode layer a. UV lithography using AZ 5214E with the mask from Figure II.3 and standard recipe laid out in Table II.5. b. O2 plasma cleaning to remove leftover resist (Table II.3) c. Metal evaporation of Al or Ti/Pd using Alcatel (Table II.2) 3. 2 nd electrode layer a. UV lithography as above, with mask rotated 90˚ (Figure II.3) b. O2 plasma cleaning to remove leftover resist (Table II.3) c. Metal evaporation of Al or Ti/Pd using Alcatel with angled sample holders (Figure II.4, Table II.2). It is imperative not to use sample holder rotating at this stage 4. Top layers a. O2 plasma cleaning to prepare for alumina deposition (Table II.3)

b. Alumina deposition (discussed below) c. optional island deposition (discussed further in next chapter on full devices) d. Gate patterning and deposition (discussed further in next chapter on full devices) e. CHF3 etching to open the contact pads (Table II.3)

Table II .

 II 8 -RTA procedures for Pt dewetting on TEM grids

	Temperature	Ramp Up	Anneal Time	Ramp Down to 100°C	Ramp Down 50°C
	400°C	40s	50s	90s	150s
	600°C	30s	60s	300s	150s
	800°C	30s	60s	260s	160s
	1000°C	30s	60s	300s	150s

Table of Contents

 of

I. Introduction ................................................................................................................................. II. Two Terminal Device Fabrication .............................................................................................. 1. Encapsulated Pt Islands Layers ............................................................................................... 2. Filled Gap Planar Structure ..................................................................................................... 3. Vertical Structures...................................................................................................................

Table III .

 III 1 -Summary of nanoparticle devices built and tested in two-terminal configuration in this section

	Device Name	Configuration	Electrode Type	Active Layer	Conductive Layer
					Composition
	Vertical Reference	Vertical	Al	Alumina	14nm of Al2O3
		Capacitor
	Vertical Multistack	Vertical	Al	5 layers of Pt	50 cycles of Pt each
		Capacitor		Islands	separated by 2.4nm of Al2O3
	Planar Reference	Nanogap	Al	Alumina	24 nm of Al2O3
		Electrodes
	Planar Filled Gap	Nanogap	Al	Monolayer Pt	50 cycles of Pt separated by
		Electrodes		Islands	2.4nm of Al2O3 on each
					electrode side
	Planar Buried	Nanogap	Ti/Pd	5 layers of Pt	50 cycles of Pt each
	Multistack	Electrodes		Islands	separated by 2.4nm of Al2O3
	Planar Buried	Nanogap	Ti/Pd	5 layers of Pt	30 cycles of Pt each
	Multistack	Electrodes		Islands	separated by 2.4nm of Al2O3
	Planar Buried	Nanogap	Ti/Pd	Monolayer Pt	30 cycles of Pt each
	Monolayer	Electrodes		Islands	separated by 2.4nm of Al2O3

Table III .

 III 2 -Condensed summary of nanoparticle devices built and tested in two-terminal configuration in this section

		# of Island
	Layer type	Layers	Island Size / Pt PEALD cycles	Island Spacing with Al2O3
	Monolayer	1	~2.4nm / 50 cycles	3nm
	Monolayer	1	~1.8nm / 30 cycles	2.4nm
	Multistack	5	~2.6nm / 50 cycles	2.4nm
	Multistack	5	~2.3nm / 50 cycles	2.4nm
	Multistack	5	~1.8nm / 30 cycles	2.4nm

Table III .

 III 3 -Standard transport mechanism formulas used for fitting. Adapted from Chiu andBarbottin 1,2

	Model										Formula
	Schottky										-𝑞(𝜑-√	𝑞𝐸 4𝜋𝜺 𝒊 𝜀 0	)
			𝐽 =	120𝑚 * 𝑚 0	𝑇 2 𝑒 (	𝐾 𝑏 𝑇	)
	Fowler-Nordheim						𝐽 =	𝑞 3 𝐸 2 8𝜋h𝑞𝜑	𝑒	(	-8𝜋√2𝑞𝑚 * 3h𝐸	𝜑	3 2 ⁄ )
	Poole-Frenkel						𝐽 = 𝑞μN c 𝐸𝑒	(	-𝑞 𝐾 𝑏 𝑇	)(𝝋 𝑇 -√	𝑞𝐸 𝜋𝜺 𝒊 𝜀 0	)
	Poole-Frenkel Modified for		𝐽 = qE * μN c 𝑒	(	-𝑞𝝋 𝑇 𝐾 𝑏 𝑇	) 𝑒	(	𝑞 𝐾 𝑏 𝑇	√	𝑞𝐸 𝜋𝜺 𝒊 𝜀 0	)
	Fitting	Term in red defined as variable "A" for
											fitting
	Hopping									𝐽 = 𝑞𝑎𝑛𝜈𝑒	(	(𝑞𝑎𝐸)-𝐸 𝑎 𝐾 𝑏 𝑇	)
	Variable Range										𝑅 ∝ 𝑒	((	𝑇 0 𝑇	𝛾 )	)
	Hopping
	(VRH)
	Cotunneling	𝐼~𝑉 𝑗	( 𝑔 𝑞 𝑔	)	𝑗	( 𝑗𝐸 𝑐 𝑒𝑉	) 2𝑗-2	[1 + 𝑗 2 (𝑗 -1) ( 𝑘 𝐵 𝑇 𝑒𝑉	)

2 ]

Table III .

 III

		5 -Fit data for Fowler-Nordheim reference devices
	T (K)	Φ (eV)	m* (me)	Ep (eV)
	280	1.90	0.44	1.5E+08
	250	1.82	0.40	1.0E+08
	200	1.80	0.38	8.7E+07
	150	1.74	0.36	5.4E+07
	100	1.75	0.36	5.3E+07

  .7.

	Table III.7 -Fit parameters corresponding to Figure III.22
	T (K)	A (m -1 .V -1 .s -1 )	εi
	300	1.6E+15	83
	250	3.7E+14	54
	200	6.0E+13	37
	150	1.0E+13	42
	100	8.5E+11	55

  III.35 -Absolute value of I-V response with a negative of buried multistack island structure with 30nm gap with PF fits

	Table III.10 -Fit parameters corresponding to Figure III.35
		T (K)		A (m -1 .V -1 .s -1 )	εi
		300		2.6E+15	20
		250		8.9E+14	22
		150		1.0E+14	36
		100		5.6E+13	69
		77		5.1E+13	114
			Buried Islands Multi-Stack Structure
			30nm gap, 1.8nm NP (30 cycles)
		1E-8	2m electrode Ids vs. Vds
			Poole Frenkel Fit
		1E-9
	(A)
	DrainI	1E-10
		1E-11					300 K 250 K
							150 K
		1E-12					100 K
				Absolute Values at Negative Bias	77 K Fits
		1E-13
			0.0	0.2	0.4	0.6	0.8	1.0
					DrainV (V)

Table III

 III

	CHAPTER 3
	Two-Terminal Platinum Nanoparticle Nanogap Device Characterization
		1E-8	Buried Island Multi-Stack Structure 30nm gap, 1.8nm NP (30 cycles)
			2m electrode
		1E-9	Ids vs. Vds Poole Frenkel Fit
	(A)	1E-10
	DrainI	1E-11					300 K
							250 K
		1E-12					150 K 100 K
							77 K
		1E-13					Fits
		0.0	0.2	0.4	0.6	0.8	1.0
					DrainV (V)
			.11 -Fit parameters corresponding to Figure III.38
		T (K)				A	B	C
		300			4.8E-9	2.8	0.1
		250			2.3E-9	2.7	0.06
		150			6.8E-10	3.2	0.07
		100			6.5E-10	3.9	0.18
		77			4E-10	2.6	0.002
							Page | 104

Table III .

 III 12 -The number of tunneling junction j calculated from the B and C parameters for comparison

	T (K)	j from B	j from C
	300	1.9	5.6
	250	1.9	5.4
	150	2.1	7.8
	100	2.5	13.7
	77	1.8	3.9

1 .s -1 ) εi

  Cotunneling fits were also applied over this lower voltage range with the results seen in Figure III.42 and TableIII.15. The most easily analyzed B parameter falls roughly within the same range as before. In terms of tunneling junction analysis this result would be expected, as the gap and island sizes are all

		300				4.8E+13	69	300	2.4E+13	42
		250				3.7E+13	95	250	1.4E+13	51
		200				2.2E+13	130	200	5.1E+12	53
		150				1.3E+13	198	150	1.9E+12	70
		100				7.3E+12	366	100	3.4E+11	93
		77				5.8E+12	579	77	1.4E+11	121
			Buried Island Monolayer Structure
			30nm gap, 1.8nm NP (30 cycles)
		1E-10	2m electrode
			Ids vs. Vds
			Cotunneling Fit
	(A) DrainI	1E-11						T (K)	300
								250
		1E-12						200
								150
								100
								77
		1E-13						Fits
		0.0	0.5	1.0	1.5	2.0	2.5	3.0
						DrainV (V)
		Figure III.42 -Cotunneling fit applied from 0-1.5V

Table III .

 III 15 -Fit parameters corresponding to FigureIII.42

	T (K)	A	B	C
	300	1.7E-11	2.3	0.06
	250	1.2E-11	2.5	0.09
	200	8.3E-12	2.7	0.06
	150	5.5E-11	2.9	0.07
	100	3.4E-12	3.3	0.004
	77	3.0E-12	3.4	0
	Figure III.43 -I-V response of buried monolayer island structure with 70nm gap with PF fits (green) across whole range and
	(blue) from 0-4V

Table III .

 III 16 -Fit parameters corresponding to FigureIII.43

Table of Contents

 of

I. Introduction ............................................................................................................................... II. Completing the Transistors: Gate Fabrication and Device Preparation .................................... III. Transistor Device Characterization ...........................................................................................

Table IV .

 IV 1 -Summary of transistor devices studied for gating effects

	Device Type	Island Size	Gap Length	Gap
				Width
	Buried multistack	1.8nm	30nm	2μm
	Buried multistack	1.8nm	30nm	4μm
	Buried multistack	1.8nm	70nm	2μm
	Buried monolayer	1.8nm	30nm	2μm

Table A .

 A 1 -E-beam evaporation recipes

	PEALD Platinum Island Recipe
				Chamber
	Metal Al Table A.3 -PEALD Pt recipe Machine Edwards	Vacuum Level 1E-7 mBar	Deposition Rate 2 Å/s	E-beam Current 190mA
	Al	Step	Alcatel Instruction	1E-7 mBar Component # Value Units	2 Å/s	180 mA Verbose Command
	Cr		Edwards flow	5E-7 mBar 0	20 sccm	1.5 Å/s	20mA start Ar flow
	Ti Cr/Au Ti/Pt Ti/Pd Beginning ALD Alumina Recipe Edwards Edwards flow Edwards heater Alcatel heater heater heater stabilize stabilize	5E-7 mBar 5E-7 mBar 1 5E-7 mBar 12 200 c 40 sccm 1E-7 mBar 13 200 c 14 200 c 15 200 c 12 heater 13 heater	0.2 Å/s 1.5 / 1.5 Å/s 0.2 / 1.5 Å/s 2 Å/s	76 mA start Ar flow 20 / 176 mA heating set 76 / 150 mA ~1 turn of knob for each heating set heating set heating set heating check heating check
			stabilize	14			heater	heating check
	Table A.2 -ALD alumina recipe stabilize	15			heater	heating check
	Beginning Pt	Step	Instruction wait flow flow flow flow heater MFCvalve heater wait heater pulse heater wait stabilize flow stabilize wait stabilize plasma stabilize wait wait plasma flow flow flow flow	Component # 0 0 1 1 12 3 13 14 3 15 12 3 13 14 15 0 0 1 3	Value Units 600 sec 20 sccm 60 sccm 40 sccm 200 sccm 200 c 1 openO2 200 c 10 sec 200 c 1 sec 200 c 10 sec heater 20 sccm heater 5 sec heater 300 watt heater 20 sec 600 sec 0 watt 30 sccm 60 sccm 100 sccm 0 sccm	wait before Pt process starts Verbose Command start Ar flow start Ar flow start Ar flow start Ar flow Open O2 Valve heating set wait before Pt heating set pulse Pt heating set wait between heating set flow O2 heating check wait for plasma heating check plasma on heating check wait while plasma is on heating check plasma off wait before Al2O3 process starts safety check flow 0 start Ar flow start Ar flow flow O2 off
	Alumina		wait pulse wait goto wait MFCvalve	27 3	1	10 sec 0.06 sccm 10 sec 30 cycles 10 sec 0 O2 off	wait for Ar flows to stabilize TMA Pulse wait after repeat Pt cycles wait between Close O2 Valve
	End		pulse flow wait flow	0 1	0	0.06 sec 5 sccm 10 sec 10 sccm	reset flows H2O Pulse wait after reset flows
			goto doorpurge	15		24 cycles 0 off	repeat Al2O3 cycles turn off protective door purge
			flow		0		5 sccm	reset flows
	End		flow		1		10 sccm	reset flows
			doorpurge				0 off	turn off protective door purge

Table A .

 A 4 -Full ALD recipe for building alumina encapsulated Pt nanoparticles

	ANNEX
			pulse	1	0.06 sccm	TMA Pulse
			wait			10 sec	wait between
			pulse	0	0.06 sec	H2O Pulse
			wait			10 sec	wait after
			goto	46		24 cycles	repeat Al2O3 cycles
	End	flow flow	0 1		5 sccm 10 sccm	reset flows reset flows
			Step Instruction doorpurge	Component #	Value Units 0 off	Verbose Command
			flow flow	0 1 RÉSUMÉ EN FRANÇAIS 20 sccm 40 sccm	start Ar flow start Ar flow
			heater	12		200 c	heating set
	beginning	heater heater heater stabilize stabilize	13 14 15 12 13		200 c 200 c 200 c heater heater	heating set heating set heating set heating check heating check
			stabilize	14		heater	heating check
			stabilize	15		heater	heating check
		wait wait I. Blocs élémentaires constituant un transistor à un électron : 600 sec wait to stabilize 120 sec wait before Al2O3 process starts
			flow flow Résultats sur la fabrication des électrodes à nanogap et 0 30 sccm start Ar flow 1 100 sccm start Ar flow
	alumina	wait pulse wait pulse	10 sec 0.06 sec 10 sec 0.06 sccm croissance d'îlots de platine 0 1	wait between H2O Pulse wait before Al TMA Pulse
	wait goto Fabrication des électrodes à nanogap 15	10 sec 24 cycles	wait after repeat Al2O3 cycles
			flow	0		5 sccm	reset flows
	flow Choix initiaux pour la photolithographie et de fabrication des électrodes 1 10 sccm	reset flows
			wait			120 sec	wait before Pt process starts
			flow	0		60 sccm	start Ar flow
			flow	1		200 sccm	start Ar flow
			MFCvalve	3		1 openO2	Open O2 Valve
			wait			10 sec	wait before Pt
			pulse	3		1 sec	pulse Pt
			wait			10 sec	wait between
			flow	3		20 sccm	flow O2
			wait			5 sec	wait for plasma
	Pt	plasma			300 watt	plasma on
			wait			20 sec	wait while plasma
			plasma			0 watt	plasma off
			flow	0		60 sccm	safety check flow 0
			flow	3		0 sccm	flow O2 off
			wait			10 sec	wait after
			goto	27 30 or 50 cycles	repeat Pt cycles
			flow	0		20 sccm	reset flows
			flow	1		40 sccm	reset flows
			MFCvalve	3		0 O2 off	Close O2 Valve
			goto	11	0 or 5 cycles	repeat whole stack
	alumina to	finish	wait flow flow wait	0 1		120 sec 30 sccm 100 sccm 10 sec	wait before Al2O3 process starts Ar Ar wait before Al
							Annex Page | 5

  Tableau I.1 -Tableau des paramètres d'évaporation par canon à électron. Le symbole « / » indique un interface « couche d'accroche / électrode mince ».Les raisons qui ont mené à l'abandon de l'utilisation de l'Al au profit de la bicouche Ti/Pd sont de deux types. D'une part il 'est avéré lors des mesures électriques, et plus particulièrement à basse température, que compte tenu de la nature très ductile d'aluminium les contacts étaient particulièrement difficiles à prendre et les électrodes très facilement endommagées. Par ailleurs, au niveau des étapes technologiques, des problèmes de délamination des motifs d'aluminium se sont posés lors du second lift-off, probablement en raison d'une trop bonne adhésion entre la résine et l'aluminium. Le titane seul s'est avéré également trop adhérant, la combinaison Ti/Pd avec une couche d'adhérence de 5 nm pour le Ti s'est avéré donner les meilleurs résultats et a donc été utilisés pour la réalisation des dispositifs.Utilisation de la RIE pour le nettoyage des échantillons et la gravure de l'alumineNous avons fait appel à la gravure ionique réactive à différents stades du procédé de fabrication des échantillons. D'une part un plasma oxygène a été utilisé pour le nettoyage des échantillons avant l'étalement de résine et les dépôts métalliques. Dans les dispositifs de type transistors, une gravure à base de CHF3 a été utilisée pour graver l'alumine et libérer les plots de contact. La RIE utilisée est une Nextral NE 110 et les recettes utilisées sont détaillées dans le tableau I.2. I.2 -Recettes RIE pour le nettoyage du substrat (en haut) et le nettoyage de l'électrode de contact (en bas)

		Tableau Ga	Pressur	Vacuu	Powe	Loa	Tun	Voltag	Tim
	s		e	m	r	d	e	e Bias	e
		O2	15 sccm	15 mTorr	60 W	200	603 8	200 V	180 s
			Pressur	Vacuu	Powe	Loa	Tun	Voltag	Tim
		Gas	e	m	r	d	e	e Bias	e
	3	CHF	50 sccm	15 mTorr	75 W	174	603 8	150 V	300 s
			1st layer	2nd layer	Chamber	Deposition	E-beam
		Metal	thickness	thickness	Vacuum Level	Rate	Current
				50-		1E-7
		Al	20-50nm	100nm		mBar	2Å/s	190mA
		Ti/Pd	5/20nm	5/45nm		1E-7	2Å/s	~1 turn
						mBar		of knob for
								both
								Résumé Page | 6

  Tableau II.1 -Paramètres extraits à l'aide du modèle Fowler-Nordheim sur la structure de référence Concernant la structure verticale incluant des nanoparticules de Pt, nous avons identifié un mécanisme de transport de type Poole-Frenkel. Ce mécanisme de transport implique l'émission thermique de porteurs de charge dans la bande de conduction du diélectrique depuis des niveaux de piège présents dans la bande interdite. Contrairement au mécanisme Fowler-Nordheim qui est limité à l'interface Métal/Isolant, le mécanisme Poole-Frenkel est donc limité dans le volume du diélectrique. L'expression analytique du modèle Poole-Frenkel est :

	T (K)	Φ (eV)		m* (kg)	Ep (eV)
	280	1.90		0.44	1.5E+08
	250	1.82		0.40	1.0E+08
	200	1.80		0.38	8.7E+07
	150	1.74		0.36	5.4E+07
	100	1.75		0.36	5.3E+07
		% <&= ' > ' 23 4	( ? @ A	' B /C D E F (*	;

Table II .

 II 3 -Paramètres extraits pour la structure planaire à partir du modèle Poole-Frenkel

	T (K)	A (m -1 .V -1 .s -1 )	εi
	300	1.6E+15	83
	250	3.7E+14	54
	200	6.0E+13	37
	150	1.0E+13	42
	100	8.5E+11	55

  Tableau III.1 -Résumé des dispositifs de transistors étudiés

	Echantillon	Dimension	Longueur	Largeur
		nanoparticules	du gap	du gap
	Multicouches	1.8nm	30nm	2μm
	Multicouches	1.8nm	30nm	4μm
	Multicouches	1.8nm	70nm	2μm
	Monocouche	1.8nm	30nm	2μm

Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2017LYSEI131/these.pdf © [D. Thomas], [2017], INSA Lyon, tous droits réservés