Alexis Rodrigo
email: rodrigo.iga@st.com

Iga Jadue

Sylvain Engels
email: sylvain.engels@st.com

A Novel Continuous TDC Measurement Technique

Keywords: Amplitude shift keying (ASK) demodulator, nonuniform sampling scheme, asynchronous logic, level-crossing analog-to-digital converters, time-to-digital

This paper presents a novel technique implementing a continuous Time-to-Digital Converter (TDC) measurement circuit that has been used for designing an Event-Based ADC (EB-ADC) implementing a LCSS (Level Crossing Sample Scheme). In the case presented in this brief, the EB-ADC has been connected to a bundled-data asynchronous digital ASK demodulation algorithm module, and has been sent to fabrication using FDSOI 28nm STMicroelectronics technology. For the ASK demodulation implementation purpose, only two crossing levels have been defined. Then, the EB-ADC is composed only by two comparators, one for each level. These comparators were characterized though an electrical simulation and then modeled in SystemVerilog in order to be integrated in a fully digital simulation. Thus, the TDC, its internal elements and the demodulation module has been synthetized and placed and routed, for obtaining the final layout. A post-layout simulation has been executed to validate the whole design and hence the continuous TDC measurement between each consecutive input request events. The obtained demodulation performance of the system has been a BER = 3.33•10 -7 for a bitrate of 6.78 Mbps and SNR greater than 16 dB.

I. INTRODUCTION

Nowadays, smart sensor, IoT cards and all sort of standalone communication devices require very low power consumption implementation solutions, permitting that each battery charge can last for several years. One of the known alternatives for reducing the power consumption is the usage of asynchronous circuits, for taking profit of long idle or sleep periods, one of the main characteristics of these kind of devices.

For implementing a system taking profit of these idle times, a Level Crossing Sample Scheme (LCSS) can be used [START_REF] Bidegaray-Fesquet | Levels, peaks, slopes… which sampling for which purpose?[END_REF] [START_REF] Han | An efficient non-uniform filtering method for level-crossing sampling[END_REF], to generate input events of the system only when new activity occurs. In this case, a new event will be generated on each level crossing, and a measurement of the time elapsed between two consecutives level crossing events must be done. This solution is called Event-Based Analog-to-Digital Converter (EB-ADC). For designing the latter, two main blocks are necessary, the first allowing to detect the level crossings, for example a comparator connected to a Digitalto-Analog converter (DAC) with some already programmed levels in a memory, and the second block permitting to measure the time elapsed between two adjacent events, for example a Time-to-Digital Converter (TDC). The TDC designs found in literature usually measures the time between a start and a stop signal or the time equivalent to a pulse width. This brief presents a continuous time measurement TDC solution, allowing to measure the time between two successive request signal arrival (events) and ensuring the proper reset of the current TDC measurement before accepting a new input request.

II. IMPLEMENTATION

The continuous measurement TDC circuit proposed in this work is presented in Figure 1. This TDC uses a Ring Oscillator (or a high-speed clock) connected to a n-bits counter. This counter is reset on each new input event (reqInTDC), and its current value is saved in the output n-bits register (TimeOut). For ensuring the correct registration of the output time value, a synchronization method has been implemented, using two C-elements in series (C1 and C2), to transmit a rising-edge of the reqInTDC signal, into the delay module, only on a rising edge of the clkRO signal, and consequently a falling-edge of reqInTDC only on a falling-edge of clkRO. This assertion will be only valid if the delay of the path through the C-elements, called d_clkRO_inv is larger than the delay of the path d_clkRO. The latter configuration simplifies and ensures the timing assumption that the clkRO period must be larger than the added delays of C1, C2, the delay line, TDC_ctrl and its interconnections.

The reset mechanism, presented in Figure 2, is the main contribution of this brief. As described before, it commands the reset of the TDC counter only after assuring the correct registration of the current time, and also blocking new event arrivals until the TDC counter was correctly reset. This method mixes a 4-phase WCHB protocol in the handshake signals input (reqIn and ackIn) and a 2-phase handshake CLICK register controller [START_REF] Bidegaray-Fesquet | Levels, peaks, slopes… which sampling for which purpose?[END_REF] modified and shaped for the reset process. This solution uses the phase-decoupled version presented in [START_REF] Mardari | Design and FPGAimplementation of Asynchronous Circuits Using Two-Phase Handshaking[END_REF]. The latter has been modified to activate the reset_counter signal after the input request arrives, and then ensure that the reset has already been executed, verified by an or_tree module, before switching back the input handshake signals to its initial state. Two timing assumptions must be considered for the right operation of this circuit. The first one is when the register R1 returns to its initial state, value 0, we must assure that the propagation of the new initial state of R1 through the Xor1 gate (d_Clk1) is shorter than its propagation through Delay2 (d_Z1) for avoid generating an erroneous rising edge in Clk2. The second timing assumption to consider, using Delay1 is when a new input request arrives, then the rising edge of clk1 produces a switching state in R1, so if the environment response is quicker than the switching state of R2, it will generate a wrong rising edge in Clk1.

III. TESTCHIP AND RESULTS

This continuous measurement TDC implementation has been tested in a real digital event-based ASK demodulation circuit implementation, depicted in Figure 3. For this purpose, a level crossing detector circuit has been implemented using two comparators and two reference voltages, one near gnd (the reference of the circuit) and the other near vdd (the supply voltage of the circuit). The latter has been connected to the continuous measurement TDC to form the EB-ADC. The latter will generate new request events on each level crossing, and the TDC will provide the time measurement between two consecutive events. These measurements are used by a digital demodulation algorithm for obtaining the demodulated output symbols of the system. The resulting symbols are outputted to the test environment using an asynchronous serial communication.

The presented circuit has been conceived in FDSOI 28 nm from STMicroelectronics and delivered for fabrication. Nevertheless, it has not been received back yet. So, for confirming that the designed TDC solutions works in a real circuit implementation, a post-layout simulation of our proposal is presented in Figure 4. These simulations have been executed in a SystemVerilog (SV) ecosystem where the comparators have been characterized through electrical simulations and modelled in SV to be incorporated in a full digital simulation. The RF input signal and its noise model, expressed in Signal-to-Noise Ratio (SNR), has been modelled by replicating the awgn function of python's commpy library [START_REF] Taranalli | CommPy: Digital Communication with Python[END_REF]. The input code of the system is randomly generated in 32-bit packets using urandom function, and the encoding is NRZ. In this result, all the simulations apply a RF input signal with a Modulation Index (MI) of 10% and a carrier frequency at 13.56 MHz. The simulations are limited by the number of error bits, the maximal number of sent bits and the simulation time. In all the testbench simulations, we have set the limits to 20 bit errors, 3,000,000 sent bits and 40 seconds of simulation.

The performance result of the designed testchip is showed in Figure 4, presenting a proper BER v/s SNR performance. A previews solution has been tested under the same simulation environment, observing a BER performance progress around 26 dB. As depicted in Figure 4, the proposed solution obtains a BER enhancement around 15 dB, demonstrating a significant improvement compared to the previous work. As an example, in the simulation where !"#$%& = 2 ' , a BER of 3.33•10 -7 is obtained for ()* ≥ 16,-.

IV. CONCLUSION

This paper proposed a continuous measurement TDC implementation, combining a 4-phase handshake protocol signals to a 2-phase CLICK register controller. This solution ensures in the first place the current time measurement registration, and then the right internal TDC counter reset, before letting the system to continue its normal operation. This proposal was validated using a real implementation of a digital event-based ASK demodulation circuit in FDSOI 28nm technology from STMicroelectronics. This solution uses a bundled-data asynchronous circuit and a demodulation algorithm to process the events and the measurements generated by the designed EB-ADC. The post-layout simulations result depicted in Figure 4 validate the right operation of the proposed TDC, reaching a BER value of 3.33•10 -7 for ()* ≥ 16,-.

Figure 2 :

 2 Figure 2: TDC Reset block implementation. Figure 1: Diagram of the TDC solution.

Figure 1 :

 1 Figure 2: TDC Reset block implementation. Figure 1: Diagram of the TDC solution.

Figure 3 :

 3 Figure 3: Schematic of the implemented testchip.

Figure 4 :

 4 Figure 4: SNR v/s BER performance of the implemented testchip.

ACKNOWLEDGMENT This work has been supported by the CIFRE ANRT/STMicroelectronics (N° 2018/0549) and the LabEx PERSYVAL-Lab (ANR-11-61 LABX-0025-01).


Mohamed Akrarai

Nils Margotat

Gilles Sicard

Laurent Fesquet

A hybrid event-based pixel for low-power image sensing

Keywords: Event-based, trigger, Dynamic Vision Sensor pixel, Time To First Spike pixel

This article presents a hybrid pixel dedicated to event-based image sensors, which suppresses spatial and temporal redundancies. This pixel is a combination between two kinds of pixels, known as TFS and DVS. The first one is able to reduce -associated to a dedicated readout -spatial redundancies, while the second manages the temporal redundancies. Each pixel is classically built with a photodiode but this hybrid structure shares the photodiode between the DVS and the TFS pixels. In our design, 4 TFS pixel photodiodes are shared with 1 DVS pixel, which exploits the average current of the latter. In order to evaluate such a pixel, a comparison is made between a hybrid pixel matrix and a matrix composed of TFS and DVS pixels. The evaluation is made in terms of activity and power but also by analyzing their fill-factor, circuitry and layout. A testchip including the 2 event-based image sensors has been designed in FDSOI 28 nm technology from STMicroelecronics.

I. INTRODUCTION

Asynchronous image sensors introduce a new approach for image acquisition. The approach does not rely on reading the full image at a fixed framerate, like standard CMOS image sensor, but rely on sparsely reading pixels when the pixels fire themselves. Based on an asynchronous logic protocol, the pixels autonomously generate an event when detecting luminance variations or measuring it. Furthermore, such pixels own intrinsic redundancy suppression properties.

One of the pixels is the Time-to-First Spike (TFS), first presented by Shoushun & Bermak [START_REF] Shoushun | A low power CMOS imager, based on time-to-first-spike encoding and fair AER[END_REF], and introduced an implementation of the time-based encoding. A detailed characterization of the pixel was also given in [START_REF] Guo | A Time-to-First-Spike CMOS Image Sensor[END_REF], and various pixel matrix implementations followed, targeting low power image sensor design, for power critical application such as wireless endoscopy [START_REF] Zhang | A low power CMOS image sensor design for wireless endoscopy capsule[END_REF]. Another unique asynchronous pixel is the Dynamic Vision Sensor (DVS) pixel, first presented by Delbruck [START_REF] Lichtsteiner | A 128× 128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor[END_REF]. This pixel detects and reacts to luminance slope changes, and suppresses temporal redundancy internally. Furthermore, in [START_REF] Li | A 132 by 104 10µm-Pixel 250µW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression[END_REF], the same pixel was improved with pre-readout pixel-parallel noise and local spatial redundancy suppression, enabling more data compression. The most utility that can be obtained from the DVS pixel, is by using it as a trigger pixel. In [START_REF] Posch | A QVGA 143dB dynamic range asynchronous address-event PWM dynamic image sensor with lossless pixel-level video compression[END_REF], the DVS pixel is used to trigger a TFS pixel, when there is actual activity (luminance change) in the scene.

Thereby, the image sensor only updates at the end the pixels in the image memory that have a relevant information. The image sensor has a dynamic range of 143 dB, which is a high dynamic range compared to standard CMOS image sensors.

Our idea is built on the work in [START_REF] Posch | A QVGA 143dB dynamic range asynchronous address-event PWM dynamic image sensor with lossless pixel-level video compression[END_REF]. Instead of having 1 DVS triggering one TFS pixel, the average photo-current of 4 TFS pixels is monitored by a unique DVS pixel, placed in the middle of the four TFS. When this pixel detects a significant change compared to a preset threshold, it triggers the four TFS pixels. This architecture results in less events, since averaging 4 photo-currents, will filter single photo-current noise spikes, that might generate a false event. The proposed pixel architecture is compared to a non averaging architecture to highlight its advantages.

The paper is organized as follows. In Section II we present both the DVS and TFS pixels. In section III, we report the different sub-circuits comprising our hybrid pixel architecture. In Section VI, we compare the hybrid pixel architecture, which averages photocurrents to a non averaging triggered approaches through high-level simulations, and power consumption estimations. And finally, Section V concludes on the advantages of such an approach.

II. THE DVS AND TFS PIXELS

The two pixels have different circuits and operating principles, and are the backbone of asynchronous image capture. They both are autonomous. In this section, we highlight the structure of each pixel and how they operate.

A. DVS

This pixel only reacts to a luminance intensity change. Its block schematic is presented in Figure 1a. This pixel uses a switched capacitor differentiator circuit computing the signal derivative (in time), i.e. the voltage difference between two successive samples of the photo-detector voltage, Vp. This difference is compared afterwards to two thresholds to generate ON or OFF events according to the polarity of the slope of Vp. A positive change yields to an ON Event and a negative change to an OFF event. An event is represented by the triplet (Xe; Ye; Pe) where X and Y are the pixel coordinates in the matrix and P is the event polarity (ON or OFF event). Figure 1b presents the signals operating in the pixel. In red, a photodiode current generated with a sinus current source is taken as a simple stimulus emulating a variation of the pixel luminance. The luminance slope changes are detected in the pixel thanks to a differentiator circuit, which translates to Vdiff spikes (Green). The latter go into two comparators to generate ON (blue) or OFF (Orange) events. The reset signal is used after the detection of an event to clear the request, and drive Vdiff back to its reset level, before the next detection. The full circuit schematic of the pixel will be presented in the sequel. In our hybrid pixel architecture, the DVS pixel events are only used to trigger the TFS pixels when there is a sufficient luminance change. Then, the TFS pixels start measuring the luminance.

B. TFS

This pixel operates as a one level-crossing sampling circuit. When the photodiode voltage Vph crosses an externally defined threshold, an event is generated. The pixel event is the logical address coordinates of the pixel in the pixel matrix. This is known as the Address Event Representation (AER). In order to translate this event into a gray level information, an external Time-to-Digital Converter (TDC) is used. The TDC generates the instant at which it received the event coded in a bit vector depending on the image resolution. In order to activate and communicate an event, a pixel exchanges the following signals with an external readout system (see Fig. 3 and2): generate AER events through the signal buses RowReq and ColReq, which writes at the output of the AER interfaces RowReq(0,...,1,1,0) and ColReq(0,1,1,...,0) . However, when the readout system will receive the AER address, it interprets the address, as if pixels (3,2),(3,3),(2,2) and (2,3) have all fired. To mitigate this, the readout system checks the local request of each pixel amongst the four, to verify if they truly fired or not. The verification process is mandatory since, our AER request communication is used without any arbitration, which is the strength of our approach. Using arbiters introduces many issues, such as a limited event bandwidth, a reduced scalability and inaccurate luminance measurements. The verification process solves the AER address conflicts. Even if the Fig. 3: TFS pixel communication signals Fig. 4: Pixel matrix view illustrating the need for verification verification is a sequential process, this approach is particularly interesting because it suppresses the risk of time measurement errors due to the arbitration tree. Indeed, this latter delays the requests inducing an inaccurate time stamping. Notice that the verification sequence is really fast compared to the photodiode integration time, which is several order of magnitudes slower. Thus, the verification speed is not an issue for such image sensors.

III. THE HYBRID PIXELS

In this Section, we present the hybrid pixels and the averaging circuit schematics and layouts. Using one DVS pixel -without photodiode -to trigger the surrounding 4 TFS pixels, has many advantages over a non averaging trigger approach. This is carefully examined in the sequel.

A. The averaging pixel architecture

As we already mentioned in the paper, the circuit is a DVS pixel carefully placed and routed in the middle of the four TFS pixels. This DVS pixel has no photodiode. This latter has been advantageously replaced by the average photocurrent of the 4 surrounding TFS photodiodes. Figure 5 below displays the block schematic of the global circuit. The circuit contains the 4 TFS pixels with their photodiodes, a DVS pixel without a photodiode but with the averaging circuit, and some asynchronous logic. Each component is detailed in separate subsections. The averaged photo-currents are copied using 4 currentmirrors on each TFS pixel photodiode. The sum of the currents is then fed to the DVS pixel, thanks to a final current-mirror circuit. All current-mirrors are balanced. Thus, the averaged photo-current sum is multiplied by a gain G cm of 4.

I dvs = G cm 4 n=1 I phn 4 (1)
Fig. 6: Averaging circuit(net1 and Vin link to the DVS pixel)

Figure 6 shows how the current mirrors are linked to the photodiode of the pixels. In each TFS pixel, the currentmirrors are PMOS transistors, in order to be mounted on top of the reset transistors. On the other hand, the DVS pixel receives the sum of the photo-currents using an NMOS current-mirror replacing its "own" photodiode.

C. The DVS pixel part

The circuitry of the pixel is completely standard to [START_REF] Lichtsteiner | A 128× 128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor[END_REF]. Figure 7 below presents the full schematic of the pixel.

• Transistors M1 and M2 constitute the last stage of the current mirror, form the past circuit. and M14, M15 output the ON and OFF events, by comparing Vdiff against global thresholds Voff and Von. In the pixel, the amplification gain is given by the capacitor ratio C 1 /C 2 . At the differentiator output, the luminance is expressed as follows:

V dif f ∼ C 1 C 2 .∆ log(I ph ) (2)
Note that gain introduced prior to the logarithmic compressor stage is cancelled by the differentiator circuit. Finally, the third part of Figure 8 shows all the TFS pixel NMOS transistors pulling down the buses when a pixel needs to send a request to the readout system. At the bottom of every pixel matrix row and column, there is a PMOS transistor for each bus. This latter pulls up the the buses when there is no pixel requests in the rows and columns.

E. The trigger

This circuit (see Fig. 9) connecting the DVS pixel and the 4 TFS pixels, is comprised of 4 C-elements, one for each TFS pixel (a), it is an asynchronous logic circuit memorizing the DVS trigger signal. The trigger also comprise a circuit that controls of the DVS pixel reset (b). Sub-figure (c) details the signals sequence of a trigger:

• The circuit starts functioning when both \DVSLocalReset and \ResetDVS are inactive (high). Once the DVS detects an event, ON or OFF signals start to output events, then the signal \ON TFSi becomes low through the C element, and all four TFS pixel starts photo-integration. • The first TFS pixel to successfully integrate and save an event, will be verified by the readout system. And when verified, the signal CmdPos will go up to confirm the presence of a local request. Following this, the signal \DVSLocalReset is pulled down and LocalReset goes up, so that both the DVS and the firing pixel are reset. • The 3 other TFS pixels continue integrating until they fire an event. Then they follow the same process described above. By switching the Reset mode, the pixels work in global reset mode. They follow the same trigger and integration process, except that the TFS pixels are prevented from autoreseting, and wait for the global synchronization signal Glob-alReset to start another cycle. The design of the pixel architecture described in the past sections, was done in 28 nm FDSOI technology from STMicroelectronics. Here, we present the physical implementation of our pixels, and the circuits.

A. Pixels and circuits design

In order to validate the advantages of an average trigger pixel architecture, we designed another pixel matrix with a trigger architecture that does not use an averaging circuit, but solely relies on a full DVS pixel with it's photodiode. In this non averaging architecture only 1 DVS pixel and 3 TFS pixels are routable in the same area as the averaging architecture. Figure 10 displays the layouts of both averaging and non-averaging architectures. We can see that on the left, the averaging architecture enables the insertion of one more TFS pixel (we presented the 1 DVS / 4 TFS architecture in the previous sections), compared to the non-averaging architecture. This is mainly due to the need of maintaining a symmetrical photo sensitive area implementation. Which increases the fill factor (table I) for the averaging architecture. throughout the rest of the paper, we will refer to the averaging pixel architecture with 1 DVS and 4 TFS pixels as the kernel (Av), the non averaging architecture will be referred to as kernel the (NAv).

B. Determination of the Event Rates

The power consumption of each pixel architecture, was estimated using post layout simulation data of the TFS and DVS pixels, as well as the event rate estimation of there highlevel pixel matrices simulations for different kinds of stimuli. In matlab, we designed behavioral models of the two pixels to serve as building blocks of the higher level model of the pixel matrices. The models of the pixel matrices were fed by stimuli extracted from two scenarios: the first one is a car driving on the road (High activity scene 11a) and the second is a parked car with almost no activity, only a person walking in front of the car for a few seconds (Low activity scene 11b). The duration of stimuli is 10 seconds in each scenario. The matlab simulations output the following: kernel (NAv), generated 168k events (road) and 4,4K events (parking), while kernel (Av) generated 78K events (road) and 2,1K events (parking) (see figure 12). The data collected from the simulations were used to calculate the total power consumption of the pixel matrices (table II). The collected data from the matlab simulation also yields an approximation of the Signal to Noise Ratio (SNR) of our pixel architectures: for the nonaveraging (NAv), the SNR is approximately 11 dB, while the for the averaging pixel architecture the SNR is 20 dB. This can be mostly attributed to the area difference of the photosensitive part and to the averaging.

C. Image Sensor Power Estimation

The estimated power consumption of the two pixels was obtained by dividing the total number of events of the original image (with a larger resolution) by the resolution of each pixel matrix. Indeed, our pixel matrix in Figure 10a has an effective resolution of 4x32x32 pixels (32x32 kernels with 4 TFS pixels each), while pixel matrix in Figure 10b has an effective resolution of 3x32x32 (32x32 kernels with 3 TFS pixel each). This yields to the average number of events generated for a single TFS pixel. The pixels are simulated post-layout to measure their power consumption and the result is multiplied by the number of events to approximate the power consumed by each DVS/TFS pixel. This average power consumption per pixel is then multiplied again by the resolution of the pixel matrices. Table II summarizes the power consumption of the pixels and matrices. Even though the averaging architecture is a few more complex (1 DVS pixel + 4 TFS pixels + an averaging block and a trigger) compared to the non-averaging architecture (that only contains 1 DVS pixel + 3 TFS pixels and the trigger), the table II highlights that the averaging pixel architecture reduces the event throughput, consumes less with high activity scenarios and a little bit more during low activity scenes. This is due to the photodiode integration of the TFS pixels, which becomes during the quiet scenes.

V. CONCLUSION

The presented hybrid event-based architecture, is based on the combination of two event-based pixels (TFS and DVS). This architecture has proven limiting the firing rate of the pixels, since it only measures luminance when there is relevant information in the scene. This architecture also enhances the fill factor of the pixel matrix, because the full photo-sensitive area is used for measuring luminance compared to the nonaveraging pixel architecture, which is only uses 3 of the 4 photodiodes for luminance acquisition. The hybrid pixel also shows better performances in terms power consumption when there is activity in the scene. This is due to the reduced number of events produced by this new pixel. The image quality is clearly increased because there is 33% more photodiodes in the averaging matrix for the same area with no geometrical distortion, thanks to a regular padding. Notice that the SNR is also improved by the averaging kernel.

Two image sensors, one with the hybrid averaging kernel and the other one with the non-averaging kernel, have been designed in FDSOI 28 nm from STMicroelectrtonics. The testchip is currently under fabrication and will be integrated on a camera testboard for measurements, which could confirm our simulations and analyzes more easily and more accurately the power consumption with several scenarios.

  (a) DVS block schematic (b) DVS pixel analog simulation

Fig. 1 :

 1 Fig. 1: DVS pixel

•

  the pixel starts with the signals localReset, Global reset and ON TFS inactive. • Once the DVS pixel trigger is active using the ON TFS (going to 0), the TFS pixel notifies the external readout of the start of photo-integration, by driving the two signals RowStart and ColStart. • Once the photodiode voltage level crosses an externally defined threshold, the comparator drives the TFSComp signal to go down (active), and the latter drives the RowReq and ColReq signals to go up while at the same time, it saves a local request through the signal ReqLoc. • The readout system (RS) detects the prior request signals on the row and column buses, and sends the acknowledge signals RowAck and ColAck acknowledging the pixel requests. • After the pixel receives the acknowledgement signals, it deactivates the request signals RowReq and ColReq. • Afterwards, the readout system proceeds to the verification process, by setting the RowVerif and ColVerif signals. The pixel receives the latter signals and checks its local request memory. If the ReqLoc signal is up, the response signal PxPos will be pulled down to signal the presence of a request. If instead there is no local request, and the pixel is still integrating, signal PxOn will go up, to signal the ongoing integration.

Fig. 2 :

 2 Fig. 2: TFS pixel block schematic

Fig. 5 :

 5 Fig. 5: Abstracted full circuit schematic B. the averaging circuit

  • M4, M5 and M6 form an inverting amplifier with external polarization for testing purposes, which feeds back to the logarithmic compressor M3. • M7 and M8 form a source follower isolating the previous stages of the circuit from the switching of the next stage (differentiator circuit). • Transistors M9, M10, M11 and capacitors C1 and C2 constitute the switch capacitor differentiator circuit performing the luminance change detection. • The ON and OFF comparators composed of M12, M13

Fig. 7 :

 7 Fig. 7: DVS pixel schematic D. The 4 TFS pixels The schematic of figure 8 is divided into three sections. The first one is the analog part of the pixel, the second is the digital part, and the last represents the bus connections. In the first part: • The first transistor M1 resets the photodiode whenever it receives the PixelReset signal from the digital part of the pixel. • Transistors M2 and M3 constitute the current-mirror copying the photo-current from the photodiode to the averaging circuit. • M4, M5, M6 and M7 constitute the comparator circuit. It detects the threshold crossing VComplvl after the photointegration starts (once started, the photodiode voltage decreases).

Fig. 9 :

 9 Fig. 9: Trigger logic circuit and signals diagram

  Fig. 10: The two designed pixel matrices Averaging Non averaging Photo-measurement area (µm 2 ) 3x3x4 3x3x3 Area(µm 2 ) 16.5x15 16.5x15 Fill factor (%) 14.5 10.4

  Fig. 11: The simulation test cases

Fig. 12 :

 12 Fig. 12: Total numbers of events generated during 10 seconds of stimulus

TABLE I :

 I Averaging and non averaging physical implementation comparison

TABLE II :

 II Power consumption results


Jérémy Belot

Abdelkarim Cherkaoui

Raphaël Laurent

Laurent Fesquet

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study

Recently, Stochastic Computing has sparked interest in Bayesian inference resolution for its promising efficiency in area and power consumption. This representation encodes values by the rate of bits at '1' in a bit-stream. Still, in a sequential architecture, most of the energy cost is due to the long computation time required for achieving a satisfying accuracy. In this paper, we propose a multi-rail architecture for Bayesian sensor fusion problems based on a Shift Register Isolator and permutations in order to reduce the computation time and thus, the energy consumption, without a significant increase in area. Indeed, with this resource sharing strategy, we are able to reduce the energy consumption by up to 73% in return for an area overhead of 24%, while maintaining the computation accuracy.

I. INTRODUCTION

In recent years, the advent of the Internet of Things and the energy constraints of these systems have brought to the fore sensor fusion solutions. These circuits reduce, at the closest to the sensor, a raw data flow into a few relevant information, saving unnecessary data transmission and thus power consumption. Bayesian inference appears to be a good way to build fault-tolerant and explainable models for sensor fusion. Recently, architectures based on Stochastic Computing (SC), a non-standard representation introduced in 1956 by Von Neumann [START_REF] Fesquet | Probabilistic logics and the synthesis of reliable organisms from unreliable components[END_REF] and later developed by Gaines [START_REF] Gaines | Stochastic computing[END_REF], have been successfully used to implement sensor fusion models and temporal filters [START_REF] Faix | Cognitive computation: a bayesian machine case study[END_REF]- [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF].

In unipolar representation, such circuits encode values by the rate of bits at '1' in a bit-stream. This approach is particularly interesting to perform, at a low logical cost, demanding computations in standard representation, such as multiplication. Indeed, the multiplication between two independent stochastic bit-streams can be performed with a simple AND-gate. For example, let s 0 = 1011101000101011 and s 1 = 1000100101110010 be two unipolar stochastic bitstreams, representing the values P (s 0 ) = 9 16 and P (s 1 ) = 7 16 . Their AND gated bit-stream is s 0 ∧ s 1 = 1000100000100010 and P (s 0 ∧ s 1 ) = 4 16 9 16 × 7 16 = 63 256 . Of course, the longer the bit-streams, the better the accuracy.

In order to make these bit-streams independent, they are generated using Stochastic Number Generators (SNGs) that are generally composed by:

• a Random Number Generator (RNG), usually a Linear-Feedback Shift Register (LFSR) for its low area and power consumption, that provides the bit-stream independence if the seeds are chosen wisely; • a Binary to Stochastic Converter (BSC), usually a comparator, that encodes a binary value into a bit-stream thanks to the generated random numbers.

These SNGs are responsible of the major part of SC circuit power consumption and area. Several works have successfully found ways to reduce this impact [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF]- [START_REF] Yang | Towards theoretical cost limit of stochastic number generators for stochastic computing[END_REF], but this is not the main purpose of this paper.

The conversion from the stochastic to the standard representation is done with a counter reckoning the number of '1' in the output bit-stream, and another one reckoning the Stochastic Bit-stream Length (SBL). The results correspond therefore to the ratio between the number of '1' and the SBL.

Such SC circuits can be implemented following two ways:

• Sequentially and single-rail: each bit-stream is singlewired, and each bit that composes it is generated at a different clock cycle. This is the most efficient strategy in terms of area and instantaneous power. However, this implies long computation time, especially when the wanted accuracy is high, which increases the energy consumption. • Fully parallel: as in [START_REF] Kim | An energy-efficient random number generator for stochastic circuits[END_REF], each bit-stream is a bus, and each bit that makes it up is generated in the same clock cycle. This implementation allows the calculation to be performed in a single clock cycle, which can be interesting in terms of energy efficiency, if the required accuracy is not too high, but at the price of a larger area and instantaneous power consumption. Moreover, in the case of dedicated circuits to Bayesian sensor fusion, the required accuracy strongly depends on the application and is sometimes wanted configurable. Therefore, the fully parallel implementation could not be suitable.

In this paper, we propose a hybrid solution, sequential and multi-rails taking advantage of both techniques, reducing computation time and energy while keeping comparable area and accuracy thanks to an implementation sharing resources. Firstly, we present the different works useful to introduce our solution. Then, we describe the proposed architecture and its specificities. Finally, we proceed to measurements and comparisons in terms of accuracy, computing time, area and energy consumption.

II. RELATED WORKS

A. Stochastic circuits for Bayesian sensor fusion

In a Bayesian sensor fusion model, a state variable S is usually inferred from n independent sensor readings K j using sensor models P (K j |S) thanks to Bayes' theorem [START_REF] Bessiere | Bayesian programming[END_REF]:

P (S| ∧ n j=1 K j ) ∝ P (S) n j=1 P (K j |S) (1)
The probability distribution P (S), usually called prior, encodes a priori knowledge about the state S. The conditional probability distribution P (K j |S) on sensor reading K j knowing the state S, called a likelihood, encodes knowledge related to a physical model of the sensor.

When S is a discrete variable with cardinal m, and given a set {k 1 , . . . , k n } of acquired sensor samples, for each 1 ≤ i ≤ m, Eq. 1 becomes:

P (S = s i |∧ n j=1 K j = k j ) ∝ P (S = s i ) n j=1 P (K j = k j |S = s i )
(2) As the inference of Eq. 2 only involves computing products, it may be efficiently implemented as a multiplication matrix of 1+n columns (for the prior and the likelihoods) computing in parallel on m rows the posterior distribution for all values of S [START_REF] Coninx | Bayesian sensor fusion with fast and low power stochastic circuits[END_REF].

When a new sample k is acquired, the likelihood P (K j = k j |S = s i ) is read from memory. Then, this value is converted into a bit-stream with the corresponding probability thanks to a BSC and a RNG. Since rows are independent, it is possible to share one RNG per column. Thus, only n + 1 independent numbers are needed to generate m * (n + 1) stochastic bitstreams.

Fig. 2 shows the architecture of our Bayesian sensor fusion circuit. The independent random numbers are given by the shift register, as proposed in [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF] and developed in the next subsection.

B. Architecture for sharing stochastic resources

In [START_REF] Chen | Analyzing and controlling accuracy in stochastic circuits[END_REF], Chen et al. introduce the notion of stochastic isolation in order to reuse one RNG over several bit-streams and thus save area and power consumption. To do so, they use registers (isolators) to create new bit-streams from others. These new bit-streams are shifted by one clock cycle in time and can therefore be considered as independent of the original ones. In counterpart, this single RNG has to show low autocorrelation properties to maintain original accuracy, and must be more sophisticated than a simple LFSR.

In [START_REF] Yang | Towards theoretical cost limit of stochastic number generators for stochastic computing[END_REF], Yang et al. propose a power and area efficient way to use the Weighted Binary Generator (WBG), a BSC introduced by Gupta et al. in [START_REF] Gupta | Binary multiplication with pn sequences[END_REF]. As shown in Fig. 1, the WBG has a part, the Weight Generator (WG), which does not depend on the binary value to be encoded. Thus, just like RNGs, these WGs can be shared over each computationally independent bitstream (rows in our case), as shown in Fig. 2. The second part, the Probability Encoder (PE), replaces the standard comparator in each cell of the matrix and, since it is smaller, this solution saves area and power consumption. Taking advantage of these two works, in [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF], Belot et al. propose a Shifted Register Isolator (SRI), which does not place the isolation at the bit-stream level anymore, but at the random number level. This becomes more interesting than Chen et al.'s isolators [START_REF] Chen | Analyzing and controlling accuracy in stochastic circuits[END_REF] when the size of the random numbers is smaller than the number of independent computations (number of rows here). It also implements a single WG for the whole circuit as shown in Fig. 2.

III. A MULTI-RAIL SEQUENTIAL SC ARCHITECTURE

In this paper, we propose a sequential and multi-rail architecture that further reduces the energy consumption compared to a single-rail one, without significantly increasing the SC circuit area. Moreover, this partially parallel architecture allows a compromise between area and energy consumption, which is not possible in the fully parallel architecture presented in [START_REF] Kim | An energy-efficient random number generator for stochastic circuits[END_REF]. The proposed architecture is described in Fig. 3. In this proposition, each row is split in n rails, n ∈ N * , which multiplies the number of AND-gates and PEs. The counters are modified to add more than one bit per clock cycle, and the likelihood registers are shared between the rails.

The different random numbers required for each rail are generated without any additional cost by simply permuting the outputs of the SRI between the columns. Thus, each rail in a row produces an independent bit-stream since they get different random number as input. This is done with a negligible accuracy loss until a certain number of rails. This matter is discussed in Sec. IV-A.

Moreover, one can notice that the architecture is also slightly different from the one presented in [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF]. We indeed optimize it with additional registers just after the WG in order to remove glitches occurring in PEs and thus reduce the power consumption. We also compressed the data in the shift-register in order to decrease the number of used registers. It is possible to do so since the output of the WG is redundant. Indeed, at each clock cycle, its output has always only one bit at '1' and the others are '0'. So we can encode the position of the bit at '1' instead of the whole output, and then implement only log 2 (n bit ) registers for each stage of the shift-register, instead of n bit (3 instead of 8 in our case).

In conclusion, the implementation of additional rails leads to an increase in area and power consumption. However, since many resources are shared between the rails (RNG, WG, SRI, likelihood registers), this is offset by the reduction of the computation time, allowing energy savings, as shown in Sec. IV-B.

IV. ACCURACY, AREA AND ENERGY COMPARISONS

A. Accuracy measurement and columns permutations

In order to determine the best sets of columns permutations minimizing the accuracy losses, a software simulation of the circuit has been performed in C language. The software simulation is carried out with randomized RNG seeds and likelihoods data. We use a variable SBL, 8 columns, and as many rows as possible to get a good accuracy measurement in an acceptable simulation time (around 30000 rows).

We measure the accuracy by comparing the resulting distribution of our SC circuit P stoc with the one computed with floating point (reference) P float using the Kullback-Leibler Divergence (KLD), defined in Eq. 3.

D KL (P stoc P float ) = m j=1 P stoc (j) log P stoc (j) P float (j) (3)
The KLD is always positive and the lower it is, the closer the two distributions are, so the better is the given permutation.

We first measure the precision (KLD) with 2 rails in an exhaustive way for all the 8! = 40320 possible permutations. We therefore have a set of measurements that reflect the pairwise impact of column permutations on accuracy, independently of the data. Using these measurements, we built an algorithm that is able to select the permutations minimizing their pairwise correlation for a given number of rails. Then, the accuracy (KLD) is measured to ensure that it remains approximately the same than before permutation. After that, the selected set of permutations is directly hard-coded in the circuit. This method represents a huge saving in simulation time, the exhaustive way becoming quickly intractable with a running time proportional to (8!) n rails .

For the sake of fair comparison, for the following, we wish to achieve the same KLD as the single-rail architecture, so that we can compare energy consumption at equal precision. We therefore have to slightly increase the multi-rail SBLs instead of simply dividing the single-rail SBL by the number of rails. In consequence, this accuracy correction slightly increases the energy consumption.

Table I shows the different SBL necessary to reach certain values of precision depending on the number of rails. We see that the greater the number of rails, the more cycles must be added to the ideal SBL SBL 1rail nb rails to reach the reference KLD. Furthermore, the increase of the number of permutations seems limiting the circuit to reach high precision, as shown in the last row of Tab. I. Indeed, the number of additional required cycles becomes very large, more than 1000 cycles when using more than 4 rails. These points show, despite our efforts to limit them, the negative impact of permutations on the accuracy, which must be compensated by a higher SBL and therefore a higher energy consumption.

B. Area and energy consumption measurement

The following hardware results in terms of area and energy consumption are gathered with a STMicroelectronics 65 nm • The likelihoods are encoded with 8 bits, as well as the random inputs of the PEs, and thanks to the compression, the SRI is coded on 3 bits; • The RNG is a 16-bits Xoroshiro, which has a lower autocorrelation than the LFSR as it is required for using the SRI; • The number of columns is fixed to 8 and the number of rows varies from 8 to 64; • The counters have 8-bit outputs;

• The reference accuracy varies in the range {0.005, 0.010, 0.020}; • The clock frequency is set to 100 MHz;

• The number of rails varies from 1 to 8. The results are measured on the whole Bayesian sensor fusion circuit, including the SC core described in Fig. 3, but also a control block (Finite State Machine) and models memories.

Table II Fig. 4 shows the relative changes of these measurements compared to the single-rail architecture for a KLD of 0.01.

Note that the relative comparisons are not linear since, for example, doubling the area would result in a +100% increase, while halving the energy would lead to a -50% reduction.

We can see that the more rails are implemented, the more energy is saved, until reaching a plateau with 8 rails. With a KLD of 0.01 and 8 rails, it is therefore possible to save up to 73% of energy with 8 rows and up to 59% with 64 rows.

On the other hand, the circuit area is linearly increasing with the rising number of rails. Taking 8 rails, the total circuit area overhead is up to 28% with 8 rows and up to 49% with 64 rows. Note that for the specific block of the SC core described in Fig. 3, these overheads reach 58% with 8 rows (from 15000 to 23800µm²) and up to 94% with 64 rows (from 77000 to 149400µm²).

Finally, notice that 8 rails does not seem to be a judicious choice since we obtain the same energy performances with 7 rails (-73%) while reducing the area overhead (+24% instead of +28%). Therefore, we did not study solutions beyond 8 rails, the plateau being reached.

V. CONCLUSION

In this article, we introduced the SC multi-rails architecture, a new way to parallelize SC circuits in order to reduce their computation time and thus their energy consumption. This proposition is based on an optimized version of the SRI introduced in [START_REF] Belot | An area and power efficient stochastic number generator for bayesian sensor fusion circuits[END_REF], and the permutations of its output random numbers to generate independence between the different rails without hardware cost and significant accuracy losses. Comparisons in terms of area and energy have been carried out and our proposal is able to save up to 73% of energy with 7 rails and a KLD of 0.01, in return for a 24% increase in surface area on the total circuit.

Figure 1 :Figure 2 :

 12 Figure 1: Decomposition of a WBG with 4-bits random number (r i,i∈[0;3] ) and 4-bits binary value (b i,i∈[0;3] ).

Figure 3 :

 3 Figure 3: Proposed sequential multi-rails (here 2 rails, in black and in gray) SC architecture for Bayesian sensor fusion.

Figure 4 :

 4 Figure 4: Relative change of area and energy consumption compared to a 1-rail architecture with a KLD=0.01.

Table I :

 I Stochastic Bit-stream Length required to reach different values of KLD according to the number of rails.

					Nb rails
		1	2	3	4	5	6	7	8
	KLD				SBL (in cycles)
	0.020	6000	3000	2050 1580 1330 1100	930	880
	0.010 12000	6050	4150 3050 2500 2100 1800 1700
	0.005 24000 12900 8900 6900 5900 5400 4600 4500

Table II :

 II shows the absolute comparison in energy and area consumption with different accuracy and number of rails. Energy and area comparison according to the number of rails.

								Number of rails
				KLD Rows 1	2	3	4	5	6	7	8
	Energy	consumption	(nJ)	8 0.020 64 69.2 47.9 41.9 37.0 35.4 33.4 32.3 31.5 21.5 12.6 9.70 8.36 7.70 6.95 6.36 6.34 8 41.7 24.1 18.4 15.0 13.4 12.2 11.2 11.1 0.010 64 132 89.8 77.8 65.1 60.6 57.6 56.1 54.5 8 82.2 50.1 38.1 32.4 30.0 29.4 26.7 27.4 0.005 64 256 184 159 139 134 137 133 133
	8 Area (10 3 µm²) 64	31.9 34.4 35.7 36.4 37.6 38.6 39.5 40.7 149 169 180 187 197 204 213 221

ACKNOWLEDGMENT

This work has been supported by the grant number 2019/0311 from ANRT.