Benjamin Vidales Luna

Professeur M Bertrand Raison

M Erwann Carvou

Professeur M Serge Weber

M Manuel Madrigal Martínez

M Domingo

Torres Lucio

Mme Nadia

Maria Salgado Herrera

Profesora Asociada

M José

Profesor Luis Monroy-Morales

Pour l'obtention du

sources d'énergie continues d'origine photovoltaïques.

i Remerciements I want to express from the bottom of my heart my most sincere gratitude to my beloved family for all their love and support along this path in the search of knowledge, especially to my father who with his example instilled in me the will to achieve my goals with respect and honesty.

I thank my advisor and friend Dr. Manuel Madrigal Martínez for allowing me to work shoulder to shoulder on this great project, as well as sharing his valuable advice and experiences with me, which shape me as a human being and as a professional for the future.

I thank my advisor and friend Dr. Domingo Torres Lucio for having shared his french studies experience with me, which undoubtedly motivated me to have this type of experience and which allowed me to polish new skills in a great environment of work. I thank my advisers Patrick Schweitzer and Serge Weber for all their support, advice and guidance in discovering new branches of knowledge that overcome barriers of distance, languages and cultures.

I thank all the departments of the PGIIE and IJL for all their hard work and eort which favor the high-level technological development of science without losing the human warmth and kindness that characterizes them so much. I also thank my colleagues Dr. José Luis Monroy Morales and Dr. Juan Ramón Rodríguez Rodriguez, not only for their knowledge and experience shared but also for their kind friendship.

To the National Council of Science and Technology (CONACYT), for having allowed me to be part of the scholarship holders for postgraduate studies in both my master and doctoral degree.

ii I am grateful to the National Association of Universities and Institutions of Higher Education (ANUIES) for its support through the exchange project for researchers and students, México-France ECOS-NORD.

To the Technological Institute of Morelia and the University of Lorraine for given me the opportunity to train as a professional within these beautiful educational institutions.

iii Abstract In this research work, the development of a multilevel inverter for PV applications is presented.

The PV inverter, has two stages one DC/DC converter and one DC/AC inverter, and is capable of generating an AC multilevel output of nine levels, it's a transformerless inverter and uses a reduced number of components compared to other topologies.

The conception of a novel DC/DC converter is capable of generating two isolated DC voltage levels needed to feed the DC/AC stage. This DC/DC stage is developed in two variants, buck and boost, the rst to perform the reduction of voltage when the DC bus is too high, and second to increase the voltage when the DC bus is too low to perform interconnection with the grid through the DC/AC inverter. This is achieved thanks to the parallel functioning of the developed topology, which make use of moderated duty cycles, that reduces the stress in the passive and switching components, reducing potential losses. The validation of the PV inverter is performed in simulation and experimental scenarios. In the other hand, the response of the inverter facing an arc fault in the DC bus is studied by performing a series of tests where the fault is generated in strategic points of the DC side, this is possible thanks to the design and construction of an arc fault generator based in the specications of the UL1699B norm.

During the tests is observed that with the apparition of an arc fault, there is a lost in the half-wave symmetry of the AC multilevel output voltage waveform, generating even harmonics which aren't present during normal operation, only when an arc fault is present in the DC system.

The monitoring of even harmonics set the direction for developing the detection technique.

Since the magnitude of even harmonics in the inverter is very low, the total even harmonic distortion is employed as a base for the detection technique presented in this thesis. The eectiveness of this method is veried with a series of tests performed with dierent loads. La première partie de ces travaux de thèse consiste à développer une topologie de convertisseur multiniveaux innovant. En eet une structure de convertisseur multiniveaux apporte de multiples avantages pour la génération d'énergie tels qu'un faible contenu harmonique, un nombre de composants réduit et un meilleur contrôle de la puissance transmise au réseau.

Le second thème abordé concerne l'intégration d'un système de détection de la présence d'un défaut d'arc électrique dans le convertisseur. En eet, l'apparition des défauts d'arc électrique peut conduire à l'apparition d'un incendie dans un système de génération photovoltaïque et doit absolument être détecté.

Ces arcs peuvent apparaitre soit à l'intérieur de panneaux (câbles internes de connexion des cellules silicium, entre les cellules etc.) soit à l'extérieur des panneaux (boite de connexion, câbles des distributions, etc.). Ces défauts d'arc électrique sont soit des arc séries soit des arcs en parallèle. La Fig. 3 vii En raison des nombreux points de défauts possibles et de leurs diérentes causes, le dé de développement d'un système capable de détecter ecacement les arcs dans ce type de système est une réelle préoccupation pour la sécurité des installations et des personnes.

Convertisseur Multiniveaux

Les systémes de production PV utilisent des convertisseurs électroniques de puissance an de transformer l'énergie provenant des panneaux en énergie exploitable par le réseau électrique.

Parmi ces types de convertisseurs, les onduleurs à plusieurs niveaux présentent des avantages clés par rapport aux onduleurs conventionnels à deux niveaux.

Les onduleurs multiniveaux sont couramment utilisés pour des applications de forte puissance.

La litt¯ature présente de nombreuses topologies multiniveaux destinées aux applications dans le domaine des énergies renouvelables, á base des les topologies clamping diode, ying capacitor et cellules en cascade. Les principaux inconvénients de ces deux premières topologies sont l'utilisation de nombreux composants ainsi que le déséquilibre des niveaux de tension des condensateurs.

Cette topologie de cellules est constituée de plusieurs (minimum deux) modules connectés en série, sont basé sur des ponts en H complets. Le nombre de niveaux de tension peut facilement être augmenté en ajoutant de nouveaux modules, alors que les autres topologies voient le npmbre des diodes ou de condensateurs augmenter de façon exponentielle.

Une topologie innovante de convertisseur neuf niveaux, présentée en Fig. 4, est proposée dans le chapitre 3 de la thèse.

viii aecte la tension de sortie du convertisseur (même en utilisant un bloc de régulation MPPT).

Cell 1 Cell 2 C 2 L 1 L 2 L load i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out
Néanmoins, nous montrons que l'AF crée des perturbation au niveau de l'étage de conversion DC/AC.

Détection des AF

Suite à la mise en évidence de l'inuence de l'AF sur la topologie proposée du convertisseur multiniveaux. Avec l'apparition de l'arc dans le systéme, l'équilibre entre la cellule 1 et la cellule 2 de la conguration de cellules en cascade est altéré par les rapides uctuations de l'arc. Ce changement produit la perte de certains des neuf niveaux dans la signal de sortie.

C'est sur ces phènomènes présentés dans la Fig. 12

Cell 1

Cell 2

C 2 L 1 L 2 L load i Cell1 I Load V DC V C1 V C2 VH2 V H1 V out Complex Load S 3 C 1 D 1 i Cell2

Symbols and Abbreviation

)V C 1 b)iL 1 c)V C 2 d)iL 2 . . . . . . .

4.8

Simulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out .

4.9

V Bridge1 and V Bridge2

Introduction

In recent years, the photovoltaic (PV) market has grown remarkably, especially in the last few years thanks to the various stimulating factors such as a drop of production costs and numerous governmental support and initiatives. That promotes the use of clean energy generation. These stimulating factors make the return of investment of a PV installation more and more interesting.

However, like all other industrial processes, a PV system can be subjected, during its lifespan, to various faults and anomalies that lead to a decrease in the system performance and even to total unavailability of the system. All these adverse consequences will reduce productivity, and thus the prot of the installation. Is for this reason that a next-generation power converter destined to the interface of PV generation should integrate the main features for regulation, power tracking, and protections, making every system more reliable.

PV Converters

In order to set a proper background for the development of this thesis proposal, the state of art for PV converters and arc faults protection are studied, in a manner that it can be determinate which are the best suited measures of design for this proposal.

PV inverters are the basic electronic component of PV energy generation, and because of this, many topologies have been studied and proposed achieving the interfacing PV module(s) with the grid, this by injecting a sinusoidal current into the grid. In the past the grid-connected stage was usually line commutation by means of thyristors, involving many current harmonics and poor power quality.

The undesirable large amount of harmonics was the reason of new multilevel inverter topologies and system layouts. That make the combination of multiple blocks in order overcome the power quality needs of the grid. These converters make use of solid state switching devices such as IGBT's in combination with capacitors of diodes to create multiple voltage levels across the topology which are controlled to output an AC semi sinusoidal waveform, which harmonic content is lower than conventional inverters.

Nonetheless protection requirements by the standard NEC 690 demands that the PV modules shall be grounded and monitored for ground faults when reaching a maximum output voltage of the PV's.

Since this is just one example of common protection in PV system, that external devices need to addressed. Nowadays, detection techniques to prevent a wider scope of potential catastrophic faults are based in frequency analysis.

A comparison between various recently proposed DC/AC multilevel converters, mainly based on a single DC source, is presented in Table 1.1.1. The characteristics that are considered for the selection of these topologies where the number of IGBT's, diodes, inductors and capacitors involved, but also the number of levels achieved by the topology, the elevation capacities of the proposals and the use of galvanic transformers.

Chapter 1. Introduction

The rst example is the converter in [3] that is capable of achieving a nine-level output with twelve IGBT's and is a transformerless topology, the inconvenience of this proposal is that the input voltage has to be always higher than the desired output since is based in two modied buck converters.

In references [3], [4] and [5] the converters are able to generate a nine-level output, many of these converters produce a higher total harmonic distortion (THD) and use more elements.

The actual tendency in multilevel converter development is to use the minimum number of components and improve reliability and functionality of the system. As part of the most recent developments the work in [1] is able to achieve a seven-level AC output by employing ten IGBT's, the topology presented in Fig. 1.1 consist of cascading two three-level ying capacitor inverters with a half-bridge module in between, as a particular condition, this topology needs three pre-charged capacitors at V dc/2, V dc/3 and V dc/6, respectively. The topology presented in [6] may be attractive considering the number of components employed, and also because of the elevation capacity but a transformer is required as presented in Table 1.1.1. The elevation capability is only present in [START_REF] Meynard | Modeling of multilevel converters[END_REF].

In [START_REF] Sepahvand | Capacitor voltage regulation in single-dc-source cascaded h-bridge multilevel converters using phase-shift modulation[END_REF] an asymmetrical cascade cells conguration is implemented replacing one of the voltage 1.1. PV Converters 39 sources by a capacitor accompanied by a voltage balancing control. Due to the symmetrical voltage level needed between the capacitor and the input source, the converter can only achieve ve levels which along with [2,[START_REF] Roshankumar | A ve-level inverter topology with single-dc supply by cascading a ying capacitor inverter and an h-bridge[END_REF][START_REF] Vazquez | Dc voltage ratio control strategy for multilevel cascaded converters fed with a single dc source[END_REF] are the topologies that generate the minor number of levels increasing considerably the THD.

Of the few proposals in literature, with an elevation capability, [START_REF] Rahim | Single-phase seven-level grid-connected inverter for photovoltaic system[END_REF] and [START_REF] Nami | A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diode-clamped h-bridge cells[END_REF] oers a well balanced range of features such as seven-level and no use of transformer, but they are surpassed by [3], [4].

In [START_REF] Vazquez | Dc voltage ratio control strategy for multilevel cascaded converters fed with a single dc source[END_REF] and [START_REF] Du | Fundamental frequency switching strategies of a seven-level hybrid cascaded h-bridge multilevel inverter[END_REF] is proposed a similar replacement of a DC source by a capacitor similar to [START_REF] Sepahvand | Capacitor voltage regulation in single-dc-source cascaded h-bridge multilevel converters using phase-shift modulation[END_REF], nonetheless, stable operation in this type of converters can be challenging especially if a high power is demanded as explained in [START_REF] Du | Fundamental frequency switching strategies of a seven-level hybrid cascaded h-bridge multilevel inverter[END_REF].

In [2] a ve-level converter with even less IGBT's is presented in Fig. 1.2, but as the proposals in [2,[START_REF] Sepahvand | Capacitor voltage regulation in single-dc-source cascaded h-bridge multilevel converters using phase-shift modulation[END_REF][START_REF] Vazquez | Dc voltage ratio control strategy for multilevel cascaded converters fed with a single dc source[END_REF][START_REF] Du | Fundamental frequency switching strategies of a seven-level hybrid cascaded h-bridge multilevel inverter[END_REF] one of the DC sources is replaced with a capacitor to make the converter operates.

The techniques presented in [2] and [6], uses a galvanic transformer, therefore they are not a suitable option to be implemented compared to transformerless techniques, such as those presented in [START_REF] Mackay | Series arc extinction in dc microgrids using load side voltage drop detection[END_REF]713] Figure 1.2. Schematic diagram of proposed converter in [2] In Table 1.1.1 are presented developments from year 2009 to 2019, the criterion to include these topologies are, the number of levels generated, operation from a single source, that is transformerless, and that employs the fewer amount of components possible to achieve the task.

Electric DC Arc Fault Detection

In this section will be presented the fundamental denitions of an electric arc fault (AF), the dierent types of possible AF in PV panels, the literature approaches to model this phenomenon based on implementation results, also will be analyzed the actual normative 1.2. Electric DC Arc Fault Detection that helps in the development of ecient AF detectors along with recent proposals to achieve successful detection.

An AF is a high power discharge of electricity between two or more conductors. This discharge translates into heat, which can tear down the wire's insulation and possibly trigger an electrical re. These AF can range in power from a few amps up to thousands of amps high and are extremely variable in terms of strength and duration. Common causes of arc faults include faulty connection due to corrosion and faulty initial installation.

Arc faults can be classied mainly in three categories. Series, parallel and grounding arcs.

Generally, parallel arcs can be considered as short circuit eects and they are characterised by high levels of current. On the contrary, in the case of a series arc, the current level is limited by the presence of the load in series with the arc itself. While the electrical circuit has a ground connection, the line-to-ground arc occurs when the arc ows through a grown path and in most cases it can coexist with either series and parallel arcs [START_REF] Mackay | Series arc extinction in dc microgrids using load side voltage drop detection[END_REF].

During last years, the main normative for arc protections, in order to have safer PV implementation, has been the normative by UL1699B. This rst standard for AF detection appears more than a decade ago as the normative UL1699, and soon after as a second and more detailed revision UL1699B where recent research and development of novel Arc Fault Detection Devices (AFDD) are based [START_REF]Outline of investigation for photovoltaic (pv) dc arc-fault circuit protection[END_REF].

Arc faults can appear in both systems, direct current (DC) and alternating current (AC)

systems. The aims of this bibliographic study are to analyze the detection and prevention methods oriented for AF in DC systems using PV panels.

The principal methods that have gained popularity to achieve DC AF detection are, harmonic content based detection, low pass lter, drop voltage window, current drop and frequency comparison, current limiting, among other. These type of detection algorithms will be presented in the next chapter.

PV Converters and Electric DC Arc Detector

With the advantage of converters for PV applications can be possible to use the capabilities of the converter to identify electric DC arc faults. By keeping this scope in mind, the PV inverter project is conceived and developed in this thesis.

In order to fully understand the many components present in an PV installation, the role of each stage and the possible types of faults related to them, an conscious literature analysis of both, power electronics converters and AF are required.

Some international companies such as Hager, Texas Instruments, Schneider Electric, among others have developed protection systems against AF, which under simple operating conditions presume to be able to detect this type of faults, however, these devices commonly make use the current signature of the DC bus as a detection reference. This implies that detection will be aected by the connected load, the type of converter used and the maximum power point traking (MPPT) algorithm employed, as has already been demonstrated by authors such as J. Johnson from Sandia National Laboratory US [START_REF] Johnson | Photovoltaic dc arc fault detector testing at sandia national laboratories[END_REF]. In addition to this complex subroutines must be processed in short time, which implies the use of processors with greater capacity, thus increasing the cost of protection.

Nonetheless has to be highlighted the fact that by the addition of this type of protection adds external components to the PV system which is discouraged because this increase the number of possible failure points. It's for this reason that a detection system integrated into the converter is an option since it's not necessary to add any component to the installation, it facilitates the correct detection since it provides numerous internal measurement points that 1.4. Objectives 43 allow determining, in a more precise way the nature of the fault. Not to mention the reduction of costs given that the converter is an essential part of the PV system, the acquisition of this protection is seeming less for the user.

Objectives

1. The main objective of this research project is to develop, simulation and implementation, of a power electronic inverter for PV applications that will achieve a higer number of levels with a reduced number of components.

Justication

The world leading tendency is to develop PV inverters with better performance, achieving this by generating a high number of levels with a reduced number of components. For this reason, the proposal of a transformerless PV inverter that generates a low harmonic nine-level AC output is presented, optimizing the interface of PV panels. The arc fault problematic is a well documented problem, for this reason, the PV inverter also integrates a novel DC arc fault detector that is critical in order to avoid catastrophic faults that have the potential of damaging a whole PV installation.

Chapters Description

Chapter 1 -The aim of this chapter is to examine the context of this thesis in the areas of power electronics and electric arc fault detection.

Chapter 2 -This chapter is dedicated to analyzing the bases for modeling of the main structure of the PV inverter, and also analyzes the historical background of arc faults and the popular detection techniques.

Chapter 3 -The guidelines, characteristics, and design of the newly developed DC/DC and DC/AC conversion topology for the PV inverter are described in detail in this chapter.

Chapter 4 -In this chapter the validation of the PV inverter with simulation and experimental results, using matlab simulink and the experimental test bench are presented with detail.

Chapter 5 -In this chapter the detection hypothesis in validated in experimentation by generating arc faults in dierent conguration following the UL1699B guidelines, which lay the foundations for the proposed detection technique, also detailed in this chapter.

Chapter 6 -In this chapter the concrete results of this research, the future works proposal and the main contribution of this research are presented.

Results of this Research

The results obtained throughout this period of research are presented bellow:

Journal Articles

Introduction

In this chapter will be presented a state of the art of power electronic converters, and the recent developments that contribute to a better performance in conditioning of DC/DC and DC/AC converters and also the state of art of electric DC arc fault detection technique.

Context of this Study

In early 2019 the Energy Information Administration (EIA) publishes the Annual Energy Outlook (AEO) where a projection of energy demand for the US are studied and modeled in order to predict with certain grade of certitude how the demand of energy will be from now to 2050, this study is based in the AEO National Energy Modeling System (NEMS), an integrated model that captures interactions of economic changes and energy supply, demand, and prices [START_REF]Energy Information Administration, Annual energy outlook 2019[END_REF]. According to this study, the generation of energy by means of renewable sources as wind and solar PV are going to be the main energy source of the future, solar PV The increasing capacity of solar PV installations has led to research and development of high power converters, required to interconnect the PV panels to the main grid. These power technology converters try to achieve a reduction in the number of components, high eciency, and protection against faults among others.

Photovoltaic Installation Structure

The PV installation is built out of several components as presented in Fig. 2.2, however, a fundamental block of this type renewable energy production system is the DC/AC inverter.

Since this converter is responsible for the conversion of energy, it is essential that this is performed with the highest possible eciency index. To achieve this, the DC/AC converters have undergone a constant change over time and with the appearance of new generation components. The dierent topologies developed have been strongly inuenced by the needs of the industry. This is reected in the rst-ever publication on a three-level inverter [START_REF] Holtz | A new type of voltage fed inverter for the megawatt range[END_REF]. The Multilevel Converters (MLC) were invented with the explicit aim of overcoming the voltage limit of semiconductor devices of that time. The concept of utilizing multiple small levels to perform power conversion was presented over 40 years ago [START_REF] Holtz | Self-commutated three-phase inverters with staircase voltage waveforms for high-power applications at low switching frequency[END_REF], [START_REF] Nabae | A new neutral-point-clamped pwm inverter[END_REF]. While the rst-ever patent three-level inverters and multilevel inverter (MLI) was in 1983.

The original idea of MLI's was tantamount to connect multiple devices in series and clamp the voltages between them. An early patent appeared in 1975 [START_REF] Baker | Electric power converter[END_REF], in which the cascaded inverter was rst dened with a structure that connects separately DC-Sourced Full-Bridge cells in series to synthesize a staircase AC output voltage [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF].

Following this idea and redesigning the converter with diodes blocking the sources, the diode-clamped MLI was then patented [START_REF] Baker | Switching circuit[END_REF], [START_REF] Baker | Bridge converter circuit[END_REF]. This inverter was also called the Neutral Point Clamped (NPC) inverter because it was rst used in a three-level inverter where the mid-voltage level was dened as the neutral point [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF].

One of the main advantages provided by this new NPC inverter was doubling the device voltage without precise voltage matching, thanks to this the topology prevailed during the 1980s [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF].

50

Chapter 2. Inverter for PV Applications and electric DC arc Fault Detection

Although the cascade inverter was invented earlier, it had few applications until the mid-1990s. Due to the great demand for MV high-power inverters, the cascade inverter has drawn tremendous attention ever since [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF], [START_REF] Peng | Multilevel cascade voltage-source inverter with separate dc sources[END_REF]. Several patented works were suggested for the use of cascade MLI in the regenerative type of motor drive applications [2730].

However, most of the application in this area has occurred over the last few years. Despite the signicant innovations in this area, there is still much more that can be done [START_REF] Corzine | Operation and design of multilevel inverters[END_REF].

Due to the fact that the ML output voltage exhibits lower harmonic distortion in comparison with the two-level voltage, typical problems like stator winding insulation breakdown, bearing failures, and electromagnetic interference (EMI) associated with the high switching frequency can be signicantly reduced when using MLCs [START_REF] Corzine | Operation and design of multilevel inverters[END_REF], [START_REF] Muetze | Experimental evaluation of mitigation techniques for bearing currents in inverter-supplied drive-systems -investigations on induction motors up to 500 kw[END_REF]. In the three-level inverters, the semiconductors have voltage ratings of only Udc/2 and an increased voltage power ratio [START_REF] Corzine | Operation and design of multilevel inverters[END_REF]3336].

MLCs have been investigated extensively, particularly for MV high-power applications [START_REF] Corzine | Operation and design of multilevel inverters[END_REF][START_REF] Muetze | Experimental evaluation of mitigation techniques for bearing currents in inverter-supplied drive-systems -investigations on induction motors up to 500 kw[END_REF]3748]. They have been investigated for other applications such as utility interface for renewable energy systems [4953], high-voltage DC transmission [START_REF] Rufer | An aid in the teaching of multilevel inverters for high power applications[END_REF], exible AC transmission system [START_REF] Tolbert | A multilevel converter-based universal power conditioner[END_REF], electric traction systems, active power ltering [START_REF] Veenstra | Control of a hybrid asymmetric multilevel inverter for competitive medium-voltage industrial drives[END_REF], [START_REF] Rufer | An aid in the teaching of multilevel inverters for high power applications[END_REF], unied power ow controllers, superconducting magnetic energy storage [START_REF] Barros | Optimal predictive control of three-phase npc multilevel converter for power quality applications[END_REF], and static synchronous compensators [START_REF] Lin | Modeling and control of neutral-point voltage balancing problem in three-level npc pwm inverters[END_REF], [5558]. Recently, the use of ML congurations has become more prevalent in the active rectier eld [START_REF] Corzine | Operation and design of multilevel inverters[END_REF], [START_REF] Holmes | pulse with modulation for power converters[END_REF], [START_REF] Kazmierkowski | Current control techniques for three-phase voltage-source pwm converters: a survey[END_REF].

Among MLCs [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], the following three topologies have been successfully implemented as standard products for MV industrial drives 1) the four-level neutral point clamped (NPC)

2) the four-level ying capacitor (FLC) and 3) the cascade cells multilevel inverter (CCMI) [START_REF] Hammond | Medium voltage pwm drive and method[END_REF], [START_REF] Hammond | A new approach to enhance power quality for medium voltage ac drives[END_REF], [START_REF] Beinhold | A new range of medium voltage multilevel References inverter drives with oating capacitor technology[END_REF]. These congurations are further described in the following sections.

Photovoltaic

Neutral Point Clamped Multilevel Inverter

For NPC inverter topology [START_REF] Nabae | A new neutral-point-clamped pwm inverter[END_REF] the midpoint potential of a capacitive voltage divider in the DC link is used to stabilize the voltage distribution between devices with the help of clamping diodes, D 1 and D 2 presented in Fig. 2.3. The topology adds the zero level to the output voltage waveform and, thus, also serves to reduce its harmonic content. The three-level inverter topology permits operation at double voltage, which also doubles the maximum output power. Furthermore, the capacitors can be pre-charged as a group [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF], [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], [START_REF] Lai | Multilevel converters-a new breed of power converters[END_REF], [START_REF] Tolbert | Multilevel converters for large electric drives[END_REF]. The concept can be extended to any number of levels by increasing the number of capacitors and diodes. However, due to capacitor voltage balancing issues, the NPC inverter implementation has been mostly limited to the three-level inverter [START_REF] Holtz | Neutral point potential balancing algorithm at low modulation index for three-level inverter medium-voltage drives[END_REF], [START_REF] Enjeti | Optimal power control strategies for neutral point clamped (npc) inverter topology[END_REF].

This type of inverter is widely used in MV applications and is one of the most commonly applied topologies [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], [START_REF] Lai | Multilevel converters-a new breed of power converters[END_REF], [START_REF] Holtz | Neutral point potential balancing algorithm at low modulation index for three-level inverter medium-voltage drives[END_REF].

It characterizes a relatively small DC link capacitor, a simple power circuit topology, a low component count, and straightforward protection and modulation schemes [START_REF] Steen | State of the art and developments of medium voltage converters -an overview[END_REF]. Therefore, the three-level NPC is a competitive topology for a large variety of low and medium switching frequency applications. Additionally, the three-level NPC has the highest converter eciency among the available solutions for the industry [START_REF] Krug | Comparison of 2.3-kv medium-voltage multilevel converters for industrial medium-voltage drives[END_REF]. The NPC has found an important market in more conventional high-power AC motor drive applications like conveyors, pumps, fans, and mills, among others, which oer solutions for industries including the oil and gas, metal, power, mining, water, marine, and chemical industries [6466].

Because all of the phases share a common DC bus, the capacitance requirements of the converter are minimized. For this reason, a back-to-back topology is possible. This conguration for regenerative applications has also been a major benet, for example, in regenerative conveyors for the mining industry or grid interfacing of renewable energy sources like wind power [START_REF] Alepuz | Interfacing renewable energy sources to the utility grid using a three-level inverter[END_REF], [START_REF] Portillo | Modeling strategy for back-to-back three-level converters applied to high-power wind turbines[END_REF]. Although this topology has a simple circuit, usually, it needs a large inductive capacitive output lter to operate standard motors [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF].

Flying Capacitor Multilevel Inverter

Flying capacitor multiple inverter (Flying Capacitor) shown in Fig. 2.4 is another popular voltage source MLI uses the ying capacitor topology [START_REF] Meynard | Modeling of multilevel converters[END_REF]. This topology oers the advantages of MLCs. However, the needs to balance the capacitors voltages and pre-charge the capacitors at the start time, in addition to a larger number of capacitors, is the disadvantages of this topology. The high capacitance values and stored energies of the ying capacitors limit the use of three-level and four-level FLC to high switching frequency applications [START_REF] Fazel | Design and comparison of 4-kv neutral-point-clamped, ying-capacitor, and series-connected h-bridge multilevel converters[END_REF].

In the FLC, the load current charges every capacitor; hence, the respective capacitor voltages change. The resulting changes must be maintained within permissible limits. Thus, the required capacitance increases approximately in inverse proportion to the switching frequency. This makes the FLC topology impractical at very low switching frequencies. Therefore, the stored energy of the ying capacitors and the dimension of the LC inverter output lter is increased by a factor of about 10 (for three-level FLC) and 20 (for four-level FLC) in comparison to three-level NPC [START_REF] Fazel | Design and comparison of 4-kv neutral-point-clamped, ying-capacitor, and series-connected h-bridge multilevel converters[END_REF]. The high cost of ying capacitors at low and medium switching frequencies is the reason that the FLC topology is not competitive in applications that only require low and medium 2.3. Photovoltaic Installation Structure 53 switching frequencies 1500-1800 Hz [START_REF] Fazel | Design and comparison of 4-kv neutral-point-clamped, ying-capacitor, and series-connected h-bridge multilevel converters[END_REF]. Nevertheless, the symmetrical switches loss distribution and the resulting high rst carrier band frequency of the converter voltage make this topology attractive for some applications such as highspeed drives and test benches [START_REF] Krug | Comparison of 2.3-kv medium-voltage multilevel converters for industrial medium-voltage drives[END_REF], [START_REF] Lai | Multilevel converters-a new breed of power converters[END_REF], [START_REF] Franquelo | The age of multilevel converters arrives[END_REF], [START_REF] Fazel | Design and comparison of 4-kv neutral-point-clamped, ying-capacitor, and series-connected h-bridge multilevel converters[END_REF]. In these applications, the three-level FLC is an interesting alternative to the four-level FLC due to the reduced cost of ying capacitors. At lower frequencies and high converter eciency, neither topology is competitive compared to the three-level NPC and the ve-level CCMI [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], [START_REF] Krug | Comparison of 2.3-kv medium-voltage multilevel converters for industrial medium-voltage drives[END_REF].

Cascade Cells Multilevel Inverter

Cascade cells multilevel inverter is a topology that connect in series H-bridge that appeared in mid 1970s [START_REF] Baker | Electric power converter[END_REF], and several recent works were registered [START_REF] Steinke | Use of an lc lter to achieve a motor-friendly performance of the pwm voltage source inverter[END_REF], [START_REF] Pohler | Optimisation of output lters for inverter fed drives[END_REF], [START_REF] Hammond | Medium voltage pwm drive and method[END_REF]. Since this topology consists of series power conversion cells, the voltage and power level may easily be scaled [START_REF] Corzine | Operation and design of multilevel inverters[END_REF]. However, a disadvantage is the large number of required isolated power supplies. However, the cells can be supplied by phase-shifted transformers (an expensive 54 Chapter 2. Inverter for PV Applications and electric DC arc Fault Detection solution) in order to provide high power quality at the utility side [START_REF] Corzine | Operation and design of multilevel inverters[END_REF], [START_REF] Hammond | Medium voltage pwm drive and method[END_REF]. The ve-level CCMI shown in Fig. 2.5 requires the lowest switch power rating and stored energy of the LC lter. Compared to the three-level NPC, the installed switch power and the stored energy are signicantly reduced (even up to 80%) [START_REF] Peng | Multilevel cascade voltage-source inverter with separate dc sources[END_REF], [START_REF] Krug | Comparison of 2.3-kv medium-voltage multilevel converters for industrial medium-voltage drives[END_REF]. However, a complicated grid transformer, increased dc-link capacitance compared to the three-level NPC, and the high number of semiconductor devices are its drawbacks [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF]. The absence of a common dc voltage bus is an additional disadvantage of the ve-level CCMI [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF].

The cascaded H-bridge has been applied for high-power and power-quality industrial requirements due to its series expansion capability [START_REF] Franquelo | The age of multilevel converters arrives[END_REF]. This topology has also been used for active lter and reactive power compensation [START_REF] Rodriguez | Multilevel inverters: a survey of topologies, controls, and applications[END_REF], [START_REF] Peng | Multilevel cascade voltage-source inverter with separate dc sources[END_REF], [START_REF] Lai | Multilevel converters-a new breed of power converters[END_REF], [START_REF] Khoucha | Hybrid cascaded h-bridge multilevel inverter motor drive dtc control for electric vehicles[END_REF], [START_REF] Sirisukprasert | A high-frequency 1.5 mva h-bridge building block for cascaded multilevel converters using emitter turn-o thyrister[END_REF], electric vehicles [START_REF] Tolbert | Charge balance control schemes for cascade multilevel converter in hybrid electric vehicles[END_REF], photovoltaic power conversion [5153], interruptible power supplies (UPSs), and magnetic resonance imaging [START_REF] Franquelo | The age of multilevel converters arrives[END_REF], etc. A hybrid asymmetric MLC is constructed by combining the CCMI with the NPC topologies [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF]. Such a combination produces more output voltage levels with the same number of components as a symmetric MLC [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF]. Although an H-bridge cell and a leg of the NPC converter provide the same output voltage levels, the hybrid asymmetric ML topology requires a smaller number of separate DC sources and H-bridge cells for the same output voltage levels [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], [START_REF] Veenstra | Control of a hybrid asymmetric multilevel inverter for competitive medium-voltage industrial drives[END_REF]. This topology can be operated at a low or a high switching frequency for high or low voltage applications. However, the need for a complex input transformer remains, and the control system would be too complex due to its structure therefore, it is not commercially oered [START_REF] Veenstra | Control of a hybrid asymmetric multilevel inverter for competitive medium-voltage industrial drives[END_REF], [START_REF] Manjrekar | A hybrid multilevel inverter topology for drive applications[END_REF]. This is also true for the nine-level CCMI, although it is a good topology for manifold MV drives, e.g., high-speed drives [START_REF] Fazel | Investigation and comparison of multi-level converters for medium voltage applications[END_REF], [START_REF] Fazel | Design and comparison of 4-kv neutral-point-clamped, ying-capacitor, and series-connected h-bridge multilevel converters[END_REF].

Other interesting and competitive topology try new methods, like combining the basic NPC and half-bridge principles. A ve-level topology was proposed, where each phase of the inverter consists of two three-level NPC half-bridges connected in series. One arm is connected to the output terminal and the other is connected to the neutral point. The half bridges are supplied by isolated DC sources, which are often composed of multi-pulse diode rectiers [START_REF] Cheng | A novel switching sequence design for ve-level npc/h-bridge inverters with improved output voltage spectrum and minimized device switching frequency[END_REF]. The topology was named NPC/H-bridge inverter. Taking into account the reviewed information of PV inverters, the proposal of this research protect is presented in In the next section the overall problematic related to the appearance of AF on PV panels will be discussed.

Arc Fault Modeling

Arc faults can appear in both types of PV systems new and aged installation, this due to the fact that cable insulators, panels and junction boxes are expose to the elements. Another common cause of fault is due to inadequate installation, this can cause a small separation in the conductors from its connection, producing an AF. Since this malfunction happens in the DC side, the detection can be challenging as will be analyzed in the sections below.

The dielectric constant of an insulating material denes the maximum electric eld that the material can withstand before breakdown occurs. A sustained arc results if the energy produced inside the arc is higher than the energy lost due to thermal radiation, light, sound, etc. The dielectric constant of air is approximately 3 V/u, and it depends on surrounding pressure, humidity, presence of impurities, etc. [START_REF] Bower | Electrical and thermal nite element modeling of arc faults in photovoltaic bypass diodes[END_REF], [START_REF] Strauch | Solar module arc fault modeling at sandia national laboratories[END_REF].

56

Chapter 2. Inverter for PV Applications and electric DC arc Fault Detection

In addition, the initiation/sustainability of an arc also depends on the size/shape of the electrodes, the air gap between the electrodes, and presence of chemical products from the arc (e.g., melted metals from electrodes, melted/vaporized polymers from glass, wire insulation).

An arc is initiated across an air gap when high electric elds ionize air molecules and accelerate the ion toward the opposite electrode. This leads to a high-velocity particle collisions, which generate additional charged particles. This runaway ion generation converts the normally insulating air medium into a conductive medium.

The voltagecurrent relationship of an arc is highly nonlinear. The transient behavior of a DC parallel arc in a PV array connected to an inverter decrease in voltage and increase of current during the on-set of an electric arc. In the case showed in Fig. 2.6 the arc produces a fall in the DC bus voltage, represented in purple, also the current of the whole array is aected presented in red. This drop is equivalent to the AF current and voltage levels presented in blue and green, respectably. the average resistance of the arc at steady state deduced from the average values of the arc voltage and current [START_REF] Strauch | Solar module arc fault modeling at sandia national laboratories[END_REF]. Approaches with additional details for modeling this nonlinear V-I characteristics of the arc are summarized in [START_REF] Yao | Characteristic study and time-domain discrete-wavelet-transform based hybrid detection of series dc arc faults[END_REF], in most cases, to determine arc length empirical equations are included to nd a relationship between the arc voltage and current.

As an example, Yao et al. have proposed a modied Paukert form for describing the V-I relationship of arc in the PV system. As follows [START_REF] Strauch | Solar module arc fault modeling at sandia national laboratories[END_REF]: region (Limited by the dotted line in Fig. 2.7), the arc voltage drops as the arc current increases, as a result, the arc power tends to remain relatively constant in this region. For larger currents, the arc voltage increases slightly with increasing arc current. In the cases of deep study of AF behavior it exists a transition current, which denes the boundaries between the low and high-current regions that will not be discussed in this work, but more information about arc fault is mentioned in the appendix.

V arc = a + bL I arc c + dL
2.5. Arc Fault Detection Techniques 59 2.5 Arc Fault Detection Techniques Its as been already discussed that series arc faults tend to appear when there is a discontinuity between CCC's. Was discussed as well the locations where AF can appears in the PV panels, In the Fig. 2.9 the schematic circuit of a PV system is presented in order to provide a solid base to further explications and location of AF. In Fig. 2.9 are represented in blocks the main Solar panels have a non linear behavior, which means that the constant changes in solar irradiation will be reected as a change in the output value of voltage and current provided.

It exists a point where the maximal power can be extracted from the panels, which refer to a balance between voltage and current were the maximum power transfer is achieved by the panels.

The MPPT DC/DC converter shown in the Fig. 2.9 has the task of receiving the voltage and current generated by the panels and then, according to control algorithm, modify the DC/DC output voltage and current levels by modifying the duty cycle of the DC/DC converter, achieving a constantly track and follow of the maximum eciency point according to the irradiation received by the panels.

After assuring that the maximum power is extracted from the panels, the DC/AC power inverter has the task to transform this DC energy into AC, this conversion of energy can be achieve in many dierent ways and with a wide variety of power electronics topologies, nevertheless in Fig. 2.9 the basic topology (H Bridge) for performing this conversion is presented. Another task related to the inverters role is the synchronization with the electric grid.

The AF detection normally is using a type of algorithms, implemented in an electronic device.

These types of algorithms can be developed in many dierent ways depending of the approach the author employs. Conventionally is perform a frequency analysis were all the harmonic content of signal are displayed and studied, based on this variations they are compared to a reference harmonic content and then be able to recognize if an AF is present in the DC system, this is the method that is proposed in the works of J. Johnson and F. Schimpf [START_REF]Outline of investigation for photovoltaic (pv) dc arc-fault circuit protection[END_REF], [START_REF] Johnson | Photovoltaic dc arc fault detector testing at sandia national laboratories[END_REF], [START_REF] Hall | Arcing faults on direct current trolley systems[END_REF]. Some techniques to identify the DC arc faults are described below.

Spectrum Analysis Detection Technique

In this type of approach a Fourier analysis is perform in the current signal from the DC bus in order to extract the harmonic content, with the aims of analyzing several kHz bands (at very low frequency or low frequency) in which the baseline signals are signicantly increased in the presence of an AF, this is considered one of the conventional methods that can detect DC arc faults.

During the apparition of the AF in a PV system a series of events are follow and it's possible to describe them in ve main events:

1. An arc fault triggers at a specic location in the DC string and generates, 1/f AC noise presented in Fig. 2.10 with magenta on top of the DC current. This signal travels down the line through the system.

2. As this signal passes through the PV modules and connectors, a variable attenuation occurs in the PV modules and connectors and changes the frequency amplitude (prole) of the electrical noise as it propagates downstream.

3. Phenomena such as antenna eects, crosstalk and RF modies the signal prole and characteristics even more.

4. The eects mentioned change the original arcing signal that reaches the AFCI, and depending on the PV cell technology, system topology, metrological conditions, and age of the modules, this signal reaching the AFCI is dierent from the original arcing signal allowing the arc to pass undetected. 5. Also the inverter noise injected into the PV string. This due to the inverter switchings that generates harmonics from 1kHz to 100 kHz [START_REF] Schimpf | Recognition of electric arcing in the dc-wiring of photovoltaic systems[END_REF].

The Fig. 2.10 presents the frequency behavior of dierent signals, that represented two systems, one where the signals are represented with purple and blue colors, and second the same signals but this time with an inverter connected to the system [START_REF] Johnson | Photovoltaic dc arc fault detector testing at sandia national laboratories[END_REF].

If this two signals of Fig. 2.10 are compared, is possible to identify an important fact that is mentioned in the works of J.Johnson, F. Schimpf and Gab-Su Seo, and is that in the early base bands of frequency is easier to identify the changes on the frequency signature of arc signals. Taking the example of Fig. 2.10 is observed that the two systems have a current frequency signature with a magnitude of around -70 db, when the 2 dierent power inverters are added to the system this magnitude of change in the both cases to around -40 db and -20 db, respectably. It's important to note that in this comparison the AF event is not yet considerer in the analysis, nevertheless the changes in the very low and low frequency bands is noticeable. In AF case, a similar change in the frequency signature is observed, this represents the base line for the frequency analysis detection method. Depending on the PV system topology, the impact of AF's may vary. In single string tests, the operating DC current and voltage drops initially, because the string impedance suddenly increased from the AF event, this characteristic is explored to evaluate its potential for detection AF's in DC systems as proposed and explored for L. Mackay [START_REF] Mackay | Series arc extinction in dc microgrids using load side voltage drop detection[END_REF]. This Phenomena has been noticed as well by J. Johnson, although this happens only if measuring the voltage and currents present in a single string, in Fig. 2.11 and 2.12 are presented the signal signatures of a single string for both current and voltage respectably. In this two gures is possible to appreciate the dierent types of response during an AF event for a system with a resistive load bank and other with an inverter connected. On the contrary when an AF appears is easily identied because the current in the string decrease from its nominal value immediately after the arc apparition. This happens also in the case where the system has an inverter connected to it.

In this work is possible to see that the noise that the power inverter injects in the system change the response of the system, the characteristics magnitude of this noise depends of converters topology, switching, frequency, power capacity, etc. To cite and example in Fig. 2.13 present the waveform signatures for six dierent PV system congurations detailed in Table 2.5.1. To create the ignition of an arc fault, the voltage exceeds the permittivity of free space, current begins owing between the electrodes, and the gas ionizes to create a plasma.

To determine if the initial period of the arc fault contained dierent frequency content than succeeding time periods, the arcing time domain was subdivided into 0.10 second blocks and the discrete fourier transformation (DFT) of each time subsection was calculated. While the amplitude of all arcing frequencies was signicantly larger than the baseline measurements, the location of the arc fault had little eect on the frequency content at the AFDD.

Likewise, when the detector was placed at the end of the string and at a location 30 m further along the conductor, there was no signicant eect on the detected frequencies [START_REF] Johnson | Photovoltaic dc arc fault detector testing at sandia national laboratories[END_REF]. Baseline measurements and arcing measurements at the centers of the strings were taken.

The binned frequency content Fig. 2.16 illustrates that certain frequency ranges are exceeded It can be seen that with T sw = 5 ms and T sw = 25 ms, there is a signicant dierence between no-arcing stage and stable arcing stage. With T sw = 1 ms, the dierence between arcing and no-arcing condition is relatively subtle which shows that 1 ms is too short to include enough current randomness in one single-time window. It can also be seen that with

T sw = 125 ms, the dierence between arcing and no-arcing is still noticeable but is not improved compared with T sw = 5 ms and T sw = 25 ms.

Therefore, a T sw value between 5 and 25 ms is considered appropriate because it is long enough to represent current randomness appropriately with the detection time guaranteed.

T sw starts from 1 ms which involves 200 data points, and is increased by the factor of 5 each 69

D 3 D 4 Cell 1 Cell 2 C 2 S 1 L 1 L 2 L load i L1 i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out

Development of the DC/DC Stage

The DC/DC stage proposal has the capacity of voltage regulation to no more that 400V for security reasons. Considering that the output voltage of the whole system needs to be suited for interconnection with the grid in the range between 150V-250V AC (50 and 60 Hz grids) in order to ensure a proper transfer of energy. The task of reducing voltage can be achieved with a buck converter topology. However, the DC/AC inverter stage of this proposal needs two isolated DC inputs, one for each cascaded cell (Full H bridge) in order to properly 3.2. Development of the DC/DC Stage 71 generate the multilevel output. The use of additional DC sources is considered a disadvantage because it leads to employ additional components such as, voltage and current sensors for monitoring, additional PWM control, etc. All together decreasing the reliability, increases complexity and cost of the converter. A commonly employed solution to this issue is replacing DC sources with pre-charged capacitors, nevertheless, this replacement generates unbalance voltages between DC levels which will increase the output harmonic distortion. In order to achieve a transformerless inverter topology that will integrate the advantages of solid state electronics into the inverter, the development of a novel modied DC/DC converter capable of producing two controlled and isolated DC voltages from a single DC voltage source was needed. This novel architecture of converter was developed in two variants each described in the next two sections.

Isolated Double Boost Converter for DC/DC Stage

In this section and the next, the theoretical functioning for both buck and boost variants of the proposed DC/DC converter are described with detail.

Operational Principle of Double Boost Converter

In the schematic of Fig. 3.1, boost 1 and boost 2 converters have two possible functioning states, one when switch S 1 is in conduction (on) (S 1 = 1) state and second state when is open (o) (S 1 = 0). Due to this, four topological states can be generated when connected in parallel, as showed in Table 3.2.1. These converters extract power from the sources in alternate times, which is achieved with a phase delay of 50% between control signals m 1 and m 2 as illustrated in Fig. 3.3. In order to operate this proposed topology, switching state where S 1 = 0 and S 2 = 0 has to be avoided, in order to conserve ground isolation between boost 1 and boost 2 .

i D 1 i D 2 i D 3 i D 4 1 0 0 (V DC -V C 1 )(1-Duty 1 )T L 1 (V DC -V C 2 )(1-Duty 2 )T L 2
on on on on

2 0 1 (V DC -V C 1 )(1-Duty 1 )T L 1 (V DC Duty 2 T ) L 2 on on o o 3 1 0 (V DC Duty 1 T ) L 1 (V DC -V C 2 )(1-Duty 2 )T L 2
o o on on 4 1 1

(V DC Duty 1 T ) L 1 (V DC Duty 2 T ) L 2 o o o o
One advantage of the boost variant over the buck variant [3] is the possibility to work with a duty cycle higher than 50%. This feature allow the converter to achieve a maximum elevation ratio of 1:10 times the input V DC , when both duty cycle m 1 and m 2 are set to 80%. This achievement represents one of the main contributions of this topology, compared to conventional boost converter elevation capacities of only three times input V DC .

The PWM control signals and variables involved in this converter are presented in Fig.

C 1 , f ) i L 2 and V C 2 g) i Load . S 1 = 0 S 2 = 0 P rohibited State S 1 = 1 S 2 = 0 S 1 = 0 S 2 = 1 S 1 = 1 S 2 = 1 (3.3)
Considering the eqs. (3.1)-(3.3), when the S 1 is in logical state 1, the current through the inductor L 1 results in an energy storage expressed as:

∆i L 1on = 1 L 1 Duty 1 T 0 V DC dt = Duty 1 T L 1 V DC (3.4)
When S 1 is in logical state 0, the current through the inductor L 1 is expressed as,

∆i L 1 of f = T Duty 1 T (V DC -V C 1 )dt L 1 (3.5) ∆i L 1 of f = (V DC -V C 1 )(1 -Duty 1 )T L 1 (3.6)
In Table 3.2.1 the conduction state of the diodes in each switching combination is presented.

The output voltage for the converter can be expressed as:

V C 1 = V DC 1 -Duty 1 (3.7)
Although in any moment that the switch S 1 or S 2 holds a logical state 0, the complementary boost output voltage will depend for a short period on the capacitor resulting in the circuit of Fig. 3.4.

Where Cell 1 acts as a drain current for C 1 , as a consequence, the output voltage during that time will fall. The capacitor C 1 must be able to maintain the voltage for a long period of time when the load is light, otherwise, in order to maintain the voltage, the value of the capacitor has to be wisely selected. The capacitor voltage is related to currents i C 1 and i Cell 1 , both are needed to determine the boost converter output V C 1 supplied to Cell 1 . The i C 1 current for the capacitor is given by:

i c 1 (t) = C 1 dV C 1 (t) dt (3.8)
The capacitor voltage V C 1

V C 1 (t) = 1 C 1 i C 1 (t)dt + V 0 C 1 (3.9) V C 1 (t) = 1 C 1 (i L 1 (t) -i Cell 1 (t))dt + V 0 C 1 (3.10)
When S 1 change from logical 0 to 1, the current i DC 1 (t) becomes zero. Thus, the capacitor voltage during this disconnection time is,

V C 1 (t) = - 1 C 1 i Cell 1 (t)dt + V 0 C 1 (3.11)
The equations described in this section serve as a mathematical fundament for the rst boost converter and the same equations can be applied to describe the behavior of the second boost converter by expressing the equations in terms of boost 2 . In order to obtain Chapter 3. Inverter Proposal for PV Applications the components values, since the alternating behavior of this proposal bases its functioning in a power extraction from the DC source at alternated stages, this behavior doesn't have a repercussion in the interaction between both converters, hence the conventional equations to determine the values of components can be employed.

Double Boost Proposal Switching States

To illustrate the proposed system operation. In Fig. 3.5 are highlighted the current paths corresponding to state 3 of Table 3. An important contribution of this proposed topology is that both converters are able to work beyond 50% of the duty cycle, unlike topologies in [3]. Consequently, a high elevation factor of 1:5 is used in this thesis but a maximum elevation can be attained to reach a ratio of 1:10 by setting m 1 =80% and m 2 =80%. (on) (S 1 = 1 S 2 = 1) and a second state when is open (o) (S 1 = 0 S 2 = 0). The four possible topological combinations that can achieved for this conguration of parallel connected converters, is shown in Table 3.2.2. These converters extract power from the sources in alternate time, and this is achieved thanks to a phase delay of 50% between control signals m 1 and m 2 as described in equation (3.12) and (3.13). The state S 1 = 1 S 2 = 1 and S 3 = 1 S 4 = 1 where both converters will be (on) at the same time has to be avoided to conserve the isolation between buck 1 and buck 2 . This is one limitation of this parallel buck topology, since the maximum duty cycle is of only 50%.

The state 3 of Table 3

i D 1 i D 2 1 0 0 V C 1 L 1 t 1 of f T V C 2 L 2 t 2 of f T on on 2 0 1 V C 1 L 1 t 1 of f T (V DC -V C 2 ) L 2 t 2 on T on on 3 1 0 (V DC -V C 1 ) L 1 t 1 on T V C 2 L 2 t 2 of f T o o 4 1 1 P rohibited P rohibited o o
Considering that:

m 1 =      1 when
∆i L 1on = 1 T Duty 1 T 0 (V DC -V C 1 ) L 1 dt = (V DC -V C 1 ) L 1 t 1 on T (3.14)
When S 1 is in logical state 0, the current through the inductor L 1 is expressed as,

∆i L 1 of f = 1 T T Duty 1 T -V C 1 L 1 dt = -V C 1 L 1 t 1 of f T (3.15)
The state 2 of Table 3.2.2 where S 1 = 0 and S 2 = 1 is presented in Fig. 3.9, considering that current i DC 2 ows from the power supply V DC , from collector-emitter of switch S The voltages V C 1 and V C 2 have to satisfy the asymmetrical ratio determined by: 1,0,0,1 1,0,0,1 The comparisons of the carriers against the sinusoidal 60 Hz fundamental signal will create a pulse that will be employed later to generate the eight signals that will command the IGBT's of this inverter. The schematic circuit for the cascade cells and the boolean logic to obtain each IGBT signal is presented in Fig. 3.12a and Fig. 3.12b. With the detailed description of modeling, control and functioning for both buck and boost DC/DC variants and also for the DC/AC chosen inverter topologies in the next chapter will be presented the simulation and experimental results of the proposed PV inverter.

V C 1 = 3 2 V C 2 (3.16)
V C 1 + V C 2 1,0,0,1 0,1,0,1 V C 1 0,1,0,1 1,0,0,1 V C 2 1,0,0,1 0,1,0,1 V C 1 -V C 2 0,1,0,1 0,1,0,1 0 0,1,0,1 1,0,0,1 -V C 1 + V C 2 0,1,0,1 0,1,0,1 -V C 2 0,1,0,1 0,1,0,1 -V C 1 0,1,0,1 0,1,0,1 -V C 1 -V C 2
c + i =      1 when carry + i < m i 0 when carry + i > m i (3.17) c - i =      1 when carry - i > m i 0 when carry - i < m i (3.

Chapter 4

Inverter Simulation and Experimental Results

Introduction

In this chapter, the functioning of the proposed inverter is evaluated in both simulation and experimental test bench. The results are obtained using M atlab Simulink and the series of test performed are detailed in the following sections.

Simulation Results

In order to evaluate the response of the DC/DC buck and boost variants of the proposed inverter, both are connected to the asymmetrical CCMI, by this the quality of the output is studied. Considering that the voltage generated by each DC/DC stage posses a ripple instead of being constant, the impact of this in the nine-level AC output is evaluated.

86

Chapter 4. Inverter Simulation and Experimental Results

Inverter Buck Variant

In order to perform the simulation of the inverter structure, the software M atlab Simulink is employed, all the parts that need to be included in this simulation are: the new developed of DC/DC stage, the asymmetrical cascade cell multilevel topology, and the respective control strategy for each stage, which was presented in Fig. 3.12a.

Cell 1

Cell 2 In order to obtain these results the simulation values employed are enlisted in Table 4.2.1.

C 2 L 1 L 2 L load i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out
)V C 1 b)iL 1 c)V C 2 d)iL 2 .
To obtain these results was used for the buck variant of the inverter, although depending on the application, the DC/DC stage can be changed to its boost variant.

Components

V alue F requency 2kHz DutyCycle1

45% DutyCycle2 32% L 1 438µH L 2 438µH C 1 2200µF C 2 2200µF Load 47Ω V out 50V p(100V pp)
D 3 D 4 Cell 1 Cell 2 C 2 S 1 L 1 L 2 L load i L1 i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out
, V C 1 , iL 1 , V C 2 , iL 2 ,
and iDC, the only dierence is that the voltage levels reached are higher, given the nature of this DC/DC stage. One of key advantages of using this variant, is a constant current supplied to the DC/AC stage, as can be appreciated in Fig.

)V C 1 b)iL 1 c)V C 2 d)iL 2 e)iDC .
In order to obtain these results the components values employed are enlisted in Table 4.2.2. This simulation is rated to a power of 2 kW. With the results obtained and described in this simulation scenario, the validation of functioning for both inverter variants is completed. And the with the gathered data, the next step is to design the experimental boards for each of the variant, and evaluate the results. This are presented and studied in the appendix section.

Inverter Experimental Implementation Results

In this section will be presented the result obtained by the test of all the converters designed and constructed, which are presented in the appendix section. Each sub-section will describe the behavior of the inverter with buck and boost variants, for each of the dierent test the list of components employed to obtain the results in presented.

Inverter Buck Variant

As can be seen in Fig. 4.9a, 4.9b and 4.10, the signals waveforms obtained in the experimental results for the buck variant of the inverter are consistent.

DC Arc Fault Generation

In order to study the electric DC AF phenomena, the standard UL1699B denes the operational modes necessary to study dierent AF types: Series, parallel, types of loads involved, detection time, and the method how properly to generate an Arc Fault (AF).

Series Arcing Test Connection

In this work the eect of series AF will be studied, using the AF generator device presented in Fig. 5.1. In order to perform the generation of an series AF the description of the main characteristics of the device is described. The simplest AF case of study will result in the schematic circuit presented in Fig. 5.3, this circuit will allow to study the voltage and current signatures of series arc fault type, for an specic type of load. The electrode gap can be adjusted to achieve the desired arc behavior.

The test is conducted by connecting the arc generator in series with the device under test using 6 mm electrodes. An AF generator, build according to standard 1699B specication is employed to perform the experimental results presented in this chapter as shown in Fig.

Converter Conguration for Arcing Test

In order to perform the test that will be presented in the following sections of this work the schematic diagram of Fig. 5.4 will be employed. In this conguration the source is adjusted to 40 V output that is the MPPT controller voltage limit that will be included in the experiments.

Cell 1

Cell 2 The general values employed in the AF experiments are summarized in Table 5.3.1.

C 2 L 1 L 2 L load i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out

Converter Behavior under DC Arc Fault

In this section the behavior of the DC/DC and DC/AC stages of the PV inverter facing an electric DC AF is studied. This signals were extracted from the experimental test bench and signals measured for each case are indicated in the schematic diagrams respectably.

DC/DC converter

In order to conceptualize an innovative DC arc detection strategy, it's fundamental to understand the waveforms involved in each stage of the PV inverter. Also, a deep comprehension of the changes involved in the system with the AF apparition is needed. For this an observatory stage of analysis is described below, were the dierent parts involved in the proposed system are studied when facing a series AF. The goal of this observatory stage is to evaluate the possible exploits for an eective detection criteria.

In order to study the AF eect, the observation stage is separated in the study of the DC/DC and DC/AC stages of the system. The test is performed by generating an AF located in the DC bus. In Fig. The response of the converter is presented in Fig. 5.7. In the rst stage of this experiment it can be seen that the output voltage V out measured in channel 1 (C 1) and current i ( out) in channel 2 (C 2) are constant just before the AF occurs. When the AF ignites, both voltage and current slightly modied during the electrodes priming, during this process the current required by the arc is not elevated due to the fact that the AF as not stable yet, but soon after, when the arc reaches a sustained state, it can be seen that both voltage and current are severely aected, and strong perturbations are visible.

Nonetheless, during these perturbations can be noticed that the AF suers micro interruptions were no current nor voltage is consumed by the AF, these phenomena can be caused by bonded points in the electrodes due to the rise of temperature of electrodes.

Since no regulation algorithm is implemented in this DC/DC stage the converter will follow the uctuations of the arc as long as the arc persist.

The V arc in channel 3 (C3) and i DC in channel 4 (C4) presented also in Fig. 5.7 help to determine if the disturbances present in V out and i out are truly caused by the presence of an AF, this is achieved by verifying if V arc is dierent from zero during the time t under study.

Converter Behavior under DC Arc Fault 103

Using this process for the study of signals we can accurately perform the interpretation of the converter signals and the perturbations that an AF cause in the system, in the next section the DC/AC stage facing an AF is studied.

DC/AC converter

As presented in the 5.4.1 section the AF perturbations produces fast and strong voltage and current variations in the DC/DC converter.

In this section the DC/AC converter implementation presented in Fig. 5.8 is studied under AF as well. The strategic point of measure for this case are V arc , i Cell 1 , i out and V out highlighted in Fig. 5.8.

The results obtained with this converter facing an AF are presented in Fig. 5.9 where we can observe on the left side of the gure a near perfect nine level waveforms measured in C1 and C2 representing V out and I out . In center of Fig. 5.8 when the AF occurs, the voltage V 1 and current i Cell 1 uctuates gure right side. In C3 is presented the arc voltage V arc and in C4 we observe the current delivered from the source to Cell 1 .

The signal V out suer an important deformation with the appearance of the AF, this chaotic and fast variations also observed with the DC/DC converter, aects the balance ratio needed between V 1 and V 2 to generate a balanced nine-level AC output. This interesting phenomena is present in both V out and I out , where the number of levels and symmetry of the signal change from its typical waveforms. This uctuations produce a change in the default harmonic content of a nine level signal.

Both signals V out and I out doesn't seem to be perturbed during the brief millisecond of the electrodes priming before the AF is fully established. Nonetheless, immediately half cycle after the AF appears, the signal V out passes from nine levels to only ve levels, and a complete cycle after the AF, it passes to seven levels.

In C4 current I out experience similar changes when the AF is established. In this case, the most noticeable change is that the signal losses the totality of the upper switching steps, and Chapter 5. Analysis of Internal Signal Perturbations in DC/DC and DC/AC Converters Under AF during the last cycle, we also observe a width steps change. This eect is more pronounced when the V arc variations amplitude become higher.

This lost in the number of levels generated by the multilevel inverter, and the the technique to exploit it for AF detection will be analyzed and explained in chapter 6. From Fig. 5.8

when the arc is established the I arc that in reality is the current supplied to Cell 1 also suer the disturbances losing its periodic characteristic which are explained with the aid of Fig.

5.6.

Cell 1

Cell 2 Considering that both types of converters DC/DC and DC/AC are aected by the appearance of the AF, the changes in voltage and current, and the lost of symmetry can be exploited to achieve detection of the AF, nonetheless another factor that needs further study is the inuence of a common energy extraction optimization algorithm present in most renewable energies systems, and is the MPPT tracking system. The inuence of this control during a series AF is studied in the next section.

L load i load VBridge2 V Bridge1 V out Load DC/AC Stage Cascade Cells Multilevel Inverter V 1 V 2 i Cell1 Arc Fault Varc Iout Vout

Arc Fault Inuence in a MPPT Tracking System

To ensure the optimum power extraction of solar panels, a DC/DC converter is often employed called MPPT tracking. This additional converter can be connected individually for each panel or also installed in series with the DC bus (when panels are arrange in series and parallel to meet the system V/I requirement) by using a single converter. For the next experiments we will employ a single MPPT in series with the source, two possible congurations are studied, with an AF inuence tested by generating it before and after the MPPT converter.

MPPT Arc Fault Test Considerations

In order to perform the experimental tests with a complete structure of the system, the values presented in TABLE 5 With this parameters considered the test are performed by generating a series AF in two dierent scenarios. In the rst case the AF is generated before the MPPT controller, and second the AF in generated after the MMPT. The changes and perturbations observed are described with detail for each case in the next section.

Components

V alue F requency 2kHz

DutyCycle1 45% DutyCycle2 32% L 1 438µH L 2 438µH C 1 2200µF C 2 2200µF Load 47Ω V in 40V V out
50V p(100V pp)

Single Phase Arcing before MPPT Module

To analyze the inuence of an AF in the rst case where the arc is located before the MPPT converter, the schematic diagram presented in Fig. 5.11 is employed, in this test the data acquisition of three waveforms is performed, the rst point of measure corresponds to V Bridge1 measured with C1 in Fig. 5.12, in C2 the V arc is measured, essential signal to conrm if the uctuations in C1 and C3 are related to the AF appearance. Finally in C3 the input current I in is measured.

Arc Fault Inuence in a MPPT

Cell 2 In C2 we observe the V arc , which remains constant until the MPPT controller starts to compensate the loose of voltage caused by the arc. Although, the MPPT control module will attempt to keep the output voltage constants at 40V, regardless of the AF apparition this regulation has no success since it's limited by the elevation capabilities of the converter.

C 2 L 1 L 2 L load i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out Load S 3 C 1 D 1 i Cell2
This behavior can be observed in Fig. 5.12, when the voltage drop surpass the converter capability to regulate, and then the control ability to regulate the voltage is loose and limits the regulation to follow the uctuations generated by the AF only.

Even if the arc is extinguished, the algorithm of the MPPT converter is not capable of recovering its initial stable regulation, so the voltage is distorted even more after the fault has stopped. This phenomena can be observed in the current I in presented in C4.

Single Phase Arcing After MPPT Module

The implemented schematic for this experiment is presented Fig. 5.13. In this section the acquisition of signals will be focus on V out , V arc and I out . The reason behind this change is to validate that the uctuations generated by the AF also aect these points of measure in the converter.

Cell 1

Cell 2 In this case the MPPT presents a similar behavior to the previous case, as presented in Fig.

C 2 L 1 L 2 L load i Cell1 i load V DC V C1 V C2 VBridge2 V Bridge1 V out Load S 3 C 1 D 1 i Cell2

5.14.

In C1 is presented the signal V out , in C2 the V arc and in C3 the I out . For this case is observed that the control algorithm assumes a more active voltage regulation behavior.

Nonetheless, the control is still limited by the amount of current that can be delivered by the MPPT controller.

Because of this limitation, after approximately 0.5 seconds (that is the average reaction time of the MPPT module) of the initial V out drop, the MPPT detect this change, which is traduced in a increased current consumption of the system. In an eort to raise the loose in voltage and thus compensate for the drop detected, the MPPT module will deliver more current, this starts a vicious loop, because by increasing the delivered current, the AF will proportionally augment its current consumption. facing an AF, it can be concluded that the AF has an important impact on the MPPT system.

The control loop malfunctioning of the MPPT facing the AF, caused stronger uctuations in V arc , thus aecting in a important manner V out and I out gradating the T HD of the output signals.

This behavior was observed whether it appears before or after the module, being the failure after the MPPT the more problematic of these two cases. This because it favors the maintenance of the arc, given that the control algorithm will try to deliver more current to the system in an eort to raise the voltage, current that will be consumed by the arc.

With the results obtained in this chapter, we can conclude two facts: the rst is that the internal signals in both types DC/DC and DC/AC converters are aected by the appearance of an AF , and second that the use of a MPPT module in the system does not provide any advantage in the prevention of AF, instead the control algorithm worsted the AF behavior when trying to regulate the voltage drop generated by the AF.

With these is possible to proceed with the development of a detection technique that can take advantage of the AF disturbances in the power converter. This will be presented in next chapter, for both cases: an isolated PV system and for a grid interconnected.

Chapter 6

Study of Harmonics Decomposition

Technique in Both PV Isolated and Interconnected Systems Using Experimental Signals

Introduction

In this chapter will be presented the study of the frequency analysis applied to experimental signals measured on the new multilevel proposal in dierent congurations. Commonly used stand alone and grid interconnected systems will be considered in order to validate the results, these will allow to validate the harmonic decomposition detection technique for AF in low power DC systems. In order to perform the grid interconnected system, the load type is changed at the output of the converter, this since the LCL lter detailed in section 6.5.3 remains the same throughout the dierent tests.

Harmonics in AC Systems Under Normal Operation

In order to fully exploit the changes that appear in the system when facing an AF, the main symmetry characteristics of the inverter have to be studied during normal operation.

The Total Harmonic Distortion (THD) index is employed to study these signals. This represents the measurement of the harmonic distortion present in a signal and is dened as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency.

In conventional AC electric grids, in common conguration or with inverters, the current and voltage waveforms are periodic functions, and they possess half wave symmetry in normal operation. In this condition, the harmonics components that make up the signal is of type Odd.

Harmonics in AC Systems Under Normal Operation 113

With the dierent variety of perturbations that can appear on this systems, the half-wave symmetry remains unaected, nonetheless, in case of an AF this symmetry of the signals are aected, hence a detection approach can be proposed based on this perturbations, as will be analyzed throughout the next sections.

Where V h is dened as the harmonic of order h and θ h has the angle of the harmonic.

For a periodical signal, the THD is dened in equations 6.1 and 6.2 for voltage and current:

T HD V = N h=2 V 2 h V 1 × 100% (6.1) T HD I = N h=2 I 2 h I 1 × 100% (6.2) IHD h = V h V 1 × 100% (6.3)
Equation 6.3 dene the individual harmonics distortion for harmonic h. Equation 6.1 can be rewritten as:

T HD = V 2 2 + V 2 3 + V 2 4 + V 2 5 + ... V 1 × 100% (6.4)
The THD for even and odd harmonic can be dened as:

T HD even = V 2 2 + V 2 4 + V 2 6 + ... V 1 × 100% (6.5) T HD odd = V 2 3 + V 2 5 + V 2 7 + ... V 1 × 100% (6.6)
The THD's dened in 6. It should be noted that under AF conditions, the output AC multilevel signal suers aleatory loose of levels, then changing the THD, increasing the inexistent T HD even . This phenomena results of the half-wave symmetry lost.

In power electronics, the main goal of multilevel converters is to generate as few harmonics as possible, by employing the fewer number of electronics components. With the generation of a stepped waveform (employing cascade cell multilevel topologies as presented in sections 5.5.2 and 5.14) the converter is generating a signal of 60 Hz whose T HD is 15.45 % as shown in Fig. 6.1. To obtain this result the nine levels output voltage is analyzed using Matlab Simulink taking into consideration 5 cycles of the steady state signal. Since the total number of levels generated is a odd number, the harmonics components in the signal will be excursively composed of odd harmonic. This is a key factor to highlight for further analysis of the signals presented in this chapter. In the next section this knowledge will be put into practice by analyzing both type of system, stand alone and grid interconnected systems from a harmonics perspective, which will serve as an ideal introduction to the detection technique proposed in this work. In the other hand when an AF is produced between time 49.8 -166 ms, it can be seen that the arc fault is aecting the waveform of V out . The AF caused a signicant increase of 10-12 % in the total THD, these changes can be easily visualized. With the constant and random variations produced by the arc in the supplied voltage of the multilevel inverter, the balance of voltage between cells (V Bridge1 and V Bridge2) is altered. This aects symmetry of the signal, during this perturbation we can observe a loose of levels in V out and also a the zero crossing time of the voltage is increased.

The multilevel converter generates a nine-level stepped signal, this waveform is the result of the addition of voltage waveforms V Bridge1 and V Bridge2, generated by Cell 1 and Cell 2 of the converter topology. In the graphic of Fig. 6.2 b), the frequency spectrum analysis of V out is presented in blue.

However, has to be noted that the change in this value can easily be modied by several factors that are not related to an AF(Type load, variations in irradiation, instant load changes, etc.). However the THD is composed of two main groups of harmonics, even (T HD even ) and odd(T HD odd ), which can be studied independently, as necessary as presented in Fig. 6.2 b).

When employing a cascade cells multilevel inverter, usually the last cell generates a more complex commutated signal, hence more sensible to perturbations which is ideal for this study.

For this reason the voltage V Bridge2 is the signal employed in the study of experimental tests, this since the perturbations will be more visible as mention before due to the commutation pattern of the converter. A second advantage of measuring this voltage in terminals of each cell , is that the signal doesn't suer any modication despite the type of load.

In addition to this signal, the use of a complementary signal will be explored by measuring I out in the system, this in order to improve the overall performance of the detection. The schematic employed and the points of measurement are presented in Fig. 6.3.

The harmonics decomposition technique presented in Fig. 6.2 b) results fundamental for the proposed detection technique. The base of this relies in the fact that, the voltage output is a nine-level signal. This is translated into a frequency spectrum that is purely composed by "odd" harmonics. Then when an AF appears, it clearly the complete T HD spectrum, but more specic due to the symmetry lost of the original 'purely odd harmonics'(nine-levels)

T HD odd signal, the T HD content is contaminated with pair harmonics. This increase in T HDe after the AF appearance can be exploited by using the converter internal signals.

Ideally, the content of even harmonics in the signal is 0%, however when dealing with real signal, has to be considered that disturbances of the dv/dt type are present due to the IGBT's switching, and other irregularities that will slightly increase this index. This phenomena happen only when an AF in generated in the system, nor changes in the load, radiance modications or complex loads like motors aect this criteria of detection, as validated and presented in the experimental test bench. The harmonic content of the T HD even is a suitable criterion for detection since its only triggers when an arc fault appears.

Cell 1

Cell 2 Since the DC/AC conversion stage generate an approximative waveform of a 60Hz perfect sinusoidal waveform the Fourier analysis can also e applied to V Bridge1 (V H1) and V Bridge2 (V H2) because this two signals shares the same T of the 60Hz fundamental. Interconnected Systems Using Experimental Signals

C 2 L 1 L 2 L load i Cell1 I Load V DC V C1 V C2 VH2 V H1 V out Complex Load S 3 C 1 D 1 i Cell2
Clearly the THD will be high, but if this content is studied by isolating the T HD even component, will be obtained a detection criterion that will remain unaected by changes in the load, irradiation and with a fast response time.

For the experiment performed in Fig. 6.2 a resistive load was used, which has little inuence on the output waveform. In a real scenario, the inverter will face far complex loads of the RLC type. Therefore, to assess the eciency of this criterion, the topology of the inverter is proven by generating arcs with the following four combinations of complex loads: RL, RL, Drill-motor, Vacuum-motor.

AF Inuence Study in a Stand Alone Isolated PV

System

In this section both signals V Bridge2 and I out are considered and analyzed in order to study the variations in T HDe when an AF occurs, its fundamental to verify if the T HDe is not modied despite the dierent type of load feed.

THD Case (1) -Resistive and low inductive load (22ohms + 20mH)

The F F T analysis of V Bridge2 and the harmonics analysis of T HD even and T HD odd are presented in 6.4 a). When the arc ignites T HD strongly rises, above its usual value on steady state. In Fig. 6.4 b) is presented the same harmonic analysis in the zoomed area when the arc appears. During steady state the T HDe oscillates between 1% and 18%, but when the arc ignites this oscillations increased to reach a max of 60%.

In Fig. 6.5 the analysis is performed on I out . Given the inductive nature of the load, the stepped multilevel is smoothed close to a sinusoidal shape.

The I out THD, increases from 14% to 25% with the appearance of the arc, and the T HD even (a) THD analysis of V Bridge2.

(b) T HD even zoomed area of V Bridge2. rises only about a 3% during ignition. The use of this signal as a main detection criteria is not suitable, nonetheless exploitable as a complementary signal. In this case of study, a heavy inductive load is employed, to stress the converter and evaluate if V Bridge2 will still be reliable at terminals of the converter. In Fig. 6.6 a peculiar phenomenon is observed, once the arc is initiated, after passing 1 second the T HDe of V Bridge2 returns to its nominal value. This means that if an arc is triggered during the feeding of an extreme inductive load, the detection system needs to have a response time of We can observe a similar behaviour in the variations of T HDe related to the appearance of the AF. As presented in Fig. 6.6 b), these results are the same as for the low inductive load presented in Fig 6 .4, the only dierence is that the variation of T HDe only last for 0.5 seconds.

Also in Fig. 6.7 the harmonic study of I out is presented, which follows the same behavior of the last experiment presented in Fig. 6.5 with only an small increase of 3% in the T HD even during arc ignition.

THD Case (3) -1200W Hammer-Drill Test

To perform the evaluation of this technique, in detailed and complete manner, a hammer-drill with a power rate of 1200 W is employed as complex load. Despite the fact of being feed not whit his nominal value due to the power to which the inverter is tested, this represents a challenging load since it injects a large amount of distortion type di/dt into I out . The results obtained are presented and analyzed in a similar manner. As for RL type load tested before. In Fig. 6.8 a) the evolution of V H2 during a lapse of 2.5 sec is presented. For this load, the amplitudes of the the THD oscillations increases from its amplitude from 1-18% to 5-33%. Given this observation the AF detection can be perform. Despite disturbances of the di/dt generated by this load, the T HDe index obtained by the FFT on Iout, will still give a accurate detection indication as presented in Fig. 6.9.

THD Case (4) -1200W Vacuum Cleaner Test

For the nal test, a vacuum cleaner of 1200W is employed as load. In Fig. 6.10 a) and b) it's possible to observe the changes in V H2 before and after the AF. In this test an increase in the oscillations of T HD even is observable, similar to the drill test, since the index increased from 1-18% of amplitude to 5-30%. Interconnected Systems Using Experimental Signals And in the analysis of Iout is possible to conclude that the increase in T HD even only during arc ignition is clearly detectable with a peak reaching 8%, as presented in Fig. With the results obtained in the analysis of experimental signal V H2 for the stand alone system, two important facts can be concluded. The rst is that the V H2 signal is reliable to be used as a detection criteria by employing the THD decomposition technique. The reason behind this conclusion is that the experiments tested, as soon as the arc fault is triggered, the appearance of a perturbation in the T HDe is observed, even under extreme conditions with an important value of inductive load.

Thanks to precedent experiments the summary of changes in the THD, T HD even and T HD odd for both V H2 and Iout facing an AF is presented in Fig. 6.12. For the overall cases an increment in the T HD even of approximately 13% is observed in signal V H2 when facing the AF. By considering Iout we also noted that the average increment in T HD even was only of 3% since this value is strongly aected by the load type connected to the inverter.

Nonetheless, this data can eventually be used as an auxiliary criterion to achieve a better detection performance. Another observation is that the output voltage I out is unreliable to be exploited as a main detection criteria, since the THD is perturbed by the type of load that is connected to the system. Thanks to this a dierent alternative to improve detection will be explored and detailed in the section 6.6.

6.5 AF Inuence Study in a Grid Synchronized PV System 6.5.1 Introduction

In the precedent section the tests to explore the possibility of using V H2 and I out as detection criteria was presented. Nonetheless, in most cases the real PV installation will be interconnected to the electrical grid, which may eventually aect the detection signals employed with the THD decomposition technique. In the precedent analysis only the study of complex loads operating in a stand alone conguration was performed. This is for this reason that in this section is presented the experimental results obtained by using a grid connected system. This is achieved by studying the theory needed to achieve the grid coupling of the proposed inverter by an LCL lter. The design of the lter is validated in both simulation and experimental scenarios. Also, the version of the detection algorithm will be updated by analyzing both V H2 & Iin. In order to study a grid interconnected system under fault, the main schematic structure of an modern distribution grid integrating renewable energies sources is presented in Fig. 6.13. In this conguration the main DC sources can be an arrangement of PV panels, as well as wind turbines, or a combination both.

Considering this scenario the structure will include a DC-DC conversion stage (immediately after the source), accomplishing the regulation of voltage levels required by the DC-AC converter. This regulation stage also integrates the MPPT tracking system.

The DC-AC converter is coupled to the electrical grid by using a special conceived lter, the selection of both topologies used will depend of the local regulations for interconnection.

Grid Interconnection

For the smallest power outputs (under 10kW) the most used inverters are the single-phase inverters [START_REF] Nayar | A low cost power electronic interface for small scale wind generators in single phase distributed power generation system[END_REF]. The photovoltaic plants connected to the power network must operate in maximum power output mode of the PV panels. This is achieved by using Maximum Power Point Tracking (MPPT) algorithm integrated in the inverter [START_REF] Raju | Applications of power electronic interfaces for grid connected variable speed wind energy conversion systems[END_REF]. Usually the inverter consists of two parts [START_REF] Tan | Optimum control strategies in energy conversion of pmsg wind turbine system without mechanical sensors[END_REF]: a DC-DC converter with MPPT controller and a DC-AC module (inverter and lter) that produces current with a sinusoidal shape supplied to the power grid as presented in Fig 6 .13. where Vz is the voltage drop on the impedance Ż, Vinv is the RMS value of the rst harmonic of the inverters output voltage and Vgrid is the grid voltage. The phasor-diagram corresponding to eq. 6.7 is shown on Fig. 6.15.

In this gure, the phase angle between the current İout and the voltage Vgrid is less than 90 because of the active-inductive character of the impedance Ż. In real conditions ϕ = 0, so the current and the grid voltage are in phase. In this case the phasor-diagram is as shown of In order to perform the coupling to the grid, numerous parameters have to be considered and depending of this calculation the arrangement for the coupling lter can be determined. The theory behind this calculation will be presented in the next section of this chapter. In this section is described step by step how to proceed with the calculation of each component necessary for the coupling lter. To do this, several characteristics must be considered in the design, such as current ripple, lter size and switching ripple attenuation desired. It's necessary to take into consideration that the reactive power requirements may cause a resonance of the capacitor interacting with the grid, therefore a passive or active damping must be added to the lter, this by including a resistor in series with the capacitor.

In this work, passive damping is adopted, but active solutions can also be applied.

To perform the calculation of values for the lter the following parameters are needed: Line to Line RMS voltage U n (inverter output), rated active power P n , link voltage V DC , grid frequency f g , switching frequency f sw , resonance frequency f res . Thus, the lter values can be obtained in a percentage of the base values as presented in 6.8 and 6.9, this two values represents the impedance of the grid that can have an predominant inductive or capacitive.

Z b = U 2 n P n (6.8) C b = 1 (w g )(Z b ) (6.9)
Adopting 2.7 % impedance for the converter side [START_REF] Mihet-Popa | Modeling, control design and simulation of a grid connection control mode for a small variable-speed wind turbine system[END_REF] [88], a 10 % current ripple can be obtained when using only an L lter. With additional LC part the aim is to reduce the ripple at 2 %:

Z L = Z b (2.7%) (6.10)
The inverter side inductance (L i ) is then:

L i = Z L Wg .
The design of the lter capacity depends from the maximal power factor variation acceptable by the grid is 5%. The lter capacitance can therefore be calculated from C b using eq 6. Considering the reduction in eectiveness caused by the chosen value of r= 165.25Ω the chosen damping resistor value of r is 1.2, the grid side inductance L g can be calculated as:

L g = (r)(L i ).
The last step in the design is the control of the resonant frequency of the lter. The resonant frequency must be higher than the grid frequency and must be minimally one half of the switching frequency, indeed the lter must have enough attenuation in the switching frequency of the converter. The resonant frequency for the LCL lter can be calculated as:

f res = 1 2π L i + L g L i L g C f (6.12)
In order to reduce oscillations and unstable states of the lter, a capacitor should be added with a resistor connected in series. This solution is sometimes called âpassive damping.

It is simple and reliable, but it increases the heat losses in the system and it greatly decreases the eciency of the lter. The value of the damping resistor can be calculated as [START_REF] Mihet-Popa | Modeling, control design and simulation of a grid connection control mode for a small variable-speed wind turbine system[END_REF] [88]:

R d = 1 3w res C f (6.13)
By substituting the parameters of T able 4.2.2 in the equations described in this section, the values obtained for the coupling LCL lter are: In this section are presented the results obtained by employing a improved approach to the study of experiment signals. In order to improve the detection accuracy based in the results obtained in section 6.4.5 the algorithm will benet from employing a more reliable signal with similar characteristics of V Bridge2. Additionally to the monitoring of magnitude in THDe, the idea of using the number of peaks that surpass the normal operation T HDe contained within a single period is explored.

L i = 18mH, L g = 21.6mH, C f = 3.73uF , R f = 165.25Ω
The analysis of V Bridge2 remains unchanged and continue to be compared against the predened experimental normal functioning value of T HDe, from this data the count of exceeding peaks values is stored. This in order to perform a comparison against the actual period and the precedent, serving as a reference of the evolution in T HDe from period to period. This process is illustrated in Fig 6 .18 and 6.19.

After obtaining the T HD content, only the rst 25 harmonics components are considered, then each value of magnitude for each harmonic is separated in two groups, the pair harmonics (T HDe) and the odd harmonics (T HDo) depending of its position in the frequency spectrum.

In this study this method of analysis is studied for signals V H2, I out , I in .

Since the detection algorithm will analyze dierent periodic signals in intervals of one cycle, this means that the length of the proposed analysis sliding window will also correspond to This is presented in Fig. 6.19, where we can observe how the concentration of peaks increase drastically when the AF appears, and continues as long as the AF is sustained.The next step in the strategy to detect AF's is to use number of T HDe peaks within a sliding window repeating this process until analyze the totality of the sampled signal.

The results of employing this approach are presented in Fig. 6.20 where we can observe that ones the proper conditions are meet (programmed in the algorithm and explained in detail in the next section), an AF ag will be activated. This ag is presented in this series of test as a logic value with two possible values 0 and 1 indicating the presence of an AF if the value of this ag becomes 1. Interconnected Systems Using Experimental Signals The analysis of signal Iin, is also included in this study which allows to evaluate its detection potential as a criteria in both type of systems (Stand alone and Grid Interconnected). The T HD analysis as presented in Fig. 6.21 validates that the perturbations in this signal are also important when the AF occurs.

The signal treatment employed in this second section of test will validate the bases for the algorithm, that will achieve eective detection even in complex cases of AF where the fault happens for a few milliseconds generating a small amount of distortion or in multiple AF.

The rst results obtained show that is possible to achieve detection even in complex cases when the AF distortion happens for a few milliseconds. In the next section we consider the results for the stand alone and grid interconnected congurations. Interconnected Systems Using Experimental Signals With the results obtained in the stand alone system, its clear that the use of I out for detection purposes is limited. In order to improve detection performance a new approach is adopted.

The method explained in this section make use of a sliding window that analyses the T HDe of two strategic points of measure V H2 and I in . In the experiments presented the T HDe of I in is added to the monitoring to illustrate the changes when an AF appears.

The main structure of the detection algorithm "Sliding Window Harmonics Component Decomposition Technique" is presented in Fig. 6.22.

The strategy employed by the algorithm consist of periodically analyze the harmonics content in V H2 and I in , this operation is repeated for each cycle, dened as the period T of the 60 Hz output.

Additional the data of the passed cycle N-1 is stored if the T HDe surpass the experimental dened normal operation value.

Its functioning consists rstly in sampling signals V H2 and I in at a rate of 250k/s, then the fast Fourier transform is applied to extract the frequency signature of the signals. The next step is the decomposition of T HD into its two T HD even and T HD odd components. This is of essential importance because the converter under normal operation will output a nine level AC output that results from the combination of V H1 and V H2. The harmonics content of the output voltage is composed exclusively by odd harmonics (this given the number of levels generated). When an AF is present in the system it will alter the signal symmetry hence altering harmonics, this produces T HD even in the system that the algorithm will detect. The second signal presented, is the measured experimental AF voltage and as mentioned before, is a fundamental signal that helps to accurately evaluate the response of the algorithm.

Finally the third signal presented is the frequency signature of I in , this signal is presented in each gure in order to visualize the changes in THD when the AF appears.

The summary of the dierent test performed for the evaluation of the algorithm is presented in Table 6 Resistive Load AF scenario

In order to test the detection capabilities of the algorithm using I in . The rst results using resistive loads of 22Ω and 47Ω are presented below. In Figs. 6.23 and 6.24 we observe two dierent cases of AF. In 6.23 the AF is generated with a small spacing distance between electrodes (noted 'short'). Which will produce an overall constant AF that generates relatively low noise across the frequency spectrum as can be conrmed in I in THD signature. This short distance AF will have a voltage of approximately 35 V.

In Fig. 6.24 the gap between electrodes is increased (noted 'long') to a distance where the AF is still stable, this gap change will cause a strong variations in the AF voltage, hence increase the noise generated. This long gap AF will have an average voltage of around 55 V.

6.7. Performance of the Proposed THD Decomposition Technique with Sliding Window 141

When the AF starts, a peak in the THD of I in also is triggered, this phenomena repeats across the tests presented in this section. This disturbance is employed in the detection algorithm instead of I out signal, since its not aected by the type of load feed as well as V H2. By using both V H2 and I in the algorithm generates the AF ag correctly for both cases. In Figs. 6.25 and 6.26 the AF is generated using the two distance gaps between electrodes as mentioned above, the same protocol is adopted for the following tests. This aim to study the response in more challenging situations for the detection algorithm.

For the study of signals presented the algorithm is congure to stop the AF ag when the AF disappear, in a real application scenario a circuit break will be triggered when the rst AF ag is activated so further AF will not be able to detect since the system will stop functioning.

The AF ag appears at the instant the fault appears in the system. Nevertheless, in both cases it should be noted that only resistors that constitute the simplest of loads employed. In the next test the algorithm capabilities will be analyzed with a various values of RL load.

Resistive-Inductive Load AF scenario

The detection algorithm is tested with a resistive-inductive load as presented in Fig. 6.27, 6.28, 6.29, 6.30, 6.31 and 6.32. The results of Fig. 6.27 and 6.28 are generated with a constant distance between electrodes. As a result the noise level generated by the fault is less important compared to the rest of tests for this type of load. In this results is observed that I in increase hence the perturbation the AF generated.

In this case the algorithm is capable to perform detection accurately by using both signatures V H2 and Iin. Nonetheless it can be seen that the AF ag suers a small delay at the end of some cases, this is due to the fact that the Iin signature takes a approximately 10 ms to regain its periodic waveform when the AF disappears from the system. This delay will be extended if the inductive value increase, because the distortion will be greater hence the time for the signal to recover its original waveform as observed in cases of 31 mH and 51mH.

In Fig. 6.29 and 6.30 the inductive value of 31mH is employed, this will modify considerably the output signal generated by the converter and also increase the distortion levels when an AF appears. Nonetheless the algorithm still detect even with multiple AF as presented in Fig. 6.29 and 6.30.

In order to test the algorithm in a extreme condition the value of inductance is elevated to 51mH. In this case the output signal of the converter is completely sinusoidal and even under this circumstances the detection algorithm achieves detection accurately as can be seen in In a stand alone operation the system will also need to perform detection while feeding complex loads such as motors. For this reason the algorithm is tested with a 1200 W vacuum cleaner, the results are presented in Fig. 6.33 -6.35. In Fig. 6.33 the algorithm manages to detect.

When using a vacuum cleaner as load a peculiar eect is produced, when the AF is present the vacuum cleaner start and stops repeatedly during the AF. This explains why the small and repeatedly AF ags across Fig. 6.33 -Fig. 6.35. As can be seen in this challenging case of detection, the algorithm based in V H2 and I in performs detection successfully. The results presented in this section, validates this detection method across numerous cases of AF in a stand-alone system perform accurate detection without major problems. These results also validate the robustness to sudden load changes as well as to disturbances generated by universal motor loads. In this section will be presented and discussed the result obtained in an experimental scenario by generating an AF in the system, using the calculated coupling lter detailed in section 6.5.3.

LCL Coupling lter AF

For the evaluation of detection performance of the algorithm in an interconnected scenario, the results obtained in Figs. 6.37, 6.38, 6.39 and 6.40 are studied. In this four dierent AF signatures presented the algorithm is able to correctly detect the apparition of the fault and generate the AF ag. Its necessary to be noted that the apparition of the ag is delayed between 15 and 40 ms. These presence of a delay is similar to the delays encountered in the case of an RL load.

The response of the algorithm can be increased with a modication of the sliding window.

Such change can potentially aect the performance for other types of loads, this action can be adopted only in the case of a single well known load.

The AF ag correctly indicate the apparition of the AF in the four cases implemented and presented in this section despite the change in the signals due to the additional lter. These results validate the functioning of the proposed detection approach also in a system interconnected with the electrical grid. For grid-connected systems, it is also important to test the robustness to variations in sunlight. This changes are tested in experimentation by changing the input voltage rst at a slow speed and a secondly at a higher speed.

In Fig. 6.41 and 6.42 are presented two examples of fast radiance changes and the response of the detection algorithm, the voltage is modied from 50V to 30V and then adjusted again to the nominal 50V. In Fig. 6.41 one small distortion AF ag is generated by algorithm, the cause is not clear, since none of the signals V H2 nor Iin presents a high distortion during this period of time. One possible answer is that the variation in the power input source.

Nonetheless the in the rest of test presented in Fig. 6.42 and Fig. 6.43 and 6.44(b) the signal results are obtained correctly with the algorithm given no AF ag when the change in radiance occurs.

The limit of the maximum 'falling' and 'rising' speed of the voltage under a change of radiation, depends of the capacitor value in the DC/DC converter. Depending of this value the charge and discharge speed will equals the falling and rising speed for this particular case of disturbance.

Since this capacitor value is calculated in order to reduce the converters output ripple voltage, its typically calculated value will not aect in a signicant manner the performance of the detection.

Thanks to all the detection results in this thesis, it can be concluded that the approach employed using the peaks value and also the peack concentration within the sliding window allow the algorithm to perform accurate detection under a wide range of loads. This is true not only in an stand alone conguration, but also in an interconnected grid scenario. This was possible thanks to the initial results obtained for the stand alone system. Next a improve detections strategy is adopted by the use of a sliding window that combines the use of an T HDe limit for normal operation in signal V H2 and I in . Additionally, the number of T HDe peaks withing a period of signal V H2 is integrated into the decision stage of the algorithm. This technique was validated in both isolated and grid interconnected congurations with a various types of loads. In the totality of experimental cases presented the proposed algorithm successfully detect the presence of the AF (multiple AF's in certain cases). The eectiveness of detection was not compromised by the load type connected to the inverter or the perturbation related to the changes in PV irradiation. Also, the proposal of real time implementation of the algorithm is described for future development.

iv

  Résumé de ThèseEn 2019, l'EIA (Energy Information Adminitration) a publié l'annual Energy Outlook (AEO) où la projection énergétique pour les Etats-Unis est étudiée et modélisée an de prédire d'une façon approximative la demande d'énergie nécessaire d'ici 2050. Cette étude est basée sur le système national de modélisation énergétique AEO (NEMS), un modèle intégré qui prend en compte les interactions des changements économiques, tels que l'ore et la demande mais également les prix de l'énergie. Selon cette étude, la production d'énergie au moyen de sources renouvelables, comme la production éolien et le solaire photovoltaïque seront les principales sources d'énergies du futur. Le solaire photovoltaïque représentera 48% de la production totale et la production éolienne 25% d'ici l'an 2050, comme le montre la Fig. 1.

Figure 1 .

 1 Figure 1. AEO report of renewable energy production projected to 2050.

Figure 2 .

 2 Figure 2. Distribution Grid arrangement.

Figure 3 .

 3 Figure 3. Potential Arc Fault in PV panels.

Figure 4 .

 4 Figure 4. Inverter proposed system schematic diagram, buck variant.

Figure 5 .

 5 Figure 5. Cascade cells multilevel inverter topology and control.

Figure 6 .

 6 Figure 6. Simulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out .

Figure 7 .

 7 Figure 7. V Bridge1 and V Bridge2 signals obtained using DC/DC Buck variant.

Figure 8 .

 8 Figure 8. Voltage and current waveforms of the nine-levels AC output, using buck variant.

Figure 9 .Figure 10 .Figure 11 .

 91011 Figure 9. Experimental Test bench.

  que se base la stratégie de détection présentée dans ces travaux. La perte de niveaux associée à l'apparition est une d'arcs est une perturbation spécique des défauts d'arc. Par contre, les modications du rayonnement solaire sur le panneau n'aectent pas la symétrie des ondes comme le fait l'apparition d'arc. Dans le mode de fonctionnement neuf niveaux du convertisseur (dans un mode de fonctionnement sans défaut dans le circuit), l'analyse spectrale de la tension montre que le xiv spectre est exclusivement composé d'harmoniques impaires. Cela signie qu'avec l'apparition d'un arc, la symétrie de l'onde est modieé et la quantité d'harmoniques paires (inexistante en fonctionnement normal) se voit augmentée brusquement à l'apparition d'arcs (taux de distorsion d'harmoniques paires donc T HDe).

Figure 12 .Figure 13 .

 1213 Figure 12. Multilevel waveforms obtained under AF.

Figure 14 .

 14 Figure 14. AF Testing protocol for dierent loads, with highlighted measuring points.

Figure 15 .

 15 Figure 15. V Bridge2 harmonics decomposition.

Figure 16 .

 16 Figure 16. I out THD Decomposition technique.

Figure 17 .Figure 18 .

 1718 Figure 17. Summary of Results for AF Tests.

Figure 19 .

 19 Figure 19. T HDe peak saturation analysis before and after an AF.

Figure 20 .

 20 Figure 20. V H2 and AF Flag comparison.

Figure 21 .Figure 22 .

 2122 Figure 21. Multiple AF scenario with a 47Ω load.

Figure 23 .

 23 Figure 23. AF test side by side with a resistive switched load and its eect in the THD content.

4 . 4

 44 Stimulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out .4.5 Schematic diagram of the inverter boost variant. . . . . . . . . . . . . . . . . 4.6 Simulink resulting schematic diagram of the Fig. 4.5. . . . . . . . . . . . . . 4.7 Simulation results of the DC/DC stage a)V C 1 b)iL 1 c)V C 2 d)iL 2 e)iDC . . . .

Figure 1 . 1 .

 11 Figure 1.1. Schematic diagram of proposed converter in [1].

Chapter 1 .

 1 IntroductionThe most common DC arc faults are classied as: ground fault, line to line fault, hot spot formation, polarity mismatch, PV arc fault, open fault, bypass diode and dust/soil formation in a PV array. Where the ground fault, line to line fault and PV arc fault are the mayor responsible for what is called a catastrophic failure[START_REF] Alam | A comprehensive review of catastrophic faults in pv arrays: Types, detection, and mitigation techniques[END_REF].

2 . 3 . 4 .

 234 To propose an electric DC arc fault detection technique base on the operation of the proposed PV inverter. Develop an electric DC arc fault generator based on the UL1699B. Validate the proposed PV inverter and the DC arc fault detector under dierent load conditions and arc fault locations.

1 . 1 . 7 .

 117 B. Vidales, J. L. Monroy-Morales, J.R. Rodríguez-Rodriguez, M. Madrigal and D. Torres-Lucio, "A transformerless topology for a micro inverter with elevation factor of 1:10 for photovoltaic applications," International Journal of Electrical P ower and Energy Systems, ELSEVIER, Volume 109, June 2019, Pages 504-512, ISSN 0142-0615. Results of this Research Chapter 2 Inverter for PV Applications and electric DC arc Fault Detection 2.

48 Chapter 2 . 1 Figure 2 . 1 .

 482121 Figure 2.1. AEO report of renewable energy production projected to 2050.

Figure 2 . 2 .

 22 Figure 2.2. Main structure of a PV installation.

Figure 2 . 3 .

 23 Figure 2.3. Schematic diagram of three-level NPC MLI.

Figure 2 . 4 .

 24 Figure 2.4. Schematic diagram of four-level FLC MLI.

2. 4 . 55 Figure 2 . 5 .

 45525 Figure 2.5. Schematic diagram of nine-level CCMI.

Figure 2 . 6 .

 26 Figure 2.6. Output DC voltage and current of a PV array under normal and AF conditions.

58 Chapter 2 .

 582 Inverter for PV Applications and electric DC arc Fault DetectionValues a, b, c and d are constants, while V arc , I arc , and L are arc voltage, current, and length, respectively. Two other signicant aspects of PV arc faults are arc temperature and burn-through time of CCC insulation. Burn-through time depends on the temperature, power density, metals and adjacent materials, also radiative heating can ignite ammable materials near the arc fault. Therefore, use of re-retardant materials may help extinguish the arc and abate subsequent re hazards in a PV array[START_REF] Bower | Electrical and thermal nite element modeling of arc faults in photovoltaic bypass diodes[END_REF]. Fig. 2.8 shows an DC arc fault generator. The circuit of Fig. 2.8 is dened for an arc of xed length. In the low-current

Figure 2 . 8 .

 28 Figure 2.8. AF generator schematic diagram.

Figure 2 . 9 .

 29 Figure 2.9. Main blocks diagram of a PV installation.

Figure 2 .

 2 Figure 2.10. PV system current signature tested with two dierent inverters and without inverter, after an AF scenario.

Figure 2 .

 2 Figure 2.11. PV system current signatures tested with two dierent types of inverter and without it, under AF scenario.

Figure 2 .

 2 Figure 2.12. PV system current signatures tested with two dierent types of inverter and without it, under AF scenario.

Figure 2 .

 2 Figure 2.13. Single string current waveform for PV congurations of Table 2.5.1.

Figure 2 . 14 .

 214 Figure 2.14. String current arc signatures, applying DFT for 0.10s subsections.

Figure 2 .

 2 Figure 2.15. PV modules distribution for noise recording in tests of Sandia Labs.

Figure 2 . 16 .

 216 Figure 2.16. Noise recordings with AF scenario and baseline system in DETL.

Figure 2 . 17 . 3 Inverter

 2173 Figure 2.17. Idif waveform from dierent time window length (a) T sw= 1 ms. (b) T sw=

Figure 3 . 1 .Figure 3 . 2 .

 3132 Figure 3.1. Inverter proposed system schematic diagram, Boost variant.

3 . 3 (

 33 a)-(g). The Carry 1 and Carry 2 are sawtooth signals which are compared to a DC signal in order to achieve the desired duty cycles. For m 1 and m 2 , the output voltages of boost 1 and boost 2 V C 1 and V C 2 are controlled. The generation of m 1 and m 2 is based on equations (3.1) and (3.2). These pulses are applicable to switches S 1 and S 2 . As showed in Fig. 3.3(a) and (c), Carry 1 and Carry 2 are out of phase in order to obtain the alternated behavior of this proposal which is described in the next section. The currents in the inductors iL 1 and iL 2 are shown in Fig. 3.3 e) and f ) respectively. As shown, these boost converters are working in a continuous conduction mode. Equation (3.3) shows the possible combinations between S 1 and S 2 .

1 when 2 ( 3 . 2 )Figure 3 . 3 .

 123233 Figure 3.3. Control strategy for boost variant converter; a) Carry 1 and Duty 1 , b) Pulsem 1 c) Carry 2 and Duty 2 , d) Pulse m 2 , e) i L 1 and V C 1 , f ) i L 2 and V C 2 g) i Load .

Figure 3 . 4 .

 34 Figure 3.4. Discharging circuit during state 0.

2 . 1 .Figure 3 . 5 .

 2135 Figure 3.5. Proposed topology in switching state 3 where S 1 =1, S 2 =0 with highlighted currents paths.

Figure 3 . 6 .

 36 Figure 3.6. Proposed topology in switching state 2 where S 1 =0, S 2 =1 with highlighted currents paths.

Figure 3 . 7 .

 37 Figure 3.7. Proposed topology in switching state S 1 =1, S 2 =1 with highlighted currents paths.

Figure 3 .

 3 Figure 3.10. Multilevel V out for cascaded converter.

3. 3 . 83 3. 3 . 2

 38332 Multilevel DC/AC Stage Nine-Level SPWM ModulationThe employed multilevel modulation technique in this paper uses eight modulating waves carriers. These signals can be constant voltage levels to generate a multiple pulse width modulation (MPWM), triangular, sawtooth or sinusoidal waveforms to generate a sinusoidal pulse width modulation (SPWM). This process is illustrated in Fig.3.11.

Figure 3 .

 3 Figure 3.11. Nine-level SPWM technique.

  18) (a) Boolean logic combination for a nine-level asymmetrical inverter. (b) CCMI schematic circuit for a nine-level asymmetrical inverter.

Figure 3 . 12 .

 312 Figure 3.12. Cascade cells multilevel inverter topology and control.

Figure 4 . 1 .

 41 Figure 4.1. Schematic diagram of the smart inverter buck variant.

Figure 4 . 2 .

 42 Figure 4.2. Simulink resulting schematic diagram of the Fig. 4.1.

Figure 4 . 3 .

 43 Figure 4.3. Stimulation results of the DC/DC stage a)V C 1 b)iL 1 c)V C 2 d)iL 2 .

Figure 4 . 4 .

 44 Figure 4.4. Stimulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out .

4. 2 . 2

 22 Inverter Boost VariantIn this section are to be submitted the simulation results obtained with the inverter, employing the DC/DC boost variant. To obtain these results the schematic of Fig. 4.5 is employed, by representing all components needed in M atlab Simulink, the resulting schematic diagram is shown in Fig. 4.6. With this conguration are obtained the results of

Figure 4 . 5 .

 45 Figure 4.5. Schematic diagram of the inverter boost variant.

Fig. 4 . 7 ,

 47 Fig. 4.7, in this graphic are presented the same signals as for the simulation of the buck variant, V C 1 , iL 1 , V C 2 , iL 2 , and iDC, the only dierence is that the voltage levels reached

4. 7 .

 7 Concerning V C 1 and V C 2 it can be seen that the voltage generated is constant, which help to keep the integrity of the multilevel output.

Figure 4 . 6 .

 46 Figure 4.6. Simulink resulting schematic diagram of the Fig. 4.5.

Figure 4 . 7 .

 47 Figure 4.7. Simulation results of the DC/DC stage a)V C 1 b)iL 1 c)V C 2 d)iL 2 e)iDC .

Figure 4 . 8 .

 48 Figure 4.8. Simulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out .

  Voltage and current waveforms of V Bridge1 (b) Voltage and current waveforms of V Bridge2

Figure 4 . 9 .

 49 Figure 4.9. V Bridge1 and V Bridge2 signals obtained using DC/DC Buck variant.

4. 3 . 2

 32 Inverter Boost VariantSimilar to the results of the last section it can be seen in Fig.4.11a, 4.11b and 4.12, the signals waveforms obtained in the experimental results for the boost variant of the inverter are consistent as well.

Figure 4 .

 4 Figure 4.10. Voltage and current waveforms of the nine-levels AC output, using buck variant

Figure 4 .

 4 Figure 4.11. V Bridge1 and V Bridge2 signals obtained using DC/DC boost variant.

Figure 4 .

 4 Figure 4.12. Voltage and current waveforms of the nine-levels AC output, using boost variant.

Figure 4 . 96 Chapter 5 .

 4965 Figure 4.13. Experimental test bench.

Figure 5 . 1 .

 51 Figure 5.1. UL1699B AF generator mechanism diagram

Figure 5 . 2 .

 52 Figure 5.2. AF generation "Fixed Distance Ignition".

Chapter 5 .

 5 Analysis of Internal Signal Perturbations in DC/DC and DC/AC Converters Under AF 5.1.

Figure 5 . 3 .

 53 Figure 5.3. AF Load Study Schematic Diagram.

1 SFigure 5 . 4 .

 154 Figure 5.4. UL1699B AF generator mechanism diagram

Figure 5 . 5 .

 55 Figure 5.5. DC/DC stage (Buck variant), with highlighted measuring point.

Figure 5 . 6 .

 56 Figure 5.6. Current waveform i DC delivered for the DC/DC stage.

Figure 5 . 8 .

 58 Figure 5.8. Cascade cells conguration for AF testing.

Figure 5 . 9 .

 59 Figure 5.9. Multilevel waveforms obtained under AF.

  .5.1 are employed. The selection of components was based in the operating values of the chosen MPPT control module ('SM72445' by Texas Instruments) presented in Fig 5.10. This module is capable of a constant regulation of up to 40V.

Figure 5 .

 5 Figure 5.10. Texas Instruments MPPT Prototyping Board.

Figure 5 . 11 .

 511 Figure 5.11. Schematic diagram for AF testing with AF before MPPT module.

Figure 5 . 12 .

 512 Figure 5.12. Experimental results of arcing before MPPT module.

Figure 5 . 13 .

 513 Figure 5.13. Schematic diagram for AF testing with AF after MPPT module.

Figure 5 . 14 .

 514 Figure 5.14. Experimental results of arcing after MPPT module.

Figure 6 . 1 .

 61 Figure 6.1. THD study of multilevel waveform.

6. 3 . 6 . 3

 363 Signals Analysis Guidelines for Stand Alone System Tests 115 Signals Analysis Guidelines for Stand Alone SystemTestsThe initial test is performed using resistive a load, with this conguration the signal obtained is presented in Fig.6.2. The method employed for the analysis of experimental signals is performed using Matlab. First the experimental signals V Bridge2 and I out are sampled at 250ks/s across 2.5 sec (T = 4166 samples), and in this particular case a zoomed window of 9 period (since the output of the converter is a 60 Hz T =16.66ms [9T =149ms]) is presented where the AF is triggered in order to visualize the change in harmonics and exploit these as a detection criteria for series AF.Then the FFT calculation (represented across time) is performed to the entire length of the experimental signals and presented in Fig.6.2 b). We observe the converter operating under normal conditions from time 0 -49.8 ms, where the voltage presents no alteration and the nine-level waveform is generated without perturbation.

Figure 6 . 2 .Chapter 6 .

 626 Figure 6.2. THD decomposition in T HD even and T HD odd before and after an AF.

Figure 6 . 3 .

 63 Figure 6.3. AF Testing protocol for dierent loads, with highlighted measuring points.

Figure 6 . 4 .

 64 Figure 6.4. V Bridge2 harmonics decomposition.

Figure 6 . 5 .

 65 Figure 6.5. I out THD Decomposition technique.

Figure 6 . 6 .

 66 Figure 6.6. V Bridge2 harmonics decomposition.

Figure 6 . 7 .

 67 Figure 6.7. Iout Harmonic Decomposition.

  (a) THD analysis of V H2.(b) T HD even analysis with zoomed area of V H2.

Figure 6 . 8 .

 68 Figure 6.8. V H2 harmonics decomposition.

Figure 6 . 9 .

 69 Figure 6.9. I out THD analysis for hammer-drill load.

Figure 6 .

 6 Figure 6.10. V H2 harmonics decomposition.

Figure 6 . 11 .

 611 Figure 6.11. Iout THD analysis for vacuum load.

Figure 6 . 12 .

 612 Figure 6.12. Summary of Results for AF Tests.

Figure 6 . 13 .

 613 Figure 6.13. Distribution Grid arrangement.

Figure 6 . 14 .

 614 Figure 6.14. Schematic diagram of impedance between the converter and the grid.

Fig. 6 .

 6 Fig. 6.15 b.

Figure 6 .

 6 Figure 6.15. Phasor-diagram of the voltages and currents of the single-phase inverter.

6. 5 .

 5 AF Inuence Study in a Grid Synchronized PV System 129 6.5.3 Coupling LCL Filter Design Procedure

  When this values are calculated, the actual connection is performed following the schematic diagram presented in Fig.6.16.

Figure 6 .

 6 Figure 6.16. LCL coupling lter schematic.

Figure 6 . 17 .

 617 Figure 6.17. Nine level inverter voltage and LCL coupling lter smoothed voltage.

  one period, and since the signals under study have a base frequency of 60 Hz the sliding window will posses a length of 16 ms. For the next series of experimental tests the length of the recorded signals V Bridge2 and I in is increased from 2.5 sec to 10 sec allowing to generate multiple AF in a single sample.

Figure 6 .

 6 Figure 6.18. T HDe Analysis of V H2 before and after an AF.

Figure 6 .

 6 Figure 6.19. T HDe peak saturation analysis before and after an AF.

Figure 6 .

 6 Figure 6.20. V H2 and AF Flag output comparison.

Figure 6 .

 6 Figure 6.21. T HD Analysis of Iin.

6. 7

 7 Performance of the Proposed THD Decomposition Technique with Sliding Window 6.7.1 Introduction

6. 7 .Figure 6 . 22 .

 7622 Figure 6.22. Proposed electric DC AF detection algorithm.

Figure 6 .

 6 Figure 6.23. Single AF with a 22Ω load, constant electrodes spacing, detection algorithm result.

Figure 6 .

 6 Figure 6.24. Single AF with a 22Ω load, variable electrodes spacing, detection algorithm result.

6. 7 .Figure 6 . 25 .

 7625 Figure 6.25. Multiple AF scenario with a 47Ω load.

Figure 6 .

 6 Figure 6.26. Multiple AF scenario with a 47Ω load.

Fig. 6 .Figure 6 . 27 .

 6627 Fig. 6.31 and 6.32. Until this point it can be concluded that both signals V H2 and I in are reliable signals to perform AF detection.

Figure 6 . 28 .

 628 Figure 6.28. Test 2 with RL of 22Ω and 5mH load.

Figure 6 . 29 .

 629 Figure 6.29. Test 3 with RL of 22Ω and 31mH load.

Figure 6 . 30 .

 630 Figure 6.30. Test 4 with RL of 22Ω and 31mH load.

6. 7 .Figure 6 . 31 .

 7631 Figure 6.31. Test 5 with RL of 22Ω and 51mH load.

Figure 6 .

 6 Figure 6.32. Test 6 with RL of 22Ω and 51mH load.

Figure 6 . 33 .Figure 6 . 34 .

 633634 Figure 6.33. Test 1 algorithm results, 1200 W vacuum load.

Figure 6 .

 6 Figure 6.35. Test 3 for Vacuum cleaner of 1200W.

Figure 6 .

 6 Figure 6.36. AF test side by side with a resistive switched load and its eect in the THD content.

6. 7 .

 7 Performance of the Proposed THD Decomposition Technique with Sliding Window 151 6.7.6 Grid Synchronized PV System Study

Figure 6 .

 6 Figure 6.37. AF test 1 with coupling LCL lter.

Figure 6 .Figure 6 . 39 .

 6639 Figure 6.38. AF test 2 with coupling LCL lter.

Figure 6 .

 6 Figure 6.40. AF test 4 with coupling LCL lter.

6. 7 .Figure 6 . 41 .

 7641 Figure 6.41. Test 1 -fast radiation uctuation in the DC input source.

Figure 6 .Figure 6 . 43 .

 6643 Figure 6.42. Test 2 -fast radiation uctuation in the DC input source.

Figure 6 . 7 Conclusions

 67 Figure 6.44. Test 4 -slow radiation uctuation in the DC input source.

Figure A. 1 .

 1 Figure A.1. Schematic diagram of an ungrounded PV system.

Figure A. 2 .

 2 Figure A.2. Schematic diagram of a grounded PV system.

  (a) Bottom layer of the isolated double boost converter. (b) 3D Representation of physical converter.

Figure B. 3 .

 3 Figure B.3. Design of isolated double boost converter.

Figure B. 5 .

 5 Figure B.5. Developed double DC/DC boost converter (left) and full H bridge (Right).

TABLE 0 .

 0 0.3. AF Algorithm testing with dierent loads.

	Loads &	V alue of Load
	N umber of AF tested
	Resistance 5	47Ω
	Resistance 5	22Ω
	Resistive 47Ω Inductive 5 each = 15 5mH, 30mH, 58mH
	Resistive 22Ω Inductive 5 each = 15 5mH, 30mH, 58mH
	Resistive 22Ω + 1200W V acuum 5	F ast speed
	Resistive 22Ω + 1200W V acuum 5	Slow speed
	LCL Couplin F ilter 5	LCL F ilter V alues
	T otal 55

  renewable energy production projected to 2050. . . . . . . . . iv Distribution Grid arrangement. . . . . . . . . . . . . . . . . . . . . . . . . . vi Potential Arc Fault in PV panels. . . . . . . . . . . . . . . . . . . . . . . . . vi Inverter proposed system schematic diagram, buck variant. . . . . . . . . . . viii Cascade cells multilevel inverter topology and control. . . . . . . . . . . . . . Proposed electric DC AF detection algorithm. . . . . . . . . . . . . . . . . . Test 2, algorithm results with 1200 W vacuum load. . . . . . . . . . . . . . . xxii 23 AF test side by side with a resistive switched load and its eect in the THD content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main structure of a PV installation. . . . . . . . . . . . . . . . . . . . . . . . 2.3 Schematic diagram of three-level NPC MLI. . . . . . . . . . . . . . . . . . . Inverter proposed system schematic diagram, Buck variant. . . . . . . . . . . Control strategy for boost variant converter; a) Carry 1 and Duty 1 , b) Pulse m 1 c) Carry 2 and Duty 2 , d) Pulse m 2 , e) i L 1 and V C 1 , f ) i L 2 and V C 2 g) i Load . Proposed topology in switching state 3 where S 1 =1, S 2 =0 with highlighted currents paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Proposed topology in switching state 2 where S 1 =0, S 2 =1 with highlighted currents paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

	xxiv	List of Figures	xxvii
		N P C 3.1	Neutral Point Clamped Inverter proposed system schematic diagram, Boost variant. . . . . . . . . .
		F LC 3.2	Flying Capacitor
	IGBT CCM I EM I U P S DET L DF T T ws M P W M Multiple Pulse Width Modulation Insulated Gate Bipolar Transistor Cascade Cells Multilevel Inverter Electro Magnetic Interference Uninterpretable Power Supply Distributed Energy Technologies Laboratory Discrete Fourier Transform Time Windows List of Figures 1.1 Schematic diagram of proposed converter in [1]. . . . . . . . . . . . . . . . . 1.2 Schematic diagram of proposed converter in [2] . . . . . . . . . . . . . . . . . 2.1 AEO report of renewable energy production projected to 2050. . . . . . . . . 3.3 3.4 Discharging circuit during state 0. . . . . . . . . . . . . . . . . . . . . . . . . 3.5 AEO report of xxii 2.2 3.6
		AF SP W M	Electric Arc Fault Sinusoidal Pulse Width Modulation
		P V T HD	Photovoltaic Total Harmonic Distortion
		AF DD T HD even Total Even Harmonic Distortion Arc Fault Detection Devices
		DC T HD odd	Direct Current Total Odd Harmonic Distortion
		AC		Alternating Current
		DC/AC	Direct Current to Alternating Current
		M P P T	Maximum Power Point Tracking
		N CC	Non Current Carrying
		CCC	Current Carrying Conductor
		EGC	Equipment Grounding Conductor
		N EC	National Electric Code
		AF CI	Arc Fault Circuit Interrupter
		kW		kilowatt = 1000 Watts
		RC		Resistive Capacitive
		RLC	Resistive Inductive and Capacitive
		EIA	Energy Information Administration
		AEO	Annual Energy Outlook
		N EM S	National Energy Modeling System
		M LC	Multilevel Converter
		M LI	Multilevel Inverter
				xxiii

viii Simulation results of the DC/AC stage a)V Bridge1, b)V Bridge2, c)V out , d)I out . ix V Bridge1 and V Bridge2 signals obtained using DC/DC Buck variant. . . . x Voltage and current waveforms of the nine-levels AC output, using buck variant. x Experimental Test bench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii AF Generation device UL1699B. . . . . . . . . . . . . . . . . . . . . . . . . . xii AF Load Study Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . xiii Multilevel waveforms obtained under AF. . . . . . . . . . . . . . . . . . . . . xiv THD decomposition in T HD even and T HD odd before and after an AF. . . . xv AF Testing protocol for dierent loads, with highlighted measuring points. . xv V Bridge2 harmonics decomposition. . . . . . . . . . . . . . . . . . . . . . . xvi I out THD Decomposition technique. . . . . . . . . . . . . . . . . . . . . . . . xvi Summary of Results for AF Tests. . . . . . . . . . . . . . . . . . . . . . . . . xvii xviii T HDe peak saturation analysis before and after an AF. . . . . . . . . . . . xix V H2 and AF Flag comparison. . . . . . . . . . . . . . . . . . . . . . . . . . xix Multiple AF scenario with a 47Ω load. . . . . . . . . . . . . . . . . . . . . . xxi xxv xxvi List of Figures 22 2.4 Schematic diagram of four-level FLC MLI. . . . . . . . . . . . . . . . . . . . 2.5 Schematic diagram of nine-level CCMI. . . . . . . . . . . . . . . . . . . . . . 2.6 Output DC voltage and current of a PV array under normal and AF conditions. 2.7 The volt-ampere (V-I) characteristics of electric arcs fault. . . . . . . . . . . 2.8 AF generator schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Main blocks diagram of a PV installation. . . . . . . . . . . . . . . . . . . . 2.10 PV system current signature tested with two dierent inverters and without inverter, after an AF scenario. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 PV system current signatures tested with two dierent types of inverter and without it, under AF scenario. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 PV system current signatures tested with two dierent types of inverter and without it, under AF scenario. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13 Single string current waveform for PV congurations of Table 2.5.1. . . . . . 2.14 String current arc signatures, applying DFT for 0.10s subsections. . . . . . . 2.15 PV modules distribution for noise recording in tests of Sandia Labs. . . . . . 2.16 Noise recordings with AF scenario and baseline system in DETL. . . . . . . 2.17 Idif waveform from dierent time window length (a) T sw= 1 ms. (b) T sw= 5 ms. (c) T sw = 25 ms. (d) T sw = 125 ms. . . . . . . . . . . . . . . . . . . 2.18 Baseline AF signature to perform calculations. . . . . . . . . . . . . . . . . . 3.7 Proposed topology in switching state S 1 =1, S 2 =1 with highlighted currents paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Proposed topology buck variant in switching state S 1 =1, S 2 =0 with highlighted currents paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Proposed topology buck variant in switching state S 1 =0, S 2 =1 with highlighted currents paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Multilevel V out for cascaded converter. . . . . . . . . . . . . . . . . . . . . . . 3.11 Nine-level SPWM technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Cascade cells multilevel inverter topology and control. . . . . . . . . . . . . . 4.1 Schematic diagram of the smart inverter buck variant. . . . . . . . . . . . . . 4.2 Simulink resulting schematic diagram of the Fig. 4.1. . . . . . . . . . . . . . 4.3 Stimulation results of the DC/DC stage a

  .11 V Bridge1 and V Bridge2 signals obtained using DC/DC boost variant. . . . 4.12 Voltage and current waveforms of the nine-levels AC output, using boost variant. 4.13 Experimental test bench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I out THD analysis for hammer-drill load. . . . . . . . . . . . . . . . . . . . . 6.10 V H2 harmonics decomposition. . . . . . . . . . . . . . . . . . . . . . . . . . Summary of Results for AF Tests. . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Distribution Grid arrangement. . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 Schematic diagram of impedance between the converter and the grid. . . . .

	xxx	List of Figures	List of Figures	xxix
		6.37 AF test 1 with coupling LCL lter. . . . . . . . . . . . . . . . . . . . . . . . 6.38 AF test 2 with coupling LCL lter. . . . . . . . . . . . . . . . . . . . . . . . 6.39 AF test 3 with coupling LCL lter. . . . . . . . . . . . . . . . . . . . . . . . 6.12 6.15 Phasor-diagram of the voltages and currents of the single-phase inverter. . . 6.40 AF test 4 with coupling LCL lter. . . . . . . . . . . . . . . . . . . . . . . .
		5.1	UL1699B AF generator mechanism diagram . . . . . . . . . . . . . . . . . .
	5.2 6.41 Test 1 -fast radiation uctuation in the DC input source. . . . . . . . . . . . AF generation "Fixed Distance Ignition". . . . . . . . . . . . . . . . . . . . . 6.16 LCL coupling lter schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 Nine level inverter voltage and LCL coupling lter smoothed voltage. . . . . 6.42 Test 2 -fast radiation uctuation in the DC input source. . . . . . . . . . . . List of Tables Contents Chapter 1
		5.3	AF Load Study Schematic Diagram.	. . . . . . . . . . . . . . . . . . . . . .
		6.18 T HDe Analysis of V H2 before and after an AF. . . . . . . . . . . . . . . . . 6.43 Test 3 -slow radiation uctuation in the DC input source. . . . . . . . . . .
		5.4	UL1699B AF generator mechanism diagram . . . . . . . . . . . . . . . . . .
		6.19 T HDe peak saturation analysis before and after an AF. . . . . . . . . . . . 6.44 Test 4 -slow radiation uctuation in the DC input source. . . . . . . . . . .
		5.5	DC/DC stage (Buck variant), with highlighted measuring point. . . . . . . .
	5.6 A.1 Schematic diagram of an ungrounded PV system. . . . . . . . . . . . . . . . Current waveform i DC delivered for the DC/DC stage. . . . . . . . . . . . . 6.20 V H2 and AF Flag output comparison. . . . . . . . . . . . . . . . . . . . . . 0.0.1 Test Bench Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbols and Abbreviation xxiii	xi
			6.21 T HD Analysis of Iin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.0.3 AF Algorithm testing with dierent loads. . . . . . . . . . . . . . . . . . . .	xx
	5.7 5.8 A.3 RC model representation of PV panel. . . . . . . . . . . . . . . . . . . . . . Conventional DC/DC boost converter behavior, before and after an AF. . . Cascade cells conguration for AF testing. . . . . . . . . . . . . . . . . . . . 1.1.1 Single Sourced Converters Comparison . . . . . . . . . . . . . . . . . . . . . 6.22 Proposed electric DC AF detection algorithm. . . . . . . . . . . . . . . . . . A.2 Schematic diagram of a grounded PV system. . . . . . . . . . . . . . . . . . List of Figures xxv
	5.9 A.4 Potential points of internal fault in a PV panel . . . . . . . . . . . . . . . . . Multilevel waveforms obtained under AF. . . . . . . . . . . . . . . . . . . . . 6.23 Single AF with a 22Ω load, constant electrodes spacing, detection algorithm 2.5.1 PV Congurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Tables xxxi
			result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
	5.10 Texas Instruments MPPT Prototyping Board. . . . . . . . . . . . . . . . . . 6.24 Single AF with a 22Ω load, variable electrodes spacing, detection algorithm A.5 Potential points of fault in a PV array . . . . . . . . . . . . . . . . . . . . . 3.2.1 Boost Variant Switching States. . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction 36
		5.11 Schematic diagram for AF testing with AF before MPPT module. . . . . . . A.6 Arc Fault damage in a 10 kW installation, due to inappropriate AF handling.
		1.1	result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Buck Variant Switching States. . . . . . . . . . . . . . . . . . . . . . . . . . PV Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
		5.12 Experimental results of arcing before MPPT module. . . . . . . . . . . . . . A.7 V-I characteristics curves of AF for dierent materials of electrodes. . . . . .
		1.2	6.25 Multiple AF scenario with a 47Ω load. . . . . . . . . . . . . . . . . . . . . . 3.3.1 Stepping Logic for a Nine-Level Converter. . . . . . . . . . . . . . . . . . . . Electric DC Arc Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . 40
		5.13 Schematic diagram for AF testing with AF after MPPT module. . . . . . . . A.8 V-I AF ignition curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
		1.3	6.26 Multiple AF scenario with a 47Ω load. . . . . . . . . . . . . . . . . . . . . . PV Converters and Electric DC Arc Detector . . . . . . . . . . . . . . . . . 42
		5.14 Experimental results of arcing after MPPT module. . . . . . . . . . . . . . . 6.27 Test 1 with RL of 22Ω and 5mH load. . . . . . . . . . . . . . . . . . . . . . B.1 Design of isolated double buck converter. . . . . . . . . . . . . . . . . . . . . 4.2.1 Simulation Components Values. . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
		6.1 B.2 Developed double DC/DC buck converter. . . . . . . . . . . . . . . . . . . . THD study of multilevel waveform. . . . . . . . . . . . . . . . . . . . . . . . 6.28 Test 2 with RL of 22Ω and 5mH load. . . . . . . . . . . . . . . . . . . . . . 4.2.2 Component Values and Settings. . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Justication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
		6.2 B.3 Design of isolated double boost converter. . . . . . . . . . . . . . . . . . . . THD decomposition in T HD even and T HD odd before and after an AF. . . . 6.29 Test 3 with RL of 22Ω and 31mH load. . . . . . . . . . . . . . . . . . . . . . 5.3.1 Test Bench Equipment and Values. . . . . . . . . . . . . . . . . . . . . . . . 1.6 Chapters Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44	100
		6.3 B.5 Developed double DC/DC boost converter (left) and full H bridge (Right). . AF Testing protocol for dierent loads, with highlighted measuring points. . 6.30 Test 4 with RL of 22Ω and 31mH load. . . . . . . . . . . . . . . . . . . . . . 5.5.1 Experimental Values for MPPT Test. . . . . . . . . . . . . . . . . . . . . . .	106
		6.4 B.4 PCB Design of the full bridge for the DC/AC stage. . . . . . . . . . . . . . . V Bridge2 harmonics decomposition. . . . . . . . . . . . . . . . . . . . . . . 6.31 Test 5 with RL of 22Ω and 51mH load. . . . . . . . . . . . . . . . . . . . . . 6.7.1 AF Algorithm testing with dierent loads. . . . . . . . . . . . . . . . . . . .	140
		6.5 C.1 Fourier representation of a square waveform as the sum of a series of sinusoidal I out THD Decomposition technique. . . . . . . . . . . . . . . . . . . . . . . . 6.32 Test 6 with RL of 22Ω and 51mH load. . . . . . . . . . . . . . . . . . . . . .
		6.6	V Bridge2 harmonics decomposition. . . . . . . . . . . . . . . . . . . . . . . waves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33 Test 1 algorithm results, 1200 W vacuum load. . . . . . . . . . . . . . . . . . C.1.1Waveform Symmetry Characteristics. . . . . . . . . . . . . . . . . . . . . . .	193
		6.7	Iout Harmonic Decomposition. . . . . . . . . . . . . . . . . . . . . . . . . . 6.34 Test 2 algorithm results, 1200 W vacuum load. . . . . . . . . . . . . . . . . .
		6.8	V H2 harmonics decomposition. . . . . . . . . . . . . . . . . . . . . . . . . . 6.35 Test 3 for Vacuum cleaner of 1200W. . . . . . . . . . . . . . . . . . . . . . .
		6.9	6.36 AF test side by side with a resistive switched load and its eect in the THD
			content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
					xxxi

signals obtained using DC/DC Buck variant. . . . 4.10 Voltage and current waveforms of the nine-levels AC output, using buck variant xxviii List of Figures 46.11 Iout THD analysis for vacuum load. . . . . . . . . . . . . . . . . . . . . . .

TABLE 1

 1

				.1.1. Single Sourced Converters Comparison
	Publications	Year	No.	No.	No.	No.	No.	No.	Elevation	Continous
			Levels Transformer IGBTs Capacitors Indutors Diodes	Factor	Current
	[2]	2017	5	0	8	1	0	4	None	None
	[1]	2016	7	0	10	3	0	0	None	cap&cell
	[3]	2015	9	0	12	2	2	4	None	None
	[4]	2014	9	0	11	3	1	4	None	None
	[13]	2014	7	0	10	4	1	0	None	None
	[6]	2014	7	1	8	3	2	5	2:1	None
	[9]	2013	5	0	8	1	0	0	None	None(absorb)
	[10]	2012	5	0	8	2	0	0	None	cap&cell
	[7]	2011	7	0	7	4	10	10	2:1	None
	[8]	2011	7	0	15	3	11	11	3:1	None
	[11]	2009	5	0	8	1	0	0	None	cap&cell
	[12]	2009	7	0	8	1	0	0	None	cap&cell
	[5]	2009	9	4	9	0	0	0	None	Yes

TABLE 2 .

 2

			5.1. PV Congurations.
	Conguration	Inverter	Modules	Strings Module:String

TABLE 3 .

 3 2.1. Boost Variant Switching States. States S 1 S 2

	iL 1	iL 2

  .2.2 where S 1 = 1 and S 2 = 1 is presented in Fig.3.8, considering that current i DC 1 ows from the power supply V DC , from collector-emitter of switch S 1 , followed by the inductor L 1 to the capacitor C 1 , closing the circuit to ground by D 1 GN D and the extra switch S 2 . It is noted that for this current mesh, the diode D 1 is not polarized. Figure 3.8. Proposed topology buck variant in switching state S 1 =1, S 2 =0 with highlighted currents paths.

	3.2. Development of the DC/DC Stage				79
			Buck1 Converter
		i DC(Continuous)	S 1	L 1	i Cell1
			D 1	C 1	V C1	Cell 1
		S 2 D 1Gnd
	Renewable Energy Source	V DC	S 3	L 2	i Cell2
				C 2
			D 2		V C2	Cell 2
		S 4 D 2Gnd
			Buck2 Converter		DC/AC Stage
			DC/DC Stage		Cascade Cells Multilevel Inverter
		Single Source Double Isolated Output, Buck Converter

Parallel to this process the buck 2 converter is in state i L2 of f , this current is only dependent of voltage V C1 , described in equation (3.15) and when the S 1 is in logical state 1, the current through the inductor L 1 results in an energy storage expressed in equation

(3.14)

.

TABLE 3 .

 3

		2.2. Buck Variant Switching States.
	States S 1 S 2	iL 1	iL 2

  Duty 1 > Carry 1 Figure 3.9. Proposed topology buck variant in switching state S 1 =0, S 2 =1 with highlighted currents paths.

	80		Chapter 3. Inverter Proposal for PV Applications
				Buck1 Converter
		i DC(Continuous)	S 1	L 1		i Cell1
				D 1	C 1	V C1	Cell 1
		S 2 D 1Gnd
	Renewable Energy Source	V DC	S 3	L 2		i Cell2
					C 2
			D 2		V C2	Cell 2
		S 4 D 2Gnd
				Buck2 Converter		DC/AC Stage
				DC/DC Stage		Cascade Cells Multilevel Inverter
		Single Source Double Isolated Output, Buck Converter
						(3.12)
				0 when Duty 1 < Carry 1
			
		m 2 =	 	1 when Duty 2 > Carry 2	(3.13)
			 	0 when Duty 2 < Carry 2

Table 3

 3 3 , followed by the inductor L 2 to the capacitor C 2 , closing the circuit to ground by D 2 GN D and the extra switch S 4 . It is noted that for this current mesh, the diode D 2 is not polarized. .2.2 the conduction state of the diodes in each switching combination is also presented. Although in any moment that the switch buck 1 or buck 2 holds a logical state 0, the complementary buck output voltage will depend for a short period on the capacitor out results from the combination of possible states between Cell 1 and Cell 2 . Both cells can adopt three states +V C 1 , 0, -V C 1 for Cell 1 and +V C 2 , 0, -V C 2 for

	3.3. Multilevel DC/AC Stage

Parallel to this process the buck 1 converter is in state i L1 of f , this current is only dependent

of voltage V C 2 .

As mentioned multilevel inverters are the tendency in the development of power electronics, and cascade cells topology contributes with the best features without compromising number of components and performance in the DC/AC conversion, in this selection the DC/AC stage of the PV inverter is presented.

3.3.1 DC/AC Proposal Operational Principle

The DC voltage, produced by the PV panel is conditioned with the modied double buck topology presented in this research, afterwards both DC levels are used to feed an asymmetrical cascade cell multilevel topology in order to perform the conversion into AC. Cell 2 . Taking into account the asymmetrical values of V C 1 and V C 2 nine combinations between the two cells are possible, which are presented in Table 3.3.1, also the required logic value for switches in Cell 1 and Cell 2 are presented.

TABLE 3 .

 3 3.1. Stepping Logic for a Nine-Level Converter.

	Cell 1	Cell 2

Combinational S 1 , S 2 , S 3 , S 4 S 1 , S 2 , S 3 , S 4

Levels

TABLE 4 .

 4 2.1. Simulation Components Values.

TABLE 4 .

 4 2.2. Component Values and Settings.

	Components	Simulation
	Frequency	2000 Hz
	m1	66%
	m2	50%
	L1	4mH
	C1	20, 200µF
	L2	4mH
	C2	20, 200µF
	RLoad

TABLE 5 .

 5 3.1. Test Bench Equipment and Values.

	Componet	V alue -Image
	T emperature	20C •
	Electrodes M aterial

TABLE 5 .

 5 5.1. Experimental Values for MPPT Test.

112

  Chapter 6. Study of Harmonics Decomposition Technique in Both PV Isolated and Interconnected Systems Using Experimental Signals This frequency analysis will be applied specically to signals V H2 and I out , the points of measure are detailed further into this section in Fig. 6.3. The developed test bench, is prepared according to the values in table 5.5.1. The experiments for stand alone systems are performed in normal conditions and on presence of AF considering each type of load.

	The current and voltage signals are extracted from the experimental test bench by sampling
	at 1M samples/sec. The harmonic analysis of experimental signals are made using Matlab
	code.

  4, 6.5 and 6.6 are used to analyze the AC voltage (since this signal is less aected by the feed load) response of the PV converter under DC AF conditions. The theoretic basis for this is presented in appendix. Chapter 6. Study of Harmonics Decomposition Technique in Both PV Isolated and Interconnected Systems Using Experimental Signals

  6.11.

		Chapter 6. Study of Harmonics Decomposition Technique in Both PV Isolated and
	124	Interconnected Systems Using Experimental Signals
	6.4.5 Stand alone test conclusion

11 :

 11 Chapter 6. Study of Harmonics Decomposition Technique in Both PV Isolated and Interconnected Systems Using Experimental Signals

	C f = 0.05C b	(6.11)

  .7.1. The table includes the main characteristics of the experiment such as, type of load employed followed by the number of AF tests. A total of 55 tests are performed in this section.

TABLE 6 .

 6 7.1. AF Algorithm testing with dierent loads. Inductive 5 each = 15 5mH, 30mH, 58mH Resistive 22Ω Inductive 5 each = 15 5mH, 30mH, 58mH Resistive 22Ω + 1200W V acuum 5 F ast speed Resistive 22Ω + 1200W V acuum 5

	Loads &	V alue of Load
	N umber of AF tested
	Resistance 5	47Ω
	Resistance 5	22Ω
	Resistive 47Ω Slow speed
	LCL Couplin F ilter 5
	T otal 55

ms. (c) T sw = 25 ms. (d) T sw = 125 ms. time until the time window is too long for a fast detection. In this way, a range within which the Idif value shows a signicant change after arc happens can be obtained. Dierent T sw values among the range that has been used throughout the work of Xiu Yao are, T sw = 10 ms is used and T sw = 25 ms to feed the detection algorithm. It is important to note that the choice of proper T sw is unique as long as it is in the proper range. Frequency characteristics of the current before and during arcing are studied in this work through discrete wavelet

(a) THD analysis of V Bridge2.(b) T HD even analysis with zoom V Bridge2.

The main directions of improving the performance of power inverters are: low harmonics in the output current, elimination of the direct current in the output, control of the active and reactive power supplied by the inverter and a digital inverter control [START_REF] Nayar | A low cost power electronic interface for small scale wind generators in single phase distributed power generation system[END_REF]. The described converter conguration is not only used with photovoltaic panels but also with small wind turbines [START_REF] Nayar | An igbt inverter for interfacing small scale wind generators to single phase distributed power generation systems[END_REF], gas or water turbines and fuel cells for auxiliary power.

In the small single-phase inverters usually control of the reactive power output is not needed.

For this reason they operate with a unity power factor, which means that the current supplied to the grid is in phase with the grid voltage [8486]. This simplies the control and also makes the production cheaper. The detailed general schematic of a renewable energy-based generator connected to the grid through a single-phase inverter is shown on Fig. 6.13.

Since the main goal of this conguration is to transfer the produced energy to the grid, an additional factor to be considered in the analysis, is the coupling lter inuence in the system and how it aects the detection technique performance.

With the addition of this lter, the nine levels multilevel output generated by the DC/AC stage will be smoothed making it suitable for interconnection. In order to achieve this transfer the inverter current must have a phase angle of less than 90

• from the grid voltage. This can be accomplished when the inverter voltage phase is ahead from the grid voltage. In Fig. 6.14 is presented a simplied schematic of an H bridge inverter power unit. This inverter produces an approximative sinusoidal voltage waveform by a PWM control explained in Chapter 3.

The lter at the grid terminals employs a small inductance which also determines the rst harmonic of the current supplied to the grid. At low powers, the active resistance between the inverter and grid cannot be neglected. It is determined by the active resistance of the inductive coil the conductors and also by the resistances of the power bridge's transistors.

In this case the output grid current is determined by the impedance Ż between the inverter and the grid and by the dierence between the two voltages:

Chapter 6. Study of Harmonics Decomposition Technique in Both PV Isolated and Interconnected Systems Using Experimental Signals

Before the algorithm will trigger any AF ag, two conditions have to be meet. First the magnitude value of T HDe in V H2 is studied to detect any surpass of the experimental normal operation limit (V H2 T HDe Lim ), if this happens a counter is started to store how many peaks have surpass this threshold value (S1) in one cycle. With these informations the comparison of number of peaks S1 (hence V H2 T HDe Lim surpassed) against the predened normal operation peaks quantity value is performed (V H2 T HDe P eaks ). Since the length of the analysis window in one single period of the 60 Hz signal, this is translated into T = 1/60 = 4166 sampling point, that can be expressed as 6.14 for Iin but also applicable to V H2.

The second condition (S2) to be meet is that the T HDe in I in also surpass the predened value of normal operation (I in T HDe Lim ). If one of this conditions is not meet the algorithm will jump to analyze the next period of the signals (W indow + +) until it nd a AF.

If both conditions are true, the data of the period (4166 samples) will be stored in variables:

(M -V H2Con(N )) that corresponds to the number of peaks in a period. So the comparison consists in checking if cycle N has more peaks than cycle N-1. M Iin(N ) satises equation 6.14 which corresponds to the number of samples above the limit (I in T HDe Lim ). The decision stage performs a comparison sample by sample of the T HDe data stored within the precedent

in order to determine the presence of an AF.

M Iin(N ) =

j=1

Iin j > Iin T HDe Lim (6.14)

Stand Alone Isolated PV System Study

In this section are presented the nal results obtained using the upgraded algorithm using Iin, in both a stand alone and an interconnected system. This results are obtained thanks to the numerous experimental signals generated in the test bench of Fig. In an stand alone conguration the converter will perform the energy transformation in order to feed the dierent loads, hence the detection algorithm has to be capable of achieving detection when complex loads are presented in the system.

In addition to this challenge the algorithm as to be capable of dierentiate an AF from change in radiation of the PV panels and sudden switching of loads. For this reason the proposed approach rely in the processed signals of V H2 and I in to display the AF ag.

As can be seen in Fig. 6.23 two dierent AF signatures are presented in order to validate the detection capabilities of the algorithm. In (a) the AF voltage is stable across the time, which generated the strongest uctuation of distortion at the beginning of fault. Contrary in (b) the separation between electrodes wasn't constant during the fault which generates strong perturbations in the analyzed signals. This phenomena probe to be a useful factor for detection as can be seen across the dierent experimentations performed. This ag helps with the interpretation of results.

Achievements of this Work

The principal achievements of this thesis are listed below:

Identication of the main components needed for the conceptualization of the PV inverter.

Modeling of the novel DC/DC and DC/AC converters in Simulink.

Modeling of the whole inverter topology on Simulink.

Design and fabrication of the prototype boards required for the implementation of the developed DC/DC "boost" variant converter.

Design and fabrication of the prototype boards required for the implementation of the developed DC/DC "buck" variant converter.

Design and fabrication of the prototype boards required to implement the asymmetrical cascade cell multilevel inverter.

Research and acquisition of the needed laboratory equipment (new loads, supply sources, PV panels, articial illumination system, dierential voltage proves, MPPT tracking board, etc.) to successfully test the system.

Development of the AF generation system according to standard UL1699B.

Experimental test bench setup and calibration.

Integration of a Simulink method for the use of experimental AF signatures into simulation.

Conception of a novel approach for arc fault detection, based on the harmonic index.

Matlab coding of the proposed algorithm.

Future Research Works 159

Construction of an experimental signal data base of approximately 350 cases.

Future Research Works

The algorithm is intended to be programmed in a digital signal processor (DSP). The strategy to follow in order to implement the designed algorithm into the DSP, is to adapt the M atlab code so that signals can be sampled with a window small enough in order to fulll the UL 1699B recommended detection time of 1-3 second.

This can be accomplished by employing the DSP toolbox (Matlab), that will allow to read the analog signals of V H2 and Iout in real time and then perform the signal processing to obtain the values needed for both signals. Since the control for both DC/DC and DC/AC stages of the proposed inverter can be accomplished using simulink into the DSP, the detection subroutine can be added to the programming cycle to be downloaded at the same time with the control. This implementation is key factor to achieve the real time detection.

In this research was possible to combine two scientic elds in order to solve rising electrical needs in the renewable energy eld. Thanks to this some work remain to be done, the principal ones are enlisted below:

1. The detection algorithm based in the technique presented in this thesis will be implemented in a DSP.

2. The evaluation of the inverter employing a seven-levels single bridge multilevel DC/AC inverter, remains to be studied and also the capacities of AF detection may be improved with the use of this topology.

3. The implementation of the proposed detection approach into a DSP or a FPGA to evaluate in the test bench the real AF scenario response time. Various commercial security measures exist to limit the appearance of this fault, although solutions vary from country to country, nonetheless between the solutions that have gain popularity are:

Ground Interruption Fuse: This measure let's drain the current of a fault to the ground and at the same time isolates the PV installation to protect it. There exist some regulations for the sizing of this fuse like the normative UL 1741 published in 2002 [START_REF] Markvart | Standard for at plate photovoltaic modules and panels[END_REF].

Current leakage monitoring: This method consist of performing a constant current sending, the current that is generated by the PV system is compared to the quantity that is delivered to the load, if exist a dierence bigger than a pre-dened window this means that a fault is consuming the rest of the current in some point of the system, and a safety shutdown is performed [START_REF] Flicker | Photovoltaic ground fault and blind spot electrical simulations[END_REF].

Resistance drop Window: This method of detection consists of monitoring the resistance in the ground path, in case of a fault, the resistance will vary its value and if it surpasses a dened limit this means that a fault in the system is present.

A.2 Line to Line Faults

This type of fault is the result of a low impedance current path between two CCCâs which often ends in the melting of the conductors due to an excess in the operational current they are designed to work. The magnitude of the current that ows between this two point will be proportional to the number of PV connected in parallel. The maximum current that can ow through the faulty string of a PV array with n number of strings connected in parallel A.3. PV Arc Faults 177 is (n-1) x (short-circuit current of each string).

The line to line faults and the line to ground faults share similar causes, this is due that they have similar behavior, thanks to this fact is possible to prevent them by employing strategies like overcurrent protection devices. if the presence of a ammable substance or material is close to the PV. [START_REF] Bower | Electrical and thermal nite element modeling of arc faults in photovoltaic bypass diodes[END_REF]96100].

A.3 PV Arc Faults

Unlike AC systems, current through the DC arc does not possess a periodic zero crossing, and therefore, it is much more likely that an arc in a PV system will result in a long sustained arc compared with an AC generation system [START_REF] Johnson | Dierentiating series and parallel photovoltaic arc-faults[END_REF], [START_REF] Johnson | Photovoltaic dc arc fault detector testing at sandia national laboratories[END_REF]. The impact of this fault is presented in This faults are known to have a particular type of behavior as declare [START_REF] Bower | Electrical and thermal nite element modeling of arc faults in photovoltaic bypass diodes[END_REF], an AF have particular applications which will limit the exibility of solutions. In case of PV panels the scenario is not dierent, because each arc faults case posses their own characteristics, each component in the system will play an important role in changing the behavior of the fault, this is the reason why a deeper analysis and modeling of a PV arrangement needs to be accomplished in order to have accurate AFDD. The rst standard for AF detection has appeared more than a decade ago as the normative UL 1699, and soon after a second and more detailed revision of it came out and has become the today standard for research and development of AFDD. During the last years with the exponential grown of renewable energy the development of protections in order to have a safe and optimal operation in PV systems has propelled the research of innovative and more ecient AF detection systems.

A.4 Historic Back Ground

The arc theory date back from the early 19th century, were many scientists like A. Ayrton, during dierent periods of time contribute to the development of the mathematical fundaments for the study of arcs in both AC and DC scenarios.

Ayrton equation Ayrton formulated the rst known equation used to model the electrical properties of a steady-state arc [START_REF] Ayrton | The electric arc[END_REF]. Developed in 1902, was derived for arcs in air initiated between carbon electrodes separated by a few millimeters.

V

The constants A and B are dependent on the arc length and the electrode material. The arc current is raised to a power n , where n varies as a function of the electrode material.

For arc lengths ranging from 1.0 to 10.0 mm (0.0394 to 0.394 in), the equation for copper electrodes is specied in the next equation. Also, note that the exponent n is dierent from the previous two equations. All of the models presented and developed this early years studies share in common the following characteristics:

-Arc resistance is nonlinear.

-Arc resistance is dependent on multiple factors: a) gap length, b) electrode material, c) arc-current magnitude, d) electrode conguration.

The models proposed by the precedent authors have been based on tests conducted over more than a century by dierent researchers across dierent countries and under very dierent protocols. However despite the wide range of testing methods and conditions, the results are remarkably similar.

At low current levels, the VI characteristic is inversely proportional and nonlinear. At high arcing-current levels, the analysis shows that the arc-resistance voltage-drop approaches a constant value.

In an eort to quantify the risks associated with high-current DC systems.

Arcing behavior is highly variable, and the existing DC arc models cannot be accurately and reliably assess all the characteristics of dc arcs. Additional arc testing is needed to develop more accurate VI characteristics and better DC arc resistance models. Extensive testing in a controlled environment is needed to study the incident-energy levels associated with DC arcing faults. A hazard risk assessment is needed to identify where DC arcing faults might be initiated in industrial power systems.

B.1 Smart Inverter PCB Conception

In this chapter will be presented with details, the construction and developments of the experimental boards that allow to obtain the results presented throughout this chapter, for both variants of the smart inverter. With the designed PCB's, all the components needed to test the implementation of the smart Inverter are present, and the results will be described in the next section.

Appendix C C.1 Fourier Series

Orthogonal series expansions play a key role in solving a wide range of problems encountered in physics and engineering. Fourier, Hartley, Walsh, etc., have used to approximately non linear characteristics with good results. They can also be used to solve dierential equations, resorting only to algebraic means. Because of their very interesting characteristics an high eciency as integration solvers, they have been researched widely in the elds of system identication, model reduction and control.

A basic understanding of the theory behind orthogonal series expansions is essential for learning the concepts of harmonic domain modeling. In this section the most relevant aspects of Fourier series are reviewed [START_REF] Acha | Power systems harmonics computer modeling and analysis[END_REF].

C.1.1 Periodic Functions

A periodic function f (t) with frequency f 0 and period T 0 seconds is dened as

where T 0 = 1/f 0 . The sine and cosine functions are examples of periodic functions.

C.1.2 Even and odd Functions

A Periodic function f (t) is said to be even if the following relation holds true:

and it's said to be an odd function if

An arbitrary function f (t) can be represented as

Given the nature of function with a half wave symmetry, the harmonic content of this signal will contain only even harmonics. This feature is used to develop the detection technique detailed in the next sections.

Quarter-wave Symmetry

If a periodic function f (t) has half-wave symmetry and is an even function, then f (t) is said to have even quarter symmetry.

If a periodic function f (t) has half-wave symmetry and is an odd function,then f (t) is said to have odd quarter-wave symmetry. In electric circuit theory, the coecient A 0 is referred to as the DC component, A n and θ n are the magnitude and angle of the n harmonic component.

C.1.3 Trigonometrical Fourier Series