Peng Zhang

Emmanuel Jacques

Régis Rogel

Laurent Pichon

Elucidation of the Density of States for Polycrystalline Silicon Vertical Thin-Film Transistors

Keywords: Access resistance, density of states (DOS), intrinsic mobility, polycrystalline silicon, threshold voltage, vertical thin-film transistors (TFTs)

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio I ON /I OFF of more than 10 6 and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method.

I. INTRODUCTION

P OLYCRYSTALLINE silicon thin-film transistors (TFTs) have been widely adopted in industry fields for driving different types of displays, such as in E-ink electrophoretic displays (EPDs) [START_REF] Inoue | Highresolution microencapsulated electrophoretic display (EPD) driven by poly-Si TFTs with four-level grayscale[END_REF], active-matrix liquid crystal displays (AMLCDs) [START_REF] Inoue | Surface-free technology by laser annealing (SUFTLA) and its application to poly-Si TFT-LCDs on plastic film with integrated drivers[END_REF], and active-matrix organic light-emitting diodes displays (AMOLEDs) [START_REF] Park | A poly-Si AMOLED display with high uniformity[END_REF], and also own potential applications in radio frequency identification (RFID) tags [START_REF] Yu | An LTPS TFT demodulator for RFID tags embeddable on panel displays[END_REF], X-ray detectors [START_REF] Tai | LTPS active pixel circuit with threshold voltage compensation for X-ray imaging applications[END_REF], sensors [START_REF] Yan | Polycrystalline silicon ISFETs on glass substrate[END_REF], and so forth. The flexible and transparent display might be the development directions for future display domains, where organic small molecular Manuscript received March 2, 2022; accepted April 5, 2022. This work was supported in part by the Natural Science Foundation of Jiangsu Province under Grant BK20180762 and in part by NUPTSF under Grant NY219099. The review of this article was arranged by Editor T. Grasser. (Corresponding author: Peng Zhang.)

Peng Zhang is with the College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, China (e-mail: zp@njupt.edu.cn).

Emmanuel Jacques, Régis Rogel, Laurent Pichon, and Olivier Bonnaud are with the Département OASIS (Organic and Silicon Systems), Institut d'Electronique et des Technologies du numéRique, Université de Rennes 1, 35042 Rennes, France (e-mail: emmanuel.jacques@univ-rennes1.fr; regis.rogel@univ-rennes1.fr; laurent.pichon@univ-rennes1.fr; olivier.bonnaud@univ-rennes1.fr).

Color versions of one or more figures in this article are available at https://doi.org/10.1109/TED.2022.3167938.

Digital Object Identifier 10.1109/TED.2022.3167938

and polymer TFTs own the advantage of flexibility and IGZO TFTs own the advantage of transparency. However, for the mainstream displays, the polycrystalline silicon TFTs show certain advantages over organic TFTs and IGZO TFTs, such as high ambient stability and bias stress stability, as well as high field-effect mobility and mature industrial production line, which is required especially for high-resolution displays.

In addition, for these display applications, one objective focuses on the improvement of the driving current with reduced power consumption. The main approach of obtaining larger driving current lies in the improvement of fieldeffect mobility by well controlling the polycrystalline silicon morphology, such as adopting excimer laser annealing (ELA) [START_REF] Hara | High-performance polycrystalline silicon thin film transistors on non-alkali glass produced using continuous wave laser lateral crystallization[END_REF] of the predeposited amorphous Si layer, or by other methods such as using metal-induced lateral crystallization (MILC) method [START_REF] Yoon | A high-performance polycrystalline silicon thinfilm transistor using metal-induced crystallization with Ni solution[END_REF]; however, the two crystallization methods own disadvantages. In previous work, solid-phase crystallization (SPC) method has been adopted in our group with a processing temperature of 600 • C that supports the processing on specific glass substrates, such as on Corning 1737 glass substrates, while the field-effect mobility exceeds 100 cm 2 /V • s with a current ratio exceeding 10 7 , indicating high-quality polycrystalline silicon active layer [START_REF] Pichon | Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization[END_REF]. From another aspect, the driving current can also be amplified with higher channel width/length ratio, and considering the high aperture ratio requirement for higher luminance, short-channel length is preferred. From our previous work, 3-D vertical TFTs based on SPC polycrystalline silicon active layers have been proposed, with the aim of improving current ratio by introducing an insulating barrier layer between source and drain, and thus suppress the large source-drain overlapping area [START_REF] Zhang | Quasivertical multi-tooth thin film transistors based on low-temperature technology (T≤600 • C)[END_REF], [START_REF] Zhang | P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology[END_REF]. In addition, the vertical configuration also enables high flexibility since the channel direction is perpendicular to the substrate surface. However, from previous work, even adopting the polycrystalline silicon active layer crystallized by SPC, the field-effect mobility of the vertical TFT is approximately one order lower than their lateral counterpart, which is supposed to be due to the etched rough sidewall and the small grain size of the polycrystalline silicon film grown vertically on the rough sidewall, where the growth kinetics may be different from the lateral growth [START_REF] Zhang | P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology[END_REF]. In addition, further enhancement of current ratio is preferred for realizing high-resolution displays.

In this article, optimized vertical TFTs are proposed by involving an insulating layer between source and drain, and the electrical characteristics are simply analyzed. Elucidation of the low field-effect mobility is also proposed based on the density of states (DOS) analysis. In order to verify this special DOS method, a different method adopting threshold voltage calculation is proposed, verifying the accuracy of the DOS expression. In addition, polycrystalline silicon lateral TFT was also introduced to further verify the accuracy of this evaluation method.

II. DEVICE FABRICATION

The fabrication of the polycrystalline silicon vertical TFTs was carried out as follows. Monocrystalline silicon wafers were initially employed as the substrates to guarantee the endurance of high processing temperature of 600 • C. The substrates were cleaned by a standard RCA cleaning step, following by a deposition step of a thick SiO 2 layer by atmospheric pressure chemical vapor deposition (APCVD) step at 420 • C, in order to prevent the penetration of the impurities from the substrates. Thereafter, four layers were deposited in sequence, which are an n-type heavily doped polycrystalline silicon layer, a 200-nm Si 3 N 4 layer, a 1-μm undoped polycrystalline silicon layer, and finally another n-type heavily doped polycrystalline silicon layer, and all depositions were carried out by lowpressure chemical vapor deposition (LPCVD) method. The combined barrier layers of the 1-μm undoped polycrystalline silicon layer and the 200-nm Si 3 N 4 layer are used between heavily doped polycrystalline silicon layers to facilitate better etching profile as well as to guarantee a sufficient channel length, in order to avoid serious short-channel effects.

Prior to the patterning step, the adjustments of the etching parameters were carried out, and due to the etching selectivity between Si 3 N 4 and polycrystalline silicon, the reactive ion etching (RIE) procedure adopts a high power of 50 W, a gas flow of 10 sccm, and a low pressure of 1 mTorr, in order that the physical bombard dominates over the chemical erosion in the RIE process. This enables to form continuous steep sidewalls, as shown in Fig. 1(a), even with certain relief at the Si 3 N 4 layer. Fig. 1(b) shows the fabrication procedure of the five-mask process. The first etching step aims to form sidewalls, and then, a second partial etching until reaching the bottom polycrystalline silicon layer was carried out with the aid of a laser interferometer, in order to discriminate source and drain. After that, the undoped polycrystalline silicon active layer was deposited by LPCVD with different thicknesses of 150 and 300 nm and then patterned by a third mask. Afterward, a second RCA cleaning step should be carried out prior to the deposition of gate oxide layer, in order to eliminate most defects at the active layer/gate oxide layer interface. After that, a 70-nm-thick-gate oxide layer is deposited by APCVD, with the fourth mask employed to form source and drain contact holes. Finally, a thick aluminum layer was deposited by thermal evaporation and patterned by the fifth mask and a wet etching step is carried out. Fig. 1(c) shows the 3-D configuration of the two-tooth vertical TFT, and there are four parallel channels at the sidewalls. Fig. 1(d) shows a fourtooth device configuration, where there are eight sidewalls (channels), and source and drain are well discriminated. All the electrical characterizations were carried out by an Agilent B1500 semiconductor parameters analyzer.

III. RESULTS AND DISCUSSION

The transfer characteristics for the vertical TFTs with different active layer thicknesses of 150 and 300 nm are shown in Fig. 2(a), with a low drain-source voltage of 10 mV, in order to suppress the short-channel effects and reduce power consumption. For the device with higher active layer thickness, the ON-current is approximately 6.7 × 10 -6 A, and the OFF-current is approximately 3.8 × 10 -11 A, leading to a current ratio of 6.7 × 10 -6 A/3.8 × 10 -11 A in the order of 10 5 . In contrast, when reducing the active layer thickness to 150 nm, the ON-current increases to approximately 9.7 × 10 -6 A, while the OFF-current reduces to 4.5×10 -12 A, leading to a current ratio in the order of 10 6 . The increase of the OFF-current for higher active layer thickness is mainly due to the reduced resistivity of the polycrystalline silicon layer that the larger active layer thickness enables more leakage paths at the flat-band condition (i.e., for the V GS value that approximately corresponds to the lowest current) [START_REF] Sehil | Effect of the active layer thickness on the leakage current in p + p p + accumulation polycrystalline silicon TFTs[END_REF]. In contrast, for the device with low active layer thickness, the higher ON-current is obtained. When the V gs value is smaller than -10 V, the device with a 150-nm active layer shows larger leakage current, which may be due to the thermal (field) emission through the grain boundaries, or with Poole-Frenkel effect [START_REF] Wu | A compact model for polysilicon TFTs leakage current including the Poole-Frenkel effect[END_REF]. Therefore, higher crystalline quality can be indicated in the device with 150-nm active layer, which increases the leakage current at V gs less than -10 V. In order to demonstrate the effect of the access resistance, a simple extraction method is adopted

R total = V ds I ds = R acc + L WC ox μ FE 1 V gs -V th (1)
where R acc is the access resistance, L/W is the channel length/width ratio of 1.2/80 μm, C ox is the gate capacitance per unit area, μ FE is the field-effect mobility, and V th is the threshold voltage. Prior to the extraction of access resistance, the electrical parameters of the vertical TFTs were obtained and listed in Table I. The access resistance is then calculated, as shown in Fig. 2(b). The channel resistance of the 300-nm active layer is higher than its 150-nm active layer counterpart.

For the device with 150-nm active layer, the access resistance is about 500 , which is comparable to the channel resistance at the largest V gs ; however, the access resistance is still not dominant in the total resistance, especially at a lower V gs . Note that, this evaluation method is rather simple, and the accuracy of the access resistance needs to be further verified.

In order to prove the effect of the access resistance, the accurate threshold voltage that suppressed the access resistance is proposed by a secondary derivative method, and the accurate threshold voltage is shown as the peak of the secondary derivative curve [START_REF] Boudinet | Contact resistance and threshold voltage extraction in n-channel organic thin film transistors on plastic substrates[END_REF]. From the secondary derivative method, as shown in Fig. 2(c) and (d), the threshold voltages are shown to be 1.7 and 3.1 V, respectively, which is close to the values from the extrapolation method (-0.19 and 0.44 V). Note that, even for 300-nm active layer with smaller access resistance, the threshold voltage from the secondary derivative method shows a bit difference from the value from the extrapolation method. Therefore, the access resistance

TABLE I ELECTRICAL PARAMETERS DEDUCED FROM TRANSFER CHARACTERISTICS WITH A LOW DRAIN-SOURCE VOLTAGE OF 10 mV

effect can be negligible, especially at a lower V gs . Indeed, the higher field-effect mobility and the lower subthreshold slope indicate the lower bulk and interface trap densities for the device with 150-nm active layer thickness. Therefore, the access resistance does not play an important role in the total resistance, indicating the appropriate usage of DOS to analyze the electrical performance.

The DOS calculation is based on Suzuki's theory [START_REF] Suzuki | Theoretical interpretations of the gap state density determined from the field effect and capacitance-voltage characteristics of amorphous semiconductors[END_REF], where the DOS can be calculated following the three formulas:

N DOS (E F + qψ s ) = ε si 2q 2 ∂ 2 ∂ 2 s d(x) dx x=0 2 (2) d(x) dx x=0 = - ε OX ε Si • V GS -V FB -ψ S d OX ( 3
)
dψ s = dG G 0 ε ox ε si d d ox V GS -V FB -ψ s exp qψ s kT - 1
. ( 4
)
Fig. 3 shows the calculated DOS for the vertical TFTs with different active layer thicknesses of 150 and 300 nm, respectively. The channel thickness is fixed at 10 nm [START_REF] Fossum | Effects of grain boundaries on the channel conductance of SOl MOSFET's[END_REF]. From the DOS calculation, the tail states are demonstrated, a maximum DOS of approximately 10 23 eV -1 • cm -3 is obtained for both vertical TFTs. In addition, the closer of the Fermi level to the conduction band due to the band bending indicates higher field-effect mobility of the vertical TFT with 150-nm active layer thickness, being due to that more carriers were closer to the mobility edge that separates the localized states and the delocalized states, which indicates the better crystalline quality of the channel for the 150-nm active layer. In addition, the interface trap density should also be low considering a lower subthreshold slope, for the vertical TFT with 150-nm active layer thickness.

From the typical model, the unit-area DOS can also be expressed as [START_REF] Kandpal | On the threshold voltage and performance of ZnO-based thin-film transistors with a ZrO 2 gate dielectric[END_REF]

DOS = N t k B T 0 exp E -E C k B T 0 . ( 5
)
It demonstrates the unit-area density of tail states that follows the exponential relationship with the energy level, which can be related to the bulk DOS by dividing by the channel thickness. N t is the trap density per unit area and T 0 is the characteristic temperature. Therefore, for the device with an active layer thickness of 150 nm, the relationships can be deduced from fitting the DOS of 150-nm device in Fig. 3 with (5) as

k B T 0 = 0.0254 (6)
log 10 N t -17.07 × (E c -E F ) = 6.27. (7)
In contrast, for the device with a higher active layer thickness of 300 nm, the relationships can also be shown by fitting the DOS of 300 nm device in Fig. 3 as

k B T 0 = 0.0344 (8) log 10 N t -12.6(E C -E F ) = 8.96. (9)
On the other hand, the E C -E F value can also be deduced for the threshold voltage V th shown as follows [START_REF] Kandpal | On the threshold voltage and performance of ZnO-based thin-film transistors with a ZrO 2 gate dielectric[END_REF]:

V th -V FB = ϕ = - qt acc N t 2πε ox × exp - E C -E F k B T 0 -exp - E g /2 -qφ b k B T 0 × ln 2t ox + t acc /2 t acc /2 ( 10
)
where t acc is the accumulation layer thickness with a value of approximately 10 nm for polycrystalline silicon TFT [START_REF] Fossum | Effects of grain boundaries on the channel conductance of SOl MOSFET's[END_REF], t ox is the gate oxide thickness with a value of 70 nm, ε ox is the gate oxide dielectric constant, which is 3.46 × 10 -13 F/cm, and V FB is the flat-band voltage. For polysilicon, the bandgap E g is approximately 1.12 eV. Therefore, the only unsolved parameter is the grain boundary barrier height b at the flatband state, which can be solved as follows. In another reference paper [START_REF] Zhang | Indepth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors[END_REF], the grain boundary barrier height b can be elucidated as follows:

μ eff = μ 0 exp(-b /kT ) ( 11
)
where μ eff can be deduced from the I -V characteristics as follows:

I ds = W L C ox μ eff V gs -V t - 1 2 V ds V ds ( 12
)
where V t is the intrinsic threshold voltage of -1.15 V [START_REF] Kandpal | On the threshold voltage and performance of ZnO-based thin-film transistors with a ZrO 2 gate dielectric[END_REF].

For the intrinsic mobility of μ 0 , when without considering surface scattering and the grain boundary barrier modulation parameter, it can be deduced from the ln(μ eff )-(-1)/(V gs -V t ) relationship [START_REF] Zhang | Indepth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors[END_REF], as shown in Fig. 4(a). The deduced intrinsic mobility is 33.5 cm 2 /V • s for the device with the active layer thickness of 150 nm. In contrast, this value is 27.6 cm 2 /V • s for the device with the active layer thickness of 300 nm. Therefore, from [START_REF] Zhang | P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology[END_REF] and [START_REF] Sehil | Effect of the active layer thickness on the leakage current in p + p p + accumulation polycrystalline silicon TFTs[END_REF], the grain boundary barrier height can be deduced at the flat-band state. From Fig. 4(b), the grain boundary barrier heights versus the gate voltages were demonstrated. For the device with 150-nm active layer, the grain boundary barrier height is about 0.367 eV at the flat-band state, while for the device with thicker active layer, the corresponding value is about 0.30 eV at the flat-band state. Therefore, from [START_REF] Zhang | Quasivertical multi-tooth thin film transistors based on low-temperature technology (T≤600 • C)[END_REF], the relationship between N t and E C -E F can be deduced, which are

N t exp - E C -E F 0.0254 -5
.01 × 10 -4 = -1.53 × 10 13 ( 13)

N t exp - E C -E F 0.0344 -5.18 × 10 -4 = -1.86 × 10 13 (14)
for the device with thin or thick active layer, respectively.

Therefore, E C -E F is deduced to be 0.602 eV for the device with 150-nm active layer, while E C -E F equals 0.601 eV for the device with 300-nm active layer, and the nearly same E C -E F verifies the accuracy of this evaluation method and the high reproducibility of the fabrication process. As E F is at the middle of the bandgap, by recalculating ( 13) and ( 14) with the omitted exponential term (which is negligible), the nearly same E C -E F can also be obtained, indicating the accuracy of the calculation. Even though the polycrystalline silicon active layer shows the intrinsic semiconductor property, the calculation process can also be adopted for the polycrystalline silicon TFTs with doped active layer.

For the device with 150-nm active layer, the grain boundary trap density N t is approximately 3.04 × 10 16 cm -2 ; in contrast, this value is about 3.61 × 10 16 cm -2 for the device with 300-nm active layer. The concluded DOS can therefore be expressed as

DOS(eV -1 • cm -3 ) = 1.26 × 10 24 exp(39.4(E -E C )) (15) DOS(eV -1 • cm -3 ) = 1.05 × 10 24 exp(29.1(E -E C )). (16)
For the device with 150-or 300-nm active layer, the E -E c value is from -0.352 eV to approximately -0.137 eV by considering the E -E F values ranging from 0.25 eV (corresponding to the threshold voltage) to 0.465 eV for the device with 150 nm active layer and the E -E c value is from -0.397 eV to approximately -0.199 eV by considering the E -E F values ranging from 0.204 eV (corresponding to the threshold voltage) to 0.402 eV for the device with 300-nm active layer. Obviously, the DOS for the device with 150-nm active layer is much smaller than the device with 300-nm active layer for the same E -E F , and E is closer to the mobility edge for the device with 150-nm active layer, indicating better electrical characteristics for the device with 150-nm active layer.

In order to further verify the accuracy of this method, the polycrystalline silicon lateral TFT is also studied. For the lateral TFT, from Fig. 5(a), the flat-band voltage is -3.4 V, while the threshold voltage is 3.6 V. The gate oxide layer thickness is 100 nm, the channel width/length ratio is 40/20 μm, and the drain-source voltage is 1 V. From Fig. 5(a) and (b), the intrinsic mobility is 128 cm 2 /V • s, and the deduced grain boundary barrier height at flat-band state is about 0.387 eV. Therefore, from [START_REF] Zhang | Quasivertical multi-tooth thin film transistors based on low-temperature technology (T≤600 • C)[END_REF], the trap density can be calculated to be For lateral TFT, N t is one order of magnitude lower that the values of vertical TFTs, indicating the larger field-effect mobility and better crystalline quality of lateral TFT. Nevertheless, the large channel width/length ratio of vertical TFTs also supports the high current. Note that, even with a high N t , the polycrystalline silicon vertical TFTs show a current in the order of 10 -5 A at a low V ds of 10 mV, which is promising to drive diverse displays.

IV. CONCLUSION

Polycrystalline silicon vertical TFTs were fabricated with five-mask process and different active layer thicknesses of 150 and 300 nm. For the device with 150-nm active layer thickness, the higher ON/OFF current ratio of more than 10 6 is obtained, indicating better electrical characteristics with low DOS. The DOS is calculated, and by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, the DOS expression can be detailedly elucidated through the threshold voltage calculation. Polycrystalline silicon lateral TFT was also introduced to further verify the accuracy of this evaluation method.

Fig. 1 .

 1 Fig. 1. (a) SEM image of vertical sidewall incorporating Si 3 N 4 barrier layer, (b) five-mask fabrication process of the vertical TFT, (c) threedimensional configuration of a two-tooth vertical TFT, and (d) SEM image of a four-tooth vertical TFT, where eight channels were formed at the sidewalls.

Fig. 2 .

 2 Fig. 2. (a) Transfer characteristics of vertical TFTs based on different active layer thicknesses of 150 and 300 nm, (b) access resistance deductions for the two types of vertical TFTs, the access resistances can be negligible, (c) accurate threshold voltage of 1.7 V for 150-nm active layer thickness, and (d) accurate threshold voltage of 3.1 V for 300-nm active layer thickness.

Fig. 3 .

 3 Fig. 3. DOS calculation from the surface potential for the two types of vertical TFTs.

Fig. 4 .

 4 Fig. 4. (a) Deduced intrinsic mobility with ln(µ eff ) -( -1)/(V gs -V t ) relationship and (b) deduced grain boundary barrier relationship with gate bias, the grain boundary barrier height at the flat-band state can be obtained.

Fig. 5 .

 5 Fig. 5. (a) Transfer characteristics of the polycrystalline silicon lateral TFT, (b) grain boundary barrier height of the polycrystalline silicon lateral TFT, and (c) DOS for the polycrystalline silicon lateral TFT.

  N t exp -E c -E F k B T 0 exp -0.173 k B T 0 = -2.56 × 10 13 . (17)From the DOS calculation of Fig.5(c), it can be deduced thatk B T 0 = 0.0322 (18) log 10 N t -13.5(E c -E F ) = 7.23. (19)By calculation, N t = 5.51 × 10 15 cm -2 , and E c -E F equals 0.632 eV, which is close to the values of vertical TFT (0.601 or 0.602 eV). The nearly same E c -E F further indicates the accuracy of this method, and the DOS of lateral TFT can be expressed as DOS(eV -1 • cm -3 ) = 1.71 × 10 23 exp(31.1(E -E C )). (20)

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

ACKNOWLEDGMENT

The authors would like to thank all the members in the Department of Organic and Silicon Systems, Institut d'Electronique et des Technologies du numéRique, for their assistance in the processing and useful discussion, and special acknowledgment is given to Dr. J. Lelannic for providing SEM images.