S Silvant

Based on Discrete-Time Sliding Mode Control for Modular Multilevel Converter: Experimental Results". Submitted for IEEE Transactions on Industrial Electronics

Une thèse de doctorat est un long voyage, un long parcours, une longue et belle aventure qui nécessite un moral d'acier et un bon environnement humain et matériel. Je mets à profit cette partie pour exprimer mes plus sincères remerciements à tous ceux qui m'ont aidé à vaincre les difficultés rencontrées que sont les moments de doutes, les incertitudes et les divers blocages. Je salue chapeau bas toutes ces personnes qui ont contribué à réaliser mon rêve d'enfance : celui d'obtenir le grade de DOCTEUR. Je tiens tout d'abord à remercier Messieurs les professeurs Maurice FADEL et Mauro CARPITA pour l'intérêt qu'ils ont accordé à mon travail en ayant accepté de rapporter sur mon manuscrit. Je remercie également, avec la même gratitude, Madame la professeure Manuela SECHILARIU pour avoir accepté de présider mon jury de thèse et enfin Monsieur le professeur Kamal AL HADDAD pour m'avoir fait l'insigne honneur d'être de ce jury d'évaluation en tant qu'examinateur et ce, malgré des emplois du temps très chargés. C'est pour moi un honneur et une fierté d'avoir pu rassembler ses quatre éminentes personnalités au sein de mon jury de thèse. Je tiens à exprimer mes profonds remerciements à toi Seddik. Professeur BACHA, j'ai beaucoup apprécié le fait de travailler sous ta direction. Je n'oublierai jamais notre première rencontre dans ton bureau où l'on a beaucoup échangé sur mon projet professionnel. Ce jour-là constitue un tournant dans ma vie. Merci de la confiance que tu m'as accordé et d'avoir misé sur mes capacités pour réaliser cette thèse. Je ne te remercierai jamais assez pour ta disponibilité, ton accompagnement, tes conseils, sans oublier ton côté humain et paternel. Tu es une des personnes qui ont marqué ma vie, Milles merci à toi !! Ce travail n'aurait pas été assez complet sans la collaboration et l'expertise de mes deux superviseurs Abdelkrim BENCHAIB et David FREY. Abdelkrim, je te remercie pour ton support et les conseils que tu m'as donné durant toute cette aventure. Tu étais toujours là pour moi, notamment durant les moments les plus difficiles de la thèse et grâce à toi j'ai pu transformer cette thèse « scientifique » en une précieuse expérience professionnelle dans l'industrie en tant qu'Ingénieur/Chercheur. Je te remercie pour tous les échanges fructueux, qu'on avait eus, que ce soit dans le cadre du travail ou autour d'un café, sur les différents sujets de la vie. Tes futurs doctorants seront gâtés d'avoir un manageur exemplaire comme toi. David, j'étais très chanceux de t'avoir eu comme encadrant. Contrairement à Abdelkrim et Seddik, tu étais le seul à t'engager dans cette aventure sans avoir la moindre idée sur mon profil. Ce fait a constitué pour moi une motivation perpétuelle pour être à la hauteur de la confiance que tu m'as accordée dès le départ. Merci pour ton support et l'apport de ton expertise en électronique de puissance et à sa mise en oeuvre, c'est un vrai plaisir de travailler avec toi. Je ne manquerai pas non plus de remercier Sébastien SILVANT qui a rejoint l'équipe d'encadrement en cours de route. Merci pour le support que tu as apporté à ma thèse, tes remarques et tes orientations ont toujours été des motivations pour moi. Je n'oublie pas une mention spéciale à Eric COURBON pour ses compétences informatiques et sa totale disponibilité. Je souhaite remercier aussi chaleureusement le directeur du programme P1 de Supergrid Institute, Bruno LUSCAN, qui nous a fait confiance, qui était toujours au courant de nos progressions et qui nous a soutenu tout le long du déroulement de ce travail. Je n'oublierai pas non plus les deux autres responsables de sous programmes que sont Serge POULLAIN et Alberto BERTINATO pour leurs contributions d'une façon ou d'une autre à la bonne réussite de cette thèse. J'ajouterai ici un mot spécial à Luis COSTA, ancien responsable du sous-programme P1.4 et mon tuteur durant mon stage de fin d'étude. Merci pour la confiance et la patience dont tu as fait preuve durant le stage et surtout pour le sujet de thèse que tu m'as proposé. Saches bien que c'est une fierté pour moi d'avoir eu l'opportunité de travailler avec toi et j'espère que ce travail sera à la hauteur de tes attentes. Un mot aussi pour Xavier GUILLAUD qui m'a co-encadré lors du stage et qui m'a mis le pied à l'étrier dans le domaine des convertisseurs multi modulaires. Merci aussi pour m'avoir accueilli dans son laboratoire durant une semaine au début de la thèse. Mes remerciements vont aussi à la direction générale de SuperGrid Institute et à sa tête Hubert de la GRANDIERE pour m'avoir donné l'opportunité de travailler dans cet environnement unique de recherche et développement. Au tour de mes chers collègues du programme P1 que je remercie chaleureusement. Merci aux pionniers du P1 (Kosei, William, Deiynaba, Swann et Janailson) et félicitations pour vos nouveaux grades de DOCTEUR mérités. Une pensée aussi aux futurs docteurs (Amjad, Miguel, Juan-carlos, Guilherme, Raga et Nicolas), je vous souhaite le meilleur dans vos recherches ainsi que du courage et de la persévérance pour la rédaction de vos manuscrits de thèse. Je n'oublie pas Luc-André, Boussaad, Séllé, Manuel, Leo, Theihotua et tous les stagiaires, alternants et ingénieurs qui ont eu à travailler au P1. Merci à vous tous pour les remarques et les conseils que vous m'aviez apporté au cours des follow-ups. Merci pour la bonne ambiance créée dans les bureaux et les bons moments passés ensemble que soit autour des cafés avec des croissants le matin ou le soir à star-ferry pour un afterwork. Je tiens à remercier également tous mes amis qui m'ont aidé de près ou de loin à arriver jusqu'à ce stade: mes amis d'enfance (Yahia, Toufik, les deux Yakoub…), ceux de l'ENP Alger (Ayoub, Youcef, Mouhamed, Merouan, Arezki, Tarek…), mes amis en France (Amin, Djamel, Bilal, Chawki, Nassim…). Pour tous ceux que je n'ai pas pu citer ici (la section remerciement étant limitée et la liste est longue…), sachez que je n'oubliai jamais vos contributions. Je laisse maintenant un mot pour mon ami Zaki GUICHICHE, tu es le frère que la vie m'a donné. Merci pour les voyages qu'on a organisé, les restos qu'on a fait et tous les moments de partage que ce soit à Grenoble ou à Lyon. Je te demande une seul chose : comme tu le sais les aiguilles tournent, sois courageux et patient, tous ces moment difficiles vont être récompensés tôt au tard. Merci à tous les gens qui ont fait le déplacement à Grenoble, le jour de ma soutenance, pour y assister et m'apporter leurs soutiens.

Pour finir, rien de tout cela n'aurait été possible sans l'appui de mes parents. Je vous remercie pour tous les sacrifices humains et financiers que vous avez faits afin que je puisse arriver à ce stade. Je vous remercie pour votre soutien qui, malgré la distance, a toujours été là pour moi lorsque j'en avais le plus besoin.

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Abstract

Common understanding today is that the challenges to develop the SuperGrid are huge at many levels (e.g.: political, societal, economical, financial, scientific, technical…). It is also commonly accepted that the SuperGrid will require novel technologies (breakers, cables, converters…) and operating principles (e.g.: transition from a more passive essentially ACbased power system to a more active AC/DC-based one). This thesis deals with the development of a key actor for SuperGrid technology, that is, AC/DC converters.

Recently

Thesis context

Nowadays, energy systems are facing many requirements and challenges which need a paradigm-shift. Political and public willingness to increase energy independency, reduce greenhouse gas emissions and increase exchange capabilities require urgent actions in order to meet such ambitious targets. To do so, it is highly expected that the integration of large amount of renewable energy systems will play a crucial role for future power systems. In addition, in order to increase the robustness of the actual systems and create a large electric network, the interconnection of different countries and continents can be considered as a good solution. In order to achieve a good power distribution, we cannot rely only on Kirchhoff laws. The insertion of power electronic devices associated to new control concept and the increase of the submarine links capacities will enhance the management of the energy fluxes.

Main objectives and thesis methodology

The focus of this thesis covers the modeling and control of MMC, its main objectives are:

 Investigate the existing MMC model types (detailed, equivalent and averaged).

 Propose new implementation techniques including analytical equations for existing models to reduce computational time.

 Identify the effect of Balancing Control Algorithm (BCA) regarding MMC operation as well as its dimensioning criteria.

 Propose new advanced control algorithms for current loops when the cascaded control approach is used.

 Integrate the sampling period of hardware control in the control algorithm of current loops to go further in term of response time.

 Explore the possibility of accelerating the outer layer such as the energy loop.

Thesis outline

This thesis is organized as follows:

Chapter 1: This chapter introduces the HVDC grid technology and its principle.

Introduction

This chapter provides a brief introduction to HVDC transmission system followed by the chronological evolution of various AC/DC converter employed for such application. This permits to better understand the advantages carried with the Modular Multilevel Converter and the motivations behind the research works involving this topology. An overview of development trends regarding MMC topologies ends this chapter.

Needs for HVDC

Since the 19th century, the HVAC (High Voltage Alternating current) has been the dominant solution for transmitting electrical power over long distances; transferring power from generating stations to electrical substations. However, due to technological and stability constraints, the maximum transfer capability is limited. This is especially the case when the series and shunt compensations cannot be incorporated in the transmission system (e.g. submarine cables) [START_REF] Kalair | Comparative study of hvac and hvdc transmission systems[END_REF].

With technological innovations, notably in power electronics, HVDC technology has emerged as a promising solution for such application. Compared to the HVAC solution, the HVDC allows to overcome several constraints related to the old solution [START_REF] Ahmed | Hvdc supergrids with modular multilevel converters-the power transmission backbone of the future[END_REF][START_REF] Kharade | A review of hvdc converter topologies[END_REF][START_REF] Sechilariu | Supervision control for optimal energy cost management in dc microgrid: Design and simulation[END_REF]:

 Reduce the investment cost when the distance becomes higher than a specific one, socalled "break-even distance": around 600 km for overhead lines and 50 km for submarine ones.

 No distance limitation regarding stability matter.

 Integration of renewable energy located far from consumption (e.g. wind farm energy).

 Great power transfer capability per conductor.

 Power factor is always unity: line does not require reactive compensation.

 Reduce line losses: skin effect is absent in DC technology.

 Asynchronous interconnection can be achieved which is not possible using HVAC.

 Low short circuit current.

 Less radio interference with nearby communication lines.

 Ground return can be used in some cases.

High voltage direct current

Concept

The HVDC system allows to transmit power in DC form. This is achieved through power converters which are able to convert electrical energy from AC to DC or vice versa. The vast majority of HVDC transmission system consists of three basic parts:

1) Converter station in rectifier mode to convert the power for AC to DC form.

2) Transmission line, it can be achieved using overhead lines or cables.

3) Converter station in inverter mode to convert the power for DC to AC form.

The power direction can be inversed using the associated control of converter stations. When the two converters are located in the same stations, the HVDC link is often called "Back-to-Back" configuration, see It is the simplest possible configuration and allows to connect two independent neighboring systems with different and incompatible electrical parameters (voltage, frequency, short-circuit power level). It can be also used to stabilize weak AC links in some cases.

Configurations

Depending on the nature of projects and stations location, a number of different HVDC configurations can be employed [START_REF] Setreus | Introduction to hvdc technology for reliable electrical power systems[END_REF][START_REF] Flourentzou | Vsc-based hvdc power transmission systems: An overview[END_REF]. Independently from the converter technology (see section 4), a short description of these configurations is presented below with their associated advantages and drawbacks. In the following, a point-to-point scheme is used to illustrate their schematic diagram but all of which can be extended to a Multi-Terminal DC (MTDC) grid.

3.2.1.

Asymmetric monopolar scheme

The scheme of asymmetric monopolar is illustrated in Figure I-3, it includes two converter stations, single pole line (cable/line), and two grounded electrodes (one for each station). This configuration is the simplest and the advantageous one from a cost perspective. Another advantage is the possibility of expansion to a bipolar if necessary (to increase power rating).

However, in many cases, the fact that the current return flows through the ground requires permission and can raise environmental concerns. To overcome this issue, another scheme is proposed which includes in addition to the previous scheme a small metallic return (see

Symmetric monopolar scheme

A symmetric monopolar configuration is shown in Figure I-5. It can be considered as an alternative monopole scheme that avoid a continuous ground current. The earth reference can be provided by a high impedance reactor on the AC side and in some cases by capacitor's midpoint for the DC grid. Due to its symmetry, this is the only topology where the AC transformer is not subjected to DC voltage stresses, which simplifies its design. However, it has higher cost since it requires two fully insulated conductors. In addition, it extension to bipolar scheme requires lot of modifications. A major drawback concerns all monopolar HVDC configurations is the lack of power in case of DC faults. Since there is no redundancy stations, the transferred power can be missed for a

given period which vary depending to the used DC protection strategy.

Bipolar scheme

The bipolar configuration, shown in Figure I-6, can be seen as two monopolar configurations connected in parallel. Compared to the monopolar scheme, this configuration has higher cost since at least two stations at each terminal are needed and a transformer with two secondary windings or two different transformers groups (Yg-∆ and Yg-Y) are necessary to connect the two stations to AC grid [START_REF] Xue | On the bipolar mmc-hvdc topology suitable for bulk power overhead line transmission: configuration, control, and dc fault analysis[END_REF]. The main advantage of the bipolar configuration is its redundancy, one pole can be overloaded (if the dimensioning allows it) to compensate the lack of power when the other one is out of service for whatever reason (e.g. maintenance periods). In balanced operation, small/no current flows in the ground event without metallic return scheme. When the latter is employed (see

HVDC Cable/Line

HVDC

Converter technologies for HVDC application

After presenting the different schemes of HVDC transmission, it is necessary to review the converter topologies that have been or can be used for such application. There are basically two configuration types of power converters which are: Line-Commuted Converter (LCC) known also as Current Source Converters (CSC) and Self-Commuted Converter (SCC) known also as Voltage Source Converters (VSC). The principles of both technologies with their advantages and drawbacks are presented below.

Converters)

Although the first development of power electronics for HVDC technologies back in 1930's, its first commercial application did not occur until 1954 [START_REF] Peake | The history of high voltage direct current transmission[END_REF]. Based on mercury-arc valves, a Current Source Converters (CSC) have been employed to build the world's first commercial HVDC transmission: "The Gotland HVDC link". Through submarine cable over 98 km, the latter relates Gotland island to Sweden with a power rating of 20 MW and a voltage rating of 100 kV [START_REF] Abb | The early hvdc development: The key challenge in the hvdc technique[END_REF]. With the appearance of the thyristor semiconductor in 1950, new HVDC systems using only solid-state devices have been proposed. The first complete HVDC scheme based on thyristor valves was the Eel River scheme in Canada in 1972. This technology is known as Line-Commutated Converters (LCC) since the AC grid voltage to which the converter is connected drives its commutation process and the presence of the large inductor on the DC side keeps the DC current constant with a small ripple. Thanks to its advantages regarding power rating, reliability, and size, CSC technology based on thyristor valves has dominated the HVDC industry. It has now become standard equipment for DC converter stations and considered as mature technology for HVDC systems [START_REF] Rudervall | High voltage direct current (hvdc) transmission systems technology review paper[END_REF]. The LCC converter can be used for transmitting power in rectifier or inverter modes. This is possible by applying a firing angle 𝛼 on the valves less or greater than 90 degrees respectively.

Since the firing angle cannot be negative, the AC current is always delayed from the AC voltage. For this reason, the LCC is always consuming reactive power either in rectifier mode or in inverter one.

For HVDC application, each valve consists of multiple thyristors connected in series in order to support the high DC voltage rating and/or in parallel to support the high DC current (to increase the power for a given DC voltage). Most of HVDC projects employ two thyristor bridges, known as Twelve-Pulse Bridge, connected in series in order to reduce the harmonics in DC voltage as well as in AC currents. For this purpose, the secondary winding of AC transformers are different to create a displacement between the two connected AC grids (see

AC Grid Connection

Reactive Power Compensation

AC Filter

Transformers

Smoothing

Reactor

DC Grid Connection

DC Grid Connection

LCCs Based Thyristor

DC Filter

 DC Filter: The LCC topology requires harmonic filtering on the DC system. This is especially the case for overhead line applications.

 DC Smoothing reactor: The LCC topology requires a stiff current on the DC system.

 AC Transformers: Since the secondary windings see a standing DC offset, these transformers are manufactured specifically for HVDC applications.

 AC Filter: The LCC topology requires harmonic filtering on the AC system since low frequency harmonics are generated during commutation process.

 AC Reactive support: The LCC topology requires significant reactive power compensation.

An improved topology of the LCC system to overcome part of the above mentioned problems is the capacitor-commutated converter (CCC), where AC capacitors are inserted in series between the valves and converter transformers (see Figure I-11). It has been introduced for HVDC application in 1990 and was commercialized in 1999 [START_REF] Gole | Capacitor commutated converters for long-cable hvdc transmission[END_REF].

The series connected capacitors not only supply the reactive power consumed by the thyristors, they also improve the dynamic performance of the HVDC system. However, the major drawback of the CCC concept is that the series capacitors increase the insulation costs of the valves. Moreover, since all the power passes through the employed capacitors, the latter have to be oversized which increase relatively the converter cost. Thus, the CCC has been so far only applied to back-to-back links, where the voltage level of the valves is much lower [START_REF] Rudervall | High voltage direct current (hvdc) transmission systems technology review paper[END_REF][START_REF] Persson | Hvdc capacitor commutated converters in weak networks[END_REF].

Self-Commuted Converters (Voltage Source Converters)

The continuous development of power switches leads to the emergence of self-commutated high-power switches such as Gate Turn-off Thyristors (GTOs), Insulated-Gate Bipolar Transistors (IGBTs), Integrated Gate-Commutated Thyristors (ICGTs)... Thanks to their turnon/ turn-off capabilities, a new converters topology known as Self-Commuted Voltage Source Converter (SCC or VSC) has been employed for HVDC application [START_REF] Barnes | Voltage source converter hvdc links-the state of the art and issues going forward[END_REF]. Its first application was in 1997 for Hellsjön-Grängesberg project in Sweden. Contrary to the CSC technology, the VSC has a capacitor in DC side which behaves as a constant voltage. Moreover, this topology is self-commuted and doesn't based the commutation process on the AC grid voltage. It can take place by self-controlling ON/OFF actions of the switches. For high voltage applications such as HVDC, due to the voltage limits of IGBTs, series connection of several hundred is necessary. These latter have to be switched simultaneously that require specialized types of IGBT with sophisticated gate drive circuits in order to share properly the voltages across all the connected components.

To overcome the stress related to switch simultaneously IGBTs and high order harmonics filtering, technologies of VSC have been evolving. Different multilevel topologies were proposed such as 3-level VSC, also known as neutral-point diode-clamped (NPC) [START_REF] Lindberg | Pwm and control of three level voltage source back-toback station[END_REF], Flying capacitor (FC) [START_REF] Lai | Multilevel converters-a new breed of power converters[END_REF], Cascaded Multilevel Converter [START_REF] Sirisukprasert | Modeling, analysis and control of cascaded-multilevel converter-based statcom[END_REF]… With such topologies, the switching frequency of individual semiconductors and harmonics can be reduced; however, their application for HVDC transmission is complicate due to the complexity in topology structure and control. Moreover, the failure of some devices can hinder the operation of the entire converter system.

In addition to VSC converter, the main components constitute VSC-HVDC station (see Figure

I-14) are:

 DC Capacitors: The VSC topology requires a stiff voltage on the DC system.

 AC Reactor: The VSC topology requires AC reactor in order to limit the rate of rise of current seen by the IGBTs, to act as a low pass filter and to allow the control of the input currents.

 AC Transformer: Any transformer configuration can be used to set the secondary voltage rating. Standard transformers can be used with VSC which is not the case with LCC.

 AC Filter: The VSC topology generates high order harmonics which need to be filtered using a high pass filter [START_REF] Barnes | Voltage source converter hvdc links-the state of the art and issues going forward[END_REF].

Advantages of LCC compared to VSC

 The typical losses using LCC is around 0.7%. Because of high switching frequency, the losses using VSC is relatively high (around 1.7%).

 High power and good overload capabilities for LCC compared to VSC.

 The LCC technology is cheaper than the VSC one.

 Low elements (higher reliability) employed with LCC compared to VSC [START_REF] Sellick | Comparison of hvdc light (vsc) and hvdc classic (lcc) site aspects, for a 500mw 400kv hvdc transmission scheme[END_REF].

Advantages of VSC compared to LCC

 The VSC can inject or absorb reactive power irrespective of the active power direction.

On the other hand, depending on the firing angles, the reactive power consumption of an LCC is approximately 50 to 60% of the active power.

 LCC topology requires a stiff AC side voltage to avoid commutation failures (especially on the inverter side). The self-commuting capability of VSC allows to overcome this problem.

 Harmonics filtering is required on the AC and DC system with LCC. This requirement is reduced using VSC leading to reduce the size of filter elements.

 The LCC is limited on minimum power transfer, it is about 10% of the rated power transfer. Using an appropriated control, the VSC can operate with zero AC current (zero power).

AC Grid Connection

AC Filter

Transformer

DC Capacitors

AC Reactor

DC Grid Connection

DC Grid Connection

VSC

 The reverse of power using LCC is based on changing the DC voltage polarity. For this purpose, a specific cables such as Mass Impregnated (MI) or Oil-Filled (OF) cables are employed. Thanks to bidirectional switches used with VSC, the reverse of power is based on changing current direction while the DC voltage has the same polarity. This allows to use XLPE cables which present several advantages regarding operating temperature, higher mechanical strength and lower environmental risk [START_REF] Jacobson | Hvdc with voltage source converters and extruded cables for up to±300 kv and[END_REF].

 VSC is a suitable technology for mashed Multi-Terminal DC grid (MTDC).

 The LCC creates some voltage/power stability problems when connected to a weak AC system (low short circuit capacity). No restriction regarding short circuit capacity using VSC.

 The VSC station is more compact than the LCC one (40-50 % smaller).

 LCC requires a specific AC transformer (continuous DC Voltage stress). Conventional transformers are sufficient for symmetrical monopole scheme with VSC.

 Black star process can be achieved easily with VSC, it requires additional equipment with LCC [START_REF] Bahrman | The new black start: system restoration with help from voltage-sourced converters[END_REF].

 It is possible to eliminate the converter transformers in VSC-HVDC systems.

Although all the advantages cited before, HVDC markets are still dominated by the LCC since it is a mature technology. However, it is expected that the VSC technology will take place in the future since there are lot of researches involving this technology from academic researchers as well as industrial ones.

Modular Multilevel Converter (MMC)

In order to make the VSC technology more efficient and economic, it is necessary to establish new VSC topologies which should avoid connecting several switches in series, operate with a low switching frequency, and enable scaling to different power and voltage levels. In 2003, a revolutionary Multilevel VSC topology was proposed by Professor Marquart [START_REF] Marquardt | Current rectification circuit for voltage source inverters with separate energy stores replaces phase blocks with energy storing capacitors[END_REF][START_REF] Marquardt | A new modular voltage source inverter topology[END_REF]. This topology is called Modular multilevel converter (MMC) also known as MMC, M2C or M2LC in the literature publications. It consists of connecting several 2-level converters in cascade to generate an AC voltage output. Its first commercial application for HVDC was in the Trans Bay Cable project in 2010 [START_REF] Teeuwsen | Modeling the trans bay cable project as voltage-sourced converter with modular multilevel converter design[END_REF]. Recently, there are several MMC projects being planning or in Based on those advantages, lot of researches have proved that the MMC is a promising candidate for HVDC application and all the future projects will be based on such topology. This section intends to give a review of the actual state of the art of MMC technology.

Topology and principle

The general topology of a typical three-phase MMC is illustrated in Figure I-15. It consists of 3 legs, one leg per phase, each leg can be divided into an upper part and lower one called "arms". These letter are connected in series between the DC poles while the AC output is placed at the middle of them. Each arm includes multiple cells called Sub-Modules (SMs) connected in series. The number of SM is determined according to the voltage rating of DC grid and employed switches; e.g. 300~400 SMs per arm are required for 640 kV DC voltage rating with 3.3 kV switches voltage rating. In addition to SMs, the MMC arm includes a reactor that have two main functions:  Limitation of arm current harmonics.

 Limitation of DC fault currents.

The size of arm inductance is based on those two functions. Generally, people use the second function since a small inductance value can satisfy the first one [START_REF] Tu | Parameter design principle of the arm inductor in modular multilevel converter based hvdc[END_REF].

Generally, an individual SM is formed by capacitors and switches (IGBTs with their corresponding free-wheel diodes) connected with different configuration to obtain several topologies (see section 5.2). For a given SM configuration, the SM can insert or not capacitors between its two terminal branches. Hence, with a predefine control sequence, a modulated voltage can be created with the arm by connecting or not SMs sequentially [START_REF] Siemaszko | Conception of a modular multilevel converter in a multi-terminal dc/ac transmission network[END_REF]. The inserted voltage has to meet the criterion that the sum of upper and lower one has to be equal to the DC voltage on one hand and the difference of them has to generate an AC waveform voltage on the other hand. Consequently, if the value of the modulated upper arm voltage is increased, the modulated lower arm voltage should be decreased respectively and vice versa.

SM Topologies

The MMC has been firstly proposed based on a 2-level SM, known as Half-Bridge SM (see  On-state SM: this state is achieved when S1 is turned on and S2 is turned off. The SM capacitor is connected to the arm circuit and the voltage across the SM branches is equal to capacitor one. Depending on current direction, the capacitor is charged through the diode D1 or discharged through S1.

 Off-state SM: this state is achieved when S1 is turned off and S2 is turned on. In this case, the SM capacitor is bypassed and the voltage across the SM branches is set to zero.

The current flows through either S2 or D2 while the capacitor voltage remains constant.

 Blocked state: this state is a special one that can hold during some situations, faults for example. It is achieved by setting S1 and S2 to a turn off state. The SM capacitor may charge through D1 when the arm current flows from DC to AC grid, otherwise, it will be bypassed with D2. In practice, for reliability matter, a mechanical switch is need to bypass the SM in case of internal fault. Moreover, in order to protect the diodes against the high current in case of faults, a thyristor is placed in parallel of the SM (see Figure I-18).

In the literature, several SM topologies have been proposed to build the MMC cells. The main ones are: Full-Bridge SM (FBSM), Double-Clamped SM (DCSM) [START_REF] Marquardt | Modular multilevel converter: An universal concept for hvdc-networks and extended dc-bus-applications[END_REF] and Cross-Connected Half-Bridge [START_REF] Nami | Five level cross connected cell for cascaded converters[END_REF] (see Figure I-19). In addition to the configurations obtained with Half-Bridge, these topologies can generate a negative voltage (bipolar SMs) which can give operational advantages; DC fault current capability for example. On the other hand, they carry the disadvantage that they require more IGBTs, the cost of the converter as well as the power losses increase. Therefore, only the half-bridge topology is considered in the rest of the thesis.

MMC Topologies

Recent research has highlighted a number of interesting converter topologies [START_REF] Yuan | Derivation of voltage source multilevel converter topologies[END_REF]. Hybrid MMC topology proposed by Hitachi [START_REF] Inoue | Modular multilevel converter with dc fault protection[END_REF] represents a promising solution for future HVDC projects. It consists of using Half-Bridge and Full-Bridge SMs to form the MMC arm. It carries the advantage that it is more efficient and less costly than FB MMC and brings the DC current fault capability which is the main drawback of HB MMC. It offers also the possibility to operate the symmetric monopole as an asymmetric one during riding through point to ground DC fault [START_REF] Cui | A comprehensive dc short-circuit fault ride through strategy of hybrid modular multilevel converters (mmcs) for overhead line transmission[END_REF]. The number of components is reduced compared to the standard MMC and the DC fault current can be blocked easily. However, even the commutation process of director switches (constituting 2-level converter) is based on low switching frequency, these letter are hard switched simultaneously which demands equalization of dynamic characteristics of the connected IGBTs. To overcome this problem, GE Grid Solution has propose a second version known as "Alternative Arm Converter" (AAC) [START_REF] Cross | Chain-link based hvdc voltage source converter using current injection[END_REF][START_REF] Merlin | The alternate arm converter: A new hybrid multilevel converter with dc-fault blocking capability[END_REF]. Contrary to the first version, the stack of Full-Bridge is placed in the arms and not in the AC lines. In addition to the previous advantage with the previous version (DC fault blocking capability, excellent AC voltage output), the switching constraint is reduced significantly. On the other hand, this topology requires more elements than the previous one. In partnership with university of Nottingham, GE Grid Solution has propose a novel MMC topology called "Series Bridge Converter" (SBC) [START_REF] Feldman | A hybrid modular multilevel voltage source converter for hvdc power transmission[END_REF][START_REF] Feldman | A hybrid voltage source converter arrangement for hvdc power transmission and reactive power compensation[END_REF] All these topologies, despite the advantages they offer, their application in real projects will not be in the next decade. They require lot of researches in terms of control complexity, elements sizing and practical realization.

Conclusion

This chapter permits to better understand the thesis topic (HVDC system) and its chronological evolution. The advantages of MMC based VSC compared to other proposed solutions have shown that such topology is a promising solution for future HVDC projects. For this purpose, the principle of MMC as well as its SM topologies have been presented and compared. Other MMC topologies such as AAC, SBC and hybrid MMC are new topologies that have shown a great potential however their application for HVDC projects is still early.

Because it is the cheapest topology and most of HVDC projects are based on it, the Half-Bridge topology is considered as the focus of the following work. For this topology, the problematics involving its modeling and control are presented, discussed and improved in the following of this thesis.

CHAPTER II Modular Multilevel Converter

Model categories

A model is always a simplified representation of a given real process, system or object. The ideal and perfect model must be accurate, fast, and easy to build and to implement. However, this perfect model is not existing, it is always a compromise between all these requirements. The modeling step is essential to understand, to control, to design and/or optimize, to assess, to observe and to predict the behavior of a system [START_REF] Bacha | Power electronic converters modeling and control[END_REF][START_REF] Meynard | Modeling of multilevel converters[END_REF].

 Understanding: In power system, models can be used to explain and predict the behavior of real equipment or process.

 Observing, predicting: For the benefit of power system operation, there is a need to perform various measurements at different nodes of the network with the most possible accurate values. However, it is not possible economically to have measurement devices at any node in the grid. Hence, it is necessary to develop component models using state estimation method to get a good estimated value of the given variables.

 Sizing/ optimizing: A model is also required in order to design a component. In the same aim as above, the use of model allows the determination of the constraints applied to the component. Moreover, it allows engineers to reach a given objective by choosing an adapted set of decision variables.

 Controlling: The control design needs specific models. Depending on the control law type, these models can be linear or nonlinear; time domain or frequency domain, continuous or discrete. They can be obtained from the system knowledge or from experiment tests.

According to how the model is interpreted and for which purpose it will be dedicated, the representation of a model may be different from one to another goal. For example, a model which is used for control purposes can be different to the ones used for circuit design or load flow calculation. Consequently, the users must narrow the type of models by identifying the requirements that must be fulfilled. To simplify, only the elements that are thought to play an important role and to reproduce the investigated phenomena must be considered.

When the models are developed for simulation purposes, the following criteria have to be considered [START_REF] Bacha | Power electronic converters modeling and control[END_REF]:

 The models have to reproduce all the possible system states with a good accuracy in steady state as well as for transient.



The models have to be with an acceptable level of complexity.

 The models have to fulfill with the user needs: control, offline / real-time simulations and design process.

 The models have to be implemented with a technical manner in a dedicated software.

 The inputs and outputs models have to be defined according to the type of study and explicitly represented inside the models.

 The definition domain of simulation (time or frequency based variables).

Due to the focus on dynamic and transient performances, the study is enlightening more dynamic models rather than static ones. Different dynamic model categories can be obtained for power converters, they are summarized in the following table.

Model classification criteria Model Types

Regarding the number of state variables

Full order models

Reduced order models

Regarding time domain evaluation

Continuous models

Sampled (Discrete) models

Regarding period evaluation

Switched models

Averaged models

Regarding implementation techniques

Circuit models

Mixed models

Analytical models

Regarding control law

Linear models

Nonlinear models

Regarding definition domain

Time domain models

Frequency domain models  Full order models: models where the number of explicit state variables is equal to the real system order.

 Reduced order models: models where the number of explicit state variables is less than the real system order.

 Continuous models: models that provide information with continuous set of differential equations  Sampled (Discrete) models: models that provide information about the evaluation of all state variables in a discrete manner.

 Switched models: models where the switching events are explicitly represented, i.e.

represented by a set of differential equations with a discrete input vector.

 Averaged models: models where the state variables and the inputs are represented by their average values.

 Circuit models: models where the elements are implemented using their associated physical models available in program libraries.

 Mixed models: models where some elements are implemented using their analytical equations and others are implemented using their associated circuit models.

 Analytical models: models where all the information are given by analytical equations.

 Linear models: models where all the state variable equations can be written with a linear differential equations system.

 Nonlinear models: models which contains nonlinear differential equations.

 Time domain models: models where all the variables are represented as a function of time.

 Frequency domain models: models where all the variables are represented as a function of frequency, (e.g., Laplace transform, 𝑧 transform…).

MMC modeling levels (state of the art)

This section describes the different modeling levels for the simulation of MMC which presents the key of future DC grid developments [START_REF] Sleiman | A survey on modeling, control, and dc-fault protection of modular multilevel converters for hvdc systems[END_REF]. Since there are many variables and switch elements inside the MMC, different modeling approaches can be used according to the time domain of the study, investigated phenomena and required accuracy.

To facilitate the explanation of different MMC models, it is better to start with the most accurate model which is the closest to the physical system. It is usually named as the full physics model.

In this model, the topology of the model is kept exactly the same as the real converter with respect of some basic simplifying hypotheses. Each IGBT is represented by an equivalent circuit based on their differential equations [START_REF] Strollo | A new igbt circuit model for spice simulation[END_REF] (see Figure II-1). The latter depends on the switch type and its internal configuration when it is manufactured. Since the topology requires lot of SMs, this type of model cannot be used for DC grid simulation involving MMCs.

Generally, this type of modeling is used to simulate and/or design power system packages (Gate Drivers).

Figure II-1: Physics based model for IGBT [START_REF] Strollo | A new igbt circuit model for spice simulation[END_REF].

By using simplified switch models, full detailed MMC models can be obtained [START_REF] Westerweller | Trans bay cable-world's first hvdc system using multilevel voltage-sourced converter[END_REF]. In order to accelerate the simulation, the IGBT model needs to be more simplified. For this purpose, the switches can be simulated as resistors with two values: 𝑅 𝑜𝑛 for closed state  Since the order of the model is same as the physical system, the model gives a good accuracy where all the phenomena can be seen including some degraded operation of SMs.

 The model can be used as a Benchmark to validate other MMC models.

 A current analysis inside the SMs can be easily performed allowing to have an accurate SMs losses estimation.

The main drawback of using full order model is related to the computational time. In fact, the simulation program creates an admittance matrix where the dimension is equal to the number of nodes in the system. This matrix has to be inverted at each switching operation which makes the simulation too slow.

Nodal analysis is one of various methods used by power system software to solve the electrical system circuit [START_REF] Strunz | Nested fast and simultaneous solution for time-domain simulation of integrative power-electric and electronic systems[END_REF]. Based on Dommel's algorithm [START_REF] Dommel | Digital computer solution of electromagnetic transients in single-and multiphase networks[END_REF], it consists of transforming the elements constituting the electric circuit to an equivalent model based on resistances and voltage sources or conductances and current sources through the application of trapezoidal integration method.

Since the MMC includes high number of nodes, applying such analysis allows decreasing the number of electrical nodes and consequently accelerate the simulation. To do so, each SM can be reduced to an equivalent (Thevenin or Norton) model (see Figure II-3) leading to obtain the full order equivalent model [START_REF] Gnanarathna | Efficient modeling of modular multilevel hvdc converters (mmc) on electromagnetic transient simulation programs[END_REF][START_REF] Saad | Real time simulation of mmcs using the state-space nodal approach[END_REF]. This model will be presented with more details thereafter in this section. The advantage of this modeling approach is that less electrical nodes are introduced in the model (admittance system is reduced). Consequently, the simulation will be faster compared to

Thevenin equivalent model

+ the other full order models. After its validation with full detailed models, it can be used for the validation of low level MMC control as well as for the validation of reduced order models.

To make the simulation of MMC more and more fast, reduced order models have been proposed

in [START_REF] Rodriguez | Dynamic averaged models of vsc-based hvdc systems for electromagnetic transient programs[END_REF][START_REF] Ludois | Hierarchical control of bridge-ofbridge multilevel power converters[END_REF][START_REF] Cherix | Functional modeling and energetic macroscopic representation of modular multilevel converters[END_REF]. This modeling approach is already developed for standard converters and it has been extended to particular converter structures like MMC. It consists of reducing the number of state variables inside the model by making some hypotheses. For MMC topology, the number of state variables can be reduced by assuming that capacitor voltage of SMs within one arm are perfectly balanced by an external control. The accuracy and validity of this hypothesis increases when the number of SMs per arm is relatively large. Based on this assumption, the arm behavior can be modeled with the so-called reduced order averaged arm model [START_REF] Ludois | Hierarchical control of bridge-ofbridge multilevel power converters[END_REF][START_REF] Delarue | Energetic macroscopic representation and inversion based control of a modular multilevel converter[END_REF]. It is based on modeling the arms with two controlled sources, (current and voltage) coupled as it is shown in Based on the hypothesis cited before and assuming that the averaged capacitor voltage of upper and lower arms within on leg are equal, the reduced order averaged leg model can be derived.

In this model, the averaged behavior is developed for all the leg (see Figure . This model can be simplified to a unique reduced averaged model by assuming that the averaged capacitor voltages of each leg are equal. More information about these averaged models can be found in [START_REF] Saad | Modélisation et simulation d'une liaison hvdc de type vsc-mmc[END_REF]. In general, the reduced order models are suitable to derive control laws for high level control such as current, power and energy loops [START_REF] Saad | Dynamic averaged and simplified models for mmc-based hvdc transmission systems[END_REF]. They can be used also for grid protection studies such as AC and DC grids fault when the blocking state is considered in the model.

+ +

Reduced averaged arm model

Based on the averaged model proposed in [START_REF] Saad | Modélisation et simulation d'une liaison hvdc de type vsc-mmc[END_REF], a phasor model (see Figure II-6) has been presented in [START_REF] Freytes | On the modeling of mmc for use in large scale dynamic simulations[END_REF]. This modeling methodology is based on a fundamental frequency approach and it is required for power flow studies when an electro-mechanical simulation tool is used to perform such study [START_REF] Deore | Dynamic phasor modeling of modular multi-level converters[END_REF][START_REF] Reed | Complex phasor modeling and control of modular multilevel inverters[END_REF]. Two hypotheses are taken in this modeling technique [START_REF] Norrga | Frequency-domain modeling of modular multilevel converters[END_REF]:

 All harmonics are neglected.

 All variables are perfectly sinusoidal. After presenting different MMC models proposed in the literature for simulation purposes (see Figure II-7), later, only the most interesting ones for EMT studies will be considered. A detailed analysis including the analytical equations and their implementation technique will be provided below.

The selected models are:

 The full order detailed model (DM).

 The full order equivalent model (EM).

 The reduced order averaged arm model (AVM).

Full order detailed model (DM)

The full order detailed model is obtained by simplifying the IGBT with a resistor which takes two values: 𝑅 𝑜𝑛 for closed state (milliohms) and 𝑅 𝑜𝑓𝑓 for opened state (megaohms). This model will be considered as a Benchmark for our considered purposes. When the model is implemented in software programs, according to the classification of [START_REF] Bacha | Power electronic converters modeling and control[END_REF] In order to simplify the process of obtaining the analytical model equations, at the beginning, only one SM is considered. According to Figure II-9, the SM state variable can be summarized in Table II Where:

-2.
𝑢 𝑐 : Switching function, 1 when the SM is inserted and 0 when it is bypassed.

𝐶:

SM capacitance (F).

𝑖 𝑎𝑟𝑚 : Arm current (A).

𝑣 𝐶 : SM capacitor voltage (V).

𝑅 𝑜𝑛 : Equivalent loss resistance (Ohm).

𝑣 𝑠𝑚 : Inserted SM voltage (V).
When the whole arm is considered, the inserted voltage by the stack can be seen as a modulated For a MMC with 𝑁 + 1 level, the equations system can be written as follow:

𝑓𝑜𝑟 𝑗 = 1,2, … 𝑁 𝑣 𝑐𝑗 = 1 𝐶 𝑗 ∫ 𝑖 𝑎𝑟𝑚 𝑢 𝑐𝑗 𝑣 𝐶𝛴 = ∑ 𝑣 𝑐𝑗 𝑁 𝑗=1 𝑣 𝑚 = 𝑁𝑅 𝑜𝑛 𝑖 𝑎𝑟𝑚 + ∑ 𝑣 𝑐𝑗 𝑁 𝑗=1 𝑢 𝑐𝑗 (II-2)
Where:

𝑣 𝐶Σ : Sum of SM capacitor voltages (V).

𝑁:

Number of SM per arm.

𝑣 𝑚 : Modulated arm voltage (V).

Full order equivalent model (EM)

As it was introduced previously, it is useful to have an equivalent (Thevenin or Norton) model for MMC since the most EMT programs use a nodal approach based solver. The equivalent model for MMC can be achieved by reducing the number of electrical nodes in the converter representation and keeping the same order as the real structure.

With trapezoidal integration method, each submodule capacitor can be replaced with an equivalent circuit (see Figure . The latter can be a voltage source 𝑣 𝐶𝑒𝑞 (𝑡 -𝑇 𝑠 ) in series with a resistor 𝑅 𝐶 when an equivalent resistive circuit is used or a current source 𝑖 𝐶𝑒𝑞 (𝑡 -𝑇 𝑠 ) in parallel with a conductance 𝐺 𝐶 when an equivalent conductance circuit is used. Their values are given by the following equations [START_REF] Dommel | Digital computer solution of electromagnetic transients in single-and multiphase networks[END_REF]: Where:

𝑅 𝐶 = 𝑇 𝑠 2𝐶 𝑣 𝐶𝑒𝑞 (𝑡) =
𝑢 𝑐 :
Switching function, 1 when the SM is inserted and 0 when it is bypassed.

𝑢 𝑐 ̅̅̅:

Switching function, 0 when the SM is inserted and 1 when it is bypassed.

𝑅 𝑒𝑞 𝑡ℎ : Equivalent Thevenin resistor (Ohm).

𝑣 𝑒𝑞 𝑡ℎ : Equivalent Thevenin voltage (V).

Figure From detailed to equivalent model.

The inserted SM voltage can be calculated by the following expression:

𝑣 𝑠𝑚 = 𝑅 𝑒𝑞 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞 𝑡ℎ (II-5)
When the whole arm is considered, the equations system describing the full order equivalent model can be expressed by equations (II-6):

𝑓𝑜𝑟 𝑗 = 1,

Reduced order averaged arm model (AVM)

The aim of this type of modelling is to obtain the general behavior of MMC arm. In this model, each MMC arm is averaged using an averaged function so-called "modulation index". For this purpose, two assumptions, mentioned previously, are introduced to derive the global arm behavior. They are:

 The SM capacitors are identical for one arm.

 Their voltages are perfectly balanced by an external control.

To derive the arm behavior model, 𝑣 𝐶Σ is defined as the sum of the voltages of all the arm capacitors:

𝑣 𝐶𝛴 = 𝑣 𝐶1 + 𝑣 𝐶2 + ⋯ + 𝑣 𝐶𝑁 (II-7)
The evolution of 𝑣 𝐶Σ can be derived according to the switching states of SMs. Where:

𝑛:

The number of connected SMs.

According to the equations above, the general behavior of the arm can be represented by an

Reduced Order Averaged Arm Models

Analytical Based Model

Circuit Based Model

MMC models including blocked state

Regarding the models presented in the previous section, it can be observed that only the controlled states are represented (except for circuit based model of DM). It means that, the presented models can reproduce the same behavior as a real MMC only when the SMs receive firing pulses from control level. However in reality, the MMC can be requested to operate in other situations such as when internal and external faults occurring. For example, in order to protect the SM capacitors against over voltage, the SMs packaging can block the firing pulses coming from control layer. This state is known as "blocked state" in which the MMC will operate as a Diode-Bridge converter. This operation mode can take place in the following cases:

 Start-up sequence: Before starting the converter operation, it is mandatory to charge the SMs to a minimum value that allows starting the control. The industrial solution is based on charging the SMs through the diodes. This charging step is known as "Uncontrolled step" and can be operated with AC or DC grids depending on the grid conditions.

 DC fault conditions: DC Fault is one of the degraded modes that can occur at any time specially when there is an overhead line connection. The arm currents reach rapidly high values which can be 10 times higher than their nominal values. The IGBTs protections within the SM packages have to react as soon as possible in order to block their pulse Moreover, in practice, the MMC arm contains some redundant SMs. Thanks to these cells, the converter can easily manage the internal degraded modes to remain itself available. When an internal fault occurs, the faulted SMs have to be bypassed with a mechanical switch leading to introduce some transients that have to be investigated and mitigated with converter control.

In order to reproduce easily and efficiently the previous cases by simulation, the MMC models have to take in consideration the normal, the blocked and bypassed states in the MMC

modeling. An averaged model has been proposed in [START_REF] Peralta | Detailed and averaged models for a 401-level mmc-hvdc system[END_REF] including the blocking capability when a DC fault occurs (see Figure . It has been proven that this model provides a good representation during DC faults however it is less accurate when AC faults occur. Moreover, startup sequence cannot be performed using this model. In [START_REF] Saad | Modular multilevel converter models for electromagnetic transients[END_REF], the blocked state has been integrated for the EM and AVM. The proposed solution consists in switching between two circuit models (controlled and blocked). By using a numerical solution (changing the time step of the simulation), the transients between these two circuits have been achieved. The drawback of using this solution is situated in their implementation method. The latter is based on an algorithm and not analytic equations which complicate their implementation in different EMT programs. Moreover, the transition between two circuits has to be adapted for each EMT program when this solution is considered.

Modulation Method

M

Power balance equation DC Fault Control

Scientific contributions

The main contribution of the following work is to propose a new modeling technique in order to integrate the previous functionalities; blocked and faulted conditions. The advantages of the proposed models is that all the possible states (controlled, blocked and faulted) are modeled using unique models to avoid the transition between two models as it was proposed in the first solution [START_REF] Saad | Modular multilevel converter models for electromagnetic transients[END_REF]. Furthermore, only simple functions are used to derive these models in order to facilitate their integration in EMT programs.

By adding the blocked and faulted states (see Figure , the different SM configurations with their associated state variables are summarized in Table II-

Semi-analytical modeling technique

Based on a mixed (semi-analytical) modeling technique, a new implementation method has been proposed in [START_REF] Dennetière | Validation of a mmc model in a real-time simulation platform for industrial hil tests[END_REF] for the reduced order averaged arm model. In this thesis, novel full order model versions based on the same approach have been proposed [START_REF] Zama | A Novel Modular Multilevel Converter Modelling Technique Based on Semi-Analytical Models[END_REF][START_REF]A novel modular multilevel converter modelling technique based on semianalytical models for hvdc application[END_REF]. After that, this method has been extended to other MMC topologies such as the Full-Bridge [START_REF] Saad | Modelling of mmc including half-bridge and full-bridge submodules for emt study[END_REF] and Clamp-Double SM (CDSM) [START_REF] Li | Real-time simulation of cdsm modular multilevel converter for hil test applications[END_REF].

As indicated by its name, this technique is based on a circuit part and analytical one (see Figure Figure Semi-analytical model proposed in [START_REF]A novel modular multilevel converter modelling technique based on semianalytical models for hvdc application[END_REF].

Other semi-analytical based models have been presented in [START_REF] Li | An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time hil test bench[END_REF][START_REF] Zhang | Average value mmc model with accurate blocked state and cell charging/discharging dynamics[END_REF]. In [START_REF] Li | An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time hil test bench[END_REF], the same approach as Figure II-17 has been used. The difference is situated in the position of controlled source (see Figure . Another implementation method has been proposed in [START_REF] Zhang | Average value mmc model with accurate blocked state and cell charging/discharging dynamics[END_REF], it is based on one controlled voltage source, one controlled switch and two diodes. Although the difference

Semi-Analytical Based Model

Equations System + + Arm Topology between these three models, they are supposed to reproduce the same behavior whatever the arm state is.

Full order detailed model based on semi-analytical modeling technique

In order to derive the equations system for DM with this modeling technique, first, only one SM is considered. According to the Table II-4, three switching functions are necessary to represent SM configurations.

𝑢 𝑐 : Switching function representing the controlled state, 1 when the SM is inserted and 0 when it is bypassed.

𝑢 𝑏 : Switching function representing the blocked state, 1 when the SM is blocked and 0 when it is controlled.

𝑢 𝑓 : Switching function representing the faulted state, 1 when the SM is out of order and 0 when it is available.

Semi-Analytical Based Model Arm Topology

+ + The equations describing the SM variables can be derived using the switching functions obtained above and current measurements as follow:

System

Equations

Table II-4: Switching functions used for semi-analytical modeling technique

Switches states State variables

𝑣 𝐶 = 1 𝐶 ∫(𝑖 𝑎𝑟𝑚 𝑢 𝑐 𝑢 𝑏 ̅̅̅ + 𝑖 𝐶 𝑢 𝑏 ) 𝑢 𝑓 ̅̅̅ 𝑣 𝑠𝑚,𝑐 = (𝑅 𝑜𝑛 𝑖 𝑎𝑟𝑚 + 𝑣 𝐶 𝑢 𝑐 𝑢 𝑏 ̅̅̅) 𝑢 𝑓 ̅̅̅ 𝑣 𝑠𝑚,𝑏 = 𝑣 𝐶 𝑢 𝑏 𝑢 𝑓 ̅̅̅ (II-10)
Where:

𝑖 𝐶 : Capacitor current (A).
𝑣 𝑠𝑚,𝑐 : Inserted SM voltage when it is in controlled state (V).

𝑣 𝑠𝑚,𝑏 :

Inserted SM voltage when it is in blocked state (V).

When all SMs are considered, the detailed model can be reduced to the model of For a MMC with 𝑁 SMs per arm, the equations system can be written as follow:

𝑓𝑜𝑟 𝑗 = 1,2, … 𝑁 𝑣 𝐶𝑗 = 1 𝐶 𝑗 ∫(𝑖 𝑎𝑟𝑚 𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ + 𝑖 𝐶 𝑢 𝑏𝑗 ) 𝑢 𝑓𝑗 ̅̅̅̅ 𝑅 𝑙𝑜𝑠𝑠 = ∑ 𝑅 𝑜𝑛 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 𝐶 Σ = ∑ 𝐶 𝑗 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 𝑣 𝐶Σ = ∑ 𝑣 𝐶𝑗 𝑁 𝑗=1 𝑣 𝑚,𝑐 = 𝑅 𝑙𝑜𝑠𝑠 𝑖 𝑎𝑟𝑚 + ∑ 𝑣 𝐶𝑗 𝑁 𝑗=1 𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ 𝑣 𝑚,𝑏 = ∑ 𝑣 𝐶𝑗 𝑢 𝑏𝑗 𝑁 𝑗=1 (II-11)
The equations (II-11) show that the SMs states are modelled with a unique model using simple functions (mathematic and logic operations). This advantage simplifies its implementation in EMT programs. It is worth noting that, when the faulted state is considered, 𝐶 Σ and 𝑢 𝑓𝑗 have to be communicate to the control system since the tuning of energy loops and balancing control algorithm (BCA) are based on these parameters respectively (see CHAPTER III).

Full order equivalent model based on semi-analytical modeling technique

To recall, the aim of this model type is to have an equivalent Thevenin or Norton circuit for each SM. For this purpose, each SM capacitor is replaced by an equivalent voltage source 𝑣 𝐶𝑒𝑞 (𝑡) in series with an impedance 𝑅 𝐶 by using trapezoidal integration method. According to Table II-4, the variation of voltage source can be expressed by the following formula:

𝑅 𝐶 = 𝑇 𝑠 2𝐶 𝑣 𝐶 = 𝑣 𝐶𝑒𝑞 (𝑡) = 𝑅 𝐶 (𝑖 𝑎𝑟𝑚 (𝑡 -𝑇 𝑠 ) 𝑢 𝑐 𝑢 𝑏 ̅̅̅ + 𝑖 𝐶 (𝑡 -𝑇 𝑠 ) 𝑢 𝑏 ) 𝑢 𝑓 ̅̅̅ + 𝑣 𝐶𝑒𝑞 (𝑡 -𝑇 𝑠 ) (II-12)
Including the blocking and faulted states, the expression of switch resistances can be expressed by: Since the detailed and equivalent models are full order ones, the inputs and outputs of equations system are same for both (see Figure .

𝑅 1 = (𝑅 𝑜𝑛 (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + |𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 | 𝑢 𝑏 ) + 𝑅 𝑜𝑓𝑓 (𝑢 𝑐 ̅̅̅ 𝑢 𝑏 ̅̅̅ + (1 - |𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 | ) 𝑢 𝑏 )) 𝑢 𝑓 ̅̅̅ 𝑅 2 = (𝑅 𝑜𝑓𝑓 (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + |𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 | 𝑢 𝑏 ) + 𝑅 𝑜𝑛 (𝑢 𝑐 ̅̅̅ 𝑢 𝑏 ̅̅̅ + (1 - |𝑖 𝑐 | |𝑖 𝑎𝑟𝑚 | ) 𝑢 𝑏 )) 𝑢 𝑓 ̅̅̅ (II-

Reduced order averaged arm model based on semianalytical modeling technique

The semi-analytical modeling technique has been firstly proposed for the averaged model in [START_REF] Dennetière | Validation of a mmc model in a real-time simulation platform for industrial hil tests[END_REF], however, the fault condition has not been considered.

Since the SMs are aggregated to one capacitor, all SMs have the same state. That means, the blocked and faulted states will concern the whole arm and not each SM as the full order models.

Taking into account the three MMC states, new parameters are used to derive the equations for averaged arm model:

𝑓:

Switching function for faulted state, 1 when the arm is faulted and 0 when it is available.

Semi-Analytical Based Model Arm Topology

Full Order Equivalent Model

Equations System + +

𝑏:

Switching function for blocked state, 1 when the arm is blocked and 0 when it is controlled.

𝑚:

Averaged function "modulation index"; 𝑚 = [0,1].

Based on these functions and current measurements, the equations system for semi-analytical model can be written as follows:

𝑖 𝐶Σ = (𝑚 𝑏 ̅ 𝑖 𝑎𝑟𝑚 + 𝑏 𝑖 𝐶 ) 𝑓 ̅ 𝐶 Σ = 𝐶 𝑁 𝑣 𝐶Σ = 1 𝐶 Σ ∫ 𝑖 𝐶Σ 𝑓 ̅ 𝑅 𝑙𝑜𝑠𝑠 = 𝑁 𝑅 𝑜𝑛 𝑓 ̅ 𝑣 𝑚,𝑐 = (𝑅 𝑙𝑜𝑠𝑠 𝑖 𝑎𝑟𝑚 + 𝑚 𝑏 ̅ 𝑣 𝐶Σ ) 𝑓 ̅ 𝑣 𝑚,𝑏 = 𝑏 𝑣 𝐶Σ 𝑓 ̅ (II-16)

Analytical modeling technique

Full order detailed model based on analytical modeling technique

Considering only one SM and according to Table II-5, the equations describing the SM state variables can be derived using four switching functions and current measurement:

𝑣 𝐶 = 1 𝐶 ∫ (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑢 𝑏 ) 𝑖 𝑎𝑟𝑚 𝑢 𝑓 ̅̅̅ 𝑣 𝑠𝑚 = (𝑅 𝑜𝑛 𝑖 𝑎𝑟𝑚 + (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 𝑢 𝑏 ) 𝑣 𝐶 ) 𝑢 𝑓 ̅̅̅ (II-17)
Where:

𝑢 𝑐 : Switching function for controlled state, 1 when the SM is inserted and 0 when it is bypassed.

Analytical Based Model Arm Topology

+

Equations

System

𝑢 𝑏 :

Switching function for blocked state, 1 when the SM is blocked and 0 when it is controlled.

𝑢 𝑓 : Switching function for faulted state, 1 when the SM is in out of order state and 0 when it is available.

𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ): Switching function for current direction, 1 when the current is positive, 0 when it is null and -1 when it is negative.

𝑖 𝑎𝑟𝑚 : Arm current (A).
𝑣 𝑠𝑚 : Inserted SM voltage (V).

Switches States State variables Switching functions

Inserted SM

(𝒔 𝟏 = 𝟏, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟎) 𝑣 𝑠𝑚 ≈ 𝑣 𝑐 𝑖 𝑐 = 𝑖 𝑎𝑟𝑚 𝑢 𝑐 = 𝑢 𝑏 = 𝑢 𝑓 = Bypassed SM (𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟏, 𝒔 𝒃 = 𝟎) 𝑣 𝑠𝑚 ≈ 0 𝑣 𝑐 = 𝑐𝑠𝑡 𝑖 𝑐 = 0 𝑢 𝑐 = 𝑢 𝑏 = 𝑢 𝑓 = Blocked SM (𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟎) 𝑖 𝑎𝑟𝑚 > 0 𝑖 𝑎𝑟𝑚 < 0 𝑖 𝑎𝑟𝑚 = 0 𝑢 𝑐 = 0 𝑢 𝑏 = 1 𝑢 𝑓 = 0 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) = 1 𝑢 𝑐 = 𝑢 𝑏 = 𝑢 𝑓 = 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) = -1 𝑢 𝑐 = 0 𝑢 𝑏 = 1 𝑢 𝑓 = 0 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) = 0 𝑣 𝑠𝑚 ≈ 𝑣 𝑐 𝑖 𝑐 = 𝑖 𝑎𝑟𝑚 𝑣 𝑠𝑚 ≈ 0 𝑣 𝑐 = 𝑐𝑠𝑡 𝑖 𝑐 = 0 𝑣 𝑠𝑚 ≈ 0 𝑣 𝑐 = 𝑐𝑠𝑡 𝑖 𝑐 = 0 Faulted / Out of order SM (𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟏) 𝑣 𝑠𝑚 ≈ 0 𝑣 𝑐 ≈ 𝑐𝑠𝑡 𝑖 𝑐 = 0 𝑢 𝑐 = 𝑢 𝑏 = 𝑢 𝑓 =
When all the SMs are considered, the arm model can be reduced to one voltage source (see Figure . The equations system describing the detailed model can be expressed by:

𝑓𝑜𝑟 𝑗 = 1,2, … 𝑁 𝑣 𝐶𝑗 = 1 𝐶 𝑗 ∫ (𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ + ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑢 𝑏𝑗 ) 𝑖 𝑎𝑟𝑚 𝑢 𝑓𝑗 ̅̅̅̅ 𝑅 𝑎𝑟𝑚 = ∑ 𝑅 𝑜𝑛 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 𝐶 Σ = ∑ 𝐶 𝑗 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 𝑣 𝐶Σ = ∑ 𝑣 𝐶𝑗 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 𝑣 𝑚 = 𝑅 𝑎𝑟𝑚 𝑖 𝑎𝑟𝑚 + ∑ (𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ + ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 𝑢 𝑏𝑗 ) 𝑣 𝐶𝑗 𝑢 𝑓𝑗 ̅̅̅̅ 𝑁 𝑗=1 (II-18)

Analytical Based Model Arm Topology

+

Equations

System

Full Order

Detailed Model

Full order equivalent model based on analytical modeling technique

The analytical model can be also applied to the equivalent model. The variation of voltage source can be derived using the following expression:

𝑅 𝐶 = 𝑇 𝑠 2𝐶 𝑣 𝐶𝑒𝑞 (𝑡) = 𝑅 𝐶 (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑢 𝑏 ) 𝑖 𝑎𝑟𝑚 (𝑡 -𝑇 𝑠 ) 𝑢 𝑓 ̅̅̅ + 𝑣 𝐶𝑒𝑞 (𝑡 -𝑇 𝑠 ) (II-19)
The equivalent Thevenin circuit for one SM can be calculate as follow:

𝑅 1 = (𝑅 𝑜𝑛 (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + ( 1+𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 𝑢 𝑏 ) + 𝑅 𝑜𝑓𝑓 (𝑢 𝑐 ̅̅̅ 𝑢 𝑏 ̅̅̅ - (( 1-𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) -(1 -|𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 )|)) 𝑢 𝑏 )) 𝑢 𝑓 ̅̅̅ 𝑅 2 = (𝑅 𝑜𝑓𝑓 (𝑢 𝑐 𝑢 𝑏 ̅̅̅ + (( 1+𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) + (1 -|𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 )|)) 𝑢 𝑏 ) + 𝑅 𝑜𝑛 (𝑢 𝑐 ̅̅̅ 𝑢 𝑏 ̅̅̅ -( 1-𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 𝑢 𝑏 )) 𝑢 𝑓 ̅̅̅ 𝑅 𝑡ℎ 𝑒𝑞 = 𝑅 2 (𝑅 1 + 𝑅 𝑐 ) 𝑅 2 + 𝑅 1 + 𝑅 𝑐 𝑣 𝑡ℎ 𝑒𝑞 = 𝑣 𝑐 𝑅 2 𝑅 2 + 𝑅 1 + 𝑅 𝑐 (II-20)
For MMC arm with 𝑁 SMs, the equations system for equivalent model is given by the following expressions: The obtained model is duplicated in Figure II-24.

𝑓𝑜𝑟 𝑗 = 1,2, … 𝑁 𝑅 𝑗1 = (𝑅 𝑜𝑛 (𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ + ( 1+𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 𝑢 𝑏𝑗 ) + 𝑅 𝑜𝑓𝑓 (𝑢 𝑐𝑗 ̅̅̅̅ 𝑢 𝑏𝑗 ̅̅̅̅ - (( 1-𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 ) 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) -(1 -|𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 )|)) 𝑢 𝑏𝑗 ))

Figure II-24: Full order equivalent model based on analytical modeling technique.

Analytical Based Model Arm Topology

+

Equations

System

Full Order Equivalent Model

Reduced order averaged arm model based on analytical modeling technique

In the averaged arm model, all SM voltages are considered to be well balanced and treated with the same manner. The switching functions used to derive the analytical model are:

𝑓:

Switching function for faulted state, 1 when the arm is out of order and 0 when it is available.

𝑏:

Switching function for blocked state, 1 when the arm is blocked and 0 when it is controlled.

𝑚: Averaged function, modulation index. 𝑚 ∈ [0, 1].
𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ): Switching function for current direction, 1 when the current is positive, 0 when it is null and -1 when it is negative.

The averaged arm model can be reduced to one voltage source (see Figure controlled by the following system equations:

𝑖 𝐶Σ = (𝑚 𝑏 ̅ + 𝑏 ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 )) 𝑖 𝑎𝑟𝑚 𝑓 ̅ 𝐶 Σ = 𝐶 𝑁 𝑣 𝐶Σ = 1 𝐶 Σ ∫ 𝑖 𝐶Σ 𝑅 𝑙𝑜𝑠𝑠 = 𝑁 𝑅 𝑜𝑛 𝑓 ̅ 𝑣 𝑚 = (𝑅 𝑙𝑜𝑠𝑠 𝑖 𝑎𝑟𝑚 + (𝑚 𝑏 ̅ + 𝑏 ( 1 + 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ) 2 𝑠𝑖𝑔𝑛(𝑖 𝑎𝑟𝑚 ))) 𝑣 𝐶Σ ) 𝑓 ̅ (II-23)

Validation of proposed models

In this section, the proposed models are compared and validated by simulation in order to assess

Control

MMC Station 2

Control

AC Grid 1 High Impedance Grounding AC Grid 2

High Impedance Grounding library. For simulation time reasons, the simulated MMC benchmark is reduced to 40 SMs instead of 400.

To simulate such system, it is necessary to design a dedicated control for each station. To do so, an energy based control (the next chapter discuss this MMC control in details) in DC voltage mode is employed to control the station 1.

In order to simplify the system, a DC current source is used to emulate the station 2 which is controlled in active power mode.

Controlled state tests

In this section, the validation of the dynamics response of the proposed models regarding two different step changes coming from the control layer is studied.

Step change in DC power reference

In the following test, the models are compared with a step change in DC current source. Initially the station does not exchange any power with AC and DC grids, at t=0.1 s, a step of 0.

Step change in stored energy reference

One of the advantages using energy based control is the decoupling between the DC grid voltage and SM voltages. This degree of freedom is tested in the following test case; at 0.5 s, the reference of SM voltages is increased from 1 pu to 1.05 pu. The results, see Figure show that the proposed model appears to be a good representation of the benchmark model during energy change.

Blocked state tests

In this section, the behavior in blocking mode of the proposed model is investigated. For this purpose, external disturbances are simulated.

Three phase AC fault

In this test, a three phase to ground fault is created. Initially, the converter send 0.5 pu power to the DC current source when the AC voltage drop from 1 pu to 0.01 pu at t = 1s. After 10 ms, It can be observed that, the three phase fault causes a drop in active power. Thus, the AC currents increase to compensate this drop. When the blocking state is activated (t =1.01s), the AC power converges to zero. Thanks to the diodes represented as a circuit in the model, the semi analytical model gives the same dynamics as the benchmark model. Despite a small difference between the analytic model and the circuit one when the blocking state is activated, it allows a good representation without any circuit representation of switches. The differences are due to the presence of snubber in the switches for the benchmark models which is not well represented with the analytical model.

Pole to pole DC fault

In the following case, a permanent pole-to-pole DC fault is scheduled at t=1. The sign function creates small numerical oscillations in the arms current when they are equal to zero, see Figure II-36. However, the results show a good agreement between the three models since the error introduced by the analytical model is less than 1%.

Faulted state tests

In this section, the dynamic behavior of the proposed models against SMs failure is investigated.

Loss of 10% SMs for one arm

The loss of 10% of SMs in upper arm for phase 𝑎 is applied at t = 3 s. the transient response of

Loss of one arm

In the following test, the loss of one arm is performed at t= 3.

Simulation performances

To show the advantage of the proposed models in term of simulation performance, the simulation time of 1s for different MMC levels is calculated and compared. The simulations have been performed on a computer with a 3.6 GHz Intel Core XeonE5-1650V4 processor. The corresponding results are shown in Table II-7. As it is observed, the acceleration of the simulation with the proposed models is more important when the number of SM is relatively high. The semi analytical model allows reducing 2*N switches per arm to only two diodes keeping the same number of state variables. This allows reducing the size of system matrix created by the solver and consequently accelerating the simulation time. The system matrix is more reduced using analytical model since the switches are not employed as a circuit. Thus, the simulation is more accelerated.

Conclusion

In this chapter, the problems related to MMC modeling for HVDC application have been addressed. After a description of different MMC model types presented in the literature, the zoom implementation technique of some models including detailed, equivalent and averaged models has been analyzed and discussed. In order to improve and integrate the blocking and faulted states in these models, two new implementation methods have been proposed which are: Semianalytical and Analytical methods. They allow obtaining unique models using simple functions to facilitate their integration in EMT programs on one hand and accelerate the simulation using less circuit elements on the other hand. The simulations with different operation conditions have proved that the proposed models give good accordance with the benchmark model. The proposed models will facilitate the integration of MMC in HVDC systems for different studies such as:

 Investigate the effect of low level control (full order models).

 Derive control laws for high level control (reduced order model) and their validations (full order models).

 Develop protection algorithms for large HVDC grids (reduced and full order models).

The various developed models will be used for simulations purposes as well as controls tuning in the next of this thesis.

Introduction

As the MMC is a particular topology which involves huge number of state variables, the MMC control requires a special care. The aim of this chapter is to provide a literature review regarding this topic. The different layers constituting the whole control are presented, explained and discussed. Given that there are so many possibilities of MMC control structures, the considered control in this thesis will end this chapter.

MMC Control principle

In order to manage the exchanged powers between AC and DC grids through the MMC, it is necessary to develop a control system which can insure this purpose. However in reality, the  First, a controller has to calculate the modulated voltage inserted by each arm according to the requested powers. This control layer is called "High Level Control".

 Then, another controller has to select the inserted and bypassed SMs in order to satisfy the requested voltage. This control is known as "Low Level Control".

High Level Control Low Level Control MMC Control Control Objectives Control Actions

Low level control

The goal of this control is to generate arm voltages as requested by the high level control and ensure a balance of energy between the different SMs. For this purposes, the low level control

Modulation technique

The aim of this bloc is to determine the number of SMs to be inserted according to the voltage references provided by the higher control layer (see Figure III-2). Two steps are necessary for this purpose:  First, calculation of modulation indexes.

 Then, calculation of number of inserted SMs.

Low Level Control

BCA Modulation method Modulation technique

Modulation index calculation Modulation Method

Modulation index calculation

The objective of this bloc is to calculate the modulation indexes corresponding to the ratio between the inserted and the available SMs within one arm. Two approaches can be used to calculate the modulation indexes which are:

Direct modulation

When the direct modulation approach is used, the modulation indexes are calculated based on DC voltage value as for standard VSCs [START_REF] Marquardt | A new modular voltage source inverter topology[END_REF].

𝑚 𝑖 𝑢 * = 𝑣 𝑚𝑖 𝑢 * 𝑣 𝑑𝑐 𝑚 𝑖 𝑙 * = 𝑣 𝑚𝑖 𝑙 * 𝑣 𝑑𝑐 (III-1)

Indirect modulation

This modulation approach is based on the available total voltage for each arm. The modulation indexes are given by the following expressions. Two manners can be used to obtain the available total voltage in the arms. They can be measured and sent to the control system as a feedback signals, in this case, the modulation

Direct modulation

Indirect modulation

Modulation index approach

Open loop

Closed loop approach will be considered as a closed loop modulation [START_REF] Antonopoulos | On dynamics and voltage control of the modular multilevel converter[END_REF]. An open loop modulation can be obtained by using some estimation or prediction models for available arm voltages [START_REF] Angquist | Open-loop control of modular multilevel converters using estimation of stored energy[END_REF][START_REF] Oates | Observer based monitoring and control of submodules in modular multilevel converter[END_REF].

The modulation index approach is a critical point in the overall MMC control since it changes the high level control architecture as well as the internal dynamics of MMC. This point will be covered when the high level part is addressed.

Modulation techniques

Low switching frequency

High switching frequency

Multilevel modulation techniques Multicarrier PWMs

Space Vector Modulation

Selective Harmonic Elimination

Nearest Level Control

For HVDC application, when the losses are the most important selective factor, low-frequency modulation techniques are preferred due to the reduction of switching losses. Therefore, next, only these methods are explained and used for thesis contribution validations.

Multilevel Selective Harmonic Elimination (SHE)

The Selective Harmonic Elimination (SHE) method has been firstly introduced by [START_REF] Enjeti | Programmed pwm techniques to eliminate harmonics-a critical evaluation[END_REF] for 2level VSC and extended to multilevel converters such as MMC by [START_REF] Du | Active harmonic elimination for multilevel converters[END_REF]. It has a theoretical potential tight control of the low order harmonics and work with low switching frequencies by using a programmed waveform reference. Where:

𝑛 :

The odd harmonic order.

By controlling the switching angles (𝛼 It has been proved in [START_REF] Du | Active harmonic elimination for multilevel converters[END_REF] that, in order to eliminate 𝑛 harmonics, 𝑛 + 1 equations have to be solved. Generally, iteration methods such as Newton-Raphson and genetic algorithms are used to solve the nonlinear equations of (III-3). Once the switching angles are obtained, they are implemented and stored in a table in order to be interpolated according to the operating conditions. In case of HVDC, when the MMC includes numerous SMs, the application of SHE method is relatively complicated due to the high number of equations that should be solved and stored.

Nearest level control (NLC)

The principle of Nearest Level Control (NLC) method is based on finding the number of inserted SMs that can generate the closest voltage to the desired reference [START_REF] Kouro | High-performance torque and flux control for multilevel inverter fed induction motors[END_REF]. This method uses an assumption that the dispersion of SM voltages is low. Once the modulation references are received, they are multiplied by the number of available SMs 𝑁 in order to get their corresponding inserted number 𝑛 𝑖 𝑢,𝑙 * . Thanks to the round function, only the nearest integer of the inserted numbers 𝑛 𝑖 𝑢,𝑙 * will be considered (e.g., round of 2.6 = 3, round of 2.4 = 2).

Consequently, the output signals take a staircase waveform as it is shown in Figure III-7. Thanks to the conceptual and implementation simplicity of NLC method, it will be used in this thesis for control algorithms validation: offline simulations, Hardware in the Loop (HIL) and experimental tests.

Balancing Control Algorithm (BCA)

The aim of this control algorithm is to choose the best arm configuration in order to maintain the voltages balanced between SM capacitors within one arm [START_REF] Bouarfa | An optimization formulation of converter control and its general solution for the four-leg two-level inverter[END_REF] . As it was introduced in CHAPTER I (see section 5.1), depending on the current flowing through the SMs and the switches state, the voltage across the SM capacitor 𝑣 𝐶 increases, decreases or stays constant. So, without such controller, some SMs will be solicited more than others leading to charge some and discharge others. To overcome this problem, a controller called "Balancing Control Algorithm (BCA)" has to ensure that the powers flowing into/from different SMs are quite equal [START_REF]A fast active-balancing method for the 3-phase multilevel flying capacitor inverter derived from control allocation theory[END_REF]. The first (typical) BCA for MMC, so-called "Basic BCA", was introduced by [START_REF] Marquardt | A new modular voltage source inverter topology[END_REF]. At each BCA cycle, the SM capacitor voltages within one arm are measured, listed and sorted in descending order, and the number of SMs to be switched on 𝑛 is received. If the arm current is positive or zero, the SMs with the lowest capacitor voltages will be switched on, otherwise, the highest capacitor voltages will be connected (see Figure III-8).

Classification of different BCAs

Four important factors and variables are impacted and/or impacting BCAs. They are: averaged switching frequency of SMs, operational point (𝑃, 𝑄), voltage ripple and voltage tolerance. The averaged switching frequency is referred to the activation and deactivation of each SM.

The operation point (𝑃, 𝑄) is corresponding to the transferred powers through the converter.

The voltage ripple, voltage tolerance and natural ripple are explained in Figure III-9.

In [START_REF] Bergna | An energy-based controller for hvdc modular multilevel converter in decoupled double synchronous reference frame for voltage oscillation reduction[END_REF], the authors have demonstrated that the circulating current which can be controlled with the high level control is highly coupled with the voltage ripple. Even those injected currents can reduce the average ripple on one hand, they increase the rms value of arm currents on the other hand. Consequently, reducing the ripple using the circulating current can be applied for some emergency situation however it is not the best solution since the conducting losses are directly affected.

A perfect BCA is an algorithm that can, reduce the switching frequency (less than 100 Hz), reduce the ripple voltage (<10 %) and eliminate the voltage tolerance between SMs for a maximum operation point (𝑃, 𝑄) 𝑚𝑎𝑥 . However, this algorithm does not exist since all these parameters are coupled. Each algorithm tries to minimize one parameter without much affecting the others. Following this philosophy, the BCA can be considered as a bloc where its inputs are the imposed parameters (according to algorithm objectives) and the outputs will be the impacted parameters (see Figure .

Control Objectives

BCAs with frequency mitigation

The goal of these methods is to minimize the switching frequency. They depend only on the operating point of the MMC and the voltage ripple will be considered as a consequence. The main BCAs with frequency mitigation presented in the literature are: This technique reduces the switching frequency by changing the state of one SM each BCA cycle [START_REF] Tu | Reduced switching-frequency modulation and circulating current suppression for modular multilevel converters[END_REF]. To do so, the algorithm distinguishes between inserted SMs and bypassed ones. By using MAX and MIN functions, the algorithm determines the maximum and minimum voltages for both inserted and bypassed SMs. Each BCA period, the difference between the new number of inserted SMs and the previous one (obtained at the previous cycle) is calculated. The algorithm chooses which SM has to be inserted or bypassed according to the algorithm presented in Figure III-12. It should be pointed out that the RSF method is not activated when ∆𝑛 = 0. The principle of IRSF method is identical to the previous one (RSF) except when ∆𝑛 = 0. For this case, the BCA permutes between one activated and one bypassed SMs when some conditions are satisfied [START_REF] Saad | Mmc capacitor voltage decoupling and balancing controls[END_REF]. When the voltage ripple becomes higher than the excepted one and according to the current direction, the BCA permutes between the MAX and the MIN of bypassed and activated SMs (see Figure . The aim of this new case is to have a better balancing between SM and to reduce (not control) the voltage ripple.

Reduced Switching Frequency (RSF)

With frequency mitigation

With ripple mitigation

Improved Reduced Switching Frequency (IRSF)

BCAs with ripple mitigation

In this BCA category, the voltage ripple is mastered in order to reduce its value. For this purpose, an additional input which is a tolerance parameter is used in order to increase or decrease voltage ripple. By choosing an appropriate value for tolerance parameter, it provides a relatively low switching frequency and maintains an adequate fluctuation of SM voltages.

Average Tolerance Band (ATBsort)

It was introduced by [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF], its corresponding flowchart is illustrated in Figure III-14. Compared with the basic BCA method, the manner how the sorting of SM voltages is made constitutes the main difference. Thanks to the tolerance parameter around the mean value, the sorting algorithm is activated only when it is necessary. This leads to a fluctuation of SM voltages without exceeding the limits set by the tolerance parameter.

Cell Tolerance Band (CTBsort)

The principle which is very close to ATB method is presented in Figure III-15. The tolerance parameter is fixed around the nominal SM voltage (not the mean value as for ATB). At each BCA cycle, SM voltages are compared to 𝑉 𝑚𝑖𝑛 = 𝑉 𝐶𝑛 -𝜀 and 𝑉 𝑚𝑎𝑥 = 𝑉 𝐶𝑛 + 𝜀. If one SM exceeds 𝑉 𝑚𝑎𝑥 or 𝑉 𝑚𝑖𝑛 , the sorting of SM voltages will be updated. If not, the algorithm keeps the previous one [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF].

There is another Cell Tolerance Band which is based on sequential reversing, it uses a simple balancing approach rather than sorting method. However it has been demonstrated in [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF] that, in some cases, the imposed tolerance band is not performed by this BCA.

Comparison

To evaluate and compare different BCAs presented in the previous section, some simulations with test cases are carried out. The detailed model based on semi analytical implementation is used to perform this comparison. The simulation time-step is set to 5 µs where the BCA sampling period is set to 100 µs in order to be in line with industrial system. The MMC parameters are the same as the used in CHAPTER II for models validation (see Table II -6) reduced to 20 SMs in order to well analyze the results. To perform such simulation, a high level control is needed. To do so, an energy based control is employed to generate the requested modulated arm voltages (it will be explained in the next of this chapter). For different transferred power values, the associated switching frequency and the voltage ripple (peak to peak) are calculated.

Basic BCA

The SM voltages for one arm are presented in The main drawback of this method is that the latter depends only on the BCA cycle frequency.

Since the previous state is not taken into consideration, the BCA introduces several additional switches in order to have a perfect balance between SMs. Another inconvenient is the sorting technique which needs 𝑁 * 𝑙𝑜𝑔(𝑁) iterations, it creates a big challenge for industrial applications (computational abilities, FPGA memory, data communication delay…). For this purpose, some optimized sorting algorithms such as the Bitonic sorting which is presented in [START_REF] Ricco | Fpga-based implementation of sorting networks in mmc applications[END_REF] to optimize the computation speed for example.

Reduced Switching Frequency

According to the results presented in

Average Tolerance Band (Sorts)

The SM voltages for one arm and the variation of switching frequency with SMs ripple for different power levels are presented in allows to maintain the SMs voltages with the limits set by the tolerance parameter, the obtained ripple with ATB method depends on the transferred power. This difference can be attributed to the fact that the limits (𝑉 𝑚𝑖𝑛 and 𝑉 𝑚𝑎𝑥 ) are not calculated in the same manner for same tolerance parameter value. For this reason, the ATB method has to be improved in order to well control the voltage ripple. Regarding the chosen AC current direction, it can be expressed as a subtraction of arm currents.

𝑖 𝑖 𝑎𝑐 = 𝑖 𝑖 𝑢 -𝑖 𝑖 𝑙 (III-6)
Then, the equations (III-5) can be written in form of matrix as follow.

[

AC power equation

The model given in equations (III-8) offers the possibility to derive the control laws for arm currents by controlling the values of 𝑣 𝑚𝑖 𝑢 and 𝑣 𝑚𝑖 𝑙 (input vector). However, in order to understand the behavior of MMC regarding the connected grids (AC and DC grids), it is recommended to derive dedicated models where the AC and DC currents constitute their state variables. This allows obtaining an explicit relationship between the control objectives and controlled variables. To do so, some mathematical approaches are applied to model (III-5).

Summing the upper and lower parts of the model (III-5) leads to obtain the following equation.

Energy global equation

Equations (III-11) and (III-13) show that, unlike standard VSCs, the AC and DC currents can be controlled independently using MMC. The difference between input and output powers appears as variation of the stored energy inside the MMC (see Figure . The global energy is defined by the following expression:

MMC leg DC Equivalent Circuit

𝑊 𝑚𝑚𝑐 = ∑ 𝑊 𝑖 𝑢 + 𝑊 𝑖 𝑙 𝐶 𝑖=𝑎 (III-15)
Where:

𝑊 𝑖 𝑢,𝑙 : is the available energy in one arm (sum of all SMs energy within one arm).

Hence, since the MMC requires energy to operate properly, it is mandatory to have a controller to regulate the stored energy. Its objective is to ensure that the global energy stored inside the MMC allows operating the MMC in a good operation conditions. According to equation (III-14), this objective can be performed either by bringing power from AC grid or from DC side.

Energy balancing equations

Based on equation (III-15), it is obvious that controlling the global energy (𝑊 𝑚𝑚𝑐 ) is not a sufficient condition to ensure a good operation since the energy arms are not directly controlled.

An unbalanced condition of stored energy between the arms can take place without being seen by the global energy controller (see Figure . To solve this issue, it is necessary to derive

Rectifier Inverter

DC Grid AC Grid

MMC

other controllers that can ensure a balanced energy sharing between the arms. To derive these controllers, the arm energy variation must be analyzed to obtain their state-space equations. The variation of stored energy in arms can be expressed by:

𝑊 𝑖 𝑢 = 1 2 𝐶 𝛴𝑖 𝑢 (𝑣 𝐶𝛴𝑖 𝑢 ) 2 = ∫ 𝑃 𝑚𝑖 𝑢 𝑊 𝑖 𝑙 = 1 2 𝐶 𝛴𝑖 𝑙 (𝑣 𝐶𝛴𝑖 𝑙 ) 2 = ∫ 𝑃 𝑚𝑖 𝑙 (III-16)
The exchanged power by the arm capacitors can be written as follow:

𝑃 𝑚𝑖 𝑢 = 𝑣 𝑚𝑖 𝑢 𝑖 𝑖 𝑢 𝑃 𝑚𝑖 𝑙 = 𝑣 𝑚𝑖 𝑙 𝑖 𝑖 𝑙 (III-17)
Equations (III-17) can be expressed using AC and DC components. That is:

𝑃 𝑚𝑖 𝑢 =

MMC Energy

In one period, the average energy exchange in the arms are calculated as follow:

〈𝛥𝑊 𝑖 𝑢 〉 = ∫ 𝑃 𝑚𝑖 𝑢 2𝜋 0 = ∫ 𝑣 𝑚𝑖 𝑑𝑐 2

Energy leg (sum) equation

Adding 𝑃 𝑖 𝑢 and 𝑃 𝑖 𝑙 in (III-18) leads to obtain the instantaneous energy sum expression which can be written as follow:

𝑊 𝑖 𝛴 = 𝑊 𝑖 𝑙 + 𝑊 𝑖 𝑢 = ∫ 𝑃 𝑚𝑖 𝑙 + 𝑃 𝑚𝑖 𝑢 = 𝑣 𝑚𝑖 𝑑𝑐 𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐 (III-20)
The average energy sum variation in one period is given by The average energy difference variation in one period can be expressed as follow. Taking into account all the previous analysis, equations (III-11), (III-13), (III-14), (III-21) and

〈𝛥𝑊 𝑖 𝛴 〉 = ∫
(III-23) provide a generalized dynamic model of MMC which can be used for control purposes.

The following table recalls and summarizes what has been developed above.

High level control structure

Based on the control objectives presented in the previous section different control schemes can be used to build the high level control. They can be classified into two control schemes which are:

 Multivariable control.
 Cascaded control.

Multivariable control

The obtained control law is derived using a nonlinear multivariable model which integrates the considered state-space equations describing the MMC behavior (see Figure . This approach requires some advanced control strategies in order to derive its associated control laws and perform stability analysis which is necessary to prove the system stability. This approach has been applied to the MMC by [START_REF] Münch | Integrated current control, energy control and energy balancing of modular multilevel converters[END_REF][START_REF] Vatani | Control of the modular multilevel converter based on a discrete-time bilinear model using the sum of squares decomposition method[END_REF]. In [START_REF] Münch | Integrated current control, energy control and energy balancing of modular multilevel converters[END_REF], the authors propose a Periodic Linear Quadratic Regulator (PLQR) based on bilinear model which integrates currents, global energy and energy balancing models. Based on the same bilinear model, another controller based on Sum-Of-Squares (SOS) decomposition method has been presented in [START_REF] Vatani | Control of the modular multilevel converter based on a discrete-time bilinear model using the sum of squares decomposition method[END_REF].

The advantage of using multivariable control approach is that, using only one controller, all the state variables are controlled simultaneous (same response time for all variables) which is not possible with other approaches. However, this approach presents several drawbacks such as:

 Stability matters since there is a strong coupling between the state variables. This is especially the case when the control is tested with a physical system (some elements are not integrated in the model).

 Some internal variables are not directly mastered.

 Complicate to debug when instabilities occur.

For all these reasons, only the cascaded control structure will be considered in this thesis.

Cascaded control

The second scheme which is based on time-scales decoupling assumptions, consists of a cascaded structure in which the control algorithm is built and tuned step by step taking into account the internal variable limits. Widely used among researchers [START_REF] Åström | Towards intelligent pid control[END_REF][START_REF] Lee | Pid controller tuning to obtain desired closed loop responses for cascade control systems[END_REF], this scheme is based on the decomposition of the system into interconnected subsystems and in which each control loop is associated with a response time. For example, when considering only two cascaded controllers (inner and outer loops) and taking into account the time-scales decoupling assumptions, the inner (or internal) loop response time must be set faster than the outer loop (see Figure . The response time ratio between the two loops is not always easy to set, its limits can be often obtained from a rigorous stability analysis taking into account the whole control algorithm [START_REF] Chen | Control induced explicit time-scale separation to attain dc voltage stability for a vsc-hvdc terminal[END_REF].

Controller based on Multivariables statespace model

High Level Control

From a practical point of view, this ratio can be set to 10 in order to avoid any interference between the two loops regarding the stability.

Non-energy based control

A basic control structure can be obtained by applying a standard VSCs control to the MMC. In the literature, this control schema is known as "Non-energy based control" [START_REF] Tu | Reduced switching-frequency modulation and circulating current suppression for modular multilevel converters[END_REF], [START_REF] Saad | Dynamic averaged and simplified models for mmc-based hvdc transmission systems[END_REF], [START_REF] Martinez-Rodrigo | Current control of a modular multilevel converter for hvdc applications[END_REF], it According to MMC state space equations (see Table III-2), it has been demonstrate that, the stability of MMC control can be ensured by controlling the AC and DC currents (powers) as well as the stored energy. However, Figure shows that only the AC current is mastered when non-energy based control is used which is inconsistent with the previous analysis (see section 4.1.3).

In [START_REF] Antonopoulos | On dynamics and voltage control of the modular multilevel converter[END_REF], it has been demonstrated that the stability of non-energy based control can be ensured only by using a direct modulation approach where the modulations indexes are calculated based on DC voltage measurement (see equation (III-1)). Since the inserted voltages in the physical system are based on the instantaneous arm voltages (see Figure , a difference appears between the requested voltages (references) and the inserted ones leading to create uncontrolled DC current which flows between the DC grid and MMC. This current ensures a balanced power exchange between the AC and DC grids making the control stable. Moreover, the voltage inequality between the legs generates some undesired currents, so-called "Circulating current", which flow between the arms in form of second harmonics. These currents increase the converter loss such conduction losses inside the switches and SM capacitors losses. To overcome this issue, a Circulating Current Suppressing Controller (CCSC) has been proposed in [START_REF] Tu | Reduced switching-frequency modulation and circulating current suppression for modular multilevel converters[END_REF]. The main drawback of non-energy based control concerns the system stability when the direct modulation is not used. Since there are no energy loops in the control structure, the stored energy in the arms diverges (increases or decreases).

Energy based control

In [START_REF] Antonopoulos | On dynamics and voltage control of the modular multilevel converter[END_REF], the authors propose an improved control structure including energy loops to overcome The results show that the proposed control is stable and allows to control the AC current as well as the stored energy in the arms. However, the arm current are not well controlled especially during transients since the DC current is not directly controlled. For this purpose, a DC current controller has been added to the control structure by [START_REF] Bergna | Modular multilevel converter-energy difference controller in rotating reference frame[END_REF] in order to improve arm currents dynamics (see Figure . Compared to the first version, the proposed control reduces the arm harmonics amplitude as well as the transient period when step changes are applied. The control laws for each loop are derived based on the state-space equations summarized in Table III-2. Those state-space can be expressed in different reference frames: fixed frames (natural frame (𝑎𝑏𝑐), Alpha/Beta frame (𝛼𝛽0)) or rotating frame: Direct/quadrature frame (𝑑𝑞0). From theoretical aspects, these reference frames are equivalent as various configuration have been proposed in the literature. The choice criteria comes from practical implementation aspects such as time delays, PLL performances… The following table summarize those configurations and their associated references.

Considered control structure for thesis contributions

Given that there are so many possibilities of MMC control structures, it is necessary to clarify the control structure that has been considered in this thesis before addressing its contributions in term of control design.

High level control

The schematic diagram of used high level control is illustrated in

Outer loops

The proposed high level control is an energy based control where the following loops constitute its outer layer:

 DC voltage controller.

 Active power controller.

 Reactive power controller.

 Energy global controller.

For each loop, 𝑃𝐼 regulator is used to derive its control laws except for active and reactive power controllers where only proportional gain is used (P controller). The In addition to the references for each loop, two inputs parameter are used to perform the control which are:

 𝑣 𝑑𝑐 /𝑃 𝑎𝑐 : Switch the operation mode of the station.

 𝛼 𝑤 : Change the energy control strategy.

Energy parameter 𝛼 𝑤 allows to change the control strategy for energy loop. It takes 0 or 1 value, corresponding to respectively, AC grid and DC grid control strategy for energy loop. When 𝛼 𝑤 is set to a value between 0 and 1, the energy regulation will be shared between AC and DC grids.

Controller Controller

Control mode

Control strategy

Outer loops

The outputs are calculated as follow:

𝑃 𝑑𝑐 = 𝑃 * + 𝛼 𝑤 𝑃 𝑤 * 𝑃 𝑎𝑐 = 𝑃 * + (1 -𝛼 𝑤 )𝑃 𝑤 * 𝑄 𝑎𝑐 = 𝑄 𝑎𝑐 * (III-24)
Where:

𝑃 𝑤 * : Output of energy loop.

Energy balancing loops

According to the analysis given above (see section 4. Where:

 𝑖 1,2 𝛴 * : Output of energy sum controller.

 𝑖 𝑎,𝑏,𝑐 𝛴 * : Output of energy difference controller.

It can be observed that, thanks to transformations given in equations (III-26) of energy balancing loops, the sum of 𝑖 𝑐𝑖𝑟 * requested by energy balancing loops is always equal to zero.

Current references calculation

In the proposed control, two control strategies can be adopted:

 AC and DC currents control.

 Arm currents control.

Inner loops based on AC and DC currents controller

When the first principle is employed, the reference frames for AC and DC current loops are (𝑑𝑞0) and (𝑎𝑏𝑐) respectively. The 𝑎𝑏𝑐 frame reference for DC current controller allows to control each phase independently since the reference of circulation currents coming from energy balancing loops are given for each phase. The advantage of using rotating frame (𝑑𝑞0) in control theory is that, the sinewave references become a continuous components. To do so, the AC currents are transferred to direct and quadrature components and compared to their references. This transformation needs to measure the phase angle of AC voltage using a Phase locked loop (PLL) (see APPENDICES, section 2.5) requesting high performances in terms of convergence time and robustness. The current references using this current control strategy are given by the following expressions:

𝑖 𝑖 𝑑𝑐 * = 𝑃 𝑑𝑐 3 𝑣 𝑑𝑐 + 𝑖 𝑖 𝑐𝑖𝑟 * 𝑖 𝑑 𝑎𝑐 * = 𝑃 𝑎𝑐 𝑣 𝑑 𝑎𝑐 𝑖 𝑞 𝑎𝑐 * = -𝑄 𝑎𝑐 * 𝑣 𝑑 𝑎𝑐 (III-27)
The response time of current loops depends on the controller design. For example, when a 𝑃𝐼 controller is used, the response time can be set to 5 ms for AC current controller and 3 ms for DC one. Advanced controller design techniques are requested if the response time needs to be accelerated.

Inner loops based on AC and DC currents controller.

If equation (III-27) is considered, the first strategy will strongly depend on the PLL performances. In order to reduce its impact on the MMC control, an inner control strategy based on arm currents is proposed here. In this control strategy, the arm currents controller is derived in (𝑎𝑏𝑐) frame. Based on the inverse of alpha/beta transformation, the three phase AC currents can be calculated by the following expression: (III-28)

[ 𝑖 𝑎 𝑎𝑐 * 𝑖 𝑏 𝑎𝑐 * 𝑖 𝑐 𝑎𝑐 * ] = √ 2 3 1 (𝑣 𝛼 𝑎𝑐 2 + 𝑣 𝛽 𝑎𝑐 2 ) [ 1 0 - 1 2 √3 2 - 1 2 - √3 2
The relation between the arm currents, AC currents, circulating currents and DC current is given by the following equation: The response time of the inner loops has to be set as fast as possible when the arm currents control strategy is adopted in order to follow the arm current references sinewaves. Therefore, advanced control algorithms are needed to overcome the 𝑃𝐼 controller limitations. A comparative assessment by simulation show that there is no perfect method since all the parameters (switching frequency, voltage ripple, tolerance parameter and operation point) are directly coupled.

Conclusion

The high level control has to calculate the modulated voltages for each arm according to control objectives. The state-space equations of the MMC system have been extracted to understand its behavior regarding the connected grids and design its associated control algorithms. A global consideration of the MMC system by handling its state space model as multivariable control problem and cascaded control formulation which is based on time scales assumption have been discussed; the latter (cascaded control) has been chosen in the proposed work. Thereafter, The energy based and non-energy based controls have been explained with conclusion that the first control allows to obtain a better control of all MMC variables which is not the case with nonenergy based control.

The energy based control which has been considered in this thesis allows to control the active power, reactive power, DC voltage and stored energy simultaneously. The energy regulation strategy can be adapted using energy parameter 𝛼 𝑤 and enabling the control of MMC energy from AC grid, DC grid or a contribution of both with a chosen ratio. Finally, it has been shown that two control strategies can be employed to master the current references provided by the outer loops as well as energy balancing ones. The first strategy is based on controlling the output current (AC and DC currents) where the second one is based on controlling the internal currents (arm currents).

Introduction

The purpose of this chapter is to provide contributions for both high and low level layers.

Regarding the lower level, the Average Tolerance Band (ATB) method is improved in order to obtain a desired ripple and reduce the switching frequency. In order to overcome the large response time for outer loops when a cascaded structure is considered, a high dynamics controllers are proposed for MMC currents. First, for both (AC and DC currents/MMC arm currents) control strategies, continuous-time controllers based on variable structure control "sliding mode control" are proposed and validated using simplified models. To go further in term of performances and in order to integrate the hardware constraints such as sampling period (𝑇), explicit formulation based on novel discrete-time controllers have been derived considering exact discrete-time models. The obtained solutions has been compared to the known one based on Euler approximation. Finally, offline validation of proposed controllers for normal operations and against externals events are carried out to show their advantages.

A contribution to low level control: Improved

Averaged Tolerance Band (IATB) method

Introduction

As a reminder, the proposed ATB method in [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF] consists of mitigating the SMs ripple while maintaining a relatively low number of switching. Thanks to the tolerance band parameter 𝜀, the ATB algorithm ensures that the SM voltages are kept inside a hysteresis band (dashed lines)

as it is shown in Figure IV-1. The results presented in Table IV-1 have been calculated using the same simulation parameter in CHAPTER III (see section 3.4). According to Table IV-1, it can be concluded that the obtained ripple using ATB method depends on the transferred power. This can be attributed to the fact that the limits of hysteresis band are calculated based on the average ripple which is imposed by the operation point (transferred powers). In order to consider the ATB method as BCA with ripple mitigation, the presented ATB in [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF] has to be improved to keep the SM voltages ripple equal to the desired one. new algorithm is proposed here where the tolerance parameter becomes a degree of freedom.

Improved ATB algorithm

The latter becomes a control parameter in order to:

 Maintain the ripple of SMs equal to the limits.

 Minimize the switching frequency and consequently the switching losses.

In the new ATB method (see Figure IV-3) and in addition to standard inputs (current direction, SM voltages and number of SMs to be inserted), the desired ripple value, operation point (𝑃, 𝑄)

and the characteristics of Figure IV-2 are used to perform this BCA [START_REF] Zama | Optimisation des pertes par commutation dans un convertisseur modulaire multiniveaux (mmc)[END_REF]. The tolerance parameter is calculated in real time according to the power setpoints and the desired ripple. This makes it possible to keep the MMC working with optimized switching frequencies according to the power exchanged while keeping the same ripple of the voltages.

Simulation and validation

In order to test the proposed method, the following simulations have been carried out. The same simulation circuit with same parameters used in CHAPTER III (see section 3.4) are employed to perform the following test cases. Initially, the exchanged power is set to zero where the ripple reference is set to 11%. The events are steps change in the active power reference, it takes different values as follows:

 At t=0, an increased step of 0.6 pu is applied.

 At t=0.2, a decreased step of 0.3 pu is applied.

 At t=0.4, an increased step of 0.6 pu is applied.

The simulation results are presented in As it can be seen, the proposed BCA makes it possible to keep the voltage ripple less than the imposed value (11%) for different levels of exchanged power. Making the tolerance parameter as variable allows to decouple the obtained ripple from the transferred power level which was not possible with the first version of ATB method presented in [START_REF] Hassanpoor | Tolerance band modulation methods for modular multilevel converters[END_REF]. A zoom on SM voltages is The proposed BCA enables the MMC to operate with low switching frequencies (100-150 Hz) at low power levels (0.3 pu) and medium frequencies with high power levels (0.9 pu) (see Table IV-2).

Another important point playing a crucial role in the voltage ripple is the capacitor value. The latter plays an important role in the voltage ripple. An oversizing of its value reduces the natural ripple of the voltages, thus allowing to switching frequency reduction. Consequently, a costbenefit analysis (switching losses / SM sizing) is necessary in order to properly size the MMC capacitors.

Less switching frequency

High switching frequency

Contributions to high level control: high dynamics MMC control

Introduction

In cascaded control scheme configuration, the main hypothesis in order to decouple the system, is to establish control layers where the response time of each layer is set inside a time range.

Knowing that our aim is to accelerate the whole control system, in such configurations, the response time of the outer loops is highly related to the inner loop ones. The outer loops cannot be accelerated beyond a critical value in order to not deteriorate the stability of the control system which conflict with the starting hypothesis of cascaded systems. From practical point of view which is often used in industry, the ratio between response time of outer and inner loops is set higher than 10. Moreover, the response time of the inner loops cannot be decreased indefinitely as it is limited by the physical limits of the converter and by the hardware technology in which the balancing control algorithm is implemented. Different control based techniques for MMC currents have been presented in the literature: 𝑃𝐼 controllers [START_REF] Bergna | An energy-based controller for hvdc modular multilevel converter in decoupled double synchronous reference frame for voltage oscillation reduction[END_REF][START_REF] Antonopoulos | On interaction between internal converter dynamics and current control of high-performance high-power ac motor drives with modular multilevel converters[END_REF],

Proportional-resonant controllers [START_REF] Picas | Closed-loop discontinuous modulation technique for capacitor voltage ripples and switching losses reduction in modular multilevel converters[END_REF], Internal Mode Control (IMC) [START_REF] Li | A modular multilevel converter type solid state transformer with internal model control method[END_REF] and optimal Linear Quadratic Regulator (LQR) controller [START_REF] Rakhshani | Modeling and control of multi modular converters using optimal lqr controller with integral action[END_REF]. These controllers have been obtained using continuous state-space models. They offer good dynamics if their response time requirement is large enough. However, reducing their response time can make the system unstable. Moreover, when they are implemented in digital signal processors, some simplifying assumptions have to be introduced. These assumptions can affect the desired dynamics and create instability in the control system. In the following, new controllers based on variable structure control are proposed which allow to accelerate the response time of current loops. In order to not burden the reading, it should be noted that all developments based design has been applied to the first current control strategy which is controlling the output currents (AC and DC currents). For the second control strategy (MMC arm currents), it is given in APPENDICES, section 3.

Variable structure MMC control: sliding mode control

Since the objective of this work is to accelerate the response time of inner loops and consequently the outer loops, sliding mode control based design has been chosen to derive their control laws. In addition to converge in finite time, the design of such variable-structure control makes the derived control law insensitive to parameter uncertainties and external disturbances which is hardly possible with other fast controllers [START_REF] Carpita | Experimental study of a power conditioning system using sliding mode control[END_REF][START_REF] Mendalek | Sliding mode control of 3-phase 3-wire shunt active filter in the dq frame[END_REF][START_REF] Fadel | Fixed frequency sliding mode control for boost converter[END_REF][START_REF] Grégoire | High reliability observers for modular multilevel converter capacitor voltage evaluation[END_REF]. In this section, the sliding mode approach is applied to the AC and DC continuous-time models in order to derive their associated control laws.

Sliding mode control for MMC

As a reminder, for a three-phase MMC, the continuous state-space AC and DC model in 𝑑𝑞

and 𝑎𝑏𝑐 references frame respectively can be written as: Based on equations (IV-1) and (IV-2), the current controllers have to calculate the control vector 𝑣 𝑟𝑙 𝑎𝑐 and 𝑣 𝑟𝑙 𝑑𝑐 to bring the currents to their references. For this purpose, two sliding surfaces for AC side and three for DC one can be chosen according to control target (reference requirements), that are:

𝑠 𝑎𝑐 = { 𝑠 1 𝑎𝑐 = 𝜀 1 𝑎𝑐 𝑠 2 𝑎𝑐 = 𝜀 2 𝑎𝑐 𝑠 𝑑𝑐 = { 𝑠 1 𝑑𝑐 = 𝜀 1 𝑑𝑐 𝑠 2 𝑑𝑐 = 𝜀 2 𝑑𝑐 𝑠 3 𝑑𝑐 = 𝜀 3 𝑑𝑐 (IV-3)
Where: 𝛽 𝑑𝑐 = 𝐷 Since the input vector appears explicitly in the time derivative of sliding surfaces, then, the transversality condition is satisfied for the considered system (equations (IV-5) [START_REF] Bacha | Power electronic converters modeling and control[END_REF].

𝜀 1 𝑎𝑐 = 𝑖 𝑑 𝑎𝑐 -
Putting the input vectors as function of sign function of sliding surfaces, that are:

[ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] 𝑖 = [ 𝑣 𝑖𝑑 𝑎𝑐 𝑣 𝑖𝑞 𝑎𝑐 ] = -𝛽 𝑎𝑐 -1 𝑘 𝑖 𝑎𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑎𝑐 ) [ 𝑣 𝑟𝑙𝑎 𝑑𝑐 𝑣 𝑟𝑙𝑏 𝑑𝑐 𝑣 𝑟𝑙𝑐 𝑑𝑐 ] 𝑖 = [ 𝑣 𝑖𝑎 𝑑𝑐 𝑣 𝑖𝑏 𝑑𝑐 𝑣 𝑖𝑐 𝑑𝑐 ] = -𝛽 𝑑𝑐 -1 𝑘 𝑖 𝑑𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑑𝑐 ) (IV-6)
Where:

𝑘 𝑖 𝑎𝑐 = [ 𝑘 𝑖11 𝑎𝑐 0 0 𝑘 𝑖22 𝑎𝑐 ] 𝑘 𝑖 𝑑𝑐 = [ 𝑘 𝑖11 𝑑𝑐 0 0 0 𝑘 𝑖22 𝑑𝑐 0 0 0 𝑘 𝑖33 𝑑𝑐 ]
Taking into account equations (IV-6), the time derivative of sliding surfaces (equations (IV-4))

becomes: In addition to the attractivity conditions and in order to ensure that the sliding surfaces are invariant when the state variables are equal to their references (i.e. 𝑠 𝑎𝑐 = 𝑠 𝑑𝑐 = 0), the time derivative of sliding surfaces has to be equal to zero. The control derived from this condition is usually called "equivalent control" in sliding mode control theory.

𝑑𝑠 𝑎𝑐 𝑑𝑡 = 𝛼 𝑎𝑐 +

Validation

In this section, the control laws (IV-11) and (IV-12) are tested by simulation using the continuous-time models (see Figure IV-7) where the parameters are given in Table IV-3. To test the control algorithms with conditions that represent the real ones, the control loops are running with 200 µs sampling period (𝑇) corresponding to the hardware time-step. The models are running with 10 µs simulation time-step (𝑇 𝑠 ) to have a good representation of physical system evolution.

Two step changes for active and reactive power references are tested in the following validation. Since there is no method to set properly the sign function vector gain, different values are used to highlight its effects.

Active Power reference [pu] Reactive power reference [pu

AC Continuous-Time Model

Control Based on Sliding Mode Control Ts = 10 µs T = [0.1 2] ms

DC

Continuous-Time Model

Control Based on Sliding Mode Control Ts = 10 µs T = [0.1 2] ms

Control System Physical System

References calculation As it can be observed the proposed control laws allow to bring the state variables to their associated references. For same gains value, it can be remarked that the obtained response time However, it can be observed that undesirable oscillations with finite frequency and amplitude, well known as "Chattering phenomenon", take place on direct components as well as on the quadrature one. It can be attributed to the large gain of sign function on one hand and the discretization of controllers with large sampling period (200 µs) on the other hand. In sliding mode control theory, such problem can be prevented with different methods [START_REF] Lee | Chattering suppression methods in sliding mode control systems[END_REF]. Choosing the interpolation solution [START_REF] Benchaib | Sliding mode input-output linearization and field orientation for real-time control of induction motors[END_REF], the sign function is replaced with a continuous function as follow:

𝑠𝑖𝑔𝑛(𝑥) = { 1, 𝑠 > 𝜎 -1, 𝑠 < -𝜎 𝑥 𝜎 , |𝑠| < |𝜎| (IV-13)
Where: 𝜎 design parameter that can change boundary limits. It can be observed from the obtained results that no chattering occurs in steady state and it is significantly reduced during transients. The currents quality is much better but at the cost of response time since the latter is increased even with same gain values as the previous test case.

In order to decrease the response time of current loops, the gain values have been increased three times bigger than the previous values. It can be concluded from all these test cases that, the choice of gain vector for equations (IV-11)

and (IV-12) is a trade-off between the response time and chattering phenomenon. Since the objective of this work is to obtain the highest dynamics without any current chattering, the actual control laws have to be improved.

Improved sliding mode control

In order to go further in term of currents loops performances, the obtained control laws (see Where:

(
𝑘 𝑝 𝑎𝑐 = [ 𝑘 𝑝11 𝑎𝑐 0 0 𝑘 𝑝22 𝑎𝑐 ] 𝑘 𝑝 𝑑𝑐 = [ 𝑘 𝑝11 𝑑𝑐 0 0 0 𝑘 𝑝11 𝑑𝑐 0 0 0 𝑘 𝑝11 𝑑𝑐 ]
Taking into account equations (IV-14), the time derivative of sliding surfaces become:

𝑑𝑠 𝑎𝑐 𝑑𝑡 = 𝛼 𝑎𝑐 -

Stability analysis

For the stability proof, Lyapunov based method is employed. Only the stability prove for AC controller is considered in the following development, the same approach can be applied for DC one.

Consider the following positive definite function (Lyapunov function) for AC side defined as.

𝜓 𝑎𝑐 = 1 2 𝑠 𝑎𝑐 𝑇 𝑄 𝑠 𝑎𝑐 (IV-20)
Where:

𝑠 𝑎𝑐 = [ 𝑖 𝑑 𝑎𝑐 -
(IV-23)
The asymptotical convergence condition is one of the method that can prove control stability.

It corresponds to prove that the time derivative of Lyapunov function is negative definite. That is: It can be concluded that the asymptotic stability of the obtained control law (equation (IV-18)) can be guaranteed and the sliding motion can be ensured for the gain vector satisfying conditions of equation (IV-17).

𝑑𝜓 𝑎𝑐 𝑑𝑡 =

Validation

After obtaining the new sliding model control laws and showing their stability, they are tested with simulation in the following. This means that, the derived control laws gains values have to be set according to the sampling period of controller when implemented. In order to well adjust the response time of current loops, it is better to consider à priori the sampling period in the control law derivation.

Discrete-time MMC control

It has been concluded in the previous section that the sampling period has a major impact on the response of continuous-time controllers. To overcome this problem, a suitable discrete-time model taking into account a priori the sampling period of the hardware controller is proposed to derive the current control law. Following this philosophy, a discrete-time controller based on model predictive control has been proposed in [START_REF] Qin | Predictive control of a modular multilevel converter for a back-to-back hvdc system[END_REF]. To go further, the Dead-Beat controllers based on discrete-time model have been proposed in [START_REF] Xi-Mei | Research on deadbeat control strategy of modular multilevel converter[END_REF][START_REF] Wang | Incorporating deadbeat and low-frequency harmonic elimination in modular multilevel converters[END_REF][START_REF] Stringfellow | A new arm voltage balancing technique for the control of modular multilevel converters[END_REF][START_REF] Oates | EnglishVoltage source converter control[END_REF]. In these papers, the authors have used simplified discrete-time models based on Euler approximation to derive these controllers. However, due to these assumptions, the desired response (one sampling period response) cannot be ensured accurately by these controllers especially when the sampling period is relatively large (i.e. 200~500 µs). In the following, a novel philosophy based on exact discrete-time models is adopted which allows the fastest dynamics as long as the system physical limits allow it and whatever the sampling period value is.

Exact discrete-time MMC modeling

For time discretization of a continuous state-space model, there are several numerical methods including Euler's forward method, Euler's backward method or Tustin's method [START_REF] Grégoire | Multi-rate real-time simulation of modular multilevel converter using cpu and fpga[END_REF].

Considering the following state-space model in continuous-time (𝑡) representation.

𝑑𝑋(𝑡) 𝑑𝑡 = 𝐴 𝑋(𝑡) + 𝐵 𝑈(𝑡) (IV-25)

The discrete-time model of equation (IV-25) can be derived using one of the methods cited before. Taking the Euler's backward method as example, the discrete-time model can be obtained using the following simplification:

𝑑𝑋(𝑡) 𝑑𝑡 = 𝑋 (𝑡 𝑛 + 𝑇) -𝑋 (𝑡 𝑛 ) 𝑇 (IV-26)
Thus, the discrete-time model based on Euler method can be written as follows.

𝑋 (𝑡 𝑛 + 𝑇) = (1 + 𝐴 𝑇) 𝑋(𝑡 𝑛 ) + 𝐵 𝑇 𝑈(𝑡 𝑛 ) (IV-27)

Thanks to its simplicity, the model of equation (IV-27) is often used when a discrete-time controller is derived [START_REF] Xi-Mei | Research on deadbeat control strategy of modular multilevel converter[END_REF][START_REF] Oates | EnglishVoltage source converter control[END_REF]. However, the simplification given in equation (IV-26) is not always exact when the sampling period is increased. To overcome this problem and in order to make sure that the obtained discrete-time models are quite close to real MMC system (continuous-models), we propose to use an exact method to derive the MMC discrete-time models.

The exact discretization of the equation (IV-25) can be derived with the assumptions that the matrices 𝐴 and 𝐵 are time invariant between 𝑡 𝑛 and 𝑡 𝑛 + 𝑇 [START_REF] Borne | Modélisation et identification des processus[END_REF]. That is:

𝑋 (𝑡 𝑛 + 𝑇) = 𝐹(𝑇) 𝑋(𝑡 𝑛 ) + 𝐺(𝑇) 𝑉 (IV-28)
Where 𝑉 is the mean vector of 𝑈 between 𝑡 𝑛 and 𝑡 𝑛 + 𝑇 and 𝐹(𝑇) and 𝐺(𝑇) are given by the following expressions:

𝐹(𝑇) = 𝑒 𝐴 𝑇 𝐺(𝑇) = 𝐴 -1 (𝑒 𝐴 𝑇 -𝐼)𝐵 (IV-29)
The Taylor expansion of 𝐹(𝑇) shows that, contrary to the Euler method, all the terms are taking in the account using the above discretization, see equation (IV-30).

(IV-30)

The main proposal here is to calculate 𝑒 𝐴 𝑇 without any first order or second order approximations. In [START_REF] Rotella | Théorie et pratique du calcul matriciel[END_REF], the authors propose to diagonalize the matrix 𝐴 enabling to find a new form for the discretized state-space representation. It is then possible to rewrite the discrete-time equation based on the eigenvectors of matrix 𝐴. That is:

𝑒 𝐴 𝑇 = 𝑃 𝑒 𝐷 𝑇 𝑃 -1 (IV-31)
Where 𝐷 and 𝑃 are, respectively, the diagonalized and transfer matrices of A. This approach will be used to derive the discrete-time models for MMC current [START_REF] Zama | High dynamics control for mmc based on exact discrete-time model with experimental validation[END_REF]. As said before and except the assumption that matrices A and B are time invariant between 𝑡 𝑛 and 𝑡 𝑛 + 𝑇, no additional simplifications or approximation are used unlike traditional method obtained by Euler or Tustin discretization.

DC side modeling

The same approach is applied to the continuous- Where:

𝐻(𝑇) = 𝑒 𝐶 𝑇 = 𝑒 -𝑇( 𝑅 𝑒𝑞 𝑑𝑐 𝐿 𝑒𝑞 𝑑𝑐 ) [ 1 0 0 0 1 0 0 0 1 ] 𝐾(𝑇) = 𝐶 -1 (𝑒 𝐶 𝑇 -𝐼)𝐷 = - 𝑒 -𝑇( 𝑅 𝑒𝑞 𝑑𝑐 𝐿 𝑒𝑞 𝑑𝑐 ) -1 𝑅 𝑒𝑞 𝑑𝑐 [ 1 0 0 0 1 0 0 0 1 ]

Models validation

The -23). This result reflects that the first or second order approximations are no longer valid when the sampling period increase. The risk with such approximate models is that the derived controls will be inaccurate highlighting unexpected behavior.

2) DC model validation

As It can be concluded that both discrete-time models (Exact and Euler) give quite equivalent response as the reference one. Moreover, contrary to the results obtained with the AC discretetime models, the error with Euler model is small enough even with a large time-step (100 µs).

This result can be explained by the absence of coupling parameters in the state matrix C of the DC model making the transition matrix simple.

Discrete-time MMC control based on pole placement method

After obtaining the exact discrete-time models for MMC output currents and showing their accuracy, control laws can be derived using those models. It should be pointed out that all control laws can be used with those models. The objective here is to have the fastest current dynamics. To do so, pole placement control technique is used to derive the control law.

Considering the state-space model of equation (IV-28), the discrete-time controller based on pole placement method has to satisfy the following condition:

[𝑋 (𝑡 𝑛 + 𝑇) -𝑋 * ] = 𝐾 𝑔 [𝑋(𝑡 𝑛 ) -𝑋 * ] (IV-34)
Where:

𝑋 * :
The reference value for state variable 𝑋.

𝐾 𝑔 : Controller gain.

The controller gain 𝐾 𝑔 is chosen to place the poles in the unity circle as required for stability matters.

AC current control law

Based on the previous condition of equation and in order to force the tracking error to the origin, the discrete-time controller of the AC side has to satisfy the following condition: Where: 𝐾 𝑔 𝑎𝑐 is the tuning gain vector for AC system.

[
In order to set properly the tuning gain vector, the pole placement based stability analysis is presented below. (IV-37)

For control system theory, in particular for discrete-time control, stability analysis is mandatory to guarantee that all poles are in a suitable region of the complex plane. For this purpose, pole location is used to analyze the stability of the proposed controller in order to set the controller gains properly. In this analysis, only the dynamic of 𝑖 𝑑 𝑎𝑐 is presented. For the 𝑖 𝑞 𝑎𝑐 the same analysis can be derived using the same approach.

Using (IV-32) and (IV-37), the transfer function for 𝑖 𝑑 𝑎𝑐 in closed loop can be derived as follows. Equation (IV-38) shows the active power dynamics regarding active power reference change.

Using the same approach, the transfer function for active power dynamics regarding reactive power reference change can be written as follows:

𝑇𝐹 𝑖 𝑑 𝑎𝑐 (𝑍) = 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * = 1 -𝐾 𝑔 12 𝑎𝑐 𝑍 -𝐾 𝑔 12 𝑎𝑐 (IV-39)
For discrete-time domain, to ensure the stability of the system, all the poles have to be inside the unit circle. According to (IV-38) and (IV-39), the gain values which satisfy this condition are:

-1 ≪ 𝐾 𝑔 11 𝑎𝑐 ≪ 1 -1 ≪ 𝐾 𝑔 12 𝑎𝑐 ≪ 1 (IV-40)
By allocating the pole in the origin of equation (IV-38), the fastest dynamic response for 𝑖 𝑑 𝑎𝑐 can be ensured. The gain condition for Dead-Beat control is given by:

𝐾 𝑔 11 𝑎𝑐 = 0 (IV-41)
Since the equation (IV-37) allows to master the decoupling between active and reactive power, allocating the pole of equation (IV-39) in the origin allows to reduce the impact of reactive power reference change. That is:

𝐾 𝑔 12 𝑎𝑐 = 0 (IV-42)
The conditions (IV- Equation (IV-47) shows that the condition 𝐾 𝑔 𝑎𝑐 = 0 is not sufficient to obtain the fastest response. In addition to 𝐾 𝑔 𝑎𝑐 = 0, the following conditions have to be satisfied:

{ 𝐺(𝑇)(𝐵 𝑇) -1 = 𝐼 𝐹(𝑇) -𝐺(𝑇)(𝐵 𝑇) -1 (1 + 𝐴 𝑇) = 0 (IV-48)
The conditions given in equations (IV-48) show that the sampling period has a big impact on the performance of the control algorithm derived from Euler discrete-time model. The proposed solution (exact discrete-time model) allows to solve this problem by ensuring the desired response.

DC current control law

As before and in order to satisfy the tracking conditions for DC side model, the following condition has to be satisfied: Taking in the account the expression of 𝑖 𝑎,𝑏,𝑐 𝑑𝑐 (𝑡 𝑛 + 𝑇) (see equation (IV-33)), the control law for the DC system is given by the following expression: Using pole location analysis, the controller gains can be set properly. Taking the current 𝑖 𝑎 𝑑𝑐 as example, its transfer function in 𝑍 representation can be derived based on equations (IV-33)

and (IV-50):

𝑇𝐹 𝑖 𝑎 𝑑𝑐 (𝑍) = 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑎 𝑑𝑐 * = 1 -𝐾 𝑔 11 𝑑𝑐 𝑍 + 𝐾 𝑔 11 𝑑𝑐 (IV-51)
The stability of 𝑖 𝑎 𝑑𝑐 can be ensured by choosing the gain value according to the following conditions:

-1 ≪ 𝐾 𝑔 11 𝑑𝑐 ≪ 1

(IV-52)
The fast dynamics can be achieved by allocating the pole in the origin. That is

𝐾 𝑔 11 𝑑𝑐 = 0 (IV-53)
The main advantage of pole placement technique is the possibility of setting the control gain within the unity circle but not necessary at the origin. This placement pole flexibility could be useful when the control outputs are saturated since that the proposed method does not take into account explicitly the limited resources of the control.

Consequently, a compromise between control dynamics and control resources (limitations) has to be taken into account in the gain tuning, especial when working at structural limitations. Of course, these limitations should be taken into account a priori in the control design. This work is not within the scope of the thesis and will be considered later.

Sliding mode discrete-time control could achieve this purpose without going deeply in the structural limitations analysis.

Discrete-time MMC control based on sliding mode control

In the following, the sliding mode control is applied to the discrete-time models given in equations (IV-32) and (IV-33). Considering the following sliding surfaces in instance 𝑡 𝑛 , defined as:

𝑠 𝑎𝑐 (𝑡 𝑛 ) = { 𝑠 1 𝑎𝑐 (𝑡 𝑛 ) = 𝜀 1 𝑎𝑐 (𝑡 𝑛 ) 𝑠 2 𝑎𝑐 (𝑡 𝑛 ) = 𝜀 2 𝑎𝑐 (𝑡 𝑛 ) 𝑠 𝑑𝑐 (𝑡 𝑛 ) = { 𝑠 1 𝑑𝑐 (𝑡 𝑛 ) = 𝜀 1 𝑑𝑐 (𝑡 𝑛 ) 𝑠 2 𝑑𝑐 (𝑡 𝑛 ) = 𝜀 2 𝑑𝑐 (𝑡 𝑛 ) 𝑠 3 𝑑𝑐 (𝑡 𝑛 ) = 𝜀 3 𝑑𝑐 (𝑡 𝑛 ) (IV-54)
Where:

𝜀 1 𝑎𝑐 (𝑡 𝑛 ) = 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝜀 2 𝑎𝑐 (𝑡 𝑛 ) = 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) 𝜀 1 𝑑𝑐 (𝑡 𝑛 ) = 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) -𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 ) 𝜀 2 𝑑𝑐 (𝑡 𝑛 ) = 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) -𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝜀 3 𝑑𝑐 (𝑡 𝑛 ) = 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) -𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 )
The control laws can be obtained by setting the sliding surfaces in instance 𝑡 𝑛 + 𝑇 to zero, that are:

𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = { 𝑠 1 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) -𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) = 0 𝑠 2 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇) -𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) = 0 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = { 𝑠 1 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 + 𝑇) -𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) = 0 𝑠 2 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 + 𝑇) -𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) = 0 𝑠 3 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 + 𝑇) -𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) = 0 (IV-55)
Replacing 𝑖 𝑑,𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇) and 𝑖 𝑎,𝑏,𝑐 𝑑𝑐 (𝑡 𝑛 + 𝑇) by their expressions (equations (IV-32) and (IV-33)), the equations (IV-55) in matrix form are given by: It can be noted that, the control laws obtained with sliding mode control is a particular case (𝑘 𝑔 𝑎𝑐 = 𝑘 𝑔 𝑑𝑐 = 0) of the obtained control laws with pole placement method (see equations (IV-37) and (IV-50)).

𝐹(𝑇
To be in line with sliding mode control design in continuous-time domain, the control law which ensures that the state variables are always equal to their references when the sliding motion is achieved, is stated "equivalent control" [START_REF] Utkin | Sliding mode control in electro-mechanical systems[END_REF]. The obtained control laws of equations (IV-57) are rewritten as: Equations (IV-58) can be modified as function of sliding surfaces as follow:

𝑈 𝑎𝑐 (𝑡 𝑛 ) = 𝑈 𝑒𝑞 𝑎𝑐 = [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 ) ] = 𝐺(𝑇) -1 [-𝐹(𝑇
𝑈 𝑎𝑐 (𝑡 𝑛 ) = 𝑈 𝑒𝑞 𝑎𝑐 + 𝐺(𝑇) -1 𝑠 𝑎𝑐 (𝑡 𝑛 ) -𝐺(𝑇) -1 𝑠 𝑎𝑐 (𝑡 𝑛 ) 𝑈 𝑑𝑐 (𝑡 𝑛 ) = 𝑈 𝑒𝑞 𝑑𝑐 + 𝐾(𝑇) -1 𝑠 𝑑𝑐 (𝑡 𝑛 ) -𝐾(𝑇) -1 𝑠 𝑑𝑐 (𝑡 𝑛 ) (IV-59)
Replacing 𝑠 𝑎𝑐 (𝑡 𝑛 ), 𝑠 𝑑𝑐 (𝑡 𝑛 ), 𝑈 𝑒𝑞 𝑎𝑐 and 𝑈 𝑒𝑞 𝑑𝑐 by their expressions given in (IV-54) and (IV-58) respectively leads to the following expressions: As the control laws are constrained by structural limits of converter (control resources), the equivalent control cannot be higher than a given values "𝑈 0 𝑎𝑐 " and "𝑈 0 𝑑𝑐 ". The bounds of equivalent control should be taken into account [START_REF] Utkin | Sliding mode control in electro-mechanical systems[END_REF] Taking in the account equations (IV-60), the following conditions have to be satisfied by the controllers. That are: When the previous conditions are not satisfied, a saturation of 𝑈 𝑎𝑐 (𝑡 𝑛 ) and 𝑈 𝑑𝑐 (𝑡 𝑛 ) takes place as follow:

𝑈 𝑎𝑐 (𝑡 𝑛 ) = -𝐺(𝑇) -1 𝑠 𝑎𝑐 (𝑡 𝑛 ) -𝐺(𝑇) -
‖-𝐺(𝑇) -1 [(𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) ]]‖ ≤ 𝑈 0 𝑎𝑐 ‖-𝐾(𝑇) -
𝑈 𝑎𝑐 (𝑡 𝑛 ) = { 𝑈 𝑒𝑞 𝑎𝑐 𝑓𝑜𝑟 ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ ≤ 𝑈 0 𝑎𝑐 𝑈 0 𝑎𝑐 𝑈 𝑒𝑞 𝑎𝑐 ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ 𝑓𝑜𝑟 ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ > 𝑈 0 𝑎𝑐 𝑈 𝑑𝑐 (𝑡 𝑛 ) = { 𝑈 𝑒𝑞 𝑑𝑐 𝑓𝑜𝑟 ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ ≤ 𝑈 0 𝑑𝑐 𝑈 0 𝑑𝑐 𝑈 𝑒𝑞 𝑑𝑐 ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ 𝑓𝑜𝑟 ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ > 𝑈 0 𝑑𝑐 (IV-62)
Using results of equations (IV-62), it should pointed out that the control outputs are saturated with control direction kept unchanged.

To prove the convergence of state variables to their references (𝑠 = 0), it is necessary to show that ‖𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇)‖ < ‖𝑠 𝑎𝑐 (𝑡 𝑛 )‖ and ‖𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇)‖ < ‖𝑠 𝑑𝑐 (𝑡 𝑛 )‖ for the two cases of equations (IV-62). For this purpose, based on equations (IV-56), the surfaces 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) and 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) are rewritten as function of 𝑠 𝑎𝑐 (𝑡 𝑛 ) and 𝑠 𝑑𝑐 (𝑡 𝑛 ) respectively. That are: According to equation (IV-60), the norm of ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ and ‖𝑈 𝑒𝑞 𝑑𝑐 ‖can be written as: From equations (IV-61), it can be concluded that the above conditions are verified.

𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝐹(𝑇
‖𝑈 𝑒𝑞 𝑎𝑐 ‖ = ‖𝐺(𝑇) -1 ‖

Control laws validation

In this section, the control laws (IV-37) and (IV-50) are tested by simulation using the continuous-time models (see Figure where the parameters are given in Table IV-3.

Gain vector tuning

In this section, the response of the proposed controllers is investigated regarding the gain vector values. For the following test, the sampling period of the control algorithms is set to 0.5 ms.

The event is a step change of 0.2 pu in active power reference which is initially set to zero.

Three values for gain vector elements (𝐾 𝑔 𝑎𝑐 , 𝐾 𝑔 𝑑𝑐 ) are used to highlight their effect: (-0.3,-0.3), (0,0) and (0.3,0.3). that, when the gain is set to -0.3, the poles of system become negative leading to a second order response. For 0.3 and 0 values, the dynamics of system is a first order response. As it was proved in the theoretical analysis (see equations (IV-41) and (IV-53)), the high dynamics response (one sampling period) is obtained when the gain values are equal to zero.

AC Continuous-Time Model

Control Based on Exact

Sampling period effect

To investigate the performances of the proposed controllers regarding the sampling period value, the following test cases are carried out. The results show that the proposed control can ensure the desired dynamics which is one sampling period response (2 ms). The three phase components highlight disturbances until the direct component has achieved its reference.

Thereafter, to test the performances of the proposed controllers, the sampling period of the control algorithms is decreased. For this purpose, different values have been chosen: 0.1, 0.5 and 1 ms. The event is a step change in active power reference 𝑃 𝑎𝑐 * . Initially set to 0.2 pu, an increased step of 0.1 pu is applied at t= 0.1 s. The obtained results (see Figure show the performances of the proposed control in terms of overshoots and dynamic responses. As the sampling period increases, the response time also increases while the control performances are kept equivalent (same response type).

Comparison with other solution

In this section, the proposed control algorithms are compared with a discrete-time controller based on Euler discrete-time model. For this purpose, two sampling periods (0.5 and 2 ms) have

Offline validation of proposed controllers

After validation of proposed control algorithms on simplified models, in this section, they are incorporated in the whole control system (outer loops + low level control) presented in CHAPTER III, see section 5, to control MMC station represented with the full order detailed model using semi-analytical implementation (see section 4.

Control in normal operation

High dynamics test (Step change of reactive power)

Since the reference of active power is given by DC voltage controller (𝑃𝐼) (see Figure , it is better to test the high dynamics response of the proposed control on the reactive power reference. Initially, the converter is consuming 0.4 (pu) active power (power flows from AC to DC grids) and delivering 0.4 (pu) reactive power. At t=0.5 s, the reactive power reference is reversed from 0.4 to -0.4 pu. A sampling period of 200 µs has been chosen to perform this test.

MMC Station 1

Control

MMC Station 2

Control

AC Grid 1

High Impedance Grounding AC Grid 2

High Impedance Grounding

The Thanks to the proposed controller, the converter changes its reactive power as it is required by the reference in a minimum time (less than 1 ms), the control requires four sampling periods to achieve the applied reference (-0.8 pu). On the other hand, the AC currents follow the references change and converge in four sampling period also (less than1 ms) as it is shown in

Energy reference step

In this section, the time response of energy loop is investigated with the proposed current controllers. For this purpose, at t=1s the reference of energy loop is changed from 1 pu to 0. respectively. It can be noted that, whatever is the control strategy for energy loop, the dynamics of energy loop is well respected in term of response time and overshoot.

Control against external events

In this section, the behavior of the proposed control versus external disturbances is investigated.

Symmetric ac voltage dip

At t=1.5 s, in order to emulate a three phase fault located far from the station, the AC voltage amplitude is decreased by 50% during 100 ms. Before the event, the MMC is sending 0.

Asymmetric ac voltage dip

For asymmetric fault located far from the station, the AC voltage amplitude for two phases is decreased by 50% a t=2s during 100 ms. Initially, the MMC is sending 0.2 pu active power to the DC source and doesn't exchange reactive power with the AC grid. It can be concluded from the previous tests that the proposed control algorithms can reduce the impact of external events such as symmetric and asymmetric faults.

Real-Time simulation

Real-Time (RT) simulation has become a mandatory step in control testing, allowing to demonstrate its performance in conditions close to real life [START_REF] Etxeberria-Otadui | Generalized average modelling of facts for real time simulation in arene[END_REF][START_REF] Ocnasu | Real-time hybrid facility for the study of distributed power generation systems[END_REF][START_REF] Gaztanaga | Real-time analysis of the control structure and management functions of a hybrid microgrid system[END_REF]. Widely used in industry, it provides a mean to test the actual control software running on a dedicated hardware together with a virtual model or a prototype of the plant. This increases the realism of the simulation (real-time execution with real conditions) and provides access to hardware features that are currently not available in offline (non-real time) simulation [START_REF] Gaztanaga | Real-time analysis of the transient response improvement of fixed-speed wind farms by using a reduced-scale statcom prototype[END_REF][START_REF] Guillaud | Applications of real-time simulation technologies in power and energy systems[END_REF].

The real-time simulation has many advantages such as:

 RT simulation presents a good trade-off between traditional simulation and the real system regarding the cost and the time development [START_REF] Gregoire | Hardware-in-the-loop (hil) to reduce the development cost of power electronic converters[END_REF].

 RT simulation combines the benefits of both computer simulation and experimentations to provide reliable testing results with minimum resources [START_REF] Courtecuisse | Use of real time simulation to validate primary frequency control with wind turbine[END_REF].

 RT simulation allows the simulation of some real operation conditions: communication delay, measurement noises…  RT simulation is a safe test, it allows to simulate destructive events without any component damage.

Such simulation tests require high performances software and hardware technologies in order to execute the considered system with a small time-step (less than 20 micro seconds for power electronics and electromagnetic transients). For our specific applications, systems involving CPU with real-time Operating System (OS) and Field-Programmable Gate Array (FPGA) cards are powerful enough to perform the real-time simulations with these requirements. During the simulation time-step, the real-time constraint requires to solve all equations and functions representing the system. When the number of equations and elements representing the system are relatively large or in order to speed up the simulation time-step, it may be necessary to use

Small scale MMC sizing

One of the objectives of the thesis was to size a small scale MMC for SuperGrid Institute realtime platform in order to be used for RCP and Power Hardware in the Loop (PHIL) validations.

Given that there are many possibilities to size a given system, in our case, the main objective was to obtain the same dynamics as a real MMC station with the small scale one.

Number of SMs

Once the input parameters (𝑃 𝑛 , 𝑉 𝑑𝑐 and 𝑉 𝑎𝑐 ) are fixed, the first dimensioning factor that should be defined is the number of SM per arm. Most of existing MMC prototypes are limited in term of number of levels (5 SMs per arm) due to prohibiting development costs [START_REF] Vasiladiotis | Accurate capacitor voltage ripple estimation and current control considerations for grid-connected modular multilevel converters[END_REF][START_REF] Clemow | Lab-scale experimental multilevel modular hvdc converter with temperature controlled cells[END_REF][START_REF] Stankovic | An hvdc experimental platform with mmc and two-level vsc in the back-to-back configuration[END_REF][START_REF] Siemaszko | Implementation and experimental set-up of a modular multilevel converter in a multi terminal dc/ac transmission network[END_REF].

Their operation requires high switching frequency modulation methods in order to obtain an acceptable Total Harmonic Distortion (THD). Since the MMCs in HVDC applications operate with low switching frequency methods, it is necessary to increase the number of SMs in order to be able to work with such modulation strategies. Therefore, a trade-off has to be chosen in order to be representative in term of SMs number and to not increase the development costs.

For this purpose, some offline simulations for different MMC levels using NLC modulation strategy have been carried out. From Figure V-1, it can be observed that with 5 SMs, the THD is relatively high (more than 10%). On another hand, increasing the number of SMs beyond 15 SM does not greatly improve the voltage quality and obviously increases the development cost. Figure V-1 shows that with 10 SMs per arm the obtained THD is less than 5% which is an acceptable value. Based on all this results, 10 SMs value has been chosen as a compromise for our MMC small scale prototype.

SM capacitor

In general, the sizing of the SMs capacitor has to meet two requirements: SM voltages rating and SMs capacitance value. The first requirement is directly calculated based on the DC voltage rating and the selected SMs number. That is:

𝑣 𝐶𝑛 = 𝑉 𝑑𝑐 𝑁 𝑆𝑀 = 400 10 = 40 𝑉 (V-1)
Since our objective is to represent the dynamics of the small scale MMC in a best possible way (the closest to a real MMC), the size of the SM capacitors can be obtained taking into account the ratio between the stored energy inside the SMs (the energy in arm inductances is neglected)

and its nominal power. This parameter is known as electrostatic constant (𝐻 𝑐 ). It has been proved in [START_REF] Jacobson | Vsc-hvdc transmission with cascaded two-level converters[END_REF] that, in order to obtain an averaged ripple of 10%, the electrostatic constant (𝐻 𝑐 ) has to be set between 30-40 ms.

Nsm

According to [START_REF] Ilves | On energy storage requirements in modular multilevel converters[END_REF], the SMs capacitor can be calculated by the following expression:

𝐶 𝑠𝑚 = 𝑁 𝑆𝑀 * 𝑃 𝑛 * 𝐻 𝑐 3 * 𝑉 𝑑𝑐 2 (V-2)
For an electrostatic constant of 40 ms, the SMs capacitor is:

𝐶 𝑠𝑚 = 10 * 6000 * 40 * 10 -3 3 * 400 2 = 5 𝑚𝐹

Arm inductance

The sizing of arm inductance depends on the rise of DC current fault and the circulating current within the legs [START_REF] Tu | Parameter design principle of the arm inductor in modular multilevel converter based hvdc[END_REF]. In our dimensioning, the size of arm inductance has been calculated to be equal to the industrial MMC using per-unit approach. The obtained value is:

𝐿 𝑎𝑟𝑚 (𝑝𝑢) = 0.15 → 𝐿 𝑎𝑟𝑚 (𝑆𝐼) = 𝑉 𝑎𝑐 2 𝑃 𝑛 𝐿 𝑎𝑟𝑚 (𝑝𝑢) 𝑤 𝑛 = 3.44 𝑚𝐻 (V-3)
The same approach is applied to the AC filter, the obtained value is:

𝐿 𝑓 = 0.18 𝑝𝑢 → 𝐿 𝑓 = 4.13 𝑚𝐻 (V-4)

Hardware in the loop (HIL) validation

In this section, an HIL test setup is used to validate the control laws obtained in CHAPTER IV.

This step allows to consider additional real time constraints such as delay and noises before going to RCP validation. In the following, we focus on the results for output MMC currents control (AC and DC currents) only. The results obtained using the control based on internal currents (arm currents) are exactly same.

HIL setup (configuration)

The overview of the HIL platform for testing MMC controls is presented in

Model implementation

In order to satisfy the real-time constraint regarding the execution time, it is necessary to parallelize the computation by separating the electrical system into several subsystems. In generally, the transmission lines and artificial short line "Stubline" allow performing this decoupling. RT-LAB provides specific solver known as Artemis/State Space Nodal (SSN) which derives the Norton equivalents of Matlab/Simulink models by dividing them into branches or groups [START_REF] Dufour | Custom-coded models in the state space nodal solver of artemis[END_REF]. It has been shown in [START_REF] Saad | Real-time simulation of mmcs using cpu and fpga[END_REF] that such method allows to simulate the MMC with 100 SMs with 25 μs time-step.

In the following HIL test, the simulation circuit is the same as the one used through the whole thesis, see

Control implementation

The  Arm current of upper arm for leg (a).

 3*AC grid voltage.

 DC grid voltage.

 DC grid current.

The other SM voltages are communicated to the FPGA card using PCI express as it is shown

in Figure V-3.
It should be pointed that, in addition to one time step delay required for Software in the Loop (SIL) simulation (1 core for model, 1 core for control), the used HIL simulation necessitates one or two additional delays depending on the time-step ratio and FPGA communication type (synchronous or asynchronous).

HIL validation 4.2.1. Start-up sequence

The start-up process is given by the following steps:

 Connect the DC side in order to be able to charge the DC capacitor bus and SMs capacitor simultaneously during the next step (t=𝑡 0 ).

 Close the AC breaker (connect the AC grid) to charge the system (t=𝑡 1 ).

 Bypass the AC pre-insertion resistances (t=𝑡 2 ).

 Activate the MMC control and increase the DC voltage as well as SM voltages to 1 pu (t=𝑡 3 ).

The obtained results for all this process are shown in A zoom on steady state results after control activation is shown in Figure V-6. It can be observed that a small offset appears on reactive power. This offset can be attributed to the delay introduced by the HIL communication. It can be solved with one of the following methods:

 Add an integral term with a small gain to the control law given in equation (IV-37).

 Compensate the offset via the reactive power reference (𝑄 𝑎𝑐 = 𝑄 𝑎𝑐 * -𝑄 𝑎𝑐 𝑜𝑓𝑓𝑠𝑒𝑡 ). (c) The second solution has been chosen in order to keep unchanged the obtained control law and consequently not to change its dynamic response.

High dynamics test

In this test, the reactive power reference is changed from 0.4 pu to -0.4 pu, the active power being set to -0.4 pu. The obtained results (see Figure V-7) show that the direction of reactive power changes as it is required by its reference. The amplifiers used are:  CINERGIA 15 kW: Switching power amplifier in DC control mode to emulate the DC grid.

MMC Station

DC current source AC voltage source

High Level Control Low Level Control

FPGA card CPU

PCIe

MMC Control

Since the DC amplifier is used to emulate the DC grid perturbation (Power control mode), the MMC has to be controlled in DC voltage mode to ensure DC grid stability.

The Opal-RT hardware device (OP4510) is used to implement the control of the MMC station.

Due to the high quantity of data exchanged between the station and its control, the OP4510 device communicates with the station via optical fiber links using FPGA card (Kintex7-TE0741). It receives measurements (arm currents and SM voltages) from sensors and sends the pulse signals for each SM. The OP4510 is also used to send the references to AC and DC amplifiers via analog outputs and Modbus communication respectively (see Figure V-9).

Experimental tests validation

In this section, the same events used for offline validation in the previous chapter (see section 3.4) are applied to the MMC station.

Start-up sequence

In order to start operating the MMC test bench, it is necessary to charge the SM capacitors as well as the DC grid one to their nominal values. For this purpose, the previous start-up process used in HIL validation (see section 4.2.1) is applied to the small scale MMC.

High dynamics test

In the following, the high dynamics response of the proposed control is tested on the reactive power. For a step change of 0.8 pu (from 0.4 to -0.4 pu), the obtained results are shown in It can be observed that the experimental result is slightly different than the simulation one (one time step delay). This difference can be attributed to delay introduced by the AC amplifier on one hand and the parameter errors such as the equivalent resistance of switches. However, the results show a high performances of the proposed control in term of response time (less than 1 ms) and overshoot.

Energy step

It has been shown with offline simulation that, thanks to the high dynamics response of the proposed current controllers, the response time of outer loops such as energy loop can be decreased. In this test, the energy reference is decreased from 1 pu to 0.95 pu, with the energy controller being set to different response time values.

Symmetric AC dip

Asymmetric AC dip

To emulate a 2 phase AC fault located far from the station, a two phase AC voltage dip is applied to the MMC station (50%). The obtained results are presented in that the delay introduced by the loop back leads to a small offset in the reactive power. This latter has been taken in the account in the reference calculation for reactive power in order to

Conclusions

In the recent years, The HVDC has emerged as adequate solution for integration of renewable energy sources coming from wind farm or hydro power stations. Since its innovation, the modular multilevel converter (MMC) topology of VSC has been considered as a promising solution for such application. This thesis has carried out with the context of developing models and control system for this structure.

Before addressing the control and modeling problematics covered by this thesis, the topology of MMC with its operation principle have been presented. This allows to introduce the challenges of modeling and control due to the high number of switching elements and state variables, and clarify the motivation behind this thesis. Even if several research studies have been carried out on this problematic, there still exists many barriers and locks which have not been addressed in exhaustive manner.

The first objective was to remove the ambiguities regarding the implementation of MMC models proposed in the literature. New implementation techniques (analytical and semianalytical) have been applied in order to add new functionalities (blocking capability and operation under endogenous faults conditions) to the MMC models. In addition, these techniques allow to simplify their implementation and reduce the elements constituting the models. The simulation results have shown a good correlation between the proposed models and the benchmark one (detailed model with circuit implementation) for controlled, blocked and faulted states.

The second objective of the present thesis was to investigate the control of the MMC using cascaded control methodology. For a good MMC operation, the low level control has to maintain a voltage balance between SMs within one arm. The average tolerance band method has been improved in order to reduce the switching frequency and impose the desired ripple whatever is the transferred power.

On the base of MMC topology and principle, its state space equations have been derived in order to be used for control purposes. Unlike standard VSCs, the MMC control has to regulate its internal energy in order to ensure the converter operation. Thanks to energy based control structure, the voltage of equivalent arm capacitor can take different value than the DC one. This opens the opportunity to use the MMC as a storage system which can be used as an additional degree of freedom to provide some services such as oscillations damping. This necessitates a fast response time for the energy loop and consequently high dynamics controller for current loops since the cascaded control is based on time scaling principle. A special new control algorithms have been developed to address this issue.

At first, sliding mode control design for continuous-time models has been used to accelerate

Perspectives

To go beyond the work proposed in this thesis, several research topics can be carried out:

• Modeling and control:

• Considering the structural limits à priori in control laws synthesis in order to well drive the dynamics response of MMC currents.

• Applying the proposed methodology regarding modeling and control for other MMC topologies such as Full-Bridge, Double-Clamped, Alternate Arm

• MMC with its environments:

• Including and studying the proposed MMC control with Multi terminal DC grid (MTDC).

• Considering the AC system dynamics especially in case of weak AC grids.

• Investigating the possibility of large buffer storage system inside the MMC for more flexibility and interaction with AC systems.

• Experimental validation:

• Go further in term of control assessment using PHIL tests. La structure du contrôle en cascade basée sur le principe des boucles imbriquées permet de contrôler les variables d'états du system d'une manière découplée. Un tel découplage nécessite un temps de réponse lent pour les boucles extérieures (objectifs de contrôle) afin de maintenir le rapport de temps de réponses entre les boucles. Step change in stored energy reference

Contexte de la thèse

High Level Control

Blocked state tests

Three phase AC fault

Pole to Pole DC fault

Loss of 10% SMs for one arm

Loss of one arm

Validation of proposed averaged models

In this section, the semi analytical as well as the analytical modeling techniques for the equivalent model are compared to the Benchmark model for all MMC states (controlled, blocked and faulted). As for the equivalent model, good correlation between the averaged and Benchmark models results. Step change in stored energy reference Where 𝜔 𝑛 and 𝜁 are, respectively, the natural frequency and the damping ratio. They are calculated based on the desired response time and overshoot: 𝜁 = 0,707 for 5% overshoot

Controlled state tests

Step change in DC power reference

Blocked state tests

Three phase AC fault

Pole to Pole DC fault

Faulted state tests

Loss of 10% SMs for one arm

Loss of one arm

𝜔 𝑛 = 3 𝑡 𝑟 (B-5)
Then, the gains of DC voltage controller are given by:

𝑘

Energy global controller

As a reminder, the state space equation representing the energy global variation is given by the following expression:

𝑑𝑊 𝑚𝑚𝑐 𝑑𝑡 = 𝑃 𝑑𝑐 -𝑃 𝑎𝑐 (B-7)
Where the global energy is defined as follows: It is worth noticing that the block diagram is given in 𝑆𝐼 system. The electrostatic constant needs to be considered when the block diagram is given in 𝑝𝑢 system.

𝑊
It can be observed that the control objective (energy regulation) can be achieved by creating an unbalanced between AC and DC powers. Hence, two strategies can be employed for this purpose:

 DC Control strategy.

 AC Control strategy.

Taking the first case (DC control strategy) as an example, the energy controller has to adjust the DC power reference till the stored energy becomes equal to its reference value. The DC power reference in this case is given by the following expression:

𝑃 𝑑𝑐 * = 𝑃 𝑎𝑐 * + 𝑃 𝑤 * (B-9)
Where 𝑃 𝑊 * represents the output of energy loop controller. When a 𝑃𝐼 regulator is used to derive the energy controller, its gains can be calculated using the transfer function of

Energy leg (sum) controller

As a reminder, the state space equation representing the energy sum variation is given by the following expression where its block diagram is presented in As for the global energy, the energy leg controller can be achieved either with the AC currents or with the DC one. In order to avoid an unbalanced operation conditions, it is better to use the DC current for this purpose.

The equation (B-13) shows that the instantaneous energy leg contains (2𝜔) frequency component. Since the aim is controlling the average value of the stored energy in the leg, it is necessary to eliminate this frequency using a filter (e.g Notch filter).

Once the signal is filtered, the energy leg controller can be derived as follows:

𝑃 𝑤𝑖 Σ * = (𝛥𝑊 𝑖 𝛴 * -〈𝛥𝑊 𝑖 𝛴 〉)𝐶 Σ 𝑤 (𝑠) The tuning of control gains can be obtained using the same approach as before.

Current Control Loop

Filter

Energy difference controller

As a reminder, the state space equation representing the energy difference variation is given by the following expression: The equation (B-15) can be represented with a block diagram as follows: The block diagram in closed loop is then: Where: The model (C-1) offers the possibility to derive the control laws for arm currents by controlling the values of 𝑣 𝑟𝑙𝑖 𝑢 and 𝑣 𝑟𝑙𝑖 𝑙 (input vector).

Exact discrete-time MMC modeling

Discrete-time controllers based on pole placement method

In order to obtain the fastest dynamics for arm currents, a placement pole method is chosen to derive their control laws. Based on the convergence condition given in equation (IV-34), the arm discrete-time controller has to satisfy the following condition:

[

Offline validation

The obtained control laws are tested with the simulation circuit of Figure IV-31. The same parameters with the same events are used in order to be in line with the obtained results in CHAPTER IV, section 3.4.

High dynamics test

Symmetric ac voltage dip

Asymmetric ac voltage dip

XVII 2 . 5 .

 25 Phase locked loop ................................................................................................ Appendix C: High dynamics MMC control based on MMC arm current controllers 3.1. Introduction .......................................................................................................... 3.2. Exact discrete-time MMC modeling .................................................................... 3.3. Discrete-time controllers based on pole placement method ................................ 3.4. Offline validation ................................................................................................. 3.4.1. High dynamics test ....................................................................................... 3.4.2. Symmetric ac voltage dip ............................................................................. 3.4.3. Asymmetric ac voltage dip ...........................................................................

Figure I- 1 :

 1 Figure I-1: HVDC system concept. ..........................................................................................

Figure I- 2 :

 2 Figure I-2: Back-to-back scheme. ............................................................................................

Figure I- 3 :

 3 Figure I-3: Asymmetric monopolar scheme without metallic return. ......................................

Figure I- 4 :

 4 Figure I-4: Asymmetric monopolar scheme with metallic return. ...........................................

Figure I- 5 :

 5 Figure I-5: Symmetric monopolar scheme. ..............................................................................

Figure I- 6 :

 6 Figure I-6: Bipolar scheme without metallic return. ................................................................

Figure I- 7 :

 7 Figure I-7: Bipolar scheme with metallic return. .....................................................................

Figure I- 8 :

 8 Figure I-8: Three phase Line-Commuted Converter (LCC). ...................................................

Figure I- 9 :

 9 Figure I-9: (a) DC voltage waveform, (b) AC current waveform with LCC. ..........................

Figure I- 10 :

 10 Figure I-10: LCC-HVDC station..............................................................................................

Figure I- 11 :

 11 Figure I-11: Three phase Capacitor-Commutated Converter (CCC) .......................................

Figure I- 12 :

 12 Figure I-12: Three-phase 2-level Voltage Souce Converter (VSC). ........................................

Figure I- 13 :

 13 Figure I-13: (a) Requested AC voltage, (b) generated AC voltage with VSC. ........................

Figure I- 14 :

 14 Figure I-14: VSC-HVDC station..............................................................................................

Figure I- 15 :

 15 Figure I-15: Three-phase Modular Multilevel Converter (MMC). ..........................................

Figure I- 16 :

 16 Figure I-16: Operation principle of 5-level MMC. ..................................................................

Figure I- 17 :

 17 Figure I-17: Different states for Half-Bridge SM. ...................................................................

Figure I- 18 :

 18 Figure I-18: Half-Bridge SM including protecting Thyristor and mechanical switch. ............

Figure I- 19 :

 19 Figure I-19: Comparison of features of various SM topologies: (a) Full-Bridge, (b) Clamp-Double, (c) Cross-Connected. ..................................................................................................

Figure I- 20 :

 20 Figure I-20: Hybrid modular multilevel converter (FB+HB) SMs [30]. .................................

Figure I- 21 :

 21 Figure I-21: New hybrid modular multilevel converter (2-level+FB SMs) [32]. ....................

Figure I- 22 :

 22 Figure I-22: Alternative Arm Converter (AAC) [34]. ..............................................................

Figure I- 23 :

 23 Figure I-23: Series bridge converter (SBC) [35]. .....................................................................

Figure II- 1 :

 1 Figure II-1: Physics based model for IGBT [40]. ....................................................................

Figure II- 2 :

 2 Figure II-2: Detailed based models for IGBT: (a) non-linear diodes model, (b) resistances equivalent model. .....................................................................................................................

Figure II- 3 :

 3 Figure II-3: Equivalent Thevenin model for one SM. ..............................................................

Figure II- 4 :

 4 Figure II-4: Reduced averaged arm model. ..............................................................................

Figure II- 5 :

 5 Figure II-5: Reduced averaged leg model. ...............................................................................

Figure II- 6 :

 6 Figure II-6: Phasor MMC model. .............................................................................................

- 7 : 41 Figure II- 8 : 42 Figure II- 9 : 42 Figure II- 10 : 44 Figure II- 11 : 46 Figure II- 12 : 47 Figure II- 13 : 48 Figure II- 14 : 50 Figure II- 15 : 54 Figure II- 19 : 57 Figure II- 20 : 59 Figure II- 21 : 60 Figure II- 22 : 61 Figure II- 23 : 63 Figure II- 24 : 69 Figure II- 28 : 69 Figure II- 29 : 70 Figure II- 30 : 72 Figure II- 36 : 72 Figure II- 37 : 73 Figure II- 38 : 74 Figure III- 1 : 81 Figure III- 5 : 82 Figure III- 6 : 83 Figure III- 7 : 84 Figure III- 8 : 85 Figure III- 9 : 85 Figure III- 10 : 88 Figure III- 14 : 89 Figure III- 15 :

 7418429421044114612471348145015541957205921602261236324692869297030723672377338741815826837848859851088148915 Figure II-7: Summary of different model types for MMC. ...................................................... 41 Figure II-8: Full order detailed models: (a) circuit based model, (b) analytical based model. 42 Figure II-9: SM configurations for controlled states. ............................................................... 42 Figure II-10: Capacitor equivalent circuit: (a) resistive, (b) conductance. .............................. 44 Figure II-11: From detailed to equivalent model. .................................................................... 46 Figure II-12: Full order equivalent model. ............................................................................... 47 Figure II-13: Reduced order averaged arm models: (a) circuit based model, (b) analytical based model. ....................................................................................................................................... 48 Figure II-14: Reduced order averaged model including blocking capability. .......................... 50 Figure II-15: Reduced order averaged arm model: (a) controlled state, (b) blocked state. ..... 51 Figure II-16: SM Configurations including blocked and fault states. ...................................... 52 Figure II-17: Semi-analytical model proposed in [61]. ............................................................ 53 Figure II-18: Semi-analytical model proposed in [64] ............................................................. 54 Figure II-19: Full order detailed model based on semi-analytical modeling technique. .......... 57 Figure II-20: Full order equivalent model based on semi-analytical modeling technique. ...... 59 Figure II-21: Reduced order averaged arm model based on semi-analytical modeling technique. .................................................................................................................................................. 60 Figure II-22: Proposed analytical model. ................................................................................. 61 Figure II-23: Full order detailed model based on analytical modeling technique. .................. 63 Figure II-24: Full order equivalent model based on analytical modeling technique. .............. 65 Figure II-25: Reduced order averaged arm model based on analytical modeling technique. .. 67 Figure II-26: Simulation circuit for models validation. ........................................................... 67 Figure II-27: Dynamics response of detailed models for a DC power step change: (a) active power, (b) DC current, (c) average SM voltages for upper and lower arms for phase a. ........ 69 Figure II-28: Dynamics response of detailed models for a stored energy step change: (a) active power and (b) average SMs voltages for upper and lower arms for phase a. .......................... 69 Figure II-29: Active power dynamics of detailed models for a three phase AC fault. ............ 70 Figure II-30: Arm currents (phase a) dynamics of detailed models for a three phase AC fault. .................................................................................................................................................. 70 Figure II-31: DC current dynamics of detailed models for a three phase AC fault. ................ 71 Figure II-32: Models dynamics of the detailed model for a three phase AC fault: average SMs voltages for upper and lower arm of phase a. .......................................................................... 71 Figure II-33: DC current dynamics of detailed models for a pole-to-pole DC fault. ............... 72

Figure III- 22 :

 22 Figure III-22: SM voltages using ATB algorithm with 1 pu transferred power. .....................

Figure III- 23 :

 23 Figure III-23: (a) Switching frequency, (b) voltage ripple variations regarding transferred power level using ATB algorithm. ......................................................................................................

Figure III- 24 :

 24 Figure III-24: Simplified circuit for one MMC leg. .................................................................

Figure III- 25 :

 25 Figure III-25: Upper and lower voltage loops. .........................................................................

Figure III- 26 :

 26 Figure III-26: MMC equivalent circuit from AC standpoint. ..................................................

Figure III- 27 :

 27 Figure III-27: MMC equivalent circuit from DC standpoint. ..................................................

Figure III- 28 :

 28 Figure III-28: Power exchange inside the MMC. ..................................................................

Figure III- 29 :

 29 Figure III-29: Distribution of stored energy in the MMC. .....................................................

Figure III- 30 :

 30 Figure III-30: Multivariable control diagram for MMC. .......................................................

Figure III- 31 :

 31 Figure III-31: Cascaded control principle. .............................................................................

Figure III- 32 :

 32 Figure III-32: Cascaded control scheme for MMC. ...............................................................

Figure III- 33 :

 33 Figure III-33: Non-energy based control diagram. ................................................................

Figure III- 34 :

 34 Figure III-34: Direct modulation indexes calculation. ...........................................................

Figure III- 35 :

 35 Figure III-35: Non energy based control diagram including CCSC. .....................................

Figure III- 36 :

 36 Figure III-36: Energy based control diagram (first version). .................................................

Figure III- 37 :

 37 Figure III-37: Energy based control diagram (second version). ............................................

Figure III- 38 :

 38 Figure III-38: Schematic diagram for the considered low level control for thesis contributions. ................................................................................................................................................

Figure III- 39 :

 39 Figure III-39: Schematic diagram for the considered high level control for thesis contributions. ................................................................................................................................................

Figure III- 40 :

 40 Figure III-40: Zoom on outer loops configuration. ................................................................

Figure III- 41 :

 41 Figure III-41: Zoom on energy balancing loops configuration. .............................................

Figure IV- 1 :

 1 Figure IV-1: SM voltages variation using ATB algorithm. ...................................................

Figure IV- 2 :

 2 Figure IV-2: (a) Switching frequency, (b) voltage ripple variations regarding transferred power and tolerance band parameter. ................................................................................................

Figure IV- 3 :

 3 Figure IV-3: Proposed improved average tolerance band method diagram. ..........................

Figure IV- 4 :

 4 Figure IV-4: Proposed improved average tolerance band algorithm flowchart. ....................

Figure IV- 5 :

 5 Figure IV-5: Simulation results: (a) SM voltage for one arm, (b) active power. ...................

Figure IV- 6 :

 6 Figure IV-6: A zoom on SM voltages. ...................................................................................

Figure IV- 7 :

 7 Figure IV-7: Simulation circuit for sliding mode control validation. ....................................

- 8 :FigureFigure IV- 13 :Figure IV- 14 :Figure IV- 16 :Figure IV- 17 :Figure IV- 19 :Figure IV- 20 :Figure IV- 27 :Figure IV- 28 :Figure IV- 32 :Figure IV- 34 :Figure IV- 36 :Figure IV- 37 :Figure IV- 38 :Figure IV- 39 :Figure V- 2 :Figure V- 3 :Figure V- 4 :Figure V- 5 :Figure V- 6 :Figure V- 8 :Figure V- 9 :Figure V- 10 :Figure V- 11 :Figure V- 12 :Figure V- 13 :Figure V- 14 :Figure V- 15 :Figure V- 16 :Figure V- 18 :Figure V- 19 :Figure- 1 :Figure- 2 :Figure- 3 :Figure- 4 :Figure- 5 :Figure- 6 :Figure- 7 :Figure- 8 :Figure- 9 :Figure- 10 :

 81314161719202728323436373839234568910111213141516181912345678910 Figure IV-8: Simulation results for active power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ................................................................................................... 131 Figure IV-9: Simulation results for reactive power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ................................................................................................... 132 Figure IV-10: Simulation results for active power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ..................................................................................... 133 Figure IV-11: Simulation results for reactive power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. .............................................. 133 Figure IV-12: Simulation results for active power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=30000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ..................................................................................... 134 Figure IV-13: Simulation results for reactive power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=30000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ............................................................................... 134 Figure IV-14: Simulation results for active power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50, 𝑘𝑝𝑎𝑐=𝑘𝑝𝑑𝑐=3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. .................................................... 139 Figure IV-15: Simulation results for reactive power reference change (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50, 𝑘𝑝𝑎𝑐=𝑘𝑝𝑑𝑐=3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. .................................................... 139 Figure IV-16: Simulation results for active power reference change with T=0.5 ms (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50, 𝑘𝑝𝑎𝑐=𝑘𝑝𝑑𝑐=3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ......... 140 Figure IV-17: Simulation results for reactive power reference change with T=0.5 ms (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50, 𝑘𝑝𝑎𝑐=𝑘𝑝𝑑𝑐=3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ......... 140 Figure IV-18: Simulation results for active power reference change with T=1 ms (𝑘𝑖𝑎𝑐=𝑘𝑖𝑑𝑐=10000, 𝜎=50, 𝑘𝑝𝑎𝑐=𝑘𝑝𝑑𝑐=3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. ......... 141

Chapter 2 :Chapter 3 and chapter 4 :

 24 First, the HVDC configurations are presented with their associated advantages and drawbacks. After that, the main AC/DC converter technologies which are Line-Commuted Converter (LCC) and Voltage Source Converter (VSC) are presented and compared. Finally, the advantage of MMC compared to other VSC topologies are shown in order to understand the motivation behind the focus of the thesis. This chapter deals with the modeling of MMC. In order to well understand this research axis, the problematic related to its dynamics modeling is addressed. After a state of the art based on recent bibliography references, three dynamic models are chosen to address thesis contributions in the field of MMC modeling which are: detailed, equivalent and averaged models. For the considered models, new implementation methods are developed, explained and validated. These two chapters cover the problematic related to the control of MMC. Chapter 3 introduces the MMC control principle and its two main layers. These latter are explained and reviewed based on recent bibliography publications with the conclusion that the energy based control allows to obtain a better control of all MMC variables. The cascaded structure which is based on time scales assumption allows to handle the control objective in a decoupling manner. Such decoupling necessitates slow response time for outer loops (control objectives) in order to maintain the time ratio between the layers. Chapter 4 proposes high dynamics controllers for inner loops in order to accelerate the response time of outer ones.Based on exact discretization of MMC state-space models, two control methods have been used to derive current control laws which are: pole placement method and discrete-time sliding mode control. Offline simulations have demonstrated that the proposed controls present many advantages in terms of performances on one hand and allow to accelerate the outer loops such as energy loop (5 ms) on the other hand.

Figure I- 1 :

 1 Figure I-1: HVDC system concept.

Figure I- 2 .

 2

Figure I- 2 :

 2 Figure I-2: Back-to-back scheme.

Figure I- 3 :

 3 Figure I-3: Asymmetric monopolar scheme without metallic return.

Figure I- 4 :

 4 Figure I-4: Asymmetric monopolar scheme with metallic return.

  scheme a small metallic return (see FigureI-4). The latter, which does not require high-voltage

Figure I- 5 :

 5 Figure I-5: Symmetric monopolar scheme.

Figure I- 6 :

 6 Figure I-6: Bipolar scheme without metallic return.

Figure I- 7 )

 7 Figure I-7), the bipolar scheme ensures that no current is flowing through the ground whatever the operation conditions are.

Figure I- 7 :

 7 Figure I-7: Bipolar scheme with metallic return.

Figure I- 8 :Figure I- 8 .

 88 Figure I-8: Three phase Line-Commuted Converter (LCC).The schematic diagram of basic LCC topology, known as the Graetz Bridge, is illustrated in Figure I-8. Because of thyristor commutation process, only turn-on capability, the commutation process of LCC generates voltage harmonics on the DC grid and current harmonics on the AC grid as it is shown in Figure I-9 .

Figure I- 9 :

 9 Figure I-9: (a) DC voltage waveform, (b) AC current waveform with LCC.

Figure I- 10

 10 Figure I-10).

Figure I- 10 :

 10 Figure I-10: LCC-HVDC station.A typical LCC-HVDC station is presented in Figure I-10. In addition to LCC converter, its main component parts are[START_REF] Blasco-Gimenez | Lcc-hvdc connection of offshore wind farms with reduced filter banks[END_REF]:

Figure I- 11 :

 11 Figure I-11: Three phase Capacitor-Commutated Converter (CCC)

Figure I- 12 :

 12 Figure I-12: Three-phase 2-level Voltage Souce Converter (VSC). The basic configuration of a three-phase two level VSC is presented in Figure I-12. It consists of six valves, each valve consists of a switching device (IGBT) and an anti-parallel freewheeling diode. Thanks to turn-on/ turn-off capabilities of IGBTs, the AC voltage generated by a 2-level VSC is a square wave corresponding to the electrical positive and negative DC voltage (+𝑣 𝑑𝑐 and -𝑣 𝑑𝑐 ).

Figure I- 13

 13 Figure I-13: (a) Requested AC voltage, (b) generated AC voltage with VSC. With a predefined switching strategy such as Pulse-Width Modulation (PWM), it is possible to generate a sinewave AC voltage as it is shown in Figure I-13. To achieve a good voltage quality

Figure I- 14 :

 14 Figure I-14: VSC-HVDC station



  development over the world: INELFE (France-Spain, 2015), south west-link (Sweden-Norway, 2014) and several projects in china… Conceptually, the MMC has the same advantages of standard VSCs and does not have the drawbacks of the multilevel ones. Compared to them, the MMC offers the following advantages: Modularity and the scalability to different power and voltage levels.  Simple capacitor voltage balancing which constitutes the main issue with other multilevel converters.  Thanks to low switching frequency operation, the converter losses are reduced (around 1%).  Ability to deliver a very high voltage with excellent harmonic performance. Thus, filtering requirements are reduced.  High voltage insulation coordination between the capacitors.  Robustness for component failures (high reliability), failure of one SM will not affect the functioning of MMC.  Well management of external degraded modes.

Figure I- 15 :

 15 Figure I-15: Three-phase Modular Multilevel Converter (MMC).

  Figure I-16 explains the previous principle for a 5-levels MMC.

Figure I- 16 :

 16 Figure I-16: Operation principle of 5-level MMC.

Figure I- 17

 17 Figure I-17), it includes two IGBTs with their corresponding free-wheel diodes and one capacitor 𝐶. According to the state of S1 and S2, the SM can takes three different states (see Figure I-17).

Figure I- 17 :

 17 Figure I-17: Different states for Half-Bridge SM.

Figure I- 18 :

 18 Figure I-18: Half-Bridge SM including protecting Thyristor and mechanical switch.

Figure I- 19 :

 19 Figure I-19: Comparison of features of various SM topologies: (a) Full-Bridge, (b) Clamp-Double, (c) Cross-Connected.

Figure I- 20 :

 20 Figure I-20: Hybrid modular multilevel converter (FB+HB) SMs [30]. GE Grid Solution "Alstom Grid" has proposed a series of new converters which combine the advantages of both MMC and 2-level converters. The first proposed version consists of adding to a 2-level VSC a stack of Full-Bridge SMs in the AC line (see Figure I-21) in order to improve the quality of the generated AC voltage [32].

Figure I- 21 :

 21 Figure I-21: New hybrid modular multilevel converter (2-level+FB SMs) [32].

Figure I- 22 :

 22 Figure I-22: Alternative Arm Converter (AAC)[START_REF] Merlin | The alternate arm converter: A new hybrid multilevel converter with dc-fault blocking capability[END_REF].

  (see Figure I-23). Based on a combination of Half-Bridge and Full-Bridge SMs, the number of required SMs is 30-35% reduced compared to an equivalent MMC.

Figure I- 23 :

 23 Figure I-23: Series bridge converter (SBC)[START_REF] Feldman | A hybrid modular multilevel voltage source converter for hvdc power transmission[END_REF].

Introduction

  Power converters are characterized by a variable structure behavior. The development of new conversion systems leads always to new modeling approaches or methodologies. One of the most important issue related to the MMC is concerning its modeling for different reasons: very huge number of state variables (large mathematical dimension), strong coupling of these variables and large set of dynamics behavior. This chapter is dedicated to the MMC modeling aspects. After a state of the art base on recent bibliography references, thesis contributions in the field of MMC general modeling are explained and developed. To finish, the proposed models are implemented, assessed and validated.

  Figure II-2-(a) shows a simplified IGBT model including one ideal switch and two non-linear diodes. The nonlinear behavior of the diodes can be tuned based on manufacturer data sheets or experimental measurements. Since the switch model introduces nonlinear elements, the simulation still takes a long time for a short time event.

Figure II- 2 :

 2 Figure II-2: Detailed based models for IGBT: (a) non-linear diodes model, (b) resistances equivalent model.

(

  milliohms) and 𝑅 𝑜𝑓𝑓 for opened state (megaohms) (see FigureII-2-(b))[START_REF] Selhi | Generalised tlm switch model for power electronics applications[END_REF]. The resistance value depends on the gate signal and arm current direction. Thanks to this simplified model (less elements), the simulation of MMC model is faster than the previous ones.The advantages of full detailed based models are:

Figure II- 3 :

 3 Figure II-3: Equivalent Thevenin model for one SM.

Figure II- 4 .

 4 Figure II-4. The arm inductance remains the same but the capacitors are reduced to an equivalent one. The sources are controlled by an averaged switching function, known as modulation index, which is provided by an upper control level. This averaged model will be analyzed in details after.

Figure II- 4 :

 4 Figure II-4: Reduced averaged arm model.

Figure II- 5 :

 5 Figure II-5: Reduced averaged leg model.

Figure II- 6 :Figure II- 7 :

 67 Figure II-6: Phasor MMC model.

Figure II- 8 :

 8 Figure II-8: Full order detailed models: (a) circuit based model, (b) analytical based model.

Figure II- 9 :

 9 Figure II-9: SM configurations for controlled states.

  voltage. So the arm model can be reduced to a voltage source controlled by an equations system representing the arm equations model as shown in Figure II-8-(b).

Figure II- 10 :

 10 Figure II-10: Capacitor equivalent circuit: (a) resistive, (b) conductance.

Figure II- 12 :

 12 Figure II-12: Full order equivalent model.

  Figure II-13: Reduced order averaged arm models: (a) circuit based model, (b) analytical based model.

  averaged model is obtained as duplicated in Figure II-13. Its implementation can be achieved by using a circuit based model (see Figure II-13-(a)) or by using an analytical based model where only one controlled voltage source is used (see Figure II-13-(b)).

  signals. So diodes have to conduct the arm current for a short time before enabling the protection thyristor (see Figure I-18).

Figure II- 14 :

 14 Figure II-14: Reduced order averaged model including blocking capability.

Figure II- 15 :

 15 Figure II-15: Reduced order averaged arm model: (a) controlled state, (b) blocked state.

Figure II- 16 :

 16 Figure II-16: SM Configurations including blocked and fault states.

  = 𝟏, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟎) 𝑣 𝑠𝑚 ≈ 𝑣 𝑐 𝑖 𝑐 = 𝑖 𝑎𝑟𝑚 Bypassed SM (b) (𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟏, 𝒔 𝒃 = 𝟎) 𝟏 = 𝟎, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟏) 𝑣 𝑠𝑚 ≈ 0 𝑣 𝑐 = 𝑐𝑠𝑡 𝑖 𝑐 = 0

II- 17 )

 17 . The arm circuit is reduced to two controlled voltage sources and two diodes. The controlled source 𝑣 𝑚,𝑐 represents the inserted voltage by the SMs which are in controlled state.On the other hand, the controlled source 𝑣 𝑚,𝑏 represents the inserted voltage by the SMs when the IGBTs are blocked. Since the state variables change the value according to current direction when the blocked state is activated, the two diodes are used to obtain current direction. The analytic part contains the equations that describe the arm. It exchanges information with circuit part by receiving measurements (currents) and sending voltages values to the controlled sources. The inputs and outputs of this bloc change according to the type of models presented in the previous section.

Figure II- 18 :

 18 Figure Semi-analytical model proposed in[START_REF] Li | An equivalent circuit method for modelling and simulation of modular multilevel converters in real-time hil test bench[END_REF]

Faulted/

  Out of order SM(𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟎, 𝒔 𝒃 = 𝟏)

Figure II- 19 by

 19 using three switching variables and 2 measurements.

Figure II- 19 :

 19 Figure II-19: Full order detailed model based on semi-analytical modeling technique.

Figure II- 20 :

 20 Figure II-20: Full order equivalent model based on semi-analytical modeling technique.

Figure II- 21 :

 21 Figure II-21: Reduced order averaged arm model based on semi-analytical modeling technique.

  Another modeling technique based on analytical based implementation can be used to obtain general MMC models. In this solution, only one controlled source is used as a circuit part as it is shown in Figure Theoretically, for the same simulation time-step, decreasing the (switches and sources) in the model will accelerate the simulation time compared to the first solution. On the other hand, the equations system controlling the source has to adapt its output voltage to represent the three states which makes complicated the related equations building. It has been seen in the first solution that the current direction is important when the blocked state is activated. Since there are not switches inside the model using this solution, a new variable indicating current direction is used to derive the analytical equations.

Figure II- 22 :

 22 Figure II-22: Proposed analytical model.

Figure II- 23 :

 23 Figure II-23: Full order detailed model based on analytical modeling technique.

Figure II- 25 :

 25 Figure II-25: Reduced order averaged arm model based on analytical modeling technique.

  Figure II-26: Simulation circuit for models validation.The case study is a point-to-point MMC based HVDC link where the parameters of the stations are presented in Table II-6. These parameters correspond to those available in EMTP-RV MMC

  5 is applied to the DC current source reference. The obtained results are presented in Figure II-27 where the active power, the DC current and the average SM voltages for upper and low arms for a given leg are presented in (a)-(c) respectively. The results show that the three models have the same behavior during transient as well as during the steady state.

Figure II- 27 :

 27 Figure II-27: Dynamics response of detailed models for a DC power step change: (a) active power, (b) DC current, (c) average SM voltages for upper and lower arms for phase a.

Figure II- 28 :

 28 Figure II-28: Dynamics response of detailed models for a stored energy step change: (a) active power and (b) average SMs voltages for upper and lower arms for phase a.

  Figure II-31 for DC current and Figure II-32 for average SM voltages for upper and lower arms.

Figure II- 29 :

 29 Figure II-29: Active power dynamics of detailed models for a three phase AC fault.

Figure II- 30 :Figure II- 31 :

 3031 Figure II-30: Arm currents (phase a) dynamics of detailed models for a three phase AC fault. Regarding the arm currents (see Figure II-30) and DC current (see Figure II-31) dynamics, the blocking activation is well represented with the proposed models. However, for the same reason as before, the convergence of arm currents to zero is a bit different for the analytical model. Moreover, some numerical oscillations can be observed in the steady state value of DC and arm currents. This phenomenon can be explained by the sign function used by the analytical model which is sensitive to the simulation time-step. By decreasing the time step those oscillations become smaller.

Figure II- 32 :

 32 Figure II-32: Models dynamics of the detailed model for a three phase AC fault: average SMs voltages for upper and lower arm of phase a.

  5. The blocking state is activated after 0.5 ms to avoid a big discharge of SM capacitors. The dynamic responses produced by the three models are shown in Figure II-33 for DC current, Figure II-34 for active power, Figure II-35 for average SMs voltages for upper and lower arms and Figure II-36 for arm currents dynamics. When the DC fault occurs, a high increase of DC current, due to the discharge of SMs and AC grid contribution, appears. When the blocking state is activated, the DC current takes a rectifier form with a peak and a steady state values around 12 pu and 8.5 pu respectively. It can be observed from Figure II-33 and Figure II-34 that the whole responses of the three models are quite equal.

Figure II- 34 :

 34 Figure II-34: Active power dynamics of detailed models for a pole-to-pole DC fault. As indicated in Figure II-35, the blocking state allows stopping the SM capacitors discharging through the fault. This phenomenon is well represented with the semi analytical model as well as the analytical one.

Figure II- 35 :

 35 Figure II-35: Average SMs voltages for upper and lower arms dynamics of detailed models for a pole-to-pole DC fault.

Figure II- 36 :

 36 Figure Arm currents dynamics of detailed models for a pole-to-pole DC fault (phase a).

  the models are illustrated in Figure II-37-(a) for the active power and Figure II-37-(b) for average SM voltages for upper and lower arms. Thanks to the energy loops, the control detects this event and reacts by increasing the active power in order to compensate the lack of energy in the arm. It can be observed that the proposed models allow to simulation such transient operations.

Figure II- 37 :

 37 Figure II-37: Dynamics response of detailed models for a loss of 10% SMs in one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

Figure II- 38 :

 38 Figure II-38: Dynamics response of detailed models for a loss of one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

  MMC control mission is to communicate the SMs configuration by sending the pulse signals for SM switches. It means that, the control objectives have to be transferred by the control system to a given arm configuration. To do so, two steps are necessary to calculate the corresponding pulse signals (see Figure III-1):

Figure III- 1 :

 1 Figure III-1: General scheme of MMC control.

  will generate the IGBT control signals to select the appropriate SMs to be inserted in a manner to balance their voltages. The schematic diagram of low level MMC control can be separated in two distinguished parts as it is presented in Figure III-2.

Figure III- 2 :

 2 Figure III-2: Architecture of low level control.

Figure III- 3 :

 3 Figure III-3: Modulation method diagram.

Figure III- 4 :

 4 Figure III-4: Modulation index classification.

Figure III- 5 :

 5 Figure III-5: Multilevel modulation classification.

Figure III- 6 :

 6 Figure III-6: Modulated arm voltage using SHE modulation technique.

Figure III- 6

 6 Figure III-6 shows the inserted arm voltage for six levels MMC. The equation describing the inserted voltage can be expressed as Fourier series by the following equation:

Figure III- 7 :

 7 Figure III-7: Nearest level modulation scheme.

Figure III- 8 :

 8 Figure III-8: Basic BCA flowchart.

Figure III- 9 :

 9 Figure III-9: Voltage ripple ∆𝑉 = ∆𝑉 1 + ∆𝑉 2 , average ripple ∆𝑉 1 and voltage tolerance ∆𝑉 2 .

Figure III- 10 :

 10 Figure III-10: Criteria and choices of balancing control algorithms. Without considering explicitly the operating point (𝑃, 𝑄) and circulation current injection (𝑖 𝑐𝑖𝑟 ≈ 0), it is proposed to classify BCAs in two categories (see Figure III-11): BCAs with frequency mitigation and BCAs with voltage ripple mitigation [75].

Figure III- 12 :

 12 Figure III-12: Reduced switching frequency algorithm flowchart.

- 13 :

 13 Figure III-13: Improved reduced switching frequency algorithm flowchart.

Figure III- 14 :

 14 Figure III-14: Average tolerance band algorithm flowchart.

Figure III- 15 :

 15 Figure III-15: Cell tolerance band algorithm flowchart.

Figure III- 16 .

 16 Figure III-17-(a) and Figure III-17-(b) respectively for different power transfer setpoints. It is observed that the ripple variation is linear regarding the transferred power where the switching frequency doesn't change.

Figure III- 16 :

 16 Figure III-16: SM voltages using Basic BCA with 1 pu transferred power.

Figure

  Figure III-17: (a) Switching frequency, (b) voltage ripple variations regarding transferred power level using Basic BCA.

  Figure III-18, this method operates the MMC with low switching frequency [50-60 Hz] leading to decrease the switching losses (see Figure III-19-(a)). Using MAX and MIN functions decreases also the constraints regarding the computational time for FPGA. On the other hand, the SM voltages are not perfectly balanced and the voltage ripple is four times higher than obtained for Basic BCA. It can cause insulated problem for IGBTs, increase the losses in SM capacitors and reduce the life time of the SMs (see Figure III-19-(b)).

Figure III- 18 :

 18 Figure III-18: SM voltages using RSF-algorithm with 1 pu transferred power.

Figure III- 19 :

 19 Figure III-19: (a) Switching frequency, (b) voltage ripple variations regarding transferred power level using RSF-algorithm.

  Figure III-20). From Figure III-21-(a) it can be seen that this method has the same variation as the previous one in term of switching frequency when the transferred power is lower. The advantage of this method can be observed when the transferred power increases. Thanks to ∆𝑁 𝑂𝑁 = 0 case, the ripple is decreased (see Figure III-21-(b)) to the half and the MMC is still working with low switching frequency 70 𝐻𝑧.

Figure III- 20 :

 20 Figure III-20: SM voltages using IRSF algorithm with 1 pu transferred power.

Figure III- 21 :

 21 Figure III-21: (a) Switching frequency, (b) voltage ripple variations regarding transferred power level using IRSF algorithm.

  Figure III-22 and Figure III-23 respectively. Those results have been obtained with tolerance parameter 𝜀 = ∓5%. Contrary to CTB method which

Figure III- 22 :

 22 Figure III-22: SM voltages using ATB algorithm with 1 pu transferred power.

Figure III- 23 : 4 . 1 .

 2341 Figure III-23: (a) Switching frequency, (b) voltage ripple variations regarding transferred power level using ATB algorithm.

Figure III- 24 :

 24 Figure III-24: Simplified circuit for one MMC leg. By applying Kirchhoff's voltage law to Figure III-24, two voltage loops can be considered as it is duplicated in Figure III-25: one for the upper arm (green loop) and one for the lower part (yellow loop). Their associated equations can be written as:

Figure III- 28 :

 28 Figure III-28: Power exchange inside the MMC.𝑑𝑊 𝑚𝑚𝑐 𝑑𝑡 = 𝑃 𝑑𝑐 -𝑃 𝑎𝑐 -𝑃 𝑙𝑜𝑠𝑠

Figure III- 29 :

 29 Figure III-29: Distribution of stored energy in the MMC.

23 )

 23 By setting the equation (III-23) to none zero value, it is possible to control the difference between the lower and upper arms energy. To do so, an alternative component of 𝑖 𝑖 𝑑𝑐 which is in phase with 𝑣 𝑚𝑖 𝑎𝑐 is injected by energy difference controller. Hence, the first component of equations (III-23) becomes none zero leading to change/ regulate the energy difference between the arms.

Figure III- 30 :

 30 Figure III-30: Multivariable control diagram for MMC.

Figure III- 31 :

 31 Figure III-31: Cascaded control principle.

  The general diagram of MMC cascaded control is duplicated in Figure III-32. Depending to which controllers are considered and how there are connected, two controls schema can be obtained.

Figure III- 32 :

 32 Figure III-32: Cascaded control scheme for MMC.

Figure III- 33 :

 33 Figure III-33: Non-energy based control diagram.

Figure III- 34 :

 34 Figure III-34: Direct modulation indexes calculation.

Figure III- 35 :

 35 Figure III-35: Non energy based control diagram including CCSC.

  the instability problem of MMC control. The outline of the proposed control, known as "Energy based control", is shown in Figure

Figure III- 36 :

 36 Figure III-36: Energy based control diagram (first version).

Figure III- 37 :

 37 Figure III-37: Energy based control diagram (second version).

5 . 1 .

 51 Low level controlIn order to avoid unexpected internal dynamics inside the MMC, the closed loop indirect modulation is used to calculate the modulation index references. The nearest level control constitutes the modulation technique block to be in line with industrial system. When a detailed MMC model is used for control validations, the basic BCA ensures the balancing between the SMs. The schematic diagram of the used low level control is summarized in Figure

Figure III- 38 :

 38 Figure III-38: Schematic diagram for the considered low level control for thesis contributions.

  Figure III-39.

Figure III- 39 :

 39 Figure III-39: Schematic diagram for the considered high level control for thesis contributions.

  controller gains have been calculated to obtain the desired response times shown in Figure III-40. The manner how they are calculated is presented in APPENDICES, section 2.

Figure III- 40 :

 40 Figure III-40: Zoom on outer loops configuration.

Figure III- 41 :

 41 Figure III-41: Zoom on energy balancing loops configuration. In this thesis, energy balancing loops are considered as an intern regulation. It means that their references are set to constant values: 1 pu for energy sum and 0 for energy difference. Their response times have been set four times slower than the energy loop one (see Figure III-41).

  This chapter has been reviewing the problematic related to MMC control. It has been shown that two control layers are necessary to transform the control objectives into signal pulses that are: High level control and Low level control. The low level control has to choose the best arms configuration in order to balance the energy between the arms. The parameters impacting and/or impacted by this control layer have been investigated leading to propose a new classification of different BCAs proposed in the literature.

Figure IV- 2 -

 2 Figure IV-2-(a) and Figure IV-2-(b) show the variation of voltage ripple and switching frequency with tolerance parameters for different power set points.

Figure IV- 2 :

 2 Figure IV-2: (a) Switching frequency, (b) voltage ripple variations regarding transferred power and tolerance band parameter.By setting the tolerance parameter to a constant value, a given ripple and switching frequency are obtained according to the transferred power. From control point of view, we are concerned with the ripple of the voltages and the switching frequency (which have direct impacts on converter operation performances) and not the tolerance band parameter. For this purpose, a

Figure IV- 3 :

 3 Figure IV-3: Proposed improved average tolerance band method diagram.

Figure IV- 4 :

 4 Figure IV-4: Proposed improved average tolerance band algorithm flowchart.

Figure IV- 5

 5 where the SM voltages of upper arm for leg (a) and active power variation are illustrated in (a)-(b) respectively.

Figure IV- 5 :

 5 Figure IV-5: Simulation results: (a) SM voltage for one arm, (b) active power.

  IV-6. It can be observed that the switching frequency of IGBTs changes according to the transferred power level.

Figure IV- 6 :

 6 Figure IV-6: A zoom on SM voltages.

Figure IV- 7 :

 7 Figure IV-7: Simulation circuit for sliding mode control validation.

  At the beginning the gains are set to 10000 which satisfy the condition that has been derived from attractivity equations (see equations (IV-9)). The obtained results are presented in Figure IV-8 for active power step and Figure IV-9 for reactive power one.

Figure IV- 8 :

 8 Figure IV-8: Simulation results for active power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

  step change value: 2 ms for 0.2 pu step change (reactive power step) and 5 ms for 0.5 pu step change (active power step).

Figure IV- 9 :

 9 Figure IV-9: Simulation results for reactive power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 10 :

 10 Figure IV-10: Simulation results for active power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 11 :

 11 Figure IV-11: Simulation results for reactive power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 12 :

 12 Figure IV-12: Simulation results for active power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =30000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 13 :

 13 Figure IV-13: Simulation results for reactive power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =30000, 𝜎=50): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents. The results, presented in Figure IV-12 and Figure IV-13, show that the response time is relatively decreased however the chattering phenomena appears again even with the smooth continuous function.

Figure IV- 14 :

 14 Figure IV-14: Simulation results for active power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50, 𝑘 𝑝 𝑎𝑐 =𝑘 𝑝 𝑑𝑐 =3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 15 :

 15 Figure IV-15: Simulation results for reactive power reference change (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50, 𝑘 𝑝 𝑎𝑐 =𝑘 𝑝 𝑑𝑐 =3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 16 :

 16 Figure IV-16: Simulation results for active power reference change with T=0.5 ms (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50, 𝑘 𝑝 𝑎𝑐 =𝑘 𝑝 𝑑𝑐 =3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 17 :

 17 Figure IV-17: Simulation results for reactive power reference change with T=0.5 ms (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50, 𝑘 𝑝 𝑎𝑐 =𝑘 𝑝 𝑑𝑐 =3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

Figure IV- 18 :Figure IV- 19 :

 1819 Figure IV-18: Simulation results for active power reference change with T=1 ms (𝑘 𝑖 𝑎𝑐 =𝑘 𝑖 𝑑𝑐 =10000, 𝜎=50, 𝑘 𝑝 𝑎𝑐 =𝑘 𝑝 𝑑𝑐 =3200): (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

  obtained discrete-time models as well as the approximated Euler based solution are compared by simulation to the continuous-time models which are considered here as reference test models, see Figure IV-20. The simulation has been carried out in Matlab/Simulink using Dormand-Prince (ode8) solver for continuous model with a fixed time-step (𝑇 𝑠 ) of 1 µs allowing to obtain the most accurate results.

Figure IV- 20 :

 20 Figure IV-20: Simulation circuit for discrete-time models validation.

Figure IV- 21 :

 21 Figure IV-21: AC discrete-time models dynamics with 10 µs: (a) 𝑖 𝑑 𝑎𝑐 , (b) 𝑖 𝑞 𝑎𝑐 variations.As it is observed in Figure IV-21, despite there is a small difference between Euler model and the reference one, no visible difference appears between the three simulated models.

Figure IV- 22 :Figure IV- 23 :

 2223 Figure IV-22: AC discrete-time models dynamics with 50 µs: (a) 𝑖 𝑑 𝑎𝑐 , (b) 𝑖 𝑞 𝑎𝑐 variations.

  Figure IV-24-(b) for 50 µs and Figure IV-24-(c) for 100 µs.

Figure IV- 24 :

 24 Figure IV-24: DC discrete-time models dynamics: 𝑖 𝑎 𝑑𝑐 variation with (a) 10 µs, (b) 50 µs and (c) 100 µs.

Figure IV- 25 :

 25 Figure IV-25: Simulation circuit for discrete-time controller validation.

Figure IV- 26 :

 26 Figure IV-26: Proposed controllers dynamics with different gain values: (a) direct component for AC currents, (B) DC current, (c) quadrature component for AC currents. The corresponding results; direct component of AC currents, DC current and quadrature component of AC currents are presented in Figure IV-26 (a)-(c) respectively. It can be observed

Figure IV- 27 :

 27 Figure IV-27: Proposed controllers dynamics with 2 ms sampling period: (a) direct component for AC currents, (b) quadrature component for AC currents, (c) DC current, (d) three phase AC currents.

6 T

 6 ime (ms) AC currents[pu]

  The first test is to evaluate the AC and DC control laws with 2 ms sampling period to highlight the advantage of the proposed solution. Initially the reference of 𝑃 𝑎𝑐 * is set to 0.2 pu; at t= 10 ms it is increased to 0.6 pu. The corresponding results are presented in Figure IV-27, where the direct component, quadrature component, DC current and three phase AC currents variation are illustrated in (a)-(d) respectively.

Figure IV- 28 :

 28 Figure IV-28: Proposed controllers dynamics with different sampling periods: (a) direct component for AC currents, (b) DC current, (c) quadrature component for AC currents.

  highlight the effects on control dynamics. The gain values have been set to ensure the fastest dynamics (i.e. poles located in the origin). The test case is a step increase of 0.1 pu in active power reference initially set to 0.2 pu.

Figure IV- 29 :

 29 Figure IV-29: Discrete-time controllers performances with 0.5 ms sampling period: (a) direct component for AC currents, (b) DC current, (c) quadrature component for AC currents.

Figure IV- 30 :

 30 Figure IV-30: Discrete-time controllers performances with 2 ms sampling period: (a) direct component for AC currents, (b) DC current, (c) quadrature component for AC currents. The corresponding results are presented in Figure IV-29 for 0.5 ms and Figure IV-30 for 2 ms sampling periods. It can be remarked that the dynamics of the controller derived from Eulermodel is close to the one derived from the exact discrete-time model when the sampling period is 0.5 ms. It means that, by decreasing more and more the sampling period, the dynamics of the two controllers is similar. However, a small sampling period cannot be used since it can interfere with low level control and consequently deteriorated the stability margins.

  1.1). The simulations have been carried out in Matlab/Simulink where its associated circuit is presented in Figure IV-31.

Figure IV- 31 :

 31 Figure IV-31: Simulation circuit for offline control validation.

  simulation results are shown in Figure IV-32, where the active and reactive powers, DC current with DC voltage, AC voltages, AC currents, upper arm currents, lower arm currents and averaged SM voltages for upper and lower arms are illustrated in (a)-(h) respectively.

Figure IV- 32 :

 32 Figure IV-32: Simulation results with 0.2 ms sampling period: (a) active and reactive power, (b) DC current with DC voltage, (c) AC voltages, (d) AC currents, (e) upper arm currents, (f) lower arm currents, (g) average SM voltages for upper arms, (h) average SM voltages for lower arms.

Figure IV- 32 -

 32 Figure IV-32-(a) shows that the control changes rapidly the reactive power direction as it is requested by its reference. This result can be confirmed with AC current and AC voltage waveforms (see Figure IV-32-(d) and Figure IV-32-(c)). Thanks to the proposed control, no overcurrent is produced in the AC currents as well as the arm ones (see Figure IV-32-(e) and Figure IV-32-(f)). However, a small active power drop is observed during transient which could be attributed to the fact that the decoupling between active power and reactive one is related to the Phase Lock Loop (PLL) which will not hold during transient. This variation leads to a small perturbation in the DC current, see Figure IV-32-(b). Due to the high dynamics applied by the

Figure IV- 33

 33 Figure IV-33 Zoom on simulation results with 0.2 ms sampling period: (a) reactive power, (b) AC current phase (a), (b) AC current phase (b), (b) AC current phase (c).

Figure IV- 34 :

 34 Figure IV-34: Reactive power for different controllers with 0.2 ms sampling period: (a) measurement, (b) seen by control. The same event has been tested with 0.5 ms sampling period. The experimental results are illustrated in Figure IV-35. Since the sampling period increases, the difference between the proposed control and Euler based one becomes more and more important. It is also observed that the proposed discrete-time controller has the same response time (1 ms) to achieve the reference whatever is the control sampling period which is not possible using Euler based controller.

Figure IV- 35 :

 35 Figure IV-35: Reactive power for different controllers with 0.5 ms sampling period: (a) measurement, (b) seen by control.

95 pu.Figure IV- 36 :

 9536 Figure IV-36: Simulation results with different energy loop time response (𝛼 𝑊 = 0): (a) MMC energy, (b) active power, (c) DC voltage. The simulation results presented in Figure IV-36 have been obtained with (𝛼 𝑤 = 0) corresponding to AC grid control strategy for energy loop. From these results, it is observed that the energy stored inside the arm decrease as it is requested by energy reference. The response time as well as the overshoot are well respected for all response time values. Since the response time decrease, the impact in the AC grid becomes bigger. The same test case is applied with (𝛼 𝑤 = 1) corresponding to DC grid control strategy for energy regulation. The simulation results with different energy loop response time are shown in Figure IV-37, where the MMC energy, active power and DC voltage are illustrated in (a)-(c)

Figure IV- 37 :

 37 Figure IV-37: Simulation results with different energy loop time response (𝛼 𝑊 = 1): (a) MMC energy, (b) Active power, (c) DC voltage.

  2 pu active power to the DC source and doesn't exchange reactive power with the AC grid. The simulation results are shown in Figure IV-38, where the active with reactive powers, DC current with DC voltage, AC voltages, AC currents, upper arm currents, lower arm currents, average SM voltages for upper arms and average SM voltages for lower arms are presented in (a)-(h) respectively. Thanks to the high dynamics of inner loops, the MMC can increase rapidly its AC current (without any overcurrent in the arms) in order to maintain the same power requested by DC source. Since the current increases, the conduction losses inside the converter increase also leading to a small variation of active power and increasing of capacitor voltages ripple. It can be observed that no perturbations are seeing in the DC grid components (see Figure IV-38-(b)).

Figure IV- 38 :

 38 Figure IV-38: Simulation results for symmetrical AC voltage dip with 0.2 ms sampling period: (a) active and reactive power, (b) DC current with DC voltage, (c) AC voltages, (d) AC currents, (e) upper arm currents, (f) lower arm currents, (g) average SM voltages for upper arms, (h) average SMvoltages for lower arms.

Figure IV- 39 :

 39 Figure IV-39: Simulation results for Asymmetrical AC voltage dip with 0.2 ms sampling period: (a) Active and reactive power, (b) DC current with DC voltage, (c) AC voltages, (d) AC currents, (e) Upper arm currents, (f) lower arm currents, (g) Average SM voltages for upper arms, (h) Average SM voltages for lower arms. The simulation results are presented in Figure IV-39. It can be observed that the proposed current controllers allow maintaining power as requested by the DC current source during and after the event. Despite the unbalance of AC voltages, the AC current controller can balance the resulting AC currents (see Figure IV-39-(c) and Figure IV-39-(d)). As a result, the active as well as reactive powers start oscillating with double frequency of AC grid (see Figure IV-39-(a)). Thanks to the decoupling between the AC and DC grids, the applied event is damped by the stored energy inside the MMC (see Figure IV-39-(g) and Figure IV-39-(h)) and consequently doesn't disturb the DC grid components: current and voltage (see Figure IV-39-(b)).

  chapter, the contributions regarding MMC control have been addressed. First, an improved Average Tolerance Band method has been proposed to reduce the switching frequency of MMC keeping the ripple value close to the desired one. Thereafter, advanced current controllers have been derived for high level control in order to obtain the fastest dynamics response. At the beginning, sliding mode control design based on continuous-time models has been chosen to synthetize the current control laws. It has been proved that the sampling period of control hardware has a major impact on the performances of the obtained controllers which requires its integration a priori in the derivation of control algorithms. Since discrete-time controllers allow such integration, they have been chosen for this purpose.Based on exact discretization, discrete-time models for AC and DC as well as arm currents have been obtained and validated. Next, these discretized models have been used to derive the control laws for current loops using two control methods: pole placement based control and discretetime sliding mode control. It has been demonstrated that the two methods allow to obtain the fastest response with a specific advantage for each method: i.e. integration of implicit structural limitations for sliding mode control and flexibility for pole placement method via the gain tunings. The off-line simulations have shown that the proposed control techniques present many advantages in terms of performances for references tracking in normal operations as well as for external disturbance rejections. Thanks to the high dynamics of the inner controller, the outer loops response time can be accelerated without affecting the stability margin which is mandatory in cascaded control philosophy between two successive layers (inner and outer in our case).Motivated by the quite good performances of the proposed current controllers obtained in offline simulation, it is has been decided to go deeper in the assessment by integrating real-time constraints before validation on experimental set-up. This is the aim of the next chapter .IntroductionWhen new concepts (e.g. control algorithms) are developed and validated with offline simulations, the questions concerning their behavior with a real system arise since many real life situations are not then considered. One way to address these questions is to improve the model by emulating communication delays, including sensor models and measurement noises…. It necessitates in some cases new simulation tools as well as new infrastructures to be as close as possible to the final application on the real system. Hardware in the loop (HIL) and Rapid control prototyping (RCP) are two solutions which help satisfy such requirements. This type of simulation is usually used in the industry to test control algorithms performances and hardware implementation before the commissioning. In this chapter, the main results obtained throughout the thesis are validated using those two techniques involving real-time simulation.

  parallel computing using several CPU/ FPGAs. Different manufacturers propose real-time simulation solutions (hardware and software) such as Speedgoat (MATLAB/Simulink), Opal-RT (eMEGAsim, HYPERSIM), RTDS (RSCad), National Instrument (LabVIEW), Typhoon… In this thesis, the real-time solution proposed by Opal-RT (RT-LAB software with OP4510 target) is chosen to perform the real-time validation.

  The real MMC station parameters are based on the data of INELFE-HVDC project, their values are given in Table V-1. The proposed MMC parameters are calculated based on the following inputs (𝑃 𝑛 = 6𝑘𝑊, 𝑉 𝑑𝑐 = 400𝑉, 𝑉 𝑎𝑐 = 208 𝑉).

Figure V- 1 :

 1 Figure V-1: The variation of voltage THD regarding the number of SMs.

  Figure V-2. The setup includes: the host computer, a real time target (OP4510) and IO communication links: PCI express to communicate between the FPGA card and different cores, DB37 to have access to digital and analog inputs/outputs.

Figure V- 2 :

 2 Figure V-2: Hardware in the loop simulation circuit.Host: Thanks to its user friendly interface, RT-LAB allows to generate C code from a MATLAB/Simulink block diagram, compile and upload it on a dedicated hardware (OP4510 in our case). This process is achieved in 6 steps:

  Figure IV-31. The model used for the MMC converter is the detailed model with semi-analytical implementation where the parameters correspond to the proposed small scale MMC (see Table V-1). For the DC side and in order to have a smoothed DC voltage, a capacitance of 6 mF has been added between the MMC station and the DC current source. The simulation circuit (AC grid, MMC and DC grid) is assigned to run on one core with 20 μs timestep (𝑇𝑠).

  control structure presented in CHAPTER III (see section 5) is used in the following HIL validation. The high level control is assigned to run on one core (different than the one used for the model) with a control sampling period (𝑇) where the low level control is running on a FPGA card with the BCA sampling period (𝑇 𝑏𝑐𝑎 ) (see Figure V-3).

Figure V- 3 :

 3 Figure V-3: Zoom on the HIL configuration.

  Due to the high quantity of data exchanged between the model and its control system(60 pulse signals, 60 SM voltages, 6 arm currents, 3 AC voltages and one DC voltage), only few signals can be communicated via analog communications (16 signals). The send measurements have been chosen in order to obtain a complete loopback HIL test for one arm:  10*SM voltages of upper arm for leg (a).

  Figure V-4 where the active power, reactive power, DC voltage and average SM voltages are presented in (a)-(d) respectively.

Figure V- 4 :

 4 Figure V-4: HIL results for start-up sequence: (a) active power, (b) reactive power, (c) DC grid voltage, (d) average SM voltages for leg (a).The obtained results for DC voltage and average SMs voltage have been compared to the offline simulation ones (see FigureV-5). It can be seen the results are quite similar.

Figure V- 5 :

 5 Figure V-5: Comparison between offline and HIL simulation results for control activation during the start-up process: (a) DC grid voltage, (b) upper arm average SM voltage for leg (a), (c) active power.

Figure V- 6 :

 6 Figure V-6: Zoom on HIL results for start-up sequence: (a) Active power, (b) reactive power, (c) DC grid voltage, (d) average SM voltages for leg (a).

Figure V- 7 :

 7 Figure V-7: HIL simulation results for reactive power step change: (a) active and reactive powers, (b) DC voltage with DC current, (c) AC voltage, (d) AC current, (e) upper average SM voltages, (f) lower average SM voltages.

5 . 2 .

 52 Test bench structureThe experimental setup is presented in Figure V-9. It is composed of MMC rack with two power amplifiers connected in manner to emulate a point to point HVDC link. A capacitor is connected in parallel to emulate the DC cable (see FigureV-9).

Figure V- 9 :

 9 Figure V-9: Experimental test bench setup.



  Puissance+ PCU-3X5000-BC: high bandwidth linear power amplifier to emulate the AC grid.

Figure V- 10 :

 10 Figure V-10: Experimental results for start-up sequence: (a) Active power, (b) reactive power, (c) DC grid voltage, (d) average SM voltages for leg (a).

zoom

  The obtained results are presented in Figure V-10 where the active power, the reactive power, DC grid voltage and the average SM voltages for leg (a) are shown in (a)-(d) respectively. It can be observed that the process is working well without creating any over voltages.

Figure V- 11 .

 11 Figure V-11. It can be observed that the proposed control ensure a high dynamics without any over current in the arms neither on the AC and DC ones.

Figure V- 11 :Figure V- 12 :

 1112 Figure V-11: Experimental results for reactive power step change: (a) active and reactive powers, (b) DC voltage with DC current, (c) AC voltage, (d) AC current, (e) upper arm currents, (f) lower arm currents, (g) upper average SM voltages, (h) lower average SM voltages.The obtained results are compared to the offline ones for reactive power variation (see FigureV-12).

Figure V- 13 :

 13 Figure V-13: Experimental results for energy step change with AC control strategy(𝛼 𝑊 = 0): (a) MMC energy, (b) active power, (c) DC voltage.

Figure V- 14 :

 14 Figure V-14: Experimental results for energy step change with DC control strategy(𝛼 𝑊 = 1): (a) MMC energy, (b) active power, (c) DC voltage. The experimental results are presented in Figure V-13 where the energy is controlled with the AC side and in Figure V-14 where it is controlled with the DC side. For 10 ms response time, the experimental result is compared to the simulation one (see Figure V-15). It can be observed that the two obtained results have the same behavior.

Figure V- 15 :

 15 Figure V-15: Comparison between simulation and experimental results for energy step change withAC control strategy (𝛼 𝑤 = 0).

Figure V- 16 :

 16 Figure V-16: Experimental results for symmetric AC voltage dip (50%): (a) active and reactive powers, (b) DC voltage with DC current, (c) AC current, (d) AC voltage, (e) upper average SM voltages, (f) lower average SM voltages. The results show that the proposed control maintain the same power level during and after the event. The comparison between the experimental and simulation results show that the two results are quite similar (see Figure V-17).

Figure V- 17 :

 17 Figure V-17: Comparison between simulation and experimental results for symmetric AC voltage dip (50%): (a) Active power, (b) reactive power.

  Figure V-18 where the active and reactive powers, DC voltage with DC current, AC current, AC voltage, upper arms average SM voltages and lower arms average SM voltages are shown in (a)-(f)

  Figure V-18: Experimental results for asymmetric AC voltage dip (50%): (a) active and reactive powers, (b) DC voltage with DC current, (c) AC current, (d) AC voltage, (e) upper average SM voltages, (f) lower average SM voltages

  it. The experimental results show good performances of the proposed control and good correlation with the obtained results with offline simulation.

  the response time of current controllers. Even if this control algorithm has shown very good performances in term of dynamic response and robustness, undesired oscillations (known as chattering when using sliding mode technique) have appeared making the choice of this type of control difficult to argue in front of other techniques presented in the literature. This chattering comes from the hypothesis that ideal sliding mode control considers infinite switching (sampling) periods. Therefore, our thoughts went to the necessity to integrate à priori the sampling period in the control design. In addition to the fast dynamics response requirement, it naturally leads to use discrete-time control techniques. To do so, discrete-time model of the MMC is required. In the literature, discrete-time based controllers are often derived using Euler approximation for the continuous-time model discretization. One of the main contributions of the present thesis is the derivation and the use of exact discrete-time model of the MMC. Discrete-time sliding mode control and pole placement method have shown a high dynamics tracking performances for normal operation as well as for external perturbations rejection. This results have been confirmed with real time validations such as hardware in the loop and rapid control prototyping tests.

Figure- 1 :Chapitre 2 :

 12 Figure-1: La structure du convertisseur MMC étudiée dans la thèse

Figure- 2 :

 2 Figure-2: Le modèle semi-analytique proposé pour un bras du MMC.

Figure- 3 :Chapitre 3 :

 33 Figure-3: Le modèle analytique proposé pour un bras du MMC.

Figure- 4 :

 4 Figure-4: Schéma de contrôle retenu pour l'étage supérieur.

Figure- 5 :

 5 Figure-5: Schéma de contrôle retenu pour l'étage inférieur.

Chapitre 4 :

 4 Contributions au control des convertisseurs MMCs Ce chapitre propose des contrôleurs de dynamique élevés pour les boucles internes afin d'accélérer le temps de réponse des boucles externes. Sur la base d'une discrétisation exacte des modèles d'état du MMC, deux méthodes de contrôle ont été utilisées pour synthétiser les lois de contrôle de courants qui sont: le placement de pôles et le contrôle en mode glissement à temps discret. Des simulations ont démontré que les contrôles proposés présentent de nombreux avantages en termes de performances d'une part et permettent d'accélérer les boucles extérieures telles que la boucle d'énergie (5 ms) d'autre part.

Figure- 6 :

 6 Figure-6: Résultats de simulation pour un échelon sur la puissance réactive avec une période d'échantillonnage de 0,2 ms: (a) puissance réactive, (b) courant alternatif dans la phase (a), (c) courant alternatif dans la phase (b), (d) courant alternatif dans la phase (c).

Figure- 7 :

 7 Figure-7: Résultats de simulation pour un échelon sur l'énergie interne du MMC: (a) énergie stockée dans le MMC, (b) la variation de la puissance active, (c) la variation de la tension du bus DC.

Chapitre 5 :

 5 Validation HIL et RCP Le but de ce chapitre est de valider les résultats précédents sur un banc de test. Pour se faire, un MMC à échelle réduit a été dimensionné et développée dans le but d'obtenir la même dynamique qu'un MMC réel. Avant d'aller directement vers les tests expérimentaux, la validation avec des simulations en temps réel (HIL) a permet d'anticiper certaines contraintes telles que les retards et les bruits de mesures. Les résultats expérimentaux ont montré une bonne corrélation avec les résultats obtenus en simulation hors temps réel.

Figure- 8 :

 8 Figure-8: Comparaison entre les résultats de simulation et les résultats expérimentaux pour unéchelon sur l'énergie interne du MMC.

Figure- 9 :

 9 Figure-9: Comparaison entre les résultats de simulation et les résultats expérimentaux pour un creux symétrique de tension AC (50%): (a) la variation de la puissance active, (b) la variation de la puissance réactive.

Figure- 10 :

 10 Figure-10: Comparaison entre les résultats de simulation et les résultats expérimentaux pour un creux asymétrique de tension AC (50%): (a) la variation de la puissance active, (b) la variation de la puissance réactive.

Figure A- 2 :

 2 Figure A-2: Dynamics response of equivalent models for a stored energy step change: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

Figure A- 3 :

 3 Figure A-3: Dynamics response of equivalent models for a three phase AC fault: (a) DC current, (b) active power, (c) lower arm current for phase (a), (d) average SM voltages for upper and lower arms for phase a.

Figure A- 4 :

 4 Figure A-4: Dynamics response of equivalent models for a pole-to-pole DC fault: (a) DC current, (b) active power, (c) average SM voltages for upper and lower arms for phase a.

Figure A- 5 :

 5 Figure A-5: Arm currents dynamics of equivalent models for a pole-to-pole DC fault.

Figure A- 6 :

 6 Figure A-6: Dynamics response of equivalent models for a loss of 10% SMs in one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

  0

Figure A- 7 :

 7 Figure A-7: Dynamics response of equivalent models for a loss of one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

Figure A- 8 :

 8 Figure A-8: Dynamics response of averaged models for a DC power step change: (a) active power, (b) DC current.

Figure A- 9 :

 9 Figure A-9: Dynamics response of averaged models for a stored energy step change: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

Figure A- 10 :

 10 Figure A-10: Dynamics response of averaged models for a three phase AC fault: (a) DC current, (b) active power, (c) upper arm current for phase (a), (d) average SM voltages for upper and lower arms for phase a.

Figure A- 11 :

 11 Figure A-11: Dynamics response of averaged models for a pole-to-pole DC fault: (a) DC current, (b) active power, (c) average SM voltages for upper and lower arms for phase a.

Figure A- 12 :

 12 Figure A-12: Arm currents dynamics of averaged models for a pole-to-pole DC fault.

Figure A- 13 :

 13 Figure A-13: Dynamics response of averaged models for a loss of 10% SMs in one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

  0

Figure A- 14 :

 14 Figure A-14: Dynamics response of averaged models for a loss of one arm: (a) active power, (b) average SM voltages for upper and lower arms for phase a.

  Figure A-16.

Figure A- 16 : 2 (B- 3 )

 1623 Figure A-16: Block diagram of DC voltage control in closed loop. According to Figure A-16, the transfer function describing DC voltage variation regarding its reference is given by:

8 )

 8 Figure A-17.

Figure A- 17 :

 17 Figure A-17: Block diagram for MMC energy equivalent model.

10 )

 10 The block diagram of energy loop in closed loop is presented in Figure A-18.

Figure A- 18 :

 18 Figure A-18: Block diagram of energy control in closed loop.

Figure A- 18 . 2 (B- 11 )

 18211 That is:As before, using pole placement method, the denominator of this transfer function is compared to the desired characteristic equation. After calculation, the gains values are:

Figure A- 19 Figure A- 19 :

 1919 Figure A-19: Block diagram of energy leg (sum) equivalent model.

(B- 14 )

 14 The block diagram of energy leg loop in closed loop is presented in Figure A-20.

Figure A- 20 :

 20 Figure A-20: Block diagram of energy leg (sum) control in closed loop.

Figure A- 21 :

 21 Figure A-21: Block diagram of energy difference equivalent model.

Figure A- 22 :

 22 Figure A-22: Block diagram of energy difference control in closed loop.

Figure A- 23 :-Figure A- 24 :Figure A- 25 :

 232425 Figure A-23: Zoom on reactive power dynamics with 0.2 ms sampling period.

Figure A- 26 :

 26 Figure A-26: Simulation results for symmetrical AC voltage dip with 0.2 ms sampling period: (a) active and reactive power, (b) DC current with DC voltage, (c) AC voltages, (d) AC currents, (e) upper arm currents, (f) lower arm currents, (g) average SM voltages for upper arms, (h) average SMvoltages for lower arms.

Figure A- 27 :

 27 Figure A-27: Simulation results for asymmetrical AC voltage dip with 0.2 ms sampling period: (a) active and reactive power, (b) DC current with DC voltage, (c) AC voltages, (d) AC currents, (e) upper arm currents, (f) lower arm currents, (g) average SM voltages for upper arms, (h) average SM voltages for lower arms

  , the Modular Multilevel Converter (MMC) has gained more and more importance for different applications, particularly for High Voltage Direct Current (HVDC). This topology,

firstly proposed by Lesnicar and Marquardt in 2003, has many advantages compared to other Voltage Source Converter (VSC) topologies. As the name suggests, the topology is modular and easily scalable in terms of voltage levels: excellent AC output voltage and DC voltage can be easily increased by adding new cells. Moreover, thanks to the redundant cells, the MMC can also manage its internal degraded modes which are important technical and economic issues.

The development of a complex structure such as the MMC, requires a detailed analysis of its state variables and a depth understanding of its behavior when integrated. This necessitates developments of accurate models (detailed and/or simplified) and performant control systems.

In 2014, when this work has started, many studies from academia as well as industry involving modeling and control of Modular Multilevel Converter have been carried out. In this thesis, these two aspects have been reviewed, analyzed and improved by proposing new models based on several implementation methods, in addition to develop innovative control algorithms in order to fulfill industrial requests by allowing fast MMC dynamics. Real time simulation as well as experimental tests have been carried out to validate our findings.

XXXI

Résumé

La compréhension commune aujourd'hui est que les défis pour développer le réseau SuperGrid sont énormes et à plusieurs niveaux (p. Ex.: Politique, sociale, économique, financier, scientifique, technique ...). Il est également admis que le réseau SuperGrid nécessitera de nouvelles technologies (disjoncteurs, câbles, convertisseurs ...) et de nouveaux principes de fonctionnement (p. Ex.: transition d'un système d'alimentation passif essentiellement à base d'un réseau alternative (AC) à un système plus actif à base d'un réseau hybride alternative/continue (AC/DC)). Cette thèse porte sur la modélisation et le contrôle d'un élément clé pour les réseaux SuperGrid qui est le convertisseur AC / DC. Récemment, et pour beaucoup d'application telle que le transport d'électricité en courant continu à très haute tension (HVDC), le Convertisseur Modulaire Multiniveau (MMC) semble devenir un élément incontournable. Cette topologie, proposée par Lesnicar et Marquardt en 2003, présente de nombreux avantages par rapport aux autres topologies de convertisseur à source de tension (VSC). Comme son nom l'indique, cette topologie est modulaire et facilement évolutive en termes de niveaux de tension: une excellente qualité de tension alternative en sortie et une tension continue qui peut être augmentée facilement en ajoutant des cellules en série. De plus, grâce aux cellules redondantes, le MMC peut également gérer ses modes dégradés internes qui peuvent donner lieu à des problèmes (techniques et économiques) importants. Le développement d'une structure complexe telle que le MMC nécessite une analyse détaillée de ses variables d'état et une compréhension approfondie de son comportement avant son intégration. Cela nécessite des développements de modèles précis (détaillés et/ou simplifiés) et des systèmes de contrôle performants. En 2014, lorsque ce travail a débuté, une analyse de l'état de l'art des recherches et études menées par des chercheurs universitaires et industriels impliquant la modélisation et le contrôle-commande des MMC a été réalisée. Dans cette thèse, ces deux aspects principaux ont été revus, analysés et améliorés. D'abord en proposant de nouveaux modèles et méthodes de mise en oeuvre, ensuite en développant des algorithmes innovants pour répondre aux demandes industrielles permettant une dynamique rapide pour le MMC. Des simulations en temps réel ainsi que des tests expérimentaux ont été réalisés pour valider ces résultats obtenus.

  Thanks to its scalability, performance and efficiency, this topology is considered as the most promising solution for AC/DC converter for HVDC applications.

	This thesis deals with the development of models and associated controls of MMCs. The large
	number of switching elements and state variables inside of the MMC introduce modelling
	challenges especially when implemented in electromagnetic transient (EMT) programs for
	simulation purpose. Moreover, the control system for this structure is a bit different than other
	VSC topologies, since the storage management is not the same, which necessitates a special
	attention. More specifically, this thesis investigates these two aspects in order to well
	understand these challenges and propose new solutions.

It is therefore necessary to look for an optimum transmission solution (economical, technical, financial…) to meet all these needs. High Voltage Direct Current (HVDC) based on Voltage Source Converter (VSC) technology has broadly appeared as a good solution to answer this question. Several HVDC projects have been developed or currently planned around the world: Trans Bay Cable, (USA), INELFE (France-Spain), Rio Madeira (Brazil), Nanao multi-terminal VSC-HVDC (China)…This will lead to the development of meshed grids including Multi terminal DC grid (MTDC) which opens an opportunity for hybrid AC/DC transmission systems. For this purpose, new operation philosophies as well as sophisticated equipments to operate such new transmission systems are more and more required. Considerable research are carried out today to meet these needs such as:  Define new DC grid code.  Investigate the interaction between AC and DC grids.  Develop new equipment: cables, breakers, power converters, surge-arresters… One of the key actors for HVDC technology development is the AC/DC converter. Various VSC topologies, including two-level, three-level and floating capacitor converters have been proposed in the literature. For further improvements of power quality and reliability, the Modular Multilevel Converter (MMC) has been gathering considerable attention since its invention. The first contribution of this thesis is the development of new models (full order and reduced order), based on different implementation techniques. The obtained models allow to reduce the switching elements leading to facilitate their implementation in EMT programs and, hence, accelerate the simulations. The second contribution is to propose new control algorithms for current controllers. Two methods have been used to derive their control laws which allow to obtain the fastest response time.

  The obtained results in this thesis are mainly derived from theoretical analysis of the considered converter topology (MMC based on Half-Bridge Sub-Modules). This is achieved by, first, deriving different analytical expressions for several model types. After that, the simplified models are used to perform theoretical analysis of MMC operation which leads to propose new control algorithms. The obtained results, in term of modeling and control, are then validated either by offline/Real-time simulations or by experimental tests.

Chapter 5 :

 5 The aim of this chapter is to validate the previous results on real time simulation test bench. Before going to Rapid Control Prototyping (RCP) test, Hardware in the Loop (HIL) validation is used to anticipate some constrains such as measurements delay and noises. Small

scale MMC has been sized in order to have the same dynamics as a real MMC which will be used for the RCP test. The experimental results show a good correlation with simulation ones.

Table I

 I

		-1: Comparison of features of various SM topologies.
	SM topology	Output voltage level	DC fault blocking capability	Losses
	Half-Bridge	0, 𝑣 𝑐	No	Low
	Full-Bridge	-𝑣 𝑐 ,0, 𝑣 𝑐	Yes	High
	Clamp-Double	-𝑣 𝑐 ,0, 𝑣 𝑐 , 2𝑣 𝑐	Yes	Medium
	Cross-Connected	-2𝑣 𝑐 , -𝑣 𝑐 ,0, 𝑣 𝑐 , 2𝑣 𝑐	Yes	Medium

Table II -

 II 1: Model categories for power converters.

Simulation speed Fast Slow Physics Non- linear diodes resistance model Thevenin / Norton arm Leg converter Phasor Model Detailed (switch) Equivalent (SM) Reduced order averaged models Full order models

	, it can be given as a
	circuit based model, see Figure II-8-(a). This modeling technique offers a high accuracy since
	the switches are explicitly represented, however, it introduces a high number of electrical nodes
	which makes the simulation too slow. Consequently, it is preferred to derive the equations
	system for this model type by exploiting its topology in order to obtain its analytical based
	model. As it can be observed in Figure II-8-(b), the analytical based model is more compact
	and introduces less electrical nodes in the arm compared to its circuit based model.

Table II -2: State variables for SM in controlled states. Switches states State variables

 II

	Inserted SM	𝑣 𝑠𝑚 ≈ 𝑣 𝐶
	( 𝒔 𝟏 = 𝟏, 𝒔 𝟐 = 𝟎)	𝑖 𝐶 = 𝑖 𝑎𝑟𝑚
	Bypassed SM	𝑣 𝑠𝑚 ≈ 0
		𝑣 𝐶 = 𝑐𝑠𝑡
	( 𝒔 𝟏 = 𝟎, 𝒔 𝟐 = 𝟏)	𝑖 𝐶 = 0
	The equations describing the SM state variables can be derived using one switching function
	as follow.

Full Order Detailed Models Analytical Based Model + Equations System Arm Topology Circuit Based Model (a) (b)

	𝑣 𝐶 =	1 𝐶	∫ 𝑖 𝑎𝑟𝑚 𝑢 𝐶
			(II-1)
	𝑣 𝑠𝑚 = 𝑅 𝑜𝑛 𝑖 𝑎𝑟𝑚 + 𝑣 𝐶 𝑢 𝐶

Trapezoidal integration method Thevenin's theorem A

  straightforward way to implement this arm model in EMT programs is to use an analytical based model (see Figure II-12). It can be observed that, by using an analytical based model, the EM and DM are quite equivalent.

			+	+
			2, … 𝑁
	𝑅 𝑗1 = 𝑅 𝑜𝑛 𝑢 𝑐𝑗 + 𝑅 𝑜𝑓𝑓 𝑢 𝑐𝑗 ̅̅̅̅
	𝑅 𝑗2 = 𝑅 𝑜𝑓𝑓 𝑢 𝑐𝑗 + 𝑅 𝑜𝑛 𝑢 𝑐𝑗 ̅̅̅̅
	𝑖 𝐶𝑗 = 𝑖 𝑎𝑟𝑚 (𝑡 -𝑇 𝑠 ) 𝑢 𝑐𝑗
	𝑅 𝐶𝑗 =	𝑇 𝑠 2𝐶 𝑗
	𝑣 𝐶𝑗 = 𝑣 𝐶𝑒𝑞𝑗 (𝑡) = 𝑅 𝐶𝑗 𝑖 𝐶𝑗 + 𝑣 𝐶𝑒𝑞𝑗 (𝑡 -𝑇 𝑠 )
			𝑁	(II-6)
	𝑣 𝐶Σ = ∑ 𝑣 𝐶𝑗
			𝑗=1
	𝑅 𝑒𝑞𝑗 𝑡ℎ =	𝑅 𝑗2 (𝑅 𝑗1 + 𝑅 𝐶𝑗 ) 𝑅 𝑗2 + 𝑅 𝑗1 + 𝑅 𝐶𝑗
	𝑣 𝑒𝑞𝑗 𝑡ℎ = 𝑣 𝐶𝑗	𝑅 𝑗2 𝑅 𝑗2 + 𝑅 𝑗1 + 𝑅 𝐶𝑗
	𝑁
	𝑣 𝑚 = ∑(𝑅 𝑒𝑞𝑗 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞𝑗 𝑡ℎ )
	𝑗=1

Full Order Equivalent Model Analytical Based Model + Equations System Arm Topology

	𝐶	𝑑𝑣 𝐶𝛴 𝑑𝑡	= 𝐶	𝑑𝑣 𝐶1 𝑑𝑡	+ 𝐶	𝑑𝑣 𝐶2 𝑑𝑡	+ ⋯ + 𝐶	𝑑𝑣 𝑐 𝑁 𝑑𝑡
		𝐶	𝑑𝑣 𝐶𝛴 𝑑𝑡	= 𝑖 𝐶1 + 𝑖 𝐶2 + ⋯ + 𝑖 𝐶𝑁
					𝐶	𝑑𝑡 𝑑𝑣 𝐶𝛴	= 𝑛 𝑖 𝑎𝑟𝑚	(II-8)
		𝐶 𝑁	𝑑𝑣 𝐶𝛴 𝑑𝑡	= 𝑖 𝑎𝑟𝑚	𝑛 𝑁	= 𝑖 𝑎𝑟𝑚 𝑚

Table II -

 II

3: State variables for SM configurations including controlled, blocked and faulted states.

  [START_REF] Persson | Hvdc capacitor commutated converters in weak networks[END_REF] The inserted SM voltage can be derived using the equivalent Thevenin circuit (one voltage source in series with impedance).

	Arm Topology	𝑣 𝑒𝑞𝑗 𝑡ℎ = 𝑣 𝐶𝑗	Semi-Analytical Based Model 𝑅 𝑗2 + 𝑅 𝑗1 + 𝑅 𝐶𝑗 𝑅 𝑗2
				𝑁
	𝑅 𝑒𝑞 𝑣 𝑚,𝑐 = ∑(𝑅 𝑒𝑞𝑗 𝑅 2 (𝑅 1 + 𝑅 𝑐 ) 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞𝑗 𝑡ℎ ) 𝑢 𝑏𝑗 ̅̅̅̅ 𝑢 𝑓𝑗 ̅̅̅̅ 𝑡ℎ = 𝑅 2 + 𝑅 1 + 𝑅 𝑐 𝑗=1	Equations System
	+ 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞𝑗 𝑡ℎ = 𝑣 𝐶 𝑣 𝑒𝑞 𝑁 𝑅 2 𝑣 𝑚,𝑏 = ∑(𝑅 𝑒𝑞𝑗 𝑡ℎ ) 𝑢 𝑏𝑗 𝑢 𝑓𝑗 ̅̅̅̅ 𝑅 2 + 𝑅 1 + 𝑅 𝑐 𝑗=1
						Full Order	+
		Detailed Model 𝑣 𝑠𝑚 𝑐 = (𝑅 𝑒𝑞 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞 𝑡ℎ ) 𝑢 𝑏 ̅̅̅ 𝑢 𝑓 ̅̅̅
	𝑣 𝑠𝑚 𝑏 = (𝑅 𝑒𝑞 𝑡ℎ 𝑖 𝑎𝑟𝑚 + 𝑣 𝑒𝑞 𝑡ℎ ) 𝑢 𝑏 𝑢 𝑓 ̅̅̅
	𝑏𝑗 ̅̅̅̅ +	|𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 |	𝑢 𝑏𝑗 ) + 𝑅 𝑜𝑓𝑓 (𝑢 𝑐𝑗 ̅̅̅̅ 𝑢 𝑏𝑗 ̅̅̅̅ + (1 -	|𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 |	) 𝑢 𝑏𝑗 )) 𝑢 𝑓𝑗 ̅̅̅̅
	𝑅 𝑗2 = (𝑅 𝑜𝑓𝑓 (𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ +	|𝑖 𝐶 | |𝑖 𝑎𝑟𝑚 |	𝑢 𝑏𝑗 ) + 𝑅 𝑜𝑛 (𝑢 𝑐𝑗 ̅̅̅̅ 𝑢 𝑏𝑗 ̅̅̅̅ + (1 -	|𝑖 𝑐 | |𝑖 𝑎𝑟𝑚 |	) 𝑢 𝑏𝑗 )) 𝑢 𝑓𝑗 ̅̅̅̅
						𝑅 𝐶𝑗 =	𝑇 𝑠 2 𝐶 𝑗
						(II-15)
						𝑁
						𝐶 Σ = ∑ 𝐶 𝑗 𝑢 𝑓𝑗 ̅̅̅̅
						𝑗=1
						𝑁
					𝑣 𝐶Σ = ∑ 𝑣 𝐶𝑗 𝑢 𝑓𝑗 ̅̅̅̅
						𝑗=1
				𝑅 𝑒𝑞𝑗 𝑡ℎ =	𝑅 𝑗2 (𝑅 𝑗1 + 𝑅 𝐶𝑗 ) 𝑅 𝑗2 + 𝑅 𝑗1 + 𝑅 𝐶𝑗

(II-

[START_REF] Barnes | Voltage source converter hvdc links-the state of the art and issues going forward[END_REF]

When all SMs are considered, the modulated voltage inserted per arm can be obtained with the following equations system. 𝑓𝑜𝑟 𝑗 = 1,2, … 𝑁 𝑅 𝑗1 = (𝑅 𝑜𝑛 (𝑢 𝑐𝑗 𝑢 𝑖 𝐶𝑗 = (𝑖 𝑎𝑟𝑚 (𝑡 -𝑇 𝑠 ) 𝑢 𝑐𝑗 𝑢 𝑏𝑗 ̅̅̅̅ + 𝑖 𝐶 (𝑡 -𝑇 𝑠 ) 𝑢 𝑏𝑗 ) 𝑢 𝑓𝑗 ̅̅̅̅ 𝑣 𝐶𝑗 = 𝑣 𝐶𝑒𝑞𝑗 (𝑡) = 𝑅 𝐶𝑗 𝑖 𝐶𝑗 + 𝑣 𝐶𝑒𝑞𝑗 (𝑡 -𝑇 𝑠 )

Table II -

 II

5: Switching functions used for analytical modeling technique.

Table II -

 II 6: MMC station parameters for models validation.

Nominal power [MW]

1000

AC

nominal voltage 𝒗 𝒂𝒄 [kV] 320 (rms line to line) DC nominal voltage 𝒗 𝒅𝒄 [kV] 640 (pole to pole) Number of SM 40 Inductance of the grid reactor 𝑳 𝒇 [pu] 0.18 Resistance of the grid reactor 𝑹 𝒇 [pu] 0.005 Arm resistance 𝑹 𝒂𝒓𝒎 [pu] 0.01 Arm inductance 𝑳 𝒂𝒓𝒎 [pu] 0.15 Electrostatic Constant 𝑯 𝒄 (ms) 0.04 Capacitor Cable 𝑪 𝒅𝒄 [µF] 48.4

Table II -

 II

		Detailed Model	Equivalent Model	Averaged Model
	Number of SM	400	100	40	400 100	40	400	100	40
	Benchmark	2100 s 308 s 160 s	/	/	/	/	/	/
	(Circuit) model
	Semi-analytical	87 s	38 s	18 s	85 s 33 s	17 s	12 s 12 s 12 s
	Analytical	70 s	24 s	15 s	69 s 22 s	15 s	9 s	9 s	9 s

7: Simulation time of MMC models for 1 s effective time.

  1 , 𝛼 2 … 𝛼 5 ), the fundamental output voltage as well as harmonics can be mastered. The number of harmonics that can be eliminate depends on the

	2
	0
	0	0.005	0.01	0.015	0.02

MMC level. For example, four harmonics (5 th , 7 th , 11 th , and 13 th ) can be eliminated by controlling the switching angles of Figure

Average ripple Circulating Current Switching Frequency SMs Ripple SMs Ripple Switching Frequency SMs Ripple Switching Frequency Conducting Losses High Level Control BCA Objective Exchanged Powers BCA

	Figure III-11: Balancing control algorithms classification.

Table III -

 III 1: Simulation results for discussed BCA methods with 1 pu power exchange.

	BCA Methods	Basic BCA	RSF	IRSF	ATB
	Ripple for the
	worst individual submodule (peak	9.65	40	22	17.3
	to peak) (%)
		mean	974	56	71	185
	Switching
	frequency	max	983	67	80	215
	(Hz)
		min	968	53	68	173
	Sorting frequency (Hz)	Each BCA cycle (10kHz)	Max and (10kHz) Min Each BCA cycle	Max and (10kHz) Min Each BCA cycle	200

  The equation (III-10) can be represented with the following equivalent circuit (see Figure, it illustrates how the MMC looks like from the standpoint of AC grid. It can be concluded from Figure III-26 that, the half of the difference between the lower and upper arm voltages creates a modulated AC voltage 𝑣 𝑚𝑖 𝑎𝑐 . By controlling 𝑣 𝑚𝑖 𝑎𝑐 , it is possible to control the exchanged powers (AC current 𝑖 𝑖 𝑎𝑐 ) between the MMC and the AC grid. Like standard VSCs, the active and reactive powers can be mastered by controlling, respectively, the phase shift and amplitude of 𝑣 𝑚𝑖 𝑎𝑐 compared to 𝑣 𝑖 𝑎𝑐 . The equation (III-10) can be arranged as follow.It can be observed that, according to the chosen direction for arm currents, the sum of arm currents is a current which flows between the MMC leg and DC grid (DC component). Equation (III-12) can be arranged as follow by introducing new variables.Equation (III-13) shows how the MMC behaves from the standpoint of DC grid. By controlling the modulated DC voltage 𝑣 𝑚𝑖 𝑑𝑐 created by the MMC, the exchanged power between the MMC and the DC grid (DC current 𝑖 𝑖 𝑑𝑐 ) can be mastered.

	MMC leg
				AC Equivalent
				Circuit
		Figure III-26: MMC equivalent circuit from AC standpoint.
		Figure III-27: MMC equivalent circuit from DC standpoint.
	Where:	𝑣 𝑚𝑖 𝑎𝑐 -𝑣 𝑖 𝑎𝑐 = 𝑅 𝑒𝑞 𝑎𝑐 𝑖 𝑖 𝑎𝑐 + 𝐿 𝑒𝑞 𝑣 𝑑𝑐 -𝑣 𝑚𝑖 𝑑𝑐 = 𝑅 𝑒𝑞 𝑑𝑐 𝑖 𝑖 𝑑𝑐 + 𝐿 𝑒𝑞 𝑑𝑐 𝑑𝑖 𝑖 𝑎𝑐 𝑑𝑐 𝑑𝑡 𝑎𝑐 𝑑𝑖 𝑖 𝑑𝑡	(III-13) (III-11)
	Where:	𝑣 𝑚𝑖 𝑑𝑐 = 𝑣 𝑚𝑖 𝑢 + 𝑣 𝑚𝑖 𝑙
	𝑣 𝑚𝑖 𝑙 -𝑣 𝑚𝑖 𝑢 + 𝐿 𝑎𝑟𝑚 ( 𝑑𝑖 𝑖 𝑙 𝑑𝑡 Taking into account equation (III-6) and dividing the equation (III-9) in two lead to obtain the -𝑑𝑖 𝑖 𝑢 𝑑𝑡 ) + 𝑅 𝑎𝑟𝑚 (𝑖 𝑖 𝑙 -𝑖 𝑖 𝑢 ) = 2 (𝑣 𝑖 𝑎𝑐 + 𝑅 𝑓 𝑖 𝑖 𝑎𝑐 + 𝐿 𝑓 𝑑𝑖 𝑖 𝑣 𝑚𝑖 𝑎𝑐 = 𝑣 𝑚𝑖 𝑙 -𝑣 𝑚𝑖 𝑢 2 𝑖 𝑖 𝑖 𝑖 𝑢 𝑙 + 𝑖 𝑖 𝑑𝑐 = 2 𝑎𝑐 𝑑𝑡 ) (III-9) 𝑅 𝑒𝑞 𝑅 𝑎𝑟𝑚 𝑅 𝑒𝑞 𝑑𝑐 = 2 𝑅 𝑎𝑟𝑚 𝑎𝑐 = 𝑅 𝑓 + 2 𝐿 𝑒𝑞 2 𝑎𝑐 = 𝐿 𝑓 + 𝐿 𝑎𝑟𝑚 𝐿 𝑒𝑞 𝑑𝑐 = 2 𝐿 𝑎𝑟𝑚
	following equation.
	4.1.2.	DC power equation
	𝑣 𝑚𝑖 𝑙 -𝑣 𝑚𝑖 𝑢 2 On the other hand, subtracting the upper and lower parts of model (III-5) leads to obtain the -𝑣 𝑖 𝑎𝑐 = (𝑅 𝑓 + 𝑅 𝑎𝑟𝑚 2 ) 𝑖 𝑖 𝑎𝑐 + (𝐿 𝑓 + 𝐿 𝑎𝑟𝑚 2 ) 𝑎𝑐 𝑑𝑖 𝑖 𝑑𝑡 (III-10)
	following equation where all the AC components are eliminated. Its equivalent circuit is
	illustrated in Figure III-27.
	𝑣 𝑑𝑐 -(𝑣 𝑚𝑖 𝑢 + 𝑣 𝑚𝑖 𝑙 ) -𝐿 𝑎𝑟𝑚	𝑑 𝑑𝑡	(𝑖 𝑖 𝑙 + 𝑖 𝑖 𝑢 ) + 𝑅 𝑎𝑟𝑚 (𝑖 𝑖 𝑙 + 𝑖 𝑖 𝑢 ) = 0	(III-12)

  Under steady state operation, 𝑣 𝑚𝑖 𝑑𝑐 and 𝑖 𝑖 𝑑𝑐 have a constant value while 𝑣 𝑚𝑖 𝑎𝑐 and 𝑖 𝑖 𝑎𝑐 have a sinusoidal waveform with same frequency. It can be concluded from equations (III-19) that, the averaged arms energy can be changed by creating unbalance between AC and DC powers (first two components) in one period. The two last components cannot change the average arms energy during one period, however, they introduce a ripple in the instantaneous upper and lower arms energy with opposite direction.

		2𝜋 0		𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐 2	-𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑑𝑐 +	𝑣 𝑚𝑖 𝑑𝑐 2	𝑎𝑐 𝑖 𝑖 2
	〈𝛥𝑊 𝑖 𝑙 〉 = ∫ 𝑃 𝑚𝑖 𝑙 2𝜋 0	= ∫ 0 2𝜋	𝑣 𝑚𝑖 𝑑𝑐 2	𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐 2	+ 𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑑𝑐 -	2 𝑣 𝑚𝑖 𝑑𝑐	2 𝑖 𝑖 𝑎𝑐	(III-19)
	one leg.		(𝑊 𝑖 Σ = 𝑊 𝑖 𝑙 + 𝑊 𝑖 𝑢 ).
	 Energy diff 𝑊 𝑖 ∆ : represents the difference between the lower and upper arm energies
	within one leg.		(𝑊 𝑖 ∆ = 𝑊 𝑖 𝑙 -𝑊 𝑖 𝑢 ).

Based on equations (III-

[START_REF] Sellick | Comparison of hvdc light (vsc) and hvdc classic (lcc) site aspects, for a 500mw 400kv hvdc transmission scheme[END_REF]

, two new variables are introduced in order to simplify the energy balancing control:  Energy per leg (sum) 𝑊 𝑖 Σ : represents the sum of lower and upper arm energies within

  Equation (III-21) shows that it is possible to regulate/change the averaged value of energy in leg 𝑖 by changing the AC or DC currents (𝑖 𝑖 𝑎𝑐 or 𝑖 𝑖 𝑑𝑐 ). Nevertheless, in order to avoid an unbalanced AC operation, it is better to choose the second solution based on controlling the DC

	current ( 𝑖 𝑖 𝑑𝑐 ).
	4.1.4.2.	Energy Difference equation
	Substituting 𝑃 𝑖 𝑙 and 𝑃 𝑖 𝑢 in (III-18) yields the instantaneous energy difference equation.
	𝑊 𝑖 𝛥 = ∫ 𝑃 𝑚𝑖 𝑙 -𝑃 𝑚𝑖 𝑢 = 2 𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑑𝑐 -	𝑑𝑐 𝑣 𝑚𝑖 2	𝑖 𝑖 𝑎𝑐	(III-22)
		2𝜋
		0	𝑣 𝑚𝑖 𝑑𝑐 𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐 = 𝑃 𝑚𝑖 𝑑𝑐 -𝑃 𝑚𝑖 𝑎𝑐	(III-21)

Table III -

 III 2: MMC state-space equations.

	Control objectives	State variables	Control inputs	State space equations
	AC powers	𝑖 𝑎𝑐	𝑣 𝑚𝑖 𝑎𝑐 =	𝑣 𝑚𝑖 𝑙 -𝑣 𝑚𝑖 𝑢 2	𝐿 𝑒𝑞 𝑎𝑐 𝑑𝑖 𝑖 𝑎𝑐 𝑑𝑡	= -𝑅 𝑒𝑞 𝑎𝑐 𝑖 𝑖 𝑎𝑐 + 𝑣 𝑚𝑖 𝑎𝑐 -𝑣 𝑖 𝑎𝑐
	DC power	𝑖 𝑑𝑐	𝑣 𝑚𝑖 𝑑𝑐 = 𝑣 𝑚𝑖 𝑢 + 𝑣 𝑚𝑖 𝑙	𝐿 𝑒𝑞 𝑑𝑐 𝑑𝑖 𝑖 𝑑𝑐 𝑑𝑡	= -𝑅 𝑒𝑞 𝑑𝑐 𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑑𝑐 + 𝑣 𝑑𝑐
	Energy global	𝑊 𝑚𝑚𝑐	𝑖 𝑎𝑐 or 𝑖 𝑑𝑐 (depending to the control strategy)	𝑑𝑊 𝑚𝑚𝑐 𝑑𝑡	𝑐 = 𝑣 𝑑𝑐 𝑖 𝑑𝑐 -∑ 𝑣 𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐 𝑖=𝑎
			𝑖 𝑖 𝑎𝑐 or 𝑖 𝑖 𝑑𝑐
	Energy Sum (leg)	𝑊 𝑖 𝛴	(it is recommended to use 𝑖 𝑖 𝑑𝑐 in order to avoid unbalanced AC	𝛴 𝑑𝑊 𝑖 𝑑𝑡	= 𝑣 𝑚𝑖 𝑑𝑐 𝑖 𝑖 𝑑𝑐 -𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑎𝑐
			operation)
	Energy diff	𝑊 𝑖 𝛥		𝑖 𝑖 𝑑𝑐	𝑑𝑊 𝑖 𝛥 𝑑𝑡	= 2 𝑣 𝑚𝑖 𝑎𝑐 𝑖 𝑖 𝑑𝑐 -	𝑑𝑐 𝑣 𝑚𝑖 2	𝑖 𝑖 𝑎𝑐

Table III - 3 :

 III3 Reference frames for MMC control loops.

	Natural

frame (abc) Alpha/Beta frame (αβ0) Rotating frame (dq0) AC current loop

	DC current loop	[89]	[87]	[74]
	Energy sum (leg)	[66]	[89] [87]	[74]
	Energy diff	[66]	[89]	[74] [86]

[START_REF] Martinez-Rodrigo | Current control of a modular multilevel converter for hvdc applications[END_REF]

[87]

[START_REF] Jasim | Advanced control method for vsc-hvdc systems connected to weak grids[END_REF]

[76] [52]

[START_REF] Martinez-Rodrigo | Current control of a modular multilevel converter for hvdc applications[END_REF]

Table IV -

 IV 1: Switching frequencies using ATB method with 𝜀 = 5%.

	Figure IV-1: SM voltages variation using ATB algorithm.
	Transferred power (pu )	0.3 p.u	0.6 p.u	0.9 p.u
	Ripple (%)		9.2	13.81	17.1
		Average	121	135	181
	Switching frequency (Hz)	Max	147	158	212
		Min	104	125	170

Table IV -

 IV

	Transferred power (pu )	0.3 p.u	0.6 p.u	0.9 p.u
	Ripple (%)		10.5	10.8	10.93
		Average	111	186	342
	Switching frequency (Hz)	Max	135	213	373
		Min	102	151	302

2: Switching frequencies using proposed BCA.

  That are:

								𝑑𝑠 𝑎𝑐 𝑑𝑡	= 0 = 𝛼 𝑎𝑐 + 𝛽 𝑎𝑐 [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑑𝑐 𝑣 𝑟𝑙𝑎 𝑎𝑐 ] [ 𝑒𝑞 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] = 𝛽 𝑎𝑐 -1 𝛼 𝑎𝑐 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑒𝑞 𝑣 𝑟𝑙𝑐 𝑑𝑐 𝑒𝑞 [ 𝑣 𝑟𝑙𝑏 𝑑𝑐 ] = 𝛽 𝑑𝑐 -1 𝛼 𝑑𝑐
								𝑑𝑠 𝑑𝑐 𝑑𝑡	= 0 = 𝛼 𝑑𝑐 + 𝛽 𝑑𝑐 [	𝑣 𝑟𝑙𝑐 𝑑𝑐 𝑣 𝑟𝑙𝑎 𝑑𝑐 𝑣 𝑟𝑙𝑏 𝑑𝑐	]	𝑒𝑞	(IV-10)
											𝑣 𝑟𝑙𝑎 𝑑𝑐
											[	𝑣 𝑟𝑙𝑏 𝑑𝑐	]	= 𝛽 𝑑𝑐 -1 𝛼 𝑑𝑐
											𝑑𝑐 𝑣 𝑟𝑙𝑐	𝑒𝑞
	Consequently, the control law based on sliding mode control for AC side is given by:
								[	𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] = [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] 𝑖	+ [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑎𝑐 ] 𝑣 𝑟𝑙𝑞 𝑒𝑞
	[ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] 𝑖	= -𝛽 𝑎𝑐	-1 𝑘 𝑖 𝑎𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑎𝑐 ) with { |𝑘 𝑖22 |𝑘 𝑖11 𝑎𝑐 | > |𝐴 11 𝑖 𝑑 𝑎𝑐 + 𝐴 12 𝑖 𝑞 𝑎𝑐 -𝑎𝑐 | > |𝐴 21 𝑖 𝑑 𝑎𝑐 + 𝐴 22 𝑖 𝑞 𝑎𝑐 -	𝑑𝑖 𝑑 𝑎𝑐 * 𝑑𝑡 𝑑𝑡 𝑑𝑖 𝑞 𝑎𝑐 * | |	(IV-11)
											[	𝑎𝑐 𝑣 𝑟𝑙𝑑 𝑣 𝑟𝑙𝑞 𝑎𝑐 ]	𝑒𝑞	= 𝛽 𝑎𝑐 -1 𝛼 𝑎𝑐
	For DC side, it is:
									𝑣 𝑟𝑙𝑎 𝑑𝑐	𝑣 𝑟𝑙𝑎 𝑑𝑐	𝑣 𝑟𝑙𝑎 𝑑𝑐
								[	𝑣 𝑟𝑙𝑏 𝑑𝑐	] = [	𝑣 𝑟𝑙𝑏 𝑑𝑐	]	+ [	𝑣 𝑟𝑙𝑏 𝑑𝑐	]
										𝑣 𝑟𝑙𝑐 𝑑𝑐	𝑣 𝑟𝑙𝑐 𝑑𝑐	𝑖	𝑑𝑐 𝑣 𝑟𝑙𝑐	𝑒𝑞
	[	𝑣 𝑟𝑙𝑏 𝑑𝑐 𝑣 𝑟𝑙𝑐 𝑑𝑐 𝑣 𝑟𝑙𝑎 𝑑𝑐	]	𝑖	= -𝛽 𝑑𝑐	-1 𝑘 𝑖 𝑑𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑑𝑐 ) with	{ |𝑘 𝑖22 |𝑘 𝑖33 𝑑𝑐 | > |𝐶 33 𝑖 𝑐 𝑑𝑐 -𝑑𝑐 | > |𝐶 22 𝑖 𝑏 𝑑𝑐 -|𝑘 𝑖11 𝑑𝑐 | > |𝐶 11 𝑖 𝑎 𝑑𝑐 -	𝑑𝑖 𝑐 𝑑𝑡 𝑑𝑐 * 𝑑𝑖 𝑏 𝑑𝑡 𝑑𝑐 * 𝑑𝑖 𝑎 𝑑𝑐 * 𝑑𝑡	| | |	(IV-12)

Table IV -

 IV 3: MMC parameters for control validation.Simulation

	Nominal power (MW)	1000
	AC nominal voltage 𝒗 𝒂𝒄 (kV)	320 (rms line to line)
	DC nominal voltage 𝒗 𝒅𝒄 (kV)	640 (pole to pole)
	Number of SM	40
	Inductance of the grid reactor 𝑳 𝒇 [pu]	0.18
	Resistance of the grid reactor 𝑹 𝒇 [pu]	0.005
	Arm resistance 𝑹 𝒂𝒓𝒎 [pu]	0.01
	Arm inductance 𝑳 𝒂𝒓𝒎 [pu]	0.15
	Electrostatic Constant 𝑯 𝒄 [pu]	0.04
	Capacitor Cable 𝑪 𝒅𝒄 [µF]	48.4

time-step 𝑻 𝒔 (µs) 10

Control Sampling period 𝑻 (ms)

[0.

[START_REF] Kalair | Comparative study of hvac and hvdc transmission systems[END_REF][START_REF] Kalair | Comparative study of hvac and hvdc transmission systems[END_REF]

   and (IV-12)) are reworked. For this purpose the control laws are modified as follow:

	[ 𝑣 𝑟𝑙𝑑 𝑎𝑐 𝑣 𝑟𝑙𝑞 𝑎𝑐 ] 𝑖	= [ 𝑣 𝑖𝑑 𝑎𝑐 𝑣 𝑖𝑞 𝑎𝑐 ] = -𝛽 𝑎𝑐	-1 (𝑘 𝑖 𝑎𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑎𝑐 ) + 𝑘 𝑝 𝑎𝑐 (𝑠 𝑎𝑐 ))
	[	𝑣 𝑟𝑙𝑎 𝑑𝑐 𝑣 𝑟𝑙𝑏 𝑑𝑐	]	= [	𝑣 𝑖𝑏 𝑑𝑐 𝑣 𝑖𝑎 𝑑𝑐	] = -𝛽 𝑑𝑐	𝑑𝑐 𝑠𝑖𝑔𝑛(𝑠 𝑑𝑐 ) + 𝑘 𝑝 𝑑𝑐 (𝑠 𝑑𝑐 )) -1 (𝑘 𝑖	(IV-14)
		𝑣 𝑟𝑙𝑐 𝑑𝑐	𝑖		𝑣 𝑖𝑐 𝑑𝑐

  Based on the calculation of 𝑒 𝐴 𝑇 with equation (IV-31), the matrices 𝐹(𝑇) (known as transition matrix) and 𝐺(𝑇) (known as input matrix) are given by:

	3.3.1.1.	AC side modeling
	Since the system of equation (IV-1) is being linear, it is possible to obtain its corresponding
	discrete-time model as:
	[	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇)	] = 𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐺(𝑇) [	𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 )	]	(IV-32)
	𝐹(𝑇) = 𝑒 𝐴 𝑇 = [ -𝑒 𝑒 -𝑇( -𝑇( 𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) 𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) cos(𝑇𝜔) 𝑒 sin(𝑇𝜔) 𝑒 -𝑇( -𝑇( 𝐿 𝑒𝑞 𝑎𝑐 𝑅 𝑒𝑞 𝐿 𝑒𝑞 𝑎𝑐 ) cos(𝑇𝜔) sin(𝑇𝜔) 𝑎𝑐 ) 𝑅 𝑒𝑞 𝑎𝑐	]
				𝐺(𝑇) = 𝐴 -1 (𝑒 𝐴 𝑇 -𝐼)𝐵 = [	𝐺 11 𝐺 12 𝐺 21 𝐺 22	]
	𝐺 11 =		𝜔𝐿 𝑒𝑞 𝑎𝑐 𝑠𝑖𝑛(𝑇𝜔) 𝑒	-𝑇(	𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) 𝐿 𝑒𝑞 𝑎𝑐 2 𝜔 2 + 𝑅 𝑒𝑞 -𝑅 𝑒𝑞 𝑎𝑐 𝑐𝑜𝑠(𝑇𝜔) 𝑒 𝑎𝑐 2	-𝑇(	𝑎𝑐 𝑅 𝑒𝑞 𝐿 𝑒𝑞 𝑎𝑐 )	𝑎𝑐 + 𝑅 𝑒𝑞
	𝐺 12 = -	= Exact Method = 𝑎𝑐 𝑐𝑜𝑠(𝑇𝜔) 𝑒 𝜔𝐿 𝑒𝑞 -𝑇( Euler Method 𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) + 𝑅 𝑒𝑞 𝑎𝑐 𝑠𝑖𝑛(𝑇𝜔) 𝑒 Neglected Terms -𝑇( 𝐿 𝑒𝑞 𝑎𝑐 2 𝜔 2 + 𝑅 𝑒𝑞 𝑎𝑐 2	𝑎𝑐 𝑅 𝑒𝑞 𝐿 𝑒𝑞 𝑎𝑐 )	𝑎𝑐 -𝜔𝐿 𝑒𝑞
	𝐺 21 =	𝜔𝐿 𝑒𝑞 𝑎𝑐 𝑐𝑜𝑠(𝑇𝜔) 𝑒	-𝑇(	𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) 𝐿 𝑒𝑞 𝑎𝑐 2 𝜔 2 + 𝑅 𝑒𝑞 + 𝑅 𝑒𝑞 𝑎𝑐 𝑠𝑖𝑛(𝑇𝜔) 𝑒 𝑎𝑐 2	-𝑇(	𝑎𝑐 𝑅 𝑒𝑞 𝐿 𝑒𝑞 𝑎𝑐 )	𝑎𝑐 -𝜔𝐿 𝑒𝑞
	𝐺 22 =	𝜔𝐿 𝑒𝑞 𝑎𝑐 𝑠𝑖𝑛(𝑇𝜔) 𝑒	-𝑇(	𝑅 𝑒𝑞 𝑎𝑐 𝐿 𝑒𝑞 𝑎𝑐 ) 𝐿 𝑒𝑞 𝑎𝑐 2 𝜔 2 + 𝑅 𝑒𝑞 -𝑅 𝑒𝑞 𝑎𝑐 𝑐𝑜𝑠(𝑇𝜔) 𝑒 𝑎𝑐 2	-𝑇(	𝑎𝑐 𝑅 𝑒𝑞 𝐿 𝑒𝑞 𝑎𝑐 )	𝑎𝑐 + 𝑅 𝑒𝑞

  time DC system (see equation (IV-2)). Using equation (IV-31), the exact discrete-time model can be extracted. That is:

	𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 + 𝑇)		𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 )	𝑣 𝑟𝑙𝑎 𝑑𝑐 (𝑡 𝑛 )
	[ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 + 𝑇)	] = 𝐻(𝑇) [	𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 )	] + 𝐾(𝑇) [	𝑣 𝑟𝑙𝑏 𝑑𝑐 (𝑡 𝑛 )	]	(IV-33)
	𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 + 𝑇)		𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 )		𝑣 𝑟𝑙𝑐 𝑑𝑐 (𝑡 𝑛 )

  Replacing 𝑖 𝑑,𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇) by its expression (IV-32), equation (IV-35) becomes:

	𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐺(𝑇) [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 )	] -[ 𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 * ] = 𝐾 𝑔 𝑎𝑐 [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * ]	(IV-36)
	Arranging (IV-36), the control law can be written as:
	[ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 )	] = 𝐺(𝑇) -1 [-𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐾 𝑔 𝑎𝑐 [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * ] + [ 𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 * ]]

  [START_REF] Westerweller | Trans bay cable-world's first hvdc system using multilevel voltage-sourced converter[END_REF] and (IV-42) can be verified by replacing 𝑣 𝑟𝑙𝑑,𝑞 𝑎𝑐 (𝑡 𝑛 ) in equation (IV-32) by their expressions obtained from equation (IV-37). That is:

	[	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇)	] = 𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐺(𝑇) [(𝐵 𝑇) -1 [-(1 + 𝐴 𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] +
								𝐾 𝑔 𝑎𝑐 [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * ] + [	𝑖 𝑞 𝑎𝑐 * ]]] 𝑖 𝑑 𝑎𝑐 *	(IV-46)
	By setting 𝐾 𝑔 𝑎𝑐 to zero, equation (IV-46) can be arranged as follows:
			[	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇)	] = (𝐹(𝑇) -𝐺(𝑇)(𝐵 𝑇) -1 (1 + 𝐴 𝑇)) [ 𝐺(𝑇)(𝐵 𝑇) -1 [ 𝑖 𝑞 𝑎𝑐 * ] 𝑖 𝑑 𝑎𝑐 *	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] +	(IV-47)
		[	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇)	] = 𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐺(𝑇) [𝐺(𝑇) -1 [-𝐹(𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] +
								𝐾 𝑔 𝑎𝑐 [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * ] + [	𝑖 𝑞 𝑎𝑐 * ]]] 𝑖 𝑑 𝑎𝑐 *	(IV-43)
	By setting 𝐾 𝑔 𝑎𝑐 to zero, equation (IV-43) can be arranged as follows:
								[	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 + 𝑇)	] = [	𝑎𝑐 * 𝑖 𝑑 𝑖 𝑞 𝑎𝑐 * ]	(IV-44)
	Equation (IV-44) shows that the state variables 𝑖 𝑑 𝑎𝑐 and 𝑖 𝑞 𝑎𝑐 achieve the reference values after
	one sampling period as long as the control resources are sufficiently available.
	When the Euler model is used to perform the control algorithm, the control law using pole
	placement method is given by the following expression:
	[ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 )	] = (𝐵 𝑇) -1 [-(1 + 𝐴 𝑇) [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 )	] + 𝐾 𝑔 𝑎𝑐 [	𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑑 𝑎𝑐 * 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) -𝑖 𝑞 𝑎𝑐 * ] + [	𝑎𝑐 * 𝑖 𝑑 𝑖 𝑞 𝑎𝑐 * ]]	(IV-45)
	Taking in the account equation (IV-45), the expression of 𝑖 𝑑 𝑎𝑐 and 𝑖 𝑞 𝑎𝑐 becomes:

  Replacing 𝑠 𝑎𝑐 (𝑡 𝑛 ) and 𝑠 𝑑𝑐 (𝑡 𝑛 ) by their expressions (see equations (IV-54)) leads to:Calculating the norm of 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) and 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇), that is:

	Taking into account equations (IV-60) in equations (IV-65) leads to: ‖𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇)‖ = ‖𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇)	]
	) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] + 𝐺(𝑇) [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] -𝑠 𝑎𝑐 (𝑡 𝑛 ) + 𝑠 𝑎𝑐 (𝑡 𝑛 ) 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) ] + 𝐺(𝑇)𝑈 0 𝑎𝑐 -𝐺(𝑇) -1 𝑠 𝑎𝑐 (𝑡 𝑛 ) -𝐺(𝑇) -1 (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) ]‖ (1 -𝑎𝑐 𝑈 0 ‖𝑈 𝑒𝑞 ) 𝑎𝑐 ‖ 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ ‖𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇)‖ ≤ ‖𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 ]‖ 𝑎𝑐 * (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝐻(𝑇) [ 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) ] + 𝐾(𝑇) [ 𝑣 𝑟𝑙𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑐 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] -𝑠 𝑑𝑐 (𝑡 𝑛 ) + 𝑠 𝑑𝑐 (𝑡 𝑛 ) 𝑎𝑐 +𝐺(𝑇) -1 [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] -𝐺(𝑇) -1 [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) ] + ‖𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 ] 𝑎𝑐 * (𝑡 𝑛 + 𝑇) + 𝐺(𝑇)𝑈 0 ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) 𝑎𝑐 -𝑈 0 ]‖ ‖𝑈 𝑒𝑞 𝑎𝑐 ‖	(IV-63)
		𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 )		𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇)	𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 )
	𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [	𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 )	] -[ 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 )	]	(IV-66)
	𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ + 𝐺(𝑇) [ 𝑣 𝑟𝑙𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑞 𝑎𝑐 (𝑡 𝑛 ) ] 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑎 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) ] 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) ] + 𝐾(𝑇) [ 𝑣 𝑟𝑙𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑐 + ‖𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] 𝑑𝑐 (𝑡 𝑛 ) ] + 𝐾(𝑇)𝑈 0 𝑑𝑐 +𝐾(𝑇) -1 [ 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] -𝐾(𝑇) -1 [ 𝑖 𝑎 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 ‖𝑈 𝑒𝑞 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑑𝑐 ‖ 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) 𝑑𝑐 * (𝑡 𝑛 ) ‖𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇)‖ ≤ ‖𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) ]‖ ] 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 ) 𝑑𝑐 * (𝑡 𝑛 ) 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) + 𝐾(𝑇)𝑈 0 𝑖 𝑎 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) ]] ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ + [ 𝑖 𝑎 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) ]‖ (1 -‖𝑈 𝑒𝑞 𝑑𝑐 ‖ ) 𝑈 0 𝑑𝑐 𝑑𝑐 * (𝑡 𝑛 ) 𝑑𝑐 (𝑡 𝑛 ) ‖𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇)‖ = ‖𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ]	(IV-64) (IV-68)
	Considering the worst case when ‖𝑈 𝑒𝑞 𝑎𝑐 ‖ > ‖𝑈 0 𝑎𝑐 ‖ and ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ > ‖𝑈 0 𝑑𝑐 ‖, from equations (IV-62), the sliding surfaces 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) and 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) become: 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 + 𝐺(𝑇)𝑈 0 ‖𝑈 𝑒𝑞 𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = (𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) ] 𝑎𝑐 ‖ 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑎 (IV-67) 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑎𝑐 𝑈 𝑒𝑞 𝑎𝑐 𝑎𝑐 * (𝑡 𝑛 ) ] 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) Arranging equations (IV-66) gives: 𝑠 𝑎𝑐 (𝑡 𝑛 + 𝑇) = (𝑠 𝑎𝑐 (𝑡 𝑛 ) + (𝐹(𝑇) -𝐼) [ 𝑖 𝑑 𝑎𝑐 (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 (𝑡 𝑛 ) ] -[ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑞 + [ 𝑖 𝑑 𝑎𝑐 * (𝑡 𝑛 ) 𝑖 𝑞 𝑎𝑐 * (𝑡 𝑛 ) ]) (1 -‖𝑈 𝑒𝑞 𝑎𝑐 ‖ ) 𝑈 0 𝑎𝑐 𝑎𝑐 * (𝑡 𝑛 + 𝑇) ] + [ 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) 𝑑𝑐 -𝑈 0 ]‖ ‖𝑈 𝑒𝑞 𝑑𝑐 ‖
	𝑠 𝑑𝑐 (𝑡 𝑛 + 𝑇) = 𝑠 𝑑𝑐 (𝑡 𝑛 ) + (𝐻(𝑇) -𝐼) [ ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ + 𝐾(𝑇)𝑈 0 𝑑𝑐 𝑈 𝑒𝑞 𝑑𝑐 𝑖 𝑐 𝑖 𝑎 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 (𝑡 𝑛 ) 𝑑𝑐 (𝑡 𝑛 ) + [ 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 ) ]) (1 -𝑑𝑐 𝑈 0 ‖𝑈 𝑒𝑞 𝑑𝑐 ‖ )	] -[ 𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 + 𝑇)	] + [	𝑖 𝑎 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑏 𝑑𝑐 * (𝑡 𝑛 ) 𝑖 𝑐 𝑑𝑐 * (𝑡 𝑛 )	]	(IV-65)

𝑑𝑐

-𝐾(𝑇) -1 𝑠 𝑑𝑐 (𝑡 𝑛 ) -𝐾(𝑇) -1 [(𝐻(𝑇) -𝐼) [

Table V -

 V 1: Small scale and INELFE MMC parameters.

		Small-scale MMC	Real MMC (INELFE)
	Nominal power	6 (kW)	1000(MW)
	Nominal AC voltage	206 (V) (rms line to line)	320 (kV) (rms line to line)
	Nominal DC voltage	400 (V) (pole to pole)	640 (kV) (pole to pole)
	Number of SMs per arm	10	400
	SM capacitor/ 𝑯 𝒄	4.92 (mF) / 39.2 (ms)	13 (mF) / 40 (ms)
		𝐿 𝑓 = 0.22 [pu]	𝐿 𝑓 = 0.18 [pu]
	AC filter impedance	𝑅 𝑓 = 0.0036 [pu]	𝑅 𝑓 = 0.005 [pu]
	Arm impedance	𝐿 𝑎𝑟𝑚 = 0.26 [pu] 𝑅 𝑎𝑟𝑚 = 0.0049 [pu]	𝐿 𝑎𝑟𝑚 = 0.15 [pu] 𝑅 𝑎𝑟𝑚 = 0.01 [pu]

  De nos jours, les systèmes énergétiques sont confrontés à de nombreux défis et exigences qui nécessitent un changement de paradigme. Les volontés politique et publique d'accroître l'indépendance énergétique, de réduire les émissions de gaz à effet de serre et d'accroître les capacités d'échange exigent des actions urgentes pour atteindre ces objectifs ambitieux. Pour ce faire, il est prévu que l'intégration des énergies renouvelables à grande échelle jouera un rôle crucial pour le développement des futurs réseaux électriques. En outre, afin d'accroître la robustesse des réseaux actuels et de créer un grand réseau électrique, l'interconnexion des différents pays et continents peut être considérée comme une bonne solution. De ce fait, et afin d'obtenir une bonne distribution de puissance, nous ne pouvons pas compter uniquement sur les lois de Kirchhoff. L'insertion de dispositifs d'électroniques de puissance associés à un nouveau concept de contrôle et l'augmentation des capacités de liaison sous-marine amélioreront la La deuxième contribution est de proposer de nouveaux algorithmes de contrôle pour les contrôleurs de courants actuels. Pour cela, deux méthodes ont été utilisées pour dériver leurs lois de contrôle qui permettent d'obtenir le temps de réponse le plus rapide. Cela conduit à proposer de nouveaux algorithmes de contrôle pour les boucles de régulations des courants. Les résultats obtenus, en termes de modélisation et de contrôle, sont ensuite validés par des simulations offlines (hors temps réel), simulations en temps réel et par des tests expérimentaux. Cette thèse est organisée comme suit : Le premier chapitre est consacré à expliquer le principe des réseaux HVDC et la motivation derrière les recherches impliquant la topologie MMC. Le deuxième chapitre traite la problématique de modélisation et propose de nouveaux modèles avec des nouvelles fonctionnalités. Le contrôle commande de MMC avec ces deux étages de contrôle est étudié dans le troisième chapitre. Cela permet de bien choisir la structure de contrôle utilisée dans la suite la thèse et de justifier ce choix. Le quatrième chapitre est dédié à présenter les contributions de la thèse en terme de contrôle-commande. La validation de ces contributions en temps réel et avec testes expérimentaux constitue le cinquième chapitre.

	 Développer de nouveaux équipements basés sur de nouvelles technologies comme des  Étudier les différents modèles de MMC présentés dans la littérature (détaillé, équivalent
	disjoncteurs, câbles, convertisseurs ou des parafoudres. et moyen) ;
	L'un des principaux acteurs contribuant au développement des futurs réseaux HVDC est le  Proposer des versions améliorés des modèles existants en utilisant des nouvelles
	convertisseur AC/DC. Diverses topologies de convertisseurs VSC ont été proposées dans la techniques de mise en oeuvre ;
	littérature comme les convertisseurs à deux niveaux, à trois niveaux, et les « Flying Un résumé de chacun de ces chapitres est présenté ci-dessous:
	Capacitor Convertisseur». Dans le but d'améliorer la qualité de la tension et la fiabilité du  Identifier l'effet d'algorithme d'équilibrage des sous-modules (SMs) concernant
	system, la topologie de convertisseur modulaire multiniveaux (MMC) a attiré beaucoup l'opération du MMC ainsi que ses critères de dimensionnement (dimensionnement des Chapitre 1: Les architectures et les technologies des
	d'attention depuis son invention. Grâce à son évolutivité, ses performances et son efficacité, SMs) ; réseaux HVDC
	cette topologie est considérée comme la solution la plus prometteuse pour les applications  Proposer de nouveaux algorithmes de contrôle pour les boucles de courants pour une
	HVDC. approche de boucles en cascade ;
	Cela donnera l'opportunité de pouvoir développer un grand réseau électrique fortement maillé
	dont les réseaux DC multi-terminaux font partie. Ce qui ouvre l'opportunité d'un nouveau
	concept basé sur un réseau de transmission hybride (AC / DC). À cette fin, de nouvelles
	philosophies opérationnelles ainsi que des équipements sophistiqués pour l'exploitation de ce
	nouveau système de transport d'électricité sont de plus en plus nécessaires. Des recherches
	considérables sont menées aujourd'hui pour répondre à ces besoins tels que:
	 Définir des Grid codes pour les réseaux HVDC. Les objectives de la thèse et sa méthodologie La structure de la thèse
	 Étudier l'interaction entre les réseaux à courant alternatif et les réseaux à courant
	continu. L'objectif de cette thèse porte sur la modélisation et le contrôle des MMCs, ci-dessous ces
	principaux objectifs:

gestion des flux d'énergie. Il est donc nécessaire d'adopter une solution de transmission optimale (économique, technique, financière ...) pour répondre à tous ces besoins. Le transport d'électricité en courant continu et à haute tension (HVDC) basé sur la technologie de convertisseur à source de tension (VSC) est largement apparu comme une solution adéquate pour faire face à ces défis. Plusieurs projets HVDC ont été réalisés ou sont actuellement en cours de développement à travers le monde: Trans Bay Cable aux USA, INELFE entre la France et l'Espagne, Rio Madeira au Brésil, ou encore Nanao multi-terminal VSC-HVDC (Chine)... Cette thèse traite le développement de modèles et de contrôle du convertisseur de type MMC. Le nombre élevé d'éléments de commutation et de variables d'état internes présentent des défis de modélisation, en particulier lorsqu'ils sont mis en oeuvre dans des logiciels de type transitoires électromagnétiques (EMT). En outre, le contrôle de cette topologie diffère de celui des autres topologies de convertisseurs VSC vu que la gestion du stockage interne est différente, ce qui nécessite une attention particulière. Plus précisément, cette thèse étudie ces deux aspects (modélisation et contrôle) afin de bien comprendre ces défis et de proposer de nouvelles solutions. La première contribution de cette thèse est de développer de nouveaux modèles (d'ordre complet et d'ordre réduit), en utilisant différentes techniques de mise en oeuvre. Les modèles obtenus permettent de réduire le nombre des éléments de commutation dans la structure. Cela conduit à faciliter leur mise en oeuvre dans les programmes EMT et accélérer les simulations.  Prendre en compte la période d'échantillonnage du système de contrôle dans la synthèse de la loi de commande des boucles de courants afin d'améliorer leurs temps de réponses ;  Explorer la possibilité d'accélérer les boucles externes ; la boucle d'énergie par exemple.

La méthodologie de la thèse

Les résultats obtenus dans cette thèse proviennent principalement de l'analyse théorique de la topologie du convertisseur (MMC basées sur des sous-modules (SMs) en demi-pont). Ceci est obtenu, d'abord, en dérivant les différentes expressions analytiques pour les modèles du MMC. Ensuite, son modèle simplifié est utilisé pour comprendre son principe de fonctionnement et obtenir ces équations d'états. Ce chapitre présente la technologie du réseau HVDC et ses principes. Tout d'abord, les configurations HVDC sont présentées avec leurs avantages et inconvénients associés. Ensuite, les principales technologies de conversion AC/DC, que sont les LCC et les VSC, sont présentées et comparées. Enfin, l'avantage du MMC par rapport aux autres topologies VSC est montré afin de comprendre la motivation derrière l'objectif de la thèse.

  After calculation, the matrices 𝐸 and 𝐽 are given by the following expressions: 𝑎𝑟𝑚 + 𝐿 𝑎𝑟𝑚 𝑅 𝑓 + 𝐿 𝑓 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) 𝐿 𝑎𝑟𝑚 𝑅 𝑓 -𝐿 𝑓 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) 𝐿 𝑎𝑟𝑚 𝑅 𝑓 -𝐿 𝑓 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) -𝐿 𝑎𝑟𝑚 𝑅 𝑎𝑟𝑚 + 𝐿 𝑎𝑟𝑚 𝑅 𝑓 + 𝐿 𝑓 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) ]

	𝐸 = [ -(𝐿 𝑎𝑟𝑚 + 𝐿 𝑓 ) -𝐿 𝑓 𝐽 = [ -(𝐿 𝑎𝑟𝑚 + 𝐿 𝑓 ) 𝐿 𝑓 (𝐿 𝑎𝑟𝑚 + 𝐿 𝑓 ) ] -1 -𝐿 𝑓 (𝐿 𝑎𝑟𝑚 + 𝐿 𝑓 ) [ (𝑅 𝑎𝑟𝑚 + 𝑅) 𝑅 𝐿 𝑓 ] -1 [ 𝑣 𝑟𝑙𝑖 𝑢 𝑣 𝑟𝑙𝑖 𝑙 ] = [ 𝑣 𝑚𝑖 𝑢 -𝑣 𝑑𝑐 2 + 𝑣 𝑖 𝑎𝑐 𝑣 𝑚𝑖 𝑙 + 𝑣 𝑑𝑐 2 + 𝑣 𝑖 𝑎𝑐 ] -𝐿 𝑎𝑟𝑚 + 𝐿 𝑓 𝐿 𝑓 -𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) -(𝑅 𝑎𝑟𝑚 + 𝑅 𝑓 ) -𝑅 𝐿 𝑎𝑟𝑚 𝑅 𝐽 = [ 𝐿 𝑓 𝐿 𝑓 -𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) 𝐿 𝑎𝑟𝑚 (𝐿 𝑎𝑟𝑚 + 2 𝐿 𝑓 ) ]	]
	𝐸 =
	[

  Thanks to the linearity of equation, the exact discrete-time model for arm currents can be written After calculation of 𝑒 𝐸 𝑇 using equation (IV-31), the matrices 𝐿(𝑇) and 𝑀(𝑇) are given by the

	as follows:
								[	𝑖 𝑖 𝑢 (𝑡 𝑛 + 𝑇) 𝑖 𝑖 𝑙 (𝑡 𝑛 + 𝑇)	] = 𝐿(𝑇) [	𝑖 𝑖 𝑢 (𝑡 𝑛 ) 𝑖 𝑖 𝑙 (𝑡 𝑛 )	] + 𝑀(𝑇) [ 𝑣 𝑟𝑙𝑖 𝑢 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑖 𝑙 (𝑡 𝑛 )	]	(C-2)
	following expressions:
	𝐿(𝑇) = 𝑒 𝐸 𝑇 =	[	1 2 1 2	𝑒 𝑒	-𝑇( -𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + ) -	1 2 1 2	𝑒 𝑒	-𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓 -𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓	) 1 2 ) 1 2	𝑒 𝑒	-𝑇( -𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) -) +	1 2 1 2	𝑒 𝑒	-𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓 -𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓	) )	]
																		𝑀(𝑇) = 𝐸 -1 (𝑒 𝐸 𝑇 -𝐼) 𝐽 = [ 𝑀 21 𝑀 22 𝑀 11 𝑀 12	]
	𝑀 11 =	1 2	𝑅 𝑎𝑟𝑚 𝑒	-𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + 2 𝑅 𝑓 𝑒	-𝑇( 𝑅 𝑎𝑟𝑚 (𝑅 𝑎𝑟𝑚 + 2 𝑅 𝑓 ) 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 ) + 𝑅 𝑎𝑟𝑚 𝑒 -𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓	) -2 𝑅 𝑎𝑟𝑚 -2 𝑅 𝑓
	𝑀 12 = -	1 2		𝑅 𝑎𝑟𝑚 𝑒	-𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + 2 𝑅 𝑓 𝑒 𝑅 𝑎𝑟𝑚 (𝑅 𝑎𝑟𝑚 + 2 𝑅 𝑓 ) -𝑇( 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 ) -𝑅 𝑎𝑟𝑚 𝑒	-𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓	) -2 𝑅 𝑓
	𝑀 21 =	1 2	𝑅 𝑎𝑟𝑚 𝑒	-𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + 2 𝑅 𝑓 𝑒 𝑅 𝑎𝑟𝑚 (𝑅 𝑎𝑟𝑚 + 2 𝑅 𝑓 ) -𝑇( 𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚 ) -𝑅 𝑎𝑟𝑚 𝑒	-𝑇( 𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓	) -2 𝑅 𝑓
	𝑀 22 = -	2 1	𝑅 𝑎𝑟𝑚 𝑒	-𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + 2 𝑅 𝑓 𝑒	-𝑇(	𝑅 𝑎𝑟𝑚 𝐿 𝑎𝑟𝑚	) + 𝑅 𝑎𝑟𝑚 𝑒	𝑅 𝑎𝑟𝑚 +2 𝑅 𝑓 -𝑇( 𝐿 𝑎𝑟𝑚 +2 𝐿 𝑓

) -2 𝑅 𝑎𝑟𝑚 -2 𝑅 𝑓 𝑅 𝑎𝑟𝑚 (𝑅 𝑎𝑟𝑚 + 2 𝑅 𝑓 )

  Replacing 𝑖 𝑖 𝑢,𝑙 (𝑡 𝑛 + 𝑇) by its equation (C-2), the condition (C-3) becomes:Then, the control law for arm currents controller can be written as:

			𝑖 𝑖 𝑢 (𝑡 𝑛 + 𝑇) -𝑖 𝑖 𝑢 * 𝑖 𝑖 𝑙 (𝑡 𝑛 + 𝑇) -𝑖 𝑖 𝑙 * ] = 𝐾 𝑔 𝑎𝑟𝑚 [ 𝑖 𝑖 𝑢 (𝑡 𝑛 ) -𝑖 𝑖 𝑢 * 𝑖 𝑖 𝑙 (𝑡 𝑛 ) -𝑖 𝑖 𝑙 * ]	(C-3)
		𝐿(𝑇) [ 𝑖 𝑖 𝑢 (𝑡 𝑛 ) 𝑖 𝑖 𝑙 (𝑡 𝑛 )	] + 𝑀(𝑇) [	𝑣 𝑟𝑙𝑖 𝑢 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑖 𝑙 (𝑡 𝑛 )	] -[ 𝑖 𝑖 𝑢 * 𝑖 𝑖 𝑙 * ] = 𝐾 𝑔 𝑎𝑟𝑚 [	𝑖 𝑖 𝑢 (𝑡 𝑛 ) -𝑖 𝑖 𝑢 * 𝑖 𝑖 𝑙 (𝑡 𝑛 ) -𝑖 𝑖 𝑙 * ]	(C-4)
	[	𝑣 𝑟𝑙𝑖 𝑢 (𝑡 𝑛 ) 𝑣 𝑟𝑙𝑖 𝑙 (𝑡 𝑛 )	] = 𝑀(𝑇) -1 [𝐿(𝑇) [ 𝑖 𝑖 𝑢 (𝑡 𝑛 ) 𝑖 𝑖 𝑙 (𝑡 𝑛 )	] + 𝐾 𝑔 𝑎𝑟𝑚 [ 𝑖 𝑖 𝑢 (𝑡 𝑛 ) -𝑖 𝑖 𝑢 * 𝑖 𝑖 𝑙 (𝑡 𝑛 ) -𝑖 𝑖 𝑙 * ] + [	𝑢 * 𝑖 𝑖 𝑖 𝑖 𝑙 * ]]	(C-5)

Remerciements

List of Publications

The publications resulting from this thesis are listed below:

CHAPTER V Real-Time (HIL and RCP) Validations

 Open the model which is already created in Matlab/Simulink (.mdl) with a supported version (2013a for example).

 Edit the open model to adapt it to the real-time computation constraints.  Generate the real-time code for the model and prepare its transfer to the target.

 Specify exactly on which target will be executed each subsystem (model assignation).

 Allow the transfer of the code to the selected nodes; the different subsystems are loaded on each CPU and the communication is established.

 Allow to run the real-time simulation in parallel on all the nodes/targets.

Once the simulation is running, RT-LAB allows the user to change the simulation parameters, monitor the simulation (overrun, execution time…) and perform data acquisitions.

Real-time target OP4510: it is a compact real-time target with 4 core high performance processor from Intel that can run the simulation with a small time-step (down to less than 7 μs).

This target also integrates a Field-Programmable Gate Array (FPGA) card for multi rate HIL applications and inputs/outputs management. The general specifications of OP4510 are: The system contains the following inputs/outputs ports for HIL applications:

 Digital output channels: 32 channels.

 Digital input channels: 32 channels.

 Analog input converter: 16 channels.

 Analog output converter: 16 channels.

Rapid Control prototyping (RCP) validation

Rapid Control Prototyping (RCP) systems are ideal for designing, prototyping and testing complex control system. They provide a fast and inexpensive way for control and signal processing engineers to verify designs early and evaluate design tradeoffs. In this section the test bench used for this validation test is described.

Mock-up description

Based on the proposed parameters in Table V-

Conclusions and Perspectives

Appendix A: Validation of proposed MMC models

Validation of proposed equivalent models

In this section, the semi-analytical as well as the analytical modeling techniques for the equivalent model are compared to the Benchmark model for all MMC states (controlled, blocked and faulted). As it can be observed from the results presented below, the proposed equivalent models give the same response as the Benchmark one.

Controlled state tests

Step change in DC power reference

Appendix B: MMC controllers tuning

In this section, the tuning of MMC control loops are presented and explained.

DC voltage controller

For DC systems, the DC voltage has the same role as the frequency in AC system. It indicates the grid stability based on input and output powers. Generally, one or several stations have to be controlled in DC voltage mode in order to ensure this objective. For a given station, the equation describing the DC voltage grid variation can be written as follows.

Where:

The equivalent DC grid capacitor (cables capacitors).

𝑖 𝑙 : DC current coming from other stations (DC grid).

When the MMC is controlled in DC voltage mode, the control system has to adapt the DC current (𝑖 𝑑𝑐 ) in order to maintain the stored energy inside the DC grid equal to its reference. Where:

Phase locked loop

In order to connect a MMC (VSC) to AC grid, the control has to detect the frequency as well as the angle of the connected grid. This step is performed using Phase Locked Loop (PLL). It can be also used to perform a vector control for AC currents based on a rotating frame (𝑑𝑞0).

This control philosophy allows to control continuous components instead of sinewave ones. In this rotating frame, the active and reactive powers can be calculated using the following expressions: