PART ONE: INTRODUCTION AND GENERAL CONSIDERATIONS OF THE DISSERTATION

.4 (a). The motor voltage, therefore, is not well controlled in case that the drive operates in full speed mode. This causes distortion of the motor flux and ripple in the motor torque. Negative effects of that are well known: oscillations and mechanical stress of the load machine, noise and vibrations.

1.1.4.5. Single Phase Supply with or without the Drive De-rating Operation of three-phase variable speed drives on single-phase supply is an application issue to be considered too. Single-phase supply could be due to the mains degradation when one of three phases is disconnected. In that case the drive rectifier is supplied with one phase-to-phase voltage. From the rectifier side it is nothing other than a single-phase supply. Another application example is rural single-phase supply network or specific drive applications, such as irrigation and small water supply systems.

.4 (b). The current peak is 5 to 10 times greater than the first harmonic current. This causes significant losses in the dc bus capacitor and input rectifier bridge. To be able to continuously operate under such conditions, the drive power has to be reduced to less than 40% of the drive rated power.

Smoothing of the Drive Peak Power

Some controlled drive applications are characterized by low ratio of the average to peak power. Typical examples are lifts and hosting applications, and industrial tolling PART TWO: PARALLEL CONNECTED ENERGY STORAGE DEVICE FOR CONTROLLED ELECTRIC DRIVES * Based on technological trends, the energy density will in near future be increased by a factor of 10 or more.

Short History of the Ultra-capacitors

The double-layer capacitor effect was discovered and described by Helmholtz in 1879 [69]-[73]. Almost a century after that, a first ultra-capacitor was patented by Standard Oil Company in 1966. A decade after NEC developed and commercialized this device in 1978 [69]-[73]. The first high power ultra-capacitor was developed for military applications by the Pinnacle Research Institute in 1982 [69]-[73]. Ten years after, in 1992, the Maxwell Laboratory had started development of DoE ultra-capacitors for hybrid electric vehicles. Today, the ultra-capacitors are commercially available from a number of manufacturers [74].

GENERAL INTRODUCTION

1.1. Background

Short History of Electric Drives

Through the centuries, "the production power" was the power of animals and slaves, hydro power and wind power. In the 1800s, after the invention of James Watt, it was the power of the steam machine. With the invention of electricity, electrical energy gradually came into focus. The first motors were direct current (DC) motors. At the end of 1800s, Nikola Tesla invented the three-phasevoltage system and the most famous motor; the induction motor was born. Because of many advantages over DC motors, the induction motors became dominant in most constant speed electric drive applications. However, difficulty with speed regulation was the basic disadvantage of the induction motor, and the main limiting factor for application in variable speed applications.

At the beginning of 20 th century, a few configurations of variable speed drives were used.

1) Ward-Leonard motor-generator group. Since power conversion in such a system is done three times and a dc machine is included in the loop, this concept had not been broadly accepted in high power applications.

2) Wound rotor induction motor. The motor speed were adjusted and "regulated" by a circuit connected to the rotor via set of brushes, while the stator is connected to the fixed frequency supply. 1) The rotor resistor control and 2) "constant power" Kramer or "constant torque" Scherbious configurations [1].

All these drive configuration were fairly inefficient and faced a problem of reliability.

The Early "Power Electronics" Driven ac Drives

The first period in development of "power electronics" controlled electric drives was the period between 1910 and 1940. Early "power electronics" drives were based on triggeredarc power switches, such as controlled mercury-arc rectifiers, thyratrons and ignitrons. The drive configurations were the electronic Kramer configuration using uncontrolled rectifier bridge, electronic Scherbius using rectifier-inverter configuration, Brown Boveri commutatorless drive, thyratron motor configuration and early version of load commuted synchronous motor drive [1]. In 1930s, the first cycloconvertor was used. All those topologies did not have broad success in industrial applications, simply because of complexity and reliability issues of the "power electronics" switches.

In early 1960s, the first silicon controlled rectifier (SCR) was invented. This invention brought a large step in development of power electronics controlled electric drives. Kramer and Scherbius drive configuration, load commuted synchronous motor drives and cycloconvertor drives become dominant in most of high power applications. Later on, current sourced inverter with variable output frequency became a very competitive scheme for induction motor applications. Voltage source drive topologies became competitive with the invention of the gate turn-off thyristors (GTO) in 1970s and insulated gate bipolar transistors (IGBT) in the 1980s.

Present

Today, 70 % of the world electricity production is consumed by some kind of controlled electric drives; traction and transportation drives, industrial drives, home appliance drives and so on. This indicates the importance of controlled electric drives in everyday life.

Modern low voltage controlled electric drives are exclusively based on three-phase motors, either induction or permanent magnet synchronous motors [2]- [3]. The motor is powered from a power converter, so-called the drive converter, having variable output voltage and frequency. The drive converter is supplied from low voltage industrial or distributive three-phase mains 230 V to 690V, 50 Hz to 60Hz. The most common converter topology is a cascade-connected diode front-end rectifier and voltage source pulse width modulated (PWM) inverter. A simplified circuit diagram is depicted in Fig. 1.1. The drive converter consists of an input three-phase diode rectifier (D 1 -D 6 ), dc bus link with passive filter (L BUS C BUS ) and pulse width modulated (PWM) output inverter (S 1 -S 6 ). The rectifier generates dc bus voltage v BUS , which is further inverted in the output variable ac voltage via PWM inverter. The input rectifier is based on Si diodes, while the output inverter is exclusively based on IGBT devices [4]. Switching frequency falls in range of few kHz up to 20kHz. The PWM inverter is controlled from the upper level controller using some of advanced digital control techniques. The control objective is the control of the motor torque and speed in closed or open loop control mode [3].

An additional switch S B , diode D B and resistors R B , so-called brake chopper and resistor are used in applications with a demand for braking of the drive load (hoisting and large inertia applications). The braking energy is dissipated in the brake resistor R B via the brake chopper S B D B. This is, in fact, one of the most limiting factors for advanced high efficient drive applications. The first type of applications that are in the scope of this project are hoisting type applications. Fig. 1.2 (a) shows photography of one typical on-port rubber tyred gantry (RTG) crane [5]. The hoisting drive time-power profile is sketched in Fig. 1.2 (b). When lifting the load, the hosting drive takes energy from the primary supply, in this case a diesel engine generator. When lowering the load, the drive operates in braking mode. As a diesel engine generator is not reversible, the braking energy cannot be pumped back into the primary power source. Instead, it is dissipated as heat in the brake resistor. Lift applications are similar to the RTG crane applications, except for two differences. The mains as the primary power supply source in lift applications is reversible. This means that the drive braking energy can be pumped back to the mains. The lift load (cabin) is balanced with a counterweight. Thus, the drive operating mode depends on the load direction (up or down) and ratio of the load to the counterweight.

Machines with Intermittent Load

The second type of application to consider is industrial machines with intermittent load. Such applications are characterised by low ratio of average to peak power. The input power is highly positive when the drive accelerates, and the power is highly negative when the drive decelerates. During constant speed operation, the input power is normally low. Fig. 1.3 illustrates the time-power profile of such a drive application. Typical application is tools carriers in automatic milling machines [3].

Blowers and Pumps Applications

These applications are normally the simplest controlled electric drive applications. Blowers and pumps do not require specific control scheme and do not require braking (at lest do not require fast braking). In some cases, those applications can be sensitive to the mains power interruptions if applied in critical process industry.

Low power irrigation pump systems are specific application because the mains supply is often single-phase network. The motor is a three-phase induction motor powered from a three-phase PWM inverter.

Remaining Technical Issues in Application of Controlled Electric Drives

Six technical issues in application and design of modern variable speed drives can be identified. Those issues are still a great challenge for power electronics researchers and drive designers [6].

Saving and Recovery of the Drive Braking Energy

A lot of industrial and other applications, such as lifts, cranes and tooling machines are characterized by low balance between the input average power and peak power. Moreover, such applications have a demand for braking at full power. In ordinary variable speed drives, the mechanical energy stored in rotating mass of the motor load and the motor shaft is usually realized and wasted in a braking resistor. The energy losses in such applications go up 20 to 50% of the consumed energy. In today's energy crisis, energy efficiency has become the issue that needs an urgent solution [6].

The Drive Ride-Through Capability

Modern controlled electric drives are sensitive to the mains supply disturbances. The most frequent disturbances are voltage dips/sags. A voltage sag is defined as instantaneous decrease in the RMS voltage, where the decrease is in range of 10 to 90% of the nominal voltage, while the sag duration is in order of a half cycle up to a minute [7]- [11]. Such a power interruption causes the dc bus voltage to drop below its lower limit, and then the entire drive system trips. The system interruptions are very costly and unacceptable when the drive is applied in critical process industry, oil pump systems, semiconductor and glass industry.

Such kind of industries have reported losses ranging from 10k$ to 1M$ per disrupting event [10].

Quality of the Drive Input Current

Another power quality issue, which is introduced by the drive itself, is quality of the drive input current. Harmonic spectra of the drive input current depends on the drive rectifier topology. Ordinary diode front-end rectifiers equipped with passive LC filter draws the input current that is distorted and rich with higher harmonics. An example set of waveforms is depicted in Fig. 1.4 (a). Total harmonic distortion (THD) factor can be as high as 150%, or even higher [12].

The mains current harmonics cause additional heating and stress of the distribution transformers, power factor correction capacitors and neutral line in low voltage distribution network. Electromagnetic interference (EMI) with communication network and sensitive equipment is a critical issue too. To avoid or at least minimize those problems, advanced controlled electric drive converters have to comply with the input current harmonics limitations defined by international standards [13].

Quality of the Drive Converter DC Bus Voltage

The dc bus voltage is the intermediate voltage in the conversion path from the mains supply to the motor terminal. To achieve full motor voltage without distortion, it is important to provide sufficient dc bus voltage without significant fluctuation and ripple. Moreover, the higher dc bus voltage the better performance of the motor current and torque control [3]. machines having intermittent load. Fig. 1.5 shows waveforms of the mains current i MAINS and dc bus voltage v BUS of an example controlled electric drive application. Peak power is 5500W for 0.8s, while minimum power is 500W for 1.6 s. It gives the ratio of average to peak power of 0.31. Thus, the drive cabling, fuses and contactors have to be over-sized by factor of 3. This type of load may also cause fluctuation and flicker in weak supply networks [START_REF] Rufer | A supercapacitor-based energy storage substation for voltage compensation in weak transportation networks[END_REF]. In lift applications the peak to average power ratio could be greater than 10, as reported in [START_REF] Rufer | A supercapacitor-based energy-storage system for elevators with soft commutated interface[END_REF]. The drive load is cycling between 500W and 5500W at period of 2.2s with duty cycle of 30%. The average power is approximately 31% of the peak power.

Literature Overview 1.2.1. Regenerative Drives Based on Back to Back and Matrix Converter

Most of the existing regenerative controlled electric drive solutions belong to two groups; back to back PWM rectifiers [START_REF] Rodríguez | PWM Regenerative Rectifiers: State of the Art[END_REF], and so-called direct (matrix) converters, [START_REF] Venturini | A new sine wave in sine wave out, conversion technique which eliminates reactive elements[END_REF], [START_REF] Wheeler | Matrix converters: A technology review[END_REF]. Fig. 1.6 shows simplified circuit diagram of voltage source back-to-back and matrix drive converters. The drive takes energy from the mains whenever operates in motoring mode, and pumps the energy back to the mains whenever operates in breaking mode. The main disadvantage of such solutions is the fact that functionality and reliability of the drive is strongly linked to the mains reliability. Simple speaking, any power interruption of the mains is reflected on the drive. The drive is disabled whenever the mains is interrupted for longer than the mains cycle (20ms). Moreover, these drives have a high power demand during acceleration and deceleration (low ratio of average to peak power). This modulated input power produces additional losses and disturbances (flicker) in the weak supply mains.

Regenerative Drives Based on the Energy Storage Concept

A block diagram of a regenerative drive based on energy storage concept is given in Fig. 1.7. The drive system consists on an ordinary diode front-end converter equipped with an energy storage device [START_REF] Attaianese | High performance supercapacitor recovery system for industrial drive applications[END_REF]- [START_REF] Inoue | An efficient induction motor drive method with a regenerative power storage system driven by an optimal torque[END_REF]. This concept has come into focus recently with broad application of new electro-chemical double layer capacitors (EDLC), so-called ultracapacitors [START_REF] Kotz | Principles and applications of electrochemical capacitors[END_REF]. An ultra-capacitor is electro-chemical capacitor having two porous electrodes made of activated carbon that are separated by a separator and impregnated with electrolyte [START_REF] Kotz | Principles and applications of electrochemical capacitors[END_REF]. Thanks to large specific surface (2000m 2 /g) of activated carbon electrodes, the specific capacitance and energy are much higher than for standard electrolytic capacitors. In addition, the specific peak power of the ultra-capacitors is much higher than peak power of the existing electro-chemical batteries. Flywheel energy storage is usefully used in such a drive concept too [START_REF] Inoue | An efficient induction motor drive method with a regenerative power storage system driven by an optimal torque[END_REF].

The kinetic energy of the drive rotating masse, so-called braking energy is stored into the ultra-capacitor during the drive braking sequence. During the next motoring sequence, the energy is restored from the ultra-capacitor and realized on the drive. The first commercial applications of the ultra-capacitor based regenerative drives were traction and hybrid car drives [START_REF] Solero | Design of multiple-input power converter for hybrid vehicle[END_REF]- [START_REF] Allegre | Energy storage system with supercapacitor for an innovative subway[END_REF]. General purpose variable speed drive with such an energy saving concept could be used in lift and hoisting applications, tooling machines having high demand for frequent and fast start/stop sequence, and many other application having a demand for braking. In [5], such a drive concept is analyzed and successfully applied on the rubber tyred gantry (RTG) crane. As reported in [5], the fuel saving is 30% to 40%. Moreover, the diesel gen-set can be re-sized and smaller unit could be used. The same drive concept has been proposed for building lift applications [START_REF] Tominaga | Development of energy saving elevator using regenerated power storage system[END_REF], [START_REF] Rufer | A supercapacitor-based energy-storage system for elevators with soft commutated interface[END_REF]. The ultra-capacitor as the energy storage for short term UPS function or extension of the drive ride-through capability is applied in critical industrial applications [START_REF] Duran-Gomez | An approach to achieve ride-through of an adjustable-speed drive with flyback converter modules powered by super capacitors[END_REF], [START_REF] Tongzhen | A supercapacitor based ride-through system for industrial drive applications[END_REF]. Unlike electrochemical battery, the ultra-capacitor state of charge strongly depends on the capacitor terminal voltage. The capacitor voltage varies a lot when the capacitor is charged/discharged. That means the ultra-capacitor cannot be connected directly to the drive dc bus, because the voltage adaptation and matching between the ultra-capacitor and dc bus. To achieve flexibility and high efficiency, a dc-dc power converter is used as a link between the ultra-capacitor and the drive [START_REF] Jih-Sheng | Energy management power converters in hybrid electric and fuel cell vehicle[END_REF]- [START_REF] Guidi | An optimized converter for battery supercapacitor interface[END_REF].

Most of dc-dc converter topologies are based on the ordinary two-level single-phase or multiphase interleaved topologies [5], [START_REF] Jih-Sheng | Energy management power converters in hybrid electric and fuel cell vehicle[END_REF]- [START_REF] Ortúzar | Ultracapacitor-based auxiliary energy system for an electric vehicle: implementation and evaluation[END_REF]. The main drawback of these topologies is the switches voltage rating. The switches are rated on the full dc bus voltage. As the dc bus voltage may go up to 800V, even more, the switches are rated on 1200V. This becomes an issue if the converter switching frequency is quite high; let us say above 20kHz. Switching losses become quite significant. It causes degradation in the conversion efficiency and additional difficulties in the converter thermal design. Two-level dc-dc converter with soft switching has been presented in [START_REF] Zhang | High-power density design of a soft-switching high-power bidirectional dc-dc converters[END_REF]. This solution offers lower switching losses. However, since the converter operates in discontinuous conduction mode (DCM), the peak current and ripple current are significantely greater than one that operates in continuous conduction mode (CCM). This causes a problem of the inductor losses, particularly the core losses. Moreover, additional losses on the ultra-capacitor internal resistance cannot be neglected if the output current is not well filtered. Isolated dc-dc converter topologies with soft switching have been analyzed in [START_REF] Inoue | A bidirectional dc-dc converter for an energy storage system with galvanic isolation[END_REF], [START_REF] Ma | A zero-voltage-switching bidirectional dc-dc converter with state analysis and soft-switching-oriented design consideration[END_REF]. These topologies are attractive solutions when ratio of the dc bus voltage to the ultra-capacitor voltage is high, greater than 2. If the ratio is lower than 2, the efficiency is lower than that of a non-isolated ordinary topology. Three-level converters are well adopted solution in applications with high input voltage and relatively high switching frequency [START_REF] Xinbo | Fundamental considerations of three-level dc-dc converters: Topologies, analyses, and control[END_REF]- [START_REF] Jin | Three-level bi-directional converter for fuel cell/battery hybrid power system[END_REF]. The switches are stressed on half of the total dc bus voltage. This allow us to use lower voltage rated switches having better switching and conduction performance compared to the switches rated on the full blocking voltage. Therefore, the converter overall performances, including cost and efficiency, can be significantly improved compared to twolevel converters, especially when the switching frequency is above 20kHz or MOSFETs are used [START_REF] Grbovi} | High-voltage auxiliary power supply using series-connected MOSFETs and floating self-driving technique[END_REF].

Most of the control methods presented in the literature are focused on hybrid electric vehicle and power sources [START_REF] Rufer | A supercapacitor-based energy storage substation for voltage compensation in weak transportation networks[END_REF], [START_REF] Solero | Design of multiple-input power converter for hybrid vehicle[END_REF]- [START_REF] Allegre | Energy storage system with supercapacitor for an innovative subway[END_REF], [START_REF] Schupbach | 35kW ultracapacitor unit for power management of hybrid electric vehicle: bi-directional dc-dc converter design[END_REF]- [START_REF] Ortúzar | Ultracapacitor-based auxiliary energy system for an electric vehicle: implementation and evaluation[END_REF], [START_REF] Thounthong | Control strategy of fuel cell and supercapacitors association for a distributed Generation system[END_REF]- [START_REF] Greenwell | Predictive control of voltage and current in a fuel cellultracapacitor hybrid[END_REF]. Only a few publications are focused on control of the ultra-capacitor based electric drives [5], [START_REF] Duran-Gomez | An approach to achieve ride-through of an adjustable-speed drive with flyback converter modules powered by super capacitors[END_REF]- [START_REF] Tongzhen | A supercapacitor based ride-through system for industrial drive applications[END_REF].

The Mains Current Harmonics and Related Issues

The energy storage based electric drives provide a more efficient way to save braking energy and improve global efficiency and reliability of the controlled electric drive systems [START_REF] Grbovi} | Regenerative controlled electric drive with extended ride-through capability using an ultra-capacitor as energy storage device[END_REF]. The input current quality, however, remains an unsolved challenging issue. In the last decade, numerous different solutions for this problem have been proposed and discussed in literature.

Single-switch three-phase continuous conduction mode (CCM) boost rectifier is a solution that offers numerous advantages compared to the ordinary diode front-end rectifier [START_REF] Prasad | An active factor correction technique for three-phase diode rectifiers[END_REF]- [START_REF] Rastogi | A Comparative Evaluation of Harmonic Reduction Techniques in Three-phase Utility Interface of Power Electronic Loads[END_REF]. The rectifier output current is constant and therefore the mains current is 2π/3 square waveform with THD of approximately 30%. The dc bus voltage is actively controlled and boosted above the mains phase to phase peak voltage. The low frequency voltage ripple is small and it could be neglected compared to that of the diode rectifier. A variant of the CCM boost rectifier is discontinuous conduction mode (DCM) boost rectifier [START_REF] Kolar | A comprehensive design approach for a tree-phase high frequency single switch discontinuous mode boost power factor corrector based on analytically derived normalized converter component rating[END_REF]- [START_REF] Jang | A new input-voltage feed-forward harmonic-injection technique with nonlinear gain for single-switch, three phase, DCM boost rectifiers[END_REF]. This topology offers lower THD of the input current than CCM boost rectifier (10-15% in comparison to 30%).

A common disadvantage of the single-switch boost topologies is power rating of the semiconductor switches. The switches are rated for the full dc bus voltage and full rectifier current. Generally speaking, a semiconductor switches' performance; conduction and switching strongly depend on the switch voltage rating and the switch technology. Lower voltage rating means lower conduction losses, better switching performance, higher efficiency and lower cost. For example, let us consider a 400V three-phase rectifier. The dc bus voltage is 700 to 800V. For the ordinary single-switch boost converter, the switch and boost diode voltage rating is 1000V to 1200V. For this voltage rating, 1200V IGBT and 1200V fast diode are used. In this case, maximum switching frequency is limited by the switching performance of the IGBT and the diode. To reduce switching losses, soft switching techniques can be used [START_REF] Dah-Chuan | A single switch continuous conduction mode boost converter with reduced reverse recovery and switching losses[END_REF]- [START_REF] Jang | High power factor soft switched boost converter[END_REF]. However, the soft switching techniques require additional active switches, diodes and passive resonant circuits, which make the circuit more complex and expensive. Double-boost rectifiers employ two interleaved active switches and boost diodes. The switches and diodes are rated for half dc bus voltage and full rectifier current. As a result, the conversion losses are slightly lower in comparison to the single-switch boost rectifier [START_REF] Zhang | Single-phase three-level boost power factor correction converter[END_REF]. The boost inductor is approximately 25% that of the single-switch topology.

A dc side shunt active filter, applied on a single-phase diode rectifier has been analysed in [START_REF] Garica | Harmonic reducer converter[END_REF]. The filter circuit is connected on the rectifier dc side, and as such it is simple and cost effective in comparison to the state of the art ac side connected active filters. This approach could be extended to three-phase rectifiers, wherein the input current THD can be reduced to approximately 30%. The main disadvantage of such a filtering concept is high current stress and low efficiency. The first reason for this is an additional diode in the main current path. The current that circulates between the dc filter and dc bus capacitor is a few time greater than the mains current. Hence, losses of the filter and dc bus capacitor are significant.

The electronic smoothing inductor (ESI) has been proposed and analysed in [START_REF] Ertl | A constant output current three-phase diode bridge employing a novel "electronic smoothing inductor[END_REF]- [START_REF] Ertl | A constant output current three-phase diode bridge rectifier employing a novel "electronic smoothing inductor[END_REF]. An auxiliary low voltage dc-dc converter is serially connected between the rectifier and the dc bus capacitor. The rectifier current is actively controlled to be constant or pseudo-constant. The input current THD is approximately 30%, the same as that of the CCM single-switch boost rectifier. A key advantage of the ESI concepts is that the auxiliary dc-dc converter is rated on full current and a fraction (normally 20%) of the dc bus voltage. Hence, the auxiliary converter losses are quite small. The entire rectifier efficiency can go above 98% [START_REF] Ertl | A constant output current three-phase diode bridge rectifier employing a novel "electronic smoothing inductor[END_REF]. The main disadvantage of the ESI is that the dc bus average voltage is not controlled and it is slightly lower than the rectifier average voltage.

The concept of a third harmonic injection method for three-phase diode rectifiers is well presented in monograph [START_REF] Pejovic | Low harmonics three-phase diode bridge rectifiers based on the current injection principle[END_REF]. Although the harmonic injection method is simple, it does not have broad application in conventional industrial rectifiers. The main reason for this lays in the need for bulky passive elements, mainly coupling transformers. The overall efficiency is not sufficiently high as required by the applications.

Single-phase supplied three-phase controlled electric drives and related application issues are not often treated in the literature. Single-phase supplied rectifier with passive LC dc bus filter and three-phase pulse width modulated (PWM) inverter is the most common solution in low power low cost applications. The dc bus capacitor is a large electrolytic capacitor, while the inductor is small or even absent. Such a rectifier works as peak detecting circuit; the dc bus voltage is charged to the peak mains voltage and the mains current is a train of narrow pulses. Apart the fact that such a rectifier is simple, cost effective and robust, the drive manufactures do not recommended it because of a few serious limitations:

-The input current is distorted, with peaks that are 5 to 10 times of the fundamental RMS current. The total harmonic distortion factor is as high as 150%, or even higher. The power factor is low.

-A bulky dc bus capacitor is necessary to keep the dc bus voltage ripple acceptably low.

-A filter inductor must be used to limit peak of the input current. The inductance value is however limited because the dc bus voltage quickly decays with the inductance.

-The dc bus voltage is reduced in comparison to three-phase supplied drive. Hence, available motor voltage is reduced too.

-The drive life time is limited by the dc bus capacitor life time (the capacitor is the most stressed component).

-The drive may be de-rated by 50% when single-phase supplied, which means higher installation cost per kW.

Single-phase single-switch and double-boost rectifier is the most popular solution in applications that require boosted dc bus voltage and sinusoidal or pseudo-sinusoidal input current, [START_REF] García | Single phase power factor correction: A Survey[END_REF], [START_REF] Singh | A review of single-phase improved power quality ac-dc converters[END_REF]. This topology is often used in low power supplies such as PC and small telecom supplies. In variable speed drives, however, this is rarely used topology because cost, size and efficiency.

Split-capacitor three-leg rectifier/inverter is used in low cost low power variable speed drive applications, such as air-conditioning and home appliance applications [START_REF] Jacobina | Induction motor drive system for low-power applications[END_REF], [START_REF] Lee | Control of single-phase-to-three-phase ac-dc-ac PWM converters for induction motor drives[END_REF]. This topology offers the lowest count of the active and passive components in comparison to the other solutions. However, two drawbacks make this topology inappropriate in high power industrial applications; 1) The dc bus capacitor current stress at low frequency, and 2) the output current ripple.

Smoothing of the Input Peak Power

The problem of the peak power filtering and voltage fluctuation in weak distribution supply in public transportation is briefly analysed in [START_REF] Rufer | A supercapacitor-based energy storage substation for voltage compensation in weak transportation networks[END_REF]. The peak power and braking issue in lift application has been analysed [START_REF] Rufer | A supercapacitor-based energy-storage system for elevators with soft commutated interface[END_REF]. Ultra-capacitor based energy storage has been proposed as a solution. Control aspects have been briefly presented in [START_REF] Rufer | A supercapacitor-based energy storage substation for voltage compensation in weak transportation networks[END_REF].

The Dissertation Objective

The objective of this dissertation is to identify and discuss some of the remaining technical issues in application of advanced controlled electric drives. Then, a solution or set of solutions for the problems that are identified have to be proposed, analysed, discussed and validated by simulation and set of experiments. Three sub-objectives can be summarized as follows.

Parallel Connection of Energy Storage Device and Controlled Electric Drive

The first objective is to analyse the existing solutions of parallel connected energy storage device and controlled electric drive. The system operating modes have to be analysed in details and critical points clearly identified. Important properties of the ultra-capacitor as energy storage device for power conversion application have to be discussed too. Then, an appropriate topology of the interface dc-dc converter has to be proposed. Finally, the entire conversion system should be modelled and a new control scheme proposed. The proposed solution(s) has to be competitive with state of the art solutions regarding efficiency, cost, size of active and passive components and heat sink, and dynamic performances of the dc bus voltage control, the ultra-capacitor state of the charge control and the ultra-capacitor current control.

The Mains Current Harmonics, DC Bus Voltage Control and Single Phase Supply

State of the art solutions of three-phase diode boost rectifiers have to be analysed and disadvantages clearly identified. A new topology for three-phase diode boost rectifier has to be proposed, analysed, discussed and verified by simulations and set of experiments. The proposed solution(s) has to be competitive with state of the art solutions regarding efficiency, size of passive components including heat sink, cost and dynamic performances of the voltage and rectifier current control.

Energy Storage and Power Factor Correction Device for Electric Drive Applications

Last but not least is to merge the solutions of 1.3.1 and 1.3.2 into one generic solution that intents to solve all the six technical issues mentioned in section 1.1.4. Analyses, discussion and verification by simulations and experiments have to be done. The solution has to be competitive with state of the art solutions regarding efficiency, size, cost and dynamic performances of the overall system.

The Dissertation Organization

The dissertation is organised in five parts. Each part presents one or set of similar technical problems as well as a new solution for those problems. Each part consists of one or more logically organised chapters.

Part One: General Introduction

In the first part, a general introduction is given. Background of controlled electric drives is given, typical applications of controlled electric drives are discussed and remaining applications issues are identified. An overview of the literature is given, and objectives of the dissertation are also given.

Part Two: Parallel Connected Energy Storage Device for Controlled Electric Drives

In the second part of the dissertation, the ultra-capacitor as an energy storage device for advanced power conversion application is discussed. Then, the concept of parallelconnected energy storage device for controlled electric drives is presented and discussed. The presented solution solves the first two technical issues mentioned in the introduction; 1) saving of the drive braking energy and 2) Extension of the drive ride-through time.

The ultra-capacitor as an energy storage device is discussed in chapter 2. The basic operating principle of the ultra-capacitors is described. As an electric device, the ultracapacitor can be modeled for two purposes; analysis of the electric circuit dynamic behavior (analysis and synthesis of the control) and thermal behavior of the ultra-capacitor. Those two modeling aspects are discussed in the second part of chapter 2. Finally, the ultra-capacitor losses versus frequency of the excitation current are discussed and losses model is proposed.

In chapter 3, a controlled regenerative electric drive using the ultra-capacitor as energy storage device is discussed. The basic operating modes are described. Then, the ultracapacitor design and selection guidelines are given. The conversion losses and efficiency versus size of the ultra-capacitor are discussed. The system cost versus the conversion efficiency is also briefly discussed.

Chapter 4 presents a three-level dc-dc converter that is employed as a link between the variable speed drive and the ultra-capacitor. The converter operating principle is discussed and advantages of such a topology are clearly identified. Design guidelines are given. Finally, a design example is presented at the end of the chapter.

Modelling and control aspects are discussed in chapter 5. Firstly, some modelling technique theory is presented. Thereafter a non-linear and linearzed model of the dc-dc converter is developed. The dc bus circuit model is discussed too. Finally, a non-linear and small signal linear model of the entire conversion system is developed. The model is verified by Matlab/Simulink simulations. In the second party of chapter 5, a new control scheme is presented and discussed. Control of the ultra-capacitor current and the voltage balancing error is presented. The presented control is experimentally validated. The results are discussed. Then, control of the ultra-capacitor voltage and the dc bus voltage is presented and analysed. The controllers' synthesis procedure is given in details. The designed control system is validated by simulations and set of experiments.

In chapter 6, the solution presented is compared with state of the art solutions. At first, concept of the ultra-capacitor based regenerative electric drive is compared to back-to-back and matrix converters. Then, the three-level dc-dc converter is compared with state of the art topologies. Three parameters are compared: 1) properties of the active switches (IGBTs and diodes), 2) properties of the passive components (the output filter inductor and input filter capacitor) and 3) the conversion losses. Control aspects are also discussed and compared.

Part Three: Three-terminal Power Factor Correction and Voltage Control Device

In the third part, the three-terminal power factor and the dc bus voltage control device is presented is discussed. The presented solution solves the following three technical issues: 1) the mains current harmonics, 2) the dc bus voltage control and 3) single-phase supply.

Background and state of the art of active rectifier topologies is given in chapter 7. A novel half-dc-bus-voltage rated boost rectifier is briefly presented.

The new half-dc-bus-voltage rated boost rectifier is presented in chapter 8. Structure of the topology is analysed in detail. A design example is given and the new topology is experimentally validated. The results are discussed.

Modelling and control aspects of the new topology are discussed in chapter 9. Nonlinear and small signal models are developed. Those models are verified by Matlab/Simulink simulations. The control scheme is given and the controllers' synthesis procedure discussed.

Single phase operation of the presented boost rectifier is analysed in chapter 10. Critical design points are discussed.

Chapter 11 is gives a comparison of the presented boost rectifier versus state of the art solutions.

Part Four: Three-terminal Energy Storage and PFC Device for Controlled Electric Drives

In the fourth part, a three-terminal energy storage and PFC device for controlled electric drives is presented and discussed. The presented solution intents to solve all six technical issues mentioned in the introduction: 1) Saving and recovery of the drive braking energy, 2) Extension of the drive ride-through time, 3) The mains current harmonics, 4) The dc bus voltage control, 5) Single-phase supply and 6) The mains peak power shaving function.

In chapter 12, the concept of the three-terminal energy storage and PFC device for controlled electric drives is discussed and necessary theoretical analysis is given. Some aspects of the system design are given.

Modelling aspects and control scheme are discussed in chapter 13. The entire power conversion system consisting of the input boost rectifier, dc link, the ultra-capacitor interface dc-dc converter and the PWM inverter is modelled. Then, a new control scheme is proposed. The control scheme is validated by Matlab/Simulink simulation and set of experiments performed on a laboratory industrial prototype. The results are presented and discussed in chapter 14.

Part Five: Concluding Remarks and Conclusions

The dissertation work and contribution are discussed in chapter 15. Final concluding remarks and perspectives are given in chapter 16.

AN ULTRA-CAPACITOR AS ENERGY STORAGE DEVICE FOR POWER CONVERSION APPLICATIONS

The Ultra-Capacitors

An electric capacitor is a passive dynamic one-terminal electric device. In this context, dynamic means the device terminal voltage to current ratio is not a constant and linear. The voltage and current are linked via a differential equation which is in the general case a nonlinear equation. As that, the electric capacitor has capability to store energy as electric charge, more precisely as electric field between the capacitor plates. There are three different types of capacitors, namely electrostatic, electrolytic and electrochemical capacitors. In this dissertation, the electrochemical capacitors, so-called the ultra-capacitors are considered only.

Ultra-capacitors are different from the other type of capacitors mainly because their specific capacitance, [F/dm 3 ] and energy density, [kJ/dm 3 ] are several orders of magnitudes larger than that of electrolytic capacitors. In comparison to electrochemical batteries, the energy density is lower while the power density is larger than that of conventional batteries. Cycling capability is also significantely better compared to batteries. Today, the ultra-capacitors are composed of two electrodes separated by a porous membrane, the so-called a separator. The separator and the electrodes are impregnated by a solvent electrolyte. The electrodes are made of porous material such as activated carbon or carbon nano-tubes [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF]- [START_REF] Halper | Supercapacitor: a brief overview[END_REF]. Typical specific surface area of the electrode is about 2000m 2 /g. Such a large surface area and very thin layer of the charges, in order of nm gives specific capacitance of up to 250F/g [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF]- [START_REF] Halper | Supercapacitor: a brief overview[END_REF]. Rated voltage of the ultra-capacitor cell is determined by the decomposition voltage of the electrolyte. Typical cell voltage is 1 to 2.8V, depending on the electrolyte technology [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF]- [START_REF] Halper | Supercapacitor: a brief overview[END_REF]. To obtain higher working voltage, which is determined by the application, a number of cells must be series-connected into one capacitor module.

Ultra-capacitors as energy storage devices have found very wide application in power conversion due to their advantages over the conventional capacitors and electro-chemical batteries; high energy and power density, high efficiency, high cycling capability and long life.

Overview of Different Technologies

Fig. 2.1 shows taxonomy of the existing types of electrochemical capacitors. Whole family of the ultra-capacitors can be divided into two groups: electric double layer capacitors (EDLC) and pseudo-capacitors. A combination between the EDLC and pseudo-capacitors is group of hybrid capacitors. The EDLC group consists of three-subgroups; activated carbon, carbon nano-tubes and carbon aero gels. In this dissertation, application of activated carbon EDLC is discussed.

Electric Double Layer Capacitors -EDLC

The Ultra-capacitor Structure

In order to increase the capacitance of anultra-capacitor, it is necessary to maximize contact surface are. To achieve this without increaseing in the capacitor volume, one must use a special material for the electrode. This material must have a porous structure and consequently a very high specific surface. The most frequently used material is activated carbon or carbon nano-tubes. In both cases, the specific surface may be as high as 1000m 2 /g to 3000m 2 /g. The simplified structure of super-capacitor cell is depicted in Fig. 2.2. The elementary capacitor cell consists of positive and negative current collectors, positive and negative porous electrodes made of activated carbon which are attached on the current collectors, and a separator between the porous electrodes. The separator is material transparent to ions but an insulator for direct contact between the porous electrodes. Since the first development of double layer capacitors, there have been several iterations and models of the basic structure.

The very first work on double layer capacitors was carried out by Helmholtz in 1853. He supposed that the layer in an electrolyte is a single layer of the electrolyte molecules attached to the solid electrode, Fig. 2

.3 (a).

The specific capacitance of such a structure is

d c ε = ' , ( 2.1)
where ε is the solvent electrolyte permittivity and d is thickness of the layer, which equals to the molecule diameter.

The specific capacitance is overestimated compared to the experimentally obtained value. For aqueous electrolyte with ε R =78 and d=0.2nm, equations ( 2.1) gives 340µF/cm 2 , what is much greater than the measured value 10µF/cm 2 to 30µF/cm 2 . Also, the model does not take in account that the capacitance is voltage dependent.

In order to describe voltage dependence of the capacitance, Gouy introduced a theory of random thermal motion in 1910, and considered a space distribution of the charge in the electrolyte in proximity of theboundary between the electrolyte and electrode, Fig. 2.3 (b). A few years later, Chapman defined the charge distribution in the electrolyte as a function of linear distance and properties of the electrolyte. The specific capacitance is estimated as

      Ψ = kT q z ch kT n q z c M 2 2 ' 0 2 ε , ( 2.2)
where q is elementary charge, n 0 is the concentration of anions and cations, z is the valence electrolyte ions, ε is the electrolyte permittivity, k is Bolzman' constant, and T is the temperature.

In the model, the charge is considered as point charge (charge density is Dirac function of space). Thus, the specific capacitance is over-evaluated. In 1924 Stern proposed new model which improved Gouy and Chapmen's models. He introduced the real dimension of solvent molecules and then divided the space charge into two layers; compact layer and diffused layer, Fig. 2

.3 (c).

Total specific capacitance is estimated as

D C D C c c c c c ' ' ' ' ' + = , ( 2.3)
where c' C is the compact layer capacitance, and c' D is the diffused layer capacitance defined as

      Ψ = kT q z ch kT n q z c D D 2 2 ' 0 2 ε . ( 2.4)

The Ultra-capacitors Macro (Electric Circuit) Model

In this section, the ultra-capacitor macro model is analysed and discussed. The ultracapacitor macro model is used for the conversion system control analysis and design, as well as evaluation of the ultra-capacitor losses and temperature in different operating modes.

Full Theoretical Model

The traditional model consists of an ideal linear capacitor and equivalent series resistance (ESR). This simple model cannot be used in a super-capacitor model because two phenomena: (1) the capacitance is voltage dependent, and (2) the time/space redistribution of the charge due to porosity of the activated carbon electrodes. The porous electrode structure behaves as a nonlinear transmission line, [START_REF] Belhachemi | A physical based model of power electric doublelayer supercapacitors[END_REF]- [START_REF] Buller | Impedance-Based Simulation Models for Energy Storage Devices in advanced Automotive Power Systems[END_REF]. It is known from theory of electric circuit that an electrically short transmission line can be approximated with N th order RLCG ladder network. At low frequency, below 100 Hz, distributed serial inductance L can be neglected [START_REF] Buller | Impedance-Based Simulation Models for Energy Storage Devices in advanced Automotive Power Systems[END_REF]. Distributed conductance G can be neglected too, except if long term steady state analysis is needed. Thus, an approximated model of an ultra-capacitor having porous electrodes is serial connection of two RC leader networks of N th order, the separator resistance R SP and the current collector resistances R CP and R CN . A schematic diagram of the approximated model is given in Fig. 2.4. Considering that the positive and negative electrodes are symmetric, the circuit in Fig. 2.4 can be reduced to a simple N th order RC ladder network, depicted in Fig. 2.5. Resistances of the equivalent circuit in Fig. 2.5 are ( 2.7)

                        +             =             N CP
                        +             =             N CN CN CN N CN CN CN N N N N N N N N u u u K K K C C C C C C ..
            +             +             + + =             N N N N N P P P CN SP CP N R R R R R R R R R R R R . .
For simplicity of notation, we will use electrical elastance as inverse variable of capacitance to define the capacitances of the equivalent model,

                  +                   =                   N N N N N P P P N C C C C C C C C C . . 2 1 .. 2 1 .. 2 1 1 1 1 1 1 1 1 1 1 M M M .
( 2.8)

Ultra-capacitor Model in Frequency Domain

The circuit of Fig. 2.5 is a nonlinear circuit because the capacitances depend on the voltage. To develop a model in the frequency domain we have to linearize the nonlinear circuit. Expanding ( 2.5) and ( 2.6) into a Taylor series, taking just the zero order members and substituting them into ( 2.8) yields ( 2.9)

                  ⋅ + ⋅ + ⋅ + =                   ⋅ + ⋅ + ⋅ + +                   ⋅ + ⋅ + ⋅ + ≅                   N C N C N C C C C N C N CN N N C CN N C CN N N C N CP N P C CP P C CP P N U K C U K C U K C U K C U K C U K C U K C U K C U K C C C C .. 0 .. .. 0
Now, having a linearizerd mode of the super capacitor ladder network and using the N Extra Element theorem [76] one can develop the ultra-capacitor input impedance Z C0 ω). Since the capacitances are voltage dependent, the developed impedance is a small signal impedance, which is valid just in proximity of the capacitor voltage operating point U C0 .

( )

0 0 0 ) ( 1 ) ( 0 0 C C C C C C U u C U u C U u C C j R j Z = = = + = ω ω ω ω ( 2.10)
As one can see from equation ( 2.10), the super-capacitor equivalent series resistance R C0 and equivalent capacitance C C are frequency dependent properties. The resistance and capacitance are defined for zero frequency (DC operational mode) and high frequency as

∑ = = → = N i i U u C C C C C 1 0 0 ) ( lim ω ω , 1 0 ) ( lim C C C C U u C = = ∞ → ω ω , ( 2.11) ∑ = = → = N i i U u C R R C C 1 0 0 0 ) ( lim ω ω , 1 0 ) ( lim R R C C U u ESR = = ∞ → ω ω . ( 2.12)
To illustrate these properties, a 2500F/2.5V ultra-capacitor cell has been modelled as a 5 th order RC ladder network . The super-capacitor parameters are given in The magnitude and phase of the capacitor input impedance are plotted in Fig. 2.6 (a) and Fig. 2.6 (b). From this plot one can see that the ultra-capacitor behaves as a pure capacitor in the very low frequency range, up to 20mHz. In the high frequency range, let say above 10Hz, the ultra-capacitor bank behaves as a pure resistor. In the mid-frequency range, it behaves as a RC element.

The equivalent serial resistance and capacitance versus frequency were calculated and plotted in Fig. 2.6 (c) and Fig. 2.6 (d). Both resistance and capacitance decrease with frequency. The resistance is high and constant at low frequency up to 200mHz, and then decreases to a minimum value at frequencies above 10Hz. Ratio max/min resistance is approximately 1.6. The equivalent capacitance varies in the same frequency range as the resistance. The ratio max/min capacitance is approximately 10. In the following section we will discuss these properties in more detail.

The ESR versus Frequency

As already mentioned, the ultra-capacitor is not an ideal loss-free device. Whenever current flows through the capacitor, regardless on the conversion process and power flow the ultra-capacitor collectors, porous electrodes, separator and electrolyte. The quantity of energy wasted generally depends on the resistance and current. In power applications, the capacitor current is a varying quantity, depending on charge/discharge cycle. In addition, the capacitor current containes a high frequency component due to switch mode operation of the power conversion unit which charges/discharges the ultra-capacitor. The capacitor current spectra falls in range from, let say mHz up to kHz or tens of kHz. As the equivalent resistance is frequency dependent, the contribution of each spectral component on the losses is different. This is discussed in section 2.4.

The input impedance amplitude versus

The Capacitance versus Frequency

The capacitance varies more significantly with frequency than the resistance. The factor C MAX /C MIN could be up to 10 or more. What are typical implications of this in real power application application? The capacitance variation with frequency means that one needs certain time to store the required energy in the capacitor. If one charges the capacitor with high power, close to maximum, the capacitor voltage will increase fast, and reach the maximum voltage before the capacitor is fully charged. Thus, the full energy capability of the capacitor is not used. In contrast to this, if one charges the capacitor with low power, the voltage increases slowly and the charge is distributed over the entire capacitor. Once the voltage reaches maximum voltage, the capacitor is fully charged, and the energy capability is maximized. From this short discussion one can conclude that the total capacitance is available only at very low frequency, and consequently light load. Fig. 2.7 (a) shows the dynamic specific energy versus pulse width. The ultra-capacitor voltage charge/discharge variation is 10% of the rated voltage. Notice that the specific energy (energy capability) decreases as the pulse width decreases. Variation of the energy capability is due to the frequency dependent capacitance which is caused by the relaxation phenomenon in the porous electrodes [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF], [START_REF] Buller | Modeling the dynamic behaviour of supercapacitors using impedance spectroscopy[END_REF]. There is another factor that limits the ultra-capacitor energy capability. That is voltage drop of the electrode and separator resistance, and porous electrode resistance close to the input. Fig. 2.7 (b) illustrates two different cases. The red plot illustrates the charging process with relatively high charging current, while the blue waveforms illustrate charging process with current, 10% of the previous. This issue could be solved by the control of charge/discharge process, wherein the real capacitor voltage is estimated from the capacitor model and measured input voltage and current. The charge criterion is the voltage across the capacitor terminals, which should not be higher than U C0max . The difference between the steady state voltages U C01 , U C02 represents the difference in the stored energy in the ultra-capacitor for different charging speeds. Considering a linear capacitor with frequency dependent capacitance, one can estimate the difference in energy stored as ∆E.

        ∆ + ∆ = ∆ 0 01 2 0 0 2 1 2 1 C C C U U U C E , ( 2.13)
where ∆U C0 strongly depends on the time profile of the charging current.

Simplified Model

For simplicity of the following analysis, a first order nonlinear model of an ultracapacitor is used. The model takes in account the linear (voltage independent) internal resistance R C0 and total capacitance as a function of the capacitor voltage. Effects of the transmission line are neglected. The internal equivalent resistance R C0 is modelled as a constant and frequency independent resistance. Fig. 2.8 depicts a simplified model of ultracapacitor used in the analysis. The equivalent capacitor consists of a linear capacitor C 0 and parallel connected voltage dependent capacitor C(u C ). The total capacitance of an ultra-capacitor is voltage controlled capacitance defined as ( )

C C C u k C u C ⋅ + = 0 , ( 2.14)
where C 0 is initial linear capacitance which represents electrostatic capacitance of the capacitor, and k C is a coefficient which represent the effects of the diffused layer of the supercapacitor. In case of a hybrid super-capacitor, the coefficient models the Faradic effect and electrochemical processes on one side of the capacitor [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF].

The capacitor current defined is

( ) ( ) ( ) dt du u C dt du du u dC u u C t Q i C C I C C C C C C =         + = ∂ ∂ = .
( 2.15)

The capacitance denoted as C I (u C ) is a virtual capacitance, the so-called current capacitance. Substituting ( 2.14) in ( 2.15) yields ( )

C C C I u k C u C ⋅ + = 2 0 and ( ) dt du u k C i C C C C ⋅ + = 2 0 .
( 2.16)

The Ultra-capacitor Energy Capacity

Energy stored in the ultra-capacitor charged to a voltage u C is

( ) ( ) 2 2 0 2 1 3 4 2 1 C C E C C C C C u u C u u k C u E =       + = .
( 2.17)

The capacitance denoted as C E (u C ) is the so-called energetic capacitance.

The energy available from the ultra-capacitor discharged from the initial voltage U C0max to the final voltage U C0min is ( ) ( ) .18) This equation will be used to compute the energy that can be stored and restored from the ultra-capacitor in real applications. For example, it could be braking energy or ride-through energy in variable speed drive systems. This will be discussed in more detail in chapter 3.

3 min 0 3 max 0 2 min 0 2 max 0 0 3 2 2 C C C C C C U U K U U C E - + - = ∆ . ( 2

The Ultra-capacitor Charge/Discharge Methods

Theoretically, four different power conversion modes are possible; constant voltage, constant resistance, constant current and constant power conversion mode. The first one is not applicable because the ultra-capacitor is some kind of voltage source with an internal resistance. The most important characteristics of the other three conversion methods are briefly discussed in the following section.

Constant Resistive Load

Constant resistive load is the simplest charge/discharge method. The capacitor is charged from voltage source V BUS via a charge resistor R 0 and discharged in the load resistor R 0 . However, because low conversion efficiency this method is rarely used in power applications, and therefore will not be discussed.

Constant Current

The ultra-capacitor can be charged/discharged with a constant current load/source. Constant current load/source is often found in regulated power converters, such as regulated chargers and constant torque driven electric motors.

Discharging

Let the ultra-capacitor initial voltage be U C0 and the ultra-capacitor, and assume the ultra-capacitor is being discharged by constant current I 0 . The capacitor internal voltage declines as ( ) ( )

DIS C C C C C C C T t k C t I k U C U k k C t u < < - - + + = 0 .......... .......... 2 1 4 0 0 2 0 0 0 2 2 0 , ( 2.19)
where the discharge time is ( )

2 0 0 0 0 1 C C C DIS U k U C I T + = .
( 2.20)

Maximum Discharge Power

Maximum power delivered to the load is limited and defined by the capacitor internal resistance R C0 ,

0 2 0 4 C C MAX R u P = . ( 2.21)
The current I 0 is limited and depends on the capacitor voltage u C and the internal resistance R C0 .

MAX

I I 0 0 0 ≤ ≤ where 0 0 C C MAX R u I = ( 2.22)
If the current exceeds the limit, the capacitor terminal voltage u C0 becomes negative and the load changes in the nature and turns to be a source. However, the capacitor is still being discharged. All energy recovered from the capacitor and energy delivered from the current source is dissipated in the capacitors internal series resistance R C0 .

Charging

The ultra-capacitor voltage during the charging process is

( ) ( ) CH C C C C C C C T t k C t I k U C U k k C t u < < - + + + = 0 .......... .......... 2 1 4 0 0 2 0 0 0 2 2 0 .
( 2.23)

The charge time is

        - -         + - - = 2 0 0 0 2 0 0 0 max 0 2 0 0 2 4 1 C C C C C C CH U k U C k C I R U k C I T , ( 2.24)
where U 0MAX is the capacitor terminal voltage.

Maximum Charging Power

In charging mode the current I 0 is negative. Maximum current that can be injected into the ultra-capacitor is limitated by the capacitor terminal voltage U 0MAX ,

0 0 0 C C MAX MAX R u U I - = .
( 2.25)

From ( 2.25) one can define maximum charging power as a function of the capacitor resistance and the capacitor voltage, ( )

0 max 0 max 0 0 C C MAX R u U U P - = .
( 2.26)

Constant Power

In power conversion applications, most of load and sources behave as constant power, either positive or negative. Typical examples of such constant power loads are power converters having regulated output voltage, such as pulse width modulated (PWM) variable speed drives and dc-dc converters. According to the convention on Fig. 2.11, power of the load is defined as

0 0 0 C C C i u P - =
, where power is positive in sink (load) mode and negative in source mode. Fig. 2.11 Charging/discharging the ultra-capacitor with a constant power source.

Discharging

The circuit in Fig. 2.11 is described by the following differential equation,

2 0 4 0 2 0 2 0 0 0 3 0 2 0 0 0       + - = dt di i P C R dt di i P C P C C C C C C C C , ( 2.27)
where the ultra-capacitor is taken as a linear capacitor (k C =0). If the ultra-capacitor is properly selected, the power P C0 is much lower than the matched maximum power,

0 2 max 0 4 C C C R u P P = <<
, and therefore the ultra-capacitor resistance R C0 can be neglected in the analysis. From those two approximations one obtains the ultra-capacitor discharging current

t P U C U C U P i C C C C C C 0 2 0 2 0 0 0 2 - - ≅ , ( 2.28)
where the voltage U C0 is the ultra-capacitor initial voltage. The maximum discharge time is

0 2 0 0 2 C C P U C t ≤ .
( 2.29)

Maximum Discharge Power

Just as in the case of current or resistive discharge, the capacitor maximum power is limited due to internal series resistance R C0 . The maximum power that can be delivered to the load having constant power characteristic is

0 2 0 4 C C MAX R u P = .
( 2.30)

Please note that the maximum power is defined by the capacitor voltage and R C0 , exactly as in the two previous two cases (constant resistance and constant current load). There is however an essential difference. If the load is higher than the maximum power at given the ultra-capacitor voltage, the system becomes unstable and the voltage collapses.

Charging

In the charging mode of an ultra-capacitor, the power of the power source P C0 is negative according to the notation in Fig. 2.11. Using the same method as we used before, but simply applying negative power, we obtain the ultra-capacitor charging current

t P U C U C U P i C C C C C C 0 2 min 0 2 min 0 min 0 0 2 + ≅ , ( 2.31)
where the initial ultra-capacitor voltage is U Cmin .

Maximum Charging Power

In charging mode the power P C0 is negative. Thus, the maximum power stability criteria is not applicable in this case. In other words, the system described by Fig. 2.11 is stable in charging mode regardless on the power P C0 . In a real application, however, there is another limitation that defines maximum power that can be transfered into the ultra-capacitor bank. It is the limitation of the power source maximum voltage U 0MAX , ( )

ESR C MAX MAX MAX R u U U P - = 0 0 0 .
( 2.32)

Frequency Related Losses

As mentioned in section 2.2.1, the ultra-capacitor is a non-linear device, with voltage and frequency dependent properties. In this section, the effect of the frequency dependent resistance on the conversion losses is discussed.

One can distinguish two different frequency ranges in spectrum of the capacitor current. The first one is low frequency, which is related to the capacitor operational mode and cycle. The second one is high frequency current due to the nature of the power converter used to charge/discharge the ultra-capacitor. Low frequency current is normally aperiodic, while high frequency current is periodic, where the basic period is multiple or fraction of the switching period T S .

How to Calculate Total Losses in Case that the ESR is a Function of Frequency?

The serial equivalent series resistance is the frequency dependent resistance. Based on the time to frequency transformations, one can conclude that the resistance is alos time dependent.

( )

ω 0 0 C C R R = ⇒ ( ) t R R C C 0 0 = ( 2.33)
Due to the frequency dependent resistance, instantaneous voltage and current are not linked by a simple coefficient R C0 , ( ) ( )

t i R t u C C ESR 0 0 ⋅ ≠ .
( 2.34)

Considering the excitation current i C0 is sinusoidal function ( )

) sin( 0 0 0 t I t i C C ω =
, one can write that instantaneous voltage and current are linked by a simple coefficient R C0 , where R C0 is the resistance at a specified frequency,

( ) ( ) ( ) ( ) t i R t I R t U t u C C C C ESR ESR 0 0 0 0 0 0 0 0 ) sin( ) sin( ω ω ω ω ω ω ω ω = = = = = .
( 2.35)

Instantaneous power of the resistor R C0 carrying a current i 0 is

( ) ( ) ( ) ( ) ( ) t i t i f t i t u t p ESR 0 0 0 ) ( ⋅ = ⋅ = , ( 2.36) where ( ) ( )
t i f u C ESR 0 =
is the voltage across the equivalent series resistance of the capacitor as a function of the current. This nonlinearity is some kind of hidden nonlinearity, which exists due to the frequency dependent resistance of the capacitor.

Average power calculated over a period T is

( ) ( ) ( ) ( ) τ τ τ d i i f T T P C T t t C AV 0 0 1 ∫ + = .
( 2.37)

where the period T represents the fundamental period in case of periodic function. If the current is non-periodic, T represents the period of observation.

The Current is Periodic Function

Consider the current i C0 is periodic function with a period T 0 , and angular frequency ω 0 . This current can be expanded in a Fourier series:

( ) ( ) ( ) ∑ +∞ = + = 0 0 0 0 sin k k k C C t k I t i ϕ ω . ( 2

.38)

The voltage across equivalent series resistance con also be expanded in a Fourier series ( ) ( ) ( ) ( )

∑ +∞ = + ⋅ = 0 0 0 0 0 sin k k k C C ESR t k I k R t u ψ ω ω , ( 2.39)
where

( ) ( ) ω ω 0 0 0 C C R k R =
is the frequency dependent R C0 of the capacitor. Since the resistor is quasi-linear ( 2.35), the phase displacement for each harmonic is zero, and

k k ϕ ψ =
as a consequence. Inserting ( 2.38) and ( 2.39) into ( 2.36) yields instantaneous power dissipated on the resistor R C0,

( ) ( ) ( ) ( ) ( ) ∑ ∑ +∞ = +∞ = + ⋅ + = 0 0 0 0 0 0 0 0 sin sin ) ( k k k C C k k k C t k I k R t k I t p ϕ ω ω ϕ ω . ( 2.40)
Using the Lagrange identity [START_REF] Kurtz | Handbook of applied mathematics for engineers and scientists[END_REF],

( ) ( ) ( ) ( ) ( ) ( ) ∑∑ ∑ ∑ ∑ +∞ = +∞ = ≠ +∞ = +∞ = +∞ = + = ⋅ = ⋅ 0 0 1 1 0 2 1 0 2 0 1 2 1 n m m n m n k k k k k k k F F F F F F f f , ( 2.41)
where f 1 and f 2 are regular functions which could be expanded in potential series, yields

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ∑∑ ∑ ∞ + = ∞ + = ≠ +∞ = + ⋅ + ⋅ + + - = 0 0 0 0 0 0 0 0 0 0 2 0 0 0 sin sin 2 2 cos 1 2 1 ) ( n m m n m n m C n k k k C t m t n I m R I t k I k R t p ϕ ω ϕ ω ω ϕ ω ω .
( 2.42)

The average power dissipated over a period T is

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ∫ ∑∑ ∑ + ∞ + = ∞ + = ≠ +∞ =             + + ⋅ + + + - = T t t n m m n m n m C C n C k k k C C AV d m n I m R I k I k R T T P τ ϕ τ ω ϕ τ ω ω ϕ τ ω ω 0 0 0 0 0 0 0 0 0 0 2 0 0 0 sin sin 2 2 cos 1 2 1 1 ) ( . ( 2
∑ +∞ = ⋅ = 0 2 0 0 0 2 1 ) ( k k C AV I k R T P ω . ( 2.45)
Please note from ( 2.45), that the total average power depends strongly on the frequency spectrum of the capacitor current. Thus, to estimate total losses one has to take account of the real time profile of the capacitor current.

Low Frequency Current

In the general case, the low frequency current would be either pseudo-periodic or periodic, depending on the application. The dominant time constant and fundamental frequency depends on the charge/discharge cycle and power/current level. This can be expressed as

( ) ( ) C R U P i t i C C LF C LF C , , , 0 0 0 _ 0 _ 0 = .
( 2.46)

Two application examples are illustrated in Fig. 2.12 and Fig. 2.13. The first one is a tooling machine application with intermittent load. The ultra-capacitor is used as an energy storage device to filter peak power from the mains supply. Fig. 2.12 (a) shows an experimental waveform of the ultra-capacitor current and voltage. The current amplitude spectrum is shown in Fig. 2.12 (b). Note that the dominant frequency (first harmonic) is 0.48 Hz and the higher harmonics fall in the mid-frequency range (see example in Fig. 2.6). Hence, the losses have to be computed taking all spectral components of the current and the frequency dependent resistance into account, as given in ( 2.45). Another typical application is a lift or hoisting application with a requirement for braking. The waveforms over one entire cycle are shown in Fig. 2.13 (a), while the amplitude spectrum is shown in Fig. 2.13 (b). In this example, the current fundamental frequency is below the ultra-capacitor mid-frequency range. Therefore the losses can be computed using the total RMS current and that the resistance is constant (frequency independent).

High Frequency Current

The ultra-capacitor high frequency current is the current ripple caused by the power converter used to charge/discharge the ultra-capacitor. The current ripple depends on the power converter topology. This will be discussed in more details in chapter 4. For the moment, we can assume that the power converter is designed in such a way to have the current ripple significantly smaller than the average current (selecting an appropriate topology or adding a low pass filter between the converter and the ultra-capacitor). Also, it is assumed that fundamental frequency of the current ripple is far above the ultra-capacitor cut-off frequency (the capacitance and resistance can be assumed as constant properties).

The Current is Non-periodic Function

Let's consider that the capacitor current is non-periodic function. Typical example is variable speed drive with extended ride-through capability. The ultra-capacitor is employed as the energy storage to supply the drive system in case of short power interruption. An example is illustrated in Fig. 2.14. The waveforms of the ultra-capacitor current and voltage are shown in Fig. 2.14 (a). The ultra-capacitor current and voltage drop on the equivalent resistor R C0 could be represented by Fourier's integrals

( ) ( ) ω ω π ω d e j I t i t j ∫ +∞ ∞ - = 2 1 0 , ( ) ( ) ( ) ω ω ω π ω d e j I j R t u t j C ESR ∫ +∞ ∞ - = 0 2 1 .
( 2.47)

Then, instantaneous power dissipated on the R C0 is

( ) ( ) ( ) ω ω ω ω ω π ω ω d e j I j R d e j I t p t j C t j ∫ ∫ +∞ ∞ - +∞ ∞ - ⋅ = 0 2 4 1 ) ( .
( 2.48)

From the conditions

( ) ∞ < ∫ +∞ ∞ - dt t i 0 and ( ) ∞ < ∫ +∞ ∞ - dt t u ESR it follows that average power is zero 0 ) ( 1 lim 2 2 = = ∫ + - ∞ → T T T AV dt t p T P .
( 2.49)

Please, note that average power ( 2.49) is zero, and as that it has no practical value. However, the question is how to evaluate the ultra-capacitor losses? Is it sufficient to compute the losses or is some other quantity as important? The quantities are important, namely: 1) the energy dissipated on the internal resistor and 2) the module temperature increase.

The Energy Losses

The energy dissipated on the ultra-capacitor resistance is

( ) ( ) ( ) ∫ ∫ ∫ ∫ ∞ ∞ - +∞ ∞ - +∞ ∞ - ∞ ∞ -         ⋅ = = dt d e j I j R d e j I dt t p E t j C t j RESR ω ω ω ω ω π ω ω 0 2 4 1 ) ( .
( 2.50)

The Ultra-capacitor Temperature Increase

The power losses can be computed in the frequency domain from ( 2.47) and using convolution in the frequency domain.

( ) ( ) ( ) ( ) ( ) ( ) ∫ +∞ ∞ - - = υ υ ω υ υ π ω d j I j I j R j p C 0 2 1 ( 2.51) ( ) υ j R C 0
is the ultra-capacitor resistance as a function on the frequency ( 2.10), ( ) υ j I is a spectrum of the ultra-capacitor current and υ is angular frequency.

The ultra-capacitor temperature rise can be computed as

( ) ( ) ( ) ω ω ω π θ ω d e j Z j p t t j ∫ +∞ ∞ - = ∆ 2 1 , ( 2.52)
where ( )

ω j Z
is the ultra-capacitor thermal impedance.

Trends in the Ultra-capacitors Development

Two key features are relevant for the development of new generation of the ultracapacitors: 1) energy density and 2) the internal equivalent series resistance that basically determines the power density. Presently, most commercially available ultra-capacitors have the energy density around 5Wh/kg and a power density up to 20kW/kg [START_REF] Schneuwly | Properties and applications of supercapacitors: From the state-of-the-art to future trends[END_REF]- [START_REF] Halper | Supercapacitor: a brief overview[END_REF], [START_REF] Schindall | New [Old] Technologies for Energy Storage[END_REF]. Existing ultra-capacitors energy density is approximately 5% of the energy density of the broadly used lithium-ion batteries. For most of applications this is not sufficient. There is need for energy densities of 20Wh/kg or more.

Currently, there are four different mainstreams in the ultra-capacitors development: 1) Carbon nano-tube technology, 2) Nano-gate technology, 3) so-called EeStore technology, and 4) Mega farad super-capacitor technology. A summary of all four ongoing ultra-capacitor technologies is given in TABLE 2-3.

A team at Massachusetts Institute of Technology (MIT) led by Professor Joel Schindall has started development of new ultra-capacitor based on carbon nano-tube technology [START_REF] Signorelli | Fabrication and electrochemical testing of the first generation carbon-nanotube based ultracapacitor cell[END_REF], [START_REF] Signorelli | High energy and power density nanotube ultracapacitor design, modelling, testing and predicting performance[END_REF]. An ultra-capacitor based on such an approach could have energy density as high as 25% or even 50% of the energy density of the existing chemical batteries.

Okamura Laboratory and Power Systems have announced first significant development results of new generation of ultra-capacitor based on very promising Nano-gate technology in September 2007 [START_REF] Okamura | The nanogate-capacitor has finally been launched by our factory[END_REF]. The expected energy density is 50 to 80Wh/kg, which is the same order as the existing electrochemical batteries.

The third, quiet different ultra-capacitor technology is so-called EeStore technology, which promises to increase the energy density up to 280Wh/kg, and the operating voltage up to 3000V, [START_REF] Weir | Electrical energy storage unit (EESU) utilizing ceramic and integrated circuit technologies for replacement of electrochemical batteries[END_REF]. These ultra-capacitors are based on high voltage multilayer ceramic technology, and therefore the internal series resistance is expected to be very low compared to the existing technologies.

A recently announced technology is the double layer capacitor with a thin layer of high permittivity material on top of the activated carbon electrode [START_REF] Ezzat | New mega-farad ultracapacitors[END_REF]. Expected energy density is two order of magnitude greater than existing technology, ~500[Wh/kg]. The ultra-capacitor cost is driven by the market, mainly the automotive industry. As the application fields of ultra-capacitors increase so the cost of ultra-capacitors decrease. The cost prediction for 2010 is 1.28US$ per kJ of the stored energy [START_REF] Schindall | New [Old] Technologies for Energy Storage[END_REF], [START_REF] Miller | Ultracapacitor technology: state of technology and application to active parallel energy storage systems[END_REF].

Short Conclusion

In this chapter, the ultra-capacitor as an energy storage device dedicated for power conversion applications has been discussed. In comparison to state of the art electrochemical batteries, the ultra-capacitors have higher power density, higher efficiency, longer lifetime and greater cycling capability. In comparison to the state of the art electrolytic capacitors, the ultra-capacitors have higher energy density. All these advantages make the ultra-capacitors good candidate for many power conversion applications with a need for short term, 0.1 to 15s, energy storage. The applications could be industrial applications, power transmission/distribution network, building and IT centre.

The ultra-capacitor macro model has been discussed. Depending on the application need, a simplified first order or higher order RC model is proposed. The model can be used to estimate the ultra-capacitor losses and temperature. The first order model is sufficient if the ultra-capacitor current frequency is well below or above the transition frequency. Otherwise, a second or even third order model is necessary. The first order model is sufficiently accurate for the interface power converter controllers' analysis and synthesis.

State of the art ultra-capacitor technology is activated carbon double layer capacitor [START_REF] Schneuwly | Properties and applications of supercapacitors: From the state-of-the-art to future trends[END_REF]- [START_REF] Halper | Supercapacitor: a brief overview[END_REF], [START_REF] Schindall | New [Old] Technologies for Energy Storage[END_REF]. Among this, there are four different technologies under development: 1) Nano tube capacitor [START_REF] Signorelli | Fabrication and electrochemical testing of the first generation carbon-nanotube based ultracapacitor cell[END_REF], 2) Nano-gate capacitor [START_REF] Okamura | The nanogate-capacitor has finally been launched by our factory[END_REF], 3) EeStore high voltage multilayer capacitor [START_REF] Weir | Electrical energy storage unit (EESU) utilizing ceramic and integrated circuit technologies for replacement of electrochemical batteries[END_REF], and 4) Mega Farad ultra-capacitor [START_REF] Ezzat | New mega-farad ultracapacitors[END_REF]. All technologies under development promise order of magnitude higher energy density in comparison to the state of the art technology. Some of them, for example technology 3) and 4), promise energy density even greater than state of the art electrochemical batteries.

ULTRA-CAPACITOR BASED REGENERATIVE ELECTRIC DRIVES

Background

In general introduction of the dissertation, application of controlled electric drives and some associated technical issues have been discussed. For the sake of clarity and simplicity, a part of that discussion has been repeated in this chapter.

Modern controlled electric drives are exclusively based on three phase motors, either the induction or permanent magnet (PM) synchronous motors. The motor is powered from a pulse width modulated (PWM) converter, and the converter is supplied from the industrial or distributive mains 230 V to 690V and 50 to 60Hz. Several technical issues in application of such drives are still a big challenge. Two of these issues, namely 1) recovery of the braking energy and 2) the drive ride-through capability, are discussed and a solution is proposed in this chapter.

Most of drive applications, such as lifts, cranes, tooling machines, and so on, are characterized by low balance between average and peak power. Moreover, such applications have a demand for braking at rated power. In ordinary variable speed drives, the mechanical energy of rotating mass of the motor load and the motor shaft is usually dissipated in a brake resistor. The energy losses in such applications can be 20 to 50% of the consumed energy. Nowadays, having in mind energy crisis, this has become an issue that needs a very urgent solution [6].

Modern variable speed drives are sensitive to the mains supply disturbances. The most frequent disturbance is voltage dip/sag [10]. Power interruptions cause drop in the dc bus voltage below the limit, and then the entire drive system trips. The system interruptions are very costly and unacceptable when the drive is applied in critical process industry, oil pump systems or glass industry. Such kind of industry have reported losses ranging from 10k$ to 1M$ per a disrupting event [10].

State of the art solutions can be split into two different groups: 1) back to back PWM rectifiers and 2) direct (matrix) converters [START_REF] Rodríguez | PWM Regenerative Rectifiers: State of the Art[END_REF]- [START_REF] Wheeler | Matrix converters: A technology review[END_REF]. These regenerative drives draw the energy from the mains when operates in motoring mode, and pump the energy in the mains while the drive is in breaking mode. The main disadvantage of such solutions is the fact that functionality of the drive is strongly linked to the mains. In other words, any power interruption of the mains is reflected to the drive, and the drive is disabled whenever the mains is interrupted for longer than one the mains cycle (20ms). Moreover, such kind of drives has a high power demand during acceleration and deceleration. This modulated power produces additional disturbances and losses in weak supply mains.

A basic idea of the regenerative controlled electric drive system using an ultracapacitor as an energy storage device is illustrated in Fig. 3.1. The drive system consists of an ordinary variable speed drive converter (the input diode rectifier, voltage dc link and output inverter) and a parallel connected energy storage device. The rectifier is connected to the three-phase distribution network, while the inverter feeds a three-phase motor (the induction or synchronies PM motor). The energy storage device is composed of an ultra-capacitor C C0 and a bi-directional dc-dc power converter. The energy storage could be another type of storage device, such as flywheel or battery. However, the battery is not an appropriate solution because limited power density, while the flywheel is a system that is more complex in comparison to the ultra-capacitor system.

For generality of the analysis, in the first part of this section the dc-dc power converter will be considered as a controllable bi-directional dc-dc power converter with one input (the dc bus voltage v BUS ) and one output (the ultra-capacitor voltage u C0 ). The dc-dc converter could be, for example, non-isolated two-level or three-level converter, multiphase interleaved converter or an isolated dc-dc converter. The dc-dc converter is controlled by the control variable m that could be duty cycle, phase shift or switching frequency, depending on the converter topology. More details of the dc-dc power converter will be given in chapter 4.

Operational Modes

The drive system whose block circuit diagram is depicted in Fig. 3.1 may operate in six different modes. The modes are illustrated in Fig. 3.2 and Fig. 3.3. The drive system is represented by the rectifier, inverter, dc bus capacitor C BUS , dc-dc converter and the ultracapacitor. The dc bus inductor L BUS is not relevant for this analysis and therefore it is just indicated in the circuit as an inductance between the rectifier and inverter. Fig. 3.4 illustrates relevant waveforms for different operating conditions. The signification of voltages V BUSmax , V BUSmin , U C0max , U C0inM and U C0min that appear in Fig. 3.4 will be discussed shortly after.

MM)

Motoring from the mains is illustrated in Fig. 3.2 (a). The drive operates in motoring mode, being powered from the mains. The dc bus voltage v BUS is slightly lower than the input phase to phase peak voltage. The dc-dc converter controls the ultra-capacitor voltage to U C0inM , in order to prevent energy flow between the ultra-capacitor and the drive dc bus. In this mode, the rectifier voltage v REC is determined by the mains voltage and conduction state of the rectifier diodes, where the diodes state is determined by dc bus filter capacitor, inductor and load [START_REF] Grbovi} | Regenerative controlled electric drive with extended ride-through capability using an ultra-capacitor as energy storage device[END_REF]. B) Braking and energy storing mode is illustrated in Fig. 3.2 (b). The drive operates in braking mode. As the dc bus load is negative (the motor turns to be a generator), the dc bus capacitor is charged and therefore the dc bus voltage v BUS increases. Once it reaches V BUSmax , the dc-dc converter starts to regulate the ultra-capacitor current i C0 in order to regulate the dc bus voltage to V BUSmax . The ultra-capacitor current is positive and the ultra-capacitor voltage increases. The braking energy is stored into the ultra-capacitor. Since the dc-dc converter controller is designed to maintain the dc bus voltage V BUSmax greater than the input phase to phase peak voltage, the drive rectifier is blocked. Thus the drive input current is zero and the rectifier voltage v REC is equal to the dc bus voltage v BUS . The ultra-capacitor is sized to store certain energy during a braking phase. Thus, at the end of a braking phase the ultra-capacitor voltage has to be lower than the maximum rated voltage U C0max .

STB)

Standby mode: There is not energy flow between the drive, mains and ultracapacitor. The ultra-capacitor voltage is constant, taking any value between U C0max and U C0inM . The control system is designed in such a way to maintain the dc bus voltage to V BUSmax whenever the ultra-capacitor voltage is greater than U C0inM . Therefore, if this is case in standby mode, the dc bus voltage will stay constant at V BUSmax . MC 0 ) Motoring and energy recovery mode is illustrated in Fig. 3.3 (a). The drive operates in motoring mode, being powered from the ultra-capacitor. The ultra-capacitor voltage is greater than U C0inM . The dc bus voltage controller acts on the dc-dc converter, in order to maintain the dc bus voltage constant (V BUSmax ). The ultra-capacitor is discharged and its voltage decreases towards the intermediate level U C0inM . The energy is restored from the ultra-capacitor. Once the ultra-capacitor has been discharged to the intermediate level U C0inM , the dc bus voltage falls to the nominal voltage and the drive rectifier diodes start to conduct. The drive is again powered from the mains. RT) Ride-through mode is illustrated in Fig. 3.3 (b). The mains supply is interrupted and the dc bus voltage starts to decrease quickly. Once it has reached the minimum voltage V BUSmin , the dc-dc converter starts to discharge the ultra-capacitor and maintain the dc bus voltage to V BUSmin . The drive is powered from the ultra-capacitor. The ultra-capacitor is discharged deeper below the intermediate level U C0inM towards the minimum level U C0min .

MM-CH)

The ultra-capacitor charging mode is illustrated in Fig. 3.3 (b). The mains supply is recovered and then the ultra-capacitor is recharged to the intermediate level U C0inM .

Definition of the Reference Voltages

Let us now explain the signification of the reference voltages V BUSmax , V BUSmin , U C0max , U C0inM and U C0min . Fig. 3.5 (a) illustrates the signification of the reference voltages V BUSmax and V BUSmin . OBF signifies Over-Braking Fault, while USF signifies the Under Supply Fault. When the system operates in the mains motoring mode, the dc bus voltage takes a value between minimum and maximum input voltage. In order to avoid unnecessary charge and discharge of the ultra-capacitor, the dc bus voltage references V BUSmin and V BUSmax must stay outside of the normal operation range, as shown in Fig. 3.5 (a). On other side, to prevent the system fault, either OBF or USF, the dc bus voltage references must not be in the forbidden regions. Therefore, the reference V BUSmin is located within an interval [USF, Min Input Voltage] while the reference V BUSmax is located within an interval [Max Input Voltage, OBF].

The ultra-capacitor voltage takes value within an interval [U C0max , U C0min ], as shown in Fig. 3.5 (b). The maximum voltage U C0max is determined by the ultra-capacitor rated voltage. This limit must not be exceeded in any case; otherwise the ultra-capacitor will be damaged or even totally destroyed. The minimum voltage U C0min is determined by the current capability of the power converter and the ultra-capacitor; the lower voltage the higher current capability and vice versa. The intermediate voltage U C0inM can take any value between the maximum and minimum, depending on the design criteria (ratio of the braking energy capability to the ridethrough energy availability).

Some Experimental Waveforms

Block diagram of an experimental set-up is depicted in Fig. 3.6. A general purpose variable speed drive ATV71 (5.5kW 400V) was used in the test set up. An ultra-capacitor module of 0.4F rated capacitance and 800V rated voltage was connected to the drive via the custom designed bi-directional dc-dc converter. The converter was controlled by a digital signal processor (DSP) TMS 320F2808 and interfacing analog/digital electronic circuitry (measurement, gate driving and protection). Different operation modes were analysed and some waveforms recorded. The waveforms are depicted and discussed hereafter. Fig. 3.7 (a) shows waveforms of the dc bus voltage v BUS , the drive input current i MAINS , the ultra-capacitor current i C0 and voltage u C0 when the drive operates in motoring/braking/motoring cycle. The drive system runs in motoring mode (MM) being supplied from the mains. The ultra-capacitor voltage is U C0inM , while the dc bus voltage is determined by the mains phase to phase voltage (≈1.41V MAINS ). Once the drive load is inverted, the drive enters in the braking phase (B) and the energy being transferred from the load to the drive dc bus. The dc bus voltage v BUS elevates up to the upper reference V BUSmax and then stayes regulated to that level. At the same time, the input current i MAINS falls to zero. The ultra-capacitor voltage increases and the current decreases (charging/discharging power is roughly constant). When the braking phase is finished, the drive load becomes again positive and the drive enters in motoring mode (MC 0 ), being supplied from the ultra-capacitor. The current i C0 turns negative and the voltage u C0 starts to decrease towards the reference U C0inM . When the ultra-capacitor voltage reaches the reference U C0inM the current droppes to zero and the dc bus voltage falls to the nominal value. The ultra-capacitor discharging is finished and the drive is again supplied from the mains (MM). Fig. 3.7 (b) illustrates the system behaviour when the braking energy is greater than the ultra-capacitor storage capability. In this case the ultra-capacitor is charged to the maximum voltage U C0max before the braking is finished. As the voltage reaches the maximum, charging is stopped to prevent break-down of the ultra-capacitor. The dc bus voltage v BUS starts to increase until reached over-braking protection level and drive system falls into overbraking fault (OBF). Shortly before the ultra-capacitor voltage has reached the maximum, the dc bus voltage started to increase and follow the increase in the ultra-capacitor voltage. This is caused by the dc-dc converter duty cycle saturation (dmax=97.5%). Fig. 3.8 (a) shows the waveforms in case of the mains short interruption. The drive runs in the mains motoring mode (MM). Once the mains is interrupted, the dc bus voltage falls to the minimum reference V BUSmin , and stays at that level regulated by the dc bus voltage controller. The drive operates in the ride-through mode (RT), being supplied from the ultracapacitor. The ultra-capacitor voltage decreases below U C0inM towards U Cimin . Once the mains is recovered after 1.5s, the ultra-capacitor is re-charged to U C0inM (the mains motoring and charging mode (MM-CH)). Fig. 3.8 (b) illustrates a case when the power interruption is longer than the specified. The ultra-capacitor is discharged to the minimum voltage U C0min , and then the ultra-capacitor discharge current i C0 falls to zero. Since the dc bus voltage is not controlled any more, it falls below the limit, and the drive falls into under-supply fault (USF).

Ultra-capacitor Selection and Design

The ultra-capacitor design and selection criterion is based on the three parameters. 1) Rated voltage of the ultra-capacitor module, 2) the ultra-capacitor rated capacitance, and 3) the ultra-capacitor losses and conversion efficiency.

Voltage Rating

The ultra-capacitor module rated voltage depends on the interface dc-dc converter topology. In this analysis we have assumed that the dc-dc converter is a non-isolated direct dc-dc converter with voltage gain not greater than unity u C0 /v BUS ≤1. Therefore, the ultracapacitor voltage cannot be greater than the dc bus voltage. As the ultra-capacitor is charged when the drive dc bus voltage is maximum (the drive is braking), the ultra-capacitor rated voltage U C0max is

max max 0 BUS C V U ≤ . ( 3.1)
The ultra-capacitor minimum operating voltage is determined by the dc-dc converter current capability I C0max and conversion power P 0 , max 0

0 min 0 C C I P U ≥ . ( 3.2)
Very often, the minimum voltage is limited to 40 to 50% of the rated voltage (U C0min =0.4÷0.5 U C0max ).

The Capacitance

Most of the ultra-capacitor models presented in the literature consider a non-linear (the voltage dependent) transmission line or a finite ladder RC network [START_REF] Buller | Modeling the dynamic behaviour of supercapacitors using impedance spectroscopy[END_REF]. For simplicity of the analysis, the transmission line effect is neglected, and a first order nonlinear model depicted in Fig. 3.9 is used [START_REF] Belhachemi | A physical based model of power electric doublelayer supercapacitors[END_REF]. The equivalent series resistance R C0 is the frequency-independent resistance. The ultra-capacitor total capacitance is the voltage-controlled capacitance defined as ( )

C C C C u k C u C ⋅ + = 0 0 , ( 3.3)
where C 0 is the initial capacitance that represents the electrostatic capacitance of the capacitor, and k C is a coefficient that represents effects of the diffused layer of the supercapacitor [START_REF] Conway | Electrochemical supercapacitors, scientific fundamentals and technological applications[END_REF].

C C C C C C U U k U U C E - + - = , ( 3.4)
where U C0max is the ultra-capacitor maximum voltage, which has been defined in ( 3.1) and U C0 is the ultra-capacitor initial voltage. The initial capacitance C 0 for the given braking energy E B and coefficient k C can be computed from ( 3.4) as

( ) ( ) 2 0 2 max 0 3 0 3 max 0 0 2 3 2 inM C C inM C C C B U U U U k E C -       - - = , ( 3.5)
where the ultra-capacitor voltage U C0inM is the intermediate voltage that has been defined in Fig. 3.5 (b). The braking energy E B is ( )

∫ = B t B B dt t P E 0 0 η , ( 3.6)
where η B is efficiency of the entire conversion system, including the motor, drive converter, dc-dc converter and the ultra-capacitor efficiency. Power P 0 (t) is the motor shaft power and t B is braking time.

The ultra-capacitor energy that is available for ride-through cycle is ( ) ( )

3 min 0 3 0 2 min 0 2 0 0 3 2 2 C inM C C C inM C RT U U k U U C E - + - = , ( 3.7)
where U C0min is the ultra-capacitor minimum voltage that has been defined in Fig. 3.

(b).

The ride-through energy E RT , which the ultra-capacitor has to provide to the drive during a power interruption, is ( )

∫ = RT t M RT dt t P E 0 0 1 η , ( 3.8)
where t RT is the ride-through time. η M is efficiency of the entire conversion system, which depends on the motor shaft power P 0 (t) and internal resistance of the ultra-capacitor.

The ultra-capacitor intermediate voltage U C0inM is selected according to the application requirement, for the braking energy capability E B ( 3.6) and the ride-through energy availability E RT ( 3.8). The intermediate voltage U C0inM can be computed from ( 3.5) and ( 3.7) as

RT C C B C RT inM C E E U E U E U + + ≅ 2 min 0 2 max 0 0 , ( 3.9)
where k C ≅0.

Fig. 3.10 illustrates the ultra-capacitor intermediate voltage U C0inM versus braking energy E BR and minimum discharge voltage u C0min . The ultra-capacitor voltages are normalized on the rated voltage U C0max , while the braking energy is normalized on the ridethrough energy E RT . For example, if the ride through energy is 25% of the braking energy (Ebr/Ert=4 on the x axis) and minimum discharge voltage is 50% (the blue trace), the intermediate voltage is approximately 63%.

Current Stress and Losses

The ultra-capacitor current, in general case has two essentially different frequency components: 1) Very low frequency, and 2) high switching frequency current. Very low frequency current corresponds to the energy transfer between the drive dc bus and the ultra-capacitor (braking and motoring from the ultra-capacitor). Considering that the ultra-capacitor is a linear capacitor (k C ≅0.) and neglecting the internal resistance R C0 one can find the ultra-capacitor charging current as

t P U C C P i C C C C 0 2 min 0 0 0 0 0 2 + ≅ , ( 3.10)
where the initial ultra-capacitor voltage is U C0min .

Discharging current has similar form

t P U C C P i C C C C 0 2 0 0 0 0 0 2 - - ≅ , ( 3.11)
where the voltage U C0 is the ultra-capacitor initial voltage. The ultra-capacitor charging/discharging power P C0 is constant.

The ultra-capacitor losses are computed from ( 3.10) and ( 3.11) as ( )

       - + ≅ G DISCHARGIN t P U C C CHARGING t P U C C P R t P C C C C C C C 0 2 0 0 0 0 2 min 0 0 0 2 0 0 2 2 .
( 3.12)

The losses model ( 3.12) is correct only if the frequency of the charging/discharging current is lower that the ultra-capacitor cut-off frequency. Otherwise the losses have to be computed using the method described in section 2.4.2.

High frequency ripple ∆i C0 could be neglected because the ripple is normally quite smaller than the average current. If this is not a case, the additional high frequency losses have to be taken into account.

2

) ( 0 ) ( 0 ) ( RMS C HF C HF C i R P ∆ ≅ , ( 3.13)
where R C0(HF) is the ultra-capacitor resistance at high frequency.

Conversion Efficiency

As given in ( 3.12), the ultra-capacitor losses depend on a few parameters: the series resistance, capacitance and the ultra-capacitor initial voltage. Is it possible to select the ultracapacitor for the losses given as a design parameter? To find answer on this question, let us consider that the ultra-capacitor is charged (braking mode of the drive system) from U C0inM toward U C0max with a constant power P C0 . The losses-time profile and the energy lost during entire charge time can be defined as ( )

t P E U C C P R t P C BR C C C C 0 2 max 0 0 0 2 0 0 2 2 + - ≅ , ( 3.14) BR C C C C T C BR C C C LOSSES E U C U C C P R dt t P E U C C P R E CH 2 ln 2 2 2 2 max 0 0 2 max 0 0 0 0 0 0 0 2 max 0 0 0 2 0 0 - = + - ≅ ∫ , ( 3.15)
where T CH is the ultra-capacitor charge time, in this case the braking time.

The ultra-capacitor resistance depends also on the capacitance. The greater capacitance the smaller resistance ( 3.17)

) ( 0 1 0 C f R C = , 0 ) ( 0 0 1 < ∂ ∂ C C f . ( 3
Charge/discharge (round trip) energy efficiency is ( ) The conversion efficiency versus capacitance and voltage is computed from ( 3.5) and ( 3.18).The module cost is computed using prediction of 1.28 $/kJ for an ultra-capacitor cell. Taking into account that the module cost is approximately twice of the cell cost, we have 2 €/kJ of total stored energy capacity.

        - + - =         - = BR C C BR C BR LOSSES E U C U C C E P E E 2

THREE-LEVEL INTERFACE DC-DC CONVERTER

Background and State of the Art

For the sake of better flexibility and higher efficiency of the controlled electric drive with the ultra-capacitor energy storage, the ultra-capacitor cannot be directly connected to the drive dc bus. An interface power converter is necessary. The converter is controlled in the way depending on the system control objectives: control of the dc bus voltage, the ultracapacitor state of charge, active sharing of the energy between the drive and ultra-capacitor and so on.

Typical dc-dc converter and variable speed drive system is specified as follows:

• The drive is supplied from a three-phase 400V 50Hz industrial network,

• The converter input is the dc bus:

V BUSmin =450V, V BUSmax =800V,
• The converter output is the ultra-capacitor:

U C0min >250V, U C0max =780V,
• The converter output current ripple: ∆i C0 ≤20%,

• Effective switching frequency: f SW_E ≥50kHz,

• Passive components: minimized,

• Efficiency: >95%.

Most of dc-dc converter topologies are based on ordinary two-level single-phase or multiphase interleaved topologies [START_REF] Jih-Sheng | Energy management power converters in hybrid electric and fuel cell vehicle[END_REF]- [START_REF] Ortúzar | Ultracapacitor-based auxiliary energy system for an electric vehicle: implementation and evaluation[END_REF], Fig. 4.1 (a) and (b). The main drawback of these topologies is the fact that the switches are rated for the full dc bus voltage. As the dc bus voltage may go up to 800V, or more, the switches are rated on 1200V. This becomes an issue if the converter switching frequency is high, let us say above 20kHz. Two-level dc-dc converter with soft switching is an alternative [START_REF] Zhang | High-power density design of a soft-switching high-power bidirectional dc-dc converters[END_REF]. This solution offers lower switching losses. However, since the converter operates in discontinuous conduction mode (DCM), the peak current and ripple current are quite greater than of that one operates in continuous conduction mode (CCM). This causes problem of the inductor losses, particularly the core losses. Fig. 4.1 (c) and (d) shows circuit diagrams of single-phase boost-back and buck-boost topology. Those topologies are used in applications that require large variation of the ultracapacitor voltage around the dc bus voltage. Isolated dc-dc converter topologies with soft switching have been analyzed in [START_REF] Inoue | A bidirectional dc-dc converter for an energy storage system with galvanic isolation[END_REF], [START_REF] Ma | A zero-voltage-switching bidirectional dc-dc converter with state analysis and soft-switching-oriented design consideration[END_REF]. These topologies are attractive solution when ratio of the dc bus voltage to the ultra-capacitor voltage is high, greater than 2. If the ratio is lower than 2, the efficiency is lower than efficiency of a non-isolated topology.

Three-Level DC-DC Converter

Three-level converter is well adopted solution in applications with high input voltage and high switching frequency. The switches are stressed on half of the total dc bus voltage. This allow us to use lower voltage rated switches with better switching and conduction performance compared to the switches rated for the full dc bus voltage. Therefore, the converter overall performances, including cost and efficiency, can be significantly better compared to two-level converters, especially when switching frequency is above 20kHz or MOSFETs are used as the switches. The input filter capacitors are series connected and serve as a capacitive voltage divider to split the dc bus voltage v BUS into two equal voltages v C1 and v C2 . The capacitors mid-point is connected to the switching cell mid-point.

Analysis

The switches SW 1A and SW 1B states are determined by a switching function s 1 and the complementary function, while the switches SW 2B and SW 2A states are determined by a switching function s 2 and the complementary function. The switching functions s 1 and s 2 are generated by the pulse width modulators PWM1 and PWM2. The switching functions s 1 and s 2 are

( ) ( ) ( ) ( )              - + ≤ - <       + + ≤ - <       - +       + ≤ - < =              - + ≤ <       + + ≤ <       - +       + ≤ < = 2 1 2 2 , 0 1 2 2 1 & 2 2 , 1 2 1 2 , 0 1 2 1 & 2 , 1 2 2 2 2 2 1 1 1 1 1 d k T T t d k T T k T t d k T d k T T t kT t s d k T t d k T T k t d k T d k T t kT t s SW SW SW SW SW SW SW SW SW SW SW SW SW SW SW , ( 4.1)
where k is an integer The stage A): The converter can be in this stage only if the duty cycles are lower than 1/2. The switches SW 1B and SW 2A are closed, while the switches SW 1A and SW 2B are opened. As the current i C0 is assumed as positive according to the circuit diagram, the currents i 1B and i 2A are negative; the freewheeling diodes D 1B and D 2A are conducting. The output voltage is v OUT =0, and therefore the current i C0 decreases.

0 0 0 0 <         - = C C C L u dt di ( 4.2)
The stage B): The switches SW 1A and SW 2A are closed, while the switches SW 1B and SW 2B are opened. The current i 1A is positive and the current i 2A is negative; the freewheeling diode D 2A is conducting. The filter capacitor C B1 is discharged by the current i 1A . The output voltage is v OUT =v C1 . The current i C0 decreases or increases. It depends on the ultra-capacitor voltage (duty cycle consequently).

( )

   > < < > - = 1 0 1 0 0 1 0 0 0 0 1 C C C C C C C C v u v u u v L dt di ( 4.3)
The stage C): The switches SW 1B and SW 2B are closed, while the switches SW 1A and SW 1B are opened. The current i 2B is positive and the current i 1B is negative; the freewheeling diode D 1B is conducting. The filter capacitor C B2 is discharged by the current i 2B . The output voltage is v OUT =v C2 . The current i C0 decreases or increases, depending on the duty cycle, ( ) The stage D): The converter can be in this stage only if the duty cycles are greater than 1/2. The switches SW 1A and SW 2B are closed, while the switches SW 1B and SW 2A are opened. The switches currents i 1A and i 2B are positive. The output voltage is v OUT =v BUS , and therefore the current i C0 increases.

   > < < > - = 2 0 2 0 0 2 0 0 , 0 , 0 1 C C C C C C C C v u v u u v L dt di . ( 4

(

)

0 1 0 0 0 > - = C BUS C C u v L dt di ( 4.5)
Instantaneous output voltage v OUT can be expressed as

( ) ( ) ( ) ( ) ( ) t s t s v t s v t v C BUS OUT 2 1 1 1 - + = , ( 4.6)
where s 1 (t) and s 2 (t) are the switching functions ( 4.1).

Assuming that d 1 =d 2 =d and v C1 =v C2 =v BUS /2 (this is a case when the converter is well designed and controlled), from ( 4.1)-( 4.5) and Fig. 4.3 follows that ( )

t v T t v OUT SW OUT =       + 2 , ( ) d v dt t v T u BUS T OUT SW C SW = = ∫ 0 0 1 . ( 4.7)
As ( 4.7) shows, the output voltage is periodic function with period T SW /2. That means the effective fundamental frequency of the output voltage v OUT and therefore the output current i C0 is twice switching frequency, f SW-E =2f SW. This has a significant influence on design of the inductor L C0 , as it will be shown in the following section.

Filter Inductor L C0

Two main parameters are relevant for the inductor design: 1) the inductance L C0 and 2) losses P LC0 .

Inductance L C0

To compute the inductance L C0 , peak to peak current ripple ∆i C0max has to be defined. From ( 4.2)-( 4.5) and the assumptions d 1 =d 2 =d and v C1 = v C2 =v BUS /2 one finds the current ripple as a function of the duty cycle d,

( ) ( ) ( )( )        ≥ - - ≤ - = ∆ 2 / 1 , 1 1 2 2 2 / 1 , 2 1 2 0 0 0 d d d f L v d d d f L v d i SW C BUS SW C BUS C . ( 4.8)
Maximum of the current ripple is ( )

16 0 4 / 3 4 / 1 0 max 0 SW C BUS d d C C f L v d i i = ∆ = ∆ = = .
( 4.9)

From ( 4.9) one finds the inductance L C0

16 max 0 max 0 SW C BUS C f i V L ∆ ≥ , ( 4.10)
where the dc bus voltage (input voltage) is maximum voltage v BUS =V BUSmax . The current ripple ∆i C0max is given as a design criterion.

Please note that the inductance ( 4.10) is 25% of the inductance of two-level dc-dc converter for the same current ripple ∆i C0max and the same switching frequency f SW . That means the inductor volume is 25% of that of the conventional converter. Fig. 4.4 shows the current ripple versus duty cycle for the ordinary two-level converter and the three-level converter. ). The ripple is normalized on the maximum current ripple when two-level dc-dc converter is used.

The Inductor Losses

The inductor losses consist of the copper (winding) losses and the core losses. Both of them depends on the inductor instantaneous current. The inductor current can be expressed as

( ) ( ) ( ) ( ) ( ) ∑ ∞ = + + = 1 2 2 0 0 0 2 sin n n SW nf C DC C C SW SW t n I I t i ω ϕ ω , ( 4.11)
where

SW SW f π ω 2 =
. The converter switching frequency is SW f and n is the harmonic order.

The copper losses can be found in a general form

( ) ( ) ∑ = = n n f n Cu n RMS C CU SW R I P 0 2 2 0 , ( 4.12)
where R Cu(n) is the inductor winding resistance that depends on the frequency.

The core losses can be defined in similar way,

( ) ( ) ∑ = ≅ n n f n C n RMS C C SW R I P 0 2 2 0 , ( 4.13)
where R C(2nfsw) is the core equivalent resistance that models the core losses as a function of the frequency [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]- [START_REF] Venkatachalam | Accurate prediction of ferrite core loss with non sinusoidal waveforms using only Steinmetz parameters[END_REF]. Here we have to highlight that the core losses model ( 4.13) is an approximation of the real core losses [START_REF] Roshen | A practical, accurate and very general core loss model for nonsinusoidal waveforms[END_REF]. The core losses model ( 4.13) was extensively discussed in [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]. Experimental verification of ( 4.13) was also given.

The inductor losses model ( 4.12) and ( 4.13) takes into account harmonics of the inductor current. To simplify analysis, one can substitute the current ripple by an equivalent sinusoidal current with the RMS value and frequency same as the total current ripple. Such an approach is not completely correct, but it is sufficient for simplified calculation.

RMS value of the equivalent sinusoidal current ripple is

( ) ( ) ( )( )    ≤ ≤ - - ≤ ≤ - ∆ ≅ 1 2 / 1 , 1 1 2 2 / 1 0 , 2 1 3 4 max 0 2 0 d d d d d d i I C f RMS C SW , ( 4.14)
where ∆i C0max is the current ripple ( 4.9).

The inductor average current (dc component) is computed from output power P C0 and the ultra-capacitor voltage u C0 as

d v P u P I BUS C C C C 0 0 0 0 = = . ( 4
     ≤ ≤ - - ≤ ≤ - ∆ + +         ≅ 1 2 / 1 , 1 1 2 2 / 1 0 , 2 1 3 16 , 2 2 2 2 2 max 0 2 2 2 0 0 0 d d d d d d i R R d v P R d P P C f C f Cu BUS C DC C LC SW SW , ( ) ( ) ( ) ( ) ( ) ( ) ( )
where R DC is the inductor resistance at low frequency, while R Cu(2fsw) and R C(2fsw) are the inductor winding resistance and the core equivalent resistance at twice switching frequency.

Filter Capacitors C B1 , C B2

The filter capacitors are designed for two main criteria: 1) the capacitors peak and RMS current, and 2) the input voltage ripple. For simplicity of the analysis one can neglected the current ripple (∆i C0 ≅0), and assume that d 1 =d 2 =d and v C1 =v C2 =v BUS /2 . Fig. 4.5(a) illustrates waveforms of the currents i C1 , i C2 and the voltages v C1 , v C2 , when d<1/2. Fig. 4.5 (b) illustrates the case when d>1/2. The capacitors current and the voltage ripple are periodic functions with a period T SW =1/f SW .

Peak and RMS Current

From Fig. 4.5 one can define the capacitors instantaneous current as follows

( ) ( ) ( ) ( ) ( ) ( ) t s d i t i t s d i t i C C C C 2 0 2 1 0 1 - = - = .
( 4.17)

As the dc-dc converter is loaded by constant power P C0 , the capacitors current has to be defined as a function of the power P C0 and the ultra-capacitor voltage u C0 . Using the assumption ∆i C0 ≅0 and substituting ( 4.7) and ( 4.15) into ( 4.17) yields the peak current ( ) ( 4.20)

        - = = min min 0 max 2 max 1 1 , 1 max d d v P i i BUS C peak C peak C , ( 4
The capacitors losses are ( )

ESR BUS C C C R d d v P P P min min 2 0 1 1 1-         = = , ( 4.21)
where R ESR is the capacitors equivalent series resistance.

Input Voltage (DC Bus Voltage) Ripple

For this analysis, the filter capacitors are taken as identical, C B1 =C B2 =C. The input voltage peak to peak ripple is

( ) ( ) ( ) ( )      ≥ - - ≤ - = ∆ 2 / 1 , 1 1 2 2 / 1 , 2 1 2 0 d d d d d d f Cv P d v SW BUS C BUS . ( 4.22)
Comparison of the input voltage ripple of an ordinary two-level and the proposed three-level dc-dc converter is given in Fig. 4.6 The voltage ripple is computed for the same conditions: the capacitance C, output power P C0 and switching frequency f SW . As seen from the graph, the three-level converter ripple is quite lower than that of two-level converter. The ripple ratio depends on the duty cycle range. If the duty cycle is in a range 1/2 to 1, the voltage ripple of the three-level converter is roughly 20% of that of two-level converter. That means the filter capacitor can be five times smaller than that of two-level converter for the same voltage ripple ∆v BUS . Maximum of the input voltage ripple is

( ) ( )      ≥ - ≤ - = ∆ = 2 / 1 2 2 3 2 / 1 2 1 2 2 2 min 0 max d d d f Cv P v d SW BUS C BUS . ( 4.23)
The capacitance C is computed from ( 4.23) as

( ) ( )         ∆ - ∆ - ≥ SW BUS BUS C SW BUS BUS C f v v P f v v d P C 2 2 2 3 , 2 1 max max 0 max min 0 . ( 4.24)

Design and Selection of the Active Components

Advanced Semiconductor Switches

The most common power semiconductor switches used in switch mode power converters are Si based insulated gate bipolar transistor (IGBT), metal oxide semiconductor field effect transistors (MOSFET) and PiN diodes [START_REF] Baliga | Fundamentals of power semiconductor deices[END_REF]. In last decade, we have seen intensive development of SiC based power semiconductor switches, such as Schottky barrier diode (SBD) and junction filed effect transistor (JFET) [START_REF] Baliga | The future of power semiconductor devices technology[END_REF]. Fig. 4.7 illustrates comparison of performance of the most used semiconductor switches. The conduction losses (on-state voltage V CON ) and switching losses of three types of active switches, Si IGBT, Si MOSFET and SiC JFET are compared at two different voltage rating, 600V and 1200V. Comparison is illustrated in Fig. 4.7 (a). Regarding overall performance, switching and conduction, in both voltage ranges the SiC JFET is superior. 600V rated MOSFET and IGBT have similar conduction performances, while the MOSFET is superior regarding switching performance. In 1200V range, the MOSFET has superior switching performance in comparison to the IGBT. The situation for conduction performance is opposite; the IGBT is superior. Here, we have to highlight that technology of 600V and 1200V MOSFET is different. In 600V range, super-junction technology is dominant [START_REF] Lorenz | Matched pair of CoolMOS transistor with SiC schottky diode-advantages in applications[END_REF]. This technology offers significant improvement of the switch conduction performance. However, there is not possibility to implement the super-junction technology in 1200V range. 600V and 1200V rated Si PiN and SiC SBD switching diodes are compared. Note that switching losses of SiC SBD are quite lower than that of Si PiN diode. The difference in onstate voltage is less significant. SiC PiN diode is not considered because such type of diode is applicable in very high voltage rather than in low voltage applications.

Voltage Rating

The switches and diodes voltage rating is defined by the switch transient blocking voltage

( ) ( ) ( ) V v V V BUS D SW ∆ + = = 2 max max max , ( 4.25)
where ∆V is the commutation over-voltage [START_REF] Grbovi} | Feed forward control of turn off performances of an IGBT in short circuit conditions[END_REF].

Since the switch voltage rating is a half of the dc bus voltage, a device rated for 500 to 600V can be used. It could be either 550V CoolMOSFET or 600V IGBT. The first one offers better switching and similar conduction performance compared to the IGBT [START_REF] Lorenz | Matched pair of CoolMOS transistor with SiC schottky diode-advantages in applications[END_REF]. However, the intrinsic FWD of the CollMOSFET has inferior characteristics in comparison to the PiN diode used in the IGBT module. This issue could be solved by the use of some complex topology, but it cause additional expenses and losses. Thus, 600V IGBT with an integrated FWD is used as the switch.

Conduction and Switching Losses

The switches and diodes output characteristics are approximated by the first order functions ( ) ( )

SW SW SW SW SW SW SW SW SW SW i r V i i i F V i v v + = ∂ ∂ + ≅ = 0 0 , ( ) ( ) D D D D D D D D D D D i r V i i i v V i v v + = ∂ ∂ + ≅ = 0 0 , ( 4.26)
were V SW0 and r SW are the IGBT threshold conduction voltage and dynamic resistance. V D0 and r D are the freewheeling diode (FWD) threshold conduction voltage and dynamic resistance.

The switch and FWD conduction losses can be computed from ( 4.26) as

2 ) ( ) ( 0 0 ) ( 1 RMS SW SW AV SW SW SW T SW SW CON SW I r I V dt i v T P SW + ≅ = ∫ , 2 ) ( ) ( 0 0 ) ( 1 RMS D D AV D D D T D SW CON D I r I V dt i v T P SW + ≅ = ∫ . ( 4.27) Commutation losses are ( ) ( ) ( ) ( ) SW SW N N ON ON SW OFF SW OFF SW ON ON SW ON SW ON SW SW SW i v I V E E f i v E i v E T P + ≅ + = ) ( ) ( ) ( ) ( ) ( , , 1 , D D N N Q SW SW D i v I V E f P ≅ ) ( , ( 4.28)
where E ON , E OFF and E Q denotes turn on, turn off and reverse recovery commutation energy, which are given at the rated voltage V N , current I N and 125°C junction temperature.

Let us consider that the current i C0 is positive (the ultra-capacitor is charged). The switches and freewheeling diodes current is determined by the current i C0 and the switching functions s 1 and s 2 as follows,

( ) ( ) ( ) ( ) ( ) ( ) 0 1 1 0 0 0 2 2 0 2 1 0 1 1 2 0 2 2 1 1 0 1 = - = - = = = = = = B D C A D C B D A D C B SW A SW B SW C A SW i t s i i t s i i i t s i i i i t s i i . ( 4.29)
The losses are computed from ( 4.15), ( 4.27), ( 4.28) and ( 4.29) as ( ) ( ) If the current is negative (the ultra-capacitor is discharged), the losses have the same form as ( 4.30) and ( 4.31) but redistributed to the complementary devices. When the duty cycle is varying in time, as it is a case when the ultra-capacitor is charged/discharged, the total loses profile can easily be computed from ( 4.30) and ( 4.31) substituting the ultra-capacitor current profile ( 3.10) and ( 3.11).

0 2 1 2 1 0 2 2 0 0 0 2 1 = = + +         + = = A SW B SW SWITCHING SW OFF ON N N C CONDUCTION BUS C SW BUS C SW B SW A SW P P f E E d I V P d v P
0 2 1 1 2 1 0 2 2 0 0 0 1 2 = = + -         + = = B D A D SWITCHING SW Q N N C CONDUCTION BUS C D BUS C D B D A D P P f E d I V P d d d v P r v P V P P 4 4

The DC-DC Converter Design Example

A 5.5 kW prototype was designed (see Fig. 4.8) and the proposed bi-directional dc-dc converter experimentally verified. The converter specification and parameters of the selected main components are given in TABLE 4-1. Active power components (IGBTs and FWDs) were selected for the target switching frequency, dc bus voltage and ultra-capacitor current. The filter inductor L C0 and input filter capacitors C B1 and C B2 were designed and selected according to the specification in TABLE 4-1 and the criteria ( 4.10) and ( 4.24). R DC is the winding resistance at low frequency and R AC is the winding resistance at switching frequency, which was computed taking the high frequency resistance factor of 20 [START_REF] Shen | Design of high-density transformers for high-frequency high-power converters[END_REF]. The resistance R C is the core equivalent resistance as a model of the core losses ( 4.16). The core resistance was computed at the inductor rated current, using the manufacture datasheet [103].

The inductor losses were computed from ( 4.16) and the parameters in TABLE 4-1. Fig. 4.9 (a) shows 3-D graph of the total inductor loses versus output power and duty cycle. As seen, the core losses are dominant in most of the operating region. The core losses and the total losses reach a peak at duty cycle of d=3/4 and d=1/2 and full load. The first peak corresponds to the maximum current ripple ( 4.9) (and core losses), while the second one corresponds to the maximum conversion power (and low frequency copper losses).

The IGBTs and FWDs losses were computed from ( 4.30), ( 4.31) and data given in TABLE 4-1. Fig. 4.10 shows 3-D graph of the total losses (switching and conduction) versus conversion power and duty cycle, where the duty cycle corresponds to the ultra-capacitor voltage. As seen from the graph, the losses reach maximum of roughly 125W at the maximum output power P OUT =5500W and minimum duty cycle d=1/2. Fig. 4.13 shows the converter efficiency versus output power and duty cycle. This calculation shows that the converter efficiency is quite high, from 95% (at minimum output power of 550W and duty cycle of 3/4) up to 99% at minimum output power and maximum duty cycle (d=1). In this calculation, the filter capacitors C B1 and C B2 losses and the control circuit and gate drivers' losses were neglected. The filter capacitors losses are quite small, below 1W in the worst case (d=1/2 and maximum power). The control circuit and the gate drivers' losses were not calculated.

MODELING ASPECTS AND CONTROL SCHEME

Modelling Techniques

In last two decades we have seen much research activities in field of modeling of switching mode power converters [START_REF] Erickson | Fundamentals of Power Electronics[END_REF]- [START_REF] Vorperian | Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: Continuous Conduction Mode[END_REF]. To give background of these modeling techniques, let us consider a power converter whose circuit diagram is depicted in Fig. 5.1. The converter consists of an input voltage source v IN , a linear and time invariant passive network, a switching network, a vector of control variables and an output load given as constant current i 0 . The switching network terminal variables are v 1 , v 2 , i 1 and i 2 .The input variables are v IN and i 0 , and output variables are v 0 and i IN . The control variables can be duty cycle as wewll as switching frequency. In case of more complex converters, such as fullbridge phase shifted converters, the control variable can be phase shift of the bridge driving signals. The terminal variables (v 1 , v 2 , i 1 and i 2 ) are periodic signals with the period equal to the control signal period (as given in Fig. 5.1 (b)). Therefore, the terminal variables can be expanded in Fourier series.

( ) ( ) (

)

∑ +∞ = + = 0 1 1 1 2 sin ) ( k sw k f k k V t v ϕ π ( ) ( ) ( ) ∑ +∞ = + = 0 2 2 2 2 sin ) ( k sw k f k k V t v ϕ π ( 5.1) ( ) ( ) ( ) ∑ +∞ = + = 0 1 1 1 2 sin ) ( k sw k f k k I t i ψ π ( ) ( ) ( ) ∑ +∞ = + = 0 2 2 2 2 sin ) ( k sw k f k k I t i ψ π
( 5.

2)

The analysis could be simplified if the following assumptions are made: • The linear & time invariant passive network is essentially a low pass filter, and

• Dominant time constant of the linear passive network is much greater than the switching period, T SW <<T 0 .

The terminal variables now can be approximated by first element of the Fourier series. The first elements of the Fourier series are average value computed over a switching period, so-called local or moving average variables [START_REF] Wong | The method of double averaging: an approach for modeling power factor correction switching converters[END_REF].

τ τ d v T t v SW T t t SW ∫ + = ) ( 1 ) ( 1 1 τ τ d v T t v SW T t t SW ∫ + = ) ( 1 ) ( 2 2 ( 5.3) τ τ d t i T t i SW T t t SW ∫ + = ) )( ( 1 ) ( 1 1 τ τ d i T t i SW T t t SW ∫ + = ) ( 1 ) ( 2 2
( 5.4) Note: The switching period T SW is not necessarily constant.

The switching network variables are generally multi-frequency variables. In such a case, multi-dimensional Fourier series can be applied to obtain multi-frequency moving average value [START_REF] Caliskan | Multifrequency averaging of DC-DC converters[END_REF]. Typical power converters that show such behavior are power factor correctors.

The voltage 1 v and current 2 i are commonly treated as dependent variables, which are nonlinear functions of voltages 2 v , IN v , 0 v , the currents 1 i , IN i , 0 i and the control variables

) (t d and ) (t f SW . ( ) ( ) ( ) t t f t d i i i v v v F t v SW IN IN , , , , , , , , ) ( 0 1 0 2 1 1 = , ( ) ( ) ( ) t t f t d i i i v v v F t i SW IN IN , , , , , , , , ) ( 0 1 0 2 2 2 = , ( 5.5)
where nonlinear function F 1 and F 2 ( 5.5) depends strongly on the converter topology and operation mode, continuous conduction mode (CCM) or discontinuous conduction mode (DCM).

To perform transient analysis, nonlinear equations ( 5.5) are linearized around the steady state. The nonlinear equations ( 5.5) can be expanded in multidimensional Taylor series. Neglecting higher order elements yields a linarized equation that describes the switching network.

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t f t f F t d t d F t i i F t i i F t i i F t v v F t v v F t v v F t v SW SW IN IN IN IN ) ) ) ) ) ) ) ) ) ) ( ) ( 1 1 0 0 1 1 1 1 1 0 0 1 1 2 2 1 1 ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ ≅ ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t f t f F t d t d F t i i F t i i F t i i F t v v F t v v F t v v F t i SW SW IN IN IN IN ) ) ) ) ) ) ) ) ) ) ( ) ( 2 2 0 0 2 2 1 1 2 0 0 2 2 2 2 2 2 ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ + ∂ ∂ ≅ , ( 5.6)
The circuit given in Fig. 5.1 can be now analyzed as a standard linear circuit. Linear differential equations in time domain or unilateral Laplace transformation in complex domain are used. The output variables, in this case ac components of the output voltage v 0 and the input current i IN are determined as a function of ac components of the input voltage, output current, duty cycle and switching frequency, as expressed in matrix form ( 5.8)

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 4
s i s v s G s G s G s G s f s d s G s G s G s G s i s v             +             =       0 0 00 0 0 0 0 , ( 5
Remark: This approach is not completely correct. The small signal model is developed assuming that an instantaneous variable could be de-composed in one variable that is constant over time (steady state or equilibrium point) and one superimposed ac variable. Frequency of that ac variable must be lower than the Nyquist frequency, in this case half of the switching frequency. Applying the Laplace transformation, however, does not give any limitation of the signal spectra. It means that the signal could be any regular signal having the Laplace transformation, including the step function and even the Dirac function. This is in contradiction with the first assumption of using small signal model; limited spectra of the superimposed small signal.

The DC-DC Converter Model

Large Signal Model

Assuming that v BUS =const, the circuit in Fig. 5.2 can be described by the following set of equations, (

BUS C C C C C B B C B B C B B C C LC C C C C C v v v i i d d i C i i d d i C C dt v d i R u d v d v dt i d L B B + ∆ = - + - = - + - + = ∆ - - + = = = 2 1 1 2 1 1 2 1 2 0 1 2 1 2 0 2 1 0 0 0 2 2 1 1 0 0 2 1 , ) ( ) ( ) ( ) ( ) ( ) ( )
where

2 1 C C C v v v - = ∆
, and i B1 and i B2 are the filter capacitors leakage current.

Duty cycles d 1 and d 2 are modulation signals (PWM 1 and PWM 2 ), which are generated by a non-linear controller, where the control law is

d v u u d d v u u d BUS C BUS C ∆ - + = ∆ + + = 0 0 2 0 0 1 .
( 5.10) u 0 is the main control variable, while ∆d is the balancing duty cycle as an auxiliary control variable. u C0 is the ultra-capacitor voltage and v BUS is the dc bus voltage. The control variable u 0 is generated by the current controller, while ∆d is generated by the voltage error controller (∆v C ). This is discussed shortly after in section 5.5.2. Substituting ( 5.10) into ( 5.9) yields .11) where ∆i B =i B1 -i B2 .

B C C C LC C C C i C d i C dt v d i R d v u dt i d L ∆ - ∆ - = ∆ - ∆ ∆ + = 1 2 0 0 0 0 0 0 . ( 5

Linearization and Small Signal Model

The state and control variables of the system ( 5.11) are approximated by the first order perturbation model

{ 0 0 0 0 0 0 0 û U u i I i d D d v V v i I i B B B C C C C C C + = ∆ + ∆ = ∆ ∆ + ∆ = ∆ ∆ + ∆ = ∆ + = ≅ .
( 5.12) Substituting ( 5.12) into ( 5.11) yields small signal model

{ 0 0 0 0 0 0 0 0 1 2 2 ˆ≅ ∆ - ∆ - ∆ - = ∆ - ∆ ∆ + ∆ ∆ + = B C C C C LC C C C C i C i D C d I C dt v d i R v D d V u dt i d L .
( 5.13)

Circuit diagram of the small signal model is depicted in Fig. 5.3. Appling Laplace transformation on ( 5.13) yields the system transfer functions in a matrix form

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) s i G G s d s u s G s G s G s G s v s i B vCB B iC CONTROL d vC vCu d iC u iC OUT C C ∆       +       ∆       =       ∆ ∆ ∆ 0 0 0 0 0 0 0 4 3 42 1 4 3 42 1 , ( 5.14)
where the transfer functions are

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 0 0 2 0 0 0 0 0 2 0 0 2 0 0 0 2 0 0 2 0 0 0 0 2 0 0 2 0 0 0 0 0 2 2 2 2 2 2 2 0 0 D sCR C L s V D I R I sL s d s v G D sCR C L s D s u s v G D sCR C L s DI V sC s d s i G D sCR C L s sC s u s i G LC C C C LC C C s u C d vC LC C s d C vCu LC C C C s u C d iC LC C s d C u iC ∆ + + ∆ ∆ + + - = ∆ ∆ = ∆ + + ∆ - ∆ = ∆ + + ∆ - ∆ = ∆ = ∆ + + = = = ∆ = ∆ = ∆ = ∆ .
( 5.15)

The capacitors leakage current ∆i B is not included in transfer function ( 5.15) because this current is not dynamic variable (the capacitors leakage current is constant

0 ˆ≅ ∆ B i
). However, the leakage current has to be taken into account when computing steady state balancing duty cycle ∆D. ( 5.15). This model will be further used for synthesis of the current controller (i C0 ) and the input voltage error controller (∆v C ). The transfer functions ( 5.15) are second order functions, wherein the nominators and denominator coefficients depend on the steady state variables: ∆V C , ∆D, U 0 and I C0 . If the system is well designed and controlled, the steady state voltage balancing error is

0 = ∆ C V
. Furthermore, from ( 5.11) follows that the duty cycles d 1 and d 2 in steady state must be equal, and therefore 0 = ∆D . This is a case only if the filter capacitors leakage current can be neglected (∆i B =i B1 -i B2 =0), for example when high quality film capacitors are used. If electrolytic capacitors are used, leakage current has to be taken into account. In that case, steady state balancing duty cycle is given by ( 5.16).

Substituting conditions

s u s i G C u iC 0 0 0 0 = , c) ( ) ( ) s d s v G C d vC ∆ ∆ = ∆ , and d) ( ) ( ) s d s i G C d iC ∆ = ∆ 0 0 , ( ) ( ) s u s v G C vCu 0 0 ∆ = .

The DC Bus Circuit Model

In this section, general case of the dc bus load model is discussed. Then, PWM fed variable speed drive is analysed as an application example.

A General Case

In real applications, such as lose-less power conversion, the dc bus load is more complex than a simple current source. It could be also constant resistance and constant power as well as a combination of all the three loads. This could be an essential issue for the system control, particularly the dc bus voltage and overall system stability. To cover all these cases, we shall consider a generic load composed of constant power P LOAD , constant current I LOAD and a passive resistive load R LOAD , as given in Fig. 5.5, [START_REF] Liu | Negative input resistance compensator for a constant power load[END_REF]- [START_REF] Wang | A power shaping stabilizing control strategy for dc power systems with constant power loads[END_REF]. The dc bus filter is modelled by an ideal capacitor C BUS and equivalent series resistance R ESR . The dc bus supply is indicated by a current i BUS .

From Fig. 5.5 we have the load

equivalent current i L_E BUS LOAD BUS LOAD LOAD E L v p v R i i + + = 1 _ . ( 5.18)
Linearization around an equilibrium point yields steady state (DC component) variables

BUS LOAD LOAD BUS LOAD E L V P R V I I + + = _ , ( 5.19)
and small signal variation (ac component) around the steady state

LOAD BUS BUS BUS LOAD LOAD LOAD E L p V v V P R i i ) ) ) ) 1 1 2 _ +         - + = .
( 5.20)

P LOAD -R L_E graph for different type of load, active constant power load and passive resistive load is given in Fig. 5.6. As seen from Fig. 5.6, the load incremental resistance (small signal resistance) is negative if the load is positive constant power, while the resistance is positive when the load is either passive resistive load or negative constant power load.

PWM Inverter fed Variable Speed Drives as DC bus load

Basically, two different operational modes of a variable speed drive can be distinguished, namely constant power and constant torque mode. Most of today's drives work in constant power mode thanks to accurate control of the speed. Typical examples are lifts in constant speed mode, conveyers, pumps fans, and so on. There are, however, some applications with constant torque control. Typical examples are high performance servo positioning drives, such as robot applications, tooling machines and so on. In such applications the shaft speed is varying while to torque is controlled by an inner control loop. However, even in this case, the inverter behaves as a constant power load. The inverter output voltage is controlled to be constant, controlling the inverter duty cycle. Therefore, on short term scale in order of several 100ms, the inverter output power is constant too. If the inverter losses can be neglected, as it is case when the inverter is well designed, the inverter input power (dc bus power) is constant too, regardless on the input voltage (dc bus voltage) variation.

The Entire Conversion System Model

Large Signal Model

The large signal (nonlinear) model of the entire power conversion system is depicted in Fig. 5.7. The input rectifier is modeled by a voltage source v REC , diode D R and filter inductor L BUS . Here, we consider that the drive operates in braking or motoring mode from the ultra-capacitor. In that case the dc bus voltage is boosted, being greater that the input voltage, and therefore the input rectifier diodes are blocked. Thus, the input voltage v REC , diode D R and inductor L BUS can be dropped from the model. This is indicated by the dashed lines in Fig. 5.7 (a). The dc bus capacitor is modeled by an ideal capacitor C BUS and its equivalent series resistance R ESR . The dc bus load, in this case a controlled electric drive, is modeled by a constant power load p LOAD .

The bi-directional dc-dc converter is modeled by a loss-free power converter with an input (v BUS ) and an output (u C0 ). The input is modeled by a power source p C0 that is connected on the dc bus side. The output is modeled by a current source i C0 that is connected on the ultra-capacitor side. Details are shown in Fig. 5 The dc-dc converter contains an inductor L C0 that is carrying the current i C0 . The input to output instantaneous power balance is

dt di L i i u p C C C C C C 0 0 0 0 0 0 + = .
( 5.21)

However, if the dc-dc converter is designed in such a way to have switching frequency quite greater than bandwidth of the dc bus voltage control loop, the effect of the inductance L C0 can be neglected, and therefore it can be assumed that

0 0 0 →       dt di L C C
.Thus, the input instantaneous power is equal to the output instantaneous power,

0 0 0 C C C i u p = .
( 5.22)

Without losing generality of the analysis, one may consider that the current i C0 is well controlled by an inner current controller and as that the current i C0 will be taken as the system control variable.

0 0 0 C C C C i R u u + = ,         + - = BUS LOAD BUS C ESR B BUS v p v p R v v 0 .
( 5.25)

Linearization and Small Signal Model

Applying Taylor series expansion ( 5.6) or the first order perturbation model ( 5.12) on ( 5.23), ( 5.24) and ( 5.25) yields a linear model,

( ) ( ) C C C C C C C C C u U k C I k i U k C dt u d ) ) ) 2 0 0 0 0 2 2 2 1 + - + = , ( 5.26) p V v V P I U i V U u V I dt v d C BUS BUS BUS LOAD C C C BUS C C BUS C B BUS ) ) ) ) ) 1 2 0 0 0 0 0 0 - + + - - = , ( 5.27) 0 0 0 C C C C i R u u ) ) ) + = ,         + + - + - = p V v V P I U i V U u V I R v v BUS BUS BUS LOAD C C C BUS C C BUS C ESR B BUS ) ) ) ) ) ) 1 2 0 0 0 0 0 0 .
( 5.28)

where a variable

x X x ) + = 0
is represented by the steady state 0 X and a small variation x ) around the steady state.

Applying Laplace transformation on ( 5.26)-( 5.28) yields the transfer functions in a matrix form, The ultra-capacitor current to voltage transfer functions is

( ) ( ) ( ) ( ) ( ) ( ) ( ) 4 4 3 4 4 2 1 4 4 3 4 4 2 1 E DISTURBANC LOAD P CONTROL C BUS C BUS C s p s G s i s G s G s v s u       +       =       0 0 0 0 . ( 5
( ) ( ) ( ) ( ) ( ) ( ) P Z C C C C C C C C C C C C C C C C s s R R I U k C kI s R I U k C R R I U k R kI C s R s G ω ω + + = - + + - + + + - + = 0 2 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 , ( 5.30)
where ω Z and ω P are a zero and pole that depend on steady state variables U C0 , I C0 and the ultra-capacitor parameters.

The control and disturbance to the dc bus voltage transfer functions are

( ) ( ) ( )( ) ( ) ( ) ( ) LOAD C C LOAD C C ESR BUS BUS BUS ESR BUS C C C BUS P I U P I U R V sC V R sC U s G I s G + - + - + + - = 0 0 0 0 2 0 0 0 1 , ( ) ( ) ( ) ( ) ( ) LOAD C C LOAD C C ESR BUS BUS ESR BUS BUS P P I U P I U R V sC R sC V s G + - + - + - = 0 0 0 0 2 1 , ( 5.31)
where V BUS and P LOAD are the dc bus voltage and load power in steady state and G C0 is the ultra-capacitor voltage transfer function ( 5.30). When the electric drive operates in steady state, being supplied from the ultra-capacitor, the ultra-capacitor power and load are balanced,

0 0 0 = + LOAD C C P I U
. Substituting this condition into ( 5.31) yields

( ) ( ) ( )( ) BUS BUS ESR BUS C C C BUS V sC R sC U s G I s G + + - = 1 0 0 0 , ( ) ( ) BUS BUS ESR BUS P V sC R sC s G + - = 1 .
( 5.32)

If the ultra-capacitor is large enough to be considered as an infinite capacitance compared to the dc bus capacitor C BUS , as it is case in most of the applications, the transfer function BUS G becomes ( )( )

BUS BUS C C C ESR BUS BUS C V sC R I U R sC G C 0 0 0 1 lim 0 + + - = ∞ → .
( 5.33)

Transfer function could be further simplified. The ultra-capacitor voltage is high enough and therefore the voltage droop on the series resistance can be neglected,

0 0 0 C C C R I U >>
. The dc bus voltage transfer function is ( )

BUS BUS C ESR BUS BUS V sC U R sC G 0 1+ - ≅ .
( 5.34)

Discussion on the Model

As well known from the literature, a dc-dc converter may have right half plane zero (RHPZ) in the control to the dc bus voltage transfer function [START_REF] Erickson | Fundamentals of Power Electronics[END_REF], [START_REF] Himmelstoss | Analysis of a smith-predictor-based control concept eliminating the right-half plane zero of continuous mode boost and backboost DC-DC converters[END_REF]- [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF]. The control variable can be either duty cycle d in voltage control mode or output current i C0 in the current control mode. Location of the zero depends on the output current i C0 . The positive current the negative zero and negative current the positive zero. This causes an issue when the dc bus voltage control loop has to be fast, in the same order as the output current control loop.

Please note from ( 5.34) that the zero of the transfer function is independent on the output current. In fact, when linear model of the conversion system has being developed, it has been assumed that the dc-dc converter is a device that satisfies the instantaneous power balance ( 5.22). That means the dc-dc converter does not content any energy storage element, neither an inductor nor a capacitor. This is just an approximation. If the dc-dc converter contents an inductor L C0 which cannot be neglected, the instantaneous power balance ( 5.21) has to be used. Substituting ( 5.21) into ( 5.24) and ( 5.25), yields a transfer function that has a zero, whose position in complex plane depends on the steady state current I C0 ; the positive current the negative zero and the negative current the positive zero. If the dc-dc converter is designed in such a way to have switching frequency quite greater than bandwidth of the dc bus voltage control loop, the RHPZ can be neglected in the transfer function G BUS . Also, in this case, the current controller response time can be neglected.

Control Scheme

The Control Objectives

The primary control objective is to control the ultra-capacitor current i C0 and the voltage balancing error ∆v C [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]. The secondary control objective is to asymptotically regulate the dc bus voltage v BUS to desired reference, where the reference depends on the system operation mode [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF]. Last but not least control objective is to regulate the ultracapacitor state of the charge, where the state of charge reference depends on the operating mode [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF]. The system operating modes and corresponding references have been discussed in chapter 3, section 3.2.

Control of the Ultra-capacitor Current and Voltage Balancing Error

The Control Scheme Realization

Design and realization of the current controller is state of the art, and therefore it is not discussed. The voltage balancing controller design and realization is discussed in some more detail. As seen from ( 5.17), gain of the transfer function G vC∆d depends on the output current; the positive current the negative gain and opposite; the controller parameters depend on the current i C0 . To avoid the use of complex adaptive controller, the controller G vC∆d can be designed considering positive output current. Then, the output of the controller is multiplied by function sgn(i C0 ). Simple realization is illustrated in Fig. 5.10. If the current i C0 is positive, the control signal ∆d is the controller output signal. If the current i C0 is negative, the control signal ∆d is switched to the inverted output signal of the controller G∆v C . Fig. 5.11 illustrates the functionality and performance of the ultra-capacitor current controller and the voltage balancing controller. The current i C0 is cycling between -9A and 10A, and the voltages v C1 and v C2 were recorded. Please note that the voltages v C1 and v C2 are quite well matched. When the load current is positive the voltages are decreasing and when the current is negative the voltages are increasing. This is caused by the power supply current limitation. Fig. 5.11 (b) shows details when the output current i C0 rises from -9A to 10A, while Fig. 5.11 (c) illustrates the details when the current falls from 10A to -9A. High frequency oscillations (when the current rises/falls) are caused by the input filter inductance (not included in the analysis and the circuit diagram).

The Ultra-capacitor and the DC Bus Voltage Control

To describe the control scheme, three operational modes that are important from the control point of view are considered: 1) The mains motoring mode, 2) the braking and motoring from the ultra-capacitor, and 3) ride-through mode [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF]. Fig. 5.12 illustrates the proposed control scheme. One can distinguish an inner current controller G iC0 and three outer controllers. The inner controller G iC0 regulates the ultracapacitor current i C0 . This was discussed in the previous section. Here in this section, it will be assumed that the current i C0 is well controlled and it follows the reference without significant error.

The outer controller G uC0 regulates the ultra-capacitor voltage u C0 . This controller generates reference i C0(REF) for the ultra-capacitor current controller. The dc bus voltage v BUS is controlled by two outer voltage controllers G vBUSmax and G vBUSmin . The controller G vBUSmax regulates the dc bus voltage when the drive operates in braking and motoring mode from the ultra-capacitor (modes B and MC 0 , Fig. 3.4), while the controller G vBUSmin regulates the dc bus voltage when the system operates in the ride-through mode (mode RT, Fig.

The Mains Motoring Mode

The dc bus voltage is determined by the mains voltage, v BUS ≅1.41V MAINS , where V MAINS is the mains phase-to-phase RMS voltage. As defined in Fig. 3.5 (a), the dc bus voltage is lower than the reference V BUSmax and greater than the reference V BUSmin . Hence, the dc bus voltage controller G vBUSmax is saturated to U C0inM , while the controller G vBUSmin is saturated to zero. The ultra-capacitor voltage reference is therefore

inM C inM C ref C U U u 0 0 0 0 = + = .
( 5.35)

The controller G uC0 maintains the ultra-capacitor voltage constant to the intermediate level U C0inM in order to prevent energy flow between the ultra-capacitor and the drive.

The Drive Braking Mode and Motoring Mode from the Ultra-capacitor

The drive load is inverted (the motor operates as a generator) and therefore the dc bus capacitor C BUS is charged. The dc bus voltage v BUS increases until it reaches the reference V BUSmax . The dc bus voltage controller G vBUSmax goes out of saturation while the controller G vBUSmin stays saturated to zero. The ultra-capacitor reference voltage starts to increase from U C0inM towards U C0max and therefore the ultra-capacitor current increases. The magnitude of the current is adjusted by the cascaded controllers G vBUSmax and G uC0 to such level to maintain the dc bus voltage constant. If the braking energy is greater than the ultra-capacitor capability the voltage u C0 will reach the maximum U C0max . Then the dc bus voltage controller G vBUSmax will be saturated at U C0max . The ultra-capacitor voltage is regulated to U C0max and the current i C0 falls to zero. Charging of the ultra-capacitor is stopped. The dc bus voltage starts to increase until activation of the braking resistor or the drive over-voltage (over-braking) protection.

When the drive operates in motoring mode, the ultra-capacitor has to be discharged to the intermediate value U C0inM in order to be ready for the next braking phase. The dc bus voltage controller G vBUSmax maintains the dc bus voltage to V BUSmax . The controller G vBUSmax output decreases, and therefore the ultra-capacitor voltage reference decreases towards U C0inM .

inM C ref C C U u U 0 0 max 0 ↓≥ ≥ .
( 5.36)

The ultra-capacitor is being discharged, supplying the drive. Once the ultra-capacitor voltage reaches the intermediate value U C0inM , the dc bus voltage controller G vBUSmax will be saturated at the reference U C0inM . The ultra-capacitor voltage is regulated to U C0inM , and therefore the ultra-capacitor current falls to zero. Discharging of the ultra-capacitor is finished. The dc bus capacitor is being discharged, and therefore the dc bus voltage decreases until the drive input rectifier starts to conduct. The drive is being supplied again from the mains.

The Ride-Through Mode

When the mains is interrupted the dc bus voltage starts to decrease until it reaches the lower reference V BUSmin . The controller G vBUSmin goes out of saturation and its output starts to decrease below zero towards ∆U C0min =U C0min -U C0inM . Since the controller G vBUSmax is saturated to U C0inM , the ultra-capacitor reference voltage starts to decrease below U C0inM towards U C0min .

( )

min 0 0 min 0 0 0 0 C inM C C inM C ref C inM C U U U U u U = - + ↓≥ ≥ .
( 5.37)

It allows deeper discharge of the ultra-capacitor, and regulation of the dc bus voltage to the minimum level V BUSmin . If the power interruption is longer than specified, the ultracapacitor will be discharged to the minimum level U C0min . The ultra-capacitor current will fall to zero and then the dc bus voltage will start to decrease until it reaches the under-voltage supply fault (USF) level.

The Controller(s) Synthesis

) ( ) ( ) ( ) ( ) ( ) ( ) ( ) (
) ( )

0 0 0 0 2 0 0 0 0 0 0 0 0 1 1 C PC Z P C PC P F F Z PC C F uC C uC C REF C C R k R k T s T s s k R s G s G s G s G s G s u s u ω ω ω ω + + + + + + = + = , ( 5.38)
where ω Z and ω P are the zero and pole of the ultra-capacitor voltage transfer function ( 5.30). The ultra-capacitor voltage controller is a classical proportional (P) controller and the filter G F is a low-pass filter ( )

0 0 PC uC k s G = , ( 5.39)
( )

1 1 + = F F sT s G .
( 5.40)

Characteristic equation of ( 5.38) is

( ) ( ) ( )
2 0 0 0 2 0 0 0 0 2 0 2 1 C C C F C PC Z P F C PC P F uC s s T R k T R k T s s s D ω ω ζ ω ω ω + + = + + + + + = , ( 5.41)
where ζ C0 is damping factor and ω C0 is the closed loop natural frequency. Proportional gain of the controller and time constant of the filter can be computed from ( 5.30) and ( 5.41) using the binomial criterion (ζ C0 =1).

However, the question is how to define the natural frequency, or simply speaking how to define the close loop band-width? To answer on this question one has to keep in mind some system limitations. In fact, the controller bandwidth is determined by the ultra-capacitor voltage tracking error. In section IV it has been explained how the control system works when the ultra-capacitor is charged (the drive braking mode) and discharged (the drive motoring from the ultra-capacitor). In both modes, the ultra-capacitor voltage reference slowly increases/decreases. The ultra-capacitor voltage has to follow the reference. If the tracking error is too big, the ultra-capacitor current reference will be too small, and therefore the dc bus voltage can not be maintained constant.

Maximum bandwidth is limited by the converter current capability. If the bandwidth is high, the ultra-capacitor voltage controller will generate the current reference greater than maximum current of the dc-dc converter. Therefore, the current controller G iC0 will be saturated, and as consequence the ultra-capacitor voltage controller will not be able to regulate the voltage; the control loop is saturated.

From ( 5.41) follows relation between proportional and integral gain ( )

0 4 1 0 0 2 0 2 0 0 = - - + + PC C Z P F C C PC F P k R T R k T ω ω ζ ω . ( 5
( ) ( ) ( ) ( ) 0 0 0 0 0 1 PC C C REF C C k s i s u s u s u = - = ∆ .
( 5.43)

Let the ultra-capacitor is charged/discharged with constant current i C0max and the ultracapacitor charge/discharge time is T 0 . One can compute the ultra-capacitor voltage error as

0 max 0 0 PC C C k i u = ∆ .
( 5.44) Fig. 5.15 illustrates ( 5.44) in two different cases: the ultra-capacitor voltage is lower than the maximum U C0max , and the ultra-capacitor voltage is high, slightly lower than the maximum U C0max . The ultra-capacitor is charged by constant current i C0 . The current is determined by the dc bus voltage controller via the ultra-capacitor voltage reference in such a way to maintain the dc bus voltage constant. At the end of charging, at the moment T 0, the voltage reference u C0(REF) is limited on U C0max , while the ultra-capacitor voltage is still increasing. Therefore, the error starts rapidly decreasing, causing decrease in the ultracapacitor current. The decrease in the current will cause lost of the dc bus voltage control. If the charge/discharge time is long, the ultra-capacitor voltage error is low at the end of charging, at T 0 , Fig. 5.15 (a). The most critical case is when the ultra-capacitor initial voltage is close to the maximum U C0max . In this case that is not possible even to start controlling the dc bus voltage. This case is illustrated in Fig. 5.15 (b).

        + - + - + ± + - + + = 2 2 0 0 2 0 0 2 0 0 0 0 0 2 0 0 0 2 1 4 1 2 4 1 2 4 2 1 P C PC C PC C C PC Z P C PC C C PC Z P P F R k R k R k R k R k T ω ζ ω ω ζ ω ω ω . ( ) ( ) ( ) ( ) ( )
( 5.46) Fig. 5. [START_REF] Rodríguez | PWM Regenerative Rectifiers: State of the Art[END_REF] shows the filter time constant versus the damping factor and the ultracapacitor voltage controller gain.

The DC Bus Voltage Controller(s) Synthesis

The dc bus voltage closed loop is illustrated in Fig. 5.17. The ultra-capacitor voltage control is cascaded with the dc bus voltage control. This may cause a problem in the controller synthesis because the ultra-capacitor voltage control loop is in order of magnitude slower than the dc bus voltage control loop. Let us see how the analysis can be simplified and the dc bus voltage controller designed.

The ultra-capacitor voltage control loop appears in the dc bus voltage control loop as transfer function

( ) ( ) ( ) ( ) ( ) ( ) ( )( ) (
)

0 0 0 0 2 0 0 0 0 0 0 1 1 1 PC C Z P C PC F P F P F PC F C uC uC REF C C k R R k T s T s s s T k s G s G s G s G s u s i ω ω ω ω + + + + + + + = + = .
( 5.47) Assuming that the ultra-capacitor is large enough, ( 5.47) can be simplified as

( ) ( ) ( ) ( ) ( ) (
)

0 0 0 0 0 0 1 1 1 lim 0 C PC F F PC F C uC uC C R k sT sT k s G s G s G s G C + + + =         + ∞ → .
( 5.48)

Because current capability of the dc-dc converter is limited, the bandwidth of the ultracapacitor voltage controller is much lower than bandwidth of the dc bus voltage controller. Therefore, the filter time constant T F can be assumed as infinite in comparison to the dc bus voltage response time. ( 5.48) is therefore simplified as ( ) ( )

0 0 0 0 1 1 lim PC C PC F F PC T k R k sT sT k F =         + + + ∞ → .
( 5.49)

This simplification can be done straightforward from ( 5.47) if taken into account that the dc bus voltage controller is much faster than the ultra-capacitor voltage controller. Therefore, one can assume that the ultra-capacitor voltage reference u C0(REF) is a unity step function and then apply the initial value theorem into ( 5.47).

{ ( ) ( ) ( ) ( )

0 0 0 0 1 1 lim PC F C uC uC FUNCTION STEP UNITY s k s G s G s G s G s s =                       +       ∞ → ( 5.50)
Frequency response of the transfer function ( 5.47) and the approximation ( 5.50) have been compared. The comparison is illustrated in Fig. 5.18 Note that the approximated model and the original one are quite well matched at frequencies above 20Hz. In low frequency range, there is deviation in amplitude and phase characteristic. Now, the dc bus voltage close loop transfer function is define as

( ) ( ) ( ) ( ) ( ) ( ) ( ) (
) ( )

0 0 0 0 0 0 2 0 0 0 0 0 1 1 C PC I C PC BUS ESR I P C PC ESR P BUS BUS BUS ESR C PC PC BUS vBUS PC BUS vBUS REF BUS BUS U k k U k C R k k s U k R k V C s C sR U k k s G s G k s G s G s v s v - + - - + - = + = .
( 5.51)

The dc bus voltage controller is the classical PI controller ( )

s k s k s G I P CvBUS + = .
( 5.52)

The characteristic equation of the closed loop transfer function ( 5.51) is given by ( 5.53), where ζ BUS is damping factor and ω BUS is the closed loop natural frequency.

( ) ( ) ( ) ( ) 2
U k R k V C U k k U k R k V C U k C R k k s s s D ω ω ζ + + = - - - + - = ( 5.53)
Proportional and integral gains are computed using the Butterworth criteria (ζ BUS =0.7)

( ) ( ) ( ) ( ) (
)

BUS ESR BUS BUS ESR BUS C PC BUS BUS BUS I BUS ESR BUS BUS ESR BUS C PC BUS ESR BUS BUS BUS BUS P C R C R U k V C k C R C R U k C R V C k ω ω ω ω ω ω ω - - - = - - - - = 4
C PC BUS BUS BUS I C PC BUS BUS BUS P U k V C k U k V C k ω ω - = - = .
( 5.55)

The controllers' gains depend on the ultra-capacitor voltage, which is in general case not constant over time, taking value from the minimum U C0min to the maximum U C0max . The dc bus voltage controller has to be designed in such a way to provide sufficient damping in the worst case of the ultra-capacitor voltage U C0 . To determine the worst case, one can draw the close loop root locus versus the ultra-capacitor voltage. The root locus is depicted in Fig. 5.19. As seen, the damping factor increases as the ultra-capacitor voltage increases. Therefore, the controllers have to be designed for the minimum ultra-capacitor voltage U C0min .

In that case, the damping factor will not be lower than the desired for any value of the ultracapacitor voltage.

The gains of the dc bus voltage controllers can now be computed from ( 5.54), taking the dc bus voltage and the ultra-capacitor voltage reference from Fig.

Simulation and Experimental Results

The model and control scheme presented in this chapter were simulated by Matlab/Simulink. For simulation purpose, non-linear model (Fig. 5.7) was used. The model and control scheme were also experimentally verified. Some of the simulation and experimental results are presented and discussed hereafter. The control algorithm, PWM and protection functions were implemented in a fixed-point 32 bit digital signal processor (DSP). The complete control algorithm is executed at 50 kHz. The controllers were implemented as ordinary proportional-integral (PI) controllers. The controller parameters were computed in continuous time domain (s), and then translated into discrete time domain, (z), using the approximation

S T z s 1 1 - - =
, where

s T S µ 200 =
is the sampling period. The control system specification is given in TABLE 5-1 on the next page.

Simulation Results

Fig. 5.21 shows the waveforms during an entire operating cycle: the mains motoring (MM), braking (B), the ultra-capacitor motoring (MC 0 ) and the mains motoring mode (MM). shows the same waveforms during transition from braking to the ultra-capacitor motoring mode.

U C0max 780V V BUSmax 700V U C0inM 350V V BUSmin 450V U C0min 250V C BUS 820µF C C0 0.4F R ESR 190mΩ R C0 2Ω Bandwidth 50Hz Controller U C0 ( ) 5 0 = z G uC Controller V BUSmax ( ) 1 max 1 0065 . 0 145 . 0 - - - - = z z G vBUS Feedback filter ( ) ( ) 1
1 500

1 1 + - = - z z G F Controller V BUSmin

Experimental Results

The control system was experimentally tested under different conditions. Fig. 5.23 (a) shows the waveforms when the drive runs on the full speed and then is stopped suddenly. The dc bus voltage rapidly increases within 30ms until reaches reference V BUSmax =700V. At that instant dc bus voltage controller starts to regulate dc bus voltage with slight overshoot of approximately 12V. The ultra-capacitor current is approximately 13A. Similar test was done in case of power interruption. The drive is loaded and then the mains is interrupted. The dc bus voltage falls to minimum V BUSmin =450V within 10ms, and then stays well regulate to that level. As seen from Fig.

Discussion on the Current Controller Response Time and the DC Bus Voltage Control

In the above analysis, response time of the current controller has been neglected and the current i C0 has been taken as an independent control variable. This is sufficiently accurate approximation if the dc bus control is slow compared to the current controller. In most of the applications that is the case. The current controller response time is T iC0 ≤500µs, while response time of the dc bus voltage controller is T vBUS ≥5ms. Therefore, the current controller can be considered as a pure gain without delay, and the dc bus voltage controller can be designed as it has been described. However, in certain applications the dc bus voltage controller has to be fast, having response time in order of 1ms. Typical application is variable speed drive converter equipped with a small dc bus capacitor. In such an application, the dc bus voltage controller has to be able to regulate the voltage regardless on the dc bus load variation. Thus, the current controller response time has to be taken into account when designing the dc bus voltage controllers. V BUSmax =700V, u C0 =550V and f B =50Hz.

DISCUSSION AND CONCLUSIONS

Concept of the Ultra-capacitor Based Controlled Electric Drive

To compare the ultra-capacitor based regenerative electric drive with state of the art solutions, the following two features are considered:

1. The drive immunity on the mains interruption, and 2. The drive system cost versus braking and ride-through time.

The Drive Immunity on the Mains Power Interruption

Comparison of the ultra-capacitor based regenerative drive with back-to-back and matrix drive is summarized in TABLE 6-1. The ride-through time in braking and motoring mode are compared. The back-to-back drives have short-term ride-through capability, in order of 20ms, while the matrix converter drives do not have ride-through capability at all. In contrast to this, the ultra-capacitor based drives have the ride-through capability, wherein the ride-through time is the system design parameter. No ride-through capability

From few seconds up to minutes, depending on the design criteria

The Drive Cost Comparison

The cost of the ultra-capacitor based controlled electric drive depends on the braking and ride-through capability. Longer braking and ride-through time the bigger the ultracapacitor is. In contrast to this, cost of back-to-back and matrix converters is practically independent on the braking time. If the braking time is shorter than the critical time T CR , the ultra-capacitor based solution is more cost effective than back-to-back and matrix solution. The critical braking time T CR is currently between 10 and 15s. This limit will go up in the near future with development of new technology of the ultra-capacitors. Regarding extended ridethrough capability the ultra-capacitor solution is the most cost effective solution regardless on the ride-through time. Reason for this lays in the fact that an additional energy storage device and dc-dc or dc-ac converter are required for back-to-back and matrix solution. Fig. 6.1 illustrates the drive cost versus braking and ride-through time for different drive technology.

Interface DC-DC Converter

When comparing different power converter topologies, a few parameters are important. The first one is power rating of the active switches. The second one is size of the passive components, particularly inductors. Finally, the conversion losses and efficiency are parameters to be also considered.

Semiconductors Switches

Power rating and surface of chip of the semiconductor switch are defined by two parameters: the switch utilization factor [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF], [START_REF] Mohan | Power electronics; converters, applications and design[END_REF] and the switch voltage rating.

The Switch Utilization Factor SUF

The switch utilization factor of a power converter that consists of N switches (including diodes) is defined as where I Smax and V Smax are the switches peak current and peak voltage and P C0 is the conversion power.

The switch utilization factor of two-level and three-level topology is computed from ( 4.15) and ( 6.1) as

where subscript (3L) and (2L) denote three-level and two-level. Please, note that the SUF of the two-level and three-level converter is the same. From ( 6.2) and ( 6.3) it seems that the two topologies are equivalent.

The Switches Voltage Rating

The switches voltage rating has been taken into account as a parameter in the switch utilization factor ( 6.1). However, this is not sufficient to compare two topologies with different voltage rating of the switches. Semiconductor switch conduction and switching performance depend strongly on the switch voltage rating and the switch technology. Generally, lower voltage rating means lower conduction losses, better switching performance, higher efficiency and lower cost. For example, let us consider a 400V supplied variable speed drive. The dc bus voltage varies from 500V up to 850V. For two-level dc-dc converter (Fig. 4.1 (a), (b)), the switches and diodes voltage rating is the full dc bus voltage. For this voltage rating, 1200V IGBT and 1200V fast diode are used. In this case, maximum switching frequency is limited by the switching performance of the IGBT and the diode. To reduce switching losses, soft switching techniques can be employed [START_REF] Zhang | High-power density design of a soft-switching high-power bidirectional dc-dc converters[END_REF].

In contrast to this, for the three-level converter, the switches and diodes voltage rating is a half of dc bus voltage. In this case, 600V rated IGBT or 500V super junction MOSFET and ultra-fast diodes can be used. Switching losses of 600V rated IGBT and diode are three to four times lower than the switching losses of a 1200V rated IGBT and diode. Conduction losses are lower too in comparison to a 1200V device. If compare two MOSFETs, one 1200V and one 600V rated, the difference in conduction losses is significant, because the drain source on-state resistance depends strongly on the voltage rating [START_REF] Grbovi} | High-voltage auxiliary power supply using series-connected MOSFETs and floating self-driving technique[END_REF].

Passive Components

Filter Inductor L C0

Comparison of the filter inductor is based on the comparison of the inductance L C0 at the same conditions: the current ripple, switching frequency and the dc bus voltage. The inductance of the three-level topology is computed from ( 4.8), while the inductance for twolevel topology is computed from following equation

( ) ( )d d f L v d i SW C BUS C - = ∆ 1 0 0 . ( 6.4)
The inductors size is compared from ( 4.8) and ( 6.4) as where subscript (3L) and (2L) denote three-level and two-level. Fig. 6.3 shows the inductor relative size versus minimum duty cycle d min , where the minimum duty cycle corresponds to the ultra-capacitor minimum voltage U C0min ( 3.2). Note that the inductor for the three-level topology is 25% of the inductor for two-level topology when the minimum duty cycle is inferior to 1/2. The inductor size increases from 25% up to 50% as the minimum duty cycle increases from 1/2 towards 1. Comparison of the inductor size computed by ( 6.5) is not sufficient to compare the inductor volume. For that, the inductor losses have to be alos considered and compared. That comparison is given in section 6.2.3.

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )

The DC Bus Filter Capacitors C B1 , C B2

The filter capacitors are compared at the same conditions: the voltage ripple, switching frequency, dc bus voltage and conversion power. The filter capacitor of the three-level topology is computed from ( 4.22), while the capacitor of the two-level topology is computed from equation ( ) ( )

d f Cv P d v SW BUS C BUS - = ∆ 1 0 . ( 6.6)
The capacitors size (volume) is compared from the capacitor(s) total energy, taking into account that the voltage rating of capacitor(s) is different. One filter capacitor rated for the full dc bus voltage is used in two-level topology, and two capacitors rated for half dc bus voltage are used in three-level topology. From ( 4.22) and ( 6.6) follows

( ) ( ) ( ) ( ) ( ) ( ) L L L C L L C L L L C C V C V C size size 2 3 2 ) 2 ( 2 2 ) 3 ( 3 2 3 2 2 1 2 1 2 =       ≈ , ( 6.7)
where subscript (3L) and (2L) denote three-level and two-level. Fig. 6.4 shows the capacitor relative capacitance and energy (which corresponds to size) versus minimum duty cycle d min . Note that the capacitance of the three-level topology is below 20% of that of two-level topology when the minimum duty cycle is inferior to 1/2. The capacitance increases from 20% up to 50% as the minimum duty cycle increases from 1/2 towards 1. The capacitors total energy (size) varies from 10% at minimum duty cycle of 1/2 up to 25% at duty cycle of 1. The capacitor losses are not compared because high quality film capacitors are used and therefore the losses can be neglected.

Conversion Losses

The switches losses are computed from the models ( 4.30) and ( 4.31), and data in TABLE 4-1. Fig. 6.5 shows 3-D graph of relative losses versus the conversion power and duty cycle, where duty cycle corresponds to the ultra-capacitor voltage. The relative losses are computed as ratio of the three-level converter losses to the two-level converter losses. The losses vary from 85% at maximum duty cycle up to 89% at minimum duty cycle. That means heat sink of the three-level converter is 10% to 15% smaller than that of the two-level converter.

The inductor losses are computed from the losses model ( 4.16) and data in TABLE 4-1. Fig. 6.6 shows the inductor relative losses versus the conversion power and the ultracapacitor voltage. The relative losses are computed as ratio of the three-level converter losses to the two-level converter losses. Please note that the relative losses vary between 25% and 45% at full load, while at light load the losses vary from approximately 5% up to 50%. Fig. 6.6 The filter inductor relative losses versus duty cycle and conversion power. The relative losses are computed as ratio of total losses of two-level dc-dc converter to the three-level dc-dc converter.

Model and Control Scheme

Most of the control method presented in the literature are focused on hybrid electric vehicle and power sources [START_REF] Rufer | A supercapacitor-based energy storage substation for voltage compensation in weak transportation networks[END_REF], [START_REF] Solero | Design of multiple-input power converter for hybrid vehicle[END_REF]- [START_REF] Allegre | Energy storage system with supercapacitor for an innovative subway[END_REF], [START_REF] Schupbach | 35kW ultracapacitor unit for power management of hybrid electric vehicle: bi-directional dc-dc converter design[END_REF], [START_REF] Lhomme | Design and control of a supercapacitor storage system for traction applications[END_REF]- [START_REF] Ortúzar | Ultracapacitor-based auxiliary energy system for an electric vehicle: implementation and evaluation[END_REF], [START_REF] Thounthong | Control strategy of fuel cell and supercapacitors association for a distributed Generation system[END_REF]- [START_REF] Greenwell | Predictive control of voltage and current in a fuel cellultracapacitor hybrid[END_REF]. Only a few publications are focused on control of the ultra-capacitor based electric drives [5], [START_REF] Duran-Gomez | An approach to achieve ride-through of an adjustable-speed drive with flyback converter modules powered by super capacitors[END_REF], [START_REF] Tongzhen | A supercapacitor based ride-through system for industrial drive applications[END_REF]. In comparison to state of the art, the model and control scheme proposed in this part of the dissertation has the following features: o The entire conversion system is modeled, considering all parasitic effects, such as the voltage-dependent capacitance of the ultra-capacitor. This is particularly important for the ultra-capacitor voltage controller design and synthesis.

o The dc bus voltage is asymptotically regulated to a pre-defined reference, where the reference depends on operating mode of the drive.

o The ultra-capacitor voltage is asymptotically regulated to a desired reference, where the reference is determined depending on the application requirement. Doing this, the drive system is kept ready for the next braking and ride-through sequence.

Conclusions

Application of ultra-capacitor based energy storage devices in controlled electric drives has been discussed in this part of this dissertation. The ultra-capacitor is used to store the drive braking energy and restore the energy whenever it is possible. Moreover, the ultracapacitor can be utilized as emergency energy storage in case of the mains power interruption.

Because it is not convenient to connect the ultra-capacitor directly to the controlled electric drive, an interface dc-dc converter is necessary. State of the art topologies of interface dc-dc converters are discussed and a new three-level dc-dc converter is proposed. The proposed topology is analysed and design guidelines are given. The model of the entire conversion system is developed and a new control scheme is proposed. The control objective of the proposed control scheme is to control the ultra-capacitor current and the dc bus midpoint voltage. The second control objective is to asymptotically regulate the dc bus voltage to desired reference, depending on the operating mode. The ultra-capacitor state of charge (SOC) control is third control objective.

In comparison to state of the art solutions, such as back-to-back and matrix drive converters, the proposed ultra-capacitor based controlled electric drive has the following advantages:

o The system ride-through capability is extended. The drive time autonomy is a design parameter. Depending on the application, the ride-through time could be extended up to 15s. Above this limit, it is not cost effective to use the ultracapacitors. Electrochemical batteries are more suitable solution. This limit will move up with development of new generation of ultra-capacitors.

o The system functionality, including braking capability is not linked to the mains reliability.

o Regarding the system installation cost, the proposed ultra-capacitor based regenerative electric drive is cost effective in applications that require braking time up to 10 to 15s. Above this limit, back-to-back and matrix converter based drive is better solutions.

The three-level dc-dc converter has the following features in comparison to state of the art topologies:

o The semiconductors losses are smaller than that of the state of the art topologies, such as two-level topology and isolated topologies.

o The output inductor is smaller than that of the two-level topology. The inductor size depends on the ultra-capacitor minimum voltage, and it varies from 25% to 50% of that of the two-level converter.

o The input filter capacitor is also smaller. The capacitor volume varies between 10% and 25% of that of the two-level converter.

BACKGROUND AND STATE OF THE ART

Background

Three-phase ac-dc power converters (rectifiers) are widely used in many applications, such as variable speed drives, UPS, data centers and telecom power supplies and many other applications. The rectifier main design objectives are efficiency, size, reliability and cost. Recently, the input current harmonics have become a more and more important design criterion. In some applications, the dc bus voltage has to be constant and greater than the mains voltage regardless on the mains voltage variations and disturbances. A further issue in the application of three-phase rectifiers is single-phase supply operation. Single-phase supply could be the mains degradation when one phase is lost. In such a case, the rectifier is supplied with one phase-to-phase voltage and from the rectifier sideequvalent to a single-phase supply. Another application example is rural single-phase network or some specific application of variable speed drives, such as irrigation systems.

State of the Art

Numerous different rectifier topologies have been presented in literature and used in applications. The most important topologies are briefly presented in this section as state of the art solutions.

Three-phase diode front-end rectifier with passive LC filter is the most common rectifier topology. The circuit diagram is depicted in Fig. 7.1 (a). This is the simplest and the most robust solution. However, it has numerous disadvantages, which make it undesirable in many applications. The input current total harmonic distortion (THD) is relatively high and the power factor (PF) is low. THD depends on the inductor and capacitor size, and it could be as high as 100%, or higher. The dc bus voltage is uncontrolled and slightly lower than the mains phase-to-phase peak voltage. In addition, low frequency voltage ripple is significant too. The dc bus filter capacitor C BUS and inductor L BUS are bulky, lossy and expensive.

The single-switch three-phase continuous conduction mode (CCM) boost rectifier is a solution that offers some advantages compared to the diode front-end rectifier [START_REF] Prasad | An active factor correction technique for three-phase diode rectifiers[END_REF]- [START_REF] Rastogi | A Comparative Evaluation of Harmonic Reduction Techniques in Three-phase Utility Interface of Power Electronic Loads[END_REF]. The circuit diagram is shown in Fig. 7.1 (b). The rectifier output current i REC is constant and therefore the mains current is a square waveform of 2π/3 radians with a THD of approximately 30%. The dc bus voltage is controlled and boosted above the mains phase-tophase peak voltage. Low frequency voltage ripple is negligible compared to the diode rectifier. A variant of this topology is discontinuous conduction mode (DCM) boost rectifier [START_REF] Kolar | A comprehensive design approach for a tree-phase high frequency single switch discontinuous mode boost power factor corrector based on analytically derived normalized converter component rating[END_REF]- [START_REF] Jang | A new input-voltage feed-forward harmonic-injection technique with nonlinear gain for single-switch, three phase, DCM boost rectifiers[END_REF] (Fig. 7.1 (c)). This topology offers lower THD of the input current than CCM boost rectifier. The common disadvantage of those two topologies is power rating of the switch and the boost diode. Both of them are rated at full dc bus voltage v BUS and full rectifier current i REC . The double-boost rectifier, Fig. 7.1 (d), is a solution that offers better efficiency and smaller filter inductor in comparison to the single-switch boost topology.

An electronic smoothing inductor (ELSI) has been proposed in [START_REF] Ertl | A constant output current three-phase diode bridge employing a novel "electronic smoothing inductor[END_REF]- [START_REF] Ertl | A constant output current three-phase diode bridge rectifier employing a novel "electronic smoothing inductor[END_REF] (see Fig. 7.1 (e)). A low voltage H bridge with a low voltage capacitor and a small filtering inductor is connected between the rectifier and the dc bus plus rail. This emulates an infinity inductance and maintains the rectifier current constant. The active components are rated on a fraction of the dc bus voltage. The main disadvantage of this topology is the fact that the dc bus voltage is equal to the average value of the rectifier voltage. This means the dc bus voltage is even lower than that of the ordinary diode rectifier with capacitive filter. In some applications, this is a serious limiting factor.

A Novel Half-DC-Bus-Voltage Rated Boost Rectifier

In this part of the dissertation, chapters 8 to 11, a novel hybrid half-dc-bus-voltage rated boost rectifier is presented [START_REF] Grbovi} | A novel three-phase diode boost rectifier using hybrid half-DC-BUS-voltage rated boost converter[END_REF]. The core of the presented solution is a unidirectional power conversion device, so-called the loss-free transformer (LFT), see. The LFT has two output and input terminals. The output is series connected between the rectifier plus rail and the dc bus plus rail. The input is parallel connected with the dc bus. Because of such a connection, it is possible to control the rectifier current and to boost the dc bus voltage above the mains phase-to-phase peak voltage. The LFT is composed of two uni-directional dc-dc converters. The first converter is rated on half of the dc bus voltage and full rectifier current, while the second one is rated on half dc bus voltage and a fraction of the input rectifier current. The first converter regulates the rectifier current and the dc bus voltage, while second one assists to the first one. Power rating, size and efficiency of the entire conversion system depend strongly on the ratio of the dc bus voltage to the rectifier voltage (boosting factor). For example, if the boosting factor is low, below 1.5, the efficiency is around 98 to 99%

HYBRID HALF-DC-BUS-VOLTAGE RATED BOOST RECTIFIER

The Basic Principle

The basic principle of the proposed boost rectifier is illustrated in Fig. 8.1. One can distinguish a three-phase diode rectifier, a dc bus filter capacitor C BUS , the dc bus load and a two-terminal device designated as loss free-transformer (LFT). The output terminal of the LFT is connected between the rectifier plus rail and the dc bus plus rail, while the input is connected in parallel with the dc bus. The LFT is controlled by a control variable m(t).

Let the mains be symmetrical three phase mains with phase to phase voltages given as ( )

      - = 3 2 sin π ω p t V t v m PEAK MAINS , ( 8.1)
where p=0,1,2 is the phase order.

Let the rectifier current i REC be constant or pseudo constant (being controlled by the LFT). Since the rectifier operates in continuous conduction mode (CCM), the rectifier output voltage is

°≤ < °⋅ = 120 60 sin ) ( t m PEAK REC t V t v ω ω , ( 8.2)
with the period T=T m /6, where T m is the mains period. The rectifier voltage, the dc bus voltage, the mains phase voltage and phase-to-phase voltage, and the mains current are illustrated in Fig. 8.1 (b).

The rectifier average voltage and average current are

( ) ( ) π 3 6 3 6 PEAK T T REC m AV REC V dt t v T v m m = = ∫ , ( 8.3)
( ) ( ) 3 π PEAK LOAD AV REC LOAD AV REC V P v P i = = . ( 8.4)
As it can be seen from Fig. 8.1, the dc bus voltage v BUS is sum of the rectifier voltage v REC and the auxiliary boost voltage v 0 (t), where v 0 (t) is generated and controlled by the LFT. Hence, the dc bus voltage can be directly controlled by the boost voltage v 0 (t) via the LFT, regardless on variation of the mains voltage and the dc bus load. The instantaneous and average boost voltage is ( ) ( )

t v v t v REC BUS - = 0 , ( 8.5)
( ) π π π 3 3 0 - ≥ - = PEAK PEAK BUS AV V V v v .
( 8.6)

The LFT Realization

Some possible realizations of the LFT are illustrated in Fig. 8.2. The LFT consists of two uni-directional dc-dc converters, namely DC-DC1 and DC-DC2, and two series connected capacitors C B1 and C B2 . Output of the converter DC-DC1 is connected between the rectifier and dc bus plus rail, while the input is connected in parallel with the capacitor C B2 . The average power of the converter DC-DC1 is not zero (v 0(AV) i REC ≠0). Therefore, the current i 1 , which flows into the capacitors mid point, is not zero. Since the capacitors average current must be zero in steady state, one additional converter must be connected on the capacitors mid point in order to compensate the current i 1 . The converter DC-DC2 could be connected in three different ways.

The case A: The DC-DC2 output is parallel connected with the capacitor C B2 , while the input is connected in parallel with the dc bus (Fig. 8.2 (a)).

The case B: The DC-DC2 output is connected on the dc bus, while the input is connected in parallel with the capacitor C B1 (Fig. 8.2 (b)).

The case C: The DC-DC2 output is connected in parallel with C B2 , while the input is connected in parallel with C B1 (Fig. 8.2 (c)). The best of the three possible topologies depends on the power rating of the DC-DC2 converter. To examine this, let us compute power rating of DC-DC2 converter for all the three cases.

The average currents i 1 and i 2 are computed from the power balance as

( ) ( )       - = = 1 3 2 2 1 π BOOST BUS C LOAD AV AV k v k P i i , ( 8.7)
where the top capacitor voltage is

BUS C C v k v 2 2 =
. The dc bus voltage boosting factor k BOOST is defined as

1 ≥ = PEAK BUS BOOST V v k . ( 8.8)
From ( 8.7) and Fig. 8.2 one can find power rating of the DC-DC2 converter.

The case A:

( )       - = = 1 3 2 2 2 π BOOST LOAD C AV A k P v i P .
( 8.9)

The case B:

( )       - - = = 1 3 1 2 2 1 2 2 π BOOST LOAD C C C AV B k P k k v i P . ( 8.10)
The case C:

( ) ( ) ( )       - - = - = 1 3 1 1 2 2 2 2 2 π BOOST LOAD C C C AV C k P k v k i P .
( 8.11)

The converter relative power rating versus the voltage v C2 is plotted in Fig. 8

BUS C C v v k 2 2 =
is the voltage v C2 normalized on the dc bus voltage v BUS .

One can see from the graph, Fig. 8.3, that the power rating of the converter of case A (Fig. 8.2 (a)) is constant. In contrast to this, the power rating of the converter in case B and C (Fig. 8.2 (b) and (c)) strongly depends on the voltage v C2 . From the graph, one can conclude that the topology C requires minimum power rating of the DC-DC2 converter.

A particular case that is considered in the dissertation is v C2 =v C1 =v BUS /2 (the DC-DC2 is connected as in case C). Because some of the terminals of the DC-DC1 and DC-DC2 converters are connected together, the circuit of Fig. 8.2 (c) could be further simplified as given in Fig. 8

The Mains Current Quality

The mains current quality has become an important issue recently with broad application of nonlinear loads such as diode bridge passive rectifiers. Such loads generate higher harmonics in the mains current, which cause additional heating of the distribution transformers, capacitor banks and neutral line of the low voltage distribution network. Moreover, the higher harmonics generates electromagnetic interference (EMI) with analog communication equipment.

Based on the international IEC standard [13], total harmonic distortion factor (THD) and partially weighed harmonic distortion factor (PWHD) are defined as Please notice that harmonics up to 40 th order are taken into account in the THD and PWHD definition [13]. In the near future, it is expected that the standards will be modified and higher order harmonics (above 40 th ) will be taken into account.

In this dissertation, an intermediate solution is discussed. The mains current is squarewaveform with certain level of higher harmonics. An ideal waveform is depicted in Fig. 8.5 (a), while the current spectrum is depicted in Fig. 8 TABLE 8-1 shows the current emission limits applicable on three-phase variable speed drives. In most industrial applications, the short circuit coefficient I SC /I N is greater than 300. In this case, the square waveform current satisfies THD limit but not PWHD limit. Further improvement of the current shape regarding the PWHD factor is possible. Fig. 8.6 (a) shows some experimental waveforms that illustrate the functionality of the proposed boost rectifier. Waveform of the mains phase-to-phase voltage v MAINS , current i MAINS and the dc bus voltage v BUS are given. The current is a square-waveform, as expected from theoretical analysis. The dc bus voltage is constant, ripple-free and boosted above the mains phase-to-phase peak voltage. The same waveforms of an ordinary diode rectifier are depicted in Fig. 8.6 (b). The waveforms were recorded at the same conditions: the load and the mains voltage. The mains current peak and RMS value are 35A and 12.5A respectively in comparison to 10A and 8A in case of the proposed boost rectifier. Fig. 8.7 shows the mains current amplitude spectra. Fig. 8.7 (a) shows spectra in full frequency range, from 2 kHz up to 150 kHz, while Fig. 8.7 (b) shows spectra up to 40 th harmonic. The relative values of even harmonics up to 12 shall not exceed 16/n %. Even harmonics above order 12 are taken into account in THD and PWHD in the same way as odd order harmonics.

The DC-DC1 Converter

In this section, the DC-DC1 converter is analyzed and some design guidelines are given.

A circuit diagram of the DC-DC1 converter is depicted in Fig. 8.8. The input rectifier, DC-DC2 converter and the dc bus load are not detailed, just indicated as gray shaded boxes. Equivalent circuit diagram and waveforms (the inductor current i REC and voltage v L0 ) are given in Fig. 8.9. The input rectifier is represented by a voltage source v REC . The capacitors C B1 and C B2 are modeled as a voltage sources v C1 and v C2 that are assumed to be constant. Let Since the capacitors could be large enough to behave as constant voltage sources over a short period (order of switching period). However, on long term, the voltage v C1 has tendency to increase and v C2 has tendency to decrease because the mid point current i 1 is non-zero positive current. To keep those voltages in a constant ratio, an auxiliary converter DC-DC2 is used. Selecting a proper topology, it would be possible to maintain the voltages v C1 and v C2 in constant ratio regardless on the current i 1 . In this analysis, a particular case, v C1 =v BUS /2 is considered.

Analysis

The converter basically operates in the same way as the ordinary boost converter: the switch S 0 conducts during period dT S and the inductor current i REC increases. The boost diode D 0 conducts during the complementary period (1-d)T S and the inductor current decreases and charges the dc bus capacitor C BUS . The difference between the ordinary boost converter and the proposed one is that the switch S 0 is connected to the mid point of the capacitors C B1 and C B2 . That means the inductor voltage swing is the voltage v C2 =v BUS /2. In the standard single-switch boost topology, the switch is connected to the minus dc bus and therefore the inductor voltage swing is the full dc bus voltage v BUS . This has direct influence on the inductor size, losses and electromagnetic interference (EMI) [START_REF] Rossetto | Conducted EMI issues in a 600W single phase boost PFC design[END_REF]- [START_REF] Wang | Common mode noise reduction for boost converters using general balance technique[END_REF].

The circuit of Fig. 8.9 (a) is described by equation

   ≤ < - ≤ < - = S S BUS REC S C REC REC T t dT v v dT t v v dt di L 0 1 0 , ( 8.14)
where T S is the switching period and d is the duty cycle. From ( 8.14) and the voltsecond balance it follows that duty cycle d is

BUS REC BUS C BUS REC BUS v v v v v v v d - = - - = 2 1 , ( 8.15)
where v C1 =v BUS /2. Substituting ( 8.2) into ( 8.15) yields duty cycle Maximum boost factor and the dc bus voltage are computed from ( 8.16) and the condition that the duty cycle is maximum (d max =1) at minimum of the rectifier voltage. The boost factor (and therefore the dc bus voltage) of the proposed hybrid boost converter is limited, in contrast to the ordinary boost converter that has theoretically unlimited boost factor (in reality limited by the circuit parasitic resistance). In most of the applications, the boost factor is often lower than 1.5, and therefore the limitation ( 8.17) is not relevant.

( ) °≤ < °        - =

Design Aspects

In this section, some aspects of design of the boost inductor L 0 , the dc bus capacitor C BUS and boost switch S 0 and diode D 0 are discussed and design guidelines are given.

Boost Inductor L 0

Design of the boost inductor is one of the most important design steps in a boost converter design. The design is based on two criteria: the inductance (for allowed current ripple ∆i REC ) and the inductor losses. The current ripple has significant influence on the total losses and the inductor thermal design. For generality of the analysis, it is assumed that the maximum current ripple is given as a design parameter. The boost inductor losses are computed, however the thermal design is not discussed in detail.

o The Inductance and Current Ripple

The inductor current ripple is computed from ( 8.14) and volt-second balance as ( )

2 0 2 d d f L v i SW BUS REC - = ∆ , ( 8.18)
where f SW is the switching frequency. Fig. 8.12 shows the current ripple versus boost factor and angle ωt. Substituting ( 8.16) into ( 8.18) one can find the maximum current ripple

                 - + - = ∆ > ≤ 3 2 0 3 2 2 0 max 8 3 3 3 2 2 BOOST BOOST k SW BUS k BOOST BOOST SW BUS f L v k k f L v i . ( 8.19)
The boost inductance is computed for the worst case of ( 8. [START_REF] Attaianese | High performance supercapacitor recovery system for industrial drive applications[END_REF]) and the maximum current ripple ∆i max

SW BUS f i v L max max 0 8∆ ≥ . ( 8

.20) o The Inductor Losses

The inductor losses consist of the winding losses and the core losses.

(

∑ = + = n n nf C nf L n RMS L L SW SW R R I P 0 0 2 0 0 , ( ) ( ) ( ) ( )
where R L0(fsw) is the inductor winding resistance that dependents on the frequency. The resistance R C(fsw) is the core equivalent resistance that models the core losses [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]. The losses model ( 8.21) takes into account harmonics of the inductor current. To simplify computation, the current ripple can be substituted by an equivalent sinusoidal current having the same RMS value and frequency as the total current ripple. As can be seen from ( 8.18), the ripple current is time varying because duty cycle varies with the instantaneous rectifier voltage ( 8.2). Hence, the ripple RMS current varies too. It could be considered as local RMS current.

t i R R k v P R t P 12 ) ( ) ( 3 2 0 2 0 0 ∆ + +         = π , ( 8
DC L T L m AV L k k k k k i R R k v P R dt t P T P m                           + + - + + - × ∆ + +         = =

The DC Bus Circuit

The dc bus capacitor is designed with the dc bus voltage ripple as the design criterion. The dc bus voltage ripple at low frequency is computed from the instantaneous power balance equation

CBUS BUS LOAD REC REC i v P i v + = , ( 8.25)
where i CBUS is the dc bus capacitor current. In ( 8.25), it has been assumed that instantaneous power of the capacitors C B1 , C B2 and C S , and inductors L 0 and L S could be neglected in comparison to the dc bus capacitor. The rectifier current is assumed as constant (actively controlled by the DC-DC1 converter).

The rectifier voltage ( 8.2) can be expanded in Fourier series

( ) ( ) ( ) ( ) n m n PEAK PEAK REC t n n V V t v ϕ ω π π + - + = ∑ ∞ = 6 sin 1 6 2 3 3 1 2 . ( 8
≅ + - = ∑ ∞ = .
( 8.27)

Here, it has been assumed that 6 th harmonic of the instantaneous power ( 8.25) is dominant, and the dc bus voltage ripple is significantly lower than the average dc bus voltage,

) ( AV BUS BUS v v << ∆
. Thus, the peak-to-peak voltage ripple can be computed as is maximum dc bus voltage ripple given as a design parameter.

The Switch and Boost Diode

Three parameters are important for design and selection of the boost switch and diode:

1. The device voltage stress, 2. The device current stress, and 3. The device losses and associated thermal stress.

The device voltage rating, current stress and losses will be analyzed. Thermal aspects however will not be discussed because that is an issue well known and presented in literature, [START_REF] Nussbaumer | Design guidelines for interleaved single-phase boost PFC circuits[END_REF].

o The Device Voltage Rating

The device transient voltage defines the switch and diode voltage rating

( ) ( ) ( ) V v V V BUS D S ∆ + = = 2 max max 0 max 0 , ( 8.30)
where ∆V is commutation over-voltage

) ( )       - = ∫ = 1 3 2 3 3 2 3 0 0 BOOST BUS LOAD S AV S k v P t d i I π ω π π π , ( ) ( )         - = ∫ = BOOST BOOST BUS LOAD S RMS S k k v P t d i I π π ω π π π 3 1 2 3 3 3 2 3 2 0 0 . ( 8.32)
The switch losses are computed from the switch model (chapter 5) and ( 8.32) where the diode is approximated by threshold voltage V DF0 and dynamic resistance r D0 . E Q is reverse recovery energy at given the conditions; rated voltage V N and current I N .

( ) ( ) ( ) 4
      - = BOOST BUS LOAD AV D k v P I 3 2 0 π , ( ) 1 6 3 0 - = BOOST BOOST BUS LOAD RMS D k k v P I π π , ( 8.34)

The DC-DC2 Converter

As already mentioned in section 8.1, the role of the DC-DC2 converter is to balance the voltages v C1 and v C2 . The circuit diagram of the proposed converter is given in Fig. 8.13. Basically, the converter is a variant of a switched capacitor converter [START_REF] Wang | Common mode noise reduction for boost converters using general balance technique[END_REF]. A switch leg S 1 S 2 is connected across the bottom capacitor C B1 , and a diode leg D 1 D 2 is connected across the top capacitor C B2 . The capacitor C S is the main switched capacitor that transfers the energy, while inductor L S is an auxiliary inductor used to reduce conduction losses and achieve zero current switching (ZCS) [START_REF] Wang | Common mode noise reduction for boost converters using general balance technique[END_REF]. The switches S 1 S 2 are driven with complementary control signals at period T S2 . The duty cycle d 2 is constant, around 50%.

Analysis

For simplicity of the analysis, one can assume that the capacitors C B1 and C B2 are large enough to maintain the voltages v C1 and v C2 constant over one switching cycle T S2 . Also, the switches and diodes are modeled by constant voltage sources V S0 and V DF0 . One complete cycle T S2 can be divided into four stages, namely stage A to stage D. Fig. 8.14 illustrates topological stages and waveform of the resonant current i R2 . Stage C: The switch S 2 is closed at the instant t=T S2 /2. The capacitor C S is discharged (into v C2 ) via the switch S 2 , diode D 2 and the inductor L S . The current i 2R increases in negative direction with respect to the direction in Fig. 7 The voltage v CS decreases. After reaching the maximum, the current starts decreasing towards zero (L S C S resonant circuit).

Stage D:

The current i 2R reaches zero and diode D 2 is blocked at the instant t=T S2 /2+T 0 /2. The current remains zero until the commutation of the switch S 1 at the moment t=T S2 . One switching cycle is finished.

Neglecting the circuit resistance, the current i 2R can be described by fractions of sinusoidal function, .36) where the circuit natural frequency is

( ) ( ) ( )        + ≤ < + + ≤ <       - - = 2 1 2 2 0 2 2 2 2 sin 2 1 2 0 2 0 2 2 2 0 0 2 2 2 S S S S S S k R T k t T T k T T k t T k T k t T T i t i ω π , ( 8
S S C L T 1 2 0 0 = = π ω , ( 8.37)
and k is a floor integer defined as The current i 1 is the current of the switch S 0 (the converter DC-DC1), and is a purely discontinuous current. However, because of presence of the capacitors C B1 and C B2 that are assumed sufficiently large, the current i 1 can be considered as a constant current i 1(AV) . In steady state, the capacitors voltages are constant. As the capacitors are large, but not infinite capacitance, it follows that the capacitors current over a certain period must be zero. Hence, i 2(AV) =i 1(AV) . From ( 8.4) and ( 8.16) it follows that ( ) ( )

3 2 3 ) ( 2 sin 2 3 ) ( π ω π ω π ≤ < - = = t m BOOST BUS LOAD REC AV m t k v P t d i t i . ( 8.38)
Please, note that i 2(AV) (t) is the current averaged over a switching period T S2 . So, it can be considered as the local average current [START_REF] Wong | The method of double averaging: an approach for modeling power factor correction switching converters[END_REF]. Also, note from ( 8.36) and ( 8.38) that peak of the resonant current i 2R changes with the rectifier voltage; the lower rectifier voltage the greater peak current.

The Voltage Transfer Ratio

The converter DC-DC2 can be considered as series resonant converter that operates in discontinuous conduction mode (DCM), mode 1 [START_REF] Vorperian | Analysis of resonant converters[END_REF]. The input is voltage v C1 and output is voltage v C2 . The voltage gain of the series resonant converter operating in this mode is unity, regardless on the load and switching frequency.

( )

1 0 0 1 2 = + - = DF S C C V V v v M , ( 8.39)
where V S0 and V DF0 are the switch and diode voltage droop.

The bottom and top capacitor voltages are computed from ( 8.39) as

2 , 2 0 0 2 0 0 1 DF S BUS C DF S BUS C V V v v V V v v - - = + + = . ( 8.40)
As is it can be seen from ( 8.40), the ratio of v C1 to v C2 is constant. That means there is no need for direct measurement and control of the mid point voltage.

Design Aspects

The Switches and Diodes

The switches and diodes average and RMS current computed over a switching cycle (local averaging [START_REF] Wong | The method of double averaging: an approach for modeling power factor correction switching converters[END_REF]) are

( ) ( ) 2 2 AV AV S i i = , ( ) ( ) 0 2 2 2 2 T T i i S AV RMS S π = . ( 8.41)
The average and RMS current computed over a fundamental period ( 8.43)

3 π are ( )       - = 1 3 BOOST BUS LOAD AV S k v P i π , ( )         - - + = π π
The switches and diodes are approximated by constant threshold voltage V S and V DF and dynamic resistance r S and r D . Switching losses are neglected since the switches commute at zero current conditions. If necessary, the losses due to the switch parasitic capacitance can be taken into account.

LC Circuit

The resonant circuit RMS current and losses depend on the load power P LOAD , the boosting factor k BOOST and ratio between the switching and resonant frequency,

        - - + = π π 2 3 3 12 2 1 3 2 0 2 2 2 BOOST BOOST S BUS LOAD RMS k k T T v P i . ( 8.44)
The role of the inductor L S is to minimize the conduction losses and ensure the zero current switching condition. It follows from ( 8.37), ( 8.42) and ( 8.44) that the greater inductance the lower conduction losses. The zero current switching condition is defined as The capacitor and inductor have to be selected for minimum size, cost and losses of the LC circuit. Total volume of the capacitor and inductor can be expressed in general form ( )

                    + = S S S C T F C F W 2 2 2 1 2π
, ( 8.46) where functions F 1 and F 2 depends on the capacitor and the inductor technology.

The function F 1 has been interpolated for EPCOS film capacitors B32674 at 450Vdc rated voltage [122]. Fig. 8.17 shows the capacitor volume versus capacitance. Red squares are the data sheet values and blue line is first order interpolation, From ( 8.47) and ( 8.48) and the condition ( )

0 2 2 2 2 1 = ∂                     ∂ + ∂ ∂ = ∂ ∂ S S S S S S C C T F C C F C W π , ( 8.49)
the capacitance C S and inductance L S can be found that gives minimum volume of the converter. Another parameter that has to be verified is the capacitor RMS current. This is a trivial problem of optimisation and as that it will not be further discussed.

A Design Example

A 5.5 kW prototype was designed and the proposed half-dc-bus-voltage-rated boost rectifier experimentally verified. A picture of the prototype is shown in Fig. 8.18. The converter specification and parameters of the selected main components are given in TABLE 8-2 Active power components (MOSFETs, IGBTs and FWDs) were selected for the target switching frequencies, dc bus voltage, boost factor and rated power. R DC is the winding resistance at low frequency and R AC is the winding resistance at switching frequency [START_REF] Shen | Design of high-density transformers for high-frequency high-power converters[END_REF]. The resistance R C is the core equivalent resistance as a model of the core losses ( 8.21). The core resistance was computed at the inductor rated current, using the manufacture datasheet and design software tool [103].

The inductor losses were computed from ( 8.21) and the parameters in TABLE 8-2. Fig. 8.19 shows 3-D graph of the total inductor loses versus output power and boost factor.

The switch S 0 and diode D 0 losses were computed from ( 8.33), ( 8.35) and data given in TABLE 8-2. Fig. 8.20 and Fig. 8.21 show 3-D graph of switching and conduction losses versus conversion power and boost factor. The switch conduction losses strongly depend on the boost factor. They are dominant at full power and high boost factor. In contrast to this, the switch commutation losses are less dependent on the boost factor. The boost diode losses, particularly conduction losses vary significantly with the boost factor. The current ripple ∆i REC =2.5A The switch S 1/2 and diode D 1/2 losses were computed from losses model ( 8.43) and data in TABLE 8-2. The computed losses versus conversion power and boost factor are illustrated in Fig. 8.22. Fig. 8.23 shows the converter total losses and conversion efficiency versus conversion power and boost factor. The calculation shows that the converter efficiency is quite high, from 97% at minimum output power of 550W and boost factor k BOOST =1.7 up to 99% at maximum output power and minimum boost factor k BOOST =1. In this calculation, losses of the filter capacitors C B1 and C B2 and resonant capacitor C S and inductor L S were neglected. The control circuit and gate drivers' losses were also neglected.

S 0 : MOSFET 500V 20A D 0 : FAST DIODE 500V 20A V S0 r S0 *E ON +E O V DF0 r D0 *E Q 0 200mΩ 10µJ/A 1.13 V 11 mΩ 5µJ/A *Switching losses at V N =300V T J =150˚C BOOST INDUCTOR L 0 DC BUS CAPACITOR C BUS High Flux Powder Core 58439-A2 L 0 R DC R AC R C C ESR 325µ H 40mΩ 0.8Ω 4.4Ω 820µF 0.19 Ω L S C S S 1 /S 2 IGBT 600V 10A D 1 /D 2 FAST DIODE 600V 10A V S r S V D

MODELING ASPECTS AND CONTROL SCHEME

The model of the half-dc-bus-voltage rated boost rectifier is developed and discussed in this chapter. As mentioned in chapter 8, the half-dc-bus-voltage rated boost rectifier consists of two converters (DC-DC1 and DC-DC2). Model for each converter and then model of the entire rectifier system have to be developed. The model of the DC-DC1 converter is more or less state of the art [START_REF] Erickson | Fundamentals of Power Electronics[END_REF] and therefore it is not discussed in details in this chapter. The model of the DC-DC2 converter is less known in the literature, and is developed and discussed. Finally, a large signal and small signal model of the entire boost rectifier is developed. The model is verified by the Matlab simulations and a set of experiments.

In second part of this chapter, the control scheme is discussed and the controllers' synthesis procedure is given. The proposed control scheme is verified by Matlab/Simulink simulation and a set of experiments. The results are presented and discussed.

Model of Series Resonant Converter

As discussed in chapter 8, section 8.3, the DC-DC2 converter is the series resonant converter that operates in type 1 discontinuous conduction mode (DCM) [START_REF] Vorperian | Analysis of resonant converters[END_REF]. The series resonant converter topology is well-know topology since the age of vacuum tube high frequency generators and SCRs power converters [START_REF] Chetty | Resonant power supplies: their history and status[END_REF]. In the 1980s and 1990s this topology was in focus for high-density dc-dc conversion applications [START_REF] Chetty | Resonant power supplies: their history and status[END_REF]. Two of the most often used methods to model series resonant converter (SRC) are sinusoidal approximation [START_REF] Chetty | Resonant power supplies: their history and status[END_REF]- [START_REF] Witulski | Small signal equivalent circuit modelling of resonant converters[END_REF], and discrete time modelling [START_REF] Elbuluk | Sampled-data modelling and digital control of resonant converters[END_REF], [START_REF] Kim | A discrete time domain modelling and analysis of controlled series resonant converter[END_REF]. However, those modelling techniques are not appropriate if the resonant converter operates in continuous conduction mode (CCM) at resonant frequency or in type 1 discontinuous conduction mode (DCM) [START_REF] Vorperian | Analysis of resonant converters[END_REF]. The concept of the quantum modelling and control technique introduced in [START_REF] Jopung | A generalised quantum resonant converter using a new quantum resonant module[END_REF] can be used in analysis of type 1 DCM resonant converter.

The circuit diagram is given in Fig. 9.1 (a). The capacitors C B1 and C B2 are modelled by the ideal voltage sources v C1 and v C2 . The equivalent circuit diagram is depicted in Fig. 9.1 (b). The model consists of two voltage-controlled voltage sources (v C1 and v C2 ), two currentcontrolled current sources (i S and i D ) and an equivalent inductance L E . The controlled voltage sources are known (v C1 and v C2 ). The controlled current sources and the equivalent inductance L E have to be determined.

To determine the equivalent inductance L E , the following virtual experiment is performed. Let us consider steady state and no load condition, meaning that i 2(AV) =0, and

0 2 1 C C C V v v = =
. The switch and diode conduction voltages are neglected,

0 ≅ = DF S V V
. Hence, the resonant circuit current i 2R is zero, and the capacitor C S initial voltage is

0 C CS V v =
. Then, at the instant t=0, a step ∆V C is applied on the input voltage v C1 , while the voltage v C2 remains constant. Then, the average currents, i S , i D and i 2 will be computed. Finally, the inductance L E will be computed from variation of the average current i 2 .

The switch S 1 (Fig. 9.1 (a).) is closed and a step voltage ∆V C is applied on the voltage source v C1 at the instant t=0, while the voltage v C2 remains constant.

( ) ( ) ( 0 2 0 1 ∞ + = ∆ + ∞ + = t h V v t h V t h V v C C C C C , ( 9.1)
where h(t) is the step function defined as Neglecting the circuit resistance, the instantaneous currents i 2R , i 2 , i S and i D can be described by a train of half-sinusoidal pulses with cycle by cycle increasing magnitude. The waveforms are illustrated in Fig. 9.2 (a). The phase portrait of the resonant circuit is shown in Fig. 9.2 (b).

   > ≤ = 0 1 0 0 ) ( t t t h . ( 9
The equations describing the currents i 2R , i 2 , i S and i D are

( ) ( ) ( ) ( )        + ≤ < + + ≤ <       - ∆ + - = 2 1 2 2 0 2 2 2 2 sin 1 1 2 0 2 0 2 2 2 0 0 2 S S S S S S C k R T k t T T k T T k t T k T k t L V k t i ω ω , ( 9.3) ( ) ( ) ( )        + ≤ < + + ≤ <       - ∆ + = 2 1 2 2 0 2 2 2 2 sin 1 2 0 2 0 2 2 2 0 0 2 S S S S S S C T k t T T k T T k t T k T k t L V k t i ω ω , ( 9.4) ( ) ( ) ( )        + ≤ < + + ≤ <       - ∆ + = 2 2 2 2 0 2 2 2 2 sin 1 2 0 2 0 2 2 2 0 0 S S S S S S C S T k t T T k T T k t T k T k t L V k t i ω ω , ( 9.5) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )          + ≤ < + + + + ≤ < +       + - ∆ + + ≤ < = 2 2 2 2 1 0 2 2 1 2 1 2 1 sin 2 2 1 2 0 2 0 2 0 2 2 2 0 0 2 2 S S S S S S C S S D T k t T T k T T k t T k T k t L V k T k t T k t i ω ω . ( 9.6)
Average values of the currents ( 9.3)-( 9.6) are

( ) ( ) ( ) ( ) 2 2 0 2 2 2 2 3 2 1 S S C T t t R S AV T T L V k dt t i T k i S π ∆ + = = ∫ + , ( ) ( ) ( ) ( ) 2 2 0 2 2 1 1 S S C T t t S S AV S T T L V k dt t i T k i S π ∆ + = = ∫ + , ( ) ( ) ( ) ( ) 2 2 0 2 2 2 1 S S C T t t D S AV D T T L V k dt t i T k i S π ∆ + = = ∫ + , ( 9.7)
where k is a floor integer defined as Variation of the average current i 2 between two successive cycles is

( ) ( ) ( ) ( ) ( ) ( ) 2 2 0 2 2 2 2 2 2 S S C AV AV AV T T L V k i k i k i π ∆ = - + = ∆ . ( 9.8)
The equivalent circuit of Fig. 9.1 (b) can be described by difference equation

( ) ( ) ( ) ( ) ( ) k V k v k v L T k i C C C E AV ∆ = - = ∆ ∆ 2 1 2 , ( 9.9)
where the time step is

2 S T T = ∆
. Finally, from ( 9.8) and ( 9.9) one computes the equivalent inductance

L E as 2 0 2 2 2         = T T L L S S E π . ( 9.10)
From ( 9.7) one can also define i S and i D as

( ) ( ) ( ) ( ) k i k k k i AV AV S 2 3 2 1 + + = , ( ) ( ) ( ) ( ) k i k k k i AV AV D 2 3 2 2 + + = .
( 9.11) Fig. 9.3 illustrates interpolated equations ( 9.11). Notice that the difference between the currents i S and i D is initially 20% and it drops below 10% for k>3 (after three half-periods).

In this virtual experiment, we have assumed that the switch S 1 is closed at the same time as the variation ∆V C is applied on v C1 . As the average currents are computed over an interval (0, T S2 ), the diode average current is greater than the switch average current, as given in ( 9.7) and ( 9.11). However, if we assume that the switch S 2 is closed at the same time as the variation ∆V C is applied on v C1 , the switch average current i S(AV) will be greater than the diode average current i D(AV) . In reality, the step voltage could be applied at any instant in the interval (0, T S2 ). Thus, the diode to switch average currents ratio could be any between the two extreme cases mentioned before. However, the switching frequency f SW2 is greater that the frequency of our interest. Therefore, it could be assumed that the transition period is much shorter than the observation period. In that case the switch and diode currents can be assumed as the same ( ) ( )

AV D AV S i i ≅ .

The Entire Rectifier Model

Large Signal Model

Now, having model of the DC-DC1 and DC-DC2 converters, one can construct a model of the entire rectifier. The model is depicted in Fig. 9.4. The dc bus load is a constant power p LOAD (this is typical load in controlled power converter applications). The inductance L 0 is the boost inductor, while the resistance R 0 is an equivalent input resistance

m m L L R R ω π 3 0 0 + = .
( 9.12)

The resistance R L0 is the boost inductor parasitic resistance, which includes the winding resistance and the core losses resistance [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]. The second part of ( 9.12) is model of the rectifier commutation voltage losses [START_REF] Mohan | Power electronics; converters, applications and design[END_REF]. The frequency

m m f π ω 2 =
is the mains angular frequency and L m is the mains inductance. The large signal model of circuit in Fig. 9.4 is described by set of nonlinear differential equations,

2 0 0 C BUS REC REC REC v d v v i R dt di L ⋅ + - + - = , ( 9.13) ( )            + = - + - = - - = - + - = 2 1 2 2 1 1 2 1 2 2 1 C C BUS BUS LOAD D REC C B BUS LOAD S REC C B C C E E v v v v p i i d dt dv C v p i i dt dv C v v i R dt di L . ( 9.14)
Variable d is duty cycle as the modulation signal of the DC-DC1 converter. The duty cycle is generated by a non-linear controller, where the control law is

2 C BUS REC v v v u d + - = .
( 9.15)

The variable u is the main control variable that is generated by the upper level controller (the rectifier current controller for example). Substituting ( 9.15) into ( 9.13) yields linear differential equation

REC REC i R u dt di L 0 0 - = .
( 9.16)

The dc bus circuit is described by ( 9.14). However, notice that duty cycle d appears as an intermediate variable in ( 9.14). To find an equation that describes the dc bus circuit (the dc bus voltage v BUS ) as a function of the rectifier current i REC as the control variable, one can use the power balance

∑ ∑ ∑ = = = + + + = Q i i i i M j j j j N k k k OUT IN dt dv C v dt di L i R i p p 1 1 1 2 .
( 9.17) p IN and p OUT are the system input and output power, N is number of the resistors (including parasitic resistances ), M is number of the inductors and Q is number of the capacitors in the circuit. Applying ( 9.17) on the circuit of Fig. 9.4 yields

dt dv v C dt dv v C i R dt di i L i R dt di i L p i v C C B C C B E E REC REC REC LOAD REC REC 2 2 2 1 1 1 2 2 2 2 2 0 0 + + + + + + = . ( 9.18)
Assuming that the filter capacitors are the same

B B B C C C 2 2 1 = =
, ( 9.18) can be rearranged as

        + + + + + + = 2 2 2 2 2 2 2 2 0 0 dt i d L C i dt di L i R dt dv v C i R dt di i L p i v E B E E BUS BUS B REC REC REC LOAD REC REC . ( 9.19)
From ( 9.14) we have the following set of equations that describes the balancing current i 2 and balancing voltage error ∆v C (the DC-DC2 converter)

2 1 2 2 2 C C C REC C B C E E v v v i i d dt v d C v i R dt di L - = ∆ - ⋅ = ∆ ∆ + - = . ( 9.20)
Here, product of duty cycle and rectifier current, REC i d ⋅ , is the disturbance for the DC-DC2 converter.

Linearization and Small Signal Model

The small signal model is obtained by the use of the first order perturbation model or Taylor series expansion. Then, Laplace transformation is applied to obtain the rectifier current ( 9.21) and the dc bus voltage ( 9.22) transfer functions.

( ) ( )

0 0 1 sL R s u s i REC + = ( 9.21) ( ) ( ) ( ) ( ) ( ) 4
≅ + - - + -       - = BUS B E E BOOST BUS LOAD BUS B BUS LOAD BUS B LOAD BOOST REC BUS B LOAD BOOST LOAD BOOST BUS REC REC BUS V sC sL R k V P D s i V sC V p V sC P k s v V sC P k sL P k R V V s i s v π π π π ( 9.22)
Transfer functions of the voltage balancing error ∆v C and balancing current i 2 are, (

- - + + + = s D k V V P D s v s D k V V P s v s D V k V P L s V k V P R V D s i s i BOOST BUS C LOAD BUS BOOST BUS C LOAD REC C BOOST BUS LOAD C BOOST BUS LOAD C REC π π π π , ( 9.23)
( ) ( )( )

E E C R sL s i s v + = ∆ 2 , ( 9.24)
where the denominator D(s) is ( )

        + +         + + = 3 2 1 3 2 2 0 2 0 2 π π BOOST BUS C LOAD E BOOST BUS C LOAD E B E B E k V V P R D k V V P L D C R s C L s s D . ( 9.25)
D 0 is steady state duty cycle. Notice that the current i 2 figures in the dc bus voltage v BUS transfer function ( 9.22), and the dc bus voltage figures in the current transfer functions ( 9.23). Substituting ( 9.22) into ( 9.23) and vice versa, we can eliminate i 2 from ( 9.23) and v BUS from ( 9.22). However, in that case the dc bus voltage transfer function will be a third order function, which is complex and difficult to analyse and use in the controller synthesis.

As shown in ( 9.10), the equivalent inductance L E depends on the resonant inductor L S and ratio of the resonant to the switching frequency. The inductor L S is normally very small, in order of several hundred nH. If the DC-DC2 operates close to resonant frequency, it follows from ( 9.10) that the equivalent inductance L E is order of µH. Also, the resistance R E is quite small in comparison to the resistance R 0 . Therefor, we can assume that dominant frequency of the DC-DC2 circuit is much greater than dominant frequency of the dc bus circuit. It will be shown in the following section that the dc bus controller bandwidth is normally limited to a few hundred Hz. That means the dc bus circuit frequency of interest is below 1 kHz. On another hand, the dominant frequency of the DC-DC2 circuit is above 1 kHz. Hence, last part of ( 9.22) and ( 9.23) could be neglected.

Matlab/Simulink Model Verification

To verify transfer functions ( 9.22) and ( 9.23), simulation of the large signal model ( 9.13) and ( 9.14) has been performed in Matlab/Simulink. Frequency response at different frequencies has been simulated and compared with bode diagram of the transfer functions ( 9.22) and ( 9.23). Fig. 9.5 (a) illustrates frequency characteristics of the transfer function v BUS (s)/i REC (s). The solid blue line is computed from ( 9.22) and the red dots are the simulation of the entire large signal model ( 9.13), ( 9.14). Please, note that at low frequency, below 1kHz, the model magnitude and phase characteristics closely match the simulation. At frequency above 1 kHz, the model underestimates the magnitude and phase, because we have neglected the last part in the model. In the applications of our interest (three-phase boost rectifiers with electrolytic dc bus capacitor), the voltage controller is quiet slow, and the model ( 9.22) is accurate enough. However, if the boost converter is used in an application that requires high bandwidth of the dc bus voltage control, the simplified model is not sufficient; the effect of the DC-DC2 converter must be taken into account and the full model used. Fig. 9.5 (b) illustrates bode diagram of the transfer function i 2 (s)/i REC (s). The solid blue line is calculation from ( 9.23) and the red squares are the simulation of the entire large signal model ( 9.13) and ( 9.14). Notice that at low frequency, below 50Hz, the magnitude and phase response of the small signal model and the large signal model are quite different (magnitude is underestimated and the phase is overestimated). At frequencies above 100Hz, the magnitude and phase responses are quite well matched. As mentioned in section 9.1, the DC-DC2 converter operates in open loop and therefore no need for closed loop control of the voltage error ∆v C .

Control Scheme

The Control Objective

The primary control objective is to asymptotically regulate the dc bus voltage v BUS to a desired reference v BUS (REF) . The secondary control objective is regulate the rectifier current in order to obtain 2π/3 radians square waveform of the mains current with minimum total harmonic distortion factor (THD) and the partial weighted harmonic distortion factor (PWHD) [13].

The control scheme of the proposed boost rectifier is illustrated in Fig. 9.6. Please, note that the control scheme is more or less state of the art cascaded control [START_REF] Erickson | Fundamentals of Power Electronics[END_REF], [START_REF] Mohan | Power electronics; converters, applications and design[END_REF], [START_REF]The control handbook[END_REF], [START_REF] Buso | Digital control in power electronics[END_REF]. Two cascaded controllers can be identified: an inner current controller G iREC and an outer voltage controller G vBUS . The inner current controller regulates the rectifier current, while the outer controller regulates the dc bus voltage v BUS and generates the reference i REC_REF for the rectifier current controller. Synthesis of the rectifier current controller is state of the art [START_REF] Buso | Digital control in power electronics[END_REF], and it is not discussed in the dissertation. The dc bus voltage controller design and synthesis is discussed in detail.

The DC Bus Voltage Controller

The control block diagram is illustrated in Fig. 9.7. The rectifier current control loop appears in the dc bus voltage loop as transfer function that can be, for simplicity of the analysis, approximated by first order transfer function ( ) ( ) As a well known issue, the boost converter operating in continuous conduction mode (CCM) is a non-minimum phase system [START_REF] Himmelstoss | Analysis of a smith-predictor-based control concept eliminating the right-half plane zero of continuous mode boost and backboost DC-DC converters[END_REF]- [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF]. This is caused by the boost inductor that imposes right half plane zero (RHPZ) in the dc bus voltage transfer function. A system with the RHPZ is naturally stable system if it operates in open loop. However, when the system is in closed loop, the RHPZ appears in denominator of the dc bus voltage transfer function and as that it limits the system bandwidth [START_REF] Himmelstoss | Analysis of a smith-predictor-based control concept eliminating the right-half plane zero of continuous mode boost and backboost DC-DC converters[END_REF]- [START_REF] Grbovi} | Modeling and control of the ultra-capacitor based regenerative controlled electric drive systems[END_REF], [START_REF]The control handbook[END_REF]. It was shown in section 8.2.2.1 that the boost inductor of the proposed boost rectifier is up to 50% smaller than that of the ordinary single-switch boost rectifier. That means the RHPZ frequency is higher and therefore the dc bus voltage bandwidth can be higher too. Moreover, the smaller boost inductor, the higher bandwidth of the rectifier current controller [START_REF] Buso | Digital control in power electronics[END_REF].

1 1 _ + ≅ REC REF REC REC sT s i s i . ( 9
) ( ) ( ) ( ) s D k V P L k k V s P L k s s v s v BUS I REC LOAD I P REC LOAD P REF BUS BUS 2 0 2 0 2 _ + - + - = , ( 9.27) ( ) ( ) ( )
I REC LOAD I P REC LOAD P REC BUS B REC REC BUS B BUS k V P L k k V s P L k V V C s T V V C s s D
For simplicity of the analysis and the voltage controller design, one can assume that the boost inductor (L 0 ) is small enough. Thus, the RHPZ and the current controller response time T REC ) could be neglected. This yields the simplified transfer function ( ) ( ) ( )

I REC P REC BUS B I P REC REF BUS BUS k V k sV V C s k sk V s v s v + + + ≅ 2 _ . ( 9.29)
Proportional and integral gains of the voltage controller are computed from ( 9.29) using the Butterworth criteria (ζ BUS =0.7) [START_REF]The control handbook[END_REF].

REC BUS B B I REC BUS B B P V V C f k V V C f k 2 2 4 4 π π = = , ( 9.30)
where f B is the dc bus voltage controller bandwidth.

The Bandwidth versus the Rectifier Current Ripple

A three-phase diode boost rectifier that operates in CCM is not a ripple-free converter. The dc bus voltage is not zero ripple voltage, as given in ( 8.28) [START_REF] Grbovi} | A novel three-phase diode boost rectifier using hybrid half-DC-BUS-voltage rated boost converter[END_REF]. The voltage ripple is reflected on the rectifier current reference via the dc bus voltage controller G vBUS . To avoid distortion of the rectifier current, a few solutions are proposed in the literature [START_REF] Chen | Switch mode rectifier with digital robust ripple compensation and current waveform controls[END_REF]- [START_REF] Prodic´ | Dead-zone digital controllers for improved dynamic response of low frequency rectifiers[END_REF]. The simplest one is to design the dc bus voltage controller with low bandwidth. Another solution is ripple cancellation techniques [START_REF] Chen | Switch mode rectifier with digital robust ripple compensation and current waveform controls[END_REF], or the voltage dead zone control [START_REF] Prodic´ | Self tuning digitally controlled low harmonics rectifier having fast dynamic response[END_REF], [START_REF] Prodic´ | Dead-zone digital controllers for improved dynamic response of low frequency rectifiers[END_REF]. In this dissertation, a conventional technique is considered; the voltage controller bandwidth is low enough to avoid significant distortion of the rectifier current.

Let us find maximum bandwidth for the rectifier current ripple given as a parameter. Peak-to-peak dc bus voltage ripple has been computed in section 8.2.2.2 as

( ) BUS m BUS LOAD BUS C V P v ω 6 2 35 2 ≅ ∆ , ( 9.31)
where

m m f π ω 2 =
is the mains angular frequency. The voltage ripple equation ( 9.31) is valid only if the rectifier current is constant (the current ripple is small enough to be neglected

REC REC I i << ∆
). The ripple imposed on the current reference by the dc bus voltage ripple via the voltage controller is ( )

m I m P BUS REC k k v i ω ω 6 6 2 2 + ∆ = ∆ . ( 9.32)
The rectifier current ripple at 6 th harmonic of the mains frequency can be defined as relative ripple ( )

pu ∆
in respect to the rectifier average current ( 8.4)

( ) ( ) BUS LOAD BOOST REC REC V P k pu I pu i 3 π ⋅ ∆ = ⋅ ∆ = ∆ , ( 9.33)
where k BOOST is the boost factor ( 8.8). From ( 9.32) and ( 9.33) it follows that ( )

( ) ( ) ( ) 2
1 75 . 8 1 2 6 2 max - ∆ + pu f f m B ( 9.35)
Note that the dc bus capacitance C BUS does not figure in ( 9.35). The maximum bandwidth depends on the current ripple and the mains frequency only. The bandwidth versus current ripple is plotted in Fig. 9.8.

Experimental waveforms of the ac component of the rectifier current and the dc bus voltage are depicted in Fig. 9.9 (a). The amplitude spectrum of the rectifier current is depicted in Fig. 9.9 (b).

Matlab/Simulink Simulation Results

The voltage controller has been designed using simplified transfer function ( 9.29), for two different value of the bandwidth, f B =10Hz and f B =100Hz. Then, frequency response of the dc bus voltage control has been computed for different conditions; simplified model ( 9.29), the response time (T REC =0) of the current controller neglected, and a system without approximations ( 9.27). The results are presented in Fig. 9.10. Notice, there is not significant difference in the magnitude response for the full model and approximated one. In the phase response, however, there is significant deviation at frequency above 1 kHz.

The boost rectifier with control was simulated using a Matlab/Simulink average model ( 9.13), ( 9.14). In this model, we have assumed that i S(AV) =i D(AV) =1/2 i 2(AV) . The simulation has been done for two different controller bandwidths, f B =10Hz and f B =100Hz. The dc bus voltage and rectifier current response on the step load are illustrated in Fig. 9.11. In the first case, the dc bus voltage has over-shoot and under-shoot of approximately 70V (11%) with settling time of approximately 100ms. The rectifier current ripple can be neglected. In the case that the controller bandwidth is 100Hz, the over-shoot and under-shoot are approximately 5V (0.7%). The current ripple is however greater, approximately 0.5A (4.5% of the rectifier current). The voltage balancing error ∆v C =v C1 -v C2 and compensation current i 2 averaged over the switching period are depicted in Fig. 9.12. The voltage error is very small, below 15mV. The average current i 2 follows the shape of the rectifier current and the instantaneous duty cycle, as predicted in ( 8.36).

Experimental Results

The model and control scheme proposed in this chapter have been experimentally verified on a 5.5kW prototype. The control algorithm, PWM and protection functions were implemented in a fixed-point 32bit digital signal processor (DSP). The rectifier current controller is executed at 100 kHz, while the dc bus voltage controller is executed at 5 kHz. The dc bus voltage controller was designed for bandwidth of 50Hz.

The rectifier specification is:

V BUS =650V, P LOAD =5500W, V MAINS =400V, C B1 =C B2 =1600µF (C BUS =800µF), L 0 =300µH, f SW1 =100 kHz, f SW2 =50 kHz.
f B =100Hz (c, d). P LOAD =550-5500W, V BUS =650V, V REC =600V, L 0 =300µH, C BUS =800µF. (a) (b) (c) (d)
P LOAD =550-5500W, V BUS =650V, V REC =600V, L 0 =300µH, C BUS =800µF.
The spikes circled in the green are caused by the notches that are coming from the mains supply. Those disturbances can be reduced by the current controller having higher bandwidth or using some advanced current controller techniques, such as resonant or repetitive controller [START_REF] Mattavelli | Repetitive-based control for selective harmonic compensation in active power filters[END_REF]- [START_REF] Escobar | Repetitive-based controller for a UPS inverter to compensate unbalance and harmonic distortion[END_REF].

Performance of the dc bus voltage controller was tested on variation of the dc bus load. Experimental waveforms of the dc bus voltage and rectifier current are depicted in Fig. 9.14. The controller response on step load, 10% to 100% (550W to 5500W) is illustrated in Fig. 9.14 (a). The voltage undershoot is approximately 13 V (2% of the dc bus voltage) and response time is approximately 10ms. Fig. 9.14 (b) shows the waveforms when the load is reduced from 100% to 10%. The voltage over-shoot is approximately 14V (2.15%). Notice that the rectifier current is zero during the transient because the rectifier is a uni-directional device that does not allow the current in opposite direction. Thus, the current controller is saturated during this time. As a consequence, the dc bus voltage has an undershoot of approximately -9V. Once the current controller is out of saturation, the dc bus voltage settles down at the reference. This effect could be reduced, even completely eliminated by appropriate current control, but this is not subject of this dissertation.

SINGLE PHASE OPERATION 10.1. Short Introduction

Three-phase induction motors are the most popular motors in industry and other applications since the age of Tesla [1]- [3]. The three-phase motors are more efficient, less cost, last longer and have better torque/speed characteristic than single-phase motors. However, very often the three-phase public network is not available in some area where it may not be economical to install three-phase distribution network. In such applications, conversion from single-phase to three-phase is necessary.

A multi-phase system (including a three-phase system) can be represented by an equivalent two-phase system and vice versa. Single-phase system, however, cannot be represented by a multi-phase system of direct order [START_REF] Krause | Analysis of electric machinery and drive systems[END_REF]. Two-phase to three-phase transformation is easily possible by the use of the Scott transformer, while single-phase to three-phase transformation is not possible by the use of passive devices such as transformers. For this, more complex conversion systems, such as motor-generator groups or semiconductor power converters are used. The first solution has no practical value in the era of advanced power converters. Static power converters are used in most applications.

The single-phase supplied rectifier with passive LC dc bus filter and three-phase pulse width modulated (PWM) inverter is the most common solution, as shown in Fig. 10.1 (a). The dc bus capacitor is a large electrolytic capacitor, while the inductor is small or absent. Such a rectifier works as a peak detecting circuit; the dc bus voltage is charged on the peak mains voltage and the mains current is a train of narrow pulses. Apart the fact that such a rectifier is cost effective and robust, the drive manufacturers do not recommende this solution because of a few limitations:

-The input current is distorted, with peaks that are 5 to 10 times of the fundamental RMS current. The total harmonic distortion factor is as high as 150%, even higher. The power factor is low.

-A bulky dc bus capacitor is necessary to keep the dc bus voltage ripple acceptably low.

-A filter inductor must be used to limit peak of the input current. The inductance value is however limited because the dc bus voltage quickly decays with the inductance.

-The dc bus voltage is reduced in comparison to three-phase supplied drive. Hence, available motor voltage is reduced too.

-The drive life time is limited by the dc bus capacitor life time (the capacitor is the most stressed component).

-The drive may be de-rated by 50% when supplied from single-phase, which means higher installation cost per kW.

The single-phase single-switch and double-switch boost rectifier is the most popular solution in applications that require a boosted dc bus voltage and sinusoidal or pseudosinusoidal input current, Fig. 10.1 (b), (c), [START_REF] Singh | A review of single-phase improved power quality ac-dc converters[END_REF]. This topology is often used in low power supplies such as PC and small telecom supplies. In variable speed drives, however, this topology is rarely used because of cost, size and efficiency.

The split-capacitor three-leg rectifier/inverter is used in low cost low power variable speed drive applications, such as air-conditioning and home appliances [START_REF] Jacobina | Induction motor drive system for low-power applications[END_REF], [START_REF] Lee | Control of single-phase-to-three-phase ac-dc-ac PWM converters for induction motor drives[END_REF], Fig. 10.1 (d). This topology offers the lowest count of the active and passive components in comparison to the other solutions. However, two drawbacks make this topology inappropriate in higher power industrial applications; 1) The dc bus capacitor current stress at low frequency, and 2) the output current ripple. A three-phase diode boost rectifier based on half-dc-bus-voltage rated topology has been presented in chapter 8 and [START_REF] Grbovi} | A novel three-phase diode boost rectifier using hybrid half-DC-BUS-voltage rated boost converter[END_REF]. The main feature of the topology is that the switches and diodes are rated at half of the dc bus voltage and fraction of the rectifier current. Power rating, size and efficiency of the entire rectifier strongly depend on the ratio of the dc bus voltage to the rectifier voltage (the boost factor). For example, if the boost factor is low, the power converter efficiency is as high as 98 to 99%.

In this chapter, three-phase half-dc-bus-voltage rated boost rectifier that operates under single-phase supply conditions is analyzed. In section 10.2 the principle of the proposed solution is analyzed and the main equations are derived. Further, in section 10.3, and 10.4, the main conversion structure is analyzed and design guidelines are given. The dc bus capacitor design is discussed in section 10.5.

Single Phase Operation of the Half-DC-Bus-Voltage Rated Boost Rectifier 10.2.1. The Principle

The basic principle of single-phase supplied three-phase boost rectifier and relevant waveforms are illustrated in Fig. 10.2 (a). Notice that the circuit diagram is the same as Fig. The average current i 1 which flows from the DC-DC1 converter into the capacitors mid point is not zero. Since the capacitors average current must be zero in steady state, one additional converter DC-DC2 is used to compensate the current i 1 and maintain ratio between the voltages v C1 and v C2 constant.

A Short Analysis

Let the mains voltage be purely sinusoidal voltage

( ) ( ) t V t v m PEAK mains ω sin = . ( 10.1)
Also, let us assume that the rectifier current i REC is constant during a period that the rectifier instantaneous voltage is greater than half of the dc bus voltage (see Fig. 10.2 (b)).

   - ≤ ≤ = otherwise t I t i m REC REC 0 ) ( 0 0 α π ω α ( 10.2)
The threshold angle 0 α is

2 arcsin 2 arcsin 0 BOOST PEAK BUS k V v = = α , ( 10.3)
where the boost factor was defined in ( 8.4) as

PEAK BUS BOOST V v k = . ( 10.4)
The rectifier current ( 10.2) is idealized. It has been assumed that the switching frequency is far higher than the mains frequency, and therefore small boost inductor L 0 is used. This is a correct assumption because the switching frequency is as high as 50 kHz or even higher in comparison to the mains frequency of 50Hz. As a consequence of such an The rectifier voltage is

       - ≤ ≤ = otherwise v t t k v t v BUS m m BOOST BUS REC 2 sin ) ( 0 0 α π ω α ω . ( 10.5)
To find the magnitude of the rectifier current, one can use the instantaneous input power, ( )

     - ≤ ≤ = = otherwise t t I k v t i t v t p m m REC BOOST BUS REC REC IN 0 sin ) ( ) ( 0 0 α π ω α ω . ( 10.6)
Assume that the conversion losses can be neglected. Thus, the average input power P IN is equal to the load power P LOAD , ( ) ( )

0 0 cos 2 1 α π ω ω π π REC BOOST BUS m m IN LOAD IN I k v t d t p P P = = = ∫ . ( 10.7)
The rectifier peak current is computed from ( 10.7) as

0 cos 2 α π BOOST BUS LOAD REC k v P I = , ( 10.8)
where the angle 0 α ( 10.3) is a function of the boost factor ( 10.4).

THD, PH and PWHD versus the Boost Factor

The mains current is quasi-square waveform with magnitude I REC and duration of π-2α 0 radians. The current can be expanded in Fourier series

( ) ( ) ∑ ∑ +∞ = +∞ = = + = 1 0 0 1 sin cos cos 2 sin k m BOOST BUS LOAD k k m k MAINS t k k k k v P t k I i ω α α ψ ω . ( 10.9)
The mains RMS current and the first harmonic RMS current are Total harmonic distortion factor (THD), partially weighted harmonic distortion factor (PWHD) and power factor (PF) are computed from ( 10.10) as . This is the same THD that can be obtained with the three-phase diode boost rectifier.

( ) ( ) ( ) 1 cos 2 8 0 0 1 2 1 2 - - = - = α α π π RMS RMS RMS I I I THD , ∑ =         =

Remark:

The THD is computed taking into account all higher harmonics (2 to ∝), while the PWHD factor is computed using IEC 61000-3-12 norm definition ( 8.13), [13].

The DC-DC1 Converter under Single Phase Supply

The DC-DC1 converter basically operates in the same way as the three-phase supplied rectifier. Therefore, main part of the analysis given in chapter 8 will not be repeated here. The duty cycle is computed from ( 8.15) and ( 10.5) as ( )

     - ≤ ≤         - = otherwise t k t t d m BOOST m m 1 sin 1 2 0 0 α π ω α ω ω . ( 10.12)
Maximum boost factor when the rectifier is supplied from three-phase mains has been defined under condition that the rectifier current is continuous. However, this criterion cannot be used in single phase supply because the rectifier current is naturally discontinuous (zero during period 0 α ). The criterion for single-phase supply can be controllability of the dc bus voltage; the peak of the input voltage cannot be lower than half of the dc bus voltage. From this we have

( ) ( ) 2 sin 2 lim 0 2 max 0 = = → α π α BOOST k . ( 10.13)
This value is, of course, not realistic because in such a case the conduction period of the rectifier current is zero, and therefore the peak current is infinite. In most applications, the boost factor is often not greater than 1.5, and therefore the limitation ( 10.13) has no relevance.

The Mains Diode Commutation Effect

Once the rectifier voltage reaches the voltage v C1 , at the angle

0 α π α - =
, the duty cycle is limited to 1 (the boost inductor is permanently connected to the v C1 via the switch S 0 ). Then, the current i REC will start decreasing towards zero. After delay ∆α, the current reaches zero and mains diode D mains is blocked. The current remains zero and the rectifier voltage v REC jumps to the v C1 and the commutation is finished. i REC . Note that the rectifier current is not constant during the conduction period (α 0 , π-2α 0 ).

The current variation is caused by the dc bus voltage ripple that is reflected to the rectifier current reference via the dc bus voltage controller. Fig. 10.9 (b) shows a zoomed in plot of the waveforms. Please, note two irregularities in the current waveform. The first one is the mains diode commutation effect (denoted by the blue circle). The second irregularity is over-shoot (denoted by the red circle). The current over-shoot is caused by saturation of the rectifier current controller (the wind up effect). This problem could be fixed by proper design of the rectifier current controller.

The Switch and Boost Diode Stress Analysis

The switch average and RMS current computed over the mains half period are

        - - =         - = ∫ - 2 cos 2 sin 1 2 1 0 0 0 0 0 α α π ω ω π α π α BOOST BUS LOAD m BOOST m REC AV S k v P t d k t I I , ( ) ( ) ( )
        -       - = ∫         - = - BOOST BUS LOAD m BOOST m REC RMS S k v P t d k t I I 0 0 0 2 0 cos 2 cos 1 sin 1 2 1 0 0 α α π π α ω ω π α π α . ( ( 10.15) ( ) ( )
The switch conduction losses are

( ) ( ) 2 0 0 0 0 0 RMS S S AV S S S I r I V P + = .
( 10.17)

The switch S 0 is approximated by threshold voltage V S0 and dynamic resistance r S0 . The switching losses averaged over the mains half period are

( ) ( ) ( ) 0 0 cos 2 2 2 2 1 0 0 α α π ω π α π α - + = + = ∫ - SW OFF ON BOOST N N LOAD m SW OFF ON N N REC BUS Sw f E E k I V P t d f E E I V I v P , ( 10.18)
where f SW is switching frequency. E ON and E OFF are switching energy at given conditions; rated voltage V N and current I N .

Similar calculation could be applied on the boost diode D 0 . The diode is approximated by threshold voltage V D0 and dynamic resistance r D0 . E Q is reverse recovery energy at given conditions; rated voltage V N and current I N .

Boost Inductor

The inductor losses averaged over the switching period (local average) have been discussed in section 8.2.2 and given by ( 8.23). Here, that equation is re-used and adapted to single-phase condition taking into account that the inductor current is zero if the input instantaneous voltage is lower than half of the dc bus voltage. The inductor local average losses are

( ) ( ) ( ) ( )            - ≤ ≤          ∆ + +         = otherwise t t i R R k v P R t P m FREQUENCY HIGH m REC fSW C fSW L FREQUENCY LOW BOOST BUS LOAD DC L m L 0 12 ) ( ) (
where R L0(DC) is the inductor winding resistance at low frequency, R L0(fsw) is the inductor winding resistance at the switching frequency. The resistance R C(fsw) is the core equivalent resistance [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF]. The losses averaged over half of the mains period can be computed as

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 4
FREQUENCY HIGH m BOOST m BOOST m fSW C fSW L FREQUENCY LOW BOOST BUS LOAD DC L m m L AV L t d k t k t i R R k v P R t d t P P ∫ ∫ - -         -         - ∆ + + -         = = 0 0 0 0 2 2 2 2 max 0 0 2 0 0 0 0 sin 1 2 1 sin 12 16 ) ( ) ( 2 cos 2 1 α π α α π α ω ω ω π π α π α π ω ω π . ( 10.23)
Another parameter that is important for design of the boost inductor is the peak current,

2 cos 2 (max) 0 ) ( 0 REC BOOST BUS LOAD PEAK L i k v P I ∆ + = α π . ( 10

The DC-DC2 Converter Operation under Single Phase Supply

The DC-DC2 converter has been analyzed in detail in chapter 8, and therefore the main part of analysis will not be repeated, except a few details that are necessary to follow the discussion.

From ( 10.2), ( 10.8) and ( 10.12) one can find local average value of the current i 2(AV) ,

( ) ( ) ( ) ( )      - ≤ ≤         - = = = otherwise t k t k v P t d t i t i t i m BOOST m BOOST BUS LOAD REC AV S AV 0 sin 1 cos ) ( ) ( 0 0 0 0 2 α π ω α ω α π . ( 10.25)
The switches and diodes average and RMS current over the half mains period are where the switches and diodes are approximated by constant threshold voltage V S and V DF and dynamic resistance r S and r D . Switching losses are neglected since the switches commute at zero current conditions. If necessary, the losses due to the switch parasitic capacitance can be taken into account.

( ) ( )         - - = 1 cos 2 2 0 0 0 α α π BOOST BUS LOAD AV S k v P i , ( 10.26) ( ) ( )
        + - -         + × = 2 2 sin cos 4 2 2
The resonant circuit RMS current computed over a half the mains period is ( )

        + - -         + × =

The DC Bus Capacitor Design

Design of the dc bus capacitor in single-phase rectifiers is a critical design step. Unlike three-phase boost rectifiers, where the dc bus capacitor current stress is very low, the dc bus capacitor in single-phase boost rectifiers is stressed on the second harmonic. The current magnitude is order of the fundamental harmonic, even higher in case of the passive rectifier with LC filter. The dc bus capacitor is designed for two criteria; low frequency current ripple, in this case twice the mains frequency (100Hz) and the dc bus voltage ripple. To compute the current and voltage ripple, the instantaneous power balance is used.

CBUS BUS LOAD REC REC IN i v P i v p + = = , ( 10.30)
where i CBUS is the dc bus capacitor current. It is assumed in ( 10.30) that instantaneous power of the capacitors C B1 , C B2 and C S , and inductors L 0 and L S could be neglected in comparison to the dc bus capacitor C BUS . Substituting ( 10.6) into ( 10.30) yields the dc bus capacitor current ( )

     - - ≤ ≤ - = otherwise t t v P t i m m BUS LOAD CBUS 1 1 sin cos 2 0 0 0 α π ω α ω α π , ( 10.31)
where 0 α is the threshold angle ( 10.3).

The Voltage Ripple

From ( 10.31) and the dc bus circuit one can write a differential equation 0 0 .32) Peak-to-peak voltage ripple is computed from ( 10.32) as

α π ω α π + ≤ ≤ - - = t v P dt dv C m BUS LOAD BUS BUS . ( 10
( ) m BUS AV BUS LOAD BUS C v P v ω α 0 2 = ∆ .
( 10.33)

The dc bus capacitance is computed from ( 10.33) as

( ) ( ) max 0 2 BUS m AV BUS LOAD BUS v v P C ∆ ≥ ω α , ( 10.34)
where max BUS v ∆ is maximum dc bus voltage ripple given as a design parameter. Fig. 10.11 illustrates the dc bus capacitance versus the boosting factor. The capacitance is normalized on 1kW and 1V peak-to-peak ripple. This means, the value from the graph has to be multiplied by the load power in [kW] and divided by the peak-to-peak voltage ripple in [V]. For example, the boosting factor is k BOOST =1.25, the power rating is P LOAD =11kW and the voltage ripple is ∆v BUS =20V. From the graph in Fig. 10.11 it follows that the dc bus capacitance is C BUS ≥3630µF.

The Capacitor Current Stress

Assuming that the dc bus voltage ripple is negligible in comparison to the average dc bus voltage,

) ( AV BUS BUS v v << ∆
, we can compute the capacitor current ripple as

DISCUSSION AND CONCLUSIONS

Comparison with State of the Art Solutions

In this chapter, the half-dc-bus-voltage rated boost rectifier is compared with state of the art solutions. The comparison is done for three-phase and single-phase supplied system. The size of the active components (switches and diodes), filter inductor(s) and capacitor(s) and conversion losses are compared.

Three Phase Operation

In this section, the new boost rectifier supplied from three-phase mains is compared with some state of the art solutions. Three parameters are compared: rating of active switches, the conversion losses and size of the passive components.

Semiconductor Switches

Like it has been done in chapter 6, the switches comparison is based on two parameters, the switch utilization factor and the switch voltage rating.

o The Switch Utilization Factor

The switch utilization factor of the DC-DC1 converter is computed by the definition, In some applications, the switch apparent power can be determined as

( ) ( ) ∑ = = N j j AV S j S SW I V S 1 ) ( max , ( 11.2)
where I S(AV) is the switches average current. The switch apparent power definition ( 11.2) could be used in resonant converters when the IGBTs are used as switches. In that case, the switches losses depend mainly on the switch average current, while the RMS and peak current have no significant influence on the losses. Definition ( 11.2) will be used to compute the switch utilization factor of DC-DC2.

The switch utilization factor of the new boost converter is computed from the definition ( 8.4), ( 8.30) and ( 8.42) as o The Switches Voltage Rating As mentioned in chapter 6, section 6.2.1.1, the switch voltage rating is a factor that cannot be compared by simple comparison of the switch utilization factor. A semiconductor switch conduction and switching performance depend strongly on the switch voltage rating and the switch technology. Lower voltage rating means lower conduction losses, better switching performance, higher efficiency and lower cost. For example, let us consider a 400V three-phase rectifier. The dc bus voltage is v BUS =700 to 800V. For the ordinary single switch boost converter, the switch and boost diode voltage rating is 1000V to 1200V. For such voltage rating, 1200V IGBT and 1000V fast diode are used. In this case, maximum switching frequency is limited by the switching performance of the devices, mainly by the IGBT. To reduce switching losses, soft switching techniques are often used [START_REF] Jang | A new, soft switching, high power factor boost converter with IGBTs[END_REF], [START_REF] Jang | High power factor soft switched boost converter[END_REF]. This however requires additional passive and active components, which make the switch utilization factor even worst than ( 11.4). In contrast to this, in the proposed hybrid half-dc-bus-voltage rated boost rectifier, the switches and diodes voltage rating is 500V. In this case, 600V rated IGBT or 500V super junction MOSFET and ultra-fast boost diode can be used. Switching losses of 600V rated IGBT and boost diode are three to four times lower than switching losses of a 1200V rated IGBT and boost diode. Conduction losses of a 600V rated device are also lower in comparison to a 1200V rated device. If the IGBT losses are compared with high voltage MOSFETs, the difference in conduction losses is significant, because the drain source onstate resistance strongly depends on the voltage rating [START_REF] Grbovi} | High-voltage auxiliary power supply using series-connected MOSFETs and floating self-driving technique[END_REF].

The Boost Inductor Size

Size of an inductor could be defined in general case as where L 0 is inductance at rated current, I RMS the inductor RMS current and I RMS is the inductor peak current.

As the inductor current is the same for the both topologies, the new one and ordinary single-switch, the inductors relative size ( 11.5) is ratio the inductance of half-dc-bus-voltagerated topology to the inductance of the single-switch topology, where subscript ( ) HB and ( ) SSW denote hybrid topology and single switch topology. The inductance of the ordinary single-switch boost rectifier is computed from the current ripple ( )

2 0 d d f L v i SW BUS REC - = ∆ , ( 11.7)
where duty cycle d is ( )

3 2 3 sin 1 π ω π ω ≤ <         - =

Single Phase Operation

In this section, the new boost rectifier operating in single-phase supply mode will be compared with two state of the art solutions, single-switch boost rectifier and the ordinary diode rectifier. Size of the boost inductor and the switch utilisation factor will be compared for the new boost rectifier and the ordinary single switch rectifier. The mains current quality and the dc bus capacitor current and losses are compared for the presented rectifier and diode rectifier with passive LC filter.

The Boost Inductor Size

The inductor peak and RMS current for single-switch boost topology are where subscripts (HB) and (SSW) denote the hybrid boost rectifier and the single switch boost rectifier. Fig. 11.4 shows relative size of the boost inductor (comparison of the inductor for the proposed boost rectifier and the ordinary single switch boost rectifier) versus the boost factor. The inductor is approximately 50% at minimum boost factor k BOOST =1 and approximately 95% at maximum boost factor k BOOST =1.7.

S 0 : MOSFET 1000V 20A D 0 : FAST DIODE 1000V 20A V S0 r S0 *E ON +E O V D0 r D0 *E Q 0 600mΩ 30µJ/A 1.25 V 15 mΩ 15µJ/A *Switching losses at V N =600V T J =150˚C ( ) 2 2

The Switches Utilization Factor

The switch utilization factor of the hybrid boost converter is computed from the definition ( 6.1) as ( ) ( )

0 0 0 cos 2 2 2 cos 2 α α π π α - - + = BOOST BOOST HB k k SUF . ( 11.14)
The switch utilization factor of the ordinary single-switch boost converter is

Three Phase versus Single Phase Supply

Very often, a variable speed drive is designed to operate in three-phase as well as in single-phase supply mode. In this section, the hybrid boost rectifier supplied from three-phase and single-phase mains is discussed. The following parameters are compared: The mains peak and RMS current, the switches and diodes losses, and size of the boost inductor.

The Mains Current

Equations for the relevant variables (peak, average and RMS currents) of three-phase supplied diode boost rectifier have been developed in chapter 8. Those equations are re-used and relative currents are computed. The relative currents are computed as ratio of the currents of single-phase supplied rectifier to the currents of the three-phase supplied rectifier. The currents for single-phase supply are computed at three different loads: nominal (Pn), 80% of nominal (0.8Pn) and 60% of nominal (0.6Pn). Fig. 11.7 shows the mains peak current and RMS current versus boost factor. Please notice that RMS and peak current increase with the boost factor. At nominal power, singlephase supplied rectifier draws 73% more current at minimum boost factor. This is the factor of 3 , which is ratio of single-phase to three-phase current at the same power.

Conclusions

A novel three-phase diode boost rectifier based on the half-dc-bus-voltage-rated topology has been proposed and discussed in part three of the dissertation. The topology has been extensively analysed and some design guidelines given. Modelling aspects and the control scheme have been given too. The proposed topology including control scheme has been verified by Matlab/Simulink simulation and a set of experiments on a laboratory prototype. The simulation and experimental results has confirmed theoretical analysis. Singlephase operation of the proposed boost rectifier has been discussed and experimentally verified too.

The advantages of the proposed solution over single-switch and double boost rectifier are:

o Power semiconductor switche size and losses. The switches utilization factor of the new boost rectifier is higher than that of the state of the art solutions. This means that the switch cost is lower. The switch voltage rating is half of that of the single-switch boost rectifier. Therefore, better and more efficient devices could be used.

o The passive power components size and losses. The boost inductor is smaller than the inductor of single-switch boost rectifier. Thus, the inductor losses are reduced by factor 1.5 to 2. However, in comparison to the double-boost topology, the inductor of the proposed rectifier is slightly bigger.

Regarding the mains current quality and the dc bus voltage boost, there is not a difference between the new topology and state of the art single-switch and double boost topology. The mains current is square waveform with conduction angle of 2π/3 radians, while the dc bus voltage is boosted and actively controlled. However, compared to the state of the art passive diode rectifier, the current shape is significantly better. THD is approximately 30% instead of 100 to 150%, while the peak and RMS current are reduced by factor of 3.5 and 1.5. The dc bus voltage quality is better too in comparison to simple diode rectifier.

A disadvantage of the proposed boost rectifier is need for an auxiliary dc-dc converter to control the capacitors mid point voltage. The auxiliary converter is rated at a fraction of the conversion power. Therefore, the losses of that auxiliary converter can be quite low in comparison to the total conversion losses [START_REF] Grbovi} | A novel three-phase diode boost rectifier using hybrid half-DC-BUS-voltage rated boost converter[END_REF]. It will be shown in chapter 12 that the auxiliary converter can be re-used as a part of the interface dc-dc converter that has been discussed in chapter 4.

The proposed boost rectifier can effectively be a replacement for passive diode rectifiers as well as single-switch and double boost rectifier.

THE PRINCIPLE

Introduction

As discussed in the part two and three of the dissertation, some technical issues in application of modern controlled electric drives are still challenging issues. The following issues are identified as the most critical issues:

1) Saving of the drive system braking energy,

2) The system immunity on the mains power supply interruption,

3) The drive input current quality, 4) The drive dc bus voltage control and stability, 5) Single-phase supply, and 6) Reduction of the mains peak power.

The issues 1 and 2 have been discussed and a new solution proposed in the part two, chapters 3 to 6. The issues 3 to 5 have been discussed and a new solution proposed in the part three, chapters 7 to 11. In the part four, a solution for the six issues is discussed.

The three-terminal energy storage and power factor correction device is proposed as a solution to solve the above-mentioned issues. In chapter 12, the three-terminal energy storage and power factor correction (PFC) device is analysed and some design guidelines are given. The model and control aspects are discussed in chapter 13. The proposed solution is validated by Matlab/Simulink simulation and a set of experiments on a 5.5kW laboratory prototype. The results are presented and discussed.

The Principle

The basic principle of the proposed regenerative electric drive with the three-terminal energy storage and PFC device is illustrated in Fig. 12.1 (a). One can distinguish three-phase diode rectifier, dc bus capacitor C BUS , dc bus load, storage capacitor C C0 and the threeterminal power converter designated as the loss-free transformer (LFT). The terminal 0 is connected between the rectifier and the dc bus plus rail, the terminal 1 is connected in parallel with the dc bus, and the terminal 2 is connected on the storage capacitor C C0 . The storage capacitor is an electrical double layer capacitor (EDLC), well know as the ultra-capacitor. The LFT is controlled by a control variable m(t). Internal structure of the LFT is depicted in Fig. 12.1 (b). The LFT is composed of two dc-dc converters, namely DC-DC1 and DC-DC2, and two series connected capacitors C B1 and C B2 . Role of the DC-DC1 converter is to generate the voltage v 0 in order to regulate the rectifier current i REC and boost the dc bus voltage v BUS . The DC-DC2 converter has two roles. The first one is to assist to the DC-DC1 converter when the drive is supplied from the mains. More precisely, the DC-DC2 converter has the role to maintain the voltage v C1 and v C2 in a constant ratio v C1 =v C2 =v BUS /2. The second role of the DC-DC2 converter is to be the interface between the ultra-capacitor C C0 and the drive when the drive operates in the braking mode or the ultra-capacitor motoring mode [START_REF] Grbovi} | Regenerative controlled electric drive with extended ride-through capability using an ultra-capacitor as energy storage device[END_REF].

The System Operating Modes

A controlled electric drive with the ultra-capacitor energy storage device may operate in several different modes, depending on the drive load and status of the mains. The operating modes are described hereafter. Fig. 12.3 shows the power-flow diagrams, and Fig. 12.4 shows the waveforms for different operating modes. The signification of the voltages V BUSmax , V BUS(REF) , V BUSmin , U C0max , U C0inM and U C0min that appear in Fig. 12.4 is discussed later on in the following section. a) Motoring mode from the mains (MM). The drive is supplied from the mains and running in the motoring mode. The input and output power are equal, P IN =P OUT . The power ∆P circulates between the converters DC-DC2 and DC-DC1. This circulating power contributes boosting and control of the dc bus voltage v BUS . The ultra-capacitor power is P C0 =0 and the ultra-capacitor voltage is constant u C0 =U C0inM . The DC-DC1 actively regulates the dc bus voltage to the reference V BUS(REF), where the reference is higher than the mains phase to phase peak voltage. c) Standby mode (STB). The drive is in the standby mode, and no energy flow between the input, output and the ultra-capacitor. The DC-DC2 converter actively regulates the dc bus voltage to the reference V BUSmax . d-1) Motoring-energy recovery mode (MC 0 ). The drive operates in motoring mode. The energy required for the drive acceleration is recovered from the ultra-capacitor via the converter DC-DC2. The power P C0 is negative and the ultra-capacitor voltage decreases towards U C0inM . The DC-DC2 converter actively regulates the dc bus voltage to the reference V BUSmax . d-2) The ride-through operation mode (RT). The mains supply is interrupted, and therefore the drive is supplied from the ultra-capacitor via the power converter DC-DC2. The power P C0 is negative and the ultra-capacitor voltage decreases towards U C0min . The DC-DC2 converter actively regulates the dc bus voltage to the reference V BUSmin .

e) The ultra-capacitor charging mode (MM-CH). The mains supply is recovered and then the ultra-capacitor is charged to the pre-defined intermediate voltage u C0 =U C0inM . The DC-DC1 converter actively regulates the dc bus voltage to the reference V BUS(REF) .

f) The mains peak power filtering mode (MPFM). The drive operates in the mains motoring mode. If the load high during a short period, the input power is limited and the drive load is supplied from the ultra-capacitor. Once the load is reduced, the ultra-capacitor is recharged from the mains.

The DC Bus Voltage Reference

Fig. 12.5 illustrates the signification of the reference voltages V BUSmax V BUS(REF) and V BUSmin . The OBF signifies Over-Braking Fault, and USF signifies Under Supply Fault. When the system operates in the mains motoring mode, the dc bus voltage is regulated to the reference V BUS(REF) that must be greater than the maximum of the supply voltage (to be able to control the rectifier current). In order to avoid unnecessary charge and discharge of the ultracapacitor, the dc bus voltage references V BUSmin and V BUSmax must stay outside of the normal operation range, as shown in Fig. 12.5. On other side, to prevent the system fault, either OBF or USF, the dc bus voltage references must not be in the forbidden regions. Therefore, the reference V BUSmin is located within an interval [USF, Min Input Voltage] while the reference V BUSmax is located within an interval [V BUS (REF) , OBF]. The reference V BUS is located within an interval [Max Input Voltage, OBF]. Once the drive load becomes negative, the drive starts the braking phase (B) and the energy is transferred from the load to the drive dc bus. The dc bus voltage v BUS elevates towards the upper reference V BUSmax and then stays regulated to that level. At the same time, the input current i MAINS falls to zero. The ultra-capacitor voltage increases and the current decreases since the charging/discharging power is assumed constant. When the braking phase is finished, the drive load becomes again positive and the drive turns to motoring mode again (MC 0 ), but this time supplied from the ultra-capacitor. The current i C0 turns negative and the voltage u C0 starts to decrease towards the reference U C0inM . Once the ultra-capacitor voltage reaches the reference U C0inM , the current drops to zero and the dc bus voltage falls to the nominal value V BUS . The ultra-capacitor discharge phase is finished and the drive is supplied from the mains again (MM). Fig. 12.7 illustrates the drive immunity on the mains short interruption. The drive runs in the mains motoring mode (MM), and at some instant the mains is interrupted. The dc bus voltage falls to the minimum V BUSmin , and stays at that level regulated by the dc bus voltage controller. The drive is in the ride-through mode (RT), being supplied from the ultracapacitor. The ultra-capacitor voltage decreases below U C0inM towards U Cimin . Once the mains is recovered after 1.5s, the ultra-capacitor is re-charged to U C0inM . This is the mains motoring and charging mode (MM-CH). The current total harmonic distortion factor (THD) is 29.5% and partially weighted harmonic distortion factor (PWHD) is 54%. The THD is lower than the requirement, of 48%, [13]. However, the PWHD is slightly higher than the limit of 46%, defined by the standard [13]. Fig. 12.9 illustrates the drive capability to run on single-phase supply. It could be degradation of the mains supply (one phase lost) or the application requirement (rural area without three phase supply). The waveforms of the mains voltage and current and the dc bus voltage are shown. Fig. 12.9 (a) illustrates waveforms when the proposed solution is used and Fig. 12.9 (b) illustrates waveforms when a standard diode rectifier is used. The waveforms are recorded at nominal power of 4000W. Note significant difference in the mains peak and rms current and also the dc bus voltage ripple. Note that this circuit corresponds to circuit of Fig. 12.1 (b) (the DC-DC1 converter, two series connected capacitors and the DC-DC2 converter).

The DC-DC1 converter is a switch/diode cell with a filter inductor L 0 . The inductor is connected on the rectifier plus rail, the diode D 0 is connected on the dc bus plus rail and the switch S 0 is connected to the mid-point of the capacitors C B1 and C B2 . The DC-DC2 converter is composed of the following devices: a switching leg S 1 S 2 connected in parallel with the bottom capacitor C B1 , the switching leg S 3 S 4 connected in parallel with the top capacitor C B2 and a diode leg D 1 D 2 connected in parallel with the top side capacitor C B2 . Mid-points of the legs S 1 S 2 and S 3 S 4 are connected to the ultra-capacitor via a filter inductor L C0 . A resonant circuit L S C S is connected between the S 1 S 2 mid-point and the diode D 1 D 2 mid-point.

The DC-DC2 Converter Operating Modes

As already mentioned in the previous section, the DC-DC2 converter has two roles: 1) to control power flow between the drive and the ultra-capacitor when the drive operates in braking and ultra-capacitor motoring mode. 2) To assist to DC-DC1 converter and balance the voltages v C1 and v C2 when the drive operates in the mains motoring mode. The converter circuit diagram in different operating modes is given in Fig. 12.11 and Fig. 12.12.

The Ultra-capacitor Energy Transfer Mode

In this operating mode, the rectifier current is zero, and therefore the cell D 1 D 2 and L S C S circuit (this part of DC-DC2 converter assists to the DC-DC1 converter) can be drooped from the circuit, as illustrated in Fig. 12.11 (a). Four switches denoted as S 1 -S 4 and a filter inductor L C0 , that are connected in a threelevel topology [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF] controls power flow between the ultra-capacitor C C0 and the dc bus. More precisely, the circuit is active whenever the drive operates in the braking mode (charging the ultra-capacitor) or motoring mode from the ultra-capacitor (discharging the ultra-capacitor). The switches S 1 -S 4 are controlled by two duty cycles d 1 and d 2 . Detailed analysis of the DC-DC2 converter operating in the ultra-capacitor energy transfer mode was given in chapter 8, section 8.3. Here, in this chapter, very simplified analysis that is necessary to follow the dissertation is presented. For this, it will be assumed that v C1 =v C2 and d 1 =d 2 =d. Simplified circuit diagram depicted in Fig. 12.11 (b) is considered. Resistance R C0 is the ultra-capacitor internal resistance, which is assumed as frequency independent resistance. Resistance R LC0 is the inductor parasitic resistance, which includes the wire resistance and the core equivalent resistance [START_REF] Grbovi} | A bi-directional threelevel dc-dc converter for the ultra-capacitor applications[END_REF].

The circuit in Fig. 12.11 (b) is described by equation

0 0 0 0 0 C LC C BUS C C i R u d v dt i d L - - = , ( 12.1)
where the symbol x denotes moving average value of a variable x .

From ( 12.1) and steady state condition follows duty cycle d

min max 0 0 max 0 max max max 0 0 min 0 min 0 0 0 BUS C LC C BUS C LC C BUS C LC C v i R u d v i R u d v i R u d + = - = + = .
( 12.

2)

The ultra-capacitor current and voltage are controlled by the controllers via the duty cycle d.

The Mains Motoring Mode

Let us assume that the drive operates in the mains motoring mode. As mentioned, in this mode there is no power flow between the drive and ultra-capacitor. Hence, the ultracapacitor current is zero (the ultra-capacitor stand-by). As the current is zero, the top side switches S 3 S 4 can be drooped from the circuit, as illustrated in Fig. 12.11 (a). As already discussed and mentioned in chapter 9, the circuit of Fig. 12.11 (a) is a variant of the switched capacitor converter. A leg S 1 S 2 is connected across the bottom capacitor C B1 , and a leg D 1 D 2 is connected across the top capacitor C B2 . The capacitor C S is the main switched capacitor that transfers the energy from the bottom capacitor C B1 to the top capacitor C B2 , and the inductor L S is an auxiliary inductor. The role of the inductor L S is to minimize the conduction losses and ensure the zero current switching condition (ZCS). The switches S 1 and S 2 are driven with complementary control signals at period T S2 . The duty cycle is d 1 and depends on the ultra-capacitor voltage ( 12.2), and is normally around 50%.

An equivalent circuit diagram of the DC-DC2 converter is given in Fig. 12.11 (b). The inductance L E is an equivalent inductance of the resonant circuit, given as

2 0 2 2 2         = T T L L S S E π , ( 12.3)
where

S S C L T π 2 0 =
is the resonant period.

The current sources i D and i S are approximated by i 2 /2, as it was already discussed in section 9.1. For simplicity of the analysis, one can assume that the capacitors C B1 and C B2 are large enough to maintain the voltages v C1 and v C2 constant over the switching cycle T S2 . The switches and diodes are modeled by constant voltage sources V S0 and V DF0 .

One complete cycle T S2 can be divided into four stages, namely stage A to stage D. Simplified model, topology stages and the waveforms are given in Fig. 12.13.

Stage A: Switch S 1 is closed at the instant t=0. The capacitor C S is charged from v C1 via the switch S 1 diode D 1 and the inductor L S . The current i 2R and voltage v CS increase. Once reaches the maximum, the current starts to decrease towards zero (L S C S resonant circuit). Stage D: The current i 2R reaches zero and diode D 2 is blocked at the instant t=dT S2 +T 0 /2. The current remains zero until the commutation of the switch S 1 at the instant t=T S2 . One switching cycle is finished.

Zero Current Switching Conditions and L S C S Design

To achieve the ZCS, the resonant current i R2 must fall to zero before next commutation of the S 1 S 2 switch cell. Otherwise, the switch cell commutates at non-zero current conditions. As a consequence, the switching losses of the S 1 S 2 and D 1 D 2 will be quiet high. To satisfy the ZCS condition, the resonant frequency must be

( ) ( ) 2 max min 0 2 1 , min 1 1 S S S T d d C L π ω - ≥ = , ( 12.4)
where the maximum and minimum duty cycle have been defined in ( 12.2) as a function of the dc bus voltage and the ultra-capacitor voltage.

From the ZCS condition follows that ( ) ( )

2 2 max min 2 1 , min       - ≤ π S S S T d d C L . ( 12.5)
The capacitor and inductor can be selected using same optimization method that was discussed in chapter 9, section 9.3.2.2. Fig. 12.14 (a) shows experimental waveforms of the rectifier voltage v REC , resonant current i 2R and the rectifier current i REC . Magnitude of the current directly follows the rectifier current magnitude and inversely follows magnitude of the rectifier voltage. More precisely it follows the difference between the dc bus voltage and rectifier voltage. This was discussed and explained in chapter 8. Fig. 12.14 (b) shows zoom of those waveforms and waveform of voltage v S1 (the bottom switch S 1 voltage in Fig. 12.13). In the current waveform, note an anomaly that is denoted in the pink. Once the current reaches zero, it is expected that the current remains zero until the next switching sequence. However, the current has another peak, with lower magnitude and slightly lower frequency. In this particular case, the commutation is still soft commutation; the current falls to zero before next commutation. However, this is only a coincidence. If duty cycle is different (in this case lower) the commutation will not be soft. The switch will commute at non-zero current conditions.

To investigate the root-cause of this anomaly, let us refer on the real circuit diagram, which is shown in Fig. 12.15 (a). In the real set-up circuit, the main dc bus capacitor C BUS is dislocated from the dc-dc converter board and capacitors C B1 , C B2. This is indicated by the parasitic inductance L γ in the circuit diagram in Fig. 12.15 (a). Thus, an additional parasitic resonant circuit is created by the parasitic inductance L γ and the capacitors C B1 , C B2 . The parasitic resonant circuit is excited each time the switches S 1 S 2 commutate. The voltages v C1 and v C2 therefore oscillates around the average value. This is visible in the waveforms in Fig. 12.15 (b). Once the voltage becomes greater than the voltage of the resonant capacitor C S , the diode D 1 starts to re-conduct and charge the capacitor C S . Fig. 12.16 shows the waveforms after some modifications on the real circuit have been done. The first modification: An additional small inductance is connected between the dc bus capacitor and the converter board. Waveforms are shown in Fig. 12.16 (a). Note that the voltage ripple is greater than that in case without the additional inductance. The re-conduction time is longer and therefore the commutation is hard.

The second modification: An additional inductor of 50µH is connected between the dc bus capacitor and the converter board. Fig. 12.16 (b) shows the waveforms. The voltage ripple is smaller than that of the first case. The voltage waveform is regular triangular waveform. The resonant current is regular, no re-conduction of the diode D 1 . The switches commutate at the zero current condition.

The third modification: An additional dc bus capacitor is connected close to the converter board. In this case the parasitic inductance is significantly reduced. Fig. 12.17 shows the waveforms. The voltage ripple is smaller than before. The resonant current is regular, without re-conduction. The switches commutate at the zero current condition.

MODELING AND CONTROL SCHEME

The modelling and control scheme are discussed in this chapter. The large and small signal model of the entire conversion system (the ultra-capacitor, the dc-dc converter and drive converter) is developed. Some of the model derivations are re-used from chapter 5 and chapter 9. In the second part of this chapter, the control objective and control scheme are discussed. The model and control scheme are validated by Matlab/Simulink simulation and a set of experimental measurements. The results are presented and discussed.

The System Model

Large Signal Model

The large signal (nonlinear) model of the entire power conversion system is depicted in Fig. 13.1. The input rectifier is modeled by a voltage source v REC . The dc bus capacitor is modeled as an ideal capacitor C BUS and its equivalent series resistance R ESR . where the rectifier and the ultra-capacitor instantaneous power is

43 42 1 0 0 ≅ - = dt di L i i v p REC REC REC REC REC , ( 13
.2)

4 3 42 1 0 0 0 0 0 0 0 ≅ + = dt di L i i u p C C C C C C . ( 13.3)
Instantaneous power of the filter inductor L C0 and the boost inductor L 0 are neglected in ( 12.2) and ( 12.3).

The ultra-capacitor circuit is described by the following equations ( )

0 0 2 C C C C i dt du u k C = + , ( 13.4) 0 0 0 C C C C i R u u + = , ( 13.5)
        - - + = BUS LOAD BUS C BUS REC ESR B BUS v p v p v p R v v 0 .
( 13.6)

Small Signal Model

Appling the small signal approximation and Laplace transformation on ( 13.2)-( 13.6) yields transfer functions in matrix form

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 4 3 42 1 4 3 42 1 E DISTURBANC REC LOAD vREC P CONTROL REC C BUS BUS C BUS C s v s p s G s G s i s i s G s G s G s v s u             +             =       0 0 0 0 0 0 . ( 13.7)
The system output variables are u C0 and v BUS , the control variables are i C0 and i REC , and the disturbance variables are p LAOD and v REC . The transfer functions are ( )( )

BUS BUS C C C ESR BUS s v s p s i C BUS C BUS V sC R I U R sC s i s v G REC LOAD REC 0 0 0 0 ) ( 0 ) ( 0 ) ( 0 ) 0 ( 1 ) ( ) ( + + - = = = = = , ( ) BUS BUS ESR BUS REC s v s p s i REC BUS REC BUS V sC R sC V s i s v G REC LOAD C + = = = = = 1 ) ( ) ( 0 ) ( 0 ) ( 0 ) ( ) ( 0 , ( ) ( ) ( ) ( ) ( ) ( ) P Z C C C C C C C C C C C C C C C s v s p s i C C C s s R R I U k C kI s R I U k C R R I U k R kI C s R s i s u s G REC LOAD REC ω ω + + = - + + - + + + - + = = = = = 0 2 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ( 0 ) ( 0 ) ( 0 0 0 2 2 2 2 2 ) ( ) ( , ( 13.8) ( ) ( ) BUS BUS ESR BUS s v s i s i LOAD BUS P V sC R sC s p s v s G REC REC C + - = = = = = 1 ) ( ) ( 0 ) ( 0 ) ( 0 ) ( 0 , ( ) BUS B ESR BUS REC s p s i s i REC BUS vREC V sC R sC I s v s v s G LOAD REC C + = = = = = 1 ) ( ) ( ) ( 0 ) ( 0 ) ( 0 ) ( 0 .
( 13.9) Remark: When the transfer function G BUS(C0) was being developed, it was assumed that the ultra-capacitor is an infinite capacitance. Fig. 13.2 shows block diagram of the small signal model of the system ( 13.1)-( 13.6) Fig. 13.5 shows the small signal model and control scheme of the system working in the rectifier mode. As the dc bus voltage controllers are saturated, the ultra-capacitor voltage (small signal) reference is zero.

The Ultra-capacitor Energy Transfer Mode

In the ultra-capacitor energy transfer mode, two sub-modes can be distinguished: a) the braking mode, and b) ride-through mode. Fig. 13.6 and Fig. 13.7 depict the control scheme and small signal control block diagram.

o Braking Mode

The drive load is negative (the motor works as a generator). Because the rectifier is a uni-directional device, the dc bus capacitor is charged and the dc bus voltage v BUS increases. As the dc bus voltage increases, the dc bus voltage error decreases. Thus, the boost voltage controller trays to regulate the dc bus voltage and reduce the rectifier current reference towards zero. Once the reference reaches zero, the boost voltage controller is saturated, and can be neglected in the analysis.

Once the dc bus voltage reaches the reference V BUSmax , the dc bus voltage controller G vBUSmax is out of saturation, while the controller G vBUSmin stays saturated at zero. Thus, the ultra-capacitor voltage reference u C0(REF) starts to increase from

U C0inM towards U C0max , max 0 ) ( 0 0 C REF C inM C U u U ↑≤ < . ( 13.11)
The ultra-capacitor current is set by the controller G uC0 at such a level to maintain the dc bus voltage constant v BUS =V BUSmax . If the braking energy is greater than the ultra-capacitor capability, the ultra-capacitor will be fully charged to the maximum voltage U C0max before the end of the braking phase. The dc bus voltage controller G vBUSmax will be saturated at U C0max , and the ultra-capacitor voltage reference will stop increasing. The ultra-capacitor voltage will stay constant and the current i C0 will fall to zero; charging of the ultra-capacitor is finished. Then, the dc bus voltage will start increasing until activation of the braking resistor or the drive over-voltage (over-braking fault) protection.

When the drive operates in motoring mode, the ultra-capacitor has to be discharged to the intermediate value U C0inM in order keep the ultra-capacitor ready for next braking cycle. The dc bus voltage controller G vBUSmax regulates the dc bus voltage to V BUSmax . Output of the controller G vBUSmax decreases and therefore the ultra-capacitor voltage reference decreases towards U C0inM . The ultra-capacitor is discharged, supplying the drive load. Once the ultra-capacitor is discharged to the intermediate level U C0inM , the dc bus voltage controller G vBUSmax is saturated at the reference U C0inM . The ultra-capacitor voltage reference is therefore constant

inM C inM C REF C U U u 0 0 ) ( 0 0 = + = .
( 13.13)

The ultra-capacitor voltage is regulated to the intermediate reference, u C0 =U C0inM . Therefore, the ultra-capacitor current falls to zero and discharging is finished. The dc bus capacitor is discharged and the dc bus voltage decreases. Once it reaches the reference V BUS(REF) , the boost voltage controller G vBUS goes out of saturation and the DC-DC1 converter starts to regulate the dc bus voltage. The drive is supplied again from the mains.

o The Ride-Through Mode When the mains is interrupted, the dc bus voltage starts to decrease until it reaches the minimum V BUSmin . At that instance, the controller G vBUSmin goes out of saturation and the output u 1(REF) starts to decrease below zero towards ∆U C0min =U C0min -U C0inM . Since the controller G vBUSmax stays saturated at U C0inM , the ultra-capacitor voltage reference starts to decrease below U C0inM towards U C0min .

( )

inM C REF C C inM C C inM C U u U U U U 0 ) ( 0 min 0 0 min 0 0 ↓> ≥ = - + , ( 13.14)
The ultra-capacitor is discharged deeper while the dc bus voltage is regulated to the minimum level v BUS =V BUSmin . Once the mains is recovered, the dc bus voltage starts to increase to the nominal voltage (defined by the mains voltage). At same time, the ultracapacitor is charged and its voltage increases towards U C0inM in order to be ready for next interruption.

If the power interruption is longer than the specified, the ultra-capacitor will be discharged to the lower minimum level U C0min . Then, the ultra-capacitor current will fall to zero and the dc bus voltage will start decreasing until reaches the under supply fault (USF) level. The drive will fail in the USF and the complete system will be stopped.

o The Mains Peak Power Smoothing Mode

When the drive operates in the mains peak power filtering mode, the DC-DC1 and DC-DC2 control blocks are active. The dc bus boost voltage controller is active continuously, while the dc bus voltage min/max controllers operate complementary. Equivalent control block diagram that illustrates this operating mode is depicted in Fig. 13.8.

Simulation and Experiments

The model and control algorithm proposed in this chapter were simulated by the average model ( 13.1)-( 13.6) implemented in Matlab/Simulink and verified by a set of experiments. Some of the simulation and experimental results are presented and discussed hereafter. All relevant parameters of the system and control are summarized in TABLE 13-1. The control algorithm, PWM and protection functions were implemented in a fixedpoint 32 bit digital signal processor (DSP). The complete control algorithm is executed at

ULTRA-CAPACITOR SIDE DC BUS SIDE U C0max 780 V V BUSmax 675 V U C0inM 350 V V BUS 650V U C0min 250 V V BUSmin 625 V ∆u C0 3 V C BUS 820 µF i C0max 15 A R ESR 200 mΩ C C0 0.3 F f BUS 50Hz ( ) s s s G vBUS 32 145 . 0 min + - = k C 0.000143 F/V G vBUS(max) ( ) 1 max 1 0065 . 0 145 . 0 - - - - = z z G vBUS ( ) s s s G vBUS 45 2 . 0 min + - = R C0 2 Ω G vBUS(min) ( ) 1 min 1 009 . 0 2 . 0 - - - - = z z G vBUS k PC0 5 f BOOST 50Hz & 1Hz ( ) 1 1 . 0 1 + = s s G F ( ) ( )       + + = s s s s s G boost vBUS
three different rates: the rectifier current control at 100 kHz, the ultra-capacitor current control at 25 kHz and the dc bus voltage control at 5 kHz. The controllers were designed as the standard proportional-integral (PI) controllers. The controller parameters were computed in continuous time domain (s), and then translated into discrete time domain, (z), using the approximation

S T z s 1 1 - - =
, where is the sampling period is

Simulation Results

Fig. 13.9 shows waveforms simulated during an entire operating cycle: the mains motoring (MM), braking (B), the ultra-capacitor motoring (MC 0 ) and the mains motoring mode (MM). Fig. 13.10 shows the dc bus voltage and the mains current waveforms during transition from the mains motoring mode to braking mode. Fig. 13.10 shows the dc bus voltage and the mains current during transition from the mains motoring mode to the braking mode. Once the dc bus load becomes negative, the dc bus voltage starts to rise from the reference V BUS(REF) =650V towards the reference V BUSmax =655V, while the mains current drops to zero. The dc bus voltage overshoot is small, approximately 15V, which is 2.3% of the nominal voltage. Fig. 13.11 shows the dc bus voltage and the mains current waveform during transition from the ultra-capacitor motoring mode to the mains motoring mode. The dc bus voltage falls from the reference V BUSmax =655V towards the reference V BUS(REF) =650V, while the mains current rises slowly. Note, the dc bus voltage undershoot is small, around 1V that is 0.15% of the nominal voltage.

The Mains Peak Power Smoothing

Fig. 13.12 and Fig. 13.13 illustrate the drive system behaviour in presence of a discontinuous load. The dc bus load is cycling between 10% and 100% with repetition period of 1s and duty cycle of 35%. Waveforms of the dc bus voltage and the mains current when the mains peak power filter mode is not active (the voltage controller bandwidth is f BOOST =50Hz) are shown in Fig. 13.12. The dc bus is regulated to the reference V BUS(REF) =650V. Magnitude of the mains current is modulated by the dc bus load, and varies from approximately 1A (at light load) to 9.5A (at full load). Fig. 13.13 shows waveforms of the ultra-capacitor current and voltage. The current is zero with narrow positive and negative spikes. The spikes are caused by the dc bus min/max voltage controller because difference between the dc bus voltage references is narrow, in this case V BUSmax -V BUSmin =10V. The system behavior is simulated when the mains peak power filter mode is active (the voltage controller bandwidth is f BOOST =1Hz). Fig. 13.14 shows the dc bus voltage and the mains current waveforms. The dc bus voltage regularly commutates between V BUSmin =645V and V BUSmax =655V. The mains current is slightly modulated, but with much lower variation in comparison the previous case. Fig. 13.15 shows the ultra-capacitor voltage and current waveforms. The current commutates between -9A (full load on the dc bus side) and 5A (light load on the dc bus side). Discontinuity is the ultra-capacitor voltage is in the voltage drop on the ultra-capacitor internal resistance R C0 . The dc bus load step from 10% to 110%, and b) from 110% to 10%. V BUS =650V, V MAINS =400Vrms, L 0 =325µH, C BUS =820µF and f BOOST =50Hz.

The DC Bus Voltage Controller G BUSmax Performance

Fig. 13.17 illustrates the functionality of the dc bus voltage braking controller, G VBUSmax . The ultra-capacitor is charged on 550V. Fig. 13.17 (a) shows the ultra-capacitor voltage and current, ac component of the dc bus voltage and rectifier current when the drive switches from stand-by mode to the ultra-capacitor mode. The controller response time is approximately 5 ms, while the voltage undershoot is approximately -13V. Fig. 13.17 (b) shows the waveforms when the drive switches from the ultra-capacitor mode to the stand-by mode. The voltage overshoot is approximately 12V. The controller response time is similar to the previous one.

The Mains Peak Power Smoothing Controller Performance

The capability of the drive system to reduce the mains peak power is tested and results are illustrated in Fig. 13.18 . The waveforms of the ultra-capacitor voltage u C0 and current i C0 , the dc bus voltage v BUS and the mains current i MAINS are shown. The dc bus load is cycling between 10% and 100% with repetition period of 2.2s and duty cycle of 40%. Fig. 13.18 (a) illustrates a case when the peak power filtering function is deactivated (the dc bus voltage boost controller bandwidth is 50Hz). As one can see from the waveform, the dc bus voltage is well regulated at the reference V BUS(REF) =650V. The ultra-capacitor current is zero. The mains current is modulated with the load and it varies from 1A up to 11A. Fig. 13.18 (b) illustrates a case when the peak power filtering function is activated (the dc bus voltage boost controller bandwidth is 1Hz). The dc bus voltage is well regulated at two different references V BUSmax =675V and V BUSmin =625V. The ultra-capacitor current commutates between -8A (the dc bus load is 100%) and 6A (the dc bus load is 10%). The mains current magnitude is approximately 6A, continuous without significant variations.

CONCLUSION

In this part of the dissertation, a new solution for the ultra-capacitor based regenerative electric drive has been proposed. The proposed solution intents to successfully solve some the technical issues that still exist in the application of controlled electric drives: 1) Saving of the braking energy, 2) extension of the drive system ride-through capability (immunity on the mains interruption), 3) the drive input current quality, 4) the drive dc bus voltage control, 5) single phase operation and 6) smoothing of the mains peak power.

The proposed solution has been theoretically analysed. The analyses results are confirmed by the Matlab/Simulink simulation and a set of experiments on an industrial prototype. The conversion efficiency has been computed and is between 97% and 99%. Please, note that the ultra-capacitor efficiency is excluded from this calculation. As it was discussed in chapter 3, the ultra-capacitor efficiency strongly depends on the capacitor size and conversion power, the smaller capacitor the lower efficiency. Therefore, efficiency of the entire drive system depends on the ultra-capacitor size.

In comparison to state of the art solutions, such as regenerative rectifiers or matrix converters, the proposed solution has the following advantages:

1) The system ride-through capability is extended. The drive autonomy time is a design parameter. Depending on the application, the ride-through time could be extended up to 15s. Above this, it is not cost effective to use the ultra-capacitors. Instead, electrochemical battery can be better solution. This limit will move up with development of the new generation of ultra-capacitors [START_REF] Burke | Ultracapacitors: Present and Future[END_REF].

2) The system functionality, including braking capability is not linked to the mains reliability.

3) Operation of the drive system in single-phase supply mode is possible.

4) The mains peak power is controlled and the drive effects on the mains are reduced. This is particularly important in case of a weak supply network. Also, smoothing of the input power allows better sizing of the drive installation (smaller cabling cabinet, fuses and contactors).

A disadvantage of the proposed solution is the input current total harmonic distortion (THD) that cannot be lower than 30%. However, according to the existing standards [13], THD of 30% is sufficient for general purpose industrial drive applications.

THE DISSERTATION CONTRIBUTION

Contribution of the dissertation could be summarized as follows:

o The Ultra-capacitor Application in Power Conversion A comprehensive analysis of the ultra-capacitor as an energy storage device for power conversion applications has been performed. The ultra-capacitor macro model has been discussed. The conversion losses model, which takes into account frequency of the capacitor current and the frequency dependent resistance of the capacitor, has also been developed.

o Parallel Connected Energy Storage Device for Controlled Electric Drives

Regenerative controlled electric drive with braking capability and extended ridethrough capability, using parallel connected ultra-capacitor as an energy storage device has been extensively analysed. Such a drive concept allows saving and recovery of the drive braking energy in most of controlled electric drive applications. Moreover, the drive ridethrough capability can be extended, depending on an application need.

o Interface DC-DC Converter Three-level dc-dc converter as interface between the ultra-capacitor and the controlled electric drive has been proposed and discussed. The advantages of the three-level dc-dc converter have been clearly identified and discussed.

o The System Model and Control Scheme Dynamic nonlinear and small signal linear model of the controlled electric drive with the ultra-capacitor and dc-dc converter has been developed. The model takes into account all the relevant effects that are present in such a complex power conversion system. A novel control scheme has been also proposed. The control scheme allows control of the ultracapacitor current, the ultra-capacitor state of the charge (SOC) and the dc bus voltage. The advantages of the proposed control scheme have been identified and discussed.

o Three-terminal Power Factor Correction Device

The mains current quality, dc bus voltage control and operation on single-phase supply have been discussed. A novel boost dc-dc converter based on the half-dc-bus-voltage rated topology has been proposed as a solution for the above-mentioned issues. The new topology has been theoretically analysed and the concept verified by a set of experiments. Modelling aspects and control scheme have been discussed. Particular attention has been paid on the model of the resonant dc-dc converter that is used to balance the dc bus mid-point voltage. The advantages of the new topology have been clearly identified and discussed. The ultra-capacitor as an energy storage device dedicated for power conversion has been discussed in the first part of the dissertation. In comparison to state of the art electrochemical batteries, ultra-capacitors have higher power density, higher efficiency, longer life time and greater cycling capability. In comparison to state of the art electrolytic capacitors, ultra-capacitors have higher energy density. All those advantages make ultracapacitors the most suitable candidate for power conversion applications with a need for short-term energy storage, up to 15s. Some of the possible applications are industrial controlled electric drives, hoisting applications, power transmission/distribution networks, traction drives and UPS in building and IT centres.

State of the art ultra-capacitor technology is the double layer capacitor with activated carbon electrodes. Beside this technology, there are four different technologies under development: 1) Nano tube capacitor, 2) Nano-gate capacitor, 3) EeStore high voltage multilayer capacitor and 4) Mega-farad ultra-capacitor. All the technologies under development promise higher energy density than state of the art ultra-capacitors. Some of them, for example technology 3) and 4), promise energy density even greater than state of the art electrochemical batteries.

The ultra-capacitor macro model has been discussed. Proper electrical model is essential for the ultra-capacitor losses and temperature evaluation and the conversion system control analysis and synthesis. The first order RC model is sufficiently accurate if dominant frequency of the ultra-capacitor current is well below or above the capacitor cut-off frequency. Otherwise, the second or higher order model is necessary to accurately compute the capacitor losses and internal temperature. For the most commercially available ultracapacitors, lower cut-off frequency is around 0.1Hz, while the upper cut-off frequency is around 10Hz. The first order RC model is sufficient for analysis and synthesis of the power converter controllers.

The concept of the ultra-capacitor based regenerative electric drive has been discussed in part two of the dissertation. The ultra-capacitor is employed as the energy storage device to store the drive braking energy and restore the energy whenever it is possible. Moreover, the ultra-capacitor is used as an emergency power supply in case of the mains interruption. Unlike electrochemical batteries, the ultra-capacitor state of charge (SOC) strongly depends on the terminal voltage. Thus, it is not practical and convenient to connect the ultra-capacitor directly to the controlled electric drive. An interface dc-dc converter is necessary. State of the art topologies are discussed and the new three-level dc-dc converter topology is proposed. The proposed topology is analysed and design guidelines are given. Model of the entire conversion system is developed and new control scheme is proposed. Objective of the proposed control is to control the ultra-capacitor current and the dc bus mid-point voltage. The second control objective is to asymptotically regulate the dc bus voltage at desired reference, depending on the operating mode. The ultra-capacitor state of charge (SOC) control is the third control objective.

In comparison to state of the art solutions, such as back-to-back and matrix converters, the proposed ultra-capacitor based controlled electric drive converter shows the following advantages.

o The system ride-through capability is extended. The drive autonomy is a design parameter. Depending on the application, the ride-through time can be extended up to 15s. Above this, it is not cost effective to use the ultracapacitors. Electrochemical batteries are more suitable solution. This limit will move up with development of the new generation of ultra-capacitors.

o The system functionality, including braking capability and reliability is not linked to the mains reliability.

Regarding to the three-level interface dc-dc converter, the following advantages compare to state of the art topologies are identified.

o The semiconductors losses are smaller than that of the two-level topology and isolated topologies.

o The output inductor is smaller than that of the ordinary two-level topology.

The inductor size depends on the ultra-capacitor minimum voltage, and varies between 25% and 50% of that of the two-level converter.

o The input filter capacitor is smaller too. The capacitor volume varies between 10% and 25% of that of the two-level converter.

Novel Diode Boost Rectifier

The novel three-phase diode boost rectifier using the half-dc-bus-voltage-rated topology has been proposed and discussed in part three of the dissertation. The proposed boost converter consists of two dc-dc converters and two series connected dc bus capacitors. The first converter regulates the rectifier current and boosts the dc bus voltage above the mains phase-to-phase peak voltage. This converter is state of the art dc-dc converter, which is connected on the rectifier plus rail, the dc bus plus rail and the dc bus capacitors mid-point. The second dc-dc converter is an auxiliary converter that assists to the first one. This converter is a variant of the series resonant converter that operates in discontinuous conduction mode, type 1. Nonlinear model and small signal model of the entire rectifier have been discussed. Particular attention has been paid on the auxiliary resonant dc-dc converter model. Control scheme has been proposed and validated by simulation and a set of experiments.

The advantages of the proposed boost rectifier compared to the ordinary single-switch and double-boost rectifier can be summarized as follows.

o The switches utilization factor is higher than that of state of the art solutions.

Therefore, the switches cost is lower.

o The switches voltage rating is half of that of the single-switch boost rectifier. Thus, better and more efficient devices could be used.

o The boost inductor is smaller than the inductor of single-switch boost rectifier.

o The conversion efficiency is greater than that of state of the art solutions. o The need for an auxiliary dc-dc converter to control the dc bus capacitors midpoint voltage. This converter is rated on a fraction of the total conversion power. Therefore the conversion losses can be quite low in comparison to the total conversion losses.

o The input current total harmonic distortion factor (THD) and partially weighted harmonic distortion factor (PWHD). Because of operation principle of threephase diode boost rectifier operating in continuous conduction mode (CCM), the THD cannot be reduced below 30%, while the PWHD is around 55%. However, according to the existing standards [13], THD of 30% is sufficiently low for industrial drive applications, while PWHD is slightly above the limit.

The PWHD, however, can be reduced below 46% as required by the standard by the use of 6 th harmonic injection [START_REF]Apparatus and Method for Mains Harmonic Reduction in AC Drive Circuits[END_REF].

The new boost rectifier is an effective replacement for passive diode rectifiers as well as single-switch and double boost rectifier. This topology could be used in three-phase supplied and single -phase supplied three-phase controlled electric drives.

All Together

In last part of the dissertation, a compilation of the parallel-connected energy storage device (discussed in part two of the dissertation) and the new boost rectifier (discussed in part three of the dissertation) is proposed. The proposed solution intents to successfully solve the following technical issues that still exist in application of controlled electric drives: 1) Saving of the braking energy, 2) extension of the drive system ride-through capability (immunity on the mains interruption), 3) the drive input current quality, 4) the drive dc bus voltage control, 5) single phase operation and 6) smoothing of the mains peak power. The proposed solution is theoretically analysed and design guidelines are given. The concept has been validated by simulation and a set of experiments.

Compared to state of the art solutions, such as regenerative back to back and matrix converters, the proposed solution has the following advantages.

o The system ride-through capability is extended.

o The system functionality, including braking capability is not linked to the mains reliability.

o Single-phase supply operation is possible too.

o The mains peak power is controlled and the drive effects on the mains are reduced. This is particularly important if the electric drive is supplied from a weak public supply network. Moreover, smoothing of the input power allows better sizing of the drive installation (smaller cabling cabinet, fuses and contactors).

o The conversion efficiency is greater that that of state of the art solutions.

Perspectives for Future Work

Perspectives for future work on the project can be summarized as follows.

Commissioning and Self-tuning of the System Controllers

The first objective for future work on this project would be the system commissioning and self-tuning process. Two parameters have to be well known for proper tuning of the system controllers: 1) Capacitance of the dc bus capacitor, and 2) capacitance of the ultracapacitor. The first one is important for the dc bus voltage controllers' adjusment, while the second one is important for the ultra-capacitor state of charge (SOC) controller adjustment.

On-line Monitoring and the Ultra-capacitor Life Time Estimation

The ultra-capacitor lifetime prediction is another aspect to be considered. In certain applications, such as critical industrial processes [10], unexpected interruptions of the system are not allowed. Hence, failures such as end of life of the ultra-capacitor must be predicted and preventive replacement done on time. For this, on-line lifetime estimation is essential. Some work has been already done in field of electrolytic capacitors failure prediction [START_REF] Ma | Fault diagnosis and failure prediction of aluminum electrolytic capacitors in power electronic converters[END_REF]. Similar concept can be used to predict end of life of the ultra-capacitor. • La fonctionnalité système du variateur de vitesse, incluant sa capacité de freinage, n'est pas reliée à la fiabilité de l'alimentation

• Le fonctionnement en marche dégradée lors de la perte d'une phase réseau est simple à gérer et amène à de très bonnes performances.

• Les pics de puissance sont limités, et conduisent à une réduction des contraintes électriques au niveau réseau.

• La consommation électrique du système est fortement réduite grâce au stockage et au développement d'une solution électronique à haut rendement.

Dispositif correcteur de facteur de puissance à base de super-condensateur pour variateur de vitesse

Les variateurs de vitesse modernes sont exclusivement basés sur l'utilisation de moteurs triphasés alimentés par des onduleurs à modulation de largeur d'impulsion (MLI). La plupart des applications modernes de la variation de vitesse, comme les ascenseurs, les grues et les machines-outils sont caractérisées principalement par un rapport élevé entre la puissance crête et la puissance moyenne et une forte demande de freinage à la puissance nominale. Dans les variateurs de vitesse ordinaires, l'énergie de freinage, qui est de l'ordre de 30 à 50% de l'énergie consommée, est dissipé dans une résistance. Outre les problèmes « énergétiques », les interruptions et dégradations de la tension d'alimentation ainsi que la qualité du courant d'entrée et la fluctuation de la charge, sont d'autres questions à aborder et à résoudre.

Le super-condensateur dédié aux applications de conversion de puissance est ainsi proposé. Un variateur de vitesse équipé avec des super-condensateurs est présenté dans la thèse. Les super-condensateurs, interconnectés par un convertisseur DC-DC sont utilisés pour stocker et ré-injecter l'énergie de freinage. De plus, le convertisseur DC-DC contrôle le courant du redresseur et la tension du bus DC. Le THD du courant d'entrée est ramené à 30%. La tension du bus DC est élevée et en permanence contrôlée et lissée indépendamment de la charge et de la variation de la tension réseau. Pour terminer, les pics de puissance peuvent être lissés. La solution présentée est analysée théoriquement et vérifiée par un ensemble de simulations et expérimentations. Les résultats sont présentés et commentés.

Ultra-capacitor based regenerative energy storage and power factor correction device for controlled electric drives

Modern controlled electric drives are exclusively based on three-phase motors that are fed from threephase pulse width modulated (PWM) inverters. Most of modern controlled electric drive applications, such as lifts, cranes and tooling machines are characterized by high ratio of the peak to average power, and high demand for braking at the rated power. In ordinary drives, the braking energy, which represents 30-50% of the consumed energy, is dissipated on a braking resistor. Apart from the "energetic" issue, the mains interruption and degradation, the input current quality and the load fluctuation are additional issues to be addressed and solved.

The ultra-capacitor dedicated for power conversion applications has been discussed. In comparison to electrochemical batteries, the ultra-capacitors have higher power density and efficiency, longer life time and greater cycling capability. This makes the ultra-capacitor an excellent candidate for power conversion applications.

A new electric drive converter equipped with the ultra-capacitor is presented in the dissertation. The ultra-capacitor with an inter-connection dc-dc converter is used to store and recover the drive braking energy. Moreover, the dc-dc converter controls the rectifier current and the dc bus voltage. The drive input current THD is reduced to 30%. The dc bus voltage is boosted and controlled constant and ripple free regardless on the load and the mains voltage variation. Moreover, the drive input peak power can be smoothed. The presented solution is theoretically analysed and verified by set of simulations and experiments. The results are presented and discussed.

Fig. 1 . 1 1 . 1 . 3 . 1 . 1 . 3 . 1 .

 111131131 Fig. 1.1 State of the art low voltage drive converter based on voltage source indirect AC-DC-AC conversion. The output voltage is pulse width modulated (PWM) having fundamental voltage that is adjustable in amplitude, frequency and phase.

Fig. 1 .

 1 Fig. 1.2 a) Rubber tyred gantry crane. b) Typical power profile of a hoisting application: lifting the load and acceleration (1), lifting the load at constant speed (2), lowering the load at constant speed (3) and lowering the load and deceleration (4).

Fig. 1 . 3

 13 Fig. 1.3 Typical power profile of a controlled electric drive applied in a machine with cycling load: acceleration (1), constant speed (2), and deceleration (3).

Fig. 1 . 4

 14 Fig. 1.4 Waveforms of the mains current, voltage and the dc bus voltage. a) Three-phase supply, P LOAD =5500W, the current scale [10A/div]. b) Single phase supply, P LOAD =4000W, the current scale [20A/div].

Fig. 1 . 5

 15 Fig. 1.5 Waveforms of the mains current i MAINS [20A/div] and the dc bus voltage v BUS [100V/div]. The drive load is cycling between 500W and 5500W at period of 2.2s with duty cycle of 30%. The average power is approximately 31% of the peak power.

Fig. 1 .

 1 Fig. 1.6 a) Voltage source back to back regenerative controlled electric drive. b) Voltage source matrix drive converter.

Fig. 1 . 7

 17 Fig. 1.7 Controlled electric drive based on an ordinary drive converter with parallel connected energy storage and emergency power supply device.

Fig. 2 . 1

 21 Fig. 2.1 Taxonomy of the ultra-capacitors.

Fig. 2 . 2

 22 Fig. 2.2 Construction of an electrochemical double layer capacitor with porous electrodes (activated carbon).

Fig. 2 .

 2 Fig. 2.3 a) Helmholtz's model of a DLEC (1857). b) Gouy and Chapman's model (1910 and 1913). C) Stern's model (1924).

Fig. 2 . 4

 24 Fig. 2.4 An approximated model of the electrochemical double layer capacitor taking in the account porosity of the electrodes.

6 )

 6 The coefficients K CN1 ….K CP..N models the voltage dependency of the capacitance due to the diffused layer. Voltages u CN1 ….u CP..N are the voltage across each elementary capacitor cell.

Fig. 2 .

 2 Fig. 2.5 N th order equivalent model of an electrochemical double layer capacitor.

Fig. 2 . 6

 26 Fig. 2.6 The ultra-capacitor input impedance versus frequency. a) Amplitude, b) phase, c) the equivalent series resistance and d) the capacitance. The ultra-capacitor is 2500F/2.5V cell.

Fig. 2 . 7

 27 Fig. 2.7 Illustration of the effect of the ultra-capacitor frequency dependent capacitance on energy storage capability. a) Effective specific energy versus charging/discharging pulse width, and b) time diagrams for two different cases, short pulse and long pulse.

Fig. 2 . 8

 28 Fig. 2.8 Simple RC model of the ultra-capacitor.

Fig. 2 . 9

 29 Fig. 2.9 The ultra-capacitor resistive power conversion. a) Charging, and b) discharging.

Fig. 2 .

 2 Fig. 2.10 Charging/discharging the ultra-capacitor with a constant current source.

. 43 )

 43 Using orthogonal property of the sin and cos functions,

Fig. 2 .Fig. 2 .

 22 Fig. 2.12 Variable speed drive with the ultra-capacitor as energy storage device used to filter the drive input peak power. a) Experimental waveform of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div]. b) The current amplitude spectra.

  Fig. 2.14 (b) shows the current amplitude spectrum computed within a window T=50s.

Fig. 2 .

 2 Fig. 2.14 Variable speed drive with emergency supply based on the ultra-capacitor as an energy storage device. a) Experimental waveform of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div]. b) The current amplitude spectra.

Fig. 3 . 1

 31 Fig. 3.1 Concept of regenerative controlled electric drive based on an auxiliary energy storage device and an interface dc-dc converter.

Fig. 3 . 2

 32 Fig. 3.2 The power flow for different operating modes a) the mains motoring mode (MM), b) braking mode (B).

Fig. 3 . 3

 33 Fig. 3.3 The power flow for different operating modes: a) energy recovery mode (MC 0 ) and ride-through mode (RT), b) the ultra-capacitor charging mode (MM-CH).

Fig. 3 . 4

 34 Fig. 3.4 The waveforms for different operating modes: the mains motoring mode (MM), braking mode (B), stand-by mode (STB), energy recovery mode (MC 0 ), ride-through mode (RT), the ultracapacitor charging mode (MM-CH) and the mains peak power filtering mode (MPFM).

Fig. 3 . 5

 35 Fig. 3.5 Definition of the reference voltages, (a) V BUSmax , V BUSmin , and, b) U C0min , U C0inM and U C0max .

Fig. 3 . 6

 36 Fig. 3.6 Experimental set-up. An ultra-capacitor is connected to a general purpose variable speed drive ATV71 5.5kw via the dc-dc converter.

Fig. 3 . 7 Fig. 3 . 8

 3738 Fig. 3.7 Experimental waveforms of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div], the dc bus voltage v BUS [100V/div] and the mains current i MAINS [50A/div] during an entire braking-motoring cycle. a) The ultra-capacitor is properly sized, and b) the ultra-capacitor is under-sized.

Fig. 3 . 9

 39 Fig. 3.9 First order RC model of the ultra-capacitor.

Fig. 3 .

 3 Fig. 3.10 The ultra-capacitor intermediate voltage u C0inM versus relative braking energy (determined as ration between the braking energy E B and ride-through energy E RT ) and relative minimum ultracapacitor voltage (determined as ratio of minimum to maximum ultra-capacitor voltage).

. 16 )Fig. 3 .

 163 Fig. 3.11 shows an example. The ultra-capacitor series resistance R C0 versus the capacitance C 0 is plotted for an 800V ultra-capacitor module. The module is composed of series/parallel connected ultra-capacitor cells rated on 2.8V [91].

Fig. 3 .

 3 Fig. 3.11 The ultra-capacitor resistance R C0 versus the capacitance C 0 . The red squares are value from datasheet and blue line is interpolation. The module is arranged as series/parallel connection of 2.8V rated ultra-capacitor cells. The module rated voltage is U C0max =800V. Substituting ( 3.16) in ( 3.15) yields the conversion energy losses as a function on the capacitance C 0 , ( )

Fig. 3 .

 3 Fig. 3.12 and Fig. 3.13 illustrate the conversion efficiency versus the capacitance C 0 , the intermediate voltage U C0inM and cost of the ultra-capacitor module.

Fig. 3 .Fig. 3 .

 33 Fig. 3.12 The conversion efficiency and intermediate voltage U C0inM versus the ultra-capacitor rated capacitance C 0 and the ultra-capacitor module cost. The ultra-capacitor module rated voltage U C0max =800V, braking time T BR =20s, the conversion power P C0 =4kW, 5.5kW, 7.5kW and 11kW.

Fig. 4 . 1

 41 Fig. 4.1 State of the art topologies of the inter-connection dc-dc converters. a) single phase two level , b) three phase two level, c) boost-buck, d) buck-boost.

Fig. 4 .

 4 Fig. 4.2 shows a circuit diagram of a three-level bi-directional dc-dc converter. The converter is composed of four switches SW 1A , SW 1B , SW 2A and SW 2B and four freewheeling diodes D 1A , D 1B , D 2A and D 2B , an output filter inductor L C0 and two input filter capacitors C B1 and C B2 .

Fig. 4 . 2

 42 Fig. 4.2 Circuit diagram of the interface bidirectional dc-dc converter based on three-level topology.

  and T SW is the switching period. The modulation signals d 1 and d 2 are duty cycles generated by the control circuit. The control circuit controls the ultra-capacitor current i C0 and balances the voltages v C1 and v C2 . The modulation carriers are triangular signals v T1 and v T2 shifted for π radians and running at the same frequency f SW (see Fig. 4.3 ). Fig. 4.3 (a) shows the converter waveforms when d 1 =d 2 <1/2, while Fig. 4.3 (b) shows the waveforms when d 1 =d 2 >1/2. Depending on the switches state, four different topological stages can be distinguished, namely A, B, C and D. Equivalent circuit diagrams for these stages are illustrated in Fig. 4.3 (c). The input filter capacitors are modeled as ideal voltage sources v C1 and v C2 .

Fig. 4 . 3

 43 Fig. 4.3 Different topological stages of the three-level dc-dc converter: a) ideal waveforms for d<1/2, b) ideal waveforms for d>1/2, c) equivalent circuits for the stages A, B, C and D.

Fig. 4 . 4

 44 Fig. 4.4 The inductor current ripple ∆i C0 versus duty cycle d (the duty cycle corresponds to the ultracapacitor voltage u C0 ). The ripple is normalized on the maximum current ripple when two-level dc-dc converter is used.

Fig. 4 . 5

 45 Fig. 4.5 The filter capacitors currents i C1 and i C2 and the voltages v C1 and v C2 at different duty cycle: a) d<1/2 and b) d>1/2.

Fig. 4 . 6

 46 Fig. 4.6 The capacitors voltage ripple ∆v BUS versus duty cycle d (duty cycle corresponds to the ultracapacitor voltage u C0 ). The conversion power P C0 and the dc bus voltage V BUS are considered as constant. The ripple is normalized on the maximum voltage ripple when two-level dc-dc converter is used.

Fig. 4 . 7

 47 Fig. 4.7 Advanced power semiconductor switches performances versus rated voltage. a) Active switches and b) diodes.

Fig. 4 . 8

 48 Fig. 4.8 Prototype of 5.5kW three-level dc-dc converter.

Fig. 4 . 9

 49 Fig.4.9 The inductor losses versus the load power P C0 and duty cycle (that is proportional to the ultracapacitor voltage d≈u C0 /v BUS ). v BUS =700V and the inductor core temperature T C =100°C.

Fig. 4 .Fig. 4 .

 44 Fig.4.10 The switches total losses versus the load power P C0 and duty cycle (that is proportional to the ultra-capacitor voltage d≈u C0 /v BUS ). The dc bus voltage v BUS =700V, the switch junction temperature T J =150°C.

Fig. 4 .

 4 Fig. 4.11 and Fig. 4.12 show graph of the IGBT and FWD losses versus conversion power and duty cycle. The IGBT switching losses are dominant and quite dependent on the duty cycle. In contrast to this, the IGBT conduction losses are almost constant overall whole range of the duty cycle. The FWD losses, particularly conduction losses vary significantly with the duty cycle.

Fig. 4 .

 4 Fig. 4.12 The FWD losses versus the load power P C0 and duty cycle (that is proportional to the ultra-capacitor voltage d≈u C0 /v BUS ). a) Conduction losses, b) switching losses. The dc bus voltage v BUS =700V, the switch junction temperature T J =150°C.

Fig. 4 .

 4 Fig.4.13 The switches losses versus the load power P C0 and duty cycle (that is proportional to the ultracapacitor voltage d≈u C0 /v BUS ). The dc bus voltage v BUS =700V, the switch junction temperature T J =150°C, the inductor core temperature T C =100°C.

Fig. 4 .

 4 Fig. 4.14 and Fig. 4.15 show waveforms of the converter output voltage v OUT , the ultra-capacitor voltage u C0 and the current i C0 when the ultra-capacitor voltage u C0 takes different value. Fig. 4.14 (a) and Fig. 4.14 (b) show the waveforms when u C0 <v BUS /2 (d<1/2). The output voltage takes discreet value of zero and v BUS /2, which corresponds to the topological stages A, B and C (Fig. 4.3).

Fig. 4 .

 4 Fig. 4.15 (a) and Fig. 4.15 (b) show the waveforms when u C0 >v BUS /2 (d>1/2). The output voltage v OUT takes discreet value of v BUS /2 or v BUS , which corresponds to the topological stages B, C and D (Fig. 4.3). Fig. 4.14 (b) and Fig. 4.15 (b) show the waveforms when the ultra-capacitor voltage is slightly lower or greater than v BUS /2. In the both cases the current ripple almost disappeared, as given in ( 4.8).

Fig. 4 .

 4 Fig. 4.14 Experimental waveforms of the output voltage v OUT [100V/div] the ultra-capacitor current i C0 [2A/div] and the ultra-capacitor voltage u C0 [100V/div] for different duty cycle d. a) d<1/2, b) d=1/2ε, where ε≈0. v BUS =500V, i C0(AV) =10A, L C0 =600µH, f SW =25kHz.

Fig. 4 .

 4 Fig. 4.16 (a-c) shows waveforms of the output current and ac component of the voltages v C1 , v C2 and v BUS when the duty cycle takes different values; a) d≅1/4, b) d≅1/2, c) d≅3/4. Noise in the voltage waveforms is the commutation noise picked up by the active voltage probes that were used to measure the capacitor voltages. The output current ripple and dc bus voltage ripple are practically disappeared as the duty cycle approaches 1/2.

Fig. 4 .

 4 Fig. 4.16 (d-f) shows the output current, the ac component of the voltages v C1 and v C2 , and the capacitors mid-point current ∆i C when the duty cycle takes different values, d) d≅1/4, e) d≅1/2, f) d≅3/4. The capacitors mid-point current ∆i C is alternative current having symmetrical positive and negative segments. Spikes that are seen in the current waveforms (the red ellipses) are the FWD reverse recovery current.

Fig. 4 .

 4 Fig. 4.16 Experimental waveforms of the capacitor voltages v C1 , v C2 , [5V/div], the dc bus voltage v BUS [5V/div] and the ultra-capacitor current i C0 [5A/div] at different the duty cycle. a) d≅0.25, b) d≅0.5 and c) d≅0.75.The waveforms of the capacitor voltages v C1 , v C2 , the mid point capacitor current ∆i C and the ultra-capacitor current i C0 at different duty cycle. d) d≅0.25, e) d≅0.5 and f) d≅0.75. v BUS =500V, i C0(AV) =10A, L C0 =600µH, f SW =25kHz.

Fig. 5 . 1

 51 Fig. 5.1 An example of switching mode power converter that consists of a linear passive network and a non-linear switching network. a) Circuit diagram and b) waveforms of the switching cell voltages and currents.

Fig. 5 .

 5 Fig. 5.2 shows the converter equivalent circuit diagram. The input filter capacitors are modeled by ideal capacitors C B1 , C B2 . The capacitors leakage current is modeled by the current sources i B1 and i B2 . Resistance R LC0 is the inductor resistance that is a constant (frequency independent) resistance.

Fig. 5 . 2

 52 Fig. 5.2 The dc-dc converter large signal (average) model.

Fig. 5 . 3

 53 Fig. 5.3 The dc-dc converter small signal model.

Fig. 5 .

 5 Fig. 5.4 (a) illustrates a block diagram of the small signal model( 5.15). This model will be further used for synthesis of the current controller (i C0 ) and the input voltage error controller (∆v C ). The transfer functions ( 5.15) are second order functions, wherein the nominators and denominator coefficients depend on the steady state variables: ∆V C , ∆D, U 0 and I C0 . If the system is well designed and controlled, the steady state voltage balancing error is

  The transfer functions G iCu0 and G vC∆d have become first order functions. The crosscoupling terms G iC∆d and G iC0∆d are zero; u 0 has no influence on the voltage balancing error ∆v C and ∆d has no influence on the output current i C0 . Bode diagrams of the transfer functions ( 5.15) have been computed for different conditions and depicted in Fig.5.4 (b), (c) and (d).To prove small signal model( 5.15), the dc-dc converter frequency response was simulated under different conditions. The results are included in the Bode diagram of Fig.5.4 at different frequencies; 1Hz, 10Hz, 100Hz and 1kHz.

Fig. 5 .

 5 Fig. 5.4 a) The dc-dc converter small signal model. Bode diagram of the system transfer functions: b) the control to the ultra-capacitor current system transfer function

Fig. 5 . 5

 55 Fig. 5.5 Model of the dc bus filter and load.

Fig. 5 .

 5 Fig. 5.6 Incremental (small signal) resistance versus the dc bus load.

  .7 (a). Block diagram of the converter model is depicted in Fig. 5.7 (b).

Fig. 5 . 7

 57 Fig. 5.7 Model of entire power conversion system. a) Circuit diagram and b) bloc diagram.

. 29 )

 29 Block diagram of the small signal model ( 5.29) is depicted in Fig.5.8.

Fig. 5 . 8

 58 Fig. 5.8 Block diagram of small signal model of the conversion system of Fig. 5.7.

Fig. 5 .Fig. 5 . 9

 559 Fig. 5.9 illustrates small signal block diagram of the converter, including control scheme for the ultra-capacitor current and the voltage balancing error. The converter model and two controllers can be distinguished. The controller Gi C0 controls the ultra-capacitor current i C0 , while the controller G∆v C controls the voltage balancing error ∆v C . The current reference is i C0REF , while the reference for the voltage balancing controller is zero.

Fig. 5 .

 5 Fig. 5.10 Realization of the ultra-capacitor current and the voltage balancing error control.

  3.4). The ultracapacitor voltage reference u C0(REF) is sum of the output signals of the dc bus voltage controllers G vBUSmax and G vBUSmin .

Fig. 5 .

 5 Fig. 5.11 Experimental waveforms of the capacitor voltages v C1 , v C2 [10V/div] and the ultra-capacitor current i C0 [5A/div]. The ultra-capacitor current commutes from -9A to +10A.

Fig. 5 .

 5 Fig. 5.13 The ultra-capacitor voltage closed loop.

5. 5 . 4 . 1 .

 541 Fig. 5.14 shows the ultra-capacitor voltage control loop, where G C0 is the ultracapacitor current to voltage transfer function ( 5.30), G uC0 is the voltage controller and G F is the feedback filter.

Fig. 5 .

 5 Fig. 5.14 The ultra-capacitor voltage closed loop.

(

. 42 )From Fig. 5 .

 425 14 and ( 5.39) one can determine the ultra-capacitor voltage error as

Fig. 5 .

 5 Fig. 5.15 Relation between the ultra-capacitor controller gain and control performance. a) The ultracapacitor voltage is lower than the maximum U C0max . b) the ultra-capacitor voltage is high, slightly lower than the maximum U C0max .The controller proportional gain k PC0 is computed from ( 5.44) as

Fig. 5 .

 5 Fig. 5.16 a) The filter time constant T F versus damping factor and the controller gain. R C0 =2Ω, C C0 =0.3F, k C =0.1/700 F/V. b) T F versus damping factor at fixed controller gain k PC0 =5.

Fig. 5 .

 5 Fig. 5.17 Block diagram of the dc bus voltage closed loop control.

Fig. 5 .

 5 Fig. 5.18 Bode diagram of the transfer function ( 5.47). The ultra-capacitor feedback filter time constant is T F =100ms. The ultra-capacitor C C0 =0.4F (the red trace) and an infinite capacitance (the blue trace).

54 )

 54 If the dc bus capacitor series resistance can be neglected,

Fig. 5 .

 5 Fig. 5.19 The dc bus voltage closed loop root locus versus the ultra-capacitor voltage U C0 . V BUS =700V, f BUS =25Hz, k PBUS =0.08, k IBUS =16.

Fig. 5 .

 5 Fig. 5.20 Bode diagram of the dc bus voltage transfer function v BUS (s)/v BUS(REF) (s) for different time constant of the ultra-capacitor voltage feedback filter.

Fig. 5 .

 5 Fig.5.22 (a) shows the dc bus voltage and the ultra-capacitor current and voltage waveforms during transition from the mains motoring mode to braking mode. Fig.5.22 (b)

Fig. 5 .

 5 Fig. 5.21 Simulation waveforms of the dc bus voltage v BUS , the ultra-capacitor voltage u C0 and current i C0 during the mains motoring-braking-the ultra-capacitor motoring mode. v BUSmax =700V, f B =50Hz, P LOAD =+/-5000W, C BUS =820µF, C C0 =0.4F.

Fig. 5 .Fig. 5 .

 55 Fig. 5.23 Experimental waveforms of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div], the dc bus voltage v BUS [100V/div] and the mains current i MAINS [50A/div]. a) Transition from the mains motoring mode to the braking mode. b) Transition from the mains motoring to ride-through mode.

Fig. 5 .

 5 Fig. 5.24 Experimental waveforms of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div], the dc bus voltage v BUS [100V/div] and the rectifier current i REC [5A/div]. The dc bus voltage controller response on a step load. a) Transition from stand by mode to the ultra-capacitor motoring mode, b) transition from the ultra-capacitor motoring mode to stand by mode. V BUSmax =700V, u C0 =550V and f B =50Hz.

Fig. 6 . 1

 61 Fig. 6.1 Cost comparison of the ultra-capacitor based regenerative drive versus back-to-back and matrix converter regarding braking time and ride-through time.

Fig. 6 . 2

 62 Fig. 6.2 Two-level versus three-level dc-dc converter.

Fig. 6 . 3

 63 Fig. 6.3 Comparison of the filter inductor size versus minimum duty cycle (corresponds to the minimum ultra-capacitor voltage).

Fig. 6 . 4

 64 Fig. 6.4 Comparison of the filter capacitance (a) and the filter capacitor total energy (b) versus minimum duty cycle (corresponds to the minimum ultra-capacitor voltage). The capacitance and energy are computed as ratio of the capacitance and energy of the filter capacitor of two-level to three-level topology.

Fig. 6 . 5

 65 Fig. 6.5 The switches (IGBT+FWD) relative losses versus duty cycle and conversion power. The relative losses are computed as ratio of total losses of two-level dc-dc converter to the three-level dc-dc converter.

Fig. 7 . 1

 71 Fig. 7.1 State of the art rectifier topologies a) diode front end rectifier, b) continuous conduction mode (CCM) single switch boost rectifier, c) discontinuous conduction mode (DCM) single switch boost rectifier, d) double boost, and e) an electronic smoothing inductor (ESI) rectifier.

Fig. 8 .

 8 Fig. 8.1 a) Basic principle of the proposed boost rectifier, b) the rectifier voltage v REC , the dc bus voltage v BUS and the compensation voltage v 0 , the mains phase-to-phase voltage v MAINS , the mains phaseto-neutral voltage v MAINS(phase) and the mains phase current i MAINS .

Fig. 8 . 2

 82 Fig. 8.2 Realization of the LFT with two dc-dc converters. a) DC-DC2 is connected on top capacitor C B2 and the dc bus, b) DC-DC2 is connected on bottom capacitor C B1 and the dc bus, and c) DC-DC2 is connected on C B1 and C B2 .

Fig. 8 . 4

 84 Fig. 8.4 Realization of the LFT using two three-points connected dc-dc converters, and b) some details of a possible realization.

  .5 (b). The THD and PWHD factors are indicated in Fig. 8.5 (b).

Fig. 8 .

 8 Fig. 8.5 a) Ideal waveform of the mains current, and b) amplitude spectra up to 40 th harmonic. The THD and PWHD factor are computed from definitions ( 8.12) and ( 8.13).

Fig. 8 . 6 Fig. 8 . 7

 8687 Fig. 8.6 Experimental waveforms the mains current i MAINS [5A/div] and voltage v MAINS [200V/div] and the dc bus voltage v BUS [200V/div]. a) Rectifier with proposed half-dc-bus-voltage rated topology. b) An ordinary diode rectifier with capacitive filter. V MAINS =400V, V BUS =650V, P LOAD =5.5kW.

Fig. 8 . 8

 88 Fig. 8.8 Circuit diagram of the DC-DC1 converter.

Fig. 8 .

 8 Fig. 8.9 a) The equivalent circuit of the DC-DC1 converter. b) Waveforms of the inductor voltage v L0 , and the current i L0 , and c) the voltages v REC , v 1 , v BUS , v 0 , v C1 and v C2 .

Fig. 8 .

 8 Fig. 8.10 shows 3-D graph of the duty cycle ( 8.16) versus the boost factor and angle

Fig. 8 .

 8 Fig. 8.10 Duty cycle d versus the boost factor k BOOST and angle ω is the mains angular frequency.

Fig. 8 .Fig. 8 .

 88 Fig. 8.11 (a) illustrates the functionality of the DC-DC1 converter. Experimental waveforms of the rectifier voltage v REC , rectifier current i REC and the voltage v 1 are shown. The voltage v 1 is the voltage between the inductor and minus dc bus (see Fig. 8.11 (a)).Fig.

Fig. 8 .

 8 Fig. 8.12 The rectifier current ripple versus the boost factor k BOOST and angle ωt, where ω is the mains angular frequency. The ripple is normalized on the maximum current ripple achieved at d=0.5.

SI

  is the switch peak current and F t is the current fall time. Notice that the voltage rating is one half of the dc bus voltage in contrast to the ordinary boost converter.o Current Stress and LossesThe switch average and RMS current are

(

Fig. 8 .

 8 Fig. 8.13 DC-DC2 converter circuit diagram.

Fig. 8 .

 8 Fig. 8.14 Different topological stages of the converter. A) S1, D1 are conducting, B) S1 is conducting D1 is blocking, C) S2, D2 are conducting, and D) S2 is conducting D2 is blocking.

Fig. 8 .

 8 Fig. 8.15 illustrates the functionality of the DC-DC2 converter. Waveforms of the rectifier voltage v REC and current i REC and the resonant current i 2R are shown. Note that the peak of the current i 2R changes as the rectifier voltage changes, as predicted in ( 8.36) and ( 8.38). Fig. 8.16 shows a zoomed in disply of these waveforms and voltage v S1 of the bottom switch S 1 (circuit in Fig. 8.13); Fig. 8.16 (a) is zoomed at the peak of the rectifier voltage and Fig. 8.16 (b) is zoomed at the minimum rectifier voltage. Note that the switches commutate at the zero current condition.

Fig. 8 .Fig. 8 .

 88 Fig. 8.15 Experimental waveforms of the rectifier current i REC [5A/div], the rectifier voltage v REC [100/div] and resonant circuit current i R2 [5A/div]. V MAINS =400V, V BUS =650V, P LOAD =5.5kW.

  average and RMS current, one can compute conduction losses of the switch and diode as

Fig. 8 .

 8 Fig. 8.17 a) Volume of MKP Epcos film capacitors B32674 versus capacitances at 450Vdc rated voltage. b)Volume of an air-core inductor versus the inductance at 10Arms rated current.

Fig. 8 .Fig. 8 .

 88 Fig. 8.18 a) Prototype of the boost converter. b) The resonant air-core inductor 0.6µH 10Arms.

Fig. 8 .Fig. 8 .

 88 Fig. 8.20 The switch S 0 losses versus the boost factor and conversion power.

Fig. 8 .Fig. 8 .

 88 Fig. 8.22 The switch S 1/2 and diode D 1/2 losses versus the boost factor and conversion power. The losses are computed per one device (total losses are twice).

)

Fig. 9 .

 9 Fig. 9.1 a) Simplified circuit diagram of the DC-DC2 converter, and b) the equivalent circuit diagram.

Fig. 9 . 2

 92 Fig. 9.2 The resonant current i R2 . a) Time diagram, and b) the phase portrait.

Fig. 9 . 3

 93 Fig. 9.3 Average current of the switch and diode versus number of cycles k.

Fig. 9 . 4

 94 Fig. 9.4 Large signal model of the entire boost rectifier.

Fig. 9 . 5

 95 Fig. 9.5 Bode diagram of the system transfer functions. a) v BUS (s)/i REC (s) and b) i 2 (s)/i REC (s). Red dots/squares: simulated values, blue line: value computed from ( 9.22) and ( 9.23).

Fig. 9 . 6

 96 Fig. 9.6 The boost converter control structure.

. 26 )

 26 Let us consider that the bus voltage controller is a conventional proportional-integral (PI) controller s k k I P + . The dc bus voltage closed loop transfer function is

(

Fig. 9 . 7

 97 Fig. 9.7 Simplified small signal block diagram.

  [START_REF] Jih-Sheng | Energy management power converters in hybrid electric and fuel cell vehicle[END_REF]) into ( 9.34) yields a biquadratic function with the dc bus voltage controller bandwidth f B as unknown variable. Real and positive solution of that equation gives maximum bandwidth f Bmax for the relative current ripple ( ) pu ∆ given as the design parameter.

Fig. 9 . 8 Fig. 9 .

 989 Fig. 9.8 The controller bandwidth versus the rectifier current ripple at 300Hz.

Fig. 9 .

 9 Fig. 9.10 Frequency response of the dc bus voltage controller under different conditions; 1) simplified model (33), 2) neglected the current control response time (T REC =0), and 3) a system without approximations. a) f B =10Hz and b) f B =100Hz.

Fig. 9 .

 9 Fig. 9.13 (a) shows waveforms of ac component of the rectifier voltage and current. Note the 300Hz component in the current waveform. This harmonic is caused by the dc bus voltage ripple via the voltage controller.

Fig. 9 .

 9 Fig. 9.11 Simulation of the boost rectifier under step load variation (10% to 100% to10%). a) and c) the dc bus voltage, and b) and d) the rectifier current. The controller bandwidth f B =10Hz (a, b), andf B =100Hz (c, d). P LOAD =550-5500W, V BUS =650V, V REC =600V, L 0 =300µH, C BUS =800µF.

Fig. 9 .

 9 Fig. 9.12 Simulation of the boost rectifier under step load variation (10% to 100% to10%). (a, c) the balancing voltage error ∆v C and (b, d) the current i 2 that is averaged over the switching period. The controller bandwidth f B =10Hz (a, b), and f B =100Hz (c, d). P LOAD =550-5500W, V BUS =650V, V REC =600V, L 0 =300µH, C BUS =800µF.

Fig. 9 .Fig. 9 .

 99 Fig. 9.13 The voltage controller response on step load. The rectifier current i REC [1A/div] and ac component of the dc bus voltage v BUS [50V/div]. a) Step load from 10% to 100%, and b) from 100% to 10%. V BUS =650V, V MAINS =400V, L 0 =325µH, C BUS =800µF and f BOOST =50Hz.

Fig. 10 . 1

 101 Fig. 10.1 State of the art solutions. a) Diode rectifier with passive filter, b) single switch boost rectifier and c) double boost rectifier.

8. 4

 4 Fig. 10.2 a) Circuit diagram of the half-dc-bus-voltage-rated boost rectifier under single-phase supply conditions. b) Waveforms of the dc bus voltage v BUS , rectifier voltage v REC , the mains current i MAINS and voltage v MAINS .

Fig. 10 .

 10 Fig. 10.3 shows waveforms of the mains voltage and current and the dc bus voltage when the proposed boost rectifier and the ordinary diode rectifier with capacitive filter are used. The waveforms are recorded at 4000W load.

Fig. 10 . 3

 103 Fig. 10.3 Experimental waveforms of the mains voltage v MAINS [200V/div] and current i MAINS [20A/div] and the dc bus voltage v BUS [200V/div]. V BUS(AV) =650V, V mains(RMS) =400V, P LOAD =4000W, C BUS =820µF.

  idealization, the current fall time and rise time are zero. That means the current instantaneously commutes from zero to I REC at instant 0 α α = and from I REC to zero at instant factor k BOOST are plotted in Fig. 10.4. Notice that the minimum angle 0 α is 30° (π/6

Fig. 10 . 4

 104 Fig. 10.4 The threshold angle α 0 and conducting angle π-2α 0 versus the boost factor.

Fig. 10 .

 10 Fig. 10.5 illustrates the mains peak and RMS current versus the boost factor k BOOST .

  versus the boost factor are plotted in Fig. 10.6. The minimum THD that is possible to obtain is approximately 31% at minimum angle °= 30 0 α

Fig. 10 . 5

 105 Fig. 10.5 The mains peak and RMS current versus the boost factor.

Fig. 10 . 6

 106 Fig. 10.6 Total harmonic distortion (THD) and power factor (PF) versus the boost factor.

10. 3 . 1 .Fig. 10 .

 3110 Fig. 10.7 a) The DC-DC1 converter equivalent circuit. b) The dc bus voltage v BUS , the rectifier voltage v REC and switching voltage v 1. .

Fig. 10 . 8

 108 Fig. 10.8 Commutation of the mains diode. a) the equivalent circuit, and b) zoom of the rectifier voltage and current.

Fig. 10 .

 10 Fig. 10.9 (a) shows experimental waveforms of the rectifier voltage v REC and current

Fig. 10 .

 10 Fig. 10.9 a) Experimental waveforms of the rectifier voltage v REC [100V/div] and current i REC [10A/div] and the dc bus voltage v BUS [100V/div]. b) Zoom. V BUS(AV) =650V, V MAINS(RMS) =400V, P LOAD =4000W, C BUS =820µF .

  .[START_REF] Inoue | An efficient induction motor drive method with a regenerative power storage system driven by an optimal torque[END_REF]

Fig. 10 .

 10 Fig. 10.10 shows experimental waveforms of the dc bus voltage v BUS , the rectifier voltage v REC , and current i REC and the resonant circuit current i 2R . Fig. 10.10 (b,c,d) shows zoom of the waveforms at different operating points; b) start of the mains diode conduction (ω m t=α 0 ) , c) end of the mains diode conduction (ω m t=π-2α 0 ), and d) peak of the rectifier voltage (ω m t=π/2).

Fig. 10 .

 10 Fig. 10.10 Experimental waveforms of the rectifier voltage v REC [100V/div] and current i REC [10A/div], the dc bus voltage v BUS [100V/div] and the resonant current i R2 [20V/div]. b) start of the mains diode conduction (ω m t=α 0 ), c) end of the mains diode conduction (ω m t=π-2α 0 ) and d) zoom at peak of the rectifier voltage (ω m t=π/2). V BUS(AV) =650V, V MAINS(RMS) =400V, P LOAD =4000W, C BUS =820µF.

Fig. 10 .

 10 Fig.10.12 illustrates the capacitor ripple current versus the boost factor. The capacitor RMS current is normalized to 1kW. Hence, to compute the absolute current ripple, the value from the graph in Fig.10.12 has to be multiplied by the load power given in [kW].

Fig. 10 .

 10 Fig. 10.11 The dc bus capacitance normalized on 1kW dc bus load and 1Vpp the dc bus voltage ripple

Fig. 10 .

 10 Fig. 10.12 The capacitor RMS current normalized on 1kW of the dc bus load.

3 )Fig. 11 .

 311 Fig.11.1 shows the switch utilization factor versus the boosting factor for the ordinary single switch boost converter, the electronic smoothing inductor (ESI) and the hybrid boost converter proposed in this dissertation. As seen, the ESI has the highest utilization factor. However, it operates only at the fixed boosting factor of 0.955. The proposed boost converter shows better switch utilization factor in entire range of the boost factor (1 to 1.73).

Fig. 11 . 1

 111 Fig. 11.1 The switches utilization factor versus boosting factor and different topologies.

Fig. 11 .

 11 Fig. 11.2 illustrates the inductor relative size ( 11.6) versus the boosting factor. The inductor of single-switch boost topology is taken as reference.

Fig. 11 . 2

 112 Fig. 11.2 The boost inductor relative size versus the boosting factor.11.1.1.3. Conversion LossesThe switch losses of the ordinary single switch boost rectifier are

Fig. 11 .

 11 Fig.11.3 shows ratio of the total losses of the proposed topology to the losses of a standard single switch boost converter. Note that the relative losses vary between 50% and 95%, depending on the conversion power P LOAD and boost factor. This result clearly illustrates advantage of the proposed solution in comparison with state of the art solutions.

Fig. 11 . 3

 113 Fig. 11.3 Comparison of the conversion losses of the proposed boost rectifier versus an ordinary singleswitch boost rectifier. v BUS =650V. The losses were computed from the losses model ( 8.33), ( 8.43) and ( 11.9).

  [START_REF] Tominaga | Development of energy saving elevator using regenerated power storage system[END_REF],( 10.8), ( 10.10) and ( 11.12) one can compute relative size of the proposed boost rectifier

Fig. 11 .

 11 Fig.11.5 shows the switch utilisation factor plotted versus the boost factor. Note that the proposed topology has greater the switch utilisation factor than the ordinary single-switch boost converter if the boost factor is lower than 1.55. When the boost factor is greater than 1.55, the ordinary single-switch topology has slightly greater switch utilisation factor than the new one.

Fig. 11 . 4

 114 Fig. 11.4 The boost inductor size versus the boost factor. The inductor size is normalized on the singleswitch boost inductor size.

Fig. 11 .

 11 Fig. 11.6 a) Experimental waveforms of the mains phase-to-phase voltage v MAINS [200V/div], the dc bus voltage v BUS [200V/div] and the mains current i MAINS [20A/div] when the drive is single-phase supplied. a) The drive with the proposed topology, and b) a drive with diode rectifier and passive LC filter. V BUS(AV) =650V, V MAINS(RMS) =400V, P LOAD =4000W, C BUS =820µF.

Fig. 11 . 5

 115 Fig. 11.5 The switch utilization factor versus the boost factor.

Fig. 11 .

 11 Fig. 11.7 a) The mains peak current and b) RMS current versus the boost factor. The currents are computed as ratio between currents of single-phase supplied rectifier at different load (Pn, 0.8Pn and 0.6Pn) and three-phase supplied rectifier at nominal load (Pn).

Fig. 12 .

 12 Fig. 12.1 a) Regenerative three-phase variable speed drive with the dc bus voltage boost function using the three-terminal loss-free transformer (LFT) with energy storage. b) Realization using two dcdc converters and an ultra-capacitor.

Fig. 12 . 3

 123 Fig. 12.3 Power flow for different operating modes a) the mains motoring mode (MM), b) barking mode (B), c) stand by mode (STB), d) energy recovery mode (MC0) and ride-through mode (RT), e) the ultra-capacitor charging mode (MM-CH) and f) the mains peak power filtering mode (MPFM).

Fig. 12 . 4

 124 Fig. 12.4 Waveforms at different operating modes of the drive system: the mains motoring mode (MM), braking mode (B), stand by mode (STB), energy recovery mode (MC 0 ) and ride-through mode (RT), e) the ultra-capacitor charging mode (MM-CH) and the mains peak power filtering mode (MPFM).

Fig. 12 . 5

 125 Fig. 12.5 Definition of the reference voltages V BUSmax , V BUS(REF) and V BUSmin .

Fig. 12 .

 12 Fig.12.6 illustrates the capability of the drive system to store and recover the braking energy. Waveforms of the dc bus voltage v BUS , the rectifier current i REC , the ultra-capacitor current i C0 and voltage u C0 when the drive operates in motoring/braking/motoring cycle are shown. The drive runs in the motoring mode (MM) and is supplied from the mains. The ultracapacitor voltage is U C0inM , while the dc bus voltage is regulated to the reference V BUS(REF) .Once the drive load becomes negative, the drive starts the braking phase (B) and the energy is transferred from the load to the drive dc bus. The dc bus voltage v BUS elevates towards the upper reference V BUSmax and then stays regulated to that level. At the same time, the input current i MAINS falls to zero. The ultra-capacitor voltage increases and the current decreases since the charging/discharging power is assumed constant. When the braking phase is finished, the drive load becomes again positive and the drive turns to motoring mode again (MC 0 ), but this time supplied from the ultra-capacitor. The current i C0 turns negative and the voltage u C0 starts to decrease towards the reference U C0inM . Once the ultra-capacitor voltage reaches the reference U C0inM , the current drops to zero and the dc bus voltage falls to the nominal value V BUS . The ultra-capacitor discharge phase is finished and the drive is supplied from the mains again (MM).

Fig. 12 .Fig. 12 . 7

 12127 Fig. 12.6 a) Experimental waveforms of the ultra-capacitor current i C0 [5A/div] and voltage u C0 [100V/div], the dc bus voltage v BUS [100V/div] and the mains current i MAINS [5A/div] during an entire braking-motoring cycle of the drive system. b) Zoom of transition from stand-by to the ultra-capacitor motoring mode and stand by mode. The ultra-capacitor voltage is approximately U C0 =550V. The rectifier current i REC is shown instead of the mains current i MAINS .

Fig. 12 .

 12 Fig. 12.8 (a) illustrates the system capability to control the dc bus voltage and reduce distortion of the mains current. Waveforms of the dc bus voltage v BUS , the mains phase-tophase voltage v MAINS , the rectifier current i REC and the mains current i MAINS are shown. The mains current is a square waveform of 2π/3 radians with magnitude of approximately 10A. The RMS current is 8.28A RMS. The dc bus voltage is constant and ripple-free. More details of control performance in presence of step variation of the load are discussed in the following chapter. For comparison, the waveforms of the standard diode rectifier are shown in Fig. 12.8 (b). The mains current amplitude spectrais is shown in Fig. 12.8. (c). The current total harmonic distortion factor (THD) is 29.5% and partially weighted harmonic distortion factor

Fig. 12 .

 12 Fig. 12.8 a) Experimental waveforms of the mains phase-to-phase voltage v MAINS , the dc bus voltage v BUS [200V/div], the rectifier current i REC and the mains current i MAINS [10A/div] when the drive operates in the mains motoring mode (MM). b) The same waveforms when a standard diode rectifier is used. The mains current scale is [10A/div]. c) The mains current amplitude spectra. The red bars are current spectrum of a standard diode rectifier and the blue bars are current spectra of the new drive rectifier. V BUS =650V, V MAINS =400V P LOAD =5500W.

12. 3 .

 3 Three-terminal Energy Storage and Power Factor Correction Device 12.3.1. Basic Principle Realisation of the three-terminal energy storage and power factor correction device is discussed in this section. Fig. 12.10 (a) shows circuit diagram of the solution that was proposed and discussed in part two of the dissertation. Fig. 12.10 (b) shows circuit diagram of the solution that was proposed and discussed in part three of the dissertation. Combining those two solutions into one, yields a solution that solves all the problems mentioned in the introduction, section 12.1. Circuit diagram is depicted in Fig. 12.10 (c).

Fig. 12 .

 12 Fig. 12.10 Evolution of the three-terminal energy storage and PFC device. a) Topology of parallel connected ultra-capacitor and interface dc-dc converter, b) half-dc-bus-voltage rated boost rectifier, and c) energy storage end PFC device as a combination of the previous two topologies.

Fig. 12 .

 12 Fig. 12.11 The DC-DC2 converter operating in the ultra-capacitor energy transfer mode and b) an equivalent circuit diagram [48].

Fig. 12 .

 12 Fig. 12.12 a) The DC-DC2 converter operating in the mains motoring mode, and b) an equivalent circuit diagram.

  Stage B: The current i 2R reaches zero and diode D 1 is blocked at the instant t=T 0 /2. The current remains zero until commutation of the switch S 2 .Stage C: The switch S 2 is closed at the instant t=dT S2 . The capacitor C S is discharged into v C2 via the switch S 2 , diode D 2 and the inductor L S . The current i 2R increases in negative direction in respect to the direction in Fig.12.12. The voltage v CS decreases. After reaching the maximum, the current starts to decrease towards zero (L S C S resonant circuit).

Fig. 12 .

 12 Fig. 12.13 a) Circuit diagram of the converter DC-DC2 based on ZCS switched capacitor converter. b) Different topological stages of the converter. A) S1, D1 are conducting, B) S1 is conducting D1 is blocking, C) S2, D2 are conducting, and D) S2 is conducting D2 is blocking.

Fig. 12 .Fig. 12 .Fig. 12 .

 121212 Fig. 12.14 a) Experimental waveforms of the rectifier current i REC , the resonant circuit current i 2R [10A/div] and the rectifier voltage v REC [100V/div]. The conversion power step from 10% to 100%. The bus voltage is V BUS =650V and nominal load P LOAD =5500W. b) Zoom of the waveforms including the bottom switch voltage v S1 [100V/div].

Fig. 12 .

 12 Fig. 12.17 The waveforms of the resonant circuit current i 2R [10A/div], ac component of the bottom filter capacitor voltage v C1 [5V/div], and the bottom switch voltage v S1 [100V/div]. The dc bus capacitor is connected on the board (the parasitic inductance L γ significantly reduced).

Fig. 13 . 1

 131 Fig. 13.1 Large signal model of the three-terminal energy storage and power factor correction device, rectifier and inverter load.

Fig. 13 . 5

 135 Fig. 13.5 Small signal block diagram of the control system operating in the rectifier mode.

Fig. 13 . 6

 136 Fig. 13.6 Control scheme in the ultra-capacitor energy transfer mode. The rectifier control system is saturated (deactivated).

Fig. 13 . 7

 137 Fig. 13.7 Small signal block diagram of the control system operating in the ultra-capacitor energy transfer mode.

Fig. 13 . 8

 138 Fig. 13.8 Small signal block diagram of the system operating in the mains peak power filtering mode. All controllers are active.

Fig. 13 . 9 Fig. 13 .Fig. 13 .

 1391313 Fig. 13.9 Simulated waveforms of the dc bus voltage v BUS , rectifier voltage, the ultra-capacitor voltage u C0 and current i C0 during an entire cycle; the mains motoring (MM), braking (B), the ultracapacitor motoring (MC 0 ) and the mains motoring mode (MM). P LOAD =+/-5000W, C BUS =820µF, C C0 =0.4F, V MAINS =400Vrms.

Fig. 13 .

 13 Fig.13.12 Simulated waveforms of the dc bus voltage v BUS and the mains i MAINS current when the load is cycling 10% to 100% to 10%. The bus voltage is v BUS =650V, the mains phase-to-phase voltage V MAINS =400Vrms, the dc bus capacitor C BUS =820µF and the boost voltage controller bandwidth is f BOOST =50Hz.

Fig. 13 .

 13 Fig. 13.13 Simulated waveforms of the ultra-capacitor voltage and current when the load is cycling 10% -100% -10%. The bus voltage is v BUS =650V, the mains phase-to-phase voltage V MAINS =400Vrms, the dc bus capacitor C BUS =820µF and the boost voltage controller bandwidth is f BOOST =50Hz.

Fig. 13 .

 13 Fig. 13.14 Simulated waveforms of the dc bus voltage v BUS and the mains i MAINS current when the load is cycling 10% -100% -10%. The bus voltage is v BUS =650V, the mains phase-to-phase voltage V MAINS =400Vrms, the dc bus capacitor C BUS =820µF and the boost voltage controller bandwidth is f BOOST =1Hz.

Fig. 13 .

 13 Fig. 13.15 Simulated waveforms of the ultra-capacitor voltage and current when the load is cycling 10% -100% -10%. The bus voltage is v BUS =650V, the mains phase-to-phase voltage V MAINS =400Vrms, the dc bus capacitor C BUS =820µF and the boost voltage controller bandwidth is f BOOST =50Hz.

Fig. 13 .

 13 Fig. 13.16 illustrates the functionality of the dc bus voltage boost controller, G VBUS , in presence of a step change in the dc bus load. Fig (a) shows the rectifier current, ac component of the dc bus voltage and the ultra-capacitor voltage and current when the dc bus load is stepped from 10% to 110%. The controller response time is approximately 10ms, while the voltage undershoot is approximately -15V. Fig. 13.16 (b) shows the waveforms when the load is stepped from 110% to 10%. The voltage overshoot is approximately 12V. The controller response time is slightly greater than that of the previous case. The reaction time is extended because the rectifier current is limited at zero. It cannot be negative because the input rectifier is uni-directional device. The ultra-capacitor current remains zero, because it should not be power flow between the ultra-capacitor and the drive.

Fig. 13 .

 13 Fig. 13.16 Experimental waveforms of the rectifier current i REC [5A/div], the ac component of the dc bus voltage v BUS [10V/div], the ultra-capacitor voltage u C0 [100V/div] and current i C0 [5A/div]. a)The dc bus load step from 10% to 110%, and b) from 110% to 10%. V BUS =650V, V MAINS =400Vrms, L 0 =325µH, C BUS =820µF and f BOOST =50Hz.

Fig. 13 .Fig. 13 .

 1313 Fig. 13.17 Experimental waveforms of the dc bus voltage v BUS [10V/div] and the mains i MAINS current [5A/div], the ultra-capacitor voltage u C0 [100V/div] and current i C0 [5A/div]. a) Transition from stand-by to the ultra-capacitor motoring mode and b) transition from the ultra-capacitor motoring mode to stand-by mode. V BUS =675V, u C0 =550V, V MAINS =400V, L 0 =325µH, C BUS =820µF and f BOOST =50Hz.

o 1 .

 1 Three-terminal Power Factor Correction and Energy Storage DeviceThe three-terminal energy storage and power factor correction device for controlled electric drive applications has been proposed. The proposed three-terminal device is a solution that solves some of the technical issues that still exist in application of controlled electric drives. The proposed solution has been deeply analysed and the concept verified by a set of experiments. The advantages and disadvantages have been clearly identified and discussed o Publications Most of the work presented in the dissertation is in publication and review process for IEEE Transaction on Industrial Electronics. The Ultra-capacitor in Electric Drives and Other Power Conversion Applications

  the proposed boost rectifier are identified too.

  qualité du courant d'entrée, contrôle et stabilité du bus continu, fonctionnement monophasé, et puissance crête appelée sur le réseau.La plupart des applications modernes des variateurs de vitesse, comme les ascenseurs, les grues, les machines-outils, etc… sont caractérisées par un fort déséquilibre entre leur puissance moyenne et leur puissance crête. De plus, ces applications requièrent un freinage à puissance nominale. Dans les variateurs de vitesse classiques, l'énergie mécanique emmagasinée dans la charge en mouvement est dissipée via une résistance. Les pertes énergétiques dans de telles applications s'élèvent à hauteur de 30 à 50% de l'énergie consommée. A l'heure actuelle, dans un contexte de crise énergétique, l'efficacité de ces systèmes d'entraînement devient une préoccupation prioritaire qui nécessite des réponses industrielles à très court terme. Les variateurs modernes sont sensibles aux coupures du réseau d'alimentation. Ces coupures sont susceptibles d'interrompre le fonctionnement du variateur et de bloquer une ligne entière de production. Ces interruptions sont extrêmement coûteuses et inacceptables quand le variateur est utilisé dans un processus critique comme l'extraction de pétrole ou l'industrie du verre. De telles industries ont rapporté des pertes allant de 10k$ à 1M$ par interruption. Un autre problème introduit par le variateur lui-même est la qualité du courant prélevé sur le réseau. Les redresseurs à diodes classiques équipés de filtres LC prélèvent un courant à fort contenu harmonique. L'alimentation monophasée de variateurs triphasés est une autre problématique de la qualité de l'énergie, par exemple lors de la déconnexion d'une phase du réseau d'alimentation. Dans certaines applications comme les pompes d'irrigation, le fonctionnement monophasé constitue même le mode de fonctionnement normal. Les deux solutions les plus fréquemment évoquées pour récupérer l'énergie de freinage des variateurs de vitesse sont les convertisseurs réversibles AC-DC-AC indirects, et les convertisseurs AC-AC, appelés convertisseurs matriciels. Ces variateurs utilisent l'énergie du réseau lors des phases d'accélération, et réinjectent de l'énergie dans le réseau lors des phases de freinages (décélération). Le principal inconvénient incombant à ces solutions, vient du fait que cette fonctionnalité est fortement dépendante de la qualité et de la fiabilité du réseau d'alimentation. Chaque interruption d'alimentation perturbe le variateur de vitesse, et celui-ci s'arrête complètement de fonctionner lorsque l'interruption dépasse une période réseau. Les fonctionnements en monophasé sont limités, voir impossibles pour les convertisseurs matriciels. De plus, certains variateurs de vitesse ont une forte demande en courant durant les phases d'accélération et de décélération. Ces variations importantes de courant aux bornes du variateur de vitesse ajoutent des perturbations et des pertes sur les réseaux d'alimentation peu fiables. Un autre concept de variateur de vitesse à récupération d'énergie est basé sur un convertisseur classique AC-DC-AC à diode, équipé d'un dispositif de stockage d'énergie. Ce concept revient au gout du jour, grâce aux larges applications qu'offrent les nouveaux condensateurs double couches électrochimiques (EDLC), aussi appelé supercondensateurs. En comparaison aux actuelles batteries électrochimiques, les supercondensateurs ont une densité de puissance élevée, un meilleur rendement, une durée de vie plus longue, ainsi que de meilleures performances dynamiques. Tous ces avantages font des supercondensateurs les meilleurs candidats pour les applications de puissance nécessitant un stockage énergétique. Dans notre cas, les super-condensateurs viennent stocker l'énergie durant les phases de freinage du variateur de vitesse. Cette énergie est ensuite réutilisée lors des phases d'accélération suivantes. Les variateurs de vitesse utilisant un tel concept de récupération d'énergie peuvent alimenter des ascenseurs, des machines à outils ayant des séquences accélération-décélération rapides, ainsi que d'autres applications sollicitant souvent la fonction freinage du variateur de vitesse. De plus, les supercondensateurs peuvent assurer la fonctionnalité UPS (alimentation sans interruption -uninterruptable power supply) et ainsi permettre au variateur de vitesse de rester sous tension lors des microcoupures d'alimentation, ce qui est déterminant pour des applications industrielles critiques où les arrêts sont très couteux. Dans la première partie de ce document, une introduction générale est donnée. Puis, dans la deuxième partie de ce document, sera présenté le concept de variateur de vitesse à récupération d'énergie basé sur les supercondensateurs. Les supercondensateurs sont utilisés comme élément de stockage d'énergie lors des freinages, et comme source d'énergie lorsque cela est possible. De plus, les supercondensateurs sont utilisés comme alimentation de secours lors des microcoupures de courant. A la différence des batteries électrochimiques, l'état de charge (SOC) des supercondensateurs dépend fortement de la tension à leurs bornes. Ainsi, il n'est pas possible de connecter directement les supercondensateurs au variateur de vitesse. Il est nécessaire d'utiliser une interface électronique DC-DC. L'état de l'art sur ces topologies est présenté, et un nouveau convertisseur multiniveaux DC-DC est proposé. Celle-ci est analysée et les règles de conception sont exposées. Le modèle complet du système de conversion est ensuite développé et un contrôle/commande est proposé. L'objectif de la partie contrôle est triple. Le premier objectif est de réguler le courant du supercondensateur ainsi -219-que le point milieu du bus continu du hacheur multiniveaux. Le second objectif est de faire tendre la tension du bus continu vers la tension de référence dépendant du mode d'exploitation choisi. Le dernier objectif est de contrôler l'état de charge du supercondensateur. La troisième partie de ce document présente un variateur de vitesse triphasé novateur à pont redresseur à diode en entrée mais doté d'un convertisseur élévateur alimenté par la demitension du bus continu. Ce convertisseur élévateur est composé de deux convertisseurs DC-DC ainsi que de deux condensateurs en série sur le bus continu. Le premier convertisseur régule le courant continu de sortie du redresseur d'entrée et élève la tension du bus continu à une valeur supérieure à la tension composée réseau crête. Ce convertisseur est connecté entre la borne + du bus DC et le point milieu des capacités du bus DC. Le deuxième convertisseur DC-DC est un convertisseur auxiliaire qui assiste le premier. Ce convertisseur est un convertisseur résonnant série fonctionnant en mode discontinue (type 1). Le modèle complet, non-linéaire et de petit signal, est présenté, ainsi que le mode de contrôle, le tout étant validé expérimentalement. Les avantages du hacheur élévateur original proposé comparativement aux solutions connues sont le rendement de conversion plus élevé ainsi que la taille réduite des composants aussi bien actifs (diodes et interrupteurs de puissance) que passifs (inductances et condensateurs). Cependant, le taux de distorsion harmonique du courant total (THD) ainsi que le taux de distorsion harmonique pondérée partiel (PWHD) restent élevé. Le THD tourne autour des 30% alors que le PWHD tourne autour de 55%. Comme les normes acceptent un THD de 30% pour les variateurs de vitesse utilisés à des fins industrielles tant que le PWHD est légèrement en dessous de la valeur limite, le nouveau convertisseur élévateur est une solution viable pour remplacer les convertisseurs passif à diode tout comme les redresseur à prélèvement sinus utilisant des hacheurs boost ou double boost. Cette topologie peut être utilisée aussi bien sur les variateurs monophasés que les variateurs triphasés. Dans la quatrième partie de ce document, une solution regroupant les deux solutions précédentes est présentée. Cette solution permet de résoudre les problèmes techniques actuels qui existent dans la variation de vitesse : 1) Récupérer l'énergie de freinage 2) Empêcher les disfonctionnements du variateur de vitesse lors des microcoupures 3) Augmenter la qualité du courant d'entrée du variateur de vitesse -220-4) Contrôler la tension continu (bus DC) du variateur de vitesse 5) Permettre un fonctionnement dégradé lors de la perte d'une phase réseau 6) Lisser les pics de puissance provoqués par la charge et prélévés habituellement sur le réseau La solution proposée à été analysée et les règles de conception ont été exposées. Le concept a été validé par des simulations sur Matlab/Simulink et un prototype a été réalisé et testé en laboratoire. Si on compare la solution innovante proposée avec les solutions non industrielles envisagées habituellement pour la variation de vitesse (convertisseur matricielconvertisseur classique avec stockage, convertisseur MLI réversible…), la solution originale proposée a les avantages suivant : • Capacité du variateur de vitesse à rester fonctionnel lors des microcoupures d'alimentation est améliorée. La durée de microcoupure maximale tolérée est alors un paramètre de dimensionnement du stockage.

TABLE 2 -

 2 1 compares the most important properties of the ultra-capacitor versus batteries and other type of capacitors.

TABLE 2 - 1 :

 21 Properties of the existing energy storage devices.

		Capacitors	Ultra-capacitors	Electro-chemical batteries
	Energy density [Wh/kg]	~0.1	1-6 (*)	~100
	Peak power density [kW/kg]	10 4	2-20	0.1-0.5
	Number of cycle	10 10	10 6	~10 3
	Life time [years]	~10	~15	~5

TABLE 2

 2

-2.

TABLE 2 -

 2

			2: Simulated parameters of a 2500F/2.5V ultra-capacitor at U C0 =1V. The capacitance C in
				[F] and the resistance R in [Ω].
	R 1	C 1	R 2	C 2	R 3	C 3	R 4	C 4	R 5	C 5
	0,324E-04 23,2	0,0324E-06	211	55,4E-06	235	88,4E-06	699	0,389E-04 1172

TABLE 2 -

 2 3: Existing ultra-capacitor technology versus technology under development.

		The existing	Nano-tube	Nano-gate	EesE	Mega Farad
		technology				super-capacitor
	Energy density	~5	20-40	50-80	~280	~500
	[Wh/kg]
	Operating	<2.8	~3	~3.9	3000	<2.8
	voltage [V]
	Internal	0.66+1000/C*	As the existing	As the existing	Lower than the	As the existing
	resistance [mΩ]				existing
	* This is an approximation where C is the cell capacitance [F].

TABLE 4 -

 4

1. The converter specification

TABLE 5 -

 5 1. Specification of the control system.

	ULTRA-CAPACITOR	DC BUS

TABLE 6 -

 6 1: Comparison of different drive concepts regarding ride-through capability.

		Back-to-back drive	Matrix drive converter	The ultra-capacitor based
		converter		drive
	Ride-through time in	Depends on the load. At	No ride-through	From 100ms up to
	motoring mode	full load and 100%	capability	several seconds or
		interruption, the ride-		minutes, depending on
		through time is less than		the design criteria
		100ms
	Ride-through time in	Normally less the mains
	braking mode	period (20ms)

TABLE 8 -

 8

			1: Current emission limits for balanced three-phase equipment, based on the IEC 61000-3-12
					standard [13].
	Short circuit	Admissible individual current harmonics I n /I 1 [%]		Admissible harmonic
	ratio	N SC I I					distortion factors
			I 5	I 7	I 11	I 13	THD	PWHD
		33	10.7	7.2	3.1	2	13	22
		66	14	9	5	3	16	25
		120	19	12	7	4	22	28
		250	31	20	12	7	37	38
		≥350	40	25	15	10	48	46

  .[START_REF] Chlodnicki | Supercapacitor storage application for reduction drive negative impact on supply grid[END_REF] where R L0(DC) is the inductor winding resistance at low frequency. Substituting ( 8.18) into ( 8.23) one can compute the inductor average losses,( 8.24). Here, we have to highlight that the losses model ( 8.24) is not very accurate, but sufficient as an initial step in the inductor design procedure.

	( )			( )		( )	LOAD	BOOST
						4 4 4 4 3 2 4 4 4 4 1 BUS
							LOW	FREQUENCY	LOSSES
	(	L	fSW	C	fSW	)
			BOOST			BOOST	(	)	BOOST	BOOST
	4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 BOOST
							HIGH	FREQUENCY	LOSSES

  SW is switching frequency. The switch S 0 is approximated by threshold voltage V S0 and dynamic resistance r S0 . E ON and E OFF are switching energy at the given conditions; rated voltage V N and current I N .Similar calculation is applied on the boost diode D 0 . Average and RMS currents and losses are

	S P	0	=	4 4 4 3 2 4 4 4 1 LOSSES CONDUCTION RMS S S AV S S I r I V + 2 0 0 0 0	+	4 4 4 4 2 4 4 4 4 4 1 OFF ON N N BOOST LOAD f 3 SW E E I V k P + 2	,	( 8.33)
						SWITCHING	LOSSES
	where f ( )

TABLE 8 - 2 :

 82 Specification of the half-dc-bus-voltage rated boost rectifier.

	Nominal power	P C0 =5500W
	DC bus voltage	V BUS =650V
	Minimum input (line RMS) voltage	V mains =350V
	Switching frequency DC-DC1	f SW1 =100kHz
	Switching frequency DC-DC2	f SW2 =50kHz

TABLE 11 -

 11 1 shows parameters of the boost switch and diode used in the ordinary single-switch boost rectifier. The rectifier specification (power, voltage and switching frequency) is the same as for the new boost rectifier, TABLE 8-2.

TABLE 11 - 1 :

 111 Specification of the switch and diode for the ordinary 5.5kW single switch boost rectifier.

TABLE 11 -

 11 2. P CBUS is the dc bus capacitor losses computed from the capacitor RMS current and equivalent series resistance (ESR) given as data sheet parameter.

TABLE 11 - 2 :

 112 Comparison of the ordinary diode rectifier and the proposed boost rectifier.

TABLE 13 - 1 :

 131 The conversion system and control parameters. Sampling time for the dc bus voltage controllers and the ultra-capacitor filter is

13.3.2. Experimental Results 13.3.2.1. The DC Bus Voltage Controller G BUS(REF) Performance

ACKNOWLEDGEMENTS

I wish to express my gratitude to the dissertation supervisor, Professor Philippe Le Moigne for giving me an opportunity to start my dissertation with L2EP. I appreciate his patience and time he spent to read my fifteen-pages long IEEE Transaction "essays". direction, an amount of energy is wasted as the Jule's energy. This is due to the resistance of

PART THREE: THREE-TERMINAL POWER FACTOR CORRECTION DEVICE

The Switches Losses

The switch losses are computed from ( 10.17), ( 10.18) and ( 10.21) and compared with the losses of three-phase supplied rectifier ( 8.33), ( 8.35) and ( 8.43). Fig. 11.8 shows the relative power losses that are computed as ratio of power losses of three-phase supplied rectifier to the single-phase supplied rectifier at different load (nominal, 80% of nominal and 60% of nominal). At nominal power, the losses are approximately 10% greater than that of three-phase supplied rectifier if the boost factor is lower than 1.3. At maximum boost factor, the losses are approximately 30% greater.

The Inductor Size

The size of the boost inductor for single-phase and three-phase supplied rectifier can be compared using the same method that was used in section 11. PART FOUR: THREE-TERMINAL ENERGY STORAGE AND PFC DEVICE Fig. 13.2 Small signal model of the entire power conversion system.

Control Aspects 13.2.1. The Control Objectives

The primary control objective is to asymptotically regulate the dc bus voltage to the reference, where the reference depends on the system-operating mode. The secondary control objective is to regulate the rectifier current to be constant or quasi-constant in order to reduce the mains current total harmonic distortion (THD). The last control objective is to regulate the ultra-capacitor state of the charge, where the state of charge reference depends on the operating mode.

Control Scheme

The control scheme is illustrated in Fig. 13.3. Note two sections, namely DC-DC1 CONTROL and DC-DC2 CONTROL. The first control block consists of the controllers G iREC and G vBUS . The controller G iREC regulates the rectifier current, while the controller G vBUS asymptotically regulates the dc bus voltage to the reference V BUS (REF) . The block denoted as DC-DC2 CONTROL consists of the ultra-capacitor current controller G iC0 , the ultra-capacitor voltage controller G uC0 and two dc bus voltage controllers, G vBUSmax and G vBUSmin . The midpoint voltage balancing controller is not illustrated in the control structure. It was discussed in chapter 6.

Operational Modes

From control perspective, the system may operate in three different modes: 1) the rectifier mode, 2) the ultra-capacitor energy transfer mode and 3) the mains peak power filtering mode.

The Rectifier Mode

Fig. 13.4 illustrates the control scheme when the drive operates in the rectifier (the mains motoring) mode. When operates in this mode, the drive is supplied from the mains. The dc bus voltage is actively controlled by the DC-DC1 converter to the reference V BUS(REF) .

13. MODELING AND CONTROL SCHEME -185- As mentioned before, in chapter 12 (Fig. 12.5 (a)), the dc bus voltage is v BUS =V BUS (REF) , where the reference V BUS(REF) is lower than the reference V BUSmax and greater than the reference V BUSmin . Thus, the controller G vBUSmax is saturated at U C0inM , while the controller G vBUSmin is saturated at zero. Please, note that the controllers G vBUSmax and G vBUSmin are designed in such a way to have

, where out is the controllers output u 1(REF) and u 2(REF) , and error is the controllers input (the dc bus voltage control error). The symbols ↑ and ↓ denote that the variable increases and decreases respectively.

The ultra-capacitor voltage reference is constant,

( 13.10)

The controller G uC0 regulates the ultra-capacitor voltage to the intermediate reference U C0inM in order to prevent power flow between the ultra-capacitor and the drive. (  )

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