Vladyslav Shaposhnyk

Pierre Dutoit

Stephen Perrig

Alessandro E P Villa

Functional connectivity driven by external stimuli in a network of hierarchically organized neural modules

Keywords: spiking neural networks, hierarchical neural networks, distributed computing, computational neuroscience, EEG

Complex neural modules with embedded neural development and synaptic plasticity features have been connected to form a hierarchical recurrent circuit. Virtual electrodes have been used to record a "neural" generated signal, called electrochipogram EChG, from each module. The EChG are processed by frequency domain methods to determine the modifications in functional connectivity by assessing quadratic phase coupling. The experimental paradigm is aimed to describe what happened prior to, at the beginning, towards the end, and after repeating an external input at fixed frequency. The results are discussed by comparing with the same signal processing methods applied to a human study.

Introduction

At mesoscopic level, the recording of brain activity by means of electroencephalography (EEG), electrocorticography (ECoG) and local field potentials (LFP) collects the signals generated by multiple cell assemblies. The neurophysiological processes underlying those signals are determined by highly non-linear dynamical systems [START_REF] Nunez | Electric Fields of the Brain[END_REF]. Because of these nonlinearities the functional interactions between brain areas that are simultaneously sampled by electrophysiological techniques generate signals that can be better analyzed by third order polyspectral methods that retain phase relationships [START_REF] Brillinger | An introduction to polyspectra[END_REF]. This analysis was applied to EEG by pioneers as early as the 1970s [START_REF] Dumermuth | Analysis of the interrelations between frequency bands of the EEG by means of the bispectrum. a preliminary study[END_REF]. Phase coupling frequencies can be interpreted as frequencies of resonance of standing waves whose wavelength is associated to the average distance between interacting cell assemblies [START_REF] Villa | Corticofugal modulation of functional connectivity within the auditory thalamus of rat[END_REF][START_REF] Villa | Non-linear cortico-cortical interactions modulated by cholinergic afferences from the rat basal forebrain[END_REF].

In the present study we simulate the activity of interconnected neural networks undergoing neural developmental phases. The implementation of such complex models requires high performance of the simulation that can be achieved thanks to a powerful hardware platform, its bio-inspired capabilities, its dynamical topology, and generic flexibility of artificial neuronal models presented elsewhere [START_REF] Iglesias | Effect of stimulus-driven pruning on the detection of spatiotemporal patterns of activity in large neural networks[END_REF][START_REF] Iglesias | Emergence of preferred firing sequences in large spiking neural networks during simulated neuronal development[END_REF]. The outcome is the implementation of each neural network into a Ubidule and a network of Ubidules as a Ubinet. Within each Ubidule the emergence of functional connectivity driven by neural development, cell and synaptic pruning, and selective external stimuli was assessed by recording Electrochipograms (EChG) which are analog signals similar to EEG generated by virtual electrodes located into each Ubidule [START_REF] Shaposhnyk | A framework for simulation and analysis of dynamically organized distributed neural networks[END_REF].

The experimental paradigm is aimed to describe what happened prior to, at the beginning, towards the end, and after repeating an external input at fixed frequency. The rationale is that the spike timing dependent plasticity (STDP) embedded in the neural network models would drive the build-up of auto-associative network links, within each Ubidule, such to generate an areal activity, detected by EChG, that would reflect the changes in the corresponding functional connectivity within and between Ubidules. This experiment is compared to a small set of recordings performed in patients suffering of primary insomnia whose EEG recordings were analyzed during several sleep phases, before and after a clinical treatment.

Hybrid system implementation

The Ubidule is a custom reconfigurable electronic device allowing an implementation of several bio-inspired mechanisms such as growth, learning, and neural processing [START_REF] Sanchez | Perplexus: Pervasive computing framework for modeling complex virtually-unbounded systems[END_REF]. The common Ubidule platform is an hybrid system with an XScale-class processor that manages the software components of the system, such as ontogenetic processes, communications with other Ubidules, monitoring and recording of the activity. This processor is equipped with an open hardware subsystem which allows connecting any sort of USB device (sensors, actuators, Wifi / Bluetooth dongles, mass storage, etc.). The processor runs an embedded Linux operating system which facilitates Ubidule programming and management while ensuring portability at the same time.

Both hardware and software platforms are based upon modular architecture that offers interoperability among the hardware and the software parts of the system and simplifies the usage of bio-inspired features of the hardware. The neural system simulator consists of multiple computational modules, each one corresponding to a neural network, exchanging their neural activity and/or receiving input data from hardware sensors (camera, photodiode, radars, etc.) and/or providing output to hardware actuators (motor, diode array, etc.). The characteristics of the implementation naturally geared the modeling framework towards agent oriented programming. An evaluation of the available platforms of this kind led us to select JADE [START_REF] Bellifemine | Developing Multi-Agent Systems With Jade[END_REF] for the development and runtime execution of peer-to-peer applications which are based on the agent oriented paradigm [START_REF] Brousse | A bio-inspired agent framework for hardware accelerated distributed pervasive applications[END_REF]. It is a JAVA-based multi-agent development system that fulfils the FIPA specifications [START_REF] Fipa | Fipa communicative act library specification[END_REF].

In this study each network is a 2D lattice of 20 x 20 units that includes 80% of excitatory units and 20% of inhibitory units. Our framework implements several features of brain maturation, including apoptosis active during the very initial 700 time units and STDP active from the end of apoptosis until the end of simulation. This framework was extensively described elsewhere [START_REF] Iglesias | Dynamics of pruning in simulated large-scale spiking neural networks[END_REF][START_REF] Iglesias | Effect of stimulus-driven pruning on the detection of spatiotemporal patterns of activity in large neural networks[END_REF][START_REF] Iglesias | Emergence of preferred firing sequences in large spiking neural networks during simulated neuronal development[END_REF]. Synaptic pruning occured when the activation level of a synapse reached a value of zero, so that besides cell death and axonal pruning of dead cells provoked by apoptosis, the units whose all synaptic connections were characterized by a zero level of activation were definitely eliminated from the network. All units were simulated by leaky integrate-and-fire neuromimes with background activity used to simulate the effect of afferences that were not explicitly simulated within a network. The background activity to each neuron was set to 900 spikes/s with a low amplitude (1 mV ) generated by uncorrelated Poisson distributed inputs. In each Ubidule two sets of 20 excitatory units were randomly selected among the excitatory units corresponding to the "input" and "output" layers of the Ubidule. The neurons of these layers send and receive connections from the other units of both types (excitatory and inhibitory) within the network in addition to the connections with other Ubidules.

Our circuit topology remained fixed during all simulations and the Ubidules were characterized by their role in the network, i.e., sensory, processing, or motor (Fig. 1). In our network, the u1Sensory Ubidule has a pure sensory role. Ubidules labeled u3Process, u4Process, u5Process, u6Process have a pure information processing role and are characterized by having neither external inputs nor afferences from the motor Ubidule. They are all reciprocally interconnected and send efferent projections to u2Motor.

Electrochipograms

Our design of the bio-inspired artificial neural networks allowed us to implement realistic virtual electrodes to record neuro-mimetic signals, called Electrochipograms (EChG), characterized by dynamics and features similar to those recorded in living brain structures. In our implementation the virtual electrode measures the potentials over a certain 'area' of the 2D lattice neuronal network according to an appropriate weighted sum [START_REF] Shaposhnyk | A framework for simulation and analysis of dynamically organized distributed neural networks[END_REF]. The main parameters of the electode are its position over the neural network and its sensibility function. The tip of the virtual electrode was located in the middle of the 2D lattice of each Ubidule neural network. The sensibility function depends only on the distance between a given point of the lattice and the centre of the electrode field. According to this model, all neurons located at the same radial distance from the center of the electrode field make an equivalent contribution to the final electrode output and thus form an equi-potential layer [START_REF] Shaposhnyk | A framework for simulation and analysis of dynamically organized distributed neural networks[END_REF]. In this study, the sensibility radius was set equal to 9 with a linear decaying function.

The EChG was recorded with a 6 channels virtual electrode system with one channel per Ubidule during 350 trials. Each trial had a fixed duration and included two intervals: a stimulation interval followed by an inter-stimulus interval. The stimulation was generated by spatio-temporal external stimuli applied only to the input layer of u1Sensory lasting 128 (Type A) and 512 (Type B) time steps. The group of simulations with higher stimulation frequency (0.89 Hz) was called "Simulations A" and the group with lower stimulation frequency (0.67 Hz) was called "Simulations B". The extensive use of Fast Fourier Transform in our signal analysis imposed, for improved efficiency, sampling frequencies which are powers of two. In practice the time-steps of the simulator were selected for convenient time units, i.e., 1024 time steps corresponding to 1000 ms. The inter-stimulus interval was always equal to 1000 ms. The recording time was divided into four periods defined following the amount of time the Ubinet was exposed to the stimulation: (i) PRE-learning beginning at time zero and lasting 27 trials characterized by the absence of any external stimulation (i.e., only the background activity was present during the stimulation interval); (ii) EARLY-learning lasting 50 trials, between trials #28 and #77; (iii) LATE-learning lasting 50 trials, between trials #228 and #277; and (iv) POST-learning lasting 50 trials, between trials #278 and #327 again characterized by the absence of any external stimulation.

The signals recorded during the stimulation interval were averaged across several trials in order to compute evoked potentials (e.g., Fig. 2). The signals recorded during the inter-stimulus interval were used for frequency domain analyses that included power spectrum, bispectrum and bicoherence analyses.

Power Spectrum Analysis

Figure 3 shows the averaged evoked potentials for the "first" (u3P,u4P ) and the "second" (u5P,u6P ) processing layers and their corresponding Power Spectrum Densities (PSD). In the PSD several peaks could be observed around 10 Hz, 15 Hz and 25 Hz. The results obtained during the EARLY-learning stage were not significantly different from the PRE recording condition. This suggests that PSD is little affected by the stimulus structure and by the subsequent functional connectivity at the begin of the stimulation. This is probably due to the fact that stimulus-driven selective cell and synaptic pruning were not yet producing any effect. During the LATE period the PSDs were characterized by a generalized decrease in the power and the preservation of the peak near 10 Hz with a noticeable decrease of the other peaks. It is interesting to notice that in the POST-learning stage the multiple peaks tended to appear again, thus suggesting that they are mainly driven by the combined effect of background activity and internal features of the model. Another general observation is that in mature networks, i.e. during the LATE-and POST-learning phases in comparison with EARLY-and PRE-learning phases, PSD is getting lower, which means the total amount of energy transferred by the neural networks is decreasing. The POST-learning phase was characterized by 3.5 dB/Hz lower values of power than appropriate values during PRE-learning phases. This decrease is likely to be associated to the pruning of synpatic links and cell death.

Quadratic Phase Coupling

The bispectral analysis was performed for all channels separatedly and the values of phase-coupled frequencies (i.e., the frequencies of resonance f 3 ) were determined. Let us consider the distribution of all phase-coupled frequencies f 3 observed in single-channel and cross-channel analyses. Let us consider the frequency band ]1 -24] Hz for EChG and LF the relative number of f 3 falling into this low frequency range. Let us consider the frequency band ]60 -84] Hz and HF the relative number of f 3 falling into this high frequency range. The index of resonant frequencies IRF is defined in the range 0-100 as follows: IRF = 1 2 × 100 + HF -LF HF +LF × 100 . A value of IRF close to 100 corresponds to a shift of f 3 towards higher frequencies and value of IRF close to 0 corresponds to a shift of f 3 towards lower frequencies. IRF values close to 50 indicates the phase-coupling was equally distributed in low-and high-frequency bands. The raw frequency ratio is simply defined by RF R = LF HF . This means a large value of RF R corresponds to a shift of phase-coupling towards higher frequencies and a low value of RF R corresponds to a shift towards lower frequencies.

0 20
Figure 4 shows the distribution of f 3 in the range 1 to 100 Hz during all recording periods and for the two types of stimulus used in the Ubinet simulation. These histograms show a shift towards an increase in low-frequencies resonances during the LATE-learning phase, especially when compared with the distribution during the POST-learning, when the input stimulus was absent. The quantitative assessment of this analysis presented in Table 1 emphasizes the change in the value of IRF between EARLY-and LATE-learning phases. IRF ≈ 60 decreased to IRF ≈ 14 followed by an increase to the range 26-29 during the POSTlearning phase suggests that the shift towards low frequencies of phase-coupling was provoked by the learning protocol and not only due to the maturation of the network. The analysis of IRF and RF R shows also that in the POST-learning stage the resonant features remained affected by the functional connectivity that developed during the trials with external stimulation and the values were intermediate between PRE/EARLY-learning and LATE-learning phase.

Table 2 shows the relative count of phase-coupling in the frequency bands of interest and the values of indexes IRF and RF R for all recording periods in controls and patients suffering primary insomnia before and after treatment [START_REF] Perrig | Changes in quadratic phase coupling of eeg signals during wake and sleep in two chronic insomnia patients, before and after cognitive behavioral therapy[END_REF]. The frequency ranges of the bands refer to those generally used for human studies and are different from those used for studying the Ubinet activity. However, there is a linear correspondence between the two sets of frequency bands. The general pattern was a high level of high frequency coupling in the group of patients before treatment. The main effect of the treatment was to reduce highfrequency coupling and shift phase-coupling towards low frequencies, somehow with a significant increase of low frequency coupling compared to the controls. The treatment significantly increased the phase-coupling in the low frequency band during all other intervals, either re-establishing a level close to the controls or even beyond that level, as observed during the REM sleep phases.

Discussion

This paper described the implementation of a neuronal system simulator on a hybrid scalable multi-agent hardware platform based on the Ubidules framework [START_REF] Sanchez | Perplexus: Pervasive computing framework for modeling complex virtually-unbounded systems[END_REF] and its application to the study of information processing in hierarchically organized neural networks circuits. We have explored one simple Ubinet network circuit characterized by a sensory network processing the external input that projects to a hierarchically organized multilayered (in our case formed by only two layers) recurrent network of processing areas which eventually project on a motor network that generates an activity keen to be encoded into actuators.

The experimental approach to the Ubinet activity by recording the EChG was aimed to assess the effect of a repeated stimulation on the functional connectivity established between the Ubidules. Our PRE-learning stage could represent a control situation driven exclusively by the background activity of the subject's brain. The subject is naive to the coming stimulus so that a learning process can occur. During the EARLY-learning stage the repetition of the stimuli at regular intervals might initiate an unsupervised recognition process that eventually shaped the functional connectivity of feature detecting cell assemblies after selective synaptic and cell pruning. The third order spectral analysis of EChG and EEG allows to determine the frequency range of quadratic phase coupling (resonant frequency) across cortical areas [START_REF] Villa | Corticofugal modulation of functional connectivity within the auditory thalamus of rat[END_REF][START_REF] Villa | Non-linear cortico-cortical interactions modulated by cholinergic afferences from the rat basal forebrain[END_REF]. According to the usual interpretation based on standing waves theory, high resonant frequencies mean that information processing is transmitted at short distance (i.e., the distance between two nodes of the wave). A coupling that occurs at high frequencies may be interpreted as a sign of focal cortical interactions. Conversely, a coupling at low frequencies suggests an increased cross-areal involvement in neural processing.

A remarkable result is the finding that in the Ubinet simulations the LATElearning stages were characterized by IRF ≈ 14 compared with PRE-and EARLY-learning stages (IRF ≈ 43 -62). In the study with human Subjects we observed that controls and patients after treatment were characterized, during all sleep phases by values of IRF lower than insomniac patients before treatment. It is also worth reporting that the only condition that let appear a difference of resonant frequencies in the range ]13-33] Hz was during NREM sleep irrespective of the treatment. This last result suggests that despite an overall shift of resonant frequencies towards recovery, focal cortical interactions tended to persist in patients during NREM sleep periods. Both an appropriate stimulation of the Ubinet and the cognitive brain therapy appear to modify the ratio of resonant frequencies provoking a shift of the indexes towards low frequencies at all brain states. Our findings suggest that new tools provided by modular and scalable neural network simulators offer new opportunities to neurophysiologists and clinicians to test hypotheses based on the analysis of neural signals at mesoscopic levels.

2 Fig. 1 .

 21 Fig. 1. The Ubinet hierarchical circuit used in all simulations. Solid arrows depict connections and directions of information flow between the Ubidules.

Fig. 2 .

 2 Fig. 2. Evoked potentials averaged over 50 trials obtained from u1Sensory (blue solid trace) and from u4Process (green dotted trace) Ubidules during the EARLY-learning stage. The stimulus was applied during 256 time steps. The upper panel displays the raw evoked potentials and the lower panel shows the signals smoothed by a Blackmann smoothing window in order to emphasize the low frequency components.

Fig. 3 .

 3 Fig. 3. Evoked Potentials and Power Spectrum Densities for the averaged recordings of the pair of Ubidules in Layer 1 and in Layer 2. The left panels correspond to stimulus Type A and the right panels to stimulus Type B. The gray stripes correspond to the periods of stimulation. From top to bottom the results referred to the PRE-learning, EARLY-learning, LATE-learning and POST-learning periods.

Fig. 4 .

 4 Fig. 4. Relative distribution of the frequencies of resonance for each period for Simulations A and B. Bin size corresponds to 2 Hz intervals. The dotted lines delineate the limits of LF and HF bands.

Table 1 .

 1 Percentage of phase-coupled frequencies in each frequency bands of interest for the stimulus Type A and B within neural network development stages. IRF: index of resonant frequencies. RFR: raw frequency ratio.

	Learning	Percentage of phase-coupled frequencies	Indexes
	Phase	LF: ] 1-24]Hz	]24-60]Hz	HF: ]60-84]Hz	IRF	RFR
	Stimulus Type A
	PRE	27	53	20	43	1.34
	EARLY	20	50	30	60	0.66
	LATE	38	56	6	13	6.67
	POST	38	49	13	26	2.83
	Stimulus Type B
	PRE	20	48	32	62	0.62
	EARLY	21	47	31	60	0.68
	LATE	49	43	8	14	6.00
	POST	44	38	18	29	2.43

Table 2 .

 2 Percentage of phase-coupled frequencies in each frequency bands of interest for the the control group and for the group of patients before and after treatment. REM: rapid eye movement sleep. NREM: rapid eye movement sleep.

	Subject Group	Percentage of phase-coupled frequencies		Indexes
		LF: ] 1-13]Hz ]13-33]Hz	HF: ]33-48]Hz	IRF RFR
	Eyes Closed
	Control	12	74	14	54	1.17
	Patient before	2	77	21	91	10.50
	after treatment 8	88	4	33	0.50
	NREM
	Control	57	30	13	19	0.23
	Patient before	27	60	13	33	0.48
	after treatment 42	57	1	2	0.02
	REM
	Control	4	90	5	56	1.25
	Patient before	4	85	12	75	3.00
	after treatment 19	79	2	10	0.11

Acknowledgments. The authors ackowledge the support by the European Union FP6 grant #034632 (perplexus) and the contributions of J. Iglesias,

Victor Contreras-Lámus for the simulations of O. Brousse, Th. Gil, G. Sassatelli, F. Grize for the JADE integration and of K. Espa-Cervena for the analysis of the clinical data.


C Krzeminski
email: christophe.krzeminski@isen.fr

Stress mapping in strain-engineered silicon pMOSFET device using process simulation

Keywords: numbers: 82.20.Wt, 85.40.Bh, 83.85.St

Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments

Christophe Krzeminski

I. INTRODUCTION

For CMOS devices downscaling, sharp requirements have been defined by the International Technology Roadmap for Semiconductors (ITRS) in terms of drive current, off state current, power density, making the geometric scaling a challenging task [START_REF]The International Technology Roadmap for Semiconductors[END_REF] . The new vector adopted to extend the Moore's law is the channel mobility enhancement through the introduction of stress in the channel [START_REF] Mohta | Mobility enhancement: The next vector to extend moore's law[END_REF] . Different method of stress engineering have been introduced to boost the electrical performance of the logic devices. Intense research work has been devoted in the last decade to increase the channel mobility by biaxial layer but it has been observed to be difficult to implement for technical and cost issues. Local mechanical stress control [START_REF] Shimizu | Local mechanical-stress control (lmc): a new technique for cmos-performance enhancement[END_REF] and uniaxial stress are on the fundamental point of view more favourable on the band structure engineering and the resulting mobility enhancement [START_REF] Thompson | Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed si and ge channel mosfets[END_REF] and easier to implement on the technological point of view [START_REF] Mistry | Delaying forever: Uniaxial strained silicon transistors in a 90nm cmos technology[END_REF] .

Several technological stress-transfer techniques have been developed in order to introduce such uniaxial stress in the channel device. First, embedded SiGe stressors (eSiGe) in the source/drain regions have been proposed to induce a compressive stress in the pMOS channel [START_REF] Ghani | a 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon cmos transistors[END_REF][START_REF] Thompson | A 90nm logic technology featuring strained-silicon[END_REF][START_REF] Bai | A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 cu interconnect layers, low-k ild and 0.57 mu;m2 sram cell. Electron Devices Meeting[END_REF][START_REF] Ouyang | Investigation of cmos devices with embedded sige source/drain on hybrid orientation substrates[END_REF][12] . The filling of the source/drain by a SiGe material with a lattice spacing larger than silicon leads to a large compressive stress in the channel and drive current improvement [START_REF] Chidambaram | Fundamentals of silicon material properties for successful exploitation of strain engineering in modern cmos manufacturing[END_REF] . Next, an another technique is the deposition of a stress material on top of the gate stack after silicide formation. If one single liner is used, the electrical performance of the opposite type of device will be degraded. With the possibility to engineer compressive or tensile stress depending on the process conditions with nitride film [START_REF] Ito | Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design[END_REF] , successful integration of dual Contact Etch Stop Liner (CESL) have been reported [START_REF] Pidin | A novel strain enhanced cmos architecture using selectively deposited high tensile and high compressive silicon nitride films[END_REF] . Uniaxial strain boosters have been widely adopted in order to increase the performance of logic device for the 90nm [START_REF] Ghani | a 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon cmos transistors[END_REF] down to 45nm technology nodes [START_REF] Yang | Dual stress liner for high performance sub-45nm gate length soi cmos manufacturing[END_REF] . Some studies focuses on the optimisation of these different techniques in order to enhance the stress level generated and also on the integration with the main aim to cumulate the effect of different stressor 12 . Research activities are also dedicated to enhance the stress level generated by these different uniaxial stress techniques. Despite these large technological progress, many challenges are faced by the uniaxial stress engineering approach for 32nm technology nodes and below in terms of scalability since the stress coupling effect between the gate pitch and the various stressors like eSiGe and CESL is expected to be smaller for decreasing nodes [START_REF] Sleight | Challenges and opportunities for high performance 32 nm cmos technology[END_REF] . Next the yield is also concerned with the integration of multiple sources of local and global stress in such a way that the channel mobility is enhanced without exceeding the local critical shear where defects appears. Finally, circuit design is also pitch-and layout-dependent effects must be taken into account as the device geometries shrink and strain distribution should be investigated on a larger scale.

Therefore, intense research work have been dedicated the last few years to develop or improve ex-situ or in-situ characterisation techniques in order to quantify the strain introduced in nanoelectronics device. MicroRaman Spectroscopy (µ-RS) [START_REF] Senez | Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and microraman spectroscopy[END_REF] and Coherent Beam Electron Diffraction (CBED) [START_REF] Zhang | Direct strain measurement in a 65 nm node strained silicon transistor by convergent-beam electron diffraction[END_REF] analysis are the most often usual characterisation technique [START_REF] Mayuzumi | High-performance metal/high-k nand p-mosfets with top-cut dual stress liners using gate-last damascene process on (100) substrates. Electron Devices[END_REF] .

However with these two techniques, the stress field can only be investigated in a few points of the structure. Significant progress have been achieved with the development of the Geometric Phase Analysis (GPA) technique [START_REF] Hÿtch | Nanoscale holographic interferometry for strain measurements in electronic devices[END_REF] which enable a more complete two dimensional mapping of strain field component in silicon crystalline on relatively large scale ∼ µm with a resolution of a few nanometers. On the other side, a direct confrontation between CBED and GPA analysis using High-Angle Annular-Dark-Field Scanning Transmission Electron Microscopy (HAADF STEM) shows that the difference in absolute strain measured could exceed 300 MPa [START_REF] Diercks | Comparison of convergent beam electron diffraction and geometric phase analysis for strain measurement in a strained silicon device[END_REF] . In the present case, the difficulty to define a strain reference relative to the unstress level is probably the main source of discrepancy. An other study also stress the influence of sampling preparations in stress evaluation [START_REF] Cooper | Strain mapping for the semiconductor industry by dark-field electron holography and nanobeam electron diffraction with nm resolution[END_REF] . Even if these remarkable experimental achievements clearly improve the understanding on how stress is generated and distributed in the silicon channel of the nanodevice, some limitations are faced.

In order to address these challenges associated to downscaling, process simulation and TCAD tools have probably a significant and complementary role to play in order to provide guidelines for process optimisation. In comparison to dopant diffusion modelling [START_REF] Pichler | Intrinsic Point Defects, Impurities, and Their Diffusion in Silicon[END_REF] , very few studies have been dedicated to the stress simulation. The modelling of the stress by TCAD tools was introduced in the 90's in order to estimate the stress generated by silicon oxidation in the case of LOCOS (LOCal Oxidation of Silicon) and next STI (Shallow Trench Isolation) fabrication. The aim was to make predictive simulations in order to provide guidelines for the stress minimisation generated by various process steps such as oxidation, nitride deposition, densification, implantation, silicidation [START_REF] Hoffman | Multidimensional Modeling and Simulation of Mechanical Stresses in Advanced Silicon Technlogies[END_REF][START_REF] Senez | Investigations of stress sensitivity of 0.12 cmos technology using process modeling[END_REF] and also to minimize defects formation. As discussed previously, the philosophy has radically changed as stress engineering is now the principal technology booster to improve electrical device performance for logic nanodevice. This approach impacts largely process simulation tools as it is critical to evaluate layout dependent stress variations and to take into account the influence on the design information flow [START_REF] Bork | Trends, demands and challenges in tcad[END_REF] . Some recent research work have been undertaken for the simulation of the stress field generated by these technological booster. Different strained-silicon options have been analysed with simple stress simulations [START_REF] Moroz | Analyzing strained-silicon options for stressengineering transistors[END_REF] . The amount of stress generated in the channel by eSiGe stressor has been estimated [START_REF] Cea | Front end stress modeling for advanced logic technologies[END_REF][START_REF] Yeo | Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions[END_REF] . Eneman et al. also investigate the scalability of eSiGe stressor [START_REF] Eneman | Layout impact on the performance of a locally strained pmosfet[END_REF][START_REF] Eneman | Scalability of the si/sub 1-x/ge/sub x/ source/drain technology for the 45-nm technology node and beyond[END_REF] . Stress transfer has been found to be highly dependent on downscaling and to decrease with the dimension of the active area. However, some questions remain open concerning the predictivity of these results. For example, in the case of the stress field generated by CESL, Loiko et al. [START_REF] Loiko | Multi-layer model for stressor film deposition[END_REF] criticises the method often used for the modelling of the stress introduced by the deposition step. Orain et al. [START_REF] Orain | Method for managing the stress due to the strained nitride capping layer in mos transistors[END_REF] perform a complete 3D mechanical simulation study using a pseudo-3D structure in order to investigate the complex mechanisms responsible of the stress transfer for CESL. The main objective of this work is first to investigate the stress field generated for several front-end key step and next to evaluate the stress mapping for a stress-engineered pMOSFET.

In this study, the paper is organised as follow : in the first section, the stress modelling and the rheological parameters used are briefly presented. The stress distribution for eSiGe and CESL stress booster on simple test structures are simulated and confront to available experimental characterisation. Finally, a simplified complete process flow matching as far as possible, a realistic one is performed in order to estimate the stress mapping generated in such nanoscale stress engineered MOSFET device.

II. METHODOLOGY A. Stress modelling

Various sources of mechanical stress can be modelled using a process simulator such as i) the intrinsic stress generated by deposition step ii) the etching or material removal iii) the growth iv) the thermal stress and finally the stress generated by material structuring. All these different steps modify the stress equilibrium of the structure and the forces balance. A macroscopic modelling of the mechanical deformation associated with these process. With the knowledge of the initial mechanical state and the modelling of the stress generated by the different step, the stress distribution σ can be estimated thanks to the following equation :

{σ} = [D]({ǫ} -{ǫ 0 }) + {σ 0 }
where [D] is the elasticity matrix, {ǫ} is the effective strain tensor representing the various stress components in the device structure and {ǫ 0 } (resp. σ 0 ) the sources of initial deformation (resp. stress).

In order to calculate the evolution of this equation during the simulation of a front-end process flow, a Finite Element (FE) based method is usually used. Bi-dimensional finite element based simulations have been perform using the Sentaurus Process simulator in the Z-2007.03 release [START_REF]Synopsys tcad tools: Sprocess user's manuals[END_REF] . A specific set of mechanical parameters has been used as described in the next section. All the plane strain simulations performed in this study have been done assuming free boundary conditions and an initial stress-free state for the structure.

B. Rheological parameters

A large number of materials are used in front-end processing with a large number of complex of rheological behaviour. For example, silicon is considered in all the studies as an anisotropic elastic material with Young's modulus equals to 131 GPa along [100], 169 GPa [110] and 187 GPa [111] with a thermal expansion coefficient given by the following relationship as function of the temperature T (in Kelvin) : α(T) = 3.05 + 1.24 • 10 -03 T.

The deformation generated by the thermal expansion can often be described by a simple elastic rheologicial behaviour. On the other side, amorphous material like SiO 2 or Si 3 N 4 exhibit a viscoelastic behaviour. A common set of mechanical parameters are used for the description of the rheological behaviour of the different materials. This database describing the rheological behaviour is the result of Brillouin Light Scattering or beam bending experiment from literature [START_REF] Hoffman | Multidimensional Modeling and Simulation of Mechanical Stresses in Advanced Silicon Technlogies[END_REF] . Table I summarises the various mechanical parameters used in the study.

III. RESULTS

The main objective of this section is to estimate the stress distribution generated by the two main front-end process steps : embedded SiGe stressor (eSiGe) and Contact Etch Stop Liner (CESL) separately.

A. Simulation of eSiGe stress distribution

The epitaxy of this SiGe layer is known to generate a lattice stress mismatch at the silicon interface since the lattice parameter of the Si 1-x Ge x alloy has a larger lattice parameter a Si (1-x) Ge (x) = xa Ge + (1x)a SiGe according to Vegard's law. This biaxial strain generated can be estimated thanks to the following relation : As point out in an other study, the correspondence and the modelling between the strain induced by frequency shift and the stress field in non-uniformly strained layer is not straightforward [START_REF] Jain | Raman spectra of ge 0.11 si 0.89 quantum wires[END_REF] .

ǫ 0 = xa Ge + (1 -x)a Si a Si (

Stress distribution and Dark Field Electron Holographic

Fig. 3 presents the periodic structure with Si 0.8 Ge 0.2 sources/drains and a simplified gate stack matching the experimental one of reference [START_REF] Hÿtch | Nanoscale holographic interferometry for strain measurements in electronic devices[END_REF] . The main objective of this subsection is to confront the map predicted by simulation and those obtained by the Dark Field Electron Holographic technique. The lateral and vertical two dimensional stress map are reported in the figure 3. Despite various approximations, these stress maps can be compare to the geometric phase variations obtained by Hÿtch et al. [START_REF] Hÿtch | Nanoscale holographic interferometry for strain measurements in electronic devices[END_REF] . Concerning the variation of the lateral strain predicted by simulation, a close agreement has been obtained as shown in figure 4.

The average lateral variation of ǫ xx over 60nm in the silicon part can be directly compard to those predicted by the process simulator. Near the gate oxide, the maximum lateral compressive strain is -1.34 % compared to -1.4 % estimated by the GPA technique.

Strain, CBED and GPA distribution

In a recent work, a comparison between CBED and GPA measurements on Si 0.82 Ge 0.18

stressors have been performed by Diercks et al. [START_REF] Diercks | Comparison of convergent beam electron diffraction and geometric phase analysis for strain measurement in a strained silicon device[END_REF] . The differences between the two mea-surements methods are illustrated in Fig. 5. For the lateral strain, the agreement between the FEM simulations and CBED measurements could be emphasised whereas GPA gives a higher stress level of about one third. For the vertical strain, a nice agreement is also observed for distance below 50nm. It could noticed that the stress relaxation towards a free stress state for the domain where only GPA measurements are available is also well described.

B. Simulation of CESL stress distribution

As previously discussed, the Contact Etch Stop Liner technique (CESL) has been intensively integrated as a low cost technique to introduce strain for both pMOSFET and nMOSFET device. The modelling of the stress field generated by compressive stress liner for a pMOSFET device is undertaken. For such purpose, an intrinsic stress component σ int is introduced in the process simulator in order to modelize the stress distribution generated by the stress liner deposition. The deformation introduced to take into account the intrinsic stress is given by the following equation:

ǫ 0 = 1 -ν E σ int (2)
A simple device test structure with a polysilicon gate (width 50nm) and a nitride spacer (width 7nm) has been considered. A 50nm nitride stress liner with a 1.5 GPa intrinsic compressive stress has been introduced on top of the structure. As pointed out by Loiko et al. [START_REF] Loiko | Multi-layer model for stressor film deposition[END_REF] with refined structural mechanical simulations, the method used for the deposition step modelling is important for the quality of the resulting stress field. A multi-step deposition operation is considered using five elementary steps where for each one 10nm is deposited.

Fig. 6 reports the stress mapping in the structure for the different stress components σ xx , σ yy .

Using this particular approach, a non uniform stress field is created in the CESL particularly in the gate stack region a shown by the figure 6. A larger tensile stress is generated around the polysilicon gate as the stress level reaches 600 MPa. As pointed out by Orain et al. [START_REF] Orain | Method for managing the stress due to the strained nitride capping layer in mos transistors[END_REF] the lateral part of the CESL in mechanical interaction with the silicon has a direct influence on the stress generated in the channel. Therefore, the channel is directly impacted as the stress generated in the channel is much more important and a lateral compressive stress of 590 MPa just below the gate oxide is observed. The vertical stress generated in the channel is much lower, around 260 MPa just under the gate, whereas a large compressive peak for the shear stress of 560 MPa is observed near the nitride spacer. MPa. The standard thermal budget and the intrinsic stress for PECVD nitride is used for the gate stack. A particular attention is made on the modelling of the etching step in order to match as fine as possible the shape of the source/drain recess regions. A similar approach to section III A is followed for the modelling of the SiGe epitaxy. As no reliable silicidation step modelling is available, a deposition of NiSi is used considering an intrinsic stress of 800

IV. STRESS MODELLING OF ESIGE/CESL

MPa to take into account the tensile stress generated during the temperature ramp down.

Standard thermal budget are used for the various deposition step and an annealing at 1030 • C is considered for the junction activation step 12 . Finally, the method used in section III B for the modelling of CESL is also adopted. As clearly shown here, all the previous work on simple test structures in order to evaluate the stress field by each uniaxial stress technique is beneficial.

B. Results

Fig. 7 reports the evolution from the top to the bottom of respectively σ xx , σ xy and σ yy component for eSi 0.75 Ge 0.25 stressor and a 1.5 GPa compressive stress liner which is expected to exhibit the maximum stress in the channel. A large compressive lateral and vertical tensile stress confined by the two embedded SiGe stressors in the silicon channel is observed. For the shear stress σ xy , large peaks of about 600 MPa are observed at the convex corner of the eSi 0.8 Ge 0.2 stressors and at the extremity of the gate stack spacer. Table II presents the variation of the σ xx and σ yy components for various experimental conditions.

The parasitic stress level in the absence of intentional stressors has been estimated as well other then MPa but might be subject to large errors given the numerous assumption. The impact of the different stressors combination is however clearly emphasise. In the case where a 15% Ge content SiGe stressor is integrated, a lateral stress of 460 MPa is observed 10nm just under the gate oxide. The stress level is higher compared to the previous results of section III A 1 observed in µ-RS experiment as the silicon channel width of the device about 30nm is much smaller here. As shown previously, an increase of the Ge concentration is clearly beneficial, as the lateral stress is estimated to be increased by a factor 1.7 to reach 720 MPa. A 1.5 GPa compressive stress liner is also observed to increase the stress peak of 650 MPa in the silicon channel. The maximum lateral stress of 920 MPa is obtained in the case of a 25 % Ge concentration with a 1.5 GPa CESL. The same behaviour can be observed for the other component σ yy . Whereas a tensile component is created for σ yy , the same conclusions apply as function of the stress liner combination. It could be noticed that the additive effect of the different stressors are relatively well described by simulation and the stress enhancement could be correlated with the increase of the drive current observed experimentally 12 . The hole mobility enhancement ∆µ µ is often assumed [START_REF] Chung | Practical and reproducible mapping of strains in si devices using geometric phase analysis of annular dark-field images from scanning transmission electron microscopy[END_REF] to be linearly dependent on the piezoresistance coefficients by the following equation:

∆µ µ ≈ |π σ xx + π ⊥ (σ yy + σ zz )| (3)
where π = 718 × 10 -12 Pa -1 and π ⊥ = -663 × 10 -12 Pa -1 . Using the maximum strain level predicted in the experimental split (σ xx = -920 MPa and σ yy = 610 MPa) predicted would lead to a theoretical 106 % increase of the hole mobility at the top center of the gate oxide. However, it has been clearly shown by the stress mapping that it decreases rapidly far from the gate oxide in the silicon channel which could explain reasonably that the total drive current is not enhanced to the same level.

V. CONCLUSION

Given the complexity, the cost and the various experimental limitations to estimate the stress field in the silicon channel by using only experimental technique, process simulation is a complementary interesting approach. In the case of eSiGe embedded stressors, the simulation and the confrontation to three different experimental configurations and various experimental characterisation have been undertaken. Despite some limitations in the approach due to the plane strain approximations for two dimensional FEM simulations, a relatively good agreement is obtained for the stress estimated by the different characterisation technique. Some significative difference are observed in the case of µ-RS measurements but the peak deconvolution by the Pinardi's approach is a complex task and an relative issue. A nice agreement for CBED and GPA has been obtained with the FEM simulations.

Basically for simple stress technology booster like eSiGe stressor or CESL, first order stress modelling based on the introduction of an intrinsic or lattice mismatch stress can provide some insight about the level and the distribution of the stress field generated in the silicon channel after the different processing steps. The possibility to describe additive effects of intentional and parasitic stress sources for a pMOSFET device with several stress sources have been underlined. A link can be made between the enhancement of the drive current observed experimentally and the increase in term of stress level in the channel predicted by process simulation. It shows the interest for process simulation combined with experimental characterisation to investigate the stress map in the channel device. However, some limitations have been also be discussed on the way to model the deposition step for stress liners and on the influence of the silicidation step on the global stress field. This step has been observed to decrease significantly the level of stress generated by eSiGe stressor [START_REF] Cooper | Strain mapping for the semiconductor industry by dark-field electron holography and nanobeam electron diffraction with nm resolution[END_REF]

  1) as a function of the Germanium concentration x. This biaxial strain generates in reaction large forces in the silicon substrate. In order to estimate these two dimensional stress distribution, different test structures have been considered matching as far as possible several experimental study of the literature 21,36 . First, silicon pads stressed by SiGe thin layer and characterised by Microraman technique and next a comb structure by the Dark Field Holographic technique. 1. Stress distribution and Microraman characterisation Planar structures made of Si/SiO 2 /Si 3 N 4 pads of Nouri et al. 36 has been simulated with surrounding trenches where a SiGe layer is deposited. Fig. 1 shows that the experimental configuration where large enough to allow Microraman characterisation and to estimate the stress level near the silicon surface. Fig 2 shows that the experimental variation of the mean lateral stress is strongly influenced by the topological parameters such as the silicon width or the etch depth on the magnitude of the compressive stress in the silicon part. Fig. 2 also provides the lateral stress distribution for this large structure of 36 µm width considering a 20% Ge concentration for the SiGe stressor. The silicon etch depth for this simulation 150nm. Standard intrinsic stress of table I are being considered for SiO 2 and Si 3 N 4 . The lateral stress distribution σ xx is of particular relevance. For the largest silicon pad 5µm, asmall lateral compressive stress is generated at the corner whereas a compressive maximum located at the middle of each silicon pad is created. This stress increases with decreasing line-width to reach a 280 MPa stress for the smallest one in agreement with the stress level extracted from Raman measurements. The situation is completely different just under the SiGe stressor as a tensile stress is generated in the silicon with the larger lattice parameter of SiGe. Using the approach of Pinardi et al.[START_REF] Pinardi | A method to interpret micro-raman experiments made to measure nonuniform stresses: Application to local oxidation of silicon structures[END_REF] , the Raman spectra has been estimated by calculating the secular equation using the component of the previous stress tensors. The FE simulation is able to reproduce the variation in term of frequency shift induced by the different SiGe stressors in the silicon part. However, some significative differences can be easily observed in term of magnitude of the frequency shift and the width of the different peak.

  PMOS DEVICE A. Modelling aspectIn order to simulate the final stress field resulting of the integration of several stress liners, a simplified process flow has been considered. This subsection describes the various assumptions used for the modelling of the stress field generated by the addition of several uniaxial source of stress for pMOSFET. The experimental split is based on different eSiGe stressors and on the use of CESL as shown in table II matching the experimental work of Verheyen et al.12 . In this work, a significant improvement of the drive current was observed as function of the different stressors. The stress generated by the STI formation is approximated by the introduction of a 140 MPa residual stress to match the stress field obtained after the densification step of the deposited chemical oxide. The stress generated by the thin oxide gate and the high-κ (HfO 2 ) is obtained by an intrinsic isotropic compressive stress of 400

Fig. 2

 2 Fig.2The top figure presents the lateral stress distribution estimated in the structure.A Si 0.8 Ge 0.2 layer of 150nm is considered corresponding to the maximum stress level possible

Fig. 3 Fig. 4

 34 Fig. 3 Respectively lateral (top figure) and vertical (bottom) stress distribution estimated by process simulation in the structure matching those used by Hÿtch et al. 21 for the Dark Field Electron Holographic technique. In relative agreement with the experimental result, the maximum lateral strain ǫ xx near the oxide gate predicted by FEM simulations is -1.34 % corresponding to a lateral stress σ xx of 1.3 GPa.Fig. 4 Comparison between the mean lateral cross section of the ǫ xx component reported by Hÿtch et al. 21 and the results of FEM simulations also averaged on several depth over 60nm. The lateral strain variations along the structure are relatively well described by process simulation.

Fig. 5

 5 Fig. 5 Comparison between the lateral and vertical strain distribution of Diercks et al. using CBED and GPA and FEM simulations. The strain relaxation as function of the distance from the base of the gate oxide is well described and in nice agreement with CBED experiments with a maximum error less than 15 %.

Fig. 6 Fig. 7

 67 Fig. 6 Lateral and vertical stress distribution generated by a 1.5 GPa intrinsic compressive stress liner. The interaction between the CESL nitride layer and the gate generate mostly an uniaxial stress in the channel Fig. 7 This figure presents respectively (from the top to the bottom) the σ xx , σ xy and σ yy stress distribution generated by the various stress sources. The reference roughly estimates the parasitic stress that should originate from undesired sources such as STI and silicidation.The interaction between the CESL nitride layer and the gate increases the uniaxial stress generated by the eSiGe stressors in the channel.

TABLE I .

 I . Many new and complex uniaxial stress techniques are under optimisation in the stress engineering approach. Such complex techniques like stress memorisation 40 are very difficult to modelise even empirically and are interesting challenges for future research work. contribution to the project PULLNANO under contract n • IST-026828 from the Information Society Technologies Programme (IST). Mechanical parameters and rheological behaviour of the different materials considered.E correspond to an elastic material whereas VE to a viscoelastic behaviour.

	Material	Equip	Young Poisson α Intrinsic Rheolo
		-ment Modulus Ratio	Stress -gical
			[GPa]		[MPa]
	SiO 2	Thermal	66	0.17 0.5	-400	VE
		HDP	80	0.2	0.5	0	VE
		TEOS	60	0.25 0.6	0	VE
	Si 3 N 4	PECVD	143	0.28 3.0	-150	VE
		LPCVD	290	0.28 3.0 1200	VE
	PolySi	LPCVD	180	0.27 3.05 -350	E
	TiN	Sputtering	410	0.3	9.6 N/A	E
	NiSi	Thermal	112	0.3	9.5		VE
		Split	σ xx	σ yy	ǫ xx	ǫ yy ∆I on
			(MPa) (MPa)	(%)	(%) (%)
	Reference	∼ -50 ∼ -30 ∼ -0.01 ∼ -0.01 -
	eSi 0.85 Ge 0.15	-460	150 -0.29	0.21 20 %
	eSi 0.75 Ge 0.25	-720	320 -0.50	0.35 40 %
	CESL	-210	260 -0.18	0.23 30 %
	eSi 0.85 Ge 0.15 & CESL	-650	460 -0.48	0.46 50 %
	eSi 0.75 Ge 0.25 & CESL	-920	610 -0.68	0.63 65 %

TABLE II .

 II Various technological stress sources and stress component observed at the top center of the silicon channel 10nm just below the gate oxide. The last column reports the experimental increase in terms of drive current observed experimentally 12 . Experimental structure of Nouri et al. where each Si/SiO 2 /Si 3 N 4 pad is separated by a SiGe layer. Each layer has a length of 5µm and a variable depth between 30-150 nm.

	CAPTIONS
	Fig. 1

ACKNOWLEDGMENTS

The author is grateful to Jean-Michel Droulez for his regular support on information technology aspect. This work has been supported in part by the European Commission as a