Hewlett-Packard Hp

Hrs

Kevin J M Martin
email: kevin.martin@univ-ubs.fr

Mostafa ; Rizk
email: mostafa.rizk@imt-atlantique.fr

Martha Johanna Sepulveda
email: johanna.sepulveda@tum.de

Jean-Philippe P ; Diguet
email: jean-philippe.diguet@univ-ubs.fr

Khaled Alhaj
email: khaled.alhaj-ali@imt-atlantique.fr

Amer ; Baghdadi
email: amer.baghdadi@imt-atlantique.fr

Jalal " Jomaah
email: jomaah@enserg.fr

K ; Ali

K A ; Ali

Mrl Crossbar

rd Generation Partnership Project 5G 5 th Generation Mobile Networks ACT Approximate Computing Technique

Keywords: Artificial Intelligence AIS Automatic Identification System ALU, Arithmetic Logic Unit ALTD, Average-link Token Delay APTD, Average-path Token Delay ASIC Application-Specific Integrated Circuit ASIP Inertial Sensors ISA Instruction NoC based architecture, data-flow, memory NoC, Heterogeneous MPSoC, Run-time remapping, Dataflow actor, Move-based algorithm CMOS, crossbar, full adder, logic design, memristor

My research topics are mainly focused on the hardware/software co-design. My

In the first theme, the No-Instruction-Set-Computer (NISC) design methodology is explored to design dedicated modules of turbo receiver. Two NISC-based architectures are demonstrated. The obtained results in terms of performance and implementation area confirm the feasibility of adopting NISC concept in designing flexible yet efficient applicationspecific processors in the domain of digital communications.

In the second theme, the novel Notifying Memories (NM) concept is introduced to eliminate useless accesses to memories. Memories are transferred into masters that notify processors when the data is ready to be processes. The use of the NM concept leads to significant reductions in latency, injection rate, transported flits and switch conflicts. Also, the throughput is highly enhanced while saving power. In addition, a novel remapping algorithm and network-on-chip (NoC)-based architecture design are proposed to cope with the dynamicity of dataflow actors.

In the third theme, memristive devices are adopted to enhance the computing performance. First, memory-based computing on NoC architecture is introduced by making use of emergent non-volatile memories with power-gating capabilities to enhance the performance and attain low power consumption. In addition, the use of memristors to design architectures which combine flexibility and efficiency, has been explored and introduced through the proposal of original architectures that break the limits of the existing ones. The exploration and study have been conducted in three main levels: (1) interconnect level, (2) processing level and (3) memory level.

The fourth theme focuses on the design and implementation of efficient machine learning algorithms targeting the tactile sensing application. In particular, approximate computing techniques and designing of custom hardware accelerators are adopted to reduce the computational complexity and achieve higher performance with low power consumption.

Current research activities focus on embedded computer vision (CV) and artificial intelligence (AI) with the goal of achieving efficient implementations on edge devices with low computational resources and low power budget. The application domains are real-time drone navigation, marine object detection using deep learning and multi-view object detection. Re-xix sults achieved so far are novel and very encouraging.

Concerning the research perspectives, in the short and medium term, several perspectives are proposed: interactive machine learning on edge devices for object detection application, distributed learning on connected devices and tiny machine learning. In the longer term, it is planned to focus on building memory centric low-power processor.

Résumé long

Ce xxiii Mes activités de recherche actuelles se concentrent sur la vision par ordinateur et l'intelligence artificielle embarquées dans le but de réaliser des implémentations efficaces sur des dispositifs embarqués avec de faibles ressources de calcul et un faible budget énergétique.

Les domaines d'application concernent la navigation de drones en temps réel, la détection d'objets marins par apprentissage profond et la détection d'objets avec multi-vues. Les résultats obtenus jusqu'à présent sont originaux et très encourageants.

En ce qui concerne les perspectives de recherche, à court et à moyen terme, plusieurs pistes sont proposées : l'apprentissage automatique interactif sur les dispositifs embarqués pour les applications de détection d'objets, l'apprentissage distribué sur dispositifs connectés et l'apprentissage machine embarqué (TinyML). À plus long terme, il est prévu d'explorer la construction de processeurs basse consommation centrés sur la mémoire.

Preface

This document represents my Habilitation thesis manuscript. It summarizes my academic and professional career including recent and future research activities. It is organized as follows:

The first part includes my detailed Curriculum Vitae. It includes 3 chapters. Chapter 1 presents my personal resume. Chapter 2 and Chapter 3 provide my research and teaching experiences respectively.

The second part gives a high level view on my previous research activities. It includes 4 chapters:

• Chapter 4 presents the first research topic related to the proposal of flexible and efficient architectures for applications in digital communication.

• Chapter 5 presents the second research topic related to efficient algorithms and architectures for dataflow applications.

• Chapter 6 presents the third research topic that tackles the use of memristive devices in realizing efficient hardware architectures.

• Chapter 7 presents the fourth research topic about designing efficient hardware architectures for machine learning algorithms.

The third part provides a brief review of current research work (Chapter 8) and long-term future work (Chapter 9).

Part I Detailed Curriculum Vitae

and the team specialized in Algorithm Architecture Interactions (2AI) in collaboration with research laboratories in Lebanon.

The performed research work has focused on the hardware/software co-design for embedded architectures, circuits and systems. It stands at the crossing point between development and refinement of algorithms and designing digital embedded architectures. My conducted research has been supported in several projects and has been valorized through a number of publications in well reputable journals and through international and national conferences.

Since I defended my PhD in the end of 2014, which addressed the topic of designing novel flexible and efficient implementations for applications in the domain of digital communication, I have been doing research consistently in the domain of embedded systems targeting the realization of flexible and efficient architectures with reduced power implementations in multitude application domains. My research work has tackled emergent topics such as smart memory architectures, memory-based computing and in-memory computing. An important work has been done to investigate adopting novel non-volatile memory technologies and memristive devices to achieve flexible architectures with reduced power consumption. My research work has addressed the design and implementation of novel hardware architectures for applications in the fields of data-flow, embedded machine learning, embedded vision, and embedded intelligence aiming to attain the emergent flexibility requirement, and the ever increasing requirements of enhanced performance and reduced power consumption. The performed work has targeted the elaboration of new algorithms and hardware architectures in these fields.

During the last seven years , I have been involved in a number of research projects. I participated in the supervision of two successfully defended Ph.D theses. I was the direct tutor for several Master theses and undergraduate projects. Also, I served as member in several evaluation committees and participated in a number of theses juries.

My teaching activities lay in the domains of electronics, computer and communication engineering and informatics for undergraduate and graduate levels.

Research Collaboration

The following list enumerates the institutes where I share research activities:

• CROSSING -IRL 2010, Australia

• University of Genoa, Italy

• Université Bretagne Sud, France

• Tohoku University, Japan

• American University of Culture and Education, Lebanon

• American University of Beirut, Lebanon

• Lebanese University, Lebanon

• Lebanese International University, Lebanon

Involvement in Research Projects

I participated in the following research projects:

1. Mobile and wireless communications Enablers for Twenty-twenty Information Society (METIS):

• Goal: aims to lay the foundation of 5G, the next generation mobile and wireless communications system

• Funding: co-funded by the European Commission as an Integrated Project under the Seventh Framework Program for research and development (FP7)

• My Role: PhD student 2. Design Oriented Model of Computation for Embedded and Adaptive Multiprocessor (COMPA):

• Goal: aims to propose generic models for adaptive multi-processors embedded systems • Goal: aims to offer a new optoelectronic system that can detect a maritime security problem as early as possible while costing less than a radar tool

• Partners: conducted as collaboration between Lab STICC (IMT Atlantique and UBS) and two French Companies: Exavision and Inpixal

• Funding: funded by Bretagne region, France

• My Role: Post-doc Researcher 5. Deployment of electro-optical sensors and drones for living human detection and localization in search and rescue missions

• Goal: aims to demonstrate a novel low-cost solution that makes use of the availability and the affordability of drones to enhance detecting and locating wounded and lost individuals during and after disasters.

• Funding: funded by the Lebanese University

• My Role: Project technical leader

Publications

The results of my research activities led to the following publications: Further information about the publications is detailed in Appendix A.

Supervision and Tutorship

I have been involved in supervision and tutorship of 2 Ph.D. theses, 24 Master theses and 14 graduation projects. • 1 internship in the field of Embedded Systems

Supervision of Graduation Projects

Since 2016, I have supervised several graduation projects in different universities. The following list presents these projects classified according to the universities and majors. • IEEE International New Circuits and Systems Conference (NewCas)

• IEEE International Conference on Communications and Information Technology (ICCIT)

• IEEE International Conference on Microelectronics (ICM)

• IEEE New Generation of Circuits and Systems Conference (NGCAS)

• IEEE International Conference on Computer and Applications (ICCA).

• IEEE International Conference on Electronics Circuits and Systems (ICECS).

• IEEE International Symposium on Rapid System Prototyping (RSP)

• IEEE Microwave Theory and Techniques in Wireless Communications (MTTW)

• International Conference on System-Integrated Intelligence (SysInt)

Committee Membership

I have served as a committee member for evaluating Master theses and graduation projects in different majors at different universities. The following list shows my participation in evaluation committees classified according to university, level and major:

1. Lebanese University (LU), Faculty of Sciences (FS), Lebanon: I have participated in teaching several courses and practical work related to electric circuits, electronics and fundamental logic circuits. During my academic career and for several academic years, I have taught "Electric Circuits", "Fundamentals of Digital Logic Design" and "Signals and Systems" courses, where I have applied the concepts in a fun and operational way using software simulators and basic hardware platforms.

Note that in my previous teaching work, I have participated in developing the plan of study to include the "Introduction to Engineering" which aims to teach engineering students how to solve a problem and implement the solution through building simple algorithms and implementing them on available hardware platforms, in particular Arduino toolset and its compatible sensors. Several teaching methods have been adopted especially project-based teaching in order to give the students the opportunity to develop knowledge and skills through engaging projects set around real-life challenges and problems.

Courses in the field of embedded systems

I have a long experience in teaching courses about processors and microcontrollers, advanced digital logic systems, hardware description languages, computer architecture and embedded systems for under graduate and graduate levels.

I have taught "Advanced Logic Design" course that introduces designing of logic elements used in computations targeting Programmable Logic Devices (PLDs) and Field Programmable Gate Array (FPGA) devices. It aims to teach how to design, in VHDL, several modules such ad decoders, memories, ALU, multiplexers, registers, etc. Students are directed to use ModelSim in order to verify the designed modules. Also, I contributed in developing a practical course for graduate level about designing MIPS processors from scratch. The course aims to teach how to design, in VHDL, the sub-modules of the processor as well as the instruction set. Students are directed to use ModelSim in order to verify the designed processors.

I participated in teaching the technical work of the "Signals and Image Processors" course in the research Master program in Signals, Telecom, Image and Speech (STIP). This course focuses on implementing image processing techniques on FPGAs from algorithm till the hardware realization. In particular, the course introduces the design and implementation of Sobel filter on Spartan-6 FPGA.

I have taught the "Computer Architecture" course for graduate level. The course aims to introduce essential computer architecture design and analysis techniques. The course treats fundamental methods used to improve performance of microprocessors like pipelining, caches hierarchies, superscalar processors and out-of-order execution. This graduate course also considers parallel processing topics at different levels (instruction-level parallelism, data-level parallelism and thread-level parallelism). Scheduling and fault-tolerance strategies are also covered in this course.

For several years, I have taught microprocessors and microcontrollers courses, which target the microchip PIC, ARM-based and Atmel microcontrollers. In general, these courses introduce the architectures of the targeted processors and their corresponding instruction sets. Moreover, these courses introduce programming of the microcontrollers including looping, branching, arithmetic and logical operations, timers, interrupts, communication protocols (UART, I2C, SPI, etc.) and controlling input-output pins. Students are directed to use the the associated software development tools (MPLab, CCS, STM32CubeMX, Arduino IDE, etc.) and software simulation tools -such as Proteus -to develop projects Furthermore, I have taught the "Embedded Systems" course for graduate students which aims to provide the students with the basic information about embedded systems. The first part of this course introduces in details the ARM-based/AVR microcontrollers. The second part is devoted to the programming of embedded systems, where the students learn to design and develop a programmable embedded platform from scratch and interface a variety of sensors. In addition, the course cover multitasking by introducing real time operating system (RTOS) and using FreeRTOS to apply Queues, Semaphore and Mutex targeting Atmelbased processors (integrated in Arduino platforms) and ARM-based processors (integrated in STM32 platforms). Moreover, I have taught "Operating Systems" course and the "Linux" technical lab targeting Raspberry Pi platforms.

Courses in the field of digital communication

Since 2016, I have taught the course of "Digital Communication" which is an introduction to modern digital communications at a graduate/senior undergraduate level. The coverage emphasizes a conceptual understanding of principles, techniques, and fundamental limits in digital communication systems. This course covers modulation for digital communications over additive white Gaussian noise (AWGN) channels; bandpass and low-pass signal representation; signal space representation of waveforms; modulation; demodulation; optimum receivers for AWGN channels; probability of error analysis; channel coding; synchronization; an introduction to digital communication through band-limited channels.

The course has been further developed in 2018 to include, in addition to theoretical concepts, direct applications of the theoretical concepts using MATLAB. It gives hands-on experience in translating digital communication concepts into software-defined radio technology using MATLAB coding of the different basic blocks of a digital communication system. Students can experiment a complete functional digital communication system by putting all the designed blocks together. Note that the Lab course of this work includes implementing the algorithms using USRPs from national instruments using LabView.

Courses in the field of artificial intelligence and computer vision

I have taught the "Multimedia Networks" course for graduate level. The course aims to introduce different media types such as audio, image and video showing their characteristics and the techniques used in coding along with the corresponding available standards. Also, I have taught for graduate level the course of "Image Processing and Computer Vision" that includes the topics of filtering, transformation, edge detection, feature extraction and the use of neural networks and deep learning in computer vision.

I have initiated the teaching course "Neural Network and Deep Learning" in the Image-Signal Module in the program of the Research Master's degree of Science in "Medical Physics and Living Imaging" at the Faculty of Sciences at Lebanese University.

Courses in the field of software engineering

I have taught practical course about software applications using object oriented programming (OOP). I teach an introductory course about relational database that includes a practical work that enables students to design an application embedding a database from scratch (SQL, phpmyadmin, Java, etc.).

Courses in the field of mechatronics

I have developed a course to introduce mechatronics to electronics engineers. The course scope is to practically lead students to collect data from different sensors, analyze, and take decisions to control electromechanical actuators. The course introduces mechanical mechanisms (gears, pulleys, belts, pinions, screws, etc.); motion sensors (GPS, encoders, accelerometers, speed sensors, proximity sensors, etc.) and actuators (motors, servo motors, solenoids, etc.). I have organized practical tutorials for students that demonstrate the interaction between embedded systems and electromechanical system.

Technical Training Courses

I provide technical training courses in the domain of basic and advanced programming, telecommunication and electronics (logic, digital systems, OOP programming, circuit design, and PCB assembly, FPGAs) to engineers, university and technical institutes students. These lectures are presented during private training sessions and workshops. 1. Flexible yet efficient architectures for applications in the digital communication domain:

This topic was the subject of my PhD thesis. However, I continued working on this topic afterward. It spans the refinement of algorithms to meet with hardware constraints and exploring new design methodologies to achieve flexiblity, efficiency and designing productivity. In particular, the No-Instruction-Set-Computer design methodology has been explored to design hardware architectures of the base-band modules.

Efficient algorithms and architectures for dataflow applications:

In this topic, new algorithms and architectures have been devised to enhance the performance of dataflow applications and to reduce the communication overheads and the power consumption. In particular, the notifying memory concept has been introduced to reduce the number of useless attempts, which processors perform to read from and/or write into memories. Also, a novel approach has been introduced to remap the actors (tasks) during run-time on NoC-based heterogeneous MPSoCs in order to fit with the dynamic behavior of dataflow applications.

Efficient and flexible design paradigms based on emergent memristive devices:

An important part of my research activities targets exploiting emergent memristive devices to achieve flexible high performance architectures. The novel NoC-Memory based computing concept has been realized and validated by making use of emergent nonvolatile magnetoresistive random-access memory with power-gating capabilities targeting database search application implemented with neuromorphic architecture based on Sparse-Neural-Network. In addition, the use of memristors to design architectures which combine flexibility and efficiency, has been explored and introduced through the proposal of original architectures that break the limits of the existing ones. The exploration and study have been conducted in three main levels: (1) interconnect level, (2) processing level and (3) memory level.

Efficient implementations of machine learning algorithms:

The main objective of this topic is to design efficient implementations of machine learning algorithms with as much reduced hardware area and energy consumption. The application targets tactile data processing. This topic addresses basically designing specific hardware accelerators and exploiting approximate computing techniques to accelerate 43 demanding portions of machine learning algorithms and to adequately reduce the algorithms computational complexity respectively.

In the following, for each topic, the context of the conducted work is given. After introducing the topic, motivations are provided along with the background showing the related performed work and what is missing from the state-of-the-art. Then, the list of contributions and the performed technical work is provided. Most important results are shown next followed by the most impacting publication on the subject.

Introduction

Applications in the field of wireless digital communications are becoming increasingly complex and diverse. Recent emergent wireless communication standards support various modes and configurations related to channel coding type, modulation type, and antenna dimension for multiple-input multiple-output (MIMO) transmission techniques. On the other hand, iterative concept is also utilized at the receiver side to alleviate the destructive effects of the channel [3], but data the cost of additional computational complexity.

In digital communication application domain, flexibility is an emerging design feature that permits the hardware architectures to cope with the various requirements of multiple communication standards for different system configurations. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints, but also the requirement of flexibility. Because of the rapid evolution of related standards, modern wireless digital communication systems are highly concerned about the flexibility feature. This flexibility requirement is foreseen to become even much higher with the multiple communication scenarios and modes [4].

Nowadays, highly flexible architectures are supposed to be exploited in multiple wireless communication standards (WiFi, WiMax, LTE, LTE-A, and DVB). The implementations of these architectures should function properly within different system configurations and should not be restricted to certain types of modulation, mapping styles, and/or antenna dimensions. Application-specific processor design approaches allow to tune the performanceflexibility tradeoff as required by the target application. The concept has emerged several years ago. Note that the flexibility degree can be fully tuned by the designer. The concept has no limitation in this regard. In this context, flexible application-specific hardware architectures implementing the functionalities of digital baseband components of the receiver are under design scope. Application-specific processors constitute a key trend in implementing definite blocks of wireless system since they provide a good solution in designing flexible architectures that can fulfill nowadays requirements in terms of low error-rate performance and high throughput, and satisfy the tight constraints on implementation area and power consumption.

The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing the hardware. In general, available design approaches that adopt dynamic scheduling of instructions add an overhead due to the instruction decoding. To minimize this overhead, several approaches have been introduced, which opt static scheduling. In this context, No-Instruction-Set-Computer (NISC) concept has been introduced to design application-specific processors without an instruction set. NISC concept proposes that there is no need to first design and then use an instruction set when the hardware is programmed by its designers rather than its users. NISC designing approach offers a good compromise between flexibility, productivity, and quality for the design of a digital system.

In this research work, NISC approach is explored through the design of flexible and efficient architectures dedicated for digital communication applications which fulfill the requirements imposed by multiple emergent communication standards.

Context and Motivations

Design Approaches Overview

The baseband modules could be implemented using dedicated or programmable hardware implementations, depending on the target performance requirements. The dedicated hardware implementations adopting low-level design approaches at Register Transfer-Level (RTL) ensure best exploitation of the allocated resources to execute the desired functions, however the main issue of such approach concerns designer productivity and the typical low degree of flexibility. On the other hand, programmable hardware, i.e. instruction-set based processors, are highly flexible through software programmability, yet present several limitations in terms of achievable performance and energy/area efficiency. High-Level Synthesis (HLS) tries to improve the productivity by converting directly high-level language, C for example, description into RTL. When using HLS, the designer cannot manage precisely the correlation between the modifications applied to the application and the obtained implementation performance/cost metrics such as area, power, clock frequency, routable layout, etc. To improve the quality, the designer can depend only on guess-try-check strategy. The quality of the result is noticeably low compared to manual RTL, particularly for complex applications. Furthermore, in HLS the area and delay of the design increase rapidly as the size of the software application description increases. Moreover, the design generated by HLS is not reprogrammable contradicting the ever increasing requirement of flexibility in emerging applications. Figure 4.1 illustrates the traditional available design approaches. The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver sets up a new design metric added to the requirements of efficiency and productivity. Application-Specific Instruction-set Processor (ASIP) design concept has been introduced as an increasingly popular option for implementing flexible architectures. ASIP concept offers a tradeoff in terms of designer productivity and the final quality of the hardware implementation. In ASIP designs, the instruction set is designed to fit in with a specific application. This specification of ASIP designs provides a compromise between the flexibility of a general-purpose processor and the performance of applicationspecific integrated circuit (ASIC) [5]. In ASIP, the functionality and datapath structure can be adjusted to fit in with specific application through using custom instructions. At run-time, custom instructions are decoded and executed by the dedicated hardware. describing the controller and instruction decoder is tedious and very time-consuming. Additionally, all available ASIP design approaches demand the design of instruction decoder. In cases where the hardware is dedicated for a specific application, designing and implementing the instruction decoder create an overhead in terms of complexity, power consumption, and implementation area.

NISC design approach has been introduced as a solution to fill the gap between designer productivity and design metrics, which are two important factors for emerging design methodologies. The approach simplifies ASIP design approach by eliminating the tedious task of defining and describing custom instruction set at the designing phase and the complex task of decoding instructions at run-time. The removing of the instruction set enhances the productivity of the designer and reduces the time-to-market. In contrast to ASIP, NISC approach reduces the complexity of the architecture since the hardware resources are allocated to fit in with the exact needs of the required application. The hardware is simplified due to omitting of instruction decoder. A simple controller is added instead of fetching and decoding stages. The program memory containing instructions is replaced by control memory that contains the control words that must be applied to the datapath components at run-time. Figure 4.3 illustrates the transition from ASIP design approach to NISC design approach. In NISC design approach, the fundamental functionalities of the controller in a processor such as fetching and decoding the instruction, analyzing the dependency, and scheduling the instructions are performed statically by the compiler. The compiler is neither restricted by a specific hardware resources due to the size of implementation area nor limited by timing constraints due to the desired execution performance. At compilation time the compiler generates the set of control words (CWs), which should be delivered to the datapath at runtime, and stores it in the control memory. At run-time, the controller simply loads CWs at every clock cycle and derives them to the control ports of the components constituting the datapath. In other words, the decoding and scheduling of instructions are done at compiler's execution time. Hence, their overhead does not impact the application execution time.

Overview on NISC design approach

NISC is a custom-hardware design technology which has been developed initially at the Center for Embedded Computing Systems (CECS), UC Irvine [6]. NISC architectures do not include an instruction set abstraction. The designer selects a custom datapath for the desired processor. A compiler first captures the code of the application, which is developed using a high level language. Then, at each clock cycle, it generates the proper control signals for the specified datapath.

Figure 4.5 shows the general overview of a processor that can be described as a controller and a datapath. In each clock cycle, the controller transfers the control bits to the datapath in order to perform a specific task and gets a feedback from the datapath in order to determine the state of the system in the next clock cycle. Every processor has a controller that transfers the sequence of control signals in memory (address space dimension) to a sequence of control words for each clock cycle (time dimension). Each instruction implicitly determines the behavior of all datapath components at specified execution cycle. NISC architectures follow the same architectural template as general processors except that instruction decoder is removed and it is shifted from hardware at run-time to the compiler at compilation time. Recently, the compiler has been given more control over the processor. This design concept has constituted a key trend in implementing hardware designs. The idea of expanding the functionality of the compiler and consequently increasing its control over the processor refers to many facts. The compiler has a bigger observation window than the hardware decoder because of its ability to parse the entire application program. In addition, the compiler can implement easier complex algorithms since it is not restricted by limited hardware resources. Moreover, transferring tasks to be performed in software rather than hardware results in simplifying the latter complexity and reduces the run-time overhead.

Instructions

Data

Controller Datapath

In NISC technology, the compiler schedules operations and decodes them into control words that control the hardware resources at run-time at each clock cycle. NISC designs have no instructions; hence no decoding stage is required. Furthermore, since all operations are scheduled statically, NISC designs do not include run-time hardware scheduler. In other words, the roles of the decoder and scheduler are transferred from hardware to software compiler. The control words (also called nanocodes), which are stored in program memory, are directly loaded to control ports of datapath components. Architectures adopting NISC concept face the risk of having extra memory needs to store the control words. This issue is called code bloating and is considered as a common problem in statically scheduled Horizontal Microcoded Architectures (HMA) [7]. Thus, the size of the control memory creates a new design challenge for the designers. In fact, the size of the control memory depends on the target application and the opted architecture choices. However, several techniques have been proposed and applied to reduce the memory size such as code packing, dictionary based and arithmetic-based compression [8].

NISC Dynamic flexibility

In NISC-based architectures, dynamic flexibility can be attained by storing CWs related to different configurations in the control memory where each configuration has a different starting offset address. Hence in this case, offset address information is sufficient to change the configuration. On the other hand, the large size of CWs constitutes typically an issue for statically scheduled architectures. However, this issue depends on the considered application and target flexibility requirement, besides the devised architectural choices for the datapath components. Furthermore, several optimization techniques such as code packing, dictionary-based or arithmetic-based compression techniques can be applied to overcome this issue [8].

Contributions and Performed Work

In this work, NISC concept is adopted to design flexible architectures dedicated for turbo equalization [9] and turbo demapping [10] functions that can be utilized in digital communication systems which fulfill the requirements imposed by multiple communication standards. The objective of this research work is to apply jointly flexibility and optimization on algorithms and hardware, with the aim of finding the best compromise between performance of the algorithms and the cost of their flexible implementation. The originality and novelty of the work mostly lie in designing simplified versions of the equalization and demapping functions of single-input-single-output (SISO) wireless receivers, with a manageable degradation of detection performance, then applying the designs on a NISC architecture, and then implementing the architecture on an FPGA. It has been shown that the devised approach is different from the ones described in the literature, and illustrated how the produced performance results have consistently superior to those of the other approaches. The contributions of this research work is summarized in the following subsections:

Study the requirements and features of modern communication systems

The objective of this work is to explore a new design approach for flexible architectures dedicated for wireless digital communication applications. Each wireless communication standard specifies a set of parameters concerning different components of the wireless communication system. So, the first step is studying the requirements and features of modern communication systems, including WiFi [11], WiMax [12], LTE [13], LTE-Advanced [14] and DVB (RCS [15,16],T2 [17,18] and S2 [19]). The specifications supported by these different wireless communication standards are investigated thoroughly.

Accordingly, the common building blocks of the transmission chain are analyzed, especially those that are computationally intensive and could represent bottlenecks when processing information symbols, both on the transmitter and receiver sides. In this work, the two blocks that were identified are the receiver's equalizer and the demapper which complexities have increased considerably, especially with the advent of Multiple Input Multiple Output (MIMO) transceiver designs.

Exploring NISC design methodology and toolset

NISC design approach is investigated to find its relevance in designing flexible yet efficient architectures in counterpart other available design approaches. The advantages of NISC architecture are analyzed to determine its potentials in speeding up computations, and hence making the case for its suitability and ability for accelerating the receiver's functions, for reducing power consumption, and for reducing implementation complexity.

On the other hand, NISC design methodology is explored in deep along with the available toolset. In fact, based on this exploration, an appropriate design and prototyping flow, which combines the conventional NISC toolset flow and direct controlling of hardware resources to ensure both productivity and implementation efficiency is devised.

Contributions in algorithmic domain

In order to design efficient low complexity architectures, the algorithms of soft-in soft-out turbo equalization and turbo demapping are refined toward hardware implementation:

• Both targeted algorithms are thoroughly investigated. Algorithmic computations are surveyed to extract the characteristics of all involved parameters. Sufficient mathematical analysis is devised to simplify the computational overhead of operations in different algorithmic steps.

• For the equalization algorithm, several novel decompositions is applied to complex number operations and complex matrix operations leading to enhanced performance and to a significant reduction of utilized computations. This work has been published in the Journal of Circuits, Systems and Computers (JCSC), 2019 [20].

• For the demapping algorithm, the developed simplifications have been analyzed to achieve best tradeoff in terms of performance and complexity for different system configurations. In addition, reference software model is developed to validate all refinement techniques performed on these algorithms. Note that a detailed survey about the simplifications on the demmaping algorithm and the corresponding hardware implementations has been published in 2022 in the Journal of Circuits, Systems and Computer s(JCSC) [21].

• For both algorithms, the complexity of the adopted refined forms is evaluated. The required numbers and types of real operations are determined. Studying and analyzing in details the functions of the receiver's equalization and demapping blocks, and proposing simplified alternatives to their typical implementation architectures, while at the same time considering the resulting degradation in symbol error rate performance. Not only these simplifications make the algorithms more suitable for implementation on NISC architectures, but they can also improve performance in terms of speed and power consumption, with anticipated tolerable degradation in detecting symbols correctly.

Contributions on Hardware implementations

In the following, the main contributions to realize the hardware designs of two NISC processors for turbo equalization and turbo demapping functions:

• The dependency among algorithm steps is studied to provide the scheduling of computational operations achieving high parallelism degree.

• The requirement of flexibility in both designs is analyzed based on the specifications of emergent wireless communication standards. For each architecture design, several flexibility parameters is defined to cope with multiple standard requirements for different system configurations.

• A careful numerical study is conducted to determine the accurate quantization and fixedpoint representation of all parameters and computational values involved in the algorithms at different algorithmic steps to ensure numerical stability of implemented algorithm. A reference software model is developed to evaluate the impact of devised quantization and fixed-point arithmetic on the error-rate performance. The detailed numerical study and its impact on the error rate performance have been published in EURASIP Journal on Embedded Systems, 2017 [22].

• A hybrid design flow is proposed as a combination between available NISC toolset flow and direct controlling of hardware resources. The adopted design flow to realize the hardware implementations has been described in Electronics, 2016 [1]. Figure 4.7 shows an overall presentation of the adopted flow. • Taking into account the refined algorithm with reduced complexity and based on the standards requirements, flexibility parameters are specified. All computational operations are scheduled achieving maximum parallelism. Depending on required flexibility parameters and operation scheduling, the architecture choices are selected to achieve an efficient architecture for different system configurations. The hardware design of flexible NISC-based architectures dedicated for turbo equalization and turbo demapping functions is tailored such that the hardware resources are allocated according to selected architecture choices.

GNR description

Prebound-C Generator

• The proposed NISC architectures are implemented on top of FPGA fabric, specifically using the well known Xilinx Virtex-7 XC7VX485T FPGA. Also, the devised NISCbased architectures are synthesized towards ASIC target. The detailed architectures of the devised demapper and detector have been published respectively in IEEE Transactions on Circuits and Systems II, 2015 [23] and in the Journal of Circuits, Systems and Computers (JCSC), 2021 [24].

• Using proven analysis and testing tools, the design and the implementation are verified and tested. On-chip validation of the two proposed NISC-based architectures is performed to verify the exact performance of the implemented architectures. Xilinx

ChipScope Pro Analyzer is used to record the output results of the design as illustrated in Figure 4.8.

USB JTAG interface

Host computer with Chipscope Pro software VC707 Evaluation Board • Testing and validation allow for producing descriptive results for related performance measures and complexity costs of the implementations and for comparing the obtained results with those of other designs and implementations found in the literature [25,26,27,28,29,30,31,32,33]. The adopted approach, results and comparisons have been published in 2018 in IEEE International Conference on Computer and Applications (ICCA), 2018 [34] and then detailed in Design Automation for Embedded Systems (DAEM),2021 [35].

Findings

In both designed NISC-based architectures, the obtained results in terms of performance and implementation area confirm the feasibility of adopting NISC concept in designing flexible yet efficient application-specific processors in the domain of digital communications.

Both designed NISC-based architectures have been compared to state-of-the-art ASIPbased architectures using similar computational resources and supporting same flexibility parameters. The obtained results show that the proposed NISC-based architectures provide a significant improvement in execution performance while having reduced implementation costs.

Also, the obtained results show that the size of the required control memory depends on the considered algorithm and the devised architectural choices. In the detector module, the adopted re-usability of allocated resources imposes separate controlling of each component; hence, additional control signals are implied. Whereas for the demapper module, implemented hardware components are considered to perform specific operations and to deal with the same type of data; hence, the number of control signals can be reduced significantly. Abstract-Applications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. An application-specific instruction-set processor (ASIP) design approach is a key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions that generally leads to an overhead related to instruction decoding. The no-instruction-set-computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this brief, the NISC approach is explored through a case-study design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-of-the-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters. Index Terms-Demapper, flexibility, iterative processing, multistandard wireless system, no-instruction-set-computer (NISC).

NISC-Based

I. INTRODUCTION

C URRENTLY, flexibility is a major design requirement of embedded systems and circuits. Hardware architectures are supposed to accommodate multitude system configurations as well as their corresponding algorithmic variants. Because of the rapid evolution of related standards, modern wireless digital communication systems are highly concerned about the flexibility feature. However, the emergent flexibility need should not come at the cost of performance and implementation requirements. Application-specific processors are increasingly adopted to implement definite blocks of wireless system since they provide a good solution in designing flexible architectures that can fulfill nowadays requirements in terms of low error-rate performance and high throughput, and satisfy the tight constraints on implementation area and power consumption.

The application-specific instruction-set processor (ASIP) concept offers a tradeoff in terms of the flexibility of generalpurpose processors and the efficiency of application-specific integrated circuit (ASIC) by customizing the functionality and M. Rizk, A. Baghdadi, and M. Jézéquel are with the Department of Electronics, Telecom Bretagne, Le Centre national de la recherche scientifique (CNRS) unites mixtes de recherche (UMR) 6285 Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance (Lab-STICC), 29238 Brest, France (e-mail: mostafa.rizk@telecom-bretagne.eu; amer.baghdadi@telecom-bretagne.eu; michel.jezequel@telecom-bretagne.eu).

Y. Mohanna and Y. Atat are with the Faculty of Sciences, Lebanese University, Beirut, Lebanon (e-mail: yamoha@ul.edu.lb; youssef.atat@ul.edu.lb).

Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2015.2455991 the data path structure through a custom instruction set [1]. This tradeoff can be tuned in a language-based ASIP design approach, when the degree of flexibility is limited, to reach an implementation efficiency comparable to parameterized architectures using classical register-transfer level (RTL) design approach [2]. However, when hardware is dedicated for a specific application, processes of specifying and describing instructions at the designing phase and decoding them at runtime form an overhead in terms of productivity, execution performance, and implementation costs. The no-instruction-set-computer (NISC) concept [3] adopts static scheduling of operations instead of dynamic scheduling (i.e., decoding instructions at runtime to determine which operations to execute) to simplify the ASIP approach. Design productivity is increased by obviating the task of finding and designing a custom instruction set. The design quality is better ensured by reducing design complexity to match exactly the requirements of the desired application. In a previous work, presented in [4], the NISC concept has been explored to realize flexible turbo equalizer. The comparison with a similar ASIP implementation, which uses identical computational resources and supports the same flexibility parameters, illustrates significant improvement in throughput with reduced implementation costs. However, additional memory locations are required to implement the control memory with respect to the ASIP program memory. In fact, this is directly related to the considered application and devised architecture choices. the NISC concept is evaluated in this brief through a different application design and architecture choices. This brief presents a novel NISC-based universal demapper. The proposed architecture is thoroughly described. In addition, the design is compared with a state-of-the-art ASIP-based equivalent implementation in terms of performance, throughput, and area of implementation. Recent emergent wireless communication standards, support various modes and configurations related to the characteristics of the target constellation such as modulation type and mapping style. Different order constellations have been employed starting from binary phase-shift keying (BPSK) up to 256-ary quadrature amplitude modulation (QAM).

Constellations with Gray mapping are adopted to achieve the lowest possible bit-error probability [5]. Furthermore, the independence between the in-phase (I) and the quadrature (Q) components of a symbol in Gray-mapped constellations can be exploited to reduce the computational complexity without suffering any performance loss. Accordingly, numerous simplifications have been proposed for specific constellations [6]. These simplifications can not be applied when incorporating signal space diversity (SSD) with rotated constellation introduced in DVB-T2 standard since the independence between I and Q components is broken.

On the other hand, an iterative receiver can significantly improve the performance compared with the noniterative receiver [7]. In iterative schemes, a priori information, which is generated by the decoder, is involved in demapping and imposes additional complexity. Most demapper implementations reported in the literature are of limited flexibility. In [8], the proposed soft-decision demapper architecture supports only four modulation schemes as specified in the DVB-S2 standard. Other demapper design has been presented in [9] for rotated QAM constellations targeting the DVB-T2 standard. To the best of our knowledge, only one universal demapper has been introduced in [2]. The demapper architecture is ASIP based and covers all flexibility requirements for recent wireless standards. Such wide flexibility to support different mapping styles, modulation schemes, SSD with rotated constellation, iterative and noniterative processing schemes becomes crucial in the current trend toward the convergence of wireless communication services [10] and the requirement of multistandard terminals. Furthermore, demonstrating the ability of designing highly flexible, yet efficient, demapping architectures can trigger the proposal of new modulation schemes and parameters that better suit the application and environment conditions. Such new schemes, associated with efficient flexible implementations, can then constitute potential candidates for adoption in next-generation communication systems.

II. SYSTEM MODEL AND ALGORITHM

Fig. 1 shows the block diagram of iterative receiver. Depending on the transmitter configuration and propagation conditions, the input from the wireless channel can be either directly delivered to the demapper or passed through a channel equalizer. To reduce the computational complexity, the demapper works in logarithmic domain and generates probabilities ṽ on received sequence in the form of log-likelihood ratios (LLRs), where v represents the binary mapping of the transmitted sequence. These LLRs construct, after deinterleaving, the input c to channel the decoder. Through the feedback loop, the a posteriori information output from the decoder is interleaved and then fed back to the demapper and the equalizer. In this brief, the channel fading has a Rayleigh distribution with additive white Gaussian noise (AWGN). To compute the LLRs, the following expression is used [11]:

L ṽi t = ln ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ x∈X i 1 ⎛ ⎝ e -1 2σ 2 |yt-ρt•x| 2 • m-1 l=0 l =i P vl t ⎞ ⎠ x∈X i 0 ⎛ ⎝ e -1 2σ 2 |yt-ρt•x| 2 . m-1 l=0 l =i P vl t ⎞ ⎠ ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ( 1
)
where m is the number of bits per symbol, i = 0, 1, . . . , m -1, L(ṽ i t ) is the LLR of the ith bit of transmitted symbol at time t, X i 0 and X i 1 are the symbol sets of constellation for which symbols have their ith bit equals b ∈ {0, 1}, ρ t is the channel fading coefficient and σ 2 is the AWGN variance, and P (v l t ) is the probability of lth bit of symbol x computed through a priori information. To reduce the complexity, max-log approximation [12] is applied by using the following formulas: The expression in (1) becomes

L ṽi t ≈ min x∈X i 0 (D -Ap i ) -min x∈X i 1 (D -Ap i ) (2)
where

D = y I t -ρ I t • x I 2 + y Q t -ρ Q t • x Q 2 2σ 2 (3)
Ap i = m-1 l=0 l =i and v l =1 L vl t (4)
where v l is the lth bit of each received modulated symbol.

The simplified expression in (2) exhibits four main computation steps: 2-D Euclidean distance computation, a priori LLR summation, minimum operations referred by the min functions, and subtraction operation of minimum values. In the case of noniterative demodulation, no a priori information is provided to the demapper. The expression of LLRs in (2) becomes

L ṽi t ≈ min x∈X i 0 (D) -min x∈X i 1 (D). (5)
Moreover, for Gray-mapped constellations, I and Q components are independent from each other; hence, the Euclidean distance is calculated in one dimension. In case where m is even, further simplification can be applied. LLR computation expression in (5) can be transformed in this case into the following [6]:

L ṽi t ≈ min x∈X (I) i 0 (D I ) -min x∈X (I) i 1 (D I ) for i = 0, 1, . . . , m 2 -1 (6) L ṽi t ≈ min x∈X (Q) j 0 (D Q ) -min x∈X (Q) j 1 (D Q ) for j = m 2 , . . . , m-1 (7)
where

D I = y I t -ρ I t • x I 2 2σ 2 D Q = y Q t -ρ Q t • x Q 2 2σ 2
and X (I) i b and X (Q) j b are the constellation point sets on I-axis and Q-axis with ith and jth bits of symbol x that have a value equals to b. Applying this simplification, 2 m/2 1-D Euclidean distances are computed instead of 2 m 2-D Euclidean distances for each LLR. For rotated constellations, a simplification has been proposed in [9] to reduce the number of Euclidean distance computations by dividing the constellation into four subregions. This subpartitioning technique reduces the number of candidate constellation points involved in computing 2-D Euclidean distances of QAM schemes from 2 m to (2 (m-2)/2 + 1) 2 .

III. ARCHITECTURE DESIGN

The variety of specifications in multiple wireless standards imposes designing hardware architecture of high flexibility to enable the computation of LLR values for different system configurations. The resources of the demapper flexibility are related to the characteristics of target constellation and the iterative demodulation concept. In this section, the architecture design proposed for the universal demapping is described. It is capable to generate soft-output probabilities in the logarithmic domain for various modulation schemes starting from BPSK up to 256-QAM with and without iterative demodulation using either the generic form or simplifications relative to the constellation rotation and the Gray mapping.

A. Architecture Choices

Toward achieving flexible demapper design, the following architecture choices are considered:

1) Modulation Order: Constellation information is stored in a lookup table (LUT) whose depth varies according to m. I and Q components of symbols and their corresponding binary mapping μ are rewritten for each target constellation. In addition, sufficient hardware operators, which are required to find minimum values and perform their corresponding subtractions required in (2), ( 5), (6), and (7), are allocated considering the largest target constellation (256-QAM). For lower order modulation schemes, unused resources are not activated. Sharing hardware resources among these operations decreases the throughput particularly for high-order modulation schemes. Furthermore, this architecture choice allows a fair comparison with the ASIP-based design presented in [2].

2) Mapping Style: The same hardware operators are utilized in computing Euclidean distances for Gray or non-Gray mapping styles. In fact, the computation of one 2-D distance is equivalent to that of two separate 1-D distances.

3) Iterative Demapping: Operators involved in a priori LLR summation are instantiated to accommodate all target constellations.

4) Quantization and Fixed-Point Arithmetic: To reduce the implementation complexity, fixed-point arithmetic is used, and computational values are quantized. Targeting a fair comparison with an ASIP-based design [2], identical quantization has been adopted for all computational parameters. With the aid of long simulations and analysis, bit widths are carefully selected to ensure least performance degradation. Using a reference software model, a degradation below 0.05 dB is measured at 10 -3 frame-error rate over a fast fading Rayleigh channel.

5) Pipelining: Temporal parallelism using pipelining is applied to minimize the length of critical path and to enhance the computation performance and the efficiency of utilized hardware resources.

B. NISC Architecture

Fig. 2 presents the structure of the proposed architecture and shows the input/output connections. The inputs to the demapper architecture are the LLRs stored in AprMem, variance σ 2 , CWs saved in CMem, constellation information arranged in Constellation LUT, and received symbols and fading factors reserved in YMem and ρMem, respectively. In addition, the LUT (1/2x)LUT provides the 1/2x inverse values required in the inversion operations.

The designed architecture is basically composed of a simple control unit and the module that performs the demapping functionality. Here, this module is referred to as DemaNISC.

1) Control Unit: It is mainly responsible for loading CWs from CMem into the components of DemaNISC module. To accomplish this functionality, the unit handles the address of CMem memory and constructs links to distribute the controlsignal bits of CWs to appropriate components. In addition, the control unit manages the flow of input data coming from YMem, ρMem, and Constellation LUT. These basic tasks reveal the simple hardware structure required to implement the control unit.

2) DemaNISC Module: It is considered the main core of the demapper architecture. From a hierarchical scope, it can be viewed as a concatenation of five units.

a) EDU: This unit includes all hardware resources that incorporate in computing the Euclidean distance expressed in (3). It is supplied by I and Q components of received symbol y I and y Q , constellation symbol x I and x Q , and fading factor ρ I and ρ Q in addition to the noise variance σ 2 . At each computation, Euclidean distance unit (EDU) can deliver two 1-D distances or one 2-D distance. EDU contains 18 registers, 6 real multipliers, 1 real adder, 2 real subtractors, and 1 2-to-1 multiplexer. The operators of the Euclidean distance calculator spread over five pipeline stages (stages 2-6, Fig. 2). In the second, third, and fourth pipeline stages, I and Q components of y, x, and ρ are exploited to compute two 1-D Euclidean distances. At the 5th pipeline stage, the two calculated distances may be added into one 2-D distance ED satisfying the implementation requirements of ( 2) and ( 5). In the case of Gray mapping style with no a priori information, the two 1-D distances are transferred to the next stage (ED I and ED Q ). At this stage (fifth), the inverse value of σ 2 , being provided at the 1/2x LUT index in the third pipeline stage, is retrieved. the summation of input a priori LLRs as described in (4). The inputs to a priori LLR summation unit (ASU) are LLR values saved in AprMem memory and vector v representing the binary mapping μ of symbols from the Constellation LUT. ASU contains 38 registers, 7 real adders, 8 real subtractors, and 16 2-to-1 multiplexers. These components spread over five pipeline stages (stages 3-7, Fig. 2). The summation process is managed by the bit values of v, which represents the binary mapping of constellation symbol x under consideration and propagates along pipeline stages. In the case of turbo demodulation, input LLRs L(v i t ), which are loaded in the second pipeline stage, are summed cumulatively in the third, fourth, and fifth stages. At this computational level, a copy of input a priori information is needed to subtract the LLR corresponding to bit v i as expressed in (4). The final a priori information summations Ap i corresponding to all bits are delivered at the end of the 6th pipeline stage. • one 2-D distance minus the a priori information as expressed in (2); • one 2-D distance only (noniterative demodulation case) as expressed in (5); • two 1-D distances (Gray mapping with noniterative demodulation case) as expressed in ( 6) and (7).

d) MFU:

This unit integrates eight minimum finder blocks whose architecture is presented in Fig. 3 and are established to realize minimum functions listed in (2), ( 5), (6), and (7) considering 256-QAM constellation. Each block is concerned to find minimum values associated to a bit location v i along all constellation symbols. As shown in Fig. 3, the minimum finder structure contains two registers. The first register stores the updated minimum value that corresponds to symbol set X i 0 ; whereas the second register stores the minimum value corresponding to X i 1 . For each new received symbol y, the two registers are initialized by loading the maximum numerical value. Each minimum finder benefits from new-updated D i values in addition to v i bits. Depending on v i value ("0" or "1"), one of the two registers is chosen to be updated. The current value is replaced by input value D i if the latter is smaller than the former. Otherwise, the register maintains its current value. A comparison is established by evaluating the sign S of the difference resulting from the subtraction operation of current value from input value D i . At the input of each minimum finder block, a multiplexer is allocated to control input data flow to minimum finder block according to the required dimension of the Euclidean distance. Overall, minimum finder unit (MFU) is composed of 16 registers, 8 real subtractors, 31 2-to-1 multiplexers, 16 AND-gates, and 16 negators. All these components are placed at the eighth pipeline stage.

e) OU: This unit is in charge of delivering finally the LLR values corresponding to each bit L(ṽ i t ) constellation symbol x. Inputs of the output unit (OU) are the minimum values available in the registers of MFU. Once minimum values of all constellation points are determined, the OU produces the difference between minimum pairs (min xt∈X i 0 and min xt∈X i 1 ) corresponding to each bit location v i . After processing all constellation symbols, final resultant differences are loaded to their corresponding output registers (out 0 to out 7 ).

IV. RESULTS AND COMPARISON

In this brief, the NISC design toolset has been used. The adopted design flow is thoroughly described in [13]. Table I summarizes the synthesis results, whereas Table II shows the number of clock cycles required to produce LLRs for different system configurations along with the achieved throughput. The results are in addition compared with those of DemASIP [2], which is an ASIP dedicated for demapping with customized data path and instruction set. Both processors support same flexibility parameters, use identical computational resources, and adopt identical quantization for all computational parameters. The comparison between the two designs shows a significant improvement in terms of execution time and implementation area. For fair comparison, logic synthesis of the proposed architecture HDL description has been conducted targeting the same device (Xilinx Virtex-5 LX330 FPGA) and using the same synthesis options and tools. Logic utilization is reduced by 30.8% for slice registers and 52.4% for slice LUTs compared with DemASIP. In fact, the implementation of resources responsible for instruction fetching and decoding increases hardware resource utilization. Whereas, in the NISC-based proposed demapper, the architecture is designed to match exactly the requirements of the application. Moreover, DemASIP can operate at a maximum frequency of 186 MHz, whereas the proposed architecture can achieve a maximum operating frequency of 240 MHz. Hence, it is 1.29 times faster than DemASIP. This is due to the DemASIP critical path that includes several levels of combinational logic and which is related to fetch program address generator, whereas only one level of logic exists in the critical path of the proposed design. In addition, Table I shows a comparison between the ASIC implementation of DemASIP and that of the NISC-based architecture on dedicated chips. In fact, the HDL code generated by Synopsys (ex CoWare) for the ASIP-based design (which is available at our research group) and the HDL code generated by NISC toolset for NISC-based design are delivered as sources to the Design Compiler tool from Synopsys to achieve the ASIC implementation targeting the ST CMOS 65-nm technology. The comparison shows that the NISC-based design offers about 10% area reduction compared with the ASIP-based design. Note that the detailed results illustrate that the control unit occupies only 1.6% of total implementation area of proposed architecture, whereas the components dedicated for fetching and decoding instructions occupy 7% of DemASIP implementation area.

On the other hand, operations in ASIP-based design are limited to the available instruction set. Overlapping of operations is not allowed. The instructions are fetched and decoded at runtime, and their functionalities are limited to their structure. Whereas, the NISC-based proposed design enables a direct and mastered access to control signals of hardware resources. Different operations are combined and then scheduled statically. Merging of operations ensures less execution time compared with DemASIP. At runtime, operations are directly performed, and LLRs are generated with no additional overhead. Table II shows that the proposed architecture outperforms DemASIP in all system configurations. For all combinations of mapping styles, modulation types, and SSD, better throughput is always provided.

Concerning CMem requirements, its width is significantly optimized (from 91 bits to 18 bits) by specifying same control bits to all components that have the same executions in all steps, whereas its depth varies according to the number of the needed execution steps to compute all LLRs corresponding to one input symbol. The required memory size varies from 23 B for quadrature PSK (QPSK) with Gray-mapped constellation to 594 B for 256-QAM with non-Gray mapped constellation. Compared with the ASIP program memory, CMem requires less memory space to be implemented. In fact, the assembly code used for DemASIP includes in addition to PROCESS instruction, which is the core instruction of LLR generation, instructions dedicated to loading input data, exporting output LLRs, looping, and no-operation instructions [2]. The available assembly code for QPSK non-Gray constellation shows that these additional instructions forms 54% of the total number of listed instructions [2]. For this system configuration, the memory space required to implement the program memory of DemASIP is 60.3% more than that required to implement the control memory (CMem) of the NISC-based proposed demapper. Note that, for both processors, CWs and assembly code are produced and optimized by hand as in this case the hardware is highly dedicated to the application, and it is programmed by its designers and not by its users. Furthermore, the proposed demapper is compared with the dedicated architectures reported in [8] and [9], which use a classical RTL design approach. These architectures support softdecision demapping; however, their flexibility is limited to the requirements of DVB-S2 and DVB-T2 standards, respectively. Targeting a fair comparison, our proposed design has been implemented on the same target devices used in [8] (Virtex II XC2-V6000) and [9] (Virtex II Pro XC2VP30). Compared with the architecture in [9], the proposed demapper requires almost 3.33 times less dedicated multipliers, 3.1 times less LUTs, but 2.2 times more registers. In terms of throughput, it outperforms the design in [9] for QPSK by 6.2 times, for 16-QAM by 3.1 times, and for 64-QAM by 1.2 times. Whereas for 256-QAM, the design in [9] shows better throughput (2.6 times) since it can concurrently compute nine Euclidean distances. In [8], the timing information about the hardware implementation is not available. The presented logic utilization summary reveals the need of 1.8 times more logic devices and 2.67 times more multipliers compared with the proposed NISC-based demapper.

V. CONCLUSION

In this brief, an NISC-based architecture of universal demapper for multiple wireless communication standards has been proposed. The flexibility of the demapper is not restricted to certain modulation types and/or mapping styles. Hardware design and implementation have been conducted using the NISC design approach. While using identical computational resources and supporting same flexibility parameters, the proposed NISC-based demapper architecture outperforms state-ofthe-art ASIP-based architecture with reduced implementation costs. In addition, less memory space is required to implement control memory compared with the ASIP program memory.

Introduction

Considering the evolution towards manycore and multiprocessor architectures in embedded systems, the interconnect network has a strong impact on performance and energy efficiency. On the software side, we observe a renewed interest for dataflow (DF) programming models that offer clear design guidelines to deal with application complexity and scalability. It allows for explicitly specifying both spatial and temporal parallelism of an application. DF programming is also a very convenient approach to manage the evolution of standards based on a large set of reused functions and to generate correct-by-construction code. One of the side effects of dataflow applications is the overhead of memory accesses. DF actors (dataflow nodes) must check firing rules including availability of input data and output buffer space. This penalty is even more important for dynamic actors, which are unavoidable in real life applications.

NoCs implement concurrent communications, increasing the bandwidth and taking advantage of parallelism at the actor level. However, NoCs also increase communication latency, penalizing DF applications which rely on a large number of requests to memories for firing rule validation. Some recent work has addressed the problem of NoC latency. It relies on path or time slot allocation and processor or buffer mapping to minimize read and write 61 delays, but it is still based on the fact that memories are slaves [38]. The idea of smart or active memory aims also to reduce the number of transactions and improve memory access efficiency by moving part of computations to the memory side [39,40].

In this research work, we address the question with a totally new approach that transforms memories into masters, able to initiate transfers by means of notifying actions when data is ready, so to get rid of useless accesses. We call this concept Notifying Memories (NM). The immediate consequence of a new balance between memory and processors is the reduction of the number of transactions and injection rates. It provides memories with notification and processors with listening mechanisms, which are conceptually close to the observer design pattern, used in software engineering. They are implemented in the network interface (NI). Our solution is thus independent from memory, processor architectures and NoC parameters. Moreover, the notifying memories perfectly match with the DF models. In real-life DF applications, both static and dynamic actors are required. The uncertainty of computing due to data-dependency prevents from any static scheduling.

Context and Prior Related Work

Many approaches rely on the same idea of the one we propose: reducing the number of transactions to save bandwidth for useful communications by trimming conflicts. In [40], an active memory processor is introduced. It is a processor that resides inside the memory controller to process data on the memory side. The computation on a set of data is done directly inside the memory and thus it reduces the number of transactions on the bus. In [39], the concept of smart memory is presented. It is a modular reconfigurable architecture that can be adapted to better match the application requirements. The goal is to propose a target that can efficiently execute applications specified with a wide range of programming models, from the stream programming model to speculative and random programming model. The works in that domain mainly focus on improving the efficiency of memory access [40]. By means of intelligent cache, memory and protocol controllers, the goal is to break the passivity of the memories. The contribution of this work follows the same trend in the way that memory is the best element to know what is in the memory. The main idea is to program memories so that they can trigger a notification. It supposes that the event is known in advance. The data-flow paradigm with the different models of computation makes this possible.

Executing data-flow applications onto an NoC-based architecture has been an active topic and gained renewed interest with the advent of parallel architectures [41]. Executing a dataflow application, naturally parallel, onto a parallel architecture seems obvious but the problem is actually more challenging [42]. The approaches in the data-flow domain propose to extend a baseline model of computation to support architectural features, to adopt a specific scheduling policy, or to tune the architecture to fit the programming model. Our approach is complementary to the existing works and is compatible with any DF model of computation (MoC) and any scheduling policy.

Motivations

Figure 5.1 presents the actor network model. An actor can contain several actions. An action is executed (fired) when a set of conditions is satisfied. This set is called a firing rule. This firing rule usually consists of checking that the number of tokens in the input First-In First-Out (FIFO) is greater than the number needed to compute, and that the output FIFO is empty enough to store the produced tokens. In this work, we propose the FIFO to notify directly the processor about its content. This idea is inspired from the observer design pattern that is used for software design. This work stands in this context of data-flow application where different models of computation are used. We use as a case study an MPEG-4 Simple Profile decoder (MPEG4-SP) specified in RVC-CAL [43]. This decoder is specified with heterogeneous MoC and contains up do 40% of dynamic actors [44]. The Open RVC-CAL Compiler (Orcc) tool is used for compiling and software synthesis [45]. This research work relies on the C-backend that generates C code for multi-core platforms. Since the number of actors (about 40) is greater than the number of processing cores, an actor scheduler is needed. Different policies have been proposed, one of the most efficient one remains the Round Robin which is the the default in Orcc. They all have the same major drawback related to DF principles, which is the inefficient polling that leads to useless accesses to the memory when a scheduling attempt is not successful. Figure 5.2 presents the structure of the software FIFO generated by Orcc tool. It is composed of five parts:

1. size of the FIFO 2. FIFO content, where memory allocation is done according to the FIFO size and size of data type 3. number of readers, since one actor can write in a FIFO but there might be several readers 4. index of readers, each reader has its own index

index of writer

The synchronization is handled through indexes. Only one actor can write in a FIFO but there might be several readers. Each reader has its own index. In the simple case where there is one reader, the difference between the reader index and writer index is computed to know the number of tokens inside the FIFO. When multiple readers occur, the minimum index is used. It might happen that one slow reader blocks the other readers. Given this FIFO structure, the processor that executes an actor has to read the values of the different indexes in order to know the number of tokens in the FIFO. This leads to two memory requests for each of the concerned FIFO. Let us take the example of the firing rule given in listing 5.1. In order to compute numTokens FIFO1, the number of tokens in the first FIFO, the processor emits two requests, one for the index of the writer, and one for the index of the reader. Note that in this example we consider only one reader for sake of simplicity. For the second FIFO, the processor emits another couple of two requests. Then, in order to check for the output FIFO, two other requests are emitted on the NoC. In C language, if the first condition is not satisfied, the whole test is stopped. The worst case is when the input conditions are satisfied but not the output condition, which would lead to six transactions for no action firing. Of course, next scheduling attempt will test again these conditions although the conditions on the input FIFO are satisfied. It has to be noticed that these conditions cannot become false on the next trial. The number of zero firings (no action could be fired) is determined out of the total number of scheduling attempts. Figure 5.3 shows the percentage of useless scheduling attempts for different video sequences from [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF]. There are two reasons why no action can be fired:

1. one of the input FIFO is empty (i.e. does not contain enough tokens) 2. one of the output FIFO is full (i.e. does not contain enough space) Figure 5.3 also shows the repartition between empty and full FIFO. The obtained results show that at least 20% of scheduling attempts suffer failure. Although the lack of tokens in the input FIFO seams to be the major reason, the disparity among the different video sequences prevents from drawing any clear conclusion.

Contributions and Performed Work

This research work has focused on how to delete useless memory requests, independently from the implemented scheduling policy although combining our approach with new scheduling policy is relevant. The main issue is to stop the polling on the NoC because:

• It is useless when no action can be fired.

• It consumes bandwidth that would be useful for effective transactions.

The current situation is that memories are subjected to processor requests. The idea is to give new capabilities to memories so that they can inform the concerned processors that their FIFO content has changed.

Our proposition is inspired from the software observer design pattern. The observer design pattern defines a one-to-many dependency between objects so that when one object changes state, all its dependents are notified and updated automatically [47]. That behavior is exactly what we expect when the content of a FIFO changes: notify the concerned processors that execute the actors connected to that FIFO.

The main contributions of this research work are:

• Introducing the Notifying Memories concept, which includes a notifier module in the NI of the memories and a listener module in the NI of the processors. For each devised module, the structure and functionality are identified. Accordingly, their hardware architectures are designed.

• Designing an NoC-based architecture which integrates the notifier and listener moudules. The NIs are modified to accommodate the devised modules without impacting the typical processes. To cope with the NM concept and to remain compliant with any existing processor or memory and to be independent from NoC parameters such as topology, router buffer depth and routing policy, the new elements are integrated into the NI of the NoC. Besides, we need a master component that can send packets through the network and a component that can monitor requests, the NI is the only component to offer such features.

• Demonstrating a model and an implementation of the devised NoC-based architecture in SystemC TLM. A cycle-accurate simulator that models the NoC and connected nodes has been created. The devised model executes an MPEG4-SP decoder with 41 actors and 70 FIFOs specified in RVC-CAL.

• The mean values of execution time of all actions are found from profiling data on a desktop computer. These values are imported to the simulator model and utilized in order to compensate the execution time of actions, which are functionally simulated.

• Introducing a new type of packet, the notification packet. The structure of the packet is described and implemented. The modules of the NIs dedicated to make/de-make packets are modified to generate/parse the new packet type.

• Conducting experimental simulations using the devised simulation model running a real-life MPEG4-SP decoder for different video sequences from [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF] in order to demonstrate the interest of the notifying memories concept in terms of performance, data traffic and power consumption. Note that the selected video sequences differ in their characteristics (motion, background, etc.) and formats (QCIF, CIF, 4CIF, etc.).

• In order to check the relevancy of the proposed concept, the obtained results when adopting NM are compared with the ones obtained when adopting ordinary memories while using identical NoC features. The comparison is demonstrated in terms of latency, throughput, injection rate and switch conflicts. As the NM concept induces sending additional data related to the notifier configuration and notifications, a detailed investigation is conducted to determine the impact of new transferred flits on the NoC traffic.

• Preliminary synthesis is achieved to estimate the impact of NM concept on implementation area and power consumption. The implemented design integrates a worst-case design, where a single notifier, which is implemented in all memory NIs, and a single listener, which is implemented in all processor NIs, can manage all firing rules of all actors. The size of the registers in all listener and notifier modules are adjusted to accommodate the signals for all actors. The area and power results are obtained with the Cadence Encounter RTL Compiler RC12.24 tool. The synthesis targets the 65nm process technology at 500 MHz operating frequency and 25 • C. Total power was obtained by using the leakage and dynamic power of the NoC components relying on the switching activity traced by the SystemC simulation.

Findings

The comparison of the results when adopting notifying memories with those obtained when adopting ordinary memories shows significant reductions in terms of latency, injection rate , switch conflicts and total number of flits along with remarkable throughput improvement.

The obtained results confirm the efficiency of NM concept and show that adopting notification memories leads to great reductions reaching 75.14% for latency, 53.96% for injection rate, 58.25% for transported flits, and 75.88% for switch conflicts. Also, the throughput enhancement is improved by up to 9.69%.

The synthesis results show that the NoC adopting notifying memories saves up to 49.1% of power consumption compared to the reference NoC. Besides, the power overhead of the interfaces of the proposed NoC presents a modest value of 16.3%. Regarding the area, the proposed NoC presents an overhead of 12.4%, when compared to reference NoC.

The conducted comparison between the number of extra flits for mapping and notification and the number of flits required to request and retrieve FIFO indexes shows that the added flits for notification and extra mapping in the case of notification memories are negligible compared to the required flits to request and retrieve FIFOs indexes in ordinary memories.

INTRODUCTION

Considering the evolution towards manycore and multiprocessor architectures in HPC and embedded systems, the interconnect network has a strong impact on performance and energy efficiency. On the software side, we observe a renewed interest for dataflow (DF) programming models that offer clear design guidelines to deal with application complexity and scalability. It allows for explicitly specifying both spatial and temporal parallelism of an application. DF programming is also a very convenient approach to manage the evolution of standards based on a large set of reused functions and to generate correct-by-construction code. One of the side effects of data-flow applications is the overhead of memory accesses. DF actors (data-flow nodes) must check Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. firing rules including availability of input data and output buffer space. This penalty is even more important for dynamic actors, which are unavoidable in real life applications.

Networks-on-Chips (NoCs) implement concurrent communications, increasing the bandwidth and taking advantage of parallelism at the actor level. However, NoCs also increase communication latency, penalising DF applications which rely on a large number of requests to memories for firing rule validation. Some recent work has addressed the problem of NoC latency. It relies on path or time slot allocation and processor or buffer mapping to minimise read and write delays, but it is still based on the fact that memories are slaves [4]. The idea of smart or active memory aims also to reduce the number of transactions and improve memory access efficiency, by moving part of computations to the memory side [1,11].

In this work, we propose to address the question with a totally new approach that transforms memories into masters, able to initiate transfers by means of notifications when data is ready, so to get rid of useless accesses. We call this concept Notifying Memories (NM). The immediate consequence of a new balance between memory and processors is the reduction of the number of transactions and injection rates. It provides memories with notification and processors with listening mechanisms, which are conceptually close to the observer design pattern, used in software engineering. They are implemented in the network interface (NI). Our solution is thus independent from memory, processor architectures and NoC parameters. Moreover, the notifying memories perfectly match with the DF models. In real-life DF applications, both static and dynamic actors are required. The uncertainty of computing due to data-dependency prevents from any static scheduling. We need to demonstrate the efficiency of the approach with real application execution, so we prove the concept and the implementation with cycle accurate SystemC simulation. We have chosen an MPEG4-SP decoder and related benchmark videos to show how we can significantly improve throughput, latencies, injection rate and so power consumption.

The contributions of this paper are:

• The Notifying Memories concept, which includes a notifier in the NI of the memories and a listener in the NI of the processors.

• A model and an implementation of the notifying memory in SystemC. It includes the introduction of a new kind of packet, the notification packet.

• Experimental results running an MPEG4-SP decoder for different video sequences that demonstrate the interest of the concept in terms of performance, injection rate and power consumption.

Section 2 presents the related work. Section 3 introduces the initial situation and a motivational example. Section 4 reminds briefly the observer design pattern and presents in details the notifying memories. Section 5 shows the results and Section 6 concludes this paper.

RELATED WORK

Many approaches rely on the same idea of the one we propose: reducing the number of transactions to save bandwidth for useful communications by trimming conflicts. An active memory processor is introduced in [11]. It is a processor that resides inside the memory controller to process data on the memory side. As the computation on a set of data is done directly inside the memory, it reduces the number of transactions in the NoC. In [1], the concept of smart memory is presented. It is a modular reconfigurable architecture that can be adapted to better match the application requirements. The goal is to propose a target that can efficiently execute applications specified with a wide range of programming models, from the stream programming model to speculative and random programming model. The work in that domain mainly focuses on improving the efficiency of memory access [11]. By means of intelligent cache, memory and protocol controllers, this kind of work breaks the passivity of the memories. Our contribution follows the same objective but is compliant with any memory controller. Our idea is to program memories so that they can trigger a notification according to some events. These events can be application specific or related to the programming model. The DF models of computation (MoC) are based on a paradigm that makes our approach particularly efficient.

Executing DF applications onto an NoC-based architecture is an active topic and gained renewed interest with the advent of parallel architectures [5]. Executing a DF application, naturally parallel, onto a parallel architecture seems obvious but the problem is actually more challenging [8]. One commercial example is the MPPA programmed with sigmaC [7]. The approaches in the DF domain propose to extend a baseline MoC to support architectural features, to adopt a specific scheduling policy, or to tune the architecture to fit with the programming model. Our approach is complementary to existing works and is compliant with any DF MoC and any scheduling policy.

MOTIVATIONAL EXAMPLE

Figure 1 presents the actor model of the Caltrop Actor Language (CAL). An actor can contain several actions. An action is executed (fired ) when a set of conditions is satisfied. This so-called firing rule usually consists of checking that the number of tokens in the input FIFO is greater than the number needed to compute, and that the output FIFO is empty enough to store the produced tokens. In this paper, we propose the FIFO to notify directly the processor about its content. This idea is inspired from the observer design pattern, used in software engineering.

We use as a case study an MPEG-4 Simple Profile decoder (MPEG4-SP) specified in RVC-CAL [6]. This decoder is specified with heterogeneous MoC and contains up do 40% of dynamic actors [9]. The ORCC tool is used for compiling and software synthesis [6]. Our work relies on the C-backend that generates C code for multi-core platforms. Since the number of actors (41) is greater than the number of processing cores, an actor scheduler is required. Different policies have been proposed, one of the most efficient one remains the round-robin (the default in ORCC). They all have the same major drawback related to DF principles, which is the inefficient polling that leads to useless accesses to the memory when a scheduling attempt is not successful.

Figure 2 presents the structure of the SW FIFO generated by ORCC [6]. It is composed of five parts: i) size of the FIFO; ii) FIFO content, where memory allocation is done according to the FIFO size and size of data type; iii) number of readers, since one actor can write in a FIFO but there might be several readers; iv) index of readers, each reader has its own index; and v) index of writer. Synchronisation is handled through indexes. The difference between the reader index and writer index determines the number of tokens inside the FIFO. When multiple readers occur, the minimum index is used. It might happen that one slow reader blocks the other readers. Many papers deal with FIFO sizing and FIFO handling but it is out of the scope of this paper. Given this FIFO structure, the processor that executes an actor has to read the values of the different indexes in order to determine the number of tokens in the FIFO. This leads to a set of memory requests for each FIFO. Taking the example of the firing rule given in Listing 1, to compute numTo-kens_FIFO_IN1, the number of tokens in the first FIFO, the processor emits two requests, one for the index of the writer, and one for the index of the reader (one for each reader actually). For the second FIFO, the processor emits another set of requests. Then, in order to check for the output FIFO, other requests are emitted on the NoC. In C language, if the first condition is not satisfied, the whole test is stopped. The worst case occurs when the input conditions are satisfied but not the output condition, which would lead to six transactions for no action firing. Of course, next scheduling attempt will test again these conditions although the conditions on the input FIFO are satisfied. It has to be noticed that true conditions cannot become false on the next trial. Our contribution also relies on this property. We have carried out some experiments using the C backend of ORCC and executed the MPEG4-SP decoder on a desktop computer. We have traced the number of firings of each actor during one scheduling attempt. We have counted the number of zero firings, i.e. no action could be fired, out of the total number of scheduling. Table 1 shows the percentage of unsuccessful scheduling for different video sequences from [10]. There are two reasons why no action can be fired: 1) one of the input FIFO is empty (i.e. does not contain enough tokens); or 2) one of the output FIFO is full (i.e. does not contain enough space). Table 1 also shows the distribution between empty and full FIFO. These results show that at least 20% of scheduling attempts are unsuccessful. Although the lack of tokens in the input FIFO seams to be the major reason, the disparity among the different video sequences prevents from drawing any clear conclusion. This observation motivates the integration of mechanisms able to monitor the FIFO status and to emit notifications. This mechanism can be integrated in the memory NI, close to the FIFO implementation.

This paper focuses on how to delete useless memory requests, independently from the processors, memories, NoC parameters and scheduling policy 1 . The main issue is to stop the polling on the NoC that: 1) is useless when no action can be fired; and 2) consumes bandwidth that would be useful for effective transactions. The current situation is that memories are subjected to processor requests. The idea is to give new capabilities to memories, so that, they can inform the concerned processors that their (FIFO) content has changed.

THE NOTIFYING MEMORIES

Our idea is inspired from the observer design pattern, widely used in software engineering. Before detailing the implementation in the NoC of the observer pattern, a brief description of the software pattern is given.

The observer design pattern

The observer design pattern defines a one-to-many dependency between objects so that when one object changes state, all its dependents are notified and updated automatically [2]. That behaviour is exactly what we expect when the content of a FIFO changes: notify the concerned processors that execute the actors connected to that FIFO. Figure 3 shows the UML class diagram of the observer design pattern. The subject is the element to watch. The observer is the element that should react whenever a change occurs from the subject. The subject notifies a change to their observers by means of a method.

1 although combining our approach with a new scheduling policy is relevant

NoC Implementation

Porting the observer design pattern to our context, the memory is the subject and the processor is the observer. There are two elements to be added in the NoC platform: the notifier and the listener. In order to remain compliant with any existing processor or memory and to be independent from NoC parameters such as topology, router buffer depth and routing policy, we have decided to integrate these elements into the NI of the NoC. Besides, we need a master component that can send packets through the network and a component that can monitor requests, the NI is the only component to offer such features.

Figure 4 illustrates the structure of the NoC used to demonstrate the notifying memory concept. The NoC is a 4 × 4 mesh-based network which interconnects 28 IP cores (13 processing and 15 memory nodes). It is based on usual wormhole packet switching mode, deterministic XY routing algorithm to avoid deadlocks, and flow control policy without virtual channels. The routers have one arbiter per port and one buffer per input port. Our approach is actually generic and can be applied to NoC with different features. For instance, N-flit buffers can be used to improve performance at the cost of more memory, in that case all transactions including notifications will take advantage of it. The backend part of the NI is typical, it includes a packet maker and packet un-maker to assemble and disassemble the packets, a scheduler/priority manager to synchronize packet transmission and reception. The modifications lie in the front-end of the network interface by either implementing the notifier or the listener. The notifier is implemented in the NI of a memory. The listener is added in the NI of a processor. The structures of the additional components are detailed in the following subsections.

Notifier

The notifier is a hardware module that transmits the status of all FIFOs allocated in a node accommodating memory. For each FIFO, the notifier generates a notification sig- nal that is passed to the FIFO's writer whenever it contains enough space to save new tokens, or to the FIFO's readers whenever enough tokens are available. The notifier architecture is illustrated in Figure 5. It is basically composed of a comparator, 2 subtractors, a maximum finder, an and-gate, an inverter, and set of registers classified in seven banks: FI-FOs indexes bank (FIB ), FIFOs status bank (FSB ), firing rule conditions bank (RCB ), firing rule satisfaction bank (RSB ), notification history bank (NHB ), actors ID bank (AIDB ) and actors locations bank (ALB ). The notifier functionality can be divided into three phases: the configuration phase, the checking phase, and the notification phase.

… … 𝐼1[𝑅1] 𝐼1[𝑅𝑛 1 ] … … … … FIB FSB … … … 𝑇𝑘[𝑅1] 𝑇𝑘[𝑅𝑛 𝑘 ] … … 𝑇1[𝑅1] 𝑇1[𝑅𝑛 1 ] … Reader_sel FIFO_sel - … … 𝐹𝑆1 𝐹𝑆𝑘 … … … 𝑅𝑒𝑔 FIFO_sel 𝐼1[𝑊] 𝐼𝑘[𝑊 ≤ Compare_sel … 𝑇𝑘[𝑅1] 𝑇𝑘[𝑅𝑛 𝑘 … 𝑇1[𝑅1] 𝑇1[𝑅𝑛 1 ] … … FSB 𝐹𝑆1 𝐹𝑆𝑘 … … … … … 𝐶𝑘[𝑅1] 𝐶𝑘[𝑅𝑛 𝑘 ] … 𝐶1[𝑅1] 𝐶1[𝑅𝑛 1 ] … … RCB 𝐶1[𝑊] 𝐶𝑘[𝑊] 8 bits 9 bits 9 bits … 𝑆𝑘[𝑅1] 𝑆𝑘[𝑅𝑛 𝑘 ] … 𝑆1[𝑅1] 𝑆1[𝑅𝑛 1 ] … … RSB 𝑆1[𝑊] 𝑆𝑘[𝑊] 1 bit … … … … … … … … … 𝑁𝑘[𝑅1] 𝑁𝑘[𝑅𝑛 𝑘 … 𝑁1[𝑅1] 𝑁1[𝑅𝑛 1 ] … … NHB 𝑁1[W] 𝑁𝑘[W] … … … … … … … … Phase_sel 1 bit … 𝐿𝑘[𝑅1] 𝐿𝑘[𝑅𝑛 𝑘 ] … 𝐿1[𝑅1] 𝐿1[𝑅𝑛 1 ] … … ALB 𝐿1[𝑊] 𝐿𝑘[𝑊] 4 bits … 𝐴𝑘[𝑅1] 𝐴𝑘[𝑅𝑛 𝑘 ] … 𝐴1[𝑅1] 𝐴1[𝑅𝑛 1 ] … … ALB 𝐴1[𝑊] 𝐴𝑘[𝑊]

Configuration phase.

Once the system is launched, the manager processor provides the mapping data to all notifiers. A packet is sent to each memory node specifying the number of involved FI-FOs in the notifier scope. Also, it specifies for each involved FIFO the locations (ID of processing nodes) of its writer and readers as well as their firing rule conditions and the IDs of their corresponding actors. The registers of ALB, FCB, and AIDB store this information respectively to be used in the next two phases. The registers of the other banks are reset.

Checking phase.

When a node receives a new packet modifying one of the FIFOs' indexes, the packet un-maker provides the notifier by the FIFO address (f ), and its modified writing index (If [W ]) or i th reading index (If [Ri]). The notifier stores the new received index in its specific register in FIB. If the writing index of FIFO f has changed, the notifier recomputes the number of available tokens for all its readers (Tf [Ri]). If one of its reading indexes is modified, the notifier recomputes the available free space (F Sf ) in FIFO f .

The notifier assigns the computed values to their corre-

Algorithm 1 Checking firing rules satisfaction

Input: k the number of FIFOs, nf the number of readers of FIFO f for all f ∈ {1, ..., k} do if If [W ] modified then for all i ∈ {1, ..., nf } do

Tf [Ri] = If [W ] -If [Ri] if Tf [Ri] ≥ Cf [Ri] then Sf [Ri] = true end if end for end if for all i ∈ {1, ..., nf } do if If [Ri] modified then F Sf = If [W ] - max i∈{1,...,n} (If [Ri]) if F Sf ≥ Cf [W ] then Sf [W ] =

Notification phase.

In this phase, the notifier loops around the bits of RSB in a round-robin manner and generates consecutively the notification signals, which should be sent to targets (readers and writers) with satisfied firing rules. The notifier provides the packet maker with the target location, identity number, satisfied firing rule identity number, and the number of available tokens or free space. The packet maker assembles the notification packet as depicted in Figure 6. To reduce the number of sent packets, the notification history is recorded in NHB which reserves one bit for each target. When a notification is sent, the target corresponding bit in NHB is set to "1", and it is reset to "0" when the notification is consumed by the target. By using simple logic (and-gate and inverter) the notifier limits the generation of notifications to targets with "0" in their corresponding bits.

Listener

The listener stores the information included in the notification packets sent by notifiers. The coupled listener to each processor specifies the validation statuses of all firing rules related to all actions of all actors mapped to the processor. The processor accesses the validation status of all firing rules corresponding to an action before it is fired. In addition to the status, the listener stores the value of the available tokens at the input FIFO and the free space at the output FIFO for each input and output firing rules respectively. The information is thus available locally to the processor and no memory requests through the NoC are needed. The S: status A: actor D: notification data

… 𝐷1[𝐴𝑛] 𝐷𝑘 𝑛 [𝐴𝑛] … 𝐷1[𝐴1] 𝐷𝑘 1 [𝐴1] … NDB 9 bits … 𝑆1[𝐴𝑛] 𝑆𝑘 𝑛 [𝐴𝑛] … 𝑆1[𝐴1] 𝑆𝑘 1 [𝐴1] … RSB 1 bit … … … … … … … … … LUT + Actor ID Firing rule ID 1 0 Notification data load set/ reset … … …
Figure 7: The listener architecture listener architecture is illustrated in Figure 7. It is composed of a look-up table (LUT), an adder, and set of registers classified in two banks: the firing rule status bank (RSB ) and the notification data bank (NDB ). The listener functionality is divided into two phases: the configuration phase and the execution phase.

Configuration phase.

The listener benefits from the mapping information provided to the processor at system boot. It acquires the specification of the mapped actors (number, identification number, number of firing rules) to set its configuration. The look up table (LUT) is configured such that the starting address specified to store notifications of each mapped actor is retrieved at the LUT output when the actor identification number is provided at the LUT input.

Execution phase.

When a node receives a notification packet, the payload is provided to the listener. The actor ID is given to the LUT input; whereas the firing rule ID is used as an offset to determine the storage index j. Accordingly, the listener stores the notification data (free space or available tokens) in the j th register of NDB and set the j th bit of RSB to "1" indicating the validation of the firing rule. To access the notification information of a specific rule, the processor uses the same mechanism of loading data to the listener by providing the actor ID and the firing rule ID. Once the notification information is consumed, its relative bit in RSB is reset to "0".

DF-level deadlock avoidance

In the DF paradigm, an actor in non preemptive. Once fired, an action consumes and produces the tokens according to the firing rule. The indexes of the FIFOs are updated afterwards (conservative synchronisation scheme). Since the memory requests are triggered by the notifications and the execution of the action is not preemptive, there can never be any race conditions. A valid firing rule at time t is still valid at time t+1 if the associated action has not been fired.

EXPERIMENTS AND RESULTS

Experimental Setup

In order to check the relevancy of the proposed approach, the adopted NoC implementing notifying memories has been described in SystemC TLM model as a proof of concept. The devised model executes an MPEG4-SP decoder with 41 actors and 70 FIFOs specified in RVC-CAL. The number of FIFOs are approximately equally distributed on all nodes accommodating memories. The actors are then mapped man- ually such that the number of hops is minimized between one actor and its FIFOs. The SystemC model is cycle accurate at the NoC level and network interface; whereas actions are functionally simulated. We strive to accurately reproduce the timing features of actions executions in addition to their functionalities. The mean values of execution time of all actions are imported from profiling data on a desktop computer. Multiple simulations have been conducted to decode ten frames for several video sequences from [10]. To evaluate the efficiency of NM concept, the obtained results are compared with the ones of ordinary memories. Both models use identical NoC features (e.g. 500 MHz frequency, switching mode, routing algorithm), processing elements features, and mapping strategy.

Results and Comparison

Performance results

Table 2 shows the results obtained after decoding 10 frames of ice video sequence in 4CIF format in terms of throughput, latency 2 , injection rate, switch conflicts, total number of transported flits, and power consumption. The comparison between the two cases, ordinary and notifying, shows significant reductions in terms of latency, injection rate, switch conflicts, and number of transported flits and packets. Also the throughput is improved such that it is compatible to the 25 frames per second standard without using additional hardware accelerators or processing speedups.

The analysis of the results reveals an additional traffic overhead in case of ordinary memories which increases significantly the injection rate and switch conflicts. To track its cause, packets are classified according to their functionality into two categories: data and control packets. Packets holding tokens or requests for reading tokens are data packets, while control packets category includes all other packets that are used to transport mapping information, set FIFO indexes, request or retrieve FIFO indexes, and notification signals produced by notifiers. This classification is also applied to flits. Figure 8 presents a comparison between notifying and ordinary memories in terms of control and data categories for transported packets and flits for the ice-4CIF video. The figure shows that ordinary memories induce 19 times more control packets and 10 times more control flits than notifying memories. The number of data packets and flits is approximately the same in the two cases. The simulation is stopped after 10 fully decoded frames while the network contains partially decoded frames. This explains the traffic overhead, due to the additional control packets injected to the NoC. Investigating thoroughly the types of transported control flits shows on one hand that more flits 2 the time between the first token consumed and the first token produced by the application are needed for mapping information when notifying memories is adopted since the manager have to send additional information for all notifiers. Also, additional notification flits are transported from notifiers to the listeners. On the other hand, the adoption of notification memories eliminates the use of flits to request and retrieve FIFO indexes. Figure 9 shows in logarithmic scale the number of each type of control flits transported while decoding 10 frames of ice video sequence in 4CIF format for the case of notification memories and ordinary memories. It shows that the added flits for notification and extra mapping in the case of notification memories are negligible (4.58%) compared to the required flits to request and retrieve FIFOs indexes in ordinary memories. Due to space limitations, the comparisons for other video sequences are summarized in Table 3. These average results confirm the efficiency of NM concept and show that adopting notification memories leads to great reductions reaching 78% for latency, 60% for injection rate, 67% for transported flits, and 85% for switch conflicts. Also the throughput enhancement is improved by up to 16%.

Preliminary synthesis results

We have implemented a worst-case design, where a single notifier, which is implemented in all memory NIs, and a single listener, which is implemented in all processor NIs, can manage all firing rules of all actors. The number of firing rules of in the MPEG4-SP application is 145. Hence, 145 registers are required in all banks of the 12 listeners (one per processor) and 15 notifiers (one per memory). The area and power results are obtained with the Cadence Encounter RTL Compiler RC12.24 tool. The synthesis targets the 65nm process technology at 500 MHz operating frequency and 25 • C. Total power was obtained by using the leakage

CONCLUSIONS AND FUTURE WORK

This paper presents the notifying memories, a hardware implementation based on the observer design pattern, to enhance communication of data-flow application that are deployed on a multi-processor platform. The notifying memories are baseline memories extended by a notifier implemented into the NI of the NoC. The notifying memories send a new kind of packet, the notification packet that is caught by a listener, a module implemented in the NI of the processor. The notifying memory concept raises new opportunities and new challenges. At the hardware level, an exploration is needed to find out the size of the components: number of possible notifications, size of the listener. Another challenge is to make it configurable or programmable for other programming models. At the software level, the compiler should detect the firing rules to appropriately separate the code onto the notifier and the listener. Finally, new scheduling policies could take advantage of notifications.

Run-Time Remapping of Dataflow Actors on NoCbased Heterogeneous MPSoCs

Introduction and Motivations

Multiprocessor system-on-chip (MPSoC) platforms have been emerging as the main solution to cope with processor frequency ceiling and power density issues while still improving performances. Then, networks-on-chip have been adopted to provide the increasing number of processors with the required communication bandwidth as well as with the necessary flexibility. But legacy code for instance, mainly designed for single or few core architectures, does not scale well with manycore architectures and fails to fully benefit from the available parallelism. However, as discussed decades ago [START_REF] Najjar | Advances in the dataflow computational model[END_REF], dataflow programming can address the limitations of conventional approaches regarding synchronization and shared memory issues. With the rise of massively parallel architectures, we can reconsider the use of dataflow programming as a solution to efficiently exploit the resources of parallel architectures for computing intensive application domains such as video coding, computer vision, machine learning and physics simulation for instance.

A dataflow application can be specified as a graph where nodes, called actors, process data called token(s). The computational models are based on FIFO buffers and respect their formalized read and write rules. Each FIFO holds a set of tokens. A network of actors holds specific features that make it different from a generic task graph. Figure 5.1 presents a simple example on network of actors.

First, an actor is non-preemptive. Once started, an actor ends its execution. Second, the actor can start if and only if there are enough tokens as input, and enough space in the output FIFOs. The FIFOs are considered updated (i.e. tokens consumed and produced) at the end of the execution of the actor, establishing a conservative synchronization scheme, and preventing from any data race.

When the number of actors is larger than the number of processing elements (PEs), then the main design challenge is the mapping of actors on the network of PEs [42]. In the case of static dataflow [START_REF] Lee | Synchronous data flow[END_REF], where the number of tokens produced and consumed by the actors is known, an optimal solution can be computed offline [START_REF] Lesparre | Evaluation of synchronous dataflow graph mappings onto distributed memory architectures[END_REF]. However, an increasing number of applications cannot be specified with a static graph since the performance improvement of complex applications usually lead to context and data-dependent optimizations. This evolution is, for instance, significant in the domain of video coding.

Dynamic models are then used to express data-dependent behavior of some applications. Dynamic dataflow is a useful MoC for handling streaming data and video processing applications [START_REF] Lee | Dataflow process networks[END_REF]. As the workload of an actor may change according to the input data set, adapting the mapping, while the application runs, is required to optimize the use of the computing and communication resources. Hence, adopting any static or offline dynamic scheduling for mapping tasks will not cope with the computation variations. This research work introduces an original run-time mapping algorithm based on the Move Based (MB) method targeting a dedicated heterogeneous NoC-based MPSoC architecture to achieve workload balancing and optimized communication traffic. The devised algorithm compromises monitoring the execution of actors while running in real-time on processors. Based on the recorded performance metrics, an estimation of performance gain and cost is determined to move one actor in order to enhance the overall performance.

Context and Related Work

The question of mapping parallel applications on multi or many-core architectures is a very wide problem, with a large number of dimensions, including the programming model, the target architecture (homogeneous or heterogeneous, bus-based or NoC-based, etc.), and the optimization goal (throughput, execution time, energy, etc.) [42].

The mapping problem can be solved based on two main strategies: design-time, and runtime. When solved at design-time, the mapping is called static since it's computed offline and does not change while the application runs. This approach allows for exact methods to find an optimal solution [START_REF] Huang | A scalable and adaptable ILP-Based approach for task mapping on MPSoC considering load balance and communication optimization[END_REF] [51] [START_REF] Li | Chordmap: Automated mapping of streaming applications onto CGRA[END_REF], but suffers from a lack of flexibility since it cannot capture the dynamic behavior of some applications. Moreover, even in the case of deterministic execution times of actors in a static context, the paper [START_REF] Rubattu | Pathtracing: Raising the level of understanding of processing latency in heterogeneous mpsocs[END_REF] interestingly shows the difference between the optimal mapping obtained from a well-formalized problem and the real execution trace, due to execution variabilities coming from the hardware.

The dynamic workload should be handled using run-time techniques. The run-time mapping strategies can themselves be divided into two categories:

1. on-the-fly mapping 2. hybrid mapping On-the-fly mapping techniques are application -and platform -agnostic and solve the problem online. Very simple and efficient heuristics should be used to shorten the response time. For NoC-based MPSoCs, various fast heuristics targeting the reduction of communications under constraints have been already proposed [START_REF] Chou | Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip[END_REF] [57] [START_REF] Fattah | Adjustable contiguity of run-time task allocation in networked many-core systems[END_REF]. These approaches consider one task per core. Allowing multiple tasks on one core is considered in [START_REF] Maqsood | Dynamic task mapping for network-on-chip based systems[END_REF]. Heuristics are fast but can be far from optimal solutions, so hybrid approaches have been introduced. They are based on pre-computed optimal solutions for a set of cases. The job is split into two phases:

(1) at design-time, a set of solutions is computed, and (2) one solution is selected at run-time. A wide variety of approaches can then be cited: based on traces in [START_REF] Singh | Resource and throughput aware execution trace analysis for efficient run-time mapping on MPSoCs[END_REF], on priority in [START_REF] Ykman-Couvreur | Linking run-time resource management of embedded multi-core platforms with automated design-time exploration[END_REF], on scenario in [START_REF] Quan | A scenario-based run-time task mapping algorithm for MPSoCs[END_REF], on previously identified design points in [START_REF] Singh | Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs[END_REF], or on WCET and scheduling in [START_REF] Skalistis | Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees[END_REF]. None of these studies demonstrates its efficiency with real video applications running reference sequences. The proposed real-time mapping reconfiguration method in [START_REF] Henkel | Dynamic resource management for heterogeneous many-cores[END_REF] requires to suspend the currently running application and the manager remaps the tasks at run-time according to scenarios previously defined at design-time based on the evaluation of multiple mappings, optimizing for their resource requirements and power consumption. In [START_REF] Wang | Dynamic application allocation with resource balancing on NoC based many-core embedded systems[END_REF], the authors have proposed a dynamic resource balance algorithm targeting NoC-based many-core homogenous platforms to enhance the system performance by balancing the utilization of on-chip computing resources and communication resources. Most of the available methods focus on determining the suitable mapping of tasks before starting the execution of the application [START_REF] Kaushik | Computation and communication aware run-time mapping for NoC-based MPSoC platforms[END_REF][START_REF] Mendis | Dynamic and static task allocation for hard real-time video stream decoding on nocs[END_REF][START_REF] Rapp | Neural network-based performance prediction for task migration on S-NUCA many-cores[END_REF][START_REF] Paul | Adaptive task allocation and scheduling on NoC-based multicore platforms with multitasking processors[END_REF][START_REF]A hybrid adaptive strategy for task allocation and scheduling for multiapplications on NoC-based multicore systems with resource sharing[END_REF].

Finally, a last approach can fall into the family of hybrid mappings, which considers to recompute partially the mapping problem at run-time. This is called run-time remapping.

Our work follows such an approach for dataflow applications. First, profiling results are used to find at run-time a first mapping. Then, the application is monitored to update the profiling results and a run-time remapping algorithm runs regularly to check if a new mapping would be better than the current one.

Among the innumerable works dealing with task mapping, we consider run-time methods for dataflow tasks, and have identified a limited number of solutions. In [START_REF] Yviquel | Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms[END_REF], the mapping is modeled as a graph partitioning problem, and the problem is solved at run-time by METIS tool, based on profiling information obtained by a first run. Though the migration cost of the actors is not taken into account, the results are promising and could be improved if the mapping does not change completely at each iteration. The approach in [START_REF] Ngo | Move based algorithm for runtime mapping of dataflow actors on heterogeneous MPSoCs[END_REF] allows to successively refine the mapping according to the dynamic behavior of the application, by allowing only one actor to move at a time from one processor to the other. This approach assumes dynamic dataflow application and the target architecture is composed of several heterogeneous cores interconnected by a bus or a NoC. The communication cost is computed based on a rough analytical model of the interconnection network, with the loss of accuracy that comes with it, whereas in our work, we consider profiled values gathered automatically by the system, with a finer grain down to the link.

In [START_REF] Quan | A hybrid task mapping algorithm for heterogeneous MPSoCs[END_REF], the application is specified with KPN (Kahn Process Network) and the target architecture is a shared-memory based MPSoC, with also a model of the communication channel (bus or NoC). The approach proposes to rely on three main steps: the two usual design-time preparation and run-time mapping steps plus a new customization step. The design time step computes a set of candidates and populates a database. The run-time mapping initialization derives from the candidates a new initial mapping for the given workload. Finally, the run-time customization step incorporates a Scenario-based run-time Task Mapping (STM) algorithm that is applied to find new mapping of tasks when the system detects that an objective is unsatisfied.

Contributions and Performed Work

This research work addresses the problem of reconfiguring at run-time and at the application level the mapping of dataflow actors on heterogeneous processors, that share the same instruction set architecture (ISA) while having different coprocessors and different clock domains. The proposed method, which is called run-time remapping, relies on continuous monitoring of exact performance metrics such as the computational time and communication time during real-time execution of the application. Accordingly, a new mapping of the involved actors is determined at run-time targeting the enhancement of the overall performance. This approach is sequentially repeated while the application is running. The application is neither suspended nor modified. The proposed remapping method meets with the dynamic behavior of dataflow applications, where static or offline mapping methods cannot capture the dynamic behavior and thus may not lead to optimal solutions. Also, on-the-fly and hybrid mapping methods suffer from a lack of means to monitor the performance and remap the actors accordingly. The contributions of this research work are described in the following subsections:

Design of NoC architecture for dataflow application

A new heterogeneous MPSoC architecture is proposed. The target architecture contains several different processing elements and shared memories connected with a NoC. The PEs and memory modules are technologically independent of the structure of the NoC. They communicate through the network using a network interface. The devised platform includes heterogeneous PEs. All PEs are implemented be able to execute any of the involved actors. However, some PEs are augmented with hardware accelerators in order to perform special functions more efficiently. In addition, the PEs have been specified randomly to operate on different frequencies. The memory modules include the FIFOs and store the data which is either imported to the system or processed by the PEs.

In order to implement the remapping algorithm, the designed architecture includes a manager and two special types of memories. One memory module is dedicated to store the binary codes of all actor and forwards the binary code of the moved actor to a given PE according to a notification from the manager. Another memory module is in charge of storing the mapping information, which is generated by the manager and indicates which actors are to be executed by each PE, and the monitoring information, which is collected by the PEs during processing a specified number of video frames.

The manager is a PE that executes the following five tasks.

1. map initially the actors on the available PEs 2. parse the feedback collected data from all modules (memories and PEs) 3. apply the run-time remapping algorithm and selects the actor to be moved (if any) 4. notify the corresponding PEs (looser, gainer, etc.) about the updated mapping 5. manage the transferring of the binary code corresponding to the moved actor from the shared memory into the cache of the gainer processor

Implementing the actor scheduler

An actor scheduler is implemented in order to manage the order of execution of actors on PEs, which are considered to run more than one actor as the number of PEs is smaller than the number of actors. In this work, the well-known round-robin scheduling technique has been adopted. The actors are given the attempt to be executed in a circular order without priority. The PE will execute the allocated actor if there are enough input tokens and enough space in the output FIFOs as specified in dataflow applications.

Introduce new types of command packets

In this work, new types of command packets are opted in order to manage FIFO accesses, send mapping information, collect monitoring data, and manage the transferring of binary codes. Command packets are initiated by the cores and processed by the NIs of destination nodes. The following list enumerates the devised packet types and describes briefly their corresponding roles.

1. Notification packet (NP): aims to inform the PEs that new information is ready to be requested.

2. Monitoring/Mapping information reading request packet: used to request the monitoring or mapping information as a response to the NPs.

3. Mapping information packet (M p IP): is used by the manager to inform all involved PEs after determining or modifying the actor mapping strategy.

4. Mapping Confirmation packet (MCP): aims to inform the manager that the new mapping information is well received by both the former and the new owner of the actor.

5. Monitoring information packet (M n IP): holds the feedback information needed by the manager to perform the RR algorithm.

6. FIFO index packet (FIP): holds the writing indexes or reading indexes of FIFOs.

7. Data reading request packets (DRP): holds the reading request of data from PE to memory module 8. Code transferring packet (CTP): holds a command from the manager to transfer the binary code referring to the moved actor from the shared memory to the cache of the new PE.

Present new NoC services to implement the observation and adaptation mechanisms

In order to apply the proposed method, the architecture of NoCs is augmented to efficiently provide new services of monitoring performance metrics and remapping the actors, which are not available in conventional networks. In addition, the typical NIs of memory modules are extended to accommodate the services for managing the addressing and arranging the retrieved output bits into flits. These new functionalities are implemented as additional components in the front-end of the NI corresponding to each memory module type in order to be independent of NoC parameters and to remain compliant with any available memory.

Devise new approaches to estimate NoC communication time delay

Communication time delay is a critical factor in HMPSoC platforms using NoCs. The communication time of the moved actor is affected by the location of the new hosting PE in the network. NoC time-delay estimation impacts directly the prediction process of the communication time of the moved actor. Hence, the accuracy level in estimating the delay latency changes the decision on the actor move in the RR algorithm. In this work, two novel methods have been proposed to estimate the communication time delay for transferring one token in the NoC. Both proposed methods make use of the monitoring data, which is collected while processing the video frames in the previous observation window.

The first method is called the average-path token delay (APTD) and it is based on finding the average delay for transferring one token depending on the path delays between all nodes of the NoC where a path is considered to be formed from the set of the interconnections between two specific nodes. As a deterministic routing is applied in this work, the packets always use the same path between the source node and the destination node.

The second approach is called the average-link token delay (ALTD) and considers the time-delay of the token according to the used physical links connecting the NoC components while transferring the token. A link is defined as the interconnection between two consecutive components of the NoC: router, memory and PE. Each path is segmented into a set of links. Then the average communication time delay per token is determined for each link based on the monitored tokens in the link and the accumulated communication time of these tokens.

Optimize the MB algorithm targeting the NoC-based architecture

A novel run-time remapping (RR) algorithm based on the MB method, which allows only one actor to move at a time from one processor to another, is demonstrated targeting NoC-based architecture. The algorithm benefits from the monitoring information captured in PEs and memory modules during run-time to decide the moving of an actor. The devised algorithm is divided into two main stages:

1. In the first stage, all possible candidate actors which their moves would enhance the overall throughput are identified. MB algorithm define the throughput as the inverse of the maximum period over all processors where the period of a PE is the sum of total computation time and total communication time of all actors mapped on this PE. So, the set of candidate actors includes the actors running on the PE with maximum period.

2. In the second stage, a tradeoff between the cost of migration and the predicted improvement of the performance is performed. The actor with maximum total gain is chosen to be moved. The actor selected to be moved should have a maximum total gain. Thus, the manager estimates the total gain achieved for all combinations of mapping the actors which belongs to the candidate list onto all available PEs. The estimated total gain of a mapping combination is computed by finding the difference between the estimated performance gain and the estimated migration cost of the actor The mapping combination that leads to the maximum estimated total gain is then selected. The engaged processor and actor are specified and so-called the gainer processor and moved-actor respectively. Note that the estimated NoC communication time delay (found using APTD or ALTD) is utilized to estimate the communication time and the migration time required to compute the total gain.

Building an experimental framework

In order to assess the feasibility of our proposed run-time remapping method, a real-time simulator is developed.

• The simulator is described in SystemC TLM model [START_REF] Grotker | System Design with SystemC[END_REF]. The devised simulator models the MPSoC platform using NoC concept for interconnecting embedded modules. The platform incorporates heterogeneous processing elements, memory blocks, and the manager. The simulator platform is designed with hierarchical modules that can work concurrently and intercommunicate via ports using simple or complex communication channels. SystemC features are exploited to mimic the accurate functionality of the tailored modules.

• The SystemC model adopted in the simulation platform is cycle accurate at the level of the NoC and the network interfaces. The timing of all corresponding action executions on PE is compensated in the simulation according to the profiling data extracted while running the application on a reference computer. Profiling data provides, for each involved action, the mean value of the number of cycles required to execute it. During SystemC simulations, for each fired action, its corresponding execution time determined in profiling is mapped according to the processor frequency and is used as time delay to compensate the real execution time.

• In this work we target the multimedia application domain. We adopt the well-known MPEG4 part 2 Simple Profile video decoder (MPEG4-SP) which is developed by the Moving Picture Experts Group. This multimedia application is typically used in decompression of encoded video digital data. MPEG4-SP is specified with heterogeneous dataflow MoCs and includes up to 40% of dynamic actors. It is composed of 41 actors and 70 FIFOs [44].

• The functionality of the modeled actors is verified. First, several benchmark video sequences with different formats from [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF] have been encoded. The resultant data has been used as input to the simulator. These same encoded videos have been decoded on a desktop computer and the FIFO contents have been traced over the decoding period. The contents stored in the FIFOs in the simulator have been compared to the traced FIFO data. Also, the output data of the simulator have been reconstructed into visual video in order to verify the functionality of the devised simulator.

Evaluation of the devised RR algorithm

The encoded video sequences are decoded without applying remapping targeting the same NoC-base architecture and the obtained results are compared to that obtained when the video sequences are decoded adopting the MB remapping algorithm applying ALTD and APTD for estimating the communication time delay while considering an observation window of 10 frames. The comparison is conducted in terms of packet delay, timings and performance.

Applying remapping induces additional control packets and data packets to send the mapping information, monitoring data, notifications and to transfer the binary codes. In order to evaluate the effect of applying the MB remapping algorithm on the traffic in the network, the transported flits and the number of packets that travel through the network during the decoding of the video sequences, are recorded in the case of applying the MB remapping and the case of decoding the video without remapping.

Comparison with state-of-the art

In order to determine the relevancy of the devised algorithm, it is compared to the STM method introduced in [START_REF] Quan | A hybrid task mapping algorithm for heterogeneous MPSoCs[END_REF]. In fact, the authors in [START_REF] Quan | A hybrid task mapping algorithm for heterogeneous MPSoCs[END_REF] have presented a hybrid task mapping algorithm that consists of three steps. The two first steps (design-time preparation and runtime mapping initialization) are not related to our work. The third step, so-called run-time customization, incorporates STM algorithm that is applied to find new mapping of tasks when the system detects that an objective is unsatisfied [START_REF] Quan | A hybrid task mapping algorithm for heterogeneous MPSoCs[END_REF]. According to the best of our knowledge, STM is the only similar remapping approach when focusing on the small subset of the existing work around hybrid and run-time (re-)mapping of dataflow applications on NoC-based architectures. To achieve fair comparison, the STM method is modeled and implemented on our devised NoC-based architecture.

In addition, the exact method presented in [START_REF] Huang | A scalable and adaptable ILP-Based approach for task mapping on MPSoC considering load balance and communication optimization[END_REF] is implemented for the initial mapping, with two differences: we have used constraint programming instead of ILP, and the objective function is the maximum period as it is our optimization goal. The workload used for the computation time of the actors is based on the profiling of Foreman video.

Findings

Data transport

The recorded number of packets are classified into two main categories. The first category includes the flits which are used basically for dataflow such as data transfer and requesting and setting FIFO indexes. The second category includes the induced flits by applying the remapping algorithm. The comparison shows that the additional flits induced by applying the MB algorithm forms less than 0.02% from total transported flits.

In addition, the impact of transferring the binary code on the traffic is evaluated. The percentage of flits transporting the binary code of migrated actors from the total number of transported flits in the network is computed while decoding several video sequences. The presented percentages illustrate that the impact of actor migration on the traffic is negligible (varies from 0.0008% to the 0.0348%. This variation depends on number of moves and the sizes of the binary codes of the moved actors.

Timings

It is noticed that applying the MB remapping algorithm affects the time-delay of the packets. The comparison with the case of ordinary decoding illustrates that using MB remapping decreases gradually the total packet time-delay. The traced graphs show that the total packet delay decreases after the conducted moves of actors. This refers to the fact that task remapping contributes in distributing the tasks on PEs that are nearer to the memory modules accommodating the input and output FIFOs.

Performance

The comparison of average FPS achieved when processing multitude video sequencing while adopting different remapping techniques shows that the MB algorithm achieves the maximum average performance enhancements of 26% and 14.11% when adopting ALTD and APTD respectively compared to the achieved throughput of processing the frames without remapping. Whereas, remapping using STM algorithm achieves a maximum average enhancement of 4%. Performance results of all decoded video sequences shows that the MB remapping outperforms STM remapping technique when considering either APTD or ALTD for estimating the NoC communication time delay. Also, the obtained results show that our method has not failed to enhance the performance for all target video sequences. Whereas, in some cases the STM method leads to deterioration in the performance. In fact, the STM method selects critical task to be moved in each observation window without estimating the resulting total performance gain. Moving the task without determining its effects on the whole system performance degrades the overall performance. While in our proposed algorithm, the maximum achieved total gain among all mapping combinations is first determined as explained. Accordingly, a task is specified to be moved if the estimated maximum total gain is positive. It is noticed that in some observation windows no tasks are moved when the MB algorithm is applied. In these cases, the estimation shows that no performance enhancement will be achieved for all mapping combinations. The results obtained from the "optimal" mapping approach proposed in [START_REF] Huang | A scalable and adaptable ILP-Based approach for task mapping on MPSoC considering load balance and communication optimization[END_REF] show that the MB algorithm, starting from a random mapping (without significant initial delay), performs better that the optimal with no remapping for Foreman video sequence in CIF format. Note that the "optimal" mapping corresponds to the best mapping found based on the profiling of Foreman video after a time out of one hour (like the original paper), and the optimality is not proven.

As the optimality is searched for the Foreman profile, we used the optimal mapping as a starting point for the MB algorithm, and the results show that it further improves the throughput. As expected, the optimal mapping for Foreman does not perform good for other video sequences (such as Ice video sequence in 4CIF format and Grandma video sequence in QCIF format).

The so-called optimal method cannot be used for two reasons. First it introduces an unpractical initialization delay without guaranty of optimality. Secondly, a static solution is not appropriate to data-dependent applications since a solution can be good for one data-stream and inefficient for another one and more importantly the efficiency of a mapping varies over time.

Perspectives

The notifying memory concept raises new opportunities and new challenges. At the hardware level, an exploration is needed to find out the size of the components: number of possible notifications per memory module, size of the listener. Accordingly, the hardware implementations are to be realized in order to determine the exact resources and energy consumption. Another challenge is to make the NI configurable or programmable for other models. At the software level, the compiler should detect the firing rules to appropriately separate the code onto the notifier and the listener. Finally, new scheduling policies could take advantage of notifications.

Concerning the research work about run-time remapping on heterogeneous MPSoC several we are planning to address several topics concerning the hardware architecture and algorithm. At the hardware level, the implementation of the integrated modules in the NIs and estimating their overhead in terms of area and energy will be done. Future work would also address the reduction of NoC power consumption. Another topic to be addressed is the moving of FIFO modules rather than actors. Novel algorithms would be devised targeting the reducing of the communication time and the impact of the migration cost of actors binary codes. Also, a study would be performed to indicate the impact of the size of the observation window used to monitor the metrics on the overall performance. An important work would be done to study the scalability of the devised architecture and its degree of heterogeneity (number and types of memories and processing elements).

In addition, it would be interesting to investigate the impact of using the notifying memories concept on the devised remapping algorithm in terms of performance and power consumption.

I. INTRODUCTION

M ULTIPROCESSOR system-on-chip (MPSoC) plat- forms have been emerging as the main solution to cope with processor frequency ceiling and power density issues while still improving performances. Then, networks-on-chip (NoCs) have been adopted to provide the increasing number of processors with the required communication bandwidth as well as with the necessary flexibility. But legacy code for instance, mainly designed for single or few core architectures, does not scale well with manycore architectures and fails to fully benefit from the available parallelism. However, as discussed decades ago [1], dataflow programming can address the limitations of conventional approaches regarding synchronization and shared memory issues. With the rise of massively parallel architectures, we can reconsider the use of dataflow programming as a solution to efficiently exploit the resources of parallel architectures for computing intensive application domains such as video coding, computer vision, machine learning and physics simulation for instance.

A dataflow application can be specified as a graph where nodes, called actors, process data called token(s). The computational models are based on First-In First-Out (FIFO) buffers and respect their formalized read and write rules. Each FIFO holds a set of tokens. Fig. 1(a) illustrates a network of actors, which exchange tokens through defined FIFO channels [2]. Fig. 1(b) presents an example of a structure of the software FIFO generated with the tool ORCC [3]. A network of actors holds specific features that make it different from a generic task graph. First, an actor is non-preemptive. Once started, an actor ends its execution. Second, the actor can start if and only if there are enough tokens as input, and enough space in the output FIFOs. The FIFOs are considered updated (i.e. tokens consumed and produced) at the end of the execution of the actor, establishing a conservative synchronization scheme, and preventing from any data race.

When the number of actors is larger than the number of processing elements (PEs), then the main design challenge is the mapping of actors on the network of PEs. In the case of static dataflow [4], where the number of tokens produced and consumed by the actors is known, an optimal solution can be computed offline [5]. However, an increasing number of applications cannot be specified with a static graph since the performance improvement of complex applications usually lead to context and data-dependent optimizations. This evolution is, for instance, significant in the domain of video coding. Dynamic models are then used to express data-dependent behavior of some applications [6]. Dynamic dataflow is a useful model of computation (MoC) for handling streaming data and video processing applications.

As the workload of an actor may change according to the input data set, adapting the mapping while the application runs is required to optimize the use of the computing and communication resources. The mapping problem is known as NP-complete. Heuristic methods, for a fast response time, are thus required to address manycore architectures. Runtime adaptation relies on system observation, decisions and configurations. Several previous works have addressed the problem of task mapping at run-time. In [7], the authors have proposed a dynamic resource balance algorithm targeting NoC-based Many-core homogenous platforms to enhance the system performance by balancing the utilization of on-chip computing resources and communication resources. In [8], the authors have introduced a hybrid application mapping that combines design-time analysis with run-time mapping in the context of dynamic thermal and reliability-aware resource management. Most of the available methods focus on determining the suitable mapping of tasks before starting the execution of the application [9], [10], [11], [12], [13], [14]. The mapping of actors is also an active topic for other target platforms like Coarse-Grained Reconfigurable Arrays (CGRA) [15] or Field Programmable Gate Array (FPGA) [16]. This research work addresses the problem of reconfiguring at run-time and at the application level the mapping of dataflow actors on heterogeneous processors. In this work, heterogeneous means that processors share the same instruction set architecture (ISA) while having different coprocessors and different clock domains. The proposed method, which is called run-time remapping, relies on continuous monitoring of exact performance metrics such as the computational time and communication time during real-time execution of the application. Accordingly, a new mapping of the involved actors is determined at run-time targeting the enhancement of the overall performance. This approach is sequentially repeated while the application is running. The application is neither suspended nor modified. The proposed remapping method meets with the dynamic behavior of dataflow applications. Static or offline mapping methods cannot capture the dynamic behavior and thus may not lead to optimal solutions. Also, on-the-fly and hybrid mapping methods suffer from a lack of means to monitor the performance and remap the actors accordingly. In order to apply the proposed method, the architecture of NoCs must be augmented to efficiently provide new services of monitoring performance metrics and remapping the actors, which are not available in conventional networks.

Adopting the devised remapping method and NoC-based architecture leads to balancing the workload. The obtained results show that the adoption of the remapping method reduces the standard deviations of the computational times and communication times of involved processors by 38.58% and 69% respectively. Thus, the variation of the use rate of processors is reduced compared to running the application without remapping. In addition, a reduction of 8.6% in the total execution time has been achieved as well as a reduction of 21% in the number of packets' hops is recorded when comparing to the execution without remapping.

In this paper we introduce three contributions:

• First, we optimize for a NoC-based architecture with het-erogeneous processors, a new run-time remapping (RR) algorithm based on the Move Based (MB) method [17], which allows only one actor to move at a time from one processor to another. Our solution is then compared with state of the art methods for dataflow architectures.

• Second, we present new NoC services that allow to implement the observation and adaptation mechanisms.

• Finally, we demonstrate our solution with a full implementation of MPEG4-SP, which is available as a reference of a typical dynamic dataflow application. It is also complex enough to exhibit data-dependent execution and communication times. We consider a SystemC packet cycle-accurate NoC simulator to fully decode reference videos and demonstrate the effectiveness of the adaptation mechanism with a real-life dataflow application. The rest of the paper is organized as follows. Section II presents the related work. Section III illustrates the adopted architecture model. Section IV describes the processing flow. Section V details the conducted experiments and presents the obtained results. Finally, Section VI concludes the paper.

II. RELATED WORK

The question of mapping parallel applications on multi or many-core architectures is a very wide problem, with a large number of dimensions, including the programming model, the target architecture (homogeneous or heterogeneous, bus-based or NoC-based, etc.), and the optimization goal (throughput, execution time, energy, etc.) [18]. The interested reader can refer to the paper gathering different mapping strategies for NoC-based architectures [19]. Following the taxonomy proposed in [18], the mapping problem can be solved based on two main strategies: design-time, and run-time. When solved at design-time, the mapping is called static since it's computed offline and does not change while the application runs. This approach allows for exact methods to find an optimal solution [20] [5] [15], but suffers from a lack of flexibility since it cannot capture the dynamic behavior of some applications. Moreover, even in the case of deterministic execution times of actors in a static context, the paper [21] interestingly shows the difference between the optimal mapping obtained from a well-formalized problem and the real execution trace, due to execution variabilities coming from the hardware.

The dynamic workload should be handled using run-time techniques. The run-time mapping strategies can themselves be divided into two categories: on-the-fly mapping, or hybrid mapping. On-the-fly mapping techniques are application-and platform-agnostic and solve the problem online. Very simple and efficient heuristics should be used to shorten the response time. For NoC-based MPSoCs, various fast heuristics targeting the reduction of communications under constraints have been already proposed [22] [23] [24]. These approaches consider one task per core. Allowing multiple tasks on one core is considered in [10]. Heuristics are fast but can be far from optimal solutions, so hybrid approaches have been introduced. They are based on pre-computed optimal solutions for a set of cases. The job is split into two phases: (1) at designtime, a set of solutions is computed, and (2) one solution 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 3 is selected at run-time. A wide variety of approaches can then be cited: based on traces in [25], on priority in [26], on scenario in [27], on previously identified design points in [28], or on WCET and scheduling in [29]. None of these studies demonstrates its efficiency with real video applications running reference sequences. The proposed real-time mapping reconfiguration method in [8] requires to suspend the currently running application and the manager remaps the tasks at runtime according to scenarios previously defined at design-time based on the evaluation of multiple mappings, optimizing for their resource requirements and power consumption. Finally, a last approach can fall into the family of hybrid mappings, which considers to recompute partially the mapping problem at run-time. This is called run-time remapping. The work presented in this paper follows such an approach for dataflow applications and leverages design-time analysis profiling results to find at run-time a first mapping. The application is then monitored to update the profiling results and a run-time remapping algorithm runs regularly to check if a new mapping would be better than the current one. Among the innumerable papers dealing with task mapping, we consider run-time methods for dataflow tasks, and have identified a limited number of solutions. In [30], the mapping is modeled as a graph partitioning problem, and the problem is solved at run-time by METIS tool, based on profiling information obtained by a first run. Though the migration cost of the actors is not taken into account, the results are promising and could be improved if the mapping does not change completely at each iteration. The approach in [17] allows to successively refine the mapping according to the dynamic behavior of the application, by allowing only one actor to move at a time from one processor to the other. This approach assumes dynamic dataflow application and the target architecture is composed of several heterogeneous cores interconnected by a bus or a NoC. The communication cost is computed based on a rough analytical model of the interconnection network, with the loss of accuracy that comes with it, whereas in our work, we consider profiled values gathered automatically by the system, with a finer grain down to the link. In [31], the application is specified with KPN (Kahn Process Network) and the target architecture is a shared-memory based MPSoC, with also a model of the communication channel (bus or NoC). The approach proposes to rely on three main steps: the two usual design-time preparation and run-time mapping steps plus a new customization step. The design time step computes a set of candidates and populates a database. The run-time mapping initialization derives from the candidates a new initial mapping for the given workload. Finally, the run-time customization step incorporates a Scenario-based run-time Task Mapping (STM) algorithm that is applied to find new mapping of tasks when the system detects that an objective is unsatisfied. It first detects the so-called critical task and then identifies why it misses its objectives: either poor locality or load imbalance. In case of poor locality, an algorithm that considers the communication between tasks is used to find a new mapping. In case of load imbalance, a load balancing strategy based on computational demands of the tasks is used. This step produces a new mapping that may move several tasks, which leads to a (re-)mapping overhead.

When focusing on the small subset of the existing work around hybrid and run-time (re-)mapping of dataflow applications on NoC-based architectures, we consider the work presented in [31] for comparison.

III. ARCHITECTURE MODEL

The target architecture is a heterogeneous Multi-Processor System on Chip (HMPSoC) containing several different PEs and shared memories connected with a Network-on-Chip (NoC). Fig. 2 presents the structure of the adopted NoCbased architecture. Our method is scalable and without loss of generality we consider a specific model of architecture which is required for a data-accurate functional simulation with a packet-level time accuracy. The target architecture is a 4 × 4 mesh-based NoC with 32-bit links that interconnects 28 intellectual property (IP) cores including 15 memory modules, 12 PEs and a processing element that acts as a manager (MGR). The PEs and memory modules are technologically independent of the structure of the NoC. They communicate through the network using a network interface (NI). We consider a simple NoC model that employs the wormhole packet switching mode, the deterministic XY routing algorithm, and a flow control policy without virtual channels. The implemented routers have one buffer of 3 flits per input port and use distributed arbitration logic (one arbiter per port). The back-end part of the NI is typical and includes a packet maker/un-maker, which are used to assemble and disassemble the packets, and a priority manager to synchronize packet transmission and reception.

In this work, it is assumed that P E1 imports the incoming streamed data from an Input buffer and P E12 outputs the processed data. Fig. 2 illustrates the buffers in order to communicate with external systems. Each PE has its local memory. It is assumed that there are no restrictions to map any MPEG4-SP application actor to any PE. The used PEs can all work in parallel according to dataflow firing rules. However, some PEs are enhanced by hardware accelerators dedicated to certain functionalities in order to perform them more efficiently. The shared memories are distributed in memory blocks which have a unique NI. From an NoC perspective, the novelty is the introduction of new command packets used as instructions to manage FIFO accesses, broadcast mapping information, collect monitoring data, and the transfer of binary codes. In order to cope with the command packet and associated notification packet concepts, the NIs implement some additional logic modules. The command packets were already proposed in [32] but only produced by the manager and for a specific application.

A. Manager

The manager is a PE dedicated to the following five tasks:

(1) map initially the actors on the available PEs, (2) parse the feedback collected data from all modules (memories and PEs), (3) apply the run-time remapping algorithm and selects the actor to be moved (if any), (4) notify the corresponding PEs (looser, gainer, etc.) about the updated mapping and (5) manage the transferring of the binary code corresponding to the moved actor from the shared memory into the cache of the gainer processor.

B. Processing Elements

The target platform includes twelve PEs. All PEs are supposed to be able to execute any of the forty-one actors involved in the MPEG4-SP application. As the number of PEs is smaller than the number of actors, each PE is considered to run more than one actor. Hence, an actor scheduler is required to manage the order of execution of actors. Mainly, in dataflow applications, all schedulers suffer from inefficient polling which leads to useless memory accesses when a scheduling attempt fails. In this work, the well-known roundrobin scheduling technique has been adopted in all PEs. The actors are given the attempt to be executed in a circular order without priority. The PE will execute the allocated actor if there are enough input tokens and enough space in the output FIFOs as specified in dataflow applications.

Furthermore, some PEs are augmented with hardware accelerators in order to perform special functions more efficiently. In this work, we adopt one of the hardware accelerator specification described in previous similar work [17]. Table I shows the list of accelerators adopted in the simulation platform. In addition, the PEs have been specified randomly to operate on different frequencies. Table II shows the randomly chosen operating frequency of all PEs in terms of the NoC operating frequency f .

C. Memory Modules

The tailored platform integrates three types of memory modules. Each module includes a memory block that returns the data allocated at its specified address. Since the PEs and the manager do not recognize the local mapping of stored data

PE ID Operating Frequency PE1, PE12, MGR f PE2, PE6, PE10 2f PE3, PE7, PE11 3f PE4, PE8 4f PE5, PE9 5f
in each memory module and in order to remain compliant with any available memory, the typical NI is extended to accommodate the services for managing the addressing and arranging the retrieved output bits into flits. These new functionalities are implemented as additional components in the front-end of the NI corresponding to each memory module type in order to be independent of NoC parameters. In the following the functionalities of each memory type is described. 1) Binary code memory module (BCM): It contains the binary codes of all actors. The manager sends a specific packet request to BCM to forward the binary code of the moved actor to a given PE according to the decision taken after executing the RR algorithm. A simple module, so-called memory address mapper (MAM), is integrated into the NI of the BCM in order to find the correct memory address. For a specific actor, MAM determines the starting address of the binary code and its corresponding size based on the actor's ID and by the means of simple look-up-tables that include the starting addresses and the size of the binary codes of all actors. Furthermore, MAM manages the extraction of data from the memory and delivers it to the packet maker unit.

2) Mapping/Monitoring information memory module (MIM): This memory module accommodates twelve memory blocks. Each block is dedicated to a specific PE and is supposed to store two types of data. The first type is the mapping information, which is generated by the manager and indicates which actors are to be executed by each PE in addition to their supplementary information about input and output FIFOs and the reading orders for each input FIFO (III-D1c). The second type is the monitoring information (III-D1e), which is collected by the PEs during processing a specified number of video frames. Storing the monitoring information overwrites the mapping information, which is not needed by the PEs anymore.

When a packet holding either mapping or monitoring information is received, the MIM module first identifies the corresponding PE. Accordingly, it dissembles the packet and stores the data found in the packet payload into the memory block assigned to the identified PE.

Moreover, the MIM informs the manager about the availability of new monitoring information and the corresponding PE about the availability of new mapping information. To do so, the MIM sends notification packets (III-D1a) as per the concept of notifying memory concept demonstrated in [2]. In addition, the MIM responds to reading requests (III-D1b) sent from the manager to acquire the stored monitoring information from the PEs or to get the new mapping information.

3) Multi-FIFO memory module (MFM): This type of memory module is dedicated to store the data which is either Writing address reaching data size imported to the system or processed by the PEs. Each MFM accommodates a specific number of FIFOs. Only one FIFO is used at once. The inputs of all FIFOs are connected to the module's inputs using demultiplexers whereas the FIFOs' output data ports are multiplexed. This signal is buffered from the value of FIFO address which is specified in the payload of the arriving packets (see Fig. 4). The multiplexer and demultiplexers are added to the adapter in the NI. Moreover, the MFMs receive the following types of packets: (1) FIFO Index packet (III-D1f) that aims either to retrieve or to set the writing and reading indexes, (2) Data Reading Request packet (III-D1g) that demands to read data from a specified FIFO and (3) Data packet (III-D2a) that is used to write data in a specified FIFO.

A simple circuit is integrated into the adapter of the NI in all MFM modules in order to manage the memory addressing for all listed-above packet types. It is composed of a simple controller and two 4-to-1 multiplexers and an adder in order to generate the appropriate address values to be given to the MFM FIFOs. After disassembling the arriving packet, the packet un-maker delivers the packet type and the data size to the controller. Accordingly, the controller generates the control signals to configure the two multiplexers, which are dedicated to select the values of starting address and the offset as listed in Table III. These two values are then added to compute the memory address. In addition, the controller determines the number and type of the required memory accesses. It incorporates a simple comparator and an address counter which is incremented for each required access.

D. Packets' structure

The developed NoC architecture considers two categories of packets: (1) command packets and (2) data packets.

1) Command packets: Command packets are initiated by the cores and processed by the NIs of destination nodes. Several command packets, described hereafter, have been opted in order to manage FIFO accesses, send mapping information, collect monitoring data, and manage the transferring of binary codes.

a) Notification packets (NP): The NPs aim to inform the PEs that new information is ready to be requested. This technique is inherited from the notifying memories (NM) concept presented in [2]. When receiving a NP, the PE will send a reading request to retrieve the available data at the corresponding notifying memory. In this work, notification packets are used either to inform an ordinary PE that new mapping information is available or to notify the manager that updated monitoring information has been generated and stored. The NP has empty payload and aims to trigger the manager and PEs to request data when it is ready rather than frequent inefficient polling.

b) Monitoring/Mapping information reading request packets (MRP): This type of packet is used to request the information stored in the MIM module as a response to the NP. It is either generated by the manager to acquire the new monitoring information sent from a definite PE or by one of the PEs to get the new mapping information provided by manager. For both information types, monitoring or mapping information, the request packet does not include any payload.

c) Mapping information packets (M p IP): The manager uses a M p IP to inform all involved PEs after determining or modifying the actor mapping strategy. Its payload includes the following: (1) the number of actors which are mapped to the PE, (2) the IDs of the mapped actors, (3) the IDs of the input and output FIFOs, and (4) the actor reading order in each input FIFO. Fig. 3 illustrates the structure of the packet holding the mapping information.

d) Mapping Confirmation packets (MCP):

A MCP aims to inform the manager that the new mapping information is well received by both the former and the new owner of the actor. The MCP payload is also empty.

e) Monitoring information packets (M n IP): This type of packet holds the feedback information needed by the manager to perform the RR algorithm. Fig. 3 presents the structure of the monitoring information packet.

f) FIFO index packets (FIP): The FIPs are designed to hold the writing indexes or reading indexes of FIFOs. As mentioned before, DF applications rely on a large number of requests to memories for firing rule checking. So, these indexes are used to determine either the number of available tokens corresponding to each reader actor or the free space in a FIFO. If data is required to be read from input FIFOs, the firing rule is satisfied by checking if the number of available tokens in all input FIFOs is equal or greater than the required number during computation. Whereas, if data has to be written to output FIFOs, the firing rule is satisfied by checking if all output FIFOs have sufficient empty room to accommodate the produced tokens. Hence, before processing an action, a PE

Holding read/write index.

As the FIFO may have several reading indexes corresponding to different reader actors, the PE has to determine the reading order of the actor and sends it in the payload of the packet. However, a FIFO has only one writer actor; hence, to attain the value of its writer index the PE has to send the FIFO address in the destination memory module. In both packets, the packet type, given in the packet's header, is used by the NI at the destination memory module to decode the request type. Fig. 4 depicts the structure of the FIP packets holding the requests of a reading index and writing index.

On the other side, whenever a memory module receives a request of reading/writing index it will retrieve its value from the specified FIFO and sends it back to the PE. The NI in the memory module will assemble a 1-flit payload packet as shown in Fig. 4.

In order to set the reading/writing index after finalizing the data transfer operations from/to a FIFO, the PE sends a control packet that notifies the FIFO about its new reading/writing index. It includes one flit that contains the FIFO address in the destination memory module, the reading order of the actor, and the new value of the reading index. Since the FIFOs have only one writer actor, the writing packet payload simply includes the address of the targeted FIFO in the destination memory module and the new value of the writing index.

g) Data reading request packets (DRP): Fig. 5 presents the packet holding the reading request of data from PE to memory module. Its payload consists of one flit that includes the address of the FIFO in the destination memory module, the starting address of reading, and the size of required data. be transferred from the shared memory to the cache of the new PE. The manager sends a command of transferring the binary code in the form of a reading request packet. The sent request includes the actor ID, the address of the new PE, and the size of transferred data per packet (see Fig. 6).

2) Data packets: The second category of packets refers to the ordinary flow of data between PEs and memory modules. These packets, described hereafter, carry data that is either processed in a PE and written in a memory module or sent from a memory module as a response to a PE reading request.

a) Dataflow packets (DFP): The DFPs encompass all packets transferred between PEs and the FIFOs distributed in the memory modules. They carry data that is either processed in a PE and will be stored in a FIFO or sent from a FIFO as a response to a PE reading request. Fig. 7 presents the structure of packets carrying processed data in their payloads.

b) Binary code packets (BCP): The BCPs aim to transfer the binary code from the shared memory to the cache memory of the new PE. Note that the binary code is divided into sections of reasonable sizes which are transferred consequently. The size of the transferred data (payload capacity) is specified by the manager according to the monitored traffic in the network and based on the required cache lines to be filled before launching the actor on the new PE. For example, the packet including in its payload 64 flits of 32-bitwidth transfers 256 bytes which form 4 lines of L1 cache.

IV. PROCESSING FLOW

A. Initial mapping

Initially, the actors are mapped randomly to the PEs, or can be mapped using the exact method presented in [20]. FIFOs are mapped randomly and are approximately equally distributed on all memory blocks. The manager informs by means of packets all involved PEs. For each PE in charge of executing actors, the manager generates and sends its corresponding mapping information in a separate packet (M p IP). Packets holding the mapping information are stored in a predefined location in MIM. Then, the involved PEs are notified to retrieve their mapping information from the shared memory using notifying packets. At this stage, the manager waits the PEs, which are incorporated in processing a specific number of video frames N F to send their monitoring information. Note that N F is set originally to a default value and may be changed dynamically by the manager. Before receiving the notification packet about initial mapping of actors, all PEs are in idle state. Once it receives the notification packet, the PE sends a request to retrieve the mapping information which includes IDs of actors to be executed, IDs of input and output FIFOs for each actor, and the reading order of each input FIFO. The mapped actors are scheduled according to the order sent from the manager and the PE begins to execute them in round-robin manner.

B. Monitoring actor execution

The execution of actors continues until receiving a new notification packet about changing the mapping information. All involved PEs monitor their running actors during the processing of N F video frames, which determine the observation window. Precisely, each PE node accumulates for every mapped actor A c its communication time

T cm [A c ], computation time T cp [A c ],
and total number of tokens received to each input port N T total [A c[I j ] ] where c ∈ {1, ..., |A|} and j ∈ {1, ..., |I c |}. In addition, the adapter, which is embedded in the NI of each node n (processor or memory), extracts from each received packet carrying processed data, the following information for each source S i : (1) the total number of transferred tokens from S i to n: N T n total [S i , n] and (2) the average time delay consumed per token to reach the node n from source S i : T av [S i , n].Table IV gathers the variables and parameters used to formalize our mapping approach.

The total number of transferred tokens is simply determined. First, input packets are classified according to their sources S i . Then, their corresponding sizes size Pk [S i ], which reflect the number of data-flits, are accumulated.

N T n total [S i , n] = K k=1 size Pk [S i , n] (1)
where i ∈ {1, ..., |P| + |M|}.

The average time delay per token per each source T av [S i , n] is calculated by dividing the time delay of each token transferred from

S i by N T total [S i , n]. T av [S i , n] = K k=1 size Pk [S i , n] × D Pk [S i , n] N T n total [S i , n] (2)
where k ∈ {1, ..., |K|}.

D Pk [S i ] is determined by embedding, at the source node, for each packet P k its sending time-stamp T s [P k ] in its header then subtracting it from the reception time T r [P k ] at the destination node. All tokens in a packet are considered to have the same delay.

D[P k ] = T r [P k ] -T s [P k ] (3)

C. Collecting monitoring information

When the number of the processed frames meets the observed window, each PE node generates its own monitoring information packet. The packet is then sent to the MIM module (presented in III-C). Directly, the accumulated values are reset with the beginning of the new observation window. Then, the PE continues executing the previously mapped actors according to the adopted circular order. This guarantees that the remapping does not impose any additional overhead in terms of latency. The MIM module notifies in its turn the manager when new monitoring data is available corresponding to a specific processor throughout a notification packet (III-D1a). Whenever a new notification packet is received by the manager, the latter directly requests to retrieve the new available monitoring data. Also, the manager requests using command packets from all memory modules to send their monitoring information. Note that memory modules respond to the manager and send the requested data directly without any notification process since the adopted MoC allows the direct communication between a memory and a processor. All received monitoring packets are disassembled and their contents are parsed and saved in the manager local registers.

When the feedback data is collected from all modules incorporated in processing the video frames, the manager applies the run-time remapping algorithm. At this stage, the manager owns locally the following data: (1) the communication time of each actor:

T cm [A c ], (

D. Estimating NoC communication time delay

Communication time delay is a critical factor in HMPSoC platforms using NoCs. The communication time of the moved actor is affected by the location of the new hosting PE in the network. NoC time-delay estimation impacts directly the prediction process of the communication time of the moved actor. Hence, the accuracy level in estimating the delay latency changes the decision on the actor move in the RR algorithm. In this work, two novel methods have been proposed to estimate the communication time delay for transferring one token in the NoC. The first method is called the average-path token delay and it is based on finding the average delay for transferring one token depending on the path delays between all nodes of the NoC. The second is called the average-link token delay and considers the time-delay of the token according to the used physical links connecting the NoC components while transferring the token. Both proposed methods make use of the monitoring data, which is collected while processing N F video frames in the previous observation window. The techniques used in estimating the NoC communication time-delay are described in the following subsections.

1) Average-path token delay (APTD):

In this approach, a path is considered to be formed from the set of the interconnections between two specific nodes. As an example, Fig. 8 illustrates in red the path P [P E1,M F M6] between processing element P E 1 to memory module M F M 6 . As a deterministic routing is applied in this work, the packets always use the same path between the source node and the destination node. Since the adopted MoC forbids the transfer of packets in between memory modules and in between PEs, the active paths are those connecting either memory modules to PEs or PEs to memory modules. Note that the packets transferred from a processing element p to a memory module m do not follow the same path used in transferring packets from the memory module m to the processing element p. Fig. 8 illustrates in red the followed path to transfer packets from P E 1 to M F M 6 and in yellow the followed path to transfer packets from M F M 6 to P E 1 . In APTD, the manager calculates the average path delay per token T av in several steps as shown in Algo. 1. T av refers to the average time delay required to transfer one token from the source node to the destination node, regardless of the path between the source and destination nodes. As an example, the average time delay of all tokens transferred through either the path P [P E1,M F M6] or the path P [M F M6,P E1] (Fig. 8) is considered equal regardless of the number of links constituting each path and the corresponding traffic in each link and the switch conflicts in the connecting routers. T av is computed by dividing the sum of the communication-time delays D total by the total number of transferred tokens in the network N T total :

T av = D total N T total (4)
The manager benefits from the collected monitoring data. It makes use of the number of input tokens N T n total [S i , n] transferred to each destination node n from each source node S i to determine the total number of all transferred tokens in Algorithm 1 Average-path token delay (APTD)

Step 1: Find the sum of the communication delays D total

Step 2: Find the total number of all tokens N T total

Step 3: Calculate the average time delay per token T av the network (N T total ) as presented in ( 5):

N T total = |P|+|M| n=1 |P|+|M| i=1 N T n total [S i , n] (5)
Also, the communication-time delays for all tokens transferred in the network are accumulated. The sum of the communication delays D total is determined according to (6):

D total = |P|+|M| n=1 |P|+|M| i=1 T av [S i , n] × N T n total [S i , n] (6)
where T av [S i , n] is the collected average time delay required to transfer one token from the source node S i to the destination node n.

2) Average-link token delay (ALTD): A link is defined as the interconnection between two consecutive components of the NoC: Router, Memory and PE. As an example, Fig. 8 shows the links constituting the path P [P E1,M F M6] . In this approach, the average communication time delay per token is determined for each link as shown in Algo. 2. The total communication-time delay in a path P [Si,n] connecting the source node S i and the destination node n is determined from the monitored data as shown in ( 7):

D P total [S i , n] = T av [S i , n] × N T n total [S i , n] (7)
D L av [S i , n] = D P total [S i , n] N L[S i , n] (8)
where N L[S i , n] is the number of links constructing the path

P [Si,n] .
Here, the links constructing a path are assumed to have similar contribution in the total communication time delay monitored in the path. As a link l is shared among different paths, the total link communication-time delay D total [l] is the sum of all average communication-time delay per link computed in all paths in which link l constitutes one of their interconnections:

D total [l] = |P|+|M| n=1 |P|+|M| i=1 D L av [S i , n] ∋ l ∈ L P[S i ,n] (9)
On the other hand, the tokens passing through a path are definitely passing through all links constructing the path. Hence, the total number of tokens N T total [l] passing through a link l is the sum of all tokens passing through all paths, which link l constitutes one of their interconnections:

N T total [l] = |P|+|M| n=1 |P|+|M| i=1 N T total [S i , n] ∋ l ∈ L P[S i ,n] (10
T av [l] = D total [l] N T total [l] (11)

E. Applying RR algorithm

For each observation window (N F frames), the manager executes at run-time the RR algorithm, which is divided into two main steps. The first step is dedicated to find all possible candidate actors which their moves would enhance the overall throughput. The second step sets a tradeoff between the cost of migration and the predicted improvement of the performance.

1) Specify the possible candidate actors: In this work, the definitions of the terms period of each processor p (P eriod p ), maximum period (P eriod max ) and throughput (T h) have been adopted as introduced in [17]. P eriod p is the sum of total computation time compT p and total communication time commT p recorded during N F video frames:

P eriod p = compT p + commT p ∀p ∈ P (12) where compT p and commT p of processor p are the sums of the computation times and of the communication times respectively of all actors which are mapped on this processor:

compT p = k:P[k]=p T cp [A k ] ∀p ∈ P ( 13
)
commT p = k:P[k]=p T cm [A k ] ∀p ∈ P (14)
The throughput is defined as the inverse of the maximum period over all processors. Hence, the first task is to find the PE with the maximum period. The manager computes the periods of all PEs during the current observation window of N F video frames. Later, a simple comparison between all obtained period values is performed in order to specify the processor with the maximum period. The processor with the maximum period (P eriod max ) is nominated as looser processor. The algorithm used to determine the looser processor is outlined in Algo. 3. The set of candidate actors to be moved C includes the actors that have been previously executed by the looser processor. Fig. 9 demonstrates an example of P eriod p and P eriod max . The figure shows three PEs (P E 1 , P E 2 and P E 3 ) that run six actors (A 1 , A 2 , A 3 , A 4 , A 5 and A 6 ). In this example, P E 1 has the largest period, thus it is selected as the looser processor.

Algorithm 3 Finding processor with maximum period P eriod max ← 0 looser ← ϕ for p ∈ P do if P eriod max < P eriod p then P eriod max ← P eriod p looser ← p end if end for 2) Decision of the actor move: The actor selected to be moved should have a maximum total gain. According to the collected monitoring values, the manager estimates the total gain achieved for all combinations of mapping the actors which belongs to the candidate list C onto all available PEs. The estimated total gain Gain e total [C Ac,p ] of a mapping combination C Ac,p , which corresponds to moving A c to p, is computed by finding the difference between the estimated performance gain Gain e per [C Ac,p ] and the estimated migration cost of the actor Cost e mig [C Ac,p ]. The mapping combination that leads to the maximum estimated total gain is then selected. The engaged processor and actor are specified and so-called the gainer processor and moved-actor respectively. a) Estimated performance gain: For each actor A c in the candidate list C, the manager considers it is moved virtually to all PEs except the looser processor. For each virtual-move combination, the manager estimates the achieved period of each processing element P eriod

) Note that the tokens, which are consumed by a certain reader actor running on a processing element P E R , are imported from a FIFO f . These tokens are previously generated by another actor running on another processing element P E W . The generated tokens are first stored in a FIFO f and then transferred once requested to the processing element P E R where the reader actor is executed. Hence, the tokens pass

𝑃𝑒𝑟𝑖𝑜𝑑 𝑃1 𝑃𝐸 1 𝑇 𝑐𝑝 [𝐴 1 ] 𝑇 𝑐𝑚 [𝐴 1 ] 𝑇 𝑐𝑝 [𝐴 2 ] 𝑇 𝑐𝑚 [𝐴 2 ] 𝑇 𝑐𝑝 [𝐴 3 ] 𝑇 𝑐𝑚 [𝐴 3 ] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑃2 𝑃𝐸 2 𝑇 𝑐𝑝 [𝐴 4 ] 𝑇 𝑐𝑚 [𝐴 4 ] 𝑇 𝑐𝑝 [𝐴 5 ] 𝑇 𝑐𝑚 [𝐴 5 ] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑃3 𝑃𝐸 3 𝑇 𝑐𝑝 [𝐴 6 ] 𝑇 𝑐𝑚 [𝐴 6 ]
𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑡𝑖𝑚𝑒 Fig. through two paths. The first path P [P EW ,M F Mf ] connects the processing element P E W , which executes the writer actor, and the memory module that accommodates the FIFO f . On the other hand, the second path P [M F Mf ,P ER] connects the memory module that accommodates the FIFO f and the processing element P E R which executes the reader actor. The communication-time delays in both paths are considered when estimating the communication time of the moved actor.

When adopting APTD method for determining the communication delay in the NoC, the estimated communication-time delay per input j for each actor A c is equal to the total number of input tokens N T total S[A c[I j ] ] transferred to the actor at this input multiplied by the double of the calculated average path communication-time delay per token T av (4). The average path delay per token is doubled to compensate the time delay of the two paths P [P EW ,M F Mf ] and P [M F Mf ,P ER] . The total estimated communication time is the sum of all estimated communication-time delays of all inputs:

T e cm [C Ac,p ] = |Ic| j=1 2 × T av × N T total [A c[I j ] ] (16)
Note that the adopted model of computation forbids the transfer of tokens in between actors (running on PEs) directly without passing through a FIFO (allocated in a memory module M F M f ). Hence, tokens produced by the writer actor (running on P E W ) will pass through two paths (P [P EW ,M F Mf ] and P [M F Mf ,P ER] ) before arriving to the reader actor (running on P E R ). The exact number of tokens passes through both paths while considering same average path delay per token T av . So, the average path delay per token is doubled in (16).

When adopting ALTD method, the estimated communication-time per input j is equal to the total number of input tokens N T total [A c[I j ] ] transferred to the actor A c through this input multiplied by the sum of all average communication-time delay per token T av [l] for each link l constructing the paths which the input tokens use to reach the processing element running the actor A c . The total estimated communication time will be the sum of all estimated communication-time delays of all inputs:

T e cm [A c ] = |Ic| j=1 i=1 T av [l i ] × N T total [A c[I j ] ] ∋ l i ∈ L P[P E W ,M F M f ] ∪ L P[MF M f ,P E R ] (17)
In addition, the estimated computation time T e cp [C Ac,p ] of the moved actor A c is determined depending on the recorded computation time of the moved actor A c during the previous mapping T cp [A c ] and the estimated total speed-up ratio SU e total [C Ac,p ], which is achieved when moving A c to p:

T e cp [C Ac,p ] = T cp [A c ] × SU e total [C Ac,p ] (18) such that SU e total [C Ac,p ] = A Ac [p] A Ac [looser] × f [looser] f [p] (19)
where f [p] is the operating frequency of processor p (Table II) and A Ac [p] is the acceleration enhancement ratio of the moved actor A c when running on processor p (Table I).

Note that for all mapping combinations, the period of the looser processor is modified when an actor A c is supposed to be mapped to another processor p. Hence, it is updated by subtracting the actual communication time T cm [A c ] and the actual computation time T cp [A c ] of the moved actor A c :

P eriod e looser [C Ac,p ] = P eriod max -T cm [A c ]-T cp [A c ] (20
) For each mapping combination, the manager determines the maximum estimated period P eriod e max [C Ac,p ] which denotes the maximum period among all processors when actor A c is mapped to processor p. These computed new periods are then used to find the performance gain related to each mapping combination:

Gain e per [C Ac,p ] = P eriod e p [C Ac,p ] -P eriod max (21) b) Estimated migration cost:
The migration cost of an actor is the required time to transfer its binary code into the local memory of the new hosting processing element. It depends on the size of the binary data required to be transferred and the communication-time delay in the network. The sizes of the binary codes of all actors are considered to be known by the manager in terms of number of flits. Accordingly, the migration cost of the moved actor is estimated by the manager using the estimated NoC communication-time delay. When adopting APTD method, the estimated migration cost related to the moving of actor A c to processor p is calculated as expressed in (22):

Cost e mig [C Ac,p ] = size bin [A c ] × T av (22)
where size bin [A c ] is the size of the binary code of actor A c and T av is the average path communication-time delay per token (4). When ALTD method is adopted, the migration cost of the moved actor A c is determined by (23):

Cost e mig [C Ac,p ] = size bin [A c ] × i=1 T av [l i ] ∋ l i ∈ L P[BCM,p] (23)
c) Estimated total gain: The manager computes the total gain estimated to be achieved for all mapping combinations by finding the difference between the estimated performance gain Gain e per [C Ac,p ] and the estimated migration cost of the actor

Cost e mig [C Ac,p ]. Gain e total [C Ac,p ] = Gain e per [C Ac,p ] -Cost e mig [C Ac,p ] (24)
The moving of an actor would lead to permanent performance gain and the migration cost is paid once. However, the estimated performance gain takes the cost of migration into account in order to aggravate the probability of enhancing the overall performance directly after applying the move (in the next observation window). In fact, the variation of the input data and its corresponding effects on executing the

𝑃𝐸 1 𝑇𝑐𝑝 𝑒 [𝐶𝐴 1,𝑃𝐸3 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 1,𝑃𝐸3 ] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴1,𝑃𝐸2 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝[𝐴3] 𝑇𝑐𝑚[𝐴3] 𝑇𝑐𝑝[𝐴2] 𝑇𝑐𝑚[𝐴2] 𝑡𝑖𝑚𝑒 𝑃𝐸 1 𝑇𝑐𝑝 𝑒 [𝐶𝐴 1,𝑃𝐸3 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 1,𝑃𝐸3 ] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴1,𝑃𝐸3 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝[𝐴3] 𝑇𝑐𝑚[𝐴3] 𝑇𝑐𝑝[𝐴2] 𝑇𝑐𝑚[𝐴2] 𝑡𝑖𝑚𝑒 𝑃𝐸 1 𝑇𝑐𝑝[𝐴1] 𝑇𝑐𝑚[𝐴1] 𝑇𝑐𝑝[𝐴2] 𝑇𝑐𝑚[𝐴2] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴3,𝑃𝐸3 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝 𝑒 [𝐶𝐴 3,𝑃𝐸3 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 3,𝑃𝐸3 ] 𝑡𝑖𝑚𝑒 𝑃𝐸 1 𝑇𝑐𝑝[𝐴1] 𝑇𝑐𝑚[𝐴1] 𝑇𝑐𝑝[𝐴2] 𝑇𝑐𝑚[𝐴2] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴3,𝑃𝐸2 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝 𝑒 [𝐶𝐴 3,𝑃𝐸2 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 3,𝑃𝐸2 ] 𝑡𝑖𝑚𝑒 𝑃𝐸 1 𝑇𝑐𝑝[𝐴1] 𝑇𝑐𝑚[𝐴1] 𝑇𝑐𝑝 𝑒 [𝐶𝐴 2,𝑃𝐸3 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 2,𝑃𝐸3 ] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴2,𝑃𝐸3 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝[𝐴3] 𝑇𝑐𝑚[𝐴3] 𝑡𝑖𝑚𝑒 𝑃𝐸 1 𝑇𝑐𝑝[𝐴1] 𝑇𝑐𝑚[𝐴1] 𝑇𝑐𝑝 𝑒 [𝐶𝐴 2,𝑃𝐸2 ] 𝑇𝑐𝑚 𝑒 [𝐶𝐴 2,𝑃𝐸2 ] 𝑃𝐸 2 𝑇𝑐𝑝[𝐴4] 𝑇𝑐𝑚[𝐴4] 𝑇𝑐𝑝[𝐴5] 𝑇𝑐𝑚[𝐴5] 𝑃𝑒𝑟𝑖𝑜𝑑 𝑚𝑎𝑥 𝑒 [𝐶 𝐴2,𝑃𝐸2 ] 𝑃𝐸 3 𝑇𝑐𝑝[𝐴6] 𝑇𝑐𝑚[𝐴6] 𝑇𝑐𝑝[𝐴3] 𝑇𝑐𝑚[𝐴3]
𝑡𝑖𝑚𝑒 Fig. 10. An example of finding the maximum periods for each mapping combination involved actors incites to consider worst case (severe) decision where the performance enhancement should be guaranteed once moving the actor. Then, the manager finds the maximum achieved total gain among all mapping combinations and accordingly specifies the actor to be moved and the gainer processing element.

F. Moving the actor to the gainer processor

The PE, after finishing the execution of the current running actor, retrieves the new mapping information and sends directly a confirmation packet so that the manager processor manages the transfer of the object code corresponding to the new mapped actor. Before running the moved actor, the Algorithm 4 Run-time Remapping (RR)

Step 1: Calculate the period of each PE

Step 2: Find PE with Max. period and assign it as looser

Step 3: Find the total gain (performance -migration cost) for each move do a-Find the performance gain . find the period for each PE . find the maximum period b-Find the migration cost c-Calculate the total gain end for Step4: Choose the move with Max. positive total gain PE checks the availability of the object file corresponding to the actor in its cache memory. Note that for the initial mapping, the manager generates and sends packets to all PEs in charge of executing actors. Whereas, after executing the RR algorithm, the manager informs only the gainer and looser processors. This procedure reduces the traffic in the network and maintain the processing performance since the PEs that are not affected by remapping process are not disturbed. In fact, the manager informs first the looser processor about the new mapping information. Then, it waits until the looser processor confirms the well reception. The looser processor sends a confirmation packet to the manager whenever it finishes the execution of the moved actor. When the manager receives the confirmation packet, it sends the new mapping information to the gainer processor. Later, the gainer sends a confirmation packet to the manager that directly manages the transferring of the object code of the mapped actor from the shared memory into the cache memory of the gainer processor by making use of BCPs described in subsection III-D2b. This guarantees that the actor is executed by only one PE in the whole platform and ensure better controlling of the traffic while migrating the binary codes. In fact, the manager sends a CTP (subsection III-D1h) which includes the ID of the gainer processor, the ID of the moved actor and the size of the BCPs (capacity) as described in subsection III-C1. After receiving the CTP, the MAM module, which is integrated into the NI of the BCM (subsection III-C1), manages retrieving the binary code from the shared memory and dividing it into sections according to the capacity specified by the manager. The generated BCPs will be transferred to gainer processor. In our work, we consider that the gainer processor can start executing the actor once at least 256 bytes, which construct 8 lines of the L1-I cache, are received and stored to the gainer processor local memory. The hierarchy of the PEs' local memories includes L1 and L2 caches. L1 cache is broken up into to halves, instruction (L1-I) and data (L1-D) each of 32KB. L2 cache size is of 256KB and is used for instructions and data.

G. RR Algorithm Complexity

The devised algorithm consists of several steps summarized in Algo. 4. The complexity of each step is illustrated to determine the overall complexity. The complexity of Step1, Note that the algorithm is computed when all monitoring data is collected, so the maximum rate is once per execution of the whole data flow, and in practice can be tuned to be slower. With respect to the complexity and the execution rates of actors, this complexity is extremely low.

V. EXPERIMENTS AND RESULTS

A. Application Model

In this work we target the multimedia application domain. We adopt the well-known MPEG4 part 2 Simple Profile video decoder (MPEG4-SP). This multimedia application is typically used in de-compression of encoded video digital data. Fig. 11 presents the structure of decoder as described in Reconfigurable Video Coding framework (RVC) [3] [33].

MPEG4-SP is specified with heterogeneous dataflow MoCs and includes up to 40% of dynamic actors [34]. It is composed of 41 actors and 70 FIFOs specified in RVC-CAL language. The ORCC tool is utilized for compiling and software synthesis [3] and we make use of the generated C-code for multicore platforms. We also use the structure of the software FIFO presented in Fig. 1-b), which is generated by ORCC.

A FIFO may have several reader actors but only one writer actor. It opts an indexing mechanism such that a specific index is assigned to each reader or writer actor. These indexes are used to determine the number of available tokens corresponding to each reader actor and the free space in a FIFO. The number of available tokens (T f [R i ]) in a FIFO (f ) is the difference between the reader index (I f [R i ]) and the writer index (I f [W ]). The free space in a FIFO is the number of memory addresses that contain no more needed data from all reader actors. In other words, it is the subtraction of the maximum available tokens from the total FIFO size (Size f ).

Each actor has its input and output ports and includes one or several actions. An action describes a specific functionality and is executed (fired) when a set of conditions, so-called firing rules, are satisfied. As an example, a firing rule consists of checking if the number of available tokens in the input FIFO is greater than the required number for computation, and that the output FIFO has sufficient empty room to store the produced tokens. In MPEG4-SP, the number of reader actors ranges from 1 (at least) to 6 (at most).

MPEG RVC defines RVC-CAL applications as dynamic dataflow applications, where the uncertainty of computing due to data-dependency prevents from any static scheduling. They are based on dataflow process network (DPN) model [6]. In such model, the actor executes when at least one of its firing rules is satisfied. For cases where several firing rules Fig. 11. MPEG4 part 2 SP decoder [33] are satisfied simultaneously, only one is selected according to its priority. Consequently, its corresponding satisfied action is fired. Each firing consumes input tokens and produces output tokens. The number of the consumed or produced tokens may be fixed or variable.

B. Experimental framework and setup

In order to assess the feasibility of our proposed runtime remapping method, we developed a real-time simulator. The simulator is described in SystemC TLM model [35]. The devised simulator models a MPSoC platform using NoC concept for interconnecting embedded modules. The platform incorporates heterogeneous processing elements (Table I), memory blocks, and the manager. The simulator platform has been designed with hierarchical modules that can work concurrently and intercommunicate via ports using simple or complex communication channels. SystemC features have been exploited to mimic the accurate functionality of the modules described in section III. The adopted NoC-based architecture, presented in section III, is implemented in the devised simulator platform. In order to accurately model the adopted application, all involved actions are functionally simulated to determine their executiontiming features and generate the real data exchanged by actors during video decoding. The SystemC model adopted in the simulation platform is cycle accurate at the level of the NoC and the network interfaces. The timing of all corresponding action executions on PE is compensated in the simulation according to the profiling data extracted while running the application on a reference computer. Profiling data provides, for each involved action, the mean value of the number of cycles required to execute it. In this work, profiling data has been extracted using on a desktop computer (i7-2620M CPU@2.7 GHz and 8GB memory). We consider that the NoC operating frequency f is 500 MHz. The clock cycle in each PE is determined according to Table II. During SystemC simulations, for each fired action, its corresponding execution time determined in profiling is mapped according to the processor frequency and used as time delay to compensate the real execution time. In addition, several benchmark video sequences with different formats from [36] have been encoded. The selected video sequences have different manner in changes between successive frames. This guarantees to evaluate the performance of the proposed algorithm for different datadependent behaviors. The resultant data has been used as input to the decoder. These same encoded videos have been decoded on a desktop computer and the FIFO contents have been traced over the decoding period. To verify the proper functionality of each actor, the contents stored in the FIFOs in the simulator have been compared to the traced FIFO data. Also, the output data of the simulator have been reconstructed into visual video in order to verify the functionality of the devised simulator. The video sequences have been decoded without applying remapping targeting the same NoC-base architecture and the obtained results have been compared to that obtained when the video sequences are decoded adopting the MB remapping algorithm applying ALTD and APTD for estimating the communication time delay while considering an observation window of N f = 10.

C. Experimental Results

1) Transported data:

The number of packets that travel through the network during the decoding of the video sequences, and their corresponding flits are recorded in the case of applying the MB remapping and the case of decoding the video without remapping. Fig. 12 presents the number of transported packets and flits in logarithmic scale during decoding the Foreman video with CIF format and Bus video with QCIF format for the case of adopting MB remapping algorithm and the case of ordinary decoding. The packets and flits are classified into control and data categories. The figure shows that the flits of control packets form about 53% of all transported flits in the two cases.

Furthermore, investigating thoroughly the types of transported control flits illustrates that 93% of control flits belong to FIP. This refers to the MoC adopted in dataflow applications which requires checking the firing rules (availability of input data and output buffer space). Fig. 13 shows in logarithmic scale the number of each type of control flits transported while decoding the Foreman video sequence in CIF format and Bus video sequence in QCIF format for the case of MB remapping and the case of ordinary decoding. Also, Fig. 13 shows that additional flits are transported in the network due to the remapping. In fact, applying remapping induces additional control and data packets. In order to evaluate the effect of applying the MB remapping algorithm on the traffic in the network, the transported flits are classified into two main categories. The first category includes the flits which are used basically for dataflow. This category encompasses the flits which occupy the payload of all FIP, DRP and DFP. The second category includes the induced flits by applying the remapping algorithm. Hence, the second category compromises the flits listed in the payloads of NP, MRP, MCP, M n IP, M p IP, CTP, and BCP. Note that both categories include data and control packets. Fig. 14 illustrates the comparison summary in terms of the number of transported flits of both categories. In the figure, the number of transported flits, which is obtained while processing the Foreman video with CIF format and Bus video with QCIF format, is presented in logarithmic scale for both cases (decoding while applying remapping algorithm and ordinary decoding). The comparison shows that the additional flits induced by applying the MB algorithm forms less than 0.02% from total transported flits.

1,0E+00 1,0E+01 1,0E+02 1,0E+03 1,0E+04 1,0E+05 1,0E+06 1,0E+07 1,0E+08 1,0E+09
In addition, Table V shows the percentage of flits transporting the binary code of migrated actors from the total number of transported flits in the network while decoding several video sequences. The presented percentages illustrate that the impact of actor migration on the traffic is negligible.

2) Packet time-delay: The packet time-delay is recorded while decoding the video sequences, following the procedure explained in subsection IV-B. Fig. 15 [36] of the sum of packet time-delays throughout the observing windows during the decoding of the Foreman video sequence with CIF format when adopting the MB remapping technique.

It is noticed that applying the MB remapping algorithm affects the time-delay of the packets. In addition, the figure shows the comparison with the case of ordinary decoding. The comparison illustrates that using MB remapping decreases gradually the total packet time-delay. Note that the task moves occur after processing 80, 100, 160, and 270 frames. Fig. 15 shows that the total packet delay decreases after the conducted moves. This refers to the fact that task remapping contributes in distributing the tasks on PEs that are nearer to the memory modules accommodating the input and output FIFOs. Also, Fig. 15 presents a comparison in terms of average time-delay of packets transported during the decoding of the Foreman video with CIF format when adopting the MB remapping technique and when using ordinary decoding. The comparison confirms that the use of MB remapping technique contributes significantly in reducing the time-delay.

3) Timings: Fig. 16 presents the recorded total communication time and total computational time throughout the observing windows during the decoding of the Foreman video with CIF format when adopting the MB remapping technique and when using ordinary decoding. It shows that the communication time represents 90% of the total execution time in both cases. Hence, the total execution time is affected more by the variation of the total communication time. Also, Fig. 16(a) shows that the total communication time is almost not changing among observation windows in the case of ordinary decoding. Whereas, when MB technique is applied, the communication time varies significantly and tends to follow a decreasing manner as shown in Fig. 16(b). This illustrates that reducing the time-delay achieved by MB remapping has a direct impact on the communication time.

The communication time of each processing element is investigated through the decoding of all video frames. It is noticed that when applying the MB remapping technique, the variation between communication times of all involved PEs is reduced. The communication time values of all PEs converges gradually to a specific interval as shown in Fig. 17.

4) Performance results: Multiple simulations have been conducted to decode several benchmark video sequences from [36]. Fig. 18(a) presents the achieved throughput in terms of frames per second (FPS) when decoding Foreman video (CIF format) and using ALTD and APTD respectively for estimating the NoC communication time delay. The figure also shows the achieved throughput when decoding the Foreman video (CIF format) without remapping. The letter "M" shown on the curves represents when an actor move occurs. Fig. 18(a) shows that using MB results in significant performance enhancement. In addition, the figure illustrates that adopting ALTD for estimating the NoC communication time delay, while decoding Foreman video sequence with CIF format, increases the achieved enhancement ratio. Other similar simulations have been conducted targeting other video sequences with different formats (CIF, 4CIF and QCIF). The selected videos are of diverse characteristics to ensure that the proposed remapping algorithm is not related to specific formats or video content. The obtained results confirm that adopting MB algorithm ensures enhanced performance when compared to decoding the video without remapping. Also, the results demonstrate that adopting ALTD rather than APTD leads to additional performance enhancement.

D. Discussion and Comparison

In order to determine the relevancy of the devised algorithm, it is compared to the STM method introduced in [31]. To achieve fair comparison, the STM method has been modeled and implemented on our devised NoC-based architecture. We have also implemented the exact method presented in [20] for the initial mapping, with two differences: we have used constraint programming instead of ILP, and the objective function is the maximum period, Eqn. 12, as it is our optimization goal. The workload used for the computation time of the actors is based on the profiling of Foreman video. Simulations have been conducted while running the MPEG4 decoder to process real-life videos.

1) Performance enhancement of MB remapping: The results presented in Fig. 18 show that for Foreman video sequence with CIF format (Fig. 18(a)), the use of MB remapping algorithm when adopting ALTD leads to a maximum performance enhancement of 38.2% (frame 280) and adopting MB-APTD leads to a maximum performance enhancement of 14.8% (frame 210) when compared to the results of processing the video without remapping. For Ice video sequence with 4CIF format (Fig. 18(b)), maximum performance enhancement of 56% (frame 450) and 16.5% (frame 250) are recorded when applying the MB algorithm adopting ALTD and APTD respectively. Furthermore, the use of MB algorithm adopting ALTD and APTD leads to a maximum performance enhancement of 10.92% (frame 120) and 7.6% (frame 50) for Bus video sequence with QCIF format (Fig. 18(c)) and Bus video with CIF format (Fig. 18(d)). For Grandma video with QCIF format (Fig. 18(e [36] using MB remapping algorithm estimation of ALTD is more accurate and usually leads to better performance compared to APTD. However, in some cases APTD performs better such as for some observation windows of Grandma video (Fig. 18(e)). This refers to the fact that the heuristic is data-dependent and the link level prediction depends on the monitoring information collected during the previous data which may not match with the that of the current processed data.

2) MB remapping in comparison to STM remapping: Fig. 18 shows a comparison between our proposed remapping and the STM algorithm in terms of throughput (FPS). The results shows that the MB remapping outperforms STM remapping technique when considering either APTD or ALTD for estimating the NoC communication time delay.

Besides, the graphs in Fig. 18 show that in some cases the STM method leads to deterioration in the performance. In fact, the STM method selects critical task to be moved in each observation window without estimating the resulting total performance gain. Moving the task without determining its effects on the whole system performance degrades the overall performance. While in our proposed algorithm, the maximum achieved total gain among all mapping combinations is first determined as explained in subsection IV-E2c. Accordingly, a task is specified to be moved if the estimated maximum total gain is positive. It is noticed that in some observation windows no tasks are moved when the proposed algorithm is applied. A move is indicated by letter "M" in Fig. 18(a). In these cases, the estimation shows that no performance enhancement will be achieved for all mapping combinations.

3) MB remapping in comparison to optimal mapping: Fig. 18 also shows the results obtained from the mapping approach proposed in [20]. Note that the "optimal" mapping corresponds to the best mapping found based on the profiling of Foreman video after a time out of one hour (like the original paper), and the optimality is not proven. The results show that the MB algorithm, starting from a random mapping (without significant initial delay), performs better that the optimal with no remapping for Foreman video sequence in CIF format (Fig. 18(a)). As the optimality is searched for the Foreman profile, we used the optimal mapping as a starting point for the MB algorithm, and the results show that it further improves the throughput. As expected, the optimal mapping for Foreman does not perform good for the Ice video sequence in 4CIF format (Fig. 18(b)) and Grandma video sequence in QCIF format (Fig. 18(e)). But surprisingly, it performs good for the Bus video in QCIF format (Fig. 18(c)) and Bus video in CIF format (Fig. 18(d)). The so-called optimal method cannot be used for two reasons. First it introduces an unpractical initialization delay without guaranty of optimality. Secondly, a static solution is not appropriate to data-dependent applications since a solution can be good for one data-stream and inefficient for another one and more importantly the efficiency of a mapping varies over time.

4) Comparison summary:

E. Scalability and generality

The scalability of our approach relies first on a negligible extra payload in the context of actor-level dataflow models, which intrinsically require a large amount of small control packets. For example, when decoding the Foreman video sequence the extra flits imposed by remapping (including the flits holding the binary codes of moved actors) constitute less than 0.02% of the flits used for dataflow. The proposed remapping method enhances the performance by exploiting the NoC structure and the characteristics of the available resources. The results show that our method positively impacts the NoC performance. Table VII illustrates the reduction percentages of packet hops when decoding different video sequences adopting the proposed MB remapping compared to ordinary decoding without remapping. The comparison shows that the proposed remapping method reduces the packet hops. The percentage of reduction is more than 20%. Secondly, the method includes the migration cost and so limits the number of moves.

Fig. 19 shows the results obtained for a 4 × 6 NoC, for Foreman and Bus video sequences, starting from a random mapping. The results show that our approach can also improve the throughout for a larger NoC. On average, the throughout is improved by 13.5% and 4% for Bus QCIF and Foreman CIF videos respectively.

VI. CONCLUSION

This paper presents an original Move-based algorithm and NoC-based architecture to map the tasks of dataflow application during run-time. The method monitors the performance and intercommunication, takes the proper mapping decision and applies the required mapping configurations. The algorithm and the devised architecture are thoroughly presented. The best way to verify the effectiveness of a run-time mapping, which is by definition data dependent, is to simultaneously execute the target application. However such demonstrations are complex, time consuming and so ignored in the literature. In this paper we address this issue by conducting a SystemC simulation of the MPEG4-SP decoder with several real-life video sequences. The obtained results demonstrate that the proposed algorithm significantly enhances the performance. In addition, the proposed algorithm outperforms the available run-time mapping technique. Future work will consider the implementation of integrated module in the NIs and estimating the overhead in terms of area and energy.

Chapter 6

Flexible and Efficient Architectures Based on Memristive Technologies

Introduction

Computing resources are continuously increasing with technology progress, yet the use of the computing capabilities is facing major limitations in terms of power dissipation, off-chip memory access time, and real available parallelism. These limitations lead to a partial use of the offered integration capabilities and increase the gap between accessible technology nodes and available design methodologies. Nevertheless, the evolution of the emerging nonvolatile memory (NVM) technologies, open new design perspectives to balance the underuse of available hardware resources.

Besides memory access time reduction due to on-chip integration, the silicon density offered by recent technology nodes can be efficiently used, and significant reductions in power consumption can be achieved as long as the leakage power can be controlled and the 103 memory bandwidth exploited. Such a configuration is made possible by applying memorybased computing (MBC) [START_REF] Hanyu | Standby-power-free integrated circuits using MTJ-based VLSI computing[END_REF] while considering a network-on-chip to broadcast requests to NVM devices and full power gating (PG) to switch-OFF unused memories. This research work proposes a novel approach that distributes and moves computing resources closer to memory. The main idea is to replace computing by memory like. It considers the replacement of results stored in memory to take advantage of dense, low power memories. Distributed memories are adopted to increase the bandwidth by making use of the increase of on-chip memory density and the emerging manycore architectures based on NoC. In practice, all memories are not addressed at the same time leading to inherently partial resource usage in time. Therefore, applying power-gating techniques to unused resources can offer important power savings. For cost and efficiency reasons, emerging NVM memories are reused without modification except the implementation of efficient power-gating techniques. Rather than implementing logic in memories, the NIs of the NoC are enhanced to turn power-gated memories into content-addressable memories. It is also important to note that our NoC-Memory Based Computing (NMBC) concept can be generalized and additional functionality (e.g. encryption, max, sum, sigmoid, etc.) can be implemented in the NIs.

Context and Motivations

A large increase in the applications that can take advantages of the capability to integrate much more on-chip memories. Datacenters related applications are one of the main examples, where the energy efficiency constraints lead to the rise of heterogeneous architectures [START_REF] Cong | Heterogeneous datacenters: Options and opportunities[END_REF]. Neuromorphic architectures based on convolutional neural networks (CNN) [START_REF] Pham | Neuflow: Dataflow vision processing system-on-a-chip[END_REF], Spiking neural networks [START_REF] Merolla | A million spiking-neuron integrated circuit with a scalable communication network & interface[END_REF] or Sparse Neural Networks (SNN) [START_REF] Jarollahi | A nonvolatile associative memory-based context-driven search engine using 90 nm CMOS/MTJ-Hybrid logic-in-memory architecture[END_REF] are another major application examples dominated by memory resources. It is worth noting here that this class of algorithms usually implies much more reading than writing accesses in the operational phase after the learning stage.

Another related use of the emerging memory integration capabilities is illustrated in [START_REF] Paul | A scalable memory-based reconfigurable computing framework for nanoscale crossbar[END_REF], where switch-based logic functions are replaced efficiently by memories especially in the case of molecular crossbars. In this approach, a partitioning of the application graph is applied to map computing elements on memory arrays. Replacing logic by memories is efficient in case of computation redundancy. Such patterns can be extracted from signal processing algorithms that allow partial pre-processing [START_REF] Lee | On the design automation of the memorybased VLSI architectures for FIR filters[END_REF]. Another different approach consists in storing the results of frequently used computations in memory. Such methods have shown significant energy improvement in the context of heterogeneous reconfigurable multicore architectures [START_REF] Rahmani | Memory-based computing for performance and energy improvement in multicore architectures[END_REF] and GPGPU architectures [START_REF] Rahimi | Energy-efficient GPGPU architectures via collaborative compilation and memristive memory-based computing[END_REF].

In memory-based computing, where the application is partitioned and mapped to dense memory arrays and compute elements [START_REF] Rahmani | Memory-based computing for performance and energy improvement in multicore architectures[END_REF], not all memories are entirely addressed at the same time. Thus, if the memories are implemented as a grid of memory blocks, the resource usage in time is inherently partial. Therefore, applying power-gating techniques allows minimizing the power consumption of partially used resources. In this context, the emergent nonvolatile memory technologies, such as magnetoresistive random-access memory (MRAM) with low-leakage characteristics and power-gating capabilities, represent a great opportunity to design energy efficient architectures. In other words, increasing on-chip resources with low-power behaviors contribute to the global architecture and energy efficiency.

Moreover, such architectures can take real advantage of more than one decade of research and achievements in NoC design, that allow configurable accesses to grids of memories as well as the implementation of pre/post-processing steps in network interfaces [36].

Memristive technologies boost the research towards logic-in-memory approaches with the idea of introducing bit-level logical function in memories. This is presented with a programmable architecture in [START_REF] Gaillardon | The programmable logic-in-memory (plim) computer[END_REF], where power-gating is not considered. The concept of active memory also enhances memory with new functionality, which is the capacity to manage high-level transactions requests with a local processor executing transfer operations [START_REF] Yoo | Active memory processor for network-on-chip-based architecture[END_REF]. These two approaches lead to specific designs, where logic and memory are tightly coupled.

Magnetic tunnel junction (MTJ) devices [START_REF] Ikeda | A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction[END_REF] represent a main class of emerging nonvolatile technologies for low-power memory circuits. Recently, several MRAM designs have been presented [START_REF] Takemura | A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme[END_REF][START_REF] Ohsawa | A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme[END_REF][START_REF] Kim | A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array[END_REF] that exhibit significantly low leakage currents realized by powergating, thanks to the non-volatility feature. These MRAM designs are designed using relatively large device technologies, such as 90 nm, yet the MTJ technology allows scaling down to 11 nm as for CMOS devices [START_REF] Sato | Properties of magnetic tunnel junctions with a MgO/CoFeB/-Ta/CoFeB/MgO recording structure down to junction diameter of 11 nm[END_REF]. The performance of MRAM devices in such recent technology nodes are also estimated in [START_REF] Chun | A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory[END_REF][START_REF] Peng | Interfacial perpendicular magnetic anisotropy in sub-20 nm tunnel junctions for large-capacity spin-transfer torque magnetic random-access memory[END_REF].

MRAM devices are designed using different MRAM cells, such as 1T-1MTJ, 2T-2MTJ, and 4T-2MTJ. This corresponds to performance trade-offs between area efficiency and read time. For example, the 1T-1MTJ MRAM exhibits the highest area efficiency with a relatively slow read time, while the 4T-2MTJ MRAM realizes faster read time with lower area efficiency. In terms of power-gating, a simple strategy that shutdowns the power of the whole MRAM device at the idle state is generally used. In the 4T-2MTJ MRAM [START_REF] Ohsawa | A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme[END_REF], a cell-level power-gating technique is used that activates only a row at the read/write state, leading to low leakage currents in the cells.

Contributions and Performed Work

This research work introduces a novel computing approach that exploits memory bandwidth and limits the leakage power by applying MBC, while considering a NoC to broadcast requests to memory and NVM to switch-OFF unused memories. The main contributions of this research work are:

• Propose a novel NMBC architecture that introduces the design of energy-efficient multicore solutions for memory-based computing. The tailored architecture interconnects three types of IP blocks: memory modules, processing elements and managers.

• Introduce a new computing paradigm is presented where the packets of a NoC are used as commands executed by configurable NI to access in parallel multiple memory blocks, which are technologically independent from the NoC. The managers send queries to memories by means of packets where known and unknown fields are specified. Then the processors collect the memories answers and apply a simple winner-take-all algorithm to select records to be send back to managers.

• Upgrade the structure of NIs associated to each memory module in order to decode the requests sent by the manager, handle the communication of results to the processors, and provide managers with monitoring data about bandwidth usage and processor usage. Note that these services are dedicated to NIs in order to remain compliant with any existing memory and to be independent from NoC parameters. Adopting PG reduces the leakage current of the cell array compared to that of an Static Random-Access Memory (SRAM) cell array. The peripheral circuits can be power-gated using the pMOS transistor when the MRAM is at the idle state.

In this work, two different policies of PG have been addressed: only cell PG (OCPG) and full PG (FPG). In OCPG, the the MRAM cells are power-gated at the idle state and the peripheral circuits are always at the active state. In FPG, the whole MRAM is power-gated at the idle state. FPG reduces the leakage current in comparison with the OCPG while a wake-up operation is required for the peripheral circuits, which cost extra energy dissipation and delay time.

• Demonstrate the effectiveness of the proposed approach through a relevant case study of a database search application implemented with neuromorphic architecture based on SNN, which is a neural network model inspired by information theory and error correcting codes. It is especially efficient for the implementation of associative memories, so it can be used to process database queries [START_REF] Jarollahi | A nonvolatile associative memory-based context-driven search engine using 90 nm CMOS/MTJ-Hybrid logic-in-memory architecture[END_REF].

• The PEs are implemented as dedicated hardware components. A specific design is tailored in VHDL, which enables to estimate the implementation area of the PEs and include their power consumption in the global power budget.

• The RTL specification of the router and the NI is synthesized in the physical layout estimation mode. The total power was obtained by using the leakage and dynamic power of the NoC and NI components, relying on the switching activity traced by the SystemC simulation.

• Build an experimental setup that model the adopted NoC implementing MRAM memories in SystemC TLM. In order to check the relevance of the proposed approach, the devised model executes the database search engine application using the Yeast database benchmarks (cellular localization in proteins) from the UCI Machine Learning Repository [START_REF]ML Repository[END_REF]. The model has been developed to mimic the exact behavior of the target architecture by designing hierarchical modules that work concurrently and intercommunicate via ports. The SytemC model is cycle accurate at the NoC level including NIs. To ensure accuracy, the timing features of memory reading response and wake ups are considered in the model. Furthermore, the execution time of computations in the PEs is based on the HDL simulation and synthesis that provide real-time environment modeling.

• Conduct experimental simulations using the devised simulation model while considering different types of memories, PG policies and number of missing fields in the queries.

• Based on the simulation results, the relevancy of the proposed concept is evaluated. The transported data is tracked. Accordingly the hit rate and injection rate are computed. Also, the power budget is estimated based on the TSMC 65-nm CMOS process, the implementation of PEs and the specifications of the memory models. The percentage of dissipated power in each module is determined and classified into static or dynamic. Also, the obtained results when adopting the MRAMs are compared with those obtained when adopting SRAMs while using identical NoC and PEs features and memory contents.

Findings

• The obtained results demonstrate important power reduction with database hit rates of about 94A slight degradation in the hit rate is recorded when increasing the number of missing fields in the queries. This is due to the fact that the ambiguity ratio increases with the decrease of the number of known fields.

• All FPG solutions provide energy gains over four times with respect to SRAM. This refers to the factor that the maximum recorded percentage of static power in FPG-MRAM is lower than that recorded when SRAM is adopted. This can be explained by the significant reduction of static power in FPG-MRAM when the memory is in idle state and that the memories are at OFF state most of the time. The recorded data shows that the MRAMs are OFF more than 75% of the time. It is worthy to indicate that the static power dissipated in FPG-MRAM in the idle state is highly less than that of SRAM. The wake-up feature in the FPG policy has not added a significant overhead as the percentage of wake-up consumed power is less than 10%. The dissipated power while reading is important since it dominates over the static power and wake-up power. Its percentage approaches to 65% of the total consumed power. However, the SRAM power consumption while reading is higher than the introduced types of MRAM.

• OCPG policy cannot outperform SRAM case with any type of MRAM as the percentage of static power dissipation of OCPG-MRAM is higher than the percentage of static power dissipation of SRAM.

• The comparison in terms of power consumption between the three types shows the following:

1. Type I outperforms Type II in the case of 256 bits as with 256 bits the gain of read operations does not compensate the increase of the static power of the Type II switch.

2. Type II is more efficient with respect to Type I when 128 accesses are possible 3. Type III outperforms Type I and Type II in any case as it takes full benefit of the reduced read energy that does not impact the PG switch overhead. Moreover, Type III can also benefit from the bitwidth granularity and efficiently exploit 32, 64, and 128-bit cases opportunities.

• The comparison of the adopted NI with the baseline NI shows that the area and power of the proposed NI, present overheads of 14.3% and 12.6%, respectively. If we consider the whole NoC, the area and power overheads are 6.1% and 5.2%, respectively.

As a conclusion, important energy savings can be achieved when the application fits with the MBC context, namely when fully power-gated NVMs can take benefit of limited activity rates. The obtained results show that such an approach can significantly modify the power budget breakdown between NoC and memory. This allows to increase the number of memory modules and so to target large-scale applications. capabilities is facing major limitations in terms of power dissipation, off-chip memory access time, and real available parallelism. These limitations lead to a partial use of the offered integration capabilities and increase the gap between accessible technology nodes and available design methodologies. Nevertheless, the evolution in memory design and on-chip memory integration, particularly the emerging nonvolatile memory (NVM) technologies, opens new design perspectives to balance the underuse of available hardware resources.

In fact, besides memory access time reduction due to on-chip integration, the silicon density offered by recent technology nodes can be efficiently used, and significant reductions in power consumption can be achieved as long as the leakage power can be controlled and the memory bandwidth exploited. Such a configuration is made possible by applying memorybased computing (MBC) while considering a network-onchip (NoC) to broadcast requests to NVM devices and full power gating (PG) to switch-OFF unused memories.

Based on these observations, we first propose a novel NoC-MBC (NMBC) architecture, which relies on an NoC-based multicore architecture that allows to take full benefit from PG capabilities of distributed MRAM. We introduce a new computing paradigm, where the packets of an NoC are used as commands executed by configurable network interfaces (NI) to access multiple distributed memory blocks in parallel. These memory blocks are technologically independent of the NoC and the processing units. Furthermore, we introduce different implementations of spin-transfer-torque magnetoresistive random access memory (STT-MRAM) with cell and peripheral PG capabilities. Finally, the effectiveness of the proposed approach is demonstrated through a relevant case study of a database search application implemented with a neuromorphic architecture based on a sparse neural network (SNN) [1].

This paper presents five new contributions that improve significantly the performances compared with our previous work [2]: 1) an original type of power-gated MRAM memory called Type III, which is based on an asymmetric read/write scheme and allows for significant power reductions with respect to previous solutions; 2) rather than a single manager, multiple manager modules can be working concurrently; 3) the processing elements (PEs) are not statically but dynamically allocated; 4) PEs are implemented as dedicated hardware components, and they are included in the global power budget; and 5) design and synthesis of all modules, including MRAM devices, are done using 65-nm technology node.

The rest of this paper is organized as follows. First, we present the proposed NMBC architecture model and the considered application case study of an SNN-based database search engine in Section III. Then, Section IV introduces the MRAM design models, including the proposed cell and peripheral PG policies and the three types of PG granularities. Section V provides the detailed evaluation setup in terms of selected database for the application case study, NoC implementation, and SystemC simulation of the proposed NMBC architecture. Section VII summarizes and discusses the obtained results before concluding this paper in Section VIII.

II. RELATED WORK

A. Memory-Based Computing

MBC can have several meanings. The first one is a method to solve the memory-wall challenge, for applications dominated by data transfers, by migrating computing within the memory. A first implementation of a full adder was introduced in [3], and a summary of a research decade on this topic is presented in [4]. The solution consists in executing some greedy operations with logic implemented in the memory device in order to reduce the bandwidth demand and latency that limit the use of static random access memory (SRAM) and DRAM. The logic-in-memory concept allows to implement logic function (F) to apply transformations and data transfer in the memory as shown in Fig. 1(b). This solution is especially efficient with NVM technologies, such as spin-orbit torque magnetic random access memory or domain wall motion memory. Fan et al. [5] compare these technologies with an Advanced Encryption Standard encryption application, which is a typical in-place computing scheme that can take full benefit from this approach. The idea of moving computing close to the memory reduces latency and increases the bandwidth compare to solution based on SRAM or DRAM. Memristive technologies are also candidate for programmable approaches. This is presented with programmable bit-level logical function in memories in [6], but PG is not considered.

Our approach aims also to distribute and move computing resources closer to memory but with a different approach. Actually, we consider distributed memories to increase the bandwidth. This solution is made possible jointly by the increase of on-chip memory density and by the emerging manycore architectures based on NoC. For cost and efficiency reasons, we also want to reuse existing (or emerging) NVM memories without modification except the implementation of efficient PG techniques. So our solution relies on the enhancement of NI, as shown in Fig. 1(a).

The second meaning of MBC is the idea that computing can be replaced by memory. Replacing logic by memories is efficient in the case of computation redundancy. Such patterns can be extracted from signal processing algorithms that allow partial preprocessing as introduced in [7]. Paul and Bhunia [8] consider dense memory, based on molecular crossbars, to implement logic functions in multi-input-multioutput lookup table (LUT) in a memory array. In this approach, a partitioning of the application graph is applied to map computing elements on memory arrays. In [9], the idea is extended to coarse-grain implementations. Both cases are shown in Fig. 1(c) and (d), respectively. It is worth noting that the two ideas can be combined if in-memory logic functions are implemented as LUTs.

Our solution also aims to replace computing by memorylike in Fig. 1(c), and however, we do not implement logic in the memories but in the NI to turn power-gated memories into content-addressable memories. It is also important to note that our NMBC concept can be generalized and additional functionality (e.g., encryption, max, sum, sigmoid, and so on) can be implemented in the NIs.

The third meaning is an extension of the second one and is based on the principle of memory cache applied to the results of frequent computations with identical inputs. It is shown in Fig. 1(e). If the same computation with the same operands occurs, then the result is available from the memory without repeating the computation. Such methods have shown significant energy improvement in application domains with important opportunities of result reuse. This technique has been implemented with associative memristive memories (AMMs) in the context of heterogeneous reconfigurable multicore [9] and GPGPU architectures [10]. Our approach considers the replacement of results stored in the memory to take advantage of dense, low-power memories. In practice, all memories are not addressed at the same time leading to inherently partial resource usage in time. Therefore, applying PG techniques to unused resources can offer important power savings. In this context, emergent NVM technologies such as MRAM with low-leakage characteristics and PG capabilities represent a great opportunity. They allow to design energy-efficient architectures where unused memory resources can be switched OFF. In other words, increasing on-chip resources with low-power behaviors contributes to the global architecture and energy efficiency. Moreover, such architectures can now take real advantage of more than one decade of research and achievements in the NoC design. NoC allows configurable accesses to grid of memories as well as the implementation of preprocessing/postprocessing steps in NI [11].

Data-centers-related applications represent a typical case where the energy efficiency constraints lead to the rise of heterogeneous architectures [12]. It covers applications dominated by memory resources, such as database accesses, search engines, data analytics, and so on. In this context, neuromorphic architectures can play a major role. It is worth noting here that this class of applications usually implies much more reading than writing accesses in the operational phase after the learning stage. Different approaches have been explored in the literature. Pham et al. [13] present an efficient run-time configurable coarse-grain reconfigurable architecture for convolutional NNs. A smart direct memory access and dedicated switches are used to feed computing nodes with data from an off-chip memory. The architecture is computation intensive and does not fit with MBC except if produced data exhibit reuse. The true north architecture [14] is different and designed for spiking NNs. It is based on an NoC to distribute synapses states to local computing cells. The chip is based on a dedicated architecture that implements 5 Mb of onchip memory but with no PG technique. Logic-in-memory is also explored for NN applications, and Wang et al. [15] implement the different NN function including Sigmoid in an NVM. Finally, an SNNs dedicated architecture is presented in [16]. It is designed using a logic-in-memory approach and MTJ devices with bit-level interconnects. It is highly optimized but at the cost of a very specific design approach. An NoCbased architecture for SNN is presented in [17], yet it is a dedicated architecture and this paper is mainly devoted to the NoC topology and the memory optimization.

Finally, one can think about the concept of active memory, which also enhances memory with new functionality. This is the capacity to manage high-level transactions requests with a local processor executing transfer operations [18]. This type of solution leads to specific designs, where logic and memory are tightly coupled.

We also consider the case of neuromorphic computation as a typical case of data reuse that can take a great benefit of an MBC model. But, as previously mentioned, we consider MRAM with efficient PG and implement additional logic resources in the NI and not in the memories. Our objective is to exploit the bandwidth and the flexibility of packetswitching NoC architecture to efficiently access the target data distributed in arrays of memories that can be switched ON when necessary.

B. Power-Gated MRAM Devices

Magnetic tunnel junction (MTJ) devices [19] represent a main class of emerging nonvolatile technologies for lowpower memory circuits. Recently, several MRAM designs have been presented [20]- [22] that exhibit significantly low-leakage currents realized by PG, thanks to the nonvolatility feature. These MRAM designs are designed using relatively large device technologies, such as 90 nm, yet the MTJ technology allow scaling down to 11 nm as for the CMOS devices [23]. The performance of MRAM devices in such recent technology nodes is also estimated in [24] and [25].

MRAM devices are designed using different MRAM cells, such as 1T-1MTJ, 2T-2MTJ, and 4T-2MTJ. This corresponds to performance tradeoffs between area efficiency and read time. For example, the 1T-1MTJ MRAM exhibits the highest area efficiency with a relatively slow read time, while the 4T-2MTJ MRAM realizes faster read time with lower area efficiency. In terms of PG, a simple strategy that shutdowns the power of the whole MRAM device at the idle state is generally used. In the 4T-2MTJ MRAM [21], a cell-level PG technique is used that activates only a row at the read/write state, leading to low-leakage currents in the cells without any additional PG transistor. We use this 4T-2MTJ MRAM model in this paper, and more details are provided in Section IV.

However, advanced PG policies and granularities, including peripheral circuits (e.g., row and column decoders), have not been presented or discussed in the available literature. It is worth noting that conventional PG techniques that can be applied to processing units and NoCs are out of the scope of this paper. These methods are independent and complementary to our proposed approach and can be efficiently combined.

III. NMBC FLEXIBLE ARCHITECTURE

A. Architecture Principle

The proposed architecture model is presented in Fig. 2(a). It is based on an NoC that interconnects three types of IP blocks: memory clusters, PEs, and managers. In the proposed approach, we consider NoC packets as commands initiated by managers, as shown in Fig. 2(b). Memories are distributed in M C clusters, and each cluster has a unique NI and is composed of M B memory blocks. The managers are in charge of a set of requests to process and send packets to memory clusters in a unicast, multicast, or broadcast way. They also apply a processor selection for postprocessing and can therefore perform load balancing. All the managers can work in parallel. The decoding of instructions is carried out by smart NIs that implement additional logic elements. NIs are in particular aware of a data mapping and manage the communication of results to processors. NIs also implement some specific bitlevel operations such as bit selection that will be detailed in Section V-B3. NIs can also provide managers with monitoring data about bandwidth and processor usage, and this type of information is sent as monitoring packets to managers.

B. Application Case Study of SNN-Based Database 1) SNN Concept:

As introduced before, database search engine is one of our target application domains. Hereafter, we explain the use of NMBC for database search engine implementation based on the SNN algorithm [1]. SNN is an NN model inspired by information theory and error correcting codes. It is especially efficient for implementing associative memories, so can be used to process database queries, as shown in [16]. SNN relies on two phases: message learning and information retrieval from partial knowledge. It is worth noting that the learning phase consists simply in writing each new record "one time" at the right place in the memories. Therefore, this phase presents a linear complexity with the database size for any devised network architecture. This is fundamentally different from the greedy learning phase of deep learning approaches. So, the write operations cost is negligible compared with read operations cost, which constitutes the major challenge in database search applications. Basically, a record is a clique that fully links neurons that belong to different clusters. The principle can be compared with low-density parity-check codes. If we consider the database application, a record M is composed of F fields (a field f (i ) per cluster). The learning phase is the mapping function that associates each field of each record to a single neuron in each cluster. Thus, each field f (i ) is coded with k i = log 2 (l i ) bits, where l i is the number of neurons in cluster f (i ). So, a record is a binary sequence of F i=1 k i bits and is associated with a clique of neurons, and each clique materializes a code word. The query or retrieval of missing data consists in the selection of the best candidate neuron for each cluster that corresponds to an unknown field by means of known neurons is other fields. This choice is made according to a ranking method, which is a winner-take-all algorithm in the original proposal. All clique edges are specified with binary weights such as C XY (i j) = 1 which means that at least one clique contains an edge from neuron i in cluster X to neuron j in cluster Y . The score of each neuron, in the target cluster, equals to the number of clique edges that exist between this neuron and known neurons in other clusters. In the original algorithm, additional iterations can be executed if multiple winners have the same score. However, in the case of database search engine, we will consider multiple answers to a given query. Other algorithmic options are possible but are out of the scope of this paper.

2) SNN on NMBC Architecture: The very dominant cost in SNN implementation is memory. Actually, it is necessary to store all the connections between every pair of clusters. We call m i, j the connection memory between clusters i and j . We demonstrated in another application domain that it is possible, by means of a dedicated memory mapping, to use a single memory for implementing m i, j and m j,i [17]. However, in this paper, we consider distinct m i, j and m j,i for two reasons. First, the NMBC architecture must be programmable to match with different configurations so the size of memory cannot fit exactly with the size of the cluster. Second, our objective is to take advantage of future MRAM memory with a low static power consumption so that unused memories do not impact significantly the power consumption. Therefore, memories are used to store the F • (F -1)/2 connection memories. Regarding the number of fields and the size of each cluster, the mapping of m i, j on the set of distributed memories results from an optimization process to maximize the use of each memory. The managers send queries to memories by means of packets where known and unknown fields are specified. Then, the processors collect the memories answers and apply a simple winner-take-all algorithm to select records to be send back to managers.

IV. MRAM MODEL

A. 4T-2MTJ MRAM Cell

MRAM circuits are designed using STT MTJ devices [19] with CMOS transistors. Fig. 3(a) shows an STT MTJ device stacked over a CMOS layer. It mainly consists of three layers: free layer, tunnel barrier, and fixed layer. The resistance of the MTJ device depends on a spin direction of the free layer. If the spin direction of the fixed layer is the same as that of the free layer, the MTJ is at the parallel state R P (low resistance). Otherwise, it is the antiparallel state R AP (high resistance). The resistance state can be changed using a current signal I MT J , as shown in Fig. 3(b). In the write operation, a data bit is stored to two MTJ devices for two steps. First, a current signal is generated from PL to one of the bit lines (BL, BL) depending on a data bit stored. In this example, b is written because BL is low. Then, b is written using a current signal from BL to PL, where the resistance is changed from R P to R AP . In the read operation, one of BL and BL is low depending on a stored bit. In the idle state (PG), both PL and WL are grounded, which totally eliminates the static power in the 4T-2MTJ cell as no leakage path exists in this case.

B. Power-Gating Policy

Fig. 5 shows an MRAM with cell PG and selective peripheral PG. It consists of the MRAM-cell array with the peripheral circuits: row decoder, row drivers, column decoder, and sense amplifiers (S/A). In the MRAM-cell array, only MRAM cells in a row are active in read/write operation, while the other MRAM cells are power-gated using the row drivers. The cell PG significantly reduces the leakage current of the cell array in comparison with that of an SRAM cell array. The peripheral circuits can be power-gated using the pMOS transistor when the MRAM is at the idle state. For the PG policy, two different policies of PG are exploited as summarized in Table I. The first policy is only cell PG (OCPG), where the MRAM cells are power-gated at the idle state and the peripheral circuits are always at the active state. Therefore, the OCPG-MRAM requires no wake-up operation with negligible leakage current in the MRAM cell array. The second policy is full PG (FPG), where the whole MRAM is power-gated at the idle state. It reduces the leakage current in comparison with the OCPG-MRAM while the wake-up operation is required for the peripheral circuits. The wake-up operation causes extra energy dissipation and delay time. Hence, there is a tradeoff between the OCPG-MRAM and FPG-MRAM. In Section V, the performance of the two different MRAMs with the two different PG policies is exploited for system-level simulations of NMBA.

C. Power-Gating Granularity

For the PG granularity, three different 256-bit × 256-word MRAMs (Type I, Type II, and Type III) are designed, as shown in Fig. 6. The detailed specifications and performance are summarized in Table II. The MRAM circuits are designed and evaluated using a TSMC 65-nm CMOS process and an MTJ model [26] HSPICE. First, let us explain the differences between Type I and Type II. Type I uses a PG transistor for a 256×256 MRAM. Type II uses four PG transistors for four 128×128 MRAM subblocks. The widths of the PG transistors are determined so as to achieve similar write and read times. Compared with Type I, the advantage of Type II is lower power dissipation of reading/writing if the read/write bitwidths are smaller than or equal to 128 bits. In fact, read and write powers are reduced because parastic capacitances of BLs and WLs are reduced, as these capacitances depend on the sizes of the MRAM subblocks. In contrast, the disadvantage of Type II is larger leakage current as the normalized total PG switch size required is double.

We observe that in MBC applications in general and search applications in particular, data are mainly read and rarely written. So we introduce Type III in order to meet both advantages of Types I and II. Type III is designed with the restriction that the maximum write bitwidths is 32 bits, whereas the maximum read bitwidth is 256 bits as for Types I and II. Considering the asymmetry of read and write occurrences in the target application domain, this restriction does not significantly affect the execution time. As only 32 bits are written in parallel in Type III, the normalized total PG switch size required is 1/4 of the Type II, leading to a lower leakage current. If write capability is limited to 32 bits, Type III offers on 6.1. NETWORKED POWER-GATED MRAMS FOR MEMORY-BASED COMPUTING the other hand opportunities to extend read configurations to 32, 64, 128, or 256 bits and so to adapt the read power according to the application demand, as shown in Table II.

V. CASE STUDY

A. Yeast Database Case

As a representative example, we consider the Yeast database (cellular localization in proteins) from the UCI Machine Learning Repository [27]. The original database is specified with 10 fields that we transform into 11 fields by splitting the first oversized field so that we get a more homogenized network. Table III shows the number of connections per field, i.e., neurons per cluster. The number of available memories is fixed by the architecture, yet the number of connection memories m i, j depends on the application. Therefore, the first design step is the memory mapping that results from an optimization process, which is out of the scope of this paper. In our case study, we map 10 × 11 = 110 connection memories in six 256 × 256-bit memory modules. Fig. 7 details the proposed mapping for one of these six memories (M5, as referenced in Fig. 8).

B. NoC Implementation

Fig. 8 presents the structure of the NoC and we consider to demonstrate the NMBC concept. The NoC is a 4 × 4 meshbased network, which interconnects 18 IP cores (6 memory clusters composed of single modules, 10 PEs, and 2 managers). It means M C = 6 and M B = 1 if we refer to the general model described in Fig. 2 The NoC employs the wormhole packet-switching mode, the deterministic XY routing algorithm, and a flow control policy without virtual channels. The implemented routers have one buffer of 3 flits per input port and use distributed arbitration logic (one arbiter per port). The back-end part of the NI is typical and includes a packet maker/un-maker and a priority manager to synchronize packet transmission and reception.

In addition to usual interface logic, the frontend of an NI associated with a memory module implements the addressing and bit selector modules. This choice is important since it allows to remain compliant with any existing memory and to be independent of NoC parameters (topology, router buffer depth, and routing policy). In a fully flexible NMBC architecture, an NI includes an area of reconfigurable hardware that can be configured to implement application-specific functions like addressing and bit selector modules in our case study. The functionality of each IP core and the structure of the additional elements are detailed hereafter.

1) Manager: Upon loading new query (e.g., from a host machine), the manager associates missing fields to clusters with unknown neurons and well-specified fields to identified neurons in other clusters. Consequently, it transmits to all memory modules the command to send to allocated PEs, the available connection information between known neurons in well-defined clusters and all neurons of the undefined clusters. The payload of sent packets is divided into segments, which are relative to definite clusters.

In the adopted application, 11 different clusters exist. Each segment has two parts. The first is one-bit flag, which is used to indicate the status of the corresponding cluster. Respectively, "0" or "1" are placed to specify if the cluster neuron is missing or known. The content of the second part depends on the cluster status. If the cluster has known neuron (i.e., known field of the query), this part contains the initial address of the neuron, which is available in the loaded query, whereas if the cluster's neuron is missing, it will be filled by the address of the PE that is in charge of processing the winner-take-all for this cluster. Fig. 9 presents an example of the sent packet. The loaded query in this example has five clusters with missing neurons (2, 3, 4, 7, and 8). The flags corresponding to these clusters is set to "0." Also, the addresses of the processing modules (P [2], P [3], P [4], P [7], and P [8]) are specified in the second part of each segment. The choice of the PE is made dynamically with a fairness load-balancing policy, whereas for the other clusters (0, 1, 5, 6, 9, and 10), the flags are adjusted to "1" and the second part of each segment is loaded by the values initially available in the query. By arranging this data into 32-bit flits, the sent packet will be composed of four flits only. On the other hand, the manager is first responsible to collect the results corresponding to each cluster from its dedicated processing module. Then, it decides to iterate in order to enhance results or to simply deliver the achieved ones.

2) Processing Elements (32 bits in Parallel): All PEs apply the winner-take-all computational principle in order to find the neurons with the highest score. The score of each neuron is incremented by the number of available connections with all known neurons, which belong to the other clusters. Each PE is assigned to one cluster with a missing field, the assignment is made dynamically by the managers, and the PE is active until the solutions are found. At last, each PE informs by means of packets and the managers by the identity(ies) of the winner neuron(s).

In a fully flexible NMBC architecture, a PE could be a small-size embedded processor or a reconfigurable hardware. In this paper, we have designed a specific PE in VHDL so that we can estimate the power consumption and the area. Each PE can process 32 bits (32 neurons) in parallel. It takes then three cycles to update in the local memory the score of the cluster neurons and the best score neuron. The PE receives the connection information related to their cluster from all memory modules. The total number of cycles depends on the number and size of known/unknown fields that determine the number of packets to be processed.

3) Memory Module: The memory modules store the connection information between the neurons of all clusters at the learning phase. For the adopted case study, six 256 × 256-bits memory modules are used to accommodate the contents of 110 connection memories. Each module includes a memory that returns the data allocated at its specified address. Each memory module should respond to the reading request and deliver all connection information between all known neurons and missing ones to the specified processing modules. The manager is not aware of the local mapping of connection memories, and the model is independent of the type of memories. Therefore, the matching between requested connections and physical addresses is performed by NIs. Since the command packet arriving from the manager does not include implicitly the specifications of the data, which is required to be retrieved (address, width, and starting bit), new tasks such as addressing and arranging the output bits into flits are required. Independently of memory and NoC architectures, these new services are implemented in separate elements in the frontend of the NI associated with each memory module, as shown in Fig. 8. Their architectures and functionalities are described in the following.

a) Address finder: It is a simple hardware element, presented in Fig. 10, which determines the addresses that must be used to access the right connection memories. These addresses are based on the ID of unknown filed and the value of known fields indicated in the command packet. It is composed of an adder and a configurable LUT, which includes the starting addresses of all clusters in the associated memory. When a command packet arrives, the packet unmaker disassembles the packet and delivers the payload to the address finder. The latter identifies the clusters with known neurons according to their flag bits. For each of those, its identity is used directly as the LUT index (address) to retrieve the starting address of the cluster. This address is considered as an offset and is used by the adder to determine the address value to be delivered to the memory. For example, in Fig. 9, cluster 5 has known neuron address 49. The starting address of cluster 5 in memory M 5 is 79, as shown in Fig. 7. Therefore, the address finder will deliver the value of 128 = 79 + 49 to the memory.

b) Bit selector: Fig. 11 shows the architecture of the bit selector. It is composed of one 256-bit barrel shifter, one 256-bit register to store input data from memory, three 32-bit registers to store output data according to a 32-bit flit size, Algorithm 1 Address Finding and Bit Selection and two LUTs that deliver most significant bit (MSB) and control output data width. The first includes the MSB values corresponding to all clusters. The second controls the output data width. Both LUTs are controlled by the cluster IDs. When the new data are retrieved from the memory, the barrel shifter shifts, for each cluster, the data by 255 -MSB steps and then delivers the result to the three output registers. The registers are then loaded according to the enable signal delivered by the second LUT. The algorithm of the address finding and the bit selection algorithm is outlined in Algorithm 1.

Finally, for all clusters with missing neurons, the retrieved connection information with known neurons is gathered according to the cluster identities. Then, each group which is relative to a definite cluster is sent consecutively to the packet maker. The latter assembles a packet that is then transmitted to the processing module dedicated to each cluster.

VI. EXPERIMENTAL SETUP

In order to check the relevance of the proposed approach, the adopted NoC implementing MRAM memories has been described in the SystemC TLM model as a proof of concept. The devised model executes the database search engine application using the Yeast benchmarks. The model has been developed to mimic the exact behavior of the target architecture by designing hierarchical modules that work concurrently and intercommunicate via ports. In addition, the SytemC model is cycle accurate at the NoC level including NIs. To ensure accuracy, the timing features of memory reading response and wake ups are considered in the model. Furthermore, the execution time per paquet of winner-take-all computations is based on the HDL simulation and synthesis that provide real-time environment modeling.

Multiple simulations have been conducted by using different numbers of queries with various number of missing clusters. In this paper, we consider four cases with 4, 5, 6, and 7 missing fields out of 11. The index of missing fields has been chosen randomly. To evaluate the efficiency of the proposed MRAM designs, the results are compared with those obtained when the SRAM-based design is adopted. The SRAM on the isocapacity condition is used. In both SRAM and MRAM cases, the total memory size is 384 kb, where six 256 × 256 distributed memories are used. Both the models use identical NoC features, including packet sizes, routing algorithm, PEs features, mapping strategy, and a common clock set to 500 MHz. We consider the two PG policies defined in Section IV-B. FPG is implemented at the query level, which means that the peripherals are switched ON when a packet is received and switched OFF when all the connection data, related to the command, are processed. We compare the three types of MRAM detailed in Section IV-C. In the case of Type II and Type III memories, readings are limited to 128, 64, or 32 bits when it is possible, namely when all the requested data are located in one of the 4 128×128-bit memory blocks.

NETWORKED POWER-GATED MRAMS FOR MEMORY-BASED COMPUTING

VII. RESULTS AND ANALYSIS

A. Functional Simulation

The data delivered by the manager is compared with the reference data from the Yeast database for the four cases with 600 random request experiments. As illustrated in Table IV, the obtained results meet our expectations with hit rates over 94% when adopting either one or two managers. The results show a slight degradation in the hit rate when increasing the number of missing fields. This is expected, and it is due to the fact that the ambiguity ratio increases with the decrease of the number of known fields. As indicated in Table V, the NoC injection rate doubles with two managers. This translates in an increase of the NoC activity and the time percentage FPG memories are ON.

B. Power and Energy

1) Memories: Fig. 12 shows the energy dissipated by different types of memory modules in order to process 600 random queries while using the two proposed PG policies with 4, 5, 6, and 7 missing fields. The power estimation is based on the TSMC 65-nm CMOS process and the MTJ model given in Table II. From these results about the required energy budgets, we can draw the following important conclusions. In 65 nm, OCPG policy cannot outperform SRAM case with any type of MRAM. The static power dissipation of OCPG-MRAM reaches 95% of the total power dissipation, as shown in Table VI, whereas in SRAM, the highest recorded percentage of static power dissipation is 81.5%. Hence, the power saving due to the reduction of dissipation while reading is not noteworthy, although it is recorded as 1.6, 1.8, and 2 times less than that of SRAM for Type I, Type II, and Type III, respectively. On the other hand, the static power dissipated in OCPG-MRAM is approximately 1.9, 2.3, and 1.6 times more than that of SRAM for Type I, Type II, and Type III, respectively. This refers to the fact that in OCPG-MRAM, only cells are power-gated at the idle state while the peripheral circuits are always at the ON state. All FPG solutions provide energy gains over four times with respect to SRAM. This refers to different factors. First, the maximum recorded percentage of static power in FPG-MRAM is 42% from the total dissipated power, which is about half of that recorded when SRAM is adopted. This can be explained by the significant reduction of static power in FPG-MRAM when the memory is in idle state and that the memories are at OFF state most of the time. VII shows that in FPG policy, the MRAMs are OFF more than 75% of the time. It is worthy to indicate that the static power dissipated in FPG-MRAM in the idle state is approximately 39.5, 27.3, and 89.3 times less than that of SRAM for Type I, Type II, and Type III, respectively. This fact demonstrates the reduced dissipation of static energy of FPG-MRAM compared with that of SRAM. Second, the wake-up feature in the FPG policy has not added a significant overhead. The percentage of wake-up consumed power is less than 10%, as shown in Table VIII. Third, in FPG-MRAM, the dissipated power while reading is important since it dominates over the static power and wake-up power. Its percentage approaches to 65% of the total consumed power, as shown in Table IX. In addition, the SRAM power consumption while reading 256 bits is recorded about 1.6, 1.8, and 2.0 times more than that of MRAM for Type I, Type II, and Type III, respectively, whereas when 128 bits are retrieved, the SRAM reading power is 3.6 and 4.0 times more than that of MRAM for Type II and Type III, respectively. This ratio increases significantly for the If we look into details [see Fig. 12(b)], we observe the significant benefit of the proposed MRAM Type III. First, we note that Type I outperforms Type II in the case of 256 bits (about 2%). With 256 bits, the gain of read operations does not compensate the increase of the static power of the Type II switch. The balance becomes positive for Type II with respect to Type I when 128 accesses are possible. The application offers opportunities that can be exploited (from 7.7% to 16.5% for 7 and 4 missing fields, respectively). Type III outperforms Type I and Type II in any case. Type III takes full benefit of the reduced read energy that does not impact the PG switch overhead, thanks to the asymmetric scheme. Moreover, Type III can also benefit from the bitwidth granularity and efficiently exploit 32, 64, and 128-bit cases opportunities. With the 32-bit Type III memory, the gains with respect to Type I go from 39.5% to 50.5% for 7 and 4 missing fields, respectively, while the energy budget reduction is about 87% when compared with SRAM. The gains with respect to Type I and Type II decrease with the activity rate, this is logical since the PG impact is reduced as well. However, it remains: 1) strongly significant with respect to Type I even with 7 unknown fields out of 11 and 2) extremely large with respect to SRAM in all cases. Therefore, we conclude that we obtain, as expected, important energy savings when the application fits with the MBC context, namely when fully power-gated NVMs can take benefit of limited activity rates.

2) NoC: The NoC and NI clock frequency is 500 MHz in nominal case operating conditions (25 • C, 1 V). The technology used is 65-nm LP LowK Std Vt High Density Tapless Library from Virage Logic Corporation. The area and power results are obtained with the Cadence Encounter RTL Compiler tool. The register transfer level (RTL) specification of the router and the NI is synthesized in the physical layout estimation mode. The total power was obtained by using the leakage and dynamic power of the NoC and NI components, relying on the switching activity traced by the SystemC simulation. Table X shows the static and dynamic power consumption of the used NoC. When compared with baseline NI, the area and power of the proposed NI, adopting the bit selector and address finder modules, present overheads of 14.3% and 12.6%, respectively. If we consider the whole NoC, the area and power overheads are 6.1% and 5.2%, respectively.

3) PEs: The power consumption of the dedicated 32-bit PE is estimated with the following methodology. The RTL specification of PE is synthesized with the TSMC 65-nm technology. The static and dynamic power consumption of a single PE running at 500 MHz are 0.32 and 3.79 mW, respectively. The activity of each PE is derived from the number of flits, and each PE is processing according to the simulation results. The power consumption of PEs is given in Table XI.

4) Global Power Budget: Finally, we analyze the power consumption of the whole NMBA considering a 65-nm technology node. The whole architecture includes memories, NoC (routers and NI with new modules), and PE (32-bit parallel version). In Table XI, we consider the global power dissipation for seven missing fields, which is the worst case for MRAM versus SRAM since the idle time is reduced. All SRAM-and MRAM-based architectures use the same NoC, the same SNN search algorithm, and the same PE and managers. In addition to the significant power reduction, a main result lies in the major change of the power distribution. With SRAM memories, the NoC represents 35%, while the memories account for more than the half of the total power (57%). If the best MRAM type and PG policy are considered (Type III FPG), the NoC share rises to 71% and the memory one drops down to 13%. So, the use of the right power-gated MRAM leads to a point where the NoC power consumption is higher than the memory one. This allows to increase the number of memory modules and so to target large-scale applications. In our case study, this number is limited to one 256 × 256-bit memory 6.1. NETWORKED POWER-GATED MRAMS FOR MEMORY-BASED COMPUTING module. However, the general model includes multiple memory modules per cluster, as shown in Fig. 2.

VIII. CONCLUSION

This paper shows the high interest of a new type of architecture designed for MBC that can fully benefit from distributed power-gated MRAMs. Memory blocks are efficiently accessed and controlled by means an NoC with smart NIs that are configured to implement application-specific processing or content-addressable memory schemes. Although memory accesses dominate in such applications, the distributed nature of the proposed memory architecture exhibits idle states so opportunities for PG. Considering the general architecture model, this paper explores different PG schemes as well as memory block and R/W granularities. This paper shows first that limiting the PG to MRAM cells does not reduce energy consumption with respect to the use of SRAM devices. Only a full PG including peripherals is efficient and provides impressive energy reduction, higher than 87% in the considered database search application case study. This significant energy reduction is obtained by considering the specificity of the application domain (database search applications and neuromorphic architectures), where the number of memory write accesses is extremely reduced compared with the number of read accesses. In this context, an original MRAM device model (Type III) is proposed with asymmetric write bitwidth (32 bits) and read bitwidth (32,[START_REF] Skalistis | Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees[END_REF][START_REF] Kvatinsky | MAGIC-Memristor-Aided Logic[END_REF], and 256 bits). It allows to jointly limit the leakage of the power-gate switch and the read/write power consumption. This new approach brings 39%-50% more improvement compared with the symmetric fixed-granularity model. Furthermore, the validity of the proposed architecture is functionally demonstrated with an application that can take advantage of MBC, namely a database search application implemented with an SNN approach. Sys-temC simulations have been conducted targeting hundreds of database queries with a high hit ratio of about 94%. Finally, the results show that such an approach can significantly modify the power budget breakdown between NoC and memory. This allows to increase the number of memory modules and so to target large-scale applications. Future work should address the reduction of NoC power consumption and the use of programmable logic in NI to allow their dynamic configuration according to the application requirements.

MRAM-based memorization system for NB-LDPC decoder

This research work investigates the use of emergent non-volatile STT-MRAM technology in designing energy-efficient components in the digital communication domain. The main aim is to reduce the power consumption due to memory accesses during intermediate processing of received data. To address this issue, an adaptive and efficient memorization system based on STT-MRAM is proposed to be implemented within Non Binary-Low Density Parity Check (NB-LDPC) decoder [START_REF] Boutillon | Design of a GF(64)-LDPC decoder based on the EMS algorithm[END_REF]. Based on the available MRAM types and array dimensions, new data mapping and efficient structure of the memorization system are proposed.

The power consumption of the NB-LDPC decoder with STT-MRAM is evaluated and compared to SRAM-based one. Simulation results show that when MRAMs are used, the proposed memorization system offers a significant energy reduction along with an increase in terms of throughput.

This work has been performed in the context of the Master's degree project at the Lebanese International University and has been published in the proceedings of IEEE International Conference on Microelectronics (ICM) [START_REF] Sabbah | MRAM-based memorization system for NB-LDPC decoder[END_REF] and in the proceedings of IEEE International Conference on Computer and Applications (ICCA) [START_REF] Sabbah | Enhanced throughput and energy-efficient MRAM-based NB-LDPC decoder[END_REF]. Moreover, the publication in the IEEE International Conference on Microelectronics (ICM) [START_REF] Sabbah | MRAM-based memorization system for NB-LDPC decoder[END_REF] was attributed one of three best student paper awards in 2017.

Memristor Based Reconfigurable FFT Architecture

Preface

This research work has been accomplished as a part of the PhD thesis of Khaled Alhaj Ali at IMT Atlantique, Brest, France. The thesis aimed to explore and introduce new memristorbased designs that combine flexibility and efficiency through the proposal of original architectures that break the limits of the existing ones. This work has focused on using memristive devices at interconnect level to allow high degree of flexibility based on programmable interconnects, where memristors are inserted as reconfigurable switches in order to establish on-chip routing. This research work has been published in the proceeding of the IEEE International Conference on Microelectronics (ICM) [START_REF] Ali | Towards memristorbased reconfigurable FFT architecture[END_REF].

Introduction

The recent development of new non-volatile memory technologies based on the memristor [START_REF] Chua | Memristor-the missing circuit element[END_REF] concept has triggered many efforts to explore their potential usage in different application domains. This novel type of two terminal nano-scale elements presents very fast switching characteristics, non-volatile dense storage capacity, and low power consumption.

Main part of conducted efforts aims to exploit them for establishing a unified and efficient memory system replacing current flash and CMOS-based memories. Before the discovery of the HP memristor, memristive devices were only employed as storage elements. Since the HP Labs presented the T i O 2 memristor in 2008, rapid progress on the fabrication of high-quality memristors has been achieved in the past few years [START_REF] Lee | Evidence and solution of over-reset problem for HfO x based resistive memory with sub-ns switching speed and high endurance[END_REF][103] [START_REF] Kang | Design and application of oxide-based resistive switching devices for novel computing architectures[END_REF]. These memristors are characterized by huge gap between their low resistance state (LRS) and high resistance state (HRS). This evolution has received significant attention and allowed for employing these devices in new fields such as non-volatile programmable switches. Memristor-based programmable switches are introduced to achieve efficient and low cost flexibility in ASIC designs. Such flexible designs are reconfigured allowing for efficient reuse of resources for different application need. Moreover, memristors have been explored as potential alternative to the traditional programmable interconnects in FPGAs [2][105][106] [START_REF] Dong | 3-D nFPGA: A reconfigurable architecture for 3-d cmos/nanomaterial hybrid digital circuits[END_REF].

The possibility to integrate memristors on top of CMOS logic gates allows for new design ideas based on close combination and interaction between memory and computation. This introduces new opportunities of efficient reconfiguration, high performance, and low power design. Designing flexible architectures, which can adapt dynamically to application needs, bring great advantages in terms of energy efficiency and performances. Such flexibility is required at processing, interconnect, and memory levels. Current technologies are inefficient for highly self-adaptive systems, due to the cost of reconfiguration, including delay and power consumption [START_REF] Kuon | Measuring the gap between FPGAs and ASICs[END_REF] [2]. Flexibility is particularly required in digital communication and multimedia applications where new standards and multiple service modes are continuously emerging, with strengthen requirements in terms of performance and energy efficiency.

In this context, the integration of memristors at the interconnect level to enable flexible and efficient configuration of digital architectures is explored. This work has proposed memristor-based reconfigurable fast Fourier transform (FFT) architecture. To the best of our knowledge, this is the first memristor-based FFT design in the literature. The proposed original architecture allows an efficient support of any combination of radix-2 and radix-3 butterflies. Scalability is ensured through a 2D mesh topology. Flexibility is realized at the level of interconnects, allowing for optimized hardware reuse through a memristor-based non-volatile routing.

Context and Motivations

Memristors are employed to implement non-volatile routing switches by logically connecting/disconnecting wires during configuration mode. Non-volatile routing preserves the configuration information stored on-chip while powered OFF, allowing the devices to immediately run when it is powered up. On the other hand, leakage power is minimized during stand-by mode, leading the system to work at extremely low-power. Moreover, the opportunity to fabricate memristors on the top of transistor layer in the same die brings significant reduction of the overall area of the system design.

These features are of high interest when targeting multi-mode ASIC designs as well as high-end FPGAs. It is reported that the routing resources in an FPGA (Figure 6.1) including switch blocks (SBs), connection blocks (CBs) and interconnects can account for up to 70% of the total area, delay, and consumed power [START_REF] Kuon | Measuring the gap between FPGAs and ASICs[END_REF]. Thus, the improvement of these programmable routing elements in FPGAs is of importance for research and development. In For instance, authors of [2] have proposed an FPGA architecture with memristor-based reconfiguration (mrFPGA). The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay. As demonstrated in Figure 6.2, the area of mrFPGA has been reduced to the total area of the logic blocks only, which takes 10% to 20% of the conventional FPGA area. Several studies [START_REF] Gaillardon | Emerging memory technologies for reconfigurable routing in FPGA architecture[END_REF] [START_REF] Tanachutiwat | FPGA based on integration of CMOS and RRAM[END_REF] have demonstrated the use of memristive devices as programmable switches instead of SRAM-based pass transistors in conventional FPGAs. Figure 6.3 shows the structures of conventional SRAM routing switch and the two memristor switches proposed [START_REF] Tanachutiwat | FPGA based on integration of CMOS and RRAM[END_REF].

FFT [START_REF] Cooley | An algorithm for the machine calculation of complex fourier series[END_REF] has been chosen as application case study since it is used widely in the fields of digital signal processing and telecommunications. Particularly, FFT is considered recently as an effective tool for spectrum enhancement of orthogonal frequency division multiplexing (OFDM)-based waveform, which is a central element in the fifth generation new radio (5G-NR) developments [START_REF] Yli-Kaakinen | FFTdomain signal processing for spectrally-enhanced CP-OFDM waveforms in 5G new radio[END_REF]. Furthermore, the size of FFT block can vary according to the system parameters and the communication channel conditions. Thus, there is a real need for highly flexible FFT implementations that support multiple configurations. The attained It is possible to implement a fully-parallel FFT flow graph directly in hardware. However, for large FFTs it may be infeasible, since the area usage would be too large [START_REF] Löfgren | On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems[END_REF]. In case of a power of 2 FFT size, radix-2 butterfly (BF) is typically used [START_REF] He | A new approach to pipeline FFT processor[END_REF]. Different radix butterflies are also proposed either to support different FFT sizes (not power of 2) and/or to reduce the computational complexity. If the application requires to have different radices, typical inefficient implementations duplicate the hardware resources. Reconfigurable implementations of FFT have been presented in the literature. Implementations with simplest form of reconfiguration exploit certain portion of the hardware resources for one radix while other independent parts are reserved for another radices. These implementations allow the concatenation/combination of several processing elements having different radices on the cost of duplication of hardware resources. Thus, they are considered inefficient in terms of area and energy. Other implementations the same processing elements can be reused for executing other radices at different instants of time. These implementations are considered reconfigurable/flexible. Figure 6.4(a), illustrates how certain portion of the hardware resources are exploited for one radix while other independent parts are reserved for another radices. Whereas, Figure 6.4(b), illustrates how the hardware resources, which are utilized for executing certain radix, can be reused for executing other radices at different instants of time. The authors in [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF] have proposed a reconfigurable FFT design that is able to support 48 different configurations with an FFT size up to 2187. The design is composed of several reconfigurable bricks, which are arbitrarily concatenated to build up a system with reconfigurable FFT size. Flexibility is achieved through a reconfigurable processing element that implements six combinations of radix-2 and radix-3 butterflies.

R a R b R c R d R a R b R c R d R a R b R c R d Enabled Disabled R a R b R c R d R a R b R c R d R a R b R c R d (a) (b)

Conducted Work and Achieved Results

In this research work, a memristor-based reconfigurable FFT architecture (mrFFT) is proposed, which allows the efficient support of many configurations with different FFT sizes. The architecture can be employed in a reuse and systematic way to support radix-2 and radix-3 kernels [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF]. Flexibility is achieved by inserting memristors at the interconnect level leading to programmable memristive nodes.

The main contributions of this work are:

• Investigate the structures of the flow graphs of FFT radices. This reveals that it is possible to extract similar/common parts. These similarities are exploited toward realizing efficient re-usability of hardware resources leading to efficient flexible designs. In particular, the analysis of radix-2 and radix-3 flow graphs shows that a radix-3 flow graph can be split into three similar butterflies and a separate real multiplier.

• Introduce the reconfigurable BF, so called RBF, which can be configured to execute radix-2 BF or any part of the radix-3 BF with the minimal added cost.

• Propose the mrFFT architecture based on RBF design with FPGA-like resource arrangement, where a group of RBFs are arranged in a 2D mesh topology with memristor-based interconnections serving as routing elements.

• Design the peripheral circuits, dedicated controller and selection blocks, that are used to reconfigure the states of the implemented memristors.

• Demonstrate the efficiency of the proposed architecture to support of 44 configurations with different FFT sizes including the 32 operating modes that are defined in 3GPP-LTE standard.

• Conduct preliminary comparisons with state-of-the-art work [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF] in terms of used resources and hardware re-usability ratio in order to determine the relevancy of our proposed mrFFT design.

Findings

The presented mrFFT design accommodates the 32 operating modes that are defined in 3GPP-LTE standard [START_REF] Gpp | Evolved universal terrestrial radio access (E-UTRA); physical channels and modulation[END_REF][START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF]. However, mrFFT is scalable in size and can be extended. Thus, it is able to support other FFT configurations in case of any future standard changes.

The amount of utilized resources in our proposed design has been estimated and compared to that in [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF]. The comparison shows that mrFFT reduces significantly the number of the utilized adders (25%), multipliers (37%), 2-to-1 multiplexers (59%), 3-to-1 multiplexers (100%) and FIFOs (25%). On the other hand, the design in [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF] has a 55.5% less number of 1-bit shifters. However, these shifters have a trivial implementation.

The attained gains in mrFFT come at the cost of the adopted routing scheme, which incorporates a set of 119 memristive node in addition to the corresponding selection blocks. In fact, the implementation cost of the selection blocks can be relatively reduced when shared to other designs targeting the same flexibility requirements.

Moreover, the percentage of resource activation has been evaluated in both designs among all supported configurations. The obtained results show better utilization of adders and multipliers in mrFFT compared to that in [START_REF] Shih | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3 2 and Radix-2 3 Design Approaches[END_REF]. This implies better hardware reusability ratios.

The evaluation of the devised mrFFT architecture has been limited to an analytical estimation of the utilized resources, the percentage of activation and the reusability ratio. Power consumption and delay analysis could not be evaluated for this first proposed design as analog/digital mixed-signal simulation environment is required, which relevant tools have not been easily available.

Hybrid Memristor-CMOS Design for Logic Computation 6.4.1 Preface

This research work aims to explore the use of memristive devices and their integration with CMOS technologies for combinational logic design. Such hybrid memristor-CMOS designs should exploit the high integration density of memristors in order to improve the performance of digital designs, and particularly arithmetic logic units. It has been conducted as apart of the PhD thesis of Khaled Alhaj ALI at IMT Atlantique, Brest, France. This research work has been initially published in the proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS) [START_REF] Ali | MRL crossbar-based full adder design[END_REF]. Then, the detailed architecture and results have been published in Electronics [118].

Introduction

Memristor technology has recently triggered many efforts to extend their usage from memory to computing [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF][START_REF] Linn | Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations[END_REF][START_REF] Kvatinsky | Memristor-based material implication (IMPLY) logic: Design principles and methodologies[END_REF][START_REF] Amaru | Majority-inverter graph: A new paradigm for logic optimization[END_REF][START_REF] Guckert | MAD gates-memristor logic design using driver circuitry[END_REF]. Memristor based logic design is an emerging concept targeting efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor-CMOS logic family [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF]. MRL requires efficient design strategy that takes into consideration the implementation phase.

In fact, MRL is a hybrid memristor-CMOS logic family. The goal behind MRL is to implement conventional combinational logic circuits which are the building blocks of digital systems. The main idea is to replace as much as possible transistors with nano-scale size memristors, while keeping the same role of the intended digital architecture. Several works have utilized MRL design style to implement various digital architectures [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF][START_REF] Liu | A signal degradation reduction method for memristor ratioed logic (MRL) gates[END_REF][START_REF] Chowdhury | Implementation of 24T memristor based adder architecture with improved performance[END_REF]. The integration of memristors and CMOS devices in MRL still lacks a consistent way for arranging memristors at the top of CMOS layer. The integration should be realized in such a way that exploits efficiently the promising characteristics of memristive devices such as density and scalability.

In this research work a novel MRL-based crossbar design namely X-MRL has been introduced. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The design methodology of X-MRL efficiently integrates memristors with CMOS devices to improve density and scalability. The evaluation of the proposed approach is performed through the design of X-MRL based full adder. The design is presented with the layout and the corresponding simulation results using Cadence Virtuoso toolset.

Context and Motivations

The fast decline of Moore's law is paving the way to explore new set of emerging technology devices [START_REF] Shalf | Computing beyond moore's law[END_REF], as it is difficult to overcome the various physical limitations of the traditional CMOS technology [START_REF] Kuhn | Considerations for ultimate cmos scaling[END_REF]. In this context, the nano-scale size memristor was introduced as a possible alternative candidate as it offers a lot of advantageous features including the capability of executing Boolean logic [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF][128] [START_REF] Kvatinsky | Memristor-based IM-PLY logic design procedure[END_REF] in addition to the storage role. The presence of these two attributes combined has given a great impetus to explore new innovative circuits and systems based on memristors. For instance, one of the main challenges of modern computers nowadays is the memory wall problem which is originated from the mismatch in the performance of processor and memory. There has been a continuous effort to move processing cores closer to where data resides to address the memory wall problem. A memristor-based logic can integrate processing and storage role (in-memory computing), an attribute which can be a promising solution to scale the memory wall.

Several memristor-based logic design styles have emerged in the literature [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF] [START_REF] Gao | Programmable cmos/memristor threshold logic[END_REF] [121] [START_REF] Kvatinsky | MAGIC-Memristor-Aided Logic[END_REF] [123] [START_REF] Amaru | Majority-inverter graph: A new paradigm for logic optimization[END_REF] . Each has its own capabilities and thus is adapted for a specific type of applications. A memristive logic design style is able to compute a certain primitive logic such as AND, OR, NOR, etc. Based on these simple operations, complex arithmetic functions can be executed as any Boolean function could be written in the form of the sum of products (SoP).

The advent of memristor-CMOS process that combines CMOS devices with the nanoscale size memristors have provided new opportunity to reduce the utilization of silicon area. However, yet CMOS devices which are considered active, cannot be totally replaced by the passive memristive devices. Thus, the integration of CMOS and memristors is essential to the development of memristor technology. To this end, hybrid configurations have been proposed that make use of the advantages of CMOS while utilizing the high density of memristors. On the other side, out of the available memristor-based logic design styles, the MRL is the only design style that meets the conventional CMOS in terms of the adopted state variable. Both MRL and CMOS use the voltage as the only state variable for representing inputs and outputs throughout all intermediate stages. Thus, MRL is very qualified for the integration in the current CMOS designs and even later can dominate. Also, the computation is accomplished in one single step. This criterion eliminates the drawbacks of the sequential process of other memristor-based logic devices.

In fact, MRL is a hybrid memristor-CMOS logic family, where the programmable resistance of memristors is exploited in the computation of the Boolean AND and OR functions. The goal behind MRL is to implement conventional combinational logic circuits which are the building blocks of digital systems. The main idea is to replace as much as possible transistors with nano-scale size memristors, while keeping the same role of the intended digital architecture. Several works have utilized MRL design style to implement various digital architectures [START_REF] Kvatinsky | MRL-memristor ratioed logic[END_REF] [124] [START_REF] Chowdhury | Implementation of 24T memristor based adder architecture with improved performance[END_REF]. The integration of memristors and CMOS devices in MRL still lacks a consistent way for arranging memristors at the top of CMOS layer. The integration should be realized in such a way that exploits efficiently the promising characteristics of memristive devices such as density and scalability.

Conducted Work

This research work introduce the novel X-MRL approach, which is dedicated for the implementation of combinational logic. For evaluation purposes, a hybrid memristor-CMOS full adder based on X-MRL approach has been devised. The main contributions of this work are:

• Introduce the X-MRL approach for realizing Boolean computation. Using X-MRL, Boolean functions are represented using pairs of memristors mapped efficiently into crossbar structure. A memristive crossbar is a two dimensional grid of memristors distributed along vertical and horizontal nanowires. A memristor is allocated between every vertical nanowire (so-called a column) and horizontal nanowire (so-called a row).

• Devise the architecture design for a full adder based on X-MRL approach. The proposed design includes memristors to execute MRL-AND and MRL-OR operations existing in the SOP of the 1-bit full adder and several CMOS inverters that are responsible for either inverting (NOT operation) and/or performing signal restoration for the logical state of the signal after several cascading stages.

• Determine the layout of the obtained X-MRL full adder architecture using Cadence Virtuoso toolset. Three layers are used. A polysilicon layer is dedicated to the connection of the gates of NMOS and PMOS transistors. Two metal layers are adopted to implement the horizontal and vertical wires of the crossbar structure. As the height of memristors is too short, vertical interconnect accesses (VIAs) are utilized to connect the two metal layers and the memristors are allocated at the top of the VIAs.

• Conduct simulations using Cadence Virtuoso toolset of the tailored architecture while adopting the VTEAM model to realize a realistic modeling of practical memristors. An important work has been done to determine the VTEAM [START_REF] Kvatinsky | VTEAM: A general model for voltage-controlled memristors[END_REF] model parameters that fit with the physical parameters of the memristor device that matches the MRL [START_REF] Lee | Evidence and solution of over-reset problem for HfO x based resistive memory with sub-ns switching speed and high endurance[END_REF].

Transient simulations are performed adopting CMOS 65 nm technology at standard 1.2V to produce the performance analysis and energy consumption.

• Compare the proposed hybrid memristor-CMOS based full adder with previous published designs, which are dedicated to the 1-bit full adder.

Findings

Timing:

The conducted simulation shows that the values of the rising time T r , falling time T f and time delay T d are affected by the switching speed of the memristor which in turn can be controlled by the fitting parameters. On the other hand, slowing down the switching speed of the memristors increases the glitches. The high resistance state (R OF F ) of the memristors has a direct effect on the value of T d which increases when increasing the value of R OF F . Moreover, it is noticed that increasing R OF F acts as a filter for the glitches. Therefore, the total delay is directly affected by the memristor physical properties.

Energy consumption:

The value of the average power consumption is relatively high for a full adder circuit. This is due to the low values of low and high resistance states of the adopted memristor device compared to the source-to-drain dynamic resistance in MOSFETs, which minimizes the leakage in current.

Memristive devices are still being actively explored and developed using a variety of materials and deposition techniques. Thus, there is the potential for the device characteristics to be improved. Memristors with high values of (R ON N ), which corresponds to LRS, and (R OF F ), which corresponds to HRS, have to be developed in order to achieve hybrid architectures with low power consumption.

Area:

The memristors are implemented at the top of CMOS due to their nano-scale and compatibility at the level of fabrication. Thus, the allocated memristors in the proposed X-MRL design do not add any overhead in terms of implementation area. The total required area refers to that occupied by CMOS devices only, which depends on the number of used inverters. The total area of the X-MRL design is 8.16 µm 2 compared to 14.78 µm 2 which is utilized in the case of pure CMOS implementation, leading to 44.79% area saving.

Comparison:

All related works published in the literature lack an estimation about the utilized area for their proposed designs. In order to achieve a fair comparison in terms of energy consumption, the energy is evaluated per 1 addition operation. The Energy.Delay metric is used for comparison. It reveals an improvement between ×5.7 and ×31 with respect to the available literature [START_REF] Liu | A signal degradation reduction method for memristor ratioed logic (MRL) gates[END_REF] [START_REF] Thangkhiew | Area efficient implementation of ripple carry adder using memristor crossbar arrays[END_REF].

Introduction

The memristor is the fourth fundamental circuit element, which relates charge and magnetic flux linkage. It was originally predicted by Professor Leon Chua in 1971 [1]. The memristor was realized later by members of HP Labs in 2008 [2]. This successful realization opened a wide area of research on the memristor and its possible applications. The HP memristor is a solid state device formed of a nanometer scale TiO 2 thin film, containing a doped and an undoped region sandwiched between two platinum electrodes. The obtained two-terminal device exhibits a dynamic resistance that is bounded between a minimum value (R ON ) and a maximum value (R OFF ). Its resistance depends on the magnitude, direction and duration of the applied voltage across its terminals. The last attained resistance value of the memristor before withdrawing the applied voltage is naturally retained. Memristors are promising in the field of non-volatile memories (NVM) because of their capability for data retention [3] with zero standby power and compatibility with a conventional CMOS in terms of fabrication and operating voltages. Due to their versatile nature, the use of memristors has been extended from memory to computing [4]. Several memristive logic design families have emerged in the literature, each with its own characteristics, capabilities and usage. Memristor Aided Logic (MAGIC) [5] and the Material Implication (IMPLY) [6] are considered as memristive stateful logic families [7]. They were introduced to allow logic computations inside memristive memory systems and are being explored to overcome the memory wall problem. Memristor-Ratioed Logic (MRL) [8] is another memristor-based logic design style. MRL is a hybrid memristor-CMOS logic family. Its goal is to implement conventional combinational logic circuits, which are the building block of digital systems [8][9][10][11]. The main idea behind MRL is to replace as many transistors with nano-scale size memristors as possible while keeping the role of the intended digital architecture the same.

Of the above-mentioned logic design styles, MRL is the only approach that matches the conventional CMOS in terms of the adopted state variable. Both MRL and the CMOS use voltage as the only state variable to represent inputs and outputs throughout all intermediate stages. Thus, MRL is the most qualified for integration in current CMOS designs. However, this integration should be performed in a way that efficiently exploits the promising characteristics of memristive devices, such as density and scalability. This can be achieved through the use of the crossbar structure, which is a highly adapted topology for arranging memristors at the top of the CMOS layer.

In this paper, we propose an MRL-based crossbar design: X-MRL. X-MRL is intended for implementing combinational logic. The conventional CMOS logic gates are implemented using MRL, and an original mapping into a crossbar structure is proposed. The proposed methodology efficiently combines the density and scalability attributes of crossbar arrays and the ability to implement memristors at the top of the CMOS layer. The proposed approach is evaluated by designing an X-MRL-based full adder circuit [12]. The designed architecture is implemented and simulated with the Cadence Virtuoso toolset.

The rest of the paper is organized as follows. Section 2 describes the behavior of the memristor and the corresponding available models. Section 3 presents a brief review of the MRL design style. Section 4 presents the proposed X-MRL design for realizing Boolean computation. Section 5 provides and discusses the simulation results and performance analysis. A comparison with previous published designs is presented in Section 6. Finally, Section 7 concludes the paper.

Memristor Behavior and Modeling

Chua [1] has defined the memristor as a previously missing relation between the flux φ and the charge q, yielding the defining relation

M(q) = dΦ/dq (1)
The current-voltage (I-V) characteristic of a memristor has the form of a pinched hysteresis loop, as illustrated in Figure 1a. The hysteresis phenomenon indicates that memristor resistance could be modulated between two resistance states R ON and R OFF . Figure 1b schematizes the 3D structure of the memristor device, and Figure 1c depicts the typically used symbol to represent a single memristor. HP Labs has described the physical model of a memristor as shown in Figure 2; it consists of two layers of TiO 2 sandwiched between platinum contacts [2]. One of the TiO 2 layers is doped with oxygen vacancies, while the other is left undoped. As a result, the doped region behaves as a semiconductor while the undoped region behaves as an insulator.

The width of the doped region w(t) varies between zero and a memristor length of D according to the amount and direction of the electric charges q(t) moving across the memristor. Thus, applying a certain bias to the memristor leads to the flow of current, which in turn changes the value of w(t). Therefore, the virtual boundary separating the doped and undoped regions moves, leading to a variation in the memristor's total resistance R MEM as expressed in Equation ( 2) [2].

R MEM (x) = R ON (x) + R OFF (1 -x) (2)
where x = w D ∈ [0, 1] and R ON and R OFF are the limiting values of memristor resistance when w = D and w = 0, respectively. The speed of the boundary movement between the two ends is called the drift velocity and is represented by the state equation [2]

dx dt = ki(t) f or k = µ v R ON D 2 (3)
where µ v is the dopant mobility. Equation (3) considers that the drift velocity is constant, resulting in a linear drift model of the memristor. However, the experiments presented in [13,14] proved that the behavior of the implemented memristor is non-linear. To manage the issue of nonlinearity, several models have been proposed in the literature. In [14], the authors proposed a non-linear dopant drift model as a relation between the current and voltage (I-V) of the memristor. In [15], the drift velocity was expressed using a window function f (w) in order to model the non-linearity, as expressed in Equation (4).

dw dt = a f (w)V(t) m (4)
where a and m are constants, f (w) is the window function and m is an odd integer. The previous presented models are based on the HP physical representation of a memristor.

In [13]

dx dt =    C o f f sinh i i o f f exp -exp x-a o f f wc -|i| b -x wc C on sinh i ion exp -exp x-aon wc -|i| b -x wc (5)
where the state variable x represents the width of the Simmons tunnel barrier, C o f f , C on , a o f f , a on , w c and b are the fitting parameters, and i o f f and i on are the current thresholds of the memristor. Obviously, Equation (5) shows that the Simmons tunnel barrier model is more complicated; thus, it is computationally inefficient. In order to attain a simplified and general model, Kvatinsky et al. [17] presented the TEAM model, which represents in simpler expressions the same physical model as the Simmons tunnel barrier model. Equation ( 6) expresses the state equation representing the TEAM model:

dx dt =          K o f f i(t) i o f f -1 α o f f f o f f (x), 0 < i o f f < i K on i(t) ion -1 αon f on (x), i < i on < 0 0 otherwise (6)
where i on and i o f f are the current thresholds of the memristor. K on , K o f f , α on and α o f f are fitting parameters, and f on (x) and f o f f (x) are the corresponding window functions of the memristor. However, experimental data acquired from several memristive devices reveal the existence of a voltage threshold rather than a current threshold [18]. In [18], the TEAM model was extended to the VTEAM model. Equation ( 7) describes the VTEAM model. It is similar to the expression in Equation ( 6), except for the voltage dependence v(t) and the respective SET and RESET voltage thresholds v on and v o f f . Moreover, the VTEAM model is considered as a general model since it can be fitted to any other memristor model [18]. Normally, the window function f (x) is added for a memristor model in order to decelerate the moving boundary of the memristor before reaching its extremities and to guarantee a zero speed exactly when it reaches either one of them. In this study, we have adopted the VTEAM model to describe the simulated memristor as it provides simple and realistic modeling.

dx dt =        K o f f v(t) v o f f -1 α o f f f o f f (x), 0 < v o f f < v K on v(t) von -1 αon f on (x), v < v on < 0 0 otherwise (7

Memristor-Based Logic Design Styles

In the literature, three main design styles for using memristors in logic design can be found. The first two design styles, which are IMPLY [6,19] and MAGIC [5], exploit only memristors for logic implementations. The third design style, known as MRL [8], adopts a combination of CMOS and memristor devices. This section presents a brief overview of these design styles.

Material Implication IMPLY Gates

In IMPLY, the memristor states (R OFF , R ON ) represent the logical state variables (0, 1), respectively. As shown in Figure 3a, the gate consists of the two memristors p and q and the resistor R G . The initial memristances of p and q represent the input to the gate, while the output is written into memristor q after applying V COND and V SET simultaneously. The truth table of the IMPLY gate is shown in Figure 3b, where p -→ q = p + q can be used as a basis for any logic function. As a result, the same memristors are used to store the logical state and/or perform a logical operation. Consequently, the computation requires several sequential operations. Several approaches have been proposed in the literature that adopt IMPLY for the execution of combinational logic [6,20,21]. All available designs require several time steps to accomplish the target computations. This fact leads to an overhead in terms of time delay compared to other logic implementation techniques.

V COND V SET R G p q (a) p q p  q 0 0 1 0 1 1 1 0 0 1 1 1

IMPLY gate Truth table

(b)

Memristor Aided Logic (MAGIC)

MAGIC is a memristor-only logic design style that supports Boolean functions [5]. Unlike IMPLY, this logic family makes use of separate memristors to store the input bits, and an additional memristor is used to store the output bit. Figure 4 illustrates the 2NOR1 MAGIC gate where in 1 and in 2 serve as the input memristor and out serves as the output memristor. The logic state in MAGIC implementation is represented by the resistance stored in the utilized memristors, where R OFF and R ON represent logic "0" and logic "1", respectively. Thus, when driving the gate with voltage V 0 , the result of the NOR operation of in 1 and in 2 is written simultaneously into out.

Applications of MAGIC in memristor-based crossbars are straightforward when using MAGIC NOR, while an additional resistor is required in case of other gates. The authors of [22][23][24] used the MAGIC NOR as the basis to perform logic computation inside the memory, thus adding processing capabilities. In other words, each processing task is divided into a sequence of MAGIC NOR operations, which are executed one after the other using the memory cells as computation elements.

MAGIC-NOR gate

Memristor Ratioed Logic (MRL)

The third design style of memristor-based logic is Memristor Ratioed Logic (MRL) [8]. It is a typical hybrid CMOS-memristor logic design where the programmable resistance of memristors is exploited in the computation of the Boolean AND and OR functions. MRL opts for voltage as the state variable, in a similar manner to CMOS-based devices; thus, the computation is accomplished in a single step. This criterion eliminates the drawbacks of the sequential process of IMPLY logic devices. Figure 5 depicts the structures of the MRL AND, NAND, OR and NOR gates. Both OR and AND gates consist of two anti-serial memristors (i.e., connected serially with opposite polarities), whereas for NOR and NAND, a CMOS inverter is added at the output. Both MRL AND and OR gates react similarly when identical values are set to their input ports (when both inputs are set either to logic "1" or "0"). In this case, no current flows through the anti-serial memristors, leading to the transfer of the input voltage to the output. In the case where different values are set to the input ports (i.e., the first port is set to "0" and the second port is set to "1", or vice versa), a current flows from the port with higher potential (logic "1") to the port with lower potential (logic "0"). The resulting potential difference changes the internal state of both memristors in an opposite manner. One memristor tends to attain the R ON state while the other tends to attain the R OFF state. In addition, the connected memristors form the well-known voltage divider circuit. Assuming R OFF >> R ON , Equations ( 8) and ( 9) present the obtained output values V out of MRL OR and AND gates, respectively [8].

V out,OR = ( R OFF R OFF + R ON ) × V CC ≈ V CC (8)
V out,AND = (

R ON R ON + R OFF ) × V CC ≈ 0 (9)
Note that the output voltage V out converges to the higher potential (logic "1") in the MRL AND gate and to the lower potential (logic "0") in the MRL OR gate. Figure 6 illustrates the logical operations of the MRL AND gate corresponding to all input combinations. However, cascading several MRL gates leads to a floating output (between logic "0" and logic "1") due to voltage degradation [8]. Since memristors are passive devices, they cannot amplify signals. Therefore, CMOS inverters can be used as buffers after several stages to restore the attained logical state [8].

R0 ≈ R OFF R1 ≈ R ON V out ≈ Gnd R0 ≈ R ON R1 ≈ R OFF V out ≈ Gnd V out ≈ Vcc Current flow=0 V out ≈ Gnd
Several recent research works presented in the literature exploit the use of MRL to design basic building blocks. In [8], a design dedicated to a universal full adder circuit was proposed using MRL gates with the aid of CMOS inverters instead of pure CMOS-based gates. In [25], the authors demonstrated a simple circuit based on MRL which is capable of executing AND, OR and XOR in parallel. The design is considered to be hybrid. However, cascading several stages of this circuit degrades its performance due to the voltage drop at the output. In [11], the authors presented an implementation strategy for a memristorbased Programmable Logic Array (PLA). The memristor-based circuit transformation of PLA is based on MRL gates. However, the arrangement of memristors at the top of the CMOS layer and the corresponding layout were not investigated by the authors.

Proposed X-MRL Design for Logic Computation 4.1. X-MRL Structure

A memristive crossbar is a two-dimensional grid of memristors distributed along vertical and horizontal nanowires. A memristor is allocated between every vertical nanowire (called a column) and horizontal nanowire (called a row). A memristive crossbar is characterized by its simple and dense structure [26] and could be fabricated on the top of a CMOS layer [27]. The potential applications of memristive crossbars range from memory to logic and from digital circuits to analog circuits. On the other hand, MRL is the only memristorbased logic design style that adopts voltage as a state variable. Thus, our proposed design considers the implementation of a combinational Boolean function in a crossbar topology.

It is well known that any Boolean function could be written in the form of the sum of products (SoP). Accordingly, it can be implemented using MRL-AND and MRL-OR with the aid of CMOS inverters. In order to clarify the proposed method, Figure 7 illustrates the design and implementation of the simple function F = AB + AC. Figure 7a shows that the function F is implemented using two MRL-AND gates and one MRL-OR gate. Figure 7b depicts the schematic layout, which illustrates the equivalent mapping of the function onto a crossbar structure. The vertical pairs of memristors corresponding to MRL-AND generate an output which drives the input of the horizontal pair that represents MRL-OR. Figure 7c presents a 3D view of the resulting crossbar structure. Figure 7d is another simplified representation of the obtained crossbar. The same procedure could be performed to implement other Boolean functions. Although the obtained array is a combination of AND and OR gates, the positive poles of the allocated memristors rely on the same planar side, which is considered to be an advantage at the level of their fabrication.

X-MRL Full Adder

This subsection presents, as an example, the design of the 1 bit full adder using the X-MRL design technique. Equations ( 10) and (11) present the expressions of the 1-bit full adder in the SoP format.

S = A ⊕ B ⊕ C in = C in (AB + AB) + C in (AB + AB) (10)
C out = AB + BC in + AC in (11) where A and B are the inputs, C in is the input carry, S is the 1-bit adder output and C out is the output carry. Figure 8a presents the direct form of an MRL based 1-bit full adder. Figure 8b presents the proposed circuit design of the 1-bit full adder using an MRL-based crossbar structure. The design requires 18 memristors, which are distributed among vertical and horizontal wires, in addition to nine CMOS inverters. In the figure, the black vertical pairs of memristors represent the AND gates while the gray horizontal pairs represent the OR gates (as illustrated in Figure 7). The CMOS inverters are responsible for either inverting (NOT operation) and/or performing signal restoration for the logical state of the signal after several cascading stages.

It is worth noting that the designed X-MRL array is different from conventional crossbar arrays as a certain number of crosspoints are vacant. In this array, all memristors are accessed simultaneously, leading to deterministic current paths. Thus, there are no unexpected current paths, and consequently it is sneak-path free.

Layout

The circuit of the full adder is composed of a memristor crossbar layer in addition to a few inverters. Figure 9 presents the layout of the circuit using the Cadence Virtuoso tool. In this layout, the positions of the allocated memristors are assigned virtually due to the lack of their definition in the Cadence library. The layout is mainly composed of three layers. The first layer is the polysilicon layer, which is dedicated to the connection of the gates of NMOS and PMOS transistors. This layer is presented in red in the figure . The second and third layers, which are called Metal1 and Metal2 and presented in the figure in violet and blue, respectively, are dedicated to the wiring. In order to achieve the desired crossbar structure, horizontal wires are constructed in the Metal2 layer, while for the vertical wires, the connections that are already utilized for the implementation of the required CMOS inverters are reused to complete the crossbar structure. However, the height of the utilized memristors is too short (around 10 nm [28]) to allow the linkage of horizontal and vertical wires through two different layers. Therefore, these links are achieved through vertical interconnect accesses (VIAs) as demonstrated in [29]. Figure 10 is a schematic view and cross-sectional transmission electron microscopy (TEM) image of a memristor integrated with a CMOS in the same die [29]. The allocated memristors in our proposed layout are implemented at the top of the VIAs immediately under the Metal2 layer. Accordingly, the CMOS inverters occupy most of the utilized area, and the additional Metal2 layer is reserved for memristors. In fact, the designed crossbar causes N-wells and P-wells to be slightly too far from each other. The obtained layout design could be made more compact if the memristors were implemented immediately above the CMOS devices. However, this prevents the realization of an X-MRL approach, as more routing signals would be then added, leading to more wiring in Metal1 and Metal2 layers. This would again cause N-wells and P-wells to be distant from each other, increasing the area overhead.

Simulation and Performance Analysis

Memristor Model Fitting

Physical models of memristors, which are based on filament formation and rupture [30,31] rather than a simplified moving boundary (as described by HP), are more realistic. However, compared to physical models, a compact model (e.g., VTEAM) provides the possibility of rapidly reproducing the phenomenological electrical behavior of memristors with a low computational cost. Accordingly, the VTEAM model has been adopted in this paper for simulation. The VTEAM model can mathematically fit the measured electrical behaviors of a memristor and can be easily extended to different types of memristors. In contrast, other models (e.g., the Stanford model [32]) focus on a specific type of memristors or even a single memristor device. Table 1 provides the experimental data of various available memristors with their respective properties. Other memristive devices that belong to the STT-MTJ family [33,34] are excluded from the table. This is due to the fact that MTJ devices usually exhibit a low R OFF /R ON ratio that does not suit the operation of MRL. Of the memristors listed in Table 1, the HfO x memristor which has been reported in [35] has properties which suit the MRL gates. The device is characterized by a low switching delay 300 ps at a low operating voltage of 1.4 V.

These characteristics mean that this memristor is eligible to be implemented in the same die with the current CMOS devices. Important work regarding the implementation of the VTEAM model parameters that fit with the physical parameters of HfO x is described in [35]. Table 2 shows the determined VTEAM model parameters. The model parameters are chosen to produce a switching delay of 300 ps for a voltage pulse of 1.4 V, as reported in [35]. TiN/TiO x /HfO x /TiN 1 k >1 M >1000 5 ns -1.5 V to +1.5 V [40] Figure 11 shows the switching behavior of the memristor corresponding to SET and RESET pulses. The device is assumed to be completely switched when the boundary position w reaches either 1% or 99% of the total length D of the memristor, corresponding to SET (V set = 1.4 V) and RESET (V reset = -1.4 V) operations, respectively. The boundary conditions of the memristor are managed by a Biolek window function. The mathematical function of the Biolek window [41], which is described in Equation ( 12), provides a continuous and smooth transition of the boundary when reaching one of the extremities of the memristor.

f (x) = 1 -(x -stp(-i(t))) 2p (12)
where stp(.) represents a unit step function and p is a positive integer. Low values of p lead to a smooth transition of the boundary of the memristor when reaching its extremities, whereas high values lead to sharp transitions.

D 3 nm α o f f 3 K on -0.0162 m/s V on 0.16 V K o f f 0.0162 m/s V o f f -0.16 V x on 0 nm x o f f 3 nm 3

Performance Analysis

A transient simulation was conducted for the proposed design of the X-MRL-based full adder in the Cadence Virtuoso environment. CMOS 65 nm technology at the standard 1.2 V was adopted. Figure 12 shows all the possible combinations at the inputs A, B and C in in addition to the corresponding outputs S and C out . The performance is analyzed below for the proposed design.

Timing Analysis

Figure 13 presents the definition of the rising time (T r ) and the time delay (T d ). Accordingly, the conducted simulation of the proposed design shows that these extracted parameters (T r and T d ) change among different value combinations of A, B and C in . The maximum recorded values are as follows: T r = 82 ps, T d = 1.2 ns, and T f = 586 ps, where T f is the falling time. These values are considered for the worst-case performance. The conducted simulation shows that the values T r , T f and T d are affected by the switching speed of the memristor, which in turn can be controlled by K on and K o f f . On the other hand, slowing down the switching speed of the memristors increases the glitches. Figure 14 shows the appearance of glitches when reducing K on and K o f f levels to -0.01 m/s and 0.01 m/s, respectively. Particularly, the high-resistance state (R OFF ) of the memristors has a direct effect on the value of T d , which decreases when increasing the value of R OFF . Therefore, the total delay is directly affected by the memristor's physical properties. Moreover, it is observed that increasing R OFF acts as a filter for the glitches. This is due to the fact that a larger R OFF value minimizes the voltage drop at the output ports of MRL gates. Reducing

Energy Consumption

Figure 12b shows the total instantaneous power p T (t) consumed by the proposed design of the full adder. The peak values in p T (t) refer to the dynamic power consumption. The lower bound in p T (t), which is formed after the end of each transition, corresponds to 142 CHAPTER 6. FLEXIBLE AND EFFICIENT ARCHITECTURES BASED ON MEMRISTIVE TECHNOLOGIES Electronics, 2021 the static power. A slight difference appears between the levels of the static power recorded after each transition. This difference is due to the change in the equivalent resistance state of the cascaded memristors for a new combination of the input signals A, B and C in , which in turn leads to a different level of current leakage. The average power consumed in the proposed design of the full adder is P av = 279.5 µW. This value is of P av is evaluated at a frequency f of 200 MHz, which is near to the maximum possible frequency at the inputs of the full adder with a hybrid structure.

The value of the average power consumption is relatively high for a full adder circuit. This is due to the low values of R ON and R OFF of the adopted memristor device compared to the source-to-drain dynamic resistance in MOSFETs, which minimizes the leakage in current. Memristive devices are still being actively explored and developed using a variety of materials and deposition techniques. Thus, there is the potential for the device characteristics to be improved. Memristors with high values of R ON and R OFF have to be developed in order to achieve hybrid architectures with low power consumption.

Utilized Area

A single memristor has an area in the order of 4F 2 [28], where F is the minimum feature size. Thus, memristors are implemented at the top of the CMOS due to their nano-scale and compatibility at the level of fabrication. Thus, the allocated memristors in the proposed X-MRL design do not add any overhead in terms of the implementation area. The total required area refers to that occupied by CMOS devices only, which depends on the number of inverters, as discussed in Section 4.3. Figure 9 presents the proposed layout. The total area of the X-MRL design is 8.16 µm 2 compared to the area of 14.78 µm 2 utilized in the case of a pure CMOS implementation, leading to a 44.79% area saving.

Comparison

The proposed hybrid memristor-CMOS-based full adder was compared with previous published designs dedicated to the 1-bit full adder. Note that related works in the literature lack an estimation of the utilized area of their proposed designs. Moreover, in order to achieve a fair comparison in terms of energy consumption, the energy was evaluated for each additional operation. The time period for an addition operation in our proposed full adder design was set to be the minimum possible time (i.e., the maximum frequency). This subsection presents the comparison summary, which is also shown in Table 3. In [9], an optimized implementation of an MRL based 1-bit full adder is proposed. The authors developed an algorithm to search for the best form of the Boolean functions of the sum (S) and carry (C). The desired form should lead to an implementation with the minimum possible number of CMOS inverters. The inverter positions are allocated in such a way that removes signal degradation. The proposed circuit design of the full adder in [9] has a smaller number of memristors as well as CMOS transistors, with reductions of 11.1% and 33.3%, respectively, compared to our proposed design. However, the obtained logic function in [9] is not in the form of SoP. Thus, it is not possible to allocate memristors in a crossbar structure. This leads to more wiring at the fabrication stage, which in turn increases the implementation area dramatically. As regards energy consumption, the values reported in [9] are in the normalized form; thus, they cannot be used for comparison.

In [42], the authors presented a hybrid memristor-CMOS-based full adder circuit based on MRL. The adder is comprised of 18 memristors and 8 MOSFETs, which corresponds to a 66.6% reduction in the number of MOSFETs compared to our proposed design. However, the energy and the step delay in [42] are much higher compared to our presented X-MRL design. The layout is not considered by the authors.

In [43], a design for a 1 bit full adder was proposed based on memristor MAGIC-NOR and NOT gates. A crossbar structure was adopted and several optimization techniques were used to minimize the number of rows and columns of the crossbar as well as the number of computational steps. It has been shown that a compromise exists between the size of the crossbar and the necessary number of steps to perform a full addition. A minimum size of 3 × 3 crossbars (i.e., nine memristors) with a total latency of 35 computational steps is achieved. In contrast, our proposed design uses 18 memristors distributed in a crossbar structure in addition to nine CMOS inverters. The output is evaluated in one computational step. Concerning energy consumption, the proposed design in [43] consumes 0.3 pJ to achieve a 1 bit full addition process, whereas our proposed design consumes 0.69 pJ.

In [23], an N-bit addition was performed using MAGIC operations (i.e., NOR and NOT gates). Several approaches were presented by the authors for realizing logic within crossbars. The best of these approaches in terms of latency corresponded to 10N + 3 computational steps, which leads to 13 clock cycle for the case of a 1 bit full adder. However, 13N -3 memristors are reserved (i.e., 10 memristors for N = 1) to accomplish the 1 bit addition process. For the purpose of minimizing the number of reserved memristors inside the crossbar, an area optimized crossbar structure was also proposed in [23]. Only five memristors were utilized; however, 15N (i.e., 15 for N = 1) computational steps were required to achieve 1-bit full addition. As a result, our proposed design, which requires one computational step, outperforms the designs presented in [23] in terms of latency. Regarding the energy consumption, all the proposed approaches in [23] have almost the same energy dissipation, which is about 3.16 pJ for the case of N = 1. Thus, the proposed design in [23] consumes 4.5 times more energy than our proposed design.

In [44], an N-bit ripple carry adder (RCA) circuit in a memristor crossbar structure was presented. The MAGIC design style was used to implement the logic gates. By considering N = 1, which is the case of 1 bit addition, the proposed crossbar MAGICbased design requires 15 memristors and can perform the addition operation in 13 clock cycles. Compared to our proposed design, the adder design in [44] needs 13 times more clock cycles to perform addition operation, while it requires three fewer memristors to be implemented. On the other hand, our design consumes 1.01 times more energy than the proposed design in [44].

In [24], logic operations were realized by two methods using MAGIC. The first method corresponds to a naive mapping: it maps the NOR/NOT netlist into a single row of the crossbar. For the case of 1 bit full addition, 12 NOT/NOR sequential operations were required for a total number of 15 memristors. The overall energy consumption is estimated as 0.68 pJ. The second method corresponds to the compact mapping: in this method, NOR/NOT MAGIC operations are performed on rows and columns of a crossbar to realize logic functions. A 1 bit full addition process is performed on an 8 × 3 crossbar structure (i.e., 24 memristors) and requires 16 computational steps. The overall energy consumption is evaluated as 0.89 pJ. Compared to our design, the naive mapping and the compact mapping consume 1.01 times less and 1.28 times more energy, respectively.

In [45], the authors proposed a 1 bit full adder that was designed using IMPLY logic. The proposed design needs 23 computational steps to perform the addition. The 1 bit full adder proposed in [45] requires six memristors, which is 33.3% of the memristors utilized in our design. However, the IMPLY logic design approach adopts three different voltage levels (V COND , V SET and V CLEAR ). Thus, additional circuitry such as analog multiplexers should be added to drive the allocated memristors. This induces an overhead in terms of the total utilized area when compared to our proposed design. Note that the energy consumption was not considered by the authors.

In [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF], the authors proposed an IMPLY-based semi-serial adder with a respective addition algorithm. The N-bit full adder is implemented using 2N + 6 memristors, which correspond to eight memristors for a 1 bit full adder. Compared to our proposed X-MRL design, the authors use 55.5% fewer memristors. The N-bit addition in [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF] is completed within 10N + 2 steps, which correspond to 12 steps for 1 bit addition. Each step requires 30 µs to be completed. Thus, our proposed X-MRL full adder design, which requires one computational step (2.5 ns in total), outperforms that in [START_REF] Taherinejad | A semi-serial topology for compact and fast IMPLY-based memristive full adders[END_REF] in terms of latency.

The authors of [47] presented the design of a semi-parallel adder based on IMPLY. As compared to the semi-serial adder mentioned above, the semi-parallel adder reduces the number of memristors to five, but this comes at the cost of an increased number of computational steps and step delay. The full adder design in [47] uses a smaller number of memristors compared to our proposed design. However, it requires a higher number of steps and larger step delay.

Table 3 summarizes the comparison results presented above. The table illustrates the key advantage of the proposed approach regarding the reduced number of computational steps with respect to other existing designs. The energy consumption remains comparable. The Energy.Delay metric is used for a global direct evaluation. This metric combines both delay and energy consumption. As shown in the table, our proposed design outperforms all existing related ones. The improvement in Energy.Delay is between ×5.7 and ×31.

On the other hand, for the works that have adopted MAGIC and IMPLY in [23,24,[43][44][45], the initialization and the evaluation of the rows and columns of the memristive crossbar require a separate CMOS controller. Moreover, a conversion mechanism is required in these designs. This mechanism includes a sensing amplifier to convert the resulting stored bits from the resistance state to the voltage state [8]. These additional peripheral drivers result in additional overheads in area and power consumption.

Conclusions

In this paper, an MRL-based crossbar design-namely, X-MRL-is proposed. The X-MRL approach is dedicated to the implementation of combinational logic. The design methodology of X-MRL efficiently integrates memristors with CMOS devices to improve density and scalability. Using X-MRL, a Boolean function is represented using pairs of memristors mapped efficiently into a crossbar structure. The obtained memristive crossbar is stacked at the top of the CMOS layer. For evaluation purposes, we designed a hybrid memristor-CMOS full adder based on the X-MRL approach. Based on a realistic memristor parameter model and CMOS 65 nm process, the design was simulated in the Cadence Virtuoso environment. The obtained layout of the full adder showed a 44.79% area reduction compared to that implemented with pure CMOS technology. Moreover, the Energy.Delay metric was used for comparison. This revealed a significant improvement (between ×5.7 and ×31) with respect to the available literature. As future work, the proposed X-MRL design may be considered for the implementation of flexible logic blocks. This research work aims to explore new in-memory computing approaches and computational memory architectures that allow efficient combination of storage and processing in order to bypass the memory wall problem and thus to improve the computational efficiency; thereafter, apply the proposed techniques and architectures in real application case studies for the sake of performance evaluation. This work has been initiated during the PhD thesis of Khaled Alhaj ALI and has been continued during his work as a post-doctoral fellow at IMT Atlantique, Brest, France. It has been valorized in two IEEE international conferences [START_REF] Ali | Crossbar memory architecture performing memristor overwrite logic[END_REF] [134] and two IEEE transactions [START_REF] Ali | Memristive computational memory using memristor overwrite logic (MOL)[END_REF] [136].

Introduction

Modern systems have to implement additional memory in order to cope with the ever increasing requirement of massive data storage. The aggressive growth in the size of processed data in addition to the increasing numbers of processing cores have placed a high demand on the currently used memory systems as well as to intensive data traffic between memory and processing cores. In-memory computing (IMC) have been introduced to overcome the memory wall problem. Instead of sending large amount of data to the processing cores, part of the tasks are computed inside the memory. This reduces the memory accesses bottleneck and can significantly improve performance.

Emerging memristive technologies such as the ReRAM or MRAM have been considered as promising candidates for the next generation of memories. Memristive memory systems have several desirable attributes. They are classified as non-volatile with near-zero standby power consumption. They have ultra high density. Recent studies have illustrated the ability to perform local computations inside memristive memories (crossbars). Computing within memristive memories is motivated by the unique properties of memristors and their versatile nature. In this context, several recent contributions have been proposed to enable computation within memristive memory arrays. [START_REF] Kvatinsky | Memristor-based material implication (IMPLY) logic: Design principles and methodologies[END_REF][START_REF] Lehtonen | Stateful implication logic with memristors[END_REF][START_REF] Talati | Logic design within memristive memories using memristor-aided logic (MAGIC)[END_REF][START_REF] Thangkhiew | Efficient implementation of adder circuits in memristive crossbar array[END_REF][START_REF] Thangkhiew | Area efficient implementation of ripple carry adder using memristor crossbar arrays[END_REF][START_REF] Shirinzadeh | Logic Synthesis for Majority Based In-Memory Computing[END_REF][START_REF] Siemon | A complementary resistive switchbased crossbar array adder[END_REF][START_REF] Xue | A 1Mb multibit ReRAM computing-in-memory macro with 14[END_REF][START_REF] Chen | A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme[END_REF][START_REF] Xue | A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices[END_REF]. However, several challenges and limitations exist in terms of manufacturability and computational accuracy regarding device variability, pattern-dependent current leakage and the area overhead of peripheral circuits, and resistance drift effects.

The nonvolatile internal resistance state of memristor could be changed according to the magnitude and duration of the applied bias across its terminals [START_REF] Yang | Memristive devices for computing[END_REF]. If sufficient magnitude and duration of the bias across the memristor terminals is guaranteed, the intermediate resistances could be ignored. Accordingly, a memristor could be considered as a two-state element (R ∈ {R ON , R OF F }). The mapping of the internal resistance between the terminals of the memristor into Boolean states allows the definition of memristor in digital domain.

Based on this understanding, MOL new logic design style, is proposed for performing logic operations. In this logic design style, the result of OR/AND logic operation is over-written into the internal state of the memristor. The latter acts either as logic accumulator with its previously stored bit or as logic operator between its two terminals. This novel logic design style is inspired from a digital representation of memristors. Unlike existing approaches, MOL can operate with different memristor technologies, regardless the LRS-HRS margin and with linear as well as threshold-type memristive devices. Furthermore, the proposed original computational memory architecture, with appropriate drivers and control sequences, allows the execution of numerous logic operations, at bit or vector-level, in one or two computational steps at most.

Context and Motivation

Several works have been carried out revealing the ability to execute logic operations inside memristive memory arrays. The Memristor Aided Logic (MAGIC) [START_REF] Kvatinsky | MAGIC-Memristor-Aided Logic[END_REF] and the statefull implication (IMPLY) [START_REF] Kvatinsky | Memristor-based material implication (IMPLY) logic: Design principles and methodologies[END_REF] have been introduced as possible solutions for the realization of logic computations inside these memories. Based on MAGIC and IMPLY, storage and processing are both allowed within the same cells of the memristive memory array. Although, these approaches are used as basis logic functions to execute arbitrary Boolean functions inside memristive crossbar arrays, both approaches induce the state drift phenomena. The corresponding states of the memristive cells performing computations are not fully digital in some cases. On the other hand, the performance of these design styles is highly dependent on the technology of the adopted memristive device. Moreover, the corresponding basis functions provided by IMPLY and MAGIC are not diverse enough to allow fast logic mapping with minimum computational cycles. More recently, other in-memory computing techniques have emerged as alternatives. Among these, the memristor-based majority (MAJ) [START_REF] Gaillardon | The programmable logic-in-memory (PLiM) computer[END_REF] has been introduced to overcome the aforementioned limitations. However, other downsides arise at the architectural level. MAJ design style is relatively complex in terms of peripheral circuits as well as excessive in-out data movement which in turn impacts latency.

In this research work, a novel MOL logic design style is introduced associated with an original MOL-based computational memory. As MOL approach is based on our proposed digital representation of memristive devices [START_REF] Yang | Memristive devices for computing[END_REF], the proposed MOL-based computation is fully digital and eligible for highly reliable applications. MOL combines the simplicity of MAGIC/IMPLY [START_REF] Kvatinsky | Memristor-based material implication (IMPLY) logic: Design principles and methodologies[END_REF] techniques and the accuracy of MAJ [START_REF] Amaru | Majority-inverter graph: A new paradigm for logic optimization[END_REF].

Moreover, MOL can operate with different memristive device technologies and allows for significant reduction in the number of required memristors and computational steps. The choice of the memristive device type is not constrained by a specified MOL requirement. It can be observed from the mechanism of MOL technique that it involves direct access to the terminals of memristive devices which highly resembles conventional write operation. During the operation of MOL, the potential difference between the terminals of the memristive device always attains a binary level. Accordingly, MOL can be implemented in a wide range of memristive memories without specifying particular device features. In contrast, the structure of pre-existing logic design styles either establishes a series connection of a resistor (e.g. IMPLY) or series connection of the memristive devices (e.g. MAGIC) for normal operation. This undoubtedly prevents direct access to the memristive device terminals and consequently imposes specific device constraints.

Contributions and Performed Work

This work proposes a MOL-based computational memory architecture. The proposed original architecture, based on coupling two conventional crossbar arrays, is able to perform bitwise AND/OR operations between two stored words. The proposed MOL-memory architecture can be simply configured between storage (memory) and computation (processing) modes. The main contributions of this work are summarized in the following:

• A new logic design style, namely Memristor Overwrite Logic (MOL), is proposed for performing logic operations. In this logic design style, the result of OR/AND logic operation is overwritten into the internal state of the memristor. The latter acts either as logic accumulator with its previously stored bit or as logic operator between its two terminals.

• Application of the approach to perform MOL inside memristive crossbar arrays. An original feature in this context concerns the ability to perform MOL on a vector of bits and the possibility to select a single or multiple rows or columns of the crossbar.

• Integration of MOL into conventional crossbar-memory architecture, with incoming data bits along bit-lines only. The proposed architecture is able to perform MOL operations in addition to its main storage function. Four supported modes are detailed (write, overwrite, read, idle) together with appropriate architectures for the memory peripheral drivers. This research work has been initially published in the proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS) [START_REF] Ali | Crossbar memory architecture performing memristor overwrite logic[END_REF].

• Proposal of a MOL-based computational memory architecture which is able to perform MOL operations between two stored words, rather than between one stored word and external arriving input bits. An original architecture with two coupled MOL memory blocks that work in complementary manner is proposed together with appropriate drivers and control sequences. Numerous logic computations can be performed by this architecture, each requiring only one computational step.

• Demonstration of the design methodology through a detailed case study of N-bit full addition implemented using the proposed MOL-based computational memory. The sequence of MOL operations is illustrated in time and space (mapping to the two coupled MOL memory blocks). Different configurations are analyzed and evaluated in terms of required number of computational steps. This research work has been published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems [START_REF] Ali | Memristive computational memory using memristor overwrite logic (MOL)[END_REF].

• Performance analysis of the proposed MOL memory architecture design using Magnetic Tunnel Junction (MTJ) device [START_REF] Wang | Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses[END_REF][147]and CMOS 65nm technology node. This includes timing analysis, area utilization, energy consumption and tolerance against device variability, in addition to a detailed comparison with existing approaches. The obtained results show significant reductions in terms of latency and area when compared to existing recent approaches [START_REF] Lehtonen | Stateful implication logic with memristors[END_REF][START_REF] Kvatinsky | Memristor-based material implication (IMPLY) logic: Design principles and methodologies[END_REF][START_REF] Talati | Logic design within memristive memories using memristor-aided logic (MAGIC)[END_REF][START_REF] Siemon | A complementary resistive switchbased crossbar array adder[END_REF][START_REF] Shirinzadeh | Logic Synthesis for Majority Based In-Memory Computing[END_REF][START_REF] Thangkhiew | Area efficient implementation of ripple carry adder using memristor crossbar arrays[END_REF][START_REF] Gharpinde | A scalable in-memory logic synthesis approach using memristor crossbar[END_REF].

• Investigate the utility of MOL approach in the field of Neural Networks. An architecture design targeting Deep Neural Network (DNN) computation has been presented to address the inefficiency of moving data between memory and processing cores which is time and energy consuming [START_REF] Balasubramonian | Near-data processing: Insights from a micro-46 workshop[END_REF]. The design is composed of interconnected computational memory blocks namely CMEMs. The design is able to execute the weighted accumulation process purely inside the storage cells. This work has been published in the the IEEE International Symposium on Circuits and Systems (ISCAS) [134].

• Employment of the computational memories based on MOL design style to perform in-memory computing in the emerging Binary Neural Networks (BNN) [START_REF] Rastegari | XNOR-Net: ImageNet classification using binary convolutional neural networks[END_REF]. A novel architecture is proposed to execute instructions inside multiple computational memories using the proposed SIMM parallelism model which stands for single-instruction multiple-memory.

Abstract-In this article, we present a novel logic design style, namely, memristor overwrite logic (MOL), associated with an original MOL-based computational memory. MOL relies on a fully digital representation of memristor and can operate with different memristive device technologies. Its integration in memristive crossbar arrays and computational memories allows the execution of bit and vector-level primitive logic operations in two computational steps at most. Promising features and performances are demonstrated through the implementation of N-bit full addition using the proposed MOL-based computational memory.

Index Terms-Crossbar array, in-memory computation, logic design, memristor, memristor overwrite logic (MOL).

I. INTRODUCTION

M EMRISTOR has been predicted theoretically by Chua [1] in 1971. Chua hypothesized that memristor which is the fourth passive device should exist and hold a relationship between magnetic flux and charge. The first fabrication of a memristor device has been developed by a research team at Hewlett-Packard (HP) Labs [2] in 2008. The device structure is comprised of a stoichiometric (TiO 2 ) and an oxygen-deficient (TiO 2-x ) layer sandwiched between two platinum electrodes. The obtained two-terminal nanodevice exhibits a dynamic resistance that can be modulated between two bounds. These bounds correspond to the low and high resistance states, and are referred to as R on and R off , respectively. Memristor possesses the ability to retain the last attained resistance value in a nonvolatile manner.

Given the nanoscale dimensions of memristors and their unique properties, several innovative applications have emerged. One of the most promising applications is the use of memristors to implement arithmetic blocks, such as full adders [3]- [5]. Compared to pure CMOS implementations, these blocks are of relatively high density and could be packed into small chip area. Other applications involve using memristorbased memories to allow processing within the storage cells. This approach, referred to as in-memory computing, is being explored recently to alleviate the time and energy cost of data movement encountered in conventional von Neumann architecture and aggravated by the recent growth in datacentric applications [6]. The concept is different from, yet can be complementary to, that of near-memory computing which dates to the 1990s [7]. The near-memory computing approach aims to place the processing units physically closer to the memory, for example, through advanced die stacking technologies or 3-D integration. Despite the reduction in time and distance to memory access, there still exists a physical separation between the memory and the compute units [8]. For in-memory computing, instead of sending a large amount of data to the processing cores, part of the tasks are computed in place inside the memory itself [9]. Depending on the application, this can reduce the computational complexity of these tasks and/or the amount of data being accessed, leading to significant performance improvement [6].

In this context, several recent contributions have been proposed to enable computation within memristive memory arrays and can be classified into two categories. The first category involves using the memristor as a single-level cell (SLC) [10]- [16]. The second category includes work that uses the memristor as a multilevel cell (MLC) or analog cell [17]- [19]. The MLC-based computing is promising when targeting applications with intensive multiply-accumulate operations, such as convolutional neural networks (CNNs) [19]. However, a number of challenges remain in terms of manufacturability and computational accuracy regarding device variability, pattern-dependent current leakage, and the area overhead of peripheral circuits [20]. Major semiconductor foundries have not included MLC technology in their development roadmaps in the near future [19]. In contrast, SLC cells have a larger readout margin that makes them tolerant against process variation and resistance drift effects. Based on SLCs, different logic design styles have been introduced together with different realizations on memristive crossbar arrays. The Material Implication (IMPLY) [10] and the Memristor Aided loGIC (MAGIC) [21] have been introduced to enable in-memory logic operations. Although promising results are demonstrated, MAGIC and IMPLY techniques still impose specific technology and 1063-8210 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

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design constraints. For instance, in order to attain acceptable performance in these techniques, the ratio R off /R on of the adopted memristive devices should be relatively high. Moreover, Fang and Tang [22] have reported that IMPLY does not ensure binary resistance switching of memristors in some cases. More recently, other in-memory computing techniques have emerged as alternatives. Among these, the memristor-based majority (MAJ) [23] has been introduced to overcome the aforementioned limitations. However, other downsides arise at the architectural level. MAJ design style is relatively complex in terms of peripheral circuits as well as excessive in-out data movement which in turn impacts latency.

In this work, we introduce a novel logic design style, namely, memristor overwrite logic (MOL), associated with an original MOL-based computational memory. MOL combines the simplicity of MAGIC/IMPLY techniques and the accuracy of MAJ. MOL can operate with different memristive device technologies and allows for a significant reduction in the number of required memristors and computational steps.

The rest of this article is organized as follows. Section II provides a brief survey on existing memristor-based logic design styles. Section III presents our proposed MOL approach. Section IV discusses the integration of MOL into the conventional memory configurations. Section V presents our proposed configurable MOL-based computational memory architecture. The design and its configuration methodology are demonstrated by a case study of a N-bit full addition in Section VI. Simulations and performance analysis are illustrated in Section VII. Comparison with available implementations is presented in Section VIII. Finally, Section IX concludes this article.

Although memristive devices encompass memristors, it is possible to use the term memristor for other memristor devices [24]. In this article, we use the term memristors and memristive devices interchangeably for simplicity.

II. MEMRISTIVE DEVICES AS COMPUTATIONAL ELEMENTS

The versatile nature of memristors allows them to be used as computational elements in addition to their storage role. Implementing Boolean logic with memristors has been widely explored. Several memristor-based logic design styles have been introduced in the literature. Each is adapted for a specific type of application and surrounded by specific limitations.

A. Logic Design Styles

The memristor ratioed logic (MRL) has been proposed in [3]. MRL integrates memristors with CMOS transistors to implement combinational functional blocks. These blocks are relatively dense compared to those implemented with pure CMOS transistors. The memristive threshold logic (MTL) has been studied in [25]. The gate uses the configurable conductance of memristors to represent weights during operation. However, these weights are very sensitive to state drift, which can be a critical issue [25]. It is considered simple, but still in preliminary stages of fabrication. IMPLY [10] and MAGIC [21] are intended for in-memory computing. In these design styles, a memristor serves as a memory element as well as a part of a computational gate inside the memory. MAD gate, or memristors-as-drivers gate, has been presented in [26]. MAD has been introduced to overcome the long delays of the IMPLY operations as well as signal degradation and buffering issues in MRL; however, each MAD gate requires a complex driving circuitry and is thus considered unsuitable for integration inside a memristive memory. MAJ has been proposed in [23]. The authors demonstrated that a single memristor is capable of performing a 3-variable majority function. Using additional inversion function (INV), a Boolean expression is represented using a majority-inverter graph (MIG). MIGs are then realized sequentially in conventional memristive crossbar arrays. The complementary resistive switches (CRS) logic has been presented in [27]. CRS logic is capable of realizing two primitive operations denoted as reverse implication (RIMP) and inverse implication (NIMP). This logic design style can be considered as a special case of MAJ (see Section III-B).

In this article, our target application concerns in-memory computing, so some logic design styles such as MRL, MAD, and MTL are excluded.

B. Limitations

MAGIC and IMPLY logic families are widely explored in the literature. Talati et al. [12], Rahman et al. [28], Hur and Kvatinsky [29], Gharpinde et al. [30], and Thangkhiew et al. [31] have presented several approaches where logic functions are broken down into several MAGIC or IMPLY operations. These operations are then performed sequentially inside memristive crossbar arrays. However, these approaches have several design constraints.

1) The analysis in [22] shows that IMPLY cannot achieve the full resistance switching of the output memristor in case both input memristors of the IMPLY gate are in the R off resistance state. Hence, the corresponding state of the output memristor is not fully digital. 2) Output memristors in IMPLY and MAGIC may be subjected to state drift [10], [12].

3) The performance of these design styles is highly dependent on the technology of the adopted memristive device (e.g., requirement of memristive devices with high R off /R on ratio) [10], [12]. 4) The corresponding basis functions provided by IMPLY and MAGIC are not diverse enough to allow fast logic mapping with minimum computational cycles. MAJ-based logic design has been recently explored by Shirinzadeh et al. [15] and Gaillardon et al. [23]. MAJ relies on a digital representation of memristors, so the limitations faced in IMPLY and MAGIC can be overcome. However, at the architecture level, other downsides arise.

1) In-memory computing architectures based on MAJ, which are available in the literature, require additional load operations, which read data bits outside the memory. This induces the overheads in terms of the total critical path, number of cycles, and the complexity of the dedicated control unit. 2) Architectures based on MAJ involve significant modifications in the peripheral circuitry of the memory. The write operations are performed on bit-lines (BLs) as well as word-lines (WLs) instead of BLs only. These limitations hold also for CRS logic design approach [27] as it can be considered as a special case of MAJ.

III. PROPOSED MOL LOGIC

In this section, we introduce a new memristor-based logic design style, namely, MOL. MOL approach is highly adapted for computing within memristive crossbar arrays and avoids the limitations encountered by preexisting logic design styles.

A. Digital Representation of Memristive Devices

The nonvolatile internal resistance state of memristor could be changed according to the magnitude and duration of the applied bias across its terminals [32]. However, a nonsufficient magnitude or duration leads to an intermediate resistance state R where R on <R<R off . In this case, the state of the memristor cannot be considered as binary, which in turn leads to more sophisticated modeling of the internal state of memristive devices in the analog domain. However, in a digital design we can represent the memristor as a two-state element where its resistance R ∈ {R on , R off } and ignoring any other intermediate states if we succeed to guarantee a sufficient magnitude and duration of the bias across its terminals. Based on this understanding, the internal state of a memristor is defined in the digital domain. Let Q n be the current internal state of a memristor while Q n+1 is the next state after applying a new external bias represented by A and B as shown in Fig. 1(a). Hence, Q n+1 will be a function of the logical states at terminals A and B and the previous internal state Q n . By considering all the possible combinations of A, B, and Q n as shown in Fig. 1(b), the state equation of a memristive device is expressed as follows:

Q n+1 = Q n A + Q n B + AB = M 3 (A, B, Q n ) ( 1
)
where M 3 represents the 3-variable majority function, which is defined in [33]. This expression demonstrates that a majority function is an intrinsic feature of memristive devices [23].

Based on the Boolean expression presented in (1), the equivalent latch circuit of a memristive device is shown in Fig. 2 where Q is the internal state of the memristor. To translate the Boolean value of Q into a resistance between the terminals of the memristor, an analog multiplexer is added. It selects either one of the two resistors, whose resistances are R on or R off , where Q = 0 and Q = 1 are mapped to R on and R off , respectively. Note that this schematic is valid and useful from the digital perspective, so it cannot be used for simulation in the analog domain.

B. MOL Logic Procedure

The state representation of memristor expressed in (1) clarifies its computational capability and simplifies its integration in the digital domain. Six possible cases can be derived from (1) and are listed in (2). Fig. 3 of these cases. They are split into two groups. The first group includes the cases from 1 to 4, which correspond to MOL. In these four cases, a memristor acts as a logic accumulator. The previously stored bit Q n is subjected to OR/AND with the new input A/B while the other terminal of the memristor is set to logic "0" or logic "1" depending on the desired function. The obtained output is simultaneously saved in the form of a new internal state Q n+1 . The remaining cases (i.e., 5 and 6) are achieved by initializing the memristor to a known state (logic "0" or logic "1"). The inputs A and B are sent to the memristor ports simultaneously. The output is saved as the new internal state (Q n+1 ) of the memristor. In fact, these two cases correspond to CRS logic operations that are explored in the literature [16], [23] [27].

is an illustration

Although MOL operations are special cases of the 3-variable majority, working with MOL is much simpler. MOL highly resembles the conventional write operation. One end of each memristor is reserved for the input operands, while the other end is employed for selection. In contrast, MAJ employs both terminals of the memristor for the input operands. This makes MOL more adapted to crossbar memory arrays

Q n+1 = ⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ Q n + A , B = 0, case : 1 (MOL) Q n A , B = 1, case : 2 (MOL) Q n + B , A = 0, case : 3 (MOL) Q n B , A = 1, case : 4 (MOL) AB , Q n = 0, case : 5 (CRS) A + B , Q n = 1, case : 6 (CRS). ( 2
)
Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. The same concept applies to a vector of bits. Fig. 4 illustrates that two consecutive steps are enough for achieving MOL operations on an N-bit vector. In step 1, which is presented in Fig. 4(a), the input vector I = [I N -1 , I N -2 , . . . , I 1 , I 0 ] is written into the N memristors by mapping logic "0" and logic "1" to the normalized voltage levels -1 and 1 V, respectively, while the common horizontal line is set to 0 V. At the end of this step, the resulting state of a given memristor M k is Q k = I k . In step 2, the same N memristors are overwritten with the input vector A = [A N -1 , A N -2 , . . . , A 1 , A 0 ]. However, the input voltage level on the common horizontal line is set to 0 or 1 V depending on the desired operation. For the case of MOL-OR [Fig. 4(b)], B is set to 0 V and the result, which is stored in a given memristor M k , is Q k = A k + I k . For the case of MOL-AND [Fig. 4(c)], B is set to 1 V and the result, which is stored in a given memristor

M k , is Q k = A k I k .

C. Performing MOL Inside Memristive Crossbars

The proposed MOL can be performed in memristive crossbar arrays. The input data bits to the crossbar can be either written or combined logically with the currently stored bits inside the crossbar. This can be simply achieved by choosing the appropriate normalized voltage levels for representing the arriving bits (i.e., -1/1 for write and 0/1 for MOL). Fig. 5(a) illustrates that a single or multiple rows of the crossbar could be selected for either MOL-OR or MOL-AND operations with the incoming data bits I = [I N -1 , I N -2 , . . . , I 1 , I 0 ] being applied on the columns. Similarly, Fig. 5(b) shows that a single or multiple columns of the crossbar could be selected for either MOL-OR-NOT or MOL-AND-NOT operations with the incoming data bits of the vector I applied on the rows.

IV. MEMORY ARCHITECTURE WITH MOL CAPABILITIES

Crossbars constitute the core element of emerging memristive memories (e.g., RRAMs and MRAMs). Integrating MOL with crossbar-memory architectures can lead to promising enhancements and provides additional computational capabilities to these memories. However, this imposes updating memory peripheral drivers to cope with MOL operations in addition to its main storage function. Fig. 6(a) presents the proposed memory architecture which is capable of performing MOL. As illustrated in Section III, write and overwrite operations could be performed along the rows as well as the columns of the crossbar. However, in a conventional memory architecture, the flow of the incoming data bits is along the BLs only while the WLs are reserved for addressing. Thus, MOL operation, which is similar to a write operation, could be only performed along the BLs. In this case, MOL-OR and MOL-AND are the only supported logic operations in the proposed memory architecture. The architecture shown in Fig. 6(a) can be configured in four different modes:

1) Write Mode: The input N-bit vector I = [I N -1 , I N -2 , . . . , I 1 , I 0 ] is first mapped via BL driver (BLD) into the normalized voltage levels of -1 and 1 V corresponding for logic "0" and "1," respectively. Fig. 7(a) presents the schematic of BLD at the transistor level. The respective voltage levels (-1 and 1 V) are then provided to the BLs of the memristive Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. crossbar through the Isolation Block (ISO), which acts in this mode as a connecting switch. Fig. 7(b) illustrates the internal structure of the ISO. Simultaneously, the enabled addressing decoder selects a single WL. The selected WL is supplied with a voltage V SEL , which is already shared with the input of each transmission gate corresponding to every WL. The shared voltage V SEL is set to the normalized voltage level of 0 V. The unselected WLs remain floating in the high impedance state (Z).

2) Overwrite Mode: In this mode, the function of the memory is switched to perform MOL among its memristive crossbar. As stated earlier, both MOL-OR and MOL-AND have to be supported. For the case of MOL-OR, the input data bits are mapped to the normalized voltage levels of 0 and 1 V corresponding to logic "0" and logic "1," respectively. The addressing decoder performs its normal selection function for a single WL. The ISO is kept at the connecting state. The level of V SEL is also set to 0 V as in the case of write mode. The resulting bits of the MOL-OR operation are simultaneously stored in the selected WL. MOL-AND is performed similarly but V SEL is switched to the high voltage level (i.e., V SEL = 1 V). 3) Read Mode: In this mode, a single WL is selected to sense the corresponding states of its allocated memristors individually. BLD is isolated using the ISO block, which acts in this case as an open switch. The selection voltage V SE L is set to 0.5 V (normalized). The sensing current generated through each memristor has to guarantee the stability of its internal state (no state drift). A sensing amplifier (SA) circuitry, whose architecture is illustrated in Fig. 7(c), is used to measure the voltages across the reference resistors of respective resistances R. R is chosen to be the midvalue between R on and R off (i.e., R = (R on + R off )/2). By considering R on < R off , the voltage across a reference resistor, which is in series to the sensed memristor, would be either in the neighborhood of 0 or 0.5 V. Depending on the state of the sensed memristor, the three cascaded inverters magnify this difference leading to -1 or 1 V at the output. 4) Idle Mode: In this mode, the memory is not active.

The memristive crossbar is totally isolated to preserve its internal state. The IB block is in the isolation mode. Hence, all BLs are in the high impedance state (Z). Moreover, the address decoder is disabled. Thus, none of the WLs is selected, keeping them in the Z state. The architecture presented in Fig. 6(a) adopts the 1-memristor (1M) configuration for the structure of the crossbar. In other words, each cell consists of one memristor which connects the vertical and horizontal nanowires of the crossbar. However, the 1M crossbar configuration suffers from the sneak path phenomenon [34]. Sneak paths correspond to current paths through unselected cells in a memristive array. These undesired paths lead, in some cases, to a drift in the state of unselected memristive cells during write or overwrite operations. Moreover, it gives false estimation about the real logical state of a given selected memristor during the reading mode. This phenomenon degrades the overall memory performance. Several efforts have been made in the literature to overcome the sneak path phenomenon [34]- [36]. All proposed methods are limited to a certain crossbar size. Thus, increasing the size of the memristive crossbar beyond a certain limit will eventually lead to the sneak paths. A possible solution to stop these paths is to use a selector in series with each allocated memristive cell. This solution induces overheads in terms of the total utilized area of the memory which in turn loses the ultrahigh density attained in the 1M case. In [37], a transistor is used as a selector. Thus, each cell inside the memory consists of one transistor in series with one memristive device (1T1M). The obtained crossbar architecture for the 1T1M configuration is considered as sneak-path free. Fig. 6(b) presents our proposed 1T1M memory architecture with added MOL capabilities. The WL transmission gates that have been used in the 1M case are no longer used in the case, of 1T1M memory architecture. Normally, each transmission gate is equivalent to two MOSFETs. Thus, for an N × M memristive crossbar array, additional N M -2N MOSFETs are used in the 1T1M architecture compared to that in the 1M case. The obtained 1T1M architecture has the same four control modes previously introduced for the 1M case.

V. MOL-BASED COMPUTATIONAL MEMORY

In this section, a MOL-based computational memory architecture is introduced. The architecture can perform MOL operations between two stored WLs. The original architecture, which is formed of two interconnected MOL memory blocks, works in a complementary manner.

A. Architecture

The proposed MOL-memory architectures, which are presented in Section IV, act as logic accumulators for the newly arriving bits. In other words, computation in such memory is restricted for logic accumulation. Accordingly, performing general Boolean functions in this memory requires an additional process to load the stored data bits outside the Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. memory. These additional load operations are at odds with the concept of computation inside the memory. To overcome these load operations, we propose the use of two coupled MOL memories (MOL-memory-A and MOL-memory-B) which work in a complementary manner. At each time step, one of these memories acts as a source of input data-bits of the second memory. The second memory performs MOL with the previously stored bits in its memristive crossbar. Fig. 8 illustrates our proposed computational-memory architecture. The architectures of MOL-memory-A and MOL-memory-B are identical. A controlled inverting driver (INV) is added after the sensing stages of the two memories. The function of this driver is to achieve a complete logic, as the OR and AND logic operations supported by the memories are not universal. Therefore, additional NOT operation is required to allow the description of any Boolean function. The architecture of INV is illustrated in Fig. 7(d). A 1-bit barrel shift driver (BSD) is added to enable bit-level operations in addition to vector-level operations. The BSD is responsible for ensuring switchable connections between the two memory blocks. It can be reconfigured either to pass the data bits or to shift them on the fly with no need for an additional cycle. The architecture of the BSD is presented in Fig. 7(e). The proposed MOL-memory architecture presented in Fig. 8 is capable of performing numerous operations including logic computation and storage. Table I lists the most important (not all) operations that could be achieved. For each listed operation, a set of appropriate commands are simultaneously sent to the blocks constituting the architecture. A single operation requires one computational step. As an example, case 19 in Table I corresponds to the arithmetic operation expressed in the following equation:

M B (n) = M B (n) AND M A (m) ( 3
)
where M A (m) and M B (n) are the bit-vectors located at the addresses m and n corresponding for MOL-memory-A and MOL-memory-B, respectively. In this case, MOL-memory-A is set to the read mode. It reads the bit-vector M A (m), which undergoes a bitwise inversion through INV block. The 1-bit shifter is disabled. Simultaneously, MOL-memory-B is set to the overwrite mode to perform MOL-AND with the vector M B (n). The result of the bitwise logic operation replaces the previous vector M B (n). The process is performed during one computational step.

B. Performing General Arithmetic Tasks

Generally, an arithmetic function (e.g., addition, subtraction, compare, and so on) could be expressed in Boolean form. Accordingly, breaking the Boolean form into several MOL operations allows its execution inside the proposed computational memory. The execution of an arbitrary Boolean function requires several computational steps, thus MOL operations are executed iteratively to finalize the desired arithmetic task. For this purpose, an external controller, which arranges these iterative operations, is needed. Fig. 9 shows the block diagram which illustrates the general structure of the memory and the controller. When the controller receives an instruction from the processor, it decides whether the role of the memory is for storage or computation. Specifically, for the case of computation, the controller breaks the received macroinstruction into several iterative microinstructions, which can be performed by the proposed memory. In our case, microinstructions correspond to the set of operations listed in Table I. A processing area should be reserved in each of MOL-memory-A and MOLmemory-B in the proposed computational memory. The area could be dynamically changed according to the need (such as the number of required tasks). Moreover, the location of the processing area could be also changed periodically. The reason for location change is to attain better endurance for the memristive memory cells that are subjected to continuous stress. The design of the controller is beyond the scope of this article.

VI. MOL BASED IN MEMORY N -BIT FULL ADDITION

In this section, an N-bit full addition is considered as a case study to evaluate the functionality of our proposed computational memory architecture.

A. Proposed Iterative N-Bit Full Addition Process Dedicated for Computational MOL-Memory

Generally, full adder is the basic digital building block for several computational operations (i.e., addition, subtraction, and multiplication). Thus, implementing a full addition process inside the memory is the first step toward in-memory computing. The following equations present the well-known expressions of the 1-bit full addition:

S = A ⊕ B ⊕ C in (4) C out = AB + BC in + AC in ( 5
)
Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. where A and B are the inputs, C in is the input carry value, S is the 1-bit adder output, and C out is the output carry. The operator ⊕ corresponds to the Boolean XOR. Assume that all the inputs are initially stored in the memory. The Boolean functions of S and C out are written in the form of the sum of products (SoP) so that their expressions could be mapped into the proposed computational memory using sequential MOL operations. The inputs of a given MOL operation should be aligned on the same columns (i.e., same BLs) in the memory; otherwise, a preshifting process is required to align the corresponding inputs. Accordingly, the number of steps required to achieve the computation of S and C out is affected by the relative positions of the input A, B, and C in inside the memory. In order to minimize the number of computational steps as well as reserve the minimum possible processing area, a dedicated N-bit addition process is proposed. The process uses a specific sequence of each operation listed in Table I.

MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING

Consider the two N-bit vectors A N and B N . The addition of A N and B N leads to the vector sum S N +1 . Normally, the additional 1 bit in S N +1 is reserved for the expected overflow in the addition process. We propose to follow the procedure illustrated in Algorithm 1 to achieve a vector level addition of A N and B N . 1) Stage 1: The vector sum S 0 which is of length N + 1 is initialized by the bitwise XOR of A N and B N . Similarly, the vector carry C 0 of length N + 1 is initialized by the bitwise AND of A N and B N . The expressions of S 0 and C 0 are presented as follows:

S 0 = A ⊕ B (6) C 0 = AB. ( 7
)
2) Stage 2: Each time, a new vector sum S i+1 and a vector carry C i+1 are created based on their previous values S i and C i , respectively. The following equations demonstrate the respective expressions of S i+1 and C i+1 . This process is repeated N -1 times:

S i+1 = S i ⊕ (C i 1) (8) C i+1 = S i (C i 1). ( 9
)
The operator "1" stands for the 1-bit shift to the left. At the end of this iterative process, the final obtained vector S N -1 corresponds to the sum of A N and B N while C N -1 will be a zero vector.

B. In-Memory N-Bit Full Addition Procedure

The proposed iterative N-bit addition process can be mapped into the computational MOL-memory using the operations listed in Table I. Fig. 10 shows a space-time representation of the N-bit full addition process, which is realized 10. Each time, the initial vector C i is shifted to the left by one bit and the resulting vector undergoes bitwise AND with the initial vector S i . The obtained result is referred as C i+1 , whose expression is presented in (9). Simultaneously, the shifted version of C i undergoes bitwise XNOR with the initial vector S i to obtain the new vector sum S i+1 . At the end of this process, the vector S N -1 is stored in MOL-memory-B. Thus, an additional step is required to make a bitwise inversion of the obtained vector.

The resulting vector S N -1 , which represents the N-bit addition of the vectors A and B, is stored in MOLmemory-A.

C. Space-Time Analysis of the N-Bit Addition Process

The total number of computational steps required to complete the N-bit addition is 6N + 1 steps as shown in Fig. 10. The total number of memristors reserved for the execution of the N-bit addition is 4N memristors corresponding to four rows of the MOL-memory architecture. These rows include the initial locations of A and B, although the initial bits of the vectors A and B are lost. However, in some cases, the destruction of the input vectors is undesired, especially when these inputs are required for other computational tasks. In order to avoid this case, precopy operations of the two input vectors A and B could be performed to reserve safe versions of these vectors. Thus, two additional computational steps are required for this case and the new total number of computational steps becomes 6N + 3. The considered operation sequence in Fig. 10 corresponds to the case where A and B are both located in MOL-memory-A. However, other two cases should also be considered: 1) if A and B belong to different MOL-memories, one additional precopy operation could be performed to drag the input vector contained in MOL-memory-B to MOL-memory-A and 2) if A and B are both contained in MOL-memory-B, two additional precopy operations are needed to drag them to MOL-memory-A. These precopy operations are performed to maintain the same operation sequence, which is presented in Fig. 10. Precopy operations can be avoided with different sequences (one for each case, with common parts).

VII. SIMULATION AND PERFORMANCE ANALYSIS

In this section, we study the performance of the proposed computational memory architecture which is implemented using a realistic model of magnetic tunnel junction (MTJ) device and a CMOS 65-nm technology node. The study includes timing analysis, energy consumption, and robustness against device variability.

A. Adopted Memristive Device

Several memristive devices have been explored in the literature. In fact, the MOL technique could apply to all types of bipolar memristive devices holding two resistance states R on and R off . Among these devices, memristors such as HfO x [38] and TiO 2 [32] exhibit promising characteristics with their high switching speed (subnanosecond) and their high R off /R on ratio (>100). However, current memristor technologies suffer from endurance limitations. Although several efforts have been carried out to enhance endurance [38], the allowed number of switchings per memristor is still limited in the range of 10 6 -10 12 for the best case. This value is relatively low for targeting intensive computations inside memristive crossbars. The spin-transfer torque magnetic memory (STT-MRAM) [39], which has been redescribed in terms of memristive systems Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. [40], is considered as one of the most promising nonvolatile memories (NVMs). STT-MRAM is eligible for high-reliability applications [41] due to its high endurance (>10 15 ) [32]. As illustrated in Fig. 11, an MTJ cell is mainly composed of two ferromagnetic layers sandwiching an ultrathin tunnel barrier. The resistance of the MTJ cell depends on the relative orientation of magnetization in the free and reference layers. The low-resistance state (logic "0") of the MTJ corresponds to the parallel configuration (P) with resistance R P , while its high resistance state (logic "1") is reached in the case of antiparallel (AP) configuration with resistance R AP . The magnitude of the applied current I must exceed a critical value noted as I C0 to allow switching. In contrast to memristors, MTJs are characterized by a relatively low margin between R P and R AP . The corresponding margin is commonly evaluated as the tunnel magnetoresistance (TMR) ratio, whose expression is presented in the following equation:

MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING

TMR = R R P = R AP -R P R P . ( 10
)
However, such a low margin has no effect on switching an MTJ cell but on the corresponding sensing mechanism of the state of this cell. This requires a more complicated sensing driver to estimate and decide the corresponding state of a given selected row inside the memory. In this work, we have used MTJs with perpendicular magnetic anisotropy (PMA). The adopted PMA MTJ is formed of CoFeB/MgO/CoFeB layers. The physical model describing the static, dynamic, and stochastic behaviors of the STT-PMA-MTJ is presented in [42] and [43]. In order to fit with experimental results in the literature, the technology parameters corresponding to the material composition are kept at their default values.

Other parameters, which depend on the designers' choice, are presented in Table II with their corresponding values. It is worth highlighting that the low TMR value of the adopted STT-PMA-MTJ device usually leads to a high complexity of SAs when the memory data need to be readout. However, in our case, the proposed simple design comprised of three cascaded inverters and a reference resistor was verified to be sufficient when combined with the designed INV and BSD blocks (Fig. 7). In fact, these two CMOS-based blocks are leveraged in order to perfectly regenerate the voltage levels corresponding to the amplified output of the cascaded inverters. Fig. 12 shows the switching behavior of an MTJ device when it is fed with a square signal of amplitude 1.2 V. τ AP-P and τ P-AP correspond to the switching delays from AP to P state and the reverse case, respectively. In fact, switching delay varies according to the applied voltage level. Fig. 13 illustrates the variation of τ AP-P and τ P-AP with respect to the applied voltage level. The graph indicates that switching delay decreases with the increase of the voltage while switching from P to AP state is faster than the reverse operation (i.e., τ AP-P < τ P-AP ).

The choice of the memristive device type is not constrained by a specified MOL requirement. It can be observed from the mechanism of the MOL technique that it involves direct access to the terminals of memristive devices which highly resembles conventional write operation. During the operation of MOL, the potential difference between the terminals of the memristive device always attains a binary level. Accordingly, MOL can be implemented in a wide range of memristive memories without specifying particular device features. In contrast, the structure of preexisting logic design styles either establishes a series connection of a resistor (e.g., IMPLY) or series connection of the memristive devices (e.g., MAGIC) for normal operation. This undoubtedly prevents direct access to the memristive device terminals and consequently imposes specific device constraints, such as the requirement of sufficient HRS/LRS ratio and/or operated with threshold-type devices only.

B. Performance Analysis

A transient simulation has been conducted for the proposed design of the MOL-memory architecture. Based on the adopted STT-PMA-MTJ device and the CMOS 65-nm Authorized licensed use limited to: Linkoping University Library. Downloaded on August 09,2020 at 18:17:54 UTC from IEEE Xplore. Restrictions apply. process, simulations have been carried out using Cadence Virtuoso toolset. In order to evaluate the performance of the architecture, the N-bit addition process described in Section VI is performed. The size of the crossbar is chosen to be 8 × 8 for MOL-memory-A as well as MOL-memory-B. The size N is chosen to be 8 bits for both numbers A and B. The corresponding operating voltage is set to 1.2 V for logic "1" and -1.2 V for logic "0." Based on the obtained transient results, total latency is evaluated as well as the total energy consumption. As an example, Fig. 14 presents the corresponding internal states of the four WLs that are reserved for the 8-bit addition process, which is performed on the two arbitrary vectors A = [01011011] and B = [00111111]. The control signals of the MOL-memory architecture follow the operation sequence presented in Fig. 10.

1) Timing Analysis:

The first two steps correspond to the initialization of vectors A and B inside MOL-memory-A. The corresponding sum S = [10011010] is evaluated after 6N + 1 computational steps which is equal to 49 for N = 8. In fact, the max delay is noticed to be τ Max = 1.7 ns which is greater than the max switching delay of MTJ devices operating at 1.2 V. This is due to the voltage drop noticed along CMOS drivers. The actual voltage supplied to MTJ devices is 0.9 V (could be interpreted from Fig. 13). This significant voltage drop (25%) is due to the adoption of low values of R P and R AP . Moreover, the width W of MOSFETs has a direct effect on the voltage drop percentage. This voltage drop could be mitigated by increasing W , but this induces overheads on the total area of CMOS drivers.

Therefore, the duration (T ) of each computational step must be greater than τ Max . The variability in τ Max due to the stochastic switching behavior of MTJs should also be considered. Thus, an additional guard interval (τ g ) is introduced to guarantee the switching of the MTJs. The resulting step duration for the proposed MOL-memory architecture is T = τ Max + τ g = 1.7 + τ g . We set τ g at 100 ps which corresponds to 6% of τ Max , so the duration T is equal to 1.8 ns. The minimum time required for finalizing the addition operation (neglecting the two initialization steps) is evaluated as 49 × 1.8 ns = 88.2 ns.

2) Robustness Against Resistance Variability: Due to the limit of the manufacturing technology, the actual thickness of the oxide layer and the free layer of MTJ devices cannot be fixed at a constant value. They typically vary in a small range but can lead to a relatively important variation in the values of LRS and HRS of MTJ. Therefore, we have examined the effect of MTJ resistance variability on the performance of our proposed MOL-based computational memory architecture. Simulations are conducted by performing the 8-bit addition. The adopted MTJ parameters TMR, t sl , and t ox are kept as presented in Table II while subjecting them to a random process. The parameters are chosen to follow either uniform or Gaussian distribution. In Gaussian distribution, no error has been detected even when reaching a variation percentage of 21% for TMR, t sl , and t ox . As for uniform distribution, the tolerated variation reaches 7%. This demonstrates the robustness of the proposed design against the resistance variability of MTJ devices.

3) Energy Estimation: Energy consumption differs according to the operation: read, write, or performing computation. In this section, we will focus on the energy consumed by the memristive crossbar of the MOL-memory architecture neglecting the consumed energy by the peripheral drivers.

a) Write-energy: Consider a single MTJ device located inside MOL-memory architecture. The energy consumed when a single bit is written into this MTJ device mainly depends on its previous resistance state (R P or R AP ) and its final one. Hence, the four cases for write-energy are considered in the following equation:

E w0/0 = V w 2 R AP T E w0/1 = V w 2 R AP τ AP-P + V w 2 R P (T -τ AP-P ) E w1/0 = V w 2 R P τ P-AP + V w 2 R AP (T -τ P-AP ) E w1/1 = V w 2 R P T ( 11
)
where E wi/j corresponds to the write-energy needed to put the MTJ device in state i ∈ {0, 1}, after it was in the previous state j ∈ {0, 1}; V w and T are the write voltage and write duration, respectively; R AP and R P represent the resistance states of 1T1M cell. R AP = R AP + R MOS and R P = R P + R MOS . Generally, the values of i and j are not deterministic, but the four cases presented in (11) are considered as equiprobable, since there is no preknowledge about the data bits inside the memory as well as the bits that would be written. Thus, the average write-energy is estimated as the average sum of the four write-energy cases as presented in the following equation:

E w = 1 4 i, j E wi/j = V w 2 R AP T 2 - τ 4 + V w 2 R P T 2 + τ 4 (12)
where τ = τ P-AP -τ AP-P . Assuming that the term ( τ/4) is almost negligible compared to (T /2), the overall expression in ( 12) is simplified as

E w ≈ V w 2 2R w T with R w = R P R AP R P + R AP . ( 13
)
R w represents the equivalent resistance of two MTJs having opposite states and connected in parallel. Ref . The corresponding state of the sensed MTJ device is assumed to be stable. The two possible cases for read-energy are presented in the following equation:

E r0 = V r 2 R AP + R Ref T E r1 = V r 2 R P + R Ref T ( 14
)
where E r0 and E r1 represent the required energy consumption for sensing AP and P states, respectively, during a period T . The corresponding average read-energy is expressed in the following equation:

E r = V r 2 2R r T with R r = R P + R Ref R AP + R Ref R P + R Ref + R AP + R Ref . (15)
c) Computation-energy: Computational operations that are performed inside MOL-memory architecture are classified into MOL or copy operations. Table III summarizes the energy consumed by each type of operation. Using the specifications of the adopted MTJ which are listed in Table IV, the average energy consumed by an MOL operation could be expressed as E MOL = E w /2 + E r = 0.196 pj whereas that consumed by a copy operation is calculated as

E COPY = E w + E r = 0.333 pj.
Normally, computation inside MOL-memory architecture is performed on N bits simultaneously. For the N-bit addition process which is performed within 6N + 1 cycles, 3N cycles corresponds to MOL operations while 3N + 1 cycles corresponds to copy operations. Thus, the overall consumed energy (E T ) could be expressed as in the following equation:

E T = (3N)(N E MOL ) + (3N + 1)(N E COPY ). ( 16
)
By substituting the corresponding values of E MOL and E COPY presented in Table III, the expression of the total energy becomes E T = 1.587N 2 + 0.333N. Specifically, for the 8-bit addition process, E T is equal to 104.2 pJ. The value of the energy consumption extracted by simulation is 124.43 pJ.

VIII. COMPARISON

In this section, the proposed MOL-memory architecture has been compared with recently published relevant designs (listed in Table V) targeting in-memory computing. The comparison has been carried out based on the performance of N-bit addition in terms of latency, energy consumption, and utilized area. Note that the considered area incorporates only the memristors involved in the computation regardless of the size of the crossbar.

4) MOL Versus IMPLY and MAGIC:

1) Except for the parallel approach in [10], our proposed design, which uses only 6N + 1 steps to perform addition, outperforms all IMPLY-and MAGIC-based designs listed in Table V in terms of number of computational steps. In fact, [10] uses the parallel approach which is intended to increase the level of parallelism in computation. However, this approach requires significant modifications in the crossbar structure by adding connections between its rows. This leads to an increased area compared to the conventional crossbar structure.

2) The step delay in our proposed design is 1.8 ns.

Although the designs presented in [12], [13], and [30] adopt memristive devices that provide better step delay (1.12 to 1.43 ns), the total latency in our proposed design is still the minimum (10.8N + 1.8 ns). The best case achieved with the competitor designs is recorded in [12] with 13N + 3.9 ns (i.e., ∼20% more latency). 3) In the proposed design, 4N memristors participate in the execution of the N-bit addition. This number ranges from 11N -1 to 24N for the majority of the designs based on MAGIC, so our proposed design exhibits ×1.75 to ×5 area reduction. On the other hand, the IMPLY-based serial approach [10], MAGIC-based area optimized design [12], and the design presented in [11] use a fixed number of memristors to perform addition operation. In other words, the required number of memristors is independent of the size N of the addition operation. This area optimization comes at the cost of a high number of computational steps (×2.5 to ×18.8). 4) The average energy consumed in picojoule for the memristive crossbar in our design is 1.5867N 2 + 0.333N. This quadratic expression indicates a significant energy consumption in the order of ×N as compared to the linear energy expressions of the other designs listed in the table. The reason for this energy gap is that for each step, the same bitwise operation is performed on the whole WL (size N). However, the other approaches from the literature perform 1-bit operation in each step.

Although our methodology induces overheads on the total energy consumption, working on the vector level rather than bit level greatly simplifies the corresponding control unit and reduces its complexity.

5) MOL Versus MAJ and CRS: 1) Logic representation using MIGs has experimentally

shown promising results in logic optimization [44].

Memristive devices can efficiently execute the intrin- and Gaillardon et al. [23] present a programmable in-memory computing system, namely, programmable logic-in-memory (PLiM). The instruction set for the PLiM architecture is based on the MAJ operation. As investigated in [15], the number of required memristors for the addition is ∼ 2N, which is equal to 50% of that in our approach. However, the execution of an N-bit addition inside PLiM requires 15N cycles for the best case, which is ×2.5 the number of cycles required in our proposed design. This high number of computational steps is related to the repeated readout operations of intermediate results, which impacts, in addition, the step delay and energy consumption (not evaluated in [15]).

2) The number of computational steps achieved in [16],

which uses the CRS approach, is less than that of our proposed computational memory. However, other parameters, such as the step delay which is not investigated by the authors, are expected to be greater. This is due to the fact that the presented architecture, based on two separate memory blocks, uses an intermediate control unit which reads data bits from one memory block and redistributes them along with BLs and WLs of the other memory block. This process increases significantly the overall critical path and consequently the step delay.

The number of memristive cells required in [16] is also less than that in our proposed design. However, it is clear that based on this approach, the reserved area corresponds to a fixed location inside the memory, as the input bits cannot be shared with all WLs especially for large memory sizes. This affects the endurance of memristive cells participating in the computation which are subjected to continuous stress.

As explained in Section V-B, the proposed memristive computational memory can perform any general arithmetic function by breaking it into a netlist of iterative MOL operations. As MOL is based on the primitive AND/OR operations, the ABC tool [45], which has been employed for existing logic design styles [30], [31], could be also leveraged in order to realize the synthesis task. This will be considered in our future work.

IX. CONCLUSION

In this article, the MOL design style is introduced together with an original architecture for MOL-based computational memory. This novel logic design style is inspired by a digital representation of memristors. Unlike existing approaches, MOL can operate with different memristor technologies, regardless of LRS-HRS margin and with linear as well as threshold-type memristive devices. Furthermore, the proposed original computational memory architecture, with appropriate drivers and control sequences, allows the execution of numerous logic operations, at bit or vector level, in one or two computational steps at most. In order to illustrate the benefits of the proposed approach and to evaluate its performances, the implementation of an N-bit full addition using the proposed MOL-based computational memory has been detailed. The design is simulated in the Cadence Virtuoso environment using a CMOS 65-nm process and realistic model parameters of the STT-PMA-MTJ device. Results comparison with existing recent approaches demonstrates significant reductions in terms of latency and area.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI

I. INTRODUCTION

D EEP convolutional neural networks (CNNs) are the cur- rent state of the art for many computer vision tasks, such as image classification, detection, and localization [1], [2]. In particular, there is an increasing focus on the deployment of CNN in mobile systems, the Internet of Things (IoT) devices, and embedded chips for the mass market [3]. The main challenge that limits the integration of CNN in such systems Various prior works have been proposed to alleviate the hardware burdens in the von Neumann model in order to get better CNN inference performance. Two of the most promising solutions are network binarization [5]- [7] and inmemory computing (IMC) [8]. Network binarization or binary neural networks (BNNs) quantize all the weights and/or inputs to +1 and -1, providing a promising solution to mitigate storage and computation bottlenecks. In the resulting BNN, each convolution is processed by simple bitwise operations (XNORs and popcounts) instead of the multiply-andaccumulate (MAC). While BNNs are compact and efficient for resource-constrained devices, a degradation in accuracy is inevitable compared to their full precision counterparts. However, recent works have been carried out to reduce the decline in accuracy [5]. For instance, Courbariaux et al. [9] demonstrated only 3% loss in accuracy when applying BNN to the CIFAR-10 dataset. For the larger ImageNet dataset, Lin et al. [10] achieved promising results where the accuracy loss is around 5%.

On the other hand, IMC is one of the emerging techniques that address the memory wall problem encountered in the conventional von Neumann model [11], [12]. By merging processing cores and the memory component into a single unit, IMC allows to perform a part of the computation inside the memory, thus eliminating the need for data exchange. Although IMC is an old concept [8], it has been revisited recently with the advent of emerging nonvolatile memory (NVM) technologies where computing is efficiently enabled on the storage cells, directly on the data location. Several recent IMC architectures [13]- [15] have been developed based on NVM technologies, such as resistive memory (RRAM), magnetic memory (MRAM), and phase-change memory (PCM). Usually, IMC breaks arithmetic tasks into elementary logic operations that are successively executed within the memory cells. Although IMC can execute any arithmetic task, some tasks may be more efficiently performed in classical CMOS implementations. In this case, dedicated near-memory units are usually added to handle such tasks. More recently, a computational memory (CMEM) architecture [13] based on memristor overwrite logic (MOL) design style has shown promising performance in terms of execution speed and throughput efficiency, especially for bitwise application tasks.

In fact, there is a great synergy between IMC and BNNs when they are combined: the low logic complexity of BNNs makes them well suited for in-memory implementation. In this context, we propose a novel MOL-based in-memory architecture design dedicated for BNNs. The related contributions can be listed as follows.

1) The proposed architecture efficiently implements a parallel rowwise in-memory XNOR-based convolution. 2) A novel mechanism for combining in-memory and nearmemory execution is proposed for certain operations such as popcount and max pooling. 3) An original in-memory bubble sorting technique is introduced to execute a majority binarization stage replacing addition and normalization operations. 4) For evaluation, a python-based environment with appropriate library and commands has been developed by emulating the functionality of the adopted MOL-based CMEM and the corresponding control unit. 5) The new architecture is presented in the form of both semiparallel and parallel models and exhibits the lowest energy consumption compared to all existing relevant works, including CPU, GPU, and field-programmable gate array (FPGA). 6) The proposed parallel model reveals the lowest inference latency when compared to recent NVM-based approaches due to the high level of parallelism offered using MOL-based IMC. The rest of this article is organized as follows. Section II provides an overview on CNN, BNN, and the adopted MOL-based IMC approach. Section III illustrates the devised methodology and algorithms for realizing a BNN inside the CMEM architecture. Section IV describes our proposed semiparallel and parallel architectures that are dedicated for BNNs. Section V presents the environment setup for performance evaluation and discusses the achieved results. Finally, Section VI concludes this article.

II. PRELIMINARIES

This section briefly reviews the basics of CNN and BNN. In addition, it introduces the MOL-based IMC technique, which is adopted in this article.

A. CNN

A CNN is a particular type of neural network. It usually takes an image at the input and computes the probabilities that the image features belong to one of the output classes. Typically, a CNN consists of several convolutional and pooling layers followed by fully connected (FC) layers, as shown in Fig. 1(a). It has been shown that FC layers could be equivalently replaced by convolutions [16]. 1) Convolutional Layers: As shown in Fig. 1, a convolutional layer takes an input feature map (Ifmap) represented by a set of channels/matrices and convolves them with a particular set of weights (called kernels) to generate an output feature map (Ofmap). The transfer from Ifmap to Ofmap follows the expression:

Y m = f b + N n=1 X n * W n,m .
(

In this expression, X n represents an Ifmap channel of index n (where n ∈ 1, N ) and Y m represents an Ofmap channel of index m (where m ∈ 1, M ). M and N are the number of channels of the Ifmap and Ofmap, respectively. W n,m is a k × k weight filter window linking X n with Y m . The parameter b is the bias. f represents the activation function.

2) Pooling Layers: Pooling is an important feature of CNN as it reduces the dimensionality of a feature map while maintaining the most important information [17]. It allows to reduce the size of the network and the number of parameters used, preventing overfitting. Considering the max pooling, a spatial neighborhood (e.g., a 2 × 2 window) is defined. The window is slided without overlapping on the Ofmap elaborated by the convolutional layer. The largest element inside that window is taken as an output. Another choice is to take the average (average pooling) or the sum of all elements in that window. In practice, max pooling has been shown to work better [17]. An intuitive example of max pooling is shown in Fig. 1(b).

B. BNN

The multiply-accumulate is the key and the most computationally expensive arithmetic operation in classical CNN. BNNs have been introduced to alleviate the need for these operations. This is achieved by forcing the inputs/weights/gradients to have binary values, especially in the forward propagation.

Various types of BNNs have been explored in the literature [9], [10], [18]. In this article, we adopt the XNOR-Net [18] BNN, which offers significant simplifications and better results than other binarization methods. In XNOR-Net, both the incoming activations and weight parameters of the convolutional layers are constrained to a binary set {-1,1} except for the first convolutional layer where the input is the image. For efficient hardware mapping, the values -1 and 1 are encoded to logic "0" and "1," respectively. Then, multiplication of weights and activations is achieved according to the XNOR truth table, as shown in Fig. 2(a).

As shown in Fig. 2(b), the accompanied MAC operations can be then replaced by a series of XNOR operations and a final popcount (difference between the number of zeros and ones). The result is then subjected to normalization and binarization (Norm-bin). The convolutional layer in a XNOR-net BNN is shown in Fig. 3 and can be modeled by the following expressions: C. MOL-Based IMC 1) In-Memory Computing: IMC has been widely explored to overcome the memory wall by avoiding the long latency originated from intensive exchange of data between host processor and memory. From the device-level perspective, emerging NVMs are promising for the implementation of IMC. In this context, several recent contributions have been proposed and can be classified into two categories. The first category includes approaches that use the NVM cell as a single-level cell (SLC) [13]- [15]. In the second category, the authors have employed the NVM cell as a multilevel cell (MLC) or analog cell [19]- [21]. MLC crossbars can perform parallelized in situ operations by eliminating sequential memory accesses. MLC-based computing is promising when targeting applications with intensive MAC operation (e.g., CNN) [22]. However, a number of challenges remain in terms of manufacturability and computational accuracy regarding device variability, pattern-dependent current leakage, and the area overhead of peripheral circuits [23]. In contrast, the SLC approach involves a larger readout margin that makes NVM cells much tolerant against process variation and resistance drift effects.

y b n,m = Norm-bin Popcount XNOR W b n,m , X b n ( 2
)
Y b m = Norm-bin N n=1 y b n,m (3)
Based on the SLC approach, various IMC techniques have been introduced in the literature [14], [15]. All these techniques attempt to realize arithmetic tasks inside NVM arrays by performing successive elementary logic operations on the stored data bits. For instance, the material implication (IMPLY) [15] and the memristor-aided logic (MAGIC) [24] have been introduced to enable in-place logic operations in memristive crossbar arrays. Although promising results have been demonstrated, these techniques present the following limitations.

1) The performance of IMPLY and MAGIC is highly dependent on the technology of the adopted NVM device (e.g., requirement of high ON-OFF margin) [14], [15]. Thus, they are not qualified for the operation with spintronic devices such as spin-transfer-torque (STT)-MRAMs.

2) The analysis in [25] reveals that IMPLY may incur partial switching and significant state drift issues [14], [15] of the NVM devices within the memory array.

3) The corresponding basis functions provided by IMPLY and MAGIC are not diverse enough to allow fast logic mapping with a minimum number of computational cycles.

Other IMC techniques, such as the sensing-based computing, that is introduced in [26], has gained large interest for its ease of implementation and the ability to execute diverse types of bitwise operations. Sensing-based computing redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows. Although fast, this technique involves a relatively high precision read circuitry that is based on sensing amplifiers (usually Op-Amps) employed as comparators. The read circuitry, which must be activated at each computational step, involves relatively high energy consumption. In this article, the recently proposed IMC approach [13], namely MOL, is adopted. The main idea behind MOL was to address the aforementioned limitations. MOL applies for various NVM technologies spanning resistive devices (memristors [27]), spintronics (STT magnetic tunnel junction (MTJ) [28]), and phase-change materials (PCMs [29]). Moreover, it allows for significant reduction in the number of required computational steps as well as the reserved processing area inside the memory.

2) MOL-Based CMEM: The CMEM presented in [13] is composed of two adjacent nonvolatile (NV) subarrays that work in a complementary manner. In this architecture, two wordlines are activated simultaneously in order to perform bitwise logic operations. A vector-level AND/OR operation can be executed within a single computational step. Moreover, shifting and inversion operations are also enabled through a dedicated intermediate driver offering flexibility in the operations, which is crucial for some arithmetic tasks. The intermediate driver involves a simple sensing circuitry followed by a set of 2-to-1 multiplexers. The role of multiplexers is to either pass the value from the sensed wordline or to pass its inverse. It can be configured depending on the desired operation. The multiplexers are followed by a configurable 1-bit shifter that can be enabled/disabled during the run time. The resulting intermediate driver passes the signals on-the-fly without additional computational steps. More details on the working mechanism of the intermediate driver can be found in [13].

An external controller arranges the operations performed inside the memory subarrays in order to finalize a desired arithmetic task. It breaks down the task into series of microoperations (bitwise MOL) that are executed one after the other. The architecture diagram is presented in Fig. 4.

Generally, the high bandwidth of IMC allows to minimize the step period of each microoperation. However, when the complexity of an arithmetic task scales up, the corresponding number of computational steps becomes large, which again increases latency and energy consumption. In this case, moving data to be processed near memory is more efficient. Hence, the performance of IMC is task-dependent.

In this article, we consider applying the principle of MOL and the corresponding CMEM for the implementation of BNNs. For higher precision neural networks, as previously stated, the multiply-accumulate operation is the crucial operation in these networks. Addition and multiplication tasks can be executed in-memory but usually necessitate a large number of computational steps, which grows when increasing the size of operands (i.e., precision of the network). As a result, such tasks might be more efficient to implement in traditional von Neumann architectures, despite the high communication cost between memory and processing cores. In contrast, the low logic complexity of BNN makes it highly suitable for IMC as the multiply-accumulate operations of a convolutional layer are mainly replaced with basic bitwise XNOR and popcount.

III. MOL-BASED IN-MEMORY BNN

A. In-Memory XNOR-Based Convolution 1) Method: The bitwise XNOR represents the most computationally expensive operation in the convolution process. Thus, optimizing its execution inside memory will enhance the overall performance of the BNN. This is why we first propose an efficient implementation of the XNOR convolution inside the CMEM. We consider a binary Ifmap X b of size h × w being XNORed with a k × k weight kernel W b . A simple example presented in Fig. 5(a) illustrates some of the steps of the proposed procedure. In this example, a 3 × 3 kernel is adopted. This kernel size is also suitable and used for large networks and datasets [30].

First, an Ifmap, zero padded at its surrounding, is loaded into subarray A of the CMEM, as shown in Fig. 5(a). The corresponding kernel is then loaded into subarray B, though in a tiled pattern fitting the width of the Ifmap. Hence, the size of the tiled kernel is k × w. Here, we assume that the width after zero padding is a multiple of k; otherwise, padding is increased. For better scheduling of the XNOR operations and in order to obtain a higher level of parallelism, the Ifmap is gridded into k × k slots without overlapping. For simplicity, we use the term sliding grid (instead of sliding window) to point on the selected regions that would be XNORed. The convolution is performed in k successive phases (three phases in this example), while each phase is carried out in k rounds. For a given phase i ∈ 0, k -1 and round j ∈ 0, k -1 , the sliding grid is right and down shifted to the position i and j , respectively. Simultaneously, the tiled kernel is right shifted to the position i . In other words, the horizontal movement of the tiled kernel follows that of the sliding grid. This specific shifting operating is enabled by the CMEM. Rowwise XNOR is then performed purely inside the CMEM based on a series of MOL operations that are discussed in Section III-A.2. At each position (i, j ) of the sliding grid, a XNOR matrix is obtained in subarray B. The resulting matrix is then moved to a near-memory processing unit to undergo popcount and binarization. In fact, the popcount process is not adapted to IMC. Its implementation is inefficient in terms of the number of required computational steps. Fig. 5(b) shows the occupied regions inside the CMEM after execution, where auxiliary processing regions are required in subarrays A and B in order to finalize the convolution task.

2) Rowwise XNOR: The Ifmap undergoes several rounds of XNOR operations inside the CMEM. Thus, an Ifmap should remain safe until the end of the convolution process. Similarly, a safe version of the kernels should be available all the time in order to be reused for later inference. Within these requirements, a nondestructive rowwise XNOR is applied based on a series of MOL operations. As shown in Fig. 6(a), an Ifmap row X b r and a kernel row W b r are assumed to be initially inside the CMEM subarrays A and B, respectively. In order to avoid destroying W b r , a copy is stored in the processing region of subarray B. After that, five successive computational steps are required. In each step, a microoperation zat(m, n) is sent to the CMEM, where z corresponds to one of the 30 microinstructions described in [13] and m and n represent the corresponding addresses of subarrays A and B, respectively. The six microoperations are defined in Fig. 6(b). At the end, the value X b r ⊕ W b r is obtained in subarray B while keeping X b r and W b r safe. As a result, only three auxiliary rows have to be reserved for the XNOR operation to be processed. As presented in Fig. 6(a), one row resides in subarray A (at address m 2 ), while the other two rows reside in subarray B (at addresses n 1 and n 2 ). The same auxiliary rows can serve for later XNORs. Yet, it is preferred to change the location of the processing region regularly to avoid the thermal accumulation in certain cells and maintain high endurance. Overall, XNORing an Ifmap of size h × w located in subarray A, with a tiled kernel of size k × w located in subarray B, requires a minimum storage space of S XNOR = (h + k + 3)w.

On the other hand, it is possible to retrieve the value of W b r logically instead of saving a spare copy. This is because the XNOR operation can be reversed. The value of W b r is still contained in the XNOR result. Yet, the required operations for retrieving W b r value are definitely more expensive in terms of computational steps, in particular that the same set of kernels is frequently needed for multiple operations and inferences. Therefore, it is more efficient in this case to use the copysaving strategy.

3) Near-Memory Popcount: The XNOR matrix obtained in subarray B is also grouped into k × k slots using the sliding grid. Horizontal slots are then moved row by row to the popcount and binarize (PB) block located inside the nearmemory unit (NMU), as shown in Fig. 5(c). In fact, the PB process is equivalent to obtaining the majority bit in a given slot. Hence, the PB block counts the number of ones in the horizontal slots simultaneously using parallel adders and accumulators. The resulting number in each slot is then compared with the threshold value (k 2 -1)/2, where this value corresponds to half of the number of elements in each slot. Exceeding this value indicates that the corresponding majority bit is "1"; otherwise, the bit "0" is returned. The architecture of PB is shown in Fig. 5(d). At the end of k successive steps, a binary row is returned to the memory. The accumulators are cleared before beginning with the next horizontal slots.

B. BNN Layer in-Memory

1) Convolutional Layer: As illustrated in Section II-B, the mth Ofmap Y b m is obtained by adding, normalizing, and binarizing the resulting N convolution channels y b n,m as expressed in (3). In fact, executing these three processes separately inside the CMEM is computationally expensive. In order to handle these processes efficiently by the CMEM, we introduce the majority-bin stage instead. The majority-bin stage involves computing the majority channel out of the N convolution channels y b n,m . Computing the majority is simply achieved through a proposed in-memory bubble sorting technique. As shown in Fig. 7(a), we consider an arbitrary vector of bits p = {p 0 , p 1 , . . . , p i , . . . , p N -1 }, where i ∈ 0, N -1 . When applying bubble sorting on p, bits holding the value "1" are swept to one side of the vector leading to new vector q = {q 0 , q 1 , . . . , q i , . . . , q N -1 }. Since the number of "0"s and "1"s after sorting remains the same, the middle bit q N/2 (if N multiple of 2) can be considered as the majority bit.

The applied bubble sorting technique is implemented using the logic tree presented in Fig. 7(b), which has a regular form and is based on the proposed bubble-flip module shown in Fig. 7(c). The module is composed of only AND and OR logic gates. It allows to flip the input bits so that "1"s appear at the output port of the OR logic gate as shown in the figure. As an optimization step, since the goal is to compute the majority bit and not to sort the bits inside the vector, bubble-flip modules and logic gates that are not participating in the generation of the majority bit have been discarded from the logic tree. The resulting optimized logic tree has been efficiently realized inside the CMEM, where the equivalent MOL operations are implemented sequentially.

Moreover, operations inside the CMEM are performed on the vector level. Thus, channels sorting is achieved rowwise, speeding up the whole sorting process. Fig. 7(d) shows how rows are being sorted ending up with a majority channel Y b m located in the middle. The required number of steps to generate a majority channel in-memory is derived as S maj = h((3/2)N 2 -4N + 3). The derived expression shows that the latency overhead of the sorting technique is independent of the width w of the channels. Although the number of steps grows quadratically when increasing the number of channels to be sorted, the high amount of parallelism at the vector level and CMEM banks level is sufficient to compensate for the time overhead of the sequential sorting process. In fact, the concept of sorting has already been adopted in the literature for replacing computationally expensive tasks. Zhang et al. [31] adopted the bitonic sorting algorithm in order to replace the FP addition and activation stages in neural networks. Alam et al. [32] implemented the bitonic sorter algorithm in memristive memory array achieving significant reduction in the processing time compared to prior sorting designs. Although bubble sort is slower than bitonic, it has a simple and more regular pattern for accessing the data to be sorted. This reduces the complexity of the control part of the architecture. Prasad et al. [33] proposed a general hardware/software design to achieve efficient sorting of floating-point numbers for data ranking. However, the mechanism imposes a custom design, which is not adapted for IMC of BNNs.

2) Pooling Layer: The input channel to the pooling layer is gridded into 2 × 2 slots without overlapping. Each slot corresponds to a max-pooling window p = {p 0 , p 1 , p 2 , p 3 }. The max pooling is defined as in [5]: maxpool( p) = 0 if and only if all elements inside p is equal to "0"; otherwise, max-pool( p) = 1. In fact, this can be handled by applying an elementary OR operation to the four elements inside p. The resulting bit corresponds to maxpool( p). Performing this inside memory is achieved in two stages. The first stage can be efficiently performed using in-memory MOL operations. Elementary OR operations are applied to the rows where all slots are managed simultaneously. Thus, the four bits in each Fig. 8.

Proposed in-memory and near-memory combined max-pooling process.

slot are compressed into two bits placed horizontally, as shown in Fig. 8. In the second stage, the resulting two bits are subjected to another OR operation resulting in maxpool( p). This stage is realized near memory using simple OR logic gates that are applied to the columns simultaneously.

IV. SEMIPARALLEL/PARALLEL ARCHITECTURE

This section presents our proposed architecture for the execution of BNN in-memory. Then, the control flow and the data mapping methodology are illustrated.

A. Architecture Design

The execution of a complete BNN layer in a single CMEM block is time consuming, as convolutions would be executed serially. In order to improve parallelism and consequently accelerate processing, we propose to split the CMEM block into smaller interconnected CMEM units. Each CMEM unit is then employed to execute a single Ofmap channel Y b m in a given layer. The same units are reprogrammed to perform the other layers. The communication between these CMEM units is managed by a master memory that receives intermediate results and redistributes them in a systematic mapping method that is illustrated in Section IV-B. Fig. 9 shows our proposed architecture with two different models. The semiparallel model shown in Fig. 9(a) shares one NMU to all CMEM banks, whereas in the parallel model shown in Fig. 9(b), each CMEM bank reserves a separate NMU. It is worth mentioning that all CMEM units are shared with a unique control bus because tasks being executed on different units are identical. Thus, a single control unit is able to cope with all these units. For this purpose, an enabling decoder block is added. It can be configured to either activate a single CMEM unit or all units at a time. Such an architecture model is equivalent to a single-instruction multiple-data (SIMD) model for IMC, so it can be called SIMM that stands for single-instruction multiple-memory.

B. Mapping Methodology

The adopted mapping method is an important factor in our proposed architecture as it highly influences the overall performance of inferencing. We classify the mapped data depending on its static or dynamic nature. Static data, such as weight kernels, is mapped during the configuration phase only and does not require any update during the running phase. On the other hand, the continuously generated data during the running phase is considered as dynamic. This type of data requires redistribution before initializing the next layer. Examples of dynamic data are the generated convolutions and Ofmap channels.

The control flow is thus divided into three phases: configuration phase, running phase, and redistribution phase.

1) Configuration Phase: As stated earlier, each CMEM unit is supposed to handle the computation of a single Ofmap channel in each layer. Thus, the mth CMEM unit (CMEM m ) receives from the master memory its own set of weight kernels (W b n,m ; n ∈ 0, N -1 ) that are required to execute the Ofmap channel Y b m . Moreover, the master memory broadcasts the Ifmaps to all CMEM units.

2) Running Phase: The control unit receives a flag to begin the inference process. All CMEM units are then activated simultaneously for parallel execution. For the case of the semiparallel architecture model, popcounting and pooling stages are performed sequentially within the NMU. Thus, during these stages, only one CMEM unit is activated at a time. At the end of this phase, an Ofmap is generated in each CMEM unit. 3) Redistribution Phase: This phase prepares the execution of the next network layer. Normally, the generated Ofmaps are fed to the next layer as Ifmaps. They are returned one after the other to the master memory, which in turn rebroadcasts them to all CMEM units. In fact, a single CMEM unit should have a certain minimum space to be capable of holding the inputs, the outputs, and the intermediate results. For a given layer with N Ifmaps and M Ofmaps, generating a single Ofmap requires N tiled kernels. Assuming the size of Ifmaps and tiled kernels as h × w and k × w, respectively, the minimum storage space required to implement the layer can be expressed as S CMEM = w(2h N + k N + 3h).

V. EVALUATION AND RESULTS

This section presents the validation and evaluation results of the proposed in-memory BNN architecture. In addition, it presents the detailed discussions and comparisons with recent relevant works.

A. Simulation Environment and Functional Validation

For functional validation, a python-based environment, with appropriate library and commands, has been developed to Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply. mimic the MOL-based IMC operations performed in the CMEM. This environment constitutes a proof-of-concept that illustrates the programmability of the proposed IMC architecture. It provides an abstract programming library that hides the complexity of the low-level logic implementation to application designers. In this environment, we deal with the CMEM subarrays as two coupled binary matrices, and each one has a separate input signal, which points to a certain row inside the matrix; "0"s and "1"s of the binary matrices correspond to the ON-and OFF-state of the NVM cells, respectively. The two matrices receive a command that is directly translated into a bitwise elementary operation where 30 types of operations are supported and described in [13]. The developed environment allows for system-level simulations as well as performance evaluation. Within this environment, the proposed in-memory XNOR-based convolution and the majority-bin and pooling operations have been simulated and cross-validated with standard methods. Moreover, the implementation of binary convolutional layers has been functionally validated.

MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING

Fig. 10 shows a simple example of a BNN layer implemented with four 28 × 28 Ifmaps taken from the Modified National Institute of Standards and Technology (MNIST) dataset. The black and white pixels represent the logic states "1" and "0" of the memory cells, respectively. This figure, which is extracted from the developed environment, corresponds to the state of the CMEM subarrays at three different instants. The first instant corresponds to the initial state, where four Ifmaps and a set of tiled kernels appear in subarrays A and B, respectively. The second instant is the end of the convolutional layer, where three Ofmaps are generated in subarray B. The last instant corresponds to the end of the combined in-memory and near-memory max-pooling process. The channels after rows and columns max-pooling processes appear inside subarrays A and B, respectively. Fig. 10. CMEM state at three different instants: the initial state, the end of the convolutional layer, and the end of the max-pooling layer.

B. Performance Evaluation

In order to evaluate the performance of our proposed architecture, the binarized neural network BinaryNet [9] and the CIFAR-10 dataset have been taken as a case study. state-of-the-art results on CIFAR-10 and allows comparing with the available relevant works [3], [34], [35]. For the rest of this article, the adopted model is referred to as the CIFAR-10 BNN model. The BinaryNet BNN consists of six convolutional layers, three fully connected layers, and three pooling layers. All convolutional layers use 3 × 3 filters and edge padding. Both Ifmaps and weight kernels of the convolutional layers are binarized to -1 and 1 except for the first convolutional layer where the input is the image. All pooling layers employ a 2 × 2 max-pooling window without overlapping.

The BinaryNet model has been chosen as it achieves near

We consider the convolutional layers CONV2-5 in our evaluations. For CONV2, CONV3, CONV4, and CONV5 layers, the numbers of input and output channels are 128 and 128, 128 and 256, 256 and 256, and 256 and 512, respectively. The corresponding sizes of the Ifmaps are 32, 16, 16, and 8, respectively. More details on CIFAR-10 BNN model parameters can be found in [34].

For both parallel and semiparallel architectures, we employ 128 CMEM units, each of 34-bit width. The adopted width supports the maximum binary image size (i.e., 32 × 32) of the CIFAR-10 after edge padding. Layers with a number of output channels exceeding 128 are performed on several stages.

The minimum step period and the average energy consumption of the performed operations are extracted from the Cadence Virtuoso toolset. The 65-nm technology node is used for the peripherals, including the intermediate driver and NMUs, while a realistic STT-MTJ device model [28] is adopted for the CMEM memory cells. The model describes the static, dynamic, and stochastic behaviors of the STT-MTJ device. It has been proven through a resistance variability analysis in [13] that a variation up to 21% in tunnel magnetoresistance (TMR), t sl , and t ox parameters of the MTJ device leads to error-free MOL operations. In this work, we consider that the resistance variability is below this limit. According to [13], a single MOL operation consumes 0.196 pJ of energy per STT-MTJ cell, with a maximum switching delay of 1.8 ns. The reported value of energy includes the average energy consumed by the peripherals as well as the intermediate driver.

On the other hand, the switching delay corresponds to a clock frequency of 555 MHz. Since the switching speed of MTJ devices is slower than that of CMOS, this frequency is set to the entire architecture, including the CMOS peripherals.

Moreover, evaluation is carried out using the emerging spinorbit torque (SOT)-MTJ device, which exhibits fast read/write speed and unlimited endurance. The read/write energy and delay for this device are taken from [36]. The maximum estimated values of energy (0.1 pJ) and delay (∼1 ns), for a single MOL operation, are then deduced according to the analytical expressions derived in [13]. Here, the delay corresponds to a maximum clock frequency of 1 GHz. The average energy consumed by a single MOL-type operation (AND, OR, AND-NOT, and OR-NOT) per MTJ device can be expressed as E MOL = E w /2 + E r , where E r and E w represent the read and write energy of the adopted MTJ device, respectively, [13]. The energy consumed by a copy operation can be expressed as E COPY = E w + E r . Other operations such as invert and shift, have an energy overhead close to that of a copy operation. A slight difference appears due to the change in the configuration of the intermediate driver. To evaluate the energy consumed by 34-bit width operations, the above expressions should be multiplied by a factor of 34. Other sources of energy consumption appear during operands movement from the memory array to the NMU. The NMU is located close to the memory array, and thus, energy consumption is mainly limited to the hybrid CMOS-resistive structure of the read circuitry, as well as the dynamic energy dissipation of the NMU's CMOS structure. Table I presents the energy consumption of the different 34-bit width operations performed in STT and SOT CMEM. This extracted information is provided to the developed pythonbased environment, which is in turn used as an evaluation tool.

The total computational energy, power, latency, and throughput efficiency for the CONV2-5 layers are evaluated in both parallel and semiparallel architectures. A comparison is carried out with relevant recent state-of-the-art works implementing BNNs using a similar IMC approach [3], [35]. Moreover, BNN implementations using a conventional computing approach on Intel Xeon E5-2640 processor (CPU), NVIDIA Tesla K40 GPU, and FPGA [34] are considered, although the two approaches are hardly comparable. Indeed, the emerging STT/SOT memory technologies are still in the development phase and there is no mature production technology for them. In contrast, real fabricated devices using mature technologies are available for accurate performance measurement on CPUs, GPUs, and FPGAs. Nevertheless, comparing with these conventional implementation approaches, which we consider as baseline, still provides useful information about the performance level of our proposed architecture.

On the other hand, it is worth noting that the proposed IMC approach does not alter the accuracy of the BNN model with respect to the conventional computing approach. It only provides a different way to implement the same computing operations on the same parameters and same data.

Comparison results are summarized in Table II. As shown in this table, our proposed semiparallel and parallel architectures exhibit the lowest energy consumption regardless of the used NVM technology (STT/SOT). The SOT-based architecture reveals 49%-99% reduction in terms of energy compared to the other implementations. Although the parallel architecture shows better inference speed than the semiparallel one (6.5×), the latter requires less number of near-memory units (M×). The choice between these two architecture models could depend on the application requirements. Furthermore, our proposed architecture with SOT technology reaches 264 to 273-image/s/W throughput efficiency, which outperforms all others, including the CPU, GPU, and FPGA solutions. It is worth noting that the semiparallel and fully parallel architectures have the same energy consumption although they have different implementation complexities. This is because they perform exactly the same operations, yet with different levels of parallelism. A slight difference appears due to the static energy consumed by the additional NMUs in the parallel architecture. However, this static energy is negligible with respect to the predominant dynamic energy consumed by the resistive switching behavior of the MTJ cells.

In terms of inference speed, the proposed parallel architecture with SOT technology achieves 1.24×, 1.35×, and 3× speedup compared to Read-SOT [35], Preset-XNOR (PXNOR)-BNN [3], and Intel Xeon E5-2640 processor (CPU) approaches, respectively, due to the high level of parallelism offered using MOL-based IMC. On the other hand, the GPU and FPGA implementations reveal higher inferencing speed (6.3× and 1.6×, respectively) compared to our SOT-based parallel architecture. However, this higher speed comes at the cost of 41× and 3.3× energy consumption. In this regard, it is worth noting that our architecture design adopts the CMOS 65-nm technology node. If the design is scaled to more recent technologies (e.g., 28 nm), we expect even better results in terms of speed and energy consumption. Finally, although the GPU and FPGA implementations present better results in terms of speed, still, they are less convenient for embedded applications such as the IoT devices where area and energy consumption are the most crucial.

C. Hardware Complexity Evaluation

The proposed architecture, which is presented in two models, is mainly composed of interconnected CMEMs, NMUs, and a control unit. The storage space of a CMEM unit should be sufficient to accommodate the Ifmaps, the resulting Ofmap, and the results of intermediate computations of the network layer. Each CMEM unit in the BinaryNet model should have a minimum of 36 kB of space, for a total of 4.5 MB for all CMEM units. It is worth noting that these units are based on the conventional 1T1M crossbar arrays and thus can benefit from the promising 3-D stacking technology of NVMs [37], [38]. Accordingly, the CMEMs crossbars can be stacked at the top of each other, leading to a compact design. In fact, it has not been possible to evaluate the area of the proposed architecture due to the lack of a layout model for the adopted MTJ devices. However, in order to get an estimation of the complexity, we evaluated the total number of components in each CMEM unit, particularly in the peripheral and intermediate drivers. Table III presents the number of utilized hardware resources for a 34-bit width as well as for a general d-bit width CMEM unit. Here, it is worth noting that the reported number of resources grows when expanding the width d of a CMEM unit. Increasing the depth (i.e., number of wordlines) has no additional cost. Table IV presents the number of components involved in the NMU. The NMU is mainly composed of k-bit adders, constant comparators, and registers. In the presented case study, as we employed 128 CMEM banks, the parallel architecture integrates 128 NMUs, whereas the semiparallel architecture integrates only one NMU.

On the other hand, the functionality of the control unit has been emulated using a python-script code, which automatically generates the commands and the address signals to the interconnected CMEM units. It is considered that this functionality can be handled using a host processor, which is programmed according to the desired application (network model, dataset, and parameters). The use of a host processor ensures programmability requirement.

VI. CONCLUSION

In this work, we presented a novel IMC architecture targeting efficient implementation of BNN. The proposed architecture follows what we called SIMM parallelism model to execute instructions inside multiple computational memories. It employs the advanced quantization algorithm of BNN and the promising MOL-based IMC technique, which is well adapted for parallel bitwise operations. The complex MAC operations are replaced by parallel rowwise XNOR and popcounts. Moreover, the addition and normalization stage is replaced by the majority-bin stage, which is achieved through the proposed in-memory bubble sorting technique of channels. An efficient data mapping methodology has been deployed. For simulation and evaluation purposes, a python-based environment with appropriate library and commands has been developed by emulating the functionality of the adopted MOL-based CMEM architecture. A study on the CIFAR-10 BNN model has demonstrated that a proposed parallel architecture, implemented in SOT-MTJ technology, has obtained a notable performance improvement compared to recent relevant state-of-the-art works. The results show 1.24× to 3× speedup compared with Read-SOT, PXNOR-BNN, and Intel Xeon E5-2640 processor (CPU) implementations. Moreover, the proposed parallel architecture outperforms all other approaches in terms of power and energy consumption, where 49%-99% reduction is achieved in terms of energy cost. Besides, it reaches 264-273-image/s/W throughput efficiency, which is much higher than all others, including the CPU, GPU, and FPGA solutions. Finally, the proposed architecture is scalable as it is able to handle larger network sizes and can in addition be compatibly applied to other types of emerging memory technologies.

Chapter 7

Efficient Implementations of Machine Learning Algorithms

Preface

This research work has been accomplished during the PhD thesis of Mr. Hamoud Younes which has been conducted in the Department of Electrical, Electronics and Telecommunication Engineering and Naval Architecture (DITEN) at the University of Genoa, Italy under the supervision of Professor Maurizio Valle. It addresses embedded machine learning with emphasis on hardware accelerators and approximate computing targeting the application of tactile data processing. It has been valorized in four well recognized journals, six IEEE international conferences, and one book chapter.

Introduction

Embedding machine learning algorithms are constrained by the high computational complexity of such algorithms. Moreover, the amount of data processed by machine learning is increasing exponentially [START_REF] Mahmud | A survey of data partitioning and sampling methods to support big data analysis[END_REF]. On the contrary, the processing resources are limited especially with the chip shortage in the last few years [START_REF] Tribe | Flexibility can help car makers cope with chip supply challenge[END_REF]. This poses challenges relevant to the requirements of real-time execution and low power/energy consumption when targeting portable wearable systems due to their limitation in terms of resources and energy budget. Nonetheless, machine learning is one of many application domains that has intrinsic tolerance to inaccuracy. These applications are mostly not about calculating a precise numerical answer; instead, "correctness" is defined as providing an outcome that is good enough, or of sufficient quality to achieve an acceptable application performance [START_REF] Venkataramani | Approximate computing and the quest for computing efficiency[END_REF].

Electronic skin (e-skin) is an artificial skin that mimics the sensing capabilities of human skin. It is usually composed of distributed tactile sensors integrated with an embedded electronic system for tactile data decoding. Meaningful information such as texture classification and pattern recognition can be decoded from tactile data by employing Machine Learning (ML) algorithms. Computations using embedded machine learning algorithms may enable the electronic skin system to be used in various application domains such as wearable, Internet of Things, prosthetic and robotics.

In this perspective, this research work aims at providing efficient implementations of embedded machine learning algorithms for tactile data processing. The core strategy behind delivering efficient implementations is the use of "Hardware Accelerators" and "Approximate Computing" to accelerate demanding portions of ML algorithms and to adequately reduce the algorithms computational complexity respectively. The implementations should offer real-time processing with a time latency less than 400 ms [START_REF] Lele | The reaction time to touch[END_REF] with as much reduced hardware area and energy consumption as possible compared to existing solutions.

Context and Motivations

Tactile sensing involves the detection of motion, the measurement of contact parameters, the processing of the signals to extract structured and meaningful information, and the transmission of such information into a higher system levels for interpretation [START_REF] Dahiya | Tactile Sensing-From Humans to Humanoids[END_REF]. The data acquired from tactile sensors corresponds to an electrical stimulus. The latter varies according to the type of the sensing material, dimensionality, responsiveness, and structure of the sensor. Processing algorithms should be able to decode and efficiently handle the acquired data. Tactile data processing algorithms presented in the literature could be divided into two categories: pre-processing [START_REF] Liu | Low-Resolution Tactile Image Recognition for Automated Robotic Assembly Using Kernel PCA-Based Feature Fusion and Multiple Kernel Learning-Based Support Vector Machine[END_REF][START_REF] Lee | Separation of tactile information from multiple sources based on spatial ICA and time series clustering[END_REF][START_REF] Xanthopoulos | Linear Discriminant Analysis[END_REF][START_REF] Trafalis | Tactile sensing for ground classification[END_REF][START_REF] Nguyen | Dynamic Texture Decoding Using a Neuromorphic Multilayer Tactile Sensor[END_REF] and classification/regression . Pre-processing algorithms involve feature extraction and dimensionality reduction, while classification and regression algorithms are mainly machine learning algorithms.

Machine learning algorithms are an efficient solution for processing tactile data in various applications [START_REF] Gastaldo | Computational Intelligence Techniques for Tactile Sensing Systems[END_REF]. ML algorithms in general, can extract a complex, non linear input-output relationship based on learning by example approach. An ML algorithm is trained using a set of examples, where each example is described by a group of informative features. ML algorithms can support intelligent and predictive systems that can make accurate decisions on unseen data. In this perspective, classification/regression problems supported by ML algorithms could be adopted in applications with tactile information. Several previous works have adopted ML algorithms for tactile sensing [START_REF] Bhattacharjee | Haptic classification and recognition of objects using a tactile sensing forearm[END_REF]163,[START_REF] Kaboli | Humanoids learn object properties from robust tactile feature descriptors via multi-modal artificial skin[END_REF][START_REF] Kaboli | Re-using prior tactile experience by robotic hands to discriminate in-hand objects via texture properties[END_REF].

Embedding machine learning in resource-limited and battery-powered applications for tactile data processing must abide with the ever increasing requirements of small hardware area, low time latency, and low energy consumption, which are mostly impacted by the computational complexity of ML algorithms Designing hardware accelerators is a common trend to implement ML algorithms efficiently, where high performance modules are assigned to complex and demanding blocks of an algorithm. Designing a hardware accelerator can be performed using several methodologies. The use of "specific design" methodology suitable for the hardware platform and application. Another designing methodology is the use of high performance cores in multi-core central processing units (CPUs) or graphics processing units (GPUs) for demanding tasks and assign less performing cores for simpler tasks. Recently, a new hardware accelerator design methodology focuses on techniques such as Near-Memory Computing (NMC) and Processing-In-Memory (PIM), have emerged to bring computing as close as possible to the memory arrays to reduce the cost of data movement between computing cores and memories [START_REF] Fujiki | In-/Near-Memory Computing[END_REF].

In this work, "specific design" methodology targeting different machine learning algorithms and hardware devices/platforms is adopted. Mainly, the design and implementation of hardware accelerators for k-Nearest Neighbor (kNN), Support Vector Machine (SVM), and Binary CNNs. Then, a set of approximate computing methods for enhancing the accelerators' performance is discussed. The performance of the exact and approximate accelerators is assessed on a tactile data processing application, mainly touch modality classification.

Contributions and Performed Work

This work addresses the design and implementation of efficient ML algorithms to handle the challenges retaled to the computational complexity, the performance/availability of hardware platforms, and the application's budget (power constraint, real-time operation, etc.). First, Approximate Computing Techniques (ACTs) are used to reduce the computational complexity of ML algorithms. Then, custom Hardware Accelerators are designed to improve the performance of the implementation within a specified budget. Finally, a tactile data processing application is adopted for the validation of the proposed exact and approximate embedded machine learning accelerators. The contributions of this work are listed below:

• Propose an exact and approximate kNN classifiers with a classification accuracy comparable with [START_REF] Gastaldo | Computational Intelligence Techniques for Tactile Sensing Systems[END_REF] for a touch modality recognition task. The experimental results demonstrate the effectiveness of Data-oriented ACTs on reducing the memory usage and execution time of the KNN classifier with an acceptable accuracy loss.

• Propose an approach for applying algorithmic level ACTs on machine learning algorithms, where each ACT in the proposed approach can serve as a quality configurable knob to trade-off quality for time latency.

• Conduct an overview about energy efficient implementation of machine learning algorithms on hardware platforms highlighting the main challenges when embedding such algorithms. The techniques that could be applied to improve the energy efficiency are reported. Furthermore, the main factors to be taken into consideration when choosing the appropriate platform are highlighted. Lastly, the strategies to overcome the challenges when building an energy efficient embedded machine learning systems are discussed.

• Survey the existing algorithms and tasks applied for tactile data processing. The survey presents the algorithms and tasks, which include machine learning, deep learning, feature extraction, and dimensionality reduction. Moreover, this survey provides guidelines for selecting appropriate hardware platforms for the algorithm's implementation. The algorithms are compared in terms of computational complexity and hardware implementation requirements.

• Perform a comprehensive assessment of applying algorithmic level approximate computing techniques on the FPGA implementation of tensorial SVM.

• Propose an architecture for Singular Value Decomposition (SVD) computation based on approximate computing techniques. The architecture is based on a shallow neural network for finding the SVD of an input matrix with two different dimensions. We provide the structure, tuning, and training of the network. Also, the FPGA implementation of the proposed neural network inference is presented. Implementation results show that the proposed network achieves a significant speedup and reductions in the required hardware resources and power consumption respectively compared to the traditional one-sided Jacobi algorithm.

• The first hardware implementation of a neural network based SVM featuring multidimensional tensorial inputs is proposed. The implementation is feasible for real-time touch modality classification with low power consumption. Moreover, the implementation scalability shows that the neural network based SVM is adequate for the acceleration of SVM on resource-limited hardware platforms.

• The design and implementation of a kNN accelerator using a selection based sorter (Selector) is proposed. The proposed accelerator overcomes similar state of the art solutions by reducing the occupied hardware area while providing noticeable speedups.

• A Hybrid fixed-point binary Convolution Neural Network (HCNN) model for touch modality classification is presented. A hardware accelerator architecture and implementation on FPGA for HCNN is proposed. The proposed accelerator can classify an input touch with a higher accuracy compared to SVM and Deep CNN. Moreover, a faster classification time is noticed while providing a low energy per classification value.

The following subsections provide a brief explanation of the proposed architectures and the achieved results along with comparisons with state-of-the-art works.

Algorithmic Level Approximate Computing Techniques for Machine Learning

Applications in domains like computer vision, media processing, machine learning, etc. have intrinsic tolerance to inaccuracy. Studies repeatedly show that such applications consist of both critical and non-critical components [START_REF] Wong | Soft Error Resilience of Probabilistic Inference Applications[END_REF][START_REF] Leem | ERSA: Error Resilient System Architecture for probabilistic applications[END_REF][START_REF] Misailovic | Quality of service profiling[END_REF]. Thus, it is not necessary for every arithmetic operation to be precisely correct and every bit of memory to be preserved at the same level of reliability. From the perspective of approximate computing, not every operation in a program needs the same level of accuracy. Auto-tuning approaches can help empirically identify error-resilient components [START_REF] Roy | ASAC: automatic sensitivity analysis for approximate computing[END_REF]. However, since machine learning algorithms don't present the same level of accuracy for all applications, the identification process varies from one application to another.

ACTs on the algorithmic level have been firstly investigated in [START_REF] Ludwig | Low-power digital filtering using approximate processing[END_REF]. Authors introduced the concept of incremental refinement. Such concept aims at reducing the number of iterations of iterative processing. A factor of ten reduction in power consumption has been recorded for a speech finite impulse response (FIR) filter implementation. In [START_REF] Chippa | Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency[END_REF], authors explored the different parameters of the SVM algorithm using algorithm level scaling to reduce the complexity of hardware implementations. A 1.2 × -2.2× energy savings have been achieved without any significant accuracy loss. Nogues et. al have presented an approach on how to apply algorithmic level approximate computing techniques on HEVC decoding [START_REF] Nogues | Algorithmic-Level Approximate Computing Applied to Energy Efficient Hevc Decoding[END_REF]. Authors offered a strategy on how to locate the error-resilient components of the decoder and which approximate technique to be applied. Energy reductions of up to 40% are demonstrated for a limited degradation of the application Quality of Service (QoS).

In this research, we propose an approach for applying algorithmic level approximate computing techniques on machine learning algorithms. The approach is based on the work presented in [START_REF] Nogues | Algorithmic-Level Approximate Computing Applied to Energy Efficient Hevc Decoding[END_REF]. kNN and tensorial SVM (TSVM) algorithms are adopted for the evaluation of the proposed approach. The evaluation is performed on both software and hardware levels. For the software evaluation, we monitored the loss in classification accuracy of a touch modality problem presented in [START_REF] Gastaldo | Computational Intelligence Techniques for Tactile Sensing Systems[END_REF] with respect to the gain in execution time and memory requirements. The software evaluation has been accomplished on an Intel CPU.

For the hardware evaluation, a FPGA implementation of both algorithms is presented. Then, the gain in hardware area, time latency, and power consumption is recorded when each technique is embedded in the hardware implementation. Results have shown that the kNN execution time and memory usage can be reduced up to 38% and 55% respectively. Similarly, a 29.6% power reduction and speedup up to 3.7× can be achieved with an approximate kNN FPGA implementation. As for approximate TSVM, the implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. All these reductions are accompanied with a classification accuracy loss than 10%. This research work has been published in the proceeding of the IEEE International Conference on Ph.D Research in Microelectronics and Electronics (PRIME) [START_REF] Younes | Data oriented approximate K-nearest neighbor classifier for touch modality recognition[END_REF] and the proceeding of the IEEE International Conference on Electronics, Circuits and Systems (ICECS) [175] This research work has been also published in the Electronics [START_REF]Algorithmic-level approximate tensorial SVM using high-level synthesis on FPGA[END_REF].

Introduction

Machine Learning (ML) algorithms are efficient solutions for various tasks including speech recognition, tactile data classification and image processing. Consequently, embedding machine learning is increasingly used in several application domains such as prosthesis, Internet of Things (IoT), robotics, smart appliances and wearable devices. Support Vector Machine (SVM) is one of the most used supervised algorithms as it exploits complex relationships among data samples by using "Kernels" to create an optimal hyperplane that separates different classes [1]. Despite having a high classification accuracy, SVM is characterized by its computational complexity. Thus, hardware implementations dedicated to SVM impose additional overhead in terms of power consumption and execution time [2]. This overhead adds a design challenge when targeting real-time embedded systems. Several hardware implementations have been presented using different computing platforms that fulfill the requirements in terms of limited hardware resources, low power consumption and low latency. These platforms include Advanced RISC Machines (ARM), Application-Specific Integrated Circuits (ASIC) and Field-Programmable Gate Array (FPGA). The authors of [3] showed that the implementation of the tensorial SVM (TSVM) algorithm on an ARM Cortex M4 microcontroller (STM32F405) operating at 165 MHz classifies an input touch in 7 s. The latter is higher than the classification time obtained using the FPGA device presented in [4], which is about 400 ms. As for ASIC, the implementation of machine learning inference is characterized by several challenges such as: reconfigurability and design cycle complexity. On the other hand, FPGAs are suitable for prototyping where their features of programmability make them more cost-effective than ASICs. Thus, FPGAs are suitable platforms for implementing such algorithms. In addition, FPGAs are desirable for ASIC prototyping. In this perspective, FPGA has been proposed as a hardware platform for implementing SVM due to its powerful and parallel processing as a re-configurable device with an efficient utilization of hardware resources [2].

The authors of [5,6] presented a hardware implementation of the linear SVM model that classifies biomedical data targeting FPGA devices. The implementations proposed in [5,6] have achieved a speedup of 85× and 6×, respectively, when compared to similar implementations targeting General-Purpose Processor (GPP). Mandal et al. [7] used a multiplier less-kernel architecture to implement a polynomial based SVM. The architecture leads to a power reduction of 3.5% compared to the use of vector-based kernel. A 2D pipelined streaming architecture with a Radial Basis Function (RBF) kernel implementation is proposed in [8], achieving a 2× speed improvement. In [4], the authors presented an FPGA implementation of SVM based on the tensorial kernel approach, which is proposed in [9]. The advantage of such implementation is that the tensorial representation of data preserves the implicit structure of the original data. Sidiropoulos et al. [10] conducted a survey that demonstrates the importance of using tensorial data in signal processing and machine learning. The survey covers several algorithms and applications, including optimization and statistical performance algorithms, collaborative filtering, classification and multilinear subspace learning. In addition, tensorial representation is recommended for applications such as image and tactile processing [9,11].

Approximate computing has emerged as a promising solution to obtain considerable resource utilization, energy and time savings at the expense of acceptable accuracy loss [12]. There exist notable hardware implementations of SVM in the literature using ACTs on both the algorithmic and circuit levels. Van Leussen et al. [13] presented a hardware architecture with re-configurable kernels and overflow resilient limiter. The proposed architecture achieved a saving of 15% in the consumed energy and 14% in the implementation area for the epileptic seizure detection application compared to a fully-exact implementation. The traditional Ripple-Carry Adder (RCA) has been replaced by an approximate accumulator ,which achieves up to 70% power reduction for the kernel computations in SVM for hyperspectral image classification problem [14]. The authors of [15] designed an approximate adder and fixed-width multiplier with a low-cost compensation. Adopting the devised adder and multiplier in SVM classifier leads to reduce the power-delay product (PDP), area and critical path delay by 32.4%, 18.7% and 16%, respectively. All the mentioned architectures imply an accuracy loss less than 8% for the target applications. However, to the best of our knowledge, there is currently no implementations of approximate tensorial SVM classifier presented in the literature.

The work presented in this paper aims to reduce the hardware complexity of the tensorial SVM algorithm using algorithmic level ACTs. A touch modality binary classification problem was adopted to validate the proposed implementation. The exact tensorial SVM classifier in [9] as taken as a reference, and then the impact of ACTs on reducing power consumption, hardware resources and time latency was analyzed. High-Level Synthesis (HLS) with Vivado 2018.3 and Virtex-7 FPGA was used for the implementation. HLS design is adopted since it offers: (1) faster development process compared to RTL design;

(2) built-in optimization directives; and (3) easier design manipulation through high-level programming languages (e.g., C/C++). The rest of the paper is organized as follows. Section 2 presents the algorithmic level approximate computing techniques and how they are applied on machine learning methods. Section 3 provides a general overview of the tensorial approach. Section 4 details the proposed approximate tensorial SVM architecture and implementation. Section 5 presents an assessment of the hardware implementation results targeting FPGA using HLS. Finally, Section 6 concludes the paper and illustrates the future work.

Algorithmic Level Approximate Computing

Approximate computing techniques can be applied at algorithmic, architecture and circuit levels [16]. Algorithmic level techniques are divided into two categories: data-7.4. CONTRIBUTIONS AND PERFORMED WORK oriented and process-oriented. The authors of [17] presented an approach on how to apply these techniques on machine learning algorithms, as shown in Figure 1. The data-oriented category involves modifying the data properties (size and bit-width) to minimize the work-load on the circuit level. This category includes:

• Dataset Reduction (DsR) decreases the amount of the processed data by eliminating samples randomly or using a subsampling method as the one proposed in [9]. Furthermore, DsR can be applied through downsampling and downscaling. The former adjusts the sampling frequency of the electronic interface used to collect raw data samples from sensors in the time domain, while the latter reduces the dimension of the collected data themselves (e.g., reducing the tensor size from 4 × 4 × 3 to 3 × 3 × 3), as shown in Figure 1. • Data Format Modification (DFM) reduces the bit-width of the data and its corresponding arithmetic operations. This can be done by replacing floating-point representation with a fixed-point one. For instance, a 24-bit fixed-point representation data is adopted in [18] instead of floating-point to represent tactile data with a negligible precision loss.

The process oriented category targets the algorithm itself by reducing the number of tasks or replacing some of them with a less-complex counterpart. This category includes [19]:

•

Computation Skipping (CS) skips a certain number of tasks in an algorithm. If these tasks are loop iterations, then it is referred to as Loop Perforation (LP). For example, in some machine learning applications, a pre-processing task such as data normalization may be skipped without affecting the quality of service of the target application. • Computation Approximation (CA) proposes an equivalent version of a computationally complex function. The two versions should be mathematically equivalent with an acceptable output error margin. For example, a division function could be replaced by a reciprocal multiplication [19].

Tensorial SVM Algorithm

Gastaldo et al. [9] presented a tensorial kernel approach for touch modalities classification. The approach involves four main steps: (i) Unfolding includes the transformation of a third-order tensor T(I 1 × I 2 × I 3 ) into three matrices M(I 1 × I 2 I 3 ), N(I 2 × I 1 I 3 ) and P(I 3 × I 1 I 2 ). (ii) Singular Value Decomposition (SVD) is used to find the eigenvectors V for each of the three unfolded matrices as:

A = USV T (1)
where U and V T contain the left and right singular vectors, respectively, and S is the diagonal matrix storing the singular values σ i of A. SVD computations are achieved by using the one sided Jacobi algorithm, which is considered as one of the fastest methods to converge compared to other algorithms [20]. (iii) Kernel computation extends the Gaussian kernels to tensorial patterns. The kernel function can be expressed as:

K(x, y) = z ∏ 1 k z (x, y) (2)
where k z is the kernel factor defined as:

k(x, y) = exp( -1 2σ 2 (I n -trace(Z T Z))) (3)
where Z = V T x V y , V x represents the singular vectors of the unfolded matrix, V y represents the singular vectors of the unfolded matrix obtained from the training phase and trace represents the sum of diagonal elements. (iv) SVM classification applies the classification function expressed in the following equation:

y = f SV M (x) = Np ∑ i β i K(x, y) + b (4)
where y represents the predicted label of an input x and β i represents the coefficients obtained during training with a bias b.

Approximate Tensorial SVM

The proposed architecture of Approximate SVM is presented in Figure 2. The architecture is an extension to the exact architecture presented in [21]. For the rest of the paper, the latter is referred to as Exact SVM. It involves two stages: offline learning and online inference.

Touch Modality Framework

The touch modality classification problem "Brushing a brush vs. Rolling a washer" referred to as Problem A in [9] was adopted to verify the proposed architecture. This problem is based on a dataset that includes readings from 70 participants. The tactile dataset was acquired by conducting experiments to sense the human touch pressure levels on a 4 × 4 tactile sensor array for a duration of 10 s with a sampling rate of 3000 samples per second. Thus, each modality can be described by a tensor φ(4 × 4× 30,000). The final dataset was split into training and testing sets with N t = 180 and N c = 80. The proposed algorithmic-level approximate computing method discussed in Section 2 was applied on the exact tensorial SVM for the mentioned classification problem. Table 1 shows the effect of using this method on the classification accuracy. The dataset reduction was applied by randomly removing samples from the original dataset. To ensure credible assessment, if a sample is removed during the 10% reduction, it is automatically removed for the 20% and 30% reductions. Loop perforation was applied on the loops of SVD computation block with a skipping factor s f (i.e., how many loops are perforated). As for data format modification, 24-and 16-bit fixed-point representations were applied for all the SVM operations with < 8, 16 > and < 6, 10 > precision, respectively, using the C libraries used in [18]. Based on the obtained results, the training and inference of the exact tensorial SVM were incorporated with the ACTs that resulted in an acceptable trade-off between accuracy and complexity. Combining several ACTs is also known as "cross-layer approximate computing" [12].

Offline Learning

The SVM training was conducted offline on a PC with Intel i7 CPU. The training process starts by activating the AU1 (Approximate Unit 1) (see Figure 2). AU1 applies dataset-reduction and downscaling techniques on the dataset by performing the following steps:

•

The dataset size is reduced by eliminating data that corresponds to five participants with noisy readings. Figure 3a shows an example of such reading where the voltage is almost constant along the measured time. Therefore, the machine learning model will not learn new information from such sample. Hence, it is removed.

•

During data collection of the tactile dataset, no precise instructions were given to the participants regarding the amount of pressure to be applied on the sensor [9]. Thus, some touch samples with silent readings where observed such as the one presented in Figure 3b. Such samples could be pre-processed to extract meaningful information in certain time frame. Each sample is truncated from 10 to 3. ) that have to be symmetrized before applying SVD. The resulting support vectors along with the Gaussian parameter σ = 1 are fed to the kernel computation block (see Figure 2). The block outputs the kernel matrices for (+1 vs. -1), (+1 vs. +1), (-1 vs. +1) and (-1 vs. -1) binary classification problems where each row being labeled with the corresponding class label. This step is essential since LIBSVM [22] does not support tensorial kernels by default but can receive precomputed kernels. The LIBSVM library is used to obtain a classification model based on the precomputed kernel. The model contains the coefficients β i and the bias b.

Online Inference

The SVM inference of the proposed architecture was implemented on FPGA through the steps shown in Figure 4. The architecture was coded in C++ using Vivado HLS. Then, the architecture was optimized using HLS directives and synthesized to ensure that it fits in the target FPGA device. Then, a C/RTL simulation was performed to ensure a coherent output from the architecture coded in C++ and the RTL design provided by Vivado HLS. Afterward, the architecture was exported as an RTL IP block targeting a Virtex-7 XC7VX980T FPGA operating at a clock frequency of 120 MHz. The IP block was imported into Vivado; then, a behavioral/combinational simulation was performed to verify the integrity of the exported IP. Then, place and route was performed to implement the architecture on the FPGA device. Finally, a detailed report about the utilized hardware resources, the number of clock cycles and the power consumption was obtained once the implementation was completed. 3) with an acceptable error margin. This technique was also applied in the offline training phase so that the equation Z = V T x V y has correct dimensions.

CONTRIBUTIONS AND PERFORMED WORK

• Data Format Modification (DFM) to all the variables and arithmetic operations in different SVM blocks. HLS offers a library called "apfixed", which allows the declaration of variables with fixed-point precision. This declaration is limited by an upper bound [23]. Specifically, the mathematical functions are Square Root (sqrt), which is used in SVD calculations, and Exponential (exp), which is used in kernel computations. These functions are supported only for bit-widths w ≤ 32 and w ≤ 16, respectively. This limitation was resolved by a variable precision architecture. Hence, all the inference blocks are implemented with 24-bit fixed-point representation with a < 12, 12 > precision except the kernel computation block.

Finally, the output of the kernel computation (i.e., a kernel) is used by the classification block to predict a class for the tested tensor according to Equation (4).

Performance Booster

The performance of the proposed architecture was enhanced to achieve the lowest possible time latency for applications with timing constraints [24] while increasing the throughput. These requirements are usually accompanied by an increase in hardware resources, but the use of algorithmic level approximate computing techniques, specifically "dataset reduction" and "data format modification", would compensate such increase.

These requirements are facilitated by the use of Vivado HLS optimization directives [23]. The used directives are: 3) is executed in parallel, as shown in Figure 7.

FPGA Implementation Results and Assessment

Implementation Results

Figure 8 shows the normalized speedup and reduction in power consumption while assessing different approximate computing techniques. The latter are applied one-by-one resulting in eight different FPGA implementations. Each implementation is compared to the exact implementation where the time latency (L) is recorded as:

L = N × 1 f max ( 5
)
where N is the number of clock cycles and f max is the maximum operating frequency. As for the power consumption, a vector-based method was adopted as it provides the power consumption related to the processing under a defined testbench. The method involves generating a "saif" file via post-implementation functional and timing simulations. Using the obtained results in Figure 8, a cross-layer Approximate SVM implementation was performed where the adopted techniques are: 10% dataset reduction, loop perforation with s f = 2 and 24-bit DFM. Moreover, the implementation details was recorded with the performance booster ON and OFF to differentiate between the gain due to approximate computing techniques with and without HLS optimization directives. Table 2 summarizes the performance profile for the FPGA implementations based on the architecture in Figure 2. The Exact SVM is based on the architecture presented in [21]. The boosted Approximate SVM corresponds to the Approximate SVM where the "Performance Booster" block is activated (See Figure 2), i.e., with HLS optimization directives. The reduction is calculated as:

Reduction(%) = 100 -( I approx I exact * 100) (6)
where I approx and I exact are the implementation element (FF, DSP, LUT, etc.) of the Approximate (or boosted approximate) and Exact SVM, respectively. As for the energy per classification, it is calculated using the equation:

E = P × T ( 7
)
where T is the time latency and P is the dynamic power consumption reported in Vivado.

Implementation Assessment

The obtained results presented in Tables 1 and2 and Figure 8 demonstrate the effectiveness of using approximate computing techniques to reduce the hardware resources utilization, time latency and power consumption of the FPGA implementation of the tensorial SVM. Such reductions are accompanied by an accuracy loss that varies between 0% and 10%. Another set of remarks can be noticed:

•

In general, loop perforation achieves lower latency and power consumption compared to dataset reduction with a comparable accuracy loss. This can be justified since the SVD computation block is among the most complex blocks of the tensorial SVM, as reported in [4].

•

The transition to fixed-point representation results in the lowest latency and power consumption compared to other methods. This is expected due to the reduced complexity of the arithmetic operations based on fixed-point representation. This can be seen in the reduced number of required DSPs between the exact and approximate implementations. However, this comes at the expense of high accuracy loss; for example, the use of a 16-bit fixed-point led to a 15% accuracy loss for the target application.

•

The number of used BRAMs is high since we are not using any external DRAM for memory read/write operations. The range of the number of LUT and DSPs is expected due to the level of parallelism introduced using HLS directives. For the target FPGA, this is not a problem as long as we obtained a relatively reduced time latency and power consumption in the case of Approximate SVM.

•

Using "cross-layer" approximate computing: with an accuracy degradation of 4%, the Approximate SVM requires about 43% less hardware resources and classifies an unseen sample 2.64× faster while consuming 50% less power compared to its exact counterpart.

•

The accuracy loss due to the use of "cross-layer" approximate computing is not the sum of the losses obtained for each single approximate technique. This is evident in the final results presented in Table 2.

• The use of ACTs shows a remarkable reduction in the energy per classification up to 82%, since such techniques affect both the time latency and power consumption of the TSVM, as shown in Table 2.

•

Applying the adopted HLS optimization directives offered an additional speedup gain to the Approximate SVM in terms of speedup up to 3.2× accompanied with 84% less energy per classification.. This added a negligible overhead less than 1% increase in the hardware resources and power consumption. This is expected due to the fact that pipelining offers a reduction in the number of clock cycles while increasing the resources/power consumption. However, such increase is compensated by the dataflow directive that allows resource sharing, providing an enhanced overall implementation.

Conclusions

This paper presents the first FPGA implementation using High-Level Synthesis of an approximate tensorial SVM classifier. An accuracy of 86% was obtained with a speedup of 3.2× and 49% power consumption reduction resulting in up to 82% reduction in the energy per classification. Such results were achieved by utilizing the concept of cross-layer approximate computing. Combining several algorithmic level approximate computing techniques demonstrated their efficiency in optimizing the proposed embedded machine learning implementation. Moreover, specific design choices (e.g., using pipe-lined architecture) could boost the implementation performance with the help of Vivado HLS directives. The obtained reduction factor in hardware resources, time latency, and power consumption through applying ACTs paves the way towards applying such techniques on the RTL HDL design of the TSVM presented in [4] where similar reductions are expected. Such promising results motivate the exploration of different types of ACTs such as circuit-level techniques or the use of neural networks to further reduce the impact of computationally expensive singular value decomposition, as it represents about 70% of the whole implementation.

Efficient Selection-based k-Nearest Neighbor Architecture on Modern SoCs

Modern System-on-Chips (SoCs) are designed with heterogeneous architectures to support a variety of computationally intensive tasks in many application domains such as IoT systems, industrial automation, robotics, etc. These systems could consist of multi-core processors or multi-processor system on chip, which could be implemented on GPUs, application specific integrated circuits, or field programmable gate arrays. The latter is used for accelerating complex operations and performing tasks concurrently compared to traditional processors.

kNN is a supervised classification algorithm used in a variety of applications such as pattern recognition, computer vision and machine learning [START_REF] Sun | A Survey of kNN Algorithm[END_REF]. However, kNN imposes significant computational workload since the complexity increases linearly with the size of the dataset and the number of classes [START_REF] Li | K-nearest neighbor algorithm implementation on FPGA using high level synthesis[END_REF]. Such workload demands significant memory requirements with high latency and power consumption [START_REF] Saikia | K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM[END_REF]. Accordingly, the implementation of kNN on embedded systems with limited available energy and resources introduces a design challenge, which makes kNN hardware acceleration a necessity. kNN algorithm involves independent operations e.g. the distance computation between a point A and point B is independent of that between points A and C. Thus, kNN doesn't require the sorting of the entire distance vector to find the K-Nearest Neighbors. Such characteristics could be exploited to reduce the computational complexity of the algorithm using a pipelined architecture and tweaking the sorting process.

In this research work, we propose the design and implementation of a kNN architecture that is characterized by a novel selection-based sorter (Selector). The proposed selector overcomes similar state of the art solutions by reducing the occupied hardware area by up to 48% while providing a speedup up to 4.5×. The proposed kNN architecture is implemented using both exact and approximate computations. The approximate architecture utilizes the use of algorithmic level ACTs. When validated on a touch modality classification problem, both the proposed exact and approximate kNNs offer a real-time classification while consuming 6 µJ and 1.9 µJ respectively when implemented on Xilinx Zyqnberry platform. Compared to similar kNN architectures, the proposed kNN achieves a speedup between 1.4× and 875× with 41% to 94% less energy consumption and 12% to 94% average hardware area reduction. Moreover, applying algorithmic level ACTs on the proposed architecture improves its performance by achieving a 56.4% average area reduction, a speedup by 2.3×, and an energy reduction of about 69%. An accuracy degradation of 2.6% has been reported using the proposed approximate architecture. This research work has been published in the IEEE Open Journal of Circuits and Systems (OJCS) [START_REF] Younes | An efficient selection-based kNN architecture for smart embedded hardware accelerators[END_REF].

I. INTRODUCTION

M ODERN System-on-Chips (SoCs) are designed with heterogeneous architectures to support a variety of computationally intensive tasks in many application domains such as IoT systems, industrial automation, robotics, etc. These systems could consist of multi-core processors, or specialized hardware such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The latter is used for accelerating complex operations and performing tasks concurrently compared to traditional processors. K-Nearest Neighbor is a supervised classification algorithm used in a variety of applications such as pattern recognition, computer vision and machine learning [1]. However, kNN imposes significant computational workload since it has a linear scalability with the size of the dataset and the number of classes [2]. For embedded implementations, such workload demands significant memory requirements with high latency and power consumption [3], which makes kNN hardware acceleration a necessity. kNN algorithm involves independent operations e.g. the distance computation between a point A and point B is independent of that between points A and C, and kNN doesn't require the sorting of the entire distance vector to find the K-Nearest Neighbors. Such characteristics could be exploited to reduce the computational complexity of the algorithm using a pipelined architecture and tweaking the sorting process. Another solution for complexity reduction could be the use of Approximate Computing Techniques (ACTs). Approximate computing is the idea of reducing the accuracy to an acceptable limit to save energy, memory, and execution time without affecting the applications' overall qual- ity [4]. Compared to Exact Computation Techniques (ECTs) i.e. performing arithmetic operations following the IEEE-754 and IEEE-854 standards for floating-point operations [5], the challenge of using ACTs is to maintain the approximation error acceptable with respect to the target quality of service (QoS) [6]. ACTs can be divided into two categories as shown in Figure 1: Processing-oriented and Data-oriented [6]. Processingoriented techniques consist of "Computation Skipping" and "Computation Approximation". The former technique involves removing some processing tasks (e.g. image compression, encoding, etc.). The latter one replaces computationally intensive blocks with approximate ones that implements the same mathematical operations. Data-oriented techniques target dataset modifications as "Dataset Reduction" and "Data Format Modification". Dataset Reduction aims at decreasing the number of processed samples through Downsampling and Downscaling. Downsampling includes adjusting the sampling frequency of a processing block or truncating the size of an acquired sample. Downscaling reduces the dimension of the 7.4. CONTRIBUTIONS AND PERFORMED WORK data by adjusting the matrix or vector size for vector-based applications. As for Data Format Modification, it changes the data from floating-point to fixed-point representation to simplify the involved arithmetic operations." Approximate computing can lead to significant improvements from algorithmic to circuit level. Authors in [7] have presented an assessment of the different approximate computing techniques applied at the circuit, architecture, and algorithmic levels. Applying ACTs on supervised learning algorithms at the algorithmic level has been the focus of Younes et. al in [8] with a case study on the kNN algorithm. Authors reported that approximate kNN offers a computation boost in terms of 2× speedup compared to Exact kNN.

To design a hardware accelerator for the kNN algorithm, an efficient architecture is proposed in this paper. The architecture introduces novel sorting process dedicated for kNN accompanied with several design optimizations. Moreover, ACTs are incorporated to further enhance the performance of the embedded implementation. For the rest of the paper, the term "performance" is used to report the characteristics of a kNN hardware implementation in terms of area, time latency, power consumption, and energy per classification. While, the term "quality" reflects the highest classification accuracy that a kNN architecture could achieve.

The main contributions of this paper could be summarized as follows:

• It proposes the design and implementation of a selectionbased sorter (Selector) for the K-Nearest Neighbor (kNN) algorithm. The proposed selector overcomes similar state of the art solutions by reducing the occupied hardware area by up to 48% while providing a speedup up to 4.5×.

• It presents a novel kNN architecture that outperforms similar state of the art solutions in terms of occupied hardware area, time latency, and energy consumption. When validated on a touch modality classification, the proposed kNN achieves a speedup between 1.4× and 875× with 41% to 94% less energy consumption and 12% to 94% average hardware area reduction.

• It applies algorithmic level ACTs on the proposed architecture to improve its performance: the results show a 56.4% average area reduction, a speedup by 2.3×, and an energy reduction of about 69%. For a touch modality classification problem, an accuracy degradation of 2.6% was reported using the proposed approximate architecture.

• It demonstrates the feasibility of the implemented system for real-time touch modality classification when validated on Xilinx Zyqnberry platform. The proposed exact and approximate kNNs consume 6 µJ and 1.9 µJ respectively.

The rest of the paper is organized as follows: Section II reports on some of the efficient implementations of kNN presented in the literature. Section III explains the design and the high-level synthesis of the proposed selection-based kNN architecture. Also, it describes the selector integration into exact and approximate kNN classifiers. Section IV presents an overview of the tactile data processing case study and the experimental setup used to asses the quality of the proposed architecture. This Section also highlights the implementation tools and methodology with emphasis on the adopted design optimization techniques. Section V provides a performance analysis for the FPGA implementation of both the exact and approximate kNN classifiers. Also, a comparison with similar works from the literature is conducted. Section VI concludes the paper highlighting some future works.

II. STATE-OF-THE-ART

Several architectures have been proposed in the literature for implementing the kNN algorithm on hardware platforms. One of the first architectures and implementations is presented in [9]. The architecture is based on a neural network with SIMD-style architecture, which imposed excessive response time while performing complex operations. Authors in [10] designed flexible IP cores based on linear array architecture for the FPGA implementation of the kNN algorithm. The cores achieved a very high throughput when validated on a medium size FPGA device, very large size classification problems, and with thousands of reference data vectors. A novel dynamic partial reconfiguration (DPR) architecture of the kNN algorithm is presented in [11]. The architecture is characterized by an efficient reconfiguration time for different values of K. Speedups between 68× and 76× were recorded when compared to General Purpose Processor (GPP) implementation. Pu et. al designed a kNN-specific bubble sort algorithm to take advantage of the FPGA parallel pipeline structure using OpenCL [12]. The overall implementation showed an enhanced performance compared to conventional GPU implementations. Authors in [13] adopted a Bitonic sorting algorithm to implement the kNN algorithm on both FPGA and GPU. Using OpenCL coding style and some HLS directives, the results showed that an FPGA implementation could be comparable to a GPU in terms of execution time. Another HLS based implementation has been reported in [2]. With a reduced number of comparators in the sorting process and by utilizing the memory-mapped AXI4-Master Interface of the Xilinx ZC706 FPGA board, a 35.1× speedup over a GPP based implementation is noticed. In [14], several architectures are presented, where each one adopt a single or multiple HLS optimization directives. Speedups between 3.8× and 58× could be achieved while using the quick sort algorithm and the BCW 9 dataset. Both hardware and software designs using Xilinx MicroBlaze platform were used to verify the bubble sort based architecture of the kNN algorithm in [15]. The hardware design achieved 127× speedup compared to its software counter counter-part. To reduce the impact of the memory-access constraint in kNN classification problems, an HLS based kernel is proposed in [16]. The kernel employs two data access reduction methods: low precision data representation and principal component analysis based filtering (PCAF). The kernel performed to an equivalent 56-thread CPU server while greatly reducing external memory-accesses.

A common characteristic of the most existing efficient kNN architectures is the use of the conventional sorting algorithms without optimizations for the kNN algorithm. The efficiency of these algorithms is affected by the: i) need to sort all the vector's elements, ii) large number of required comparators, and iii) increased complexity/latency for large vector size. In this work, we propose a kNN architecture that avoids such sorting algorithms and adopts a selection-based one with a reconfigurable division ratio for complexity and latency tradeoffs (see Section III.C). Moreover, existing kNN implementations focus on acceleration gains compared to CPU-based implementations. This work reports a detailed comparison with FPGA-based kNN implementations that sheds the light on different implementation strategies and their effect on the kNN performance.

III. K-NN PROPOSED HARDWARE ARCHITECTURE

A. k-Nearest Neighbor Algorithm Overview

The kNN algorithm classifies an input sample according to the class of the majority of K-nearest samples. For an input sample, the kNN classifier 1) calculates the distance between the input sample and all the samples in the training set T i ∈ T , 2) sorts the distances in ascending order, and 3) selects an output class based on the minimum distance towards K neighbors. The three main considerations for kNN are:

• The number of nearest neighbors K. A 1-NN classifier is naïve, while a large value of K might result in overfitting. Thus, the value of K is determined using a tradeoff between accuracy and complexity.

• The distance metric could be Chebyshev, Manhattan, Cosine, Euclidean, etc [17].

• The sorting algorithm could be bubble, select, quick, etc [18].

B. Selection-based kNN Architecture

The block diagram of the proposed hardware architecture is shown in Figure 2. The "kNN Classifier" block has been designed in HLS (coded in C++), whereas the other blocks are existing IP blocks embedded in Vivado. The SDRAM memory is used to store the training set, which is more suitable than the Block RAM (BRAM) of the FPGA for platforms with limited number of BRAMs or applications with large datasets. The AXI Interconnect IP handles the read and write operations from and to the memory. It adopts an AXI smart connect IP to use one AXI port for 1) writing to the data acquisition block and 2) reading the classification result from the class determination block. The Zynq processing system IP is the main block of the design which uses a processor system reset IP to drive all blocks with a common clock and reset signals. The kNN HLS IP starts operating once the Data acquisition block receives the training samples. To reduce the access overhead imposed by DRAM, we fetch the samples in bursts to reduce the number of memory accesses. Such technique has shown its efficiency in [13] and [19]. First, the distance between a testing sample and all training samples is performed. Then, the K minimum distance values are determined using the proposed selector (see subsection C), and finally a class is assigned for the testing sample using the class majority of the samples corresponding to the K minimum distance values.

C. Nearest Neighbors Selector

The proposed architecture aims to replace the conventional sorter block with a "Selector" which finds the K-minimum distances without sorting the entire vector [20] as depicted in Algorithm 1. While coding the selector in HLS, the minimum K-distance values are saved in the same vector to be sorted, thus decreasing the memory footprint.

The selector operations can be detailed in three steps: have been coded in C++ using Vivado HLS. The distance vector V has been used as a testing vector for the three implementations. In this paper, the best K value and division ratio were determined to be 3 and 6:4 (for the case study presented in section IV.B) i.e. there is a need to sort only 60% of the vector and step 3 can be aborted without affecting the selection process accuracy. The obtained synthesis results for finding the three minimum numbers in V are presented in Table I. Results show that the selector occupies less hardware area than the implementations of both sorters. Specifically, an average reduction of 21.4% and 48.7% is reported compared to the sorters in [12] and [21] respectively. Concerning the time latency of the sorting process, the selector is faster than the sorter in [21] by 4.5×. Compared to the sorter in [12] that adopts one of the fastest sorting algorithm (QuickSort), the performance depends on the selection of the division ratio in step 1 and the number of neighbors K. In fact, if all the minimum numbers are located in V2, or if the required value of K is very large; the selector is now sorting all the elements of V resulting in a slower sorting process. Hence a speedup of ±1.2× (for 6:4 and 5:5 ratios respectively) has been observed for the given task.

• Step 1: The distance vector V of size S is divided into two vectors V 1 and V 2.

D. Approximate kNN Blocks

In [23], we have presented a complete assessment of using algorithmic level ACTs on a kNN classifier. The assessment included the degradation in accuracy to the gain in memory and execution time on Intel i7 CPU. In [8], the studied techniques have been formulated into a general approach that has been tested for the FPGA implementation of two machine learning classifiers. The reported approach has been adopted in this paper where a trade-off between the classifiers performance and quality has been considered. The trade-off resulted in our selection for the ACTs presented in the proposed approximate kNN architecture. All the adopted techniques belong to the data-oriented approximate computing category [8]. The adopted ACTs are Dataset Reduction (Downsampling (DS) and Downscaling (DSc)), and Data Format Modification (DFM). DS means varying the signal sampling frequency during signal acquisition. Since tactile data used in this work are from an already available dataset, the sampling frequency can't be changed. As a consequence, DS is applied offline on the dataset by reducing the number of samples. DSc is applied by adjusting the sample size as shown in subsection IV.A. DFM reduces the sample resolution. This can be achieved through the use of fixed-point or mixed precision instead of floating-point data representation. In this paper, fixed-point representation is adopted, and the precision is determined as a trade-off between resolution (32, 24, 16, and 8-bit) and classification accuracy." The approximate kNN classifier starts operating once the Data Acquisition block receives the training samples (after DS/DSc has been applied offline) from the memory. Then, the same steps performed by the kNN HLS IP are executed.

IV. SELECTION-BASED KNN IMPLEMENTATION AND CASE STUDY

A. Case Study: Tactile Data Processing for Electronic Skin Systems Electronic skin system is an artificial system developed to mimic human skin behaviour or to implement intelligent tasks in applications such as robotics, prosthetic, etc. Intelligence involves the use of learning algorithms for tactile data processing in tasks such as surface texture, object compliance, touch modality, etc. [24], [25]. Touch modality classification allows the integration of gesture-based actions to be performed by robots or humans with prosthetic hands. For a medical purpose of caring for patients with mild mental impairment; a humanoid equipped with artificial skin has been trained to discriminate between nine touch modalities (scratch, tickle, rub, etc.) [26]. Recognition rates up to 96.7% has been achieved using four machine learning algorithms including kNN, SVM, DT, and Logitboost. Authors in [27] and [23] have adopted a touch modality classification problem that involves three patterns: brushing a paint brush, rolling a washer, and sliding a finger on 4 × 4 tactile sensory array. SVM and Extreme Learning Machine (ELM), kNN, and Deep CNN based on transfer learning have been chosen as learning algorithms. A classification accuracy of 90%, 89.8%, and 76.9% has been recorded respectively.

In this paper, the kNN algorithm is adopted for the design of an embedded tactile data processing architecture due to the: 1) high level of parallelization of the kNN algorithm, which makes it adequate for hardware acceleration, 2) high classification accuracy with a reduced computational complexity compared to state-of-the-art algorithms operating on the same task [28], [29], and 3) ability of complexity reduction without affecting the application quality using approximate computing techniques [23].

The dataset collected in [30] has been selected for the validation of the proposed kNN architecture. The experimental setup is shown in Figure 4 and can be described as follows:

• Dataset: The dataset contains records for the two touch modalities performed by 70 participants. Each modality was recorded from a 4 × 4 tactile sensor for 10 seconds at 3 kHz sampling frequency. Thus, each raw data sample can be modeled in the form of a tensor of size 4×4×30,000. The touch modalities were performed on both the horizontal and vertical directions for two trials, resulting in a dataset of 840 samples.

• Simulation Software: An open-source machine learning simulation tool called "Weka" has been used [31]. Weka involves a collection of learning algorithms that can be applied to a pre-defined dataset or invoked from a Java code. The tool has options for classification, clustering, regression, etc.

• Classification Task: the binary problem "Sliding a finger" vs "Washer Rolling". For Weka simulation an Attribute-Relation File Format (ARFF) file is required. Thus, a header describing the features and the possible output class of each sample is added to the original tactile dataset.

Fig. 4. Experimental Setup

• kNN Characteristics: A 10-fold cross-validation simulation using the Weka tool has been carried to determine the best value of K. The adopted distance between two tactile samples T 1 and T 2 is the squared euclidean distance written as:

d(T 1 , T 2 ) = 16 0 (T X ij -T X mn ) 2 (1)
where T X ij and T X mn are the taxels inside a 4 × 4 tactile sample.

• Classification Metric: The kNN algorithm has been assessed by calculating the classification accuracy i.e. the ratio of correctly classified samples to the total number of available samples. The ARFF file was loaded into Weka and classification using kNN is performed. A kNN classifier with 3-nearest neighbors resulted in the highest classification accuracy of 89.8%. This result was achieved based on a model selection approach. Based on the best kNN model obtained, a novel efficient kNN architecture is proposed in this paper. Furthermore, approximate computing techniques have been applied to enhance the overall performance of the proposed architecture without affecting the quality of the application.

The best obtained kNN model with K=3 is referred to as Exact kNN. As for Approximate kNN, it employs the following techniques to the Exact architecture: 1) Downsampling which applies an approximate window on the touch modality, where only the data that corresponds to the interval [a,b] seconds is considered. First, the interval [a, b] is selected such that 0.1 < a 1 and 9.5 < b < 10. Then, the values of a and b are varied, while calculating the classification accuracy. The interval [3.5, 7] provided the highest accuracy among others. Thus, each modality tensor can be written as φ = 4 × 4 × 10, 500 (touch readings that belong to the interval [3.5, 7] seconds), and 2) downscaling which reduces the tensor size to φ = 4 × 4 × 1, where the last dimension is the mean of the 10,500 readings according to the equation:

mean = T X ij 10500 (2)
where T X ij is the individual taxel inside the 4×4 tactile sample. Figure 5 shows the initial and obtained touch modalities after applying DS and DSc.

It is worth mentioning that the tensor representation of data has been adopted by [30] since it preserves the initial structure of the data, which is still valid after applying approximate computing techniques. This is evident in Figure 5 (b),(c) where the two touch modalities can still be differentiated. For both the Distance Calculation and Nearest Neighbor Selection blocks, the operations are implemented in 24-bit fixed-point representation with a < 6, 18 > precision. The adopted precision is based on a trade-off between complexity and classification accuracy.

B. Hardware and Software Design Tools

The Zynqberry TE0726-03M [32] was adopted for implementation. Zynqberry is a small-sized platform in the form of a Raspberry Pi compatible System-on-Chip (SoC) module integrating a Xilinx Zynq-7010 with a 512 MB SDRAM memory. The Zynq SoC has a hybrid structure of combining a dual-core ARM Cortex-A9 processor as a Processing System (PS) and an FPGA as Programmable Logic (PL) in a single SoC. Moreover, for comparison purposes, the architecture has As for the software tools, Vivado HLS 2018.3 and Vivado 2018.3 were used. Vivado HLS allows the design of an embedded system on FPGA using a high-level programming language such as C and C++ compared to traditional hardware description languages (HDL). The use of HLS decreases the FPGA development time and effort. Also, it offers a set of optimization directives that can be used to enhance the design performance. Once the design is completed, it can be exported as a Register Transfer Level (RTL) Intellectual Property (IP) block. The latter is imported into Vivado and can be connected to the processing system (PS) via built-in IPs; thus, it is possible to obtain the hardware resources, time latency, and power consumption of the whole design.

C. Implementation Methodology

Once the whole design code is completed in HLS and design optimizations are applied, a co-simulation is performed. This simulation runs both the C++ and the RTL simulations together to verify a matching output. Then, the design is exported as an IP block. The latter is imported into Vivado 2018 and connected to the Zynq processor and other IP blocks as seen in Figure 2. First, a behavioral simulation is performed to verify the functionality of the design. Then, synthesis and place and route occur to finalize implementation. At this point, the generated report contains the occupied area percentage (BRAM, DSPs, etc.) and the number of clock cycles passed to generate an output. Concerning power consumption estimation, Vivado offers two methods: Vector-based and Vector less. This estimation can be performed at any stage between postsynthesis to post routing. For a credible estimation, a postimplementation functional and timing simulation is used to generate a Switching Activity Interchange File (SAIF) to be used for a vector-based estimation post-routing.

D. Design Optimization

Targeting the real-time functionality on a small-sized platform such as Zynqberry, the proposed architecture has been optimized to ensure an acceptable balance between time latency and hardware requirements. This has been achieved with several design optimizations as shown in Fig. 6. Such optimizations are facilitated with the use of Vivado HLS directives [33]

1) BRAM Resources Reduction: The BRAM size is 18K in the FPGA, if many arrays have a size less than 18K, it is better to combine them into a single array. Since kNN is a supervised algorithm, the class of each query must be known. Thus, we can benefit from this directive to combine the "Distance" and "Modality" arrays into a single array as shown in Figure 6(a). Thus, when the selector block finds the three minimum neighbors, the class of each selected neighbor is available at the same instant. This process is referred to as "Array Map" where the horizontal option means that the two arrays are combined into a single array with more elements (see Algorithm 2). 2) Parallelization: To exploit the capabilities of the FPGA, the operations of the distance calculation and the class determination blocks are executed in parallel with a small unroll factor. In HLS terms this is known as "Unrolling", where unrolling a loop creates multiple copies of its body in the RTL design, which allows some or all of its iterations to occur in parallel. This optimization has been applied to (1) denoted as Unrolled Distance Calculation (UDC) and the Class Determination blocks leading to accelerating the calculation and output class decision. However, executing all the operations in parallel leads to a high power consumption and increased resource requirements. To avoid the negative impact of unrolling on the hardware cost and power consumption, the loops are partially unrolled (unroll factors of 4 and 6) as it is shown in Algorithm 2, and the design is implemented at an operating frequency of 100 MHz which is lower when compared to similar work [21]. Each touch modality sample has 16 features, thus an UNROLL factor equals to 4 is used. This means that the distance between each 4 features is calculated in a single time interval as shown in Figure 6 3) Function Inline: The inlined function is treated as a part of the calling function that is calling it rather than a separate entity. This optimization is applied for the distance calculation function. Thus, whenever the classification function is called, the distance calculation is executed within it and it no longer appears as a separate level of hierarchy in the RTL design. Thus improving the overall latency of the classification task.

V. IMPLEMENTATION RESULTS AND ASSESSMENT

The performance and quality of the proposed exact and approximate implementations are assessed on the touch modality classification problem mentioned in section IV. The assessment involves three case studies: (1) Proposed Exact kNN versus approximate kNN, (2) Exact kNN on FPGA versus GPU, and (3) Exact kNN versus similar works. For cases (1) and (3), the time latency T is calculated according to the equation:

T = N × 1/f max ( 3
)
where N is the number of clock cycles obtained in postimplementation reports and f max is the maximum operating frequency the design can achieve. The Joule per classification energy E is calculated as:

E = T × P ( 4
)
where T is the time latency and P is the dynamic power consumed by the programmable logic (PL) of the Zynqberry reported by Vivado i.e the power consumed by the simulated kNN architecture to compute a classification of an input sample (excluding the static power of the processing system (PS) as it is device dependent).

For case (2), Exact kNN architecture has been coded using Python language running inside the CUDA computing platform. The GPU power estimation was obtained using NVIDIA System Managment Interface (NVSMI). The latter is a command utility that can be issued on any Python development environment with the CUDA libraries imported [34].

Case 1: Exact versus Approximate kNN The implementation results on Zynqberry of the proposed Exact and Approximate kNN are shown in Table II. Exact kNN occupies 12% of the hardware resources, consumes 0.236 W, and classifies an input sample within 25.7 µs. The obtained time latency verifies the real-time classification of a touch modality in less than 400 ms [35]. Applying downsampling and downscaling have decreased the input size from 4 × 4 × 30, 00 (a 10s sample) to 4 × 4 × 1 (a 3.5s sample) offering a 65% reduction in data size. Such reduction led to a significant decrease in the hardware resources and time latency. Using the 24-bit fixed-point representation instead of 32-bit floating-point one provides a 25% reduction in the word length of data exchanged between the different blocks of the kNN architecture and the complexity of the arithmetic computations. Consequently, the dynamic power consumption has been reduced. Thus, the proposed approximate kNN offers an average hardware resource reduction up to 56.4%, by accelerating the classification of a test sample by 2.3× with an energy reduction of about 69% compared to the proposed Exact kNN. For the whole design, an accuracy degradation of 2.6% is reported. The proposed approximate kNN provides real-time classification of touch modalities with a reduced time latency of 11.2 µs. These results motivate the use of approximate computing techniques.

Case 2: Exact kNN on FPGA versus GPU Using the CUDA platform and NVSMI tool, the GPU implementation of Exact kNN provided a classification time of 80 ms while consuming 14.12W for the touch modality classification problem. Table III shows a comparison between the FPGA and GPU implementations in terms of execution time and energy consumption. The results are significantly in favor of the FPGA, where the acceleration of the proposed kNN architecture on FPGA could be achieved with a fraction of the energy consumed using GPUs. This can be justified due to two possible reasons:

• GPUs use DRAM for the communication between the different blocks of the kNN architecture (referred to as kernels) [36], which is slower than using a hybrid structure as proposed in Figure 2 where BRAMs are used to communicate between different blocks and DRAM is used only for dataset storage.

• The proposed kNN architecture exploits the parallelism capabilities of the FPGA. Thus, the "if-then-else" conditions are executed in parallel. On the other hand, the "then" and "else" parts are executed serially on GPUs resulting in a significant time latency increase. Such issue is known as "thread divergence" [37]. Case 3: Comparison with similar works Comparing two kNN implementations is not a straight forward task due to the large number of differences such as: the number of nearest neighbors (K), dataset size (N ), number of features per sample (f ), development environment (HLS or HDL), hardware device used, etc. To achieve a fair comparison with Exact kNN, three similar architectures have been selected. These three architectures have been chosen such that they all have:

• Used HLS for development since the comparison with an HDL implementation is not feasible.

• Achieved a high acceleration gain (i.e speedup) with respect to equivalent CPU-based kNN implementation, so the architecture resembles an efficient accelerator.

• Used similar (and different) values of K, N , and f to generalize the comparison. Table IV presents the existing implementation settings for the three architectures. Denote by S i =[K i , N i , f i , Dataset i ] the settings used in the first [14], second [15] and third implementation [21] respectively. Exact kNN is implemented using the settings S i i.e the proposed kNN architecture is implemented and validated using the testbench reported in each architecture. The implementation results are shown in Table V with the original implementation results of each architecture.

kNN-S 1 achieves a 12.3× classification speedup with 94% less energy consumption while requiring a 61% less hardware resources compared to the kNN presented in [14]. This is due to two main reasons: 1) the selector used in kNN-S 1 is an enhanced version of the one used in [14] where the division factor plays a key role in decreasing the sorting time as presented in section IV.C, and 2) the aim of the kNN architecture in [14] is to attain the highest speedup possible for real-time embedded applications. This has been accomplished by combining the UNROLL, PIPELINE, and DATAFLOW directives. Such directives are known for speedup gains due to the level of parallelism introduced at the expense of a noticeable increase in the hardware resources. The latter was not an issue when using the relatively large FPGA in the ZedBoard platform. Meanwhile, in kNN-S 1 only the UNROLL directive is used with an unrolling factor that balances the speedup and complexity for the target application, while achieving more speedup with the use of the selector.

When compared to the kNN implementation in [15], kNN-S 2 provides a huge acceleration gain of 875× with 94% less required hardware resources. Such gain is due to the design choices adopted by the authors in [15] such as: 1) using the euclidean distance metric, which compared to (1), has an added complexity due to the square root operation, 2) applying the normalization of the data on-chip, which presents a complexity overhead, and 3) performing the sorting operation using a single comparator and multiple BRAMs to compare each pair of data points, this process is very slow compared to the proposed selector. Although no power/energy details were provided for the kNN in [15], kNN-S 2 is expected to be more efficient due to the 90% reduction in the number of DSPs.

The implementation requirements of kNN-S 3 exceeds the capacity of the FPGA fabric in Zynqberry and thus the design couldn't be routed to achieve the 240MHz operating frequency. Thus, for comparison reasons only, kNN-S 3 is implemented on the target device used in [21] i.e Vertix-7 knowing that implementing kNN on Zynqberry has achieved the real-time and low power consumption demands for the target touch modality application as reported in Table II. kNN-S 3 offers a speedup of 1.4× with 41.5% and 12.3% reduction in hardware resources and energy per classification respectively. Such results are justified with the lower number of FF and LUTs required by kNN-S 3 . This is expected since the kNN in [21] uses the Bitonic sorter, which is outperformed by the proposed selector as shown in Table I. Compared to kNN-S 1 and kNN-S 2 , the gain achieved by kNN-S 3 is relatively lower since the kNN in [21] exploits the high optimization capabilities of OpenCL for extensive computations and large datasets.

VI. CONCLUSION

This paper introduces an efficient novel architecture for the hardware acceleration of the k-Nearest Neighbor algorithm using a selection-based sorter. The architecture has been coded in HLS, synthesized, and routed on the Zynqberry platform. Two efficient implementations were provided based on exact and approximate computing. The implementations exploit the parallelism nature of the kNN algorithm along with the use of ACTs to achieve real-time classification with relatively low power consumption. Compared to similar state-of-the-art solutions, the proposed Exact kNN offers acceleration gain between 1.4× and 875× with lower energy per classification between 41% and 94% depending on the used settings. Compared to GPU-based implementations, the proposed kNN-FPGA implementation offers efficient and faster classification for the target application. Such results pave the way towards embedding intelligence using a small-sized platform such as the Zynqberry for applications with low power and real- Tensor based learning techniques permit the effective exploitation of the structure of data used in various fields such as vision (e.g. image recognition), neuroscience (e.g. MRI data), chemistry (excitation-emission data), etc. At the beginning of the last decade, ML communities started showing interest in tensors and their use for supervised learning [START_REF] Tao | Supervised tensor learning[END_REF]. Authors in [START_REF] Signoretto | A kernel-based framework to tensorial data analysis[END_REF] proposed a tensorial kernel that could be used for supervised tensor-based learning models while utilizing the structural information embodied in the data and exploiting the algebraic properties of tensors of any order. Such kernel methods lead to flexible nonlinear models that have been proven successful in many different contexts. When used with SVM algorithm, the tensorial kernel achieved better classification accuracy than the Gaussian-Radial Basis Function and linear kernels in an image recognition task.

Gastaldo et. al have extended the tensorial kernel approach for tactile data processing in [START_REF] Gastaldo | A Tensor-Based Pattern-Recognition Framework for the Interpretation of Touch Modality in Artificial Skin Systems[END_REF]. This approach has been adopted for a touch modality classification problem since it preserves the inherent tensorial structure of the data collected by tactile sensors. As an end result, the tensorial-based SVM has achieved higher accuracy in classifying touch modalities compared to the Regularized Least Square algorithm. In [START_REF] Ibrahim | Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing[END_REF], the first FPGA implementation of the SVM algorithm based on tensorial kernel has been presented. Specifically, two implementations were provided: Cascaded and Parallel. The former failed to ensure real-time classification of touch (i.e in less than 400ms [START_REF] Lele | The reaction time to touch[END_REF]), and the latter reported a relatively large hardware area and high power consumption of 1.14W. Such results were not acceptable for applications with limited power budget and area constraints [START_REF] Fares | Distributed Sensing and Stimulation Systems for Sense of Touch Restoration in Prosthetics[END_REF].

In this research work, we present a new architecture and hardware implementation of the TSVM aiming at reducing the hardware complexity and power consumption while keeping real-time operation. The architecture is characterized by the introduction of a Shallow Neural Network for the SVD computations. The proposed neural network architecture achieves 324× speedup with 58% and 67% reductions in the required hardware resources and power consumption respectively compared to the traditional one-sided Jacobi algorithm. Such reductions demonstrate the feasibility of the implemented TSVM for real-time tactile data classification while consuming 6.28 mJ. The proposed TSVM architecture achieves 131× classification speedup with a 39% and 50% resources and power reductions respectively compared to similar stat-of-the-art solution [START_REF] Ibrahim | Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing[END_REF]. Furthermore, a scalability assessment of the proposed TSVM architecture is provided. The assessment shows that replacing the onesided Jacobi with a neural network demands only 1% increase in the required flip flops compared to 29% when the number of training tensors is doubled. This research work has been published in the proceeding of the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) [START_REF] Younes | Efficient FPGA implementation of approximate singular value decomposition based on shallow neural networks[END_REF] and then extended in IEEE Transactions on Circuits and Systems I: Regular Papers [187].

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR

I. INTRODUCTION

T ENSOR based learning techniques permit the effective exploitation of the structure of data used in various fields such as vision (e.g. image recognition), neuroscience (e.g. MRI data), etc. Authors in [1] proposed a tensorial kernel that could be used for supervised tensor-based learning models while utilizing the structural information embodied in the data. When used with Support Vector Machine (SVM) algorithm, the tensorial kernel leads to better classification accuracy than the Gaussian-Radial Basis Function (RBF) and linear kernels in an image recognition task. Gastaldo et. al. have extended the tensorial kernel approach for tactile data processing in [2]. This approach has been adopted since it preserves the inherent tensorial structure of the data collected by tactile sensors. As an end result, the tensorial-based SVM achieves higher accuracy in classifying touch modalities compared to the Regularized Least Square (RLS) algorithm. In [3], the first FPGA implementation of the Support Vector Machine (SVM) algorithm based on tensorial kernel has been presented. Specifically, two implementations were provided: Cascaded and Parallel. The former failed to ensure real-time classification of touch (i.e in less than 400 ms [4]), and the latter reported a relatively large hardware area and high power consumption of 1.14W. Such results were not acceptable for the application with limited power budget and area constraints [5].

In this paper, our main goal is to provide a new architecture and hardware implementation of the tensorial SVM (TSVM) aiming at reducing the hardware complexity and power consumption while keeping real-time operation. For this purpose, we analyzed the complexity of the tensorial SVM architecture to pin-out most computationally complex and demanding blocks. Fig. 1 illustrates the estimated number of operations required in each step of the tensorial SVM algorithm, where m and n are the dimensions of the unfolded matrix, N c , N t , and N sv are the number of classes to be discriminated, the number of training tensors, and the number of support vectors, respectively. In [3], the one-sided Jacobi algorithm has been adopted for finding the singular vectors. Such algorithm involves a high number of arithmetic operations and requires several iterations to converge [6]. As reported in [3] (m = 8, n = 20, N c = 2, N t = 100, etc.), the Singular Value Decomposition (SVD) computation corresponds to about 96% of the overall algorithm. Thus, the main focus of the proposed new architecture is to find an alternative algorithm for SVD computation. This alternative should impose complexity reductions without affecting the classification accuracy of the tensorial SVM.

A Neural Network (NN) is one of the candidates for the SVD computation. The idea first surfaced in 1991 when Samardzija et. al. proposed an artificial continuous-time neural network to estimate the eigenvectors and eigenvalues [7]. In [8], the convergence and computational complexity through computer simulations of such network are assessed. Another neural network has been presented in [9]. The network is characterized by an order n-Ordinary Differential Equations (ODEs) leading to reduced dimensionality. Such neural network has evolved to further applications such as Principle Component Analysis (PCA) [10].

Triggered by the performance of neural networks in many domains [11] and the continuous quest for efficient designs specifically for resource-limited applications [12], a neural network based tensorial SVM architecture is proposed. The main contributions of this paper are summarized as follows:

• It presents a novel architecture for SVD computation using shallow neural networks. The architecture achieves 324× speedup with 58% and 67% reductions in the required hardware resources and power consumption respectively compared to the traditional one-sided Jacobi algorithm. Such reductions are obtained while providing a comparable performance in terms of Mean Squared Error (MSE) and Cosine Similarity (CS) metrics. Moreover, the proposed architecture is adequate for implementations on resource-limited platforms (e.g. Zynqberry [13]). • It presents the first hardware architecture and implementation of SVM algorithm featuring multidimensional tensorial inputs, where shallow neural networks are employed to compute the singular value decomposition. • It demonstrates the feasibility of the implemented system for real-time touch modality classification while consuming 6.28 mJ. The proposed cascade architecture achieves 131× classification speedup with a 39% and 50% resources and power reductions respectively compared to similar stat-of-the-art solution [3].

• It provides scalability assessment of the proposed SVD architecture. Replacing the one-sided Jacobi with a neural network in the tensorial SVM architecture reported only 1% increase in the required FFs compared to 29% when the number of training tensors is doubled. The rest of the paper is organized as follows: Section II presents an overview of the tensorial SVM for touch modality classification. Section III provides a review on the efficient existing SVD algorithms and their hardware implementations. It also reports the complexity of the proposed architecture compared to existing solutions. Section IV details the process of designing a neural network for SVD and its performance when tested on a tactile dataset. Section V provides the FPGA implementation and verification of the tensorial SVM based on SVD computation via shallow neural networks. Section VI presents a scalability study of the proposed architecture in terms of hardware resources and time latency. Section VII concludes the paper and illustrates some observations.

II. SVM CLASSIFICATION BASED ON TENSORIAL KERNEL

A. Overview

A theoretical approach that extends kernel methods to tensor data has been presented in [14]. The framework allows the classification of an input tensor using SVM in 4 main steps:

• Tensor Unfolding: A tensor φ(

I 1 × I 2 × I 3 ) is transformed into three matrices X 1 (I 1 × I 2 I 3 ), X 2 (I 2 × I 1 I 3 ) and X 3 (I 3 × I 1 I 2 ).
• SVD Computation: The unfolded matrices are symmetrized into square matrices that can be written in the form:

X 1 = U SV T (1)
where U and V T contain the left and right singular vectors respectively, and S is the diagonal matrix storing the singular values σ i of X 1 .

• Kernel Computation: The tensorial kernel extended from the Gaussian kernel is computed using the function:

K (x, y) = z 1 k z (x, y) (2)
where k z is the kernel factor defined as:

k(x, y) = exp( -1 2σ 2 (I n -trace(Z T Z ))) (3)
where Z = V T x V y , V x and V y represent the singular vectors of the unfolded matrix obtained during the inference and training phase respectively, and trace represents the sum of diagonal elements.

• Classification: Applying the SVM classification function expressed as:

ŷ = f SV M (x) = n i β i K (x i , x) + b ( 4
)
where ŷ is the predicted label of input tensor x, n is the number of training tensors, β i are the coefficients obtained during training, and b is the bias.

B. Touch Modalities Classification

The tensorial SVM has been initially presented as an effective algorithm for touch modality classification in [14]. In this paper, three binary and one multi-class classification problems are used to test the accuracy of the proposed neural network based tensorial SVM. Specifically, the problems are:

• Problem A: "brushing a paintbrush" versus "rolling a washer" • Problem B: "brushing a paintbrush" versus "sliding the finger" • Problem C: "sliding the finger" versus "rolling a washer" • Problem D: "one versus the others" where 20 is the obtained number of samples using the data pre-processing algorithm (Algorithm 1) reported in section IV.

III. SVD ALGORITHMS AND IMPLEMENTATIONS

A. Literature Review

Singular value decomposition can be computed numerically through several methods such as the Jacobi method, the QR method, and the one-sided Hestenes method [15]. For parallel implementations, computing the SVD using the Jacobi method is superior to other methods in terms of complexity and execution time [15]. Brent et. al. have shown that two-dimensional systolic array could be used for implementing the Jacobi method [16]. In [17], the authors have presented various realization for the Jacobi SVD computation using Coordinate Rotation Digital Computer (CORDIC) [18]. The latter is adopted in majority of the existing hardware implementations of the Jacobi SVD method. For small matrix dimensions, an efficient implementation of SVD for the use in Multiple Input Multiple Output (MIMO) precoding and real-time signal processing has been presented in [19]. The implementation is based on CORDIC processors. For an arbitrary m × n matrix, Ibrahim et. al. have presented an FPGA implementation with fixed-point arithmetic [20]. The implementation managed to compute the SVD of an 32 × 127 matrix in 13 ms while occupying 20% and 67% slice registers and LUTs respectively on a Virtex-6 FPGA. Fast and efficient FPGA implementation for computing the singular and eigen value decomposition based on a simplified CORDIC-like algorithm is presented in [21]. The implementation uses fixed-point arithmetic for sequential and parallel operations leading about 3× faster computation in an image denoising application compared to computations via an Intel CPU based PC. The authors in [22] used High-Level Synthesis (HLS) to model the one-sided Jacobi SVD computation on a Zedboard development board. For a 16 × 16 matrix, SVD computation takes around 1.1 seconds with a power consumption of 1.38W. Using CMOS 28-nm technology, Deng et.al proposed a hardware architecture for tensor SVD [23]. Compared with real-world CPU-based implementations, the architecture provides an average of 14× speed on various workloads.

Targeting the TSVM architecture in [3] where the one-sided Jacobi is identified as a performance bottleneck, the existing alternative implementations for SVD computation share several common challenges: (1) they operate only on square matrices. Thus, if the input matrix is rectangular, an additional complexity is added due to matrix symmetrization [23].

(2) if the implementation uses floating-point representation, the complexity is relatively high even for small matrix dimensions [24], and (3) depending on the required output precision, the algorithm might require additional iterations to converge [6]. Recently, a scalable SVD engine on FPGA has been introduced in [25] targeting these challenges. The proposed engine managed to compute the SVD of rectangular matrices using floating-point arithmetic. However, the implementation results show that a large number of DSPs is required for several matrix dimensions which has a direct impact on the power consumption of hardware implementations. Another noticeable observation is that the authors compared the SVD engine only to CPU-based SVD computations. In this paper, a new architecture for SVD computation based on shallow neural networks is proposed. The architecture offers the ability to operate on rectangular matrices (thus symmetrization is not needed, see Fig. 2) and utilizes floating-point arithmetic. As for convergence, the neural network training is usually performed offline on a high-end computing device. Thus, a network could be trained several times for any given amount of time to achieve top notch performance.

B. Computational Complexity

In this section, we compare the complexity of the one-sided Jacobi algorithm with that of a shallow neural network in terms of the total number of operations. Consider a shallow neural network of one hidden layer of size H and an output layer of size O. For an input A m×n , the outputs of the hidden layer Y h and the output layer Y O are expressed respectively as:

Y h = f h (W h .A + b h ) (5) Y O = f O (W O .Y h + b O ) (6)
where W , b, and f represent the weight, bias, and activation function respectively. The output of each layer consists of matrix multiplication, addition, and activation operations. The number of operations for matrix multiplication and addition is expressed as:

N h = H (2m × n -1) + H = 2H (m × n) (7)
Assuming that the activation function requires N Act operations, the total number of operations in the hidden layers is expressed as:

N h = 2H (m × n) + N Act h ( 8
)
The same can be applied to the output layer, thus the number of required operations is: Finally, the number of operations for the whole network could be expressed as: (10) To estimate N, suppose there exists an upper bound T such that N ≤ T . T is an upper bound when both N Act h and N Act O correspond to the most complex activation function i.e. the tangent hyperbolic function (tanh). The latter is expressed as:

N O = 2H × O + N Act O ( 9
N = N h + N O = 2H (m × n + O) + N Act h + N Act O
f (z) = e z -e -z e z + e -z (11)
To find the number of operations required for the term e z , we referred to the function implementation in the IEEE-754 library in [26]. The implementation uses the Taylor expansion with an order 3 for floating-points, leading to a total of 16 operations. Thus the number of operations N Act h = 35H . Similarly, N Act O = 35O. For the network to output the right singular vectors V of an m × n matrix, the output layer size O is equal to n 2 . This simplifies (10) to:

N <= (2H × n)(m + n) + 35H + 35n 2 (12)
Knowing that the number of operations for the one-sided Jacobi algorithm is (see Fig. 1):

N j = 24m(n -1)[n 2 (2n -1) + n 3 + 6] (13)
through simulations, the values of m, n, and H are varied to compare ( 12) and ( 13). Fig. 3 plots the number of operations N j and N required to compute the SVD of a matrix using one-sided Jacobi and a shallow neural network respectively. Generally, the comparison results are in favor of the neural network approach as shown in Fig. 3. The one-sided Jacobi is superior for very small dimensions such as 2 × 2 for H > 21. As the dimension starts to increase, the neural network requires significantly less number of operations for SVD computations. For instance, for (m, n) = (20, 16) and (m, n) = (4, 80) (these dimensions are often used for tensorial SVD implementations based on the one-sided Jacobi algorithm [3], [27]), computing the right singular vectors V using a shallow neural network requires less number of operations than using the one-sided Jacobi (N < N j) for all values of H ≤ 70, 000 and H ≤ 800, 000 respectively. Such values of H are very large even for the largest existing neural networks. The number of operations (N) required for each activation function is presented in Table I. The hidden layer activation function could be ReLU (Standard, LeakyReLU or Parametric), Sigmoid, or hyperbolic tangent (tanh), it is selected based on the trade-off between complexity and the required performance. In the output layer, only the hyperbolic tangent function can be used, due to the fact that the values of the singular vectors are bounded between -1 and 1.

IV. SVD USING NEURAL NETWORKS

A. Network Structure

A regression model is targeted since the NN is needed to compute the singular vectors. For that, there are two possible categories to work on: (1) Classification NN that should be modified to perform regression and re-trained [28] and (2) Regression NNs [29]. Although the classification accuracy achieved by the one-sided Jacobi TSVM could be obtained by an existing NN model from the two above mentioned categories, the main concern remains in the computational Even the smallest models such as MobileNet [30], Shuffle Net [31], and EffNet [32] contains at least four layers. On the other hand, for the regression NNs, with only one hidden layer, a shallow network is considered to be the smallest possible regression NN model.

A tactile tensor φ(4×4×20) is unfolded into three matrices M(4 × 80), N(4 × 80), and P(20 × 16). According to (1) each matrix could be decomposed into:

M 4×80 = U 4×80 × 80×80 × V T 80×80 (14) N 4×80 = U 4×80 × 80×80 × V T 80×80 ( 15
)
P 20×16 = U 20×16 × 16×16 × V T 16×16 (16)
Authors in [14] and [33] reported that for tensor SVD, only a small number of the columns of V is required to obtain acceptable classification accuracy when embedded in SVM. Using the three touch modality problems reported in section II.B, the V matrices that resulted in the highest classification accuracy are: V T 80×4 , V T 80×4 , and V T 16×2 . Fig. 4(a) shows the proposed shallow neural network that is capable of computing the right singular vectors V . The network is composed of three fully connected layers: an input layer of size m × n, a hidden layer of size H , and an output layer of size O = n × t, where t is the selected number of columns from V . Thus, two neural networks are designed. one with an 80 × 4 output and the other with a 16 × 2 output.

The neural networks share two activation functions ( f h ) and ( f O ) defined as:

f h (z i ) = z i z i ≥ 0 βz i other wise (17) f O (z) = ⎧ ⎪ ⎨ ⎪ ⎩ -1 z < -1 1 z > 1 z otherwise (18)
The function f h shown in Fig. 4(c) is called Parametric Rectified Linear Unit (PReLU) where z i is just one feature out of the feature vector z and β is a learnable weight used to keep negative values compared to the standard ReLU function. It is adopted for the hidden layer to preserve the sign of the neurons' output with low computational complexity compared to other activation functions (e.g. Sigmoid function). The function f O shown in Fig. 4(e) is called hard hyperbolic tangent activation function [34]. It is used at the output layer to output the elements v i of the V matrix in the range [-1, 1] with a reduced computational complexity compared to the hyperbolic tangent function.

B. Network Training and Tuning

The chosen network model is trained using floating-point representation during both forward and backward propagation. The network is trained to export the right singular vectors V with the least possible error margin compared to exact computations obtained via MATLAB. The proposed network is a regression model that outputs singular vectors, for that the performance is determined based on two metrics: (1) Mean Squared Error (MSE) and (2) Cosine Similarity (CS). These metrics are defined as:

M SE = 1 n n i=1 (V i -Vi ) 2 (19) C S = 1 n n i=1 ( V i . Vi ||V i || × || Vi || ) ( 20
)
where V is the matrix generated from the neural network and V is the one generated from applying the SVD using MATLAB software. Thus, the training aims at finding a network model that achieves the lowest MSE (i.e. the elements v i of the V and V matrices have similar values) and highest C S (i.e. the vectors V i of the V and V matrices have similar direction i.e C S tends to 1). The proposed neural network is hand crafted and can be customized. The training process is used to tune the network hyperparameters [35] i.e. parameters that determines the network structure and training behavior (e.g. size of hidden layer H , learning rate) and parameters (e.g. weights). During training, the weights and biases of the network are randomly initialized, then updated using one of the below optimizers. As for the hyperparameters, the following settings have been tested:

• The tactile dataset from [14] is used for training. However, some modifications have been applied based on the following:

• Some participants recordings are noisy (see Fig. 5(a)), thus their corresponding data has been removed from the training dataset. • Since no particular indications were given to the participants in [14] about the pressure level, silent intervals (i.e. voltage readings from sensor taxels equals to zero, see Fig. 5(b)) are observed in the recordings. These silent intervals will not help the neural network to learn new patterns and thus are removed. Specifically, all reading outside the timing interval [3.5, 7] are omitted. Algorithm 1 summarizes the pre-processing technique applied to the dataset. The algorithm truncates each modality from 10s to 3.5s resulting in a tensor T (4 × 4 × 10, 500). Afterwards, subsampling is applied to obtain 20 readings (P = 20) from the 10,500 resulting in a final tensor φ(4 ×4 ×20). After pre-processing, 4480 matrices of dimensions 4 × 80 and 20 × 16 have been derived. Then, their corresponding V matrices are generated using MATLAB. These matrices are divided into 80% for training, 10% for validation, and 10% for testing.

C. Network Performance

The neural network is coded in Python using Tensorflow and Keras libraries. Then, it is trained on an ASUS PC equipped with an NVIDIA GTX 1650 graphics card with 4GB VRAM.

TABLE II

BEST MODEL PERFORMANCE COMPARED TO ONE-SIDED JACOBI Fig. 6 shows the MSE and CS while testing the proposed network under different activation functions. Although using the hyperbolic tangent function leads to a model with the lowest MSE and highest CS, it imposes the highest computational complexity as reported in Table I. Hence, PReLU activation function has been adopted for the hidden layer as a trade-off between complexity and MSE/CS. Fig. 7 shows the MSE and CS of the model with best achieved performance. The latter is obtained using the characteristics presented in Table II. One noticeable observation is that the size of the hidden layer differs for the two input dimensions. This is due to the fact that the network has to output 320 elements (80 × 4) for the input dimension (4 × 80) The obtained performance is compared to that of computing the SVD using the one-sided Jacobi algorithm based on the architecture presented in [20]. According to the comparison shown in Table III, the proposed neural network is capable of computing the right singular vectors V while: (1) providing low MSE and high CS during training, validation, and testing, and (2) achieving comparable performance in terms of MSE and CS to the exact computation using the one-sided Jacobi. This is evident for both input dimensions 4 × 80 and 20 × 16.

V. HARDWARE IMPLEMENTATION AND VERIFICATION

This section presents the architecture and implementation details of the two shallow neural networks and the overall tensorial SVM. The latter is characterized by adopting these networks for SVD computation. The input, weights, and biases are represented in 32-bit floating point. Each hardware architecture has been coded in C++, synthesized and implemented using Vivado/Vivado HLS 2020.1 targeting Virtex-7 FPGA device operating at 100 MHz. To test and validate the hardware implementation, a C++/RTL co-simulation is performed in Vivado HLS to compare the results between the C++ simulation and the RTL implementation. Afterwards, the RTL implementation has been exported as an Intellectual Property (IP) to Vivado where the hardware resources and number of clock cycles are recorded. The time latency is computed as:

T = cc × 1/ f max ( 21
)
where cc is the number of clock cycles in post-implementation timing simulation and f max is the maximum operating frequency. As for power consumption, a post implementation functional and timing behavioral simulation is performed to generate a Switching Activity Interchange File (SAIF). This file is used to obtain a vector-based power estimation post-routing.

For the rest of the paper, let NN1 and NN2 denote the neural networks with input dimensions 4 × 80 and 20 × 16 respectively.

A. FPGA Implementation of the Shallow Neural Network

Fig. 8 shows the architecture of the proposed shallow neural network. For an input X of size L (one of the unfolded matrices), it outputs the V matrix using sequential operations. The outputs Y h and Y O corresponds to the equations ( 5) and ( 6), where f h and f O are the PReLU and the hard tangent hyperbolic activation functions respectively. The input X and the weights are stored on-chip using BRAMs and the multiplier is fed from the BRAM to perform elementby-element multiplication of the input and weight values. Similarly, the multiplication result is fed to the adder and the bias values are read from on-chip BRAMs. The right singular vectors matrix V is obtained by transforming the output vector Y O into a 2D array as shown in Fig. 9. The advantage of such architecture is that it allows the use of network pruning without any loss in performance (MSE/CS). The weight and bias matrices obtained from the offline training phase have been analyzed to identify neurons with very low weight/bias values. These neurons could be removed without affecting the network performance during inference. Thus, pruning is applied on matrix multiplication/addition by skipping operations where W

[i ], b[i ] ≤ 10 -4 .
Table IV shows the implementation details for the SVD computation on a 4 × 4 × 20 input tensor (i.e. NN1 is utilized twice to compute the SVD of the matrices M, N while NN2 is utilized once to compute the SVD of the matrix P) compared to the one-sided Jacobi based on the architecture presented in [3]. The obtained results show that using neural networks for SVD computations allows for a 324× speedup with an average resources and power reductions of 58% and 67% respectively. Another observation is that the neural network architecture uses slightly more BRAMs. This is due to the fact IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS Fig. 8. Shallow Neural Network Architecture.

TABLE IV IMPLEMENTATION RESULTS FOR TENSOR SVD COMPUTATIONS

that the weights and biases matrices obtained from network training are mapped into BRAMs and are not saved on an external memory. Knowing that the Virtex-7 FPGA is used for implementation to have a credible comparison with the state-of-the-art, the obtained results show that the proposed neural network for SVD computations is adequate to fit in a resource-limited platform such as the Zynqberry. This is not possible for the implementation of the one-sided Jacobi targeting large matrix dimensions.

B. FPGA Implementation of the Neural Network Based SVM

The neural networks NN1 and NN2 have been embedded into the cascade architecture of the tensorial SVM presented in [3]. The new NN-based TSVM architecture is presented in Fig. 10. The "NN Memory" contains the weights and biases matrices of the designed neural networks. The "SVM Memory" contains the singular vector training matrices. k 1 , k 2 , and k 3 are the three kernel factors obtained using (3). The architecture performs the SVD computation of the three unfolded matrices using the proposed NN1 and NN2 neural networks. Table V shows the different operating modes in the cascade architecture. For S 0 S 1 = 00, the first unfolded matrix X 1 is selected and NN1 is activated, then for S 0 S 1 = 01, the second unfolded matrix X 2 is selected and NN1 is utilized. As for S 0 S 1 = 10, the third unfolded matrix X 3 is selected and NN2 is activated. When active, each network computes the right singular vector matrix V of each of the unfolded input matrices. The obtained V matrices along with the ones exported from the training phase are used to compute the kernel factors as depicted in (3), which are required to output a classification decision as shown in (4). and N c = 2. The energy per classification is computed as E = P × T where P is the dynamic power consumption and T is the time latency. The NN-based TSVM and Jacobi-based TSVM recorded 0.9 W and 1.8 W respectively. Results show that replacing the one-sided Jacobi algorithm with a shallow neural network in the architecture of the TSVM leads to faster classification time up to 131×. The NN-based TSVM also requires 39% less average hardware resources with 50% reduced power consumption. This leads 2) achieves real-time classification using cascaded architecture, which was not possible using the Jacobi-based TSVM as reported in [3]. The latter has been the main reason for using the parallel architecture which has led to high power consumption, (3) offers the reductions in resources and energy per classification at the expense of increased memory requirements to store the weights and biases matrices compared to Jacobi-based TSVM.

C. Performance Verification

The NN-based TSVM implementation is verified using the four classification problems mentioned in Section II.B. Table VII presents the classification accuracy achieved by the proposed NN-TSVM in comparison with existing methods targeting the same touch modality classification. The classification accuracy of different methods is tested using a dataset with 30 samples. Using neural networks to compute the right singular vectors V provides approximate values compared to the exact one-sided Jacobi. However, this resulted in acceptable classification accuracy with only 3% loss in the worst case. This is evident in the comparable MSE/CS of both architectures as presented in Table III.

Compared to other methods, for binary classification (A, B, and C), the proposed NN-TSVM shows a worst case of 6% loss compared to RLS for Problem B and a 5% better accuracy for Problem C, and 9.6% loss compared to kNN for Problem C while providing up to 20% accuracy increase in Problems A and B. Problem C has been identified as very challenging for TSVM in [14], it has been solved in [37] using k-Nearest Neighbor (kNN). For multiclass classification (Problem D), NN-TSVM achieves an accuracy comparable to Jacobi-TSVM and RLS, with a 7% worst case loss compared to Deep Convolutional Neural Network (DCNN) and TSVN with Ideal Regularized Composite kernel (TSVM-IRCK).

VI. SCALABILITY OF NEURAL NETWORK BASED TSVM

In order to quantify the scalability of the NN-based TSVM hardware complexity (resources and time latency), two cases are assessed: (1) Scalability of the shallow neural network, and (2) Scalability of the NN-based TSVM. The former is studied by varying the hidden/output layer size and tuning the network to achieve the same MSE/CS reported in Table III. The latter is performed by increasing the number of training tensors while maintaining the overall classification accuracy of the NN-based TSVM as reported in Table VII.

A. Case 1

The scalability of the neural network depends on the size of each layer and the activation function in use. Through Fig. 3, an insight about the number of operations with respect to the dimensions (i.e. m, n, and H ) could be learned for a certain application. To assess the scalability of the proposed NN architecture, the hidden and output layer sizes are varied. L is chosen so that the network maintains the same MSE/CS reported in Table III. O is derived from the dimension of the V matrix of the unfolded matrices obtained from the input tensor 4 × 4 × 20. We designed and implemented two more neural networks that compute the right singular vectors V without truncation i.e. output layer size O = n × n instead of O = n × t. Fig. 11 presents the hardware resources and the time latency with respect to hidden and output layer sizes for This is due to the longer operations required to perform matrix multiplication/addition. However, according to the comparison in Section III.B, this is faster than using the one-sided Jacobi as long as H ≤ 70, 000 (H ≤ 800, 000) for 20 × 16 (4 × 80) matrices. The presented scalability assessment supports the use of these networks for SVD computations as an efficient solution especially for large matrix dimensions. Hence, the proposed idea could be extended into other applications via a two-stage approach as shown in Fig. 12: • Stage 1: Unfold all the tensors φ i in a dataset into 3 matrices. Then, find the V matrix for each of the unfolded matrices using MATLAB or other software. For the majority of the applications, a tensor has the same first two dimensions (e.g. image, touch modality) hence, two of the generated matrices will have the same dimension hence can be grouped in a subset A. The remaining matrix and its corresponding V matrix will be added to a subset B. • Stage 2: For each of the subsets, a shallow neural network is to be designed. Start with random hyperparameters for the initial model, then tune it using the generated subset to reach the required MSE and CS. Once, the best model is found, the weights and biases matrices could be exported and used by the architecture in Fig. 8.

For complexity tuning, one could modify the pruning rule while preserving the required performance metric imposed by the application.

B. Case 2

To study the scalability of the proposed NN-based TSVM, the number of training tensors has been varied between 200 and 900 and the implementation requirements are recorded once the NN-based TSVM recorded a comparable accuracy to the one presented in Table VII. According to the results obtained in Fig. 13: • The required hardware resources (FFs, LUTs, BRAMs) are slightly increased with the increase of the number of training tensors. In case of BRAMs, a steeper slope is real-time classification. The latter is assured using the proposed cascaded architecture for all of training tensors sizes.

The importance of the presented work lies in the ability to scale such architecture for processing larger number of samples while respecting the constraints of the application. When scaled up, the designed NN-TSVM could enable intelligence on smaller platforms (e.g. Zynqberry) if two issues are tackled. The first issue is reducing the number of DSPs: this could be achieved by using some approximate computing techniques [42] or using LUTs-only custom core for matrix operations. The second issue is reducing the number of BRAMs: this could be achieved by further pruning of the weight/bias matrices as long as the application performance is not highly affected. Another method is to offload these matrices completely to external DRAM. This imposes additional timing overhead. However, authors in [43] have presented a strategy to overcome such design challenge.

VII. CONCLUSION

This paper introduced a shallow neural network architecture for the SVD computation of tensorial inputs. The architecture achieves comparable performance to the stateof-art solutions while imposing significant reductions in the implementation requirements. Once embedded in the SVM architecture, the NN-based TSVM is capable of delivering faster touch modality classification time up to 131× using a cascade architecture. The latter is characterized by a 39% and 88% decrease in the resources and energy per classification respectively compared to the architecture presented in [3] targeting the same application. Moreover, the proposed NN-based SVM obeys the constraints imposed by the tactile data processing application e.g. small size, real-time response, and low power consumption. The encouraging scalability results present the first effective trial for designing an efficient embedded processing unit for an e-skin. A unit that is capable of delivering real-time performance with relatively acceptable power consumption without the need for high performance platform or multi-core devices.

A hybrid precision architecture for an efficient binary convolutional neural network accelerator

Convolutional neural networks are a promising solution in many application domains such as Internet of Things (IoT), image processing, tactile processing, etc. However, the computational complexity and memory requirements are the main challenge in the deployment of CNNs on resource-limited devices for energy-constrained applications [START_REF] Alippi | Moving Convolutional Neural Networks to Embedded Systems: The AlexNet and VGG-16 Case[END_REF]. For instance, the VGG-16 network contains about 140 million 32-bit floating-point parameters and implements 1.6 × 10 10 arithmetic operations [START_REF] Qin | Binary neural networks: A survey[END_REF]. There have been numerous efforts on the complexity reduction of CNNs such as network pruning [START_REF] He | Channel Pruning for Accelerating Very Deep Neural Networks[END_REF], knowledge distillation [START_REF] Yim | A Gift from Knowledge Distillation: Fast Optimization, Network Minimization and Transfer Learning[END_REF], and weight quantization [START_REF] Gong | Compressing Deep Convolutional Networks using Vector Quantization[END_REF].

Quantization of CNNs may cause an information loss especially if it is applied to the extreme using 1-bit representation i.e. binarization. To address this issue, a variety of methods have been proposed in recent years [START_REF] Qin | Binary neural networks: A survey[END_REF]. These methods aim to: 1) minimize the quantization error, for instance by only quantizing the weights, 2) improve the network loss function to adapt to the binary values propagating through the network, and 3) reduce the gradient error by the adjustment of the Back Propagation (BP) training algorithm to adapt with binarization functions. Among these methods, minimizing the quantization error is the most used technique since it leads to relevant memory saving and complexity reductions [START_REF] Qin | Binary neural networks: A survey[END_REF][START_REF] Gong | Compressing Deep Convolutional Networks using Vector Quantization[END_REF][START_REF] Fischer | BinArray: A Scalable Hardware Accelerator for Binary Approximated CNNs[END_REF].

In this research work, a new architecture based on hybrid precision representation is proposed as a trade-off between the reliability of CNNs and the low complexity of Binary Convolution Neural Networks (BCNN). The architecture adopts binarization of hidden layers and 32-bit floating-point for the first and last layer with binary weights. A design methodology is provided on how to select the network topology, placement of binarization layers, and training process. The network is designed and trained using Larq framework [START_REF] Geiger | Larq: An Open-Source Library for Training Binarized Neural Networks[END_REF], which is an extension of Tensor-Flow that offers a library to design, train, and deploy quantized/binarized CNNs. The proposed hybrid-precision binary weight network (H-BWN) achieved more than 35% accuracy increase in classifying touch modalities compared to traditional BCNN topology. The H-BWN requires less than 5 KB of storage requirements achieving an efficient architecture that fits in a wide range of microcontrollers (e.g. STM32F0x2). When implemented on Zynq-7010 platform, the H-BWN accelerator provided a real-time classification within 0.8 ms with a 42.4 µJ energy per classification. Compared to exiting solutions, H-BWN achieved higher classification accuracy with an energy reduction up to 99% accompanied with a speedup up to 6875×. This research work has been published in the proceeding of the IEEE International Conference on Ph.D Research in Microelectronics and Electronics (PRIME) [START_REF] Younes | A mixed-precision binary neural network architecture for touch modality classification[END_REF] and the proceeding of the IEEE International Conference on Electronics, Circuits and Systems (ICECS) [196].

Perspectives

The deployment of machine learning algorithms on embedded devices for applications with a constrained requirements is an active challenge. In this work,two of the main methods that are widely used to reduce the obstacles faced while overcoming such challenge have been investigated. The first method is the use of approximate computing to reduce the computational complexity of ML algorithms with an acceptable margin of error. The second method is to design custom hardware accelerator architectures optimized for a certain algorithm implemented on a specific hardware platform.

With the continuous adoption of machine learning algorithms in different domains, future work in this research area involves tracking the advancements of such algorithms especially deep learning. For instance, Transformers have been lately investigated for the use of image classification [START_REF] Vaswani | Attention Is All You Need[END_REF][START_REF] Dosovitskiy | An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale[END_REF]. Which could be possibly adopted for tactile data processing due to the tensorial nature of tactile signals. Consequently, monitoring the new methodologies for the design and implementation of hardware accelerators. In addition, due to the error resilience nature of ML algorithms, new approximate computing techniques are emerging such as adaptive approximate computing [START_REF] Huang | A Hardware/Software Co-Design Methodology for Adaptive Approximate Computing in clustering and ANN Learning[END_REF] and approximate adders with Single LUT delay [START_REF] Nomani | xUAVs: Towards Efficient Approximate Computing for UAVs-Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization[END_REF].

Chapter 8

Ongoing Research Works

Preface

My ongoing research activities focus on applications in the domain of embedded computer vision (CV) and embedded artificial intelligence (AI) with great emphasis on achieving efficient implementations on embedded edge devices with reduced computational resources an power budget. This research track has been initiated during my work at the Lebanese International University and Lebanese University where I have supervised several Master theses that have tackled topics for applications of visual drone navigation, change detection and object detection. Also, I was the manager of a research project that aims to detect humans from areal images during search and rescue mission. Furthermore, I am currently involved in a research project that aims to optimize the detection and classification of marine objects using deep learning techniques on embedded edge devices. The following sections introduce my current research topic, describe the conducted work, present the achieved results and highlight the future work.

Real-Time Visual SLAM Drone Navigation in GNSS-Denied Regions

The use of unmanned aerial vehicles (UAVs) is expanding in several fields such as commerce, agriculture, scientific research, rescue missions, pollution detection, etc. Initially, UAVs have been developed to be controlled by an on-ground pilot by the means of a remote-control communication system. Currently, UAVs are drawing closer to navigate at high degrees of autonomy, where knowing the location is an essential attribute. Most UAVs exploit global navigation satellite system (GNSS) technology and inertial sensors (INS) to estimate its own geo-spatial positioning. UAVs are augmented with GNSS receivers, which benefit from the received time radio signals transmitted from satellites to calculate the location (longitude, latitude, and altitude). The location estimation based on the INS alone drifts when the GNSS signal drops-off. Hence, in order to navigate autonomously a course accurately, it is essential to ensure the well receiving of radio signals from at least four satellites simultaneously. This cannot be guaranteed when a UAV mission includes intermediate locations where GNSS signal becomes unreliable, such as urban zones, indoor environments, landscapes covered with forests, valleys surrounded by mountains, etc., or when the radio signals are mitigated by spoofing and gaming operations, which are easily performed especially for GNSS receivers operating on civilian frequencies. Many research works have been conducted to cope with GNSS failure. The technique of localizing a robot in a certain environment and mapping it at the same time is so called Simultaneous Localization and Mapping (SLAM). Several solutions have been demonstrated to apply SLAM adopting INS, ultrasonic and infrared sensors, Laser range finders [START_REF] Newman | Outdoor SLAM using visual appearance and laser ranging[END_REF], rotary encoders, inertial sensors, and GNSS. Recently, as computer vision has witnessed rapid development, SLAM methods employing cameras have been actively introduced and referred to as visual SLAM [START_REF] Taketomi | Visual slam algorithms: A survey from 2010 to 2016[END_REF]. Several works have discussed the use of visual SLAM for UAV navigation, landing, etc [START_REF] Engel | Camera-based navigation of a low-cost quadrocopter[END_REF][START_REF] Yang | Monocular vision SLAM-based UAV autonomous landing in emergencies and unknown environments[END_REF][START_REF] Lu | A survey on vision-based UAV navigation[END_REF].

This research work demonstrates the usage of image stitching method for SLAM to circumvent the limitations of available methods. Image stitching is basically used to form a single panoramic image with high resolution by merging two or more images of the same scene. Originally, image stitching has been wildly used to do the complete mapping of particular region benefiting from digital maps and satellite images. The use of image stitching for SLAM eliminates the need of selecting landmarks and extracting their features. The features of each two consecutive captured images are used to determine the flight distance and bearing angle. Matching the features is performed only between the stitched image and the two consecutive images, which are captured in the same conditions and using the same camera. This reduces the computational complexity, lessens the required memory space and delivers a solution to localize UAVs in unknown paths and cope with landmarks' modifications.

A novel method to localize UAVs in GNSS-denied regions is provided. It adopts Scale Invariant Feature Transform (SIFT) method to detect the features in the captured images. The features extracted from consecutive images are used to stitch the images. Accordingly, the bearing angle and moving distance are estimated. Figure 8.1 shows how SLAM is applied using the proposed method. . In Fig. 8.1(f), the bearing angle is shown between the green line, which represents the original heading, and the red line, which represents the current path. Note that the total required execution time to determine the coordinates is less than the flight duration. In order to check the relevancy of the proposed approach, the location in the meta-data is compared with the achieved results. The comparison shows for the illustrated example an error of 5 meters in the estimated distance and 4.6 degrees at most in the bearing angle as shown in Figure 8.2, where the red line shows the distance and angle based on the proposed method and the yellow line shows the distance and angle based on the meta-data of the frames. Note that the coordinates delivered in the meta-data are provided by a commercial GPS, which has an equivalent user error of 7 meters. This work has been initiated in the context of a Master's degree project at the Lebanese International University and has been published in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) [START_REF] Rizk | Real-time SLAM Based on image stitching for autonomous navigation of UAVs in GNSS-denied regions[END_REF]. In order to perform the experiments in the laboratory rather than real flights, a GNSS receiver emulator has been designed and implemented. The emulator has been demonstrated in the IEEE International Conference on work includes the phases of implementation and verification in terms of power consumption and performance targeting real-time scenarios. In addition, it is planned to augment the system with a light detection and ranging (LiDAR) to measure the UAV height, which should be involved in the computation during real experiments.

Marine Objects Detection Using Deep Learning on Embedded Edge Devices

In this work, we address the problem of detecting and classifying maritime objects. Marine object detection and classification are two essential tasks for many applications such as vessel identification and positioning, collision avoidance system, safe autonomous navigation, search and rescue mission, etc. Marine objects can span from stationary floating objects such as buoys to small boats and kayaks and other large vessels such as ferries, passenger ships and cargo ships. Surveillance adopting shared information from Electronic Chart Display and Information System (ECDIS) and GNSS can provide locations of marine vessels [START_REF] Schöller | Assessing deep-learning methods for object detection at sea from LWIR images[END_REF]. However, this depends on the reliability of data, which may degrade due to spoofing, jamming or even dis-activating automatic identification system (AIS). Radar-based methods can be effective to detect the presence of large vessels. Small boats and floating objects on water surface are difficult to be identified [START_REF] Schöller | Assessing deep-learning methods for object detection at sea from LWIR images[END_REF].

Visual detection of marine objects using electro-optical sensors provides a solution for detecting and classifying marine objects [START_REF] Blanke | Outlook for navigation -comparing human performance with a robotic solution[END_REF]. Classification and detection of objects using captured images have been widely used in several application domains [START_REF] Prasad | Video processing from electro-optical sensors for object detection and tracking in a maritime environment: A survey[END_REF] [START_REF] Bi | A survey of ship target feature extraction based on video surveillance[END_REF]. However, the characteristics of the scenes captured in marine environment arise additional challenges to the task of detecting objects in images or videos compared to other environments. Factors such as dynamic nature of the background, unavailability of static cues, presence of small objects at distant backgrounds and illumination effects impact the performance of commonly used image processing and computer vision approaches [START_REF] Prasad | Challenges in video based object detection in maritime scenario using computer vision[END_REF]. Tides and waves lead to a continuously dynamic background in both spatial and temporal dimensions. Also, floating objects are subjected to a lot of motion with unpredictable patterns. The illumination of marine scenes varies due to weather conditions (haze, fog, rain, bright sunlight, twilight, etc.). Speckles and glints are mainly induced by the variation of the solar incident angle on water. Furthermore, the disparity of color gamut depends on illumination conditions. Color gamut varies respectively between dark, yellow and red, blue and gray during night, sunset, daylight, and hazy conditions respectively. These factors affect the visibility of objects in marine environments and hence the detection performance. An effective technique for certain cases with specific illumination type, weather condition and water dynamicity may not suit other conditions.

Artificial intelligence techniques based on deep learning provide robust solutions to detect and locate objects. The achieved performance proves the relevance of CNNs in circumventing existing computer vision challenges. Deep learning methods, known as deep neural networks, make use of multiple hidden layers between the input and output layers to learn a hierarchy of features that are invariant to geometric transformations from raw input images. AI methods with CNNs play dominant role in classifying and locating multi objects in images and videos leading to accurate detection. One-stage detection methods have been introduced to provide real-time performance with acceptable precision and accuracy. These methods exclude the stage of pre-selecting the regions of classification and abstract post-processing techniques (refining bounding boxes, eliminating duplicates and adjusting detection scores) used in two-stage methods such as the well known region-convolutional neural network (R-CNN) [START_REF] Girshick | Rich feature hierarchies for accurate object detection and semantic segmentation[END_REF] and its enhanced versions [START_REF] Girshick | Fast R-CNN[END_REF][START_REF] Ren | Faster R-CNN: Towards real-time object detection with region proposal networks[END_REF] in order to reduce the complexity and ensure real-time detection speed.

You Only Look Once (YOLO) has been recently proposed in [START_REF] Redmon | You Only Look Once: Unified, real-time object detection[END_REF] as an efficient onestage CNN-based model that is able to detect multi objects in real-time. Published peer reviewed comparisons [START_REF] Qiao | Marine vision-based situational awareness using discriminative deep learning: A survey[END_REF][208] [START_REF] Zhang | Survey on deep learning-based marine object detection[END_REF] illustrate that YOLO outperforms two-stage detection methods and other available one-stage methods such as single shot detector (SSD). Since introduced, many versions of YOLO have been introduced such as YOLOv2 [START_REF] Redmon | YOLO9000: Better, faster, stronger[END_REF], YOLOv3 [220], YOLOv4 [START_REF] Bochkovskiy | Yolov4: Optimal speed and accuracy of object detection[END_REF] and YOLOv5. In YOLOv2 [START_REF] Redmon | YOLO9000: Better, faster, stronger[END_REF], the fully connected layers at the end have been eliminated and Darknet-19 architecture has been adopted. YOLOv3 [220] uses Darknet-53 architecture and inherits the concept of residual networks. The detections are made at 3 different scales which enables the detection of small objects. YOLOv4 and YOLOv4-tiny proposed initially in 2020 [START_REF] Bochkovskiy | Yolov4: Optimal speed and accuracy of object detection[END_REF] optimize and improve every part of YOLOv3. The main optimization is to use CSPDarknet-53 as its backbone network for extracting features. The difference between YOLOv4-tiny and YOLOv4 is that the tiny version only has two YOLO heads at the end (2 scale factor instead of 3). The experiments targeting Microsoft common object in context (COCO) dataset [222] show that YOLOv4 is faster and more accurate than real-time neural networks EfficientDet [START_REF] Tan | Efficientdet: Scalable and efficient object detection[END_REF] and RetinaNet [START_REF] Lin | Focal loss for dense object detection[END_REF] provided by Google and Facebook respectively. Comparisons have been made between YOLOv3, YOLOv4 and YOLOv5, in which some authors claim that YOLOv4 is more accurate while others claim that YOLOv5 is more accurate. The reason for different reported results can be attributed to many factors, such as the different datasets used, the modified hyperparameters, etc [START_REF] Nepal | Comparing YOLOv3, YOLOv4 and YOLOv5 for autonomous landing spot detection in faulty UAVs[END_REF].

The deployment of CNNs on embedded edge devices targeting real-time inference sets a challenge due to the limited computing resources and power budgets. Several optimization techniques such as pruning, quantization and use of light neural networks enable the realtime inference but at the cost of precision degradation. However, using efficient approaches to apply the optimization techniques at training and inference stages enables high inference speed with limited degradation of detection performance.

Accordingly, we investigate different versions of YOLO for real-time object detection and compare their performance for the specific application of detecting maritime objects. The trained YOLO networks are efficiently optimized targeting three recent edge devices: Nvidia Jetson Xavier AGX, AMD-Xilinx Kria KV260 Vision AI Kit, and Movidius Myriad X VPU. Also, we make use of emergent optimization techniques to deploy the trained networks on embedded edge devices. Figure 8.4 shows sample predictions using the trained model. This work comes in the context of ODESSA research project which gathers several researchers and engineers from Lab-STICC and two companies. The performed work and obtained results have been described in a research paper [START_REF] Heller | Marine objects detection using deep learning on embedded edge devices[END_REF] which is submitted to the IEEE International Workshop on Rapid System Prototyping (RSP), which will be held as a part of the Embedded Systems Week (ESWEEK) international conference, Shanghai in October 2022.

The main contributions of this work are:

• Create a diverse dataset of marine objects, which has the widest number of classes and annotations compared to available datasets,

• Train and evaluate several YOLO neural networks with different sizes and architecture specifications,

• Apply structured pruning using sparsifying [START_REF] Liu | Learning efficient convolutional networks through network slimming[END_REF] to reduce the network size while maintaining the detection performance,

• Optimize the trained networks towards implementation on popular edge devices to achieve the best compromise between inference speed and detection performance.

The proposed deployments demonstrate promising results with an inference speed of 90 frames per second (FPS) and a limited degradation of 2.4% in the mean average precision (mAP). The analysis of the obtained results reveals that Jetson Xavier AGX is the most powerful device among the three platforms in terms of detection performance. It achieves the highest inference speed while maintaining acceptable precision values. However, it requires more power budget. It achieves 3.23 FPS/Watt for YOLOv4-tiny and 1.46 FPS/Watt for YOLOv4.

The KRIA KV260 AI VISION KIT power consumption is 4 times less than the GPU on Jetson Xavier AGX. However, the achieved inference speed is 1.6 times and 4 times less than that achieved using the GPU for YOLOv4-tiny and YOLOv4 respectively. It is necessary to realize a graph pruning to achieve 15 FPS with only one DPU B4096@300Mhz. While considering performance per watt criterion only, the KRIA KV260 kit outperforms the other targeted devices when running YOLOv4. It achieves 1.875 FPS/Watt.

The MOVIDIUS MYRIAD X VPU suffers from a lack of computing power, yet it is enough to infer a YOLOv4-tiny at 31 FPS with a power consumption less than 5 Watts with OAK-D camera. The comparison in terms of performance per Watt shows that for YOLOv4tiny, the VPU outperforms the other two devices as it achieves 7.75 FPS/Watt. Future work will include the following steps:

• Extend the dataset in order to include new classes of marine objects and to balance the number of images among classes.

• Examine the new version of YOLO so called YOLOv7 and conduct comparisons in terms in detection performance and inference speed.

• Propose and implement an original method to switch dynamically, during run-time, between different scaled neural network models according to environment, power profile or required accuracy and precision.

Smart-Cameras Network for Multi-View AI-based Object Detection

Implementing CNNs on embedded edge devices with limited computational resources and power budget creates a challenge. Recently, several techniques have been applied such as light networks with fewer layers, pruning to reduce the number of connections, factorization to combine various aspects of the network architecture, and quantization of weight and/or activation values. These techniques ensure better deployment of CNN-based object detection methods on edge devices but at the cost of accuracy and precision drop.

The use of multiple cameras providing different angles of view for the same scene can be used to improve the detection performance leading to the reduction of the number of missing detections or false detections. On the other hand, incorporating multiple camera views for detection alleviates the impacts related to object occlusion, illumination, intra-class variation, similarity between classes, background clutter, ambiguity, etc. This work makes use of multi-views of the same scene to increase the detection accuracy. It proposes to build and implement a network of smart-cameras, where each consists of a camera connected to an embedded processing unit executing a CNN-based object detection algorithm. Each smart-camera has its own point of view. The distributed smart-cameras collaborate in order to enhance the accuracy and precision of the detection by merging the prediction results of all involved nodes. Figure 8.5 shows an overview of the proposed multiview smart-camera network. The main contributions of this work are:

• Create a novel dataset for mutli-view object detection with accurate measurements in terms of orientation and distances by acquiring images with multiple cameras for the same scenes.

• Determine the best hyperparameters of the targeted neural network and conduct training processes accordingly.

• Implement and demonstrate the network of smart cameras.

• Devise and develop an efficient strategy to collect and aggregate prediction data from the nodes of the network in order to reduce the communication overhead and power consumption.

• Propose and implement smart decision-making algorithm to provide the final detection result based on different nodes detections.

• Verify the relevance of the proposed approach by deploying it in the network of smartcameras with live demonstration and comparing the obtained results with those obtained when multi-view is not adopted.

• Determine the power budget of the proposed system and compare it with the power consumption of single-view system with similar detection performance.

The conducted work has been performed in the 2AI (Algorithm Architecture Interactions) team of the MEE (Mathematical and Electrical Engineering) department at IMT Atlantique, Brest, France in the context of one senior engineering project and two internships. The contributions and achieved results have been valorized in 2 papers [START_REF] Gong | Efficient communication and decision strategies for multi-view ai-based object detection on edge devices[END_REF][229] submitted to the IEEE International Workshop on Rapid System Prototyping (RSP), which will be held as a part of the Embedded Systems Week (ESWEEK) international conference, Shanghai, October 2022. Future work will tackle the development of the devised approach to consider different aspects such as the location of the smart-cameras, their angles of view and the similarity of objects' occurrences in consecutive video frames in order to enhance the overall detection result. Also, we will investigate the impact of including orientation to the object annotations during training and inference.

In addition, we have initiated a research work that aims to use top-view scenes in order to assist multi-view marine object surveillance using embedded artificial intelligence and computer vision by exploiting the features of top-view scenes. Figure 8.6 illustrates an overview of this proposed topic. This work is done in the context of a Masters thesis held at the Lebanese University in collaboration with Lab-STICC and IMT Atlantique. The performed work includes creating a huge dataset that includes images of marine objects captured from top view. We have prepared about 200,000 annotated images taken by the means of drones or satellites. Training is conducted targeting YOLOv4 models. The validation of the trained models show promising results in terms of detection performance. The performed work and obtained results are described in a research paper [START_REF] Sharafaldeen | Top-view real-time embedded ai detector to assist multi-view marine object surveillance[END_REF] which is submitted to the IEEE International Conference on Smart Systems and Power Management (IC2SPM), which will be held in Beirut, Lebanon next November 2022. Future work includes the following tasks:

• Investigate the impact of optimization techniques such as quantization and pruning on detection performance.

• Deploy the optimized networks on emergent edge devices and conduct comparisons in terms of detection performance, inference speed and power consumption.

• Apply the tracking algorithms and examining their corresponding performance on test videos. [START_REF] Agency | Annual overview of marine casualties and incidents 2021[END_REF] that during the 2014-2020 period, 367 marine casualties resulted in a total of 550 lives lost and 6921 injuries in the waters of European Union (EU) Member States or involving EU ships. The ability to quickly locate missing people aids in the direction of rescuers and medical personnel, which plays an important role in increasing the chances of saving human lives while also lowering costs.

Embedded AI to Assist Search and Rescue Missions

Years ago, visual surveillance in the maritime domain has been explored. However, most surveillance activities have been assigned to areas near the coasts and ports and mainly depend on human monitoring and analysis for security reasons. Computer vision techniques are also adopted in few works. However, videos and images capturing maritime environment pose challenges that are absent or less severe in other environments such as the dynamic nature of the background, unavailability of static cues, presence of small objects at distant backgrounds and illumination effects [START_REF] Prasad | Challenges in video based object detection in maritime scenario using computer vision[END_REF]. These challenges impact the efficiency of traditional computer vision techniques in detecting individuals in marine environments.

Recently, deep learning approaches have introduced efficient solutions to detect, classify and localize several objects in images and videos. In particular, the evolution of neural networks architectures has elevated the performance to a point that they are considered on par with human performance for some of these problems. The growing use of AI-based detection methods is of great interest in aiding SAR missions [START_REF] Castellano | Preliminary evaluation of TinyYOLO on a new dataset for search-and-rescue with drones[END_REF][START_REF] Liu | Real-time human detection and gesture recognition for onboard UAV rescue[END_REF][START_REF] Rizk | Toward AI-assisted UAV for human detection in search and rescue missions[END_REF][START_REF] Sambolek | Automatic person detection in search and rescue operations using deep cnn detectors[END_REF][START_REF] Rosero | Deep learning with real-time inference for human detection in search and rescue[END_REF]. However, only few works have addressed the detection of humans in open water or for man overboard accidents [START_REF] Lygouras | Unsupervised human detection with an embedded vision system on a fully autonomous UAV for search and rescue operations[END_REF][START_REF] Feraru | Towards an autonomous UAV-based system to assist search and rescue operations in man overboard incidents[END_REF][START_REF] Qingqing | Towards active vision with UAVs in marine search and rescue: Analyzing human detection at variable altitudes[END_REF]. Other available works adopting deep learning in marine environment have focused mainly on the detection of sea ships [START_REF] Qiao | Marine vision-based situational awareness using discriminative deep learning: A survey[END_REF].

The detection performance of CNN-based methods comes at the cost of increased hardware resources and power consumption especially for real-time scenarios with high requirements of accuracy and precision. YOLO has been recently introduced as an efficient unified model of all phases of a CNN for doing object detection in real-time. The recent version of YOLO, so called YOLOv4, has been justified to detect objects in real-time with high level of precision. Several models of YOLOv4 exist, with different architecture specifications and consequently different detection performance in terms of accuracy and precision, detection speed and required energy budget. In this work, the relevance of the YOLO in detecting humans in maritime environment is investigated. The available models of YOLOv4 are trained using a custom dataset. The trained models are evaluated using recognized evaluation parameters. In addition, the trained models are optimized targeting embedded low-power hardware platforms dedicated for AI applications.

The main contributions of this work are:

• Create a novel dataset of humans in marine scenes from various positions and from different perspectives and scales with different backgrounds, resolutions and luminosity.

• Train and validate the target networks using different architecture specifications (number of layers, activation functions, shortcuts, etc.), data augmentation methods and input image resolutions.

• Evaluate the trained models and conduct comparisons in terms of well know metrics (mAP, precision, recall, F1-score and average IOU) [START_REF] Padilla | A comparative analysis of object detection metrics with a companion open-source toolkit[END_REF] in order to find the combination that leads to the best performance.

• Examine the detection performance using several recorded videos. Thee videos show humans in open water from different perspectives, points of view and scale.

• Apply several optimization approaches such as pruning to reduce the number of parameters and quantization of weight and/or activation values in order to ensure better deployment of CNN-based object detection methods on edge devices.

• Deploy the optimized models on popular embedded edge devices (Nvidia Jetson Xavier AGX, AMD-Xilinx Kria KV260 Vision AI Kit, and Movidius Myriad X VPU)

The obtained results show that applying data augmentation enhances the detection performance. The use of higher image resolution enhances the mAP performance but at the cost of reduced inference speed and longer training time. Sample detection results from network testing are shown in Figure 8.7. The figure shows that trained models are able to accurately detect and classify the presence of humans in different maritime environments.

The inference speed of the trained networks is evaluated by running several captured videos, showing humans in open water, targeting embedded platforms with different power modes. Figure 8.8 shows samples of the obtained detection results in captured video sequences. The obtained results show that YOLOv4-tiny can achieve real-time detection of humans in maritime environment with acceptable accuracy and precession. As an example, an inference speed of 90 FPS with mAP of 0.8 can be achieved when running YOLOv4-tiny on Jetson Xavier AGX. Whereas, YOLOv4 can achieve 15 FPS with mAP of 0.859.

In order to achieve real-time inference, optimization techniques are applied targeting three hardware platforms: Nvidia Jetson Xavier AGX, AMD-Xilinx Kria KV260 Vision AI Kit, and Movidius Myriad X VPU. The obtained results show that the optimization targeting Jetson Xavier AGX increases the inference speed while achieving better accuracy for all tested networks. This refers to the optimization process that implements several techniques such as kernal fusion, precision calibration, kernel auto-tuning, dynamic tensor memory and multi-stream execution. YOLOv4 can achieve 20 FPS when FP32 is adopted while attaining The deployment of trained models on Kria KV260 Vision AI Kit reveals that YOLOv4tiny can achieve an inference speed of 65 FPS with 0.451 mAP (-2.46 points in mAP) when the network parameters are quantized to INT8, which is the only supported representation. The YOLOv4 model can achieve an inference speed of 11 FPS with 0.818 mAP.

In order to achieve high-speed inference with high-precision detection, YOLOv4 model is pruned at the level of channels and layers. First, training under channel-level sparsity-induced regularization is performed in order to identify insignificant channels [START_REF] Tian | Pruning-based YOLOv4 algorithm for underwater gabage detection[END_REF]. L1 regularization of the loss during training is adopted based on the work presented in [START_REF] Liu | Learning efficient convolutional networks through network slimming[END_REF]. Channel pruning is then applied to eliminate the channels with little contribution by deleting its input-output connections and corresponding weights. After channel pruning, layer pruning is performed in order to address the cross layer connections (residual) in YOLOv4 network where the output of a layer is the input to several subsequent layers. Finally, fine tuning is then applied to assist the pruned model to restore accuracy.

The obtained results after each pruning step of YOLOv4 network with leakyRelu activation function are reported. It is shown that the mAP drops by 2.3 points after sparsity training. However, this degradation, which is due to the modification of the loss function, is compensated later by the conducted fine-tuning on the pruned network. Also, the results illustrate that the channel pruning greatly reduces the number of model parameters (-98.4%) and the FLOPS (-91.64%) that involve a speed-up effect on embedded devices without suffering from accuracy loss. Fine-tuning of the YOLOv4 network recovers the accuracy loss due sparsity training. The obtained results show that the fine-tuned network achieves higher accuracy (+2.1 points in mAP) than the baseline network while preserving a significant decrease in the required memory (-90.4% reduction of parameters) and computations (-91.66% reduction of FLOPS).

The pruned YOLOv4 network is deployed on Kria KV260 Vision AI Kit. An inference speed of 69 FPS is achieved while the mAP is degraded to 0.348. The pruned YOLOv4 model is also deployed on Movidius Myriad X VPU [START_REF] Ionica | The movidius myriad architecture's potential for scientific computing[END_REF]. The model is optimized and quantized to FP16 representation, which is the only supported representation by the VPU. The resultant model achieves an inference speed of 29.8 FPS (2 threads running on 6 SHAVE cores) and 14.7 FPS (1 thread running on 6 SHAVE cores) with a slight degradation in the mAP (71.01%) when compared to the unquantized pruned network (72.4%). In addition, the YOLOv4-tiny model is deployed on Movidius Myriad X VPU. It achieves 30 FPS inference speed with a mAP of 72.4%.

The performance per Watt is determined when running the models on all targeted embedded edge platforms. Jeston Xavier AGX can achieve 3.83 FPS/W and 1.73 FPS/W for YOLOv4-tiny and YOLOv4 networks respectively. Kria KV260 Vision AI kit can achieve 8.125 FPS/W, 1.375 FPS/W and 8.625 FPS/W for YOLOv4-tiny, YOLOv4 and pruned YOLOv4 networks. Movidius Myriad X VPU can achieve 7.45 FPS/W for pruned YOLOv4 model and 7.5 FPS/W for YOLOv4-tiny model. The analysis of the obtained results shows that Jetson Xavier AGX can achieve best inference speed and mean average precision but at the cost of higher power consumption. This work has been presented initially in the International Conference on System-Integrated Intelligence (SysInt), 2022 and published as a book chapter in Advances in System-Integrated Intelligence [START_REF] Rizk | Towards real-time human detection in maritime environment using embedded deep learning[END_REF]. Also, the extended work about the optimization and deployment on hardware devices has been accepted to be published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) [START_REF] Rizk | Optimization of deeplearning detection of humans in marine environment on edge devices[END_REF] which will be held in Glasgow, UK in October, 2022. Future work will focus on the following:

• Enrich the dataset to include more images and add thermal images to enable the detection in all conditions (night, fog, etc.)

• Examine multi-view approach to enhance detection by making use of collaboration between different cameras which capture same scene from different points of view.

• Examine the detection of humans from cameras situated under the water for man overboard application.

Chapter 9

Future Research Directions 9.1 Design of Memory-centric Ultra-Low Power Processor

The possibility to run complex deep learning (DL) algorithms for hours outdoors on unplugged wearable devices paves the way for new and potentially disruptive applications. Recent developments in non-volatile memory (NVM) technologies and processor architectures for information processing make this opportunity possible and allow the design of wearable devices with efficient AI-capabilities.

One of the future research topics is to investigate the design of a novel memory-centric multicore architecture for ultra-low power AI-based object detection. The target architecture should devise the best of memory-oriented techniques in order to drastically minimize the power consumption. Based on our previous results on Memory-based Computing [START_REF] Rizk | NoC-MRAM architecture for memory-based computing: database-search case study[END_REF][START_REF] Diguet | Networked power-gated MRAMs for memory-based computing[END_REF] and Processing-In-Memory [START_REF] Ali | Crossbar memory architecture performing memristor overwrite logic[END_REF]134,[START_REF] Ali | Memristive computational memory using memristor overwrite logic (MOL)[END_REF][START_REF] Ali | MOL-based in-memory computing of binary neural networks[END_REF] design approaches, we will target the heterogeneous multicore architecture. MBC replaces logic by Non-Volatile power-gated memories to leverage computation redundancy. PIM is a promising approach to reduce memory transfers and power consumption, particularly when using memristive memory arrays. PIM is very efficient for bulk-bitwise logic operations and for matrix multiplications, where the energy cost of moving data is orders of magnitude higher than the computation itself. Nevertheless, for some complex arithmetic tasks that require many successive basic PIM computation steps, passing the operands to a near-memory computing unit could be more time and energy efficient. Accordingly, the mapping of tasks over PIM, MBC and NMC components will be investigated to devise the best design. to not only track different objects, but also to feed the algorithms to add or reject objects (in incremental learning) considering users' feedback.

While traditional machine learning systems process the data that has been given to them in advance, interactive machine learning considers that the learning process could benefit from interactions with the environment as well as with humans [START_REF] Jiang | Recent research advances on interactive machine learning[END_REF], and that inputs and outputs from and for humans carry meaningful information. Indeed, humans may provide input to a learning algorithm [START_REF] Holzinger | Interactive machine learning: Experimental evidence for the human in the algorithmic loop[END_REF], including inputs in the form of labels, demonstrations, advice, rewards or rankings. The interaction is all the more useful as the human can guide along the learning process [START_REF] Amershi | Power to the people: The role of humans in interactive machine learning[END_REF] while adapting his guidance to the outputs of the algorithm. Feedback from the users will be used to help algorithms: define zones to focus for detection using hand gestures, refine the confidence of the object class, define new object classes. The AI-based computer vision algorithms will help automatically annotate and overlay visual cues onto real-world objects in the field of vision of the users, as well as to recognize hand gestures allowing them to interact with these objects. For instance, humans could dismiss some tracked objects that are not useful or that can overload the display, or they would also be able to mark in real time objects "missed" by the computer vision algorithm (feeding incremental learning) that they wish to track in the future.

Having a lower power solution opens up opportunities to have more substantial intelligence on the edge devices. Beyond the application itself, it is required to address the challenge of performing online the incremental learning on edge devices.

Distributed Learning on Connected Devices

Autonomous systems can benefit from growing embedded computing capacities that allow decision making based on multi-sensor fusion and/or complex visual navigation based on semantic recognition [START_REF] Mousavian | Visual representations for semantic target driven navigation[END_REF] and joint mapping and planning [START_REF] Gupta | Cognitive mapping and planning for visual navigation[END_REF]. Current challenges are related to learning issues for both object recognition based on offline training of Deep Neural Networks and navigation tasks based on Reinforcement Learning [START_REF] Kulhánek | Vision-based navigation using deep reinforcement learning[END_REF]. First offline supervised learning and online inference are efficient but require huge labeled datasets that hardly represent all cases to be experienced by autonomous agents in real-life or at a price of energy and time that can be prohibitive [START_REF] Strubell | Energy and policy considerations for modern deep learning research[END_REF]. Therefore, new training phases with updated data-sets may be required according to edge/cloud computing paradigm [START_REF] Wang | Convergence of edge computing and deep learning: A comprehensive survey[END_REF]. Navigation tasks can be based on pre-trained models but are more efficient if they can learn online from their actions [START_REF] Wortsman | Learning to learn how to learn: Self-adaptive visual navigation using meta-learning[END_REF] while detecting/identifying obstacles and targets. In both cases, self-adaptivity is required to improve autonomy. The question to be answered is then: how to improve learning on a set of distributed embedded systems (e.g. CPU-GPU) by favoring unsupervised methods such as Reinforcement Learning to improve the autonomy of autonomous systems evolving in groups.

Tiny Machine Learning (TinyML)

TinyML refers to the integration of machine learning algorithms within ultra-low-power devices, such as Microcontroller Units (MCUs) [START_REF] Han | Putting AI on diet: TinyML and efficient deep learning[END_REF]. Such integration could be the ultimate key towards the reduction of processing power required by applications employed on the edge. Applications such as smart cities and homes, environmental monitoring, industry and business, autonomous driving, and eHealth. This vast spectrum of applications is driving the need for the rapid evolution of TinyML systems, an evolution that faces several challenges along the way. To name a few, the generation of convenient datasets, design of less complex yet effective ML algorithms, memory management, compatibility with existing frameworks for rapid development, etc. [START_REF] Han | TinyML: A systematic review and synthesis of existing research[END_REF]. The challenges faced by TinyML cover the whole ML application development pipeline. Thus, solutions like the design of custom hardware accelerators, in-memory computing, approximate computing, network compression, etc. could be a potential interest of the current TinyML research. Moreover, due to the memory constraint of ultra-low-power devices, one could search for new ML algorithms or efficient deep neural network architectures aside from the existing large models. (2) Efficient algorithms and architectures for dataflow applications; (3) Efficient and flexible design paradigms based on emergent memristive devices and (4) Efficient implementations of machine learning algorithms. Current research activities focus on embedded computer vision and artificial intelligence with the goal of achieving efficient implementations on edge devices with low computational resources and low power budget.

This

  Habilitation to supervise research presents the numerous research activities performed since 20114 targeting the development of flexible and efficient architectures for high performance embedded computing. The presented research activities aim at the realization of flexible and efficient architectures in multitude application domains such as digital communication, data-flow, neural networks, embedded machine learning and embedded vision. These research works have addressed the design and implementation of novel hardware architectures aiming to attain the emergent flexibility requirement, and the ever-increasing requirements of enhanced performance and reduced power consumption and implementation resources. The performed work has targeted the elaboration of new algorithms and hardware architectures using different design paradigms. Several approaches have been adopted including (1) the demonstration of design approaches that lead to better exploiting of resources; (2) making use of optimization techniques such as approximate computing, quantization, and building dedicated hardware architectures; (3) refinement of available algorithms or proposing new algorithms that enhance the performance; (4) exploiting the technological advancements especially related to memristive devices; (5) tackling emergent computing styles such as smart memory architectures, memory-based computing and in-memory computing and (6) benefiting from MPSoC design approaches. In this context, several research works have been initiated through completed or ongoing research projects, two defended PhD theses and several Master theses. The most significant achievements are presented by grouping them in four sub-themes: (1) Flexible yet efficient architectures for applications in the digital communication domain; (2) Efficient algorithms and architectures for dataflow applications; (3) Efficient and flexible design paradigms based xvii xviii on emergent memristive devices and (4) Efficient implementations of machine learning algorithms.

  mémoire d'habilitation à diriger des recherches présente mes nombreuses activités de recherche menées depuis 2014 visant le développement d'architectures flexibles et efficaces pour le calcul embarqué haute-performance. Les activités de recherche présentées visent la proposition et la conception d'architectures flexibles et efficaces dans plusieurs domaines applicatifs tels que la communication numérique, les flots de données, les réseaux de neurones, l'apprentissage automatique et la vision embarquée. Ces travaux de recherche ont porté sur la conception et la mise en oeuvre de nouvelles architectures matérielles visant à répondre aux exigences émergentes en matière de flexibilité, ainsi qu'aux exigences toujours plus grandes en termes de performances et de réduction de la consommation d'énergie et des ressources matérielles. Plusieurs approches ont été explorées, notamment : (1) la démonstration d'approches de conception permettant une meilleure exploitation des ressources, (2) l'utilisation de techniques d'optimisation telles que le calcul approximatif, la quantification et la construction d'architectures matérielles dédiées, (3) l'optimisation d'algorithmes existants ou la proposition de nouveaux algorithmes améliorant les performances, (4) l'exploitation des avancées technologiques, notamment en ce qui concerne les dispositifs memristifs, (5) la prise en compte des paradigmes de calcul émergents tels que le calcul en mémoire et les architectures de mémoire intelligente et (6) la mise à profit des approches de conception de MPSoC. Dans ce contexte, plusieurs travaux de recherche ont été initiés à travers des projets de recherche terminés ou en cours, deux thèses de doctorat soutenues et plusieurs thèses de Master. Les réalisations les plus significatives sont présentées en les regroupant en quatre sous-thèmes : (1) Architectures flexibles et efficaces pour des applications dans le domaine des communications numériques, (2) Algorithmes et architectures efficaces pour des applicaxxi xxii tions de flot de données, (3) Paradigmes de conception efficaces et flexibles basés sur des dispositifs memristifs émergents et (4) Implémentations efficaces d'algorithmes d'apprentissage automatique. Dans le premier thème, la méthodologie de conception No-Instruction-Set-Computer (NISC) est explorée pour concevoir des accélérateurs dédiés aux récepteurs itératifs. Deux architectures basées sur NISC sont proposées et conc ¸ues. Les résultats obtenus en termes de performance et de surface confirment la pertinence de l'adoption du concept NISC dans la conception de processeurs flexibles et efficaces dans le domaine des communications numériques. Dans le deuxième thème, le nouveau concept de Notifying Memories (NM) est introduit pour éliminer les accès inutiles aux mémoires. Les mémoires sont transposées dans des maîtres qui informent les processeurs lorsque les données sont prêtes à être traitées. L'utilisation du concept NM conduit à des réductions significatives de la latence, du taux d'injection, les flits transportés, des conflits de commutation. De plus, le débit est fortement amélioré tout en réduisant la consommation énergétique. En outre, un nouvel algorithme de remapping et une architecture basée sur un réseau-sur-puce (NoC) sont proposés pour faire face à la dynamicité des acteurs du flot de données. Dans le troisième thème, les dispositifs memristifs sont explorés. Tout d'abord, une nouvelle architecture de NoC avec du calcul basé sur mémoire est introduite en utilisant des mémoires non-volatiles pour améliorer les performances et réduire la consommation énergétique. En outre, l'utilisation des memristors pour concevoir des architectures combinant flexibilité et efficacité a été explorée et introduite par la proposition d'architectures originales qui dépassent les limites des architectures existantes. L'exploration et l'étude ont été menées à trois niveaux : (1) au niveau des interconnexions, (2) au niveau du traitement et (3) au niveau de la mémoire. Le quatrième thème porte sur la conception et la mise en oeuvre d'algorithmes efficaces d'apprentissage automatique ciblant l'application de détection tactile. En particulier, des techniques de calcul approximatif et la conception d'accélérateurs matériels dédiés sont investiguées pour réduire la complexité du calcul et atteindre des performances plus élevées avec une faible consommation d'énergie.

•

  Digital design of flexible processing systems • Intellectual Properties for wireless communication • Hardware/software implementations • Application Specific Processors (ASP) • Network-on-Chip (NoC) design • Embedded systems design in the fields of audio, video, and data-flow domains • Embedded Multi-processor System-on-Chip (MPSoC) architectures • Embedded systems based on emerging non-volatile memory technologies • Memory-based computing, near-memory computing and in-memory computing • Algorithm development and refinement for digital base-band components • Algorithm development for task scheduling on MPSoC • Embedded computer vision

• 4 .

 4 Partners: gathers three laboratories in Bretagne region (Lab-STICC, IETR, and IRISA) • Funding: funded by the French National Research Agency (ANR, project ANR-11-INSE-0012) • My Role: Research Engineer 3. Hierarchical Hardware Architectures Based on Associative-Memories and Network on Chips for Cyber-Attack Detection in Telecom Networks (CyAM): • Goal: aims to exploit associative-memories and network on chips in Cyber-Attack detection • Partners: conducted as collaboration between Lab-STICC and University of Tohoku in Japan • Funding: funded by Bretagne region, France • My Role: Post-doc Researcher Optimization of Observation, Detection, Classification and Tracking of Seaships for Maritime Security by Mean of Embedded Deep Learning (ODESSA)

2. 7 . 1 1 . 1 .• 1 2 . 3 . 4 .

 71111234 Supervision of Ph.D. Theses Supervision of the Ph.D. thesis of Dr. Hamoud Younes Post doctoral fellow at IMT Atlantique, Brest, France • Title: Embedded machine learning emphasis on hardware accelerators and approximate computing for tactile data processing • Academic Years: 2018-2021 • University: University of Genoa, Italy 2. Supervision of the Ph.D. thesis of Dr. Khaled Alhaj Ali Post doctoral fellow at IMTAtlantique, France • Title: New design approaches for flexible architectures and in-memory computing based on memristor technologies • Academic Years: 2016-2020 • University: IMT Atlantique, Brest, France 2.7.2 Supervision of Master Theses Since 2015, I have supervised the several Master theses in different universities. The following list presents these theses classified according to universities and the Master's programs. Supervision of Master theses at Lebanese University, Lebanon: • 4 Master theses in the program of the professional Master's degree of Sciences in Field Electro-Mechanical Engineering • 1 Master thesis in the program of the professional Master's degree of Sciences in Medical Physics and Imaging Technologies • 3 Master theses in the program of the research Master's degree of Sciences in Medical Physics and Life Imaging • 1 Master thesis in the program of the research Master's degree of Sciences in Field Electro-Mechanical Engineering • 1 Master thesis in the program of the research Master's degree of Sciences in Signal, Telecoms, Image, and Speech (STIP) Master thesis in the program of the research Master's degree of Sciences in Information System and Big Data Intelligence Supervision of Master theses at Lebanese International University, Lebanon: • 11 Master theses in the program of the Master's degree of Sciences in Computer and Communication Engineering • 2 Master theses in the program of the Master's degree of Sciences in Electrical and Electronics Engineering Supervision of Master theses at IMT Atlantique, Mathematical and Electrical Engineering Department, France: • 2 internships in the program of Engineering in Embedded Systems • 1 internship in the field of embedded artificial intelligence collaboration with the Lebanese University Supervision of Master theses at Lab STICC, Lorient, France:

1 .

 1 Scientific journals: • IEEE Transactions on Signal Processing • IEEE Transactions on Circuits and Systems (TCAS-I) • IEEE Transactions on Circuits and Systems-Part II (TCAS-II) • IEEE Access • IEEE Embedded Systems Letters • Elsevier Embedded Hardware Design journal (Microprocessors and Microsystems) • International Journal of Embedded Systems (IJES) • Journal of Systems Architecture • Journal of Aerospace Technology and Management 2. International conferences: • IEEE Design, Automation and Test in Europe (DATE)

• 4 • 2 • 5 2 .• 9 1 19 • 1 .

 425291191 Master theses in the program of the professional Master's degree of Sciences in Field Electro-Mechanical Engineering (FEME) Master theses in the program of the professional Master's degree of Sciences in Medical Physics and Imaging Technologies (MPIT) Master theses in the program of the research Master's degree of Sciences in Medical Physics and Life Imaging (MPLI) Lebanese International University (LIU), School of Engineering (SoE), Lebanon: Master theses in the program of the Master's degree of Sciences in Computer and Communication Engineering (MCCE) • 10 graduation projects in the program of the Bachelor's degree of Sciences in Computer Engineering (CENG) Further information about my teaching experience is detailed in Appendix C. Teaching and Administrative Responsibilities I have worked as course coordinator for several courses at different universities. Course coordination involves following up the course progress and examination process in different branches and sections. The following list presents the courses that I have coordinated: • Introduction to Mechatronics course in the program of the Master's degree of Science in Electrical and Electronics Engineering at School of Engineering at Lebanese International University • Introduction to Computer course in the program of the Bachelor's degree in Computer at School of Arts and Sciences the American University of Culture and Education • Microprocessors and Interfaces course in the program of the Bachelor's degree in Computer at School of Arts and Sciences the American University of Culture and Education 3.2 Construction and Development of University Courses I have worked on remodeling and development of several courses at different universities. The reconstruction of a course includes the following duties: developing the syllabus, enhancing the course material, choosing the textbooks and updating the course assessment (exams and assignments). • Microprocessors and Interfaces course in the program of the Bachelor's degree in Computer at School of Arts and Sciences the American University of Culture and Education • Introduction to Computer course in the program of the Bachelor's degree in Computer at School of Arts and Sciences the American University of Culture and Education • Introduction to Mechatronics course in the program of the Master's degree of Science in Electrical and Electronics Engineering at School of Engineering at Lebanese International University Contract Administration and Project Management course in the program of the Professional Master's degree of Science in Field Electromechanical Engineering at the Faculty of Sciences at Lebanese University • Neural Network and Deep Learning course in the Image-Signal Module in the program of the Research Master's degree of Science in Medical Physics and Living Imaging at the Faculty of Sciences at Lebanese University • Digital Electronics course in the program of the Master I degree of Science in Fundamental Physics (Biomedical Physics Course) at the Faculty of Sciences at Lebanese University 3.3 Teaching University Courses 3.3.1 Teaching E Overview Since 2011, I have taught several courses in the programs of various degrees in the following universities: Lebanese University, Faculty of Sciences, Lebanon: • Research Master's degree of Sciences in Signal, Telcom, Image and Speech • Professional Master's degree of Sciences in Field Electro-Mechanical Engineering 2. Lebanese University, Institute of Social Sciences, Lebanon: • Bachelor of Social Sciences 3. Lebanese International University (LIU), School of Engineering, Lebanon • Bachelor's degree of Sciences in Computer Engineering • Bachelor's degree of Sciences in Electrical Engineering • Bachelor's degree of Sciences in Electronics Engineering • Master's degree of Sciences in Computer and Communication Engineering 4. American University of Culture and Education (AUCE), Lebanon • Bachelor's degree of Sciences in Computer Sciences Further information about my teaching experience is detailed in Appendix D .

  Low level design at Register transfer level (RTL) (b) Processor-based (c) High level synthesis (HLS)

Figure 4 . 1 -

 41 Figure 4.1 -Traditional available design approaches

Figure 4 . 2 -

 42 Figure 4.2 -ASIP design approach

Figure 4 . 3 -

 43 Figure 4.3 -Transition from ASIP to NISC design approach

  Figure 4.4 demonstrates the stages of NISC designing approach.

Figure 4 . 4 -

 44 Figure 4.4 -NISC designing approach stages

Figure 4 . 5 -

 45 Figure 4.5 -General processor block diagram

Figure 4 . 6 -

 46 Figure 4.6 -Dynamic flexibility in NISC

Figure 4 . 7 -

 47 Figure 4.7 -Adopted design flow [1].

Figure 4 . 8 -

 48 Figure 4.8 -On-board validation using Xilinx ChipScope Pro Analyzer

Fig. 1 .

 1 Fig. 1. Iterative receiver block diagram.

  a)ln(b) ln(e δ1+•••+e δn ) ≈ max i∈{1,...,n} δ i max(a)max(b) = min(-b)min(-a).

Fig. 2 .

 2 Fig. 2. Block diagram of the proposed NISC-based architecture detailing the pipeline structure of DemaNISC module.

  I and Q components of 1-D Euclidean distance (D I and D Q ) or 2-D Euclidean distance D are ready at the end of the sixth pipeline stage (see Fig. 2). b) ASU: In the case of turbo demodulation, the hardware resources embedded in this unit are responsible for generating 4.6. SELECTED PAPERS 57 IEEE Transactions on Circuits and Systems II, 2015

Fig. 3 .

 3 Fig. 3. Architecture of the minimum finder block.

  c) ISU: This unit collects a priori LLR summation values produced by ASU and subtracts them in parallel from the value of 2-D Euclidean distance calculated by EDU. To perform this functionality, intersubtraction unit (ISU) includes a subtractor set, which is made of eight real subtractors considering the highest modulation order with m = 8. ISU also contains nine registers to store the subtraction results (D i = D -Ap i ) in addition to the value of the Q-component of the 1-D Euclidean distance D Q . Subtractors of ISU are placed in the seventh pipeline stage and are capable of producing up to eight D i values (D 0 to D 7 ). If turbo demodulation is omitted, the computed values of Euclidean distance are transferred to the next pipeline stage (eighth) with no modifications. At the end of the seventh stage, three types of data are possible to be achieved:

Figure 5 . 1 -

 51 Figure 5.1 -Actor network model

Figure 5 . 2 -

 52 Figure 5.2 -Structure of a software FIFO generated by Orcc tool

Listing 5 . 1 -

 51 Example of a firing rule\ c e n t e r i n gi f ( numTokens FIFO IN1 >= 64 && numTokens FIFO IN2 >= 1 ) { i f ( SIZE FIFO OUT -numTokensFIFO OUT > 6 4 ) { / / f ir e a c t i o n }}Some experiments are conducted using the C backend of Orcc by executing the MPEG4-SP decoder on a desktop computer in order to trace the number of firings of each actor.

Figure 5 . 3 -

 53 Figure 5.3 -Useless scheduling attempts by the MPEG4-SP decoder for different video

DAC ' 16 ,

 16 June 05-09, 2016, Austin, TX, USA c 2016 ACM. ISBN 978-1-4503-4236-0/16/06. . . $15.00 DOI: http://dx.doi.org/10.1145/2897937.2898051

Figure 1 :

 1 Figure1: CAL actor model[3]

Figure 2 :

 2 Figure 2: Structure of a SW FIFO generated by ORCC

Figure 3 :Figure 4 :

 34 Figure 3: UML Diagram of Observer Design Pattern for software implementation

Figure 5 :

 5 Figure 5: The notifier architecture

Figure 9 :

 9 Figure 9: Classification of control flits according to their types after 10 decoded frames of ice-4CIF

2 (Fig. 1 .

 21 Fig.1. Actors and software FIFO Models[2]

CHAPTER 5 .Fig. 2 .

 52 Fig. 2. The structure of the used NoC-based architecture

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 5

Fig. 3 .

 3 Fig. 3. Packets structure for mapping (left) and monitoring (right) information

Fig. 6 .Fig. 7 .

 67 Fig. 6. Manager command requesting the transfer of the moved actor code origin / destination / type / time FIFO Address Writing Address Data Flit 1

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 7

  2) the computation time of each actor: T cp [A c ], (3) the number of input tokens corresponding to every input port of all actors: N T a total [A c[I j ] ], (4) the number of incoming tokens to each processor module from each memory module m: N T n total [S m , p], (5) the average communication delay of received tokens to each processor p from each memory module m: T av [S m , p], (6) the number of incoming tokens to each memory module m from each processor module p: N T n total [S p , m], and (7) the average communication delay of received tokens to each memory module m from each processor module p: T av [S p , m] where c ∈ {1, ..., |A|}, j ∈ {1, ..., |I c |}, m ∈ {1, ..., |M|} and p ∈ {1, ..., |P|}.

Fig. 8 .

 8 Fig. 8. Example on path declaration in the NoC

  Each path is segmented into a set of links L P[S i ,n] . The average communication time delay per link D L av [S i , n] in the path P [Si,n] is determined as follows:

  )The average communication-time delay per token T av[l] for each link l is determined by dividing the accumulated communication-time delay D total [l] by the number of tokens Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY Algorithm 2 Average-link token delay (ALTD) Step 1: for each path P [Si,n] do a-Find the total communication-time delay D P total [S i , n] b-Calculate average communication time delay per link D L av [S i , n] end for Step 2: for each link l do a-Find the total link communication-time delay D total [l] b-Find the total number of tokens N T total [l] b-Calculate the average communication time delay per token T av [l] end for N T total [l] passing through this link.

  e p [C Ac,p ]. The new period of processor p is estimated by adding to the processor period P eriod p the estimated communication time T e cm [C Ac,p ] and the estimated computation time T e cp [C Ac,p ] of the moved actor A c as shown in the following expression: P eriod e p [C Ac,p ] = P eriod p + T e cp [C Ac,p ] + T e cm [C Ac,p ]

  Fig. 10 demonstrates an example of finding P eriod e max [C Ac,p ]. The figure considers the example illustrated in Fig. 9. Three actors are mapped to the looser processor P E 1 . The candidate list C includes three actors: A 1 , A 2 and A 3 . Six mapping combinations are illustrated: C A1,P E2 , C A1,P E3 , C A2,P E2 , C A2,P E3 , C A3,P E2 and C A3,P E3 . The figure shows how to find the maximum estimated period P eriod e max [C Ac,p ] for each mapping combination. It is shown in the figure that both the estimated communication time and estimated computation time of the same actor differ when mapped to different PEs.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 12 the step of finding the period of each processor, is O(|P|). Then, Step2, the step of finding the processor with maximum period has the complexity of O(|P|). The complexity of Step3, estimating the total gains corresponding the move of the candidate actors to all PEs rather than the looser processor, is O((|P| -1).|A c ∈ C|). The complexity of Step4, choosing the best move, is O(|A c ∈ C|.(|P| -1)). If we consider a well balanced distribution of actors among the processors at initiation (|A c ∈ C| ≈ |A| |P| ), the overall complexity becomes O(|P|) + O(|A|) knowing that |P|-1 |P| ≈ 1.

Fig. 12 .

 12 Fig. 12. Classification of transported packets and flits

Fig. 13 .

 13 Fig. 13. Classification of control flits according to their types

Fig. 14 .

 14 Fig. 14. Number of transported flits

  (a) Foreman with CIF format (b) Ice with 4CIF format (c) Bus with QCIF format

Mostafa

  Rizk received his Maitrise degree in Electronics, M.Sc in Biomedical Physics, and M.Sc in Signal, Telecom, Image, and Speech from the Lebanese University in 2007, 2008 and 2010 respectively. He received his Ph.D. degree in Sciences and Technologies of Information and Communication from Telecom Bretagne, France in 2014 and a Ph.D degree in Electronics and Telecommunication from the Lebanese University in 2015. Dr. Rizk has been a post-doctoral researcher at UBS University and Lab-STICC laboratory CNRS, France. Dr. Rizk has been an associate professor at LIU, Lebanon and associate researcher at IMT-Atlantique, France. Currently, Dr. Rizk is a researcher at Lab-STICC laboratory CNRS, Brest, France. His general research interests include both algorithm development and corresponding hardware/software implementations and digital circuit design; NoC design and new MPSoC architectures based on emerging non-volatile memory technologies; ICT of drone systems; embedded machine learning and embedded computer vision. Kevin J. M. Martin received a M.S. degree in electrical and computer engineering in 2004 and a PhD in computer science in 2010 from the Université de Rennes, France. He is since 2011 an associate professor at Université Bretagne-Sud in Lorient, France, in the Lab-STICC. His research interests stand at the crossing point between architecture, methods and tools, including but not limited to: custom processors, CGRA, multi-processor platforms, high-level synthesis, computer-aided design tools, compilers and software engineering. Jean-Philippe Diguet is a CNRS director of research. He has been A/Prof. at UBS University and research visitor/invited Prof. in different Institutions (IMEC/Belgium, UQ/Australia, Tohoku/Japan, USP/Brasil). At Lab-STICC he has led the team MOCS from 2008 to 2016 and then the ITC and Drones program. Since 2021 his is the director of CROSSING, an International CNRS Lab in Adelaide, Australia dedicated to Human/Automous-Agents teaming. His research work focused initially on various aspects of embedded system design and now addresses various levels of embedded intelligence. Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply.

Fig. 1 .

 1 Fig. 1. Types of MBC. (a) NoC-based with separated PG NVM (this paper). (b) Logic in memory. (c) Processing mapped in LUT (fine grain). (d) Processing mapped in LUT (coarse grain). (e) AMM caching frequent computer results.

Fig. 2 .

 2 Fig. 2. NMBC architecture example with M C = 16 memory clusters composed of M B = 4 memory modules (Mi j), 6 PEs (P[x]), and 2 managers (MGR i ). (a) Architecture. (b) Packet-based command. (c) Example of execution steps.

Fig. 3 .

 3 Fig. 3. STT MTJ. (a) Structure. (b) R-I characteristic.

Fig. 4 .Fig. 5 .

 45 Fig. 4. 4T-2MTJ MRAM cell with PG. (a) Circuit diagram. (b) Timing diagram.

Fig. 4 (

 4 a) shows a 4T-2MTJ MRAM cell with PG. The MRAM designed based on [21] consists of four transistors and two MTJ devices controlled by the power line (PL), the word line (WL), and the bit lines (BL, BL). A data bit is represented by complementary signals, b and b, stored in the two MTJ devices. Fig. 4 (b) shows a timing diagram of the MRAM cell.

Fig. 6 .

 6 Fig. 6. PG types and granularity in 256-bit × 256-word MRAMs. (a) Type I. (b) Type II. (c) Type III.

Fig. 7 .

 7 Fig. 7. Yeast database: m i, j mapping in memory M5.

Fig. 8 .

 8 Fig. 8. Structure of the used NoC.

Fig. 9 .

 9 Fig. 9. Structure of the command packet.

Fig. 10 .

 10 Fig. 10. Architecture of the address finder.

Fig. 11 .

 11 Fig. 11. Architecture of the bit selector.

Fig. 12 .

 12 Fig. 12. Energy consumption for the different memory types and PG policies. (a) 2 Managers-600 requests and 4 configurations with 4, 5, 6, and 7 missing fields. (b) 2 Managers-600 requests and 4 configurations [zoomed on cases, where E < 10 µJ (all FPG policies)].

  Jean-Philippe Diguet (M'07) received the Ph.D. degree from the University of Rennes 1, Rennes, France, in 1996. In 1997, he was a Visiting Researcher at imec, Leuven, Belgium. He was an Associate Professor with the University of Southern Brittany, Lorient, France, until 2002. In 2003, he co-funded the dixip company in the domain of wireless embedded systems. Since 2004, he has been a CNRS Researcher with Lab-STICC, Lorient/Brest, France, where he is currently heading the MOCS Team and the CNRS Director of Research. He was a Visiting Researcher at The University of Queensland, Brisbane, QLD, Australia, in 2010, and an Invited Professor at Tohoku University, Sendai, Japan, in 2014, and at the University of São Paulo, São Paulo, Brazil, in 2016. His current research interests include embedded system design: designs and tools for network-on-chip-based MPSoC architectures, self-adaptivity for uncertain environments, and dedicated hardware architectures, including security and embedded vision. Naoya Onizawa (M'09) received the B.E., M.E., and D.E. degrees in electrical and communication engineering from Tohoku University, Sendai, Japan, in 2004, 2006, and 2009, respectively. He was a Post-Doctoral Fellow at the University of Waterloo, Waterloo, ON, Canada, in 2011, and McGill University, Montreal, QC, Canada, from 2011 to 2013. In 2015, he was a Visiting Associate Professor with the University of Southern Brittany, Lorient, France. He is currently an Assistant Professor with the Frontier Research Institute for Interdisciplinary Sciences, Tohoku University. His current research interests include the energy-efficient VLSI design based on asynchronous circuits and probabilistic computation and their applications, such as associative memories and brainlike computers. Dr. Onizawa received the Best Paper Award from the 2010 IEEE ISVLSI, the Best Paper Finalist at the 2014 IEEE ASYNC, the 20th Research Promotion Award from the Aoba Foundation for the Promotion of Engineering in 2014, and the Kenneth C. Smith Early Career Award for Microelectronics Research from the 2016 IEEE ISMVL. Mostafa Rizk received the Maitrise degree in electronics, the M.Sc. degree in biomedical physics, and the M.Sc. degree in signal, telecom, image, and speech from Lebanese University, Beirut, Lebanon, in 2007, 2008, and 2010, respectively, the Ph.D. degree in sciences and technologies of information from Telecom Bretagne, Brest, France, in 2014, and the Ph.D. degree in electronics and communication from Lebanese University in 2015. He has been a Post-Doctoral Researcher with the University of Southern Brittany, Lorient, France, and with the Lab-STICC Laboratory CNRS, Lorient. He is currently an Assistant Professor with Lebanese International University, Beirut, and an Associate Researcher with IMT Atlantique, Brest, France. His current research interests include algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design, network-on-chip design, and new MPSoC architectures based on emerging nonvolatile memory technologies. Johanna Sepulveda (M'04) received the M.Sc. and Ph.D. degrees in electrical engineering microelectronics from the University of São Paulo, São Paulo, Brazil, in 2006 and 2011, respectively. She was a Post-Doctoral Fellow with the Integrated Systems and Embedded Software Group, University of São Paulo, and the Group of Embedded Security, University of Southern Brittany, Lorient, France. She was a Visiting Researcher with the Computer Architecture Group, University of Bremen, Bremen, Germany. In 2014, she was a Senior INRIA Post-Doctoral Researcher at the Heterogeneous Systems Group, University of Lyon, Lyon, France. Since 2015, she has been a Senior Researcher Assistant at the Technical University of Munich, Munich, Germany. She has been involved in the embedded security design for more than 10 years. Her current research interests include high-performance SoC design and new technologies design. Amer Baghdadi (M'00-SM'15) received the Engineering, M.Sc., and Ph.D. degrees from the Grenoble Institut National Polytechnique, Grenoble, France, in 1998, 1998, and 2002, respectively, and the Accreditation to Supervise Research (HDR) degree in sciences and technologies of information and communication from the University of Southern Brittany, Lorient, France, in 2012. He is currently a Professor with IMT Atlantique/ Lab-STICC Laboratory, France. He has coauthored over 100 papers on scientific journals and proceedings of international conferences. His current research interests include theoretical and practical aspects, both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design, digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Dr. Baghdadi serves on the technical program committee for several international conferences. Takahiro Hanyu (M'89-SM'12) received the B.E., M.E., and D.E. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1984, 1986, and 1989, respectively. He is currently a Professor and the Vice Director with the Research Institute of Electrical Communication, Tohoku University. His current research interests include nonvolatile logic circuits and their applications to ultralow-power and/or highly dependable VLSI processors, and postbinary computing and its application to brain-inspired VLSI systems. Dr. Hanyu received the Sakai Memorial Award from the Information Processing Society of Japan in 2000, the Judge's Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News of Japan in 2002, the Special Feature Award at the University LSI Design Contest from ASP-DAC in 2007, the APEX Paper Award from the Japan Society of Applied Physics in 2009, the Excellent Paper Award at IEICE, Japan, in 2010, the Ichimura Academic Award in 2010, the Best Paper Award at the IEEE ISVLSI 2010, the Paper Award at SSDM 2012, the Best Paper Finalist at the IEEE ASYNC 2014, and the Commendation for Science and Technology by MEXT, Japan, in 2015.

Figure 6 . 1 -

 61 Figure 6.1 -Conventional FPGA architecture

Figure 6 . 2 -

 62 Figure 6.2 -Memristor based-programmable routing structure for FPGA proposed in [2]

Figure 6 . 3 -

 63 Figure 6.3 -Memristive switches: (a) 7T SRAM routing switch, (b) 2T1R routing switch, (c) 2T2R routing switch

Figure 6 . 4 -

 64 Figure 6.4 -The block diagram of the reconfigurable FFT

) 6 . 4 .

 64 HYBRID MEMRISTOR-CMOS DESIGN FOR LOGIC COMPUTATION 133 Electronics, 2021

Figure 1 .Figure 2 .

 12 Figure 1. Memristor: (a) Pinched hysteresis loop, (b) structure: metallic electrodes sandwiching a thin dielectric insulating layer, (c) symbol.

Figure 3 .

 3 Figure 3. IMPLY gate: (a) schematic of a memristor-based IMPLY gate, (b) truth table of the IMPLY function.

Figure 4 .

 4 Figure 4. Structure of MAGIC NOR gate.

6. 4 .Figure 5 .

 45 Figure 5. Schematic layout of MRL AND, NAND, OR and NOR gates.

Figure 6 .

 6 Figure 6. Logical operations performed with MRL AND gate.

Figure 7 .

 7 Figure 7. Example of an MRL logic function performed using X-MRL. Reproduced with permission from [12], Copyright 2019, IEEE.

Figure 8 .

 8 Figure 8. One-Bit Full Adder based on the proposed X-MRL structure. Reproduced with permission from [12], Copyright 2019, IEEE.

Figure 9 .

 9 Figure 9. Proposed layout for the hybrid memristor-CMOS 1-bit full adder based on the X-MRL design technique.

Figure 10 .

 10 Figure 10. Memristor layer at the top of VIAs [29]: (a) a TEM image; (b) a schematic view. Reproduced with permission from [29], Copyright 2019, IEEE.

Figure 11 .

 11 Figure 11. Memristor switching time for V set = 1.4 V and V reset = -1.4 V according to the device in [35].

6. 4 .Figure 12 .Figure 13 .Figure 14 .

 4121314 Figure 12. Transient response of the proposed full adder for the input signals A, B and C in .

6. 4 .

 4 HYBRID MEMRISTOR-CMOS DESIGN FOR LOGIC COMPUTATION 6.5 Memristor Overwrite Logic (MOL) for In-Memory Computing 6.5.1 Preface

Fig. 1 .

 1 Fig. 1. Memristor. (a) Internal state after applying external bias represented by A and B. (b) Truth table.

Fig. 2 .

 2 Fig. 2. Equivalent latch circuit of memristor with binary resistive ports.

Fig. 3 .

 3 Fig. 3. Six possible logic cases performed by a memristor.

Fig. 4 .

 4 Fig. 4. Performing MOL on a vector of bits. (a) Writing N -bits into memristors. (b) Overwrite step for MOL-OR. (c) Overwrite step for MOL-AND.

Fig. 5 .

 5 Fig. 5. MOL inside memristive crossbar. (a) MOL-OR or/and MOL-AND. (b) MOL-OR-NOT or/and MOL-AND-NOT.

Fig. 6 .

 6 Fig. 6. Configurations of MOL memory architectures. (a) 1M. (b) 1T1M.

6. 5 .

 5 MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING 155 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021

Fig. 7 .

 7 Fig. 7. Drivers architectures for the proposed MOL-memory approach.

Fig. 8 .

 8 Fig. 8. Computational memory architecture.

Fig. 10 . 1 ) 1 : 2 )

 10112 Fig.10. Operations sequence for an in-memory N -bit addition process using MOL-memory.

Fig. 11 .

 11 Fig. 11. Typical MTJ. (a) Core structure. (b) Resistance variation.

Fig. 12 .Fig. 13 .

 1213 Fig. 12. Switching behavior of MTJ device when fed with square signal.

Fig. 14 .

 14 Fig. 14. Transient simulation for the in-memory 8-bit addition process.

) SYSTEMS 1 MOL-

 1 Based In-Memory Computing of Binary Neural Networks Khaled Alhaj Ali , Amer Baghdadi , Senior Member, IEEE, Elsa Dupraz , Member, IEEE, Mathieu Léonardon , Member, IEEE, Mostafa Rizk , and Jean-Philippe Diguet , Senior Member, IEEE Abstract-Convolutional neural networks (CNNs) have proven very effective in a variety of practical applications involving artificial intelligence (AI). However, the layer depth of CNN deepens as user applications become more sophisticated, resulting in a huge number of operations and increased memory size. The massive amount of the produced intermediate data leads to intensive data movement between memory and computing cores causing a real bottleneck. In-memory computing (IMC) aims to address this bottleneck by directly computing inside memory, eliminating energy-intensive and time-consuming data movement. On the other hand, the emerging binary neural networks (BNNs), which is a special case of CNN, show a number of hardwarefriendly properties, including memory saving. In BNN, the costly floating-point multiply-and-accumulate is replaced with lightweight bitwise XNOR and popcount operations. In this article, we propose an IMC programmable architecture targeting efficient implementation of BNN. Computational memories based on the recently introduced memristor overwrite logic (MOL) design style are employed. The architecture, which is presented in semiparallel and parallel models, efficiently executes the advanced quantization algorithm of XNOR-Net BNN. Performance evaluation based on the CIFAR-10 dataset demonstrates between 1.24× and 3× speedup and 49% and 99% energy saving compared to state-of-the-art implementations and up to 273-image/s/W throughput efficiency. Index Terms-Binary neural networks (BNNs), convolutional neural networks (CNNs), in-memory computing (IMC).

Fig. 1 .

 1 Fig. 1. Structure of the CNN: (a) multiple layers of CNN including convolution layer (CONV), pooling (POOL), and FC layer, and (b) illustration on the convolution and the max-pooling operation.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply.

Fig. 2 .

 2 Fig. 2. BNN: (a) XNOR truth table and (b) XNOR-popcount process.

Fig. 3 .

 3 Fig.3. Convolutional layer in a BNN followed by a pooling layer.

  where y b n,m represents the output after convolving the nth binary Ifmap X b n with its corresponding binary weight kernel W b n,m and Y b m represents the mth Ofmap after adding and binarizing all the N outputs y b n,m .

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply. 6.5. MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING 167 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022

Fig. 4 .

 4 Fig. 4. Architecture diagram of the MOL-based CMEM.

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Fig. 5 .

 5 Fig. 5. Proposed in-memory XNOR-based convolution method: (a) samples of the CMEM state taken from different operation phases, (b) CMEM regions partitioning, (c) example on the near-memory popcount and binarization stage, and (d) architecture of the popcount and binarize (PB) block located inside the NMU.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply.6.5. MEMRISTOR OVERWRITE LOGIC (MOL) FOR IN-MEMORY COMPUTING169 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

Fig. 6 .

 6 Fig. 6. Rowwise XNOR: (a) operations sequence for an MOL-based in-memory XNOR operation, where each column corresponds to the state of the CMEM at a certain step, and (b) definition of the six microinstructions used.

Fig. 7 .

 7 Fig. 7. Proposed bubble sort-based majority technique: (a) middle bit after bubble sort represents the majority bit, (b) used bubble-flip module, (c) logic tree implementation for input vector size N =6, and (d) in-memory rowwise channel sorting in order to obtain Ofmap Y b m .

Fig. 9 .

 9 Fig. 9. Proposed in-memory BNN architecture with two different models: (a) semiparallel model shares one NMU to all CMEM banks and (b) parallel model where each CMEM unit reserves a separate NMU.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on May 15,2022 at 06:08:47 UTC from IEEE Xplore. Restrictions apply.

Figure 1 .

 1 Figure 1. Algorithmic level Approximate Computing Techniques: (a) data-oriented; and (b) processing-oriented. Adopted from [17].

Figure 2 .

 2 Figure 2. Sketch of the proposed Approximate Tensorial SVM.

  3 s by omitting readings outside the interval [3.7, 7] s. This results in a new tensor φ(4 × 4 × 10, 500). • To reduce the computational complexity of the tensor-based learning algorithms, the tensor size could be reduced without the loss of information originality using subsampling. The latter is applied by truncating each sample into a new tensor φ(4 × 4 × 40) with 40 random time readings. Then, the resulting tensor is unfolded into three matrices M(4 × 160), N(4 × 160) and P(40 × 16

Figure 3 .

 3 Figure 3. Touch Modalities: (a) touch with noisy readings; and (b) touch with silent intervals.

Figure 4 .

 4 Figure 4. FPGA implementation process.The inference starts by fetching a sample tensor from the testing set (that was already approximated using AU1). The selected tensor undergoes the unfolding, symmetrization and SVD processes. The obtained support vectors along with the support vectors from the training phase are provided to the kernel computation block. During online inference, Approximate Unit 2 is active. It operates by applying:• Loop perforation (LP) technique to the SVD block with a skipping factor s f . The support vectors are obtained using the one side Jacobi Algorithm. The latter is an iterative algorithm, thus it is perforated with s f = 2. This technique accelerates the SVD computations but a large s f could not be applied to ensure the algorithm's convergence. • Computation Approximation (CA) to the computation of Z in Equation (3). The obtained singular vector matrices from the SVD block are V1(160 × 160), V2(160 × 160) and V3(16 × 16). These matrices are truncated to V1 (160 × 4), V2 (160 × 4) and V3 (16 × 2). Such truncation reduces the complexity of the matrix multiplication in Equation (3) with an acceptable error margin. This technique was also applied in the offline training phase so that the equation Z = V T x V y has correct dimensions.• Data Format Modification (DFM) to all the variables and arithmetic operations in different SVM blocks. HLS offers a library called "apfixed", which allows the declaration of variables with fixed-point precision. This declaration is limited by an upper bound[23]. Specifically, the mathematical functions are Square Root (sqrt), which is used in SVD calculations, and Exponential (exp), which is used in kernel computations. These functions are supported only for bit-widths w ≤ 32 and w ≤ 16, respectively. This limitation was resolved by a variable precision architecture. Hence, all the inference blocks are implemented with 24-bit fixed-point representation with a < 12, 12 > precision except the kernel computation block.

•

  Array Partition: tThis directive partitions a large BRAM occupied by a multidimensional array into smaller separate memories. The array partitioning can be complete, cyclic or block. The latter was applied on the tensor φ(4 × 4 × 40) with block size = 16, as shown in Figure 5. This results in an RTL IP block with smaller memories while improving the throughput of the Unfolding process. • Dataflow: This directive allows functions to overlap in their operations, enhancing the overall throughput and latency of the design. The functions unfold and symmetrization are executed in a task-level pipelining using this directive, as shown in Figure 6. • Pipelining: This directive allows the parallel execution of loop iterations, hence reducing the time latency. The computation of Z in Equation (

Figure 5 .

 5 Figure 5. Array partitioning: (a) without partitioning; (b) block partitioning; and (c) block with size=16.

Figure 6 .

 6 Figure 6. Dataflow pipelining: (a) without dataflow; and (b) with dataflow.

Figure 7 .

 7 Figure 7. Pipeline directive applied on vector multiplication.

Figure 8 .

 8 Figure 8. Speedup and power consumption reduction under different ACTs.

  The suitable division ratio (a%:b%) is determined via a software simulation. Start by decreasing the size of V until the classification accuracy drops to obtain the value of a. Hence, b = Sa.• Step 2: K-registers are initialized with a maximum value (e.g. 1000). Each distance value V 1[i] is compared to the content of register 1. If it is smaller, V 1[i] occupies the register, and the old content in register 1 is shifted to register 2. Then, the content in register 2 is shifted to occupy register 3. Consequently, the content in register i is shifted to occupy register i+1. Else, V 1[i] is compared

Fig. 2 .

 2 Fig. 2. The Proposed Hardware Architecture

Fig. 5 .

 5 Fig. 5. Touch Modalities: (a) Rolling with DS, (b) Rolling after DSc, (c) Sliding after DSc, * Window been also implemented on the Virtex-7 FPGA and the NVIDIA GTX 1650 GPU.As for the software tools, Vivado HLS 2018.3 and Vivado 2018.3 were used. Vivado HLS allows the design of an embedded system on FPGA using a high-level programming language such as C and C++ compared to traditional hardware description languages (HDL). The use of HLS decreases the FPGA development time and effort. Also, it offers a set of optimization directives that can be used to enhance the design performance. Once the design is completed, it can be exported as a Register Transfer Level (RTL) Intellectual Property (IP) block. The latter is imported into Vivado and can be connected to the processing system (PS) via built-in IPs; thus, it is possible to obtain the hardware resources, time latency, and power consumption of the whole design.

Fig. 6 .

 6 Fig. 6. Design Optimization: (a) BRAM Resources Reductions, (b) Unrolled Class Determination, (c) One Unrolled Distance Calculation (UDC) Block, (d) Complete Unrolled Distance Calculation

  (c). Similarly, Figure 6(d) shows how the UDC block is used to calculate the distance between the testing sample and all training samples. An UNROLL factor equals to 6 is used, thus 112 timing intervals are required to finish all the distance calculations for a training set size of 80%. The distance from a testing sample to (80 * 840/100) = 672 training samples is calculated in batches of 6 calculations per timing interval i.e 672/6 = 112 intervals. As for Class Determination, since K = 3 and we have a binary classification, the process could be fully unrolled as shown in 6(b).

PAPERS 1 A

 1 Shallow Neural Network for Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing Hamoud Younes , Graduate Student Member, IEEE, Ali Ibrahim , Member, IEEE, Mostafa Rizk , Member, IEEE, and Maurizio Valle , Senior Member, IEEE Abstract-This paper presents a novel hardware architecture of the Tensorial Support Vector Machine (TSVM) based on Shallow Neural Networks (NN) for the Single Value Decomposition (SVD) computation. The proposed NN achieves a comparable Mean Squared Error and Cosine Similarity to the widely used one-sided Jacobi algorithm. When implemented on an FPGA, the NN offers 324× faster computations than the one-sided Jacobi with reductions up to 58% and 67% in terms of hardware resources and power consumption respectively. When validated on a touch modality classification problem, the NN-based TSVM implementation has achieved a real-time operation while consuming about 88% less energy per classification than the Jacobi-based TSVM with an accuracy loss of at most 3%. Such results offer the ability to deploy intelligence on resource-limited platform for energy-constrained applications. Index Terms-Embedded machine learning, real-time, tensorial kernel, tactile sensors, neural networks, singular value decomposition, FPGA.

  Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 26,2021 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.7.4. CONTRIBUTIONS AND PERFORMED WORK 209 IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS), 2021 These modalities are derived from a tactile dataset that has been collected by 70 participants. Each participant performed the modality on both the horizontal and vertical axes of a 4 × 4 tactile sensor for a duration of 10 seconds. Thus each touch modality is represented by a tensor φ(4 × 4 × 30, 000). However, such tensor size is reduced into φ(4 × 4 × 20)

Fig. 2 .

 2 Fig. 2. SVD Computation using: (a) one-sided Jacobi, (b) Neural Network.

Fig. 3 .

 3 Fig. 3. Number of Operations required in one-sided Jacobi (Nj) and Shallow Neural Network (N), (m,n) are the matirx dimension and H is the hidden layer size.

Fig. 4 .

 4 Fig. 4. Proposed Shallow Neural Network: (a) Overall Structure, (b) Hidden Layer Neuron, (c) PReLU Activation Function, (d) Output Layer Neuron, (e) Approximate Hyperbolic Tangent Activation Function.

  Fig. 5. Touch Modality with: (a) Noisy Readings, (b) Silent Intervals.

  H = [10, 20, . . . . . . 200] • PReLU β: learned parameter through Channel-wise or channel-shared modes [36] • Learning rate = [0.1, 0.01, 0.001, . . . 10 -5 ] • Optimizer: [SGD, Adam, Adadelta, RMSprop] • Batch size = [50, 100, 150]

Algorithm 1 Fig. 6 .

 16 Fig. 6. Network Performance Under Different Activation Functions.

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Fig. 7 .

 7 Fig. 7. Best Model Performance: (a) CS for V (80 × 4), (b) MSE for V (80 × 4), (a) CS for V (16 × 2), (b) MSE for V (16 × 2).

Fig. 9 .

 9 Fig. 9. Vector Y O to Array V Transformation.

Fig. 10 .

 10 Fig. 10. Neural Network based SVM Cascade Architecture.

  Fig. 11. Scalability of Shallow Neural Network for varying the hidden/output layers size.

Fig. 12 .Fig. 13 .

 1213 Fig. 12. SVD Computation Approach via Shallow Neural Network.

  Figure 8.1(a) and Figure 8.1(b) show two consecutive captured images Im x and Im x+1 .

  Figure 8.1(c) shows the stitched image Im x,x+1 . Figure 8.1(d) and Figure 8.1(e) present respectively the matching of the two original images Im x and Im x+1 in the resulting stitched image Im x,x+1

Figure 8 . 1 -

 81 Figure 8.1 -Sample application of the proposed method

Figure 8 . 2 -

 82 Figure 8.2 -Bearing angle comparison results

Figure 8 .

 8 3 shows the block diagram of YOLOv4 network.

Figure 8 . 3 -

 83 Figure 8.3 -Block diagram of YOLOv4 network

Figure 8 . 4 -

 84 Figure 8.4 -Sample predictions of marine objects using the trained model

Figure 8 . 5 -

 85 Figure 8.5 -Overview of the proposed multi-view smart-camera network

1

 1

Figure 8 . 6 -

 86 Figure 8.6 -Overview of the proposed top-view detection to assist multi-view marine object surveillance

Figure 8 . 7 -

 87 Figure 8.7 -Sample detection results using the testing dataset images

Figure 8 . 8 -

 88 Figure 8.8 -Samples of the obtained detection results using recorded video sequences

Figure 9 .

 9 1 illustrates the target architecture model combining PIM, MBC and NMC.

9. 2 Figure 9 . 1 -

 291 Figure 9.1 -Target architecture model combining PIM, MBC and NMC

Titre:

  Architectures efficaces pour calcul embarquée haute-performance Mots clés : Architectures efficaces, flexibilité, calcul embarquée, haute-performance Résumé : Ce mémoire d'habilitation à diriger des recherches présente mes nombreuses activités de recherche menées depuis 2011 visant le développement d'architectures flexibles et efficaces pour le calcul embarqué haute-performance. Les activités de recherche présentées visent la proposition et la conception d'architectures flexibles et efficaces dans plusieurs domaines applicatifs tels que la communication numérique, les flots de données, les réseaux de neurones, l'apprentissage automatique et la vision embarquée. Ces travaux de recherche ont porté sur la conception et la mise en oeuvre de nouvelles architectures matérielles visant à répondre aux exigences émergentes en matière de flexibilité, ainsi qu'aux exigences toujours plus grandes en termes de performances et de réduction de la consommation d'énergie et des ressources matérielles. Dans ce contexte, plusieurs travaux de recherche ont été initiés à travers des projets de recherche terminés ou en cours, deux thèses de doctorat soutenues et plusieurs thèses de Master. Les réalisations les plus significatives sont présentées en les regroupant en quatre sous-thèmes : (1) Architectures flexibles et efficaces pour des applications dans le domaine des communications numériques, (2) Algorithmes et architectures efficaces pour des applications de flot de données, (3) Paradigmes de conception efficaces et flexibles basés sur des dispositifs memristifs émergents et (4) Implémentations efficaces d'algorithmes d'apprentissage automatique. Mes activités de recherche actuelles se concentrent sur la vision par ordinateur et l'intelligence artificielle embarquées dans le but de réaliser des implémentations efficaces sur des dispositifs embarqués avec de faibles ressources de calcul et un faible budget énergétique. Title : Efficient Architectures for High-Performance Embedded Computing Keywords : Efficient Architectures, Embedded Computing, Flexibility, High-Performance Abstract: This Habilitation to supervise research presents the numerous research activities performed since 2014 targeting the development of flexible and efficient architectures for high performance embedded computing. The presented research activities aim at the realization of flexible and efficient architectures in multitude application domains such as digital communication, data-flow, neural networks, embedded machine learning and embedded vision. These research works have addressed the design and implementation of novel hardware architectures aiming to attain the emergent flexibility requirement, and the ever-increasing requirements of enhanced performance and reduced power consumption and implementation resources. The performed work has targeted the elaboration of new algorithms and hardware architectures using different design paradigms. In this context, several research works have been initiated through completed or ongoing research projects, two defended PhD theses and several Master theses. The most significant achievements are presented by grouping them in four sub-themes: (1) Flexible yet efficient architectures for applications in the digital communication domain;

Table B . 2 -

 B2 Supervised Master theses at Lebanese University

	Table B.3 -Supervised Master theses at Lebanese International University
	Academic Year	Thesis Title
	Academic Year		Thesis Title	Major
			Acoustic Classification Using Machine Learning on
	2021-2022		Embedded Edge Devices to Assist Real-Time Drone	STIP
			Detection
		Evaluation of the conformity of the maintenance department
	2018-2019	at the company Flashmed to the quality control technical and	MPIT
			management requirements
	2019-2020		Surgical tool detection in cataract surgery	MPLI
	2019-2020		Examining image processing techniques for living human detection and localization for search and rescue missions	MPLI
	2020-2021	Crowd detection in closed areas to assure physical distancing during COVID-19 pandemic	MPLI
	2020-2021		Remote real-time monitoring of the environment of pharmaceuticals and food	FEME
	2017-2018		Hadat faculty of sciences buildings electrical auditing and power economy	FEME
	2016-2017		Hadat desalination using reverse osmosis	FEME

Table C . 2 -

 C2 Master theses I have participated in their evaluation committees

	Inistitute Academic Year	Thesis Title	Major
	LIU LIU LIU Appendix D 2020-2021 2020-2021 2020-2021	University system for advising (USA) Human-computer interface using eye gaze Deep learning with JavaScript	MCCE MCCE MCCE
	LIU LIU Teaching Activities 2020-2021 Android malware detection using machine learning 2019-2020 Optimal RSU placement for VANET	MCCE MCCE
	LIU	2019-2020	Development of NB-LDPC codes based on different GF for iterative receivers	MCCE
	LIU	2019-2020	Parallel implementation of feed-forward neural networks	MCCE
	LIU	2017-2018	A Lebanon wide IoT network	MCCE
	LIU	2017-2018	Augmented reality using Kinect	MCCE
	UL	2018-2019	Facilities management and security: preparing for accreditation at DAR-AL-AMAL hospital	MPIT
	UL	2018-2019	Microwave microfluidic sensor for detecting biological cells	MPIT
			Analysis of the effect of auditory and visual
	UL	2018-2019	simulations on EEG signals using Wavelet	MPLI
			Transform
	UL	2019-2020	Texture analysis of uterine fibroma on MRI	MPLI
	UL	2019-2020	X-ray image segmentation and fracture detection using image processing techniques	MPLI
	UL	2020-2021	Covid-19 lung infected image analysis and interpretation	MPLI
	UL	2020-2021	Image Analysis and Interpretation of Knee Osteoarthritis	MPLI
	UL	2020-2021	Heating, ventilation and air-conditioning systems in the context of COVID-19	FEME
	UL	2019-2020	An optimum selection of secondary batteries for UPS systems: a comprehensive study	FEME
	UL	2019-2020	Distance Patient Monitoring	FEME
	UL	2018-2019	Pharmaline BMS project	FEME

Table . D

 . .1, Table. D.2 and Table. D.3 list the taught courses classified according to the university, level, and major.

Table D . 1 -

 D1 Taught courses at American University of Culture and Education, Lebanon

	Table D.3 -Taught courses at Lebanese International University Introduction to My Research Activities
	Academic Years		Title	Level	Major Length
	2015-2018 My previous research activities since the beginning of my PhD thesis have addressed four Electric Circuits I BS-L1 LENG 45h
	2017-2018 topics:	Fundamentals of Digital Logic Design BS-L2	CENG		45h
	2017-2020		Advanced Digital Logic Design	BS-L2	CENG		45h
	2015-2017 2015-2016 2016-2017		Fundamentals of Optoelectronics Electrical Systems Simulation Operating Systems Part II	BS-L3 BS-L3 BS-L3	LENG EENG CENG		45h 45h 45h
	Academic Years 2011-2012 2018-2021 Introduction to Database Systems Title Microprocessors and Interfaces BS-L3 Level Major Length CS 40h BS-L2 CENG 45h 2016-2017 Microprocessors and Microcontrollers BS-L2 CENG 45h 2016-2017 Signals and Systems BS-L2 CENG 45h Overview of Past Research Activities
	2011-2012 2016-2017	Introduction to Computers Senior Project -LENG	BS-L1 BS-L3	CS LENG	40h	45h
	2011-2012 2016-2021	Calculus I Senior Project -CCE	BS-L1 BS-L3	CS CENG	40h	45h
	2018-2020		Communication Networks Lab	BS-L3	CENG		45h
	2015-2016		Fiber optics	MS-M1 MCCE		45h
	2016-2020		Table D.2 -Taught courses at Lebanese University Digital Communication MS-M1 MCCE		45h
	Academic Years 2016-2019 2011-2013 2019-2021 2017-2018 2020-2021 Image Processing and Computer Vision MS-M2 MCCE Title Computer Architecture MS-M1 MCCE Level Major Length 45h Multimedia Networks 45h MS-M2 MCCE Signals and Image Processors MS-M2 STIP 24h Contract Administration 45h MS-M2 FEME 24h 2018-2021 Project Management 2017-2020 Introduction to Mechatronics 45h MS-M1 MLENG MS-M2 FEME 24h 2019-2021 Informatics BS-L1 2017-2021 Embedded Systems 45h MS-M1 MCCE SS 50h 2017-2018 Linux Lab BS-L3 CENG 23h
	2016-2018	Software Applications and Design Lab BS-L2	CENG		23h
	2017-2018		Embedded Systems Lab	MS-M1 MCCE		23h
	2016-2019		Computer Architecture Lab	MS-M1 MCCE		23h
			39

  Soft-Input-Soft-Output Demapper Mostafa Rizk, Student Member, IEEE, Amer Baghdadi, Member, IEEE, Michel Jézéquel, Senior Member, IEEE, Yasser Mohanna, and Youssef Atat

  Manuscript received March 1, 2015; revised April 23, 2015; accepted June 12, 2015. Date of publication July 13, 2015; date of current version October 30, 2015. This brief was recommended by Associate Editor G. Masera.

TABLE I SYNTHESIS RESULTS

 IRESULTS

TABLE II

 II

	EXECUTION PERFORMANCE RESULTS

Table 1 :

 1 Unsuccessful scheduling by the MPEG4-SP decoder for different video sequences and formats

	Video	Useless	Empty	Full
	Sequence Format attempt input FIFO output FIFO
	Akiyo	CIF	42.7%	63.7%	36.3%
	Parkjoy	720p	21.3%	90.8%	9.2%
	Foreman	CIF	34.8%	90.7%	9.3%
	Coastguard	CIF	27.8%	98.4%	1.6%
	Stefan	CIF	25.9%	83.3%	16.7%
	Bridge far	QCIF	23.8%	38.4%	61.6%
	Ice	4CIF	45.6%	70.4%	29.6%

Table 2 :

 2 Results of decoding 10 frames of ice video sequence in 4CIF format

	Parameter	Notifying Ordinary memory memory	gain
	Latency (µs)	143.42	665.06	-78.44%
	Throughput (frames/s)	27.53	23.29	+15.41%
	Injection rate(flits/s) 60 167 732 121 635 294 -50.53%
	Switch conflicts	71 182 509 288 574 519 -75.33%
	Transported flits	109 264 000 261 123 000 -58.16%
	Transported packets 15 376 400 107 050 000 -85.64%

Table 3 :

 3 Notification memory gain for decoding 10 frames of different video sequences

	Video SequenceFormat	ThroughputLatency	Injection Switch Flits rate conflictsnumber
	Bridgefar QCIF	+15.53%	-73,96% -45,80% -71,38% -54,22%
	bus	CIF	+2.84%	-73,79% -53,40% -72,90% -54,73%
	grandma QCIF	+16.79%	-68,96% -60,78% -85,50% -67,36%
	foreman	CIF	+14.26%	-78,41% -46,81% -72,86% -54,39%
	ice	4CIF	+15.41%	-78,44% -50,53% -75,33% -58,16%
	and dynamic power of the NoC components relying on the
	switching activity traced by the SystemC simulation of 10
	decoded frames of the ice-4CIF video sequence. The results
	show that the NoC adopting notifying memories saves up
	to 49.1% of power consumption compared to the reference
	NoC. Besides, the power overhead of the interfaces of the
	proposed NoC presents a modest value of 16.3%. Regarding
	the area, the proposed NoC presents an overhead of 12.4%,
	when compared to reference NoC.

TABLE I HARDWARE

 I

	ACCELERATORS USED IN THE SIMULATION PLATFORM
	PE ID PE3 & PE6 PE4 PE10 PE11	Accelerated Function IDCT IQ + IAP Add Interpolation	Acceleration Ratio 1/0.3 1/0.75 1/0.57 1/0.4

TABLE III ADDRESSES

 III DETERMINED BY THE MFM-NI CONTROLLER

	Packet Type Request/Set writing index Request/Set reading index Reading Request packet Data packet	Starting Address F IF Osize F IF Osize + 1 Reading address	Offset 0 reading order incremented till

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	Packet header	origin / destination / type / time
	Packet payload	FIFO Address	Reading Order
	Packet header	origin / destination / type / time
	Packet payload		Reading Order FIFO Address
	Packet header	origin / destination / type / time
	Packet payload	FIFO Address	Reading Order New Index Value
	Fig. 4. Packet structures for holding reading (top) / writing (middle) index requests and set index (bottom)
	Packet header	origin / destination / type / time
	Packet payload	FIFO Address Reading Address	Data Size
	Fig. 5. The structure of the packets holding the reading requests

has to request the reading and/or writing indexes of input and output FIFOs. When the PE receives the value of demanded reading/writing index, it will check the satisfaction of the firing rule. After reading/writing data from/to a FIFO, the reading/writing index has to be incremented by the size of the transferred data. The PE, which consumes/produces data, has to set the new reading/writing index in the targeted FIFO after reading/writing operation is performed. Accordingly, four types of packets are utilized: (1) Request read index, (2) Request write index, (3) Setting read/write index, and

TABLE IV PARAMETERS

 IV AND VARIABLES USED FOR THE MAPPING ALGORITHM

	Parameter	Definition
	DPN application graph (DPNapp)
	|A| |F| |K| |Ic|	Number (Nb) of actors Nb of FIFO channels Nb of data packets Nb of input ports of actor Ac Architecture graph (arch)
	|P| |M|	Nb of processing elements Nb of memory modules Profiling data (profile)
	Ri	Mean number of firings of actor i
	W i	Total computation cost of actor i
	Cs i	Instruction code size of actor i

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	1.0E+09	Total Control Packets					1.0E+09	Total Control Fits
	1.0E+05 1.0E+06 1.0E+07 1.0E+08	39403214 Total Data Packets 34526921 3557420 3485096	369690083	27498650	360090870	27402634	1.0E+05 1.0E+06 1.0E+07 1.0E+08	71236445 Total Data Flits 62805072 54553400	51551080	665961105	579717000	647391250	579580560
	1.0E+04							1.0E+04
	1.0E+03							1.0E+03
	1.0E+02							1.0E+02
	1.0E+01							1.0E+01
	1.0E+00							1.0E+00
		No	MB	No	MB		No	MB	No	MB
		Remapping	Remapping	Remapping	Remapping		Remapping	Remapping	Remapping	Remapping
		bus QCIF		ForemanCIF			bus QCIF			ForemanCIF

TABLE V PERCENTAGE

 V OF FLITS TRANSPORTED IN BCP FROM TOTAL FLITS

	Video Sequence Format Foreman CIF Bus CIF Ice 4CIF Bus QCIF	Remapping Algorithm MB-ALTD MB-APTD 0.0044% 0.0067% 0.0008% 0.0125% 0.0027% 0.0019% 0.0348% 0.0272%

  presents the variation Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 14

		6.2E+08 6.4E+08	MB-Remapping	No Remapping
		6.0E+08
		5.8E+08
	Clock cycles	5.0E+08 5.2E+08 5.4E+08 5.6E+08
		4.8E+08
		4.6E+08
		4.4E+08
		44 45	MB -Remapping	No Remapping
	clock cycles/packet	37 38 39 40 41 42 43
		35 36		Frames
	Fig. 15. Sum of packet time-delays (top) and average packet time-delay (bottom) while decoding Foreman video with CIF format

  )), maximum performance enhancement of 33.2% (frame 170) and 23.9% (frame 190) are recorded when applying the MB algorithm adopting ALTD and APTD respectively. The simulation results show that the link level Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 15

			6.0E+08 7.0E+08	Communication Time	Computational Time
	Clock cycles		1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08
	(a)	0.0E+00	10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300
			6.0E+08 7.0E+08	Communication Time	Computational Time
	Clock cycles		2.0E+08 3.0E+08 4.0E+08 5.0E+08
			1.0E+08
	(b)	0.0E+00	10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300
	Fig. 16. Total communication and computational times recorded throughout the observing windows during the decoding of the Foreman video with CIF format [36]; when adopting (a) ordinary decoding and (b) MB remapping
		6.0E+07	PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12
		5.0E+07
	Clock cycles	1.0E+07 2.0E+07 3.0E+07 4.0E+07
		0.0E+00
				0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 mapping iterations

Fig. 17. PE communication time in terms of FPS of decoding Foreman video with CIF format

  Table VI summarizes the comparison of average FPS achieved when processing multitude video sequencing while adopting different remapping tech-Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. 1045-9219 (c) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPDS.2022.3177957, IEEE Transactions on Parallel and Distributed Systems JOURNAL OF ...., VOL. XX, NO. X, MONTH YYYY 16

	45	No Remapping	Remapping -MB ALTD	Remapping MB APTD	Remapping STM	No Remapping Optimal
	40
	35
	25 30 frames/s
	20
	15
	10
					frames
		No Remapping		Remapping -MB ALTD	Remapping -MB APTD
		Remapping -STM	No Remapping Optimal
	frames/s
					frames

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	frames/s	65 70 75 80 85 90	No Remapping	No Remapping Remapping STM Remapping MB ALTD Optimal Remapping MB ALTD	Remapping MB APTD No Remapping Optimal M	Remapping MB ALTD M Remapping MB APTD Optimal
		60
		55
	(a) Foreman with CIF format	frames
	350	No Remapping	Remapping MB ALTD
	330
	290 310 frames/s
	270
	(e) Grandma with QCIF format frames/s No Remapping Remapping -MB APTD Fig. 18. Throughput in terms of FPS when decoding video sequences [36] using MB and STM remapping algorithms frames Remapping -MB ALTD No Remapping Optimal Authorized licensed use limited to: IMT ATLANTIQUE. Downloaded on August 15,2022 at 05:05:28 UTC from IEEE Xplore. Restrictions apply. frames (b) Bus with QCIF format Fig. 19. Throughput in terms of FPS when decoding video sequences [36] using MB remapping algorithms targeting 4 × 6 NoC TABLE VI ACHIEVED RESULTS ADOPTING DIFFERENT REMAPPING TECHNIQUES 1045-9219 (c) 2021 IEEE. 250 Video Remapping Algorithm Sequence Format MB-ALTD MB-APTD STM Foreman 11.4% 5% 4.1% CIF Bus CIF 5.4% 5.4% -17.7% Ice 4CIF 26.1% 2% -13.04% Bus QCIF 9% 8% -20% Grandma QCIF 14.91% 14.11% NA

niques. The table shows that the MB algorithm achieves the maximum average performance enhancements of 26% and 14.11% when adopting ALTD and APTD respectively compared to the achieved throughput of processing the frames without remapping. Whereas, remapping using STM algorithm achieves a maximum average enhancement of 4%.

TABLE VII REDUCTION

 VII OF PACKET HOPS WITH MB-ALTD AND MB-APTD

	Video Sequence Format Foreman CIF Bus QCIF Grandma QCIF	Remapping Algorithm MB-ALTD MB-APTD 20.94% 12.64% 3.24% 5.29% 14.18% 8.33%

  Type I: controls one 256 × 256 MRAM and adopts one PG transistor 2. Type II: controls four 128 × 128 MRAMs and adopts four PG transistors for thr four 128 × 128 MRAM subblocks

	• Introduce novel implementations of Spin-Transfer-Torque Magnetoresistive Random-
	Access Memory (STT-MRAM) with cell and peripheral power-gating capabilities.
	Three different types of 256-bit × 256-word MRAMs with different power gating poli-cies are adopted:
	1.

3. Type III: controls four 128 × 128 MRAMs and adopts one PG transistor Type I controls one 256 × 256 MRAM; whereas, Type II and Type III control four 128 × 128 MRAMs. Type I adopts one PG transistor for a 256 × 256 MRAM. Type II adopts four PG transistors for four 128 × 128 MRAM subblocks. The maximum write bitwidth for Type III is 32 bits, whereas the maximum read bitwidth is 256 bits as for Types I and II.

nonvolatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed magnetoresis- tive random access memory (MRAM). The proposed architecture uses a network-on-chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable network interfaces allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is imple- mented with a sparse-neural-network approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65-nm technology, energy savings reach 87% when compared with an static random access memory-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable, and configurable implementation of memory-based computing. Index Terms-Database, magnetoresistive random access memory (MRAM), network-on-chip (NoC), power gating (PG), sparse neural networks (SNNs).

  Baghdadi is with Lab-STICC, 56100 Lorient, France, and also with IMT Atlantique, 29100 Brest, France.Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2018.2856458

	Networked Power-Gated MRAMs for
	Memory-Based Computing
	Jean-Philippe Diguet , Member, IEEE, Naoya Onizawa , Member, IEEE, Mostafa Rizk,
	Johanna Sepulveda, Member, IEEE, Amer Baghdadi, Senior Member, IEEE,
	and Takahiro Hanyu , Senior Member, IEEE
	Abstract-Emerging I. INTRODUCTION
	C OMPUTING resources are continuously increasing with technology progress, yet the use of the computing
	Manuscript received September 2, 2017; revised February 9, 2018 and
	May 4, 2018; accepted June 26, 2018. This work was supported in part
	by JSPS KAKENHI, Japan, under Grant JP16H06300, in part by the
	Region Bretagne CyAM Project, France, and in part by the MFC Project
	of Future and Rupture IMT Program, France. (Corresponding author:
	Jean-Philippe Diguet.)
	J.-P. Diguet is with CNRS, Lab-STICC, 56100 Lorient, France (e-mail:
	jean-philippe.diguet@univ-ubs.fr).
	N. Onizawa and T. Hanyu are with Tohoku University, Sendai 980-8577,
	Japan.
	M. Rizk is with Lab-STICC, STICC, 56100 Lorient, France, and also with
	Lebanese International University, Beirut, Lebanon.
	J. Sepulveda is with the Technical University of Munich, 80333 Munich,
	Germany.
	A.

TABLE II PERFORMANCES

 II OF 256 × 256 MRAMs USING THE TSMC 65-nm CMOS PROCESS AND THE MTJ MODEL[26]

TABLE III NUMBER

 III OF NEURONS PER CLUSTER IN YEAST DATABASE

TABLE VI PERCENTAGE

 VI OF STATIC POWER FROM TOTAL POWER CONSUMED IN THE CASE OF SEVEN MISSING FIELDS AND TWO MANAGERS

	TABLE IV
	HIT RATE
	TABLE V
	INJECTION RATE (FLITS/CLOCK CYCLE)

TABLE VII TIME

 VII PERCENTAGE OF THE ON STATE

TABLE VIII PERCENTAGE

 VIII OF POWER DISSIPATED WHILE WAKING UP IN FPG-MRAM FROM TOTAL POWER CONSUMED IN THE CASE OF SEVEN MISSING FIELDS AND TWO MANAGERS

	TABLE IX
	PERCENTAGE OF POWER DISSIPATED WHILE READING IN FPG-MRAM
	FROM TOTAL POWER CONSUMED IN THE CASE OF SEVEN
	MISSING FIELDS AND TWO MANAGERS
	TABLE X
	AVERAGE NOC POWER CONSUMPTION (mW)

  Table VII indicates the time percentage of ON state. Table

TABLE XI GLOBAL

 XI AVERAGE POWER CONSUMPTION-WORST CASE OF SEVEN MISSING FIELDS cases of reading 64 and 32 bits from MRAM Type III to reach 8.0 and 16.1, respectively.

Table 1 .

 1 Practical memristor devices.

	Voltage Range	Reference

Material

R ON (ohm) R OFF (ohm) R OFF /R ON Switching Speed

Table 2 .

 2 VTEAM fitting parameters for the device in[35].

	Parameter	Value	Parameter	Value
	R ON	1 kΩ	p	2
	R OFF	200 kΩ	α on

Table 3 .

 3 Comparison with previous approaches.

	Reference	Memristors CMOS Transistors Energy Steps Step Delay Energy.Delay
	(This work)	18	18	0.69 pJ	1	2.5 ns	1.72 pJ.ns
	MRL [9]	16	12	-	1	-	-
	MRL [42]	18	8	93.7 pJ	1	44.4 ns	4161 pJ.ns
	MAGIC [43]	9	Peripheral drivers	0.3 pJ	35	1.89 ns	19.84 pJ.ns
	MAGIC (Optimized no. of steps) [23]	10	Peripheral drivers	3.16 pJ	13	1.3 ns	53.40 pJ.ns
	MAGIC (Area optimized) [23]	5	Peripheral drivers	3.16 pJ	15	1.3 ns	61.62 pJ.ns
	MAGIC [44]	15	Peripheral drivers	0.68 pJ	13	1.12 ns	9.94 pJ.ns
	MAGIC (Naive mapping) [24]	15	Peripheral drivers	0.68 pJ	12	1.43 ns	11.66 pJ.ns
	MAGIC (Compact mapping)[24]	24	Peripheral drivers	0.89 pJ	16	1.43 ns	20.36 pJ.ns
	IMPLY [45]	6	Peripheral drivers	-	23	5 ns	-
	IMPLY (Semi-serial) [46]	8	Peripheral drivers	-	12	30 µs	-
	IMPLY (Semi-parallel) [47]	5	Peripheral drivers	-	17	50 µs	-

  The architecture employs the advanced quantization algorithm of BNN and the promising MOL-based in-memory computing technique which is well adapted for parallel bit-wise operations. This research work has been published in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems[START_REF] Ali | MOL-based in-memory computing of binary neural networks[END_REF].

	Memristive Computational Memory Using
	Memristor Overwrite Logic (MOL)
	Khaled Alhaj Ali , Graduate Student Member, IEEE, Mostafa Rizk, Amer Baghdadi , Senior Member, IEEE,
	Jean-Philippe Diguet , Senior Member, IEEE, Jalal Jomaah, Naoya Onizawa , Member, IEEE,
	and Takahiro Hanyu, Senior Member, IEEE

TABLE II ADOPTED

 II VARIABLES AND PARAMETERS FOR PMA MTJ DEVICE

  Reading a single MTJ device requires a sensing voltage V r and a reference resistor R Ref connected in series with a MOSFET. The total resistance of this 1T1R cell is R

	TABLE III
	ENERGY CONSUMED BY A COMPUTATIONAL OPERATION
	b) Read-energy:

TABLE IV SPECIFICATIONS

 IV

TABLE V COMPARISON

 V OF DIFFERENT LOGIC FAMILIES FOR N -BIT ADDITION IN TERMS OF AREA, LATENCY, AND ENERGY CONSUMPTION sic resistive MAJ operation. Shirinzadeh et al.[15]

  Manuscript received August 23, 2021; revised November 30, 2021 and February 13, 2022; accepted March 4, 2022. (Corresponding author: Khaled Alhaj Ali.) Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, and Mathieu Léonardon are with IMT Atlantique, Lab-STICC, UMR CNRS 6285, 29238 Brest, France (e-mail: khaled.alhajali.lb@gmail.com). Mostafa Rizk is with IMT Atlantique, Lab-STICC, UMR CNRS 6285, 29238 Brest, France, also with the School of Engineering, International University of Beirut, Beirut 1105, Lebanon, and also with the Physics Department, Faculty of Sciences, Lebanese University, Beirut 1105, Lebanon. Jean-Philippe Diguet is with IRL CROSSING CNRS, Adelaide, SA 5000, Australia. Color versions of one or more figures in this article are available at https://doi.org/10.1109/TVLSI.2022.3163233. Digital Object Identifier 10.1109/TVLSI.2022.3163233 is the requirement for a substantial amount of computation and memory. For instance, the VGG-19 network exhibits over 140 million floating-point (FP) parameters and requires more than 15 billion FP operations in order to classify one image [4]. Embedding such networks in traditional cores that deploy the von Neumann model (e.g., CPUs and GPUs) poses significant problems in terms of execution speed and power consumption. Massive intermediate data are produced during CNN execution revealing intensive I/O data congestion between memory and processing cores causing a real bottleneck.

TABLE I ENERGY

 I CONSUMED PER 34-BIT WIDTH OPERATION IN CMEM (IN pJ)

TABLE II PERFORMANCE

 II IS COMPARED WITH STATE-OF-THE-ART DESIGNS FOR THE CIFAR-10 BNN MODEL

TABLE III NUMBER

 III OF PERIPHERAL COMPONENTS PER CMEM UNIT

TABLE IV NUMBER

 IV OF COMPONENTS IN EACH NMU

Table 1 .

 1 Effect of approximate computing techniques on classification accuracy.

	Approximate Computing Technique	Accuracy (%)
	None (Exact SVM) 10% Data Set Reduction 20% Data Set Reduction 30% Data Set Reduction Loop perforation with sf = 2 Loop perforation with sf = 3 Loop perforation with sf = 4 DFM (24-bit) DFM (16-bit)	90.47 90.47 80.95 80.95 90.47 85.71 80.95 85.71 75

Table 2 .

 2 FPGA performance profile of Exact and Approximate SVM.

		FF	LUT	DSP	BRAM	SRL	Time Latency (s)	Power Consumption (W)	Energy per Classification (J)	Classification Accuracy (%)
	Exact SVM Approximate SVM Boosted Approximate SVM	37057 17,187 17,197	42261 25,558 25,588	475 283 284	297 291 292	1060 202 203	2.4 0.91 0.75	6.3 3.12 3.2	15.12 2.83 2.4	90 86 86
	Approximate to Exact Reduction Boosted Approximate to Exact Reduction	53.62% 39.5% 53.59% 39.45% 40.21% 40.4%	2.02% 1.68%	80.94% 80.84%	2.64× 3.2×	50.4% 49.2%	81.28% 84.12%	-4% -4%

  Hamoud Younes, Ali Ibrahim, and Maurizio Valle are with the Department of Electrical, Electronic and Telecommunications Engineering and Naval Architecture, University of Genova, 16145 Genova, Italy E-mails: hamoud.younes, ali.ibrahim, maurizio.valle@unige.it Hamoud Younes, Ali Ibrahim, and Mostafa Rizk are with the Department of Computer and Communication Engineering, Lebanese International University, Lebanon E-mails: hamoud.younes, ali.ibrahim, mostafa.rizk@liu.edu.lb Fig. 1. Approximate Computing Techniques (ACTs)

  as depicted in Algorithm 2. These optimizations are summarized as follows:

	Algorithm 2: kNN Design Optimization
	#pragma HLS ARRAYMAP variable=Distance Instance=AllPatterns horizontal variable=Modality Instance=AllPatterns horizontal
	/ * M: nb of features function UDC(T 1 , T 2 ): for i ←0 to M do #pragma HLS UNROLL factor=4 Execute (1)	* /
	/ * Tactiles: trainingset, q: testing point * / / * N: nb of training points * / for i ←0 to N do #pragma HLS INLINE #pragma HLS UNROLL factor=6 Distance[i]= UDC(p, Tactiles[i]) Modality[i]=Tactiles[i][16]
	/ * K: nb of Neighbors NearestNeighbors=Selector(K, Modality) for i ←0 to K do #pragma HLS UNROLL if N earestN eighbors[i] == 1 then modality1count++ else	* /

  Manuscript received March 31, 2021; revised June 11, 2021 and July 8, 2021; accepted July 25, 2021. This work was supported in part by the TACTIle feedback enriched virtual interaction through virtual realITY and beyond (TACTILITY) Project under Grant EU H2020 and Grant Topic ICT-25-2018-2020, Research and Innovation Actions (RIA) Proposal ID 856718. This article was recommended by Associate Editor P. K. Meher. (Corresponding author: Hamoud Younes.) Hamoud Younes and Ali Ibrahim are with the Department of Electrical, Electronic and Telecommunications Engineering and Naval Architecture, University of Genova, 16145 Genova, Italy, and also with the Department of Computer and Communication Engineering, Lebanese International University, Beirut 146404, Lebanon (e-mail: hamoud.younes@edu.unige.it; ali.ibrahim@edu.unige.it). Mostafa Rizk is with the Department of Computer and Communication Engineering, Lebanese International University, Beirut 146404, Lebanon (e-mail: mostafa.rizk@liu.edu.lb). Maurizio Valle is with the Department of Electrical, Electronic and Telecommunications Engineering and Naval Architecture, University of Genova, 16145 Genova, Italy (e-mail: maurizio.valle@unige.it). Color versions of one or more figures in this article are available at https://doi.org/10.1109/TCSI.2021.3102303. Digital Object Identifier 10.1109/TCSI.2021.3102303 Fig. 1. Computational Complexity of the Tensorial SVM algorithm.

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TABLE I COMPLEXITY

 I

ASSESSMENT UNDER DIFFERENT ACTIVATION FUNCTIONS

TABLE III BEST

 III MODEL PERFORMANCE COMPARED TO ONE-SIDED JACOBI compared to 32 elements (16 × 2) for the input dimension (20 × 16), which justifies the longer training time required (higher number of epochs). However, the training can be shortened into 250 and 100 epochs for output dimensions (80 × 4) and (16 × 2) respectively.

TABLE V NN

 V

-BASED TSVM OPERATING MODES

TABLE VI IMPLEMENTATION

 VI RESULTS FOR TENSORIAL SVMTable VI presents the implementation details of both the NN-based TSVM and Jacobi-based SVM for N t = 200

  Maritime search and rescue (SAR) missions are crucial for most coastal states. According to the International Organization for Migration 218,062 irregular maritime migration attempts are recorded in the Mediterranean Since 2014 [231]. From which, 23,939 dead and missing persons are recorded during attempted overseas crossings. Furthermore, the European Maritime Safety Agency reports in the Annual Overview of Marine Casualties and Incidents 2021

1.2. PROFESSIONAL EXPERIENCES

Design Automation Conference (DAC), 2016

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6.4. HYBRID MEMRISTOR-CMOS DESIGN FOR LOGIC COMPUTATION

Electronics, 2021Electronics 2021, 10, 1018

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This research topic aims to include the Human in the loop, namely designing an interactive (AI ◁▷ Human) solution rather than a machine providing visual notifications or applying human commands. The originality of this topic concerns the use of interactive annotations 239

Manuscript received February 26, 2020; revised May 11, 2020 and June 17, 2020; accepted July 10, 2020. This work was presented at the 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), November 2019, Genoa, Italy. (Corresponding author: Khaled Alhaj Ali.) Khaled Alhaj Ali and Amer Baghdadi are with IMT Atlantique, CNRS Lab-STICC Laboratory, 29238 Brest, France (e-mail: khaled.alhaj-ali@ imt-atlantique.fr). Mostafa Rizk is with IMT Atlantique, 29285 Brest, France, also with the School of Engineering, International University of Beirut, Beirut 1105, Lebanon, and also with the Physics Department, Faculty of Sciences, Lebanese University, Beirut 1003, Lebanon. Jean-Philippe Diguet is with the CNRS Lab-STICC Laboratory, 56100 Lorient, France. Jalal Jomaah are with the Physics Department, Faculty of Sciences, Lebanese University, Beirut 1003, Lebanon. Naoya Onizawa and Takahiro Hanyu are with the Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577 Japan. Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2020.3011522

ACKNOWLEDGEMENT

The authors acknowledge partial financial support from TACTIle feedback enriched virtual interaction through virtual realITY and beyond (TACTILITY) project: EU H2020, Topic ICT-25-2018-2020, RIA, Proposal ID 856718.

Funding: This research was partially funded by Carnot TSN-IMT Atlantique through the FLEX-DEM project.

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Abbreviations

The

to the next register, and so on. At the end of step 2, the K minimum distance values are saved in the K registers in the order min1 < min2 < ..... < minK.

• Step 3: Each distance value V 2[i] is compared to the highest minimum i.e. minK as shown in Figure . 3 (K=3).

If it is larger, the minimums obtained from V 1[i] are not updated and a new value of V 2 is fetched. Else, V 2[i] is compared to the other minimums to reach a register to occupy. Once V 2[i] occupies a register, the old value of that register is shifted to occupy the register of the next minimum. The advantage of this architecture compared to the one presented in [14], is that if V 2[i] is greater than minK, step 3 will not be executed. Thus, the K minimum distances are the output of step 2. This will result in a reduced selection time for hardware implementations. Moreover, the architecture in [14] selects the K minimum distances in a single step, which imposes hardware complexity and increased time latency for large datasets. While in the proposed architecture, the selection is performed in two smaller steps with a high probability that the third step will not be executed (V 2[i] > minK). Although the proposed selector finds the K-nearest neighbors without sorting the entire vector, a comparison with two sorters reported in the literature, i.e. QuickSort [12] and Bitonic Sorter Fig. 3. Sorting Process Step 3 (K=3): Dashed Line (new value), Solid Line (old value), Colored Lines (concurrent operations) [21], has been carried out. In general:

• Bitonic sorting is a recursive algorithm that sorts a Bitonic sequence in a parallel operating fashion. A Bitonic sequence is a sequence of M elements in which L elements out of M are sorted in ascending form, and the other M -L elements are sorted in descending order [22]. If the sequence is not Bitonic, an additional task is imposed before the ability to sort the vector. The proposed selector can operate on any vector form.

• QuickSort selects one of the elements in the sequence to be the pivot and divides the sequence into two sequences one with all elements less than the pivot while the other contains all the elements greater than the pivot. The process is recursively (add more burden on the hardware) applied to each of the sub sequences. QuickSort has a worst-case complexity of O(n 2 ) when the given sequence is sorted; this resembles the best-case scenario for the proposed selector as it will select the K minimums faster (the minimums occupy the first K registers). Then all the comparisons fail thus no shift operations are performed. Consequently, step 3 is not executed at all.

• The number of comparators required by the selector depends on the number of neighbors K, while it depends on the size of the vector N in the case of Bitonic and QuickSort. In machine learning applications, usually, it is valid that K (the number of Nearest Neighbors in kNN) N (size of training vector). Given that the selector doesn't sort the complete vector, the number of comparisons is decreased.

Both the sorters presented in [12], [21], and the selector Maurizio Valle (Senior Member, IEEE) received the M.S. degree in electronic engineering and the Ph.D. degree in electronics and computer science from the University of Genova, Italy, in 1985 and 1990, respectively. Since December 2019, he has been a Full Professor of electronics with the DITEN, University of Genova, where he leads the Connected Objects, Smart Materials, Integrated Circuits-COSMIC Laboratory. He has been and is in charge of many research contracts and projects funded at local, national, and European levels and by Italian and foreign companies. He is the coauthor of more than 200 articles on international scientific journals and conference proceedings. His research interests include bio-medical circuits and systems, electronic/artificial sensitive skin, tactile sensing systems for prosthetics and robotics, neuromorphic touch sensors, and electronic and microelectronic systems. He is a member of the IEEE CAS Society.