Michael Kraemer
email: mkraemer@laas.fr

Daniela Dragomirescu

Robert Plana

Design of a Very Low-power, Low-cost 60 GHz Receiver Front-End Implemented in 65 nm CMOS Technology

come

Design of a Very Low-power, Low-cost 60 GHz Receiver

Front-End Implemented in 65 nm CMOS Technology

The very first 60 GHz receiver front-ends in CMOS technology by Razavi in 2005 [START_REF] Razavi | A 60-GHz CMOS receiver front-end[END_REF] and Alldred et al. in 2006 [2] consisted only of an LNA, a mixer, and, in the latter case, associated LO and IF buffers. While the receiver front-end presented by Razavi exhibits a quite low power consumption, it does not include such power-hungry elements as the LO and IF buffers and the VCO [START_REF] Razavi | A 60-GHz CMOS receiver front-end[END_REF].

More complete front-ends that also include a means to generate the LO signal were published subsequently. While [START_REF] Emami | A highly integrated 60GHz CMOS front-end receiver[END_REF][START_REF] Sanduleanu | CMOS integrated transceivers for 60GHz UWB communication[END_REF][START_REF] Lee | A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly[END_REF][START_REF] Bozzola | A sliding IF receiver for mm-wave WLANs in 65nm CMOS[END_REF][START_REF] Vecchi | A wideband mm-wave CMOS receiver for Gb/s communications employing interstage coupled resonators[END_REF] present the integration of an on-chip VCO together with a downconverter, a phase locked loop (PLL) was integrated in [START_REF] Mitomo | A 60-GHz CMOS receiver front-end with frequency synthesizer[END_REF][START_REF] Chen | A dual-band 61.4-63GHz/75.5-77.5GHz CMOS receiver in a 90nm technology[END_REF]. These realizations allow a more realistic comparison of the front-end power consumption, because the trade-off between the LO-power available to the mixer and the power consumption of VCO and mixer is done on-chip.

Note that also complete 60 GHz CMOS radios have been published and are even commercially available. However, they usually are not optimized with respect to power consumption. To the best of the author's knowledge, the transceiver by Marcu et al. [START_REF] Marcu | A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry[END_REF] presents the lowest power consumption at this high level of integration for a 60 GHz radio.

The work presented in the following concentrates on the front-end, as it is the part mainly responsible for the circuit's power consumption [START_REF] Marcu | A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry[END_REF]. A comparison to circuits exhibiting a comparable level of complexity, given in section V., shows that the results with respect to power consumption presented in this paper constitute record values. The achieved minimization is accomplished by a systematic design for low required LO-power (mixer), high efficiency (VCO) and low dissipated DC power (LNA). Furthermore, the use of a direct conversion architecture allows for a low device count and thus low complexity.

As second issue addressed by the design presented in this paper is the minimization of chip area: as many RFIC designers still follow the MMIC paradigm, mm-wave designs are often based on distributed elements for matching, which results in large circuit size and thus high fabrication cost. To minimize circuit area, however, spiral inductors shall be employed [START_REF] Dickson | 30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits[END_REF][START_REF] Kraemer | Accurate electromagnetic simulation and measurement of millimeter-wave inductors in bulk CMOS technology[END_REF]. This paper shows that if the use of spiral inductors coincides with a low complexity direct conversion architecture, a record value for the receiver front-ends circuit size can be achieved.

The remainder of this article is organized as follows: First, section II gives an overview of the realized circuit and briefly discussed its basic building blocks and how they contribute to the front-ends low power consumption. Next, section III shows the fabricated circuit. In section IV, the obtained measurement results are discussed. These results are compared to the state-of-the-art in section V. Finally, a conclusion is drawn.

II. 1 B 1 7 B Circuit Design

The receiver front-end presented in this paper consists of the in-phase branch of a direct conversion receiver. This circuit is part of a research effort aiming to integrate a complete 60 GHz I/Q transceiver front-end in 65 nm CMOS technology. While the final version of this transceiver allows receiving a quadrature-modulated signal, the presented receiver front-end only allows the reception of simpler, less spectrally efficient modulations.

The block-diagram of the realized receiver front-end is illustrated in Fig. 1. Its off-chip interfaces consist of a single-ended 60 GHz RF input, a differential baseband (BB) output, and DC connections for the four bias voltages, the oscillator's control voltage, the 1 V power supply and ground. The following sub-sections discuss the key building blocks (LNA, down-mixer, VCO and baseband and LO buffers) that constitute the receiver front-end. Their circuit schematics are given together with some key figures describing their performance. The aspects of their design that concern the front-end's power consumption are also brought up. Standalone -versions of these blocks have been separately fabricated and measured before receiver integration. The results obtained from their measurements are published in [START_REF] Kraemer | A low-power high-gain LNA for the 60GHz band in a 65 nm CMOS technology[END_REF] for the LNA, [START_REF] Kraemer | A high efficiency differential 60 GHz VCO in a 65 nm CMOS technology for WSN applications[END_REF] for the VCO and [START_REF] Kraemer | A wideband single-balanced down-mixer for the 60 GHz band in 65 nm CMOS[END_REF] for the down-mixer. To integrate these building blocks to form the front-end of figure Fig. 1., the matching networks at their interfaces have been adapted accordingly. Furthermore, they are surrounded by grounded walls consisting of shunted metal layers that allow the isolation of adjacent building blocks.

LNA RF BB BB LNA V control VCO V bias1 V bias2 V bias3 V bias4 V DD mixer

A)

6 B 2 2 B The Low Noise Amplifier (

) 1
It illustrates that the receiver noise can be minimized only if the LNA has a low noise figure and high gain, the latter to decrease the influence of the subsequent stages on the noise performance. To achieve the optimization of these two parameters at the same time, a twostage cascode LNA with the schematic given in Fig. 2. is employed. Its input stage is simultaneously noise and power matched by sizing the input transistor M1 and employing inductive source degeneration [START_REF] Kraemer | A low-power high-gain LNA for the 60GHz band in a 65 nm CMOS technology[END_REF].

The cascode topology is preferred over a common source stage in order to increase reverse isolation, which is necessary to ensure unconditional stability and parasitic LO leakage from the mixer to the antenna. While the LNA has a certain influence on the receiver linearity, it is the subsequent stages that are decisive in this regard. Thus, as power consumption is directly related to the linearity of the LNA (but does, in a first order consideration, not depend on the gain of the LNA), it can be minimized by sizing the transistors to yield minimum noise (first stage) or maximum power gain (second stage) for low bias currents. The measured performance of the standalone LNA is summarized in table 1. It stems from a redesigned version of the LNA presented in [START_REF] Kraemer | A low-power high-gain LNA for the 60GHz band in a 65 nm CMOS technology[END_REF] which operates at a slightly higher center frequency. An in-detail discussion of the performance of the initial LNA is given in [START_REF] Kraemer | A low-power high-gain LNA for the 60GHz band in a 65 nm CMOS technology[END_REF].

B) 7 B 2 3 B The Down-conversion Mixer

When designing a low-power mixer circuit, two kinds of power consumption have to be taken into account: the dissipated DC power P DC and the local oscillator power P LO necessary for abrupt switching. Of these two powers, the latter one is by far the most expensive one in terms of overall receiver power consumption, as the on-chip oscillator used to generate the LO signal is usually of very low efficiency.

Besides power consumption, the Friis equation has to be respected, demanding high gain and low noise figure to minimize overall receiver performance. Furthermore, the down-mixer is the component limiting the receiver linearity, thus, it has to be optimized in this regard as well. To find an optimum compromise between all of these requirements, the single-balanced mixer shown in Fig. 3. is employed [START_REF] Kraemer | A wideband single-balanced down-mixer for the 60 GHz band in 65 nm CMOS[END_REF]. An active mixer has been chosen to obtain conversion gain and limit the required LO power. The input stage is simultaneously noise and power matched as in the case of the LNA.

R 1 R 1 C 1 C 1 L D L B R B V DD V DD LO LO IF IF RF M1 M3 M2 V DD C B L 1 C 2 L 1 C 2 L 3 L 4 L 2
The most important design technique ensuring the good performance of this mixer is current bleeding by the means of the inductor L B and the resistor R S [START_REF] Kraemer | A wideband single-balanced down-mixer for the 60 GHz band in 65 nm CMOS[END_REF]. As part of the bias current of M1 by-passes M2 and M3, the lower transistor M1 can provide high transconductance, while the switching pair is made up of small transistors that require only low LO power for fast switching. Furthermore, the bleeding inductor resonates the parasitic capacitances at the terminal common to all of the transistors, thus increasing conversion gain.

Note also the use of the capacitor C 1 that short-circuits the resistive loads for the LO and RF signal. This allows for high LO and RF to baseband isolation and increases linearity and conversion gain.

The presented mixer exhibits an excellent compromise between all requirements over the whole unlicensed 60 GHz band. They are discussed in [START_REF] Kraemer | A wideband single-balanced down-mixer for the 60 GHz band in 65 nm CMOS[END_REF] and summarized in table 2. Note that these measurements result from a standalone version with baseband buffer (cf. Fig. 5a). The mixer's key performance, if a low-power receiver is desired, is the very low required LO power of only -5 dBm. Rather than minimizing the DC power consumption of the VCO, its efficiency, i.e. P out / P DC , has to be optimized to achieve a low-power receiver front-end. Otherwise, subsequent, powerhungry buffer stages become necessary. The VCO used for this purpose is given in Fig. 4. [START_REF] Kraemer | A high efficiency differential 60 GHz VCO in a 65 nm CMOS technology for WSN applications[END_REF]. Due to the use of a differential Colpitts architecture based on cross-coupled common-source transistors, the amplitudelimiting nonlinearity affects the behavior of the VCO only for quite high output powers. Thus, output power is higher than for other oscillator architectures at a given DC power consumption.

V control L tail L tank VDD C 2 C 1 M 2 C 2 C 1 M 1 Vbias L 1 C pad V DD V y L L2 L L1 C c L 1 C pad V DD V x L L2 L L1 C c
The VCO employs an octagonal 155pH inductance with differential Q of 19.1 at 60 GHz in the resonator. The frequency tuning is accomplished by differentially tuned accumulation-MOS varactors. A source-follower output buffer is attached to the oscillator core.

Further details on the design of the VCO are discussed together with the obtained results in [START_REF] Kraemer | A high efficiency differential 60 GHz VCO in a 65 nm CMOS technology for WSN applications[END_REF]. Table 3 summarizes the performance of the VCO. Its record efficiency is one of the main reasons for the very low power consumption of the entire receiver, while the limited tuning range can be optimized by optimizing the (full-custom) varactor design.

D) 9 B 2 5 B The LO and baseband buffers

In addition to the fundamental building blocks like LNA, mixer and oscillator, buffer amplifiers are employed in the receiver front-end. Their schematics are given in Figures 5a and5b.

V DD L 2 M 1 M 2 R F LO IN L S C F V DD L 2 L 1 C 1 LO out L 1 C 1 LO out LO IN R 1 R 1 C 1 C 1 R m V DD V DD IN OUT OUT M1 M3 M2 V DD IN M1' V DD L V DD L Fig. 5a. Second LO buffer Fig. 5b. Baseband output buffer
The LO buffer is used to further increase the LO power level at the input of the down-mixer and to increase common-mode rejection in the LO signal path by means of the tail impedance consisting of C F and R F . It is based on a differential common-source amplifier. Due to the low LO power requirements of the mixer this buffer is not essential, but is integrated in view of a later quadrature receiver. In the receiver at hand it is biased at very low bias current.

The baseband buffer of Fig. 5b is added to the baseband output of the mixer. It is necessary to drive the differential 100 Ω load, which is encountered if characterizing the receiver front-end using a measurement setup with instruments that exhibit single-ended 50 Ω input impedances.

It is based on a current-mirror biased differential pair. The load impedances consist of an onchip R-C load (which filters LO and RF signals) and a large off-chip inductance that allows biasing the buffer transistors without suffering from the large voltage drop that would occur if the bias current would pass by the resistors.

The baseband buffer consumes 14 mW due to the large current required by the lowimpedance load. In a more complete integrated receiver circuit, it shall be replaced by a variable gain amplifier (VGA) with high impedance load, achieving much lower power consumption (<5mA) while exhibiting huge, variable gain (>50 dB).Thus, the front-end's power consumption can be considered 14 mW lower, if it is integrated with the baseband circuit.

III. 2 B 1 8 B THE FABRICATED FRON-END CIRCUIT

Fig. 6. shows the die photograph of the fabricated receiver frontend. Its very small size of 0.550 mm² is essentially pad-limited: the aligned circuit blocks without pads are only about 200 μm wide. This is the result of using a total of 17 compact spiral inductors for matching.

The number of pads can further be reduced because multiple VDD and ground connections are provided (see the respective symbols in Fig. 6.). These redundant connections are not essential for the operation of the receiver due to its low supply current (about 43 mA). Furthermore, the bias voltages could be derived from V DD in a redesigned version, allowing to remove four more pads. The part of the circuit shown at the right in Fig. 6., which consists of the differentially implemented parts, is very symmetric to reduce mismatch and improve isolation.

Fig. 6. Microphotograph of the fabricated CMOS receiver front-end

IV. 3 B 1 9 B MEASUREMENT RESULTS

The receiver front-end was characterized on-wafer using a 67GHz single-ended 100 μm G-S-G Picoprobe to provide the RF signal and a differential G-S-G-S-G probe of the same type to measure the baseband output. The DC voltages were connected using two eyepass sixfinger probes. The measurements were done using either an Anritsu MS4647A 70GHz VNA to obtain the return loss. In this case, one of the differential baseband outputs was matched to 50Ω by a precision load. Or, for conversion measurements, an Agilent E8257D 67GHz synthesizer served as signal source and a LeCroy SDA813Zi 13GHz real time oscilloscope with spectrum analyzer functionality was connected to the circuit's differential baseband output. The loss due to cable and probes is de-embedded and 3 dB is added to the output power in case of single ended measurements.

A) 1 0 B 2 6 B Power Consumption

The receiver front-end is biased at the optimum current densities of the circuit components by applying bias voltages of V bias1 = 460mV, Vbias2 = 390mV, Vbias3 = 510mV and Vbias4 = 540mV. It draws about 43mA from a 1V supply, thus consuming P DC = 43mW. This power consumption can be reduced by the amount contributed by the baseband buffers (i.e. ≈ 14mA, cf. section 4.4) in an integrated version, because the BB output usually does not have to drive two 50Ω loads but a variable gain amplifier with high impedance inputs. Thus, VCO, LO buffers, down-mixer and LNA together consume only 29mW.

B) 1 1 B 2 7 B In-and Output Return Loss

The return loss at the RF input and the baseband output of the receiver front-end were measured at the above mentioned bias point with a control voltage of V control = 0 V, corresponding to a LO frequency of about f 0 = 57.5GHz. However, the oscillation frequency does not have any influence on the return loss, as both input and output of the receiver are very well isolated from the LO.

The left part of figure 7 shows the measured excellent, broadband input match which lies below -10 dB from 53.1GHz up to 66.0 GHz. A minimum return loss of -42.7 dB is achieved at 58.9 GHz. The measured return loss at the baseband output of the receiver front-end, shown in the right part of figure 7, is about -17.4 dB within the entire required baseband bandwidth of about 1 GHz, and stays below -10 dB up to 12.5 GHz. As for the VCO presented above, the frequency tuning range of the receiver is about 3 GHz. However, the absolute oscillation frequencies have slightly shifted for the complete receiver. They lie between 57.0GHz and 60.0GHz for a control voltage between 0.15V and -3V. This can be explained by the different loads connected to the VCO and the fact that automatic dummy insertion was done differently between the fabrication runs of the standalone VCO and the receiver front-end.

D) 1 3 B 2 9 B Conversion Gain

To measure the receiver's conversion gain, a low-power sinusoidal signal is injected at the RF port of the receiver front-end. In the lower sideband (LSB), this signal lies f IF below the carrier frequency, in the upper sideband (USB) this signal is f IF above f LO . The ratio between the received power at the differential baseband output and the injected signal power is denoted as power conversion gain G C in the following. (Note that due to the use of very high impedances at the baseband output, receivers in literature often report the voltage conversion gain [START_REF] Razavi | A 60-GHz CMOS receiver front-end[END_REF], which in these cases is considerably higher than the power conversion gain).

Fig. 8. (left) plots the conversion gain in the LSB and USB for baseband frequencies of 1GHz and 2 GHz. A maximum power conversion gain of 29.5 dB is achieved for a baseband frequency of f IF =1 GHz. In agreement with the input return loss and the characteristic of the LNA, the LO frequency for which both sidebands have the same conversion gain is about 58.75 GHz. The 3 dB RF bandwidth of the receiver, which is limited by the response of the LNA, reaches from about 56.5GHz to about 61.5 GHz, thus spanning 5GHz in the lower part of the unlicensed 60GHz band. The LO frequency range considered is limited by the oscillator's tuning range. It illustrates that within the bandwidth of 1.88GHz around the carrier, which is required by the different standards, quite high values between 26 dB and 30 dB are achieved at all possible LO frequencies. For the central LO frequency of f LO =58.5 GHz, the one-sided 3 dB baseband bandwidth is measured to be about 1.5 GHz, corresponding to a channel bandwidth of 3GHz around the carrier. The receiver's bandwidth is not limited by the baseband circuitry or the mixer, but rather by the characteristics of the LNA, which results in the fact that input signals above and below the center frequency of 58.5GHz experience less gain.

G C in dB f LO in GHz LSB, f IF =1 GHz USB, f IF =1 GHz LSB, f IF =2 GHz USB, f IF =2 GHz

E) 1 4 B 3 0 B Output Waveforms

To analyze the balance of the differential signal at the baseband output of the receiver, the voltage waveforms were measured for different frequencies and input powers. Fig. 9. shows this signal at both baseband outputs when the frequency difference is 1 GHz. Even at this relatively high frequency, the phase shift of 180° is well maintained, while variations occur due to the phase variations of the unlocked VCO. For lower baseband frequencies, the voltage waveforms are even better balanced. The linearity of the receiver front-end is characterized by its 1 dB compression point P -1dB . Fig. 10. plots power conversion gain and output power versus input power to obtain its value: it shows that the receiver achieves an output-referred compression point OP -1dB =-11 dBm, which corresponds to an input-referred compression point of IP -1dB =-36 dBm. This quite low value at the input of the receiver results from the high conversion gain and the moderate linearity of the output buffer. However, as both the received in-band power and the interference power level at the receiver input are expected to lie well below this value, this compression point is sufficient for a 60GHz receiver and helps to keep power consumption low.

- The front-ends achieving the best performance for each column are highlighted. The comparison shows that the first strength of the proposed implementation is its very low power consumption of only 43mW (which is even lower, i.e. 29 mW, without the baseband buffers). This value is lower than that of other receiver front-ends of comparable complexity. The second strength is the very small size of the presented implementation, which originates from the use of spiral inductors and the realization in 65nm technology. Furthermore, the achieved conversion gain of 30 dB compares very favorable to the state of the art. As the noise figure of the receiver could not be measured, a final statement is not possible with respect to this characteristic. However, the simulated value indicates that the circuit also achieves good noise performance.

Regarding the realized bandwidth, the table shows that most of the receiver front-ends only cover parts of the unlicensed 60GHz band. The proposed realization is no exception. With 5GHz it exhibits a typical performance in this regard. The weak point with respect to the state of the art of the presented front-end is its linearity, quantified by an input-referred compression point of only -36 dBm. This low value can be explained by the front-end's low supply voltage of 1.0V and its high conversion gain, which results in a saturation of the output stages. However, for the application of the front-end this is not critical, as the received input power is not expected to ever attain this compression point. An important point in low-power 60 GHz receiver design is to correctly predict the expected maximum input signal (usually originating from interference) and adjust the required linearity accordingly, as it is directly related to the achievable minimum power consumption.

VI. 5 B 2 1 B CONCLUSION

This paper presented the design and implementation of a low-power low-cost receiver frontend for the unlicensed 60 GHz band in 65 nm CMOS technology. With its record-low power consumption of only 43 mW (29 mW without the baseband buffers that are used to drive 50 Ω loads and are not necessary in a high-impedance integrated baseband), its record-small circuit size of 0.55 mm², its RF bandwidth spanning from 56.5 to 61.5 GHz and its very high conversion gain of 30 dB it compares very favorable to the state-of-the art.

This paper shows that to achieve this kind of results, the design of the 60 GHz building blocks must be optimized with respect to efficiency and both DC and LO power consumption (the latter in the case of the mixers). Furthermore, the interfaces between the blocks need not only to be power-matched to each other, but also the power levels at these interfaces need to be accounted for to optimize overall system performance. Furthermore, the use of spiral inductors, rather than distributed elements, is essential for achieving small circuit size.

List of figures and tables

Fig. 1 .

 1 Fig. 1. Block diagram of the realized front-end with interfaces.

Fig. 2 .

 2 Fig.2. Circuit schematic of the employed LNA[START_REF] Kraemer | A low-power high-gain LNA for the 60GHz band in a 65 nm CMOS technology[END_REF]

Fig. 3 .

 3 Fig. 3. Circuit schematic of the employed Down-conversion mixer.

Fig. 4 .

 4 Fig. 4. Circuit schematic of the VCO with integrated common-drain buffer

Fig. 7 .

 7 Fig. 7. Measured in-and output return loss of the receiver front-end

Fig. 8 .

 8 Fig.8. Measured conversion gain G C of the receiver front-end Fig.8(right) plots the conversion gain versus RF input frequency for different LO frequencies. It illustrates that within the bandwidth of 1.88GHz around the carrier, which is required by the different standards, quite high values between 26 dB and 30 dB are achieved at all possible LO frequencies. For the central LO frequency of f LO =58.5 GHz, the one-sided 3 dB baseband bandwidth is measured to be about 1.5 GHz, corresponding to a channel bandwidth of 3GHz around the carrier. The receiver's bandwidth is not limited by the baseband circuitry or the mixer, but rather by the characteristics of the LNA, which results in the fact that input signals above and below the center frequency of 58.5GHz experience less gain.

Fig. 9 .F) 1 5 B 3 1 B

 9151 Fig. 9. Measured baseband output voltages for f LO =58 GHz, f RF =59 GHz and P RF =-45dBm

Fig. 10 .

 10 Fig. 10. Measured output versus input power of the receiver front-end

Fig. 1 . 4 . 6 . 7 . 8 . 9 .

 146789 Fig. 1. Block diagram of the realized front-end with interfaces. Fig. 2. Circuit schematic of the employed LNA Fig. 3. Circuit schematic of the employed Down-conversion mixer Fig. 4. Circuit schematic of the VCO with integrated common-drain buffer Fig. 5a. Second LO buffer Fig. 5b. Baseband output buffer Fig. 6. Microphotograph of the fabricated CMOS receiver front-end Fig. 7. Measured in-and output return loss of the receiver front-end Fig. 8. Measured conversion gain G C of the receiver front-end Fig. 9. Measured baseband output voltages for f LO =58 GHz, f RF =59 GHz and P RF =-45dBm Fig. 10. Measured output versus input power of the receiver front-end

Table 1 .

 1 Performance summary of the LNA

	Parameter	Value
	Center frequency	58.3 GHz
	Transducer power gain	16.8 dB
	IP -1dB	-25 dBm
	NF (simulated)	5.2 dB
	V DD	1V
	P DC	11 mW
	Area (pad-limited)	0.4 × 0.4 mm²

Table 2 :

 2 Performance summary of the down-mixer

	Parameter	Value
	RF frequency range	54 -65 GHz
	IF frequency range	0 -2 GHz
	Max. power conversion gain	9.1 dB
	OP -1dB	-5 dBm
	NF (DSB, simulated)	9 dB
	V DD	1V
	P LO	-5 dBm
	P DC (incl. buffer)	16.8 mW
	Area (pad-limited)	0.49 × 0.52 mm²
	C)

8 B 2 4 B The Voltage-Controlled Oscillator

Table 3 :

 3 Performance summary of the VCO[START_REF] Kraemer | A high efficiency differential 60 GHz VCO in a 65 nm CMOS technology for WSN applications[END_REF].

	Parameter	Value
	Frequency tuning range	57.58-60.8 GHz
	Minimum Phase Noise	-90.3 dBc/Hz @ 1MHz
	V DD	1V
	P out	-0.9 dBm
	P DC (incl. buffer)	16.5 mW
	P out / P DC	4.93 %
	Area (pad-limited)	0.35 × 0.59 mm²

Table 1

 1 compares the presented receiver front-end to the state of the art. It contains published front-ends of comparable levels of complexity. The third column shows which components, besides LNA and mixer(s), are included in each circuit.

Table 4 .

 4 CMOS receiver front-ends of comparable complexity found in literature

	Ref.	Tech. [nm]	Consists of LNA, mixer &	RF [GHz]	IF [GHz]	NF(DSB) [dB]	G C [dB]	IP -1dB [dBm]	P DC [mW]	Area [mm²]
	S. Emami, 2007 [1]	130	IF amp., doubler VCO,	57-63	2.0	10.4	11.8	-15.8	76.8	3.8
	Sanduleanu, 2007 [2]	90	VCO	59-61	0	9.5	23	N.A.	54	0.86
	T. Mitomo, 2008 [3]	90	BB buff., PLL, antenna	61.3-63.4	0.1	8.4	22.5	N.A.	144	2.64
	K.H. Chen, 2008 [4]	90	PLL	61.4-63	1	5.64	25.2	-16	132	1
	J. Lee, 2009 [5]	90	IF buff., demod. VCO, OOK	60	10	7	25	-26	103	0.68
	S. Bozzola, 2009 [6]	65	BB & LO buff., VCO	62-67	20	9	281	-26	80	0.52
	F. Vecchi, 2010 [7]	65	BB & LO buff., VCO	55-68	20	5.6	35.5	-39	75	2.5
	proposed front-end	65	BB & LO buff., VCO	56.5-61.5 0-1.5	8.45	30	-36	43	0.55

Table 1 .

 1 Performance summary of the LNA

Table 2 :

 2 Performance summary of the down-mixer

Table 3 :

 3 Performance summary of the VCO Table4. CMOS receiver front-ends of comparable complexity found in literature

ACKNOWLEDGEMENT

This work has been supported by the French National Research Agency (ANR) in the framework of the program Recherche Technologique Nano-INNOV/RT NANOCOMM project NANR-09-NIRT-004 and by the european Medea+ project QStream.

Bibliographies

that includes the reliability. In 1993, as associate professor at LAAS-CNRS, he has started a new research area concerning the investigation of millimeter-wave capabilities of Silicon based technologies. More precisely, he has focussed on the microwave and millimeter-wave properties of SiGe devices and their capabilities for low noise circuits. In 1995, he has started a new project concerning the improvement of the passives on silicon through the use of MEMS technologies. In 1999, he has been involved with SiGe Semi-conductor in Ottawa where he was working on the low power and low noise integrated circuits for RF applications. In the same year, he has received a special award from CNRS for his works on Silicon based technologies for millimeter-wave communications. In 2000, he has been professor at Paul Sabatier University and Institut Universitaire de France and he has started a research team at LAAS-CNRS in the field of Micro and Nanosystem for RF and millimeter-wave communications. Its main interests are on the technology, design, modelling, test, characterization and reliability of RF MEMS for low noise and high power millimeter-wave applications and the development of the MEMS IC concept for smart microsystems. He has built a network of excellence in Europe in this field "AMICOM" regrouping 25 research groups. He has authored and co-authored more than 300 international journals and conferences. In


Mariano Ercoli

Daniela Dragomirescu

Robert Plana

Small Size High Isolation Wilkinson Power Splitter for 60 GHz Wireless Sensor Network Applications

Keywords: CMOS, divider, power splitter, Wilkinson

published or not. The documents may come   L'archive ouverte pluridisciplinaire

I. INTRODUCTION

During the last decade the research on transceiver systems operating on 60 GHz free band had an unstoppable growth. Thanks to the reduction of the gate size, the cutoff frequency in the silicon device increases achieving the CMOS employment in this slice of market. After the 130 nm generation, the CMOS device has prevailed the III-V group materials in particular for commercial applications. The Monolithic Microwave Integrated Circuits (MMICs) have been left to military and spatial applications. The Radio Frequency Integrated Circuits (RFICs) had become the new low cost commercial way.

In terms of performances the two devices categories are very different. In the RFIC there are different constraints compared to MMIC. First of all the performance on the active devices: in the CMOS technology the short channel and the very thin gate oxide impose limited supply voltage to avoid the break of the transistor. Consequently the admitted output power is highly limited. For the MESFET or HEMT thanks also to their physical constitution the supply voltage is higher as well as the achievable output power. Another not negligible aspect for the CMOS technology is the losses on the substrate; these conditions impose a limitation on the interconnection lines' dimension, to limit the power dissipation on the substrate.

Considering the last constraint the target for the RFIC architecture is the minimization of the entire system size to mitigate the substrate losses. In the wireless sensor network, minimizing the losses in the payload signal path, allows a smaller power dissipation and this is fundamental for battery driven systems. To increase the rejection of the spurious signal and perform the transfer of information architecture with balanced architecture and in phase and quadrature signal (I/Q) have been developed. In the architecture shown in Figure ?? there are many different passive blocks to allow power splitting, imbalanced to balanced transformation and a 90 degree phase shift. The effectiveness of the system is strictly dependent on the behaviour of these passive components. The quality of the active blocks become useless if the passive parts have a poor response. In MMIC technology the employment of Wilkinson splitters, Marchand balun, hybrid branch line or Lange coupler are widely used. The dimensions of MMICs chips allow the use of this components because the dimension of each single blocks is proportional to the wave length of the signal. Hence, the design of the passive block is relative easy and allows good response. In the RFIC the wavelength is much smaller than the block dimension and with a relative permittivity around the 4.12 the dimension of λ/4 is near to 650 µm. These dimensions are huge if compared to the typical dimension of 65 nm active building blocks. The dissipation in the silicon substrate attenuates the radio frequency (RF) signal and the derived noise destroys the Signal to Noise Ratio (SNR). In the literature there are many different approaches to reduce the block dimension. Slow wave approach is one. By this technique is possible to reduce the length of the lines by a factor of 0.7 [?]. Another approach, proposed by J-G Kim [?] is based on the lumped component. This second approach is interesting and it will be investigated in this paper. The build of the Wilkinson has been done in seven metal layer plus Alucap metal layers of the ST Microelectronics 65nm CMOS technology. Section II gets a brief description about the architecture and features of Wilkinson divider. Section III summarizes the principle of function of the lumped component representation. Section IV explains the model of the inductance taking into account the influence of the technology constraints and their implication on the complete structure. Section V shows the obtained Wilkinson structure with the complete simulation results. The aim of this paper is to propose a design flow for the Wilkinson power divider underlying the principal issues, shown in the next sections and giving the solution to overcome them.

II. WILKINSON DIVIDER ARCHITECTURE

The Wilkinson divider is an important component with a very simple architecture. The role of this element is the split of its input signal into two different parts maintaining the phase and amplitude equilibrium between the two output ports. An important characteristic in the Wilkinson splitter is the reciprocal high isolation between the two output port. This feature is the great advantage of the Wilkinson splitter. If a little structural difference on the two symmetrical chains occurs, a part of signal can be returned back. In the Wilkinson divider a shunt resistance placed in correspondence of the output port blocks the signal and avoid the interfering propagation through the other parts of the circuit.

III. LUMPED ELEMENT REPRESENTATION

It is know that there are two different lumped component architecture to reproduce the behaviour of a section general lines: the T and Π representation. Figure ?? shows the second one. Adopting the Π scheme the admittance matrix for a lines with an electrical length of θ are:

1 2 θ=π/2, Y0 1 2 L C C (a) (b)
Y Line = -jY 0 sin θ cos θ -1 -1 cos θ (1) with θ = π 2 2πf 2πf 0 (2)
.

Where f 0 is the central frequency and Y 0 = 1/Z 0 is the characteristic impedance (50Ω) of the input and output ports. For the frequency f = f 0 i.e. θ = π/2 is obtained a quarter wave length for the line. Applying the equation for the ABCD matrix [?] at Formula ??, it becomes:

Y Π = 1 -jωL 1 -ω 2 LC -1 -1 1 -ω 2 LC (3)
Where L and C are the series inductance and shunt capacitance of the lines. For the Wilkinson λ/4 lines the lumped component values are:

L √ 2Z0Ω = 1 Z2πf 0 = 187.5pH (4)
and

C √ 2Z0Ω = Z 2πf 0 = 37.5f F (5)
The equivalent circuit composed by the previous lumped element is shown in Figure ??(b). A circuit simulation by Agilent ADS software was done, (not showed here), to confirm the theoretical behaviour of the circuits.

IV. LUMPED INDUCTOR DESIGN

In the ST Microelectronic technology is possible to use the last three metals (6th, 7th an Alucap layer) to build an inductor having good performance. The choice of the inductor shape is critical to achieve the best performance: multi-metal or planar structure is the first step in the inductor design. The advantage of the multi-metal approach is the concentration of the magnetic field and the reduction of the coil planar surface. The drawback is a parasitic coupling capacitance between the superimposed coils causing structure auto-resonance frequency dropping. The design of a coil with an operative band near the auto-resonance frequency is not allowed because the inductance value changes for a large bandwidth signal and destroys the ideal response of the entire block. Instead, a planar structure minimize this problem as the parasitic capacitive coupling is limited at the fringing coupling between each following run of the line. This second shape increases the occupied surface indeed, but also increases the resonance frequency. The choice of the metal layer to use for the coils' design has been determinate by practical considerations based on the physic of the system. To build the principal coil of the inductor, the best solution is using the 7th copper metal layer. This layer combine the higher conductivity property compared to 8th aluminium layer and minimize the losses influence in the silicon substrate. In this condition the obtained quality factor for the inductor increases. [?].

Once fixed the shape of the inductance, the second step is the inductance value optimization. Differently from the lumped capacitance existing on the CMOS Design Kit, the equivalent circuit of the coils is far from an ideal lumped inductance. Dickson et al. in [?] show an equivalent lumped circuit to model the spiral inductor. During the integration phase between the two coils and the shunt capacitance these parasitic effects are not negligible. To consider these effects, an iterative procedure has been employed to design the optimal spiral inductor.

The software used to conduct this optimization are: 1) ASITIC, for the first step sizing of the coil; 2) Sonnet 12.52, for the electromagnetic simulation; 3) Agilent ADS, for the synthesis of the complete structure. The first step on the coil design has been fixed with ASITIC. This software in fact gets a good compromise between the accuracy and simulation speed. To maximize the accuracy on the simulation the successive analysis have been executed with Sonnet environment. The experience in spiral inductor in 60 GHz applications with Sonnet has been demonstrated by Kraemer et al. in [?]. In this paper another aspect is also taken into account i.e. the influence of the "dummy" metal around the coils. These parts of small floating copper are present to assure the minimal concentration of metal among the different layers. Their presence is necessary to avoid undesired mechanical stress on the superimposed layers and to allow a smooth surface in the different metal level. The presence of these inactive metals changes the magnetic flows around the coils as well as the inductive response. Figure ?? is a 3D Sonnet representation that highlights the difference between the same coils with and without the dummy metal. As is possible to see the presence of the dummies has a strong influence on the inductor value. The EM simulation of the structure with dummy is very difficult to do because it needs a large amount of memory that usually is not possible to satisfy. In this case to estimate the dummy influence an approximation on the metal characteristics has been done. Instead to consider the dummies like a solid blocks they have been model like a ideal metal sheet. In this condition the number of mesh cells remains low and it is possible to understand the variation on the inductance response. This method does not confirm an exact prevision on the realized coils response but contributes to increase the fitting from the measure results with the EM simulation. shows the inductance of the two inductor shown in Figure ??. As it is possible to see, the difference between the two coils is remarkable.

V. COMPLETE WILKINSON STRUCTURE

The inductor design for the Wilkinson divider block is only the first step. Another important effect to take into account and simulate is the potential EM coupling between the two coils that create the output branch. Figure ?? show the 3D complete structure of the Wilkinson divider. A metallic wall, joined to the ground, divides the 2 coils to attenuate the undesired mutual coupling effect. A simulation of the entire structure is needed to evaluate the entire structure at the same time. Otherwise, a not considered effects like parasitic coupling, can modify the response of the splitter and change mainly the input and output return loss. After the simulation using Sonnet tool, a small coupling effect that changes the total response has been found and a second optimization run is needed. At this state of the design, small variation in terms of coils size, are enough to re-establish the expected response. Figure ?? shows the input and output return loss for the splitter. As is possible to see, the divider shows a very large band. This behaviour, differently of classical λ/4 architecture, is achieved by the lumped component approach. The input return loss is better than -13dB for all the simulated band. The output return loss is still improved with -15 dB. In the interest band: 57-67 GHz the values have been optimized with a maximum amount around -21 dB for all reflection coefficients. Concerning the transmission values, the losses showed in figure ?? are lower than 0.5dB within the whole band of interest. The isolation instead was optimized by a transformation of the output shunt resistance. Theoretically the requested value is 100 Ohm resistance but, to allow the maximum isolation value in the center of the band of interest. A R-C circuit has been developed. The optimum value for the R-C net is a series of R-C-R with two 27 Ohm resistance and one 50 fF capacitance. Thanks to this combination, the maximum isolation value is placed in the center of band (-25 dB) with a minimum value of -20 dB around 50-70 GHz. As shown in Figure ??. The synthesized splitter shows a good behaviour. Comparing to the state of the art presented in [?] the Wilkinson divider proposed in this paper has better performance combining with a size of 115 × 50µm 2 : 15 times smaller than the reference (536 × 150µm 2 ).

Input Port

Output Ports

VI. CONCLUSION

In this paper an optimized version of lumped Wilkinson power splitter is showed. The main work is based on the characterization of the boundary condition of the structure. The influence of the dummies, the parasitic coupling and a new circuit to increase the isolation have been analysed and developed. The performances of the structure have been simulated. Previous experience in our research group [?] [?] [?]the inductance design and measurement confirms the quality of the simulation as well as the behaviour of the designed structures. The obtained result shows a excellent behaviour for the splitter that overcome the state of the art in terms of isolation, insertion loss and principally in size.

Fig. 1 .

 1 Fig. 1. Principal passive blocks (highlighted) for a full balanced I/Q receiver in 60 GHz application.

Fig. 2 .

 2 Fig. 2. Lumped model representation for a quarter wave line length.

Fig. 3 .

 3 Fig. 3. Example of simulated inductance with (a) and without(b) dummy metal. The size the mesh and the boundary condition are the same for the two different structures.

Fig. 4 .

 4 Fig. 4. Difference in terms of inductance value between the same structure, (represented in Figure ?? with(b) and without (a) dummy metal.

Fig. 5 .

 5 Fig.5. 3D view of lumped Wilkinson power splitter. A thick metal model representation of dummy metal are showed. In this configuration a complete EM analysis is impossible because it requires an huge quantity of memory (higher than 163 GB!)

Fig. 6 .

 6 Fig. 6. Lumped Wilkinson splitter input and output return loss.

Fig. 7 .

 7 Fig. 7. Principal passive blocks (highlighted in red) for a full balanced I/Q receiver in 60 GHz application.

ACKNOWLEDGMENT

This work has been supported by the French National Research Agency (ANR) in the frame of its program "Recherche Technologique Nano-INNOV/RT" (NANOCOMM project n • ANR-09-NIRT-00 4) The authors wish to acknowledge Dr. Michael Kraemer for the interesting discussion on the lumped component simulations.