Sara Mannaa

Arnaud Poittevin

Cédric Marchand

Damien Deleruyelle
email: damien.deleruyelle@insa-lyon.fr

Bastien Deveautour
email: bastien.deveautour@cpe.fr

Alberto Bosio

Ian O'connor

Chhandak Mukherjee

Yifan Wang

Houssem Rezgui

Marina Deng

Cristell Maneux

Jonas Müller

Sylvain Pelloquin

Konstantinos Moustakas

Guilhem Larrieu

3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs

Keywords: 3D electronics, vertical nanowire transistor, compact model, logic circuit design, electrothermal modeling I

This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heattransport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit level simulations indicate a strong impact of temperature variation on functionality and figures of merits such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

INTRODUCTION

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. With the deployment of large numbers of sensors and smart devices to form the edge of the Internet of Things to the scale of 50 billion and rising, data is now being generated at the edge rather than in the large-scale data centers that form the cloud. Current estimates put the ratio of data generation at the edge at over 40x that of global data center traffic, today around some 20ZB. The pure cloud computing model cannot handle this massively distributed, YB-scale quantity of data -the network infrastructure resources simply do not have the capacity to move the data from the edge to the cloud, the data is vulnerable to attacks and the transmission delay is prohibitively high. In advanced applications where delay requirements are particularly stringent (e.g. 1 ms in cooperative autonomous driving), the cloud computing model cannot consistently meet the deadlines.

The limits of the cloud computing model have given rise to the emergence of edge computing, where computing tasks are performed as close as possible to data sources to meet the low power and latency criteria [START_REF]The International Roadmap for Devices and Systems[END_REF]. However, resources are constrained at the edge, in terms of available computational power, memory capacity and most importantly energy.

Hardware is critical at this level and there is a clear need to explore the suitability of breakthrough emerging technologies to meet the energy-efficiency, performance and compactness requirements of edge computing hardware as alternatives to traditional von Neumann machines. IRDS identifies Gate-All-Around (GAA) nanowire field effect transistors (NWFETs) as a future mainstream solution [START_REF]The International Roadmap for Devices and Systems[END_REF], both in lateral and vertical configurationshowever, the challenge is to extrapolate analyses beyond the device level to quantify relevant performance metrics [START_REF] Jeong | Performance-power management aware state-of-theart 5nm FinFET design (5LPE) with dual CPP from mobile to HPC application[END_REF][START_REF] Yasuda-Masuoka | High performance 4nm FinFET platform (4LPE) with novel advanced transistor level DTCO for dualCPP/HP-HD standard cells[END_REF].

In particular, junctionless Vertical NWFETs (VNWFET), capable of addressing existing process challenges such as downscaling, short-channel effects, compactness and electrostatic control, are difficult to meaningfully compare to existing mainstream technologies due to the additional vertical dimension and opportunities for innovative 3D logic design [START_REF] Hsueh | First demonstration of ultrafast laser annealed monolithic 3D gate-all-around CMOS logic and FeFET memory with near-memory-computing macro[END_REF]. A critical specific issue in this evaluation lies in the correct evaluation of the electrothermal behavior of the device [START_REF] Venkateswarlu | Electro-Thermal performance boosting in stacked Si gate-all-around nanosheet FET with engineered source/drain contacts[END_REF]. Indeed, the electrical performances of aggressively scaled transistors are strongly impacted by selfheating, ultrafast thermal transport and thermal conductivity degradation, all of which link to electron-phonon coupling which is not well understood at the nanoscale. The integration of this technology in the mainstream design flow is thus not straightforward and requires design technology cooptimization (DTCO) at an early stage [START_REF] Song | System design technology co-optimization for 3D integration at <5nm nodes[END_REF][START_REF] Maneux | Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence[END_REF]. This paper is an important step to achieve this goal.

In this paper, we propose a compact model to enable multiphysics evaluation of intrinsic transistors, considering electro-thermal and trapping effects investigated through multiphysics simulations based on non-Fourier heat-flow [START_REF] Tang | Ballistic thermal wave propagation along nanowires modeled using phonon Monte Carlo simulations[END_REF]. From the theoretical understanding of these effects in junctionless devices, the proposed compact model [START_REF] Mukherjee | Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design[END_REF] captures temperature-induced increase in drain current through temperature dependence of model parameters including threshold voltage, drain/source Schottky barrier height and series access resistances. The proposed model also incorporates two additional sub-circuits for dynamic selfheating and trapping phenomena for evaluation of these effects at circuit level. We then project device performance to circuit level by using this compact model to characterize four basic 3D logic cells (INV, NAND, NOR and XOR) based on vertical nanowire transistors in terms of delay and energy consumption, thus proving that this emerging technology can be used as the basic building block for logic gates.

The paper is organized as follows: section II first describes the physical basis and implementation of the compact model (based on experimental measurements of the devices under test). Section III subsequently describes the logic cells and our characterization methodology in terms of delay and energy consumption, and with varying temperature. Section IV discusses results and perspectives, and summarizes possible future work.

II. TRANSISTOR: COMPACT AND NUMERICAL MODELING

A. Multiphysics modeling of intrinsic transistors

To accurately capture the underlying physics of junctionless FETs, the compact model presented in this work has been specifically developed based on the understanding of carrier transport studied using numerical multiphysics and TCAD simulations. Junctionless FETs offer a much and simpler fabrication process in comparison with classical MOSFETs [START_REF] Guerfi | Vertical silicon nanowire field effect transistors with nanoscale gate-all-around[END_REF], making them compatible for pursuing scaling beyond the sub 20-nm nodes. Most importantly, along with the absence of metallurgical junctions in these devices, they are heavily doped and the nanowire diameters are tailored to be quite thin in order to maintain gate electrostatic control over the channel. In order to ensure design compatibility between the junctionless VNWFET technology [START_REF] Guerfi | Vertical silicon nanowire field effect transistors with nanoscale gate-all-around[END_REF] and associated circuit simulations, the transistor compact model developed based on charge transport in gate-all-around junctionless transistors [START_REF] Mukherjee | Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design[END_REF] is used first to calibrate the model parameters against experimental data of a wide range of transistor geometries (22 and 34 nm NW diameter with 16 to 81 nanowires in parallel) at room temperature.

Key physical parameters include doping, gate work function, mobility, drain/source Schottky barrier and threshold voltage. Once a good accordance between the model and the data is obtained, the compact model is then modified to take into account electrothermal and trapping effects, two critical issues in nano-scale junctionless transistors that can potentially impact dynamic circuit performance. To do so, we leveraged on-wafer DC measurements over a wide temperature range (15-100 °C) and pulsed-conditions with varying pulse widths (1 µs -10 ms) to dissociate temperature and trap-induced effects. From the experimental observations, it could be understood that increasing the temperature leads to a monotonically increasing drain current conforming to prior observations in junctionless transistors [START_REF] Lee | High-Temperature Performance of Silicon Junctionless MOSFETs[END_REF]. This is explained by the strong temperature dependence of the threshold voltage in junctionless devices that leads to an increase in drain current along with a degradation of the on-off current ratio. This effect is further pronounced by the weak temperature dependence of the mobility due to competing lattice and impurity scattering mechanisms [START_REF] Lee | High-Temperature Performance of Silicon Junctionless MOSFETs[END_REF]. From the pulsed I-V measurements, it could similarly be observed that the drain current showed a continuous increase with increasing gate pulse-width, allowing for an increasing number of traps to activate while the device temperature increases simultaneously. For very large pulses, the transistor current saturated to the measured DC current. This phenomenon can also be considered to impact the threshold voltage as confirmed by the VTH-shift with pulse width. This further affirmed that the threshold voltage in junctionless transistors is an important parameter to model both electrothermal and trapping effects. In the following sections, in-depth physical understanding of these effects, obtained through multiphysics simulations and compact modeling, are presented.

1) Electro-thermal and Trapping effects

Thermal management is one of the most challenging design criteria in nanoscale transistors owing to a lack of understanding of the heat conduction governed by phonon transport in sub-10 nm devices that include (1) ballistic, (2) boundary scattering and (3) confinement regimes [START_REF] Kwon | Thermal transport in Si and Ge nanostructure in the 'confinement' regime[END_REF].

Junctionless transistors are fabricated with a very thin channel along with a chosen gate work-function to ensure that the transistors switch to off state at zero gate bias, switching to full depletion mode. In addition, the nanowires are required to be strongly doped to ensure a higher drive current in order to compensate for the Schottky barriers at the source and drain sides. Phonons can be considered as a quasiparticle originating due to lattice vibration and can be confined in the Si/SiO2 interface similar to trapping, leading to a reduction of the thermal conductivity. In addition, due to electron-phonon coupling and phonon confinement, carriers (electron or hole) can also be trapped in the lattice distortion leading to the wellknown self-trapped electron phenomena [START_REF] Varley | Role of self-trapping in luminescence and p-type conductivity of wide-bandgap oxides[END_REF]. Moreover, in the nanoscale regime, explaining ultrafast heat flow using the classical hydrodynamic formalism based on Fourier's law no longer remains valid. The Guyer and Krumhansl equation (GKE) has recently been demonstrated to capture nondiffusive heat transport in the nanoscale regime beyond classical Fourier's law, offering understanding of non-local thermal effects [START_REF] Guo | Phonon hydrodynamics for nanoscale heat transport at ordinary temperatures[END_REF].

To understand the electron-phonon coupling behind the electrothermal behavior and trapping effects for nonequilibrium states in both steady and transient conditions in junctionless transistors, we leveraged finite element method (FEM) based COMSOL multiphysics simulations [START_REF]COMSOL Multiphysics[END_REF] based on the GKE formulation by solving the non-Fourier heat equation coupled with the drift-diffusion model and interface trapping effects. The material parameters are included in the simulator physics library whereas the operating conditions and device geometries are defined according to our experimental setups. The governing equation of the GKE for non-Fourier heat dissipation is written as [START_REF] Wang | Evidence of Trapping and Electrothermal Effects in Vertical Junctionless Nanowire Transistors[END_REF],

𝑞 𝑥 (𝑟) = -𝜅 𝑑𝑇 𝑑𝑥 + 𝑙 2 𝑑 2 𝑞 𝑥 (𝑟) 𝑑𝑟 2 + 𝑙 2 1 𝑟 𝑑𝑞 𝑥 (𝑟)

𝑑𝑟

(1) where 𝑞 is the heat flux, 𝜏 𝑅 is the phonon relaxation time, 𝜅 is the thermal conductivity, ℓ is the phonon MFP, 𝑐 is the heat capacity, T is the temperature. To consider the electrothermal effect we use the energy-conservation equation:

𝑐 𝑑𝑇 𝑑𝑡 + 𝛻. 𝑞 𝑥 (𝑟) = 𝑃 (2)
where 𝑃 is the dissipated power defined as 𝑃 = 𝑉 𝐷𝑆 𝐼 𝐷 . The multiphysics simulations reveal that the temperature distribution inside the nanowire exhibits a steady increase of internal device temperature along the channel (Fig. 1(a)), reaching the peak near the drain (Fig. 1(b)), implying thermal confinement and self-heating at elevated temperatures and bias conditions. This is reflected by an equivalent degradation in thermal conductivity within the channel (Fig. 1(b)). As highlighted in the previous section, the temperature variation induces a linear threshold voltage shift which can be extracted from experimental results (Fig. 1(c)). In addition, the thermal resistances (RTH) of the VNWFETs have been extracted from both measurements and Multiphysics simulations [START_REF] Maneux | Strategies for Characterization and Parameter Extraction of Vertical Junction-less Nanowire FETs dedicated to Design Technology Co-Optimization[END_REF] which exhibit an inverse geometrydependence (Fig. 1(d)).

Similarly, under pulse conditions, we studied the thermal conductivity and temperature rise using COMSOL for various pulse widths that also indicated an increase of the device temperature (along with an equivalent reduction of thermal conductivity) due to phonon accumulation near the drain region at high bias conditions and larger pulse widths (Fig. 2(a)). The numerical model was then used to extract the trap densities (Fig. 2(b)) that were compared with the VTH variation for different pulse widths, which revealed a clear trend in both cases: the VTH drift observed from the measurements could be described by a similar relation that also governs trap density, 𝑁 𝑇 = 𝑁 𝑆𝑆 (1 -exp (-𝑡 𝑝𝑢𝑙𝑠𝑒 /𝜏) ). This led us to define the following physical relation for trapinduced VTH-shift in our model: ∆V 𝑇𝐻 = αqN T /C ox , where α is a constant, q is the electronic charge and COX is the gate oxide capacitance. Figs. 3(a 2) Compact model implementation Following the multiphysics simulations, it could be confirmed that in the junctionless nanowires, thermal conductivity reduces significantly with temperature, thus creating temperature hot-spots and leading to possible device self-heating. Moreover, the trap density evolves exponentially with applied gate pulse width saturating to the DC value where internal device temperature rises significantly coupled with the presence of traps. To translate these effects for compact modeling, we modify the expression of the threshold voltage to capture the effect of internal device temperature increase and trap density fluctuation. To do so, we leverage the equation ∆𝑉 𝑇𝐻 = ∆𝑉 𝑇𝐻 (𝑇) + ∆𝑉 𝑇𝐻 (𝑁 𝑇 ), where the first term captures a linear temperature dependence through a temperature coefficient whereas the second term incorporates a trap density-like dynamic exponential formulation activated through a FLAG parameter, with both parameters extracted from experimental results. In addition, an equivalent electrical subcircuit consisting of the thermal resistance and capacitance (extracted from low-frequency S-parameter measurements) has also been added to the compact model formulation in order to capture the dynamic variation of internal device temperature due to self-heating which can also be activated through a FLAG parameter. Lastly, temperature coefficients of additional model parameters such as the Schottky barrier height, series access resistances, intrinsic carrier concentration and drain induced barrier lowering are also implemented in the model equations. Compact model simulation results are validated against experimental data for both pulsed (Fig. 3

B. Enhanced devices through the integration of materials

or architectures While junctionless VNWFETs already bring significant benefits to transistor performance, additional features can be naturally achieved. This subsection covers emerging characteristics of such functional enhancements from a prospective viewpoint.

1) Ferro gate

Adding ferroelectric material to the VNWFET gate stack [START_REF] Fujisawa | Nonvolatile operation of vertical ferroelectric gate-all-around nanowire transistors[END_REF] enables non-volatile logic as well as non-volatile reconfigurability. For example, a non-volatile full adder [START_REF] Yin | Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits[END_REF] is able to store one of the summands in a non-volatile manner, which is of particular interest in multiplication operations used in digital filters or convolutional neural networks, and where one summand varies constantly (data), while the other one varies rarely (coefficients). Reconfigurable in-memory computing is enabled by the conjunction of ferroelectric VNWFETs with classical LookUp Table (LUT) circuit structures such as a LUT2 [START_REF] Breyer | Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory[END_REF] and where the output depends both on the select inputs (S0 and S1) as well as on the stored states (here 4 states stored in a non-volatile manner to reflect a 2-input truth table), i.e. 𝑌 = 𝐴. 𝑆 1 ̅ . 𝑆 0 ̅ + 𝐵. 𝑆 1 ̅ . 𝑆 0 + 𝐶. 𝑆 1 . 𝑆 0 ̅ + 𝐷. 𝑆 1 . 𝑆 0 .

2) Reconfigurable FETs

Polarity-controllable transistors (PC-FETs) leverage a multitude of input gates on a single ambipolar channel, to dynamically select both conduction state, as well as carrier type (Fig. 4) [START_REF] Mikolajick | Reconfigurable field effect transistors: a technology enablers perspective[END_REF]. PC-FETs connected to a common body enable inherent X-to-1 multiplexing in a single transistor with V TH (V) X independent drain-contacts. Non-volatile PC-FETs in a 3D tile also intimately incorporate multi-bit memory capability within computing elements, thus opening the way for a new concept for computing-in-memory.

1x10 1 1 2x10 1 1 3x10 1 1 4x10 1 1 5x10 1 1 N T (cm -2 ) D=22nm, NW=25 (

C. Toward Dynamic Modeling

Another design perspective for improved dynamic performance of the logic cells includes optimized test structures. To ensure circuit design involving a 3D emerging technology, accurate compact models capturing the static and dynamic device behavior are mandatory [START_REF] Maneux | Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence[END_REF], but on-wafer test structures of such devices also include parasitic elements induced by pads and interconnects that are necessary to probe the devices under test (DUT). Due to the 3D nature of interconnects, standard methods to remove these parasitic contributions (de-embedding) become inaccurate owing to the fact that classical design of passive test-structures (Open and Short) no longer remain sufficient to completely model the extrinsic 3D parasitic network. Figure 5 shows the respective sizes of the DUT and its associated test structure illustrating the requirement to reinvent dedicated deembedding methods for the 3D VNWFET technology. In [START_REF] Wesling | Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor[END_REF] a new de-embedding method for this technology was introduced that makes use of electromagnetic (EM) simulations to virtually reconstruct the entire parasitic network including coupling capacitive, inductive and resistive parasitic elements.

The values of all these parasitic elements constituting the small-signal equivalent circuit (SSEC) were calculated through (i) analytical equations from the physical dimensions, (ii) the material properties of the device, (iii) the standard calibration techniques such as SOLT (Short-Open-Load-Thru) as well as (iv) from EM simulations. The overall SSEC is shown in Fig. 6 along with the values of the parasitic elements. At this stage, this SSEC can be used to generate the ABCD matrices of the gate and drain parasitic access contributions for successful de-embedding of the intrinsic Sparameter measurements [START_REF] Maneux | Strategies for Characterization and Parameter Extraction of Vertical Junction-less Nanowire FETs dedicated to Design Technology Co-Optimization[END_REF][START_REF] Wesling | Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor[END_REF]. This allows us to extract the intrinsic transistor S-parameters for device modeling and subsequently continue towards 3D logic cell design.

III. STANDARD LOGIC CELL MODELING

In this section, we leverage the developed compact model to assess the performance metrics of various 3D logic cell circuit topologies in the VNWFET technology. The ultimate goal of this study is to enable logic synthesis, which needs a library of characterized basic logic cells as a prerequisite.

A. Energy-delay characterization of standard logic cells

The goal of the following simulation-based exploration is to study the impact of using a large range of nanowires per transistor on typical static and dynamic logic performance metrics, for several standard logic cell topologies. In the simulation protocol, we assume that the gate capacitance behaves in the same way for both p-and n-type VNWFETs, and that the capacitive load on the output of each structure is equivalent to that of a single inverter of drive strength 1. Since the VNWFET gate capacitance is experimentally determined to be 20aF per NW, and assuming that its evolution with NW number is linear, we deduce a capacitance contribution for INV1X1 as 160aF.

In this context we aimed to study the behavior of four main logic cells: INVX1, NAND2X1, NOR2X1, and XOR2X1. Figure 7 depicts the transistor-level schematics of these Boolean gates, where the formalism OPnXk indicates the boolean operation OP, the number of inputs n and the number of outputs k of each gate. carried out simulations using the HSpice TM commercial simulator, where we used the compact model described in section II implemented as an executable Verilog-A model for the VNWFET. The gate physical length Lg and the nanowire (NW) diameter dnw are both parameters which are determined by the fabrication process. Throughout this work, and based on experimental devices, the values of these parameters are set to Lg = 18 nm and dnw = 22 nm respectively. Based on this, as well as the definition of other fixed model parameters, we investigated the number of nanowires for p-type and n-type transistors to be used, as the only design parameter remaining to enable the optimization of device and circuit performance. The first essential step in this work is to verify the functionality of the n-type and p-type VNWFET devices themselves through DC-sweep simulation in order to ensure that they have the expected IDS/VGS characteristic behavior, as illustrated in Figure 8. Subsequent to this verification, we simulate an elementary inverter gate shown in Figure 7(a) in order to determine the correct ratio between n-type and p-type NW (number of nanowires per VNWFET) values to obtain an optimal midpoint voltage. In this work, we also chose a range of values of NW for n-type transistors that allows us to study the behavior of the device under different drive strengths. For each value, we run DC-sweep simulations while varying the gate voltage from 0 to VDD and assessing the output behavior for varying numbers of nanowires for the p-type device. We find that for all the defined NW values, a ratio of 1 between the number of NWs of p-type and n-type will give us an optimal midpoint voltage at half VDD as shown in Figure 9, which leads to balanced noise margins and well-matched rise and fall times of the cell. Fig. 9: Variation of inverter output voltage as function of the input voltage variation between 0 and VDD (1V) for different ratios between the number of nanowires (NW) used for p-type and n-type transistors. It can be clearly seen that a ratio of 1 between NW of p-type and n-type devices achieves optimal midpoint voltage at half VDD.

It is important of course to note that this ratio depends on the set of parameters used in the simulation. For this study, the chosen values for the number of NWs of the n-type device of the inverter were 4, 24, 44 and 64. The corresponding number of NWs for the p-type device is chosen according to the above described methodology. For the other cells, and in order to achieve drive strengths equivalent to that of the inverter, we redefine the number of nanowires by doubling the number of NWs in case of two series transistors. After defining the sets of NW parameters, we identify the simulation limitations of the executable model and adjust our simulations accordingly. Then a detailed study of the static and dynamic behavior of all cells was carried out, as detailed in the following subsections.

This study was done by varying the number of nanowires used in each logic gate to study their behavior under different drive strength. The simulations showed that using this technology we can successfully implement logic NOT, NAND, NOR and XOR functionalities as shown in Fig 10.

To characterize the library of standard logic cells, it is necessary to study the main conventional performance metrics of the targeted logic cells, i.e. propagation delay, rise/fall time and dynamic power consumption where:  The delay corresponds to the time difference between the output voltage and input voltage to reach half VDD  Rise (resp. fall) time corresponds to the time needed by the output voltage to rise (resp. fall) from 0.1VDD (resp. 0.9VDD) to 0.9VDD (resp. 0.1VDD)  The dynamic power consumption for a particular transition is calculated by measuring the supply current during the output transition  The leakage power is calculated by measuring the supply current during all static combinations of inputs For each cell, all the possible output transitions based on input(s) transitions are defined. Then for each case, the timing and energy consumption are measured as described above. For all the cells under study we found, as expected, that with the increase in the number of NWs used, a decrease in delay (Fig 12) and rise/fall times is observed as well as an increase in dynamic power consumption (Table I).

B. Parasitic-annotated assessment

For devices with such small dimensions and compact footprint, circuit-level parasitics (in particular from coupling capacitance, metal contact, layout-related issues) can significantly limits the benefit in design. In order to assess the impact of parasitics, we designed the layout for a 2-input XOR gate (one of the more complex logic functions, and including in-cell generation of complemented inputs) as shown in Fig. 13(a) and extracted the associated parasitic network based on the aforementioned geometrical parameters and material coefficients. Metal interconnect layers connect top and bottom nanowire contacts, as well as gate contacts surrounding the nanowires to create GAA devices. Transient simulation results for the resulting parasitic-annotated 2-NW/transistor XOR2 cell are shown in Fig. 13 (b). This enabled us to carry out a comparative study in order to quantify the impact of parasitic interconnect networks on key performance metrics. The full dataset is shown in Table II.

Comparing delay and energy per transition figures, we quantify the average increase in delay as +4% and energy/transition as +19% when considering the parasitic interconnect network.

C. Impact of electro-thermal and trapping effects

In order to study the electrothermal and trapping effects on the behavior of VNWFET based logic cells, we first set the related model FLAG parameters to 1 (described in section II-A) to activate self-heating and trapping. Next, we vary the temperature (250K-400K), within the range allowed by the technology and model specifications, and perform logic circuit simulations. For all logic cells, we observe that these variations have no effect on the functional behavior. We also observe that while the propagation delay decreases with the increase of temperature, dynamic energy consumption/transition increases. These phenomena result from a reduction of the threshold voltage with temperature, leading to a higher drive current as well as a higher leakage current. Fig. 14 shows these trends using the INV1 and XOR2 cells as examples.

IV. DISCUSSIONS AND PERSPECTIVES

We presented comprehensive insights into 3D logic circuit design based on junctionless vertical nanowire transistors leveraging multi-physics simulations and SPICE-compatible compact models. In particular, we studied temperature effects and trap dynamics through dedicated measurements and extracted associated model parameters that couple these effects dynamically to circuit simulations. Cell-level performance of circuits such as inverter or XOR, studied based on the developed compact model, indicate a strong impact of electrothermal effects in the VNWFET technology. Threshold voltage shift due to increasing temperature leads to an increase in drive current at the detriment of a reduced on-off current ratio which in turn limits circuit functionality at elevated temperatures especially at the onset of self-heating due to confinement effects for cells with increased complexity. In addition, interface trapping has a major role in determining dynamic performance metrics such as the delay. Careful consideration is thus required for designing circuits operating under high-temperature conditions using the current state of the VNWFET technology. Work-around solutions such as gate work-function / doping engineering can be envisioned that could be useful as a feedback for fabrication process improvement. Other potential improvements include test-structure and cell-level 3D interconnect design optimization to achieve low-latency and compact 3D logic circuits.

  ) and (b) show the multiphysics simulation results depicting good agreement with experimental I-V characteristics.

Fig. 1 :

 1 Fig. 1: Electrothermal simulations using COMSOL: (a) temperature contours along the nanowire, (b) Temperature and thermal conductivity at different measurement temperatures; Extracted (c) temperature dependence of the threshold voltage, (d) thermal resistance of the VNWFETs.

Fig. 2 :

 2 Fig. 2: Electrothermal simulations using COMSOL: (a) temperature and thermal conductivity distribution inside the nanowire obtained at room temperature under different pulse conditions along the nanowire, (b) Extracted threshold voltage (measurement) and trap density (COMSOL) showing similar dependence on the pulse width.

Fig. 3 :

 3 Fig. 3: Evolution of drain current with (a) different pulse widths and (b), (c) measurement temperatures comparing experimental results, multiphysics and compact model simulations for a p-VNWFET with 25 parallel nanowires of 22 nm diameter.

  (a)) and temperature (Figs. 3(b) and (c)) measurements.

  nm NF = 16 D = 22 nm NF = 25 D = 22 nm NF = 36 D = 22 nm NF = 49 V TH (T) =  VT *(T-T0)

Fig. 4 .

 4 Fig. 4. Polarity-controllable transistor with Fe-Gate. While PC-FETs require a constant input to program gates, Fe-gate oxides are programmed by a pulse, reducing the dynamic power consumption.

Fig. 5 :

 5 Fig. 5: Schematic depicting the size of the test structure featuring GSG (Ground-Signal-Ground) pads allowing the use of the RF probe with regards to the size of one single nanowire featuring the channel of the VNWFET.

Fig. 6 :

 6 Fig. 6: The complete SSEC (Small-Signal Equivalent Circuit) of the passive elements associated with the VNWFET test structure.

Fig. 7 .

 7 Fig. 7. Schematics of logic cells studied: (a) INV1X1, (b) NAND2X1, (c) NOR2X1, (d) XOR2X1. The first step was to prove the ability of implementing such cells based on the VNWFET technology. In this context, we

Fig. 8 .

 8 Fig. 8. Variation of drain-source current IDS with gate-source voltage VGS and number of nanowires per VNWFET NW of (a) n-type VNWFET and (b) ptype VNWFET.

Fig. 10 :

 10 Fig. 10: All possible output transitions in: (a) Inverter, (b) NAND, (c) NOR, and (d) XOR affected by input transitions.

Fig. 11 .

 11 Fig. 11. Delay in output (a) rising, (b) falling transitions of a NAND gate as affected by different input transitions

Fig. 11

 11 Fig.11is a detailed example on how we studied the delay behavior of each logic cell. It is clear that the delay is dependent on the input(s) transitions, and that with the increases of NWs used per VNWFET the delay will decrease. For all the cells under study we found, as expected, that with the increase in the number of NWs used, a decrease in delay (Fig12) and rise/fall times is observed as well as an increase in dynamic power consumption (TableI).

Fig. 13 .

 13 Fig. 13. 2-input XOR logic cell. (a) Layout used for parasitic extraction. (b) Transient simulation results with and without parasitic annotation.

Fig. 14 .

 14 Fig. 14. The variation of logic cell performance metrics with number of NWs per VNWFET and temperature while considering self-heating and trapping effects. (a) INV1 / propagation delay (ps). (b) INV1 / dynamic rising energy consumption (aJ). (c) XOR2 / propagation delay (ps). (d) XOR2 / dynamic rising energy consumption (fJ).

Table I :

 I The dynamic energy values (aJ) for the logic cells under study, for all possible input transitions leading to output rising or falling transitions and for different number of NWs.

Delay (ps) Energy / transition (aJ) Output transition Input transition A B Without PEX With PEX Without PEX With PEX

	↑	↓1	93.74	83.83	724.81	825.82
		↑0	90.93	111.63	725.42	803.65
		1↓	90.73	83.41	724.91	851.42
		0↑	89.40	100.32	725.77	792.08
	↓	↑1	92.12	85.60	5.09	34.69
		↓0	90.75	112.12	5.29	58.59
		1↑	95.57	83.42	4.70	45.04
		0↓	92.73	102.55	5.00	59.05
		Average	92.00	95.36	365.12	433.79
		Increase		+3.65%		+18.81%

Table II :

 II Delay (ps) and energy/transition values (aJ) for a 2-NW per transistor XOR2 with and without layout-extracted parasitic annotation.

ACKNOWLEDGMENT

This work was supported by the project FVLLMONTI funded by European Union's Horizon 2020 research and innovation program under grant agreement N•101016776.


Emile Blettery

Valérie Gouet-Brunet

Blettery Gouet-Brunet

Re-ranking Image Retrieval in Challenging Geographical Iconographic Heritage Collections

Keywords: Information systems → Information retrieval, Image search, Information retrieval, • Applied computing → Arts and humanities Geographic iconographic heritage, Image retrieval, Re-ranking, Content interlinking

As the number of digitized geographic iconographic heritage collections increases, their global use is under-exploited by their lack of structure at large scale, which does not facilitate their access nor their understanding. Using automatic image retrieval methods appears to be the solution to bring structure by building links between contents, within and between collections. This paper presents an overview of methods for image retrieval applied to geographic iconographic heritage collections, both from the perspectives of image content description and of post-processing re-ranking. The article evaluates features and methods to identify their efficiency when faced with a challenging dataset. Moreover, new re-ranking approaches exploiting structuring information (scene geometry, metadata) are proposed to improve retrieval without having to adapt image descriptors to the specific data (retraining, fine-tuning, etc.) for every new specific collection.

INTRODUCTION

In this article, we are interested in the geographical iconographic heritage, i.e. digitized or born-digital image collections, acquired at variable temporal periods and showing the territory and its humanmade and natural visual landmarks. As a huge visual testimony of our environment, this category of contents is widespread but generally scattered in multiple provider or host institutions, such as GLAMs (Galleries, Libraries, Archives and Museums) or mapping agencies. Their exploitation embraces a large number of applications, ranging from historical and sociological studies up to mobile mapping scenarios, through digital tourism, education or landscape ecology. Some research works already try to exploit semi-automatic and automatic methods to use heritage collections for some of those applications ([3ś5, 18]). As illustrated in Figure 1 with iconography from Paris at the street level, the visual representations associated with such contents are diverse given the various acquisition conditions (different sources, dates, viewpoints) and the evolution of landmarks over time, making their analysis still challenging today. They are usually described and indexed with metadata of variable quality and specification, making them not always easily interoperable, accessible, understandable in different contexts, and then largely under-exploited. To mitigate these issues and address new demands, one well-established alternative is to use image retrieval in order to describe, compare and link the contents directly, independently of the organization set up for the collection. Because of the specificity of such contents, in this work our aim is to evaluate image retrieval techniques for this type of data, in order to illustrate the practical feasibility of building visual links automatically and thus helping to bring structure to the collections.

The article is organized as follows: Section 2 revisits state-ofthe-art descriptors and re-ranking approaches for image retrieval. Section 3 in turn presents the geographic iconographic dataset considered in the developments. We then evaluate retrieval methods, up to re-ranking, on this dataset in Section 4. Finally, in Section 5, we propose methods to improve the retrieval on such data, by exploiting the specificity and structure of the data and propagating it during re-ranking.

CONTENT-BASED IMAGE RETRIEVAL OVERVIEW

This section presents an overview of the state of the art on contentbased image retrieval, both from the perspective of visual descriptors and the perspective of post-processing methods for re-ranking the images returned with the descriptors.

Features for image retrieval

Main improvements to image retrieval came with the advent of new image descriptors. From handcrafted to learned descriptors, the methods are numerous and current learned methods have proved to be state-of-the-art [START_REF] Chen | Deep learning for instance retrieval: A survey[END_REF]. Multiple networks have first been developed for image classification and have been exploited for the more specific task of instance retrieval. Example backbones for image classification are VGG [START_REF] Simonyan | Very deep convolutional networks for large-scale image recognition[END_REF], ResNet [START_REF] He | Deep residual learning for image recognition[END_REF] or ResNest [START_REF] Zhang | ResNeSt: Split-Attention Networks[END_REF]. State-ofthe-art image descriptors are built on the features extracted by those backbones. On the one hand, the features can be aggregated in one global feature describing the whole image. Depending on the pooling operation used for the aggregation, different features can be extracted. Examples of global descriptors are SPoC [START_REF] Babenko | Aggregating local deep features for image retrieval[END_REF], MAC [START_REF] Tolias | Particular Object Retrieval With Integral Max-Pooling of CNN Activations[END_REF] and RMAC [START_REF] Tolias | Particular Object Retrieval With Integral Max-Pooling of CNN Activations[END_REF], GeM [START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF] but also the more recent CVNet [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF]. On the other hand, as with hand-made methods like VLAD [START_REF] Jégou | Aggregating local descriptors into a compact image representation[END_REF], local features can also be extracted and aggregated to describe an image. Some learned methods also build on this paradigm, using attention mechanisms to select the most meaningful features in the image, such as DeLF [START_REF] Noh | Large-scale image retrieval with attentive deep local features[END_REF] or How [START_REF] Tolias | Learning and aggregating deep local descriptors for instance-level recognition[END_REF]. As with the visual-bag-of-words paradigm, local features are aggregated in a vector to perform similarity comparison between images. Several methods have been devised to perform the aggregation step: we can specifically mention ASMK [START_REF] Tolias | Image search with selective match kernels: aggregation across single and multiple images[END_REF] which performs highly with local features. Finally, several works attempt to combine local and global features to improve image retrieval performance, like DELG [START_REF] Cao | Unifying deep local and global features for image search[END_REF], DOLG [START_REF] Yang | Dolg: Single-stage image retrieval with deep orthogonal fusion of local and global features[END_REF] or CVNet [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF]. However, whereas DOLG fuse both features to obtain a single descriptor, DELG and CVNet exploit the local features in a second time, as a trained re-ranking step, an essential step that will be discussed in section 2.2. Retrieving similar images simply based on visual descriptors and their similarities may not always yield the best results at the top of the list, because some other kinds of information, e.g. geometry in the image, was not encapsulated in the visual descriptor in order to be robust to the many transformations an image can undergo. Consequently, retrieval is usually considered as a two-step process: at first retrieval at large scale with descriptors, then re-ranking of the responses based on other finer or more specific criteria.

Re-ranking approaches

As presented in Figure 2, re-ranking methods can be divided into several categories. First, a very common re-ranking method is a geometric verification step. The idea is to match local features between the query image and each retrieved image, estimate the transformation parameters using a robust approach such as RANSAC [START_REF] Cao | Unifying deep local and global features for image search[END_REF][START_REF] Martin | Random sample consensus: a paradigm for model fitting with applications to image analysis and automated cartography[END_REF], and reorder the results based on the number of matches considered as inliers. Local features can be the ones used in the retrieval step as in [START_REF] Noh | Large-scale image retrieval with attentive deep local features[END_REF] with DELF, but also other more precise features used in other computer vision tasks, such as SfM, like SuperPoint [START_REF] Daniel Detone | Superpoint: Self-supervised interest point detection and description[END_REF]. This step can also be included directly in the descriptor training process as in DOLG [START_REF] Yang | Dolg: Single-stage image retrieval with deep orthogonal fusion of local and global features[END_REF], DELG [START_REF] Cao | Unifying deep local and global features for image search[END_REF] or CVNet [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF] which does not apply RANSAC with local features, but a dense cross-scale feature correlation to assess the coherence between images.

Another family of approaches regroups query expansion methods. The main idea is to take advantage of contextual information from the first retrieved images list by aggregating the features of the query and its most similar images to increase the meaningfulness of the query descriptor in order to improve the retrieval results. Multiple adaptations have been proposed, such as changing the aggregation weighting scheme (Average-QE [START_REF] Babenko | Aggregating local deep features for image retrieval[END_REF], 𝛼-QE [START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF], etc.). Other approaches [START_REF] Lin | Aggregation of Multiple Pseudo Relevance Feedbacks for Image Search Re-Ranking[END_REF][START_REF] Lin | Block-based pseudo-relevance feedback for image retrieval[END_REF] based on pseudo-relevance feedback aggregate features to be more similar to the first retrieved images and more dissimilar to the further ranked images. More recent methods [START_REF] Gordo | Attention-based query expansion learning[END_REF][START_REF] Zhang | Indicative Image Retrieval: Turning Blackbox Learning into Grey[END_REF] use an attention mechanism to select images and their weight in the aggregation process.

A specific kind of approach within query expansion re-ranking relies on diffusion, which propagates the similarity through the 𝑘-NN graph of similar images. Such solutions have achieved stateof-the-art performance on many benchmarks [START_REF] Bai | Re-ranking via metric fusion for object retrieval and person re-identification[END_REF][START_REF] Delvinioti | Image retrieval with reciprocal and shared nearest neighbors[END_REF][START_REF] Iscen | Efficient diffusion on region manifolds: Recovering small objects with compact cnn representations[END_REF][START_REF] Pang | Deep Feature Aggregation and Image Re-Ranking With Heat Diffusion for Image Retrieval[END_REF][START_REF] Shen | Reranking for image retrieval and transductive few-shot classification[END_REF]. In the article, we focus on a representative method [START_REF] Zhang | Understanding Image Retrieval Re-Ranking: A Graph Neural Network Perspective[END_REF], that we describe in more detail: it first embeds a 𝑘 1 -NN graph in an adjacency matrix 𝐴 * with 𝑖 and 𝑗 two images in the dataset and 𝑁 (𝑖, 𝑘) the 𝑘 most similar images to 𝑖:

𝐴 * 𝑖,𝑗 =          1 if 𝑗 ∈ N (𝑖, 𝑘 1 ) ∧ 𝑖 ∈ N ( 𝑗, 𝑘 1 ) 0 if 𝑗 ∉ N (𝑖, 𝑘 1 ) ∧ 𝑖 ∉ N ( 𝑗, 𝑘 1 ) 0.5 otherwise (1)
Once the graph of 𝑘 1 -NN is set as base for the GNN process, the 𝑘 2 -NN graph is exploited to select the edges (𝑒 𝑖 𝑗 ) representing image similarity between images 𝑖 and 𝐽 𝑗 that are used during the aggregation step to update the node (image) feature; 𝑘 2 is lower than 𝑘 1 (usually much more lower). The aggregation scheme, with ℎ

(𝑙)
𝑖 the feature of image 𝑖 at the 𝑙-th layer, is:

ℎ (𝑙+1) 𝑖 = ℎ (𝑙) 𝑖 + 𝑒 𝛼 𝑖 𝑗 • ℎ (𝑙) 𝑖 , 𝑗 ∈ N (𝑖, 𝑘 2 ) (2)
This method exploits the manifold of the dataset and is very efficient because the message propagation is concurrent between all nodes. The whole dataset is re-ranked in one passage. Finally, learned methods of re-ranking have been proposed to exploit the new paradigm of transformers. [START_REF] Tan | Instance-level image retrieval using reranking transformers[END_REF] proposes Re-ranking Transformers, a network that predicts the similarity of an image pair directly, provided their global and local features, as a replacement for geometric verification methods. Meanwhile, inspired by query expansion approaches, [START_REF] Ouyang | Contextual similarity aggregation with self-attention for visual re-ranking[END_REF] proposes a transformer-based network that aggregates affinity features among the first results to enrich the representations of the images with some contextual information. [START_REF] Zhu | 𝑅 2 Former: Unified 𝑅etrieval and 𝑅eranking Transformer for Place Recognition[END_REF] exploits transformers in an end-to-end fashion, both for global image description and retrieval and then for re-ranking. It exploits vision transformer tokens instead of handcrafted or CNN local features and reranks based on correlation between features rather than a pairwise geometrical verification.

THE GEOGRAPHICAL ICONOGRAPHIC HERITAGE COLLECTION CONSIDERED

The dataset we consider consists of more or less recent heritage content depicting Paris between 1915 and 2015 from a mostly groundlevel perspective. The collections belong to eight providers: • the Paris6K public benchmark [START_REF] Radenović | Revisiting Oxford and Paris: Large-Scale Image Retrieval Benchmarking[END_REF].

•
In total, we assembled a dataset of 1,637 images of which an example is shown in Figure 1, divided into 31 classes depicting regular buildings, renowned monuments (e.g. the Panthéon), churches (e.g. the Saint-Sulpice church), and remarkable buildings (e.g. the Lavirotte building). To further challenge image retrieval in the experiments, we added 8,197 images as distractors (from the Department of Architectural History of the city of Paris), which leads to a total of 9,834 images in the dataset.

Due to the large time period of acquisition and the multitude of providers, this dataset displays a large number of specific challenges for image retrieval:

• different techniques of acquisition, colors, etc.

• different resolution, levels of details, artisticity, etc,

• collection specificities increasing the above differences,

• changes in the scenes depicted due to the evolution of Paris throughout the century. In addition to these images, several metadata may be available sometimes, such as an acquisition date or a location. The latter may be of various types, from an address manually provided (it is the case with some images of our dataset, e.g. those from the Dept. of Architectural History of the City of Paris) up to a precise pose of the camera (with the mobile mapping system Stereopolis).

EVALUATION OF STATE-OF-THE-ART METHODS ON OUR CHALLENGING DATA

In this section, we present the evaluation of state-of-the-art methods on the dataset presented in section 3. We first evaluate the recent literature on image descriptors and second, some of the most representative re-ranking methods.

Evaluation framework

All the experiments of the article are run on a Tesla-V100 GPU with 16 Go RAM and 10 CPU cores. We evaluate the efficiency of the approaches mostly with the mean Average Precision score (mAP); the implementation used is from [START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF] 2 . The choice has been made to not retrain the learning networks involved, because we consider there are no training datasets existing for the data considered here, and that the constantly evolving data in digital humanities would require regular retraining which is not a realistic approach in practical use cases. All implementations are the authors' and the networks weights used are the ones provided by the authors.

Image descriptor evaluation

Four recent state-of-the-art image descriptors were evaluated: DELG [START_REF] Cao | Unifying deep local and global features for image search[END_REF], R101-GeM [START_REF] He | Deep residual learning for image recognition[END_REF][START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF], CVNet-Global [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF], How+ASMK [START_REF] Tolias | Image search with selective match kernels: aggregation across single and multiple images[END_REF][START_REF] Tolias | Learning and aggregating deep local descriptors for instance-level recognition[END_REF]. All methods are deep detectors and descriptors. The first three ones produce a global feature per image and are trained on Google Landmarks Dataset v2 (GLDv2) [START_REF] Weyand | Google landmarks dataset v2-a large-scale benchmark for instance-level recognition and retrieval[END_REF], whereas the last one, trained on SfM120k [START_REF] Radenović | CNN image retrieval learns from BoW: Unsupervised fine-tuning with hard examples[END_REF], produces local features and then aggregates them using ASMK [START_REF] Tolias | Image search with selective match kernels: aggregation across single and multiple images[END_REF] for comparison between image descriptors.

A first evaluation was performed on the dataset without distractors as shown in Table 1. At this step, CVNet clearly outperforms the other three descriptors. However, when more deeply compared to How+ASMK (called How-A afterwards), it is revealed that it mainly [START_REF] He | Deep residual learning for image recognition[END_REF][START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF] 57.9 -CVNet-global [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF] 67.3 37.1 How + ASMK [START_REF] Tolias | Image search with selective match kernels: aggregation across single and multiple images[END_REF][START_REF] Tolias | Learning and aggregating deep local descriptors for instance-level recognition[END_REF] 55.1 41.0 improves intra-collection retrieval and not between collections: indeed, when comparing the entropy of the distribution of the various providers in the true positive retrieved images, we observed that it is higher with How-A than with CVNet-Global. When including the large number of distractors in the dataset, How-A outperforms CVNet-Global; because it is a local descriptor, How-A proves to be more discriminative when the visual elements are very similar through images, which is frequent in the considered collections displaying redundant Parisian-style architectural features.

Re-ranking methods evaluation

As presented in Section 2.2, a large number of methods have been implemented to improve image retrieval results through a re-ranking step. Starting from How-A as visual descriptor, we have tested approaches from all families to evaluate what best suited our challenging data. Table 2 shows the performance of these approaches on the whole dataset, by providing an idea of the improvement in terms of mAP when exploiting re-ranking. [START_REF] Lin | Aggregation of Multiple Pseudo Relevance Feedbacks for Image Search Re-Ranking[END_REF] < + 0.5 Transformers-based CSA [START_REF] Tan | Instance-level image retrieval using reranking transformers[END_REF], RRT [START_REF] Ouyang | Contextual similarity aggregation with self-attention for visual re-ranking[END_REF] -10 CV-Net Rerank [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF] -2 Geometric Verification [START_REF] Daniel Detone | Superpoint: Self-supervised interest point detection and description[END_REF][START_REF] Paul | SuperGlue: Learning Feature Matching with Graph Neural Networks[END_REF] + 0.5 Diffusion [START_REF] Shen | Reranking for image retrieval and transductive few-shot classification[END_REF][START_REF] Zhang | Understanding Image Retrieval Re-Ranking: A Graph Neural Network Perspective[END_REF] + 15

Descriptor aggregation methods [START_REF] Babenko | Aggregating local deep features for image retrieval[END_REF][START_REF] Radenovic | Fine-tuning CNN Image Retrieval with No Human Annotation[END_REF], as well as pseudo-relevance feedback ones [START_REF] Lin | Aggregation of Multiple Pseudo Relevance Feedbacks for Image Search Re-Ranking[END_REF], do not appear relevant to our problem because of the high variability of images, inducing a high variability in those multidimensional descriptors, in turn squashing the descriptor's specificity during aggregation.

Transformers based images (RRT [START_REF] Tan | Instance-level image retrieval using reranking transformers[END_REF], CSA [START_REF] Ouyang | Contextual similarity aggregation with self-attention for visual re-ranking[END_REF]), and the reranking part of CVNet [START_REF] Lee | Correlation Verification for Image Retrieval[END_REF] all suffer from the same drawback: although reputed to be efficient, they are not here because by default trained on GLDv2, which is not suitable for specific heritage collections as ours. The solution would be to retrain or fine-tune those methods specifically to our data, but it has not been our choice as explained in Section 5.

Geometric verification is a very common step in image retrieval pipelines. In our case, we extract SuperPoint [START_REF] Daniel Detone | Superpoint: Self-supervised interest point detection and description[END_REF] local features, match them with the SuperGlue process [START_REF] Paul | SuperGlue: Learning Feature Matching with Graph Neural Networks[END_REF] and using a classical RANSAC, we re-rank images based on their geometric coherence with the query. The mAP gain is moderate as shown in Table 2 (and confirmed further in section 5 where it serves as reference).

Finally, diffusion methods have the most impact at the re-ranking step. We tested SSR [START_REF] Shen | Reranking for image retrieval and transductive few-shot classification[END_REF] and a GNN-based re-ranking method [START_REF] Zhang | Understanding Image Retrieval Re-Ranking: A Graph Neural Network Perspective[END_REF] (called GNN-R afterwards), where the mAP gain is substantial. Furthermore, GNN-R can be repeated multiple times to further extract similarity information and then improve retrieval; we have selected it as re-ranking method in the experiments of section 5.

HOW TO IMPROVE RETRIEVAL

Some existing re-ranking methods, as GNN-R, perform well on our dataset, by improving the retrieval results notably, but they do not really take into account its specificity. A commonly used solution would be fine-tuning existing state-of-the-art learned methods with our specific data. However, this solution has its drawbacks. First, it requires a certain number of annotated data possibly equally distributed among classes and providers, which is difficult to obtain in our case of collections with a sparse overlap in distribution. Secondly, fine-tuning on some specific collections may be efficient on those ones, but when confronted to their evolution (due to ongoing massive digitization, open data access, etc.), one may need to fine-tune the model all over regularly. For these reasons, we choose to study solutions that take into account the specificity of the data without having to retrain models specifically for them. Here, we propose three ways for improving retrieval, presented in sections 5.1, 5.2 and 5.3. They are evaluated in Table 3, facing several reference approaches, i.e. simple retrieval (How-A), retrieval with re-ranking with geometric verification (How-A + RANSAC), and several degrees of diffusion (GNN-R).

3D-based geometric verification

First, a main aspect in our dataset is the very large variation in viewpoint and level of detail, which allows to better understand the disappointing performance of the classical pairwise geometric verification such as RANSAC. To overcome this drawback, our first intuition was to use a 3D reconstruction of the scene, in order to check the geometric coherence of a result image not simply against the query image but against a more global geometry of the scene.

To do this, we reconstruct a 3D point cloud of the scene using Structure-from-Motion algorithms via the library Colmap [START_REF] Lutz | Structure-from-Motion Revisited[END_REF][START_REF] Lutz Schönberger | Pixelwise View Selection for Unstructured Multi-View Stereo[END_REF] based on keypoints extracted with [START_REF] Daniel Detone | Superpoint: Self-supervised interest point detection and description[END_REF][START_REF] Paul | SuperGlue: Learning Feature Matching with Graph Neural Networks[END_REF]. To reconstruct the scene, the query and the first ten retrieved images are used. If a scene is reconstructed successfully (at least two images including the query, using Colmap's default parameters), then the first 𝑘 retrieved images are repositioned in the 3D scene through 2D-3D registration. These images are then re-ranked depending on their coherence with the scene: for each image, it is measured as the number of matches between 2D points in the image and 3D points in the point cloud exploited to compute its 3D pose.

Exploiting a 3D reconstruction encapsulates a lot more of the scene's global geometry and details than a single image, since the reconstruction belongs to several images. Thus, images very different from the query can still visually and geometrically be linked to the query image. The benefits of this approach, called R3D in the article, are quite clear when we refer to Table 3: we observe an We can also note that all these results are notably improved by using several steps of diffusion up to 2 steps ("GNN-R × 2"), the results decreasing afterwards, whatever the approach. How-A + R3D reaches a mAP of 64.2% with a 2-step diffusion (an increase of 4.9%). In the Table, the "Mean time" column provides the averaged cost in terms of computation time for the first 135 images retrieved, by adding these post-processing to the simple retrieval with How-A. Not surprisingly, the R3D reconstruction takes more time than the RANSAC step.

We also observe that combining a simple RANSAC with the R3D reconstruction further improves the results (up to 65.8%) because the images used for the reconstruction process are geometrically more similar to the query, but at the expense of an even longer computation time, since both steps are performed successively.

2D geometric query expansion

Section 5.1 has demonstrated that exploiting a 3D reconstruction of the scene brings a great consistency in geometric verification. However, in some use cases, it could be considered as an operation too computationally costly. Thus, we have studied an alternative, called R2D, that tries to leverage the benefits the 3D information, by exploiting geometric information from the whole scene fully in 2D. The idea is to use the features extracted in similar images and reproject them in the query image to enrich its geometric significance and artificially enlarge the scene it encodes. It does not only encode the geometry of the scene it depicts, but also parts of the scene depicted by its most similar images.

The first step consists in creating all triplets with the query 𝑞 and two images from its 𝑘 most similar retrieved ones: (𝑞, 𝐼 1 , 𝐼 2 ) (with 𝑘 = 10 in our experiments). Then, for each triplet:

• extract keypoints for images in triplet: sets 𝐾 𝑞 , 𝐾 𝐼 1 , 𝐾 𝐼 2 • define matches pairwise: 𝑀 𝑞,𝐼 1 , 𝑀 𝑞,𝐼 2 , 𝑀 𝐼 1 ,𝐼 2 • define the query's solid matches as :

𝐾 𝑠 𝑞 = 𝑘 if 𝑀 𝐼 1 ,𝐼 2 • 𝑀 𝑞,𝐼 1 (𝑘) = 𝑀 𝑞,𝐼 2 (𝑘), ∀𝑘 ∈ 𝐾 𝑞 ,
• define the query's unsolid matches:

𝐾 𝑢 𝑞 = 𝑘 if 𝑘 ∉ 𝐾 𝑠 𝑞 , ∀𝑘 ∈ 𝐾 𝑞 , • if |𝐾 𝑠 𝑞 | > 10, estimate homographies ℎ 𝐼 1 ,𝑞 and ℎ 𝐼 2 ,𝑞 ,
• then reproject unmatched points of 𝐼 1 and 𝐼 2 in the query:

𝐾 ℎ 𝑞 = ℎ 𝐼 1 ,𝑞 (𝑘) if 𝑘 ∉ 𝑀 𝑞,𝐼 1 [𝐾 𝑠 𝑞 ], ∀𝑘 ∈ 𝐾 𝐼 1 ∪ ℎ 𝐼 2 ,𝑞 (𝑘) if 𝑘 ∉ 𝑀 𝑞,𝐼 2 [𝐾 𝑠 𝑞 ], ∀𝑘 ∈ 𝐾 𝐼 2
The three types of points are shown in the example of Figure 3.

Once those steps are performed on all triplets, they are globally concatenated for each query:

𝐾 𝑎 𝑞 = 𝐾 𝑠 𝑞 ∪ 𝐾 𝑢 𝑞 ∪ 𝐾 ℎ 𝑞 .
Once the new set of points is created, all the similar images are matched pairwise and re-ranked using this new set, as follows:

• match the keypoints 𝐾 𝑎 𝑞 and those (𝐾 𝐼 ) of image 𝐼 : 𝑀 𝑞,𝐼 • select the subsample of solid matches 𝑆 𝑠 (matches with a solid keypoint) or the subsample of solid and unsolid matches 𝑆 𝑠,𝑢 if the number of solid matches is less than 5, • estimate a transformation via RANSAC based on this subsample of matches, • reevaluate the matches based on this transformation and keep the matches respecting this transformation up to a maximum difference of 10 pixels, • the final score 𝑠 𝐼 of 𝐼 is computed using the number of each type of match (solid: 𝑀 𝑠 𝐼 ,unsolid: 𝑀 𝑢 𝐼 , reprojected: 𝑀 ℎ 𝐼 ) and the subsample of points used for the RANSAC:

𝑠 𝐼 =          10 × |𝑀 𝑠 𝐼 | + 5 × |𝑀 𝑢 𝐼 | + 10 × |𝑀 ℎ 𝐼 | if 𝑆 𝑠 is used 10 × |𝑀 𝑠 𝐼 | + 5 × |𝑀 𝑢 𝐼 | + 5 × |𝑀 ℎ 𝐼 | if 𝑆 𝑠,𝑢 is used 10 × |𝑀 𝑠 𝐼 | + 5 × |𝑀 𝑢 𝐼 | + 1 × |𝑀 ℎ 𝐼 | otherwise (3)
Using this 2D geometric query expansion is less efficient than the 3D reconstruction. As shown in Table 3 with How-A+R2D, the performance drops even compared to a setting without reranking. It can be explained by the fact that R2D relies on several homography estimations which remains a rough estimation of the scene geometry compared to the 3D reconstruction. However, the benefits of these method reveal themselves when combined with the diffusion process: the mAP is 63% after a 2-step diffusion, for a computation time comparable to RANSAC's one. An explanation for such a high impact of the diffusion is the fact that R2D increases inter-collection retrieval, which the diffusion in turn leverages very well. Indeed, we have computed the entropy of the providers distribution on the true positives images returned: it revealed that R2D's entropy is close to R3D's and higher than RANSAC's one (and How-A's), which explains why diffusion after RANSAC leads to similar results as diffusion after How-A.

Metadata structure diffusion

As previously shown in Sections 5.1 and 5.2, exploiting structural (geometrical) information improves the retrieval performance. To continue to evaluate other tracks exploiting the specificity of the manipulated data, we chose to be interested in their metadata, starting from the observation that in practice, some metadata are present at least partially, in some of the collections. Like image retrieval, such data may provide useful links between images, that can be simply but efficiently combined with visual similarity. To evaluate our hypothesis, we focused on the position information available for some of the images in our dataset. This is universal information, but potentially of varying nature: it can be directly available for images acquired through mobile mapping (e.g. Stereopolis), or the result of a geocoding of associated addresses (e.g. those manually provided by experts of the Dept. of Architectural History of the City of Paris). It should be noted, however, that their quality can be variable, due to potential human error (when manually added, copied and digitized), to acquisition precision (e.g. low-cost mapping) and to environment evolution (e.g. streets renamed or created through centuries). Then, based on the image location available and in addition to the visual similarity score provided by image retrieval, we define a spatial proximity score 𝑤 𝑖,𝑗 between two images 𝑖 and 𝑗, which takes the location quality into account with a confidence rate (𝑐 𝑖 for 𝑖 and 𝑐 𝑗 for 𝑗), as follows:

𝑤 𝑖,𝑗 = 𝑆 (𝑥 𝑖,𝑗 ) 1 𝑐 𝑖 ×𝑐 𝑗 if 𝑆 (𝑥 𝑖,𝑗 ) < 1 𝑆 (𝑥 𝑖,𝑗 ) 𝑐 𝑖 ×𝑐 𝑗 otherwise (4)
𝑆 (𝑥 𝑖,𝑗 ) is a proximity score based on the spatial Euclidean distance between 𝑖 and 𝑗: 𝑥 𝑖,𝑗 (normalized over the diameter of Paris in our experiments). We define 𝑆 as a double sigmoid function:

𝑆 (𝑥 𝑖,𝑗 ) = 𝑎 + (𝑏 -𝑎) × tanh(𝑘 1 (𝑥 𝑖,𝑗 -𝑋 1 )) + 1 2
+ (𝑐 -𝑏) × tanh(𝑘 2 (𝑥 𝑖,𝑗 -𝑋 2 )) + 1 2 (5)
with 𝑎, 𝑏, 𝑐 the bottom, middle and top values of the double sigmoid's plateaux. 𝑋 1 , 𝑋 2 , 𝑘 1 and 𝑘 2 are respectively the values for the inflexion point and the steepness coefficient for both slopes. 𝑤 𝑖,𝑗 ranges in [0,2] and equals 1 if we do not have location information for both images. Confidence rate 𝑐 𝑖 is 1 for Stereopolis, as it is precisely acquired as part of the mobile mapping, while for geocoded addresses, we set it below (0.9 for queries, 0.8 for distractors), because they are considered slightly less reliable.

We then combine the proximity and visual similarity scores between couples of images, through a simple weighting of the similarity score with the weight of equation 4, with the objective of limiting incoherent retrieval errors due to the limitations of visual descriptors. The whole process does not modify the eventual other steps of re-ranking, which are applied as previously explained.

As shown in Table 3, exploiting this spatial information improves the retrieval score more than a classic geometric verification, for a negligible online computation cost. We first exploited all possible location information available, for queries and distractors (i.e. 80.5% of the dataset). Then only Stereopolis locations (5% of the dataset with distractors) were used: using only a small part of the dataset is still more efficient than a simple geometric verification, especially when combined with diffusion which further propagates the structure in the retrieval process. Also, not surprisingly, the more positional information available, the better the retrieval results. However, after diffusion, the results are not much higher, suggesting that quantity of information is not as important as certainty and distribution among the dataset. Furthermore, combining a geometric re-ranking step with distance weighting on the similarity scores used in the diffusion process does not increase retrieval any further (experiment "R2D + distance weighting" in Table 3), which tends to show that data linked through R2D do not suffer from inconsistency in terms of location.

CONCLUSION

In this paper, we have evaluated state-of-the-art features and reranking methods for image retrieval with a challenging dataset of geographic heritage images. We show that diffusion-based reranking methods greatly improve retrieval, without considering a re-training step on the data. To further improve retrieval, we propose re-ranking approaches exploiting the structure of the dataset better: two re-ranking methods exploiting a more global geometry of the scene, and a weighting scheme using the available metadata information, here location. Once combined with diffusion-based methods, the proposed approaches improve retrieval for a computational cost on par with classical methods. As a perspective to deal with the most difficult retrieval cases, we think to continue to exploit the potential of diffusion-based methods by wisely injecting punctual manual intervention in order to propagate more structure in the dataset, without adding too much manual overhead.

Figure 2 :

 2 Figure 2: Re-ranking methods paradigms .

  the Department of Architectural History of the City of Paris, • the COARC, a service of the Department of Architectural History specialized in religious buildings, • the mobile mapping 2015 Stereopolis dataset from the French Mapping Agency [22], • the Planet's Archives -Paris of the Albert Kahn Museum, • the Cité de l'Architecture et du Patrimoine, • the Médiathèque du Patrimoine et de la Photographie, • the Commission for the Old Paris,

Figure 3 :

 3 Figure 3: Query image set of keypoints with solid points in red, unsolid points in blue and reprojected ones in green .

Table 1 :

 1 Score of tested image descriptors.

	mAP	Dataset w/o distractors Dataset
	DELG [6]	53.2	-
	R101 -GeM

Table 2 :

 2 Improvement of mAP with re-ranking

	Approach	Order of magnitude
	Weighted descriptor aggregation [1, 25]	+ 0.1
	Pseudo relevance feedback

Table 3 :

 3 mAP score with a re-ranking step on the dataset with distractors

	Descriptor +

https://github.com/filipradenovic/cnnimageretrieval-pytorch

ACKNOWLEDGMENTS

This work was financed by the City of Paris and the French ANRT through the Cifre grant 2019/1841. This work was carried out using HPC resources from GENCI-IDRIS (Grant 2022-AD011013510).


Strategies for

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge.

In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

Characterization Challenges

In the context of emerging technologies for new computing paradigms such as neural networks, vertical nanowire field effect transistors (VNWFET) are a promising technology owing to their naturally 3D architectures [START_REF] Maneux | 67th Annual IEEE IEDM[END_REF]. For the circuit design involving such a 3D emerging technology, it is mandatory to build new and accurate compact models to capture the static and dynamic behavior of the device [START_REF] Mukherjee | [END_REF]. However, on-wafer test structures of the devices comprise parasitic elements introduced by the RF pads and interconnects that are necessary to probe the devices under test (DUT). An illustration of respective sizes of the DUT and its associated test structure is shown Figure 1. The standard procedure to characterize the parasitic effects of such a device at high frequencies can be divided into two parts. First, the measurement system requires to be calibrated in order to the reference plane is at the probe tips. This can be achieved using standard calibration techniques such as SOLT (Short-Open-Load-Thru). At this point, all the parasitic elements associated with the pads and interconnects are still included in the measurements. In the second step, Sparameters of the open and short test structures are measured and subsequently used to remove the parasitic elements external to the DUT, through a matrix subtraction process known as de-embedding [START_REF] Koolen | Proceedings of the 1991 Bipolar Circuits and Technology Meeting[END_REF]. Although the methodology of parasitic extraction is widely used in technologies targeting high frequency applications, this methodology can also be applied for technologies such as the VNWFET that are mainly designed for logic cells to improve the modeling accuracy, which normally mostly relies on DC measurements [START_REF] Maneux | 67th Annual IEEE IEDM[END_REF]. Also, an accurate modeling of the parasitic elements allows the designer to optimize the 3D layout of the logic circuits and interconnects, thereby improving performance metrics such as compactness and energydelay product of the technology.

Conventional De-embedding Method

Unfortunately, using the conventional de-embedding methodology illustrated in Figure 2 leads to unphysical capacitance values as depicted in the inset of Figure 2 with some negative capacitance values as a function of the frequency. This means that not all parasitic parameters were accounted for, and a more detailed equivalent circuit is mandatory. Therefore, a deeper understanding of the test structure complexity including substrate coupling is requested to efficiently consider the reality of the actual test structure parasitic locations and values. To construct the SSEC of the OPEN test structure, electromagnetic, EM simulations of different sections of the complete structure were performed, thus allowing to estimate their individual contributions. The pad was considered as an LC network in series with a contact resistance and a π-network was used to model the coupling capacitances between the gate, drain, and the source accesses. The pad capacitance and impedance are estimated from the EM simulations of the virtual OPEN_PAD and SHORT_PAD structures presented in Fig. 3 Moreover, analyzing the device layout and the fabrication process, one can identify additional substrate parasitic elements related to the low silicon resistivity value [START_REF] Larrieu | [END_REF]5] and the absence of a ground shield metal underneath the signal pads [START_REF] Han | IEEE International Conference on Microelectronic Test Structures[END_REF]. The substrate parasitic elements introduce a lossy path, Cpad2-Rsub-Cpad3, shown in Figure 4 along with a fringe capacitance Cpad1 [START_REF] Aktas | [END_REF]. The values of all these parasitic elements constituting the SSEC were calculated through analytical equations from the physical dimensions and material properties of the device as well as from EM simulations. The overall SSEC is given Figure 5 along with their respective values. At this stage, the successful de-embedding of the intrinsic S-parameters measurements [8] allows us allows us to continue our investigations towards the next step: The VNWFET compact modeling allowing DTCOefficient strategies.

Modelling Challenges

The DTCO is driven by the use of VNWFETs in highly compact 3D logic circuits. Design of these logic circuits relies heavily on compact models, containing a set of physicsbased analytical equations for the juntionless transistors. The compact model developed for the 18 nm VNWFET technology [START_REF] Mukherjee | Solid-State Electronics[END_REF] has been extensively validated against measurements depicting very good agreement over the entire bias range. To leverage the model for predictive design through DTCO, we further explored the scalability for all available transistor geometries that showed a visible improvement in current scalability for larger devices (Figure 6). However, process variation has limited linear current scaling in smaller nanowire diameters that are of more interest for junctionless transistor operation. In contrast, for a given number of parallel nanowires, maintaining gate electrostatic control over the channel in larger diameters becomes more difficult along with a degradation of the drain current on/off ratio, despite better current scaling (Figure 7). So as a design tradeoff for the DTCO, we chose transistors with an optimal diameter (where junctionless functionality and gate electrostatic control are maintained for individual nanowires) with a higher number of nanowires in parallel to boost the drive current. 8b). Other non-conventional methods were also explored such as low-frequency S-parameter measurements or RTH extraction using the slope of drain current versus temperature plot at different dissipated powers, all of which offered similar results. A final verification using full device thermal simulation in COMSOL multiphysics, accounting for both ballistic and diffusive heat flux, showed good agreement with experimental results. This is the first demonstration of thermal resistance extraction in highly-scaled VNWFETs identifying the location of the two thermal contributions: NW channels and PtSi contacts (Figure 8c).

Conclusion

Vertical nanowire field effect transistors (VNWFET) represents a promising dedicated emerging technology for dense neural networks. For this proof of concept meet the 3D circuit cell design requirements DTCO approach relies on the compact modeling.

In this invited paper, we have demonstrated that Two major steps have been taken towards the reality of compact VNWFET modelling.

A clear and secure de-embedding methodology involving an EM simulation step has allow to sort the intrinsic VNWFET dynamic characteristics out of its test structure measurements. Also, this is the first demonstration of thermal resistance extraction in highly-scaled VNWFETs leading to identify the location of the two thermal contributions: NW and PtSi.

In the future scope of this work, the elements of the thermal network will be integrated in the JLNT compact model for design-technology co-optimization (DTCO) [START_REF] Maneux | 67th Annual IEEE IEDM[END_REF] and will play an important part in redefining the semiconductor value chain spanning across device and system levels involving these emerging 3D vertical technologies.

  Characterization and Parameter Extraction of Vertical Junction-less Nanowire FETs dedicated to Design Technology Co-Optimization C. Maneux a , C. Mukherjee a , M. Deng a , G. Larrieu b , Y. Wang a , and B. Neckel Wesling a, c a Univ. Bordeaux, CNRS, Bordeaux INP, IMS, UMR 5218, F-33400, Talence, France b CNRS, LAAS-CNRS, Université de Toulouse, F-31400, Toulouse, France c NaMLab gGmbH, Noethnitzer Strasse 64a, 01187 Dresden, Germany

Figure 1 .

 1 Figure 1. Schematic depicting the size of the test structure featuring GSG pads allowing the use of the RF probe with regards to the size of one single nanowire featuring the channel of the VNWFET.

Figure 2 .

 2 Figure 2. Open-Short de-embedding conventional method featuring compact but simple Small Signal Equivalent Circuit, SSEC. The inset represents the Drain-to-Source capacitance values as a function of the frequency.

  of the VNWFET with GSG RF pads Port 2 (Drain) OPEN-SHORT DE-EMBEDDING Ref. plane after calibration ? Dedicated De-embedding Method for VNWFETs

  (a) and (b), respectively. The coupling capacitances are obtained from the OPEN_DUT shown in Fig. 3 (c). A figure of the substrate used in ADS software for the EM simulation is shown on Fig. 3 (d). The extracted elements are then combined to construct the more realistic distributed circuit.

Figure 3 :

 3 Figure 3: Virtual structures for the EM simulation, a) OPEN_PAD, b) SHORT_PAD, c) OPEN_DUT and (d) the substrate definition on ADS for EM simulation.

Figure 4 :

 4 Figure 4: 3D view of the distributed model.

Figure 5 :

 5 Figure 5: The complete SSEC of the passive elements.

Figure 6 :

 6 Figure 6: Normalized drain current of the VNWFETs depicting better current scaling in larger geometries.

.

  a) On and off currents and (b) DIBL and subthreshold slope as a function of the nanowire diameters Reliability assessment through electro-thermal measurements of VNWFETs is crucial when designing 3D logic circuits within DTCO framework, particularly for evaluating long-term performances. Conventional methods for thermal investigation were not applicable for the VNWFETs as the drain current shows steady increase with temperature in contrast with classical devices (Figure 8a) where the current reduces due to temperature induced mobility degradation. Since activation of self-heating could not be confirmed using traditional methods, a new methodology for thermal resistance estimation in VNWFETs is developed. It relies on estimating the temperature coefficient of threshold voltage from ID-VG curves at different measurement temperatures (TA) and power dissipations (Pdiss) corresponding to same VG and ID. From the definition of device/junction temperature, Tj=TA+RTH*Pdiss, one can extract the thermal resistances (RTH) from the relation 𝑅 Theoretical calculations corroborated extracted results with RTH values ranging between 4 and 28×10 4 K/W (Figure

Figure 8 :

 8 Junctioless transistor Thermal properties: (a) Temperature dependence of the drain current of the VNWFETs, (b) Thermal resistance as function of device width (c) Location of the thermal contributions: NW and PtSi.

Acknowledgments

This work was supported by the project FVLLMONTI funded by the European Union's Horizon 2020 research and innovation program under grant agreement N•101016776, by LEGO project (Grant ANR-18-CE24-0005-01) and by the LAAS-CNRS micro and nanotechnologies platform, a member of the Renatech French national network.


Al Heib Marwan

Al Heib

Multi-hazard analysis

published or not. The documents may come

Multi-hazard analysis of abandoned coal-mines

Marwan Al Heib. Marwan.alheib@ineris.fr L'Institut national de l'environnement industriel et des risques Abstract.

Nowadays, most coal mines in Europe are already closed or are in a state of liquidation. However, the problem concerning the abandoned coal mines and their influence on the environment is still a central objective of the mining industry and coal regions in transition. After the end of the exploitation, numerous disturbances can occur. Mines operators, local authorities and decision makers face multihazard and multi-risks related to mine closure. Land and especially planning for a proper old mining site rehabilitation require better tools to apprehend the multiplicity of hazards and constraints.

The objective to improve risk assessment by creating a new methodology to treat a global and multihazard related to abandoned coalmines instead of each hazard separately and study the interaction between the hazards related to post-mining areas.

The mining hazards concern: ground movement, hydrologic hazards, self-heating, soil and water pollution. One hazard can trigger another one. Different tools such as a global matrix, fault tree, etc. for identifying the hazard interaction. The hazard interaction matrix was built, figure 1 shows a tentative view of interactions that phenomena in the columns (source phenomenon) may have with phenomena in the rows (target phenomenon). Figure 1 also shows indicative interactions between source phenomena and target phenomena according to 4 levels of interactions: No known case of interaction between phenomena (white colour), Low (yellow), Medium (green) and High (red). The final adopted interactions are based on the feedback and the deep discussion between experts. This approach will help the mining actors to improve and design the mitigation measures facing the multihazard impact and consequences.

Figure 1 .

 1 Figure 1. Interaction matrix of different hazard related to mine closure